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#include <bits/stdc++.h> using namespace std; int main() { int arr[1000]; int num; cin >> num; for (int i = 0; i < num; i++) { cin >> arr[i]; arr[num + i] = arr[i]; } int ans = 360; for (int i = 0; i < num; i++) { int temp = 0; for (int j = i; j < num * 2; j++) { temp += arr[j]; ans = min(ans, abs(360 - 2 * temp)); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int oo = 1e9 + 9; const long long inf = 1e18 + 18; const int max6 = 1e6 + 6; const int modx = 1e9 + 123; const int mody = 997; const int base = 137; int a[max6], dd[max6], cnt[max6]; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; for (int i = 0; i <= 2 * k; ++i) dd[i] = cnt[i] = 0; for (int i = 1; i <= n; ++i) cin >> a[i]; int m = n / 2; for (int i = 1; i <= m; ++i) { int gmax = max(a[i], a[n - i + 1]) + k; int gmin = min(a[i], a[n - i + 1]) + 1; dd[gmin]++; dd[gmax + 1]--; cnt[a[i] + a[n - i + 1]]++; } int res = oo; dd[1] += dd[0]; for (int i = 2; i <= 2 * k; ++i) { dd[i] += dd[i - 1]; res = min(res, n - dd[i] - cnt[i]); } cout << res << n ; } } |
#include <bits/stdc++.h> using namespace std; struct query { int Q, id; long long res; }; const int Nmax = 200001; int n, m, parent[Nmax], Rank[Nmax]; vector<pair<int, pair<int, int> > > edge; bool cmpQ(const query &q1, const query &q2) { return q1.Q < q2.Q; } bool ret(const query &q1, const query &q2) { return q1.id < q2.id; } int Find(const int &i) { if (i == parent[i]) return i; return parent[i] = Find(parent[i]); } void Union(const int &i, const int &j) { int x = Find(i), y = Find(j); if (x != y) { if (Rank[x] > Rank[y]) { parent[y] = x; Rank[x] += Rank[y]; } else { parent[x] = y; Rank[y] += Rank[x]; } } } int main() { if (fopen( 1213G .INP , r )) { freopen( 1213G .INP , r , stdin); freopen( 1213G .OUT , w , stdout); } ios_base::sync_with_stdio(false); cin.tie(NULL); scanf( %d %d , &n, &m); for (int i = 1, _n = (n); i <= _n; ++i) parent[i] = i, Rank[i] = 1; edge.resize(n - 1); int u, v, w, q; for (int i = 0, _n = (n - 1); i < _n; ++i) scanf( %d %d %d , &edge[i].second.first, &edge[i].second.second, &edge[i].first); sort(edge.begin(), edge.end()); vector<query> qu(m); for (int i = 0, _n = (m); i < _n; ++i) { scanf( %d , &qu[i].Q); qu[i].id = i; } sort(qu.begin(), qu.end(), cmpQ); int j = 0; long long ans = 0; for (int i = 0, _n = (m); i < _n; ++i) { for (; j < n - 1; ++j) { if (edge[j].first <= qu[i].Q) { ans += (long long)Rank[Find(edge[j].second.first)] * Rank[Find(edge[j].second.second)]; Union(edge[j].second.first, edge[j].second.second); } else break; } qu[i].res = ans; } sort(qu.begin(), qu.end(), ret); for (int i = 0, _n = (m); i < _n; ++i) cout << qu[i].res << ; return 0; } |
module foo();
initial begin
a;
end
always @(a) begin
b;
end
task a (a);
begin
a = f;
a = f;
d <= 89;
sdf = sdf;
adada = > asda;
d ->> g;
aasd <<<= 3;
ccc %= 6;
d *= b;
g -= c;
end
endtask // a
property p_3;
a = > ##3 !a;
a |=> ##1 !a;
a |-> ##2 !a;
endproperty
property p_2;
@(posedge clk) b |-> ##1 c;
endproperty
property p_1;
@(posedge clk) a |-> b;
endproperty
initial d;
// ap_1 assert property (p_1); FIXME
// ap_2 assert property (p_2);
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
// Issue #940 - '=' in |=> , #=#, and [=n] operators should not mis-indent next line of continued expression
property p_nonSequential;
a |-> b[=n] ##0
c;
endproperty
property p_nonOverlapFollowedBy;
a #=#
c;
endproperty
property p_nonBlockingImplication;
a |=> b[*n] ##0
c;
endproperty
endmodule
|
/***********************************************************************************************************************
* Copyright (C) 2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
A counter that includes redundant flipflops (the high 4 FFs never go high)
*/
module RedundantFF(clear, underflow);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P19" *)
input wire clear;
(* LOC = "P20" *)
output wire underflow;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Clock source
wire clk_108hz;
GP_LFOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OUT_DIV(16)
) lfosc (
.PWRDN(1'b0),
.CLKOUT(clk_108hz)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The counter
reg[7:0] count = 15;
always @(posedge clk_108hz) begin
count <= count - 1'h1;
if(count == 0)
count <= 15;
end
assign underflow = (count == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_BLACKBOX_V
`define SKY130_FD_SC_HD__MAJ3_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__maj3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_BLACKBOX_V
|
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
parameter SRL_COUNT = 4;
parameter PRESCALER = 4;
// UART loopback
assign tx = rx;
// ============================================================================
// Reset
reg [3:0] rst_sr;
wire rst;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign rst = rst_sr[0];
// ============================================================================
// Clock prescaler
reg [32:0] ps_cnt = 0;
wire ps_tick = ps_cnt[32];
always @(posedge clk)
if (rst || ps_tick)
ps_cnt <= PRESCALER - 2;
else
ps_cnt <= ps_cnt - 1;
// ============================================================================
// SRL32 testers
wire sim_error = sw[2];
reg [SRL_COUNT-1:0] srl_q31;
wire [SRL_COUNT-1:0] error;
genvar i;
generate for(i=0; i<SRL_COUNT; i=i+1) begin
wire srl_d;
wire srl_sh;
wire srl_q31_o;
srl_shift_tester #
(
.SRL_LENGTH (33), // One extra for DFF reg
.FIXED_DELAY (33)
)
tester
(
.clk (clk),
.rst (rst),
.ce (ps_tick),
.srl_sh (srl_sh),
.srl_d (srl_d),
.srl_q (srl_q31[i] ^ sim_error),
.srl_a (),
.error (error[i])
);
always @(posedge clk)
if (srl_sh) srl_q31[i] <= srl_q31_o;
SRLC32E srl
(
.CLK (clk),
.CE (srl_sh),
.A (5'd0),
.D (srl_d),
.Q31 (srl_q31_o)
);
end endgenerate
// ============================================================================
// Error latch
reg [SRL_COUNT-1:0] error_lat = 0;
always @(posedge clk)
if (rst)
error_lat <= 0;
else
error_lat <= error_lat | error;
// ============================================================================
// Create a non-GND/VCC source for additional LED outputs.
// This is a side affect of the ROI disallowing GND/VCC connections to synth
// IO pads.
wire net_0;
LUT2 #(.INIT(4'hC)) lut_0 (.I0(|sw), .I1(&sw), .O(net_0));
// LEDs
genvar j;
generate for(j=0; j<8; j=j+1) begin
if (j < SRL_COUNT) begin
assign led[j ] = (sw[1]) ? error_lat[j] : error[j];
assign led[j+8] = srl_q31[j];
end else begin
assign led[j ] = net_0;
assign led[j+8] = net_0;
end
end endgenerate
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ctrl_boot.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ctrl_boot (
address,
clock,
q);
input [10:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../fw/ctrl_boot/bin/ctrl_boot.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.maximum_depth = 512,
altsyncram_component.numwords_a = 1280,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "ctrl"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "512"
// Retrieval info: PRIVATE: MIFfilename STRING "../../fw/ctrl/boot_old/bin/ctrl_boot.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1280"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../fw/ctrl/boot_old/bin/ctrl_boot.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1280"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ctrl_boot.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ctrl_boot.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ctrl_boot.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ctrl_boot.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ctrl_boot_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ctrl_boot_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module control_unit (
input wire clk,
input wire rst_n,
// to UART receiver
input wire[7:0] cmd,
input wire rx_rdy,
input wire tx_rdy,
output reg cmd_oen = 1,
output reg data_wen = 1,
output reg[7:0] data = 0,
// to servo fsm
input wire[7:0] servo_angle, // [-90 .. 90] in degrees projected to
output reg[7:0] start_angle, // [8'h00 .. 8'hFF] angle reg's value
output reg[7:0] end_angle,
// to servo driver
input wire servo_cycle_done,
// to sonar_driver
input wire sonar_ready,
input wire[7:0] sonar_distance,
output reg sonar_measure = 0
);
// Internal registers for sonar control
reg[7:0] distance = 0;
// Internal registers for cmd processing
parameter AUTO_MODE = 1'b0;
parameter MANUAL_MODE = 1'b1;
reg mode = AUTO_MODE;
parameter IDLE = 4'h0;
parameter FETCH_CMD = 4'h1;
parameter FETCH_DATA_PRE = 4'h2;
parameter FETCH_DATA = 4'h3;
parameter WAIT_SERVO_DONE = 4'h4;
parameter START_MEASURE = 4'h5;
parameter MEASURE = 4'h6;
parameter WAIT_TX_RDY = 4'h7;
parameter SEND_DATA = 4'h8;
parameter SEND_DATA_POST = 4'h9;
reg[3:0] state = IDLE;
reg[3:0] next_state = IDLE;
reg send_data_type = 0; // 0 - distance; 1 - angle;
// Cmd set
parameter MANUAL_CMD = 4'h0;
// Manual cmd set
parameter SET_ANGLE_CMD = 2'h0;
parameter SET_MODE_CMD = 2'h1;
parameter MEASURE_CMD = 2'h2;
// Assign new state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = IDLE;
end else begin
state = next_state;
end
end
// Next state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = IDLE;
end else begin
case(state)
IDLE: begin
if (rx_rdy) begin
next_state = FETCH_CMD;
end else if (mode == AUTO_MODE) begin // In manual mode wait for measure cmd
next_state = WAIT_SERVO_DONE;
end
end
FETCH_CMD: begin
case (cmd[7:4])
MANUAL_CMD: begin // in this case
case (cmd[3:2])
SET_ANGLE_CMD: begin
next_state = FETCH_DATA_PRE;
end
SET_MODE_CMD: begin
next_state = IDLE;
end
MEASURE_CMD: begin
next_state = START_MEASURE;
end
endcase // manual cmd case
end
default: begin // In this case: [7:4] - end angle MSB, [3:0] - start angle MSB
next_state = IDLE;
end
endcase // cmd case
end
FETCH_DATA_PRE: begin
if (rx_rdy) begin
next_state = FETCH_DATA;
end
end
FETCH_DATA: begin
next_state = IDLE;
end
WAIT_SERVO_DONE: begin
if (servo_cycle_done) begin
next_state = START_MEASURE;
end
end
START_MEASURE: begin
next_state = MEASURE;
end
MEASURE: begin
if (sonar_ready) begin
next_state = WAIT_TX_RDY;
end
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
next_state = SEND_DATA;
end
end
SEND_DATA: begin
next_state = SEND_DATA_POST;
end
SEND_DATA_POST: begin
case(send_data_type)
0: next_state = WAIT_TX_RDY;
1: next_state = IDLE;
endcase
end
endcase // state case
end
end
// Outputs logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
mode = AUTO_MODE;
cmd_oen = 1;
data_wen = 1;
data = 0;
sonar_measure = 0;
start_angle = 8'h00;
end_angle = 8'hFE;
end else begin
case(state)
IDLE: begin
cmd_oen = 1;
data_wen = 1;
sonar_measure = 0;
end
FETCH_CMD: begin
cmd_oen = 0;
case (cmd[7:4])
MANUAL_CMD: begin // in this case
case (cmd[3:2])
SET_MODE_CMD: begin
mode = cmd[0];
end
endcase // manual cmd case
end
default: begin // In this case: [7:4] - end angle MSB, [3:0] - start angle MSB
if (cmd[3:0] < cmd[7:4]) begin
start_angle = {cmd[3:0], 4'h0};
end_angle = {cmd[7:4], 4'h0};
end else begin
start_angle = {cmd[7:4], 4'h0};
end_angle = {cmd[3:0], 4'h0};
end
end
endcase // cmd case
end
FETCH_DATA_PRE: begin
cmd_oen = 1;
end
FETCH_DATA: begin
start_angle = cmd;
end_angle = cmd;
cmd_oen = 0;
end
WAIT_SERVO_DONE: begin
end
START_MEASURE: begin
sonar_measure = 1; // Generate measure pulse
end
MEASURE: begin
sonar_measure = 0;
distance = sonar_distance;
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
case(send_data_type)
0: data = {distance[7:1], 1'b0}; // Add zero as LSB for show that it's distance byte
1: data = {servo_angle[7:1], 1'b1}; // Add one as LSB for show that it's angle byte
endcase
end
end
SEND_DATA: begin
data_wen = 0;
end
SEND_DATA_POST: begin
data_wen = 1;
send_data_type = !send_data_type;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int insig; void Out(vector<long long int> x) { for (long long int i = 0; i < x.size(); i++) { cout << x[i] << ; } cout << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int N; cin >> N; vector<pair<long long int, long long int> > p; long long int c1, c2; for (long long int i = 0; i < N; i++) { cin >> c1 >> c2; p.push_back(make_pair(c1, c2)); } long long int ans = (long long int)(N * (N - 1LL) * (N - 2LL) * (N - 3LL) * (N - 4LL)) / 120LL; ans *= 5; long long int l; long long int a = 1; long long int b = -1; long double val; for (long long int i = 0; i < N; i++) { long long int x = p[i].first; long long int y = p[i].second; vector<long double> t1, t2, t3, t4, t5, t6, t7, t8; long double val; for (long long int j = 0; j < N; j++) { if (j == i) { continue; } if (p[j].first != x) { val = (long double)(((long double)(p[j].second - y)) / ((long double)(p[j].first - x))); } if (p[j].first == x && p[j].second > y) { t6.push_back(0); } else if (p[j].first == x && p[j].second < y) { t8.push_back(0); } else if (p[j].first > x && p[j].second == y) { t5.push_back(val); } else if (p[j].first < x && p[j].second == y) { t7.push_back(val); } else if (p[j].first > x && p[j].second > y) { t1.push_back(val); } else if (p[j].first > x && p[j].second < y) { t4.push_back(-val); } else if (p[j].first < x && p[j].second > y) { t2.push_back(-val); } else if (p[j].first < x && p[j].second < y) { t3.push_back(val); } } sort(t1.begin(), t1.end()); sort(t2.begin(), t2.end()); sort(t3.begin(), t3.end()); sort(t4.begin(), t4.end()); for (long long int j = 0; j < t1.size(); j++) { l = (j + t5.size() + t4.size() + t8.size() + (long long int)(t3.end() - lower_bound(t3.begin(), t3.end(), t1[j]))); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } for (long long int j = 0; j < t2.size(); j++) { l = (t2.size() - j - 1 + t6.size() + t1.size() + t5.size() + (long long int)(lower_bound(t4.begin(), t4.end(), t2[j]) - t4.begin())); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } for (long long int j = 0; j < t3.size(); j++) { l = (j + t7.size() + t2.size() + t6.size() + (long long int)(t1.end() - lower_bound(t1.begin(), t1.end(), t3[j]))); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } for (long long int j = 0; j < t4.size(); j++) { l = (t4.size() - j - 1 + t8.size() + t3.size() + t7.size() + (long long int)(lower_bound(t2.begin(), t2.end(), t4[j]) - t2.begin())); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } if (t5.size() == 1) { l = (t4.size() + t8.size() + t3.size()); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } if (t6.size() == 1) { l = (t1.size() + t5.size() + t4.size()); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } if (t7.size() == 1) { l = (t2.size() + t6.size() + t1.size()); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } if (t8.size() == 1) { l = (t3.size() + t7.size() + t2.size()); ans -= (long long int)(l * (l - 1LL) * (l - 2LL)) / 6LL; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; string input; cin >> n >> m; vector<vector<int> > nodes(n, vector<int>(26)); vector<vector<int> > G(n); int indegree[n]; memset(indegree, 0, sizeof(indegree)); cin >> input; for (int j = 0; j < n; j++) { int ascii = input[j] - a ; nodes[j][ascii]++; } for (int i = 0; i < m; i++) { int s, e; cin >> s >> e; G[s - 1].push_back(e - 1); indegree[e - 1]++; } queue<int> q; for (int i = 0; i < n; i++) { if (indegree[i] == 0) { q.push(i); } } int cycle = 0; int answer = 0; while (!q.empty()) { int u = q.front(); q.pop(); cycle++; if (G[u].size() == 0) { int curr = -1; for (int i = 0; i < 26; i++) { if (nodes[u][i] > curr) { curr = nodes[u][i]; } } if (curr > answer) { answer = curr; } } for (int nodeIndex : G[u]) { for (int j = 0; j < 26; j++) { if (j == input[nodeIndex] - a ) { if (nodes[nodeIndex][j] < nodes[u][j] + 1) { nodes[nodeIndex][j] = nodes[u][j] + 1; } } else { if (nodes[nodeIndex][j] < nodes[u][j]) { nodes[nodeIndex][j] = nodes[u][j]; } } } indegree[nodeIndex]--; if (indegree[nodeIndex] == 0) { q.push(nodeIndex); } } } if (cycle != n) { cout << -1 << n ; } else { cout << answer << n ; } } |
module opicorv32_rf_wrap (
ra2,
ra1,
d,
wa,
wr,
resetn,
clk,
q1,
q2
);
input [5:0] ra2;
input [5:0] ra1;
input [31:0] d;
input [5:0] wa;
input wr;
input resetn;
input clk;
output [31:0] q1;
output [31:0] q2;
/* signal declarations */
wire [31:0] _2356;
wire [31:0] _2354;
wire [31:0] compare_q2;
wire [31:0] _2358;
wire [63:0] _2351;
wire [31:0] _2359;
wire [63:0] _2353;
wire [31:0] _2355;
wire [31:0] compare_q1;
wire [31:0] _2361;
/* logic */
assign _2356 = _2351[63:32];
assign _2354 = _2353[63:32];
assign compare_q2 = _2354 ^ _2356;
assign _2358 = compare_q2 ^ _2356;
picorv32_rf
the_picorv32_rf
( .clk(clk), .resetn(resetn), .wr(wr), .wa(wa), .d(d), .ra1(ra1), .ra2(ra2), .q2(_2351[63:32]), .q1(_2351[31:0]) );
assign _2359 = _2351[31:0];
opicorv32_rf
the_opicorv32_rf
( .clk(clk), .resetn(resetn), .wr(wr), .wa(wa), .d(d), .ra1(ra1), .ra2(ra2), .q2(_2353[63:32]), .q1(_2353[31:0]) );
assign _2355 = _2353[31:0];
assign compare_q1 = _2355 ^ _2359;
assign _2361 = compare_q1 ^ _2359;
/* aliases */
/* output assignments */
assign q1 = _2361;
assign q2 = _2358;
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
module sia(
input clk_i,
input reset_i,
input [3:1] adr_i,
input we_i,
input cyc_i,
input stb_i,
input [1:0] sel_i,
input [SRW:0] dat_i,
output [SRW:0] dat_o,
output ack_o,
output stall_o,
output irq_o,
input rxd_i,
input rxc_i,
output txd_o,
output txc_o,
output rx_not_empty_o,
output tx_not_full_o
);
parameter BAUD_RATE_WIDTH = 20;
parameter SHIFT_REG_WIDTH = 16;
parameter BRW = BAUD_RATE_WIDTH - 1;
parameter SRW = SHIFT_REG_WIDTH - 1;
wire [4:0] wb_tr_bits;
wire wb_r_eedc, wb_r_eedd, wb_r_rxcpol;
wire [2:0] wb_t_txcmod;
wire [BRW:0] wb_tr_bitrat;
wire txclb, txdlb;
wire wb_r_pop, wb_r_oe;
wire [SRW:0] r_wb_dat;
wire r_wb_full, r_wb_not_empty;
wire wb_t_we;
wire [SRW:0] wb_t_dat;
wire t_wb_not_full, t_wb_empty, t_wb_idle;
// Facilitates external DMA circuitry. These would typically signal
// an external bus master module, such as a dedicated DMAC module.
assign rx_not_empty_o = r_wb_not_empty;
assign tx_not_full_o = t_wb_not_full;
wire rxd = txdlb ? txd_o : rxd_i;
wire rxc = txclb ? txc_o : rxc_i;
wire txd, txc;
assign txd_o = txdlb ? 1'b0 : txd;
assign txc_o = txclb ? wb_t_txcmod[0] : txc;
sia_wb wb (
.clk_i(clk_i),
.reset_i(reset_i),
.adr_i(adr_i),
.we_i(we_i),
.cyc_i(cyc_i),
.stb_i(stb_i),
.sel_i(sel_i),
.dat_i(dat_i),
.dat_o(dat_o),
.ack_o(ack_o),
.stall_o(stall_o),
.irq_o(irq_o),
.bits_o(wb_tr_bits),
.eedc_o(wb_r_eedc),
.eedd_o(wb_r_eedd),
.txcmod_o(wb_t_txcmod),
.rxcpol_o(wb_r_rxcpol),
.intena_o(),
.bitrat_o(wb_tr_bitrat),
.txdlb_o(txdlb),
.txclb_o(txclb),
.rxq_pop_o(wb_r_pop),
.rxq_oe_o(wb_r_oe),
.rxq_dat_i(r_wb_dat),
.rxq_full_i(r_wb_full),
.rxq_not_empty_i(r_wb_not_empty),
.txq_we_o(wb_t_we),
.txq_dat_o(wb_t_dat),
.txq_not_full_i(t_wb_not_full),
.txq_empty_i(t_wb_empty),
.txq_idle_i(t_wb_idle)
);
sia_rxq #(
.BAUD_RATE_WIDTH(BAUD_RATE_WIDTH),
.SHIFT_REG_WIDTH(SHIFT_REG_WIDTH)
) rxq (
.clk_i(clk_i),
.reset_i(reset_i),
.bits_i(wb_tr_bits),
.baud_i(wb_tr_bitrat),
.eedd_i(wb_r_eedd),
.eedc_i(wb_r_eedc),
.rxcpol_i(wb_r_rxcpol),
.rxd_i(rxd),
.rxc_i(rxc),
.rxq_pop_i(wb_r_pop),
.rxq_oe_i(wb_r_oe),
.rxq_dat_o(r_wb_dat),
.rxq_full_o(r_wb_full),
.rxq_not_empty_o(r_wb_not_empty)
);
sia_txq #(
.BAUD_RATE_WIDTH(BAUD_RATE_WIDTH),
.SHIFT_REG_WIDTH(SHIFT_REG_WIDTH)
) txq (
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(wb_t_dat),
.we_i(wb_t_we),
.bits_i(wb_tr_bits),
.baud_i(wb_tr_bitrat),
.txcmod_i(wb_t_txcmod),
.txd_o(txd),
.txc_o(txc),
.not_full_o(t_wb_not_full),
.empty_o(t_wb_empty),
.idle_o(t_wb_idle)
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module AST_ROM (
a,
spo
);
input wire [13 : 0] a;
output wire [7 : 0] spo;
dist_mem_gen_v8_0 #(
.C_FAMILY("zynq"),
.C_ADDR_WIDTH(14),
.C_DEFAULT_DATA("0"),
.C_DEPTH(16384),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("AST_ROM.mif"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(0),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(8'B0),
.dpra(14'B0),
.clk(1'D0),
.we(1'D0),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(),
.qspo(),
.qdpo()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long k, d, t; int main() { scanf( %lld%lld%lld , &k, &d, &t); t *= 2; long long round = ceil((double)k / d) * d; long long num = k * 2 + (round - k); long long cnt = t / num; long long left = t - cnt * num; double ans = 0.0; if (left <= k * 2) { ans = cnt * round + left / 2; if (left % 2) ans += 0.5; } else ans = cnt * round + k + (left - k * 2); printf( %.1lf n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int q[1000005]; long long i, j, t, tot, C, cnt; long long loc[10005], op[10005]; long long n, m, k, H, x, y, ans, tmp; long long a[100005], w[100005], e[25], dis[10005], heap[10005]; bool used[100005], f[10005]; map<long long, long long> A; map<long long, long long>::iterator it; void Spfa(long long s) { long long i, head, tail, x, v; for (i = 1; i <= k; i++) { dis[i] = 1999999999999999999LL; f[i] = false; } dis[s + 1] = 1; f[s + 1] = true; q[1] = s + 1; head = 1; tail = 2; while (head != tail) { x = q[head]; f[x] = false; for (i = 1; i <= tot; i++) if (dis[x] + e[i] < dis[(dis[x] + e[i]) % k + 1]) { v = (dis[x] + e[i]) % k + 1; dis[v] = dis[x] + e[i]; if (!f[v]) { q[tail] = v; f[v] = true; tail++; } } head++; } } int main() { scanf( %I64d%I64d%I64d%I64d , &H, &n, &m, &k); for (i = 1; i <= n; i++) scanf( %I64d%I64d , &a[i], &w[i]); tot = 0; memset(used, false, sizeof used); x = 1 % k; for (i = 1; i <= n; i++) { if (a[i] % k == x) { used[i] = true; it = A.find(w[i]); if (it == A.end()) A.insert(make_pair(w[i], 1)); else A[w[i]]++; } } for (t = 1; t <= m; t++) { scanf( %I64d , &C); if (C == 1) { scanf( %I64d , &x); e[++tot] = x; Spfa(1 % k); for (i = 1; i <= n; i++) if (dis[a[i] % k + 1] <= a[i]) { if (!used[i]) { used[i] = true; it = A.find(w[i]); if (it == A.end()) A.insert(make_pair(w[i], 1)); else A[w[i]]++; } } } else if (C == 2) { scanf( %I64d%I64d , &x, &y); if (used[x]) { it = A.find(w[x]); tmp = it->second; if (tmp == 1) A.erase(w[x]); else A[w[x]]--; w[x] -= y; it = A.find(w[x]); if (it != A.end()) A[w[x]]++; else A.insert(make_pair(w[x], 1)); } else w[x] -= y; } else { if (A.size() == 0) { printf( 0 n ); continue; } it = A.end(); it--; ans = it->first; printf( %I64d n , ans); tmp = it->second; if (tmp == 1) A.erase(ans); else A[ans]--; } } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:50:22 05/08/2016
// Design Name:
// Module Name: xorshift
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module xorshift(
input clk,
input rst,
input [127:0] seed,
output [31:0] out
);
reg [31:0] x_q, y_q, z_q, w_q, x_d, y_d, z_d, w_d;
assign out = w_q;
always @(*) begin
x_d = y_q;
y_d = z_q;
z_d = w_q;
w_d = w_q ^ (w_q >> 19) ^ (x_q ^ (x_q << 11)) ^ ((x_q ^ (x_q << 11)) >> 8);
end
always @(posedge clk) begin
// Auto-reset if we're in the all-zero state
if (x_q == 0 && y_q == 0 && z_q == 0 && w_q == 0) begin
x_q <= 32'h8de97cc5;
y_q <= 32'h6144a7eb;
z_q <= 32'h653f6dee;
w_q <= 32'h8b49b282;
end else if (rst) begin
x_q <= seed[127:96];
y_q <= seed[95:64];
z_q <= seed[63:32];
w_q <= seed[31:0];
end else begin
x_q <= x_d;
y_q <= y_d;
z_q <= z_d;
w_q <= w_d;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; double m1 = 200.0, m2 = 0.0, DV; int card, n, k, Q, getcard; int a[110], vs[110], b[110], len = 0; int sum = 0, tmp; int main() { memset(vs, 0, sizeof(vs)); scanf( %d%d , &n, &k); card = (int)(n / k); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); scanf( %d , &Q); for (int i = 1; i <= Q; ++i) { sum = 0; for (int j = 1; j <= card; ++j) { scanf( %d , &tmp); sum += a[tmp]; vs[tmp] = 1; } DV = double(sum) / double(card); if (DV < m1) m1 = DV; if (DV > m2) m2 = DV; } for (int i = 1; i <= n; ++i) if (!vs[i]) b[++len] = a[i]; getcard = (n - len) / card; if (len >= card && getcard < k) { sort(b + 1, b + len + 1); sum = 0; for (int i = 1; i <= card; ++i) sum += b[i]; DV = double(sum) / double(card); if (DV < m1) m1 = DV; if (DV > m2) m2 = DV; sum = 0; for (int i = len - card + 1; i <= len; ++i) sum += b[i]; DV = double(sum) / double(card); if (DV < m1) m1 = DV; if (DV > m2) m2 = DV; } printf( %.10lf %.10lf n , m1, m2); return 0; } |
#include <bits/stdc++.h> int main() { int q; std::cin >> q; while (q--) { int n, ans(0); std::cin >> n; std::set<std::string> check, p; std::string s; std::vector<std::string> res, a(n); for (int i = 0; i < n; i++) { std::cin >> a[i]; check.insert(a[i]); } for (int i = 0; i < n; i++) { if (p.find(a[i]) != p.end()) { std::string t = a[i]; for (int x = 0; x < 10; x++) { if (check.find(t) == check.end()) { check.insert(t); p.insert(t); break; } t[0] = char( 0 + x); } ++ans; res.push_back(t); } else { res.push_back(a[i]); p.insert(a[i]); } } std::cout << ans << std::endl; for (int i = 0; i < res.size(); i++) { std::cout << res[i] << std::endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005; const int inf = 1e9 + 7; int main() { int n; scanf( %d , &n); while (n--) { int x; scanf( %d , &x); if (x <= 3 || x == 5 || x == 7 || x == 11) puts( -1 ); else { int ans = 0, tg = x & 3; if (!tg) ans = max(ans, x / 4); if (tg == 2) ans = max(ans, 1 + (x - 6) / 4); if (tg == 1) ans = max(ans, 1 + (x - 9) / 4); if (tg == 3) ans = max(ans, 2 + (x - 15) / 4); printf( %d n , ans); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DFRTN_PP_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_PP_SYMBOL_V
|
//
// atabuf.v -- parallel ATA data buffer
//
module ata_buffer (clk,
bus_write, bus_addr, bus_din, bus_dout,
ata_write, ata_addr, ata_din, ata_dout);
input clk;
// bus interface
input bus_write;
input [11:2] bus_addr;
input [31:0] bus_din;
output [31:0] bus_dout;
// ata interface
input ata_write;
input [11:1] ata_addr;
input [15:0] ata_din;
output [15:0] ata_dout;
wire [9:0] internal_bus_addr;
wire [9:0] internal_ata_addr;
wire [15:0] lo_din_bus;
wire [15:0] hi_din_bus;
wire [15:0] lo_din_ata;
wire [15:0] hi_din_ata;
wire [15:0] lo_dout_bus;
wire [15:0] hi_dout_bus;
wire [15:0] lo_dout_ata;
wire [15:0] hi_dout_ata;
wire lo_write_bus;
wire hi_write_bus;
wire lo_write_ata;
wire hi_write_ata;
reg ata_out_muxctrl;
assign internal_bus_addr[9:0] = bus_addr[11:2];
assign internal_ata_addr[9:0] = ata_addr[11:2];
assign lo_din_bus = bus_din[15:0];
assign hi_din_bus = bus_din[31:16];
assign lo_din_ata = ata_din;
assign hi_din_ata = ata_din;
// pipeline register for ata output mux control
always @(posedge clk) begin
ata_out_muxctrl <= ata_addr[1];
end
assign bus_dout = { hi_dout_bus, lo_dout_bus };
assign ata_dout = ata_out_muxctrl ? lo_dout_ata : hi_dout_ata;
assign lo_write_bus = bus_write;
assign hi_write_bus = bus_write;
assign lo_write_ata = ata_write & ata_addr[1];
assign hi_write_ata = ata_write & ~ata_addr[1];
RAMB16_S18_S18 lo_buffer (
.DOA(lo_dout_bus),
.DOB(lo_dout_ata),
.ADDRA(internal_bus_addr),
.ADDRB(internal_ata_addr),
.CLKA(clk),
.CLKB(clk),
.DIA(lo_din_bus),
.DIB(lo_din_ata),
.DIPA(2'b00),
.DIPB(2'b00),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(lo_write_bus),
.WEB(lo_write_ata)
);
RAMB16_S18_S18 hi_buffer (
.DOA(hi_dout_bus),
.DOB(hi_dout_ata),
.ADDRA(internal_bus_addr),
.ADDRB(internal_ata_addr),
.CLKA(clk),
.CLKB(clk),
.DIA(hi_din_bus),
.DIB(hi_din_ata),
.DIPA(2'b00),
.DIPB(2'b00),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(hi_write_bus),
.WEB(hi_write_ata)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_TB_V
`define SKY130_FD_SC_LS__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1000000001; void run_case() { long long n; cin >> n; vector<pair<long long, long long>> v; for (long long i = 0; i < n; i++) { long long x; cin >> x; v.push_back({x, i}); } sort(v.begin(), v.end()); vector<long long> curr_max(n), maxi(n), ans(n); curr_max[0] = v[0].second; maxi[0] = v[0].second; ans[v[0].second] = -1; for (long long i = 1; i < n; i++) { curr_max[i] = max(curr_max[i - 1], v[i].second); if (v[i].first == v[i - 1].first) maxi[i] = maxi[i - 1]; else maxi[i] = curr_max[i]; ans[v[i].second] = maxi[i] - v[i].second - 1; } for (long long i = 0; i < n; i++) { cout << max(ans[i], -1ll) << ; } cout << endl; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long tc = 1; while (tc--) run_case(); return 0; } |
// chris_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
reg [31:0] reg_out;
assign avs_s0_readdata = reg_out;
//assign avs_s0_readdata = 32'b00000000000000000000000000000000;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] data_in;
reg led_out;
reg [31:0] reg_kernel[8:0];
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read&Reg_Status_Write;
assign LEDR = led_out;
// WRITE LOGIC
//
always @(posedge clock_clk)
if (reset_reset) begin
data_in <= 32'b0;
Reg_Status_Write <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
case (avs_s0_address[3:0])
4'b1000: begin
led_out <= 1'b0;
data_in <= avs_s0_writedata;
end
4'b1001: begin
led_out <= 1'b1;
data_in <= avs_s0_writedata;
end
default:begin
led_out <= avs_s0_writedata[0];
end
endcase
Reg_Status_Write <= 1'b1;
end else if (avs_s0_waitrequest && avs_s0_write)begin
Reg_Status_Write <= 1'b0;
end else begin
Reg_Status_Write <= 1'b1;
end
//
// x and z values are don't-care's
// READ LOGIC
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b1;
end else if(avs_s0_waitrequest && avs_s0_read) begin
case (avs_s0_address[3:0])
4'b0000:reg_out <= 32'h00000000;
4'b0001:reg_out <= 32'h00000001;
default:reg_out <= 32'hffffffff;
endcase
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b1;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:52:27 02/29/2016
// Design Name: FSM
// Module Name: C:/Users/Jafet/Documents/Proyectos Dis.Sist.Digitales/I_Proyecto_Laboratorio_Sistemas_Digitales/FSM_Testbench.v
// Project Name: I_Proyecto_Laboratorio_Sistemas_Digitales
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: FSM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module FSM_Testbench;
// Inputs
reg clk;
reg rst;
reg Funct_Select;
reg [3:0] Count_CT;
reg [3:0] Count_F;
// Outputs
wire [3:0] C_Digit;
wire [3:0] C_7Seg;
// Instantiate the Unit Under Test (UUT)
FSM uut (
.clk(clk),
.rst(rst),
.Funct_Select(Funct_Select),
.Count_CT(Count_CT),
.Count_F(Count_F),
.C_Digit(C_Digit),
.C_7Seg(C_7Seg)
);
//this process block sets up the free running clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
Funct_Select = 0;
Count_CT = 0;
Count_F = 0;
end
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
initial begin
rst = 1;
Funct_Select = 1'b0;
Count_CT = 4'b0000;
Count_F = 4'b0000;
#200
rst = 0;
Funct_Select = 1'b0;
Count_CT = 4'b0000;
Count_F = 4'b0000;
#800
rst = 0;
Funct_Select = 1'b1;
Count_CT = 4'b0000;
Count_F = 4'b0000;
#800
rst = 0;
Funct_Select = 1'b0;
Count_CT = 4'b0001;
Count_F = 4'b0001;
#800
rst = 0;
Funct_Select = 1'b1;
Count_CT = 4'b0001;
Count_F = 4'b0001;
#1000 $stop;
end
/*reg [3:0] i;
initial begin
rst = 1;
Funct_Select = 1'b0;
Count_CT = 4'b0000;
Count_F = 4'b0000;
#200
rst = 0;
Funct_Select = 1'b0;
for(i=4'b0;i<16;i=i+1)
always@ posedge clck
begin
Count_CT <= i;
Count_F <= i;
end
#1000 $stop;
end*/
endmodule
|
module top;
reg passed;
parameter zero = 1'b0;
parameter one = 1'b1;
parameter highz = 1'bz;
parameter undef = 1'bx;
initial begin
passed = 1'b1;
if (&zero !== 1'b0) begin
$display("FAILED const. reduction & with input 1'b0, expected 1'b0, ",
" got %b", &zero);
passed = 1'b0;
end
if (&one !== 1'b1) begin
$display("FAILED const. reduction & with input 1'b1, expected 1'b1, ",
" got %b", &one);
passed = 1'b0;
end
if (&highz !== 1'bx) begin
$display("FAILED const. reduction & with input 1'bz, expected 1'bx, ",
" got %b", &highz);
passed = 1'b0;
end
if (&undef !== 1'bx) begin
$display("FAILED const. reduction & with input 1'bx, expected 1'bx, ",
" got %b", &undef);
passed = 1'b0;
end
if (|zero !== 1'b0) begin
$display("FAILED const. reduction | with input 1'b0, expected 1'b0, ",
" got %b", |zero);
passed = 1'b0;
end
if (|one !== 1'b1) begin
$display("FAILED const. reduction | with input 1'b1, expected 1'b1, ",
" got %b", |one);
passed = 1'b0;
end
if (|highz !== 1'bx) begin
$display("FAILED const. reduction | with input 1'bz, expected 1'bx, ",
" got %b", |highz);
passed = 1'b0;
end
if (|undef !== 1'bx) begin
$display("FAILED const. reduction | with input 1'bx, expected 1'bx, ",
" got %b", |undef);
passed = 1'b0;
end
if (^zero !== 1'b0) begin
$display("FAILED const. reduction ^ with input 1'b0, expected 1'b0, ",
" got %b", ^zero);
passed = 1'b0;
end
if (^one !== 1'b1) begin
$display("FAILED const. reduction ^ with input 1'b1, expected 1'b1, ",
" got %b", ^one);
passed = 1'b0;
end
if (^highz !== 1'bx) begin
$display("FAILED const. reduction ^ with input 1'bz, expected 1'bx, ",
" got %b", ^highz);
passed = 1'b0;
end
if (^undef !== 1'bx) begin
$display("FAILED const. reduction ^ with input 1'bx, expected 1'bx, ",
" got %b", ^undef);
passed = 1'b0;
end
if (~&zero !== 1'b1) begin
$display("FAILED const. reduction ~& with input 1'b0, expected 1'b1, ",
" got %b", ~&zero);
passed = 1'b0;
end
if (~&one !== 1'b0) begin
$display("FAILED const. reduction ~& with input 1'b1, expected 1'b0, ",
" got %b", ~&one);
passed = 1'b0;
end
if (~&highz !== 1'bx) begin
$display("FAILED const. reduction ~& with input 1'bz, expected 1'bx, ",
" got %b", ~&highz);
passed = 1'b0;
end
if (~&undef !== 1'bx) begin
$display("FAILED const. reduction ~& with input 1'bx, expected 1'bx, ",
" got %b", ~&undef);
passed = 1'b0;
end
if (~|zero !== 1'b1) begin
$display("FAILED const. reduction ~| with input 1'b0, expected 1'b1, ",
" got %b", ~|zero);
passed = 1'b0;
end
if (~|one !== 1'b0) begin
$display("FAILED const. reduction ~| with input 1'b1, expected 1'b0, ",
" got %b", ~|one);
passed = 1'b0;
end
if (~|highz !== 1'bx) begin
$display("FAILED const. reduction ~| with input 1'bz, expected 1'bx, ",
" got %b", ~|highz);
passed = 1'b0;
end
if (~|undef !== 1'bx) begin
$display("FAILED const. reduction ~| with input 1'bx, expected 1'bx, ",
" got %b", ~|undef);
passed = 1'b0;
end
if (~^zero !== 1'b1) begin
$display("FAILED const. reduction ~^ with input 1'b0, expected 1'b1, ",
" got %b", ~^zero);
passed = 1'b0;
end
if (~^one !== 1'b0) begin
$display("FAILED const. reduction ~^ with input 1'b1, expected 1'b0, ",
" got %b", ~^one);
passed = 1'b0;
end
if (~^highz !== 1'bx) begin
$display("FAILED const. reduction ~^ with input 1'bz, expected 1'bx, ",
" got %b", ~^highz);
passed = 1'b0;
end
if (~^undef !== 1'bx) begin
$display("FAILED const. reduction ~^ with input 1'bx, expected 1'bx, ",
" got %b", ~^undef);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_BLACKBOX_V
`define SKY130_FD_SC_LP__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long int n, o = 0, t = 0; cin >> n; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; if (x == 1) o++; else t++; } if (t) { cout << 2 << ; t--; } if (o) { cout << 1 << ; o--; } while (t--) cout << 2 << ; while (o--) cout << 1 << ; } |
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int MOD = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; string str; cin >> str; bool good = false; for (long long int i = (1); i <= (long long int)(30); ++i) { for (long long int j = (0); j <= (long long int)(n); ++j) { if (j + (i * 4) >= n) break; else if (str[j] == * && str[j + i] == * && str[j + (2 * i)] == * && str[j + (3 * i)] == * && str[j + (4 * i)] == * ) { good = true; } } } if (good) cout << yes ; else cout << no ; } |
#include <bits/stdc++.h> using namespace std; int n, t, k, cnt = 0; int a[200005], st[200005]; struct hehe { int x, y; } e[200005]; void add(int x, int y) { cnt++; e[cnt].x = x; e[cnt].y = y; } void solve() { int i, j; int minn = 1, maxx = 1; a[0] = 1; st[0] = 1; for (i = 1; i <= t; i++) { maxx = maxx + a[i] - 1; st[i] = st[i - 1] + a[i - 1]; if (a[i] >= a[i - 1]) minn += a[i] - a[i - 1]; } if (minn > k || maxx < k) { printf( -1 n ); return; } printf( %d n , n); for (i = st[1]; i <= st[1] + a[1] - 1; i++) add(1, i); for (i = 1; i <= t - 1; i++) { if (minn < k) { for (j = 1; j <= a[i + 1] - a[i] && j <= a[i + 1]; j++) add(st[i], st[i + 1] + j - 1); int zuida; if (a[i + 1] >= a[i]) zuida = a[i] - 1; else zuida = a[i + 1] - 1; if (minn + zuida < k) { int delta = max(0, a[i + 1] - a[i]); minn += zuida; for (j = st[i + 1] + delta; j <= st[i + 1] + a[i + 1] - 1; j++) add(st[i], j); } else { int delta = max(0, a[i + 1] - a[i]); int xiaid; int zhiqian; if (a[i + 1] >= a[i]) zhiqian = 0; else zhiqian = a[i] - a[i + 1]; for (j = 1; j <= a[i] - (zhiqian + (k - minn)); j++) { xiaid = st[i + 1] + delta + j - 1; add(st[i] + j - 1, xiaid); } for (j = xiaid + 1; j <= st[i + 1] + a[i + 1] - 1; j++) add(st[i], j); minn = k; } } else { for (j = 1; j <= a[i + 1] - a[i]; j++) add(st[i], st[i + 1] + j - 1); int id = st[i]; int delta = max(0, a[i + 1] - a[i]); for (j = st[i + 1] + delta; j <= st[i + 1] + a[i + 1] - 1; j++) { add(id, j); id++; } } } for (i = 1; i <= cnt; i++) cout << e[i].x << << e[i].y << endl; } int main() { while (scanf( %d%d%d , &n, &t, &k) != EOF) { int i; cnt = 0; for (i = 1; i <= t; i++) scanf( %d , &a[i]); solve(); } return 0; } |
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire [7:0] sw,
output wire [7:0] led,
input wire jc1,
output wire jc2,
input wire jc3,
output wire jc4
);
// ============================================================================
// MMCM
wire clk_fb;
wire [3:0] oclk;
wire [3:0] gclk;
MMCME2_ADV #
(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("INTERNAL"),
.CLKIN1_PERIOD (10.0),
.CLKIN2_PERIOD (10.0),
.CLKFBOUT_MULT_F (10.5),
.CLKFBOUT_PHASE (0),
.CLKOUT0_DIVIDE_F (12.5),
.CLKOUT0_DUTY_CYCLE (0.50),
.CLKOUT0_PHASE (45.0),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_DUTY_CYCLE (0.53125),
.CLKOUT1_PHASE (90.0),
.CLKOUT2_DIVIDE (48),
.CLKOUT2_DUTY_CYCLE (0.50),
.CLKOUT2_PHASE (135.0),
.CLKOUT3_DIVIDE (64),
.CLKOUT3_DUTY_CYCLE (0.50),
.CLKOUT3_PHASE (45.0),
.STARTUP_WAIT ("FALSE")
)
mmcm
(
.CLKIN1 (clk),
.CLKIN2 (clk),
.CLKINSEL (1'b0),
.RST (sw[0]),
.PWRDWN (1'b0),
.CLKFBIN (clk_fb),
.CLKFBOUT (clk_fb),
.CLKOUT0 (oclk[0]),
.CLKOUT1 (oclk[1]),
.CLKOUT2 (oclk[2]),
.CLKOUT3 (oclk[3])
);
// ============================================================================
// Outputs
genvar i;
generate for (i=0; i<4; i=i+1) begin
BUFG bufg (.I(oclk[i]), .O(gclk[i]));
reg r;
always @(posedge gclk[i])
r <= ~r;
assign led[i] = r;
end endgenerate
// Unused
assign led[4] = 1'b0;
assign led[5] = 1'b0;
assign led[6] = 1'b0;
assign led[7] = |sw;
assign jc2 = jc1;
assign jc4 = jc3;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, t, b[100020], cnt, p, q; char s[100020], s1[100020], s2[100020]; char chose(char x, char y) { if (x != a && y != a ) return a ; else if (x != b && y != b ) return b ; else return c ; } int main() { scanf( %d%d , &n, &t); scanf( %s , s1); scanf( %s , s2); cnt = 0; p = 0; q = 0; for (int i = 0; i < n; i++) if (s1[i] != s2[i]) cnt++; if (t < (cnt + 1) / 2) { printf( -1 n ); return 0; } if (t <= cnt) { for (int i = 0; i < n; i++) { if (s1[i] == s2[i]) s[i] = s1[i]; else { p++; if (p <= 2 * t - cnt) s[i] = chose(s1[i], s2[i]); else if (p % 2 == 1) s[i] = s1[i]; else s[i] = s2[i]; } } } else { for (int i = 0; i < n; i++) { if (s1[i] == s2[i]) { q++; if (q <= t - cnt) s[i] = chose(s1[i], s1[i]); else s[i] = s1[i]; } else { p++; s[i] = chose(s1[i], s2[i]); } } } printf( %s , s); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<string> s(n); for (int i = 0; i < n; ++i) cin >> s[i]; int answer = 0; for (int col = 0; col < (int)s[0].size(); ++col) { bool is_sorted = true; for (int i = 0; i < n - 1; ++i) { if (s[i].substr(0, col + 1) > s[i + 1].substr(0, col + 1)) { is_sorted = false; } } if (!is_sorted) { ++answer; for (int i = 0; i < n; ++i) { string new_string; for (int j = 0; j < (int)s[i].size(); ++j) { if (j != col) { new_string += s[i][j]; } } s[i] = new_string; } --col; } } cout << answer << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1000010], b[1000010]; int f[1000010], g[1000010]; int tmp[1000010]; int ansf[1000010], ansg[1000010]; int main() { int sv, n, m; scanf( %d %d , &sv, &n); int p = 0, q = 0; for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); x -= sv; if (x == 0) { puts( 1 ); return 0; } int y = abs(x); if (x < 0) a[++p] = y; else b[++q] = y; } if (!p || !q) { puts( -1 ); return 0; } sort(a + 1, a + p + 1); p = unique(a + 1, a + p + 1) - a - 1; sort(b + 1, b + q + 1); q = unique(b + 1, b + q + 1) - b - 1; n = 0; for (int i = 1; i <= p; i++) { f[++n] = a[i]; ansf[a[i]] = 1; } for (int i = 1; i < 1005; i++) { int N = 0; for (int j = 1; j <= n; j++) { for (int k = 1; k <= p; k++) { int x = f[j] + a[k]; if (!ansf[x]) { ansf[x] = i + 1; tmp[++N] = x; } } } n = N; for (int j = 1; j <= n; j++) f[j] = tmp[j]; } m = 0; for (int i = 1; i <= q; i++) { g[++m] = b[i]; ansg[b[i]] = 1; } for (int i = 1; i < 1005; i++) { int N = 0; for (int j = 1; j <= m; j++) { for (int k = 1; k <= q; k++) { int x = g[j] + b[k]; if (!ansg[x]) { ansg[x] = i + 1; tmp[++N] = x; } } } m = N; for (int j = 1; j <= m; j++) g[j] = tmp[j]; } int res = 0x3f3f3f3f; for (int i = 1; i < 1000010; i++) { if (ansf[i] && ansg[i]) res = min(res, ansf[i] + ansg[i]); } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; unsigned long long lvl_len(int lvl) { static long long len[64] = {0}; if (len[lvl]) return len[lvl]; else { len[1] = 1; for (int i = 2; i < 64; ++i) len[i] = len[i - 1] * 2 + 1; } return len[lvl]; } void rec(int lvl, unsigned long long pos) { if (pos < lvl_len(lvl - 1)) rec(lvl - 1, pos); else if ((pos -= lvl_len(lvl - 1)) < 1) cout << lvl; else rec(lvl - 1, pos - 1); }; int main(int, char **) { ios::sync_with_stdio(false); unsigned long long n, p; cin >> n >> p; rec(n, p - 1); return 0; } |
#include <bits/stdc++.h> using namespace std; bool odd(int N) { while (N < 0) { N += 2; } return N % 2 == 1 ? true : false; } bool even(int N) { while (N < 0) { N += 2; } return N % 2 == 0 ? true : false; } int main() { string s, t; cin >> s >> t; int N = s.size(); string result = ; int num = 0; for (int i = 0; i != N; ++i) { if (s[i] != t[i]) { ++num; if (num % 2) { result += s[i]; } else { result += t[i]; } } else { result += s[i]; } } if (even(num)) { cout << result; } else { cout << impossible ; } return 0; } |
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: radio86rk.v
//
// Top level design file.
// --------------------------------------------------------------------
// Ported to "Aeon Lite" by Dmitriy Schapotschkin aka ILoveSpeccy
// http://www.speccyland.net '2015
module radio86rk(
input clk50,
inout [15:0] SRAM_DQ, // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR, // SRAM Address bus 18 Bits
output SRAM_UB_N, // SRAM High-byte Data Mask
output SRAM_LB_N, // SRAM Low-byte Data Mask
output SRAM_WE_N, // SRAM Write Enable
output SRAM_CE_N, // SRAM Chip Enable
output SRAM_OE_N, // SRAM Output Enable
output SOUND_L,
output SOUND_R,
output VGA_HS,
output VGA_VS,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
input PS2_CLK,
input PS2_DAT,
input SD_DAT, // SD Card Data (MISO)
output SD_DAT3, // SD Card Data 3 (CSn)
output SD_CMD, // SD Card Command Signal (MOSI)
output SD_CLK // SD Card Clock (SCK)
);
reg startup;
reg tapein = 1'b0;
wire hdla;
wire cpurst;
wire videomode;
wire[7:0] ppa1_o;
wire[7:0] ppa1_a;
wire[7:0] ppa1_b;
wire[7:0] ppa1_c;
//////////////////// RESET ////////////////////
reg[3:0] reset_cnt;
reg reset_n;
wire reset = ~reset_n;
always @(posedge clk50) begin
// if (KEY[0] && reset_cnt==4'd14)
if (!cpurst && reset_cnt==4'd14)
reset_n <= 1'b1;
else begin
reset_n <= 1'b0;
reset_cnt <= reset_cnt+4'd1;
end
end
//////////////////// MEM ////////////////////
wire sram_msb = 0;
wire[7:0] mem_o = sram_msb ? SRAM_DQ[15:8] : SRAM_DQ[7:0];
wire[7:0] rom_o;
assign SRAM_DQ[7:0] = SRAM_WE_N| sram_msb ? 8'bZZZZZZZZ : cpu_o;
assign SRAM_DQ[15:8] = 8'bZZZZZZZZ; // SRAM_WE_N|~sram_msb ? 8'bZZZZZZZZ : cpu_o;
assign SRAM_ADDR = vid_rd ? {3'b000,vid_addr[14:0]} : {3'b000,addrbus[14:0]};
assign SRAM_UB_N = vid_rd ? 1'b0 : ~sram_msb;
assign SRAM_LB_N = vid_rd ? 1'b0 : sram_msb;
assign SRAM_WE_N = vid_rd ? 1'b1 : cpu_wr_n|addrbus[15]|hlda;
assign SRAM_OE_N = ~(vid_rd|cpu_rd);
assign SRAM_CE_N = 0;
biossd rom(.clka(clk50), .addra({addrbus[11]|startup,addrbus[10:0]}), .douta(rom_o));
//////////////////// CPU ////////////////////
wire[15:0] addrbus;
wire[7:0] cpu_o;
wire cpu_sync;
wire cpu_rd;
wire cpu_wr_n;
wire cpu_int;
wire cpu_inta_n;
wire inte;
reg[7:0] cpu_i;
always @(*)
casex (addrbus[15:13])
3'b0xx: cpu_i = startup ? rom_o : mem_o;
3'b100: cpu_i = ppa1_o;
3'b101: cpu_i = sd_o;
3'b110: cpu_i = crt_o;
3'b111: cpu_i = rom_o;
endcase
wire ppa1_we_n = addrbus[15:13]!=3'b100|cpu_wr_n;
wire ppa2_we_n = addrbus[15:13]!=3'b101|cpu_wr_n;
wire crt_we_n = addrbus[15:13]!=3'b110|cpu_wr_n;
wire crt_rd_n = addrbus[15:13]!=3'b110|~cpu_rd;
wire dma_we_n = addrbus[15:13]!=3'b111|cpu_wr_n;
reg cpu_flag;
reg[10:0] cpu_cnt;
wire cpu_ce = cpu_ce2;
wire cpu_ce2 = cpu_flag^cpu_cnt[10];
always @(posedge clk50) begin
cpu_cnt <= cpu_cnt + 11'd41;
cpu_flag <= cpu_flag^cpu_ce2;
startup <= reset|(startup&~addrbus[15]);
end
k580wm80a CPU(.clk(clk50), .ce(cpu_ce & hlda==0), .reset(reset),
.idata(cpu_i), .addr(addrbus), .sync(cpu_sync), .rd(cpu_rd), .wr_n(cpu_wr_n),
.intr(cpu_int), .inta_n(cpu_inta_n), .odata(cpu_o), .inte_o(inte));
//////////////////// VIDEO ////////////////////
wire[7:0] crt_o;
wire[3:0] vid_line;
wire[6:0] vid_char;
wire[15:0] vid_addr;
wire[3:0] dma_dack;
wire[7:0] dma_o;
wire[1:0] vid_lattr;
wire[1:0] vid_gattr;
wire vid_cce,vid_drq,vid_irq;
wire vid_lten,vid_vsp,vid_rvv,vid_hilight;
wire dma_owe_n,dma_ord_n,dma_oiowe_n,dma_oiord_n;
wire vid_rd = ~dma_oiord_n;
k580wt57 dma(.clk(clk50), .ce(vid_cce), .reset(reset),
.iaddr(addrbus[3:0]), .idata(cpu_o), .drq({1'b0,vid_drq,2'b00}), .iwe_n(dma_we_n), .ird_n(1'b1),
.hlda(hlda), .hrq(hlda), .dack(dma_dack), .odata(dma_o), .oaddr(vid_addr),
.owe_n(dma_owe_n), .ord_n(dma_ord_n), .oiowe_n(dma_oiowe_n), .oiord_n(dma_oiord_n) );
k580wg75 crt(.clk(clk50), .ce(vid_cce),
.iaddr(addrbus[0]), .idata(cpu_o), .iwe_n(crt_we_n), .ird_n(crt_rd_n),
.vrtc(VGA_VS), .hrtc(VGA_HS), .dack(dma_dack[2]), .ichar(mem_o), .drq(vid_drq), .irq(vid_irq),
.odata(crt_o), .line(vid_line), .ochar(vid_char), .lten(vid_lten), .vsp(vid_vsp),
.rvv(vid_rvv), .hilight(vid_hilight), .lattr(vid_lattr), .gattr(vid_gattr) );
rk_video vid(.clk50mhz(clk50), .hr(VGA_HS), .vr(VGA_VS), .cce(vid_cce),
.r(VGA_R), .g(VGA_G), .b(VGA_B), .line(vid_line), .ichar(vid_char),
.vsp(vid_vsp), .lten(vid_lten), .rvv(vid_rvv), .videomode(videomode) );
//////////////////// KBD ////////////////////
wire[7:0] kbd_o;
wire[2:0] kbd_shift;
rk_kbd kbd(.clk(clk50), .reset(reset), .ps2_clk(PS2_CLK), .ps2_dat(PS2_DAT),
.addr(~ppa1_a), .odata(kbd_o), .cpurst(cpurst), .videomode(videomode), .shift(kbd_shift));
//////////////////// SYS PPA ////////////////////
k580ww55 ppa1(.clk(clk50), .reset(reset), .addr(addrbus[1:0]), .we_n(ppa1_we_n),
.idata(cpu_o), .odata(ppa1_o), .ipa(ppa1_a), .opa(ppa1_a),
.ipb(~kbd_o), .opb(ppa1_b), .ipc({~kbd_shift,tapein,ppa1_c[3:0]}), .opc(ppa1_c));
//////////////////// SOUND ////////////////////
assign SOUND_L = ppa1_c[0]^inte;
assign SOUND_R = ppa1_c[0]^inte;
//////////////////// SD CARD ////////////////////
reg sdcs;
reg sdclk;
reg sdcmd;
reg[6:0] sddata;
wire[7:0] sd_o = {sddata, SD_DAT};
assign SD_DAT3 = ~sdcs;
assign SD_CMD = sdcmd;
assign SD_CLK = sdclk;
always @(posedge clk50 or posedge reset) begin
if (reset) begin
sdcs <= 1'b0;
sdclk <= 1'b0;
sdcmd <= 1'h1;
end else begin
if (addrbus[0]==1'b0 && ~ppa2_we_n) sdcs <= cpu_o[0];
if (addrbus[0]==1'b1 && ~ppa2_we_n) begin
if (sdclk) sddata <= {sddata[5:0],SD_DAT};
sdcmd <= cpu_o[7];
sdclk <= 1'b0;
end
if (cpu_rd) sdclk <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void inp(long long &n, long long &m, vector<long long> &v, vector<pair<signed, signed> > &rope) { cin >> n >> m; v.resize(n + 1); rope.resize(m + 1); for (long long i = 1; i <= n; ++i) { cin >> v[i]; } for (long long i = 1; i <= m; ++i) { cin >> rope[i].first >> rope[i].second; } } void solve() { long long n, m, res = 0; vector<long long> v; vector<pair<signed, signed> > rope; inp(n, m, v, rope); for (long long i = 1; i <= m; ++i) { res += min(v[rope[i].first], v[rope[i].second]); } cout << res; } signed main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; } |
// -*- Mode: Verilog -*-
// Filename : fw_interface.v
// Description : Firmware Testing Interface
// Author : Philip Tracton
// Created On : Wed Dec 21 14:03:49 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 21 14:03:49 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module fw_interface (/*AUTOARG*/
// Outputs
wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o, trigger_reg,
// Inputs
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i,
wb_bte_i, wb_cti_i, wb_cyc_i, wb_stb_i, interrupts
) ;
//
// Wishbone Interface
//
input wire wb_clk_i;
input wire wb_rst_i;
input wire [31:0] wb_adr_i;
input wire [31:0] wb_dat_i;
input wire [3:0] wb_sel_i;
input wire wb_we_i;
input wire [1:0] wb_bte_i;
input wire [2:0] wb_cti_i;
input wire wb_cyc_i;
input wire wb_stb_i;
output wire wb_ack_o;
output wire wb_err_o;
output wire wb_rty_o;
output wire [31:0] wb_dat_o;
output wire [31:0] trigger_reg;
//
// System Interface
//
input wire [31:0] interrupts;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] data; // From wb of fw_interface_wb.v
wire [31:0] error_reg; // From wb of fw_interface_wb.v
wire [31:0] expected_reg; // From wb of fw_interface_wb.v
wire [5:0] index; // From wb of fw_interface_wb.v
wire [31:0] measured_reg; // From wb of fw_interface_wb.v
wire new_compare; // From wb of fw_interface_wb.v
wire new_error; // From wb of fw_interface_wb.v
wire new_report; // From wb of fw_interface_wb.v
wire new_warning; // From wb of fw_interface_wb.v
wire [31:0] report_reg; // From wb of fw_interface_wb.v
wire [31:0] warning_reg; // From wb of fw_interface_wb.v
wire write_mem; // From wb of fw_interface_wb.v
// End of automatics
fw_interface_wb wb(/*AUTOINST*/
// Outputs
.wb_ack_o (wb_ack_o),
.wb_rty_o (wb_rty_o),
.wb_err_o (wb_err_o),
.wb_dat_o (wb_dat_o[31:0]),
.new_report (new_report),
.new_warning (new_warning),
.new_error (new_error),
.new_compare (new_compare),
.report_reg (report_reg[31:0]),
.warning_reg (warning_reg[31:0]),
.error_reg (error_reg[31:0]),
.expected_reg (expected_reg[31:0]),
.measured_reg (measured_reg[31:0]),
.trigger_reg (trigger_reg[31:0]),
.write_mem (write_mem),
.data (data[7:0]),
.index (index[5:0]),
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wb_adr_i[31:0]),
.wb_dat_i (wb_dat_i[31:0]),
.wb_sel_i (wb_sel_i[3:0]),
.wb_we_i (wb_we_i),
.wb_bte_i (wb_bte_i[1:0]),
.wb_cti_i (wb_cti_i[2:0]),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i));
fw_interface_logic logic_inst(/*AUTOINST*/
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.new_report (new_report),
.new_warning (new_warning),
.new_error (new_error),
.new_compare (new_compare),
.report_reg (report_reg[31:0]),
.warning_reg (warning_reg[31:0]),
.error_reg (error_reg[31:0]),
.expected_reg (expected_reg[31:0]),
.measured_reg (measured_reg[31:0]),
.index (index[5:0]),
.data (data[7:0]),
.write_mem (write_mem));
endmodule // fw_interface
|
#include <bits/stdc++.h> using namespace std; template <class n, class second> ostream &operator<<(ostream &p, pair<n, second> x) { return p << < << x.first << , << x.second << > ; } template <class n> auto operator<<(ostream &p, n y) -> typename enable_if<!is_same<n, string>::value, decltype(y.begin(), p)>::type { int o = 0; p << { ; for (auto c : y) { if (o++) p << , ; p << c; } return p << } ; } void dor() { cerr << endl; } template <class n, class... second> void dor(n p, second... y) { cerr << p << ; dor(y...); } template <class n, class second> void mini(n &p, second y) { if (p > y) p = y; } template <class n, class second> void maxi(n &p, second y) { if (p < y) p = y; } const int M = 1024 * 256; int n, k, x; int in[M]; int main() { scanf( %d%d , &n, &k); for (int i = (2); i <= (int)(n); ++i) { int a, b; scanf( %d%d , &a, &b); in[a]++; in[b]++; } for (int i = (1); i <= (int)(n); ++i) { if (in[i] == 1) { x++; } } printf( %.9Lf n , (long double)(k * 2) / x); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 2) { cout << white n1 2 n ; } else if (n % 2 == 0) { cout << white n1 2 n ; } else { cout << black n ; } } |
#include <bits/stdc++.h> using namespace std; void solve(long long case_no) { long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; ++i) cin >> a[i]; map<long long, long long> mp; long long mx = LONG_LONG_MIN; for (long long i = 0; i < n; ++i) { long long x = i + a[i] % n + n; ++mp[x % n]; if (mp[x % n] > 1) { cout << NO n ; return; } } cout << YES n ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t = 1; cin >> t; for (long long i = 0; i < t; ++i) { solve(i + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1); const long double eps = 0.0000000001; const long long INF = 0x3fffffffffffffff; long long a[200005], sum[200005], n, q, x, y; long long lowbit(long long now) { return now & -now; } void add(long long pos, long long v) { while (pos <= n) { sum[pos] += v; pos += lowbit(pos); } } long long query(long long now) { long long res = 0; while (now) { res += sum[now]; now ^= lowbit(now); } return res; } long long findnext(long long now) { long long l = now + 1, r = n + 1, v = query(now); while (l < r) { long long mid = (l + r) >> 1; if (query(mid) < v << 1) { l = mid + 1; } else { r = mid; } } return l; } signed main() { ios::sync_with_stdio(false); cin >> n >> q; for (long long i = 1; i <= n; ++i) { cin >> a[i]; add(i, a[i]); } for (long long i = 1; i <= q; ++i) { cin >> x >> y; add(x, -a[x]); a[x] = y; add(x, a[x]); long long now = 1; bool flag = false; if (a[1] == 0) { cout << 1 << endl; continue; } while (now <= n) { now = findnext(now); if (now <= n && query(now) == a[now] << 1) { cout << now << endl; flag = true; break; } } if (!flag) { cout << -1 << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int r[305]; int main() { int p, n; cin >> p >> n; int a[n + 5]; for (int i = 1; i <= n; i++) { cin >> a[i]; } int sum = 0, c = 0, f = -1; for (int i = 1; i <= n; i++) { c = a[i] % p; if (r[c] == 0) { f = -1; r[c]++; } else { f = i; break; } } cout << f << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int minr = 1e9 + 2; int maxl = 0; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; if (l > maxl) { maxl = l; } if (r < minr) { minr = r; } } int m; cin >> m; int minr2 = 1e9 + 2; int maxl2 = 0; for (int i = 0; i < m; i++) { int l, r; cin >> l >> r; if (l > maxl2) { maxl2 = l; } if (r < minr2) { minr2 = r; } } int diff1 = maxl - minr2; int diff2 = maxl2 - minr; int sol = max(max(diff1, diff2), 0); cout << sol << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, x; cin >> n >> x; long long sum = 0; for (int i = 0; i < n; i++) { long long a; cin >> a; sum += a; } if (sum + n - 1 == x) return 0 * puts( YES ); puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> gr[50005]; int parent[50005]; void dfs(int src, int par) { parent[src] = par; for (auto nbr : gr[src]) { if (nbr != par) dfs(nbr, src); } } int main() { int n, x, y; cin >> n >> x >> y; for (int i = 1; i <= n; i++) { if (i == x) continue; int p; cin >> p; gr[i].push_back(p); gr[p].push_back(i); } dfs(y, 0); for (int i = 1; i <= n; i++) { if (i == y) continue; cout << parent[i] << ; } return 0; } |
/*
stage_wrapper_tb.v
Abstract: оболочка для блока при конвееризации
*/
`include "vconst.v"
`timescale 1 ns / 100 ps
`define WIDTH 8
`define LEN_WORD 15
`define IN_WIDTH 8
`define OUT_WIDTH 8
module stage_wrapper_tb;
reg clk_tmp, rst, clk_ena;
wire clk_t;
wire clk;
//wire [`WIDTH-1:0] rsin; // вход данных в стенд - выход для кодера
//reg [`WIDTH-1:0] rsout;
// stream-control and interface
wire source_val;
wire source_sop;
reg source_sop_tmp;
wire source_eop;
reg source_eop_tmp;
// analysis
wire sink_val; // окно разрешения
wire sink_sop; // начало пакета
wire sink_eop; // конец пакета
wire source_ena;
assign source_ena = 1; // пусть пока без эксцессов
wire [`IN_WIDTH-1:0] pin, pin_latch;
reg [`OUT_WIDTH-1:0] pout;
// local
reg [2*`WIDTH-1:0] ibig; // для счетчика больших циклов
reg [2*`WIDTH-1:0] isbig; // для счетчика адресов маски
reg [`WIDTH-1:0] MemV[`LEN_WORD-1:0];
/// Connecting
stage_wrapper_rtl label_sw(
.clk(clk), .rst(rst), .clk_ena(clk_ena),
// control
// slave
.first(source_eop),
.windows(windows),
// master
.last(last),
// datastream
// in
.pin(pout), // параллельная шина синдромов
.pin_latch(pin_latch),
// out
.pout(pin)
// test
);
// stream-control and interface
initial begin // общие сигналы (в реализуемом они будут внешними)
clk_tmp = 0; rst = 0; clk_ena = 0;
// сброс пусть будет здесь
#2; rst = 1; #3; rst = 0;
end
always #20 clk_tmp = ~clk_tmp; // тактовый генератор
assign #15 clk = clk_tmp;
initial begin
//$readmemb("rs_255_full8_roots.vec ", MemV); // dvbt без ошибок
$readmemb("rs_drm_tb.vec", MemV); // 8 ошибок вроде бы
// загрузка в память слова(пока одного)
ibig = 'b0; isbig = 'b0;
source_sop_tmp = 'b0; source_eop_tmp = 'b0;
end
initial
begin
//#10; clk_ena = 1; #(`LEN_WORD*20); clk_ena = 0; #80; clk_ena = 1;
clk_ena = 1;
end
// чтение памяти
always @(posedge clk_tmp) begin
pout <= MemV[ibig%`LEN_WORD];
end
always @(posedge clk_tmp) begin
// рамки слова
if(ibig%`LEN_WORD == 0) // начало пакета
source_sop_tmp = 1;
else
source_sop_tmp = 0;
if(ibig%`LEN_WORD == `LEN_WORD-1) // начало пакета
source_eop_tmp = 1;
else
source_eop_tmp = 0;
end
always @(posedge clk_tmp) begin
if(clk_ena)
ibig = ibig+1;
end
// адрес для чтения из памяти маски разрешения
always @(posedge clk_tmp) begin
isbig = isbig+1;
end
// out
assign source_val = clk_ena;
assign source_sop = source_sop_tmp & clk_ena;
assign source_eop = source_eop_tmp & clk_ena;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_video_dma_control_slave (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
swap_addresses_enable,
// Bi-Directional
// Outputs
readdata,
current_start_address,
dma_enabled
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Parameters
parameter DEFAULT_BUFFER_ADDRESS = 32'h00000000;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'h00000000;
parameter WIDTH = 640; // Frame's width in pixels
parameter HEIGHT = 480; // Frame's height in lines
parameter ADDRESSING_BITS = 16'h0809;
parameter COLOR_BITS = 4'h7; // Bits per color plane minus 1
parameter COLOR_PLANES = 2'h2; // Color planes per pixel minus 1
parameter ADDRESSING_MODE = 1'b1; // 0: X-Y or 1: Consecutive
parameter DEFAULT_DMA_ENABLED = 1'b1; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input swap_addresses_enable;
// Bi-Directional
// Outputs
output reg [31: 0] readdata;
output [31: 0] current_start_address;
output reg dma_enabled;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [31: 0] buffer_start_address;
reg [31: 0] back_buf_start_address;
reg buffer_swap;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (read & (address == 2'h0))
readdata <= buffer_start_address;
else if (read & (address == 2'h1))
readdata <= back_buf_start_address;
else if (read & (address == 2'h2))
begin
readdata[31:16] <= HEIGHT;
readdata[15: 0] <= WIDTH;
end
else if (read)
begin
readdata[31:16] <= ADDRESSING_BITS;
readdata[15:12] <= 4'h0;
readdata[11: 8] <= COLOR_BITS;
readdata[ 7: 6] <= COLOR_PLANES;
readdata[ 5: 3] <= 3'h0;
readdata[ 2] <= dma_enabled;
readdata[ 1] <= ADDRESSING_MODE;
readdata[ 0] <= buffer_swap;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
buffer_start_address <= DEFAULT_BUFFER_ADDRESS;
back_buf_start_address <= DEFAULT_BACK_BUF_ADDRESS;
end
else if (write & (address == 2'h1))
begin
if (byteenable[0])
back_buf_start_address[ 7: 0] <= writedata[ 7: 0];
if (byteenable[1])
back_buf_start_address[15: 8] <= writedata[15: 8];
if (byteenable[2])
back_buf_start_address[23:16] <= writedata[23:16];
if (byteenable[3])
back_buf_start_address[31:24] <= writedata[31:24];
end
else if (buffer_swap & swap_addresses_enable)
begin
buffer_start_address <= back_buf_start_address;
back_buf_start_address <= buffer_start_address;
end
end
always @(posedge clk)
begin
if (reset)
buffer_swap <= 1'b0;
else if (write & (address == 2'h0))
buffer_swap <= 1'b1;
else if (swap_addresses_enable)
buffer_swap <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
dma_enabled <= DEFAULT_DMA_ENABLED;
else if (write & (address == 2'h3) & byteenable[0])
dma_enabled <= writedata[2];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign current_start_address = buffer_start_address;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(0); long long n, m; cin >> n >> m; vector<long long> a, b; vector<long long> sum1, sum2; long long prev = 0; for (int i = 0; i < n; i++) { long long x; cin >> x; prev += x; a.push_back(x); sum1.push_back(prev); } prev = 0; for (int i = 0; i < m; i++) { long long x; cin >> x; prev += x; b.push_back(x); sum2.push_back(prev); } long long z; cin >> z; vector<long long> dp1, dp2; for (int l = 1; l <= n; l++) { long long mini = sum1[l - 1]; for (int i = l; i < sum1.size(); i++) { mini = min(sum1[i] - sum1[i - l], mini); } dp1.push_back(mini); } for (int l = 1; l <= m; l++) { long long mini = sum2[l - 1]; for (int i = l; i < sum2.size(); i++) { mini = min(sum2[i] - sum2[i - l], mini); } dp2.push_back(mini); } long long prod = 0; for (long long i = 0; i < dp1.size(); i++) { for (long long j = 0; j < dp2.size(); j++) { if (dp1[i] * dp2[j] <= z) { prod = max((i + 1) * (j + 1), prod); } } } cout << prod; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_FUNCTIONAL_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlp2 (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const double PI = acos(-1); long long power(long long x, long long y) { if (y == 0) return 1; else if (y == 1) return x; long long r = power(x, y / 2); if (y % 2 == 0) return (r * r); else return (r * r * x); } bool primechecker(long long i) { bool valid = true; for (int j = 2; j <= sqrt(i); j++) { if (i % j == 0) { valid = false; break; } } if (valid && i != 1) return true; else return false; } vector<bool> prime(10000001, true); void sieveprime() { prime[0] = false; prime[1] = false; for (int i = 2; i < prime.size(); i++) { if (prime[i] == true) { for (int j = i + i; j <= 10000000; j += i) prime[j] = false; } } return; } int main() { int t; cin >> t; while (t--) { long long a, b; cin >> a >> b; cout << (a ^ b) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int bench, more, temp; vector<int> v; cin >> bench >> more; for (int i = 0; i < bench; i++) { cin >> temp; v.push_back(temp); } int min, max = *max_element(v.begin(), v.end()); ; min = *min_element(v.begin(), v.end()); int max_val = max + more; for (int i = 0; i < more; i++) { sort(v.begin(), v.end()); v[0]++; } std::sort(v.begin(), v.end(), std::greater<int>()); int min_val = v[0]; cout << min_val << << max_val; } |
#include <bits/stdc++.h> using namespace std; int n; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> s; s = ? + s + ? ; int c = 0; bool flag = true; for (int i = 1; i <= n; i++) { if (s[i] == ? ) { c++; if (s[i - 1] == s[i + 1] || s[i - 1] == ? || s[i + 1] == ? ) { flag = false; } } if (s[i] == s[i - 1] && s[i] != ? ) { flag = true; break; } } cout << (c == 0 || flag ? NO : YES ) << n ; return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:28:52 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xlconcat_0_0/zqynq_lab_1_design_xlconcat_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_xlconcat_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_xlconcat_0_0,xlconcat_v2_1_1_xlconcat,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_xlconcat_0_0
(In0,
In1,
dout);
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
wire [0:0]In0;
wire [0:0]In1;
assign dout[1] = In1;
assign dout[0] = In0;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; using namespace std; long long k, p; long long getZCY(long long x) { long long res = x; while (x) { res *= 10LL; res += x % 10; x /= 10; } return res; } int main() { scanf( %I64d , &k); scanf( %I64d , &p); long long ans = 0; for (int i = (1); i <= (int)(k); ++i) { ans += getZCY(i); ans %= p; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> a[200005], b; set<int> c1; int n, k, p, f[200005], x[200005], c[200005], c2[200005]; int getdeepth(int i) { for (vector<int>::iterator j = a[i].begin(); j != a[i].end(); j++) if ((*j) != f[i]) { f[*j] = i; int x = getdeepth(*j); c[i] += c[*j]; if (c[*j] >= k) return x; } return i; } void getdeepth1(int i) { for (vector<int>::iterator j = a[i].begin(); j != a[i].end(); j++) if ((*j) != f[i]) getdeepth1(*j); if (c2[i]) b.push_back(i), c1.erase(i); } int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin >> n >> k; for (int i = 1, j, l; i < n; i++) { cin >> j >> l; a[j].push_back(l); a[l].push_back(j); } for (int i = 1, j; i <= 2 * k; i++) { cin >> j; c[j] = c2[j] = 1; c1.insert(j); } p = getdeepth(1); getdeepth1(p); for (set<int>::iterator i = c1.begin(); i != c1.end(); i++) b.push_back(*i); cout << 1 << endl << p << endl; for (int i = 0; i < k; i++) cout << b[i] << << b[i + k] << << p << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_SYMBOL_V
`define SKY130_FD_SC_HS__O41AI_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_SYMBOL_V
|
module my_rand(clk,
rst,
seed0,
num
);
input clk;
input rst;
input [31:0] seed0;
output [31:0] num;
reg [31:0] num;
reg [31:0] seed;
reg [31:0] seed1,seed2;
reg [5:0] rst_d;
always @(posedge clk) begin
rst_d <= {rst_d[4:0], rst};
end
wire rnd_rst = | rst_d ;
always @(posedge clk) begin
seed <= seed0;
end
always @(posedge clk) begin
num = seed ^ seed1 ^ ~seed2;
end
always @(posedge clk or posedge rnd_rst) begin
if(rnd_rst) begin
seed1 = 32'hab312def;
seed2 = 32'hcd975130;
end else begin
seed1[31] = seed2[00]| ~seed1[09]| seed1[13];
seed1[30] = ~seed[17]^ ~seed1[06]| ~seed2[01];
seed1[29] = seed1[08]^ ~seed[07]^ seed1[03];
seed1[28] = seed2[20]^ seed1[02]& ~seed2[01];
seed1[27] = ~seed1[01]& seed[18]^ ~seed1[13];
seed1[26] = seed[04]^ seed[16]| ~seed2[22];
seed1[25] = ~seed2[20]| seed1[14]^ ~seed[05];
seed1[24] = ~seed[04]^ seed[20]& ~seed1[22];
seed1[23] = seed[15]^ ~seed2[07]^ seed1[08];
seed1[22] = seed2[05]| seed1[13]^ seed1[20];
seed1[21] = ~seed1[12]& seed[14]^ ~seed1[16];
seed1[20] = ~seed[11]^ ~seed1[11]^ seed2[01];
seed1[19] = seed2[00]^ seed[08]^ ~seed2[18];
seed1[18] = ~seed1[13]^ seed2[08]^ seed2[15];
seed1[17] = ~seed[12]& ~seed[16]| seed[15];
seed1[16] = ~seed2[14]| ~seed1[17]| ~seed[20];
seed1[15] = ~seed[18]& ~seed1[08]^ seed2[07];
seed1[14] = seed[13]^ ~seed[15]^ ~seed1[12];
seed1[13] = seed[10]^ ~seed1[13]^ ~seed[22];
seed1[12] = ~seed2[07]& seed2[03]& seed2[01];
seed1[11] = ~seed[06]^ ~seed2[11]| ~seed1[02];
seed1[10] = seed1[19]^ seed1[03]^ ~seed1[22];
seed1[09] = seed[15]^ seed2[11]^ ~seed1[10];
seed1[08] = ~seed1[15]^ seed2[22]^ seed[07];
seed1[07] = ~seed1[10]& ~seed2[10]| seed[01];
seed1[06] = ~seed2[05]^ ~seed[16]^ ~seed1[01];
seed1[05] = seed1[22]& ~seed2[00]^ seed1[07];
seed1[04] = seed[12]& ~seed1[15]^ ~seed[02];
seed1[03] = ~seed2[22]& ~seed[12]| ~seed1[03];
seed1[02] = seed2[17]^ ~seed1[02]^ ~seed1[21];
seed1[01] = seed2[05]^ ~seed2[09]^ ~seed[02];
seed1[00] = seed1[31] ^ seed2[16]^ ~seed1[14];
seed2[31] = ~seed1[20]& seed1[14]^ seed1[18];
seed2[30] = seed1[12]& ~seed1[04]^ ~seed[15];
seed2[29] = ~seed2[04]^ seed1[02]| seed1[02];
seed2[28] = seed2[15]^ ~seed[10]| seed[15];
seed2[27] = seed2[04]& seed[01]^ seed1[18];
seed2[26] = ~seed[09]^ seed1[22]^ ~seed1[20];
seed2[25] = ~seed[08]| ~seed[19]^ ~seed[02];
seed2[24] = seed[19]^ seed1[09]| ~seed[08];
seed2[23] = seed1[21]^ seed1[13]^ ~seed2[02];
seed2[22] = seed2[16]| ~seed[03]| ~seed2[17];
seed2[21] = seed[07]| seed1[20]^ seed1[13];
seed2[20] = ~seed2[22]& seed[22]& seed1[15];
seed2[19] = seed[06]& seed2[04]^ seed2[12];
seed2[18] = seed2[21]^ seed2[01]^ ~seed2[21];
seed2[17] = ~seed1[00]^ ~seed[15]^ seed2[08];
seed2[16] = ~seed2[21]^ ~seed1[07]^ ~seed1[06];
seed2[15] = ~seed2[20]^ seed[20]| seed1[00];
seed2[14] = ~seed2[09]^ seed2[18]^ seed1[14];
seed2[13] = ~seed[02]& ~seed[08]^ ~seed1[02];
seed2[12] = ~seed[10]| seed1[19]^ ~seed2[03];
seed2[11] = seed[02]^ ~seed[15]^ seed[11];
seed2[10] = seed[15]^ ~seed1[19]^ ~seed[03];
seed2[09] = ~seed2[14]^ seed2[22]^ ~seed1[06];
seed2[08] = seed[02]^ seed1[21]| ~seed2[15];
seed2[07] = ~seed1[17]^ seed1[03]^ seed1[18];
seed2[06] = ~seed[21]^ seed1[16]^ ~seed1[22];
seed2[05] = seed2[20]^ seed2[10]| ~seed[09];
seed2[04] = seed2[18]| ~seed[21]^ ~seed[14];
seed2[03] = seed2[14]^ ~seed1[13]^ ~seed[10];
seed2[02] = ~seed2[06]| ~seed[03]^ ~seed[15];
seed2[01] = ~seed2[03]^ ~seed[13]| seed1[05];
seed2[00] = ~seed2[31] & ~seed[15]& ~seed1[22];
end
end
endmodule
|
#include <bits/stdc++.h> struct Edge { long long to, dis, next; } edge[100100]; long long n, num_edge; long long first1[100100]; long long a[100100], b[100100]; double tem; void dfs(long long x, long long fa, long long p) { long long k = first1[x]; while (k != 0) { dfs(edge[k].to, x, edge[k].dis); k = edge[k].next; } if (a[x] < b[x]) b[fa] += b[x] - a[x]; else if (a[x] > b[x]) { tem = (double)(b[x] - a[x]) * p; if (tem < -110000000000000000) { printf( NO ); exit(0); } b[fa] -= p * (a[x] - b[x]); if (b[fa] < -110000000000000000) { printf( NO ); exit(0); } } } int main() { long long i, x, k; scanf( %lld , &n); for (i = 1; i <= n; i++) scanf( %lld , &b[i]); for (i = 1; i <= n; i++) scanf( %lld , &a[i]); for (i = 2; i <= n; i++) { scanf( %lld%lld , &x, &k); edge[++num_edge].to = i; edge[num_edge].dis = k; edge[num_edge].next = first1[x]; first1[x] = num_edge; } k = first1[1]; while (k != 0) { dfs(edge[k].to, 1, edge[k].dis); k = edge[k].next; } if (b[1] < a[1]) printf( NO ); else printf( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5, INF = 1e9 + 7; long long ans[N]; int main() { long long p, k; cin >> p >> k; long long tmp = -k; long long idx = 0; while (p != 0) { long long rem = p % tmp; p /= tmp; if (rem < 0) rem += k, p++; ans[idx] = rem; idx++; } cout << idx << endl; for (int i = 0; i < idx; i++) { cout << ans[i] << ; } } |
//`#start header` -- edit after this line, do not edit this line
// ========================================
// Copyright 2013 David Turnbull AE9RB
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 10/21/2012 at 15:53
// Component: SyncSOF
module SyncSOF (
input clock,
input sod,
input sof
);
//`#start body` -- edit after this line, do not edit this line
// This will sync the PSoC PLL to 38.864 MHz with a digital lock using
// the 1kHz from USB sof (start-of-frame). Counting begins at the start
// of buffer 0 obtained from the DMA communicating with the DelSigs.
// We want exactly exactly 36864 cycles per 1ms USB frame.
wire [6:0] clockcount1;
cy_psoc3_count7 #(.cy_period(7'b0111111))
Counter0 (
/* input */ .clock(clock),
/* input */ .reset(sod),
/* input */ .load(1'b0),
/* input */ .enable(1'b1),
/* output [6:0] */ .count(clockcount1),
/* output */ .tc(clocktc1)
);
wire [6:0] clockcount2;
cy_psoc3_count7 #(.cy_period(7'b0111111))
Counter1 (
/* input */ .clock(clocktc1),
/* input */ .reset(sod),
/* input */ .load(1'b0),
/* input */ .enable(1'b1),
/* output [6:0] */ .count(clockcount2),
/* output */ .tc(clocktc2)
);
wire [6:0] clockcount3;
cy_psoc3_count7 #(.cy_period(7'b0001000))
Counter2 (
/* input */ .clock(clocktc2),
/* input */ .reset(sod),
/* input */ .load(1'b0),
/* input */ .enable(1'b1),
/* output [6:0] */ .count(clockcount3),
/* output */ .tc()
);
// Report to the CPU where we are in the frame
reg [7:0] frame_pos_hi;
cy_psoc3_status #(.cy_md_select(8'h00), .cy_force_order(`TRUE))
FRAME_POS_HI ( .status( frame_pos_hi ));
reg frame_pos_ready;
reg [6:0] frame_pos_lo;
cy_psoc3_status #(.cy_md_select(8'h01), .cy_force_order(`TRUE))
FRAME_POS_LO (
.status( {frame_pos_lo, frame_pos_ready} ),
.clock(clock)
);
// Which buffer to use for USB DMA.
reg [1:0] buffer;
cy_psoc3_status #(.cy_md_select(8'h00), .cy_force_order(`TRUE))
BUFFER ( .status({6'b0, buffer}) );
reg sof_sync;
always @(posedge sof or posedge sod)
begin
if (sod) buffer <= 1;
else
begin
sof_sync <= ~sof_sync;
if (buffer == 2 ) buffer <= 0;
else buffer <= buffer + 1;
end
end
reg sof_prev;
always @(posedge clock)
begin
if (sof_sync != sof_prev)
begin
sof_prev <= sof_sync;
frame_pos_hi = {clockcount3[3:0], clockcount2[5:2]};
frame_pos_lo = {clockcount2[1:0], clockcount1[5:1]};
frame_pos_ready = 1;
end
else frame_pos_ready = 0;
end
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 * 100 * 2 + 152; long long n, m, x, y, z, q, mark[maxn], k = 1, par1[maxn], sum[maxn], h[maxn]; pair<long long, long long> par[17][maxn]; vector<pair<long long, long long> > v[maxn]; pair<long long, pair<long long, long long> > edg[maxn]; void dfs(int x) { mark[x] = k; for (int i = 0; i < v[x].size(); i++) if (!mark[v[x][i].first]) { sum[k] += v[x][i].second; par[0][v[x][i].first] = make_pair(x, v[x][i].second); h[v[x][i].first] = h[x] + 1; dfs(v[x][i].first); } } int find_par(int x) { if (x == par1[x]) return x; return par1[x] = find_par(par1[x]); } long long LCA(int x, int y) { if (h[x] > h[y]) swap(x, y); long long fa = h[y] - h[x], jack = 0, MAX = 0; for (int i = 0; i < 17; i++) if ((1 << i) & fa) { MAX = max(MAX, par[i][y].second); y = par[i][y].first; } for (int i = 16; i >= 0; i--) if (par[i][x].first != par[i][y].first) { MAX = max(MAX, max(par[i][x].second, par[i][y].second)); x = par[i][x].first; y = par[i][y].first; } if (x != y) MAX = max(MAX, max(par[0][x].second, par[0][y].second)); return MAX; } int main() { cin >> n >> m; for (int i = 0; i < m; i++) cin >> edg[i].second.first >> edg[i].second.second >> edg[i].first; for (int i = 1; i <= n; i++) par1[i] = i; sort(edg, edg + m); for (int i = 0; i < m; i++) { int x = find_par(edg[i].second.first), y = find_par(edg[i].second.second); if (x == y) continue; v[edg[i].second.first].push_back( make_pair(edg[i].second.second, edg[i].first)); v[edg[i].second.second].push_back( make_pair(edg[i].second.first, edg[i].first)); par1[x] = y; } for (int i = 1; i <= n; i++) if (!mark[i]) { dfs(i); k++; } for (int i = 1; i < 17; i++) for (int j = 1; j <= n; j++) par[i][j] = make_pair( par[i - 1][par[i - 1][j].first].first, max(par[i - 1][j].second, par[i - 1][par[i - 1][j].first].second)); cin >> q; while (q--) { cin >> x >> y; if (k > 3 || (k == 3 && mark[x] == mark[y])) { cout << -1 << endl; continue; } if (k == 3) { cout << sum[1] + sum[2] << endl; continue; } long long jack = LCA(x, y); cout << sum[1] - jack << endl; } return 0; } |
module top;
reg pass;
wire [2:-1] vec1;
wire [2:-1] vec2;
wire [2:-1] vec3;
wire [2:-1] vec4;
wire [2:-1] vec5;
wire [2:-1] vec6;
assign vec1 = 4'bxxxx;
assign vec2 = 4'bxxxx;
assign vec3 = 4'bxxxx;
assign vec4 = 4'bxxxx;
assign vec5 = 4'bxxxx;
assign vec6 = 4'bxxxx;
assign vec1[1'bx] = 1'b1;
assign vec2[1'bx:0] = 1'b1;
assign vec3[0:1'bx] = 1'b1;
assign vec4[1'bx:1'bx] = 1'b1;
assign vec5[1'bx+:1] = 1'b1;
assign vec6[1'bx-:1] = 1'b1;
initial begin
pass = 1'b1;
if (vec1 !== 4'bxxx) begin
$display("Failed vec1, expected 4'bxxxx, got %b", vec1);
pass = 1'b0;
end
if (vec2 !== 4'bxxx) begin
$display("Failed vec2, expected 4'bxxxx, got %b", vec2);
pass = 1'b0;
end
if (vec3 !== 4'bxxx) begin
$display("Failed vec3, expected 4'bxxxx, got %b", vec3);
pass = 1'b0;
end
if (vec4 !== 4'bxxx) begin
$display("Failed vec4, expected 4'bxxxx, got %b", vec4);
pass = 1'b0;
end
if (vec5 !== 4'bxxx) begin
$display("Failed vec5, expected 4'bxxxx, got %b", vec5);
pass = 1'b0;
end
if (vec6 !== 4'bxxx) begin
$display("Failed vec6, expected 4'bxxxx, got %b", vec6);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Problem: A. Robot Program // Contest: Codeforces - Educational Codeforces Round 98 (Rated for Div. 2) // URL: https://codeforces.com/contest/1452/problem/A // Memory Limit: 256 MB // Time Limit: 2000 ms // Powered by CP Editor (https://github.com/cpeditor/cpeditor) #include <bits/stdc++.h> using namespace std; #define fi first #define se second #define pb push_back #define int long long #define F(i, n) for (int i = 0; i < n; i++) #define all(x)(x).begin(), (x).end() using ld = long double; using vi = vector <int>; using mi = map <int, int>; using pii = pair <int, int>; const int N = 100005; const int MOD = 1e9 + 7; #define show(arr) { for (auto x: arr) cout << x << ; cout << n ; } #define show_(arr, n) F(i, n) show(arr[i]) void solve() { int n; cin>>n; int a[n],sum=0,mx=0; F(i,n){ cin>>a[i]; sum+=a[i]; mx=max(mx,a[i]); } cout<<max((n-1)*((sum+n-2)/(n-1)),mx*(n-1))-sum<< n ; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int32_t t=1; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[200015]; char s[200015]; vector<pair<int, int> > ans; int main() { scanf( %d , &n); for (int i = (1); i <= (n); i++) scanf( %d , &a[i]); scanf( %s , s + 1); sort(a + 1, a + n + 1); int lp = 1, rp = n; for (int i = (1); i <= (n); i++) if (i == 1 || s[i] != s[i - 1]) rp--; lp = rp++; bool flag = 0; for (int l = 1, r; l <= n; l = r + 1) { r = l; while (r < n && s[r + 1] == s[l]) r++; int len = r - l + 1; ans.push_back(make_pair(a[rp++], s[l] == R )); for (int _ = (1); _ <= (len - 1); _++) { ans.push_back(make_pair(a[lp--], (s[1] == L ) ^ flag)); flag ^= 1; } } for (auto x : ans) { printf( %d %c n , x.first, x.second == 0 ? L : R ); } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3 ) template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; int main(); void file() {} void time() {} const int INF = 1e9 + 99; using ll = long long int; using pii = pair<int, int>; using vec = vector<int>; int main() { ios_base::sync_with_stdio(0); ; ll n; cin >> n; vector<ll> v(n); for (ll& x : v) { cin >> x; } sort(v.begin(), v.end()); ll i = 0, j = n - 1; ll x = 0, y = 0; bool ok = false; while (i <= j) { if (ok) { x += v[i]; i++; } else { y += v[j]; j--; } ok ^= 1; } ll ans = x * x + y * y; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; double dist[5001][5001]; double x[5001], y[5001], z[5001]; int n; double sqr(double x) { return x * x; } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> x[i] >> y[i] >> z[i]; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { dist[i][j] = sqrt(sqr(x[i] - x[j]) + sqr(y[i] - y[j]) + sqr(z[i] - z[j])); dist[j][i] = dist[i][j]; } } double distance = 100000; for (int i = 2; i <= n; i++) { double minn = 100000; for (int j = 2; j <= n; j++) { if (i != j) { if (dist[1][j] + dist[j][i] < minn) minn = dist[1][j] + dist[j][i]; } } if (dist[1][i] + (minn - dist[1][i]) / 2 < distance) distance = dist[1][i] + (minn - dist[1][i]) / 2; } cout.precision(20); cout << distance; return 0; } |
`timescale 1 ns /10 ps
`include "alu.v"
`include "componentes.v"
`include "cpu.v"
`include "cpu_vga.v"
`include "e_s.v"
`include "memprog.v"
`include "memvga.v"
`include "microc.v"
`include "uc.v"
// `include "vga.v"
module cpu_vga_tb;
reg clk, reset;
reg [7:0] e1,e2,e3,e4;
wire [7:0] s1,s2,s3,s4;
wire [5:0] opcode;
wire [2:0] operacion;
wire z;
always
begin
clk = 1;
#20;
clk = 0;
#60;
end
initial
begin
$monitor("time: %0d, clk: %b, reset: %b", $time, clk, reset);
$dumpfile("cpu_vga_tb.vcd");
$dumpvars;
e1 = 8'b00000011; //1
e2 = 8'b00000011; //8
e3 = 8'b00000001; //5
e4 = 8'b00000000; //128
reset = 1;
#5
reset = 0;
#5000
$finish;
end
// input wire clk, reset,
// input wire [3:0] e1,
// input wire [3:0] e2,
// input wire [1:0] e3,
// input wire [7:0] e4,
// input VGA_CLOCK,
// output wire [7:0] s1,s2,s3,s4,
// output wire [5:0] opcode,
// output wire z, //añadir nue
cpu_vga cpu_vga_(
.clk (clk),
.reset (e4),
.e1 (e1),
.e2 (e2),
.e3 (e3),
.e4 (e4),
.s1 (s1),
.s2 (s2),
.s3 (s3),
.s4 (s4),
.opcode (opcode),
.z (z));
endmodule |
#include <bits/stdc++.h> using namespace std; string s; int dpl[2010], dpr[2010]; int main() { cin >> s; memset(dpr, 0, sizeof(dpr)); memset(dpl, 0, sizeof(dpl)); int i, j, k; for (i = 0; i < s.size(); i++) { for (j = i, k = i; j >= 0 && k < s.size() && s[k] == s[j]; j--, k++) dpl[j]++, dpr[k]++; for (j = i, k = i + 1; j >= 0 && k < s.size() && s[k] == s[j]; j--, k++) dpl[j]++, dpr[k]++; } for (i = 1; i < s.size(); i++) dpr[i] += dpr[i - 1]; long long ans = 0; for (i = 1; i < s.size(); i++) ans += dpr[i - 1] * dpl[i]; printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e3 + 5; const int MOD = 1e9 + 7; int N, M, A, B; int G[MAXN * MAXN], X, Y, Z; int H[MAXN][MAXN]; int P[MAXN][MAXN]; int T[MAXN][MAXN]; long long ans; deque<pair<int, int> > qu; void reset() { qu.clear(); } void push(int v, int p) { while (qu.size() && qu.back().first >= v) { qu.pop_back(); } qu.push_back({v, p}); } int pop(int p) { while (qu.size() && qu.front().second < p) { qu.pop_front(); } assert(qu.size()); return qu.front().first; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> N >> M >> A >> B; cin >> G[0] >> X >> Y >> Z; for (int i = 1; i < N * M; i++) { G[i] = (1LL * G[i - 1] * X + Y) % Z; } for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { H[i][j] = G[i * M + j]; } } for (int i = 0; i < N; i++) { reset(); for (int j = 0; j < B; j++) push(H[i][j], j); P[i][B - 1] = pop(0); for (int j = B; j < M; j++) { push(H[i][j], j); P[i][j] = pop(j - B + 1); } } for (int j = B - 1; j < M; j++) { reset(); for (int i = 0; i < A; i++) push(P[i][j], i); ans += pop(0); for (int i = A; i < N; i++) { push(P[i][j], i); ans += pop(i - A + 1); } } cout << ans << endl; return 0; } |
// file: main_pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______466.667_____50.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module main_pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (20),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pll = pair<ll, ll>; using dd = long double; namespace { static bool constexpr dbg = 0; ll constexpr N = -999; ll n, k; bool ok(string const &s1, string const &s2) { do { if (dbg) { bool b = (s1.size() == s2.size() + 1); if (!b) cerr << s1.size() == s2.size() + 1 << : failed! n ; } } while (0); if (s1.size() != s2.size()) return s1.size() > s2.size(); for (int i = 0; i < n; ++i) if (s1[i] != s2[i]) return s1[i] > s2[i]; return true; } string solve() { string s; cin >> n >> k >> s; cout << n << n ; auto sub = s.substr(0, k); while (sub.size() < n) sub.push_back(sub[sub.size() - k]); if (ok(sub, s)) return sub; int i = k - 1; for (; i >= 0; --i) if (s[i] != 9 ) break; ++s[i]; for (++i; i < k; ++i) s[i] = 0 ; for (int j = k; j < n; ++j) s[j] = s[j - k]; return s; } } // namespace int main() { if (!dbg) { std::ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } cout << fixed << setprecision(20); cout << solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> ans; bool check(string s, int L, int R) { if (s[L] == 0 ) { if (R == L + 1) { return true; } return false; } int n = 0; for (int i = L; i < R; i++) { n *= 10; n += s[i] - 0 ; } return (n >= 0 && n < 256); } void func(string s) { int N = s.length(); for (int i = 1; i <= 3; i++) { for (int j = i + 1; j <= i + 3; j++) { for (int k = j + 1; k <= j + 3; k++) { if (N - k >= 1 && N - k <= 3) { if (check(s, 0, i) && check(s, i, j) && check(s, j, k) && check(s, k, N)) { string final; final = s.substr(0, i) + . + s.substr(i, j - i) + . + s.substr(j, k - j) + . + s.substr(k, N - k); ans.push_back(final); } } } } } } void dfs(int L, string s, int mask, int pos, int used) { if (pos == L) { if (used == mask) { func(s); return; } } int pos2 = L - 1 - pos; if (pos2 < pos) { if (mask != used) { return; } char c = s[pos2]; dfs(L, s + c, mask, pos + 1, used); } else { char c; for (int i = 0; i < 10; i++) { if (mask & (1 << i)) { c = i + 0 ; dfs(L, s + c, mask, pos + 1, (used | (1 << i))); } } } } int main() { int n; int a[11]; cin >> n; int mask = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; mask |= (1 << a[i]); } if (n <= 6) { for (int i = 4; i <= 12; i++) { dfs(i, , mask, 0, 0); } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) { cout << ans[i].c_str() << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-12; const int maxn = 100000 + 1912; const int MX = 1e6; int n; pair<int, int> a[maxn]; vector<int> p[MX * 2 + 3]; long long res = 0; void ReadData() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &a[i].first, &a[i].second); a[i].first += MX; a[i].second += MX; p[a[i].first].push_back(a[i].second); } for (int i = 0; i <= MX * 2; i++) if (((int)p[i].size())) sort(p[i].begin(), p[i].end()); } bool Found(int x, int y) { if (x < 0 || x > MX * 2) return false; vector<int>::iterator it = lower_bound(p[x].begin(), p[x].end(), y); if (it != p[x].end() && (*it) == y) return true; return false; } void Process() { for (int i = 0; i <= MX * 2; i++) if (((int)p[i].size())) { if (((int)p[i].size()) <= 520) { for (int fi = 0; fi < ((int)p[i].size()); fi++) for (int se = 0; se < fi; se++) { int len = p[i][fi] - p[i][se]; if (i >= len && Found(i - len, p[i][se]) && Found(i - len, p[i][fi])) res++; } } else { for (int j = 0; j <= i - 1; j++) { int len = i - j; for (int k = 0; k < ((int)p[j].size()); k++) { if (Found(i, p[j][k]) && Found(j, p[j][k] + len) && Found(i, p[j][k] + len)) res++; } } } } cout << res << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ReadData(); Process(); } |
#include <bits/stdc++.h> using namespace std; struct SCC { vector<pair<int, int>> minmax; int size; SCC(vector<int> v) { minmax.resize(v.size()); for (int i = 0; i < (int)v.size(); i++) { minmax[i].first = v[i]; minmax[i].second = v[i]; } size = 1; } bool operator<(SCC const& other) const { for (int i = 0; i < (int)minmax.size(); i++) { if (other.minmax[i].first < minmax[i].second) return false; } return true; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; set<SCC> s; for (int i = 0; i < n; i++) { vector<int> v(k); for (int i = 0; i < k; i++) { cin >> v[i]; } SCC scc(v); auto a = s.lower_bound(scc); auto b = s.upper_bound(scc); if (a != b) { auto x = a; while (x != b) { for (int K = 0; K < k; K++) { scc.minmax[K].first = min(scc.minmax[K].first, x->minmax[K].first); scc.minmax[K].second = max(scc.minmax[K].second, x->minmax[K].second); } scc.size += x->size; x++; } s.erase(a, b); } s.insert(scc); cout << s.rbegin()->size << n ; } } |
`ifndef _control
`define _control
module control(
input wire [5:0] opcode,
output reg branch_eq, branch_ne,
output reg [1:0] aluop,
output reg memread, memwrite, memtoreg,
output reg regdst, regwrite, alusrc,
output reg jump);
always @(*) begin
/* defaults */
aluop[1:0] <= 2'b10;
alusrc <= 1'b0;
branch_eq <= 1'b0;
branch_ne <= 1'b0;
memread <= 1'b0;
memtoreg <= 1'b0;
memwrite <= 1'b0;
regdst <= 1'b1;
regwrite <= 1'b1;
jump <= 1'b0;
case (opcode)
6'b100011: begin /* lw */
memread <= 1'b1;
regdst <= 1'b0;
memtoreg <= 1'b1;
aluop[1] <= 1'b0;
alusrc <= 1'b1;
end
6'b001000: begin /* addi */
regdst <= 1'b0;
aluop[1] <= 1'b0;
alusrc <= 1'b1;
end
6'b000100: begin /* beq */
aluop[0] <= 1'b1;
aluop[1] <= 1'b0;
branch_eq <= 1'b1;
regwrite <= 1'b0;
end
6'b101011: begin /* sw */
memwrite <= 1'b1;
aluop[1] <= 1'b0;
alusrc <= 1'b1;
regwrite <= 1'b0;
end
6'b000101: begin /* bne */
aluop[0] <= 1'b1;
aluop[1] <= 1'b0;
branch_ne <= 1'b1;
regwrite <= 1'b0;
end
6'b000000: begin /* add */
end
6'b000010: begin /* j jump */
jump <= 1'b1;
end
endcase
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { bool flag = 0, flag2 = 0; long long n, m, c = 0; cin >> n >> m; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (i % 2 != 0 && c % 2 == 0 && j != m - 1) { cout << . ; flag = 1; } else if (i % 2 != 0 && c % 2 != 0 && j != 0) { cout << . ; flag2 = 1; } else cout << # ; } cout << endl; if (flag || flag2) c++; flag = 0, flag2 = 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, T, ans; int t[N]; priority_queue<int> pq; int main() { scanf( %d%d , &n, &T); for (int i = 1; i <= n; ++i) { scanf( %d , &t[i]); t[i] = t[i] > i ? t[i] - i : 0; } for (int i = 1; i <= n; ++i) { pq.push(t[i]); while ((long long)pq.top() + i >= T && !pq.empty()) { pq.pop(); } ans = max(ans, (int)pq.size()); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e6; const int maxv = 4e5; const long long INF = 3e14 + 333; struct Node { int u, v, c; void in() { scanf( %d%d%d , &u, &v, &c); } } wo[maxn]; vector<int> G[maxv], st[maxv], ed[maxv]; int n, m; int dfn = 0; int d[maxv][2]; int wd[maxv]; void dfs(int v, int f) { d[v][0] = dfn; for (int i = 0; i < G[v].size(); i++) { int u = G[v][i]; if (u == f) continue; dfs(u, v); } for (int i = 0; i < st[v].size(); i++) wd[st[v][i]] = dfn++; d[v][1] = dfn; } unsigned long long dp[maxn]; unsigned long long val[maxn], add[maxn]; void push(int o, int l, int r) { if (r - l <= 1 || !add[o]) return; val[((o << 1))] += add[o]; val[((o << 1) | 1)] += add[o]; add[((o << 1))] += add[o]; add[((o << 1) | 1)] += add[o]; add[o] = 0; } void change(int o, int p, int l, int r, unsigned long long x) { push(o, l, r); if (r - l <= 1) { val[o] = x; return; } if (p < ((r + l) >> 1)) change(((o << 1)), p, l, ((r + l) >> 1), x); else change(((o << 1) | 1), p, ((r + l) >> 1), r, x); val[o] = min(val[((o << 1))], val[((o << 1) | 1)]); } void Add(int o, int a, int b, int l, int r, unsigned long long x) { if (a >= r || b <= l) return; push(o, l, r); if (l >= a && r <= b) { val[o] += x; add[o] += x; return; } Add(((o << 1)), a, b, l, ((r + l) >> 1), x); Add(((o << 1) | 1), a, b, ((r + l) >> 1), r, x); val[o] = min(val[((o << 1))], val[((o << 1) | 1)]); } unsigned long long rmq(int o, int a, int b, int l, int r) { if (a >= r || b <= l) return INF; push(o, l, r); if (l >= a && r <= b) return val[o]; return min(rmq(((o << 1)), a, b, l, ((r + l) >> 1)), rmq(((o << 1) | 1), a, b, ((r + l) >> 1), r)); } unsigned long long ans = 0; void DP(int v, int f) { unsigned long long sum = 0; for (int i = 0; i < G[v].size(); i++) { int u = G[v][i]; if (u == f) continue; DP(u, v); sum += dp[u]; } for (int i = 0; i < G[v].size(); i++) { int u = G[v][i]; if (u == f) continue; Add(1, d[u][0], d[u][1], 0, m, sum - dp[u]); } for (int i = 0; i < st[v].size(); i++) { int w = st[v][i]; change(1, wd[w], 0, m, sum + wo[w].c); } for (int i = 0; i < ed[v].size(); i++) { int w = ed[v][i]; change(1, wd[w], 0, m, INF); } if (v == 1) ans = sum; dp[v] = rmq(1, d[v][0], d[v][1], 0, m); } int main() { cin >> n >> m; for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d%d , &x, &y); G[x].push_back(y); G[y].push_back(x); } for (int i = 0; i < m; i++) { wo[i].in(); st[wo[i].u].push_back(i); ed[wo[i].v].push_back(i); } for (int i = 0; i < m; i++) change(1, i, 0, m, INF); dfs(1, -1); DP(1, -1); if (ans >= INF) cout << -1 << endl; else cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long oo = 0x3f3f3f3f3f3f3f3fll; const int LGN = 25; const int MOD = 1e9 + 7; const int N = 3e5 + 5; int n, a[N], m, l[N], r[N]; int mem[N * LGN], cnt; int* alloc(int x) { int* p = mem + cnt; cnt += x; return p; } struct { int* a; int ans; } st[4 * N]; void build(int p = 1, int L = 1, int R = n) { if (R < L) return; if (L == R) { st[p].a = alloc(1); st[p].a[0] = ::a[L]; st[p].ans = oo; return; } int m = (L + R) >> 1; build(2 * p, L, m), build(2 * p + 1, m + 1, R); st[p].a = alloc(R - L + 1); int* lf = st[2 * p].a; int* ri = st[2 * p + 1].a; merge(lf, lf + (m - L + 1), ri, ri + (R - m), st[p].a); st[p].ans = oo; for (long long i = 1, __R = R - L; i <= __R; i++) st[p].ans = min(st[p].ans, st[p].a[i] - st[p].a[i - 1]); } int query(int l, int r, int p = 1, int L = 1, int R = n); void update(int i, int v, int& d, int p = 1, int L = 1, int R = n) { if (R < L || i < L || R < i) return; if (L == R) { st[p].ans = min(st[p].ans, abs(st[p].a[0] - v)); d = min(d, st[p].ans); return; } int j = upper_bound(st[p].a, st[p].a + (R - L + 1), v) - st[p].a; if ((j == 0 || d <= v - st[p].a[j - 1]) && (j == R - L + 1 || d <= st[p].a[j] - v)) { d = min(d, query(L, i, p, L, R)); return; } int m = (L + R) >> 1; if (i <= m) update(i, v, d, 2 * p, L, m); else { update(i, v, d, 2 * p + 1, m + 1, R); update(m, v, d, 2 * p, L, m); } st[p].ans = min(st[p].ans, min(st[2 * p].ans, st[2 * p + 1].ans)); } int query(int l, int r, int p, int L, int R) { if (R < L || r < L || R < l) return oo; if (l <= L && R <= r) return st[p].ans; int m = (L + R) >> 1; return min(query(l, r, 2 * p, L, m), query(l, r, 2 * p + 1, m + 1, R)); } int main() { std::ios::sync_with_stdio(false); scanf( %d , &(n)); for (long long i = 1, __R = n; i <= __R; i++) scanf( %d , &(a[i])); build(); scanf( %d , &(m)); static int idx[N]; for (long long i = 1, __R = m; i <= __R; i++) scanf( %d%d , &(l[i]), &(r[i])), idx[i] = i; sort(idx + 1, idx + m + 1, [](int i, int j) { return r[i] < r[j]; }); int curr = 1; static int ans[N]; for (long long j = 1, __R = m; j <= __R; j++) { int i = idx[j]; while (curr < r[i]) { curr++; int d = oo; update(curr - 1, a[curr], d); } ans[i] = query(l[i], r[i]); } for (long long i = 1, __R = m; i <= __R; i++) printf( %d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; string A, B; cin >> A >> B; int ans = 0; for (int x = 0; x < N - 1 - x; x++) { vector<char> v; v = {A[x], A[N - 1 - x], B[x], B[N - 1 - x]}; sort(v.begin(), v.end()); if (v[0] == v[1] && v[2] == v[3]) continue; if ((v[0] == v[1] && v[1] == v[2]) || (v[1] == v[2] && v[2] == v[3])) { ans++; continue; } bool flag = true; for (int y = 1; y < 4; y++) if (v[y] == v[y - 1] && A[x] != A[N - 1 - x]) { cerr << v[y] << << v[y - 1] << endl; ans++; flag = false; break; } if (flag) ans += 2; } if (N % 2 && A[N / 2] != B[N / 2]) ans++; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int i, t = 1, j, temp; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) { long long int n, k = 0; cin >> n; long long int a[n]; map<int, long long int> m; for (i = 0; i < n; i++) { cin >> a[i]; m[a[i]]++; } map<int, long long int>::iterator itr; for (itr = m.begin(); itr != m.end(); itr++) { if (k < (itr->second)) { k = itr->second; } } if (n % 2) { (k <= ((n + 1) / 2)) ? cout << YES : cout << NO ; } else { (k <= (n / 2)) ? cout << YES : cout << NO ; } } return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 11479 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w16,
w17,
w544,
w545,
w4360,
w4905,
w16384,
w11479;
assign w1 = i_data0;
assign w11479 = w16384 - w4905;
assign w16 = w1 << 4;
assign w16384 = w1 << 14;
assign w17 = w1 + w16;
assign w4360 = w545 << 3;
assign w4905 = w545 + w4360;
assign w544 = w17 << 5;
assign w545 = w1 + w544;
assign o_data0 = w11479;
//multiplier_block area estimate = 6316.83369385294;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[1000005], b[1000005], s[1000005]; int k, T, tmp[27], vis[27], p, n, tt[27], vv[27]; bool check(int x, int cas) { memcpy(tt, tmp, sizeof(tt)); memcpy(vv, vis, sizeof(vv)); if (cas == 1) { for (int i = x; i <= n; i++) { if (tt[s[i] - a ] != -1) { if (tt[s[i] - a ] > a[i]) return 1; if (tt[s[i] - a ] < a[i]) return 0; continue; } for (int j = a[i] + 1; j <= k + a - 1; j++) if (!vv[j - a ]) return 1; if (!vv[a[i] - a ]) vv[a[i] - a ] = 1, tt[s[i] - a ] = a[i]; else return 0; } return 1; } else { for (int i = x; i <= n; i++) { if (tt[s[i] - a ] != -1) { if (tt[s[i] - a ] > b[i]) return 0; if (tt[s[i] - a ] < b[i]) return 1; continue; } for (int j = a ; j < b[i]; j++) if (!vv[j - a ]) return 1; if (!vv[b[i] - a ]) vv[b[i] - a ] = 1, tt[s[i] - a ] = b[i]; else return 0; } return 1; } } void solve() { scanf( %d%s%s%s , &k, s + 1, a + 1, b + 1); n = strlen(s + 1); memset(tmp, -1, sizeof(tmp)); p = n + 1; memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; i++) if (a[i] == b[i]) { if (tmp[s[i] - a ] == a[i]) continue; if (tmp[s[i] - a ] == -1 && !vis[a[i] - a ]) tmp[s[i] - a ] = a[i], vis[a[i] - a ] = 1; else { puts( NO ); return; } } else { p = i; break; } int flag = 0; for (int i = p; i <= n; i++) { if (!flag && a[i] > b[i]) { puts( NO ); return; } if (tmp[s[i] - a ] != -1) { if ((((flag & 2) == 0) && tmp[s[i] - a ] < a[i]) || (((flag & 4) == 0) && tmp[s[i] - a ] > b[i])) { puts( NO ); return; } if ((flag & 2) == 0 && tmp[s[i] - a ] > a[i]) flag |= 2; if ((flag & 4) == 0 && tmp[s[i] - a ] < b[i]) flag |= 4; } else if ((flag & 6) == 0) { bool used = 0; for (int j = a[i] + 1; j < b[i]; j++) if (!vis[j - a ]) { tmp[s[i] - a ] = j; vis[j - a ] = 1; flag |= 6; used = 1; break; } if (!used) { if (!used && !vis[b[i] - a ]) { vis[b[i] - a ] = 1, tmp[s[i] - a ] = b[i]; if (!check(i + 1, 2)) vis[b[i] - a ] = 0, tmp[s[i] - a ] = -1; else flag |= 2, used = 1; } if (!used && !vis[a[i] - a ]) { vis[a[i] - a ] = 1, tmp[s[i] - a ] = a[i]; if (check(i + 1, 1)) flag |= 4, used = 1; } if (!used) { puts( NO ); return; } } } else if ((flag & 2) == 0) { bool used = 0; for (int j = a[i] + 1; j <= k + a - 1; j++) if (!vis[j - a ]) { tmp[s[i] - a ] = j; vis[j - a ] = 1; flag |= 2; used = 1; break; } if (!used) { if (!vis[a[i] - a ]) vis[a[i] - a ] = 1, tmp[s[i] - a ] = a[i]; else { puts( NO ); return; } } } else if ((flag & 4) == 0) { bool used = 0; for (int j = a ; j < b[i]; j++) if (!vis[j - a ]) { tmp[s[i] - a ] = j; vis[j - a ] = 1; flag |= 4; used = 1; break; } if (!used) { if (!vis[b[i] - a ]) vis[b[i] - a ] = 1, tmp[s[i] - a ] = b[i]; else { puts( NO ); return; } } } flag |= 1; if (flag == 7) break; } puts( YES ); int now = 0; while (vis[now]) now++; for (int i = 0; i < k; i++) if (tmp[i] == -1) { tmp[i] = a + now; vis[now] = 1; while (vis[now]) now++; } for (int i = 0; i < k; i++) printf( %c , tmp[i]); puts( ); } int main() { scanf( %d , &T); while (T--) solve(); } |
#include <bits/stdc++.h> using namespace std; unsigned char G[301][301]; unsigned char bv[301]; int ints[301]; int main() { int n; cin >> n; for (register int i = 1; i <= n; i++) cin >> ints[i]; for (register int i = 1; i <= n; i++) { for (register int j = 1; j <= n; j++) { char c; cin >> c; G[i][j] = c - 0 ; } } for (register int k = 1; k <= n; k++) { for (register int i = 1; i <= n; i++) { for (register int j = 1; j <= n; j++) { G[i][j] = G[i][j] || (G[i][k] && G[k][j]); } } } for (register int i = 1; i <= n; i++) { G[i][i] = 1; } ints[0] = 0x7fffffff; for (register int i = 1; i <= n; i++) { int minn = 0; for (register int j = 1; j <= n; j++) { if (ints[j] < ints[minn] && G[i][j] && bv[j] == 0) minn = j; } printf( %d , ints[minn]); bv[minn] = 1; } return (0); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; int a[100005]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (n == 1) { cout << -1 << endl; return 0; } bool flag = true; for (int i = 1; i < n; i++) flag = flag && (a[0] == a[i]); if (flag) { cout << 1 << endl; cout << a[0] << endl; return 0; } if (n == 2) { if ((a[0] + a[1]) % 2 == 0) cout << 3 << endl; else cout << 2 << endl; cout << 2 * a[0] - a[1] << ; if ((a[0] + a[1]) % 2 == 0) cout << (a[1] + a[0]) / 2 << ; cout << 2 * a[1] - a[0] << ; return 0; } flag = true; for (int i = 2; i < n; i++) flag = flag && (a[1] - a[0] == a[i] - a[i - 1]); if (flag) { cout << 2 << endl; cout << 2 * a[0] - a[1] << ; cout << 2 * a[n - 1] - a[n - 2] << endl; return 0; } vector<int> diff; set<int> di; for (int i = 1; i < n; i++) { diff.push_back(a[i] - a[i - 1]); di.insert(a[i] - a[i - 1]); } if (di.size() != 2) { cout << 0 << endl; return 0; } sort(diff.begin(), diff.end()); int chan = diff[n - 2]; if (chan != 2 * diff[0]) { cout << 0 << endl; return 0; } for (int i = n - 3; i >= 0; i--) { if (diff[i] == chan || diff[i] != diff[0]) { cout << 0 << endl; return 0; } } for (int i = 1; i < n; i++) { if (a[i] - a[i - 1] == chan) { if ((a[i] + a[i - 1]) % 2 == 0) { cout << 1 << endl; cout << (a[i] + a[i - 1]) / 2 << endl; return 0; } else { cout << 0 << endl; return 0; } } } return 0; } |
/*
* period_count_tb.v: Test bench for period_count.v
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 100
`endif
`ifndef RESOLUTION
`define RESOLUTION 0.1
`endif
module period_count_tb ();
reg RST;
reg PWRDWN;
reg clk;
wire [31:0] period_length_1000;
reg [31:0] clk_period;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 5;
period_count #(
.RESOLUTION(`RESOLUTION))
dut(
.RST(RST),
.PWRDWN(PWRDWN),
.clk(clk),
.period_length_1000(period_length_1000));
initial begin
$dumpfile("period_count_tb.vcd");
$dumpvars(0, period_count_tb);
RST = 0;
PWRDWN = 0;
clk = 0;
clk_period = 10;
pass_count = 0;
fail_count = 0;
#10;
RST = 1;
#10;
if (period_length_1000 === 0) begin
$display("PASSED: RST");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST");
fail_count = fail_count + 1;
end
RST = 0;
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == clk_period) begin
$display("PASSED: period = 10");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = 10");
fail_count = fail_count + 1;
end
clk_period = 13;
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == clk_period) begin
$display("PASSED: period = 13");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = 13");
fail_count = fail_count + 1;
end
clk_period = 1;
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == clk_period) begin
$display("PASSED: period = 1");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = 1");
fail_count = fail_count + 1;
end
clk_period = (`WAIT_INTERVAL / 2);
#`WAIT_INTERVAL;
if ((period_length_1000 / 1000.0) == `WAIT_INTERVAL / 2) begin
$display("PASSED: period = %0d", (`WAIT_INTERVAL / 2));
pass_count = pass_count + 1;
end else begin
$display("FAILED: period = %0d", (`WAIT_INTERVAL / 2));
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #(clk_period / 2.0) clk <= ~clk;
endmodule
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_descramble
*/
module test_lfsr_descramble_64;
// Parameters
parameter LFSR_WIDTH = 58;
parameter LFSR_POLY = 58'h8000000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 1;
parameter DATA_WIDTH = 64;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg data_in_valid = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
data_in_valid
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_descramble_64.lxt");
$dumpvars(0, test_lfsr_descramble_64);
end
lfsr_descramble #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_out(data_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, *a, q, sum = 0; cin >> n; a = new long long int[n]; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } sort(a, a + n); cin >> m; for (int i = 0; i < m; i++) { cin >> q; cout << sum - a[n - q] << n ; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire input_signal = crc[0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire output_signal; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.output_signal (output_signal),
// Inputs
.input_signal (input_signal));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, output_signal};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h765b2e12b25ec97b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input input_signal,
output output_signal
);
// bug872
// verilator lint_off UNOPTFLAT
wire some_signal[1:0][1:0];
assign some_signal[0][0] = input_signal;
assign some_signal[0][1] = some_signal[0][0];
assign some_signal[1][0] = some_signal[0][1];
assign some_signal[1][1] = some_signal[1][0];
assign output_signal = some_signal[1][1];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); long long int n, s, p, q; char d; map<long long int, long long int> p1, p2; cin >> n >> s; for (long long int i = 1; i <= n; i++) { cin >> d >> p >> q; if (d == B ) p1[p] += q; else if (d == S ) p2[p] += q; } map<long long int, long long int>::reverse_iterator rit; map<long long int, long long int>::iterator it; vector<pair<long long int, long long int> > p3; long long int cnt = 0; for (it = p2.begin(); it != p2.end(); it++) { if (cnt < s) { p3.push_back(make_pair(it->first, it->second)); cnt++; } } cnt = 0; reverse(p3.begin(), p3.end()); vector<pair<long long int, long long int> >::iterator it2; for (it2 = p3.begin(); it2 != p3.end(); ++it2) { if (cnt < s) { cout << S << << it2->first << << it2->second << endl; cnt++; } } cnt = 0; for (rit = p1.rbegin(); rit != p1.rend(); ++rit) { if (cnt < s) { cout << B << << rit->first << << rit->second << endl; cnt++; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_TB_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_TB_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb16to1.v"
module top();
// Inputs are registered
reg D;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 S = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 S = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 S = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 S = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_hdll__muxb16to1 dut (.D(D), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 105; int Q[N], S[N], ok[N + N], Sav[N], mat[N + N][N]; int dp[N + N][N]; int solve(int p, int k) { if (ok[p]) return k == 0; if (!k) return 0; if (dp[p][k] != -1) return dp[p][k]; return dp[p][k] = solve(p - 1, k - 1) | solve(p + 1, k - 1); } int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> Q[i], Sav[Q[i]] = i, mat[100][i] = i; for (int i = 1; i <= n; i++) cin >> S[i]; for (int i = 99; i >= 0; i--) for (int j = 1; j <= n; j++) mat[i][j] = mat[i + 1][Sav[j]]; for (int i = 101; i <= 200; i++) for (int j = 1; j <= n; j++) mat[i][j] = mat[i - 1][Q[j]]; for (int i = 0; i <= 200; i++) { ok[i] = 1; for (int j = 1; j <= n; j++) ok[i] &= mat[i][j] == S[j]; } memset(dp, -1, sizeof(dp)); puts(solve(100, k) ? YES : NO ); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_TO_CTRL.v
// Version : 2.3
//--
//-- Description: Turn-off Control Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff,
cfg_turnoff_ok
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff;
output cfg_turnoff_ok;
reg trn_pending;
reg cfg_turnoff_ok;
// * Check if completion is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i)
trn_pending <= 1'b1;
else if (compl_done_i)
trn_pending <= 1'b0;
end
end
// * Turn-off OK if requested and no transaction is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
cfg_turnoff_ok <= 1'b0;
end else begin
if ( cfg_to_turnoff && !trn_pending)
cfg_turnoff_ok <= 1'b1;
else
cfg_turnoff_ok <= 1'b0;
end
end
endmodule // PIO_TO_CTRL
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:14:01 03/09/2017
// Design Name:
// Module Name: SimpleAI_TB
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LookupAI_TB;
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
// do stuff
X_state = 9'b000000000;
O_state = 9'b000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b100000000;
O_state = 9'b000100000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b101000000;
O_state = 9';
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b111000000;
O_state = 9';
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
LookupTableAI lai (
X_state,
O_state,
AI_move
);
endmodule
|
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