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`timescale 1ns / 1ps
module debouncer(
input clk, input reset,
input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
// from which we make three outputs, all synchronous to the clock
output reg PB_state, // 1 as long as the push-button is active (down)
output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0; always @(posedge clk) PB_sync_0 <= PB; // invert (~PB) if you want to PB to make PB_sync_0 active high
reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0;
// Next declare a 16-bits counter
reg [7:0] PB_cnt;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk, posedge reset)
if(reset)begin
PB_cnt <= 0;
PB_state <= 0;
end else
if(PB_idle)
PB_cnt <= 0; // nothing's going on
else
begin
PB_cnt <= PB_cnt + 1'b1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
assign PB_up = ~PB_idle & PB_cnt_max & PB_state;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; long long n, m, w, ai; long long cnt[300005]; bool go(long long mx) { memset(cnt, 0, sizeof cnt); long long use = m; long long add = 0; for (int i = 0; i < n; i++) { add += cnt[i]; long long curr = v[i] + add; if (curr >= mx) continue; if (mx - curr > use) return 0; add += (mx - curr); cnt[i + w] -= (mx - curr); use -= (mx - curr); } return 1; } int main() { cin >> n >> m >> w; for (int i = 0; i < n; i++) { cin >> ai; v.push_back(ai); } long long l = 1, r = 10000000000ll, bst = -1; while (l <= r) { long long mid = (l + r) / 2ll; if (go(mid)) { bst = mid; l = mid + 1; } else r = mid - 1; } cout << bst; } |
`include "defines.v"
/**
* crossbar.v
*
* @author Kevin Woo <>
*
* @brief Creates a 5x5 crossbar. Takes in two parts of data, a control line
* and a data line for each input/output. Connects each one based on
* the route_config input, a bus of 5 x 3bit control signals to select
* which input is connected to which output. Inputs are switched and
* latched on the positive edge of the clock cycle.
*
* route_config layout
* [Input 4], [Input 3], [Input 2], [Input 1], [Input 0]
**/
module crossbar (
input `control_w control0_in,
input `control_w control1_in,
input `control_w control2_in,
input `control_w control3_in,
input `control_w control4_in,
input `data_w data0_in,
input `data_w data1_in,
input `data_w data2_in,
input `data_w data3_in,
input `data_w data4_in,
input `routecfg_w route_config,
input clk,
input rst,
output reg `control_w control0_out,
output reg `control_w control1_out,
output reg `control_w control2_out,
output reg `control_w control3_out,
output reg `control_w control4_out,
output reg `data_w data0_out,
output reg `data_w data1_out,
output reg `data_w data2_out,
output reg `data_w data3_out,
output reg `data_w data4_out);
// Switches
wire [`routecfg_bn-1:0] switch0;
wire [`routecfg_bn-1:0] switch1;
wire [`routecfg_bn-1:0] switch2;
wire [`routecfg_bn-1:0] switch3;
wire [`routecfg_bn-1:0] switch4;
// Parse route_config into the switch logic
assign switch0 = route_config[`routecfg_0];
assign switch1 = route_config[`routecfg_1];
assign switch2 = route_config[`routecfg_2];
assign switch3 = route_config[`routecfg_3];
assign switch4 = route_config[`routecfg_4];
always @(posedge clk) begin
// North = Port 0
// South = Port 1
// East = Port 2
// West = Port 3
if (rst) begin
control0_out <= 0;
data0_out <= 0;
control1_out <= 0;
data1_out <= 0;
control2_out <= 0;
data2_out <= 0;
control3_out <= 0;
data3_out <= 0;
control4_out <= 0;
data4_out <= 0;
end else begin
$display("xbar: route_config = %x, c0 = %x, c1 = %x, c2 = %x, c3 = %x, d0 = %032x, d1 = %032x, d2 = %032x, d3 = %032x",
route_config, control0_in, control1_in, control2_in, control3_in, data0_in, data1_in, data2_in, data3_in);
// Output 0
case (switch0)
3'b000:
begin
control0_out <= control0_in;
data0_out <= data0_in;
end
3'b001:
begin
control0_out <= control1_in;
data0_out <= data1_in;
end
3'b010:
begin
control0_out <= control2_in;
data0_out <= data2_in;
end
3'b011:
begin
control0_out <= control3_in;
data0_out <= data3_in;
end
3'b100:
begin
control0_out <= control4_in;
data0_out <= data4_in;
end
3'b111:
begin
control0_out <= `control_n'd0;
data0_out <= `data_n'd0;
end
endcase
// Output 1
case (switch1)
3'b000:
begin
control1_out <= control0_in;
data1_out <= data0_in;
end
3'b001:
begin
control1_out <= control1_in;
data1_out <= data1_in;
end
3'b010:
begin
control1_out <= control2_in;
data1_out <= data2_in;
end
3'b011:
begin
control1_out <= control3_in;
data1_out <= data3_in;
end
3'b100:
begin
control1_out <= control4_in;
data1_out <= data4_in;
end
3'b111:
begin
control1_out <= `control_n'd0;
data1_out <= `data_n'd0;
end
endcase
// Output 2
case (switch2)
3'b000:
begin
control2_out <= control0_in;
data2_out <= data0_in;
end
3'b001:
begin
control2_out <= control1_in;
data2_out <= data1_in;
end
3'b010:
begin
control2_out <= control2_in;
data2_out <= data2_in;
end
3'b011:
begin
control2_out <= control3_in;
data2_out <= data3_in;
end
3'b100:
begin
control2_out <= control4_in;
data2_out <= data4_in;
end
3'b111:
begin
control2_out <= `control_n'd0;
data2_out <= `data_n'd0;
end
endcase
// Output 3
case (switch3)
3'b000:
begin
control3_out <= control0_in;
data3_out <= data0_in;
end
3'b001:
begin
control3_out <= control1_in;
data3_out <= data1_in;
end
3'b010:
begin
control3_out <= control2_in;
data3_out <= data2_in;
end
3'b011:
begin
control3_out <= control3_in;
data3_out <= data3_in;
end
3'b100:
begin
control3_out <= control4_in;
data3_out <= data4_in;
end
3'b111:
begin
control3_out <= `control_n'd0;
data3_out <= `data_n'd0;
end
endcase
// Output4
case (switch4)
3'b000:
begin
control4_out <= control0_in;
data4_out <= data0_in;
end
3'b001:
begin
control4_out <= control1_in;
data4_out <= data1_in;
end
3'b010:
begin
control4_out <= control2_in;
data4_out <= data2_in;
end
3'b011:
begin
control4_out <= control3_in;
data4_out <= data3_in;
end
3'b100:
begin
control4_out <= control4_in;
data4_out <= data4_in;
end
3'b111:
begin
control4_out <= `control_n'd0;
data4_out <= `data_n'd0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string ch1, ch2, ch3; getline(cin, ch1); getline(cin, ch2); for (int s = 0; s < ch1.size(); s++) { if (ch1[s] != ch2[s]) { ch3 += 1 ; } else { ch3 += 0 ; } } cout << ch3 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } template <class T> inline T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } template <class T> inline T sqr(T x) { return x * x; } template <class T> T power(T N, T P) { return (P == 0) ? 1 : N * power(N, P - 1); } template <class T> bool inside(T a, T b, T c) { return (b >= a && b <= c); } const long long INF64 = (long long)1E16; int distsq2d(int x1, int y1, int x2, int y2) { return sqr(x1 - x2) + sqr(y1 - y2); } double dist2d(double x1, double y1, double x2, double y2) { return sqrt(sqr(x1 - x2) + sqr(y1 - y2)); } double dist3d(double x1, double y1, double z1, double x2, double y2, double z2) { return sqrt(sqr(x1 - x2) + sqr(y1 - y2) + sqr(z1 - z2)); } long long toInt64(string s) { long long r = 0; istringstream sin(s); sin >> r; return r; } double LOG(long long N, long long B) { return (log10l(N)) / (log10l(B)); } string itoa(long long a) { if (a == 0) return 0 ; string ret; for (long long i = a; i > 0; i = i / 10) ret.push_back((i % 10) + 48); reverse(ret.begin(), ret.end()); return ret; } vector<string> token(string a, string b) { const char *q = a.c_str(); while (count(b.begin(), b.end(), *q)) q++; vector<string> oot; while (*q) { const char *e = q; while (*e && !count(b.begin(), b.end(), *e)) e++; oot.push_back(string(q, e)); q = e; while (count(b.begin(), b.end(), *q)) q++; } return oot; } int isvowel(char s) { s = tolower(s); if (s == a || s == e || s == i || s == o || s == u ) return 1; return 0; } int isupper(char s) { if (s >= A and s <= Z ) return 1; return 0; } int Set(int N, int pos) { return N = N | (1 << pos); } int reset(int N, int pos) { return N = N & ~(1 << pos); } int check(int N, int pos) { return (N & (1 << pos)); } int toggle(int N, int pos) { if (check(N, pos)) return N = reset(N, pos); return N = Set(N, pos); } void pbit(int N) { printf( ( ); for (int i = 10; i >= 0; i--) { bool x = check(N, i); cout << x; } puts( ) ); } char ts[200]; int n, m; int a[14][104]; int b[14][104]; int c[14][104]; int dp[14][14][104][104]; int call(int p1, int p2, int idx, int left) { if (idx == m) return 0; if (dp[p1][p2][idx][left] != -1) { return dp[p1][p2][idx][left]; } int mxx = 0; for (int i = 1; i <= left and i <= c[p1][idx]; i++) { int bcost = a[p1][idx] * i; int scost = b[p2][idx] * i; int ret = (scost - bcost) + call(p1, p2, idx + 1, left - i); mxx = max(ret, mxx); } int ret = call(p1, p2, idx + 1, left); mxx = max(ret, mxx); return dp[p1][p2][idx][left] = mxx; } int main() { memset(dp, -1, sizeof(dp)); ; int k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { scanf( %s , ts); for (int j = 0; j < m; j++) { scanf( %d%d%d , &a[i][j], &b[i][j], &c[i][j]); } } int best = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; int ret = call(i, j, 0, k); best = max(ret, best); } } cout << best << endl; } |
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_multiplier
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input hold_i
// Outputs
,output [ 31:0] writeback_value_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
localparam MULT_STAGES = 2; // 2 or 3
//-------------------------------------------------------------
// Registers / Wires
//-------------------------------------------------------------
reg [31:0] result_e2_q;
reg [31:0] result_e3_q;
reg [32:0] operand_a_e1_q;
reg [32:0] operand_b_e1_q;
reg mulhi_sel_e1_q;
//-------------------------------------------------------------
// Multiplier
//-------------------------------------------------------------
wire [64:0] mult_result_w;
reg [32:0] operand_b_r;
reg [32:0] operand_a_r;
reg [31:0] result_r;
wire mult_inst_w = ((opcode_opcode_i & `INST_MUL_MASK) == `INST_MUL) ||
((opcode_opcode_i & `INST_MULH_MASK) == `INST_MULH) ||
((opcode_opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU) ||
((opcode_opcode_i & `INST_MULHU_MASK) == `INST_MULHU);
always @ *
begin
if ((opcode_opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else if ((opcode_opcode_i & `INST_MULH_MASK) == `INST_MULH)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else // MULHU || MUL
operand_a_r = {1'b0, opcode_ra_operand_i[31:0]};
end
always @ *
begin
if ((opcode_opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU)
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
else if ((opcode_opcode_i & `INST_MULH_MASK) == `INST_MULH)
operand_b_r = {opcode_rb_operand_i[31], opcode_rb_operand_i[31:0]};
else // MULHU || MUL
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
end
// Pipeline flops for multiplier
always @(posedge clk_i or posedge rst_i)
if (rst_i)
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
else if (hold_i)
;
else if (opcode_valid_i && mult_inst_w)
begin
operand_a_e1_q <= operand_a_r;
operand_b_e1_q <= operand_b_r;
mulhi_sel_e1_q <= ~((opcode_opcode_i & `INST_MUL_MASK) == `INST_MUL);
end
else
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
assign mult_result_w = {{ 32 {operand_a_e1_q[32]}}, operand_a_e1_q}*{{ 32 {operand_b_e1_q[32]}}, operand_b_e1_q};
always @ *
begin
result_r = mulhi_sel_e1_q ? mult_result_w[63:32] : mult_result_w[31:0];
end
always @(posedge clk_i or posedge rst_i)
if (rst_i)
result_e2_q <= 32'b0;
else if (~hold_i)
result_e2_q <= result_r;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
result_e3_q <= 32'b0;
else if (~hold_i)
result_e3_q <= result_e2_q;
assign writeback_value_o = (MULT_STAGES == 3) ? result_e3_q : result_e2_q;
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/rp2a03.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Implementation of the RP2A03 chip for an fpga-based NES emulator. Contains a MOS-6502 CPU
* core, APU, sprite DMA engine, and joypad control logic.
***************************************************************************************************/
module rp2a03
(
input clk_in, // system clock
input rst_in, // system reset
// CPU signals.
input rdy_in, // ready signal
input [ 7:0] d_in, // data input bus
input nnmi_in, // /nmi interrupt signal (active low)
input nres_in, // /res interrupt signal (active low)
output [ 7:0] d_out, // data output bus
output [15:0] a_out, // address bus
output r_nw_out, // read/write select (write low)
output brk_out, // debug break signal
// Joypad signals.
input [7:0] i_jp1_state, //State of joypad 1
input [7:0] i_jp2_state, //State of joypad 2
// Audio signals.
input [ 3:0] mute_in, // disable autio channels
output audio_out, // pwm audio output
// HCI interface.
input [ 3:0] dbgreg_sel_in, // dbg reg select
input [ 7:0] dbgreg_d_in, // dbg reg data in
input dbgreg_wr_in, // dbg reg write select
output [ 7:0] dbgreg_d_out // dbg reg data out
);
//
// CPU: central processing unit block.
//
wire cpu_ready;
wire [ 7:0] cpu_din;
wire cpu_nirq;
wire [ 7:0] cpu_dout;
wire [15:0] cpu_a;
wire cpu_r_nw;
cpu cpu_blk(
.clk_in (clk_in ),
.rst_in (rst_in ),
.nres_in (nres_in ),
.nnmi_in (nnmi_in ),
.nirq_in (cpu_nirq ),
.ready_in (cpu_ready ),
.brk_out (brk_out ),
.d_in (cpu_din ),
.d_out (cpu_dout ),
.a_out (cpu_a ),
.r_nw_out (cpu_r_nw ),
.dbgreg_wr_in (dbgreg_wr_in ),
.dbgreg_in (dbgreg_d_in ),
.dbgreg_sel_in (dbgreg_sel_in ),
.dbgreg_out (dbgreg_d_out )
);
//
// APU: audio processing unit block.
//
wire [7:0] audio_dout;
apu apu_blk(
.clk_in (clk_in ),
.rst_in (rst_in ),
.mute_in (mute_in ),
.a_in (cpu_a ),
.d_in (cpu_dout ),
.r_nw_in (cpu_r_nw ),
.audio_out (audio_out ),
.d_out (audio_dout )
);
//
// JP: joypad controller block.
//
wire [7:0] jp_dout;
jp jp_blk(
.clk (clk_in ),
.rst (rst_in ),
.i_wr (~cpu_r_nw ),
.i_addr (cpu_a ),
.i_din (cpu_dout[0] ),
.o_dout (jp_dout ),
.i_jp1_state (i_jp1_state ),
.i_jp2_state (i_jp2_state )
);
/*
jp jp_blk(
.clk (clk_in ),
.rst (rst_in ),
.wr (~cpu_r_nw ),
.addr (cpu_a ),
.din (cpu_dout[0] ),
.dout (jp_dout ),
.jp_clk (jp_clk ),
.jp_latch (jp_latch ),
.jp_data1 (jp_data1_in ),
.jp_data2 (jp_data2_in )
);
*/
//
// SPRDMA: sprite dma controller block.
//
wire sprdma_active;
wire [15:0] sprdma_a;
wire [ 7:0] sprdma_dout;
wire sprdma_r_nw;
sprdma sprdma_blk(
.clk_in (clk_in ),
.rst_in (rst_in ),
.cpumc_a_in (cpu_a ),
.cpumc_din_in (cpu_dout ),
.cpumc_dout_in (cpu_din ),
.cpu_r_nw_in (cpu_r_nw ),
.active_out (sprdma_active ),
.cpumc_a_out (sprdma_a ),
.cpumc_d_out (sprdma_dout ),
.cpumc_r_nw_out (sprdma_r_nw )
);
assign cpu_ready = rdy_in & !sprdma_active;
assign cpu_din = d_in | jp_dout | audio_dout;
assign cpu_nirq = 1'b1;
assign d_out = (sprdma_active) ? sprdma_dout : cpu_dout;
assign a_out = (sprdma_active) ? sprdma_a : cpu_a;
assign r_nw_out = (sprdma_active) ? sprdma_r_nw : cpu_r_nw;
endmodule
|
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; using ll = long long; pii operator+(pii& p1, pii& p2) { return {p1.first + p2.first, p1.second + p2.second}; } bool isvalidpos(pii& p, int n) { return p.first >= 0 && p.first < n && p.second >= 0 && p.second < n; } int main() { int n; cin >> n; vector<vector<int>> v1(n, vector<int>(n, -1)); vector<vector<int>> v2(n, vector<int>(n, -1)); v1[0][0] = 1; v1[n - 1][n - 1] = 0; v2[0][0] = 1; v2[n - 1][n - 1] = 0; queue<pii> q; q.push({0, 0}); pii dyx[] = {{2, 0}, {0, 2}, {1, 1}}; while (!q.empty()) { pii now = q.front(); q.pop(); for (int i = 0; i < 3; i++) { pii nxt = now + dyx[i]; if (!isvalidpos(nxt, n)) continue; if (v1[nxt.first][nxt.second] != -1) continue; cout << ? << now.first + 1 << << now.second + 1 << << nxt.first + 1 << << nxt.second + 1 << endl; cout.flush(); int res; cin >> res; if (res == 1) v2[nxt.first][nxt.second] = v1[nxt.first][nxt.second] = v1[now.first][now.second]; else v2[nxt.first][nxt.second] = v1[nxt.first][nxt.second] = 1 - v1[now.first][now.second]; q.push(nxt); } } v1[0][1] = 0; v2[0][1] = 1; q.push({0, 1}); while (!q.empty()) { pii now = q.front(); q.pop(); for (int i = 0; i < 3; i++) { pii nxt = now + dyx[i]; if (!isvalidpos(nxt, n)) continue; if (v1[nxt.first][nxt.second] != -1) continue; cout << ? << now.first + 1 << << now.second + 1 << << nxt.first + 1 << << nxt.second + 1 << endl; cout.flush(); int res; cin >> res; if (res == 1) { v2[nxt.first][nxt.second] = v2[now.first][now.second]; v1[nxt.first][nxt.second] = v1[now.first][now.second]; } else { v2[nxt.first][nxt.second] = 1 - v2[now.first][now.second]; v1[nxt.first][nxt.second] = 1 - v1[now.first][now.second]; } q.push(nxt); } } for (int i = 1; i < n; i += 2) { cout << ? << i + 1 << << 1 << << i + 2 << << 2 << endl; cout.flush(); int res; cin >> res; if (res == 1) { v2[i][0] = v2[i + 1][1]; v1[i][0] = v1[i + 1][1]; } else { v2[i][0] = 1 - v2[i + 1][1]; v1[i][0] = 1 - v1[i + 1][1]; } } bool answer = false; pii dyx2[][4] = {{{0, 0}, {0, 1}, {0, 2}, {1, 2}}, {{0, 0}, {0, 1}, {1, 1}, {1, 2}}, {{0, 0}, {1, 0}, {1, 1}, {1, 2}}}; bool end = false; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { bool palin1 = false; bool palin2 = false; pii now = {i, j}; for (int k1 = 0; k1 < 3; k1++) { bool check = true; for (int k2 = 0; k2 < 4; k2++) { pii nxt = now + dyx2[k1][k2]; if (!isvalidpos(nxt, n)) { check = false; break; } } if (!check) continue; if (v1[now.first + dyx2[k1][0].first] [now.second + dyx2[k1][0].second] == v1[now.first + dyx2[k1][3].first] [now.second + dyx2[k1][3].second] && v1[now.first + dyx2[k1][1].first] [now.second + dyx2[k1][1].second] == v1[now.first + dyx2[k1][2].first] [now.second + dyx2[k1][2].second]) palin1 = true; if (v2[now.first + dyx2[k1][0].first] [now.second + dyx2[k1][0].second] == v2[now.first + dyx2[k1][3].first] [now.second + dyx2[k1][3].second] && v2[now.first + dyx2[k1][1].first] [now.second + dyx2[k1][1].second] == v2[now.first + dyx2[k1][2].first] [now.second + dyx2[k1][2].second]) palin2 = true; } if (palin1 || palin2) { cout << ? << now.first + 1 << << now.second + 1 << << now.first + 2 << << now.second + 3 << endl; cout.flush(); int res; cin >> res; if (res == 1) { if (palin1) answer = true; else answer = false; } else { if (palin1) answer = false; else answer = true; } end = true; break; } } if (end) break; } cout << ! << endl; cout.flush(); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (answer) cout << v1[i][j]; else cout << v2[i][j]; } cout << endl; cout.flush(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long nch(long long n) { long long ans = 0, tmp = 1, k = 1; while (n) { ans += min(n, tmp * 9) * k; n -= min(n, tmp * 9); tmp *= 10; k++; } return ans; } char get(long long n, long long d) { string s; stringstream ss; ss << n; ss >> s; return s[d - 1]; } char kth(long long n) { long long s = 0, nine = 9, d = 0, len; for (len = 1;; len++) { s += nine * len; d += nine; if (s >= n) { s -= nine * len; d -= nine; n -= s; break; } nine *= 10; } long long diff = ceil((double)n / len); long long dd = n % len; if (dd == 0) dd = len; return get(d + diff, dd); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long q; cin >> q; while (q--) { long long k, n = 1; cin >> k; for (n = 1; nch(n) < k; n++) k -= nch(n); cout << kth(k) << endl; } return 0; } |
module simple_fifo # (
parameter DEPTH_WIDTH = 1,
parameter DATA_WIDTH = 1,
parameter ALMOST_FULL_TH = 1,
parameter ALMOST_EMPTY_TH = 1
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] wr_data,
input wire wr_en,
output wire [DATA_WIDTH-1:0] rd_data,
input wire rd_en,
output wire full,
output wire empty,
output wire almost_full,
output wire almost_empty
);
//synthesis translate_off
initial begin
if (DEPTH_WIDTH < 1) $display("%m : Warning: DEPTH_WIDTH must be > 0. Setting minimum value (1)");
if (DATA_WIDTH < 1) $display("%m : Warning: DATA_WIDTH must be > 0. Setting minimum value (1)");
end
//synthesis translate_on
localparam integer DW = (DATA_WIDTH < 1) ? 1 : DATA_WIDTH;
localparam integer AW = (DEPTH_WIDTH < 1) ? 1 : DEPTH_WIDTH;
localparam integer FULLCNT = {1'b1, {(DEPTH_WIDTH){1'b0}}};
reg [AW :0] cnt;
reg [AW-1:0] write_p;
reg [AW-1:0] read_p;
wire we, re;
assign we = (wr_en & ~full);
assign re = (rd_en & ~empty);
always @ (posedge clk) begin
if (rst)
write_p <= 0;
else if (we)
write_p <= write_p + 1;
end
always @ (posedge clk) begin
if (rst)
read_p <= 0;
else if (re)
read_p <= read_p + 1;
end
always @ (posedge clk) begin
if (rst)
cnt <= 0;
else begin
case ({we, re})
2'b10: cnt <= cnt + 1;
2'b01: cnt <= cnt - 1;
default: cnt <= cnt;
endcase
end
end
/// empty
reg r_empty;
assign empty = r_empty;
always @ (posedge clk) begin
if (rst)
r_empty <= 1;
else begin
case ({we, re})
2'b10: r_empty <= 0;
2'b01: r_empty <= (cnt == 1);
default: r_empty <= r_empty;
endcase
end
end
/// full
assign full = (cnt[AW]);
/// almost_empty
reg r_almost_empty;
assign almost_empty = r_almost_empty;
always @ (posedge clk) begin
if (rst)
r_almost_empty <= 1'b1;
else begin
case ({we, re})
2'b10: if (cnt == ALMOST_EMPTY_TH) r_almost_empty <= 0;
2'b01: if (cnt == (ALMOST_EMPTY_TH + 1)) r_almost_empty <= 1;
default: r_almost_empty <= r_almost_empty;
endcase
end
end
/// almost_full
reg r_almost_full;
assign almost_full = r_almost_full;
always @ (posedge clk) begin
if (rst)
r_almost_full <= (DEPTH_WIDTH == 0);
else begin
case ({we, re})
2'b10: if (cnt == (FULLCNT - ALMOST_FULL_TH - 1)) r_almost_full <= 1;
2'b01: if (cnt == (FULLCNT - ALMOST_FULL_TH)) r_almost_full <= 0;
default: r_almost_full <= r_almost_full;
endcase
end
end
simple_dpram_sclk # (
.ADDR_WIDTH(AW),
.DATA_WIDTH(DW),
.ENABLE_BYPASS(1)
) fifo_ram (
.clk (clk),
.dout (rd_data),
.raddr (read_p[AW-1:0]),
.re (re),
.waddr (write_p[AW-1:0]),
.we (we),
.din (wr_data)
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : test_00.v
// Description : Simple ADXL362 Test Case to bring environment to life
// Author : Philip Tracton
// Created On : Thu Jun 23 11:36:12 2016
// Last Modified By: Philip Tracton
// Last Modified On: Thu Jun 23 11:36:12 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "timescale.v"
`include "simulation_includes.vh"
module test_case ();
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "uart_interrupt";
parameter number_of_tests = 5;
`include "setup.v"
reg err;
reg [31:0] data_out;
integer i;
initial begin
$display("Boot Case");
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
`UART_CONFIG;
// #150000;
// `TEST_COMPLETE;
@(posedge `TRIGGER[0]);
`TEST_COMPARE("TRIGGER HIGH", 1, `TRIGGER[0]);
`UART_WRITE_CHAR("A");
`UART_READ_CHAR("A");
`UART_WRITE_CHAR("B");
`UART_READ_CHAR("B");
`UART_WRITE_CHAR("C");
`UART_READ_CHAR("C");
#10000;
`TEST_COMPLETE;
end
endmodule // test_case
|
#include <bits/stdc++.h> using namespace std; const int MAX_MEM = (int)1e8; int mpos = 0; char mem[MAX_MEM]; inline void *operator new(size_t n) { char *res = mem + mpos; mpos += n; return (void *)res; } inline void operator delete(void *) {} struct __io_dev { __io_dev(const bool &__fastio = false) { if (__fastio) ios_base::sync_with_stdio(false), cin.tie(nullptr); srand(time(nullptr)); if (!string( ).empty()) freopen( .in , r , stdin), freopen( .out , w , stdout); } ~__io_dev() { fprintf(stderr, %.6f ms n , 1e3 * clock() / CLOCKS_PER_SEC); } } __io(false); const long long inf = (long long)1e+9 + 7ll; const long long linf = (long long)1e+18 + 7ll; const long double eps = (long double)1e-9; const long double pi = acosl((long double)-1.0); const int alph = 26; const int maxs = 512l; static char buff[(int)2e6 + 17]; long long __p[3] = {29ll, 31ll, 33ll}; long long __mod[3] = {inf, inf + 2ll, 14881337ll}; const int maxn = (int)2e5 + 17; int n; string s; long long R, K; void print(int R, int K) { string r; int cnt = 0; for (; R > 0; R /= 10) { r.push_back(char( 0 + R % 10)); ++cnt; if (cnt % 3 == 0) r.push_back( . ); } if (r.back() == . ) r.pop_back(); if (((int)(r.size())) == 0) r.push_back( 0 ); reverse(r.begin(), r.end()); printf( %s , r.c_str()); if (K != 0) printf( .%.2d , K); } int main() { scanf( %s , buff); s = string(buff); n = ((int)(s.size())); for (int i = 0; i < n; ++i) if (!( a <= s[i] && s[i] <= z )) { int r = i; string t = ; for (; r < n && !( a <= s[r] && s[r] <= z ); ++r) t += s[r]; if (((int)(t.size())) >= 3 && t[((int)(t.size())) - 3] == . ) { K += 10 * (t[((int)(t.size())) - 2] - 0 ) + t[((int)(t.size())) - 1] - 0 ; int cursize = ((int)(t.size())); t.resize(cursize - 3); } long long cur = 0; for (auto c : t) if ( 0 <= c && c <= 9 ) cur = cur * 10ll + c - 0 ; R += cur; i = r - 1; } R += K / 100; K %= 100; print(R, K); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( Ofast ) using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; long double u; cin >> n >> u; vector<long double> e(n); for (int i = 0; i < n; i++) cin >> e[i]; long double ans = 0; bool fl = 0; for (int i = 2; i < n; i++) { if (e[i] - e[i - 2] <= u) fl = 1; } if (!fl) { cout << -1 << endl; return 0; } for (int i = 0; i < n; i++) { int tmp = upper_bound(e.begin(), e.end(), e[i] + u) - e.begin() - 1; if (tmp - i < 2) continue; ans = max(ans, (e[tmp] - e[i + 1]) / (e[tmp] - e[i])); } cout << fixed << setprecision(13) << ans << endl; } |
//==============================================================================
// File: $URL$
// Version: $Revision$
// Author: Jose Renau (http://masc.cse.ucsc.edu/)
// Elnaz Ebrahimi
// Copyright: Copyright 2011 UC Santa Cruz
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2011, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Santa Cruz nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
/****************************************************************************
Description:
****************************************************************************/
`define FLOP_RETRY_USE_FLOPS 1
`define USE_SELF_W2R1 1
module fflop
#(parameter Size=1)
(input clk
,input reset
,input logic [Size-1:0] din
,input logic dinValid
,output logic dinRetry
,output logic [Size-1:0] q
,input logic qRetry
,output logic qValid
);
`ifdef USE_SELF_W2R1
// uses W2R1 implementation from
// http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.99.9778&rep=rep1&type=pdf
// {{{1 SELF IMPLEMENTATION
logic [Size-1:0] shadowq;
logic c1;
logic c2;
logic shadowValid;
logic priv_qValid;
always_comb begin
qValid = priv_qValid;
end
logic priv_dinRetry;
always_comb begin
dinRetry = priv_dinRetry;
end
// Inputs private signals
logic priv_qRetry;
always_comb begin
priv_qRetry = qRetry;
end
logic priv_dinValid;
always_comb begin
priv_dinValid = dinValid;
end
// 1}}}
// {{{1 cond1 and cond2
always_comb begin
c1 = (priv_qValid & priv_qRetry); // resend (even with failure, we can have a resend)
c2 = priv_dinValid | shadowValid; // pending
end
// 1}}}
// {{{1 shadowValid
always @(posedge clk) begin
if (reset) begin
shadowValid <= 'b0;
end else begin
shadowValid <= (c1 & c2);
end
end
// 1}}}
// {{{1 shadowq
logic s_enable;
always_comb begin
s_enable = !shadowValid;
end
always@ (posedge clk) begin
if (s_enable) begin
shadowq <= din;
end
end
// 1}}}
// {{{1 q
always @(posedge clk) begin
if (c1) begin
q <= q;
end else if (s_enable) begin
q <= din;
end else begin
q <= shadowq;
end
end
// 1}}}
// {{{1 priv_qValid (qValid internal value)
logic priv_qValidla2;
always @(posedge clk) begin
if (reset) begin
priv_qValidla2 <='b0;
end else begin
priv_qValidla2 <= (c1 | c2);
end
end
always_comb begin
priv_qValid = priv_qValidla2;
end
// 1}}}
// {{{1 priv_dinRetry (dinRetry internal value)
always_comb begin
priv_dinRetry = shadowValid | reset;
end
// 1}}}
// 1}}}
`else
// {{{1 Private variable priv_*i, failure, and shadowq declaration
// Output private signals
logic [Size-1:0] shadowq;
logic c1;
logic c2;
logic shadowValid;
logic priv_qValid;
always @(*) begin
qValid = priv_qValid;
end
logic priv_dinRetry;
always @(*) begin
dinRetry = priv_dinRetry;
end
// Inputs private signals
logic priv_qRetry;
always @(*) begin
priv_qRetry = qRetry;
end
logic priv_dinValid;
always @(*) begin
priv_dinValid = dinValid;
end
// 1}}}
// {{{1 cond1 and cond2
always @(*) begin
c1 = (priv_qValid & priv_qRetry); // resend (even with failure, we can have a resend)
c2 = priv_dinValid | shadowValid; // pending
end
// 1}}}
// {{{1 shadowValid
`ifdef FLOP_RETRY_USE_FLOPS
always @(posedge clk) begin
if (reset) begin
shadowValid <= 'b0;
end else begin
shadowValid <= (c1 & c2);
end
end
`else
logic shadowValid_nclk;
always_latch begin
if (~clk) begin
if (reset) begin
shadowValid_nclk<= 'b0;
end else begin
shadowValid_nclk<= (c1 & c2);
end
end
end
always_latch begin
if (clk) begin
shadowValid <= shadowValid_nclk;
end
end
`endif
// 1}}}
// {{{1 shadowq
logic s_enable;
always @(*) begin
s_enable = !shadowValid;
end
always@ (posedge clk) begin
if (s_enable) begin
shadowq <= din;
end
end
// 1}}}
// {{{1 q
logic q_enable;
`ifdef FLOP_RETRY_USE_FLOPS
always @(negedge clk) begin
q_enable <= !c1;
end
`else
always @(*) begin
if (!clk) begin
q_enable <= !c1;
end
end
`endif
always @ (negedge clk) begin
if (q_enable) begin
q <= shadowq;
end
end
// 1}}}
// {{{1 priv_qValid (qValid internal value)
logic priv_qValidla2;
`ifdef FLOP_RETRY_USE_FLOPS
always @(posedge clk) begin
if (reset) begin
priv_qValidla2 <='b0;
end else begin
priv_qValidla2 <= (c1 | c2);
end
end
`else
logic priv_qValidla;
always_latch begin
if (~clk) begin
if (reset) begin
priv_qValidla <= 'b0;
end else begin
priv_qValidla <= (c1 | c2);
end
end
end
always_latch begin
if (clk) begin
priv_qValidla2 <= priv_qValidla;
end
end
`endif
always @(*) begin
priv_qValid = priv_qValidla2;
end
// 1}}}
// {{{1 priv_dinRetry (dinRetry internal value)
always @(*) begin
priv_dinRetry = shadowValid | reset;
end
// 1}}}
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d%d , &n, &k); vector<char> s(n + 1), t(n + 1); scanf( %s , &s[0]); scanf( %s , &t[0]); long long ans = 0; long long cnt_a = 0; long long cnt_b = 0; bool found_diff = false; bool big_num = false; for (int i = 0; i < n; ++i) { if (found_diff && !big_num) { cnt_a = cnt_a * 2 + (s[i] == a ? 1 : 0); cnt_b = cnt_b * 2 + (t[i] == b ? 1 : 0); } if (s[i] != t[i]) { found_diff = true; } if (found_diff) { ans += min(cnt_a + cnt_b + 2, (long long)k); if (cnt_a + cnt_b + 2 >= k) { big_num = true; } } else { ++ans; } } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND4B_PP_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Inverter
// /___/ /\ Filename : INV.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module INV (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
not n1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 1; struct data { int l, r, sum; } tree[N << 2], sum_tree[N << 2]; struct node { int to, next; } a[N << 1]; int ans1 = 0, ans2 = 0, dp[N], head[N], st[N], ed[N], g[N][25], bx[N], by[N], bw[N], deep[N]; int n, m, cnt = 0; vector<int> qx[N]; void add(int x, int y) { a[++cnt].to = y, a[cnt].next = head[x], head[x] = cnt; a[++cnt].to = x, a[cnt].next = head[y], head[y] = cnt; } void dfs(int u, int fa) { st[u] = ++cnt; deep[u] = deep[fa] + 1; g[u][0] = fa; for (int i = head[u]; i != -1; i = a[i].next) { if (a[i].to != fa) dfs(a[i].to, u); } ed[u] = cnt; } void yyqx() { for (int i = 1; i < 25; ++i) for (int j = 1; j <= n; ++j) g[j][i] = g[g[j][i - 1]][i - 1]; } int GetLCA(int x, int y) { if (deep[x] > deep[y]) swap(x, y); for (int i = 24; i >= 0; --i) if (deep[y] - (1 << i) >= deep[x]) y = g[y][i]; if (x == y) return x; for (int i = 24; i >= 0; --i) if (g[x][i] != g[y][i]) x = g[x][i], y = g[y][i]; return g[x][0]; } void build(int index, int left, int right) { int mid = (left + right) >> 1; tree[index].sum = 0, sum_tree[index].sum = 0; tree[index].l = left, tree[index].r = right; sum_tree[index].l = left, sum_tree[index].r = right; if (left == right) return; build(index * 2, left, mid); build(index * 2 + 1, mid + 1, right); } void change(int index, int left, int right, int d) { if (left > right) return; if (tree[index].l >= left && tree[index].r <= right) { tree[index].sum += d; return; } if (tree[index * 2].r >= left) change(index * 2, left, right, d); if (tree[index * 2 + 1].l <= right) change(index * 2 + 1, left, right, d); } void search(int index, int x) { ans2 += tree[index].sum; if (tree[index].l == tree[index].r) return; if (x <= tree[index * 2].r) search(index * 2, x); if (x >= tree[index * 2 + 1].l) search(index * 2 + 1, x); } void sum_change(int index, int left, int right, int d) { if (left > right) return; if (sum_tree[index].l >= left && sum_tree[index].r <= right) { sum_tree[index].sum += d; return; } if (sum_tree[index * 2].r >= left) sum_change(index * 2, left, right, d); if (sum_tree[index * 2 + 1].l <= right) sum_change(index * 2 + 1, left, right, d); } void sum_search(int index, int x) { ans1 += sum_tree[index].sum; if (sum_tree[index].l == sum_tree[index].r) return; if (x <= sum_tree[index * 2].r) sum_search(index * 2, x); if (x >= sum_tree[index * 2 + 1].l) sum_search(index * 2 + 1, x); } void work(int u, int fa) { int sum = 0; for (int i = head[u]; i != -1; i = a[i].next) { if (a[i].to != fa) { work(a[i].to, u); sum += dp[a[i].to]; } } sum_change(1, st[u], ed[u], sum); dp[u] = sum; for (int i = 0; i < qx[u].size(); ++i) { int x = bx[qx[u][i]], y = by[qx[u][i]], w = bw[qx[u][i]]; int val = 0; ans1 = 0; sum_search(1, st[x]); val += ans1; ans1 = 0; sum_search(1, st[y]); val += ans1; val -= sum; ans2 = 0; search(1, st[x]); val -= ans2; ans2 = 0; search(1, st[y]); val -= ans2; dp[u] = max(dp[u], val + w); } ans1 = 0, ans2 = 0; change(1, st[u], ed[u], dp[u]); } int main() { int x, y, w; scanf( %d%d , &n, &m); memset(head, -1, sizeof(head)); for (int i = 1; i < n; ++i) { scanf( %d , &x); add(x, i + 1); } cnt = 0; dfs(1, 0); yyqx(); for (int i = 1; i <= m; ++i) { scanf( %d%d%d , &x, &y, &w); bx[i] = x, by[i] = y, bw[i] = w; qx[GetLCA(x, y)].push_back(i); } build(1, 1, n); work(1, 0); printf( %d n , dp[1]); return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : extension register instances.
// File : crt_misc.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Contains extension registers (40-4E), CR17 and
// Feature Control registers.
// The decodes for all the registers are being generated
// outside of this module in "crt_reg_dec.v"
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crt_misc
(
input dis_en_sta,
input c_raw_vsync,
input h_reset_n,
input h_hclk,
input color_mode, // 1 = color mode, 0 = mono misc_b0
input h_io_16, // 16 bit access = 1, 8 bit = 0
input h_io_wr, // IO write cycle
input [15:0] h_addr, // Host address
input [5:0] c_crtc_index, // CRT register index
input [7:0] c_ext_index, // Extended mode Index
input t_sense_n, // Monitor sense input from RAMDAC
input c_t_crt_int, // Interrupt to indicate vertical retrace
input a_is01_b5, // Video diagnostic (pixel data) bits
input a_is01_b4, // Video diagnostic (pixel data) bits
input vsync_vde, // vertical retrace ored with vde
input [15:0] h_io_dbus,
output [7:0] reg_ins0,
output [7:0] reg_ins1,
output [7:0] reg_fcr,
output reg [7:0] reg_cr17,
output c_cr17_b0,
output c_cr17_b1,
output cr17_b2,
output cr17_b3,
output c_cr17_b5,
output c_cr17_b6,
output cr17_b7,
output vsync_sel_ctl
);
reg str_fcr;
// Instantiating extension registers
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
str_fcr <= 1'b0;
reg_cr17 <= 8'b0;
end else if (h_io_wr) begin
case (h_addr)
// Mono CRT Index
16'h03b4: begin
if (!color_mode)
if (h_io_16) begin
// We can access the CRT Data registers if we are in 16 bit mode
case (c_crtc_index[5:0])
6'h17: reg_cr17 <= {h_io_dbus[15:13], 1'b0, h_io_dbus[11:8]};
endcase // case(c_crtc_index[5:5])
end
end
// Mono CRT Data
16'h03b5: begin
if (!color_mode) begin
case (c_crtc_index[5:0])
6'h17: reg_cr17 <= {h_io_dbus[15:13], 1'b0, h_io_dbus[11:8]};
endcase // case(c_crtc_index[5:5])
end
end
16'h03ba: if (!color_mode) str_fcr <= h_io_dbus[3];
// Color CRT Index
16'h03d4: begin
if (color_mode)
if (h_io_16) begin
// We can access the CRT Data registers if we are in 16 bit mode
case (c_crtc_index[5:0])
6'h17: reg_cr17 <= {h_io_dbus[15:13], 1'b0, h_io_dbus[11:8]};
endcase // case(c_crtc_index[5:5])
end
end
// Color CRT Data
16'h03d5: begin
if (color_mode) begin
case (c_crtc_index[5:0])
6'h17: reg_cr17 <= {h_io_dbus[15:13], 1'b0, h_io_dbus[11:8]};
endcase // case(c_crtc_index[5:5])
end
end
16'h03da: if (color_mode) str_fcr <= h_io_dbus[3];
endcase // case(h_addr)
end
assign reg_fcr = {4'b0, str_fcr, 3'b0};
assign vsync_sel_ctl = str_fcr;
assign reg_ins0 = {c_t_crt_int, 2'b00, t_sense_n, 4'b0000};
assign reg_ins1 = {2'b00, a_is01_b5, a_is01_b4, c_raw_vsync,
2'b00, dis_en_sta };
assign c_cr17_b0 = reg_cr17[0];
assign c_cr17_b1 = reg_cr17[1];
assign cr17_b2 = reg_cr17[2];
assign cr17_b3 = reg_cr17[3];
assign c_cr17_b5 = reg_cr17[5];
assign c_cr17_b6 = reg_cr17[6];
assign cr17_b7 = reg_cr17[7];
endmodule
|
// 32-bit ALU
// Function codes are defined on page 243
module alu( input [31:0] A, B,
input [2:0] F,
output reg [31:0] Y, output Zero);
always @ ( * )
case (F[2:0])
3'b000: Y <= A & B;
3'b001: Y <= A | B;
3'b010: Y <= A + B;
//3'b011: Y <= 0; // not used
3'b011: Y <= A & ~B;
3'b101: Y <= A + ~B;
3'b110: Y <= A - B;
3'b111: Y <= A < B ? 1:0;
default: Y <= 0; //default to 0, should not happen
endcase
assign Zero = (Y == 32'b0);
endmodule
// Example 7.6 Register file
module regfile(input clk,
input we3,
input [4:0] ra1, ra2, wa3,
input [31:0] wd3,
output [31:0] rd1, rd2);
reg [31:0] rf[31:0];
// three ported register file
// read two ports combinationally
// write third port on rising edge of clock
// register 0 hardwired to 0
always @(posedge clk)
if (we3) rf[wa3] <= wd3;
assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule
// Example 7.8 Left Shift (Multiply by 4)
module sl2(input [31:0] a,
output [31:0] y);
// shift left by 2
assign y = {a[29:0], 2'b00};
endmodule
// Example 7.9 Sign Extension
module signext(input [15:0] a,
output [31:0] y);
assign y = {{16{a[15]}}, a};
endmodule
// Example 7.10 Resettable Flip-flop with width parameter
module flopr #(parameter WIDTH = 8)
(input clk, reset,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk, posedge reset)
if (reset) q <= 0;
else q <= d;
endmodule
// Example 4.20 RESETTABLE ENABLED REGISTER with width parameter
module flopenr #(parameter WIDTH = 8)
(input clk, reset,
input en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk, posedge reset)
if (reset) q <= 0;
else if (en) q <= d;
endmodule
// Example 4.5 2:1 MULTIPLEXER with width parameter
module mux2 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
// 3:1 MULTIPLEXER with width parameter
module mux3 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2,
input [1:0] s,
output [WIDTH-1:0] y);
assign #1 y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule
// Example 4.6 4:1 MULTIPLEXER with width parameter
module mux4 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y);
always @( * )
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule
|
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-4-2017
*/
module jt51_mod(
input m1_enters,
input m2_enters,
input c1_enters,
input c2_enters,
input [2:0] alg_I,
output reg use_prevprev1,
output reg use_internal_x,
output reg use_internal_y,
output reg use_prev2,
output reg use_prev1
);
reg [7:0] alg_hot;
always @(*) begin
case( alg_I )
3'd0: alg_hot = 8'h1; // D0
3'd1: alg_hot = 8'h2; // D1
3'd2: alg_hot = 8'h4; // D2
3'd3: alg_hot = 8'h8; // D3
3'd4: alg_hot = 8'h10; // D4
3'd5: alg_hot = 8'h20; // D5
3'd6: alg_hot = 8'h40; // D6
3'd7: alg_hot = 8'h80; // D7
default: alg_hot = 8'hx;
endcase
end
always @(*) begin
use_prevprev1 = m1_enters | (m2_enters&alg_hot[5]);
use_prev2 = (m2_enters&(|alg_hot[2:0])) | (c2_enters&alg_hot[3]);
use_internal_x = c2_enters & alg_hot[2];
use_internal_y = c2_enters & (|{alg_hot[4:3],alg_hot[1:0]});
use_prev1 = m1_enters | (m2_enters&alg_hot[1]) |
(c1_enters&(|{alg_hot[6:3],alg_hot[0]}) )|
(c2_enters&(|{alg_hot[5],alg_hot[2]}));
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx ) #pragma GCC target( avx,tune=native ) using namespace std; const long long mod = 1e9 + 7; long long w[11]; vector<vector<long long> > mul(vector<vector<long long> >& a, vector<vector<long long> >& b) { vector<vector<long long> > ret(a.size(), vector<long long>(a.size(), 0)); for (long long i = 0; i < a.size(); i++) for (long long j = 0; j < a.size(); j++) ret[i][j] = 0; for (long long i = 0; i < a.size(); i++) { for (long long j = 0; j < a.size(); j++) { for (long long k = 0; k < a.size(); k++) { ret[i][j] += a[i][k] * b[k][j]; ret[i][j] %= mod; } } } return ret; } vector<vector<long long> > Pow(vector<vector<long long> > a, long long k) { vector<vector<long long> > ret = a, m = a; k--; do { if (k & 1) ret = mul(ret, m); m = mul(m, m); } while (k >>= 1); return ret; } long long dp[1 << 7], tdp[1 << 7], pre; void solve(long long x, long long times) { vector<vector<long long> > mat((1 << x), vector<long long>((1 << x), 0)); for (long long st = 0; st < (1 << x); st++) { for (long long ed = 0; ed < (1 << x); ed++) { for (long long bt = 0; bt < (1 << (x - 1)); bt++) { long long add = 1; for (long long j = 0; j < x; j++) { long long cnt = 0; if (bt & (1 << j) || j == x - 1) cnt++; if (j == 0 || (bt & (1 << (j - 1)))) cnt++; if (st & (1 << j)) cnt++; if (ed & (1 << j)) cnt++; if (cnt == 4) add = 0; } if (add) mat[st][ed]++; if (mat[st][ed] >= mod) mat[st][ed] -= mod; } } } mat = Pow(mat, times); memset(tdp, 0, sizeof tdp); long long or_mask = 0; for (long long i = pre; i < x; i++) or_mask |= (1 << i); for (long long i = 0; i < (1 << x); i++) { for (long long j = 0; j < (1 << x); j++) { tdp[j] += dp[i] * mat[i | or_mask][j]; tdp[j] %= mod; } } memcpy(dp, tdp, sizeof tdp); pre = x; } signed main() { for (long long i = 1; i <= 7; i++) cin >> w[i]; for (long long i = 1; i <= 7; i++) { if (w[i]) { dp[(1 << i) - 1] = 1; break; } } for (long long i = 1; i <= 7; i++) { if (w[i]) { solve(i, w[i]); } } for (long long i = 7; i >= 1; i--) { if (w[i]) { cout << dp[(1 << i) - 1] << endl; return 0; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_2_V
`define SKY130_FD_SC_LS__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_2_V
|
/*
* Tx Bridge
* Author: Kevin Bedrossian
*
* This module takes header input from a header queue and
* the appropriate data input from the OCP_master_FSM.
* It will then output the header and then the data on the
* Xilinx PCIe core using the AXI4 Stream interface.
*/
`define fifo_wdth 64
`define data_wdth 8
module txbridge(
input wire clk,
input wire reset,
//OCP_master connections (AXI-4 stream)/*{{{*/
input wire data_valid,
output reg data_ready,
input wire [`fifo_wdth - 1:0] data_data,
input wire [`data_wdth - 1:0] data_keep,
input wire data_last,
/*}}}*/
//AXI HEADER FIFO connections/*{{{*/
input wire header_valid,
output reg header_ready,
input wire [`fifo_wdth - 1:0] header_data,
input wire [`data_wdth - 1:0] header_keep,
input wire header_last,
/*}}}*/
//PCIe AXI connections/*{{{*/
output reg AXI_out_valid,
input wire AXI_out_ready,
output reg [`fifo_wdth - 1: 0] AXI_out_data,
output reg [`data_wdth - 1: 0] AXI_out_keep,
output reg AXI_out_last
/*}}}*/
);
//Declarations/*{{{*/
//State encoding
localparam IDLE = 3'b000;
localparam FIRST_DW = 3'b001;
localparam SECOND_DW = 3'b010;
localparam HEADER = 3'b011;
localparam DATA = 3'b100;
localparam COMPLETE = 3'b101;
//Format encoding for PCI Express 3.0
localparam NO_DATA_3DW = 3'b000; // 3DW header, no data
localparam NO_DATA_4DW = 3'b001; // 4DW header, no data
localparam W_DATA_3DW = 3'b010; // 3DW header, with data
localparam W_DATA_4DW = 3'b011; // 4DW header, with data
localparam TLP_PRFX = 3'b100; // TLP Prefix
//Type encoding for PCI Express 2.0
localparam MRD = 5'b0_0000; // Memory Read Request (if format = 000 or 001)
localparam MRDLK = 5'b0_0001; // Memory Read Request-locked
localparam MWR = 5'b0_0000; // Memory Write Request (if format = 010 or 011)
localparam CPL = 5'b0_1010; // Completion packet
localparam CPLLK = 5'b0_1011; // Completion for locked request
reg [2:0] state;
reg [2:0] next;
reg header_started;
reg is_data;
reg [1:0] address_type;
reg [1:0] header_counter;
reg [9:0] data_counter;
reg [1:0] header_length;
reg [9:0] data_length;
/*}}}*/
//State transition logic/*{{{*/
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
end
else begin
state <= next;
end
end
/*}}}*/
//Next state logic/*{{{*/
always @(state) begin
case (state)
IDLE: begin
if(header_valid & AXI_out_ready) begin
next <= FIRST_DW; // Data is in the AXI FIFO for us
end
else begin
next <= IDLE;
end
end
FIRST_DW: begin
if (header_valid & AXI_out_ready) begin
next <= SECOND_DW;
end
else begin
next <= FIRST_DW;
end
end
SECOND_DW: begin //Add an extra DW for completion packet
if(header_valid & AXI_out_ready) begin
next <= HEADER;
end
else begin
next <= SECOND_DW;
end
end
HEADER: begin
if((header_counter == header_length) & is_data) begin
next <= DATA;
end
else if((header_counter == header_length) & ~is_data) begin
next <= COMPLETE;
end
else begin
next <= HEADER;
end
end
DATA: begin
if (data_counter == data_length) begin
next <= COMPLETE; //Data is finished
end
else begin
next <= DATA;
end
end
default: begin //The "COMPLETE" state always goes to IDLE
next <= IDLE;
end
endcase
end
/*}}}*/
//Output logic/*{{{*/
always @(posedge clk) begin
//RESET/*{{{*/
if (reset) begin
//AXI input
header_ready <= 1'b0;
data_ready <= 1'b0;
//Bridge internals/*{{{*/
is_data <= 1'b0;
header_counter <= 2'b0;
data_counter <= 2'b0;
data_length <= 10'b0;
header_length <= 2'b0;
AXI_out_data <= 64'b0;
AXI_out_last <= 1'b0;
AXI_out_valid <= 1'b0;
end
/*}}}*/
/*}}}*/
else begin
case (next)
//IDLE/*{{{*/
IDLE: begin
//AXI input
header_ready <= 1'b0;
data_ready <= 1'b0;
//Bridge internals/*{{{*/
is_data <= 1'b0;
header_counter <= 2'b0;
data_counter <= 2'b0;
data_length <= 10'b0;
header_length <= 2'b0;
AXI_out_data <= `fifo_wdth'b0;
AXI_out_last <= 1'b0;
AXI_out_valid <= 1'b0;
AXI_out_keep <= `data_wdth'b0;
end
/*}}}*/
/*}}}*/
//FIRST_DW/*{{{*/
FIRST_DW: begin
//AXI input
data_ready <= 1'b0;
if(header_valid & AXI_out_ready) begin
AXI_out_valid <= 1'b1;
header_ready <= 1'b1;
end
else begin
AXI_out_valid <= 1'b0;
header_ready <= 1'b0;
end
case(header_data[31:24])
{NO_DATA_3DW, MRD}: begin
AXI_out_data <= {header_data[63:32],
W_DATA_3DW, CPL,
header_data[23:0]};
is_data <= 1'b1;
header_length <= 2'b10;
end
{NO_DATA_4DW, MRD}: begin
AXI_out_data <= {header_data[63:32],
W_DATA_4DW, CPL,
header_data[23:0]};
is_data <= 1'b1;
header_length <= 2'b11;
end
{NO_DATA_3DW, MRDLK}: begin
AXI_out_data <= {header_data[63:32],
W_DATA_3DW, CPLLK,
header_data[23:0]};
is_data <= 1'b1;
header_length <= 2'b10;
end
{NO_DATA_4DW, MRDLK}: begin
AXI_out_data <= {header_data[63:32],
W_DATA_4DW, CPLLK,
header_data[23:0]};
is_data <= 1'b1;
header_length <= 2'b11;
end
{W_DATA_3DW, MWR}: begin
AXI_out_data <= {header_data[63:32],
NO_DATA_3DW, CPL,
header_data[23:0]};
is_data <= 1'b0;
header_length <= 2'b10;
end
{W_DATA_4DW, MWR}: begin
AXI_out_data <= {header_data[63:32],
NO_DATA_4DW, CPL,
header_data[23:0]};
is_data <= 1'b0;
header_length <= 2'b11;
end
default: begin
AXI_out_data <= `fifo_wdth'b0;
is_data <= 1'b0;
header_length <= 2'b0;
end
endcase
data_counter <= 10'b0;
header_counter <= 2'b0;
data_length <= header_data[9:0];
AXI_out_last <= 1'b0;
AXI_out_keep <= header_keep;
end
/*}}}*/
//SECOND_DW empty placeholder at the moment/*{{{*/
SECOND_DW: begin
header_ready <= 1'b0;
data_ready <= 1'b0;
//Bridge internals/*{{{*/
is_data <= is_data;
header_counter <= 2'b0;
data_counter <= 2'b0;
data_length <= 10'b0;
header_length <= 2'b0;
AXI_out_data <= 64'b0;
AXI_out_last <= 1'b0;
AXI_out_valid <= 1'b0;
AXI_out_keep <= {`data_wdth{1'b1}};
end
/*}}}*/
/*}}}*/
//HEADER/*{{{*/
HEADER: begin
//AXI input
data_ready <= 1'b0;
if(header_valid & AXI_out_ready) begin
header_counter <= header_counter + 1'b1;
AXI_out_valid <= 1'b1;
header_ready <= 1'b1;
end
else begin
header_counter <= header_counter;
AXI_out_valid <= 1'b0;
header_ready <= 1'b0;
end
is_data <= is_data;
AXI_out_data <= header_data;
data_counter <= 10'b0;
data_length <= data_length;
header_length <= header_length;
AXI_out_last <= 1'b0;
AXI_out_keep <= header_keep;
end
/*}}}*/
//DATA/*{{{*/
DATA: begin
//AXI input
header_ready <= 1'b0;
if(data_valid & AXI_out_ready) begin
data_counter <= data_counter + data_keep;
AXI_out_valid <= 1'b1;
data_ready <= 1'b1;
end
else begin
data_counter <= data_counter;
AXI_out_valid <= 1'b0;
data_ready <= 1'b0;
end
//Bridge internals/*{{{*/
if(data_counter == data_length) begin
AXI_out_last <= 1'b1;
end
else begin
AXI_out_last <= 1'b0;
end
is_data <= is_data;
AXI_out_data <= data_data;
header_counter <= 2'b0;
data_length <= data_length;
header_length <= header_length;
AXI_out_keep <= data_keep;
end
/*}}}*/
/*}}}*/
//DEFAULT/COMPLETE /*{{{*/
default: begin
// AXI input
AXI_out_valid <= 1'b0;
data_ready <= 1'b0;
header_ready <= 1'b0;
//Bridge internals/*{{{*/
is_data <= 1'b0;
header_counter <= 2'b0;
data_counter <= 10'b0;
data_length <= 10'b0;
header_length <= 2'b0;
AXI_out_data <= `fifo_wdth'b0;
AXI_out_last <= 1'b0;
AXI_out_keep <= `data_wdth'b0;
end
/*}}}*/
/*}}}*/
endcase
end
end
/*}}}*/
endmodule
|
//IEEE Floating Point Adder (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
//if a is inf and signs don't match return nan
if ((b_e == 1024) && (a_s != b_s)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
end
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
if ($signed(z_e) == -1022 && z_m[52:0] == 0) begin
z[63] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
//Cells still in this file have INCOMPLETE simulation models, need to finish them
module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
parameter PWRDN_SYNC = 1'b0;
parameter CLK_EDGE = "RISING";
parameter GREATER_OR_EQUAL = 1'b0;
//TODO implement power-down mode
initial GREATER = 0;
initial EQUAL = 0;
wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
always @(posedge clk_minv) begin
if(GREATER_OR_EQUAL)
GREATER <= (INP >= INN);
else
GREATER <= (INP > INN);
EQUAL <= (INP == INN);
end
endmodule
module GP_EDGEDET(input IN, output reg OUT);
parameter EDGE_DIRECTION = "RISING";
parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;
//not implemented for simulation
endmodule
module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
parameter OSC_FREQ = "25k";
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation
//auto powerdown not implemented for simulation
always begin
if(PWRDN) begin
CLKOUT_HARDIP = 0;
CLKOUT_FABRIC = 0;
end
else begin
if(OSC_FREQ == "25k") begin
//half period of 25 kHz
#20000;
end
else begin
//half period of 2 MHz
#250;
end
CLKOUT_HARDIP = ~CLKOUT_HARDIP;
CLKOUT_FABRIC = ~CLKOUT_FABRIC;
end
end
endmodule
module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation
//auto powerdown not implemented for simulation
always begin
if(PWRDN) begin
CLKOUT_HARDIP = 0;
CLKOUT_FABRIC = 0;
end
else begin
//half period of 27 MHz
#18.518;
CLKOUT_HARDIP = ~CLKOUT_HARDIP;
CLKOUT_FABRIC = ~CLKOUT_FABRIC;
end
end
endmodule
module GP_SPI(
input SCK,
inout SDAT,
input CSN,
input[7:0] TXD_HIGH,
input[7:0] TXD_LOW,
output reg[7:0] RXD_HIGH,
output reg[7:0] RXD_LOW,
output reg INT);
initial RXD_HIGH = 0;
initial RXD_LOW = 0;
initial INT = 0;
parameter DATA_WIDTH = 8; //byte or word width
parameter SPI_CPHA = 0; //SPI clock phase
parameter SPI_CPOL = 0; //SPI clock polarity
parameter DIRECTION = "INPUT"; //SPI data direction (either input to chip or output to host)
//parallel output to fabric not yet implemented
//TODO: write sim model
//TODO: SPI SDIO control... can we use ADC output while SPI is input??
//TODO: clock sync
endmodule
//keep constraint needed to prevent optimization since we have no outputs
(* keep *)
module GP_SYSRESET(input RST);
parameter RESET_MODE = "EDGE";
parameter EDGE_SPEED = 4;
//cannot simulate whole system reset
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MxN = (int)2e5 + 9; const int mod = 998244353; long long fact[MxN + 9]; vector<int> adj[MxN + 9]; long long f(const int u, const int parent) { long long res = fact[(int)adj[u].size()]; for (int v : adj[u]) if (v != parent) { res *= f(v, u); res %= mod; } return res; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); fact[0] = 1; for (int i = 1; i <= MxN; ++i) { fact[i] = fact[i - 1] * i % mod; } int n; cin >> n; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } long long ans = n * fact[adj[1].size()] % mod; for (int x : adj[1]) { ans *= f(x, 1); ans %= mod; } cout << ans; return 0; } |
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: div_43.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.3 Build 178 02/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module div_43 (
clken,
clock,
denom,
numer,
quotient,
remain);
input clken;
input clock;
input [26:0] denom;
input [42:0] numer;
output [42:0] quotient;
output [26:0] remain;
wire [26:0] sub_wire0;
wire [42:0] sub_wire1;
wire [26:0] remain = sub_wire0[26:0];
wire [42:0] quotient = sub_wire1[42:0];
lpm_divide LPM_DIVIDE_component (
.clock (clock),
.clken (clken),
.denom (denom),
.numer (numer),
.remain (sub_wire0),
.quotient (sub_wire1),
.aclr (1'b0));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_pipeline = 5,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 27,
LPM_DIVIDE_component.lpm_widthn = 43;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_SYMBOL_V
`define SKY130_FD_SC_MS__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_SYMBOL_V
|
// Double pumped single precision floating point multiply
// Latency = 6 kernel clocks
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// !!! WARNING !!!
// This core no longer works because the core is no longer fully high-capacity
// (and has a single staging register, which messes up things in the 2x clock
// domain). See acl_fp_custom_mul_hc.v and acl_fp_custom_mul_hc_core.v for
// details.
// !!! WARNING !!!
module acl_fp_custom_mul_hc_dbl_pumped
#( parameter WIDTH = 32 )
(
input logic clock,
input logic clock2x,
input logic resetn,
input logic valid_in,
input logic stall_in,
output logic valid_out,
output logic stall_out,
input logic [WIDTH-1:0] a1,
input logic [WIDTH-1:0] b1,
input logic [WIDTH-1:0] a2,
input logic [WIDTH-1:0] b2,
output logic [WIDTH-1:0] y1,
output logic [WIDTH-1:0] y2
);
localparam LATENCY = 6; // in "clock" cycles
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
logic sel2x /* synthesis preserve */;
// This is for simulation purposes. Matches physical behavior where
// registers power up to zero.
initial
begin
sel2x = 1'b0;
end
always@(posedge clock2x)
sel2x <= ~sel2x; // either the same as clock or ~clock
// The block is high-capacity. Here are all of the
// valid_in/out, stall_in/out signals for all "clock" cycles.
//
// Index 1 corresponds to the first cycle.
typedef struct packed {
logic valid_in, valid_out;
logic stall_in, stall_out;
} stage_flow_control;
stage_flow_control s [1:LATENCY];
genvar i;
generate
for( i = 1; i <= LATENCY; i = i + 1 )
begin:stage
// valid_in
if( i == 1 )
assign s[i].valid_in = valid_in;
else
assign s[i].valid_in = s[i-1].valid_out;
// valid_out
always @(posedge clock or negedge resetn)
if( ~resetn )
s[i].valid_out <= 1'b0;
else if( ~s[i].stall_out )
s[i].valid_out <= s[i].valid_in;
// stall_in
if( i == LATENCY )
assign s[i].stall_in = stall_in;
else
assign s[i].stall_in = s[i+1].stall_out;
// stall_out
assign s[i].stall_out = s[i].valid_out & s[i].stall_in;
end
endgenerate
assign valid_out = s[LATENCY].valid_out;
assign stall_out = s[1].stall_out;
// Register before double pumping
logic [WIDTH-1:0] a1_reg;
logic [WIDTH-1:0] b1_reg;
logic [WIDTH-1:0] a2_reg;
logic [WIDTH-1:0] b2_reg;
always @(posedge clock)
if( ~s[1].stall_out )
begin
a1_reg <= a1;
a2_reg <= a2;
b1_reg <= b1;
b2_reg <= b2;
end
// Clock domain transfer
logic [WIDTH-1:0] a1_reg_2x;
logic [WIDTH-1:0] a2_reg_2x;
logic [WIDTH-1:0] b1_reg_2x;
logic [WIDTH-1:0] b2_reg_2x;
logic valid_out_2x;
always @(posedge clock2x)
if( ~s[2].stall_out )
begin
a1_reg_2x <= a1_reg;
a2_reg_2x <= a2_reg;
b1_reg_2x <= b1_reg;
b2_reg_2x <= b2_reg;
valid_out_2x <= s[1].valid_out;
end
// The multipler. Takes six "clock2x" cycles to complete
// (so takes 3 "clock" cycles to complete).
logic [WIDTH-1:0] fp_mul_inp_a;
logic [WIDTH-1:0] fp_mul_inp_b;
logic [WIDTH-1:0] fp_mul_res;
logic fp_mul_valid_out, fp_mul_stall_out;
assign fp_mul_inp_a = (sel2x) ? a2_reg_2x : a1_reg_2x;
assign fp_mul_inp_b = (sel2x) ? b2_reg_2x : b1_reg_2x;
acl_fp_custom_mul_hc the_mul(
.resetn(resetn),
.clock(clock2x),
.valid_in(valid_out_2x),
.stall_in(s[5].stall_out),
.valid_out(fp_mul_valid_out),
.stall_out(fp_mul_stall_out),
.dataa(fp_mul_inp_a),
.datab(fp_mul_inp_b),
.result(fp_mul_res));
// Track which set of inputs was selected in parallel with the
// multipler's pipeline. Track in the "clock2x" domain.
//
// There are six stages in this pipeline to correspond with the
// six stages in acl_fp_custom_mul_hc's pipeline.
logic sel_21, sel_22, sel_31, sel_32, sel_41, sel_42;
always @(posedge clock2x)
begin
if( ~s[2].stall_out ) // clock -> clock2x
begin
sel_21 <= sel2x;
sel_22 <= sel_21;
end
if( ~s[3].stall_out ) // clock -> clock2x
begin
sel_31 <= sel_22;
sel_32 <= sel_31;
end
if( ~s[4].stall_out ) // clock -> clock2x
begin
sel_41 <= sel_32;
sel_42 <= sel_41;
end
end
// Additional clock2x pipeline register to even things out
// and separate the results from the two inputs in preparation
// for the clock transfer back to the "clock" domain.
logic [31:0] res1_5, res2_5;
always @(posedge clock2x)
if( ~s[5].stall_out ) // clock -> clock2x
begin
if( sel_42 )
begin
// This is the result from the 2nd set of inputs.
res2_5 <= fp_mul_res;
end
else
begin
// This is the result from the 1st set of inputs.
res1_5 <= fp_mul_res;
end
end
// Output registers. Cross-clock path from clock2x -> clock.
always @(posedge clock)
begin
if( ~s[6].stall_out )
begin
y1 <= res1_5;
y2 <= res2_5;
end
end
endmodule
|
`timescale 1ns / 1ps
module Gato_FSM(
clk,
reset,
state,
p1_mm,
p2_mm,
//entradas que son salidas de la otra maquina de estados
p1_tie,
p1_loss,
p1_win,
p2_tie,
p2_loss,
p2_win,
//salidas que van hacia a otra maquina de estados
verifica_status,
turno_p1,
turno_p2,
win_game,
loss_game,
tie_game
);
input clk, reset;
input p1_mm, p2_mm;
input p1_tie, p1_loss, p1_win, p2_tie, p2_loss, p2_win;
output reg turno_p1, turno_p2;
output reg verifica_status;
output reg win_game, loss_game, tie_game;
output [3:0] state;
reg [3:0] state, nextState;
//Estados de las FSM
parameter P1_Move = 0;
parameter P1_Status = 1;
parameter P2_Move = 2;
parameter P2_Status = 3;
parameter Win = 4;
parameter Tie = 5;
parameter Loss = 6;
initial turno_p1 <= 1'b1;
initial turno_p2 <= 1'b0;
//Asignación sincrona del singuiente estado
always @(posedge clk or posedge reset)
begin
if (reset)
state <= P1_Move;
else
state <= nextState;
end
//Asignacion asincrona de los estados
always @(state or p1_mm or p2_mm or p1_win or p1_loss or p1_tie or p2_win or p2_loss or p2_tie)
begin
nextState = 3'bxxx;
case(state)
P1_Move:
begin
verifica_status <= 1'b0;
turno_p1 <= 1'b1;
turno_p2 <= 1'b0;
if (p1_mm == 1'b0)
nextState = P1_Move;
else if (p1_mm == 1'b1)
nextState = P1_Status;
end
P1_Status:
begin
verifica_status <= 1'b1;
turno_p1 <= 1'b0;
turno_p2 <= 1'b1;
if (p1_tie == 1'b1 & p1_loss == 1'b0 & p1_win == 1'b0)
nextState = Tie;
else if (p1_win == 1'b1 & p1_tie == 1'b0 & p1_loss == 1'b0)
nextState = Loss;
else if (p2_mm == 1'b0)
nextState = P2_Move;
end
P2_Move:
begin
verifica_status <= 1'b0;
turno_p1 <= 1'b0;
turno_p2 <= 1'b1;
if (p2_mm == 1'b0)
nextState = P2_Move;
else if (p2_mm == 1'b1)
nextState = P2_Status;
end
P2_Status:
begin
verifica_status <= 1'b1;
turno_p1 <= 1'b1;
turno_p2 <= 1'b0;
if (p2_tie == 1'b1 & p2_loss == 1'b0 & p2_win == 1'b0)
nextState = Tie;
else if (p2_win == 1'b1 & p2_tie == 1'b0 & p2_loss == 1'b0)
nextState = Win;
else if (p1_mm == 1'b0)
nextState = P1_Move;
end
Win:
begin
win_game <= 1'b1;
nextState = Win;
end
Tie:
begin
tie_game <= 1'b1;
nextState = Tie;
end
Loss:
begin
loss_game <= 1'b1;
nextState = Loss;
end
default: nextState = P1_Move;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 2000000000; using namespace std; template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } long long n; vector<int> adj[200005]; vector<bool> visited; vector<int> ans; void dfs(int v) { visited[v] = true; for (int u : adj[v]) { if (!visited[u]) dfs(u); } ans.push_back(v); } void topological_sort() { visited.assign(n, false); ans.clear(); for (int i = 0; i < n; ++i) { if (!visited[i]) dfs(i); } reverse(ans.begin(), ans.end()); } long long p2(long long x) { return x * x; } long long dist2(pair<long long, long long> p, pair<long long, long long> q) { return p2(p.first - q.first) + p2(p.second - q.second); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; vector<long long> t(n); vector<double> p(n); vector<pair<long long, long long> > x(n); for (int i = (0); i < (int)(n); i++) { long long ti, xi, yi; double pi; cin >> xi >> yi >> ti >> pi; t[i] = ti, p[i] = pi; x[i] = {xi, yi}; } for (int i = (0); i < (int)(n); i++) { for (int j = (0); j < (int)(n); j++) { if (t[i] < t[j] && p2(t[i] - t[j]) >= dist2(x[j], x[i])) adj[i].push_back(j); } } vector<double> dp(n, 0); for (int i = (0); i < (int)(n); i++) dp[i] = p[i]; topological_sort(); for (int iii = (0); iii < (int)(n); iii++) { long long i = ans[iii]; for (auto j : adj[i]) dp[j] = max(dp[j], dp[i] + p[j]); } for (int i = (0); i < (int)(n); i++) 42; 42; 42; double out = dp[0]; for (int i = (0); i < (int)(n); i++) out = max(out, dp[i]); cout << fixed << setprecision(10) << out << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long double PI = 3.14159265358979323846L; const long double E = 2.71828182845904523536L; const int INF = (1 << 30) - 1; const long long LINF = 1e18; const long double eps = 1e-7; const long long mod = 1e9 + 7; unordered_map<long long, long long> u[65][10]; vector<pair<int, int> > v; long long ans[65]; int k, n; unordered_map<long long, int> match; unordered_set<long long> skip; long long solve(long long idx, int lvl, int c) { if (u[lvl][c].count(idx)) { return u[lvl][c][idx]; } long long& r = u[lvl][c][idx]; if (match.count(idx)) { if (match[idx] != c) { r = 0; return r; } } if (lvl == k) { r = 1; return 1; } if (!skip.count(idx)) { r = ans[lvl]; return r; } long long m1 = 0, m2 = 0; for (int j = 0; j < 6; j++) { if (j == c || j == (c ^ 1)) { continue; } m1 += solve(idx * 2, lvl + 1, j); m2 += solve(idx * 2 + 1, lvl + 1, j); } m1 %= mod; m2 %= mod; r = m1 * m2 % mod; return r; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); std::cout << std::fixed << std::setprecision(20); cin >> k >> n; unordered_map<string, int> g; g[ white ] = 0; g[ yellow ] = 1; g[ green ] = 2; g[ blue ] = 3; g[ red ] = 4; g[ orange ] = 5; for (int i = 0; i < n; i++) { long long x; string s; cin >> x >> s; match[x] = g[s]; while (x) { skip.insert(x); x /= 2; } } ans[k] = 1; for (int i = k - 1; i >= 1; i--) { ans[i] = (4 * ans[i + 1]) % mod; ans[i] = (ans[i] * ans[i]) % mod; } long long r = 0; for (int i = 0; i < 6; i++) { r += solve(1, 1, i); } cout << r % mod << n ; } |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
// always on busy controller
module mbus_busy_ctrl(
input CLKIN,
input RESETn,
input BC_RELEASE_ISO,
input SC_CLR_BUSY,
input MBUS_CLR_BUSY,
output reg BUS_BUSYn);
reg clr_busy_temp;
always @ *
begin
if (BC_RELEASE_ISO==`IO_HOLD)
clr_busy_temp = 0;
else
clr_busy_temp = MBUS_CLR_BUSY;
end
wire RESETn_BUSY = ((~clr_busy_temp) & (~SC_CLR_BUSY));
// Use SRFF
always @ (negedge CLKIN or negedge RESETn or negedge RESETn_BUSY)
begin
// set port
if (~RESETn)
BUS_BUSYn <= 1;
// reset port
else if (~CLKIN)
BUS_BUSYn <= 0;
// clk port
else
BUS_BUSYn <= 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; static const int maxn = 1000 + 10; int n, m, f[maxn][maxn]; char s[maxn], t[maxn]; int main() { scanf( %d %d , &n, &m); scanf( %s , s); scanf( %s , t); int mn = n + 1; vector<int> ans; for (int i = 0; i + n <= m; i++) { int count = 0; vector<int> now; for (int j = 0; j < n; j++) if (s[j] != t[i + j]) { count++; now.emplace_back(j + 1); } if (count < mn) { mn = count; ans = now; } } printf( %d n , mn); for (int i = 0; i < ans.size(); i++) printf( %d%c , ans[i], n [i == mn - 1]); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:51:52 05/16/2015
// Design Name: IO_memory
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_IO_memory.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: IO_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_IO_memory;
// Inputs
reg clock;
reg IO_write;
reg [11:0] IO_address;
reg [15:0] IO_data_in;
reg [15:0] processor_input;
// Outputs
wire [15:0] IO_data_out;
wire [15:0] processor_output;
// Instantiate the Unit Under Test (UUT)
IO_memory uut (
.clock(clock),
.IO_write(IO_write),
.IO_address(IO_address),
.IO_data_in(IO_data_in),
.IO_data_out(IO_data_out),
.processor_input(processor_input),
.processor_output(processor_output)
);
initial begin
// Initialize Inputs
clock = 0;
IO_write = 0;
IO_address = 0;
IO_data_in = 0;
processor_input = 16'h3131;
// Wait 100 ns for global reset to finish
//#100;
// #2;
// IO_address = 12'h001;
//
// #2;
// IO_address = 12'h002;
//
// #2;
// IO_address = 12'h009;
// IO_data_in = 16'h2121;
// IO_write = 1;
//
// #2;
// IO_address = 12'h002;
// IO_data_in = 0;
// IO_write = 0;
//
// #2;
// IO_address = 12'h009;
//
// #2;
// IO_address = 12'hff0;
//
// #2;
// IO_address = 12'hff1;
// IO_data_in = 16'h5555;
// IO_write = 1;
//
// #2;
// IO_write = 0;
// IO_data_in = 0;
// IO_address = 12'h001;
//
// #2;
// IO_write = 0;
// IO_address = 12'h002;
//
// #2;
// IO_address = 12'hff1;
#30;
IO_address = 12'h000;
#20;
IO_address = 12'h00f;
#20;
IO_address = 12'h000;
#20;
IO_address = 12'hff0;
#40;
IO_address = 12'h001;
#20;
IO_address = 12'h000;
#20;
IO_address = 12'h00a;
IO_data_in = 16'h3169;
IO_write = 1;
#20;
IO_address = 12'h002;
IO_data_in = 0;
IO_write = 0;
#20;
IO_address = 12'h003;
#20;
IO_address = 12'h00a;
#20;
IO_address = 12'h004;
#20;
IO_address = 12'hff0;
IO_data_in = 16'h3170;
IO_write = 1;
#20;
IO_address = 12'h002;
IO_data_in = 0;
IO_write = 0;
#20;
IO_address = 12'hff0;
#20;
IO_address = 12'h004;
#20;
IO_address = 12'hff1;
IO_data_in = 16'h3170;
IO_write = 1;
#20;
IO_address = 12'h002;
IO_data_in = 0;
IO_write = 0;
#20;
IO_address = 12'hff1;
#20;
IO_address = 12'h004;
end
always #10 clock = !clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; const int OO = (int)1e9 + 7; const int MAX = 109; char c1, c2, c3; string s1, s2, s3; long long n, m, k, t, a, b, c, d, e, f, x, y, z, sol = 0, ans = 0; long long ar[1000009]; map<long long, bool> vis; int fun(int i) { int ret = 0; for (int i = 0; i < n; i++) { if (ar[i] % m == 0 && vis[ar[i] / m]) continue; vis[ar[i]] = 1; ret++; } return ret; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 0; i < n; i++) cin >> ar[i]; sort(ar, ar + n); cout << fun(0); cout << n n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_TB_V
`define SKY130_FD_SC_LP__O21BAI_TB_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21bai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_lp__o21bai dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long int OO = 2e7; const double EPS = (1e-7); int dcmp(double x, double y) { return fabs(x - y) <= EPS ? 0 : x < y ? -1 : 1; } bool sort_p(pair<int, int> a, pair<int, int> b) { return a.first < b.first; } int main() { ios_base::sync_with_stdio(0); cin.tie(); cout.tie(); int n; cin >> n; vector<int> a(n); vector<int> b(n, 0); vector<bool> s(n + 1); vector<int> t(n + 1); bool k = false, q = false; for (int i = 0; i < (int)(n); ++i) { cin >> a[i]; if (a[i] == 0) k = true; if (a[i] != 0 && k) q = true; s[n - a[i]] = true; t[a[i]]++; } if (k) { for (int i = 0; i < (int)(n); ++i) if (a[i] != 0) { cout << Impossible ; return 0; } } if (k) { cout << Possible n ; for (int i = 0; i < (int)(n); ++i) cout << 1 << ; return 0; } long long int sum = 0; for (int i = 0; i < (int)(n); ++i) { sum = t[i]; if (n - i != 0 && t[i] != 0 && sum % (n - i)) { cout << Impossible ; return 0; } } vector<pair<int, int>> p; for (int i = 0; i < (int)(n); ++i) { pair<int, int> r = make_pair(n - a[i], i); p.push_back(r); } sort(((p).begin()), ((p).end()), sort_p); int l = 1; int j = 0; for (int i = 0; i < ((int)((p).size())); ++i) { for (j = 0; j < p[i].first; j++) { b[p[i + j].second] = l; } i = i + j - 1; l++; } if (sum > n) { cout << Impossible ; return 0; } cout << Possible n ; for (int i = 0; i < (int)(n); ++i) cout << b[i] << ; } |
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c; long double x1, y1, x2, y2, s, x3, y3, x4, y4, x5, y5, x6, y6; cin >> a >> b >> c; cin >> x1 >> y1 >> x2 >> y2; x3 = x1; y3 = (-a * x3 - c) / b; y4 = y1; x4 = (-b * y4 - c) / a; x5 = x2; y5 = (-a * x5 - c) / b; y6 = y2; x6 = (-b * y6 - c) / a; s = min(min(min((abs(x1 - x2) + abs(y1 - y2)), (abs(y1 - y3) + abs(y2 - y5) + sqrt((y3 - y5) * (y3 - y5) + (x3 - x5) * (x3 - x5)))), min((abs(y1 - y3) + abs(x2 - x6) + sqrt((y3 - y6) * (y3 - y6) + (x3 - x6) * (x3 - x6))), (abs(x1 - x4) + abs(y2 - y5) + sqrt((y4 - y5) * (y4 - y5) + (x4 - x5) * (x4 - x5))))), (abs(x1 - x4) + abs(x2 - x6) + sqrt((y4 - y6) * (y4 - y6) + (x4 - x6) * (x4 - x6)))); cout << setprecision(19) << s; return 0; } |
#include <bits/stdc++.h> using namespace std; long long N = 10000000000000000; int points = 0; int main() { long long xo, yo, ax, ay, bx, by; cin >> xo >> yo >> ax >> ay >> bx >> by; long long x, y, t; cin >> x >> y >> t; long long X[100], Y[100]; X[0] = xo, Y[0] = yo; for (int i = 1; i < 55; i++) { X[i] = ax * X[i - 1] + bx; Y[i] = ay * Y[i - 1] + by; points++; if (X[i] >= N || Y[i] >= N) break; } long long maxi = 0; for (int i = 0; i <= points; i++) { for (int j = 0; j <= points; j++) { long long tmpx = X[i], tmpy = Y[i], tt = t, ans = 0; tt -= abs(X[i] - x) + abs(y - Y[i]); if (tt >= 0) ans = 1; int k = i + 1; if (i > j) k = i - 1; for (;;) { if ((k > i && k > j) || (k < i && k < j)) break; long long curx = X[k], cury = Y[k]; tt -= abs(tmpx - curx) + abs(tmpy - cury); tmpx = curx, tmpy = cury; if (tt < 0) break; ans++; if (i <= j) k++; else k--; } maxi = max(maxi, ans); } } cout << maxi << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x, p, q, count = 0; cin >> n; vector<int> v; vector<int>::iterator it; for (int i = 0; i < n; i++) { cin >> x; v.push_back(x); } for (int i = 0; i < n; i++) { p = i; for (int j = i + 1; j < n; j++) { if (v[p] == v[j]) { v[p] = 0; p = j; } } } for (it = v.begin(); it != v.end(); it++) { if ((*it) != 0) count++; } cout << count << endl; for (it = v.begin(); it != v.end(); it++) { if ((*it) != 0) cout << *it << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int a, b; node() { a = b = 0; } } node[10005]; int main() { int n, v; cin >> n >> v; for (int i = 0; i < n; i++) { int a, b; cin >> a >> b; node[a].a += b; } int ans = 0; for (int i = 1; i <= 3001; i++) { int vv = v; if (vv < node[i].b) { ans += vv; node[i + 1].b += node[i].a; } else { ans += node[i].b; vv -= node[i].b; if (vv >= node[i].a) { ans += node[i].a; } else { ans += vv; node[i + 1].b += node[i].a - vv; } } } cout << ans; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLRTN_BEHAVIORAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_no_pg/sky130_fd_sc_hs__u_dl_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtn (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int n, ch, x, y; vector<int> path[maxn]; vector<int> ans; int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); path[x].push_back(y); path[y].push_back(x); } ch = 0; for (int i = 1; i <= n; i++) if (path[i].size() > 2) { if (ch == 0) ch = i; else { puts( No ); return 0; } } if (ch == 0) { puts( Yes ); puts( 1 ); x = y = 0; for (int i = 1; i <= n; i++) if (path[i].size() == 1) { if (x == 0) x = i; else y = i; } printf( %d %d n , x, y); } else { puts( Yes ); ans.clear(); for (int i = 1; i <= n; i++) if (path[i].size() == 1) ans.push_back(i); printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d %d n , ch, ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 4 ; int a[N] , prefMin[N] , prefMax[N] , suffixMin[N] , suffixMax[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t ; cin >> t ; while(t--){ int n , m , q , sum =0 , s1 = 0 , s2 =0; cin >> n >> m ; string s; cin >> s; s = # + s ; for(int i = 1 ; i<=n ;++i){ if(s[i] == + ) sum++ ; else sum--; a[i] = sum; prefMin[i] = min(prefMin[i-1] ,sum); prefMax[i] = max(prefMax[i-1] , sum); } suffixMin[n+1] = suffixMax[n+1] = 0 ; sum = 0; for(int i = n ; i>=1; --i){ if(s[i] == + ) s1++ , s2++; else s1-- , s2--; s1 = min(s1 , 0); s2 = max(s2 ,0); suffixMin[i] = s1; suffixMax[i] = s2; } while(m--){ int l , r ; cin >> l >> r; int maxi = max(prefMax[l-1] , suffixMax[r+1] + a[l-1]) ; int mini = min(prefMin[l-1] , suffixMin[r+1] + a[l-1]) ; cout<<maxi+abs(mini)+1<< n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; char s[1005][11][11]; int d[1005][1005], vis[1005], fa[1005], t[1005][2]; int n, m, c; vector<int> V[1005]; struct Edge { int a, b, w; } p[500005]; int cmp(Edge x, Edge y) { return x.w < y.w; } int cal(int a, int b) { int ans = 0, i, j; for (i = 0; i < n; i++) for (j = 0; j < m; j++) if (s[a][i][j] != s[b][i][j]) ans++; return ans; } int find(int x) { if (x != fa[x]) return fa[x] = find(fa[x]); return x; } void dfs(int u, int pu) { int x, i; vis[u] = 1; t[c][0] = u, t[c++][1] = pu; for (i = 0; i < V[u].size(); i++) { x = V[u][i]; if (vis[x]) continue; dfs(x, u); } } int main() { int k, w, i, j; scanf( %d%d%d%d , &n, &m, &k, &w); for (i = 1; i <= k; i++) { for (j = 0; j < n; j++) scanf( %s , s[i][j]); } c = 0; for (i = 1; i <= k; i++) for (j = i + 1; j <= k; j++) { int dis = cal(i, j); if (dis * w <= n * m) { p[c].a = i; p[c].b = j; p[c++].w = dis * w; } } sort(p, p + c, cmp); for (i = 1; i <= k; i++) fa[i] = i; int ans = 0; for (i = 0; i < c; i++) { int fx = find(p[i].a); int fy = find(p[i].b); if (fx == fy) continue; fa[fx] = fy; ans += p[i].w; V[p[i].a].push_back(p[i].b); V[p[i].b].push_back(p[i].a); } c = 0; for (i = 1; i <= k; i++) if (!vis[i]) { ans += n * m; dfs(i, 0); } printf( %d n , ans); for (i = 0; i < c; i++) printf( %d %d n , t[i][0], t[i][1]); } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long MOD2 = 998244353; const long long MOD3 = 1812447359; const long long INF = 1ll << 62; const double PI = 2 * asin(1); void yes() { printf( yes n ); } void no() { printf( no n ); } void Yes() { printf( Yes n ); } void No() { printf( No n ); } void YES() { printf( YES n ); } void NO() { printf( NO n ); } struct SegmentTree { vector<int> Tree[21]; void Make() { for (int i = 0; i < 21; i++) { Tree[i].resize(1 << i); } } void Add(int num, int val) { for (int i = 20; i >= 0; i--) { Tree[i][num] += val; num /= 2; } } int Search(int num) { int now = 0, sum = 0; for (int i = 1; i < 21; i++) { now *= 2; if (sum + Tree[i][now] < num) { sum += Tree[i][now]; now++; } } return now; } }; int main() { int N, Q; scanf( %d%d , &N, &Q); SegmentTree T; T.Make(); for (int i = 0; i < N; i++) { int A; scanf( %d , &A); T.Add(A, 1); } for (int i = 0; i < Q; i++) { int K; scanf( %d , &K); if (K > 0) { T.Add(K, 1); } else { int num = T.Search(-1 * K); T.Add(num, -1); } } for (int i = 0; i <= 1e6; i++) { if (T.Tree[20][i] > 0) { cout << i << endl; return 0; } } cout << 0 << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Jun 01 11:35:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_stub.v
// Design : system_vga_overlay_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_overlay,Vivado 2016.4" *)
module system_vga_overlay_0_0(clk, rgb_0, rgb_1, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_0[23:0],rgb_1[23:0],rgb[23:0]" */;
input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_TB_V
`define SKY130_FD_SC_HD__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_TB_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int N = 1e5 + 1; vector<int> co[N]; long long ans = 0; void dfs(int x, int p) { ans += (int)co[x].size() * ((int)co[x].size() - 1) / 2; for (auto y : co[x]) { if (y == p) continue; dfs(y, x); } } int main() { cin.tie(0); cout.tie(0); ios::sync_with_stdio(0); int n; cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; co[a].push_back(b); co[b].push_back(a); } dfs(1, 0); cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 10; const long long MOD = 998244353; long long sq(long long x) { return x * x % MOD; } long long qpow(long long a, long long b) { return b ? sq(qpow(a, b / 2)) * (b & 1 ? a : 1) % MOD : 1; } long long inv(long long x) { return qpow(x, MOD - 2); } struct Matrix { long long v[2][2]; int n, m; Matrix(int n, int m) : n(n), m(m) { memset(v, 0, sizeof(v)); } }; Matrix unit_matrix(int n) { Matrix res(n, n); for (int i = 0; i < n; i++) res.v[i][i] = 1; return res; } Matrix operator+(const Matrix &lhs, const Matrix &rhs) { Matrix res(lhs.n, lhs.m); for (int i = 0; i < lhs.n; i++) for (int j = 0; j < lhs.m; j++) res.v[i][j] = (lhs.v[i][j] + rhs.v[i][j]) % MOD; return res; } Matrix operator*(const Matrix &lhs, const Matrix &rhs) { Matrix res(lhs.n, rhs.m); for (int i = 0; i < lhs.n; i++) { for (int j = 0; j < rhs.m; j++) { for (int k = 0; k < lhs.m; k++) { (res.v[i][j] += lhs.v[i][k] * rhs.v[k][j]) %= MOD; } } } return res; } int N, X[MAX_N], V[MAX_N], P[MAX_N]; bool banned[MAX_N][2][2]; Matrix trans(int x) { Matrix res(2, 2); res.v[0][0] = res.v[1][0] = (1 + MOD - P[x]) % MOD; res.v[0][1] = res.v[1][1] = P[x]; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) if (banned[x][i][j]) res.v[i][j] = 0; return res; } struct SegTree { int l, r, m; SegTree *cl, *cr; Matrix v; SegTree(int l, int r) : l(l), r(r), m((l + r) / 2), cl(nullptr), cr(nullptr), v(2, 2) { if (l != r) { cl = new SegTree(l, m); cr = new SegTree(m + 1, r); v = cl->v * cr->v; } else { v = trans(l); } } Matrix query() { return v; } void modify(int x, Matrix mv) { if (l == r) { v = mv; } else { if (x <= m) cl->modify(x, mv); else cr->modify(x, mv); v = cl->v * cr->v; } } } * segt; struct Event { int x, d0, d1; long long frac_x, frac_y; Event(int x, int d0, int d1, long long frac_x, long long frac_y) : x(x), d0(d0), d1(d1), frac_x(frac_x), frac_y(frac_y) {} }; bool operator<(const Event &lhs, const Event &rhs) { return lhs.frac_x * rhs.frac_y < rhs.frac_x * lhs.frac_y; } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) { scanf( %d%d%d , &X[i], &V[i], &P[i]); P[i] = P[i] * inv(100) % MOD; } segt = new SegTree(1, N); vector<Event> events; for (int i = 2; i <= N; i++) { events.emplace_back(i - 1, 1, 0, X[i] - X[i - 1], V[i - 1] + V[i]); if (V[i - 1] > V[i]) { events.emplace_back(i - 1, 1, 1, X[i] - X[i - 1], V[i - 1] - V[i]); } if (V[i - 1] < V[i]) { events.emplace_back(i - 1, 0, 0, X[i] - X[i - 1], V[i] - V[i - 1]); } } sort(events.begin(), events.end()); long long ans = 0; for (auto e : events) { Matrix t = trans(e.x + 1); for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { if (i != e.d0 || j != e.d1) t.v[i][j] = 0; } } segt->modify(e.x + 1, t); Matrix a(1, 2); a.v[0][0] = 1; Matrix b = segt->query(); Matrix c = a * b; long long p = (c.v[0][0] + c.v[0][1]) % MOD; (ans += p * e.frac_x % MOD * inv(e.frac_y)) %= MOD; banned[e.x + 1][e.d0][e.d1] = true; segt->modify(e.x + 1, trans(e.x + 1)); } printf( %lld n , ans); } |
module vga(input clk, // system clock (100mhz)
input rst,
input clk25mhz, // vga pixel clock (25.13MHz)
// one vmem port is used by the VGA module,
// another is mmaped for the CPU.
//
// Spartan6 vmem is made of 3 x 2048*8 brams
//
// Layout:
// 0-1023 - font rows for 127 "printable" characters
// 1024-XXX - 80x60 chars vmem
input [7:0] vmem_data,
output [12:0] vmem_addr,
// Monochrome VGA pins
output hsync,
output vsync,
output rgb // monochrome output, all three channels 0 or 1
);
reg [23:0] blinkreg;
always @(posedge clk)
if (!rst)
blinkreg <= 0;
else
blinkreg <= blinkreg + 1;
// Pixels are fed via a small FIFO
// vmem fsm:
// CHR0: start fetching next character -> CHRR
// CHRR: fetch a font row -> CHRR1
// CHRR1: push it into fifo or wait, -> CHR0/EOL
// EOL: increment row -> CHR0/VSYNC
// VSYNC: start over again -> CHR0
reg fifo_en;
reg fifo_rd;
reg [7:0] fifo_in;
wire fifo_full;
wire [7:0] fifo_out;
wire fifo_empty;
smallfifo1 fifo1(.rst(rst),
.clk_in(clk),
.fifo_in(fifo_in),
.fifo_en(fifo_en),
.fifo_full(fifo_full),
.clk_out(clk25mhz),
.fifo_out(fifo_out),
.fifo_empty(fifo_empty),
.fifo_rd(fifo_rd));
reg [2:0] fontrow;
reg [12:0] chrpos;
reg [12:0] chrrowpos;
wire [12:0] chrposnxt;
assign chrposnxt = chrpos + 1;
wire chr_eol;
reg [7:0] lineno;
reg [7:0] colno;
assign chr_eol = (colno)>=79;
reg [7:0] ascii;
reg [3:0] chrstate;
wire [12:0] addr_chr0;
wire [12:0] addr_chrr;
assign addr_chr0 = chrpos;
assign addr_chrr = {4'b0,ascii[6:0],fontrow[2:0]};
parameter VMEMSTART = 1024;
parameter VMEMEND = 1024 + 80*60;
parameter S_VSYNC = 0;
parameter S_CHR0 = 1;
parameter S_CHRR = 2;
parameter S_CHRR1 = 3;
parameter S_EOL = 4;
assign vmem_addr = chrstate==S_CHR0?addr_chr0:addr_chrr;
always @(posedge clk)
if (!rst) begin
fifo_en <= 0;
fontrow <= 0;
chrpos <= VMEMSTART;
chrrowpos <= VMEMSTART;
chrstate <= S_VSYNC;
ascii <= 0;
fifo_in <= 0;
lineno <= 0;
colno <= 0;
end else begin // if (!rst)
case(chrstate)
S_VSYNC: begin
fontrow <= 0;
chrpos <= VMEMSTART;
chrrowpos <= VMEMSTART;
chrstate <= S_CHR0;
lineno <= 0;
colno <= 0;
end
S_CHR0: begin
fifo_en <= 0;
//vmem_addr <= addr_chr0;
chrstate <= S_CHRR;
end
S_CHRR: begin
ascii <= vmem_data;
//vmem_addr <= addr_chrr;
chrstate <= S_CHRR1;
end
S_CHRR1: begin
if (~fifo_full) begin
chrpos <= chrposnxt;
colno <= colno + 1;
fifo_in <= (blinkreg[23] & ascii[7])?vmem_data^8'hff:vmem_data; // bit 8 = inv
fifo_en <= 1;
if (chr_eol) begin
chrstate <= S_EOL;
end else begin
chrstate <= S_CHR0;
end
end else begin
chrstate <= S_CHRR1; // keep banging the same row
end
end // case: CHRR1
S_EOL: begin
fifo_en <= 0;
colno <= 0;
// a next font row or a next char row
if (fontrow<7) begin
fontrow <= fontrow + 1;
chrpos <= chrrowpos; // back to the beginning of the same char row
chrstate <= S_CHR0;
end else begin
fontrow <= 0;
lineno <= lineno + 1;
if (lineno >= 59) begin
chrstate <= S_VSYNC;
end else begin
chrrowpos <= chrpos; // start the next row
chrstate <= S_CHR0;
end
end
end
endcase
end
//// bang pixels
reg [9:0] hcounter;
reg [9:0] vcounter;
reg ready;
wire visible;
parameter hlen = 640;
parameter hpulse = 96;
parameter hfp = 16;
parameter hbp = 48;
parameter vlen = 480;
parameter vfp = 10;
parameter vbp = 33;
parameter vpulse = 2;
parameter hlen1 = hlen + hpulse + hfp + hbp;
parameter vlen1 = vlen + vpulse + vfp + vbp;
assign hsync = ~((hcounter > hlen+hfp) & (hcounter < hlen+hfp+hpulse));
assign vsync = ~((vcounter > vlen+vfp) & (vcounter < vlen+vfp+vpulse));
assign visible = (hcounter < hlen)&&(vcounter < vlen);
always @(posedge clk25mhz)
if (!rst || !ready) begin // only start banging when there are some bits queued already
vcounter <= 0;
hcounter <= 0;
end else begin
if (hcounter >= hlen1-1) begin
hcounter <= 0;
if (vcounter >= vlen1-1)
vcounter <= 0;
else
vcounter <= vcounter + 1;
end else hcounter <= hcounter + 1;
end // else: !if(!rst)
// While in a visible area, keep sucking bits from the fifo, hoping it is being well fed
// on the other side.
reg [7:0] fontbits;
reg [7:0] fontnext;
wire nextbit;
assign nextbit = fontbits[7];
assign rgb = visible?nextbit:0;
reg [2:0] bitcount;
reg getnext;
// What a mess!!!
always @(posedge clk25mhz)
if (!rst) begin
bitcount <= 0;
fontbits <= 0;
fontnext <= 0;
ready <= 0;
fifo_rd <= 0;
getnext <= 0;
end else begin
if (!ready) begin
if (fifo_rd) begin
fifo_rd <= 0;
fontbits <= fifo_out;
ready <= 1;
bitcount <= 7;
end else fifo_rd <= 1;
end else
if (visible) begin
if (bitcount < 7) begin
bitcount <= bitcount + 1;
fontbits <= fontbits << 1;
if (fifo_rd) begin
fontnext <= fifo_out;
fifo_rd <= 0;
getnext <= 0;
end else
if ((bitcount > 4) && getnext) begin
fifo_rd <= 1;
end
end else begin // if (bitcount < 7)
fifo_rd <= 0;
bitcount <= 0;
fontbits <= fontnext;
getnext <= 1;
end
end else begin
fifo_rd <= 0; // if (visible)
fontbits <= fontnext;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s1(const pair<string, string> &x) { return x.first.substr(0, 3); } string s2(const pair<string, string> &x) { return x.first.substr(0, 2) + x.second.substr(0, 1); } const int MAXN = 1050; vector<int> g[MAXN], mt; int used[MAXN]; bool dfs(const int &v, const int &now) { if (used[v] == now) return false; used[v] = now; for (auto to : g[v]) { if (mt[to] == -1 || dfs(mt[to], now)) { mt[to] = v; return true; } } return false; } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; vector<pair<string, string>> a(n); for (int i = 0; i < n; ++i) { cin >> a[i].first >> a[i].second; } map<string, int> str_idx; map<string, bool> banned; vector<string> idx_str; for (char c1 = A ; c1 <= Z ; ++c1) { for (char c2 = A ; c2 <= Z ; ++c2) { for (char c3 = A ; c3 <= Z ; ++c3) { string name = ; name += c1; name += c2; name += c3; str_idx[name] = idx_str.size(); idx_str.emplace_back(name); } } } vector<bool> precalced(n); for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (s1(a[i]) == s1(a[j])) { precalced[i] = precalced[j] = true; } } } int cnt = 0; for (int i = 0; i < n; ++i) { if (precalced[i]) { string name = s2(a[i]); if (banned[name]) { cout << NO ; return 0; } ++cnt; banned[name] = true; } } for (int i = 0; i < n; ++i) { if (!precalced[i]) { string name1 = s1(a[i]); string name2 = s2(a[i]); if (!banned[name1]) { g[i].emplace_back(str_idx[name1]); } if (!banned[name2]) { g[i].emplace_back(str_idx[name2]); } } } mt.resize(30 * 30 * 30, -1); for (int i = 0; i < n; ++i) { if (!precalced[i]) dfs(i, i + 1); } for (int i = 0; i < 30 * 30 * 30; ++i) { if (mt[i] != -1) ++cnt; } if (cnt == n) { cout << YES n ; vector<string> ans(n); for (int i = 0; i < n; ++i) { if (precalced[i]) ans[i] = s2(a[i]); } for (int i = 0; i < 30 * 30 * 30; ++i) { if (mt[i] != -1) ans[mt[i]] = idx_str[i]; } for (auto s : ans) cout << s << n ; } else { cout << NO n ; } return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file biossd.v when simulating
// the core, biossd. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module biossd(
clka,
addra,
douta
);
input clka;
input [11 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("biossd.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mapa[35]; int main() { int n, q; scanf( %d %d , &n, &q); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); for (int j = 30; j >= 0; j--) if ((1 << j) & x) { mapa[j]++; break; } } while (q--) { int x; scanf( %d , &x); long long pos = 0, res = 0; for (int i = 30; i >= 0; i--) { long long b = (1 << i); if (b > x) continue; long long aux = min(mapa[i], (long long)x / b); res += aux; x -= b * aux; } if (x > 0) printf( -1 n ); else printf( %lld n , res); } return 0; } |
#include<bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while(t--){ string s; cin >> s; cout << s.size() << endl; } return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[1005], half; pair<int, int> info[1005]; bool cmp(pair<int, int> A, pair<int, int> B) { if (A.first == B.first) return A.second < B.second; else return A.first < B.first; } int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , arr + i); half = arr[i] / 2 + (arr[i] % 2); info[i] = pair<int, int>(half, arr[i]); } sort(info, info + n, cmp); int lvl = k, cnt = 0; for (int i = 0; i < n; i++) { if (info[i].first <= lvl) { lvl = max(k, info[i].second); } else { int num = info[i].second; while (lvl < num) { num = (num / 2) + (num % 2); if (lvl < num) cnt++; } lvl = info[i].second; } } printf( %d , cnt); } |
#include <bits/stdc++.h> using namespace std; const int MAXT = (1 << 18) + 5; int icT[MAXT], dcT[MAXT]; const int MAXN = 100010; int a[MAXN], idxofa[MAXN], b[MAXN]; int n; priority_queue<pair<int, int> > dc, ic; int main() { scanf( %d , &n); for (int i = 1; i <= (int)(n); i++) { scanf( %d , &a[i]); idxofa[a[i]] = i; } for (int i = 0; i < (int)(MAXT); i++) icT[i] = dcT[i] = 1000000000; int NN = (1 << 17) - 1; for (int i = 1; i <= (int)(n); i++) { scanf( %d , &b[i]); if (i > idxofa[b[i]]) { dc.push(make_pair(-(i - idxofa[b[i]]), b[i])); dcT[NN + b[i]] = abs(i - idxofa[b[i]]); for (int node = (NN + b[i]) / 2; node; node >>= 1) dcT[node] = min(dcT[2 * node], dcT[2 * node + 1]); } else { ic.push(make_pair(-(i - 1), b[i])); icT[NN + b[i]] = abs(i - idxofa[b[i]]); for (int node = (NN + b[i]) / 2; node; node >>= 1) icT[node] = min(icT[2 * node], icT[2 * node + 1]); } } for (int t = 0; t < n; t++) { int dcres = dcT[1] - t; int icres = icT[1] + t; printf( %d n , min(dcres, icres)); while (dc.size() > 0 && -dc.top().first == t) { pair<int, int> qt = dc.top(); dc.pop(); ic.push(make_pair(-t - (idxofa[qt.second] - 1), qt.second)); dcT[NN + qt.second] = 1000000000; icT[NN + qt.second] = -t; for (int node = (NN + qt.second) / 2; node; node >>= 1) icT[node] = min(icT[2 * node], icT[2 * node + 1]); for (int node = (NN + qt.second) / 2; node; node >>= 1) dcT[node] = min(dcT[2 * node], dcT[2 * node + 1]); } while (ic.size() > 0 && -ic.top().first == t) { pair<int, int> qt = ic.top(); ic.pop(); dc.push(make_pair(-t - (n - idxofa[qt.second]) - 1, qt.second)); icT[NN + qt.second] = 1000000000; dcT[NN + qt.second] = t + 1 + n - idxofa[qt.second]; for (int node = (NN + qt.second) / 2; node; node >>= 1) icT[node] = min(icT[2 * node], icT[2 * node + 1]); for (int node = (NN + qt.second) / 2; node; node >>= 1) dcT[node] = min(dcT[2 * node], dcT[2 * node + 1]); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_2_V
`define SKY130_FD_SC_HD__O2111AI_2_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111ai_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int p, c = 0; cin >> p; long long int x = p; long long int n = std::numeric_limits<int>::digits - 1; std::string s; s.reserve(n + 1); do s.push_back(((x >> n) & 1) + 0 ); while (--n > -1); for (auto x : s) if (x == 1 ) c++; cout << c; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 100010, LOG = 20; int n, m, k, u, v, x, y, t, a, b, ans; bool dead[MAXN]; string A; vector<vector<int>> out; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> A; n = A.size(); while (1) { int i = 0, j = n - 1; vector<int> v1, v2; while (i < j) { while (i < j && (A[i] == ) || dead[i])) i++; while (i < j && (A[j] == ( || dead[j])) j--; if (i >= j || A[i] == ) || A[j] == ( ) break; v1.push_back(i++); v2.push_back(j--); } if (v1.empty()) break; reverse(v2.begin(), v2.end()); for (int i : v2) v1.push_back(i); for (int i : v1) dead[i] = 1; out.push_back(v1); } cout << out.size() << n ; for (auto vec : out) { cout << vec.size() << n ; for (int i : vec) cout << i + 1 << ; cout << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INV_BEHAVIORAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int inf = 2e8; struct st { int l, r; }; bool cmp(st a, st b) { return a.l < b.l; } int main() { bool a1 = false, b1 = false; int i; st v, q, w; vector<st> v1, v2; string s, a = AB , b = BA ; cin >> s; for (i = 0; i < s.size() - 1; i++) { if (s.substr(i, 2) == a) { v.l = i; v.r = i + 1; v1.push_back(v); } if (s.substr(i, 2) == b) { v.l = i; v.r = i + 1; v2.push_back(v); } } sort(v1.begin(), v1.end(), cmp); sort(v2.begin(), v2.end(), cmp); if (v1.size() == 0 || v2.size() == 0) { cout << NO ; return 0; } q = v1[0]; w = v2[v2.size() - 1]; if (q.l != w.l && q.l != w.r && q.r != w.l && q.r != w.r) { cout << YES ; return 0; } q = v2[0]; w = v1[v1.size() - 1]; if (q.l != w.l && q.l != w.r && q.r != w.l && q.r != w.r) { cout << YES ; return 0; } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, a, b; scanf( %d%d , &n, &k); printf( %d , n); for (int i = n - 1; i > k; --i) printf( %d , i); a = 1, b = k; while (a < b) printf( %d %d , a++, b--); if (a == b) printf( %d , a); puts( ); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, m, same; string s; int main() { cin >> n >> m >> s; long long ans = 1LL * n * (m - 1); for (int i = 1; i < n; i++) { if (s[i] == s[i - 2]) { same++; } else { same = 0; } if (s[i] != s[i - 1]) { ans += 1LL * n * (m - 1) - same - 1; } } cout << ans << endl; return 0; } |
module test();
reg a, b;
wire a1, a2, a3, a4, a5, a6, a7;
assign (supply1, supply0) a1 = a;
rtran t1(a1, a2);
rtran t2(a2, a3);
rtran t3(a3, a4);
rtran t4(a4, a5);
rtran t5(a5, a6);
rtran t6(a6, a7);
wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15;
wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25;
wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35;
wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45;
wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55;
assign (supply1, supply0) a11 = a, b11 = b;
assign (supply1, strong0) a12 = a, b12 = b;
assign (supply1, pull0) a13 = a, b13 = b;
assign (supply1, weak0) a14 = a, b14 = b;
assign (supply1, highz0) a15 = a, b15 = b;
assign (strong1, supply0) a21 = a, b21 = b;
assign (strong1, strong0) a22 = a, b22 = b;
assign (strong1, pull0) a23 = a, b23 = b;
assign (strong1, weak0) a24 = a, b24 = b;
assign (strong1, highz0) a25 = a, b25 = b;
assign ( pull1, supply0) a31 = a, b31 = b;
assign ( pull1, strong0) a32 = a, b32 = b;
assign ( pull1, pull0) a33 = a, b33 = b;
assign ( pull1, weak0) a34 = a, b34 = b;
assign ( pull1, highz0) a35 = a, b35 = b;
assign ( weak1, supply0) a41 = a, b41 = b;
assign ( weak1, strong0) a42 = a, b42 = b;
assign ( weak1, pull0) a43 = a, b43 = b;
assign ( weak1, weak0) a44 = a, b44 = b;
assign ( weak1, highz0) a45 = a, b45 = b;
assign ( highz1, supply0) a51 = a, b51 = b;
assign ( highz1, strong0) a52 = a, b52 = b;
assign ( highz1, pull0) a53 = a, b53 = b;
assign ( highz1, weak0) a54 = a, b54 = b;
rtran t11(a11, b11);
rtran t12(a12, b12);
rtran t13(a13, b13);
rtran t14(a14, b14);
rtran t15(a15, b15);
rtran t21(a21, b21);
rtran t22(a22, b22);
rtran t23(a23, b23);
rtran t24(a24, b24);
rtran t25(a25, b25);
rtran t31(a31, b31);
rtran t32(a32, b32);
rtran t33(a33, b33);
rtran t34(a34, b34);
rtran t35(a35, b35);
rtran t41(a41, b41);
rtran t42(a42, b42);
rtran t43(a43, b43);
rtran t44(a44, b44);
rtran t45(a45, b45);
rtran t51(a51, b51);
rtran t52(a52, b52);
rtran t53(a53, b53);
rtran t54(a54, b54);
rtran t55(a55, b55);
task display_strengths;
input ta, tb;
begin
a = ta;
b = tb;
#1;
$display("a = %b b = %b", a, b);
$display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7);
$display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15);
$display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25);
$display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35);
$display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45);
$display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55);
end
endtask
initial begin
display_strengths(1'bz, 1'bz);
display_strengths(1'bx, 1'bz);
display_strengths(1'b0, 1'bz);
display_strengths(1'b1, 1'bz);
display_strengths(1'bz, 1'bx);
display_strengths(1'bx, 1'bx);
display_strengths(1'b0, 1'bx);
display_strengths(1'b1, 1'bx);
display_strengths(1'bz, 1'b0);
display_strengths(1'bx, 1'b0);
display_strengths(1'b0, 1'b0);
display_strengths(1'b1, 1'b0);
display_strengths(1'bz, 1'b1);
display_strengths(1'bx, 1'b1);
display_strengths(1'b0, 1'b1);
display_strengths(1'b1, 1'b1);
end
endmodule
|
#include <bits/stdc++.h> using LL = long long; const LL Inf = (LL)1e18; const int N = 5000 + 5; int s, e, n; LL x[N], a[N], b[N], c[N], d[N]; LL dp[2][N]; inline LL lo(int p) { return d[p] - x[p]; } inline LL ro(int p) { return x[p] + c[p]; } inline LL li(int p) { return b[p] - x[p]; } inline LL ri(int p) { return x[p] + a[p]; } inline void _min(LL &a, LL b) { if (a > b) a = b; } LL work() { if (s > e) { for (int i = 1; i <= n; ++i) { x[i] = -x[i]; std::swap(a[i], b[i]); std::swap(c[i], d[i]); } for (int i = 1; i < n + 1 - i; ++i) { std::swap(x[i], x[n + 1 - i]); std::swap(a[i], a[n + 1 - i]); std::swap(b[i], b[n + 1 - i]); std::swap(c[i], c[n + 1 - i]); std::swap(d[i], d[n + 1 - i]); } s = n + 1 - s; e = n + 1 - e; } for (int i = 0; i < 2; ++i) { for (int j = 0; j < N; ++j) { dp[i][j] = Inf; } } int cur = 0, nex = 1; dp[cur][1] = li(1) + lo(1); for (int i = 2; i <= n; ++i) { for (int left = 1; left <= i - 1; ++left) { if (dp[cur][left] == Inf) continue; for (int q = 0; q < 2; ++q) { for (int w = 0; w < 2; ++w) { if (i == s && w == 0) continue; if (i == e && q == 1) continue; if (s < i && i < e) { if (left == 1 && q == 0) continue; } LL cost = 0; cost += q == 0 ? ro(i) : lo(i); cost += w == 0 ? ri(i) : li(i); int n_left = left; if (q == w) { if (q == 0) n_left--; else n_left++; } _min(dp[nex][n_left], dp[cur][left] + cost); } } } std::swap(cur, nex); std::fill(dp[nex], dp[nex] + N, Inf); } LL ret = dp[cur][0]; if (s < e) { ret -= li(s) + ro(e); } else { ret -= ri(s) + lo(e); } return ret; } int main() { std::ios::sync_with_stdio(false); std::cin >> n >> s >> e; for (int i = 1; i <= n; ++i) std::cin >> x[i]; for (int i = 1; i <= n; ++i) std::cin >> a[i]; for (int i = 1; i <= n; ++i) std::cin >> b[i]; for (int i = 1; i <= n; ++i) std::cin >> c[i]; for (int i = 1; i <= n; ++i) std::cin >> d[i]; std::cout << work() << std::endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<string> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; } int a[26] = {0}; for (auto s : v) { for (auto i : s) { a[i - a ]++; } } int f = 0; for (int i = 0; i < 26; i++) { if (a[i] % n) { f = 1; break; } } if (f) { cout << NO << endl; } else { cout << YES << endl; } } } |
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Log:
5/18/2013: Implemented new naming Scheme
*/
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int
);
parameter MEM_SEL_0 = 0;
parameter MEM_OFFSET_0 = 32'h00000000;
parameter MEM_SIZE_0 = 32'h800000;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from mem slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 1'b0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 4'b0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 32'h0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 32'h0;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: homework.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module homework (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/homework.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/homework.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/homework.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL homework.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL homework.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL homework.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL homework.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL homework_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL homework_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( O3 , omit-frame-pointer , inline ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) using namespace std; const long long mod = 998244353; mt19937 rng((int)chrono::steady_clock::now().time_since_epoch().count()); const int mxN = 5010; int main(int argc, char *argv[]) { ios_base::sync_with_stdio(false); cin.tie(nullptr); srand(time(NULL)); cout << fixed << setprecision(9); int t = 1; while (t--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; vector<int> e; for (int i = 0; i < n; i++) { if (!e.empty() && e.back() % 2 == a[i] % 2) e.pop_back(); else e.push_back(a[i]); } cout << (e.size() <= 1 ? YES : NO ) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int ms = 2005, me = 4005; int adj[ms], to[me], ant[me], z = 0, idx[ms], path[ms], bridge[me], ind, vis[ms]; int s[ms], l[ms], ans; bool dfs(int v, int end) { if (vis[v]) return false; else if (v == end) return path[v] = true; vis[v] = 1; for (int e = adj[v]; e > -1; e = ant[e]) { path[v] = path[v] || dfs(to[e], end); } return path[v]; } int dfs2(int v, int par = -1) { int low = idx[v] = ind++; for (int i = adj[v]; i > -1; i = ant[i]) { if (idx[to[i]] == -1) { int temp = dfs2(to[i], v); if (temp > idx[v] && path[to[i]] && path[v]) ans++; low = min(low, temp); } else if (to[i] != par) low = min(low, idx[to[i]]); } return low; } void add(int a, int b) { to[z] = b; ant[z] = adj[a]; adj[a] = z++; swap(a, b); to[z] = b; ant[z] = adj[a]; adj[a] = z++; } int main() { cin.tie(0); cin.sync_with_stdio(false); int n, m; cin >> n >> m; z = 0; memset(adj, -1, sizeof adj); for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; add(a, b); } int k; cin >> k; for (int i = 0; i < k; i++) { cin >> s[i] >> l[i]; } for (int i = 0; i < k; i++) { ans = 0; memset(idx, -1, sizeof idx); ind = 0; memset(bridge, 0, sizeof bridge); memset(vis, 0, sizeof vis); memset(path, 0, sizeof path); dfs(s[i], l[i]); dfs2(s[i]); cout << ans << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_16_V
`define SKY130_FD_SC_MS__BUFINV_16_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_16_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; int n, ans; double a[2000]; struct Line { double x, y, vx, vy; void read() { double t1, t2; scanf( %lf%lf%lf%lf%lf%lf , &t1, &x, &y, &t2, &vx, &vy); vx -= x; vy -= y; vx /= t2 - t1; vy /= t2 - t1; x -= t1 * vx; y -= t1 * vy; } } line[2000]; struct point { double x, y; point() {} point(double x, double y) : x(x), y(y) {} double det(point res) { return x * res.y - y * res.x; } bool operator<(const point& rhs) const { if (abs(x * rhs.y - y * rhs.x) < eps) { if (abs(x - rhs.x) < eps) return y < rhs.y; return x < rhs.x; } else return x * rhs.y - y * rhs.x < 0; } } b[2000]; int main() { scanf( %d , &n); if (n) ans = 1; for (int i = 1; i <= n; i++) line[i].read(); for (int id = 1; id <= n; id++) { int tot = 0; for (int j = 1; j <= n; j++) if (id != j) { double vx = line[j].vx - line[id].vx, vy = line[j].vy - line[id].vy; double t = fabs(vx) > eps ? (line[j].x - line[id].x) / vx : fabs(vy) > eps ? (line[j].y - line[id].y) / vy : 0; if (fabs(line[j].x - line[id].x - t * vx) <= eps && fabs(line[j].y - line[id].y - t * vy) <= eps) a[++tot] = t, b[tot] = point(vx, vy); } sort(a + 1, a + 1 + tot); int cnt = 0; for (int i = 1; i <= tot; i++) { if (i == 1 || a[i] - a[i - 1] >= eps) cnt = 1; else cnt++; ans = max(ans, cnt + 1); } sort(b + 1, b + tot + 1); cnt = 0; for (int i = 1; i <= tot; i++) { if (i == 1 || fabs(b[i].det(b[i - 1])) > eps) cnt = 1; else if (fabs(b[i].x - b[i - 1].x) > eps || fabs(b[i].y - b[i - 1].y) > eps) cnt++; ans = max(ans, cnt + 1); } } cout << ans << endl; } |
//#############################################################################
//# Purpose: DMA sequencer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see below) #
//#############################################################################
`include "edma_regmap.vh"
module edma_ctrl (/*AUTOARG*/
// Outputs
fetch_access, fetch_packet, dma_state, update, update2d,
master_active,
// Inputs
clk, nreset, dma_en, chainmode, manualmode, mastermode, count,
curr_descr, next_descr, reg_wait_in, access_in, wait_in
);
parameter AW = 32; // address width
parameter PW = 2*AW+40; // fetch packet width
parameter ID = 4'b0000; // group id for DMA regs [10:8]
// clk, reset, config
input clk; // main clock
input nreset; // async active low reset
input dma_en; // dma is enabled
input chainmode; // chainmode configuration
input manualmode; // descriptor fetch
input mastermode; // dma configured in mastermode
input [31:0] count; // current transfer count
input [15:0] curr_descr;
input [15:0] next_descr;
// descriptor fetch interface
output fetch_access; // fetch descriptor
output [PW-1:0] fetch_packet; // fetch packet
input reg_wait_in; // register access wait
// slave access
input access_in; // slave access
input wait_in; // master/slave transfer stall
// status
output [3:0] dma_state; // state of dma
output update; // update registers
output update2d; // dma currently in outerloop (2D)
output master_active; // master is active
//###########################################################################
//# BODY
//###########################################################################
reg [3:0] dma_state;
wire [15:0] descr;
wire [15:0] fetch_addr;
wire [AW-1:0] srcaddr_out;
wire [4:0] reg_addr;
wire dma_error;
wire incount_zero;
wire outcount_zero;
//###########################################
//# STATE MACHINE
//###########################################
`define DMA_IDLE 4'b0000 // dma idle
`define DMA_FETCH0 4'b0001 // fetch cfg, next-ptr, stride_in
`define DMA_FETCH1 4'b0010 // fetch cnt_out,cnt_in, stride_out
`define DMA_FETCH2 4'b0011 // fetch srcaddr, dstaddr
`define DMA_FETCH3 4'b0100 // fetch srcaddr64, dstaddr64
`define DMA_FETCH4 4'b0101 // stall (no bypass)
`define DMA_INNER 4'b0110 // dma inner loop
`define DMA_OUTER 4'b0111 // dma outer loop
`define DMA_DONE 4'b1000 // dma outer loop
`define DMA_ERROR 4'b1001 // dma error
always @ (posedge clk or negedge nreset)
if(!nreset)
dma_state[3:0] <= `DMA_IDLE;
else if(dma_error)
dma_state[3:0] <= `DMA_ERROR;
else
case(dma_state[3:0])
`DMA_IDLE:
casez({dma_en,manualmode})
2'b0? : dma_state[3:0] <= `DMA_IDLE;
2'b11 : dma_state[3:0] <= `DMA_INNER;
2'b10 : dma_state[3:0] <= `DMA_FETCH0;
endcase // casez (dma_reg_write_config)
`DMA_FETCH0:
dma_state[3:0] <= reg_wait_in ? `DMA_FETCH0 : `DMA_FETCH1;
`DMA_FETCH1:
dma_state[3:0] <= reg_wait_in ? `DMA_FETCH1 : `DMA_FETCH2;
`DMA_FETCH2:
dma_state[3:0] <= reg_wait_in ? `DMA_FETCH2 : `DMA_FETCH3;
`DMA_FETCH3:
dma_state[3:0] <= reg_wait_in ? `DMA_FETCH3 : `DMA_FETCH3;
`DMA_FETCH4:
dma_state[3:0] <= reg_wait_in ? `DMA_FETCH4 : `DMA_INNER;
`DMA_INNER:
casez({update,incount_zero,outcount_zero})
3'b0?? : dma_state[3:0] <= `DMA_INNER;
3'b10? : dma_state[3:0] <= `DMA_INNER;
3'b110 : dma_state[3:0] <= `DMA_OUTER;
3'b111 : dma_state[3:0] <= `DMA_DONE;
endcase
`DMA_OUTER:
dma_state[3:0] <= update ? `DMA_INNER : `DMA_OUTER;
`DMA_DONE:
casez({chainmode,manualmode})
2'b0? : dma_state[3:0] <= `DMA_DONE;
2'b11 : dma_state[3:0] <= `DMA_IDLE;
2'b10 : dma_state[3:0] <= `DMA_FETCH0;
endcase
`DMA_ERROR:
dma_state[3:0] <= dma_en ? `DMA_ERROR: `DMA_IDLE;
endcase
//###########################################
//# ACTIVE SIGNALS
//###########################################
assign dma_error = 1'b0; //TODO: define error conditions
assign update = ~wait_in & (master_active | access_in);
assign update2d = update & (dma_state[3:0]==`DMA_OUTER);
assign master_active = mastermode &
((dma_state[3:0]==`DMA_INNER) |
(dma_state[3:0]==`DMA_OUTER));
assign incount_zero = ~(|count[15:0]);
assign outcount_zero = ~(|count[31:16]);
//###########################################
//# DESCRIPTOR FETCH ENGINE
//###########################################
assign fetch_access = (dma_state[3:0]==`DMA_FETCH0) |
(dma_state[3:0]==`DMA_FETCH1) |
(dma_state[3:0]==`DMA_FETCH2);
// fetch address
assign descr[15:0] = (dma_state[3:0]==`DMA_FETCH0) ? next_descr[15:0] :
curr_descr[15:0];
oh_mux3 #(.DW(16))
mux3d (.out (fetch_addr[15:0]),
.in0 (descr[15:0]), .sel0 (dma_state[3:0]==`DMA_FETCH0),
.in1 (descr[15:0]+16'd8), .sel1 (dma_state[3:0]==`DMA_FETCH1),
.in2 (descr[15:0]+16'd16), .sel2 (dma_state[3:0]==`DMA_FETCH2)
);
//address of first reg to fetch
oh_mux3 #(.DW(5))
mux3s (.out (reg_addr[4:0]),
.in0 (`EDMA_CONFIG), .sel0 (dma_state[3:0]==`DMA_FETCH0),
.in1 (`EDMA_COUNT), .sel1 (dma_state[3:0]==`DMA_FETCH1),
.in2 (`EDMA_SRCADDR), .sel2 (dma_state[3:0]==`DMA_FETCH2)
);
// constructing the address to return fetch to
assign srcaddr_out[AW-1:0] = {{(AW-11){1'b0}}, //31-11
ID, //10-7
reg_addr[4:0], //6-2
2'b0}; //1-0
// constructing fetch packet
emesh2packet #(.AW(AW),
.PW(PW))
e2p (//outputs
.packet_out (fetch_packet[PW-1:0]),
//inputs
.write_out (1'b0),
.datamode_out (2'b11),
.ctrlmode_out (5'b0),
.dstaddr_out ({{(AW-16){1'b0}},fetch_addr[15:0]}),
.data_out ({(AW){1'b0}}),
.srcaddr_out (srcaddr_out[AW-1:0]));
endmodule // edma_ctrl
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../common/hdl" "../../emesh/hdl")
// End:
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////
|
// megafunction wizard: %ALTERA_FP_FUNCTIONS v15.1%
// GENERATION: XML
// xlr8_float_add1.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module xlr8_float_add1 (
input wire clk, // clk.clk
input wire areset, // areset.reset
input wire [0:0] en, // en.en
input wire [31:0] a, // a.a
input wire [31:0] b, // b.b
output wire [31:0] q // q.q
);
xlr8_float_add1_0002 xlr8_float_add1_inst (
.clk (clk), // clk.clk
.areset (areset), // areset.reset
.en (en), // en.en
.a (a), // a.a
.b (b), // b.b
.q (q) // q.q
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_fp_functions" version="15.1" >
// Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
// Retrieval info: <generic name="ARITH_function" value="ADD" />
// Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
// Retrieval info: <generic name="ALL_function" value="ADD" />
// Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
// Retrieval info: <generic name="TRIG_function" value="SIN" />
// Retrieval info: <generic name="COMPARE_function" value="MIN" />
// Retrieval info: <generic name="ROOTS_function" value="SQRT" />
// Retrieval info: <generic name="fp_format" value="single" />
// Retrieval info: <generic name="fp_exp" value="8" />
// Retrieval info: <generic name="fp_man" value="23" />
// Retrieval info: <generic name="exponent_width" value="23" />
// Retrieval info: <generic name="frequency_target" value="200" />
// Retrieval info: <generic name="latency_target" value="1" />
// Retrieval info: <generic name="performance_goal" value="latency" />
// Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
// Retrieval info: <generic name="faithful_rounding" value="false" />
// Retrieval info: <generic name="gen_enable" value="true" />
// Retrieval info: <generic name="divide_type" value="0" />
// Retrieval info: <generic name="select_signal_enable" value="false" />
// Retrieval info: <generic name="scale_by_pi" value="false" />
// Retrieval info: <generic name="number_of_inputs" value="2" />
// Retrieval info: <generic name="trig_no_range_reduction" value="false" />
// Retrieval info: <generic name="report_resources_to_xml" value="false" />
// Retrieval info: <generic name="fxpt_width" value="32" />
// Retrieval info: <generic name="fxpt_fraction" value="0" />
// Retrieval info: <generic name="fxpt_sign" value="1" />
// Retrieval info: <generic name="fp_out_format" value="single" />
// Retrieval info: <generic name="fp_out_exp" value="8" />
// Retrieval info: <generic name="fp_out_man" value="23" />
// Retrieval info: <generic name="fp_in_format" value="single" />
// Retrieval info: <generic name="fp_in_exp" value="8" />
// Retrieval info: <generic name="fp_in_man" value="23" />
// Retrieval info: <generic name="enable_hard_fp" value="true" />
// Retrieval info: <generic name="manual_dsp_planning" value="true" />
// Retrieval info: <generic name="forceRegisters" value="1111" />
// Retrieval info: <generic name="selected_device_family" value="MAX 10" />
// Retrieval info: <generic name="selected_device_speedgrade" value="6" />
// Retrieval info: </instance>
// IPFS_FILES : xlr8_float_add1.vo
// RELATED_FILES: xlr8_float_add1.v, dspba_library_package.vhd, dspba_library.vhd, xlr8_float_add1_0002.vhd
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfxtp (
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_dst_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_dst_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_dst_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_dst_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:10:13 04/25/2015
// Design Name:
// Module Name: HallwayTop
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HallwayTop(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
if(~(CurrentY < 440)) begin
mColor[7:0] <= wall;
end
else if(CurrentX > 600)begin
mColor[7:0] <= wall;
end
else if(((CurrentY < 40) && (CurrentX < 260)) || ((CurrentY < 40) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const long long MAX = 8e18; const long long MIN = -8e18; int n; long long x[N]; long long y[N]; long long z[N]; vector<long long> ansX; vector<long long> ansY; vector<long long> ansZ; inline long long llabs(const long long &a, const long long &b) { long long res = a - b; return (res >= 0 ? res : -res); } inline long long calDist(long long z0, pair<long long, long long> &xy) { long long minA, maxA, minB, maxB, h, dist2, a, b; int i, j, k; minA = minB = MAX; maxA = maxB = MIN; for (i = 0; i < n; i++) { h = llabs(z0, z[i]); minA = min(minA, x[i] + y[i] - h); maxA = max(maxA, x[i] + y[i] + h); minB = min(minB, x[i] - y[i] - h); maxB = max(maxB, x[i] - y[i] + h); } dist2 = max(maxA - minA, maxB - minB); a = (maxA + minA) / 2; b = (maxB + minB) / 2; xy.first = (a + b) / 2; xy.second = (a - b) / 2; return dist2; } inline void solve() { int i; long long bestZ, bestY, bestX, bestDist, curDist, curY, curX, initX, initY, curZ, d; bestDist = MAX; pair<long long, long long> xy; bestZ = 0; bestDist = calDist(bestZ, xy); d = 1e18; while (d >= 1) { curZ = bestZ + d; curDist = calDist(curZ, xy); if (curDist < bestDist) { bestZ = curZ; bestDist = curDist; continue; } curZ = bestZ - d; curDist = calDist(curZ, xy); if (curDist < bestDist) { bestZ = curZ; bestDist = curDist; continue; } d /= 2; } calDist(bestZ, xy); initX = xy.first; initY = xy.second; bestDist = MAX; for (curX = initX - 1; curX <= initX + 1; curX++) { for (curY = initY - 1; curY <= initY + 1; curY++) { curDist = 0; for (i = 0; i < n; i++) { curDist = max(curDist, llabs(x[i] - curX) + llabs(y[i] - curY) + llabs(bestZ - z[i])); } if (curDist < bestDist) { bestDist = curDist; bestX = curX; bestY = curY; } } } ansX.push_back(bestX); ansY.push_back(bestY); ansZ.push_back(bestZ); } int main() { int t, i, k; scanf( %d , &t); for (k = 0; k < t; k++) { scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %l ld %l ld %l ld , &x[i], &y[i], &z[i]); } solve(); } for (i = 0; i < t; i++) { printf( %l ld %l ld %l ld n , ansX[i], ansY[i], ansZ[i]); } } |
module sevensegment (
clk,
reset_,
segment_,
digit_enable_
);
input clk; // 32 Mhz clock
input reset_; // Active low reset
output [6:0] segment_; // Segments of the display (active low)
output [3:0] digit_enable_; // Active low digit enable (which digit are we driving?)
reg [19:0] increment_ctr;
reg [3:0] display_0;
reg [3:0] display_1;
reg [3:0] display_2;
reg [3:0] display_3;
wire [6:0] display_0_coded;
wire [6:0] display_1_coded;
wire [6:0] display_2_coded;
wire [6:0] display_3_coded;
// Display driver circuit used to multiplex the four, seven-segment display
// values onto the single segment_ bus.
displaydriver driver (
.clk(clk),
.reset_(reset_),
.digit_0(display_0_coded),
.digit_1(display_1_coded),
.digit_2(display_2_coded),
.digit_3(display_3_coded),
.segment_(segment_),
.digit_enable_(digit_enable_)
);
// Instantiate four display coders; each coder converts a binary coded decimal
// value (that is, four bits representing the decimal values 0..9) to a seven
// bit vector indicating which LEDs in the display should be energized in
// order to display the desired value
bcdcoder display_0_coder (
.segment(display_0_coded), // output: segments on display to energize
.bcd(display_0) // input: binary coded value from counter
);
bcdcoder display_1_coder (
.segment(display_1_coded),
.bcd(display_1)
);
bcdcoder display_2_coder (
.segment(display_2_coded),
.bcd(display_2)
);
bcdcoder display_3_coder (
.segment(display_3_coded),
.bcd(display_3)
);
// Increment signals for each of the four displays
assign display_0_inc = &increment_ctr;
assign display_1_inc = display_0_inc && display_0 == 4'd9;
assign display_2_inc = display_1_inc && display_1 == 4'd9;
assign display_3_inc = display_2_inc && display_2 == 4'd9;
// Counter used to control the speed at which the displayed value increments.
// 20 bit counter rolls over approx 30 times per second clocked at 32MHz.
always@ (posedge clk or negedge reset_)
if (!reset_)
increment_ctr <= 20'd0;
else
increment_ctr <= increment_ctr + 20'd1;
// Binary coded decimal counters. Each represents the value displayed in a
// single, 7-segment display on the hardware (a number between 0 and 9).
always@ (posedge clk or negedge reset_)
if (!reset_)
display_0 <= 4'd0;
else if (display_0_inc && display_0 == 4'd9)
display_0 <= 4'd0;
else if (display_0_inc)
display_0 <= display_0 + 4'd1;
always@ (posedge clk or negedge reset_)
if (!reset_)
display_1 <= 4'd0;
else if (display_1_inc && display_1 == 4'd9)
display_1 <= 4'd0;
else if (display_1_inc)
display_1 <= display_1 + 4'd1;
always@ (posedge clk or negedge reset_)
if (!reset_)
display_2 <= 4'd0;
else if (display_2_inc && display_2 == 4'd9)
display_2 <= 4'd0;
else if (display_2_inc)
display_2 <= display_2 + 4'd1;
always@ (posedge clk or negedge reset_)
if (!reset_)
display_3 <= 4'd0;
else if (display_3_inc && display_3 == 4'd9)
display_3 <= 4'd0;
else if (display_3_inc)
display_3 <= display_3 + 4'd1;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[300001]; bool mark[300001]; bool vis[300001]; int road_count = 0; int main(void) { int n, m; cin >> n >> m; int a, b; for (int i = 0; i < m; i++) { cin >> a >> b; a--; b--; g[a].push_back(b); g[b].push_back(a); } memset(mark, 0, sizeof(bool) * n); queue<int> q; for (int i = 0; i < n; i++) q.push(i); while (!q.empty()) { int x = q.front(); q.pop(); int count = 0; for (int i = 0; i < g[x].size(); i++) { if (mark[x] == mark[g[x][i]]) count++; } if (count > 1) { mark[x] = !mark[x]; for (int i = 0; i < g[x].size(); i++) { if (mark[x] == mark[g[x][i]]) q.push(g[x][i]); } } } for (int i = 0; i < n; i++) { if (mark[i]) cout << 1 ; else cout << 0 ; } } |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:54:40 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R1_P4 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire intadd_27_CI, intadd_27_n3, intadd_27_n2, intadd_27_n1, n2, n3, n4,
n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18;
CMPR32X2TS intadd_27_U4 ( .A(in2[1]), .B(in1[1]), .C(intadd_27_CI), .CO(
intadd_27_n3), .S(res[1]) );
CMPR32X2TS intadd_27_U3 ( .A(in2[2]), .B(in1[2]), .C(intadd_27_n3), .CO(
intadd_27_n2), .S(res[2]) );
CMPR32X2TS intadd_27_U2 ( .A(in2[3]), .B(in1[3]), .C(intadd_27_n2), .CO(
intadd_27_n1), .S(res[3]) );
AO21XLTS U2 ( .A0(n8), .A1(n3), .B0(n9), .Y(n4) );
CLKAND2X2TS U3 ( .A(in2[0]), .B(in1[0]), .Y(intadd_27_CI) );
AOI2BB2XLTS U4 ( .B0(in2[5]), .B1(n5), .A0N(n5), .A1N(in2[5]), .Y(n6) );
OAI2BB2XLTS U5 ( .B0(n17), .B1(n16), .A0N(in1[6]), .A1N(in2[6]), .Y(n18) );
OAI32X2TS U6 ( .A0(n14), .A1(n9), .A2(n8), .B0(n13), .B1(n14), .Y(n10) );
AOI22X2TS U7 ( .A0(in2[4]), .A1(in1[4]), .B0(in2[3]), .B1(in1[3]), .Y(n13)
);
OAI211XLTS U8 ( .A0(in1[2]), .A1(in2[2]), .B0(in2[1]), .C0(in1[1]), .Y(n3)
);
AOI2BB1XLTS U9 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_27_CI), .Y(res[0])
);
NOR2X2TS U10 ( .A(in2[4]), .B(in1[4]), .Y(n14) );
AOI21X1TS U11 ( .A0(in1[4]), .A1(in2[4]), .B0(n14), .Y(n2) );
XOR2XLTS U12 ( .A(n2), .B(intadd_27_n1), .Y(res[4]) );
NAND2X1TS U13 ( .A(in1[2]), .B(in2[2]), .Y(n8) );
NOR2X1TS U14 ( .A(in2[3]), .B(in1[3]), .Y(n9) );
AOI21X1TS U15 ( .A0(n4), .A1(n13), .B0(n14), .Y(n7) );
INVX2TS U16 ( .A(in1[5]), .Y(n5) );
XNOR2X1TS U17 ( .A(n7), .B(n6), .Y(res[5]) );
NOR2X1TS U18 ( .A(in1[6]), .B(in2[6]), .Y(n17) );
AOI21X1TS U19 ( .A0(in1[6]), .A1(in2[6]), .B0(n17), .Y(n12) );
AOI222X1TS U20 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[5]), .B1(n10), .C0(in1[5]), .C1(n10), .Y(n11) );
XNOR2X1TS U21 ( .A(n12), .B(n11), .Y(res[6]) );
NOR2X1TS U22 ( .A(n14), .B(n13), .Y(n15) );
AOI222X1TS U23 ( .A0(in1[5]), .A1(n15), .B0(in1[5]), .B1(in2[5]), .C0(n15),
.C1(in2[5]), .Y(n16) );
CMPR32X2TS U24 ( .A(in2[7]), .B(in1[7]), .C(n18), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("GeAr_N8_R1_P4_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int Mmax(long long int a, long long int b) { if (a > b) return a; return b; } long long int Mmin(long long int a, long long int b) { if (a < b) return a; return b; } long long int nod(long long int a, long long int b) { while (a && b) { if (a > b) a %= b; else b %= a; } return Mmax(a, b); } long long int nok(long long int a, long long int b) { return a * b / nod(a, b); } bool IsPrime(long long int x) { if (x < 2) return false; long long int X = sqrt(x), i; for (i = 2; i <= X; i++) if (x % i == 0) return false; return true; } void hanoi(int n, int A, int C, int B) { if (n == 1) { cout << n << << A << << C << endl; } else { hanoi(n - 1, A, B, C); cout << n << << A << << C << endl; hanoi(n - 1, B, C, A); } } string pr2(string a, int d) { if (d == 0) return 0 ; string b; long long int sz = a.size(), i, prenos = 0; for (i = 0; i < sz; i++) { b[i] = a[i]; } for (i = sz - 1; i > -1; i--) { a[i] = ((b[i] - 0 ) * d + prenos) % 10 + 0 ; prenos = ((b[i] - 0 ) * d + prenos) / 10; } if (prenos) a = char(prenos + 0 ) + a; return a; } string sum(string a, string b) { bool carry = false; long long int i, sz1, sz2, maxsz, minsz; string c, d; sz1 = a.size(); sz2 = b.size(); maxsz = max(sz1, sz2); minsz = min(sz1, sz2); while (sz1 < maxsz) { sz1++; a = 0 + a; } while (sz2 < maxsz) { sz2++; b = 0 + b; } for (i = maxsz - 1; i > -1; i--) { d = char((a[i] + b[i] - 96 + carry) % 10 + 48) + d; if (a[i] + b[i] - 96 + carry > 9) carry = true; else carry = false; } if (carry == true) d = char( 1 ) + d; return d; } string pr(string a, string b) { string res = 0 , p, p2; int sz = a.size(), x = 0; for (sz = a.size(); sz > 0; sz--, x++) { int d = a[sz - 1] - 0 ; a = a.erase(sz - 1, 1); p2 = pr2(b, d); p2 += p; res = sum(res, p2); p += 0 ; } return res; } bool vesokosna(long long int x) { return (x % 4 == 0 && x % 100 || x % 400 == 0); } long long int reverse(long long int x) { long long int mirror = 0; while (x) { mirror = mirror * 10 + x % 10; x /= 10; } return mirror; } long long int ost(string x, long long int k) { long long int num = 0, i, sz = x.size(); for (i = 0; i < sz; i++) { num = num * 10; num += x[i] - 0 ; num %= k; } return num; } bool can[128][128]; vector<string> ans; int main() { char last; int k, i, j, sz2 = 1; cin >> k; string q; cin >> q; int sz = q.size(); if (sz < k) { cout << NO n ; return 0; } string help; help += q[0]; ans.push_back(help); last = q[0]; for (i = 1; i < sz; i++) { if (sz2 == k) break; bool can = true; ; for (j = 0; j < sz2; j++) if (q[i] == ans[j][0]) can = false; if (can) { string help; help += q[i]; last = q[i]; ans.push_back(help); sz2++; } else ans.back() += q[i]; } if (sz2 == k) { cout << YES n ; for (; i < sz; i++) { ans.back() += q[i]; } for (i = 0; i < sz2; i++) cout << ans[i] << endl; return 0; } cout << NO n ; return 0; } |
// limbus_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
limbus_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int n, a[maxn], cnt[maxn], mx = 0, last[maxn * 2], ans = 0; void solve1(int x) { for (int i = 1; i <= n; i++) last[n - i] = last[n + i] = -1; last[n] = 0; int cur = 0; for (int i = 1; i <= n; i++) { if (a[i] == x) cur++; else if (a[i] == mx) cur--; if (last[n + cur] == -1) last[n + cur] = i; else ans = max(ans, i - last[n + cur]); } } void solve2(int x) { for (int i = 1; i <= n; i++) cnt[i] = 0; int l = 1, equal = 0; cnt[a[l]]++; if (cnt[a[l]] == x) equal++; for (int i = 2; i <= n; i++) { cnt[a[i]]++; if (cnt[a[i]] == x) equal++; else if (cnt[a[i]] > x) { while (cnt[a[i]] > x) { cnt[a[l]]--; if (cnt[a[l]] == x - 1) equal--; l++; } } if (equal >= 2) ans = max(ans, i - l + 1); } } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; cnt[a[i]]++; mx = cnt[mx] < cnt[a[i]] ? a[i] : mx; } int limt = sqrt(n); for (int i = 1; i <= n; i++) if (cnt[i] >= limt && i != mx) solve1(i); for (int i = 1; i < limt; i++) solve2(i); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { char temp[11]; int n, m, k; cin >> n >> m >> k; int a[10][100], b[10][100], c[10][100]; for (int i = 0; i < n; i++) { cin >> temp; for (int j = 0; j < m; j++) cin >> a[i][j] >> b[i][j] >> c[i][j]; } int maxi = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { if (i == j) continue; vector<pair<int, int> > diff(m); for (int t = 0; t < m; t++) diff[t] = make_pair(b[j][t] - a[i][t], t); sort(diff.rbegin(), diff.rend()); int kc = k, cur = 0; for (int t = 0; kc > 0 && t < m && diff[t].first > 0; t++) { cur += min(kc, c[i][diff[t].second]) * diff[t].first; kc -= min(kc, c[i][diff[t].second]); } maxi = max(maxi, cur); } cout << maxi << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char s[18]; for (int i = 1; i <= 8; i++) { cin >> s; bool p = false; for (int j = 1; j < 8; j++) if (s[j] == s[j - 1]) { p = true; break; } if (p) { cout << NO ; return 0; } } cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<complex<double> > vec; double minDist(complex<double> &a, complex<double> &b, complex<double> &p) { complex<double> ab = ((b) - (a)), ap = ((p) - (a)), ba = ((a) - (b)), bp = ((p) - (b)); double distPB = sqrt(((conj(bp) * (bp)).real())), distPA = sqrt(((conj(ap) * (ap)).real())), distAB = sqrt(((conj(ab) * (ab)).real())); double thetaA = acos(((conj(ab) * (ap)).real()) / distAB / distPA); double thetaB = acos(((conj(ba) * (bp)).real()) / distAB / distPB); double ans; if (fabs(thetaA) >= 3.14159265358979323846 / 2) ans = distPA; else if (fabs(thetaB) >= 3.14159265358979323846 / 2) ans = distPB; else ans = sin(fabs(thetaA)) * distPA; return ans; } int main() { int n; long long px, py, tempX, tempY; scanf( %d %I64d %I64d , &n, &px, &py); double maxi = 0, mini = 1E12, dist; for (int i = 0; i < n; i++) { scanf( %I64d %I64d , &tempX, &tempY); dist = sqrt((tempX - px) * (tempX - px) + (tempY - py) * (tempY - py)); maxi = max(maxi, dist); complex<double> xx = complex<double>(tempX, tempY); vec.push_back(xx); } vec.push_back(vec[0]); maxi *= maxi; complex<double> P = complex<double>(px, py); for (int i = 0; i < n; i++) { mini = min(mini, minDist(vec[i], vec[i + 1], P)); } mini *= mini; double ans = (maxi - mini); ans *= 3.14159265358979323846; printf( %0.8f , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, x, m = 1e18; cin >> n; vector<long long> v; for (int i = 0; i < n; i++) { cin >> x; v.push_back(x); } sort(v.begin(), v.end()); for (int i = 0; i < v.size() / 2; i++) { m = min(m, v[v.size() / 2 + i] - v[i]); } cout << m; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, test, len; string s; cin >> test; while (test--) { cin >> s; len = s.length(); if (s[len - 2] == p && s[len - 1] == o ) { cout << FILIPINO << endl; } else if (s[len - 4] == d && s[len - 3] == e && s[len - 2] == s && s[len - 1] == u ) { cout << JAPANESE << endl; } else if (s[len - 4] == m && s[len - 3] == a && s[len - 2] == s && s[len - 1] == u ) { cout << JAPANESE << endl; } else { cout << KOREAN << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> v; string s; const int N = 1000001; int n; long long d, arr[N]; unsigned long long gcd(long long x, long long y) { if (y == 0) { return x; } return gcd(y, x % y); } void gen(long long ind, string t) { if (ind == s.size()) { if (t.size() == 3) v.push_back(t); return; } gen(ind + 1, t + s[ind]); gen(ind + 1, t); } long long check() { long long res = 0; for (long long i = 0; i < v.size(); ++i) { if (((v[i][v[i].size() - 1] - 0 ) - (v[i][0] - 0 )) <= d) { res++; } } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, l, r; bool lie = 0; cin >> n >> l >> r; int v[n], s[n]; for (int i = 1; i <= n; ++i) { cin >> v[i]; } for (int i = 1; i <= n; ++i) { cin >> s[i]; } for (int i = 1; i < l; ++i) { if (v[i] != s[i]) { lie = 1; break; } } if (!lie) { for (int i = r + 1; i <= n; ++i) { if (v[i] != s[i]) { lie = 1; break; } } } if (lie) { cout << LIE n ; } else { cout << TRUTH n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const string alf = abcdefghijklmnopqrstuvwxyz ; const int hashP = 239017; const int N = 1e5 + 10; const int MOD = 1e9 + 7; const int MOD2 = 998244353; const int INF = 1e9; const long long INF2 = 1e18; template <typename T> bool umn(T &a, T b) { return (a > b ? (a = b, 1) : 0); } template <typename T> bool umx(T &a, T b) { return (a < b ? (a = b, 1) : 0); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; string s = to_string(n); long long dl = s.size(); long long ans = 0; for (long long mask = 1; mask <= (1 << dl); mask++) { long long ch = 0; vector<long long> a; for (int i = 0; i < dl; i++) { long long c = (mask >> i) & 1; a.push_back(c); } reverse(a.begin(), a.end()); for (int i = 0; i < dl; i++) { ch *= 10; long long c = a[i]; ch += c; } if (n >= ch) ans++; } cout << ans - 1; return 0; } |
#include <bits/stdc++.h> using namespace std; void imp() { cout << 0 << endl; exit(0); } int n, m, q; int LCA[20][20]; vector<pair<int, int> > E; bool mat[20][20]; int mat2[20]; int Count[20][20]; int Bio[20]; int CheckDFS(int id, int p) { if (Bio[id] == 1) imp(); if (Bio[id] == 2) return Count[id][p]; Bio[id] = 1; int &r = Count[id][p]; for (int i = (int)(0); i < (int)(n); ++i) if (mat[id][i] && i != p) r += CheckDFS(i, id); Bio[id] = 2; return r; } map<pair<int, int>, int> M; unordered_map<int, int> M2; int Has[20]; const int None = -1; int LOW[1 << 13]; int low(int bit) { if (bit == 0) return -1; int cnt = 0; while (bit % 2 == 0) ++cnt, bit >>= 1; return cnt; } bitset<20> CANT[1 << 13]; long long dp(int id, int bit, bool ch = true) { static long long memo[20][1 << 13][2]; static bool bio[20][1 << 13][2]; long long &R = memo[id][bit][ch]; if (bio[id][bit][ch]++) return R; R = 0; if (M2.count(bit)) if (M2[bit] != id) return R = 0; if (ch) if ((Has[id] & bit) != Has[id]) return R = 0; if (CANT[bit][id]) return R = 0; if (bit == 0) return R = 1; int bit2 = (bit & mat2[id]); if (!bit2) { bit2 = bit; int t = LOW[bit]; do { if ((bit2 >> t) & 1) { if (M.count({bit, bit2})) { int bl = M[{bit, bit2}]; if (bl != None && ((bit2 >> bl) & 1)) R += dp(bl, bit2 ^ (1 << bl)) * dp(id, bit ^ bit2, false); } else for (int i = (int)(0); i < (int)(n); ++i) if ((bit2 >> i) & 1) { R += dp(i, bit2 ^ (1 << i)) * dp(id, bit ^ bit2, false); } } bit2 = (bit & (bit2 - 1)); } while (bit2 != bit); return R; } int t = (1 << LOW[bit2]); int bit3 = bit; do { if ((bit2 & bit3) == t) if (!M.count({bit, bit3}) || M[{bit, bit3}] == LOW[bit2]) { R += dp(LOW[bit2], bit3 ^ t) * dp(id, bit ^ bit3, false); } bit3 = (bit & (bit3 - 1)); } while (bit3 != bit); return R; } void AddEdge(int u, int v) { for (int bit = (int)(0); bit < (int)(1 << n); ++bit) { int bit2 = bit; do { if (((bit >> u) & 1) && ((bit >> v) & 1)) if (((bit2 >> u) & 1) && !((bit2 >> v) & 1)) { if (!M.count({bit, bit2})) M[{bit, bit2}] = v; if (M[{bit, bit2}] != v) M[{bit, bit2}] = None; } bit2 = (bit & (bit2 - 1)); } while (bit2 != bit); } } void AddLCA(int a, int b, int c) { if (a == b && a != c) imp(); if (a == b) return; if (c != a) Has[c] |= (1 << a); if (c != b) Has[c] |= (1 << b); for (int bit = (int)(0); bit < (int)(1 << n); ++bit) { if (((bit >> a) & 1) && ((bit >> b) & 1) && !((bit >> c) & 1)) { if (!M2.count(bit)) M2[bit] = c; if (M2[bit] != c) M2[bit] = None; } if (((bit >> a) & 1) && !((bit >> b) & 1)) { if (b != c) CANT[bit][b] = 1; } if (((bit >> b) & 1) && !((bit >> a) & 1)) { if (a != c) CANT[bit][a] = 1; } } } int main() { memset(LCA, -1, sizeof LCA); for (int i = (int)(0); i < (int)(1 << 13); ++i) LOW[i] = low(i); cin >> n >> m >> q; for (int i = (int)(0); i < (int)(m); ++i) { int u, v; cin >> u >> v, --u, --v; E.push_back({u, v}); AddEdge(u, v); AddEdge(v, u); mat[u][v] = mat[v][u] = true; mat2[u] |= (1 << v); mat2[v] |= (1 << u); } for (int i = (int)(0); i < (int)(q); ++i) { int a, b, c; cin >> a >> b >> c, --a, --b, --c; if (LCA[a][b] != -1 && LCA[a][b] != c) imp(); LCA[a][b] = LCA[b][a] = c; AddLCA(a, b, c); } for (int i = (int)(0); i < (int)(n); ++i) { memset(Bio, 0, sizeof Bio); CheckDFS(i, i); } cout << dp(0, (1 << n) - 2) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 100; int test[maxn]; int main() { int n, num(0), x; cin >> n; char ch; int l = 2e5; int r = l + 1; int mi, ma; for (int i = 0; i < n; i++) { cin >> ch >> x; if (ch == L ) { test[x] = l; num++; l--; mi = test[x]; } else if (ch == R ) { test[x] = r; num++; r++; ma = test[x]; } else if (ch == ? ) { int temp = test[x]; int ans = min(temp - mi, r - 1 - temp); cout << ans << endl; } } } |
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_cmd_master.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// State machine resposible for controlling command transfers ////
//// on 1-bit sd card command interface ////
//// ////
//// Author(s): ////
//// - Marek Czerski, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson () ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_cmd_master(
input sd_clk,
input rst,
input start_i,
input int_status_rst_i,
output [1:0] setting_o,
output reg start_xfr_o,
output reg go_idle_o,
output reg [39:0] cmd_o,
input [119:0] response_i,
input crc_ok_i,
input index_ok_i,
input finish_i,
input busy_i, //direct signal from data sd data input (data[0])
//input card_detect,
input [31:0] argument_i,
input [`CMD_REG_SIZE-1:0] command_i,
input [15:0] timeout_i,
output [`INT_CMD_SIZE-1:0] int_status_o,
output reg [31:0] response_0_o,
output reg [31:0] response_1_o,
output reg [31:0] response_2_o,
output reg [31:0] response_3_o
);
//-----------Types--------------------------------------------------------
reg [15:0] timeout_reg;
reg crc_check;
reg index_check;
reg busy_check;
reg expect_response;
reg long_response;
reg [`INT_CMD_SIZE-1:0] int_status_reg;
//reg card_present;
//reg [3:0]debounce;
reg [15:0] watchdog;
parameter SIZE = 2;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 2'b00;
parameter EXECUTE = 2'b01;
parameter BUSY_CHECK = 2'b10;
assign setting_o[1:0] = {long_response, expect_response};
assign int_status_o = state == IDLE ? int_status_reg : 5'h0;
//---------------Input ports---------------
// always @ (posedge sd_clk or posedge rst )
// begin
// if (rst) begin
// debounce<=0;
// card_present<=0;
// end
// else begin
// if (!card_detect) begin//Card present
// if (debounce!=4'b1111)
// debounce<=debounce+1'b1;
// end
// else
// debounce<=0;
//
// if (debounce==4'b1111)
// card_present<=1'b1;
// else
// card_present<=1'b0;
// end
// end
always @(state or start_i or finish_i or go_idle_o or busy_check or busy_i)
begin: FSM_COMBO
case(state)
IDLE: begin
if (start_i)
next_state <= EXECUTE;
else
next_state <= IDLE;
end
EXECUTE: begin
if ((finish_i && !busy_check) || go_idle_o)
next_state <= IDLE;
else if (finish_i && busy_check)
next_state <= BUSY_CHECK;
else
next_state <= EXECUTE;
end
BUSY_CHECK: begin
if (!busy_i)
next_state <= IDLE;
else
next_state <= BUSY_CHECK;
end
default: next_state <= IDLE;
endcase
end
always @(posedge sd_clk or posedge rst)
begin: FSM_SEQ
if (rst) begin
state <= IDLE;
end
else begin
state <= next_state;
end
end
always @(posedge sd_clk or posedge rst)
begin
if (rst) begin
crc_check <= 0;
response_0_o <= 0;
response_1_o <= 0;
response_2_o <= 0;
response_3_o <= 0;
int_status_reg <= 0;
expect_response <= 0;
long_response <= 0;
cmd_o <= 0;
start_xfr_o <= 0;
index_check <= 0;
busy_check <= 0;
watchdog <= 0;
timeout_reg <= 0;
go_idle_o <= 0;
end
else begin
case(state)
IDLE: begin
go_idle_o <= 0;
index_check <= command_i[`CMD_IDX_CHECK];
crc_check <= command_i[`CMD_CRC_CHECK];
busy_check <= command_i[`CMD_BUSY_CHECK];
if (command_i[`CMD_RESPONSE_CHECK] == 2'b10 || command_i[`CMD_RESPONSE_CHECK] == 2'b11) begin
expect_response <= 1;
long_response <= 1;
end
else if (command_i[`CMD_RESPONSE_CHECK] == 2'b01) begin
expect_response <= 1;
long_response <= 0;
end
else begin
expect_response <= 0;
long_response <= 0;
end
cmd_o[39:38] <= 2'b01;
cmd_o[37:32] <= command_i[`CMD_INDEX]; //CMD_INDEX
cmd_o[31:0] <= argument_i; //CMD_Argument
timeout_reg <= timeout_i;
watchdog <= 0;
if (start_i) begin
start_xfr_o <= 1;
int_status_reg <= 0;
end
end
EXECUTE: begin
start_xfr_o <= 0;
watchdog <= watchdog + 16'd1;
if (watchdog > timeout_reg) begin
int_status_reg[`INT_CMD_CTE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
go_idle_o <= 1;
end
//Incoming New Status
else begin //if ( req_in_int == 1) begin
if (finish_i) begin //Data avaible
if (crc_check & !crc_ok_i) begin
int_status_reg[`INT_CMD_CCRCE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
end
if (index_check & !index_ok_i) begin
int_status_reg[`INT_CMD_CIE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
end
int_status_reg[`INT_CMD_CC] <= 1;
if (expect_response != 0) begin
response_0_o <= response_i[119:88];
response_1_o <= response_i[87:56];
response_2_o <= response_i[55:24];
response_3_o <= {response_i[23:0], 8'h00};
end
// end
end ////Data avaible
end //Status change
end //EXECUTE state
BUSY_CHECK: begin
start_xfr_o <= 0;
go_idle_o <= 0;
end
endcase
if (int_status_rst_i)
int_status_reg <= 0;
end
end
endmodule
|
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