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`define CYCLE_TIME 50
module TestBench;
reg Clk;
reg Reset;
reg Start;
integer i, outfile, counter;
always #(`CYCLE_TIME/2) Clk = ~Clk;
CPU CPU(
.clk_i (Clk),
.rst_i (Reset),
.start_i(Start)
);
initial begin
counter = 0;
// initialize instruction memory
for(i=0; i<256; i=i+1) begin
CPU.Instruction_Memory.memory[i] = 32'b0;
end
// initialize data memory
for(i=0; i<32; i=i+1) begin
CPU.Data_Memory.memory[i] = 8'b0;
end
// initialize Register File
for(i=0; i<32; i=i+1) begin
CPU.Registers.register[i] = 32'b0;
end
// Load instructions into instruction memory
$readmemb("instruction.txt", CPU.Instruction_Memory.memory);
// Open output file
outfile = $fopen("output.txt") | 1;
// Set Input n into data memory at 0x00
CPU.Data_Memory.memory[0] = 8'h5; // n = 5 for example
Clk = 0;
Reset = 0;
Start = 0;
#(`CYCLE_TIME/4)
Reset = 1;
Start = 1;
end
always@(posedge Clk) begin
if(counter == 60) // stop after 60 cycles
$stop;
// print PC
$fdisplay(outfile, "PC = %d", CPU.PC.pc_o);
// print Registers
// $fdisplay(outfile, "Jump = %d", CPU.Control.Jump_o);
// $fdisplay(outfile, "Reg: %d %d",CPU.Registers.RSaddr_i,CPU.Registers.RTaddr_i);
// $fdisplay(outfile, "ALU: %d %d %d",CPU.ALU.data1_i,CPU.ALU.data2_i,CPU.ALU.Zero_o);
$fdisplay(outfile, "Registers");
$fdisplay(outfile, "R0(r0) = %d, R8 (t0) = %d, R16(s0) = %d, R24(t8) = %d", CPU.Registers.register[0], CPU.Registers.register[8] , CPU.Registers.register[16], CPU.Registers.register[24]);
$fdisplay(outfile, "R1(at) = %d, R9 (t1) = %d, R17(s1) = %d, R25(t9) = %d", CPU.Registers.register[1], CPU.Registers.register[9] , CPU.Registers.register[17], CPU.Registers.register[25]);
$fdisplay(outfile, "R2(v0) = %d, R10(t2) = %d, R18(s2) = %d, R26(k0) = %d", CPU.Registers.register[2], CPU.Registers.register[10], CPU.Registers.register[18], CPU.Registers.register[26]);
$fdisplay(outfile, "R3(v1) = %d, R11(t3) = %d, R19(s3) = %d, R27(k1) = %d", CPU.Registers.register[3], CPU.Registers.register[11], CPU.Registers.register[19], CPU.Registers.register[27]);
$fdisplay(outfile, "R4(a0) = %d, R12(t4) = %d, R20(s4) = %d, R28(gp) = %d", CPU.Registers.register[4], CPU.Registers.register[12], CPU.Registers.register[20], CPU.Registers.register[28]);
$fdisplay(outfile, "R5(a1) = %d, R13(t5) = %d, R21(s5) = %d, R29(sp) = %d", CPU.Registers.register[5], CPU.Registers.register[13], CPU.Registers.register[21], CPU.Registers.register[29]);
$fdisplay(outfile, "R6(a2) = %d, R14(t6) = %d, R22(s6) = %d, R30(s8) = %d", CPU.Registers.register[6], CPU.Registers.register[14], CPU.Registers.register[22], CPU.Registers.register[30]);
$fdisplay(outfile, "R7(a3) = %d, R15(t7) = %d, R23(s7) = %d, R31(ra) = %d", CPU.Registers.register[7], CPU.Registers.register[15], CPU.Registers.register[23], CPU.Registers.register[31]);
// print Data Memory
$fdisplay(outfile, "Data Memory: 0x00 = %d", {CPU.Data_Memory.memory[3] , CPU.Data_Memory.memory[2] , CPU.Data_Memory.memory[1] , CPU.Data_Memory.memory[0] });
$fdisplay(outfile, "Data Memory: 0x04 = %d", {CPU.Data_Memory.memory[7] , CPU.Data_Memory.memory[6] , CPU.Data_Memory.memory[5] , CPU.Data_Memory.memory[4] });
$fdisplay(outfile, "Data Memory: 0x08 = %d", {CPU.Data_Memory.memory[11], CPU.Data_Memory.memory[10], CPU.Data_Memory.memory[9] , CPU.Data_Memory.memory[8] });
$fdisplay(outfile, "Data Memory: 0x0c = %d", {CPU.Data_Memory.memory[15], CPU.Data_Memory.memory[14], CPU.Data_Memory.memory[13], CPU.Data_Memory.memory[12]});
$fdisplay(outfile, "Data Memory: 0x10 = %d", {CPU.Data_Memory.memory[19], CPU.Data_Memory.memory[18], CPU.Data_Memory.memory[17], CPU.Data_Memory.memory[16]});
$fdisplay(outfile, "Data Memory: 0x14 = %d", {CPU.Data_Memory.memory[23], CPU.Data_Memory.memory[22], CPU.Data_Memory.memory[21], CPU.Data_Memory.memory[20]});
$fdisplay(outfile, "Data Memory: 0x18 = %d", {CPU.Data_Memory.memory[27], CPU.Data_Memory.memory[26], CPU.Data_Memory.memory[25], CPU.Data_Memory.memory[24]});
$fdisplay(outfile, "Data Memory: 0x1c = %d", {CPU.Data_Memory.memory[31], CPU.Data_Memory.memory[30], CPU.Data_Memory.memory[29], CPU.Data_Memory.memory[28]});
$fdisplay(outfile, "\n");
counter = counter + 1;
end
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_9_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_9_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << n << n ; for (int i = 0; i < n; i++) { cout << 1 << ; } cout << n ; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int INF = (1 << 29) + 5; const long long int LLINF = (1ll << 59) + 5; const int MOD = 1000 * 1000 * 1000 + 7; int n, q; pair<string, string> arr[228]; map<string, bool> can; queue<string> now; int main() { cin >> n >> q; string st1, st2; for (int i = 0; i < q; ++i) { cin >> arr[i].first >> arr[i].second; } now.push( a ); string dd; string next; while (!now.empty()) { dd = now.front(); now.pop(); if (dd.size() >= 6) continue; for (int i = 0; i < q; ++i) { if (dd[0] == arr[i].second[0]) { next = arr[i].first + dd.substr(1, (int)dd.size() - 1); if (!can[next]) { can[next] = true; now.push(next); } } } } int answer = 0; for (auto it = can.begin(); it != can.end(); ++it) { if (it->first.size() == n) { ++answer; } } cout << answer; fclose(stdin); fclose(stdout); return 0; } |
#include <bits/stdc++.h> using namespace std; int r, g, j, f[200001], sc, kq, mod = round(1e9) + 7; long long i, h; int main() { cin >> r >> g; f[0] = 1; for (i = 1; i * (i + 1) / 2 <= r + g; i++) { for (j = r; j >= 0; j--) { if (j >= i) f[j] = (f[j] + f[j - i]) % mod; } } h = i - 1; for (i = 0; i <= r; i++) if (h * (h + 1) / 2 - i <= g) kq = (kq + f[i]) % mod; cout << kq; } |
#include <bits/stdc++.h> using namespace std; int n, m; int a[1000005], dp1[1000005], dp2[1000005], dp3[1000005]; long long ans; int main(int argc, const char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 0; i <= m + 1; ++i) { dp1[i] = 1e9; dp2[i] = -1e9; } int x; int mn = 1e9; for (int i = n; i > 0; --i) { x = a[i]; if (mn < x && mn < dp1[x]) dp1[x] = mn; if (x < mn) mn = x; } int mx = -1e9; for (int i = 1; i <= n; ++i) { x = a[i]; if (mx > x && mx > dp2[x]) dp2[x] = mx; if (x > mx) mx = x; } for (int i = m; i > 0; --i) { dp3[i] = dp1[i]; if (dp1[i + 1] < dp1[i]) dp1[i] = dp1[i + 1]; } for (int i = m; i > 0; --i) { if (dp2[i + 1] > dp2[i]) dp2[i] = dp2[i + 1]; } int l, r; for (int i = 1; i <= m; ++i) { l = i; r = m; while (l < r) { int mid = (l + r) >> 1; if (dp1[mid + 1] >= i && dp2[mid + 1] <= mid) r = mid; else l = mid + 1; } if (dp1[r + 1] >= i && dp2[r + 1] <= r) ans += m - r + 1; if (dp3[i] < i) break; } cout << ans << n ; return 0; } |
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
/* PE: processing element */
module PE(clk, reset, ctrl, d0, d1, d2, out);
input clk;
input reset;
input [10:0] ctrl;
input [`WIDTH_D0:0] d0;
input [`WIDTH:0] d1, d2;
output [`WIDTH:0] out;
reg [`WIDTH_D0:0] R0;
reg [`WIDTH:0] R1, R2, R3;
wire [1:0] e0, e1, e2; /* part of R0 */
wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
mx0, mx1, mx2, mx3, mx4, mx5, mx6, mx7, /* output of MUX */
ad0, ad1, ad2, /* output of GF(3^m) adder */
cu0, cu1, cu2, cu3, /* output of cubic */
mo0, mo1, mo2, /* output of mod_p */
t0, t1, t2;
wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
assign mx0 = c0 ? d1 : ad2;
assign mx1 = c2 ? d2 : ad2;
always @ (posedge clk)
if(reset) R1 <= 0;
else if (c1) R1 <= mx0;
always @ (posedge clk)
if(reset) R2 <= 0;
else if (c3) R2 <= mx1;
always @ (posedge clk)
if(reset) R0 <= 0;
else if (c4) R0 <= d0;
else if (c5) R0 <= R0 << 6;
assign {e2,e1,e0} = R0[`WIDTH_D0:(`WIDTH_D0-5)];
PPG
ppg_0 (e0, R1, ppg0),
ppg_1 (e1, R2, ppg1),
ppg_2 (e2, R1, ppg2);
v0 v0_ (ppg0, cu0);
v1 v1_ (ppg1, cu1);
v2 v2_ (ppg2, cu2);
v3 v3_ (R2, cu3);
assign mx2 = c6 ? ppg0 : cu0;
assign mx3 = c6 ? ppg1 : cu1;
assign mx4 = c6 ? mo1 : cu2;
assign mx5 = c7 ? mo2 : R3;
mod_p
mod_p_0 (mx3, mo0),
mod_p_1 (ppg2, t0),
mod_p_2 (t0, mo1),
mod_p_3 (R3, t1),
mod_p_4 (t1, t2),
mod_p_5 (t2, mo2);
assign mx6 = c9 ? mo0 : mx3;
assign mx7 = c6 ? (c8 ? mx5 : 0) : cu3;
f3m_add
f3m_add_0 (mx2, mx6, ad0),
f3m_add_1 (mx4, mx7, ad1),
f3m_add_2 (ad0, ad1, ad2);
always @ (posedge clk)
if (reset) R3 <= 0;
else if (c10) R3 <= ad2;
else R3 <= 0; /* change */
assign out = R3;
endmodule
// C = (x*B mod p(x))
module mod_p(B, C);
input [`WIDTH:0] B;
output [`WIDTH:0] C;
wire [`WIDTH+2:0] A;
assign A = {B[`WIDTH:0], 2'd0}; // A == B*x
wire [1:0] w0;
f3_mult m0 (A[1007:1006], 2'd2, w0);
f3_sub s0 (A[1:0], w0, C[1:0]);
assign C[207:2] = A[207:2];
wire [1:0] w104;
f3_mult m104 (A[1007:1006], 2'd1, w104);
f3_sub s104 (A[209:208], w104, C[209:208]);
assign C[1005:210] = A[1005:210];
endmodule
// PPG: partial product generator, C == A*d in GF(3^m)
module PPG(d, A, C);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i=0; i < `M; i=i+1)
begin: ppg0
f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
end
endgenerate
endmodule
// f3m_add: C = A + B, in field F_{3^M}
module f3m_add(A, B, C);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for(i=0; i<`M; i=i+1) begin: aa
f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
end
endgenerate
endmodule
// f3_add: C == A+B (mod 3)
module f3_add(A, B, C);
input [1:0] A, B;
output [1:0] C;
wire a0, a1, b0, b1, c0, c1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C = {c1, c0};
assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
(~a0 & ~a1 & b0 & ~b1) |
(~a0 & a1 & ~b0 & b1) ;
assign c1 = (~a0 & a1 & ~b0 & ~b1) |
( a0 & ~a1 & b0 & ~b1) |
(~a0 & ~a1 & ~b0 & b1) ;
endmodule
// f3_sub: C == A-B (mod 3)
module f3_sub(A, B, C);
input [1:0] A, B;
output [1:0] C;
f3_add a0(A, {B[0],B[1]}, C);
endmodule
// f3_mult: C = A*B (mod 3)
module f3_mult(A, B, C);
input [1:0] A;
input [1:0] B;
output [1:0] C;
wire a0, a1, b0, b1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_ad.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No user `defines in this module
module ent_ad
//
// Generated Module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
wire port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_hs__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_4TO2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_2_V
`define SKY130_FD_SC_LP__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_2_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; int ch = getchar(), f = 1; while (!isdigit(ch) && (ch != - ) && (ch != EOF)) ch = getchar(); if (ch == - ) { f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } const int N = 5e5 + 10, mod = 1e9 + 7; int n, ans; pair<int, int> a[N]; inline int Mod(int x) { return x >= mod ? x - mod : x; } inline void upd(int &x, int y) { x += y, x = (x >= mod ? x - mod : (x < 0 ? x + mod : x)); } struct SegmentTree { int v[N << 2], lazy[N << 2]; inline void push_up(int u) { v[u] = Mod(v[u << 1] + v[u << 1 ^ 1]); } inline void push_down(int u, int l, int mid, int r) { if (!lazy[u]) return; upd(lazy[u << 1], lazy[u]), upd(lazy[u << 1 ^ 1], lazy[u]); upd(v[u << 1], 1ll * lazy[u] * (mid - l + 1) % mod), upd(v[u << 1 ^ 1], 1ll * lazy[u] * (r - mid) % mod); lazy[u] = 0; } inline void update(int u, int l, int r, int ql, int qr) { if (l >= ql && r <= qr) return upd(v[u], r - l + 1), upd(lazy[u], 1), void(0); int mid = l + r >> 1; push_down(u, l, mid, r); if (qr <= mid) update(u << 1, l, mid, ql, qr); else if (ql > mid) update(u << 1 ^ 1, mid + 1, r, ql, qr); else update(u << 1, l, mid, ql, qr), update(u << 1 ^ 1, mid + 1, r, ql, qr); push_up(u); } inline int Query(int u, int l, int r, int ql, int qr) { if (l >= ql && r <= qr) return v[u]; int mid = l + r >> 1; push_down(u, l, mid, r); if (qr <= mid) return Query(u << 1, l, mid, ql, qr); else if (ql > mid) return Query(u << 1 ^ 1, mid + 1, r, ql, qr); else return Mod(Query(u << 1, l, mid, ql, qr) + Query(u << 1 ^ 1, mid + 1, r, ql, qr)); } } t[2]; int main() { n = read(); for (register int i = (1); i <= (n); i++) a[i] = make_pair(read(), i); sort(a + 1, a + 1 + n); for (register int i = (1); i <= (n); i++) { int x = t[0].Query(1, 1, n, a[i].second, a[i].second), sum = t[0].Query(1, 1, n, 1, a[i].second); int y = t[1].Query(1, 1, n, a[i].second, a[i].second), Sum = t[1].Query(1, 1, n, a[i].second, n); upd(ans, 1ll * a[i].first * (sum - 1ll * x * a[i].second % mod + a[i].second) % mod * (n - a[i].second + 1) % mod); upd(ans, 1ll * a[i].first * (Sum - 1ll * y * (n - a[i].second + 1) % mod) % mod * a[i].second % mod); t[0].update(1, 1, n, 1, a[i].second), t[1].update(1, 1, n, a[i].second, n); } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const long double CHANGE = 1e-8; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; int main() { puts( YES ); int n; scanf( %d , &n); while (n--) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); int ans = 0; if (abs(min(x1, x2)) % 2) ans ^= 1; if (abs(min(y1, y2)) % 2) ans ^= 2; printf( %d n , ans + 1); } } |
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module test_tiny;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [`WIDTH_D0:0] data;
// Outputs
wire [`WIDTH_D0:0] out;
wire done;
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1; // keep FSM silent
// init x, y
write(3, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
write(5, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
write(6, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
write(7, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(9);
check(1006'h2965a664a44a85426524a19821aa12a42605258540a056525248149a96061560451a6a95861496a8140985a8902955951552696a425948159a2141a0aaa5840442851218546a49a2a2496658644656a9a6162a5098a025645151aa668902aaa102a0805900488980545120462896204252584282868449488a00884995a9);
read(10);
check(1006'h244151402864a58144a0509a26121148024224a299a4062a248944801589895a04a8a681a4245492a5aa5958901a142120515582941220529512012554699982594528256086220a55641a5a212511aa50a0a4a198200560a628994925551249659028459a8a24688191044a08529064119949a112564a52082068858890);
read(11);
check(1006'h180645a168488aa651260a226a124a66080299922a8595404428610808262992a22682905a55625665824505a609882a88422a886296551a6221a29a16aa11141a12280942aa84094946860205964a26669684569054810a914124a086212a5a5821440119015a98844101854a9951141981221169224a1599a11914a504);
read(12);
check(1006'h18a6911a415584242209a6a52629464160400a0a45554552866a9a20a8520a551856814024118140a144a151604449609aa24085a609a2a0851285445a96602a2461212641204a591a66a5604211004882191912920862a9860a861a88a005516611622a44880a48690412292244615156004952521664a84a5961510225);
read(13);
check(1006'h250869062a008a1882940945a20441680111009595094282260a95488aaa4588262641912aa64a29a8526408451940619612014212441090209588888a004002462206a8294a158809258852650a15226a99808952201191614814166198a52a8151454968a288295994286919811691aa21048661a5288402182a558215);
read(14);
check(1006'h016641111896469064656661124a160226a89485469954a6a5406aa28590655a018922965688045984585a61888165085289a61a051258a59459210842108082566966664250991442a2941521806608610a52182256042680a4881900605a8459260a9824295244629865a6a62a18958a66955152404814065588150894);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task write;
input [6:0] adr;
input [`WIDTH_D0:0] dat;
begin
sel = 1;
w = 1;
addr = adr;
data = dat;
#(`P);
end
endtask
task read;
input [6:0] adr;
begin
sel = 1;
w = 0;
addr = adr;
#(`P);
end
endtask
task check;
input [`WIDTH_D0:0] wish;
begin
if (out !== wish)
begin $display("Error! %h %h", out, wish); end
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, i, j, a[2 * 100010]; vector<char> ans; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } long long l = 1, r = n, f = -1e18; while (l <= r) { if (f >= a[l] && f >= a[r]) break; if (a[l] <= f && f < a[r]) { ans.push_back( R ); f = a[r]; r--; continue; } if (a[l] > f && f >= a[r]) { ans.push_back( L ); f = a[l]; l++; continue; } if (a[l] < a[r]) { ans.push_back( L ); f = a[l]; l++; } else { if (a[l] > a[r]) { ans.push_back( R ); f = a[r]; r--; } else { int k1 = 0, k2 = 0; for (int j = l + 1; j <= r; j++) { if (a[j] > a[j - 1]) k1++; else break; } for (int j = r - 1; j >= l; j--) { if (a[j] > a[j + 1]) k2++; else break; } if (k1 > k2) { ans.push_back( L ); for (int j = l + 1; j <= r; j++) { if (a[j] > a[j - 1]) ans.push_back( L ); else break; } } else { ans.push_back( R ); for (int j = r - 1; j >= l; j--) { if (a[j] > a[j + 1]) ans.push_back( R ); else break; } } break; } } } cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) { cout << ans[i]; } } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; vector<pair<int, int> > v[N]; int n, m; int foo, bar, id; long long val[N]; long long wt[N]; int dep[N]; int dp[20][N]; int par[N]; int x1[N]; int x2[N]; void dfs(int node, int baap) { dep[node] = dep[baap] + 1; dp[0][node] = baap; par[node] = baap; for (int i = 0; i < v[node].size(); i++) { int beta = v[node][i].first; int mark = v[node][i].second; if (beta == baap) continue; val[beta] = wt[mark]; dfs(beta, node); } } int jump(int p, int dist) { for (int i = 19; i >= 0; i--) { if ((1 << i) <= dist) { dist -= 1 << i; p = dp[i][p]; } } return p; } int lca(int p, int q) { if (dep[p] < dep[q]) swap(p, q); p = jump(p, dep[p] - dep[q]); if (p == q) return p; for (int i = 19; i >= 0; i--) { int pp = dp[i][p]; int qq = dp[i][q]; if (pp != qq) p = pp, q = qq; } return dp[0][p]; } int find(int p) { if (val[p] > 1) return p; return par[p] = find(par[p]); } int main() { cin >> n >> m; for (int i = 1; i < n; i++) { scanf( %d%d%lld , &foo, &bar, &wt[i]); v[foo].push_back(make_pair(bar, i)); v[bar].push_back(make_pair(foo, i)); x1[i] = foo; x2[i] = bar; } val[1] = 2; dfs(1, 0); for (int j = 1; j < 20; j++) { for (int i = 1; i <= n; i++) { dp[j][i] = dp[j - 1][dp[j - 1][i]]; } } while (m--) { int p, q, tp; long long r; scanf( %d , &id); if (id == 1) { scanf( %d%d%lld , &p, &q, &r); int lc = lca(p, q); tp = p; while (r and dep[tp] > dep[lc]) { r /= val[tp]; tp = find(par[tp]); } tp = q; while (r and dep[tp] > dep[lc]) { r /= val[tp]; tp = find(par[tp]); } printf( %lld n , r); } else { scanf( %d%lld , &p, &r); wt[p] = r; if (x2[p] == dp[0][x1[p]]) swap(x1[p], x2[p]); val[x2[p]] = r; } } return 0; } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts incoming ascii characters into their pixel *
* representation, which is suitable for output on a display, such as a *
* VGA-compatible monitor or LCD. *
* *
******************************************************************************/
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_ASCII_to_Image (
// Global Signals
clk,
reset,
// ASCII Character Stream (input stream)
ascii_in_channel,
ascii_in_data,
ascii_in_startofpacket,
ascii_in_endofpacket,
ascii_in_valid,
ascii_in_ready,
// Image Stream (output stream)
image_out_ready,
image_out_data,
image_out_startofpacket,
image_out_endofpacket,
image_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 7;
parameter ODW = 0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Global Signals
input clk;
input reset;
// ASCII Character Stream (avalon stream - sink)
input [ 5: 0] ascii_in_channel;
input [IDW:0] ascii_in_data;
input ascii_in_startofpacket;
input ascii_in_endofpacket;
input ascii_in_valid;
output ascii_in_ready;
// Image Stream (avalon stream - source)
input image_out_ready;
output reg [ODW:0] image_out_data;
output reg image_out_startofpacket;
output reg image_out_endofpacket;
output reg image_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire rom_data;
// Internal Registers
reg internal_startofpacket;
reg internal_endofpacket;
reg internal_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
image_out_data <= 'h0;
image_out_startofpacket <= 1'b0;
image_out_endofpacket <= 1'b0;
image_out_valid <= 1'b0;
end
else if (image_out_ready | ~image_out_valid)
begin
image_out_data <= rom_data;
image_out_startofpacket <= internal_startofpacket;
image_out_endofpacket <= internal_endofpacket;
image_out_valid <= internal_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
internal_startofpacket <= 1'b0;
internal_endofpacket <= 1'b0;
internal_valid <= 1'b0;
end
else if (ascii_in_ready)
begin
internal_startofpacket <= ascii_in_startofpacket;
internal_endofpacket <= ascii_in_endofpacket;
internal_valid <= ascii_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ascii_in_ready = ~ascii_in_valid | image_out_ready | ~image_out_valid;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_ascii_rom_128 ASCII_Character_Rom (
// Global Signals
.clk (clk),
.clk_en (ascii_in_ready),
// Inputs
.character (ascii_in_data[ 6: 0]),
.x_coordinate (ascii_in_channel[ 2: 0]),
.y_coordinate (ascii_in_channel[ 5: 3]),
// Outputs
.character_data (rom_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2000000000LL; int main() { int m1, m2, m3, m4, m5; int w1, w2, w3, w4, w5; int hs, hu; int sum; cin >> m1 >> m2 >> m3 >> m4 >> m5; cin >> w1 >> w2 >> w3 >> w4 >> w5; cin >> hs >> hu; sum = max(150, 500 - 2 * m1 - 50 * w1); sum = sum + max(300, 1000 - 4 * m2 - 50 * w2); sum = sum + max(450, 1500 - 6 * m3 - 50 * w3); sum = sum + max(600, 2000 - 8 * m4 - 50 * w4); sum = sum + max(750, 2500 - 10 * m5 - 50 * w5); cout << sum + hs * 100 - hu * 50; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, p[11111], c[11111]; vector<pair<int, int> > ve; int main() { int a; cin >> n; for (int i = 2; i <= n; i++) { cin >> a; c[i] = a; } int s = 1; cin >> p[1]; for (int i = 2; i <= n; i++) { cin >> p[i]; if (p[i] != p[c[i]]) { s++; } } cout << s; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, f[33]; double ans = 0; vector<int> v[33]; string s; template <class T> ostream& operator<<(ostream& out, vector<T> v) { out << v.size() << n ; for (auto e : v) out << e << ; return out; } double check(int k) { double ans = 0, local; for (int i = 0; i < n; i++) { memset(f, 0, sizeof f); for (auto j : v[k]) { f[s[(j + i) % n] - a ]++; } local = 0; for (int i = 0; i <= z - a ; i++) if (f[i] == 1) local += (double)1. / v[k].size(); ans = max(ans, local); } return ans; } int main() { ios_base::sync_with_stdio(false); cin >> s; n = s.size(); for (int i = 0; i < s.size(); i++) v[s[i] - a ].push_back(i); for (int i = 0; i <= z - a ; i++) { ans += ((double)v[i].size() / n) * check(i); } cout << fixed << setprecision(13) << ans << n ; } |
#include <bits/stdc++.h> using namespace std; long long n, m, k, x, s, a[200005], b[200005], c[200005], d[200005], ans; int bfind(int t) { int lo = 0, hi = k - 1, mid; while (lo < hi) { mid = lo + (hi - lo + 1) / 2; if (d[mid] > t) hi = mid - 1; else lo = mid; } return lo; } int main() { cin >> n >> m >> k >> x >> s; for (int i = 0; i < m; i++) scanf( %I64d , &a[i]); for (int i = 0; i < m; i++) scanf( %I64d , &b[i]); for (int i = 0; i < k; i++) scanf( %I64d , &c[i]); for (int i = 0; i < k; i++) scanf( %I64d , &d[i]); ans = x * n; for (int i = 0; i < m; i++) { if (b[i] <= s) ans = min(ans, a[i] * n); } for (int i = 0; i < k; i++) { if (d[i] <= s) ans = min(ans, x * (n - c[i])); } for (int i = 0; i < m; i++) { if (b[i] + d[0] <= s) { int idx = bfind(s - b[i]); ans = min(ans, a[i] * (n - c[idx])); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> st; long long n, q; vector<int> swp(20, false); vector<long long> arr; void build(long long ind, long long l, long long r) { if (l == r) { st[ind] = arr[l]; return; } long long mid = (l + r) >> 1; build(2 * ind, l, mid); build(2 * ind + 1, mid + 1, r); st[ind] = st[2 * ind] + st[2 * ind + 1]; } void update(long long ind, long long l, long long r, long long req, long long level) { if (req < l || req > r) return; if (l == r) { st[ind] = arr[req]; return; } long long mid = (l + r) >> 1; if (swp[level - 1]) { update(2 * ind + 1, l, mid, req, level - 1); update(2 * ind, mid + 1, r, req, level - 1); } else { update(2 * ind, l, mid, req, level - 1); update(2 * ind + 1, mid + 1, r, req, level - 1); } st[ind] = st[2 * ind + 1] + st[2 * ind]; } long long query(long long ind, long long l, long long r, long long ql, long long qr, long long level) { if (l > qr || r < ql) return 0; if (ql <= l && r <= qr) return st[ind]; long long mid = (l + r) / 2; if (swp[level - 1]) return query(2 * ind + 1, l, mid, ql, qr, level - 1) + query(2 * ind, mid + 1, r, ql, qr, level - 1); else return query(2 * ind, l, mid, ql, qr, level - 1) + query(2 * ind + 1, mid + 1, r, ql, qr, level - 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> q; long long len = 1 << n; arr.resize(len); st.assign(4 * len, 0); for (long long i = 0; i < len; i++) cin >> arr[i]; build(1, 0, len - 1); while (q--) { long long type; cin >> type; if (type == 1) { long long ind, val; cin >> ind >> val; ind--; arr[ind] = val; update(1, 0, len - 1, ind, n); } else if (type == 2) { long long k; cin >> k; for (long long i = 0; i < k; i++) swp[i] ^= true; } else if (type == 3) { long long k; cin >> k; swp[k] ^= true; } else { long long l, r; cin >> l >> r; l--; r--; cout << query(1, 0, len - 1, l, r, n) << n ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_8_V
`define SKY130_FD_SC_HVL__FILL_8_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, const U &b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, const U &b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T1, class T2> inline void gn(T1 &x1, T2 &x2) { gn(x1), gn(x2); } template <class T1, class T2, class T3> inline void gn(T1 &x1, T2 &x2, T3 &x3) { gn(x1, x2), gn(x3); } template <class T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <class T> inline void println(T first) { print(first); putchar( n ); } template <class T> inline void printsp(T first) { print(first); putchar( ); } template <class T1, class T2> inline void print(T1 x1, T2 x2) { printsp(x1), println(x2); } template <class T1, class T2, class T3> inline void print(T1 x1, T2 x2, T3 x3) { printsp(x1), printsp(x2), println(x3); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = (long long)a * a % m) if (b & 1) ans = (long long)ans * a % m; return ans; } int size(int n) { int ans = 0; while (n) { n /= 7; ans++; } smax(ans, 1); return ans; } int f[11], p[11]; int calc(int st, int ed) { int ans = 0; int nn = 0; for (int i = ed; i >= st; i--) { ans += p[i] * f[nn]; nn++; } return ans; } int main() { int n, m; gn(n, m); int N = size(n - 1), M = size(m - 1); if (N + M > 7) return puts( 0 ); f[0] = 1; for (int i = 1; i < 11; i++) f[i] = f[i - 1] * 7; for (int i = 0; i < 7; i++) p[i] = i; int ans = 0; do { int a = calc(0, N - 1), b = calc(N, N + M - 1); if (a < n && b < m) ans++; } while (next_permutation(p, p + 7)); int num = 1; for (int i = 2; i <= 7 - N - M; i++) num *= i; println(ans / num); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int t[n]; for (int i = 0; i < n; i++) { cin >> t[i]; } if (n == 1) { cout << m - t[0]; return 0; } int ans = 0; for (int k = 0; k < n * n * n; k++) { set<int> st; for (int i = 0; i < n; i++) { if (st.count(t[i]) == 0 && t[i] < m) { st.insert(t[i]); t[i]++; } } if (st.size()) { ans++; } } cout << ans; return 0; } |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Mon Aug 29 03:22:14 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/nop/PCIe_bandwidth/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j; string ss; cin >> n >> m >> ss; for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { if (ss[j] == B && ss[j + 1] == G ) { ss[j] = G ; ss[j + 1] = B ; j++; } } } cout << ss << endl; return 0; } |
module lsu_wb_router
(/*AUTOARG*/
// Outputs
out_sgpr_dest_addr, out_sgpr_dest_data, out_sgpr_dest_wr_en,
out_sgpr_instr_done, out_sgpr_instr_done_wfid, out_vgpr_dest_addr,
out_vgpr_dest_data, out_vgpr_dest_wr_en, out_vgpr_dest_wr_mask,
out_vgpr_instr_done, out_vgpr_instr_done_wfid,
out_tracemon_retire_pc, out_gm_or_lds, out_rfa_dest_wr_req,
// Inputs
in_rd_data, in_wftag_resp, in_ack, in_exec_value,
in_lddst_stsrc_addr, in_reg_wr_en, in_instr_pc, in_gm_or_lds
);
input [8191:0] in_rd_data;
input [6:0] in_wftag_resp;
input in_ack;
input [63:0] in_exec_value;
input [11:0] in_lddst_stsrc_addr;
input [3:0] in_reg_wr_en;
input [31:0] in_instr_pc;
input in_gm_or_lds;
output [8:0] out_sgpr_dest_addr;
output [127:0] out_sgpr_dest_data;
output [3:0] out_sgpr_dest_wr_en;
output out_sgpr_instr_done;
output [5:0] out_sgpr_instr_done_wfid;
output [9:0] out_vgpr_dest_addr;
output [8191:0] out_vgpr_dest_data;
output [3:0] out_vgpr_dest_wr_en;
output [63:0] out_vgpr_dest_wr_mask;
output out_vgpr_instr_done;
output [5:0] out_vgpr_instr_done_wfid;
output [31:0] out_tracemon_retire_pc;
output out_gm_or_lds;
output out_rfa_dest_wr_req;
reg [3:0] out_sgpr_dest_wr_en;
reg [3:0] out_vgpr_dest_wr_en;
reg out_sgpr_instr_done;
reg out_vgpr_instr_done;
assign out_sgpr_dest_addr = in_lddst_stsrc_addr[8:0];
assign out_sgpr_dest_data = in_rd_data[127:0];
assign out_sgpr_instr_done_wfid = in_wftag_resp[6:1];
assign out_vgpr_dest_addr = in_lddst_stsrc_addr[9:0];
assign out_vgpr_dest_data = in_rd_data;
assign out_vgpr_dest_wr_mask = in_exec_value;
assign out_vgpr_instr_done_wfid = in_wftag_resp[6:1];
assign out_tracemon_retire_pc = in_instr_pc;
assign out_gm_or_lds = in_gm_or_lds;
always @* begin
casex({in_ack, in_wftag_resp[0], in_lddst_stsrc_addr[11:10]})
4'b0_?_??:
begin
out_sgpr_dest_wr_en <= 4'b0;
out_vgpr_dest_wr_en <= 4'b0;
out_sgpr_instr_done <= 1'b0;
out_vgpr_instr_done <= 1'b0;
end
4'b1_1_10:
begin
out_sgpr_dest_wr_en <= 4'b0;
out_vgpr_dest_wr_en <= in_reg_wr_en;
out_sgpr_instr_done <= 1'b0;
out_vgpr_instr_done <= 1'b1;
end
4'b1_1_11:
begin
out_sgpr_dest_wr_en <= in_reg_wr_en;
out_vgpr_dest_wr_en <= 4'b0;
out_sgpr_instr_done <= 1'b1;
out_vgpr_instr_done <= 1'b0;
end
4'b1_0_10:
begin
out_sgpr_dest_wr_en <= 4'b0;
out_vgpr_dest_wr_en <= 4'b0;
out_sgpr_instr_done <= 1'b0;
out_vgpr_instr_done <= 1'b1;
end
4'b1_0_11:
begin
out_sgpr_dest_wr_en <= 4'b0;
out_vgpr_dest_wr_en <= 4'b0;
out_sgpr_instr_done <= 1'b1;
out_vgpr_instr_done <= 1'b0;
end
4'b1_?_0?:
begin
out_sgpr_dest_wr_en <= 4'b0;
out_vgpr_dest_wr_en <= 4'b0;
out_sgpr_instr_done <= 1'b0;
out_vgpr_instr_done <= 1'b0;
end
default:
begin
out_sgpr_dest_wr_en <= 4'bx;
out_vgpr_dest_wr_en <= 4'bx;
out_sgpr_instr_done <= 1'bx;
out_vgpr_instr_done <= 1'bx;
end
endcase
end
assign out_rfa_dest_wr_req = (|out_vgpr_dest_wr_en) | (|out_sgpr_dest_wr_en);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct per { string name; int score; } store[55]; bool cmp(per a, per b) { return a.score > b.score; } int main() { int n, tmp; cin >> n; for (int i = 0; i < n; i++) { cin >> store[i].name; cin >> tmp; store[i].score = 0; store[i].score += tmp * 100; cin >> tmp; store[i].score -= tmp * 50; for (int j = 0; j < 5; j++) { cin >> tmp; store[i].score += tmp; } } sort(store, store + n, cmp); cout << store[0].name << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void Max(T &a, T b) { if (b > a) a = b; } template <class T> void Min(T &a, T b) { if (b < a) a = b; } template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } int main() { ios::sync_with_stdio(false); int n; cin >> n; long long ans = 0; for (int i = (3), _t = (n + 1); i < _t; ++i) { ans += (i - 1) * i; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct line { int l, r; } p[510], q[510]; struct Point { long double x, y; } Q[10], tmp[10]; int vis[10]; long double A, B, C; int n, H, F, tot, cnt; void read(int &x) { char ch = getchar(); int mark = 1; for (; ch != - && (ch < 0 || ch > 9 ); ch = getchar()) ; if (ch == - ) mark = -1, ch = getchar(); for (x = 0; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 48; x *= mark; } inline bool cmp(line a, line b) { if (a.l == b.l) return a.r > b.r; return a.l < b.l; } inline long double Get(long double x, long double y) { return A * x + B * y + C; } inline long double Abs(long double x) { if (x < 0) return -x; return x; } inline long double dis(Point X, long double A, long double B, long double C) { return Abs(X.x * A + X.y * B + C) / sqrt(A * A + B * B); } inline long double Getsum(long double x1, long double y1, long double x2, long double y2) { return x1 * y2 - x2 * y1; } Point Getp(Point X, Point Y, long double A, long double B, long double C) { long double d1 = dis(X, A, B, C), d2 = dis(Y, A, B, C); Point Ans; Ans.x = (d2 * X.x + d1 * Y.x) / (d1 + d2); Ans.y = (d2 * X.y + d1 * Y.y) / (d1 + d2); return Ans; } void solve() { int tot = 0; int s1 = 0, s2 = 0; for (int k = 1; k <= cnt; k++) { double t = Get(Q[k].x, Q[k].y); if (t == 0) vis[k] = -1, s2++; else if (t > 0) vis[k] = 1, s1++; else vis[k] = -1, s2++; } if (s1 == 0) { cnt = 0; return; } else if (s2 == 0) return; Q[cnt + 1] = Q[1]; vis[cnt + 1] = vis[1]; for (int i = 1; i <= cnt; i++) { if (vis[i] == 1) tmp[++tot] = Q[i]; if (vis[i] * vis[i + 1] < 0) { tmp[++tot] = Getp(Q[i], Q[i + 1], A, B, C); } } cnt = tot; for (int i = 1; i <= cnt; i++) Q[i] = tmp[i]; } int main() { read(n); read(H); read(F); for (int i = 1; i <= n; i++) read(p[i].l), read(p[i].r); sort(p + 1, p + n + 1, cmp); q[++tot] = p[1]; for (int i = 2; i <= n; i++) { if (p[i].l > q[tot].r) q[++tot] = p[i]; else q[tot].r = max(q[tot].r, p[i].r); } long double sum = 0; for (int i = 1; i <= tot; i++) { long double d = (long double)(F + H) / (F - H) * (q[i].r - q[i].l); sum += (d + q[i].r - q[i].l) * H * 2; } for (int i = 1; i <= tot; i++) { for (int j = 1; j <= tot; j++) { cnt = 4; Q[1].x = q[i].l; Q[1].y = -H; Q[2].x = q[i].r; Q[2].y = -H; Q[3].x = (long double)(F + H) / (F - H) * q[i].r; Q[3].y = H; Q[4].x = (long double)(F + H) / (F - H) * q[i].l; Q[4].y = H; A = H - F; B = -q[j].l; C = F * q[j].l; A = -A; B = -B; C = -C; solve(); if (cnt <= 2) continue; A = H - F; B = -q[j].r; C = F * q[j].r; solve(); if (cnt <= 2) continue; long double over = 0; for (int k = 2; k < cnt; k++) over += Getsum(Q[k].x - Q[1].x, Q[k].y - Q[1].y, Q[k + 1].x - Q[1].x, Q[k + 1].y - Q[1].y) / 2; sum -= over; } } printf( %.7lf n , (double)sum); return 0; } |
module knightrider (
clk,
reset_,
led);
input clk;
input reset_;
output [7:0] led;
// Goal is to change LED pattern roughly every 250ms. The Papilio Pro
// clock runs at 32 MHz (32.25 ns period). If we increment a 21 bit counter
// on each clock cycle, it will roll over approximately each quarter second.
// (Arithmetic left to the interested student.)
reg [20:0] count;
// Board has eight LEDs; this vector represents the state of each LED. A one
// in the corresponding bit turns the LED on; a zero turns it off.
reg [7:0] led;
// A single bit indication of whether the LED animation is moving right
// to left. (Once the active LED is in the left-most position, we clear this
// value to signal we should start shifting right.)
reg left_shift;
// Change the LED pattern each time our counter rolls over. The shift signal
// will go high (1'b1) only for the single clock cycle where the counter is
// maxed out. This is combinitorial logic; the value is continuously updated.
assign shift = count == 21'h1FFFFF;
// Increment the counter at each clock tick; set counter to 0 on reset.
always@ (posedge clk or negedge reset_)
if (!reset_)
count <= 21'h0;
else
count <= count + 1;
// Shift the state of the LEDs each time the 'shift' signal is high (should
// be the case only one clock cycle per ~250ms). LED state has one bit set,
// the remaining seven cleared.
always@ (posedge clk or negedge reset_)
if (!reset_)
led[7:0] <= 8'b1000_0000;
else if (shift && left_shift) // Move 'on' LED left one position
led[7:0] <= led[7:0] << 1;
else if (shift) // Move right
led[7:0] <= led[7:0] >> 1;
// Track whether we're moving left or right. When the 'on' LED reaches the
// left-most position, clear this value. When it reaches the right-most
// position, set it.
always@ (posedge clk or negedge reset_)
if (!reset_)
left_shift <= 1'b0;
else if (led[7:0] == 8'b1000_0000)
left_shift <= 1'b0;
else if (led[7:0] == 8'b0000_0001)
left_shift <= 1'b1;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Triple-port synchronous 128x32 RAM
* Port 1, read-only
* Port 2, read-only
* Port 3, write-only
*/
module pfpu_tpram(
input sys_clk,
input [6:0] p1_a,
output reg [31:0] p1_d,
input [6:0] p2_a,
output reg [31:0] p2_d,
input p3_en,
input [6:0] p3_a,
input [31:0] p3_d
);
/*
* Duplicate the contents over two dual-port BRAMs
* Port A(WO) Port B(RO)
* Mem1 P3 P1
* Mem2 P3 P2
*/
reg [31:0] mem1[0:127];
always @(posedge sys_clk) begin
if(p3_en)
mem1[p3_a] <= p3_d;
p1_d <= mem1[p1_a];
end
reg [31:0] mem2[0:127];
always @(posedge sys_clk) begin
if(p3_en)
mem2[p3_a] <= p3_d;
p2_d <= mem2[p2_a];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_bleeder (
SHORT,
VPWR ,
VGND ,
VPB ,
VNB
);
input SHORT;
inout VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire gnd;
pulldown(gnd);
bufif1 (VPWR, gnd, SHORT);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; int a[N], n, l, r, ans; bool check(int k) { for (int i = 1; i <= n; ++i) { if (1LL * k * (i - 1) > a[i]) return false; if (1LL * k * (n - i) > a[i]) return false; } return true; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); l = 0, r = 1e9, ans = 0; while (l <= r) { int mid = l + r >> 1; if (check(mid)) { ans = mid; l = mid + 1; } else r = mid - 1; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, f[1000010], a[1000010]; char s[1000010]; bool vis[1000010]; long long Pow(int x) { if (x < 0) return 0; if (x == 0) return 1; long long ans = Pow(x >> 1); ans = ans * ans % 1000000007ll; if (x & 1) ans = (ans * 26ll) % 1000000007ll; return ans; } long long ans; int main() { scanf( %d%d , &n, &m); if (m == 0) { printf( %lld n , Pow(n)); return 0; } scanf( %s , s); int len = strlen(s); for (int i = 1, j; i < len; i++) { for (j = f[i]; j && s[i] != s[j]; j = f[j]) ; f[i + 1] = s[i] == s[j] ? j + 1 : 0; } for (int i = f[len]; i; i = f[i]) vis[len - i] = true; scanf( %d , &a[1]); a[1]--; ans = Pow(a[1]); for (int i = 2; i <= m; i++) { scanf( %d , &a[i]); a[i]--; if (a[i] - a[i - 1] < len) { if (!vis[a[i] - a[i - 1]]) { printf( 0 ); return 0; } } else ans = (ans * Pow(a[i] - a[i - 1] - len)) % 1000000007ll; } printf( %lld n , ans * Pow(n - a[m] - len) % 1000000007ll); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000000007; vector<int> rec[100008]; int dp[2][100008], a[100008]; int fun(int minn, int val) { int ll = 0, rr, ss = rec[val].size(); if (ss == 0) return maxn; else if (rec[val][0] >= minn) return rec[val][0] + 1; rr = ss; while (ll + 1 != rr) { int mid = (ll + rr) / 2; if (rec[val][mid] < minn) ll = mid; else rr = mid; } if (rr == ss) return maxn; return rec[val][rr] + 1; } int main() { int n, m, s, e, i, cc, ans; bool f; scanf( %d%d%d%d , &n, &m, &s, &e); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i <= 100000; i++) rec[i].clear(); for (i = 0; i < m; i++) { int tmp; scanf( %d , &tmp); rec[tmp].push_back(i); } memset(dp, 0, sizeof(dp)); cc = 1; ans = 0; f = true; while (f) { f = false; for (i = ans; i < n; i++) { if (i != 0 && dp[1 - cc][i - 1] != maxn) { dp[cc][i] = fun(dp[1 - cc][i - 1], a[i]); if (i != ans) dp[cc][i] = min(dp[cc][i], dp[cc][i - 1]); if (dp[cc][i] + i + 1 + (ans + 1) * e <= s) f = true; } else if (i == 0) { dp[cc][i] = fun(0, a[i]); if (i != ans) dp[cc][i] = min(dp[cc][i], dp[cc][i - 1]); if (dp[cc][i] + i + 1 + (ans + 1) * e <= s) f = true; } else dp[cc][i] = maxn; } if (f) ++ans; cc = 1 - cc; } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const double pai = acos(-1); const double eps = 1e-8; const long long mod = 1e9 + 7; const int MXN = 1e6 + 5; vector<int> v[MXN]; int c[MXN]; int suf[MXN]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { int le; scanf( %d , &le); while (le--) { int aa; scanf( %d , &aa); v[i].push_back(aa); } int mi = INT_MAX; for (auto j : v[i]) { if (j > mi) c[i] = 1; mi = min(mi, j); } sort(v[i].begin(), v[i].end()); } long long gg = 0; for (int i = 1; i <= n; i++) { if (c[i]) { gg++; continue; } suf[v[i].back()]++; } for (int i = 1e6 - 1; i >= 0; i--) suf[i] = suf[i] + suf[i + 1]; long long ans = 0; for (int i = 1; i <= n; i++) { if (c[i]) ans = ans + (long long)n; else ans = ans + (long long)suf[v[i][0] + 1] + gg; } cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_SYMBOL_V
`define SKY130_FD_SC_HS__A32O_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:51:15 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top ip_design_auto_pc_0 -prefix
// ip_design_auto_pc_0_ ip_design_auto_pc_0_stub.v
// Design : ip_design_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
module ip_design_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_4_V
`define SKY130_FD_SC_LS__MUX2_4_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2_4 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s; cin >> s; if (n == 1 && k == 1) { cout << 0 << endl; return 0; } if (s[0] != 1 && k) { k--; s[0] = 1 ; } for (int i = 1; i < n && k; i++) { if (s[i] != 0 ) { s[i] = 0 ; k--; } } cout << s << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long a, b; cin >> a >> b; if (b - a > 5) { cout << 0 << n ; } else { long long val = 1; for (long long j = a + 1; j <= b; j++) { val *= (j % 10); val %= 10; } cout << val << n ; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); solve(); } |
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << << *it << = << a; err(++it, args...); } template <typename T, typename U> inline void min_self(T& x, U y) { if (y < x) x = y; } template <typename T, typename U> inline void max_self(T& x, U y) { if (x < y) x = y; } template <class T1, class T2> ostream& operator<<(ostream& out, pair<T1, T2> pair) { return out << ( << pair.first << , << pair.second << ) ; } template <class T> ostream& operator<<(ostream& out, vector<T> vec) { out << ( ; for (auto& v : vec) out << v << , ; return out << ) ; } template <class T> ostream& operator<<(ostream& out, set<T> vec) { out << ( ; for (auto& v : vec) out << v << , ; return out << ) ; } template <class L, class R> ostream& operator<<(ostream& out, map<L, R> vec) { out << ( ; for (auto& v : vec) out << [ << v.first << , << v.second << ] ; return out << ) ; } template <class A, class B> istream& operator>>(istream& in, pair<A, B>& a) { return in >> a.first >> a.second; } template <class A> istream& operator>>(istream& in, vector<A>& a) { for (A& i : a) in >> i; return in; } long long XX[4] = {-1, 0, 1, 0}; long long YY[4] = {0, -1, 0, 1}; void solve() { long long n, res = 0; cin >> n; vector<pair<long long, long long>> a(n); for (long long i = 0; i <= n - 1; i++) cin >> a[i]; sort(a.begin(), a.end()); long long maxi = a[0].second; for (long long i = 1; i <= n - 1; i++) { if (a[i].second < maxi && a[i].first > a[i - 1].first) { res++; } max_self(maxi, a[i].second); } cout << res << n ; return; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) { solve(); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
//
// Example module to create problem.
//
// generate a 64 bit value with bits
// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
// all other bits zero.
module t_math_imm2 (/*AUTOARG*/
// Outputs
LogicImm, LowLogicImm, HighLogicImm,
// Inputs
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
);
input [4:0] LowMaskSel_Top, HighMaskSel_Top;
input [4:0] LowMaskSel_Bot, HighMaskSel_Bot;
output [63:0] LogicImm;
output [63:0] LowLogicImm, HighLogicImm;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
genvar i;
generate
for (i=0;i<64;i=i+1) begin : MaskVal
if (i >= 32) begin
assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]);
assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]);
end
else begin
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]);
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]);
end
end
endgenerate
assign LogicImm = LowLogicImm & HighLogicImm;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O21BA_FUNCTIONAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_FUNCTIONAL_PP_V |
//#############################################################################
//# Function: Carry Save Adder (4:2) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa42 #( parameter DW = 1 // data width
)
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
input [DW-1:0] in2,//input
input [DW-1:0] in3,//input
input cin,//intra stage carry in
output cout, //intra stage carry out (2x sum)
output [DW-1:0] s, //sum
output [DW-1:0] c //carry (=2x sum)
);
wire [DW-1:0] sum_int;
wire [DW:0] carry_int;
//Edges
assign carry_int[0] = cin;
assign cout = carry_int[DW];
//Full Adders
oh_csa32 #(.DW(DW))
fa0 (//inputs
.in0(in0[DW-1:0]),
.in1(in1[DW-1:0]),
.in2(in2[DW-1:0]),
//outputs
.c(carry_int[DW:1]),
.s(sum_int[DW-1:0]));
oh_csa32 #(.DW(DW))
fa1 (//inputs
.in0(in3[DW-1:0]),
.in1(sum_int[DW-1:0]),
.in2(carry_int[DW-1:0]),
//outputs
.c(c[DW-1:0]),
.s(s[DW-1:0]));
endmodule // oh_csa42
|
#include <bits/stdc++.h> using namespace std; using ld = long double; using ll = long long; using pii = pair<int, int>; using pll = pair<ll, ll>; using vi = vector<int>; const int oo = 1e9 + 7; const ll loo = 1e18; ll modpow(ll a, ll b) { ll res = 1; while (b) { if (b & 1) res = res * a % oo; a = a * a % oo; b /= 2; } return res; } ll gcd(ll a, ll b) { return a == 0 ? b : gcd(b % a, a); } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int N = 5e5 + 7; int n, k, m; using point = complex<ll>; point p[N]; ld dist[N]; vector<int> arms[N]; int gr[N]; int num; ld cross(point a, point b) { return (conj(a) * b).imag(); } ld dot(point a, point b) { return (conj(a) * b).real(); } void input() { map<pair<ll, ll>, int> id; m = 0; for (int i = 0; i < n; i++) { ll a, b; cin >> a >> b; p[i] = point(a, b); dist[i] = sqrt(dot(p[i], p[i])); if (a == 0 && b == 0) continue; ll g = gcd(abs(a), abs(b)); pair<ll, ll> ash = make_pair(a / g, b / g); if (!id.count(ash)) id[ash] = m++; arms[id[ash]].push_back(i); gr[i] = id[ash]; } for (int i = 0; i < m; i++) { sort(begin(arms[i]), end(arms[i]), [&](int i, int j) { return dist[i] < dist[j]; }); } } ld option1() { priority_queue<pair<ld, int>> pq; for (int i = 0; i < m; i++) { for (int t = 0; t < min(k / 2, (int)arms[i].size()); t++) { ld wei = (k - 2 * t - 1) * dist[arms[i][arms[i].size() - 1 - t]]; pq.push(make_pair(wei, arms[i][arms[i].size() - 1 - t])); } } for (int i = 0; i < n; i++) if (p[i] == point(0)) { pq.push(make_pair(0, i)); } ld ans = 0; while (pq.size() && num < k) { auto pp = pq.top(); pq.pop(); ans += pp.first; num++; } return ans; } ld option2(int i, ld ans) { int half = k / 2; int s = num - half; for (int t = 0; t < arms[i].size() - half; t++) { ans += dist[arms[i][t]] * ((t + s) - (k - 1 - t - s)); if (t + 1 + num == k) break; } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k; input(); ld ans = option1(); if (num < k) { ld res = 0; for (int i = 0; i < m; i++) if (2 * (n - arms[i].size()) <= k) { res = max(res, option2(i, ans)); } ans = res; } cout << setprecision(40) << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int shi(int a[], int k, int len) { int s = 0, j; for (j = len - 1; j >= 0; j--) { s = s * k + a[j]; } return s; } int bian(int n, int k) { int i; for (i = 0; n > 0; i++) { n /= k; } return i; } int change(int a[1000], int n) { int i; for (i = 0; n > 0; i++) { a[i] = n % 10; n /= 10; } return i; } int main() { int a, b; int ta[1000], tb[1000]; int i, la, lb; while (scanf( %d%d , &a, &b) != -1) { int max = 0; la = change(ta, a); lb = change(tb, b); for (i = 0; i < la; i++) { if (ta[i] > max) max = ta[i]; } for (i = 0; i < lb; i++) { if (tb[i] > max) max = tb[i]; } max += 1; int sa = shi(ta, max, la), sb = shi(tb, max, lb); int sum = sa + sb; int ss = bian(sum, max); printf( %d n , ss); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2500 + 10; int n; pair<int, int> p[MAXN]; pair<int, int> sec[MAXN]; int sz; int half(pair<int, int> p) { assert(p.first || p.second); return p.second > 0 || (p.second == 0 && p.first < 0); } long long dot(pair<int, int> a, pair<int, int> b) { return 1ll * a.first * b.first + 1ll * a.second * b.second; } long long cross(pair<int, int> a, pair<int, int> b) { return 1ll * a.first * b.second - 1ll * a.second * b.first; } int nxt(int x) { return x + 1 == sz ? 0 : x + 1; } void solve() { cin >> n; for (int i = 0; i < n; i++) cin >> p[i].first >> p[i].second; long long ans = 0; for (int i = 0; i < n; i++) { sz = 0; for (int j = 0; j < n; j++) if (i ^ j) sec[sz++] = {p[j].first - p[i].first, p[j].second - p[i].second}; sort(sec, sec + sz, [](pair<int, int> a, pair<int, int> b) { return make_tuple(half(a), 0, dot(a, b)) < make_tuple(half(b), cross(a, b), dot(a, b)); }); long long temp = 0; int cur = 0; for (int j = 0; j < sz; j++) { if (cur == j) cur = nxt(j); while (cur != j && cross(sec[j], sec[cur]) > 0) cur = nxt(cur); int ln = cur > j ? cur - j : sz - (j - cur); temp += 1ll * (ln - 1) * (ln - 2) * (ln - 3) / 6; } ans += 1ll * (n - 1) * (n - 2) * (n - 3) * (n - 4) / 24 - temp; } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int te = 1; for (int w = 1; w <= te; w++) { solve(); } return 0; } |
// DESCRIPTION: Verilator: Unsupported tristate construct error
//
// This is a compile only regression test of tristate handling for bug514
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Rob Stoddard.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
out,
// Inputs
data, up_down, clk, reset
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
//input [7:0] data ;
input [7:0] data;
input up_down, clk, reset;
//------------Internal Variables--------
reg [7:0] out;
logic [7:0] q_out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= q_out;
end
// verilator lint_off PINMISSING
sub_mod sub_mod
(
.clk(clk),
.data(data),
.reset(reset),
.q(q_out)
);
// verilator lint_on PINMISSING
endmodule
module sub_mod (/*AUTOARG*/
// Outputs
q, test_out,
// Inouts
test_inout,
// Inputs
data, clk, reset
);
//-----------Input Ports---------------
input [7:0] data /*verilator public*/;
input clk, reset;
inout test_inout; // Get rid of this, the problem goes away.
//-----------Output Ports---------------
output [7:0] q;
output test_out; // Not assigned, no problem.
logic [7:0] que;
// Uncomment this line, the error goes away.
//assign test_inout = que;
assign q = que;
always @ ( posedge clk)
if (~reset) begin
que <= 8'b0;
end else begin
que <= data;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long M = 1000000007; signed main() { long long t; cin >> t; for (long long u = 0; u < t; u++) { long long k = 0; vector<long long> v; string s; cin >> s; for (long long i = 0; i < s.size(); i++) { if (i + 4 < s.size() && (s[i] == t && s[i + 1] == w && s[i + 2] == o && s[i + 3] == n && s[i + 4] == e )) { v.push_back(i + 3); i += 4; } else if (i + 2 < s.size()) { if ((s[i] == o && s[i + 1] == n && s[i + 2] == e ) || (s[i] == t && s[i + 1] == w && s[i + 2] == o )) { v.push_back(i + 2); i += 2; } } } cout << v.size() << endl; for (long long i = 0; i < v.size(); i++) cout << v[i] << ; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int euclid(int a, int b, int &x, int &y) { if (!a) { x = 0; y = 1; return b; } int _x, _y; int g = euclid(b % a, a, _x, _y); x = _y - b / a * _x; y = _x; return g; } void relax(int &obj, int C3, int C4, int C5, int _k3, int k4, int _k5, int &K3, int &K4, int &K5) { int f = abs(C3 * _k3 - C4 * k4) + abs(C4 * k4 - C5 * _k5); if (f < obj) { obj = f; K3 = _k3, K4 = k4, K5 = _k5; } } int main() { int n, S, a[333]; cin >> n >> S; for (int i = 0; i < n; ++i) { cin >> a[i]; } int C[11] = {0}; for (int _n(n), i(0); i < _n; i++) C[a[i]]++; int K3 = 1011111111, K4 = 1011111111, K5 = 1011111111, F = 1011111111; int ek3 = 1011111111, ek5 = 1011111111; const int D = euclid(C[3], C[5], ek3, ek5); for (int k4 = 0; k4 * C[4] <= S; ++k4) { const int REM = S - k4 * C[4]; if (REM % D) continue; int k3 = ek3 * (REM / D), k5 = ek5 * (REM / D); assert(k3 * C[3] + k5 * C[5] == REM); int idx[] = {(k4 - k3 + C[5] / D - 1) / (C[5] / D), (k5 - k4 + C[3] / D - 1) / (C[3] / D), (k5 - k4 * C[4] / C[5] + C[3] / D - 1) / (C[3] / D) + 2, (k4 * C[4] / C[3] - k3 + C[5] / D - 1) / (C[5] / D) + 2}; for (int o = 0; o < 4; ++o) { int j = idx[o]; for (int it = 0; it < 5; --j, ++it) { int _k3 = k3 + j * (C[5] / D); int _k5 = k5 - j * (C[3] / D); if (_k3 < 0) continue; if (_k3 > k4) continue; if (_k5 < k4) continue; relax(F, C[3], C[4], C[5], _k3, k4, _k5, K3, K4, K5); } } } if (F == 1011111111) { cout << -1 << endl; } else { printf( %d %d %d n , K3, K4, K5); } return 0; } |
//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// Version and Release Control Information:
//
// File Revision : $Revision: 275084 $
// File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $
//
// Release Information : Cortex-M0 DesignStart-r1p0-00rel0
//------------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//------------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// Abstract : Testbench for the Cortex-M0 example system
//-----------------------------------------------------------------------------
//
// Modified by Ronan Barzic () to add support :
// - Xilinx simulation and synthesis
// - Icarus iverilog simulation
`timescale 1ns/1ps
`include "cmsdk_mcu_defs.v"
module tb_cmsdk_mcu;
`include "tb_defines.v"
parameter ROM_ADDRESS_SIZE = 16;
wire XTAL1; // crystal pin 1
wire XTAL2; // crystal pin 2
wire NRST; // active low reset
wire [15:0] P0; // Port 0
wire [15:0] P1; // Port 1
//Debug tester signals
wire nTRST;
wire TDI;
wire SWDIOTMS;
wire SWCLKTCK;
wire TDO;
wire PCLK; // Clock for UART capture device
wire [5:0] debug_command; // used to drive debug tester
wire debug_running; // indicate debug test is running
wire debug_err; // indicate debug test has error
wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
// This signal is controlled by software,
// Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
// the command, use "UartPutc((char) 0x11)" to send debug test
// enable command, use "UartPutc((char) 0x12)" to send debug test
// disable command. Refer to tb_uart_capture.v file for detail
parameter BE = 0; // Big or little endian
parameter BKPT = 4; // Number of breakpoint comparators
parameter DBG = 1; // Debug configuration
parameter NUMIRQ = 32; // NUM of IRQ
parameter SMUL = 0; // Multiplier configuration
parameter SYST = 1; // SysTick
parameter WIC = 1; // Wake-up interrupt controller support
parameter WICLINES = 34; // Supported WIC lines
parameter WPT = 2; // Number of DWT comparators
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
cmsdk_mcu
#(.BE (BE),
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.NUMIRQ (NUMIRQ), // NUMIRQ
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT) // Number of DWT comparators
)
u_cmsdk_mcu (
.XTAL1 (XTAL1), // input
.XTAL2 (XTAL2), // output
.NRST (NRST), // active low reset
.P0 (P0),
.P1 (P1),
.nTRST (nTRST), // Not needed if serial-wire debug is used
.TDI (TDI), // Not needed if serial-wire debug is used
.TDO (TDO), // Not needed if serial-wire debug is used
.SWDIOTMS (SWDIOTMS),
.SWCLKTCK (SWCLKTCK)
);
// --------------------------------------------------------------------------------
// Source for clock and reset
// --------------------------------------------------------------------------------
cmsdk_clkreset u_cmsdk_clkreset(
.CLK (XTAL1),
.NRST (NRST)
);
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
assign PCLK = XTAL2;
cmsdk_uart_capture u_cmsdk_uart_capture(
.RESETn (NRST),
.CLK (PCLK),
.RXD (P1[5]), // UART 2 use for StdOut
.DEBUG_TESTER_ENABLE (debug_test_en),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
// UART connection cross over for UART test
assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
// --------------------------------------------------------------------------------
// Debug tester connection -
// --------------------------------------------------------------------------------
// No debug connection for Cortex-M0 DesignStart
assign nTRST = NRST;
assign TDI = 1'b1;
assign SWDIOTMS = 1'b1;
assign SWCLKTCK = 1'b1;
bufif1 (P0[31-16], debug_running, debug_test_en);
bufif1 (P0[30-16], debug_err, debug_test_en);
pullup (debug_running);
pullup (debug_err);
// --------------------------------------------------------------------------------
// Misc
// --------------------------------------------------------------------------------
`ifndef SDF_SIM
task load_program_memory;
reg [1024:0] filename;
reg [7:0] memory [1<<ROM_ADDRESS_SIZE:0]; // byte type memory
integer i;
reg [31:0] tmp;
integer dummy;
begin
filename = 0;
dummy = $value$plusargs("program_memory=%s", filename);
if(filename ==0) begin
$display("WARNING! No content specified for program memory");
end
else begin
$display("-I- Loading <%s>",filename);
$readmemh (filename, memory);
for(i=0; i<((1<<ROM_ADDRESS_SIZE)/4); i=i+1) begin
tmp[7:0] = memory[i*4+0];
tmp[15:8] = memory[i*4+1];
tmp[23:16] = memory[i*4+2];
tmp[31:24] = memory[i*4+3];
u_cmsdk_mcu.u_ahb_rom.U_RAM.RAM[i] = tmp;
end
end
end
endtask // load_program_memory
`endif
// Format for time reporting
initial $timeformat(-9, 0, " ns", 0);
`ifdef IVERILOG
initial begin
load_program_memory;
$dumpfile("tb_cmsdk_mcu.vcd");
$dumpvars(0,tb_cmsdk_mcu);
end
`endif
always@(posedge `hclk) begin
if(`pc === (32'h00000100 + 4)) begin
$write("%t -I- Test Ended - Return value : %d \n",$time,`r0);
$finish(`r0);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; const int INF = 0x3f3f3f3f; int a[110][110]; int dp[100][2]; const int M = 1e5 + 10; int vis[M], prime[M]; void prim() { memset(vis, 0, sizeof(vis)); memset(prime, 0, sizeof(prime)); int cun = 1; for (int i = 2; i <= M; i++) { if (vis[i] == 0) { prime[cun++] = i; } for (int j = 1; j <= cun && prime[j] * i < M; j++) { vis[i * prime[j]] = 1; if (i % prime[j] == 0) { break; } } } } int main() { int t; cin >> t; int sum = 0; prim(); while (t--) { long long n, m; cin >> n >> m; int temp = n + m - 2; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) a[i][j] += i - i + j - j; } for (int i = 0; i <= (temp / 2); i++) { dp[i][0] = 0; dp[i][1] = 0; } if (temp % 2) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int fl = i + j; if (fl <= temp / 2) dp[fl][a[i][j]]++; else dp[temp - fl][a[i][j]]++; } } int ans = 0; for (int i = 0; i <= temp / 2; i++) { ans += min(dp[i][0], dp[i][1]); } cout << ans << endl; } else { int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int fl = i + j; if (fl == temp / 2) continue; if (fl < temp / 2) dp[fl][a[i][j]]++; else { dp[temp - fl][a[i][j]]++; } } } for (int i = 0; i <= (temp / 2 - 1); i++) { ans += min(dp[i][0], dp[i][1]); } cout << ans << endl; } } return 0; } |
// --------------------------------------------------------------------
// ng_CTR.v - PRIORITY COUNTER
//
// Read Bus: (octal counter addr)
// 34 = cntr 1 (OVCTR)
// 35 = cntr 2 (TIME2)
// 36 = cntr 3 (TIME1)
// 37 = cntr 4 (TIME3)
// 40 = cntr 5 (TIME4)
//
// SB2 SB1
// 0 0 no counter or PINC and MINC simul active
// 0 1 PINC
// 1 0 MINC
// 1 1 not allowed
//
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_CTR(
input CLK2, // Clock Pulse 2
input [100:0] CP, // Control Pulse
input [ 15:0] WRITE_BUS, // Control Pulse
input F10X, // Clock divided by 10
output SB01,SB02, // Sequence Bus
output [ 15:0] CTR_BUS, // CTR Module output
output CPO4,CPO5 // Counter P Overflow
);
// --------------------------------------------------------------------
// JTAG Debugging Probes
// --------------------------------------------------------------------
// 1 1 3 5 5 1
// JTAG_Probe CTR_TST16(.probe ( { CPO5, CPO4, sel_ctr, pri_level, plus_in, min_in} ));
// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAG_Probe CTR_TST2(.probe({CPO5,CPO4, Yp,Ym,WOVR, SIGN,OVER, sel_ctr, WOVC, WPCTR, SB02,SB01, CT_P2P, plus_in[2]} ));
JTAG_Source1 Sourc1_F10X(.probe(F10X),.source(iF10X));
wire iF10X;
wire sTime1 = iF10X;
wire sTime2 = iF10X;
wire sTime4 = iF10X;
// --------------------------------------------------------------------
// General Control Signals
// --------------------------------------------------------------------
wire GENRST = CP[`CPX(`GENRST)]; // General reset signal
wire WPCTR = CP[`CPX(`WPCTR) ]; // Write PCTR (latch priority counter sequence)
wire WOVC = CP[`CPX(`WOVC) ]; // Write overflow counter
wire WOVR = CP[`CPX(`WOVR) ]; // Write overflow
wire OVER = WRITE_BUS[14]; // bit 14 set is overflow condition
wire SIGN = WRITE_BUS[15]; // bit 15 set is negative number
// --------------------------------------------------------------------
// Counter Trigger Registers
//
// NOTE: JK FF can be instantiated using this code:
// always@(negedge CLK or negedge CLN or negedge PRN)
// if (!CLN) Q <= 0;
// else if(!PRN) Q <= 1;
// else Q <= ~Q & J | Q & ~K;
// --------------------------------------------------------------------
reg [4:0] plus_in_i; // Plus increment Register
reg [4:0] plus_in; // Plus increment Register
reg min_in_i ; // Minus increment Register
reg min_in ; // Minus increment Register
wire CT_RST = !(!GENRST & CLK2);
wire CT_RT2 = CT_RST & resetP[1];
wire CT_RT1 = CT_RST & resetP[2];
wire CT_RT3 = CT_RST & resetP[3];
wire CT_RT4 = CT_RST & resetP[4];
always @(posedge CT_P2P or negedge CT_RT2)
if(!CT_RT2) plus_in_i[1] <= 1'b0;
else if(!CT_P2P) plus_in_i[1] <= 1'b1;
always @(negedge CT_P2P or negedge CT_RT2) plus_in[1] <= plus_in_i[1];
always @(posedge F10X or negedge CT_RT1 or posedge sTime1)
if(!CT_RT1) plus_in_i[2] <= 1'b0;
else if(sTime1) plus_in_i[2] <= 1'b1;
else if(F10X) plus_in_i[2] <= 1'b1;
always @(negedge F10X or negedge CT_RT1 or posedge sTime1) plus_in[2] <= plus_in_i[2];
always @(posedge F10X or negedge CT_RT3 or posedge sTime2)
if(!CT_RT3) plus_in_i[3] <= 1'b0;
else if(sTime2) plus_in_i[3] <= 1'b1;
else if(F10X) plus_in_i[3] <= 1'b1;
always @(negedge F10X or negedge CT_RT3 or posedge sTime2) plus_in[3] <= plus_in_i[3];
always @(posedge F10X or negedge CT_RT4 or posedge sTime4)
if(!CT_RT4) plus_in_i[4] <= 1'b0;
else if(sTime4) plus_in_i[4] <= 1'b1;
else if(F10X) plus_in_i[4] <= 1'b1;
always @(negedge F10X or negedge CT_RT4 or posedge sTime4) plus_in[4] <= plus_in_i[4];
// --------------------------------------------------------------------
// Overflow Counter section
// --------------------------------------------------------------------
wire CT_R1P = CT_RST & resetP[0];
wire CT_P1P = !(!SIGN & OVER & CLK2 & !WOVC);
always @(posedge CT_P1P or negedge CT_R1P) // OVCTR
if(!CT_R1P) plus_in_i[0] <= 1'b0;
else if(!CT_P1P) plus_in_i[0] <= 1'b1;
always @(negedge CT_P1P or negedge CT_R1P) plus_in[0] <= plus_in_i[0];
wire CT_R1M = CT_RST & resetM;
wire CT_P1M = !(SIGN & !OVER & CLK2 & !WOVC);
always @(posedge CT_P1M or negedge CT_R1M) // OVCTR
if(!CT_R1M) min_in_i <= 1'b0;
else if(!CT_P1M) min_in_i <= 1'b1;
always @(negedge CT_P1M or negedge CT_R1M) min_in <= min_in_i;
// --------------------------------------------------------------------
// Register Storage
// --------------------------------------------------------------------
reg [4:0] plus_cnt; // Plus Count Sync Register
reg min_cnt; // Minus Count Sync Register
// --------------------------------------------------------------------
// Instantiate Plus Count and Minus Count Registers
// --------------------------------------------------------------------
always @(posedge CLK2) begin
if(!GENRST) begin
plus_cnt <= 5'h00; // Clear to 0
min_cnt <= 1'b0; // Clear to 0
end
else if(!WPCTR) begin // was !(!WPCTR & CLK2);
plus_cnt <= plus_in; // Load
min_cnt <= min_in; // Load
end
end
// --------------------------------------------------------------------
// Prioritize
// --------------------------------------------------------------------
wire [4:0] pri_level;
assign pri_level[4] = plus_cnt[0] | min_cnt; // Highest Priority level
assign pri_level[3] = plus_cnt[1]; // Higher
assign pri_level[2] = plus_cnt[2]; // Medium
assign pri_level[1] = plus_cnt[3]; // Lower
assign pri_level[0] = plus_cnt[4]; // Lowest Priority level
reg [2:0] sel_ctr; // selected counter
always @(pri_level) begin
casex(pri_level)
5'b1XXXX : sel_ctr <= 3'b000; // priority 1, selctr = 0, highest
5'b01XXX : sel_ctr <= 3'b001; // priority 2, selctr = 1
5'b001XX : sel_ctr <= 3'b010; // priority 3, selctr = 2
5'b0001X : sel_ctr <= 3'b011; // priority 4, selctr = 3
5'b00001 : sel_ctr <= 3'b100; // priority 5, selctr = 4, lowest
default : sel_ctr <= 3'b111; // priority X, selctr = 7, default case
endcase
end
wire sel_EO = |pri_level; // ==1 if were any active
assign CTR_BUS = 16'o0034 + sel_ctr; // Map to registers o34 - o40
// --------------------------------------------------------------------
// PINC mux & MINC mux
// --------------------------------------------------------------------
reg Yp;
always @(sel_ctr or sel_EO or plus_cnt) begin
if(sel_EO)
case(sel_ctr)
3'b000 : Yp <= plus_cnt[0]; // priority 1, selctr = 0
3'b001 : Yp <= plus_cnt[1]; // priority 2, selctr = 1
3'b010 : Yp <= plus_cnt[2]; // priority 3, selctr = 2
3'b011 : Yp <= plus_cnt[3]; // priority 4, selctr = 3
3'b100 : Yp <= plus_cnt[4]; // priority 5, selctr = 4
default : Yp <= 1'b0; // priority X, selctr = 7
endcase
else Yp <= 1'b0;
end
reg Ym;
always @(sel_ctr or sel_EO or min_cnt) begin
if(sel_EO)
case(sel_ctr)
3'b000 : Ym <= min_cnt; // priority 1, selctr = 0
default : Ym <= 1'b0; // priority X, selctr = 7
endcase
else Ym <= 1'b0;
end
assign SB01 = !(!Yp | Ym);
assign SB02 = !( Yp | !Ym);
// Yp Ym SB1 SB2
// 0 0 0 0
// 0 1 0 1
// 1 0 1 0 <-
// 1 1 0 0
//
// --------------------------------------------------------------------
// Reset Logic; PINC, MINC demux
// --------------------------------------------------------------------
reg [4:0] resetP; // PINC dmx
always @(posedge CLK2) begin
if(!WOVR & Yp) begin
case(sel_ctr)
3'b000 : resetP <= 5'b11110; // Priority 1
3'b001 : resetP <= 5'b11101; // Priority 2
3'b010 : resetP <= 5'b11011; // Priority 3
3'b011 : resetP <= 5'b10111; // Priority 4
3'b100 : resetP <= 5'b01111; // Priority 5
default: resetP <= 5'b11111; // Priority 7
endcase
end
else resetP <= 5'b11111;
end
reg resetM; // MINC dmx
always @(posedge CLK2) begin
if(!WOVR & Ym) begin
case(sel_ctr)
3'b000 : resetM <= 1'b0; // Priority 1
default: resetM <= 1'b1; // Priority X
endcase
end
else resetM <= 1'b1;
end
// --------------------------------------------------------------------
// Control pulse Logic:
// --------------------------------------------------------------------
wire CT_EP = !SIGN & OVER & !WOVR;
reg [2:0] ctr_ovr; // Cntr P Overflow
always @(posedge CLK2) begin
if(CT_EP) begin
case(sel_ctr) // selected counter
3'd2 : ctr_ovr <= 3'b110;
3'd3 : ctr_ovr <= 3'b101;
3'd4 : ctr_ovr <= 3'b011;
default: ctr_ovr <= 3'b111;
endcase
end
else ctr_ovr <= 3'b111;
end
assign CPO4 = ctr_ovr[1];
assign CPO5 = ctr_ovr[2];
wire CT_P2P = ctr_ovr[0];
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int f; vector<string> cur; void upd(string s, int x, int y, int o) { int dx = 0, dy = 1; if (o) swap(dx, dy); for (int i = 0; i < s.size(); i++) { int xx = x + dx * i; int yy = y + dy * i; if (cur[xx][yy] == . || cur[xx][yy] == s[i]) { cur[xx][yy] = s[i]; } else { f = 0; } } } int main() { vector<string> a(6); for (auto &x : a) { cin >> x; } sort((a).begin(), (a).end()); vector<string> ans = { Z }; ans[0][0]++; vector<string> ans0 = ans; do { f = 1; vector<int> b; vector<int> c; for (int t = 0; t < 6; t += 3) { int mx = 0; int s = 0; for (int i = t; i < t + 3; i++) { s += a[i].size(); mx = max(mx, (int)a[i].size()); } for (int i = t; i < t + 3; i++) { if (a[i].size() == mx) { b.push_back(i); break; } } if (s - 2 * mx != 1) { f = 0; } } for (int i = 0; i < 6; i++) { if (i != b[0] && i != b[1]) { c.push_back(i); } } if (f) { vector<int> bb, cc; for (auto x : b) bb.push_back(a[x].size()); for (auto x : c) cc.push_back(a[x].size()); string t; for (int i = 0; i < bb[1]; i++) { t.push_back( . ); } cur = vector<string>(bb[0], t); upd(a[c[0]], 0, 0, 1); upd(a[c[2]], 0, 0, 0); upd(a[b[0]], 0, cc[2] - 1, 1); upd(a[b[1]], cc[0] - 1, 0, 0); upd(a[c[1]], cc[0] - 1, bb[1] - 1, 1); upd(a[c[3]], bb[0] - 1, cc[2] - 1, 0); } if (f) { if (cur < ans) ans = cur; } } while (next_permutation((a).begin(), (a).end())); if (ans == ans0) { cout << Impossible << endl; return 0; } for (auto s : ans) { cout << s << endl; } return 0; } |
`include "logfunc.h"
// FAST 2 port SRAM:
//
// Fast means 1 cycle read/write
//
// Max total bits is 1Kbytes (Size*Width)
//
// Size must be between 8 and 64
// (anything smaller is not worth it in SRAM, but OK)
//
module ram_2port_fast #(parameter Width = 64, Size=128, Forward=0) (
input clk
,input reset
,input req_wr_valid
,output req_wr_retry
,input [`log2(Size)-1:0] req_wr_addr
,input [Width-1:0] req_wr_data
,input req_rd_valid
,output req_rd_retry
,input [`log2(Size)-1:0] req_rd_addr
,output ack_rd_valid
,input ack_rd_retry
,output [Width-1:0] ack_rd_data
);
logic [Width-1:0] ack_rd_data_next;
logic [Width-1:0] ack_wr_data_next;
async_ram_2port
#(.Width(Width), .Size(Size))
ram (
// 1st port: write
.p0_pos (req_wr_addr)
,.p0_enable (req_wr_valid)
,.p0_in_data (req_wr_data)
,.p0_out_data (ack_wr_data_next)
// 2nd port: Read
,.p1_pos (req_rd_addr)
,.p1_enable (1'b0) // Never WR
,.p1_in_data ('b0)
,.p1_out_data (ack_rd_data_next)
);
// If it is a write, the retry has no effect. We can write one per cycle
// (token consumed)
assign req_wr_retry = 0;
fflop #(.Size(Width)) f1 (
.clk (clk),
.reset (reset),
.din (ack_rd_data_next),
.dinValid (req_rd_valid),
.dinRetry (req_rd_retry),
.q (ack_rd_data),
.qValid (ack_rd_valid),
.qRetry (ack_rd_retry)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long dp[1001][2 * 1001][2]; long long MOD = 998244353; int main() { ios_base::sync_with_stdio(false); int n, k; cin >> n >> k; dp[1][1][0] = 2; dp[1][2][0] = 0; dp[1][1][1] = 0; dp[1][2][1] = 2; for (int i = 2; i <= n; ++i) { for (int j = 1; j <= min(2 * n, k); ++j) { dp[i][j][0] = dp[i - 1][j][0] + dp[i - 1][j - 1][0] + dp[i - 1][j][1] * 2; dp[i][j][0] %= MOD; dp[i][j][1] = dp[i - 1][j][1] + dp[i - 1][j - 2][1] + dp[i - 1][j - 1][0] * 2; dp[i][j][1] %= MOD; } } cout << (dp[n][k][0] + dp[n][k][1]) % MOD << n ; } |
#include <bits/stdc++.h> using namespace std; struct Data { long long l, r; } a[200100]; long long n, s, rmax, lmin; void Docfile() { scanf( %lld%lld , &n, &s); rmax = 0; lmin = 1e18; for (int i = 1; i <= n; i++) { scanf( %lld%lld , &a[i].l, &a[i].r); rmax = max(rmax, a[i].r); lmin = min(lmin, a[i].l); } } bool cmp(Data &a, Data &b) { return ((a.l < b.l) || ((a.l == b.l) && (a.r < b.r))); } void Xuli() { sort(a + 1, a + 1 + n, cmp); long long sum1, sum2, dem1, dem2, dem3, F[200100]; long long d = lmin, c = rmax, g, kq = 0; while (d <= c) { g = (d + c) / 2; dem1 = dem2 = dem3 = sum1 = sum2 = 0; F[0] = 0; for (int i = 1; i <= n; i++) { if (a[i].r < g) { dem1++; sum1 += a[i].l; } else { if (a[i].l > g) { dem2++; sum2 += a[i].l; } else { dem3++; F[dem3] = F[dem3 - 1] + a[i].l; } } } if (dem1 > n / 2) { c = g - 1; continue; } if (dem2 > n / 2) { d = g + 1; continue; } if (dem1 < n / 2) sum1 += F[n / 2 - dem1]; if (dem2 < n / 2) sum2 += g * (n / 2 - dem2); if (sum1 + sum2 + g <= s) { kq = max(kq, g); d = g + 1; } else c = g - 1; } printf( %lld n , kq); } int main() { long t; scanf( %d , &t); for (int i = 1; i <= t; i++) { Docfile(); Xuli(); } } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class T> using pq = priority_queue<T>; template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; int scan() { return getchar(); } template <class T> void scan(T a) { cin >> a; } void scan(int &a) { cin >> a; } void scan(long long &a) { cin >> a; } void scan(char &a) { cin >> a; } void scan(double &a) { cin >> a; } void scan(long double &a) { cin >> a; } void scan(char a[]) { scanf( %s , a); } void scan(string &a) { cin >> a; } template <class T> void scan(vector<T> &); template <class T, size_t size> void scan(array<T, size> &); template <class T, class L> void scan(pair<T, L> &); template <class T, size_t size> void scan(T (&)[size]); template <class T> void scan(vector<T> &a) { for (auto &i : a) scan(i); } template <class T> void scan(deque<T> &a) { for (auto &i : a) scan(i); } template <class T, size_t size> void scan(array<T, size> &a) { for (auto &i : a) scan(i); } template <class T, class L> void scan(pair<T, L> &p) { scan(p.first); scan(p.second); } template <class T, size_t size> void scan(T (&a)[size]) { for (auto &i : a) scan(i); } template <class T> void scan(T &a) { cin >> a; } void IN() {} template <class Head, class... Tail> void IN(Head &head, Tail &...tail) { scan(head); IN(tail...); } string stin() { string s; cin >> s; return s; } template <class T, class S> inline bool chmax(T &a, S b) { if (a < b) { a = b; return 1; } return 0; } template <class T, class S> inline bool chmin(T &a, S b) { if (a > b) { a = b; return 1; } return 0; } vector<int> iota(int n) { vector<int> a(n); iota(begin(a), end(a), 0); return a; } template <class T> void UNIQUE(vector<T> &x) { sort(begin(x), end(x)); x.erase(unique(begin(x), end(x)), x.end()); } int in() { int x; cin >> x; return x; } long long lin() { unsigned long long x; cin >> x; return x; } void print() { putchar( ); } void print(bool a) { cout << a; } void print(int a) { cout << a; } void print(long long a) { cout << a; } void print(char a) { cout << a; } void print(string &a) { cout << a; } void print(double a) { cout << a; } template <class T> void print(const vector<T> &); template <class T, size_t size> void print(const array<T, size> &); template <class T, class L> void print(const pair<T, L> &p); template <class T, size_t size> void print(const T (&)[size]); template <class T> void print(const vector<T> &a) { if (a.empty()) return; print(a[0]); for (auto i = a.begin(); ++i != a.end();) { cout << ; print(*i); } cout << endl; } template <class T> void print(const deque<T> &a) { if (a.empty()) return; print(a[0]); for (auto i = a.begin(); ++i != a.end();) { cout << ; print(*i); } } template <class T, size_t size> void print(const array<T, size> &a) { print(a[0]); for (auto i = a.begin(); ++i != a.end();) { cout << ; print(*i); } } template <class T, class L> void print(const pair<T, L> &p) { cout << ( ; print(p.first); cout << , ; print(p.second); cout << ) ; } template <class T> void print(set<T> &x) { for (auto e : x) print(e), cout << ; cout << endl; } template <class T> void print(multiset<T> &x) { for (auto e : x) print(e), cout << ; cout << endl; } template <class T, size_t size> void print(const T (&a)[size]) { print(a[0]); for (auto i = a; ++i != end(a);) { cout << ; print(*i); } } template <class T> void print(const T &a) { cout << a; } int out() { putchar( n ); return 0; } template <class T> int out(const T &t) { print(t); putchar( n ); return 0; } template <class Head, class... Tail> int out(const Head &head, const Tail &...tail) { print(head); putchar( ); out(tail...); return 0; } long long gcd(long long a, long long b) { while (b) { long long c = b; b = a % b; a = c; } return a; } long long lcm(long long a, long long b) { if (!a || !b) return 0; return a * b / gcd(a, b); } vector<pair<long long, long long>> factor(long long x) { vector<pair<long long, long long>> ans; for (long long i = 2; i * i <= x; i++) if (x % i == 0) { ans.push_back({i, 1}); while ((x /= i) % i == 0) ans.back().second++; } if (x != 1) ans.push_back({x, 1}); return ans; } template <class T> vector<T> divisor(T x) { vector<T> ans; for (T i = 1; i * i <= x; i++) if (x % i == 0) { ans.push_back(i); if (i * i != x) ans.push_back(x / i); } return ans; } template <typename T> void zip(vector<T> &x) { vector<T> y = x; sort(begin(y), end(y)); for (int i = 0; i < x.size(); ++i) { x[i] = distance((y).begin(), lower_bound(begin(y), end(y), (x[i]))); } } int popcount(long long x) { return __builtin_popcountll(x); } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int rnd(int n) { return uniform_int_distribution<int>(0, n - 1)(rng); } long long rndll(long long n) { return uniform_int_distribution<long long>(0, n - 1)(rng); } template <typename T> void shuffle(vector<T> &v) { for (long long i = v.size() - 1; i >= 1; --i) { swap(v[i], v[rnd(i)]); } } vector<string> YES{ NO , YES }; vector<string> Yes{ No , Yes }; vector<string> yes{ no , yes }; template <class... T> void err(const T &...) {} template <typename T> struct edge { int from, to; T cost; int id; edge(int to, T cost) : from(-1), to(to), cost(cost) {} edge(int from, int to, T cost) : from(from), to(to), cost(cost) {} edge(int from, int to, T cost, int id) : from(from), to(to), cost(cost), id(id) {} edge &operator=(const int &x) { to = x; return *this; } operator int() const { return to; } }; template <typename T> using Edges = vector<edge<T>>; struct Graph : vector<vector<int>> { using vector<vector<int>>::vector; Graph(int n, int m) : vector(n) { read(m); } inline void add(int a, int b, bool directed = false) { (*this)[a].emplace_back(b); if (!directed) (*this)[b].emplace_back(a); } void read(int n = -1, int offset = 1, bool directed = false) { if (n == -1) n = this->size() - 1; int a, b; while (n--) { cin >> a >> b; Graph::add(a - offset, b - offset, directed); } } }; template <typename T> struct WeightedGraph : vector<Edges<T>> { using vector<Edges<T>>::vector; inline void add(int a, int b, T c, bool directed = false) { (*this)[a].emplace_back(b, c); if (!directed) (*this)[b].emplace_back(a, c); } void read(int n = -1, int offset = 1) { if (n == -1) n = this->size() - 1; int a, b; T c; while (n--) { cin >> a >> b >> c; WeightedGraph::add(a - offset, b - offset, c); } } }; struct Setup_io { Setup_io() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cout << fixed << setprecision(15); } } setup_io; int main() { int n; IN(n); vector<int> a(n); IN(a); vector<vector<vector<bool>>> dp( n + 1, vector<vector<bool>>(100, vector<bool>(3000))); vector<vector<vector<pair<int, int>>>> pre( n + 1, vector<vector<pair<int, int>>>(100, vector<pair<int, int>>(3000))); dp[0][0][0] = 1; vector<int> tr(100); for (long long i = 1; i <= 98; ++i) tr[i + 1] = tr[i] + i; sort(begin(a), end(a)); for (long long i = 0; i < n; ++i) { for (long long j = 0; j < a[i] * 2 + 2; ++j) { for (long long k = 0; k < 3000; ++k) { if (!dp[i][j][k]) continue; int jj = j + 1, kk = k + a[i]; while (kk >= tr[jj]) { dp[i + 1][jj][kk] = true; pre[i + 1][jj][kk] = pair<int, int>(j, k); jj++, kk += a[i]; } } } } int m = 0; vector<int> v; for (long long i = 1; i <= 64; ++i) { if (dp[n][i][tr[i]]) { m = i; int j = i, k = tr[i]; int t = n; while (t > 0) { auto [jj, kk] = pre[t][j][k]; for (long long _ = 0; _ < j - jj; ++_) v.emplace_back(a[t - 1]); t--, j = jj, k = kk; } break; } } if (!m) { cout << =( << n ; return 0; } reverse(begin(v), end(v)); cout << m << n ; vector<vector<int>> g(m, vector<int>(m, -1)); auto id = iota(m); for (long long i = m - 1; i >= 0; --i) { for (long long j = 0; j < v[id[i]]; ++j) g[id[i]][id[j]] = 1, g[id[j]][id[i]] = 0; for (long long j = v[id[i]]; j <= i - 1; ++j) g[id[i]][id[j]] = 0, g[id[j]][id[i]] = 1, v[id[j]]--; sort(id.begin(), id.begin() + i, [&](int a, int b) { return v[a] < v[b]; }); } for (long long i = 0; i < m; ++i) g[i][i] = 0; for (long long i = 0; i < m; ++i) { for (long long j = 0; j < m; ++j) { cout << g[i][j]; } cout << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLXTP_BEHAVIORAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_BEHAVIORAL_PP_V |
// File : ../RTL/serialInterfaceEngine/siereceiver.v
// Generated : 11/10/06 05:37:23
// From : ../RTL/serialInterfaceEngine/siereceiver.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// SIEReceiver
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
module SIEReceiver (RxWireDataIn, RxWireDataWEn, clk, connectState, rst);
input [1:0] RxWireDataIn;
input RxWireDataWEn;
input clk;
input rst;
output [1:0] connectState;
wire [1:0] RxWireDataIn;
wire RxWireDataWEn;
wire clk;
reg [1:0] connectState, next_connectState;
wire rst;
// diagram signals declarations
reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
reg [7:0]RXWaitCount, next_RXWaitCount;
reg [1:0]RxBits, next_RxBits;
// BINARY ENCODED state machine: rcvr
// State codes definitions:
`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
`define LS_CONN_CHK_RX_BITS 4'b0010
`define DISCNCT_CHK_RXBITS 4'b0011
`define WAIT_BIT 4'b0100
`define START_SRX 4'b0101
`define FS_CONN_CHK_RX_BITS1 4'b0110
`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
reg [3:0] CurrState_rcvr;
reg [3:0] NextState_rcvr;
//--------------------------------------------------------------------
// Machine: rcvr
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or connectState or CurrState_rcvr)
begin : rcvr_NextState
NextState_rcvr <= CurrState_rcvr;
// Set default values for outputs and signals
next_RxBits <= RxBits;
next_RXStMachCurrState <= RXStMachCurrState;
next_RXWaitCount <= RXWaitCount;
next_connectState <= connectState;
case (CurrState_rcvr)
`WAIT_BIT:
if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
begin
NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
next_RxBits <= RxWireDataIn;
end
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
begin
NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
next_RxBits <= RxWireDataIn;
end
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
begin
NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
next_RxBits <= RxWireDataIn;
end
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
begin
NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
next_RxBits <= RxWireDataIn;
end
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
begin
NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
next_RxBits <= RxWireDataIn;
end
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
begin
NextState_rcvr <= `DISCNCT_CHK_RXBITS;
next_RxBits <= RxWireDataIn;
end
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
begin
NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
next_RxBits <= RxWireDataIn;
end
`START_SRX:
begin
next_RXStMachCurrState <= `DISCONNECT_ST;
next_RXWaitCount <= 8'h00;
next_connectState <= `DISCONNECT;
next_RxBits <= 2'b00;
NextState_rcvr <= `WAIT_BIT;
end
`DISCNCT_CHK_RXBITS:
if (RxBits == `ZERO_ONE)
begin
NextState_rcvr <= `WAIT_BIT;
next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
next_RXWaitCount <= 8'h00;
end
else if (RxBits == `ONE_ZERO)
begin
NextState_rcvr <= `WAIT_BIT;
next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
next_RXWaitCount <= 8'h00;
end
else
NextState_rcvr <= `WAIT_BIT;
`WAIT_FS_CONN_CHK_RX_BITS:
begin
if (RxBits == `ONE_ZERO)
begin
next_RXWaitCount <= RXWaitCount + 1'b1;
if (RXWaitCount == `CONNECT_WAIT_TIME)
begin
next_connectState <= `FULL_SPEED_CONNECT;
next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
end
end
else
begin
next_RXStMachCurrState <= `DISCONNECT_ST;
end
NextState_rcvr <= `WAIT_BIT;
end
`WAIT_LS_CONN_CHK_RX_BITS:
begin
if (RxBits == `ZERO_ONE)
begin
next_RXWaitCount <= RXWaitCount + 1'b1;
if (RXWaitCount == `CONNECT_WAIT_TIME)
begin
next_connectState <= `LOW_SPEED_CONNECT;
next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
end
end
else
begin
next_RXStMachCurrState <= `DISCONNECT_ST;
end
NextState_rcvr <= `WAIT_BIT;
end
`LS_CONN_CHK_RX_BITS:
begin
NextState_rcvr <= `WAIT_BIT;
if (RxBits == `SE0)
begin
next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
next_RXWaitCount <= 0;
end
end
`FS_CONN_CHK_RX_BITS1:
begin
NextState_rcvr <= `WAIT_BIT;
if (RxBits == `SE0)
begin
next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
next_RXWaitCount <= 0;
end
end
`WAIT_LS_DIS_CHK_RX_BITS:
begin
NextState_rcvr <= `WAIT_BIT;
if (RxBits == `SE0)
begin
next_RXWaitCount <= RXWaitCount + 1'b1;
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
begin
next_RXStMachCurrState <= `DISCONNECT_ST;
next_connectState <= `DISCONNECT;
end
end
else
begin
next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
end
end
`WAIT_FS_DIS_CHK_RX_BITS2:
begin
NextState_rcvr <= `WAIT_BIT;
if (RxBits == `SE0)
begin
next_RXWaitCount <= RXWaitCount + 1'b1;
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
begin
next_RXStMachCurrState <= `DISCONNECT_ST;
next_connectState <= `DISCONNECT;
end
end
else
begin
next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
end
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : rcvr_CurrentState
if (rst)
CurrState_rcvr <= `START_SRX;
else
CurrState_rcvr <= NextState_rcvr;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : rcvr_RegOutput
if (rst)
begin
RXStMachCurrState <= `DISCONNECT_ST;
RXWaitCount <= 8'h00;
RxBits <= 2'b00;
connectState <= `DISCONNECT;
end
else
begin
RXStMachCurrState <= next_RXStMachCurrState;
RXWaitCount <= next_RXWaitCount;
RxBits <= next_RxBits;
connectState <= next_connectState;
end
end
endmodule |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module sounder_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,mask_i,tx_i_o,tx_q_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [13:0] ampl_i;
input [15:0] mask_i;
output [13:0] tx_i_o;
output [13:0] tx_q_o;
wire pn;
wire [13:0] min_value = (~ampl_i)+14'b1;
lfsr pn_code
( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),.mask_i(mask_i),.pn_o(pn) );
assign tx_i_o = ena_i ? (pn ? ampl_i : min_value) : 14'b0; // Bipolar
assign tx_q_o = 14'b0;
endmodule // sounder_tx
|
//*************************************************************************
// > ÎļþÃû: alu_display.v
// > ÃèÊö £ºALUÏÔʾģ¿é£¬µ÷ÓÃFPGA°åÉϵÄIO½Ó¿ÚºÍ´¥ÃþÆÁ
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module alu_display(
//ʱÖÓÓ븴λÐźÅ
input clk,
input resetn, //ºó׺"n"´ú±íµÍµçƽÓÐЧ
//²¦Â뿪¹Ø£¬ÓÃÓÚÑ¡ÔñÊäÈëÊý
input [1:0] input_sel, //00:ÊäÈëΪ¿ØÖÆÐźÅ(alu_control)
//10:ÊäÈëΪԴ²Ù×÷Êý1(alu_src1)
//11:ÊäÈëΪԴ²Ù×÷Êý2(alu_src2)
//´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);
//-----{µ÷ÓÃALUÄ£¿é}begin
reg [11:0] alu_control; // ALU¿ØÖÆÐźÅ
reg [31:0] alu_src1; // ALU²Ù×÷Êý1
reg [31:0] alu_src2; // ALU²Ù×÷Êý2
wire [31:0] alu_result; // ALU½á¹û
alu alu_module(
.alu_control(alu_control),
.alu_src1 (alu_src1 ),
.alu_src2 (alu_src2 ),
.alu_result (alu_result )
);
//-----{µ÷ÓÃALUÄ£¿é}end
//---------------------{µ÷Óô¥ÃþÆÁÄ£¿é}begin--------------------//
//-----{ʵÀý»¯´¥ÃþÆÁ}begin
//´ËС½Ú²»ÐèÒª¸ü¸Ä
reg display_valid;
reg [39:0] display_name;
reg [31:0] display_value;
wire [5 :0] display_number;
wire input_valid;
wire [31:0] input_value;
lcd_module lcd_module(
.clk (clk ), //10Mhz
.resetn (resetn ),
//µ÷Óô¥ÃþÆÁµÄ½Ó¿Ú
.display_valid (display_valid ),
.display_name (display_name ),
.display_value (display_value ),
.display_number (display_number),
.input_valid (input_valid ),
.input_value (input_value ),
//lcd´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
.lcd_rst (lcd_rst ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_data_io (lcd_data_io ),
.lcd_bl_ctr (lcd_bl_ctr ),
.ct_int (ct_int ),
.ct_sda (ct_sda ),
.ct_scl (ct_scl ),
.ct_rstn (ct_rstn )
);
//-----{ʵÀý»¯´¥ÃþÆÁ}end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}begin
//¸ù¾Ýʵ¼ÊÐèÒªÊäÈëµÄÊýÐ޸ĴËС½Ú£¬
//½¨Òé¶Ôÿһ¸öÊýµÄÊäÈ룬±àдµ¥¶ÀÒ»¸öalways¿é
//µ±input_selΪ00ʱ£¬±íʾÊäÈëÊý¿ØÖÆÐźţ¬¼´alu_control
always @(posedge clk)
begin
if (!resetn)
begin
alu_control <= 12'd0;
end
else if (input_valid && input_sel==2'b00)
begin
alu_control <= input_value[11:0];
end
end
//µ±input_selΪ10ʱ£¬±íʾÊäÈëÊýΪԴ²Ù×÷Êý1£¬¼´alu_src1
always @(posedge clk)
begin
if (!resetn)
begin
alu_src1 <= 32'd0;
end
else if (input_valid && input_sel==2'b10)
begin
alu_src1 <= input_value;
end
end
//µ±input_selΪ11ʱ£¬±íʾÊäÈëÊýΪԴ²Ù×÷Êý2£¬¼´alu_src2
always @(posedge clk)
begin
if (!resetn)
begin
alu_src2 <= 32'd0;
end
else if (input_valid && input_sel==2'b11)
begin
alu_src2 <= input_value;
end
end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}begin
//¸ù¾ÝÐèÒªÏÔʾµÄÊýÐ޸ĴËС½Ú£¬
//´¥ÃþÆÁÉϹ²ÓÐ44¿éÏÔʾÇøÓò£¬¿ÉÏÔʾ44×é32λÊý¾Ý
//44¿éÏÔʾÇøÓò´Ó1¿ªÊ¼±àºÅ£¬±àºÅΪ1~44£¬
always @(posedge clk)
begin
case(display_number)
6'd1 :
begin
display_valid <= 1'b1;
display_name <= "SRC_1";
display_value <= alu_src1;
end
6'd2 :
begin
display_valid <= 1'b1;
display_name <= "SRC_2";
display_value <= alu_src2;
end
6'd3 :
begin
display_valid <= 1'b1;
display_name <= "CONTR";
display_value <={20'd0, alu_control};
end
6'd4 :
begin
display_valid <= 1'b1;
display_name <= "RESUL";
display_value <= alu_result;
end
default :
begin
display_valid <= 1'b0;
display_name <= 40'd0;
display_value <= 32'd0;
end
endcase
end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}end
//----------------------{µ÷Óô¥ÃþÆÁÄ£¿é}end---------------------//
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : CFGLUT5.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision
// 12/27/05 - Initial version.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 05/13/13 - add IS_CLK_INVERTED
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module CFGLUT5 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output CDO,
output O5,
output O6,
input CDI,
input CE,
input CLK,
input I0,
input I1,
input I2,
input I3,
input I4
);
`ifdef XIL_TIMING
wire CDI_dly;
wire CE_dly;
wire CLK_dly;
`endif
reg [31:0] data = INIT;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
`ifdef XIL_TIMING
while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`else
while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`endif
deassign data;
end
`ifdef XIL_TIMING
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK_dly) begin
if (CE_dly == 1'b1) begin
data[31:0] <= {data[30:0], CDI_dly};
end
end
end else begin : generate_block1
always @(negedge CLK_dly) begin
if (CE_dly == 1'b1) begin
data[31:0] <= {data[30:0], CDI_dly};
end
end
end
endgenerate
`else
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK) begin
if (CE == 1'b1) begin
data[31:0] <= {data[30:0], CDI};
end
end
end else begin : generate_block1
always @(negedge CLK) begin
if (CE == 1'b1) begin
data[31:0] <= {data[30:0], CDI};
end
end
end
endgenerate
`endif
assign O6 = data[{I4,I3,I2,I1,I0}];
assign O5 = data[{1'b0,I3,I2,I1,I0}];
assign CDO = data[31];
`ifdef XIL_TIMING
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_ce_clk_en_p;
wire sh_ce_clk_en_n;
always @(notifier)
data[0] = 1'bx;
assign sh_clk_en_p = ~IS_CLK_INVERTED;
assign sh_clk_en_n = IS_CLK_INVERTED;
assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED;
assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED;
`endif
specify
(CLK => CDO) = (100:100:100, 100:100:100);
(CLK => O5) = (100:100:100, 100:100:100);
(CLK => O6) = (100:100:100, 100:100:100);
(I0 => CDO) = (0:0:0, 0:0:0);
(I0 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => CDO) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => CDO) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => CDO) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => CDO) = (0:0:0, 0:0:0);
(I4 => O5) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/***********************************************************************
AVR ATtX5 CPU for Lattuino
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
This module implements the CPU for Lattuino (iCE40HX1K Lattice FPGA
available in the iCE Stick board).
To Do:
-
Author:
- Salvador E. Tropea, salvador inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar>
Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial
Distributed under the GPL v2 or newer license
------------------------------------------------------------------------------
Design unit: Lattuino_Stick
File name: lattuino_stick.v
Note: None
Limitations: None known
Errors: None known
Library: work
Dependencies: IEEE.std_logic_1164
avr.Micros
miniuart.UART
CapSense.Devices
work.WBDevInterconPkg
work.CPUConfig
lattice.components
Target FPGA: iCE40HX1K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: IceStorm
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
module Lattuino_Stick
(
input CLK, // CPU clock
input RESET_P2, // Reset
// Buil-in LEDs
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
// UART
output FTDI_RXD, // to UART Tx
input FTDI_TXD, // to UART Rx
input FTDI_DTR); // UART DTR
`include "../cpuconfig.v"
localparam integer BRDIVISOR=F_CLK/BAUD_RATE/4.0+0.5;
localparam integer CNT_PRESC=F_CLK/1e6; // Counter prescaler (1 µs)
localparam EXPLICIT_TBUF=1; // Manually instantiate tri-state buffers
localparam DEBUG_SPI=0;
wire [15:0] pc; // PROM address
wire [ROM_ADDR_W-1:0] pcsv; // PROM address
wire [15:0] inst; // PROM data
wire [15:0] inst_w; // PROM data
wire we;
wire rst;
reg rst2=0;
wire [4:0] portd_in;
wire [4:0] portd_out;
wire [1:0] pin_irq; // Pin interrupts INT0/1
wire [2:0] dev_irq; // Device interrupts
wire [2:0] dev_ack; // Device ACK
// WISHBONE signals:
// cpu
wire [7:0] cpu_dati;
wire cpu_acki;
wire [7:0] cpu_dato;
wire cpu_weo;
wire [7:0] cpu_adro;
wire cpu_stbo;
// rs2
wire [7:0] rs2_dato;
wire rs2_acko;
wire [7:0] rs2_dati;
wire rs2_wei;
wire [0:0] rs2_adri;
wire rs2_stbi;
wire inttx;
wire intrx;
reg dtr_r;
wire dtr_reset;
///////////////////////////////
// RESET logic //
// Power-On Reset + UART DTR //
///////////////////////////////
assign rst=~rst2 | dtr_reset;
always @(posedge CLK)
begin : do_reset
if (!rst2)
rst2 <= 1;
end // do_reset
// The DTR reset is triggered by a falling edge at DTR
always @(posedge CLK)
begin : do_sample_dtr
dtr_r <= FTDI_DTR;
end // do_sample_dtr
assign dtr_reset=dtr_r && !FTDI_DTR;
// Built-in LEDs
assign LED1=portd_out[0]; // pin IO14
assign LED2=portd_out[1];
assign LED3=portd_out[2];
assign LED4=portd_out[3];
assign LED5=portd_out[4];
// INT0/1 pins (PD2 and PD3)
assign pin_irq[0]=0;
assign pin_irq[1]=0;
// Device interrupts
assign dev_irq[0]=0; // UART Rx
assign dev_irq[1]=0; // UART Tx
assign dev_irq[2]=0; // 16 bits Timer
ATtX5
#(
.ENA_WB(1), .ENA_SPM(1), .ENA_PORTB(0), .ENA_PORTC(0),
.ENA_PORTD(1), .PORTB_SIZE(7), .PORTC_SIZE(6),
.PORTD_SIZE(5),.RESET_JUMP(RESET_JUMP), .ENA_IRQ_CTRL(0),
.RAM_ADDR_W(RAM_ADDR_W), .ENA_SPI(ENABLE_SPI))
micro
(
.rst_i(rst), .clk_i(CLK), .clk2x_i(CLK),
.pc_o(pc), .inst_i(inst), .ena_i(1), .portc_i(),
.portb_i(), .pgm_we_o(we), .inst_o(inst_w),
.portd_i(), .pin_irq_i(pin_irq), .dev_irq_i(dev_irq),
.dev_ack_o(dev_ack), .portb_o(), .portd_o(portd_out),
.portb_oe_o(), .portd_oe_o(),
// SPI
.spi_ena_o(), .sclk_o(), .miso_i(), .mosi_o(),
// WISHBONE
.wb_adr_o(cpu_adro), .wb_dat_o(cpu_dato), .wb_dat_i(cpu_dati),
.wb_stb_o(cpu_stbo), .wb_we_o(cpu_weo), .wb_ack_i(cpu_acki),
// Debug
.dbg_stop_i(0), .dbg_rf_fake_i(0), .dbg_rr_data_i(0),
.dbg_rd_data_i(0));
assign pcsv=pc[ROM_ADDR_W-1:0];
// Program memory (1/2/4Kx16) (2/4/8 kiB)
generate
if (ROM_ADDR_W==10)
begin : pm_2k
lattuino_1_blPM_2S #(.WORD_SIZE(16), .ADDR_W(ROM_ADDR_W)) PM_Inst2
(.clk_i(CLK), .addr_i(pcsv), .data_o(inst),
.data_i(inst_w), .we_i(we));
end
else if (ROM_ADDR_W==11)
begin : pm_4k
lattuino_1_blPM_4 #(.WORD_SIZE(16), .ADDR_W(ROM_ADDR_W)) PM_Inst4
(.clk_i(CLK), .addr_i(pcsv), .data_o(inst),
.data_i(inst_w), .we_i(we));
end
else if (ROM_ADDR_W==12)
begin : pm_8k
lattuino_1_blPM_8 #(.WORD_SIZE(16), .ADDR_W(ROM_ADDR_W)) PM_Inst8
(.clk_i(CLK), .addr_i(pcsv), .data_o(inst),
.data_i(inst_w), .we_i(we));
end
endgenerate
///////////////////
// WISHBONE UART //
///////////////////
UART_C
#(.BRDIVISOR(BRDIVISOR),
.WIP_ENABLE(1),
.AUX_ENABLE(0))
the_uart
(// WISHBONE signals
.wb_clk_i(CLK), .wb_rst_i(rst), .wb_adr_i(cpu_adro[0:0]),
.wb_dat_i(cpu_dato), .wb_dat_o(cpu_dati), .wb_we_i(cpu_weo),
.wb_stb_i(cpu_stbo), .wb_ack_o(cpu_acki),
// Process signals
.inttx_o(inttx), .intrx_o(intrx), .br_clk_i(1),
.txd_pad_o(FTDI_RXD), .rxd_pad_i(FTDI_TXD));
endmodule // Lattuino_Stick
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_register_slice:1.1
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_axis_register_slice_0_0 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input [255 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input [31 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output [255 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output [31 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output m_axis_tlast;
axis_register_slice_v1_1_axis_register_slice #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(256),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00011011),
.C_REG_CONFIG(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(32'HFFFFFFFF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/);
initial begin
$display("Merge:");
$write("This ");
$write("should ");
$display("merge");
$display("f");
$display(" a=%m");
$display(" b=%m");
$display(" pre");
$display(" t=%0d",$time);
$display(" t2=%0d",$time);
$display(" post");
$display(" t3=%0d",$time);
$display(" t4=%0d t5=%0d",$time,$time,$time);
$display("m");
$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$display("mm");
$display("");
$write("f");
$write(" a=%m");
$write(" b=%m");
$write(" pre");
$write(" t=%0d",$time);
$write(" t2=%0d",$time);
$write(" post");
$write(" t3=%0d",$time);
$write(" t4=%0d t5=%0d",$time,$time,$time);
$write("m");
$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
$display("mm");
$write("\n*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> char c[301][301]; int n, m, k; int v[5][2] = {{0, 0}, {-1, 0}, {1, 0}, {0, -1}, {0, 1}}; void read() { scanf( %d %d %d , &n, &m, &k); for (int i = 0; i < n; i++) scanf( %s , &c[i]); } void print(int i, int j, int r) { for (int z = 0; z < 5; z++) printf( %d %d n , i + v[z][0] * r + 1, j + v[z][1] * r + 1); } int process() { bool ok; int i, j, x, y, z, tot = 0; for (int r = 1; (r < 2 * n) && (r < 2 * m); r++) { for (i = r; i < n - r; i++) { for (j = r; j < m - r; j++) { ok = true; for (z = 0; z < 5 && ok; z++) { if (c[i + (v[z][0] * r)][j + (v[z][1] * r)] == . ) ok = false; } if (ok) tot++; if (tot == k) { print(i, j, r); return 0; } } } } return 1; } int main() { read(); if (process()) printf( -1 ); return 0; } |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5004; int main() { int a = 1, b = 1, n; string s; cin >> n; while (n--) { cin >> s; if (s == UL || s == DR ) ++a; else if (s.size() == 2) ++b; else ++a, ++b; } printf( %lld n , 1ll * a * b); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_SYMBOL_V
|
// DESCRIPTION: Verilator: System Verilog test of a complete CPU
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// SPDX-License-Identifier: CC0-1.0
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
integer clk_count;
testbench testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Drive simulation for 500 clock cycles
// **************************************************************************
initial begin
`ifdef TEST_VERBOSE
$display( "[testbench] - Start of simulation ----------------------- " );
`endif
clk_count = 0;
end
always @( posedge clk ) begin
if (90 == clk_count) begin
$finish ();
end
else begin
clk_count++;
end
end
final begin
`ifdef TEST_VERBOSE
$display( "[testbench] - End of simulation ------------------------- " );
`endif
$write("*-* All Finished *-*\n");
end
endmodule
module testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
// **************************************************************************
// Local parameters
// **************************************************************************
localparam
NUMPADS = $size( pinout );
// **************************************************************************
// Regs and Wires
// **************************************************************************
// **** Pinout ****
`ifdef VERILATOR // see t_tri_array
wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}).
`else
wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
`endif
// **************************************************************************
// Regs and Wires, Automatics
// **************************************************************************
/*AUTOWIRE*/
// **************************************************************************
// Includes (Testbench extensions)
// **************************************************************************
// N/A
// **************************************************************************
// Chip Instance
// **************************************************************************
chip
i_chip
(
/*AUTOINST*/
// Inouts
.pad (pad[NUMPADS:1]),
// Inputs
.clk (clk),
.rst (rst));
endmodule // test
// Local Variables:
// verilog-library-directories:("." "t_sv_cpu_code")
// End:
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the 32-bit program counter
module program_counter2a (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
end
else
begin
next_pc<=next_pc+32'd4;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_2_V
`define SKY130_FD_SC_HD__XOR2_2_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xor2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_2_V
|
#include <bits/stdc++.h> using namespace std; map<int, int> m; int main() { int a, t, n, i, j, k, l, mn = INT_MAX, mx = 0; cin >> n >> k; int cnt = 0; int ans = 0; for (int i = 0; i < n; i++) { cin >> a; mn = min(mn, a); m[a]++; } int p = mn; while (p < k) { ans++; mn = INT_MAX; for (int i = k - 1; i >= p; i--) { if (m[i] > 0) m[i]--, m[i + 1]++; if (m[i] > 0) mn = min(mn, i); if (m[i + 1] > 0) mn = min(mn, i + 1); } p = mn; } cout << ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DECAPKAPWR_FUNCTIONAL_PP_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__decapkapwr (
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_FUNCTIONAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_ddiv.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
//
// Module Name: clk_ddiv
//
// Description: clock divider based on Johnson counter
//
// - supports odd/even divisors from 2 to 24 (12 stages of Jons. cnt)
// - supports clock stretch for duration of sig "stretch"
//
// - positive clock counter have sigs *joa*
// - negative clock counter have sigs *job*
//
// - outputs joa_q_2, joa_q_1, joa_q_0 might be used for synchronization
//
// - the last stages of counters "joa_q[0]" and "job_q[0]"
// are registered into "joa_q_0_reg" and "job_q_0_reg"
//
// - the "joa_q_0_reg" and "job_q_0_reg" are ORed into "out_gclk".
//
//
//
// Mimi 7/8/03 : Added input stretch_b,rst_b_l
module ctu_clsp_clkgn_ddiv (/*AUTOARG*/
// Outputs
dom_div0, align_edge, align_edge_b, dom_div1, so,
// Inputs
pll_clk_out, pll_clk_out_l, rst_l, rst_b_l, div_dec, stretch_l,
stretch_b_l, se, si
);
// Globals
input pll_clk_out;
input pll_clk_out_l;
input rst_l;
input rst_b_l;
// Divisor
input [14:0] div_dec ;
// The "stretch" is expected synced with pll_clk_out
input stretch_l;
input stretch_b_l;
// Clock outputs
output dom_div0;
output align_edge;
output align_edge_b;
output dom_div1;
input si;
input se;
output so;
/*
output out_gclk;
output out_gclk_l;
*/
ctu_clsp_clkgn_1div pos(
// Outputs
.dom_div (dom_div0),
.align_edge (align_edge),
.align_edge_b (align_edge_b),
.so (),
// Inputs
.pll_clk (pll_clk_out),
.pll_clk_l (pll_clk_out_l),
.init_l (rst_l),
.div_dec (div_dec[14:0]),
.stretch_l (stretch_l),
.se (se),
.si ());
ctu_clsp_clkgn_1div neg(
// Outputs
.dom_div (dom_div1),
.align_edge (),
.align_edge_b (),
.so (),
// Inputs
.pll_clk (pll_clk_out_l),
.pll_clk_l (pll_clk_out),
.init_l (rst_b_l),
.div_dec (div_dec[14:0]),
.stretch_l (stretch_b_l),
.se (se),
.si ());
endmodule // clk_ddiv
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2013, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//
//-------------------------------------------------------------------
//
// Filename : cur_mb.v
// Author : Yibo FAN
// Created : 2013-12-28
// Description : Current MB
//
//-------------------------------------------------------------------
//
// Modified : 2014-07-17 by HLL
// Description : lcu size changed into 64x64 (prediction to 64x64 block remains to be added)
// Modified : 2014-08-23 by HLL
// Description : optional mode for minimal tu size added
// Modified : 2015-03-12 by HLL
// Description : ping-pong logic removed
// Modified : 2015-03-20 by HLL
// Description : mode function removed
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module cur_mb_yuv (
clk ,
rst_n ,
start_i ,
done_o ,
cur_sel_i ,
cur_ren_i ,
cur_size_i ,
cur_4x4_x_i ,
cur_4x4_y_i ,
cur_idx_i ,
cur_data_o
);
//*** PARAMETER DECLARATION ****************************************************
parameter YUV_FILE = "./tv/cur_mb_p32.dat" ;
//*** INPUT/OUTPUT DECLARATION *************************************************
input clk ; //clock
input rst_n ; //reset signal
// ctrl if
input start_i ; // start load new mb from outside
output done_o ; // load done
// cur if
input cur_sel_i ; // luma/chroma selector
input cur_ren_i ; // cmb read enable
input [1 : 0] cur_size_i ; // cmb read size (00:4x4 01:8x8 10:16x16 11:32x32)
input [4 : 0] cur_idx_i ; // read index ({blk_index, line_number})
input [3 : 0] cur_4x4_x_i ; // cmb read block top/left 4x4 x
input [3 : 0] cur_4x4_y_i ; // cmb read block top/left 4x4 y
output [`PIXEL_WIDTH*32-1 : 0] cur_data_o ; // pixel data
//*** WIRE & REG DECLARATION ***************************************************
reg done_o ;
integer cmb_tp ;
//*** MAIN BODY ****************************************************************
mem_lipo_1p cmb_buf_0 (
.clk ( clk ),
.rst_n ( rst_n ),
.a_wen_i ( 1'b0 ),
.a_addr_i ( 8'b0 ),
.a_wdata_i ( 256'b0 ),
.b_ren_i ( cur_ren_i ),
.b_sel_i ( cur_sel_i ),
.b_size_i ( cur_size_i ),
.b_4x4_x_i ( cur_4x4_x_i ),
.b_4x4_y_i ( cur_4x4_y_i ),
.b_idx_i ( cur_idx_i ),
.b_rdata_o ( cur_data_o )
);
reg [`PIXEL_WIDTH*32-1:0] scan_pixel_32 ;
integer i ;
integer fp_input ;
initial begin
fp_input = $fopen( YUV_FILE ,"r" );
done_o = 0 ;
end
always @(posedge clk) begin
if (start_i) begin
// load luma
for (i=0; i<32; i=i+1) begin
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+0]} =
{scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8-1 :`PIXEL_WIDTH*0]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+1]} =
{scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+2]} =
{scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+3]} =
{scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24]};
end
// load chroma
for (i=0; i<16; i=i+1) begin
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+0]} =
{scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+1]} =
{scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+2]} =
{scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+3]} =
{scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24]};
end
#55 done_o <= 1'b1;
#10 done_o <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> struct Widget { std::string name; long long width, height; Widget(const std::string& name, long long width, long long height) : name(name), width(width), height(height) {} ~Widget() {} virtual void calculateSize() {} }; struct Box : public Widget { int spacing, border; std::vector<Widget*> children; Box(const std::string& name) : Widget(name, 0, 0), spacing(0), border(0) {} }; struct HBox : public Box { HBox(const std::string& name) : Box(name) {} virtual void calculateSize() { if (children.empty()) { width = 0; height = 0; return; } if (width == 0 && height == 0) { for (std::vector<Widget*>::iterator i = children.begin(); i != children.end(); ++i) { (*i)->calculateSize(); width += (*i)->width; height = std::max(height, (*i)->height); } width += (children.size() - 1) * spacing + 2 * border; height += 2 * border; } } }; struct VBox : public Box { VBox(const std::string& name) : Box(name) {} virtual void calculateSize() { if (children.empty()) { width = 0; height = 0; return; } if (width == 0 && height == 0) { for (std::vector<Widget*>::iterator i = children.begin(); i != children.end(); ++i) { (*i)->calculateSize(); width = std::max(width, (*i)->width); height += (*i)->height; } height += (children.size() - 1) * spacing + 2 * border; width += 2 * border; } } }; int main() { int n; std::cin >> n; std::map<std::string, Widget*> map; for (int i = 0; i < n; ++i) { std::string s; std::cin >> s; if (s == Widget ) { std::cin >> s; std::string::size_type lparen = s.find( ( ); std::string name = s.substr(0, lparen); std::string::size_type comma = s.find( , , lparen + 1); std::string::size_type rparen = s.find( ) , comma + 1); int width = strtol(s.substr(lparen + 1, comma - lparen - 1).c_str(), 0, 10); int height = strtol(s.substr(comma + 1, rparen - comma - 1).c_str(), 0, 10); map[name] = new Widget(name, width, height); } else if (s == VBox ) { std::cin >> s; map[s] = new VBox(s); } else if (s == HBox ) { std::cin >> s; map[s] = new HBox(s); } else { std::string::size_type dot = s.find( . ); std::string::size_type lparen = s.find( ( , dot + 1); std::string::size_type rparen = s.find( ) , lparen + 1); std::string name = s.substr(0, dot); std::string method = s.substr(dot + 1, lparen - dot - 1); if (method == pack ) { std::string child = s.substr(lparen + 1, rparen - lparen - 1); static_cast<Box*>(map[name])->children.push_back(map[child]); } else if (method == set_border ) { int border = strtol(s.substr(lparen + 1, rparen - lparen - 1).c_str(), 0, 10); static_cast<Box*>(map[name])->border = border; } else if (method == set_spacing ) { int spacing = strtol(s.substr(lparen + 1, rparen - lparen - 1).c_str(), 0, 10); static_cast<Box*>(map[name])->spacing = spacing; } } } for (std::map<std::string, Widget*>::iterator i = map.begin(); i != map.end(); ++i) { Widget* widget = (*i).second; widget->calculateSize(); std::cout << widget->name << << widget->width << << widget->height << std::endl; } } |
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
//
// There are two modes:
// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
// (resp. high) edge/peak is detected, with hysteresis
// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
// is detected.
// That way you can detect two consecutive edges/peaks at the same level (L/H)
//
// Output:
// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
// - ssp_clk: cross_lo
`include "lp20khz_1MSa_iir_filter.v"
`include "lf_edge_detect.v"
module lo_edge_detect(
input pck0, input pck_divclk,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk,
output ssp_frame, input ssp_dout, output ssp_clk,
input cross_lo,
output dbg,
input lf_field,
input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
);
wire tag_modulation = ssp_dout & !lf_field;
wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
// No logic, straight through.
assign pwr_oe1 = 1'b0; // not used in LF mode
assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
// when modulating, add another 33 Ohms and 10k Ohms in parallel:
assign pwr_oe2 = tag_modulation;
assign pwr_oe4 = tag_modulation;
assign ssp_clk = cross_lo;
assign pwr_lo = reader_modulation;
assign pwr_hi = 1'b0;
// filter the ADC values
wire data_rdy;
wire [7:0] adc_filtered;
assign adc_clk = pck0;
lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
// detect edges
wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
wire [7:0] max, min;
wire edge_state, edge_toggle;
lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
max, min,
high_threshold, highz_threshold, lowz_threshold, low_threshold,
edge_state, edge_toggle);
assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5001; int n, k, a[N * 60]; long long dp[N][N]; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , a + i); sort(a, a + n); for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) dp[i][j] = 5e18; dp[k - n % k][n % k] = 0; for (int i = k - n % k; i + 1; i--) for (int j = n % k; j + 1; j--) { if (i) { int last = n / k * (k - n % k - i) + (n / k + 1) * (n % k - j); dp[i - 1][j] = min(dp[i - 1][j], dp[i][j] + a[last + n / k - 1] - a[last]); } if (j) { int last = n / k * (k - n % k - i) + (n / k + 1) * (n % k - j); dp[i][j - 1] = min(dp[i][j - 1], dp[i][j] + a[last + n / k] - a[last]); } } printf( %lld n , dp[0][0]); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; const int MOD(1e9 + 7); const int MAXN(1e5 + 11); int n, first, z, a, l; int main() { scanf( %d%d%d%d%d , &n, &first, &z, &a, &l); int ans = 0; for (int ptr = 0; ptr < n;) { if (ptr) ptr += max(0, first - l); else ptr += first; first += a; first = min(first, z); ++ans; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; inline void read(int &first) { first = 0; while (1) { char ch = getchar(); if (ch == || ch == n ) break; first = first * 10 + ch - 0 ; } } inline void write(int first) { char wr[12]; int k = 0; if (!first) ++k, wr[k] = 0 ; while (first) { ++k; wr[k] = char(first % 10 + 0 ); first /= 10; } for (int i = k; i >= 1; --i) putchar(wr[i]); } const int N = 1e5 + 5; int n, k, s[N], a[N]; char ch; bool f(int len) { for (int i = 1; i <= n; ++i) { if (!a[i]) continue; int s1 = s[min(n, i + len)] - s[i - 1]; int s2 = s[i] - s[max(0, i - len - 1)]; if (s1 + s2 - a[i] >= k + 1) return 1; } return 0; } int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> ch, s[i] = s[i - 1] + (ch == 0 ), a[i] = ch == 0 ; int l = 1, r = n; while (r - l > 1) { int mid = (l + r) >> 1; if (f(mid)) r = mid; else l = mid; } if (f(l)) cout << l; else cout << r; } |
#include <bits/stdc++.h> using namespace std; const long long int mxn = 1e5 + 5; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; cin >> t; while (t--) { long long int i, j, k, n, m; cin >> n >> k; string s; cin >> s; map<long long int, long long int> mp; long long int sum = 0; for (i = 0; i < n; i++) { if (s[i] == 0 ) sum++; else sum--; mp[sum]++; } if (sum == 0 && mp[k]) cout << -1 << n ; else if (sum == 0) cout << 0 << n ; else { long long int ans = 0, p = 0; if (p == k) { ans++; } for (i = 0; i < n; i++) { if (s[i] == 0 ) p++; else p--; if ((k - p) % sum == 0 && ((k - p) / sum) >= 0) { ans++; } } cout << ans << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, s; long long ans = 0; int main() { int i, j, k; int a1, b1, a2, b2; int x1, y1, x2, y2; int p1, p2; cin >> n >> m >> s; for (i = 0; i <= n / 2; i++) { for (j = 0; j <= m / 2; j++) { for (k = 0; k <= n / 2; k++) { a1 = i; b1 = j; a2 = k; x1 = 1 + 2 * a1; y1 = 1 + 2 * b1; x2 = 1 + a2 * 2; if (x2 > x1) { if ((s - x1 * y1) % (x2 - x1) == 0 && (s - x1 * y1) > 0) { y2 = (s - x1 * y1) / (x2 - x1); if (y2 <= y1 && y2 > 0 && y2 % 2 == 1) { b2 = (y2 - 1) / 2; if (((n - 2 * a2) * (m - 2 * b1)) > 0) ans += ((n - 2 * a2) * (m - 2 * b1)); } } if (s % x2 == 0) { y2 = s / x2; if (y2 > y1 && y2 % 2 == 1) { b2 = (y2 - 1) / 2; if (((n - 2 * a2) * (m - 2 * b2)) > 0) ans += ((n - 2 * a2) * (m - 2 * b2)); } } } else if (x2 == x1) { if (x1 * y1 == s) { if (((n - 2 * a1) * (m - 2 * b1) * (b1 + 1)) > 0) ans += ((n - 2 * a1) * (m - 2 * b1) * (b1 + 1)); } if (s % x1 == 0) { y2 = s / x1; if (y2 > y1 && y2 % 2 == 1) { b2 = (y2 - 1) / 2; if (((n - 2 * a1) * (m - 2 * b2)) > 0) ans += ((n - 2 * a1) * (m - 2 * b2)); } } } else { if (s + x2 * y1 - x1 * y1 > 0 && (s + x2 * y1 - x1 * y1) % x2 == 0) { y2 = (s + x2 * y1 - x1 * y1) / x2; if (y2 > y1 && y2 % 2 == 1) { b2 = (y2 - 1) / 2; if (((n - 2 * a1) * (m - 2 * b2)) > 0) ans += ((n - 2 * a1) * (m - 2 * b2)); } } if (x1 * y1 == s) { if (((n - 2 * a1) * (m - 2 * b1) * (b1 + 1)) > 0) ans += ((n - 2 * a1) * (m - 2 * b1) * (b1 + 1)); } } } } } cout << ans << endl; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_fptrunc_64ns_32_1
#(parameter
ID = 5,
NUM_STAGE = 1,
din0_WIDTH = 64,
dout_WIDTH = 32
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [63:0] a_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
//------------------------Instantiation------------------
HLS_accel_ap_fptrunc_0_no_dsp_64 HLS_accel_ap_fptrunc_0_no_dsp_64_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
`include "config.h"
//
//
// This module implements a 2 flop input synchronization and a crude 3 flop digital filter.
// The output state will not change unless the input is high or low for 3 clock cycles.
//
module digitalfilter(out, clk, rstn, in);
output reg out;
input clk;
input rstn;
input in;
reg [4:0] taps;
reg result;
always @(posedge clk or negedge rstn) begin
if(rstn == 0) begin
taps <= 0;
out <= 0;
end else begin
taps[4] <= taps[3];
taps[3] <= taps[2];
taps[2] <= taps[1];
taps[1] <= taps[0];
taps[0] <= in;
if(taps[2] & taps[3] & taps[4])
out <= 1;
if(~taps[2] & ~taps[3] & ~taps[4])
out <= 0;
end
end
endmodule
// Edge detector with inital state output
module edgedet(clk, rstn, datain, edgeseen);
input clk;
input rstn;
input datain;
output reg edgeseen;
reg lastdata;
reg [3:0] count;
always @(posedge clk or negedge rstn) begin
if(rstn == 0) begin
edgeseen <= 0;
lastdata <= 0;
count <= 4'b0000; // This counter ensures an initial data bit is written into the FIFO after reset
end else begin
edgeseen <= 0;
// Shift once to the right
// Check for edge
if(count < 15) begin // Count if less than 15
lastdata <= datain;
count <= count + 1'b1;
end
if(count == 13) begin
edgeseen <= 1; // Record initial state after initial signal state propagates through the digital filter
end
if((count == 15) && (lastdata ^ datain)) begin
edgeseen <= 1; // Input state changed
lastdata <= datain; // Save the input state
end
end
end
endmodule
/*
* Event logger channel
*/
module channel(clk, rstn, datain, unload, counterin, byteaddr, clearoverrun, overrun, attention, dataout, testouta, testoutb);
input clk; // Counter and fifo clock
input rstn; // Global reset, low true
input datain; // Data bit in
input unload; // Unloads a word from the fifo
input [62:0] counterin; // Free running counter in
input [2:0] byteaddr; // Byte address in long long word
input clearoverrun; // Clears overrun condition
output overrun; // Indicates an overrun condition occurred
output attention; // Indicates there is something needing attention
output[7:0] dataout; // byte data out
output testouta;
output testoutb;
wire empty;
wire full;
wire datain_filt;
wire [`FIFO_DEPTH-1:0] itemsinfifo;
wire [63:0] fifooutputword;
wire [63:0] fifoinputword;
wire loaden;
wire attention_int;
reg overrun_int;
reg attention_delayed;
// Instantiate digital filter
digitalfilter df0(
.clk(clk),
.rstn(rstn),
.in(datain),
.out(datain_filt)
);
// Instantiate an edge detector
edgedet ed0(
.clk(clk),
.rstn(rstn),
.datain(datain_filt),
.edgeseen(loaden)
);
// Instantiate a fifo
ptrfifo fifo0(
.clk(clk),
.rstn(rstn),
.loaden(loaden),
.unloaden(unload),
.datain(fifoinputword),
.dataout(fifooutputword),
.empty(empty),
.full(full),
.itemsinfifo(itemsinfifo)
);
defparam fifo0.WIDTH = 64;
defparam fifo0.DEPTH = `FIFO_DEPTH;
// Instantiate a mux
mux64to8 mux0(
.sel(byteaddr),
.inword(fifooutputword),
.outbyte(dataout)
);
// Merge the data and the free running counter
// The data is in the lsb
assign fifoinputword = {counterin, datain_filt};
// Set attention if the FIFO isn't empty, or there was an overrun condition
assign attention_int = ~empty | overrun_int;
// Set external attention to attention_delayed
assign attention = attention_delayed;
// Set the external overun bit to the internal state
assign overrun = overrun_int;
// Testouta to fifo load enable
assign testouta = loaden;
// Testoutb to fifo unload enable
assign testoutb = unload;
// This detects and latches a FIFO overrun condition
// and delays attention by one clock
always @(posedge clk or negedge rstn) begin
if(rstn == 0) begin
overrun_int = 0;
attention_delayed = 0;
end else begin
// Delay attention by a clock cycle
attention_delayed = attention_int;
// Clear the overrun flag if requested
if(clearoverrun == 1)
overrun_int = 0;
else if(full & loaden)
// Set the overrun flag on an error
overrun_int = 1;
end
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build Mon Apr 27 19:22:08 MDT 2015
// Date : Sun Mar 13 09:23:31 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/mult_gen_1/mult_gen_1_stub.v
// Design : mult_gen_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0,Vivado 2015.1" *)
module mult_gen_1(A, B, P)
/* synthesis syn_black_box black_box_pad_pin="A[11:0],B[13:0],P[32:0]" */;
input [11:0]A;
input [13:0]B;
output [32:0]P;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTN_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:58:48 11/16/2011
// Design Name: toprobertsons
// Module Name: /home/ECONOLITE/lmagasweran/Documents/personal/School/EE412/Robertsons_Multiplier/robertsonstest.v
// Project Name: Robertsons_Multiplier
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: toprobertsons
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module robertsonstest;
// Inputs
reg clk;
reg reset;
reg [7:0] multiplier;
reg [7:0] multiplicand;
// Outputs
wire [15:0] product;
wire done;
// keep track of execution status
reg [31:0] cycle;
// expected results
reg [15:0] expected_product;
// Instantiate the Unit Under Test (UUT)
toprobertsons uut (
.clk(clk),
.reset(reset),
.multiplier(multiplier),
.multiplicand(multiplicand),
.product(product),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
multiplier = 0;
multiplicand = 0;
expected_product = 0;
// Add stimulus here
reset <= 1; # 12; reset <= 0;
cycle <= 1;
// 1.1 Positive Multiplicand and Positive Multiplier
multiplier = 5;
multiplicand = 6;
expected_product = 30;
// 1.2 Positive Multiplicand and Positive Multiplier
//multiplier = 7;
//multiplicand = 5;
//expected_product = 35;
// 2.1 Negative Multiplicand and Positive Multiplier
//multiplier = 5;
//multiplicand = -6;
//expected_product = -30;
// 2.2 Negative Multiplicand and Positive Multiplier
//multiplier = 7;
//multiplicand = -5;
//expected_product = -35;
// 3.1 Positive Multiplicand and Negative Multiplier
//multiplier = -5;
//multiplicand = 6;
//expected_product = -30;
// 3.2 Positive Multiplicand and Negative Multiplier
//multiplier = -7;
//multiplicand = 8;
//expected_product = -56;
// 4.1 Negative Multiplicand and Negative Multiplier
//multiplier = -5;
//multiplicand = -6;
//expected_product = 30;
// 4.2 Negative Multiplicand and Negative Multiplier
//multiplier = -9;
//multiplicand = -4;
//expected_product = 36;
end
// generate clock to sequence tests
always
begin
clk <= 1; # 5; clk <= 0; # 5;
cycle <= cycle + 1;
end
// check results
// If successful, it should write the value 7 to address 84
always@(negedge clk)
begin
if (done) begin
if (product == expected_product) begin
$display("Simulation succeeded");
$stop;
end else begin
$display("Simulation failed");
$stop;
end
end
end
endmodule
|
// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___150.000______0.000______50.0______143.858____157.402
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module design_1_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_design_1_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_design_1_clk_wiz_0_0;
wire clkfbout_buf_design_1_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT_F (19.875),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.625),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
.I (clkfbout_design_1_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_design_1_clk_wiz_0_0));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRBP_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define CONCAT(a,b) a``b
`define SHOW_LINED `CONCAT(show, `__LINE__)
bit fails;
module t (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
generate
begin : direct_ignored
show #(`__LINE__) show1();
if (1) begin check #(`__LINE__, 1) show2(); end
end
begin : empty_DISAGREE
// DISAGREEMENT: if empty unnamed begin/end counts
begin end
if (1) begin check #(`__LINE__, 0) show2(); end
end
begin : empty_named_DISAGREE
// DISAGREEMENT: if empty named begin/end counts
begin : empty_inside_named end
if (1) begin check #(`__LINE__, 0) show2(); end
end
begin : unnamed_counts
// DISAGREEMENT: if unnamed begin/end counts
begin
show #(`__LINE__) show1();
end
if (1) begin check #(`__LINE__, 0) show2(); end
end
begin : named_counts
// DISAGREEMENT: if named begin/end counts
begin : named
show #(`__LINE__) show1();
end
if (1) begin check #(`__LINE__, 0) show2(); end
end
begin : if_direct_counts
if (0) ;
else if (0) ;
else if (1) show #(`__LINE__) show1();
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : if_begin_counts
if (0) begin end
else if (0) begin show #(`__LINE__) show1_NOT(); end
else if (1) begin show #(`__LINE__) show1(); end
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : if_named_counts
if (1) begin : named
show #(`__LINE__) show1();
if (1) begin : subnamed
show #(`__LINE__) show1s();
end
end
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : begin_if_counts
begin
if (0) begin end
else if (0) begin show #(`__LINE__) show1_NOT(); end
else if (1) begin show #(`__LINE__) show1(); end
end
// DISAGREEMENT: this could be genblk01
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : for_empty_counts
// DISAGREEMENT: if empty genfor counts
for (genvar g = 0; g < 1; ++g) ;
if (1) begin check #(`__LINE__, 0) show2(); end
end
begin : for_direct_counts
for (genvar g = 0; g < 1; ++g)
show #(`__LINE__) show1();
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : for_named_counts
for (genvar g = 0; g < 1; ++g) begin : fornamed
show #(`__LINE__) show1();
end
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : for_begin_counts
for (genvar g = 0; g < 1; ++g) begin
show #(`__LINE__) show1();
end
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : if_if
if (0) ;
else if (0) begin : namedb
end
else begin
if (0) begin end
else if (1) begin
show #(`__LINE__) show1();
end
end
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : case_direct
case (1)
0 : show #(`__LINE__) show1a_NOT();
1 : show #(`__LINE__) show1();
2 : show #(`__LINE__) show1c_NOT();
endcase
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : case_begin_counts
case (1)
0 : begin show #(`__LINE__) show1a_NOT(); end
1 : begin show #(`__LINE__) show1(); end
2 : begin show #(`__LINE__) show1c_NOT(); end
endcase
if (1) begin check #(`__LINE__, 2) show2(); end
end
begin : case_named_counts
case (1)
0 : begin : subnamed show #(`__LINE__) show1a_NOT(); end
1 : begin : subnamed show #(`__LINE__) show1(); end
2 : begin : subnamed show #(`__LINE__) show1c_NOT(); end
endcase
if (1) begin check #(`__LINE__, 2) show2(); end
end
endgenerate
int cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 999) begin
if (fails) $stop;
else $write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module show #(parameter LINE=0) ();
// Each instance compares on unique cycle based on line number
// so we get deterministic ordering (versus using an initial)
always @ (posedge t.clk) begin
if (t.cyc == LINE) begin
$display("%03d: got=%m", LINE);
end
end
endmodule
module check #(parameter LINE=0, parameter EXP=0) ();
string mod;
int gennum;
int pos;
always @ (posedge t.clk) begin
if (t.cyc == LINE) begin
mod = $sformatf("%m");
gennum = 0;
for (int pos = 0; pos < mod.len(); ++pos) begin
if (mod.substr(pos, pos+5) == "genblk") begin
pos += 6;
// verilator lint_off WIDTH
gennum = mod[pos] - "0";
// verilator lint_on WIDTH
break;
end
end
$write("%03d: got=%s exp=%0d gennum=%0d ", LINE, mod, EXP, gennum);
if (EXP == 0) $display(" <ignored>");
else if (gennum != EXP) begin
$display (" %%Error");
fails = 1;
end
else $display;
$display;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool is_possible(int m, long long k, long long p[], int n, int x, int a, int y, int b) { if (a != b) { int first = 0; int second = 0; int third = 0; for (int i = 1; i <= m; i++) { if (i % a == 0 && i % b == 0) third++; else if (i % a == 0) first++; else if (i % b == 0) second++; } long long ans1 = 0; for (int i = 0; i < third; i++) { ans1 += ((p[i] * (x + y)) / 100); } for (int i = third; i <= third + first - 1; i++) { ans1 += ((p[i] * x) / 100); } for (int i = third + first; i <= third + first + second - 1; i++) { ans1 += ((p[i] * y) / 100); } long long ans2 = 0; for (int i = 0; i < third; i++) { ans2 += ((p[i] * (x + y)) / 100); } for (int i = third; i <= third + second - 1; i++) { ans2 += ((p[i] * y) / 100); } for (int i = third + second; i <= third + second + first - 1; i++) { ans2 += ((p[i] * x) / 100); } if (ans1 >= k || ans2 >= k) return true; return false; } else { long long ans1 = 0; int first = 0; for (int i = 1; i <= m; i++) { if (i % a == 0) first++; } for (int i = 0; i < first; i++) { ans1 += ((p[i] * (x + y)) / 100); } if (ans1 < k) return false; return true; } } int main() { int t; cin >> t; while (t--) { int n; cin >> n; long long aa[n]; long long p[n]; for (int i = 0; i < n; i++) { cin >> aa[i]; p[i] = aa[i]; } int x, a, y, b; cin >> x >> a >> y >> b; long long k; cin >> k; sort(p, p + n, greater<long long>()); int l = 1; int h = n; int ans = -1; while (l <= h) { int m = l + (h - l) / 2; if (is_possible(m, k, p, n, x, a, y, b)) { ans = m; h = m - 1; } else { l = m + 1; } } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; const int MXN = 200; const int MXK = 5; int bans = -1; int t[MXN][MXK]; int a[MXK]; int n; int c[MXK]; int cc[] = {500, 1000, 1500, 2000, 2500, 3000}; int cat(int c, int n) { if (c * 2 > n) { return 0; } if (c * 4 > n && c * 2 <= n) { return 1; } if (c * 8 > n && c * 4 <= n) { return 2; } if (c * 16 > n && c * 8 <= n) { return 3; } if (c * 32 > n && c * 16 <= n) { return 4; } if (c * 32 <= n) { return 5; } } int calc(int i) { int res = 0; for (int j = (0); j < (MXK); j++) { if (t[i][j] != -1) res += cc[a[j]] - t[i][j] * cc[a[j]] / 250; } return res; } bool ok(int c, int n, int tt, int j) { return cat(c + tt * (t[0][j] != -1), n + tt) <= a[j] && cat(c, n + tt) >= a[j]; } int T; void dfs(int i) { if (i == MXK) { int mn = 0; for (int j = (0); j < (MXK); j++) { if (!ok(c[j], n, T, j)) return; } if (calc(0) > calc(1)) { printf( %d , T); exit(0); } return; } for (int j = (0); j < (6); j++) { a[i] = j; dfs(i + 1); } } int main() { scanf( %d , &n); for (int i = (0); i < (n); i++) { for (int j = (0); j < (5); j++) { scanf( %d , &t[i][j]); if (t[i][j] != -1) { c[j]++; } } } for (int i = (0); i < (n * 31 + 1); i++) { T = i; dfs(0); } cout << bans; } |
#include <bits/stdc++.h> #define ll long long #define ull unsigned long long #define vll vector<ll> using namespace std; inline void sol() { ll n, m; cin >> n >> m; vll a(n); for(ll i=0;i<n;i++){ cin >> a[i]; } vector<pair<int,double>> b(m); for(int i=0;i<m;i++){ int r; double p; cin >> r >> p; b[i] = {r, p}; } int rm; for(rm = n-1; rm >= 0 and a[rm] == rm + 1; rm--); if(rm == -1){ cout << 1 n ; return; } double ans = 1; for(int i=0;i<m;i++){ if(b[i].first - 1 >= rm) ans *= (1 - b[i].second); } // cout << 1 - ans << endl; printf( %0.6lf n , 1 - ans); } int main() { // cin.tie(0); // ios_base::sync_with_stdio(false); int t; cin >> t; while(t--) sol(); return 0; } |
#include <bits/stdc++.h> using namespace std; string itosm(long long x) { if (x == 0) return 0 ; string ans = ; while (x > 0) { ans += ((x % 10) + 0 ); x /= 10; } reverse(ans.begin(), ans.end()); return ans; } long long stoim(string str) { long long ans = 0; long long k = 1; int p = 0; if (str[0] == - ) p++; for (int i = str.length() - 1; i >= p; i--) { ans += (str[i] - 0 ) * k; k *= 10; } return ans; } const long long infll = 1e18 + 3; const int inf = 1009000999; const long double eps = 1e-7; const int maxn = 1e6 + 1146; const int baseint = 1000200013; const long long basell = 1e18 + 3; const long double PI = acos(-1.0); const long long mod = 1e9 + 7; long long a[maxn]; long long t[maxn]; long long f[maxn]; long long n, r, k; bool check(long long x) { for (int i = 0; i < n; i++) f[i] = x - a[i], t[i] = 0; long long sum = 0, ans = 0; for (int i = 0; i < n; i++) { if (f[i] - sum > 0) { long long d = f[i] - sum; sum += d; ans += d; t[2 * r + i] += d; if (ans > k) return 0; } sum -= t[i]; } return 1; } void solve() { cin >> n >> r >> k; for (int i = 0; i < n; i++) cin >> a[i]; long long sum = 0; for (int i = 0; i < n; i++) { if (i - r - 1 >= 0) sum -= a[i - r - 1]; t[i] = sum; sum += a[i]; } sum = 0; for (int i = n - 1; i >= 0; i--) { sum -= a[i + r + 1]; sum += a[i]; t[i] += sum; } for (int i = 0; i < n; i++) a[i] = t[i]; long long l = 0, r = 1.2e18, mid; while (l < r) { mid = (l + r + 1) / 2; if (check(mid)) l = mid; else r = mid - 1; } cout << l; } int main() { ios_base::sync_with_stdio(0); ; cin.tie(0); cout.tie(0); solve(); return 0; } |
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