text
stringlengths 59
71.4k
|
|---|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1 ns / 1 ps
module rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter PHASE_DETECT = "OFF",
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r,
inhbt_rd_r, wtr_inhbt_config_r, maint_rank_r, maint_zq_r,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, dfi_init_complete, clk, app_zq_req,
app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input dfi_init_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd_r;
output [RANKS-1:0] wtr_inhbt_config_r;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
rank_cntrl#
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.PHASE_DETECT (PHASE_DETECT),//to controll periodic reads
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd_r (inhbt_rd_r[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.dfi_init_complete (dfi_init_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
rank_common#
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.dfi_init_complete (dfi_init_complete),
.app_zq_req (app_zq_req),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s[n]; unordered_map<string, int> mp; int count = 0; for (int i = 0; i < n; i++) { cin >> s[i]; mp[s[i]] += 1; } for (int i = 0; i < n; i++) { if (mp[s[i]] > 1) { count += 1; mp[s[i]] -= 1; for (int j = 0; j < 10; j++) { string s1 = s[i]; s1[3] = 0 + j; if (mp[s1] == 0) { mp[s1] += 1; s[i] = s1; break; } } } } cout << count << endl; for (int i = 0; i < n; i++) { cout << s[i] << endl; } } } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 7; const long long inf = 0x3f3f3f3f; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { double pi = 3.1415926535897932384626433832795028841971, n; cin >> n; printf( %.10lf n , 1 / tan(pi / (n * 2))); } return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:37 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: tx_stream.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// TX_STREAM
//
//
// Description: The TX_STREAM module converts user data from a streaming interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
// To perform streaming with Aurora, it starts an infinite frame after
// channel up and performs opporunistic clock correction automatically
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 10 ps
module aurora_201_TX_STREAM
(
// Data interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// Global Logic Interface
CHANNEL_UP,
//Clock Correction Interface
DO_CC,
WARN_CC,
// Aurora Lane Interface
GEN_SCP,
GEN_ECP,
TX_PE_DATA_V,
GEN_PAD,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
input [0:15] TX_D;
input TX_SRC_RDY_N;
output TX_DST_RDY_N;
// Global Logic Interface
input CHANNEL_UP;
//Clock Correction Interface
input DO_CC;
input WARN_CC;
// Aurora Lane Interface
output GEN_SCP;
output GEN_ECP;
output TX_PE_DATA_V;
output GEN_PAD;
output [0:15] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
//************************External Register Declarations***********
reg GEN_CC;
//************************Register Declarations********************
//State registers
reg rst_r;
reg start_r;
reg run_r;
reg tx_dst_rdy_n_r;
//*********************************Wire Declarations**********************************
//FSM nextstate signals
wire next_start_c;
wire next_run_c;
//*********************************Main Body of Code**********************************
//____________________________ Data Interface Signals__________________________
// Data interface is ready when the channel is up and running and not forcing a cc
always @(posedge USER_CLK)
tx_dst_rdy_n_r <= `DLY !CHANNEL_UP || !run_r || DO_CC;
assign TX_DST_RDY_N = tx_dst_rdy_n_r;
//____________________________ Aurora Lane Interface Signals __________________
// Generate CCs whenever DO_CC is asserted. Register the signal to line it up
// with the cycle when TX_DST_RDY_N is deasserted
always @(posedge USER_CLK)
GEN_CC <= DO_CC;
// Send an SCP to start the infinite frame
assign GEN_SCP = start_r;
// Never send ECPs or PADs
assign GEN_ECP = 1'b0;
assign GEN_PAD = 1'd0;
// Send the user's data directly to the Aurora Lane
assign TX_PE_DATA = TX_D;
// The data is valid if it is written when the channel is ready and TX_SRC_RDY_N is asserted
assign TX_PE_DATA_V = !tx_dst_rdy_n_r && !TX_SRC_RDY_N;
//_______________ State machine to start infinite frame ______________
// After channel up, the tx stream module sends an SCP character
// to start the inifinite frame that will carry the data stream, then
// goes to the run state.
//Control state machine state registers
always @(posedge USER_CLK)
if(!CHANNEL_UP)
begin
rst_r <= `DLY 1'b1;
start_r <= `DLY 1'b0;
run_r <= `DLY 1'b0;
end
else
begin
rst_r <= `DLY 1'b0;
start_r <= `DLY next_start_c;
run_r <= `DLY next_run_c;
end
//Nextstate logic
// After reset, send the SCP character to open the infinite
// frame
assign next_start_c = rst_r;
// After the start state, go to normal operation
assign next_run_c = start_r ||
run_r;
endmodule
|
//--------------------------------------------------------------------------------
// eia232.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// EIA232 aka RS232 interface.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module eia232 #(
parameter [31:0] FREQ = 100000000,
parameter [31:0] SCALE = 28,
parameter [31:0] RATE = 115200,
parameter TRXFREQ = FREQ / SCALE // reduced rx & tx clock for receiver and transmitter
)(
input wire clock,
input wire reset,
input wire [1:0] speed, // UART speed
input wire send, // Send data output serial tx
input wire [31:0] wrdata, // Data to be sent
input wire rx, // Serial RX
output wire tx, // Serial TX
output wire [39:0] cmd,
output wire execute, // Cmd is valid
output wire busy // Indicates transmitter busy
);
wire trxClock;
reg id, next_id;
reg xon, next_xon;
reg xoff, next_xoff;
reg wrFlags, next_wrFlags;
reg dly_execute, next_dly_execute;
reg [3:0] disabledGroupsReg, next_disabledGroupsReg;
wire [7:0] opcode;
wire [31:0] opdata;
assign cmd = {opdata,opcode};
//
// Process special uart commands that do not belong in core decoder...
//
always @(posedge clock)
begin
id <= next_id;
xon <= next_xon;
xoff <= next_xoff;
wrFlags <= next_wrFlags;
dly_execute <= next_dly_execute;
disabledGroupsReg <= next_disabledGroupsReg;
end
always
begin
next_id = 1'b0;
next_xon = 1'b0;
next_xoff = 1'b0;
next_wrFlags = 1'b0;
next_dly_execute = execute;
if (!dly_execute && execute)
case(opcode)
8'h02 : next_id = 1'b1;
8'h11 : next_xon = 1'b1;
8'h13 : next_xoff = 1'b1;
8'h82 : next_wrFlags = 1'b1;
endcase
next_disabledGroupsReg = disabledGroupsReg;
if (wrFlags) next_disabledGroupsReg = opdata[5:2];
end
//
// Instantiate prescaler that generates clock matching UART reference (ie: 115200 baud)...
//
prescaler #(
.SCALE(SCALE)
) prescaler (
.clock (clock),
.reset (reset),
.div (speed),
.scaled (trxClock)
);
//
// Instantiate serial-to-parallel receiver.
// Asserts "execute" whenever valid 8-bit value received.
//
receiver #(
.FREQ(TRXFREQ),
.RATE(RATE)
) receiver (
.clock (clock),
.reset (reset),
.rx (rx),
.trxClock (trxClock),
.op (opcode),
.data (opdata),
.execute (execute)
);
//
// Instantiate parallel-to-serial transmitter.
// Genereate serial data whenever "send" or "id" asserted.
// Obeys xon/xoff commands.
//
transmitter #(
.FREQ(TRXFREQ),
.RATE(RATE)
) transmitter (
.clock (clock),
.trxClock (trxClock),
.reset (reset),
.disabledGroups (disabledGroupsReg),
.write (send),
.wrdata (wrdata),
.id (id),
.xon (xon),
.xoff (xoff),
.tx (tx),
.busy (busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int W, H, N, num; char ch; multiset<int> maxHorSize, maxVertSize; set<int> horiz, vert; long long max_area; long long find_max(set<int> &setCut, char cut) { auto med = setCut.find(num); auto big = med; auto sml = med; ++big; --sml; if (cut == h ) { maxHorSize.erase(maxHorSize.find(*big - *sml)); maxHorSize.insert(*med - *sml); maxHorSize.insert(*big - *med); } else if (cut == v ) { maxVertSize.erase(maxVertSize.find(*big - *sml)); maxVertSize.insert(*med - *sml); maxVertSize.insert(*big - *med); } return (long long)(*maxHorSize.rbegin()) * (long long)(*maxVertSize.rbegin()); } int main() { scanf( %d%d%d , &W, &H, &N); horiz = {0, H}; vert = {0, W}; maxHorSize = {H}; maxVertSize = {W}; for (auto i = 1; i != N + 1 - 2 * (1 > N); i += 1 - 2 * (1 > N)) { cin >> ch >> num; if (ch == H ) { horiz.insert(num); max_area = find_max(horiz, h ); } else if (ch == V ) { vert.insert(num); max_area = find_max(vert, v ); } printf( %I64d n , max_area); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// bug420
typedef logic [7-1:0] wb_ind_t;
typedef logic [7-1:0] id_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
wire [6:0] out = line_wb_ind( in[6:0] );
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc918fa0aa882a206
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function wb_ind_t line_wb_ind( id_t id );
if( id[$bits(id_t)-1] == 0 )
return {2'b00, id[$bits(wb_ind_t)-3:0]};
else
return {2'b01, id[$bits(wb_ind_t)-3:0]};
endfunction // line_wb_ind
endmodule
|
`timescale 1ns / 1ps
module draw_symbols(
input reset,
input [10:0] vcounter,
input [11:0] hcounter,
input visible,
input [8:0] occupied,
input [8:0] symbol,
output reg VGA_R,
output reg VGA_G,
output reg VGA_B
);
//upper left position of tic-tac-toe
wire [10:0] down;
wire [11:0] left;
assign down = (479-384)/2;
assign left = (639-384)/2;
wire draw_out;
wire [3:0] row, col;
reg [1:0] select;
always @(*)
begin
if (hcounter >= left && hcounter < left+384 && vcounter >= down && vcounter < down+384) begin : selblock
integer j;
j = 3*((vcounter-down)/128)+(hcounter-left)/128;
if (occupied[j])
select = symbol[j]+1;
else
select = 0;
end else
select = 0;
end
assign row = ((vcounter-down)%128)/8;
assign col = ((hcounter-left)%128)/8;
word w(draw_out, row, col, select);
always @(*)
begin
if (visible && ~reset) begin
//draw lines on game board
VGA_R = 1'b1;
VGA_G = 1'b1;
VGA_B = 1'b1;
if (hcounter >= left && hcounter < left+384 && vcounter >= down && vcounter < down+384) begin
if (draw_out) begin
VGA_R = 1'b0;
VGA_G = 1'b0;
VGA_B = 1'b0;
end else begin
VGA_R = 1'b1;
VGA_G = 1'b1;
VGA_B = 1'b1;
end
end
if (hcounter ==left & vcounter>=down & vcounter<down+384)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
if (hcounter>=left+127 & hcounter<=left+128 & vcounter>=down & vcounter<down+384)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
if (hcounter>=left+255 & hcounter<=left+256 & vcounter>=down & vcounter<down+384)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
if (hcounter==left+384 & vcounter>=down & vcounter<down+384)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
if (hcounter>=left & hcounter<=left+384 & vcounter==down)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
if (hcounter>=left & hcounter<=left+384 & vcounter>=down+127 & vcounter<=down+128)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
if (hcounter>=left & hcounter<=left+384 & vcounter>=down+255 & vcounter<=down+256)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
if (hcounter>=left & hcounter<=left+384 & vcounter==down+384)
begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
end else begin
VGA_R=1'b0;
VGA_G=1'b0;
VGA_B=1'b0;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
// Speced ignored: system calls. I think this is nasty, so we error instead.
// Speced Illegal: inout/output/ref not allowed
localparam B1 = f_bad_output(1,2);
function integer f_bad_output(input [31:0] a, output [31:0] o);
f_bad_output = 0;
endfunction
// Speced Illegal: void
// Speced Illegal: dotted
localparam EIGHT = 8;
localparam B2 = f_bad_dotted(2);
function integer f_bad_dotted(input [31:0] a);
f_bad_dotted = t.EIGHT;
endfunction
// Speced Illegal: ref to non-local var
integer modvar;
localparam B3 = f_bad_nonparam(3);
function integer f_bad_nonparam(input [31:0] a);
f_bad_nonparam = modvar;
endfunction
// Speced Illegal: needs constant function itself
// Our own - infinite loop
localparam B4 = f_bad_infinite(3);
function integer f_bad_infinite(input [31:0] a);
while (1) begin
f_bad_infinite = 0;
end
endfunction
// Our own - stop
localparam BSTOP = f_bad_stop(3);
function integer f_bad_stop(input [31:0] a);
$stop;
endfunction
endmodule
|
/*
* File: pippo_pipectrl.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* Á÷Ë®Ïß¿ØÖÆÐźţ¬Ö÷Òª²úÉú
* pc_freeze£º¶³½áPC¼Ä´æÆ÷£¬±£´æµ±Ç°Öµ
* if_freeze£º±íʾIF¶ÎÎÞ·¨½ÓÊÜвÙ×÷
* id_freeze£º±íʾID¶ÎÎÞ·¨½ÓÊÜвÙ×÷
* ex_freeze£º±íʾEXE¶ÎÎÞ·¨½ÓÊÜвÙ×÷
* wb_freeze£º¶³½áд»Ø²Ù×÷£¬ÓÉÓÚÄ¿Ç°µÄÈý¼¶Á÷Ë®Éè¼Æ£¬wb_freezeµÈͬÓÚex_freeze
* ÒÔ¿ØÖÆÁ÷Ë®Ï߼ĴæÆ÷£¨Ö÷ÒªÊÇxx_ciaºÍxx_instµÈ£©ÐÐΪ¡£
* Specification
1. ¶³½áÁ÷Ë®Ïß
ÔÚÁ÷Ë®ÏßÓöµ½ÒÔÏÂÇéÐΣ¬±ØÐë¶ÔÁ÷Ë®ÏßÊ©¼Ó¿ØÖÆÒÔ±£Ö¤Ö¸ÁîÁ÷˳ÐòÖ´Ðв¢Íê³É¡£
£¨1£© ijЩָÁîÀàÐÍÐèÒªÔö¼ÓÁ÷Ë®¼¶£¬Èç·Ã´æÖ¸ÁîÐèÔö¼ÓMAÁ÷Ë®¼¶
£¨2£© ijÁ÷Ë®¶ÎÓÉÓÚ¸÷ÖÖÔÒòÐèÒª¶à¸öÖÜÆÚÍê³Éʱ£¬È縴ÔÓËãÊõÔËËãÖ¸Áî
£¨3£© Ö¸ÁîÖ´ÐÐʧ°Ü£¬Èç·Ã´æÖ¸ÁîÒý·¢µÄÖжϣ¬ÐèÒªÖÐÖ¹Ö¸ÁîµÄÍê³É
£¨4£© ÒÔÉ϶àÖÖÇé¿öͬʱ·¢Éú£¨·Ã´æÖ¸Áî·ÃÎÊ»º´æµ«miss£©
¸÷Á÷Ë®½×¶ÎÒý·¢µÄstallÇëÇóÈçÏ£º
IF¶Î£ºÈ¡»ØÖ¸ÁîµÄµÈ´ýÖÜÆÚ£¬ÓÐifÄ£¿éµÄif_stallÇëÇó
ID¶Î£ºÎÞ£¨ÒëÂë¼ì²âµ½·ÖÖ§Ö¸ÁÓÐidÄ£¿éµÄbp_stallÇëÇó£©
EX¶Î£º¶àÖÜÆÚÖ´ÐвÙ×÷£¨·Ã´æºÍ¸´ÔÓËãÊõÔËËãÖ¸Á£¬ÓÐlsu_stallºÍmulticycle_stallÇëÇó
ÔÚ×ÛºÏÆÀ¹ÀÁ÷Ë®Ïß״̬ºÍstallÇëÇóÖ®ºó£¬²úÉúfreezeÐźſØÖÆÁ÷Ë®ÏßÍƽø£Õý³£Á÷¶¯£¬²åÈëBubble£¨NOP»òKCS£©µÈ
¸÷Á÷Ë®¶Î¶³½á£¨freeze£©¹æÔò£ºµ±Ïֽ׶βúÉústallÇëÇó£¬Ç°Ò»¼¶Á÷Ë®±ØÐ붳½á£¬ÒÔ±ÜÃâoverlapping
µ±µÚÒ»¼¶Á÷Ë®(IF)³öÏÖstallÇëÇóʱ£¬IF¶Î¶³½á
[ͬһÖÜÆÚÄÚIF miss I$£¬·Ã´æÖ¸Áîhit D$µÄÇé¿ö]
¶³½áÐźÅÓ¦ÓùæÔòÈçÏ£ºÃ¿Ò»¼¶µÄÁ÷Ë®¼Ä´æÆ÷ά»¤ÊÜÇ°ºóÁ½¼¶Á÷Ë®ÏßµÄfreezeÐźſØÖÆ¡£
µ±Ç°¶Ë¶³½áºó¶ËÕý³£Ê±£¬²åÈëNOP£»
µ±Ç°¶Ë¶³½áºó¶Ë¶³½áʱ£¬±£³Öµ±Ç°×´Ì¬£»
µ±Ç°¶ËÕý³£ºó¶ËÕý³£Ê±£¬Õý³£Íƽø
Ç°¶ËÕý³£ºó¶Ë¶³½áµÄÇé¿ö²»·ûºÏfreezeÐźŲúÉú¹æÔò
2. Ë¢ÐÂÁ÷Ë®Ïß
³ýÊÜfreezeÐźſØÖÆÍ⣬Á÷Ë®ÏßÔÚÏÂÃæÇé¿öÏÂÐèҪˢÐÂÁ÷Ë®ÏߣÅÅ¿ÕÏÖÓÐÖ¸ÁÖØÐÂÈ¡Ö¸
£¨1£©Öжϴ¦ÀíÄ£¿é²úÉúµÄflush_exceptÒÔË¢ÐÂÁ÷Ë®Ïß
£¨2£©·ÖÖ§´¦ÀíÄ£¿éÓÉÓÚ·ÖÖ§Ô¤²â´íÎó²úÉúµÄflush_branchÒÔË¢ÐÂÁ÷Ë®Ïß
3. PCά»¤ºÍ¸üÐÂ
PCά»¤ºÍ¸üÐÂÓÐÁ½ÖÖÇé¿öÐèÒª·Ö¿ª´¦Àí
£¨1£©Á÷Ë®Ï߶³½áʱ£¬±£³ÖÏÖÓÐÈ¡Ö¸µØÖ·PC£¬´ý¶³½á½â³ýºó¼ÌÐøÈ¡Ö¸
£¨2£©Á÷Ë®ÏßË¢ÐÂʱ£¬ÐèÒª·ÅÆúÏÖÓÐPC£¬´ýË¢ÐÂÍê³Éºó·Ö±ðʹÓÃnpc_xxxÖØÐÂÈ¡Ö¸
pc_freezeÔÚ´ÓÓÐЧ״̬»Ö¸´Ê±£¬
* List2do:
* [TBV] timing relationship between flushpipe and freeze.
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_pipectrl(
flush_except, flush_branch, flushpipe,
if_stall, lsu_stall, multicycle_cnt, asyn_stall,
pc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze
);
//
// I/O
//
// stall request from pipeline stages
input if_stall;
input lsu_stall;
input asyn_stall;
input [1:0] multicycle_cnt;
// freeze command to pipeline stages
output pc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
output wb_freeze;
// flush control
input flush_except;
input flush_branch;
output flushpipe;
//
// Internal wires and regs
//
wire multicycle_stall;
//
// flush pipelining
// at the last cycle of flushpipe assertion, new fetch address will send to pc register
// 1. when flush is raised by except processing, assert for two cycles.
// 2. when flush is raised by branch processing, assert for one cycle.
//
assign flushpipe = flush_except | flush_branch;
//
// PC freeze signal
//
// pc_freeze is just for dis-asserting fetch request
assign pc_freeze = flushpipe;
//
// Pipeline freeze generation:
//
assign multicycle_stall = |multicycle_cnt;
// notes for asyn_stall: see except module
assign if_freeze = if_stall | id_freeze;
assign id_freeze = ex_freeze;
assign ex_freeze = wb_freeze | asyn_stall;
assign wb_freeze = lsu_stall | multicycle_stall;
/*
Implementation: Memory access instructions with update, under 3r1w rf design
a. Load with update instructions
pipectrl.v
×¢Ò⣺multicycle_stallÌõ¼þÒ²Ðë±ä»¯£¬µ±wb_twiceÓÐЧʱ£¬ÏÂÒ»ÌõÖ¸ÁîÒýÆðmulticycle_stall²»ÄÜÖÃÆð
rf.v
we & (~wb_freeze | wb_at_fze) //write enable logic
wb_twice come from rfwbop, and more to do:
1. logic for write address and source
2. write order of EA and loaded data?
3. wb_atfzeÓÐЧʱ¼äÖ»ÄÜÒ»ÅÄ
b. Store with update instructions
×¢ÒâÐèҪͬ²½storeµÄÍê³ÉºÍupdate£¨Ð´EA»ØRA£©µÄÍê³É
Logic.a: ¿ÉÒÔд»Øʱ£¬¶³½áwb£¬Ð´»ØÒ»´Î£¬ÔٽⶳÍê³ÉµÚ¶þ´Îд»Ø£»
pipectrl.v
//wb_atfze means: wb_freeze is asserted by wb_twice only, at this case, write-back can go.
assign wb_freeze_a = lsu_stall | multicycle_stall;
assign wb_freeze = wb_freeze_a | wb_atfze;
always @(posedge clk or posedge rst) begin
if (rst)
wb_atfze <= #1 1'b0;
else if(wb_freeze_a)
wb_atfze <= #1 rfwb_uops[0] & rfwb_uops[1];
else
wb_atfze <= #1 1'b0;
end
reg_gprs.v
assign rf_we = (~flushpipe) & ((wea & ~wb_freeze) |(wea & wb_atfze) | (web & ~wb_freeze)) ;
assign rf_addrw = wea & (!web | wb_atfze) ? addrwa : web ? addrwb : 5'd0;
assign rf_dataw = wea & (!web | wb_atfze) ? datawa : web ? datawb : 32'd0;
operandmux.v/wbmux.v
Èç¹ûʹÓÃת·¢Âß¼£¬ÔòwraºÍwrbµÄת·¢ÐèÒªÔö¼ÓÓÐЧÂß¼£»¼Æ»®ÊµÏÖÓÚwbmuxÄ£¿é
(gpr_addr_rda == ex_gpr_addr_wra) && (ex_rfwb_uops[0] & !ex_rfwb_uops[1])
(gpr_addr_rda == ex_gpr_addr_wrb) && (ex_rfwb_uops[1] & !wb_atfze)
Logic.b: ÏÈд»ØÒ»´Î£¬ÔÙ¶³½áwb¶ÎÍê³ÉµÚ¶þ´Îд»Ø£»µ¼ÖÂÎÊÌ⣺
1£¬ÏÂÒ»ÌõÖ¸ÁîÒѾ½øÈëexe¶Î£¬Èç¹ûÊǶàÖÜÆÚÖ¸ÁîÔò»áµ¼ÖÂwb_atfze±£³ÖÓÐЧ
2£¬ÐèÒª¼Ä´æaddr_wrºÍeaµÈ
assign wb_freeze_a = lsu_stall | multicycle_stall;
assign wb_freeze = wb_freeze_a | wb_atfze;
always @(posedge clk or posedge rst) begin
if (rst)
wb_atfze <= #1 1'b0;
else if(!wb_freeze_a)
wb_atfze <= #1 rfwb_uops[0] & rfwb_uops[1];
end
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<int> adj[n]; int deg[n]; for (int i = 0; i < n; i++) { deg[i] = 0; } for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; a--; b--; adj[a].push_back(b); adj[b].push_back(a); deg[a]++; deg[b]++; } vector<int> li; for (int i = 0; i < n; i++) { if (deg[i] == 1) { li.push_back(i); } } for (int i = 0; i < li.size(); i++) { int now = li[i]; for (int j = 0; j < adj[now].size(); j++) { int to = adj[now][j]; deg[to]--; if (deg[to] == 1) { li.push_back(to); } } } if (li.size() != n) { cout << No << endl; return 0; } bool v[n]; int deep[n]; for (int i = 0; i < n; i++) { v[i] = false; deep[i] = -1; } v[li[n - 1]] = true; deep[li[n - 1]] = 0; bool ok = true; for (int i = n - 1; i >= 0; i--) { int now = li[i]; if (!v[now] || deep[now] > k) { ok = false; break; } int red = adj[now].size(); if (i < n - 1) { red--; } if (red < 3 && deep[now] != k) { ok = false; break; } for (int j = 0; j < adj[now].size(); j++) { int to = adj[now][j]; if (!v[to]) { v[to] = true; deep[to] = deep[now] + 1; } } } cout << (ok ? Yes : No ) << endl; } |
// Copyright (c) 2013 Gueho Choi, Andrew Downing
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////////////////////////
// module: instruction memory ( 8 x 256 )
// inputs: ReadEnable(rdEn), WriteEnable(wrEn), Address(addr), WriteData(wrData)
// outputs: Data(Data)
//
////////////////////////////////////////////////////////////
module InstrucMemoryHardcoded (Clk, rdEn, wrEn, addr, wrData, Data);
parameter WIDTH = 8;
parameter DEPTH = 256;
input Clk;
input rdEn, wrEn;
input [WIDTH-1:0] wrData;
input [7:0] addr;
output [WIDTH-1:0] Data;
reg [WIDTH-1:0] data_out;
always @ (posedge Clk)
begin : INST_MEMORY
case (addr)
// DIVIDER
// initialization
8'h0: data_out <= 32'h0c_00_09_xx; // dividend (addr 0) = 9
8'h1: data_out <= 32'h0c_01_04_xx; // divisor (addr 1) = 4
8'h2: data_out <= 32'h0c_02_00_xx; // quotient (addr 2) = 0
8'h3: data_out <= 32'h0c_c0_00_xx; // constant 0 (addr c0) = 0
8'h4: data_out <= 32'h0c_c1_01_xx; // constant 1 (addr c1) = 1
8'h5: data_out <= 32'h0c_c4_04_xx; // constant 4 (addr c4) = 4
8'h6: data_out <= 32'h08_10_xx_xx; // jump to instruction 10 (hardcoded inputs) or 20 (user input)
// division by repeated subtraction
8'h10: data_out <= 32'h01_00_00_01; // dividend = dividend - divisor
8'h11: data_out <= 32'h0b_14_00_xx; // if dividend < 0 then jump to instruction 14
8'h12: data_out <= 32'h00_02_02_c1; // quotient = quotient + 1
8'h13: data_out <= 32'h08_10_xx_xx; // jump to instruction 10
// calculate remainder, display output, and exit
8'h14: data_out <= 32'h00_03_00_01; // remainder (addr 3) = dividend + divisor
8'h15: data_out <= 32'h0d_fa_03_xx; // ssd0 = remainder
8'h16: data_out <= 32'h02_fb_03_c4; // ssd1 = remainder >> 4
8'h17: data_out <= 32'h0d_fc_02_xx; // ssd2 = quotient
8'h18: data_out <= 32'h02_fd_02_c4; // ssd3 = quotient >> 4
8'h19: data_out <= 32'h0f_xx_xx_xx; // end program
// get inputs from user
8'h20: data_out <= 32'h09_22_e4_xx; // if BtnL = 0 then jump to instruction 22
8'h21: data_out <= 32'h0d_00_e0_xx; // dividend = FPGA switches
8'h22: data_out <= 32'h09_24_e1_xx; // if BtnR = 0 then jump to instruction 24
8'h23: data_out <= 32'h0d_01_e0_xx; // divisor = FPGA switches
8'h24: data_out <= 32'h0d_fa_01_xx; // ssd0 = divisor
8'h25: data_out <= 32'h02_fb_01_c4; // ssd1 = divisor >> 4
8'h26: data_out <= 32'h0d_fc_00_xx; // ssd2 = dividend
8'h27: data_out <= 32'h02_fd_00_c4; // ssd3 = dividend >> 4
8'h28: data_out <= 32'h0a_10_e3_xx; // if BtnU > 0 then jump to instruction 10
8'h29: data_out <= 32'h08_20_xx_xx; // jump to instruction 20
/*
// ADDER
8'h0: data_out <= 32'h0c_00_01_xx; // addend0 (addr 0) = 1
8'h1: data_out <= 32'h0c_01_01_xx; // addend1 (addr 1) = 1
8'h2: data_out <= 32'h0c_c4_04_xx; // constant 4 (addr c4) = 4
8'h3: data_out <= 32'h09_05_e4_xx; // if BtnL = 0 then jump to instruction 5
8'h4: data_out <= 32'h0d_00_e0_xx; // addend0 = FPGA switches
8'h5: data_out <= 32'h09_07_e1_xx; // if BtnR = 0 then jump to instruction 7
8'h6: data_out <= 32'h0d_01_e0_xx; // addend1 = FPGA switches
8'h7: data_out <= 32'h00_02_00_01; // sum (addr 2) = addend0 + addend1
8'h8: data_out <= 32'h0d_fa_02_xx; // ssd0 = sum
8'h9: data_out <= 32'h02_fb_02_c4; // ssd1 = sum >> 4
8'ha: data_out <= 32'h0d_fc_01_xx; // ssd2 = addend2
8'hb: data_out <= 32'h0d_fd_00_xx; // ssd3 = addend1
8'hc: data_out <= 32'h08_03_xx_xx; // jump to instruction 3
*/
/*
// TEST EVERY INSTRUCTION
8'h0: data_out <= 32'h0c_a2_05_xx;
8'h1: data_out <= 32'h0c_a3_03_xx;
8'h2: data_out <= 32'h00_a1_a2_a3; // add
8'h3: data_out <= 32'h01_a1_a2_a3; // sub
8'h4: data_out <= 32'h0c_a2_04_xx;
8'h5: data_out <= 32'h0c_a3_02_xx;
8'h6: data_out <= 32'h02_a1_a2_a3; // rshift
8'h7: data_out <= 32'h03_a1_a2_a3; // lshift
8'h8: data_out <= 32'h0c_a2_03_xx;
8'h9: data_out <= 32'h0c_a3_11_xx;
8'ha: data_out <= 32'h04_a1_a2_a3; // and
8'hb: data_out <= 32'h05_a1_a2_a3; // or
8'hc: data_out <= 32'h06_a1_a2_a3; // xor
8'hd: data_out <= 32'h07_a1_a2_xx; // inv
8'he: data_out <= 32'h0c_c0_00_xx;
8'hf: data_out <= 32'h0c_c1_01_xx;
8'h10: data_out <= 32'h0c_cf_ff_xx;
8'h11: data_out <= 32'h08_13_xx_xx; // jmp
8'h13: data_out <= 32'h09_ff_cf_xx; // jeq0 -1
8'h14: data_out <= 32'h09_ff_c1_xx; // jeq0 1
8'h15: data_out <= 32'h09_17_c0_xx; // jeq0 0
8'h17: data_out <= 32'h0a_ff_cf_xx; // jgt0 -1
8'h18: data_out <= 32'h0a_ff_c0_xx; // jgt0 0
8'h19: data_out <= 32'h0a_1b_c1_xx; // jgt0 1
8'h1b: data_out <= 32'h0b_ff_c0_xx; // jlt0 0
8'h1c: data_out <= 32'h0b_ff_c1_xx; // jlt0 1
8'h1d: data_out <= 32'h0b_1f_cf_xx; // jlt0 -1
8'h1f: data_out <= 32'h0c_a1_05_xx;
8'h20: data_out <= 32'h0d_a2_a1_xx; // copy
9'h21: data_out <= 32'h0d_a3_a2_xx; // copy
9'h22: data_out <= 32'h0f_xx_xx_xx; // halt
*/
default: data_out <= 32'hxx_xx_xx_xx;
endcase
end
assign Data = data_out;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 09:34:25 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; template <typename T> using minpq = priority_queue<T, vector<T>, greater<T>>; long long pl, pr, vl, vr; int k; long long inter(long long a, long long b, long long c, long long d) { return max(0LL, min(b, d) - max(a, c) + 1); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> pl >> pr >> vl >> vr >> k; long double ans = 0; vector<long long> lucky; for (int len = (0); len < (11); len++) { for (int x = (0); x < ((1 << len)); x++) { long long y = 0; for (int i = (0); i < (len); i++) { if ((x >> i) & 1) { y = y * 10 + 4; } else { y = y * 10 + 7; } } lucky.push_back(y); } } sort((lucky).begin(), (lucky).end()); int n = ((int)(lucky).size()); for (int i = (1); i < (n - k); i++) { int j = i + k; ans += 1.0 * inter(pl, pr, lucky[i - 1] + 1, lucky[i]) * inter(vl, vr, lucky[j - 1], lucky[j] - 1); ans += 1.0 * inter(vl, vr, lucky[i - 1] + 1, lucky[i]) * inter(pl, pr, lucky[j - 1], lucky[j] - 1); if (k == 1 && pl <= lucky[i] && lucky[i] <= pr && vl <= lucky[i] && lucky[i] <= vr) ans--; } ans /= 1.0 * (pr - pl + 1) * (vr - vl + 1); cout << fixed << setprecision(11) << ans << n ; } |
/*###########################################################################
*#Clock buffer with built in divider
*###########################################################################
*
* Division ratios: 1,2,3,4,5,6,7,8, and bypass division ratings
*
* BUFRs can drive:
* -I/O logic
* -logic resources
*
* BUFRs can be driven by:
* -SRCCs and MRCCs in the same clock region
* -MRCCs in an adjacent clock region using BUFMRs
* -MMCMs clock outputs 0-3 driving the HPC in the same clock region
* -MMCMs clock outputs 0-3
* -General interconnect
*
* Input to Output Delay (Zynq7010/7020): 1.04/0.80/0.64 (-1/-2/-3 grade)
*
*/
module BUFR (/*AUTOARG*/
// Outputs
O,
// Inputs
I, CE, CLR
);
parameter BUFR_DIVIDE=4;
parameter SIM_DEVICE=0;
input I; //clock input
input CE; //async output clock enable
input CLR; //async clear for divider logic
output O; //clock output
//assign O=I & CE & ~CLR;
//TODO: need to paraemtrize this!!!
clock_divider clock_divider (
// Outputs
.clkout (O),
// Inputs
.clkin (I),
.divcfg (4'b0010),//div4
.reset (CLR)
);
endmodule // IBUFDS
// Local Variables:
// verilog-library-directories:("../../common/hdl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LOWHVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int N, M; const double EPS = 1E-9; double solve(int r, int c) { vector<double> res(M, 0); for (int y = N - 2; y >= r; y--) { if (M == 1) { res[0] = 2 + res[0]; } else { vector<double> a(M), b(M); a[0] = 1 / 2.0; b[0] = (3 + res[0]) / 2; for (int j = 1; j < M; j++) { a[j] = 1.0 / (3 - a[j - 1]); b[j] = (4 + res[j] + b[j - 1]) / (3 - a[j - 1]); } res[M - 1] = (b[M - 2] + 3 + res[M - 1]) / (2 - a[M - 2]); for (int j = M - 2; j >= 0; j--) { res[j] = a[j] * res[j + 1] + b[j]; } } } return res[c]; } int main(int argc, char* argv[]) { scanf( %d %d , &N, &M); int r, c; scanf( %d %d , &r, &c); double res = solve(r - 1, c - 1); printf( %9lf n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[500005]; int q[500005]; int n, k, d; int main() { scanf( %d%d%d , &n, &k, &d); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); int l = 1, r = 1; q[l] = 0; for (int i = k; i <= n; i++) { while (l <= r && a[i] - a[q[l] + 1] > d) l++; if (l <= r && i - q[l] >= k) q[++r] = i; } if (q[r] == n) printf( YES n ); else printf( NO n ); return 0; } |
`timescale 1ns / 1ps
`include "../src/axis_bayer_extractor.v"
module test_bayer_extractor(
);
localparam RANDOMOUTPUT = 0;
localparam RANDOMINPUT = 0;
localparam C_COL_ODD = 0;
localparam C_ROW_ODD = 0;
wire[7:0] mdata;
wire mlast;
reg mready;
wire muser;
wire mvalid;
wire[7:0] sdata;
wire slast;
wire sready;
wire suser;
reg svalid;
reg[11:0] ori_height = 10;
reg[11:0] ori_width = 10;
reg resetn;
reg clk;
axis_bayer_extractor #(
.C_PIXEL_WIDTH(8),
.C_COL_ODD(C_COL_ODD),
.C_ROW_ODD(C_ROW_ODD)
)uut(
.m_axis_tdata(mdata),
.m_axis_tlast(mlast),
.m_axis_tready(mready),
.m_axis_tuser(muser),
.m_axis_tvalid(mvalid),
.s_axis_tdata(sdata),
.s_axis_tlast(slast),
.s_axis_tready(sready),
.s_axis_tuser(suser),
.s_axis_tvalid(svalid),
.clk(clk),
.resetn(resetn));
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
reg[11:0] in_row;
reg[11:0] in_col;
assign sdata = (in_row * 16 + in_col);
reg[11:0] out_row;
reg[11:0] out_col;
reg[7:0] out_data;
reg out_last;
assign suser = (in_row == 0 && in_col == 0);
assign slast = (in_col == ori_height - 1);
reg randominput;
reg randomoutput;
always @(posedge clk) begin
if (resetn == 1'b0)
randominput <= 1'b0;
else
randominput <= (RANDOMINPUT ? {$random}%2 : 1);
if (resetn == 1'b0)
randomoutput <= 1'b0;
else
randomoutput <= (RANDOMOUTPUT ? {$random}%2 : 1);
if (resetn == 1'b0) begin
in_row <= 0;
in_col <= 0;
end
else if (svalid && sready) begin
if (in_col != ori_width - 1) begin
in_col <= in_col + 1;
in_row <= in_row;
end
else if (in_row != ori_height - 1) begin
in_col <= 0;
in_row <= in_row + 1;
end
else begin
in_row <= 0;
in_col <= 0;
end
end
if (resetn == 1'b0)
svalid <= 1'b0;
else if (~svalid) begin
if (randominput) begin
svalid <= 1'b1;
end
end
else if (svalid && sready) begin
if (randominput) begin
svalid <= 1'b1;
end
else begin
svalid <= 1'b0;
end
end
if (resetn == 1'b0)
mready <= 1'b0;
else if (randomoutput)
mready <= 1'b1;
else
mready <= 1'b0;
if (resetn == 1'b0) begin
out_data <= 0;
out_last <= 0;
end
else if (mready && mvalid) begin
out_data <= mdata;
out_last <= mlast;
end
if (resetn == 1'b0) begin
out_col = 0;
out_row = 0;
end
else if (mready && mvalid) begin
if (muser) begin
out_col = 0;
out_row = 0;
end
else if (out_last) begin
out_col = 0;
out_row = out_row + 1;
end
else begin
out_col = out_col + 1;
out_row = out_row;
end
if (muser)
$write("start new frame: \n");
$write("%h ", mdata);
if (mlast)
$write("\n");
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
module reset_extender
#(parameter C_RST_COUNT = 10)
(input CLK,
input RST_BUS,
input RST_LOGIC,
output RST_OUT,
output PENDING_RST);
localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
localparam C_RST_SHIFTREG_DEPTH = 4;
wire [C_CLOG2_RST_COUNT:0] wRstCount;
wire [C_RST_SHIFTREG_DEPTH:0] wRstShiftReg;
assign PENDING_RST = wRstShiftReg != 0;
assign RST_OUT = wRstShiftReg[C_RST_SHIFTREG_DEPTH];
counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (RST_BUS | RST_LOGIC),
/*AUTOINST*/
// Inputs
.CLK (CLK));
shiftreg
#(// Parameters
.C_DEPTH (C_RST_SHIFTREG_DEPTH),
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wRstShiftReg),
// Inputs
.RST_IN (0),
.WR_DATA (~wRstCount[C_CLOG2_RST_COUNT]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_8_V
`define SKY130_FD_SC_LP__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_8_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a, i, j, mid, cnt = 0; cin >> n; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { cin >> a; if (i == j) cnt = cnt + a; if (i + j == n - 1) cnt = cnt + a; if (i == n / 2) cnt = cnt + a; if (j == n / 2) cnt = cnt + a; if (i == n / 2 && j == n / 2) mid = a; } } cout << cnt - (3 * mid) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int N = 1e5 + 7; int pre[N], sz[N], cnt[N], n, lencnt, dx, one; pair<int, int> a[N]; void init() { memset(pre, -1, sizeof(pre)); } int fd(int n) { return pre[n] == -1 ? n : pre[n] = fd(pre[n]); } void mg(int a, int b) { a = fd(a), b = fd(b); if (a != b) { pre[b] = a; sz[a] += sz[b]; sz[b] = 0; } } void solve(int x) { int v = x + 1; if (v <= n && sz[fd(v)]) { if (--cnt[sz[fd(v)]] == 0) --lencnt; if (--cnt[sz[x]] == 0) --lencnt; mg(x, v); if (++cnt[sz[fd(v)]] == 1) ++lencnt; } v = x - 1; if (v >= 1 && sz[fd(v)]) { if (--cnt[sz[fd(v)]] == 0) --lencnt; if (--cnt[sz[fd(x)]] == 0) --lencnt; mg(x, v); if (++cnt[sz[fd(v)]] == 1) ++lencnt; } one = cnt[sz[fd(x)]]; } int main(void) { int i; scanf( %d , &n); init(); for (i = 1; i <= n; ++i) { scanf( %d , &a[i].first); a[i].second = i; } sort(a + 1, a + 1 + n); int ans = 1; for (i = 1; i <= n; ++i) { sz[a[i].second] = 1; if (++cnt[1] == 1) ++lencnt; solve(a[i].second); if (lencnt == 1 && one > dx) { ans = a[i].first + 1; dx = one; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; struct node { int l, r, sum; } hjt[maxn * 40]; int a[maxn], root[maxn], cnt; int last[maxn]; void insert(int l, int r, int pre, int &now, int p, int v) { hjt[++cnt] = hjt[pre]; now = cnt; hjt[now].sum = hjt[pre].sum + v; if (l == r) return; int m = (l + r) >> 1; if (p <= m) insert(l, m, hjt[pre].l, hjt[now].l, p, v); else insert(m + 1, r, hjt[pre].r, hjt[now].r, p, v); } int query(int now, int l, int r, int k) { if (l == r) { if (hjt[now].sum <= k) return l; return l - 1; } int mid = (l + r) >> 1; int tmp = hjt[hjt[now].l].sum; if (tmp > k) return query(hjt[now].l, l, mid, k); else return query(hjt[now].r, mid + 1, r, k - tmp); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = n; i >= 1; i--) { if (last[a[i]]) { insert(1, n, root[i + 1], root[i], last[a[i]], -1); insert(1, n, root[i], root[i], i, 1); } else insert(1, n, root[i + 1], root[i], i, 1); last[a[i]] = i; } for (int i = 1; i <= n; i++) { int ans = 0, l = 1, r = 0; while (l <= n) { r = query(root[l], 1, n, i); l = r + 1; ans++; } cout << ans; if (i == n) cout << n ; else cout << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, l = 0, r = 0, x = 0, c[16]; cin >> n >> l >> r >> x; for (int i = 0; i < n; i++) cin >> c[i]; sort(c, c + n); int total = 0, cnt = 0, ret = 0, easy = 0, hard = 0; for (int i = 0; i < (1 << n); i++) { total = 0, cnt = 0; for (int j = 0; j < n; j++) { if ((1 << j) & i) { if (cnt == 0) { easy = c[j]; } total += c[j]; cnt++; hard = c[j]; } } if (cnt > 1 && total >= l && total <= r && hard - easy >= x) { ret++; } } cout << ret; return 0; } |
/*
* Copyright (c) 2000 Mark Schellhorn <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/****************************************************************************
The following code illustrates an apparent bug in the VCS v5.2 simulator.
The check for whether or not the memory[0] array element was set correctly
fails; yet the $display statement immediately after the check shows the
memory[0] element actually has been set correctly.
I've noted that if the $display and the check are reversed, the $display
is incorrect but the check passes.
This appears to be a problem with the simulator's internal scheduler.
***************************************************************************/
module bug_test;
reg [1:0] temp;
initial begin
/********** First test. */
$display("Running first test.\n");
// Try setting memory array in other module using hierarchical
// references & concatenation.
temp = 2'h3;
top.memory.memory[0] = {2'h0,temp};
top.memory.memory[0] = {top.memory.memory[0],temp};
// Check that setting was made correctly
if (top.memory.memory[0] != {2{temp}}) begin
$display("ERROR! top.memory.memory[0] failed to get");
$display("set correctly!");
end else begin
$display("PASS! top.memory.memory[0] set correctly.");
end
// Display the value that was checked
$display("top.memory.memory[0] = %h",top.memory.memory[0]);
/********** Second test. */
$display("\nRunning second test.\n");
// Try setting memory array in other module using hierarchical
// references & concatenation.
temp = 2'h3;
top.memory.memory[1] = {2'h0,temp};
top.memory.memory[1] = {top.memory.memory[1],temp};
// Display the value that will be checked
$display("top.memory.memory[1] = %h",top.memory.memory[1]);
// Check that setting was made correctly
if (top.memory.memory[1] != {2{temp}}) begin
$display("ERROR! top.memory.memory[1] failed to get");
$display("set correctly!");
end else begin
$display("PASS! top.memory.memory[1] set correctly.");
end
// Display the value that was checked
$display("top.memory.memory[1] = %h",top.memory.memory[1]);
$finish;
end
endmodule
// Module containing a memory array
module memory;
reg [3:0] memory [0:1];
endmodule
// Module to instantiate test and memory modules
module top;
bug_test bug_test();
memory memory();
endmodule
|
/* Simple button module */
module button (
// input clock
clk,
// I/O pins
pin_in,
press,
);
input clk;
input pin_in;
output press;
/* Pull-up settings for input:
PIN_TYPE: <output_type=0>_<input=1>
PULLUP: <enable=1>
PACKAGE_PIN: <user pad name>
D_IN_0: <internal pin wire (data in)>
*/
wire pin_din;
SB_IO #(
.PIN_TYPE(6'b0000_01),
.PULLUP(1'b1)
) pin_in_config (
.PACKAGE_PIN(pin_in),
.D_IN_0(pin_din)
);
/* Debouncing timer and period = 10 ms */
reg [31:0] debounce_timer = 32'b0;
parameter DEBOUNCE_PERIOD = 32'd120000;
reg debouncing = 1'b0;
reg buttonpress = 1'b0;
assign press = buttonpress;
/* Our high speed clock will deal with debounce timing */
always @ (posedge clk) begin
// check for button presses
if (~debouncing && ~pin_din) begin
buttonpress <= 1;
debouncing <= 1;
// reset debouncing if button is held low
end else if (debouncing && ~pin_din) begin
debounce_timer <= 32'b0;
// or if it's high, increment debounce timer
end else if (debouncing && debounce_timer < DEBOUNCE_PERIOD) begin
debounce_timer <= debounce_timer + 1;
// finally, if it's high and timer expired, debouncing done!
end else if (debouncing) begin
debounce_timer <= 32'b0;
debouncing <= 1'b0;
buttonpress <= 0;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; void add(int& x, int y) { ((x += y) >= MOD) && (x -= MOD); } void sub(int& x, int y) { add(x, -y + MOD); } int mul(int x, int y) { return x * 1ll * y % MOD; } int mpow(int a, int p) { int res = 1; for (; p > 0; p >>= 1, a = mul(a, a)) { if (p & 1) { res = mul(res, a); } } return res; } const int MAXN = 50 + 10; int mem_inv[MAXN]; int inv(int x) { int& y = mem_inv[x]; if (y) { return y; } y = mpow(x, MOD - 2); assert(mul(x, y) == 1); return y; } int n, m; bool read() { if (scanf( %d%d , &n, &m) < 2) { return 0; } n += 2; return 1; } int dp2[MAXN][MAXN]; int dp[MAXN][MAXN]; int dp_big[MAXN][MAXN][MAXN][MAXN]; int binom(int n, int k) { assert(k); add(n, k - 1); int ans = 1; for (int i = 0; i < int(k); ++i) { int cur_n = n; sub(cur_n, i); ans = mul(ans, cur_n); ans = mul(ans, inv(i + 1)); } return ans; } int calc_dp(int, int); int calc_dp2(int, int); int calc_dp_big(int, int, int, int); int calc_dp2(int n, int m) { if (n < 3) { return 0; } int& mem = dp2[n][m]; if (mem != -1) { return mem; } int ans = 0; for (int n_left = 2; n_left < n; ++n_left) { const int n_right = n - n_left + 1; for (int m_right = m; m_right < MAXN; ++m_right) { add(ans, mul(calc_dp(n_left, m), calc_dp(n_right, m_right))); } for (int m_left = m + 1; m_left < MAXN; ++m_left) { add(ans, mul(calc_dp(n_left, m_left), calc_dp(n_right, m))); } } return (mem = ans); } int calc_dp_big(int n, int m, int n1, int m1) { if (n < 2) { return 0; } if (n == 2) { return (m == 0); } if (m <= 0 || n1 < 3) { return 0; } assert(m1 >= 0); int& mem = dp_big[n][m][n1][m1]; if (mem != -1) { return mem; } int new_n1 = n1; int new_m1 = m1 - 1; if (new_m1 == -1) { new_n1--; new_m1 = MAXN - 1; } int ans = 0; for (int cnt = 0; (n1 - 2) * cnt + 2 <= n && m1 * cnt <= m; ++cnt) { int cur = cnt ? binom(calc_dp2(n1, m1), cnt) : 1; int will = calc_dp_big(n - (n1 - 2) * cnt, m - m1 * cnt, new_n1, new_m1); add(ans, mul(cur, will)); } return (mem = ans); } int calc_dp(int n, int m) { int& mem = dp[n][m]; if (mem != -1) { return mem; } int ans = calc_dp_big(n, m - 1, MAXN - 1, MAXN - 1); return (mem = ans); } int solve() { memset(dp2, -1, sizeof dp2); memset(dp, -1, sizeof dp); memset(dp_big, -1, sizeof dp_big); return calc_dp(n, m); } int main() { while (read()) { printf( %d n , solve()); } return 0; } |
//`define ZERO_BIT 1'b0
module PP_Compressor(i, pp0, pp1, pp2, pp3,
pp4, pp5, pp6, pp7,
pp8, pp9, pp10, pp11,
pp12, pp13, pp14, pp15,
pp16,
C, S);
input wire[15:0] i;
input wire[33:0] pp0;
input wire[33:0] pp1;
input wire[33:0] pp2;
input wire[33:0] pp3;
input wire[33:0] pp4;
input wire[33:0] pp5;
input wire[33:0] pp6;
input wire[33:0] pp7;
input wire[33:0] pp8;
input wire[33:0] pp9;
input wire[33:0] pp10;
input wire[33:0] pp11;
input wire[33:0] pp12;
input wire[33:0] pp13;
input wire[33:0] pp14;
input wire[33:0] pp15;
input wire[31:0] pp16;
output wire[62:0] C;
output wire[63:0] S;
supply0 ZERO_BIT;
wire[33:0] C11; wire[33:0] S11;
wire[33:0] C12; wire[33:0] S12;
wire[33:0] C13; wire[33:0] S13;
wire[33:0] C14; wire[33:0] S14;
wire[33:0] C21; wire[33:0] S21;
wire[37:0] C22; wire[37:0] S22;
wire[33:0] C23; wire[33:0] S23;
wire[33:0] C24; wire[33:0] S24;
wire[39:0] C31; wire[39:0] S31;
wire[38:0] C32; wire[38:0] S32;
wire[45:0] C41; wire[45:0] S41;
wire[45:0] C42; wire[45:0] S42;
wire[46:0] C51; wire[46:0] S51;
wire[56:0] C61; wire[56:0] S61;
wire[63:0] C71; wire[63:0] S71;
assign C = C71;
assign S = S71;
CSA #34 CSA13(
.a({{4{pp0[33]}}, pp0[33:4]}),
.b({{2{pp1[33]}}, pp1[33:2]}),
.cin(pp2[33:0]),
.cout(C13), .sum(S13));
CSA #34 CSA23(
.a(pp3[33:0]),
.b({C13[33], C13[33:1]}),
.cin({{2{S13[33]}}, S13[33:2]}),
.cout(C23), .sum(S23));
CSA #34 CSA14(
.a({{4{pp4[33]}}, pp4[33:4]}),
.b({{2{pp5[33]}}, pp5[33:2]}),
.cin(pp6[33:0]),
.cout(C14), .sum(S14));
CSA #34 CSA24(
.a({{2{pp7[33]}}, pp7[33:2]}),
.b(pp8[33:0]),
.cin({{3{C14[33]}}, C14[33:3]}),
.cout(C24), .sum(S24));
CSA #34 CSA11(
.a({{4{pp9[33]}}, pp9[33:4]}),
.b({{2{pp10[33]}}, pp10[33:2]}),
.cin(pp11[33:0]),
.cout(C11), .sum(S11));
CSA #34 CSA21(
.a(pp12[33:0]),
.b({C11[33], C11[33:1]}),
.cin({{2{S11[33]}}, S11[33:2]}),
.cout(C21), .sum(S21));
CSA #34 CSA12(
.a({{4{pp13[33]}}, pp13[33:4]}),
.b({{2{pp14[33]}}, pp14[33:2]}),
.cin(pp15[33:0]),
.cout(C12), .sum(S12));
CSA #38 CSA22(
.a({pp16[31:0], ZERO_BIT, i[15], {pp13[3:0]}}),
.b({C12[32:0], ZERO_BIT, {pp14[1:0], {2{ZERO_BIT}}}}),
.cin({S12[33:0], ZERO_BIT, i[14], ZERO_BIT, i[13]}),
.cout(C22), .sum(S22));
CSA #40 CSA31(
.a({{6{S21[33]}}, S21[33:0]}),
.b({C22[36:0], {3{ZERO_BIT}}}),
.cin({S22[37:0], ZERO_BIT, i[12]}),
.cout(C31), .sum(S31));
CSA #39 CSA32(
.a({C24[33:0], ZERO_BIT, {pp7[1:0], ZERO_BIT}, ZERO_BIT}),
.b({S24[33], S24[33:0], {C14[2:0]}, ZERO_BIT}),
.cin({{5{S14[33]}}, S14[33:0]}),
.cout(C32), .sum(S32));
CSA #46 CSA41(
.a({{5{C21[33]}}, C21[33:0], ZERO_BIT, {C11[0], ZERO_BIT}, {pp9[3:0]}}),
.b({C31[38:0], ZERO_BIT, {S11[1:0]}, {pp10[1:0], {2{ZERO_BIT}}}}),
.cin({S31[39:0], ZERO_BIT, i[11], ZERO_BIT, i[10], ZERO_BIT, i[9]}),
.cout(C41), .sum(S41));
CSA #46 CSA42(
.a({{11{C23[33]}}, C23[33:0], ZERO_BIT}),
.b({{12{S23[33]}}, S23[33:0]}),
.cin({C32[38:0], i[6], ZERO_BIT, i[5], ZERO_BIT, i[4], ZERO_BIT, i[3]}),
.cout(C42), .sum(S42));
CSA #47 CSA51(
.a({C42[45:0], ZERO_BIT}),
.b({{2{S32[38]}}, S32[38:0], {6{ZERO_BIT}}}),
.cin({S42[45], S42[45:0]}),
.cout(C51), .sum(S51));
CSA #57 CSA61(
.a({C41[44:0], {7{ZERO_BIT}}, {pp4[3:0]}, ZERO_BIT}),
.b({S41[45:0], ZERO_BIT, i[8], ZERO_BIT, i[7], {2{ZERO_BIT}}, {pp5[1:0], {2{ZERO_BIT}}}, ZERO_BIT}),
.cin({{10{C51[46]}}, C51[46:0]}),
.cout(C61), .sum(S61));
CSA #64 CSA71(
.a({C61[55:0], {2{ZERO_BIT}}, {C13[0], ZERO_BIT}, {pp0[3:0]}}),
.b({S61[56:0], ZERO_BIT, {S13[1:0]}, {pp1[1:0], {2{ZERO_BIT}}}}),
.cin({{11{S51[46]}}, S51[46:0], ZERO_BIT, i[2], ZERO_BIT, i[1], ZERO_BIT, i[0]}),
.cout(C71), .sum(S71));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_SYMBOL_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; double dp[2010][2010][2][2]; int a[2010]; pair<int, int> le[2010], ri[2010]; int ll[2010][2], rr[2010][2]; int h; double p, q; double go(int l, int r, int Li, int Ri) { if (l > r) return 0; if (dp[l][r][Li][Ri] > -1) { return dp[l][r][Li][Ri]; } int L = ll[l][Li], R = rr[r][Ri]; double res = 0; int d; if (L < le[l].second) { d = h; } else { d = a[l] - L; } res += 0.5 * p * (d + go(l + 1, r, 0, Ri)); if (R > ri[r].second) { d = h; } else { d = R - a[r]; } res += 0.5 * q * (d + go(l, r - 1, Li, 1)); if (ri[l].second > R) { d = R - a[l]; } else { d = ri[l].second - a[l]; } res += 0.5 * q * (d + go(ri[l].first + 1, r, 1, Ri)); if (le[r].second < L) { d = a[r] - L; } else { d = a[r] - le[r].second; } res += 0.5 * p * (d + go(l, le[r].first - 1, Li, 0)); return dp[l][r][Li][Ri] = res; } int main() { int n; scanf( %d%d%lf , &n, &h, &p); q = 1 - p; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } sort(a, a + n); for (int i = 0; i < n; i++) { le[i] = make_pair(0, a[0] - h); ri[i] = make_pair(i, a[i] + h); } for (int i = n - 2; i >= 0; i--) { if (a[i] + h > a[i + 1]) { ri[i] = ri[i + 1]; } else { ri[i] = make_pair(i, a[i] + h); } } for (int i = 1; i < n; i++) { if (a[i] - h < a[i - 1]) { le[i] = le[i - 1]; } else { le[i] = make_pair(i, a[i] - h); } } ll[0][0] = ll[0][1] = -1001001001; for (int i = 1; i < n; i++) { ll[i][0] = a[i - 1]; ll[i][1] = ri[i - 1].second; } rr[n - 1][0] = rr[n - 1][1] = 1001001001; for (int i = n - 2; i >= 0; i--) { rr[i][1] = a[i + 1]; rr[i][0] = le[i + 1].second; } for (int i = 0; i < 2010; i++) { for (int j = 0; j < 2010; j++) { for (int k = 0; k < 2; k++) { for (int l = 0; l < 2; l++) { dp[i][j][k][l] = -1; } } } } printf( %.12f n , go(0, n - 1, 0, 1)); return 0; } |
#include <bits/stdc++.h> int st, h, t, r, n, m, tot; int f[200 + 10][200 + 10] = {0}, g[200 + 10][200 + 10] = {0}; int a[200 + 10][2] = {0}, b[200 + 10][2] = {0}; bool hash[200 + 10][200 + 10] = {0}; int td = 0, top = 0, sum = 0; int totm[2] = {0}, e[2][10000000 + 10] = {0}, last[2][10000000 + 10] = {0}, now[2][40401 + 10] = {0}; int stack[40401 + 10] = {0}, low[40401 + 10] = {0}, dfn[40401 + 10] = {0}; int fa[40401 + 10] = {0}; bool ok[40401 + 10] = {0}, used[40401 + 10] = {0}; int dl[40401 + 10] = {0}, step[40401 + 10] = {0}; inline void set(bool t, int u, int v) { ++totm[t]; e[t][totm[t]] = v; last[t][totm[t]] = now[t][u]; now[t][u] = totm[t]; } inline void build() { int i, j, k, p, q; tot = (r + 1) * (r + 1); for (i = 0; i <= r; ++i) for (j = 0; i + j <= r; ++j) { for (k = 1; k <= n && k <= i; ++k) { p = i - k + a[k][0], q = j + a[k][1]; if (p + q <= r) set(0, i * (r + 1) + j + 1, p * (r + 1) + q + 1); } for (k = 1; k <= m && k <= j; ++k) { p = i + b[k][0], q = j - k + b[k][1]; if (p + q <= r) set(0, i * (r + 1) + j + 1, p * (r + 1) + q + 1); } } } inline void bfs() { int l = 0, r = 1; int i, j; dl[0] = st; step[st] = 1; while (l < r) { i = dl[l]; for (j = now[0][i]; j; j = last[0][j]) if (!step[e[0][j]]) { step[e[0][j]] = step[i] + 1; dl[r++] = e[0][j]; } ++l; } } void tarjan(int i) { int j; stack[++top] = i; dfn[i] = ++td; low[i] = td; for (j = now[0][i]; j; j = last[0][j]) { if (!dfn[e[0][j]]) { tarjan(e[0][j]); low[i] = ((low[i]) < (low[e[0][j]]) ? (low[i]) : (low[e[0][j]])); } else if (!fa[e[0][j]]) low[i] = ((low[i]) < (dfn[e[0][j]]) ? (low[i]) : (dfn[e[0][j]])); } if (low[i] == dfn[i]) { ++sum; do fa[stack[top]] = sum; while (stack[top--] != i); } } bool dfs3(int i) { if (ok[i]) return (1); if (used[i]) return (0); used[i] = 1; int j; for (j = now[1][i]; j; j = last[1][j]) if (dfs3(e[1][j])) return (1); return (0); } inline bool draw() { int i, j; for (i = 1; i <= tot; ++i) if (!dfn[i]) tarjan(i); for (i = 1; i <= tot; ++i) for (j = now[0][i]; j; j = last[0][j]) { if (fa[i] != fa[e[0][j]]) set(1, fa[i], fa[e[0][j]]); else ok[fa[i]] = 1; } return (dfs3(fa[h * (r + 1) + t + 1])); } int dfs2(int i, int j) { if (i + j > r) return (0); if (hash[i][j]) return (g[i][j]); hash[i][j] = 1; int k; for (k = 1; k <= n && k <= i; ++k) g[i][j] = ((g[i][j]) > (dfs2(i - k + a[k][0], j + a[k][1]) + 1) ? (g[i][j]) : (dfs2(i - k + a[k][0], j + a[k][1]) + 1)); for (k = 1; k <= m && k <= j; ++k) g[i][j] = ((g[i][j]) > (dfs2(i + b[k][0], j - k + b[k][1]) + 1) ? (g[i][j]) : (dfs2(i + b[k][0], j - k + b[k][1]) + 1)); return (g[i][j]); } int main() { int i, j; scanf( %d%d%d , &h, &t, &r); st = h * (r + 1) + t + 1; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d%d , &a[i][0], &a[i][1]); scanf( %d , &m); for (i = 1; i <= m; ++i) scanf( %d%d , &b[i][0], &b[i][1]); build(); bfs(); if (step[1]) printf( Ivan n%d n , step[1] - 1); else if (draw()) printf( Draw n ); else { memset(hash, 0, sizeof(hash)); printf( Zmey n%d n , dfs2(h, t)); } return (0); } |
#include <bits/stdc++.h> using namespace std; int gcd(int f, int s) { if (s == 0) return f; else return gcd(s, f % s); } int const N = 1002006; long long const M = 998244353; long double const ep = .000000000000000001; vector<int> G[N]; long long pw[N]; int od = 0, ev = 0; int vis[N]; bool wtf = 1; void dfs(int node, int col) { if (col % 2 == 0) ev++; else od++; vis[node] = col; for (int i = 0; i < G[node].size(); i++) { int el = G[node][i]; if (vis[el] == -1) dfs(el, col ^ 1); else if (col == vis[el]) wtf = 0; } } int main() { pw[0] = 1; for (int i = 1; i < N; i++) pw[i] = (pw[i - 1] * 2) % M; int t; cin >> t; while (t--) { int n, e; scanf( %d%d , &n, &e); for (int i = 1; i <= n; i++) { G[i].clear(); vis[i] = -1; } for (int i = 0; i < e; i++) { int temp, temp1; scanf( %d%d , &temp, &temp1); G[temp].push_back(temp1); G[temp1].push_back(temp); } wtf = 1; long long ans = 1; for (int i = 1; i <= n; i++) { if (vis[i] == -1) { od = 0, ev = 0; dfs(i, 0); long long tot = pw[od] + pw[ev]; tot %= M; ans = (ans * tot) % M; } } ans *= wtf; printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> h; vector<vector<int> > g; int h0, v0; vector<int> val; int it = 0; vector<bool> used; vector<int> treesum, par; vector<int> treemin; void update(int v, int l, int r, int ind, int d) { if (l == r) { treesum[v] += d; treemin[v] += d; return; } if (ind <= (r + l) / 2) { update(v * 2, l, (r + l) / 2, ind, d); } else { update(v * 2 + 1, (r + l) / 2 + 1, r, ind, d); } treesum[v] = treesum[v * 2] + treesum[v * 2 + 1]; treemin[v] = min(treemin[v * 2], treesum[v * 2] + treemin[v * 2 + 1]); } int query(int v, int l, int r, int x) { if (l == r) { return l; } if (treemin[v * 2] + x < 0) { return query(v * 2, l, (r + l) / 2, x); } return query(v * 2 + 1, (r + l) / 2 + 1, r, treesum[v * 2] + x); } void dfs1(int v, int p = -1) { for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; if (to != p) { val[to] = min(val[v], h[v]); par[to] = v; dfs1(to, v); } } } vector<int> uniq; int m; int mass[1000000]; void dfs2(int v) { mass[++it] = v; for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; if (to != par[v]) { if (val[to] < h[to]) { dfs2(to); } } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n; used.resize(n); g.resize(n); h.resize(n); par.resize(n, -1); val.resize(n); for (int i = 0; i < n; i++) { cin >> h[i]; uniq.push_back(h[i]); } for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--; b--; g[a].push_back(b); g[b].push_back(a); } cin >> k; vector<int> s(k); for (int i = 0; i < k; i++) { cin >> s[i]; uniq.push_back(s[i]); } sort(uniq.begin(), uniq.end()); m = unique(uniq.begin(), uniq.end()) - uniq.begin(); treesum.resize(4 * m, 0); treemin.resize(4 * m, 0); for (int i = 0; i < n; i++) { h[i] = lower_bound(uniq.begin(), uniq.begin() + m, h[i]) - uniq.begin(); } for (int i = 0; i < k; i++) { s[i] = lower_bound(uniq.begin(), uniq.begin() + m, s[i]) - uniq.begin(); } val[0] = 1e9; dfs1(0); for (int i = 0; i < n; i++) { update(1, 0, m - 1, m - min(val[i], h[i]) - 1, 1); } for (int i = 0; i < k; i++) { update(1, 0, m - 1, m - s[i] - 1, -1); } if (treemin[1] >= 0) { cout << 0; return 0; } int ans = 1e9; vector<int> b(n); for (int i = 0; i < n; i++) { if (h[i] < val[i]) { it = 0; dfs2(i); update(1, 0, m - 1, m - h[i] - 1, -it); int t = m - query(1, 0, m - 1, 0) - 1; if (t <= val[i]) { b[i] = t; update(1, 0, m - 1, m - t - 1, 1); for (int j = 2; j <= it; j++) { b[mass[j]] = min(h[mass[j]], b[par[mass[j]]]); update(1, 0, m - 1, m - b[mass[j]] - 1, 1); } if (treemin[1] >= 0) { ans = min(ans, uniq[t] - uniq[h[i]]); } for (int j = 1; j <= it; j++) { update(1, 0, m - 1, m - b[mass[j]] - 1, -1); } } update(1, 0, m - 1, m - h[i] - 1, it); } } if (ans == 1e9) { cout << -1; } else { cout << ans; } return 0; } |
/* @uthor: Amit Kumar user -->GitHub: drviruses ; CodeChef: dr_virus_ ; Codeforces: dr_virus_ ;AtCoder,Hackerearth,Hakerrank: dr_virus; */ #include <bits/stdc++.h> #include <chrono> using namespace std; using namespace std::chrono; //#include <boost/multiprecision/cpp_int.hpp> //namespace mp = boost::multiprecision; //#define ln mp::cpp_int; #define int long long #define double long double #define uint unsigned long long #define endl n #define all(vec) vec.begin(),vec.end() int google_itr = 1; #define google(x) cout<< Case # <<x<< : #define pi 3.14159265358979323846264338327950L vector<string> vec_splitter(string s) { s += , ; vector<string> res; while(!s.empty()) { res.push_back(s.substr(0, s.find( , ))); s = s.substr(s.find( , ) + 1); } return res; } void debug_out( vector<string> __attribute__ ((unused)) args, __attribute__ ((unused)) int idx, __attribute__ ((unused)) int LINE_NUM) { cerr << endl; } template <typename Head, typename... Tail> void debug_out(vector<string> args, int idx, int LINE_NUM, Head H, Tail... T) { if(idx > 0) cerr << , ; else cerr << Line( << LINE_NUM << ) ; stringstream ss; ss << H; cerr << args[idx] << = << ss.str(); debug_out(args, idx + 1, LINE_NUM, T...); } #define XOX #ifdef XOX #define deb(...) debug_out(vec_splitter(#__VA_ARGS__), 0, __LINE__, __VA_ARGS__) #else #define deb(...) 42 #endif const int mod = 1e9+7; const int inf = 1e18; void virus(){ int n; cin >> n; vector <int> arr(n), seq(n); for(auto &i:arr) cin >> i; iota(all(seq), 0); partial_sum(all(arr), arr.begin()); partial_sum(all(seq), seq.begin()); for(auto i=0; i<n; i++) { if(arr[i] < seq[i]) { cout << NO n ; return; } } cout << YES n ; } int32_t main(){ ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); /*#ifndef ONLINE_JUDGE freopen( input.txt , r ,stdin); freopen( output.txt , w ,stdout); #endif*/ int t; cin >> t; while(t--){ auto start = system_clock::now(); virus(); auto stop = system_clock::now(); duration<double> duration = (stop - start); //cerr << nTime: << fixed << setprecision(10) << (double)duration.count() << sec << endl; //your code goes here } return 0; } |
#include <bits/stdc++.h> using namespace std; bool inrange(int y) { return ((y >= 1) && (y <= 9)); } int main() { int r1, r2, c1, c2, d1, d2; bool taken[9] = {false}; cin >> r1 >> r2 >> c1 >> c2 >> d1 >> d2; int x = (r1 + r2); int y = (c1 + c2); int z = (d1 + d2); int w; if (x == y && y == z) { if ((r1 + c2 - d1) % 2) { cout << -1 n ; return 0; } y = (r1 + c2 - d1) / 2; if (!inrange(y)) { cout << -1 n ; return 0; } if (taken[y - 1]) { cout << -1 n ; return 0; } else taken[y - 1] = true; x = r1 - y; if (!inrange(x)) { cout << -1 n ; return 0; } if (taken[x - 1]) { cout << -1 n ; return 0; } else { taken[x - 1] = true; } w = d2 - y; if (!inrange(w)) { cout << -1 n ; return 0; } if (taken[w - 1]) { cout << -1 n ; return 0; } else { taken[w - 1] = true; } z = c2 - y; if (!inrange(z)) { cout << -1 n ; return 0; } if (taken[z - 1]) { cout << -1 n ; return 0; } else { taken[z - 1] = true; } cout << x << << y << n ; cout << w << << z << n ; } else cout << -1 n ; return 0; } |
#include <bits/stdc++.h> using namespace std; char st[100005]; int vis[100005]; int main() { long l, cnt = 0; scanf( %ld , &l); scanf( %s , st); if (l > 26) { cout << -1; return 0; } for (long i = 0; i < l + 10; i++) vis[i] = 0; for (long i = 0; i < l; i++) { if (vis[i] == 0) { vis[i] = 1; for (long j = i + 1; j < l; j++) { if (st[i] == st[j] && vis[j] == 0) { cnt++; vis[j] = 1; } } } } cout << cnt; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string str; getline(cin, str); char c = 0; int n = str.length(); for (int i = n - 1; i >= 0; i--) { if ((str[i] >= 65 && str[i] <= 90) || (str[i] >= 97 && str[i] <= 122)) { c = str[i]; break; } } if (c == a || c == e || c == i || c == o || c == u || c == y || c == A || c == E || c == I || c == O || c == U || c == Y ) cout << YES ; else cout << NO ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A32OI_PP_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a32oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(); int n; cin >> n; int x; cin >> x; int a[n]; int pp[100005] = {0}; for (int i = 0; i < n; i++) { cin >> a[i]; pp[a[i]]++; } long long c = 0; for (int i = 0; i < n; i++) { if (((a[i] ^ x) < 100005) && pp[a[i] ^ x]) { c += pp[a[i] ^ x]; } } if (x == 0) cout << (c - n) / 2 << n ; else cout << c / 2 << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_P_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DFF_P_SYMBOL_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_P_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_4_V
`define SKY130_FD_SC_HDLL__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_4_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int mod = 1e9 + 7; const int inf = (1 << 30) - 1; const ll infll = (1LL << 61) - 1; double a[1 << 17]; int b[1 << 17], N; ll pos_sum = 0, neg_sum = 0; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> N; for (int i = 0; i < N; i++) { cin >> a[i]; if (a[i] > 0) { b[i] = ceil(a[i]); pos_sum += b[i]; } else if (a[i] < 0) { b[i] = floor(a[i]); neg_sum += b[i]; } } if (abs(pos_sum) < abs(neg_sum)) { for (int i = 0; i < N && abs(pos_sum) < abs(neg_sum); i++) { if (a[i] < 0 && ceil(a[i]) != b[i]) { b[i] = ceil(a[i]); neg_sum++; } } } else if (abs(pos_sum) > abs(neg_sum)) { for (int i = 0; i < N && abs(pos_sum) > abs(neg_sum); i++) { if (a[i] > 0 && floor(a[i]) != b[i]) { b[i] = floor(a[i]); pos_sum--; } } } for (int i = 0; i < N; i++) { cout << b[i] << endl; } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:24:04 11/07/2015
// Design Name: RAM_Block
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/Transflineal/RAM_tst.v
// Project Name: Transflineal
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: RAM_Block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module RAM_tst;
// Inputs
reg clk;
reg [7:0] Address_w;
reg [7:0] Address;
reg W_ref;
reg W;
reg [31:0] Data_I;
// Outputs
wire [31:0] Data_O;
wire [15:0] Ref;
reg [8:0] i;
reg [15:0] ssin;
reg [15:0] ccos;
// Instantiate the Unit Under Test (UUT)
RAM_Block uut (
.clk(clk),
.Address(Address),
.Address_w(Address_w),
.W(W),
.W_ref(W_ref),
.Data_I(Data_I),
.Data_O(Data_O),
.Ref(Ref)
);
initial begin
// Initialize Inputs
clk = 0;
Address_w = 0;
Address = 0;
W = 0;
W_ref = 0;
Data_I = 0;
i = 0;
ssin = 16'd143;
ccos = 16'd8191;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for(i = 0; i <= 255; i = i+1) begin
ssin = ssin+1;
if(i == 13) ccos = 16'd8190;
if(i == 55) ccos = 16'd8189;
if(i == 89) ccos = 16'd8188;
if(i == 118) ccos = 16'd8187;
if(i == 145) ccos = 16'd8186;
if(i == 169) ccos = 16'd8185;
if(i == 191) ccos = 16'd8184;
if(i == 212) ccos = 16'd8183;
if(i == 231) ccos = 16'd8182;
if(i == 250) ccos = 16'd8181;
#3 Address_w = i[7:0];
#10 Data_I = {ssin,ccos};
#10 W = 1;
#10 W = 0;
#10 Address = i[7:0];
#10;
end
Data_I = 32'd259;
#10;
W_ref = 1;
#10;
W_ref = 0;
#100;
Address = 128;
end
always #5 clk = !clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2 * 100 * 1000; long double l[N]; long double Maks(long double dod, int n) { int i; long double as, mi, w; mi = 0; w = -10000000000000; as = 0; for (i = 1; i <= n; ++i) { as += (l[i] - dod); w = max(w, as - mi); mi = min(mi, as); } return w; } long double Minim(long double dod, int n) { int i; long double as, ma, w; ma = 0; w = 10000000000000; as = 0; for (i = 1; i <= n; ++i) { as += (l[i] - dod); w = min(w, as - ma); ma = max(ma, as); } return w; } long double TS(long double p, long double k, int n) { int i; long double s1, s2, w1, w2; for (i = 1; i <= 100; ++i) { s1 = p + ((k - p) / 3); s2 = k - ((k - p) / 3); w1 = max(abs(Maks(s1, n)), abs(Minim(s1, n))); w2 = max(abs(Maks(s2, n)), abs(Minim(s2, n))); if (w1 < w2) k = s2; else p = s1; } return p; } void WczytajLiczby(int &n) { int i; cin >> n; for (i = 1; i <= n; ++i) cin >> l[i]; } void Weakness() { int n; long double w; WczytajLiczby(n); w = TS(-10000, 10000, n); w = max(abs(Minim(w, n)), abs(Maks(w, n))); cout << fixed << setprecision(10) << w << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); Weakness(); return 0; } |
#include <bits/stdc++.h> using namespace std; int regions[100000][4]; string name[100000][3]; void compareScore(int regionNo, int score, string str) { if (score >= regions[regionNo][0]) { string tempName1 = name[regionNo][0]; string tempName2 = name[regionNo][1]; int tempScore1 = regions[regionNo][0]; int tempScore2 = regions[regionNo][1]; regions[regionNo][0] = score; name[regionNo][0] = str; regions[regionNo][1] = tempScore1; regions[regionNo][2] = tempScore2; name[regionNo][1] = tempName1; name[regionNo][2] = tempName2; } else if (score >= regions[regionNo][1]) { string tempName2 = name[regionNo][1]; int tempScore2 = regions[regionNo][1]; regions[regionNo][1] = score; name[regionNo][1] = str; regions[regionNo][2] = tempScore2; name[regionNo][2] = tempName2; } else if (score >= regions[regionNo][2]) { regions[regionNo][2] = score; name[regionNo][2] = str; } if (!name[regionNo][1].empty() && !name[regionNo][2].empty() && regions[regionNo][1] == regions[regionNo][2]) { regions[regionNo][3] = -1; } else { regions[regionNo][3] = 1; } } void solve(int n, int m) { for (int i = 0; i < n; i++) { string str; int regionNo, score; cin >> str >> regionNo >> score; compareScore(regionNo, score, str); } for (int i = 1; i <= m; i++) { if (regions[i][3] == 1) { cout << name[i][0] << << name[i][1] << endl; } else { cout << ? << endl; } } } int main() { int n, m; cin >> n >> m; solve(n, m); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_TB_V
`define SKY130_FD_SC_HDLL__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hdll__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__OR4_FUNCTIONAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; int sum(int a, int b) { return (a + b) % MOD; } int prod(int a, int b) { return a * 1ll * b % MOD; } int mpow(int b, int e) { if (e == 0) return 1; if (e & 1) return prod(b, mpow(b, e - 1)); return mpow(prod(b, b), e / 2); } int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); cout << fixed << setprecision(15); const int HALF = mpow(2, MOD - 2); int N; cin >> N; vector<vector<int> > adj(N); for (int i = 0; i < N - 1; i++) { int u, v; cin >> u >> v; adj[u - 1].push_back(v - 1); adj[v - 1].push_back(u - 1); } int ans = 0; function<int(int, int)> calc = [&](int loc, int par) { int nm = 1; for (int nbr : adj[loc]) { if (nbr == par) continue; int unv = calc(nbr, loc); unv = sum(unv, prod(HALF, sum(1, MOD - unv))); nm = prod(nm, unv); } nm = sum(1, MOD - nm); ans = sum(ans, nm); return nm; }; calc(0, 0); for (int i = 0; i < N; i++) ans = prod(ans, 2); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, string> p; map<string, string>::iterator it = p.begin(); int main() { int q; cin >> q; while (q--) { string s1, s2; cin >> s1 >> s2; if (!p.count(s1)) p[s2] = s1; else { p[s2] = p[s1]; p.erase(s1); } } cout << p.size() << endl; for (it = p.begin(); it != p.end(); it++) cout << it->second << << it->first << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long s, x; int main() { cin >> s >> x; s -= x; if (s < 0 || s % 2 != 0) { cout << 0 << endl; return 0; } s /= 2; if (s & x) { cout << 0 << endl; return 0; } long long bit = 0, result = 0; if (!s) result -= 2; while (x > 0) { bit += x & 1; x >>= 1; } result += 1LL << bit; cout << result << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, r, f[60005]; int dp[105][60005]; struct node { int a, b, sign; } pro[105]; bool cmp(node a, node b) { if (a.sign == b.sign) { if (a.sign == 1) return a.a < b.a; else return a.a + a.b > b.a + b.b; } return a.sign < b.sign; } int main() { scanf( %d%d , &n, &r); for (register int i = 1; i <= n; i++) { scanf( %d%d , &pro[i].a, &pro[i].b); if (pro[i].b >= 0) pro[i].sign = 1; else pro[i].sign = 2, pro[i].a = max(pro[i].a, abs(pro[i].b)); } sort(pro + 1, pro + 1 + n, cmp); int s = r, sum = 0; vector<node> aa; for (register int i = 1; i <= n; i++) { if (pro[i].sign == 1 && s >= pro[i].a) s += pro[i].b, sum++; else aa.push_back(pro[i]); } dp[0][s] = sum; for (int i = 0; i < (int)(aa.size()); i++) for (register int j = 0; j <= s; j++) { if (j >= aa[i].a) dp[i + 1][j + aa[i].b] = max(dp[i + 1][j + aa[i].b], dp[i][j] + 1); dp[i + 1][j] = max(dp[i + 1][j], dp[i][j]); } sum = 0; for (register int i = 0; i <= s; i++) sum = max(sum, dp[(int)(aa.size())][i]); printf( %d n , sum); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Divisor de frecuencia ////
//// ////
//// ////
//// Este archivo describe el comportamiento ////
//// de un divisor de frecuencia en Verilog ////
//// ////
//// Description ////
//// Este módulo se encarga de generar un clk de 1Hz. Recibe el ////
//// reloj del sistema (100MHz) y lo divide para generar un ////
//// de 1Hz. ////
//// ////
//// ////
//// ////
//// ////
//// Autors : ////
//// - Manuel Zumbado Corrales ////
//// - Arturo Salas Delgado ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
/// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//Modulo del divisor de frecuencia
module Divisor_Frecuencia (
input C_100Mhz, //Clock de la fpga = 100MHz
output C_1Hz
);
reg[31:0] contador = 0; //Variable que almacena Contador
reg C_1Hz=0;
always @(posedge C_100Mhz)
begin
if (contador == 50000000-1) //Si ha cuenta 1s enciende led
begin
C_1Hz <= ~C_1Hz;
contador <=0;
end
/*if (contador == 200000000-1) //Si cuenta otro segundo lo apaga y reinicia
begin
C_1Hz <= 1'b0;
contador <=0;
end*/
else
begin
contador <= contador + 1; //suma contador
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); bool t = true; int n; cin >> n; int a[200001] = {0}; vector<int> voz; vector<int> yb; for (int i = 0; i < n; i++) { int c; cin >> c; a[c]++; if (a[c] > 2) { cout << NO ; t = false; break; } else if (a[c] == 1) { yb.push_back(c); } else if (a[c] == 2) { voz.push_back(c); } } if (t) { sort(voz.begin(), voz.end()); sort(yb.begin(), yb.end()); cout << YES << n ; cout << voz.size() << n ; for (int i = 0; i < voz.size(); i++) { cout << voz[i] << ; } cout << n ; cout << yb.size() << n ; reverse(yb.begin(), yb.end()); for (int i = 0; i < yb.size(); i++) { cout << yb[i] << ; } } } |
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; bool mysort(pair<long long, long long> A, pair<long long, long long> B) { return A.second > B.second; } long long moduloMultiplication(long long a, long long b, long long mod) { long long res = 0; a %= mod; while (b) { if (b & 1) res = (res + a) % mod; a = (2 * a) % mod; b >>= 1; } return res; } void solve() { long long n, k, i, j; cin >> n >> k; if (k == 0) { if (n % 2 == 0) cout << 0 n ; else cout << 1 n ; } else { if (k <= n) { if (n == 1) cout << n - k << n ; else { if ((n + k) % 2 == 0) { cout << 0 n ; } else { cout << 1 n ; } } } else { cout << k - n << n ; } } } int32_t main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { auto start = high_resolution_clock::now(); solve(); auto stop = high_resolution_clock::now(); auto duration = duration_cast<seconds>(stop - start); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module secret #(parameter GATED_CLK = 0)
(
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input s1up_in[2],
output logic s1up_out[2],
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
/*verilator lint_off LITENDIAN*/
input [0:15] s6x16up_in[0:1][2:0],
output logic [0:15] s6x16up_out[0:1][2:0],
/*verilator lint_on LITENDIAN*/
input [15:0] s8x16up_in[1:0][0:3],
output logic [15:0] s8x16up_out[1:0][0:3],
input [15:0] s8x16up_3d_in[1:0][0:1][0:1],
output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1],
input clk_en,
input clk /*verilator clocker*/);
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
initial $display("created %m");
logic the_clk;
generate
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
/* verilator lint_off LATCH */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on LATCH */
/* verilator lint_on COMBDLY */
assign the_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign the_clk = clk;
end
endgenerate
always @(posedge the_clk) begin
secret_accum_q <= secret_accum_q + accum_in + secret_value;
end
// Test combinatorial paths of different sizes
always @(*) begin
s1_out = s1_in;
s1up_out = s1up_in;
s2_out = s2_in;
s8_out = s8_in;
s64_out = s64_in;
s65_out = s65_in;
s129_out = s129_in;
s4x32_out = s4x32_in;
end
for (genvar i = 0; i < 3; ++i) begin
assign s6x16up_out[0][i] = s6x16up_in[0][i];
assign s6x16up_out[1][i] = s6x16up_in[1][i];
end
for (genvar i = 0; i < 4; ++i) begin
assign s8x16up_out[0][i] = s8x16up_in[0][i];
assign s8x16up_out[1][i] = s8x16up_in[1][i];
end
for (genvar i = 0; i < 8; ++i) begin
assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]];
end
sub sub (.sub_in(s33_in), .sub_out(s33_out));
// Test sequential path
assign accum_out = secret_accum_q;
// Test mixed combinatorial/sequential path
assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q;
final $display("destroying %m");
endmodule
module sub (
input [32:0] sub_in,
output [32:0] sub_out);
/*verilator no_inline_module*/
assign sub_out = sub_in;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:12:55 03/06/2016
// Design Name: sumcomp
// Module Name: C:/XilinxP/Practica1/sumcomp_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sumcomp
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sumcomp_test;
// Inputs
reg xi;
reg yi;
reg ci;
// Outputs
wire Si;
wire Co;
// Instantiate the Unit Under Test (UUT)
sumcomp uut (
.xi(xi),
.yi(yi),
.ci(ci),
.Si(Si),
.Co(Co)
);
initial begin
$display("...");
// Initialize Inputs
xi = 0;
yi = 0;
ci = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
xi = 0; yi = 0; ci = 0; //000
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 0; ci = 1; //001
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 1; ci = 0; //010
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 1; ci = 1; //011
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 0; ci = 0; //100
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 0; ci = 1; //101
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 1; ci = 0; //110
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 1; ci = 1; //111
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog wrapper for lpflow_clkbufkapwr with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkbufkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:23:02 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Clock8346/Clock8346_funcsim.v
// Design : Clock8346
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "Clock8346,clk_wiz_v5_1,{component_name=Clock8346,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=true}" *)
(* NotValidForBitStream *)
module Clock8346
(clk_in1,
clk_out1,
locked);
input clk_in1;
output clk_out1;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
Clock8346_Clock8346_clk_wiz U0
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "Clock8346_clk_wiz" *)
module Clock8346_Clock8346_clk_wiz
(clk_in1,
clk_out1,
locked);
input clk_in1;
output clk_out1;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_in1_Clock8346;
wire clk_out1;
wire clk_out1_Clock8346;
wire clkfbout_Clock8346;
wire clkfbout_buf_Clock8346;
wire locked;
wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_Clock8346),
.O(clkfbout_buf_Clock8346));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_Clock8346));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_Clock8346),
.O(clk_out1));
(* box_type = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(54),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(10),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.000000),
.REF_JITTER2(0.000000),
.STARTUP_WAIT("FALSE"))
plle2_adv_inst
(.CLKFBIN(clkfbout_buf_Clock8346),
.CLKFBOUT(clkfbout_Clock8346),
.CLKIN1(clk_in1_Clock8346),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(clk_out1_Clock8346),
.CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int n, i, j, k, l, mx; int a[100001]; int p[100001], miu[100001], len; vector<int> b[100001]; vector<int> c[100001]; bool bz[100001]; int f[100001]; long long ans, s; bool cmp(int a, int b) { return a > b; } int gcd(int x, int y) { int r = x % y; while (r) x = y, y = r, r = x % y; return y; } void init() { int i, j, k, l; miu[1] = 1; for (i = 2; i <= 100000; i++) { if (!bz[i]) p[++len] = i, miu[i] = -1; for (j = 1; j <= len; j++) if (1ll * i * p[j] <= 100000) { bz[i * p[j]] = 1; if (!(i % p[j])) break; miu[i * p[j]] = -miu[i]; } else break; } } void add(int t, int s) { int i, l = b[t].size(); for (i = 0; i <= l - 1; i++) f[b[t][i]] += s; } int get(int t) { int i, k, l = b[t].size(), ans = 0; for (i = 0; i <= l - 1; i++) k = b[t][i], ans += miu[k] * f[k]; return ans; } void work(int S) { static int d[100001]; int i, j, k, l, len = c[S].size(), t = 0, A; if (!len) return; for (i = 0; i <= len - 1; i++) { A = c[S][i]; while (t && get(A)) { while (gcd(d[t], A) > 1) add(d[t], -1), --t; s = 1ll * d[t] * A * S; ans = (ans > s ? ans : s); add(d[t], -1), --t; } d[++t] = A, add(A, 1); } while (t) add(d[t], -1), --t; } int main() { init(); scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]), mx = (mx > a[i] ? mx : a[i]); sort(a + 1, a + n + 1, cmp); l = 0; for (i = 1; i <= n; i++) if (a[i] != a[i - 1]) a[++l] = a[i]; else ans = (ans > a[i] ? ans : a[i]); n = l; for (i = 1; i <= mx; i++) { s = floor(sqrt(i)); for (j = 1; j <= s; j++) if (!(i % j)) { b[i].push_back(j); if (j * j < i) b[i].push_back(i / j); } } for (i = 1; i <= n; i++) { l = b[a[i]].size(); for (j = 0; j <= l - 1; j++) k = b[a[i]][j], c[k].push_back(a[i] / k); } for (i = 1; i <= 100000; i++) work(i); printf( %lld n , ans); fclose(stdin); fclose(stdout); return 0; } |
//Fibonacci Test Bench
//Test Bench for Multiplier Functional Unit
module FibonacciTB;
reg clk, reset;
wire [15:0] result;
reg [7:0] n;
wire ready;
//Data containing 0
reg [7:0] test0Data = 8'b0;
//Data containing 1
reg [7:0] test1Data = 8'b1;
// Test regular fibonacci number
reg [7:0] testOrdinary = 8'd6;
//Test overflow number
reg [7:0] testOverflow = 8'd25;
defparam f1.inBits = 8;
defparam f1.outBits = 16;
fibonacci f1 (clk, reset, n, result, ready);
initial begin
clk = 0;
reset = 0;
end
initial begin
// $monitor("time:%t\treset: %b\tready: %b\tresult: %d\nn: %d",$time, reset, ready, result, n);
end
initial begin
#50 begin $display("Starting test 1"); reset = 1; n = testOrdinary; end
#11 reset = 0;
#90 begin $display("Starting test 2"); reset = 1; n = test0Data; end //Test fib(0) == 0
#11 reset = 0;
#50 begin $display("Starting test 3"); reset = 1; n = test1Data; end //Test fib(1) == 1
#11 reset = 0;
#50 begin $display("Starting test 4"); reset = 1; n = testOverflow; end //Test overflowing
#11 reset = 0;
#300 $finish;
end
//Simulate Clock
always begin
#5 clk = !clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using int64 = long long; template <class T> struct Matrix { vector<vector<T> > A; Matrix() {} Matrix(size_t n, size_t m) : A(n, vector<T>(m, 0)) {} Matrix(size_t n) : A(n, vector<T>(n, 0)){}; size_t height() const { return (A.size()); } size_t width() const { return (A[0].size()); } inline const vector<T> &operator[](int k) const { return (A.at(k)); } inline vector<T> &operator[](int k) { return (A.at(k)); } static Matrix I(size_t n) { Matrix mat(n); for (int i = 0; i < n; i++) mat[i][i] = 1; return (mat); } Matrix &operator+=(const Matrix &B) { size_t n = height(), m = width(); assert(n == B.height() && m == B.width()); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) (*this)[i][j] += B[i][j]; return (*this); } Matrix &operator-=(const Matrix &B) { size_t n = height(), m = width(); assert(n == B.height() && m == B.width()); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) (*this)[i][j] -= B[i][j]; return (*this); } Matrix &operator*=(const Matrix &B) { size_t n = height(), m = B.width(), p = width(); assert(p == B.height()); vector<vector<T> > C(n, vector<T>(m, 0)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) for (int k = 0; k < p; k++) C[i][j] = (C[i][j] + (*this)[i][k] * B[k][j]); A.swap(C); return (*this); } Matrix &operator^=(long long k) { Matrix B = Matrix::I(height()); while (k > 0) { if (k & 1) B *= *this; *this *= *this; k >>= 1LL; } A.swap(B.A); return (*this); } Matrix operator+(const Matrix &B) const { return (Matrix(*this) += B); } Matrix operator-(const Matrix &B) const { return (Matrix(*this) -= B); } Matrix operator*(const Matrix &B) const { return (Matrix(*this) *= B); } Matrix operator^(const long long k) const { return (Matrix(*this) ^= k); } friend ostream &operator<<(ostream &os, Matrix &p) { size_t n = p.height(), m = p.width(); for (int i = 0; i < n; i++) { os << [ ; for (int j = 0; j < m; j++) { os << p[i][j] << (j + 1 == m ? ] n : , ); } } return (os); } T determinant() { Matrix B(*this); assert(width() == height()); T ret = 1; for (int i = 0; i < width(); i++) { int idx = -1; for (int j = i; j < width(); j++) { if (B[j][i] != 0) idx = j; } if (idx == -1) return (0); if (i != idx) { ret *= -1; swap(B[i], B[idx]); } ret *= B[i][i]; T vv = B[i][i]; for (int j = 0; j < width(); j++) { B[i][j] /= vv; } for (int j = i + 1; j < width(); j++) { T a = B[j][i]; for (int k = 0; k < width(); k++) { B[j][k] -= B[i][k] * a; } } } return (ret); } }; template <int mod> struct ModInt { int x; ModInt() : x(0) {} ModInt(long long y) : x(y >= 0 ? y % mod : (mod - (-y) % mod) % mod) {} ModInt &operator+=(const ModInt &p) { if ((x += p.x) >= mod) x -= mod; return *this; } ModInt &operator-=(const ModInt &p) { if ((x += mod - p.x) >= mod) x -= mod; return *this; } ModInt &operator*=(const ModInt &p) { x = (int)(1LL * x * p.x % mod); return *this; } ModInt &operator/=(const ModInt &p) { *this *= p.inverse(); return *this; } ModInt operator-() const { return ModInt(-x); } ModInt operator+(const ModInt &p) const { return ModInt(*this) += p; } ModInt operator-(const ModInt &p) const { return ModInt(*this) -= p; } ModInt operator*(const ModInt &p) const { return ModInt(*this) *= p; } ModInt operator/(const ModInt &p) const { return ModInt(*this) /= p; } bool operator==(const ModInt &p) const { return x == p.x; } bool operator!=(const ModInt &p) const { return x != p.x; } ModInt inverse() const { int a = x, b = mod, u = 1, v = 0, t; while (b > 0) { t = a / b; a -= t * b; swap(a, b); u -= t * v; swap(u, v); } return ModInt(u); } friend ostream &operator<<(ostream &os, const ModInt<mod> &p) { return os << p.x; } friend istream &operator>>(istream &is, ModInt<mod> &a) { long long x; is >> x; a = ModInt<mod>(x); return (is); } }; const int mod = 1e9 + 7; using modint = ModInt<mod>; int main() { int64 N, M; cin >> N >> M; map<int64, vector<pair<int, int> > > add; for (int i = 0; i < N; i++) { int64 A, L, R; cin >> A >> L >> R; --A; add[L - 1].emplace_back(A, 1); add[R].emplace_back(A, -1); } add[1].emplace_back(-1, -1); add[M].emplace_back(-1, -1); vector<modint> sum(3, 0); Matrix<modint> mat(3, 3); vector<int> inc(3, 0); int64 pv = -1; for (auto &p : add) { for (auto &v : p.second) { if (~v.first) inc[v.first] += v.second; } Matrix<modint> mat2(3, 3); for (int i = 0; i < 3; i++) { for (int j = -1; j <= 1; j++) { int k = i + j; if (k < 0 || k >= 3) continue; if (inc[k] == 0) mat2[i][k] = 1; } } if (~pv) { mat ^= p.first - pv; vector<modint> sum2(3); for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { sum2[j] += sum[i] * mat[i][j]; } } sum.swap(sum2); } else { sum[1] = 1; } mat = mat2; pv = p.first; } cout << sum[1] << endl; } |
#include <bits/stdc++.h> using namespace std; struct node { int Tea; int Index; friend bool operator<(const node& a, const node& b) { return a.Tea > b.Tea; } } D[105]; int main() { int i, n, w, Ans[105]; scanf( %d%d , &n, &w); for (i = 0; i < n; i++) { scanf( %d , &D[i].Tea); D[i].Index = i; } sort(D, D + n); int Judge = 0; for (i = 0; i < n; i++) Judge += (D[i].Tea + 1) / 2; if (Judge > w) printf( -1 n ); else { w -= Judge; for (i = 0; i < n; i++) Ans[D[i].Index] = (D[i].Tea + 1) / 2; for (i = 0; i < n && w; i++) { if (w >= D[i].Tea - Ans[D[i].Index]) w -= D[i].Tea - Ans[D[i].Index], Ans[D[i].Index] = D[i].Tea; else Ans[D[i].Index] += w, w = 0; } for (i = 0; i < n; i++) { if (i) printf( ); printf( %d , Ans[i]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; char ans[1000005], tmp[1000005]; int wa; int n, x; void go(int x, int y) { int len = 0; while (x != y) { if (x < y) { y -= x; tmp[len++] = B ; } else { x -= y; tmp[len++] = T ; } if (len >= n) return; } tmp[len++] = T ; int w = 0; if (x > 1 || len != n) return; for (int i = 0; i + 1 < len; i++) if (tmp[i] == tmp[i + 1]) w++; if (wa > w) { wa = w; for (int i = 0; i < n; i++) ans[i] = tmp[i]; } } int main() { while (scanf( %d%d , &n, &x) == 2) { wa = 10000000; for (int i = 1; i <= x; i++) { go(i, x); go(x, i); } if (wa == 10000000) puts( IMPOSSIBLE ); else { reverse(ans, ans + n); printf( %d n , wa); for (int i = 0; i < n; i++) putchar(ans[i]); puts( ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long P(long long m, long long n); long long pi(long long x); long long phi(long long m, long long n); bool isprm[400005]; int cntprm[400005]; vector<long long> prm; void Init() { for (int i = 2; i <= 400000; ++i) { isprm[i] = true; } for (int i = 2; i <= 400000; ++i) { cntprm[i] = cntprm[i - 1] + isprm[i]; if (isprm[i]) { prm.push_back(i); for (int j = i + i; j <= 400000; j += i) isprm[j] = false; } } } long long sol(long long x) { long long ans = 0; long long sq = sqrt(x); for (int i = 0; i < (int)prm.size() && prm[i] <= sq; ++i) { long long a = prm[i], b = x / a; if (b <= 400000) ans += cntprm[b] - cntprm[a]; else { ans += pi(b) - cntprm[a]; } } return ans; } int main(void) { long long n; Init(); cin >> n; cout << cntprm[(int)cbrt(n)] + sol(n) << n ; } long long phi(long long m, long long n) { if (m) { if (n) { if (m <= prm[n - 1]) return 1; else { if (prm[n - 1] * prm[n - 1] >= m) return pi(m) - n + 1; else return phi(m, n - 1) - phi(m / prm[n - 1], n - 1); } } else { return m; } } else { return 0; } } long long P(long long m, long long n) { long long res = 0, sq = sqrt(m); for (int i = n; i < (int)prm.size() && prm[i] <= sq; ++i) { auto num = prm[i]; res += pi(m / num) - pi(num) + 1; } return res; } long long pi(long long x) { if (x <= 400000) return cntprm[x]; else { long long n = pi(ceil(cbrt(x))), m = x; return phi(m, n) + n - 1 - P(m, n); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O32A_FUNCTIONAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_dbg.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Top level Module: jbi_dbg
// Where Instantiated: jbi
// Description: Debug Block
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_dbg (/*AUTOARG*/
// Outputs
dbg_req_transparent, dbg_req_arbitrate, dbg_req_priority, dbg_data,
// Inputs
clk, rst_l, dbg_rst_l, hold, testmux_sel, scan_en,
csr_16x65array_margin, csr_jbi_debug_arb_max_wait,
csr_jbi_debug_arb_hi_water, csr_jbi_debug_arb_lo_water,
csr_jbi_debug_arb_data_arb, csr_jbi_debug_arb_tstamp_wrap,
csr_jbi_debug_arb_alternate, csr_jbi_debug_arb_alternate_set_l,
iob_jbi_dbg_hi_data, iob_jbi_dbg_hi_vld, iob_jbi_dbg_lo_data,
iob_jbi_dbg_lo_vld, mout_dbg_pop
);
input clk;
input rst_l;
input dbg_rst_l;
input hold;
input testmux_sel;
input scan_en;
// CSR Interface
input [4:0] csr_16x65array_margin;
input [`JBI_CSR_DBG_MAX_WAIT_WIDTH-1:0] csr_jbi_debug_arb_max_wait;
input [`JBI_CSR_DBG_HI_WATER_WIDTH-1:0] csr_jbi_debug_arb_hi_water;
input [`JBI_CSR_DBG_LO_WATER_WIDTH-1:0] csr_jbi_debug_arb_lo_water;
input csr_jbi_debug_arb_data_arb;
input [`JBI_CSR_DBG_TSWRAP_WIDTH-1:0] csr_jbi_debug_arb_tstamp_wrap;
input csr_jbi_debug_arb_alternate;
input csr_jbi_debug_arb_alternate_set_l;
// IOB Interface.
input [47:0] iob_jbi_dbg_hi_data;
input iob_jbi_dbg_hi_vld;
input [47:0] iob_jbi_dbg_lo_data;
input iob_jbi_dbg_lo_vld;
// Memory Out (mout) Interface
input mout_dbg_pop;
output dbg_req_transparent;
output dbg_req_arbitrate;
output dbg_req_priority;
output [127:0] dbg_data;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dbgq_hi_csn_rd; // From u_dbg_ctl of jbi_dbg_ctl.v
wire dbgq_hi_csn_wr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_hi_raddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_hi_rdata; // From u_dbg_buf of jbi_dbg_buf.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_hi_waddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_hi_wdata; // From u_dbg_ctl of jbi_dbg_ctl.v
wire dbgq_lo_csn_rd; // From u_dbg_ctl of jbi_dbg_ctl.v
wire dbgq_lo_csn_wr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_lo_raddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_lo_rdata; // From u_dbg_buf of jbi_dbg_buf.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_lo_waddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_lo_wdata; // From u_dbg_ctl of jbi_dbg_ctl.v
// End of automatics
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
jbi_dbg_ctl u_dbg_ctl (/*AUTOINST*/
// Outputs
.dbg_req_transparent(dbg_req_transparent),
.dbg_req_arbitrate(dbg_req_arbitrate),
.dbg_req_priority(dbg_req_priority),
.dbg_data (dbg_data[127:0]),
.dbgq_hi_raddr (dbgq_hi_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_waddr (dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_csn_wr (dbgq_hi_csn_wr),
.dbgq_hi_csn_rd (dbgq_hi_csn_rd),
.dbgq_hi_wdata (dbgq_hi_wdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_raddr (dbgq_lo_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_waddr (dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_csn_wr (dbgq_lo_csn_wr),
.dbgq_lo_csn_rd (dbgq_lo_csn_rd),
.dbgq_lo_wdata (dbgq_lo_wdata[`JBI_DBGQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst_l (rst_l),
.dbg_rst_l (dbg_rst_l),
.iob_jbi_dbg_hi_vld(iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_hi_data(iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_lo_vld(iob_jbi_dbg_lo_vld),
.iob_jbi_dbg_lo_data(iob_jbi_dbg_lo_data[47:0]),
.csr_jbi_debug_arb_max_wait(csr_jbi_debug_arb_max_wait[`JBI_CSR_DBG_MAX_WAIT_WIDTH-1:0]),
.csr_jbi_debug_arb_hi_water(csr_jbi_debug_arb_hi_water[`JBI_CSR_DBG_HI_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_lo_water(csr_jbi_debug_arb_lo_water[`JBI_CSR_DBG_LO_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_data_arb(csr_jbi_debug_arb_data_arb),
.csr_jbi_debug_arb_tstamp_wrap(csr_jbi_debug_arb_tstamp_wrap[`JBI_CSR_DBG_TSWRAP_WIDTH-1:0]),
.csr_jbi_debug_arb_alternate(csr_jbi_debug_arb_alternate),
.csr_jbi_debug_arb_alternate_set_l(csr_jbi_debug_arb_alternate_set_l),
.mout_dbg_pop (mout_dbg_pop),
.dbgq_hi_rdata (dbgq_hi_rdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_rdata (dbgq_lo_rdata[`JBI_DBGQ_WIDTH-1:0]));
jbi_dbg_buf u_dbg_buf (/*AUTOINST*/
// Outputs
.dbgq_hi_rdata (dbgq_hi_rdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_rdata (dbgq_lo_rdata[`JBI_DBGQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.hold (hold),
.testmux_sel (testmux_sel),
.scan_en (scan_en),
.csr_16x65array_margin(csr_16x65array_margin[4:0]),
.dbgq_hi_raddr (dbgq_hi_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_raddr (dbgq_lo_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_waddr (dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_waddr (dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_csn_wr (dbgq_hi_csn_wr),
.dbgq_lo_csn_wr (dbgq_lo_csn_wr),
.dbgq_hi_csn_rd (dbgq_hi_csn_rd),
.dbgq_lo_csn_rd (dbgq_lo_csn_rd),
.dbgq_hi_wdata (dbgq_hi_wdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_wdata (dbgq_lo_wdata[`JBI_DBGQ_WIDTH-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
module ex_stage( input clk,
input rst,
input wb_reg_write,
input wb_mem_to_reg,
input mem_read,
input mem_write,
input ex_imm_command,
input ex_alu_src_b,
input ex_dst_reg_sel,
input [1:0] ex_alu_op,
input pstop_i,
input [31:0] A,
input [31:0] B,
input [31:0] sign_extend_offset,
input [4:0] rt, // target register
input [4:0] rd, // destination register
input [5:0] opcode,
input [1:0] rs_fwd_sel, // forwarding muxes control
input [1:0] rt_fwd_sel, // forwarding muxes control
input [31:0] mem_fwd_val, // forwarding from EX_MEM
input [31:0] wb_fwd_val, // forwarding from WB
output [4:0] ex_dst_reg,
output [5:0] ex_opcode,
output reg [31:0] EX_MEM_alu_result,
output reg [31:0] EX_MEM_B_value,
output reg [4:0] EX_MEM_dst_reg,
output reg [5:0] EX_MEM_opcode,
output reg EX_MEM_mem_read,
output reg EX_MEM_mem_write,
output reg EX_MEM_wb_reg_write,
output reg EX_MEM_wb_mem_to_reg );
wire [5:0] func_field; // func code field in instruction
wire [5:0] func_code; // func code for ALU control
wire [4:0] alu_ctl; // ALU control lines
reg [31:0] alu_a_in;
wire [31:0] alu_b_in;
reg [31:0] b_value;
wire [31:0] alu_result;
wire zero;
always @* begin
case(rs_fwd_sel)
0: alu_a_in = A;
1: alu_a_in = mem_fwd_val;
2: alu_a_in = wb_fwd_val;
default: alu_a_in = 0; //
endcase
end
always @* begin
case(rt_fwd_sel)
0: b_value = B;
1: b_value = mem_fwd_val;
2: b_value = wb_fwd_val;
default: b_value = 0; //
endcase
end
assign alu_b_in = ex_alu_src_b ? sign_extend_offset : b_value;
assign func_field = sign_extend_offset [5:0]; // looks wierd, but func code is encoded there
assign func_code = ex_imm_command ? {{2'b10},{~opcode[2] & opcode[1] & ~opcode[0]},opcode[2:0]} : func_field;
assign ex_opcode = opcode;
assign ex_dst_reg = ex_dst_reg_sel ? rd : rt;
alu_ctrl aluctl_inst(
.alu_op (ex_alu_op),
.func_code (func_code),
.alu_ctl (alu_ctl));
alu alu_inst(
.alu_ctl (alu_ctl),
.a_in (alu_a_in),
.b_in (alu_b_in),
.result (alu_result),
.zero_flag (zero));
// EX/MEM Pipeline register
always @(posedge clk) begin
if (rst) begin
EX_MEM_alu_result <= 0;
EX_MEM_B_value <= 0;
EX_MEM_dst_reg <= 0;
EX_MEM_mem_read <= 0;
EX_MEM_mem_write <= 0;
EX_MEM_wb_reg_write <= 0;
EX_MEM_wb_mem_to_reg <= 0;
end
else begin
EX_MEM_alu_result <= alu_result;
EX_MEM_B_value <= b_value;
EX_MEM_dst_reg <= ex_dst_reg;
EX_MEM_opcode <= opcode;
EX_MEM_mem_read <= mem_read;
EX_MEM_mem_write <= mem_write;
EX_MEM_wb_reg_write <= wb_reg_write;
EX_MEM_wb_mem_to_reg <= wb_mem_to_reg;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; int a[maxn], ans[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, c; cin >> n >> m >> c; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) { int val; cin >> val; ans[i] += val; ans[i + n - m + 1] -= val; } ans[0] %= c; for (int i = 1; i < n; i++) ans[i] = (ans[i] + ans[i - 1]) % c; for (int i = 0; i < n; i++) cout << ((a[i] + ans[i]) % c + c) % c << ; cout << endl; return 0; } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module latchp (
input d,
clk,
en,
output reg q
);
initial q <= 1'b0;
always @* if (en) q <= d;
endmodule
module latchn (
input d,
clk,
en,
output reg q
);
always @* if (!en) q <= d;
endmodule
module my_latchsre (
input d,
clk,
en,
clr,
pre,
output reg q
);
always @*
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else if (en) q <= d;
endmodule
module latchp_noinit (
input d,
clk,
en,
output reg q
);
always @* if (en) q <= d;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[110], n = 0, res[1010], ch = 0, k = 0; string s; int main() { cin >> s; memset(a, 0, sizeof a); memset(res, 0, sizeof res); for (int i = 0; i < (int)s.length(); ++i) if (s[i] != , ) { a[n] *= 10; a[n] += (int)(s[i] - 0 ); } else ++n; ++n; for (int i = 0; i < n; ++i) res[a[i]] = 1; for (int i = 0; i < 1010; ++i) { if (res[i] == 1) ++ch; else { if (k > 0 && ch) cout << , ; if (ch && k == 0) ++k; if (ch == 1) cout << i - 1; else if (ch) cout << i - ch << - << i - 1; ch = 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int MOD = 998244353; const long long int INF = 3e18; long long int power(long long int base, long long int exp) { long long int res = 1; while (exp > 0) { if (exp % 2 == 1) res = (res * base); base = (base * base); exp /= 2; } return res; } long long int bitc(long long int n, long long int x) { return ((n >> x) & 1); } long long int __gcd(long long int a, long long int b) { return b == 0 ? a : __gcd(b, a % b); } long long int fsub(long long int a, long long int b, long long int p = MOD) { return ((a % p) - (b % p) + p) % p; } long long int fmult(long long int a, long long int b, long long int p = MOD) { return ((((a % p) * (b % p)) % p) + p) % p; } long long int fadd(long long int a, long long int b, long long int p = MOD) { return ((a % p + b % p) % p + p) % p; } long long int fpow(long long int n, long long int k, long long int p = MOD) { long long int r = 1; while (k > 0) { if (k & 1) r = r * n % p; n = n * n % p; k = k >> 1; } return r; } long long int inv(long long int a, long long int p = MOD) { return fpow(a, p - 2, p); } long long int fdiv(long long int a, long long int b, long long int p = MOD) { long long int yinv = inv(b); long long int ans = (a * yinv) % p; return ((ans) % p + p) % p; } long long int ceil(long long int a, long long int b) { return ceil((long double)a / b); } template <typename T> istream &operator>>(istream &in, vector<T> &a) { for (auto &item : a) { in >> item; } return in; } template <typename T, typename U> ostream &operator<<(ostream &out, pair<T, U> &a) { cout << a.first << << a.second; return out; } template <typename T, typename U> istream &operator>>(istream &out, pair<T, U> &a) { cin >> a.first >> a.second; return out; } template <typename T, typename U> ostream &operator<<(ostream &out, map<T, U> &a) { for (auto &item : a) { out << item << n ; } return out; } template <typename T> ostream &operator<<(ostream &out, vector<T> &a) { for (auto &item : a) { out << item << ; } return out; } template <typename T> ostream &operator<<(ostream &out, vector<vector<T>> &a) { for (auto &item : a) { out << item << n ; } return out; } template <int D, typename T> struct Vec : public vector<Vec<D - 1, T>> { static_assert(D >= 1, Vector dimension must be greater than zero! ); template <typename... Args> Vec(int n = 0, Args... args) : vector<Vec<D - 1, T>>(n, Vec<D - 1, T>(args...)) {} }; template <typename T> struct Vec<1, T> : public vector<T> { Vec(int n = 0, T val = T()) : vector<T>(n, val) {} }; std::vector<bool> is_prime; std::vector<long long int> primes; void sieve(long long int n) { is_prime.resize(n + 2, true); primes.clear(); long long int p; for (p = 2; p * p <= n; p++) { if (is_prime[p]) { long long int i; for (i = p * p; i <= n; i += p) { is_prime[i] = false; } } } is_prime[0] = is_prime[1] = false; long long int i; for (i = 2; i <= n; i++) { if (is_prime[i]) { primes.emplace_back(i); } } } map<long long int, long long int> prime_factors(long long int n) { map<long long int, long long int> s; long long int i; long long int tc = 0; while (n % 2 == 0) { tc++; n /= 2; } if (tc > 0) { s[2] = tc; } for (i = 3; i <= sqrt(n); i += 2) { tc = 0; while (n % i == 0) { tc++; n /= i; } if (tc > 0) { s[i] = tc; } } if (n > 2) { s[n] += 1; } return s; } std::vector<long long int> fact_vec; void fact_fun(long long int n) { fact_vec.resize(n + 10); long long int i; fact_vec[0] = 1; for (i = 1; i <= n + 2; i++) { fact_vec[i] = (fact_vec[i - 1] * i) % MOD; } } std::vector<long long int> p2; void power_2(long long int n, long long int m = MOD) { long long int i; p2.emplace_back(1); for (i = 0; i < n; i++) { p2.emplace_back(fmult(p2.back(), 2)); } } long long int ncr(long long int n, long long int r) { if (r > n) return 0; return fdiv(fact_vec[n], fmult(fact_vec[r], fact_vec[n - r])); } std::vector<long long int> spf; void sieve2(long long int MAXN) { MAXN += 10; spf.resize(MAXN, 0); spf[1] = 1; for (long long int i = 2; i < MAXN; i++) spf[i] = i; for (long long int i = 4; i < MAXN; i += 2) spf[i] = 2; for (long long int i = 3; i * i < MAXN; i++) { if (spf[i] == i) { for (long long int j = i * i; j < MAXN; j += i) { if (spf[j] == j) spf[j] = i; } } } } const int mi[4] = {-1, 0, 1, 0}, mj[4] = {0, 1, 0, -1}; const int d8i[8] = {-1, -1, 0, 1, 1, 1, 0, -1}, d8j[8] = {0, 1, 1, 1, 0, -1, -1, -1}; map<long long int, long long int> getFactorization(long long int x) { map<long long int, long long int> ret; while (x != 1) { ret[spf[x]]++; x = x / spf[x]; } return ret; } class Sol { public: Sol() { long long int i, j; } }; int main() { long long int i, j; ios::sync_with_stdio(false); cin.tie(0); long long int ti; ti = 1; while (ti--) { long long int n; cin >> n; std::vector<long long int> v(n * 2); cin >> v; sort((v).begin(), (v).end()); fact_fun(3e5 + 3); long long int tp = ncr(2 * n, n); long long int f = 0; long long int s = 0; for (i = 0; i < n; i++) { f += v[i]; } for (i = n; i < 2 * n; i++) { s += v[i]; } s -= f; tp = fmult(s, tp); cout << tp << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int dx4[] = {-1, 0, 1, 0}; const int dy4[] = {0, 1, 0, -1}; const int dx8[] = {-1, -1, -1, 0, 0, 1, 1, 1}; const int dy8[] = {-1, 0, 1, -1, 1, -1, 0, 1}; const int dxk[] = {-2, -2, -1, -1, 1, 1, 2, 2}; const int dyk[] = {-1, 1, -2, 2, -2, 2, -1, 1}; inline long long Int() { long long inputNumber = 0; char c = getchar_unlocked(); bool sign = true; while (!((c >= 0 && c <= 9 ) || c == - )) c = getchar_unlocked(); if (c == - ) sign = false, c = getchar_unlocked(); while (c >= 0 && c <= 9 ) inputNumber = (inputNumber << 1) + (inputNumber << 3) + c - 0 , c = getchar_unlocked(); return sign ? inputNumber : -inputNumber; } template <class S, class T> ostream& operator<<(ostream& out, const pair<S, T>& Pair) { out << { << Pair.first << , << Pair.second << } ; return out; } template <class T> ostream& operator<<(ostream& out, const vector<T>& Vector) { out << [ ; for (int i = 0; i < (int)Vector.size(); ++i) { out << Vector[i]; if (i + 1 < (int)Vector.size()) out << , ; } out << ] ; return out; } template <class S, class T> ostream& operator<<(ostream& out, const map<S, T>& Map) { out << [ n ; for (const auto& x : Map) { out << { Key: << x.first << , Value: << x.second << } n ; } out << ] n ; return out; } template <class T> ostream& operator<<(ostream& out, const multiset<T>& Set) { out << { ; for (auto it = Set.begin(); it != Set.end();) { out << *it; it++; if (it != Set.end()) out << , ; } out << } ; return out; } void solve(); int main() { solve(); } const double eps = 1e-10; const int mod = 1e9 + 7; const int N = 2e5 + 5; void solve() { string s; cin >> s; int len = ((int)(s).size()); string sd = ; string org = ; int br = -1; for (int i = len - 1; i >= 0; --i) { if (s[i] != a ) { sd += s[i]; } else { br = i; break; } } if (sd == ) { bool ok = true; for (int i = 0; i < (((int)(s).size())); ++i) { if (s[i] != a ) { ok = false; break; } } if (ok) { cout << s; } else { puts( :( ); } return; } reverse((sd).begin(), (sd).end()); for (int i = 0; i <= br; ++i) { org += s[i]; } string strip = ; for (int i = 0; i < (((int)(org).size())); ++i) if (org[i] != a ) strip += org[i]; if (strip == sd) { cout << org; return; } string tot = strip + sd; if (((int)(tot).size()) % 2) { puts( :( ); return; } int mid = ((int)(tot).size()) / 2; string a = tot.substr(0, mid); string b = tot.substr(mid); if (a != b) { puts( :( ); return; } reverse((s).begin(), (s).end()); reverse((a).begin(), (a).end()); if (s.substr(0, mid) == a) { reverse((s).begin(), (s).end()); int len = ((int)(s).size()) - mid; for (int i = 0; i < (len); ++i) putchar(s[i]); return; } puts( :( ); } |
#include <bits/stdc++.h> using namespace std; const int MOD = 32768, N = 109; char ch; string s[N], t; int ans, v, f[MOD + 9], num, p, pos; int ex(); int gt() { int ret = 0; if (t[pos] == n ) return pos++, v; if (t[pos] == f ) return pos += 2, ret = f[ex()], pos++, ret; while (t[pos] >= 0 && t[pos] <= 9 ) ret = ret * 10 + (t[pos] - 0 ), pos++; return ret; } int nex() { int ret = gt(); while (t[pos] == * || t[pos] == / ) { char tp = t[pos]; pos++; int t1 = gt(); if (tp == * ) ret = (int)((1ll * ret * t1) % MOD); else ret = (ret / t1) % MOD; } return ret; } int ex() { int ret = nex(); while (t[pos] == + || t[pos] == - ) { char tp = t[pos]; pos++; int t1 = nex(); if (tp == + ) ret = (ret + t1) % MOD; else ret = (ret + MOD - t1) % MOD; } return ret; } bool iex() { int p1, p2, tp; p1 = ex(); if (t[pos] == = ) tp = 0, pos += 2; else if (t[pos] == < ) tp = -1, pos++; else tp = 1, pos++; p2 = ex(); if (tp == 0) return p1 == p2; if (tp == -1) return p1 < p2; if (tp == 1) return p1 > p2; return 0; } int getans() { for (int i = 0; i < num; i++) { t = s[i]; if (t[0] == i ) { pos = 3; if (iex()) return pos += 7, ex(); } else return pos = 6, ex(); } return -1; } int main() { cin >> ans >> ch; while (ch != { ) cin >> ch; num = 0; while (true) { cin >> ch; if (ch == } ) break; if (ch == ; ) num++; else s[num] += ch; } int anst = -1; for (int i = 0; i < MOD; i++) { v = i, f[i] = getans(); if (f[i] == ans) anst = i; } cout << anst; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_LP_V
`define SKY130_FD_SC_LP__A221OI_LP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221oi_lp (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221oi_lp (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_LP_V
|
#include <bits/stdc++.h> using namespace std; char a[55][55]; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; int n, T, m; inline int valid(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } int cyc[55][55][4][2] = {}; int main(void) { scanf( %d%d , &n, &T); for (int i = 0; i < n; i++) scanf( %s , a[i]); m = strlen(a[0]); int x = 0, y = 0, DP = 0, CP = 0; int Cx = -dy[DP] * (CP ? -1 : 1), Cy = dx[DP] * (CP ? -1 : 1); int Dx = dx[DP], Dy = dy[DP]; for (int step = 1; step <= T; step++) { while (valid(x + Dx, y + Dy) && a[x + Dx][y + Dy] == a[x][y]) x += Dx, y += Dy; while (valid(x + Cx, y + Cy) && a[x + Cx][y + Cy] == a[x][y]) x += Cx, y += Cy; if (cyc[x][y][DP][CP]) { int ii = step - cyc[x][y][DP][CP]; while (step + ii <= T) step += ii; } else cyc[x][y][DP][CP] = step; if (!valid(x + Dx, y + Dy) || a[x + Dx][y + Dy] == 0 ) { if (CP == 0) CP = 1; else if (CP == 1) { DP = (DP + 1) % 4; CP = 0; } Cx = -dy[DP] * (CP ? -1 : 1), Cy = dx[DP] * (CP ? -1 : 1); Dx = dx[DP], Dy = dy[DP]; } else x += Dx, y += Dy; } printf( %c n , a[x][y]); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 21:25:06 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_g8_0_0 -prefix
// system_rgb888_to_g8_0_0_ system_rgb888_to_g8_0_0_stub.v
// Design : system_rgb888_to_g8_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_g8,Vivado 2016.4" *)
module system_rgb888_to_g8_0_0(clk, rgb888, g8)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb888[23:0],g8[7:0]" */;
input clk;
input [23:0]rgb888;
output [7:0]g8;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f, mod = 998244353; const long long INF = 0x3f3f3f3f3f3f3f3fLL; const double pi = acosl(-1.), eps = 1e-9; inline void sum(int &a, int b) { a += b; if (a >= mod) a -= mod; } const int NN = 1000100; char A[NN], L[NN], R[NN]; int n, ln, rn, B[NN]; void zval(const char *s, int len, int *z) { z[0] = 0; for (int b = 0, i = 1; i < len; i++) { z[i] = max(min(z[i - b], z[b] + b - i), 0); while (s[i + z[i]] == s[z[i]]) z[i]++; if (i + z[i] > b + z[b]) b = i; } z[0] = len; } char zl[NN << 1], zr[NN << 1]; int zL[NN << 1], zR[NN << 1]; int main() { scanf( %s %s %s , A + 1, L, R); n = strlen(A + 1); ln = strlen(L); rn = strlen(R); for (int i = 0; i < ln; i++) zl[i] = L[i]; zl[ln] = * ; for (int i = ln + 1; i <= ln + n; i++) zl[i] = A[i - ln]; zval(zl, ln + n + 1, zL); for (int i = 0; i < rn; i++) zr[i] = R[i]; zr[rn] = * ; for (int i = rn + 1; i <= rn + n; i++) zr[i] = A[i - rn]; zval(zr, rn + n + 1, zR); B[n + 1] = 1; for (int i = n, st, ed; i; i--) { B[i] = B[i + 1]; if (A[i] == 0 ) { if (ln == 1 && L[0] == 0 ) { st = ed = i + 1; } else continue; } else { st = i + ln; if (st > n + 1) continue; int p = zL[ln + i]; if (p < ln) { if (A[i + p] < L[p]) st++; } if (st > n + 1) continue; ed = i + rn; if (ed <= n + 1) { p = zR[rn + i]; if (p < rn) { if (A[i + p] > R[p]) ed--; } } else ed = n + 1; if (ed < st) continue; } int d = B[st] - B[ed + 1]; if (d < 0) d += mod; sum(B[i], d); if (i == 1) { cout << d << endl; return 0; } } puts( 0 ); return 0; } |
`timescale 1ns / 1ps
module display_refresher(
input clk,
input DISPLAY1,
input DISPLAY2,
input DISPLAY3,
input DISPLAY4,
output reg [6:0] DISPLAY,
output reg [3:0] ANODES,
output reg contador_seg
);
/* HERE STARTS THE REFRESHING MACHINE */
reg [1:0] Prstate, Nxtstate;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
initial begin Prstate = S0; end
//frecuencia de cambio entre cada display (agregar al informe, en el manual de Xilinx de la Nexys3 viene)
(* keep="soft" *)
wire CLK_1Hz;
(* keep="soft" *)
wire CLK_2Hz;
wire CLK_1KHz;
frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);
always @ (posedge CLK_1KHz) begin
Prstate = Nxtstate;
end
always @ (posedge CLK_1Hz)
begin
contador_seg = contador_seg + 1;
if (contador_seg == 10)
contador_seg = 0;
end
always @ (Prstate)
case (Prstate)
S0: Nxtstate = S1;
S1: Nxtstate = S2;
S2: Nxtstate = S3;
S3: Nxtstate = S0;
default: Nxtstate = S0;
endcase
always @ (*)
case (Prstate)
S0: // 1,2,3 o 4, en caso de espera es in -
begin
ANODES = 4'b1110;//se indica con un 0 el display
DISPLAY = DISPLAY1;
end
S1: // P
begin
ANODES = 4'b1101;
DISPLAY = DISPLAY2;
end
S2: // A o C
begin
ANODES = 4'b1011;
DISPLAY = DISPLAY3;
end
S3: // S o B
begin
ANODES = 4'b0111;
DISPLAY = DISPLAY4;
end
default:
begin // por defecto esta en espera ----
ANODES = 4'b0000;
DISPLAY = 7'b1111110;
end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_PP_SYMBOL_V
|
module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, clk, reset);
input[31:0] Xinport;
input[31:0] Yinport;
input[31:0] Uinport;
input[31:0] Aport;
input[31:0] DXport;
input clk;
input reset;
output[31:0] Xoutport;
output[31:0] Youtport;
output[31:0] Uoutport;
reg[31:0] Xoutport;
reg[31:0] Youtport;
reg[31:0] Uoutport;
reg[31:0] x_var;
reg[31:0] y_var;
reg[31:0] u_var;
wire[31:0] temp;
reg looping;
assign temp = u_var * DXport;
always @(posedge clk)
begin
if (reset == 1'b1)
begin
looping <= 1'b0;
x_var <= 0;
y_var <= 0;
u_var <= 0;
end
else
if (looping == 1'b0)
begin
x_var <= Xinport;
y_var <= Yinport;
u_var <= Uinport;
looping <= 1'b1;
end
else if (x_var < Aport)
begin
u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var);
y_var <= y_var + temp;//(u_var * DXport);
x_var <= x_var + DXport;
looping <= looping;
end
else
begin
Xoutport <= x_var ;
Youtport <= y_var ;
Uoutport <= u_var ;
looping <= 1'b0;
end
end
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
// This module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
module altera_jtag_dc_streaming #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1
) (
// Signals in the JTAG clock domain
input wire tck,
input wire tdi,
output wire tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire clk,
input wire reset_n,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// the tck to sysclk sync depth is fixed at 8
// 8 is the worst case scenario from our metastability analysis, and since
// using TCK serially is so slow we should have plenty of clock cycles.
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
// Since the tck clock is so slow, no parameter is exposed.
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
wire jtag_clock_reset_n; // system reset is synchronized with tck
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire [7:0] jtag_sink_data;
wire jtag_sink_valid;
wire jtag_sink_ready;
/* Reset Synchronizer module.
*
* The SLD Node does not provide a reset for the TCK clock domain.
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
* internal states need to be reset to 0 in order to guarantee proper
* functionality throughout resets.
*
* This reset block will asynchronously assert reset, and synchronously
* deassert reset for the tck clock domain.
*/
altera_std_synchronizer #(
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
) synchronizer (
.clk(tck),
.reset_n(reset_n),
.din(1'b1),
.dout(jtag_clock_reset_n)
);
altera_jtag_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.reset_n(jtag_clock_reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(jtag_sink_data),
.sink_valid(jtag_sink_valid),
.sink_ready(jtag_sink_ready),
.clock_to_sample(clk),
.reset_to_sample(reset_n),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
altera_avalon_st_clock_crosser #(
.SYMBOLS_PER_BEAT(1),
.BITS_PER_SYMBOL(8),
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) sink_crosser (
.in_clk(clk),
.in_reset(~reset_n),
.in_data(sink_data),
.in_ready(sink_ready),
.in_valid(sink_valid),
.out_clk(tck),
.out_reset(~jtag_clock_reset_n),
.out_data(jtag_sink_data),
.out_ready(jtag_sink_ready),
.out_valid(jtag_sink_valid)
);
altera_jtag_src_crosser #(
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) source_crosser (
.sink_clk(tck),
.sink_reset_n(jtag_clock_reset_n),
.sink_valid(jtag_source_valid),
.sink_data(jtag_source_data),
.src_clk(clk),
.src_reset_n(reset_n),
.src_valid(source_valid),
.src_data(source_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x0, y0, x1, y1; cin >> x0 >> y0 >> x1 >> y1; int n; cin >> n; multimap<int, pair<long long int, long long int> > sections; for (long long int i = 0; i < n; i++) { int r, a, b; cin >> r >> a >> b; sections.insert(make_pair(r, make_pair(a, b))); } map<pair<long long int, long long int>, bool> visited; map<pair<long long int, long long int>, int> dist; pair<long long int, long long int> start = make_pair(x0, y0); pair<long long int, long long int> target = make_pair(x1, y1); queue<pair<long long int, long long int> > que; que.push(start); visited[start] = true; dist[start] = 0; int dx[] = {-1, -1, -1, 0, 1, 1, 1, 0}; int dy[] = {-1, 0, 1, 1, 1, 0, -1, -1}; while (que.size()) { pair<long long int, long long int> cur = que.front(); que.pop(); if (cur == target) { break; }; for (long long int i = 0; i < 8; i++) { long long int nr = cur.first + dy[i]; long long int nc = cur.second + dx[i]; bool ok = false; if (visited[make_pair(nr, nc)]) continue; auto range = sections.equal_range(nr); for (auto it = range.first; it != range.second; it++) { pair<long long int, long long int> sec = it->second; if (nc <= sec.second && nc >= sec.first) { ok = true; break; } } if (ok) { visited[make_pair(nr, nc)] = true; dist[make_pair(nr, nc)] = dist[cur] + 1; que.push(make_pair(nr, nc)); } } } if (dist.find(target) == dist.end()) { cout << -1 << endl; } else { cout << dist[target] << endl; } } |
#include <bits/stdc++.h> using namespace std; struct less_key { bool operator()(pair<double, int64_t> p1, pair<double, int64_t> p2) { return (p1.first > p2.first) || ((p1.first == p2.first) && (p1.second < p2.second)); } }; struct pair_hash { std::size_t operator()(const pair<int64_t, int64_t>& k) const { return static_cast<size_t>(k.first ^ k.second); } }; const int64_t mod = 100000000007ll; const int64_t inf = 10000000000000007ll; const double eps = 0.00000001; int64_t n, k; string s; int64_t amin[256]; int64_t amax[256]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> k; cin >> s; for (int64_t i = 0; i < s.size(); i++) { if (!amin[s[i]]) { amin[s[i]] = i + 1; } amax[s[i]] = i + 1; } set<pair<int64_t, int64_t> > q; for (int64_t i = A ; i <= Z ; i++) { if (amin[i]) { q.insert({amin[i], 0}); q.insert({amax[i], 1}); } } int64_t z = 0; for (auto i : q) { if (i.second) { z--; } else { z++; } if (z > k) { cout << YES << endl; return 0; } } cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char a[2048][2048]; int flagr[2048], flagc[2048]; int n, ans = 0; void print() { cout << endl; cout << ========== << endl; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) cout << a[i][j]; cout << endl; } cout << endl; } void solve() { for (int i = 0; i < n; i++) { for (int j = n - 1; j > i; j--) { if ((a[i][j] - 0 + flagr[i] + flagc[j]) & 1) { a[i][j] = 0 ; flagc[j]++, flagr[i]++, ans++; } a[i][j] = 0 ; } } for (int i = 0; i < n; i++) { a[i][i] = (a[i][i] - 0 + flagr[i] + flagc[i]) % 2 + 48; } memset(flagr, 0, sizeof(flagr)); memset(flagc, 0, sizeof(flagc)); for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < i; j++) { if ((a[i][j] - 0 + flagr[i] + flagc[j]) & 1) { flagc[j]++, flagr[i]++, ans++; } a[i][j] = 0 ; } } for (int i = 0; i < n; i++) if ((a[i][i] - 0 + flagr[i] + flagc[i]) % 2) ans++; } int main() { int i, j, k, l; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , a[i]); } solve(); printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC FSM ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Insn cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_fsm.v,v $
// Revision 1.10 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.8 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.7 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/28 19:10:40 lampret
// Optimized cache controller FSM.
//
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
`define OR1200_ICFSM_IDLE 2'd0
`define OR1200_ICFSM_CFETCH 2'd1
`define OR1200_ICFSM_LREFILL3 2'd2
`define OR1200_ICFSM_IFETCH 2'd3
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
module or1200_ic_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
);
//
// I/O
//
input clk;
input rst;
input ic_en;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] icram_we;
output biu_read;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [2:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
//
// Generate of ICRAM write enables
//
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
| (state == `OR1200_ICFSM_LREFILL3);
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 32'b0;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cnt <= #1 3'b000;
cache_inhibit <= #1 1'b0;
end
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else begin // idle
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((!ic_en) ||
(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_ICLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
saved_addr_r <= #1 start_addr;
cache_inhibit <= #1 1'b0;
end
else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // fetch in-progress
hitmiss_eval <= #1 1'b0;
end
`OR1200_ICFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 3'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last fetch of line refill
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
end
default:
state <= #1 `OR1200_ICFSM_IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int SIZE = 1e6 + 5; const long long INF = 1LL << 58; const double eps = 1e-10; char d[2009][2009]; char a[2009][2009]; int dy[4] = {-1, 0, 1, 0}; int dx[4] = {0, 1, 0, -1}; int dy2[8] = {-2, -1, 0, 1, 2, 1, 0, -1}; int dx2[8] = {0, 1, 2, 1, 0, -1, -2, -1}; char v2[5] = ^>v< ; char v[5] = v<^> ; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < (n); ++i) { scanf( %s , (d[i])); for (int j = 0; j < (m); ++j) { if (d[i][j] == * ) a[i][j] = * ; else a[i][j] = . ; } } queue<pair<int, int> > q; for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) { if (d[i][j] == * ) continue; q.push(make_pair(i, j)); } } while (((int)(q).size())) { pair<int, int> cur = q.front(); q.pop(); int y = cur.first, x = cur.second; if (a[y][x] != . ) continue; int ck = -1; for (int k = 0; k < (4); ++k) { int ny = y + dy[k], nx = x + dx[k]; if (ny < 0 || ny >= n || nx < 0 || nx >= m) continue; if (a[ny][nx] == . ) { if (ck != -1) { ck = -1; break; } else ck = k; } } if (ck == -1) continue; int ny = y + dy[ck], nx = x + dx[ck]; a[y][x] = v[ck]; a[ny][nx] = v2[ck]; for (int k = 0; k < (8); ++k) { int ny = y + dy2[k], nx = x + dx2[k]; if (ny < 0 || ny >= n || nx < 0 || nx >= m) continue; q.push(make_pair(ny, nx)); } } for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) { if (a[i][j] == . ) { puts( Not unique ); return 0; } } } for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) { printf( %c , a[i][j]); } puts( ); } } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
reg xzcheck_window = 0;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
always @ (posedge clk)
begin
if (reset_n != 1'b0)
begin
if (!xzcheck_window && start_event == 1'b1)
xzcheck_window <= 1'b1;
else if (xzcheck_window && end_event == 1'b1)
xzcheck_window <= 1'b0;
end
else
begin
xzcheck_window <= 1'b0;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_window_assert
assert_window_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.end_event(end_event),
.xzcheck_window(xzcheck_window),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_window_assume
assert_window_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.end_event(end_event),
.xzcheck_window(xzcheck_window),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_window_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_window_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.end_event(end_event));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_window.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_window_assert (clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable);
input clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_window_assume (clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable);
input clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_window_cover (clk, reset_n, test_expr, start_event, end_event);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, test_expr, start_event, end_event;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int N = 1020; int main() { int n; cin >> n; if (n % 2 == 0) { cout << -1 << endl; } else { cout << 0; for (int i = 1; i < n; i++) { cout << << i; } cout << endl; cout << 0; for (int i = 1; i < n; i++) { cout << << i; } cout << endl; cout << 0; for (int i = 1; i < n; i++) { cout << << (i + i) % n; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int n; scanf( %d , &n); vector<vector<int> > p(n); for (int i = 0; i < n; i++) { int sz; scanf( %d , &sz); p[i].resize(sz); for (int j = 0; j < sz; j++) scanf( %d , &p[i][j]); } for (int i = 0; i < n; i++) { bool can = true; for (int j = 0; j < n; j++) { if (i == j || p[j].size() > p[i].size()) continue; int has[101] = {0}; bool ok = true; for (int k = 0; k < p[j].size(); k++) has[p[j][k]]++; for (int k = 0; k < p[i].size(); k++) has[p[i][k]]++; for (int k = 0; k < p[j].size(); k++) if (has[p[j][k]] != 2) ok = false; can &= !(ok); } if (can) puts( YES ); else puts( NO ); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> adj[200005]; long long siz = 0; long long cc = 0; long long t, n; long long a[200005]; long long vis[200005]; long long size_dict[200005]; void dfs(long long u) { vis[u] = cc; siz += 1; for (long long i = 0; i < adj[u].size(); i++) { if (!vis[adj[u][i]]) { dfs(adj[u][i]); } } } int main() { cin >> t; while (t--) { cin >> n; for (long long i = 0; i <= 200004; i++) { adj[i].clear(); } for (long long i = 0; i <= 200004; i++) vis[i] = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; adj[i + 1].push_back(a[i]); adj[a[i]].push_back(i + 1); } cc = 0; for (long long i = 0; i < n; i++) { if (!vis[i + 1]) { cc++; dfs(i + 1); size_dict[cc] = siz; siz = 0; } } for (long long i = 1; i <= n; i++) { cout << size_dict[vis[i]] << ; } cout << n ; } } |
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-27 08:30:43
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
//assign i = Stop_I;
if (SW <=`STOP_SW1 || SW <=`STOP_SW2) begin : GENSTOP
mult #(.SW(SW))
inst_mult (
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.sgf_result_o(sgf_result_o)
);
end else begin : RECURSIVE
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int knigths[300006]; set<int> s; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL), cout.tie(NULL); ios::sync_with_stdio(false), cin.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= n + 1; i++) s.insert(i); for (int i = 0; i < m; i++) { int a, b, c; cin >> a >> b >> c; set<int>::iterator itl = s.lower_bound(a); set<int>::iterator itu = s.upper_bound(b); while (*itl < *itu) { if (*itl != c) { knigths[*itl] = c; } s.erase(itl); itl = s.lower_bound(a); itu = s.upper_bound(b); } s.insert(c); } for (int i = 1; i <= n; i++) cout << knigths[i] << ; cout << endl; return 0; } |
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test different ways of accessing a 2D packed array.
module array_packed_2d();
reg [1:4][7:0] vec;
reg [4:1][7:0] vec2;
integer i;
initial begin
// test 1: assign using variable index
for(i = 1; i <= 4; i = i + 1)
vec[i] = i * 2;
// display whole vector
$display("%h", vec);
// $display using variable index
for(i = 1; i <= 4; i = i + 1)
$display(vec[i]);
// $display using constant index
$display(vec[1]);
$display(vec[2]);
$display(vec[3]);
$display(vec[4]);
// test 2: assign using a constant index
vec[1] = 2;
vec[2] = 4;
vec[3] = 6;
vec[4] = 8;
// display whole vector
$display("%h", vec);
// $display using variable index
for(i = 1; i <= 4; i = i + 1)
$display(vec[i]);
// $display using constant index
$display(vec[1]);
$display(vec[2]);
$display(vec[3]);
$display(vec[4]);
//////////////////////////////////////////
// test 1: assign using variable index
for(i = 1; i <= 4; i = i + 1)
vec2[i] = i * 2;
// display whole vector
$display("%h", vec2);
// $display using variable index
for(i = 1; i <= 4; i = i + 1)
$display(vec2[i]);
// $display using constant index
$display(vec2[1]);
$display(vec2[2]);
$display(vec2[3]);
$display(vec2[4]);
// test 2: assign using a constant index
vec2[1] = 2;
vec2[2] = 4;
vec2[3] = 6;
vec2[4] = 8;
// display whole vector
$display("%h", vec2);
// $display using variable index
for(i = 1; i <= 4; i = i + 1)
$display(vec2[i]);
// $display using constant index
$display(vec2[1]);
$display(vec2[2]);
$display(vec2[3]);
$display(vec2[4]);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> int len(const T &c) { return (int)c.size(); } template <class T> void cmin(T &a, T b) { if (b < a) a = b; } template <class T> void cmax(T &a, T b) { if (b > a) a = b; } vector<pair<int, int> > v; int main() { int n, t1, t2; cin >> n; for (int i(0), _n(n); i < _n; ++i) { cin >> t1 >> t2; if (t1 > t2) swap(t1, t2); v.push_back(make_pair(t1, t2)); } vector<int> ans; vector<pair<int, int> > tem; bool b; for (int i(0), _n(n); i < _n; ++i) { b = 1; tem.clear(); for (int j(0), _n(n); j < _n; ++j) if (j != i) tem.push_back(v[j]); sort(tem.begin(), tem.end()); for (int j(0), _n(n - 2); j < _n; ++j) { if (tem[j].second > tem[j + 1].first) { b = 0; break; } } if (b) ans.push_back(i + 1); } cout << len(ans) << endl; for (int i(0), _n(len(ans)); i < _n; ++i) cout << ans[i] << ; } |
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; long long mod = 1000000007; const int MX = 0x3f3f3f3f; bool G[8][8]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; if (n <= 6) { cout << m << endl; return 0; } for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; G[u][v] = G[v][u] = true; } int mini = INT_MAX; for (int i = 1; i <= 7; i++) { for (int j = 1; j <= 7; j++) { if (j == i) continue; int cur = 0; for (int k = 1; k <= 7; k++) cur += G[i][k] & G[j][k]; mini = min(mini, cur); } } cout << m - mini << n ; return 0; } |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.