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////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ad7980
(
input wire clk,
input wire rstn,
output wire [15:0] data,
output wire valid,
input wire ready,
input wire sdo,
output wire cnv,
output wire sclk
);
localparam [1:0]
STATE_IDLE = 3'd0,
STATE_CONVERT = 3'd1,
STATE_READ = 3'd2,
STATE_WAIT = 3'd3;
reg [1:0] state_reg, state_next;
reg [6:0] count_reg, count_next;
reg [15:0] data_reg, data_next;
reg valid_reg, valid_next;
reg cnv_reg, cnv_next;
reg sclk_reg, sclk_next;
assign valid = valid_reg;
assign data = data_reg;
assign cnv = cnv_reg;
assign sclk = sclk_reg;
always @* begin
state_next = STATE_IDLE;
cnv_next = cnv_reg;
sclk_next = sclk_reg;
count_next = count_reg;
data_next = data_reg;
valid_next = valid_reg;
case (state_reg)
STATE_IDLE: begin
if (ready) begin
cnv_next = 1'b1;
state_next = STATE_CONVERT;
end
end
STATE_CONVERT: begin
state_next = STATE_CONVERT;
count_next = count_reg + 1;
if (count_reg == 7'h46) begin
cnv_next = 1'b0;
sclk_next = 1'b1;
count_next = 7'b1;
state_next = STATE_READ;
end
end
STATE_READ: begin
state_next = STATE_READ;
count_next = count_reg + 1;
sclk_next = count_reg[0];
if (sclk_reg == 1'b0) begin
data_next = {data_reg[14:0], sdo};
end
if (count_reg == 7'h21) begin
count_next = 7'b0;
valid_next = 1'b1;
state_next = STATE_IDLE;
end
end
endcase
end
always @(posedge clk) begin
if (~rstn) begin
state_reg <= STATE_IDLE;
data_reg <= 16'b0;
valid_reg <= 1'b0;
count_reg <= 7'b0;
cnv_reg <= 1'b0;
sclk_reg <= 1'b1;
end else begin
state_reg <= state_next;
data_reg <= data_next;
valid_reg <= valid_next;
count_reg <= count_next;
cnv_reg <= cnv_next;
sclk_reg <= sclk_next;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> vv[3001]; int graf[3001][3001]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int f, t; cin >> f >> t; vv[f].push_back(t); graf[f][t] = 1; } long long ans(0); for (int a = 1; a <= n; a++) for (int c = 1; c <= n; c++) { if (a == c) continue; int cnt(0); for (int i = 0; i < vv[a].size(); i++) { int b = vv[a][i]; if (graf[b][c]) { cnt++; } } ans += 1LL * cnt * (cnt - 1) / 2; } cout << ans; } |
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard ()
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
module uart(
input clk_uart_x4, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been received.
output [7:0] rx_byte, // Byte received
output is_receiving, // Low when receive line is idle.
output is_transmitting, // Low when transmit line is idle.
output recv_error // Indicates error in receiving packet.
);
wire clk;
assign clk = clk_uart_x4;
// States for the receiving state machine.
// These are just constants, not parameters to override.
parameter RX_IDLE = 0;
parameter RX_CHECK_START = 1;
parameter RX_READ_BITS = 2;
parameter RX_CHECK_STOP = 3;
parameter RX_DELAY_RESTART = 4;
parameter RX_ERROR = 5;
parameter RX_RECEIVED = 6;
// States for the transmitting state machine.
// Constants - do not override.
parameter TX_IDLE = 0;
parameter TX_SENDING = 1;
parameter TX_DELAY_RESTART = 2;
reg [2:0] recv_state = RX_IDLE;
reg [3:0] rx_countdown;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [3:0] tx_countdown;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
always @(posedge clk) begin //or posedge rst
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
rx_countdown = rx_countdown - 1;
tx_countdown = tx_countdown - 1;
// Receive state machine
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait half the period - should resume in the
// middle of this first pulse.
rx_countdown = 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_countdown) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period to resume half-way
// through the first bit.
rx_countdown = 4;
rx_bits_remaining = 8;
recv_state = RX_READ_BITS;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_READ_BITS: begin
if (!rx_countdown) begin
// Should be half-way through a bit pulse here.
// Read this bit in, wait for the next if we
// have more to get.
rx_data = {rx, rx_data[7:1]};
rx_countdown = 4;
rx_bits_remaining = rx_bits_remaining - 1;
recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
end
end
RX_CHECK_STOP: begin
if (!rx_countdown) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_countdown = 8;
recv_state = RX_DELAY_RESTART;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
// Transmit state machine
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
tx_countdown = 4;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_countdown) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_countdown = 4;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_countdown = 8;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
end
endcase
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 10; long long n, k; int main() { scanf( %I64d%I64d , &n, &k); long long x; x = sqrt(9 + 8 * (n + k)) - 3; x /= 2; printf( %I64d n , n - x); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:32:27 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/vio_0/vio_0_stub.v
// Design : vio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2016.3" *)
module vio_0(clk, probe_in0, probe_in1, probe_in2, probe_in3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0]" */;
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
endmodule
|
module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [10:0] CounterX;
output [10:0] CounterY;
//// VGA mode 800x600x75Hz /////
//// pixel freq: 49.5MHz (should be input clk)
//// visible pixels: 800
//// visible lines: 600
//// vertical refresh freq: 46.875 kHz
//// horizontal refresh freq: 75Hz (~72Hz for wxeda 48.0Mhz clock)
//// polarization: horizontal - P, vertical - P
integer width = 11'd800; // screen width (visible)
integer height = 11'd600; // screen heigh (visible)
integer count_dots = 11'd1056; // count of dots in line
integer count_lines = 11'd625; // count of lines
integer h_front_porch = 11'd16; // count of dots before sync pulse
integer h_sync_pulse = 11'd80; // duration of sync pulse
integer h_back_porch = 11'd160; // count of dots after sync pulse
integer v_front_porch = 11'd1; // count of lines before sync pulse
integer v_sync_pulse = 11'd3; // duration of sync pulse
integer v_back_porch = 11'd21; // count of lines after sync pulse
//////////////////////////////////////////////////
reg [10:0] CounterX;
reg [10:0] CounterY;
wire CounterXmaxed = (CounterX==count_dots);
wire CounterYmaxed = (CounterY==count_lines);
always @(posedge clk)
if(CounterXmaxed)
CounterX <= 0;
else
CounterX <= CounterX + 1;
always @(posedge clk)
if(CounterXmaxed)
begin
if (CounterYmaxed)
CounterY <= 0;
else
CounterY <= CounterY + 1;
end
reg vga_HS, vga_VS;
always @(posedge clk)
begin
vga_HS <= (CounterX >= (width+h_front_porch) && CounterX < (width+h_front_porch+h_sync_pulse));
vga_VS <= (CounterY >= (height+v_front_porch) && CounterY < (height+v_front_porch+v_sync_pulse));
end
assign inDisplayArea = (CounterX < width && CounterY < height) ? 1'b1: 1'b0;
assign vga_h_sync = vga_HS; // positive polarization
assign vga_v_sync = vga_VS; // positive polarization
endmodule
|
//bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
fail <= 1'h0;
pass <= 1'h0;
ready <= 1'h0;
// End of automatics
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
out0 = 8'h0;
// End of automatics
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
next_fail = 1'h0;
next_pass = 1'h0;
next_ready = 1'h0;
// End of automatics
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
Q <= 8'h0;
// End of automatics
end
else if (clk) begin
Q <= D;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; int type[N], n, p[N], out[N]; int go(int u, bool print = false) { int res = p[u] == -1 || out[p[u]] > 1 ? 1 : go(p[u], print) + 1; if (print) cout << u + 1 << ; return res; } int main() { cin >> n; for (int i = 0; i < n; ++i) cin >> type[i]; for (int i = 0; i < n; ++i) { cin >> p[i]; if (--p[i] >= 0) ++out[p[i]]; } int res = -1; for (int i = 0; i < n; ++i) if (type[i] == 1) if (res == -1 || go(i) > go(res)) res = i; cout << go(res) << endl; go(res, true); return 0; } |
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_mem_server_request_put O 1 reg
// mem_server_response_get O 256 reg
// RDY_mem_server_response_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// mem_server_request_put I 353
// EN_mem_server_request_put I 1
// EN_mem_server_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMem_Model(CLK,
RST_N,
mem_server_request_put,
EN_mem_server_request_put,
RDY_mem_server_request_put,
EN_mem_server_response_get,
mem_server_response_get,
RDY_mem_server_response_get);
input CLK;
input RST_N;
// action method mem_server_request_put
input [352 : 0] mem_server_request_put;
input EN_mem_server_request_put;
output RDY_mem_server_request_put;
// actionvalue method mem_server_response_get
input EN_mem_server_response_get;
output [255 : 0] mem_server_response_get;
output RDY_mem_server_response_get;
// signals for module outputs
wire [255 : 0] mem_server_response_get;
wire RDY_mem_server_request_put, RDY_mem_server_response_get;
// ports of submodule f_raw_mem_rsps
wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT;
wire f_raw_mem_rsps$CLR,
f_raw_mem_rsps$DEQ,
f_raw_mem_rsps$EMPTY_N,
f_raw_mem_rsps$ENQ,
f_raw_mem_rsps$FULL_N;
// ports of submodule rf
wire [255 : 0] rf$D_IN, rf$D_OUT_1;
wire [63 : 0] rf$ADDR_1,
rf$ADDR_2,
rf$ADDR_3,
rf$ADDR_4,
rf$ADDR_5,
rf$ADDR_IN;
wire rf$WE;
// rule scheduling signals
wire CAN_FIRE_mem_server_request_put,
CAN_FIRE_mem_server_response_get,
WILL_FIRE_mem_server_request_put,
WILL_FIRE_mem_server_response_get;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h371;
reg [31 : 0] v__h365;
// synopsys translate_on
// remaining internal signals
wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2;
// action method mem_server_request_put
assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ;
assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ;
assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ;
// actionvalue method mem_server_response_get
assign mem_server_response_get = f_raw_mem_rsps$D_OUT ;
assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ;
assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ;
assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ;
// submodule f_raw_mem_rsps
FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_raw_mem_rsps$D_IN),
.ENQ(f_raw_mem_rsps$ENQ),
.DEQ(f_raw_mem_rsps$DEQ),
.CLR(f_raw_mem_rsps$CLR),
.D_OUT(f_raw_mem_rsps$D_OUT),
.FULL_N(f_raw_mem_rsps$FULL_N),
.EMPTY_N(f_raw_mem_rsps$EMPTY_N));
// submodule rf
RegFileLoad #(.file("Mem.hex"),
.addr_width(32'd64),
.data_width(32'd256),
.lo(64'd0),
.hi(64'd8388607),
.binary(1'd0)) rf(.CLK(CLK),
.ADDR_1(rf$ADDR_1),
.ADDR_2(rf$ADDR_2),
.ADDR_3(rf$ADDR_3),
.ADDR_4(rf$ADDR_4),
.ADDR_5(rf$ADDR_5),
.ADDR_IN(rf$ADDR_IN),
.D_IN(rf$D_IN),
.WE(rf$WE),
.D_OUT_1(rf$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule f_raw_mem_rsps
assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ;
assign f_raw_mem_rsps$ENQ =
EN_mem_server_request_put &&
mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 &&
!mem_server_request_put[352] ;
assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ;
assign f_raw_mem_rsps$CLR = 1'b0 ;
// submodule rf
assign rf$ADDR_1 = mem_server_request_put[319:256] ;
assign rf$ADDR_2 = 64'h0 ;
assign rf$ADDR_3 = 64'h0 ;
assign rf$ADDR_4 = 64'h0 ;
assign rf$ADDR_5 = 64'h0 ;
assign rf$ADDR_IN = mem_server_request_put[319:256] ;
assign rf$D_IN = mem_server_request_put[255:0] ;
assign rf$WE =
EN_mem_server_request_put &&
mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 &&
mem_server_request_put[352] ;
// remaining internal signals
assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 =
mem_server_request_put[319:256] < 64'h0000000000800000 ;
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
begin
v__h371 = $stime;
#0;
end
v__h365 = v__h371 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
$display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)",
v__h365,
mem_server_request_put[319:256],
64'h0000000000800000);
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkMem_Model
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls 16x2 character LCD on the Altera DE2 Board. *
* *
******************************************************************************/
module tracking_camera_system_character_lcd_0 (
// Inputs
clk,
reset,
address,
chipselect,
read,
write,
writedata,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
readdata,
waitrequest
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CURSOR_ON = 1'b1;
parameter BLINKING_ON = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input read;
input write;
input [ 7: 0] writedata;
// Bidirectionals
inout [ 7: 0] LCD_DATA; // LCD Data bus 8 bits
// Outputs
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_EN; // LCD Enable
output LCD_RS; // LCD 0-Command/1-Data Select
output LCD_RW; // LCD 1-Read/0-Write Select
output [ 7: 0] readdata;
output waitrequest;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam LCD_STATE_0_IDLE = 3'h0,
LCD_STATE_1_INITIALIZE = 3'h1,
LCD_STATE_2_START_CHECK_BUSY = 3'h2,
LCD_STATE_3_CHECK_BUSY = 3'h3,
LCD_STATE_4_BEGIN_TRANSFER = 3'h4,
LCD_STATE_5_TRANSFER = 3'h5,
LCD_STATE_6_COMPLETE = 3'h6;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_complete;
wire done_initialization;
wire init_send_command;
wire [ 8: 0] init_command;
wire send_data;
wire [ 7: 0] data_received;
// Internal Registers
reg initialize_lcd_display;
reg [ 7: 0] data_to_send;
reg rs;
reg rw;
// State Machine Registers
reg [ 2: 0] ns_lcd_controller;
reg [ 2: 0] s_lcd_controller;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd_controller <= LCD_STATE_0_IDLE;
else
s_lcd_controller <= ns_lcd_controller;
end
always @(*)
begin
// Defaults
ns_lcd_controller = LCD_STATE_0_IDLE;
case (s_lcd_controller)
LCD_STATE_0_IDLE:
begin
if (initialize_lcd_display)
ns_lcd_controller = LCD_STATE_1_INITIALIZE;
else if (chipselect)
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
else
ns_lcd_controller = LCD_STATE_0_IDLE;
end
LCD_STATE_1_INITIALIZE:
begin
if (done_initialization)
ns_lcd_controller = LCD_STATE_6_COMPLETE;
else
ns_lcd_controller = LCD_STATE_1_INITIALIZE;
end
LCD_STATE_2_START_CHECK_BUSY:
begin
if (transfer_complete == 1'b0)
ns_lcd_controller = LCD_STATE_3_CHECK_BUSY;
else
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
end
LCD_STATE_3_CHECK_BUSY:
begin
if ((transfer_complete) && (data_received[7]))
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
else if ((transfer_complete) && (data_received[7] == 1'b0))
ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER;
else
ns_lcd_controller = LCD_STATE_3_CHECK_BUSY;
end
LCD_STATE_4_BEGIN_TRANSFER:
begin
if (transfer_complete == 1'b0)
ns_lcd_controller = LCD_STATE_5_TRANSFER;
else
ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER;
end
LCD_STATE_5_TRANSFER:
begin
if (transfer_complete)
ns_lcd_controller = LCD_STATE_6_COMPLETE;
else
ns_lcd_controller = LCD_STATE_5_TRANSFER;
end
LCD_STATE_6_COMPLETE:
begin
ns_lcd_controller = LCD_STATE_0_IDLE;
end
default:
begin
ns_lcd_controller = LCD_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
initialize_lcd_display <= 1'b1;
else if (done_initialization)
initialize_lcd_display <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
data_to_send <= 8'h00;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
data_to_send <= init_command[7:0];
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
data_to_send <= writedata[7:0];
end
always @(posedge clk)
begin
if (reset)
rs <= 1'b0;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
rs <= init_command[8];
else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY)
rs <= 1'b0;
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
rs <= address;
end
always @(posedge clk)
begin
if (reset)
rw <= 1'b0;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
rw <= 1'b0;
else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY)
rw <= 1'b1;
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
rw <= ~write;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign readdata = data_received;
assign waitrequest = chipselect & (s_lcd_controller != LCD_STATE_6_COMPLETE);
// Internal Assignments
assign send_data =
(s_lcd_controller == LCD_STATE_1_INITIALIZE) ? init_send_command :
(s_lcd_controller == LCD_STATE_3_CHECK_BUSY) ? 1'b1 :
(s_lcd_controller == LCD_STATE_5_TRANSFER) ? 1'b1 : 1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_character_lcd_communication Char_LCD_Comm (
// Inputs
.clk (clk),
.reset (reset),
.data_in (data_to_send),
.enable (send_data),
.rs (rs),
.rw (rw),
.display_on (1'b1),
.back_light_on (1'b1),
// Bidirectionals
.LCD_DATA (LCD_DATA),
// Outputs
.LCD_ON (LCD_ON),
.LCD_BLON (LCD_BLON),
.LCD_EN (LCD_EN),
.LCD_RS (LCD_RS),
.LCD_RW (LCD_RW),
.data_out (data_received),
.transfer_complete (transfer_complete)
);
altera_up_character_lcd_initialization Char_LCD_Init (
// Inputs
.clk (clk),
.reset (reset),
.initialize_LCD_display (initialize_lcd_display),
.command_was_sent (transfer_complete),
// Bidirectionals
// Outputs
.done_initialization (done_initialization),
.send_command (init_send_command),
.the_command (init_command)
);
defparam
Char_LCD_Init.CURSOR_ON = CURSOR_ON,
Char_LCD_Init.BLINKING_ON = BLINKING_ON;
endmodule
|
#include <bits/stdc++.h> template <class T> T _diff(T a, T b) { return (a < b ? b - a : a - b); } template <class T> T _abs(T a) { return (a < 0 ? -a : a); } template <class T> T _max(T a, T b) { return (a > b ? a : b); } template <class T> T _min(T a, T b) { return (a < b ? a : b); } template <class T> T max3(T a, T b, T c) { return (_max(a, b) > c ? _max(a, b) : c); } template <class T> T min3(T a, T b, T c) { return (_min(a, b) < c ? _min(a, b) : c); } template <class T> T GCD(T a, T b) { a = _abs(a); b = _abs(b); T tmp; while (a % b) { tmp = a % b; a = b; b = tmp; } return b; } template <class T> T LCM(T a, T b) { a = _abs(a); b = _abs(b); return (a / GCD(a, b)) * b; } using namespace std; long long n, k, mul; int main() { cin >> n >> k; mul = (n * (n - 1)) / 2; if (mul <= k) cout << no solution n ; else { for (int i = 0; i < n; i++) { cout << 0 << << i << endl; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_V |
// Simple 8-bit UART receiver
// Author: Ross MacArthur (https://github.com/rossmacarthur)
// Description:
// - Samples input line at 16 time the baudrate
// - Receives data in 8-bit chunks, LSB first
// - No parity
// - Single start and stop bit
module UART_RX (
input clk, // 16 * baudrate
input rst, // enable receiver
input RX, // UART receive line
output reg busy, // high when receiving
output reg [7:0] data // received data
);
reg RX_d;
reg [9:0] datafill;
reg [3:0] index;
reg [3:0] sampler;
always @(posedge clk) begin
RX_d <= RX;
if (rst) begin
busy <= 1'b0;
datafill <= 10'b0;
index <= 4'b0;
sampler <= 4'b0;
end else begin
if (~busy & ~RX_d) begin
busy <= 1'b1;
sampler <= 4'b0;
index <= 4'b0;
end
if (busy) begin
sampler <= sampler + 1'b1;
if (sampler == 4'd7) begin
if (RX_d & ~|index)
busy <= 1'b0;
else begin
index <= index + 1'b1;
datafill[index] <= RX_d;
if (index == 9) begin
data <= datafill[8:1];
index <= 4'b0;
busy <= 1'b0;
end
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const int mod = 1000000007; const int MAXN = 1010; int n, m, t, x, y, xx, yy, ans, v, u, q, a, b, c, cnt; string A[MAXN]; int dist[MAXN][MAXN]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> A[i]; A[i] = . + A[i]; for (int j = 1; j <= m; j++) { if (A[i][j] == S ) { xx = i; yy = j; } if (A[i][j] == E ) { x = i; y = j; } } } queue<pair<int, int> > q; q.push({x, y}); memset(dist, 63, sizeof(dist)); dist[x][y] = 0; while (!q.empty()) { int x = q.front().first, y = q.front().second; q.pop(); if (dist[x][y] > dist[xx][yy]) break; if (x < 1 || y < 1 || x > n || y > m || A[x][y] == T ) continue; if (dist[x][y] + 1 < dist[x + 1][y]) { dist[x + 1][y] = dist[x][y] + 1; q.push({x + 1, y}); } if (dist[x][y] + 1 < dist[x][y + 1]) { dist[x][y + 1] = dist[x][y] + 1; q.push({x, y + 1}); } if (dist[x][y] + 1 < dist[x - 1][y]) { dist[x - 1][y] = dist[x][y] + 1; q.push({x - 1, y}); } if (dist[x][y] + 1 < dist[x][y - 1]) { dist[x][y - 1] = dist[x][y] + 1; q.push({x, y - 1}); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (A[i][j] == S || A[i][j] == E || A[i][j] == T ) continue; if (dist[i][j] <= dist[xx][yy]) ans += A[i][j] - 0 ; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int lcm(int a, int b) { return a * (b / gcd(a, b)); } const int maxSize = 100000 + 5; int main() { int n, k; cin >> n >> k; vector<long long int> arr(n); for (int i = 0; i < n; i++) { cin >> arr[i]; } vector<long long int> pwr; long long int limit = 1e14; long long int ans = 1; pwr.push_back(1); if (abs(k) > 1) { while (ans * k <= limit) { ans *= k; pwr.push_back(ans); } } else if (k == -1) { pwr.push_back(-1); } map<long long int, long long int> make_pair; long long int sum = 0; ans = 0; for (int i = 0; i < n; i++) { make_pair[sum]++; sum += arr[i]; for (auto pw : pwr) { if (make_pair.count(sum - pw) > 0) { ans += make_pair[sum - pw]; } } } cout << ans; } |
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ()
//
// Brief Description:
// Performs "transport multiplex adaptation" and randomization for DVB-S.
//
//------------------------------------------------------------------------------
`ifndef _ZL_SYNC_INVERT_RANDOMIZER_V_
`define _ZL_SYNC_INVERT_RANDOMIZER_V_
`include "zl_lfsr.v"
module zl_sync_invert_randomizer
(
input clk,
input rst_n,
//
input data_in_req,
output reg data_in_ack,
input [7:0] data_in,
//
output reg data_out_req,
input data_out_ack,
output reg [7:0] data_out
);
localparam S_sync_invert = 0;
localparam S_sync_passthru = 1;
localparam S_data = 2;
localparam Sync_byte = 8'h47;
localparam Packet_len = 188;
localparam Group_len = 8;
localparam Packet_len_width = 8;
localparam Group_len_width = 3;
reg [1:0] state_reg;
reg [Packet_len_width-1:0] byte_count;
reg [Group_len_width-1:0] packet_count;
wire prbs_stall;
wire prbs_clear;
wire [7:0] prbs;
zl_lfsr #
(
.LFSR_poly(16'b1100000000000001),
.LFSR_width(15),
.LFSR_init_value(15'b000000010101001),
.PRBS_width(8)
)
prbs_gen
(
.clk(clk),
.rst_n(rst_n),
//
.stall(prbs_stall),
.clear(prbs_clear),
.lfsr_state(),
.prbs(prbs)
);
assign prbs_stall = !(data_in_req && data_out_ack &&
(state_reg != S_sync_invert));
assign prbs_clear = (byte_count == Packet_len-1)
&& (packet_count == Group_len-1);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state_reg <= S_sync_invert;
byte_count <= {Packet_len_width{1'b0}};
packet_count <= {Group_len_width{1'b0}};
end
else begin
case(state_reg)
S_sync_invert: begin
// only start a group of 8 packets if we see a sync byte
if(data_in_req && data_out_ack && data_in == Sync_byte) begin
byte_count <= byte_count + 1'b1;
state_reg <= S_data;
end
end
S_sync_passthru: begin
if(data_in_req && data_out_ack) begin
byte_count <= byte_count + 1'b1;
state_reg <= S_data;
end
end
S_data: begin
if(data_in_req && data_out_ack) begin
if(byte_count == Packet_len-1) begin
if(packet_count == Group_len-1) begin
byte_count <= {Packet_len_width{1'b0}};
packet_count <= {Group_len_width{1'b0}};
state_reg <= S_sync_invert;
end
else begin
byte_count <= {Packet_len_width{1'b0}};
packet_count <= packet_count + 1'b1;
state_reg <= S_sync_passthru;
end
end
else begin
byte_count <= byte_count + 1'b1;
end
end
end
endcase
end
end
always @(*) begin
case (state_reg)
S_sync_invert: begin
data_in_ack = (data_in_req && !(data_in == Sync_byte))
|| (data_in_req && data_out_ack);
data_out_req = (data_in_req && (data_in == Sync_byte));
data_out = ~data_in;
end
S_sync_passthru: begin
data_in_ack = data_in_req && data_out_ack;
data_out_req = data_in_req;
data_out = data_in;
end
S_data: begin
data_in_ack = data_in_req && data_out_ack;
data_out_req = data_in_req;
data_out = data_in ^ prbs;
end
endcase
end
endmodule // zl_sync_invert_randomizer
`endif // _ZL_SYNC_INVERT_RANDOMIZER_V_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__AND2B_PP_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 18:41:38 09/19/2015
// Design Name: hw2problem3
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/hw2problem3/hw2problem3Test.v
// Project Name: hw2problem3
////////////////////////////////////////////////////////////////////////////////
module hw2problem3Test;
reg X, RESET, CLOCK;
wire Y;
wire [1:0] CurrentState;
hw2problem3 uut(X, Y, RESET, CLOCK, CurrentState);
always #5 CLOCK = ~CLOCK;
initial begin
CLOCK = 0; RESET = 0; X = 0; #1;
RESET = 1; #13; // Start at 00
X = 1; #10; // Go to 01
X = 1; #10; // Go to 11
X = 1; #10; // Go to 10
X = 1; #10; // Stay at 10
X = 0; #10; // Go to 00
X = 0; #10; // Stay at 00
X = 1; #10; // Go to 01
X = 0; #10; // Go to 00
X = 1; #10; // Go to 01
X = 1; #10; // Go to 11
X = 0; #10; // Go to 00
X = 1; #7; // Go to 01
RESET = 0; #10 // Reset to 00 asynchronously
$stop;
end
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
recFNToRecFN#(
parameter inExpWidth = 3,
parameter inSigWidth = 3,
parameter outExpWidth = 3,
parameter outSigWidth = 3
) (
input [(`floatControlWidth - 1):0] control,
input [(inExpWidth + inSigWidth):0] in,
input [2:0] roundingMode,
output [(outExpWidth + outSigWidth):0] out,
output [4:0] exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaN, isInf, isZero, sign;
wire signed [(inExpWidth + 1):0] sExpIn;
wire [inSigWidth:0] sigIn;
recFNToRawFN#(inExpWidth, inSigWidth)
inToRawIn(in, isNaN, isInf, isZero, sign, sExpIn, sigIn);
wire isSigNaN;
isSigNaNRecFN#(inExpWidth, inSigWidth) isSigNaNIn(in, isSigNaN);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
generate
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) begin
/*----------------------------------------------------------------
*----------------------------------------------------------------*/
wire [(outExpWidth + outSigWidth):0] tentativeOut =
in<<(outSigWidth - inSigWidth);
`ifdef HardFloat_propagateNaNPayloads
assign out = tentativeOut | isNaN<<(outSigWidth - 2);
`else
assign out =
isNaN
? {`HardFloat_signDefaultNaN, 3'b111}
<<(outExpWidth + outSigWidth - 3)
| `HardFloat_fractDefaultNaN(outSigWidth)
: tentativeOut;
`endif
assign exceptionFlags = {isSigNaN, 4'b0000};
end else begin
/*----------------------------------------------------------------
*----------------------------------------------------------------*/
roundAnyRawFNToRecFN#(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
`flRoundOpt_sigMSBitAlwaysZero
) roundRawInToOut(
control,
isSigNaN,
1'b0,
isNaN,
isInf,
isZero,
sign,
sExpIn,
sigIn,
roundingMode,
out,
exceptionFlags
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( tune=native ) #pragma GCC optimize( fast-math ) using namespace std; const int DEBUG = 0; mt19937 gen( (unsigned)chrono::high_resolution_clock::now().time_since_epoch().count()); #pragma comment(linker, /STACK:16777216 ) void solve() { int h, w; cin >> h >> w; vector<string> a(h); vector<int> x1(26, 1000000000), x2(26, -1), y1(26, 1000000000), y2(26, -1); for (int i = 0; i < h; i++) { cin >> a[i]; for (int j = 0; j < w; j++) { if (a[i][j] == . ) continue; int k = (a[i][j] - a ); x1[k] = min(x1[k], j); x2[k] = max(x2[k], j); y1[k] = min(y1[k], i); y2[k] = max(y2[k], i); } } int ok = 1; int last = -1; int last_ch = -1; for (int i = 0; i < 26; i++) { if (x1[i] != 1000000000) last_ch = i; } for (int i = 0; i < 26; i++) { if (x1[i] == 1000000000) { if (i <= last_ch && last_ch != -1) { x1[i] = x1[last_ch]; x2[i] = x2[last_ch]; y1[i] = y1[last_ch]; y2[i] = y2[last_ch]; } continue; } last = i; if (x1[i] != x2[i] && y1[i] == y2[i]) ; else if (x1[i] == x2[i] && y1[i] != y2[i]) ; else if (x1[i] == x2[i] && y1[i] == y2[i]) ; else ok = 0; } if (!ok) { cout << NO n ; return; } vector<string> b(h, string(w, . )); int cnt = 0; for (int k = 0; k < 26; k++) { if (x1[k] == 1000000000) continue; ++cnt; for (int i = y1[k]; i <= y2[k]; i++) for (int j = x1[k]; j <= x2[k]; j++) b[i][j] = char( a + k); } for (int i = 0; i < h; i++) for (int j = 0; j < w; j++) if (a[i][j] != b[i][j]) ok = 0; if (!ok) { cout << NO n ; return; } cout << YES n ; cout << cnt << n ; for (int i = 0; i < cnt; i++) { cout << y1[i] + 1 << << x1[i] + 1 << << y2[i] + 1 << << x2[i] + 1 << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.setf(cout.fixed); cout.precision(12); auto START_TIME = chrono::high_resolution_clock::now(); int test; cin >> test; while (test--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int tichnas; cin >> tichnas; while (tichnas--) { long long n, c, m, maxs = 1e9, temp, ans; map<long long, long long> type; bool possible; cin >> n; for (int i = 0; i < n; i++) { cin >> c; type[c]++; } for (auto it = type.begin(); it != type.end(); it++) maxs = min(maxs, it->second + 1); ans = n; for (int i = 2; i <= maxs; i++) { possible = true; m = 0; for (auto it = type.begin(); it != type.end() && possible; it++) { temp = it->second; if (temp % i == 0) m += temp / i; else if (i - 1 - temp % i <= temp / i) m += temp / i + 1; else possible = false; } if (possible) ans = m; } cout << ans << n ; } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO.v
// Version : 2.4
//
// Description: Programmed I/O module. Design implements 8 KBytes of programmable
//-- memory space. Host processor can access this memory space using
//-- Memory Read 32 and Memory Write 32 TLPs. Design accepts
//-- 1 Double Word (DW) payload length on Memory Write 32 TLP and
//-- responds to 1 DW length Memory Read 32 TLPs with a Completion
//-- with Data TLP (1DW payload).
//--
//-- The module designed to operate with 32 bit and 64 bit interfaces.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
)(
input user_clk,
input user_reset,
input user_lnk_up,
// AXIS
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_completer_id,
input cfg_bus_mstr_enable
); // synthesis syn_hier = "hard"
// Local wires
wire req_compl;
wire compl_done;
wire pio_reset_n = user_lnk_up && !user_reset;
//
// PIO instance
//
PIO_EP #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) PIO_EP (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.req_compl_o(req_compl), // O
.compl_done_o(compl_done), // O
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable ( cfg_bus_mstr_enable ) // I
);
//
// Turn-Off controller
//
PIO_TO_CTRL PIO_TO (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.req_compl_i( req_compl ), // I
.compl_done_i( compl_done ), // I
.cfg_to_turnoff( cfg_to_turnoff ), // I
.cfg_turnoff_ok( cfg_turnoff_ok ) // O
);
endmodule // PIO
|
#include <bits/stdc++.h> using namespace std; struct __timestamper {}; const int MAXN = 100100; int val[MAXN]; long long dp[MAXN][4]; vector<int> g[MAXN]; void dfs(int v, int p) { for (int u : g[v]) if (u != p) dfs(u, v); long long max0 = 0, smax0 = 0, tmax0 = 0; int max0v = -1, smax0v = -1; long long max1 = 0, smax1 = 0; int max1v = -1; long long max2 = 0, smax2 = 0; int max2v = -1; long long max3 = 0, smax3 = 0; for (int u : g[v]) if (u != p) { long long t = dp[u][0]; int tv = u; if (t > max0) { swap(t, max0); swap(max0v, tv); } if (t > smax0) { swap(t, smax0); swap(smax0v, tv); } if (t > tmax0) { swap(t, tmax0); } t = dp[u][1]; if (t > max1) { swap(t, max1); max1v = u; } if (t > smax1) swap(t, smax1); t = dp[u][2]; if (t > max2) { swap(t, max2); max2v = u; } if (t > smax2) swap(t, smax2); t = dp[u][3]; if (t > max3) { swap(t, max3); } if (t > smax3) swap(t, smax3); } dp[v][0] = max0 + val[v]; dp[v][1] = max(max1, max0 + smax0 + val[v]); dp[v][2] = max2 + val[v]; if (max0v == max1v) { dp[v][2] = max(dp[v][2], max(max0 + smax1, max1 + smax0) + val[v]); } else { dp[v][2] = max(dp[v][2], max0 + max1 + val[v]); } dp[v][3] = max3; dp[v][3] = max(dp[v][3], max1 + smax1); if (max0v == max2v) { dp[v][3] = max(dp[v][3], max(max0 + smax2, max2 + smax0) + val[v]); } else { dp[v][3] = max(dp[v][3], max0 + max2 + val[v]); } for (int u : g[v]) if (u != p) { long long cur = val[v] + dp[u][1]; if (u == max0v) { cur += smax0 + tmax0; } else if (u == smax0v) { cur += max0 + tmax0; } else { cur += max0 + smax0; } dp[v][3] = max(dp[v][3], cur); } } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &val[i]); for (int i = 1; i < n; i++) { int a, b; scanf( %d%d , &a, &b); --a, --b; g[a].push_back(b); g[b].push_back(a); } dfs(0, -1); printf( %lld n , *max_element(dp[0], dp[0] + 4)); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, b, i, rez, a[2013], minn[2013], maxx[2013]; int main() { minn[0] = 123456890; cin >> n >> b; for (i = 1; i <= n; ++i) { cin >> a[i]; minn[i] = min(minn[i - 1], a[i]); } for (i = n; i >= 1; --i) { maxx[i] = max(maxx[i + 1], a[i]); } for (i = 1; i <= n; ++i) { rez = max(rez, b / minn[i] * maxx[i] + b % minn[i]); } cout << rez; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, d; string s, t; map<pair<char, char>, vector<int> > M; map<char, vector<int> > N; int main() { ios_base::sync_with_stdio(false); cin >> n >> s >> t; d = 0; for (int i = 0; i < n; ++i) { if (s[i] != t[i]) { M[make_pair(s[i], t[i])].push_back(i + 1); N[s[i]].push_back(i + 1); ++d; } } for (int i = 0; i < n; ++i) { if (s[i] != t[i]) { map<pair<char, char>, vector<int> >::iterator it = M.find(make_pair(t[i], s[i])); if (it != M.end()) { cout << d - 2 << endl; cout << i + 1 << << it->second.back() << endl; return 0; } } } for (int i = 0; i < n; ++i) { if (s[i] != t[i]) { if (N.find(t[i]) != N.end()) { cout << d - 1 << endl; cout << i + 1 << << N[t[i]].back() << endl; return 0; } } } cout << d << endl; cout << -1 -1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a[3], b[3]; for (int i = 0; i < 3; i++) cin >> a[i] >> b[i]; bool flag = false; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { for (int p = 0; p < 2; p++) { if (max(a[1], a[2]) <= a[0] && b[1] + b[2] <= b[0]) flag = true; swap(a[0], b[0]); } swap(a[2], b[2]); } swap(a[1], b[1]); } if (flag) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; constexpr int64_t P0 = 2000003; constexpr int64_t P1 = 2000017; constexpr int64_t M0 = 3000000000013; constexpr int64_t M1 = 2000000000003; class TaskC { public: struct Class { int id; int cnt; }; struct Hash { int64_t a, b; Hash() : a(0), b(0) {} void update(int addition) { a = (a * P0 + addition) % M0; b = (b * P1 + addition) % M1; } bool operator<(const Hash& other) const { return std::tie(a, b) < std::tie(other.a, other.b); } }; void solve(std::istream& in, std::ostream& out) { int n, m; in >> n >> m; vector<vector<int>> schools(n); vector<Class> classes; int timer = 0; vector<Hash> hashes(m); for (int i = 0; i < n; i++) { int k; in >> k; auto& school = schools[i]; for (int j = 0; j < k; j++) { int id; in >> id; --id; school.push_back(id); } sort(school.begin(), school.end()); classes.clear(); int l = 0; while (l < k) { int id = school[l], cnt = 0; while (l < k && school[l] == id) { ++l; ++cnt; } classes.push_back(Class{id, cnt}); } sort(classes.begin(), classes.end(), [](Class lhs, Class rhs) { return lhs.cnt < rhs.cnt; }); l = 0; while (l < classes.size()) { ++timer; int cnt = classes[l].cnt; while (l < classes.size() && classes[l].cnt == cnt) { int id = classes[l].id; ++l; hashes[id].update(timer); } } } map<Hash, int> was; int64_t result = 1; int64_t MOD = (1000000000 + 7); for (auto hash : hashes) { ++was[hash]; result = (result * was[hash]) % MOD; } out << result << n ; } }; int main() { std::ios_base::sync_with_stdio(false); TaskC solver; std::istream& in(std::cin); std::ostream& out(std::cout); in.tie(0); out << std::fixed; out.precision(20); solver.solve(in, out); return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:42 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_0/zynq_design_1_axi_bram_ctrl_0_0_stub.v
// Design : zynq_design_1_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
module zynq_design_1_axi_bram_ctrl_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a,
bram_wrdata_a, bram_rddata_a, bram_rst_b, bram_clk_b, bram_en_b, bram_we_b, bram_addr_b,
bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[11:0],s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [11:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// AutoFIFOPopControl for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: Auto FIFO pop controller
// Module Name: AutoFIFOPopControl
// File Name: AutoFIFOPopControl.v
//
// Version: v1.0.0
//
// Description: Automatical FIFO data pop control
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AutoFIFOPopControl
(
iClock ,
iReset ,
oPopSignal ,
iEmpty ,
oValid ,
iReady
);
input iClock ;
input iReset ;
output oPopSignal ;
input iEmpty ;
output oValid ;
input iReady ;
reg rValid ;
assign oPopSignal = (!iEmpty && (!rValid || iReady));
assign oValid = rValid;
always @ (posedge iClock)
if (iReset)
rValid <= 1'b0;
else
if ((!rValid || iReady))
rValid <= oPopSignal;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, t; int dp[21][5][11][11][2]; int solve(int pos, int h, int mn, int mx, bool w) { if (mn > t - 1 || mx > t) return 0; if (pos == n) return mx == t && mn == t - 1; int &ref = dp[pos][h][mn][mx][w]; if (ref != -1) return ref; ref = 0; for (int i = 1; i < 5; ++i) { if (i == h) continue; bool wp = i > h; if (!pos) ref += solve(pos + 1, i, mn, mx, w); else if (pos == 1) ref += solve(pos + 1, i, mn, mx, wp); else ref += solve(pos + 1, i, mn + (!w & wp), mx + (w & !wp), wp); } return ref; } int main() { scanf( %d %d , &n, &t); memset(dp, -1, sizeof(dp)); int sol = solve(0, 0, 0, 0, 0); printf( %d n , sol); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<long long> vec(n + 1); for (int i = 1; i <= n; i++) cin >> vec[i]; vector<long long> a; for (int i = 1; i < n; i++) { if (i & 1) a.push_back(abs(vec[i] - vec[i + 1])); else a.push_back(-1 * abs(vec[i] - vec[i + 1])); } vector<long long> dp((int)a.size()); dp[0] = a[0]; long long res = dp[0]; for (int i = 1; i < dp.size(); i++) { dp[i] = max(a[i], dp[i - 1] + a[i]); res = max(res, dp[i]); } dp.clear(); a.clear(); for (int i = 1; i < n; i++) { if (!(i & 1)) a.push_back(abs(vec[i] - vec[i + 1])); else a.push_back(-1 * abs(vec[i] - vec[i + 1])); } dp = vector<long long>((int)a.size()); dp[0] = a[0]; long long res2 = dp[0]; for (int i = 1; i < dp.size(); i++) { dp[i] = max(a[i], dp[i - 1] + a[i]); res2 = max(res2, dp[i]); } cout << max(res, res2) << n ; return 0; } |
// DEFINES
`define BITS 8 // Bit width of the operands
`define B2TS 16 // Bit width of the operands
`define SWITCH 0 // No available documentation provides for macros without values so we use 0
`define NEST 0
module bm_base_multiply(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out2,
out3,
out4,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [`B2TS-1:0] out2;
output [14:0] out3;
output [14:0] out4;
reg [`B2TS-1:0] out0;
wire [`B2TS-1:0] out1;
reg [`B2TS-1:0] out2;
reg [14:0] out3;
wire [14:0] out4;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= a_in * b_in;
out2 <= temp_a & temp_b;
out3 <= e_in * f_in;
end
assign out1 = c_in * d_in;
assign out4 = f_in * e_in;
endmodule
`ifdef SWITCH
`include "ifndef_else_module_b.v"
`ifndef NEST
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock)
begin
out <= a_in & b_in;
end
endmodule
`else
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock)
begin
out <= a_in | b_in;
end
endmodule
`endif
`endif
|
/*
* The nice thing about defines that are not possible with parameters is that
* you can pull defines to an external file and have all the defines in one
* place. This can be accomplished with parameters and UCF files but that
* would be vendor specific
*/
`define FX3_READ_START_LATENCY 1
`define FX3_WRITE_FULL_LATENCY 4
`include "project_include.v"
module fx3_bus # (
parameter ADDRESS_WIDTH = 8 //128 coincides with the maximum DMA
//packet size for USB 2.0
//256 coincides with the maximum DMA
//packet size for USB 3.0 since the 512
//will work for both then the FIFOs will
//be sized for this
)(
input clk,
input rst,
//Phy Interface
inout [31:0] io_data,
output o_oe_n,
output o_we_n,
output o_re_n,
output o_pkt_end_n,
input i_in_ch0_rdy,
input i_in_ch1_rdy,
input i_out_ch0_rdy,
input i_out_ch1_rdy,
output [1:0] o_socket_addr,
//Master Interface
input i_master_ready,
output [7:0] o_command,
output [7:0] o_flag,
output [31:0] o_rw_count,
output [31:0] o_address,
output o_command_rdy_stb,
input [7:0] i_status,
input [31:0] i_read_size,
input i_status_rdy_stb,
input [31:0] i_address, //Calculated end address, this can be
//used to verify that the mem was
//calculated correctly
//Write side FIFO interface
output o_wpath_ready,
input i_wpath_activate,
output [23:0] o_wpath_packet_size,
output [31:0] o_wpath_data,
input i_wpath_strobe,
//Read side FIFO interface
output [1:0] o_rpath_ready,
input [1:0] i_rpath_activate,
output [23:0] o_rpath_size,
input [31:0] i_rpath_data,
input i_rpath_strobe
);
//Local Parameters
//Registers/Wires
wire w_output_enable;
wire w_read_enable;
wire w_write_enable;
wire w_packet_end;
wire [31:0] w_in_data;
wire [31:0] w_out_data;
wire w_data_valid;
wire [23:0] w_packet_size;
wire w_read_flow_cntrl;
//In Path Control
wire w_in_path_enable;
wire w_in_path_busy;
wire w_in_path_finished;
//In Command Path
wire w_in_path_cmd_enable;
wire w_in_path_cmd_busy;
wire w_in_path_cmd_finished;
//Out Path Control
wire w_out_path_ready;
wire w_out_path_enable;
wire w_out_path_busy;
wire w_out_path_finished;
//Submodules
//Data From FX3 to FPGA
fx3_bus_in_path in_path(
.clk (clk ),
.rst (rst ),
//Control Signals
.i_packet_size (w_packet_size ),
.i_read_flow_cntrl (w_read_flow_cntrl ),
//FX3 Interface
.o_output_enable (w_output_enable ),
.o_read_enable (w_read_enable ),
//When high w_in_data is valid
.o_data_valid (w_data_valid ),
.i_in_path_enable (w_in_path_enable ),
.o_in_path_busy (w_in_path_busy ),
.o_in_path_finished (w_in_path_finished )
);
//Data from in_path to command reader
fx3_bus_in_command in_cmd(
.clk (clk ),
.rst (rst ),
.o_read_flow_cntrl (w_read_flow_cntrl ),
//Control
.i_in_path_cmd_enable (w_in_path_cmd_enable ),
.o_in_path_cmd_busy (w_in_path_cmd_busy ),
.o_in_path_cmd_finished (w_in_path_cmd_finished ),
//Data
.i_data (w_in_data ),
//Data Valid Flag
.i_data_valid (w_data_valid ),
//Master Interface
.o_command (o_command ),
.o_flag (o_flag ),
.o_rw_count (o_rw_count ),
.o_address (o_address ),
.o_command_rdy_stb (o_command_rdy_stb ),
//Write side FIFO interface
.o_in_ready (o_wpath_ready ),
.i_in_activate (i_wpath_activate ),
.o_in_packet_size (o_wpath_packet_size ),
.o_in_data (o_wpath_data ),
.i_in_strobe (i_wpath_strobe )
);
//Data from Master to The host
fx3_bus_out_path out_path(
.clk (clk ),
.rst (rst ),
//Control
.o_out_path_ready (w_out_path_ready ),
.i_out_path_enable (w_out_path_enable ),
.o_out_path_busy (w_out_path_busy ),
.o_out_path_finished (w_out_path_finished ),
.i_dma_buf_ready (w_out_dma_buf_ready ),
.o_dma_buf_finished (w_out_dma_buf_finished ),
//Packet size
.i_packet_size (w_packet_size ),
.i_status_rdy_stb (i_status_rdy_stb ),
.i_read_size (i_read_size ),
//FX3 Interface
.o_write_enable (w_write_enable ),
.o_packet_end (w_packet_end ),
.o_data (w_out_data ),
//FIFO in path
.o_rpath_ready (o_rpath_ready ),
.i_rpath_activate (i_rpath_activate ),
.o_rpath_size (o_rpath_size ),
.i_rpath_data (i_rpath_data ),
.i_rpath_strobe (i_rpath_strobe )
);
fx3_bus_controller controller(
.clk (clk ),
.rst (rst ),
//FX3 Parallel Interface
.i_in_ch0_rdy (i_in_ch0_rdy ),
.i_in_ch1_rdy (i_in_ch1_rdy ),
.i_out_ch0_rdy (i_out_ch0_rdy ),
.i_out_ch1_rdy (i_out_ch1_rdy ),
.o_socket_addr (o_socket_addr ),
//Incomming Data
.i_master_rdy (i_master_ready ),
//Outgoing Flags/Feedback
.o_in_path_enable (w_in_path_enable ),
.i_in_path_busy (w_in_path_busy ),
.i_in_path_finished (w_in_path_finished ),
//Command Path
.o_in_path_cmd_enable (w_in_path_cmd_enable ),
.i_in_path_cmd_busy (w_in_path_cmd_busy ),
.i_in_path_cmd_finished (w_in_path_cmd_finished ),
//Master Interface
//Output Path
.i_out_path_ready (w_out_path_ready ),
.o_out_path_enable (w_out_path_enable ),
.i_out_path_busy (w_out_path_busy ),
.i_out_path_finished (w_out_path_finished ),
.o_out_dma_buf_ready (w_out_dma_buf_ready ),
.i_out_dma_buf_finished (w_out_dma_buf_finished )
);
//Asynchronous Logic
assign o_oe_n = !w_output_enable;
assign o_re_n = !w_read_enable;
assign o_we_n = !w_write_enable;
assign o_pkt_end_n = !w_packet_end;
assign io_data = (w_output_enable) ? 32'hZZZZZZZZ : w_out_data;
assign w_in_data = (w_data_valid) ? io_data : 32'h00000000;
//XXX: NOTE THIS SHOULD BE ADJUSTABLE FROM THE SPEED DETECT MODULE
assign w_packet_size = 24'h80;
//Synchronous Logic
endmodule
|
#include <bits/stdc++.h> using namespace std; void populate(string& s, char c, int n) { for (int i = 0; i < n; ++i) s[s.find_first_of( ? )] = c; } int main() { ios::sync_with_stdio(0); int n; cin >> n; string s; cin >> s; auto na = count(s.begin(), s.end(), A ); auto nc = count(s.begin(), s.end(), C ); auto ng = count(s.begin(), s.end(), G ); auto nt = count(s.begin(), s.end(), T ); auto nq = count(s.begin(), s.end(), ? ); auto m = max(na, max(nc, (max(ng, nt)))); auto da = m - na; auto dc = m - nc; auto dg = m - ng; auto dt = m - nt; if (nq < da + dc + dg + dt) { cout << === << endl; } else if ((nq - (da + dc + dg + dt)) % 4 != 0) { cout << === << endl; } else { populate(s, A , da); populate(s, C , dc); populate(s, G , dg); populate(s, T , dt); for (int i = 0; i < (nq - (da + dc + dg + dt)); i += 4) { populate(s, A , 1); populate(s, C , 1); populate(s, G , 1); populate(s, T , 1); } cout << s << endl; } } |
#include <bits/stdc++.h> using namespace std; #define all(cont) cont.begin(), cont.end() #define rall(cont) cont.end(), cont.begin() #define FOREACH(it, l) for (auto it = l.begin(); it != l.end(); it++) #define IN(A, B, C) assert(B <= A && A <= C) #define SORT(v) sort(v.begin(), v.end()) #define MP make_pair #define PB push_back #define INF (int)1e9 #define EPS 1e-9 #define PI 3.1415926535897932384626433832795 #define MOD 1000000007 const double pi = acos(-1.0); typedef long int int32; typedef unsigned long int uint32; typedef long long int int64; typedef unsigned long long int uint64; const int N = 1e5 + 5; void solve() { int64 n, q, l, r; cin>>n>>q; string s; cin>>s; vector<int64> v, v1(n); while(n--){ v.PB(s[s.size()-n-1]-96); } partial_sum(v.begin(), v.end(), v1.begin()); while(q--){ cin>>l>>r; cout<<v1[r-1]-v1[l-1]+v[l-1]<< n ; } } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; int v[MAXN], l[MAXN], r[MAXN]; int ST[4 * MAXN]; int L[4 * MAXN]; int n; void _update(int node, int lo, int hi, int i, int j, int val) { if (L[node]) { ST[node] = max(ST[node], L[node]); if (hi != lo) { L[2 * node] = max(L[node], L[2 * node]); L[2 * node + 1] = max(L[node], L[2 * node + 1]); } L[node] = 0; } if (lo > j || hi < i) return; if (lo >= i && hi <= j) { ST[node] = max(ST[node], val); if (hi != lo) { L[2 * node] = max(val, L[2 * node]); L[2 * node + 1] = max(val, L[2 * node + 1]); } return; } int mid = (lo + hi) / 2; _update(2 * node, lo, mid, i, j, val); _update(2 * node + 1, mid + 1, hi, i, j, val); ST[node] = max(ST[2 * node], ST[2 * node + 1]); } int _query(int node, int l, int r, int i, int j) { if (L[node]) { ST[node] = max(ST[node], L[node]); L[2 * node] = max(L[2 * node], L[node]); L[2 * node + 1] = max(L[2 * node + 1], L[node]); L[node] = 0; } if (r < i || l > j) return -1; if (l >= i && r <= j) return ST[node]; int mid = (l + r) / 2; int p1 = _query(2 * node, l, mid, i, j); int p2 = _query(2 * node + 1, mid + 1, r, i, j); return max(p1, p2); } int query(int i, int j) { return _query(1, 0, n, i, j); } void update(int i, int j, int val) { _update(1, 0, n, i, j, val); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &v[i]); l[0] = -1; for (int i = 1; i < n; i++) { l[i] = i - 1; while (v[l[i]] >= v[i] && l[i] != -1) l[i] = l[l[i]]; } r[n - 1] = -1; for (int i = n - 2; i >= 0; i--) { r[i] = i + 1; while (v[r[i]] >= v[i] && r[i] != -1) { r[i] = r[r[i]]; } } for (int i = 0; i < n; i++) { int ri = r[i], li = l[i]; if (ri == -1) ri = n; if (li == -1) li = -1; int segment_length = (ri - 1) - (li + 1) + 1; update(1, segment_length, v[i]); } bool first = true; for (int i = 1; i <= n; i++) { if (first) first = false; else printf( ); printf( %d , query(i, i)); } printf( n ); return 0; } |
#include <bits/stdc++.h> int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int n; std::cin >> n; std::vector<std::vector<int>> a(n, std::vector<int>(n)); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { a[i][j] = 4 * (i % (n / 2) * (n / 2) + j % (n / 2)) + i / (n / 2) * 2 + j / (n / 2); } } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { std::cout << a[i][j] << ; } std::cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> adj[n], in[n]; int ot[n]; for (int i = 0; i < n; i++) ot[i] = 0; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; y--; adj[x].push_back(y); in[y].push_back(x); ot[x]++; } int vis[n]; for (int i = 0; i < n; i++) { vis[i] = 0; } int st, en; cin >> st >> en; st--; en--; deque<int> q; int dp[n]; for (int i = 0; i < n; i++) dp[i] = 10000000; dp[en] = 0; q.push_back(en); while (!q.empty()) { int u = q.front(); q.pop_front(); if (vis[u] == 1) continue; vis[u] = 1; for (int i = 0; i < in[u].size(); i++) { int v = in[u][i]; ot[v]--; if (ot[v] == 0) { if (dp[v] > dp[u]) { dp[v] = dp[u]; q.push_front(v); } } else { if (dp[v] > dp[u] + 1) { dp[v] = dp[u] + 1; q.push_back(v); } } } } if (dp[st] != 10000000) cout << dp[st]; else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> sieve(long long n) { long long *arr = new long long[n + 1](); vector<long long> vect; for (long long i = 2; i <= n; i++) if (arr[i] == 0) { vect.push_back(i); for (long long j = 2 * i; j <= n; j += i) arr[j] = 1; } return vect; } long long binpow(long long a, long long b, long long m) { a = a % m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } class cmp { public: bool operator()(pair<long long, long long> &a, pair<long long, long long> &b) { if (a.second == b.second) return a.first < b.first; else return a.second < b.second; } }; signed main() { long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; vector<long long> v(n); for (long long i = 0; i < n; i++) cin >> v[i]; long long x = k; sort(v.begin(), v.end()); long long ans = 0; k *= 2; long long j = n - 1; vector<long long> vec; while (k--) { vec.push_back(v[j]); j--; } sort(vec.begin(), vec.end()); for (long long i = 0; i < vec.size() / 2; i++) { ans += (vec[i] / vec[i + x]); } for (long long i = 0; i <= j; i++) ans += v[i]; cout << ans << n ; ; } } |
#include <bits/stdc++.h> using namespace std; void solve(const int &test_id) { int n, p, k; cin >> n >> p >> k; vector<pair<long long, int> > aud(n); for (int i = 0; i < n; i++) cin >> aud[i].first, aud[i].second = i; sort(aud.rbegin(), aud.rend()); vector<int> twos(p + 1); for (int i = 0; i < p + 1; i++) twos[i] = (1 << i); vector<vector<long long> > skill(n, vector<long long>(twos[p])); for (int i = 0; i < n; i++) for (int j = 0; j < p; j++) cin >> skill[i][j]; vector<vector<long long> > dp(n + 1, vector<long long>(twos[p])); for (int i = 1; i < n + 1; i++) { for (int j = 0; j < twos[p]; j++) { int curr_aud_count = i - 1 - __builtin_popcount(j); if (curr_aud_count < k && curr_aud_count > -1) dp[i][j] = max(dp[i][j], dp[i - 1][j] + aud[i - 1].first); else dp[i][j] = max(dp[i][j], dp[i - 1][j]); for (int k = 0; k < p; k++) if (j & twos[k]) dp[i][j] = max(dp[i][j], dp[i - 1][j ^ twos[k]] + skill[aud[i - 1].second][k]); } } cout << dp[n][twos[p] - 1] << endl; } void solve_cases() { int test_cases = 1; for (int i = 1; i <= test_cases; i++) solve(i); } void fast_io() { ios::sync_with_stdio(false); srand(time(NULL)); cin.tie(0); cout.tie(0); cout << fixed << setprecision(15); cerr << fixed << setprecision(15); } int main() { fast_io(); solve_cases(); return EXIT_SUCCESS; } |
#include <bits/stdc++.h> int luckyDigits(long long int *a) { int count1 = 0, dig; while (*a != 0) { dig = *a % 10; if (dig == 4 || dig == 7) { count1++; } *a = *a / 10; } return count1; } int main() { long long int i, j, k, n, a, count = 0; scanf( %lld%lld , &n, &k); for (i = 0; i < n; i++) { a = 0; scanf( %lld , &a); if (luckyDigits(&a) <= k) { count++; } } printf( %lld , count); } |
// $Id: c_wf_alloc_rep.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// wavefront allocator variant which replicates the entire allocation logic for
// the different priorities and selects the result from the appropriate one
module c_wf_alloc_rep
(clk, reset, update, req, gnt);
`include "c_functions.v"
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// try to recover from errors
parameter error_recovery = 0; // FIXME: actually implement this
parameter reset_type = `RESET_TYPE_ASYNC;
// width of priority selector
localparam prio_width = clogb(num_ports);
input clk;
input reset;
// update arbitration priorities
input update;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
wire [0:prio_width-1] prio_next, prio_q;
c_incr
#(.width(prio_width),
.min_value(0),
.max_value(num_ports-1))
prio_incr
(.data_in(prio_q),
.data_out(prio_next));
wire [0:prio_width-1] prio_s;
assign prio_s = update ? prio_next : prio_q;
c_dff
#(.width(prio_width),
.reset_type(reset_type))
prioq
(.clk(clk),
.reset(reset),
.d(prio_s),
.q(prio_q));
wire [0:num_ports*num_ports*num_ports-1] gnt_by_prio;
generate
genvar prio;
for(prio = 0; prio < num_ports; prio = prio + 1)
begin:prios
wire [0:num_ports*num_ports-1] req_int;
wire [0:num_ports*num_ports-1] gnt_int;
wire [0:num_ports*num_ports-1] y;
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
wire [0:num_ports-1] x_in, y_in;
wire [0:num_ports] x_out, y_out;
wire [0:num_ports-1] req_in;
wire [0:num_ports-1] gnt_out;
assign x_in = x_out[0:num_ports-1];
assign y_in
= y[((row+num_ports)%num_ports)*num_ports:
((row+num_ports)%num_ports+1)*num_ports-1];
assign req_in = req_int[row*num_ports:
(row+1)*num_ports-1];
assign x_out = {1'b1, (~y_in | ~req_in) & x_in};
assign y_out = {1'b1, (~x_in | ~req_in) & y_in};
assign gnt_out = req_in & x_in & y_in;
assign y[((row+num_ports+1)%num_ports)*num_ports:
((row+num_ports+1)%num_ports+1)*num_ports-1]
= y_out[0:num_ports-1];
assign gnt_int[row*num_ports:(row+1)*num_ports-1]
= gnt_out;
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
assign req_int[row*num_ports+col]
= req[((prio+row)%num_ports)*num_ports +
(num_ports-row+col)%num_ports];
assign gnt_by_prio[((prio+row)%num_ports)*
num_ports +
(num_ports-row+col)%num_ports +
prio*num_ports*num_ports]
= gnt_int[row*num_ports+col];
end
end
end
endgenerate
assign gnt = gnt_by_prio[prio_q*num_ports*num_ports +: num_ports*num_ports];
endmodule
|
#include <bits/stdc++.h> using namespace std; void Freopen() { freopen( title .in , r , stdin); freopen( title .out , w , stdout); } int read() { int g = 0, f = 1; char ch = getchar(); while (ch < 0 || 9 < ch) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { g = g * 10 + ch - 0 ; ch = getchar(); } return g * f; } const int N = 5e5 + 5; const int mod = 1e9 + 7; int st[N][20], dep[N], vis[N], ta, tb, top, sa[N], sb[N], sta[N]; vector<int> G[N], F[N], R[N], C[N], size[N]; int n, fir[N], las[N], fac[N], du[N]; unordered_map<int, int> M[N]; void dfs(int x, int fa) { st[x][0] = fa; dep[x] = dep[fa] + 1; for (int i = (1); i <= (19); i++) if (st[x][i - 1]) st[x][i] = st[st[x][i - 1]][i - 1]; else break; for (auto y : G[x]) if (y ^ fa) dfs(y, x); } int Lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); for (int i = (19); i >= (0); i--) if (dep[st[x][i]] >= dep[y]) x = st[x][i]; if (x == y) return x; for (int i = (19); i >= (0); i--) if (st[x][i] != st[y][i]) x = st[x][i], y = st[y][i]; return st[x][0]; } int get(int x, vector<int>& f) { return f[x] == x ? x : f[x] = get(f[x], f); } bool Merge(int x, int y, vector<int>& f, vector<int>& size, vector<int>& ru, vector<int>& cu) { cu[x]++, ru[y]++; if (cu[x] > 1 || ru[y] > 1) return false; int fx = get(x, f), fy = get(y, f); if (fx == fy) return false; size[fx] += size[fy]; f[fy] = fx; return true; } signed main() { n = read(); memset(fir, -1, sizeof(fir)); memset(las, -1, sizeof(las)); if (n == 1) return cout << 1, signed(); fac[0] = 1; for (int i = (1); i <= (n); i++) fac[i] = 1ll * fac[i - 1] * i % mod; for (int i = (1); i <= (n - 1); i++) { int x = read(), y = read(); G[x].push_back(y), G[y].push_back(x); M[x][y] = G[x].size() - 1, M[y][x] = G[y].size() - 1; F[x].push_back(G[x].size() - 1), F[y].push_back(G[y].size() - 1); size[x].push_back(1), size[y].push_back(1); R[x].push_back(0), R[y].push_back(0); C[x].push_back(0), C[y].push_back(0); du[x]++, du[y]++; } dfs(1, 0); for (int x = (1); x <= (n); x++) { int y = read(); if (y == 0) continue; int anc = Lca(x, y); if (x == y) return cout << 0, signed(); if (vis[y]) return cout << 0, signed(); vis[y] = 1; ta = tb = top = 0; for (int t = x; t != anc; t = st[t][0]) sa[++ta] = t; for (int t = y; t != anc; t = st[t][0]) sb[++tb] = t; for (int i = (1); i <= (tb); i++) sta[++top] = sb[i]; sta[++top] = anc; for (int i = (ta); i >= (1); i--) sta[++top] = sa[i]; for (int i = (2); i <= (top - 1); i++) { int ipre = M[sta[i]][sta[i - 1]], isuf = M[sta[i]][sta[i + 1]]; if (!Merge(ipre, isuf, F[sta[i]], size[sta[i]], R[sta[i]], C[sta[i]])) return cout << 0, signed(); } fir[sta[1]] = M[sta[1]][sta[2]]; las[sta[top]] = M[sta[top]][sta[top - 1]]; for (int i = (1); i <= (top); i++) { if (fir[sta[i]] >= 0 && las[sta[i]] >= 0 && get(fir[sta[i]], F[sta[i]]) == get(las[sta[i]], F[sta[i]]) && size[sta[i]][get(fir[sta[i]], F[sta[i]])] != du[sta[i]]) return cout << 0, signed(); } } int ans = 1; for (int i = (1); i <= (n); i++) { for (int j = (0); j <= (du[i] - 1); j++) vis[j] = 0; int cnt = 0; for (int j = (0); j <= (du[i] - 1); j++) { int x = get(j, F[i]); if (vis[x]) continue; vis[x] = 1; cnt++; } if (fir[i] >= 0) cnt--; if (las[i] >= 0) cnt--; if (fir[i] >= 0 && las[i] >= 0 && get(fir[i], F[i]) == get(las[i], F[i])) cnt++; ans = 1ll * ans * fac[cnt] % mod; } return cout << ans, signed(); } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5, M = 2e4 + 5, inf = 0x3f3f3f3f, mod = 1e9 + 7; void Print(int *a, int n) { for (int i = 1; i < n; i++) printf( %d , a[i]); printf( %d n , a[n]); } int e[N], nt[N]; void Gnt(string a, int *nt) { int k = 0, p = 0, n = (int)a.size(); nt[0] = n; for (int i = 1; i < n; i++) { if (i + nt[i - k] < p) nt[i] = nt[i - k]; else { if (i >= p) p = i; while (p < n && a[p] == a[p - i]) p++; nt[i] = p - i; k = i; } } } void Exd(string a, string b, int *e, int *nt) { int k = 0, p = 0, n = (int)a.size(), m = (int)b.size(); Gnt(b, nt); for (int i = 0; i < n; i++) { if (i + nt[i - k] < p) e[i] = nt[i - k]; else { if (i >= p) p = i; while (p < n && p - i < m && a[p] == b[p - i]) p++; e[i] = p - i; k = i; } } } int cycle(string a) { int n = a.size(); Gnt(a, nt); int t = n; for (int i = 1; i < n; i++) if (i + nt[i] == n) { t = n % i ? n : i; break; } return t; } string a, b; int k, dp[N][2]; int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> a >> b >> k; dp[0][a != b] = 1; int n = (int)a.size(); a = a + a; Exd(a, b, e, nt); int x = 0, len = (int)b.size(); for (int i = 0; i < n; i++) { if (e[i] >= len) x++; } int y = n - x; for (int i = 1; i <= k; i++) { dp[i][0] = (1LL * x * dp[i - 1][1] + 1LL * (x - 1) * dp[i - 1][0]) % mod; dp[i][1] = (1LL * y * dp[i - 1][0] + 1LL * (y - 1) * dp[i - 1][1]) % mod; } printf( %d n , dp[k][0]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; for (int i = 0; i < q; i++) { int n; cin >> n; int gnum; while (1) { gnum = n; while (gnum > 0) { if (gnum % 3 == 2) { break; } gnum = gnum / 3; } if (gnum == 1 || gnum == 0) { break; } n++; } cout << n << endl; } return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casez/endcase w/ z in expr no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 )
casez (val1)
3'b000: result = 0;
3'b010: result = 1 ;
3'b110: result = 2;
endcase
initial
begin
error = 0;
val1 = 3'b0z0 ;
if(result !=0)
begin
$display("FAILED casez 3.10B - case (expr) lab1: ");
error = 1;
end
val1 = 3'b01z;
if(result !=1)
begin
$display("FAILED casez 3.10B - case (expr) lab2: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b011
if(result !=1)
begin
$display("FAILED casez 3.10B - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_gxb_gige_inst.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_gxb_gige_phyip_inst.v,v $
//
// $Revision: #23 $
// $Date: 2010/09/05 $
// Check in by : $Author: sxsaw $
// Author : Siew Kong NG
//
// Project : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description :
//
// Instantiation for Alt2gxb, Alt4gxb
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module altera_tse_gxb_gige_phyip_inst (
phy_mgmt_clk,
phy_mgmt_clk_reset,
phy_mgmt_address,
phy_mgmt_read,
phy_mgmt_readdata,
phy_mgmt_waitrequest,
phy_mgmt_write,
phy_mgmt_writedata,
tx_ready,
rx_ready,
pll_ref_clk,
pll_locked,
tx_serial_data,
rx_serial_data,
rx_runningdisp,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_syncstatus,
tx_clkout,
rx_clkout,
tx_parallel_data,
tx_datak,
rx_parallel_data,
rx_datak,
rx_rlv,
rx_recovclkout,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
reconfig_togxb,
reconfig_fromgxb
);
parameter DEVICE_FAMILY = "STRATIXV"; // The device family the the core is targetted for.
parameter ENABLE_ALT_RECONFIG = 0;
parameter ENABLE_SGMII = 1; // Use to determine rate match FIFO in ALTGX GIGE mode
input phy_mgmt_clk;
input phy_mgmt_clk_reset;
input [8:0]phy_mgmt_address;
input phy_mgmt_read;
output [31:0]phy_mgmt_readdata;
output phy_mgmt_waitrequest;
input phy_mgmt_write;
input [31:0]phy_mgmt_writedata;
output tx_ready;
output rx_ready;
input pll_ref_clk;
output pll_locked;
output tx_serial_data;
input rx_serial_data;
output rx_runningdisp;
output rx_disperr;
output rx_errdetect;
output rx_patterndetect;
output rx_syncstatus;
output tx_clkout;
output rx_clkout;
input [7:0] tx_parallel_data;
input tx_datak;
output [7:0] rx_parallel_data;
output rx_datak;
output rx_rlv;
output rx_recovclkout;
output rx_rmfifodatadeleted;
output rx_rmfifodatainserted;
input [139:0]reconfig_togxb;
output [91:0]reconfig_fromgxb;
wire [91:0] reconfig_fromgxb;
wire [139:0] wire_reconfig_togxb;
(* altera_attribute = "-name MESSAGE_DISABLE 10036" *)
wire [91:0] wire_reconfig_fromgxb;
generate if (ENABLE_ALT_RECONFIG == 0)
begin
assign wire_reconfig_togxb = 140'd0;
assign reconfig_fromgxb = 92'd0;
end
else
begin
assign wire_reconfig_togxb = reconfig_togxb;
assign reconfig_fromgxb = wire_reconfig_fromgxb;
end
endgenerate
generate if (ENABLE_SGMII == 0)
begin
altera_tse_phyip_gxb the_altera_tse_phyip_gxb (
.phy_mgmt_clk(phy_mgmt_clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset(phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
.phy_mgmt_read(phy_mgmt_read), // .read
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
.phy_mgmt_write(phy_mgmt_write), // .write
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
.tx_ready(tx_ready), // tx_ready.export
.rx_ready(rx_ready), // rx_ready.export
.pll_ref_clk(pll_ref_clk), // pll_ref_clk.clk
.pll_locked(pll_locked), // pll_locked.export
.tx_serial_data(tx_serial_data), // tx_serial_data.export
.rx_serial_data(rx_serial_data), // rx_serial_data.export
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
.rx_disperr(rx_disperr), // rx_disperr.export
.rx_errdetect(rx_errdetect), // rx_errdetect.export
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
.tx_clkout(tx_clkout), // tx_clkout.clk
.rx_clkout(rx_clkout), // rx_clkout.clk
.tx_parallel_data(tx_parallel_data), // tx_parallel_data.data
.tx_datak(tx_datak), // tx_datak.data
.rx_parallel_data(rx_parallel_data), // rx_parallel_data.data
.rx_datak(rx_datak), // rx_datak.data
.rx_rlv(rx_rlv),
.rx_recovered_clk(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.reconfig_to_xcvr(wire_reconfig_togxb),
.reconfig_from_xcvr(wire_reconfig_fromgxb)
);
end
endgenerate
generate if (ENABLE_SGMII == 1)
begin
altera_tse_phyip_gxb_wo_rmfifo the_altera_tse_phyip_gxb_wo_rmfifo (
.phy_mgmt_clk(phy_mgmt_clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset(phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
.phy_mgmt_read(phy_mgmt_read), // .read
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
.phy_mgmt_write(phy_mgmt_write), // .write
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
.tx_ready(tx_ready), // tx_ready.export
.rx_ready(rx_ready), // rx_ready.export
.pll_ref_clk(pll_ref_clk), // pll_ref_clk.clk
.pll_locked(pll_locked), // pll_locked.export
.tx_serial_data(tx_serial_data), // tx_serial_data.export
.rx_serial_data(rx_serial_data), // rx_serial_data.export
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
.rx_disperr(rx_disperr), // rx_disperr.export
.rx_errdetect(rx_errdetect), // rx_errdetect.export
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
.tx_clkout(tx_clkout), // tx_clkout.clk
.rx_clkout(rx_clkout), // rx_clkout.clk
.tx_parallel_data(tx_parallel_data), // tx_parallel_data.data
.tx_datak(tx_datak), // tx_datak.data
.rx_parallel_data(rx_parallel_data), // rx_parallel_data.data
.rx_datak(rx_datak), // rx_datak.data
.rx_rlv(rx_rlv),
.rx_recovered_clk(rx_recovclkout),
.reconfig_to_xcvr(wire_reconfig_togxb),
.reconfig_from_xcvr(wire_reconfig_fromgxb)
);
assign rx_rmfifodatadeleted = 1'b0;
assign rx_rmfifodatainserted = 1'b0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int poww(int a, int b) { for (int i = 0; i < b; i++) a *= a; return a; } int main() { int n, t; cin >> n; if (n < 10) { cout << n << endl; return 0; } long long i = 2; long long sum = 9; long long x = 10, v[] = {999999999, 99999999, 9999999, 999999, 99999, 9999, 999, 99, 9, 0, 0}; reverse(v, v + 11); for (int i = 10; i > 1; i--) { if (n - v[i] > 0) { sum += (n - v[i]) * i; n -= (n - v[i]); } } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, k, t, suan, d[1100002], f[1110000]; int main() { cin >> a >> b >> k >> t; int shu = k * 2 * t; d[shu] = 1; int y = d[0]; for (int i = 1; i <= t * 2; i++) { f[0] = y; for (int j = 1; j <= shu * 2 + k; j++) { f[j] = (f[j - 1] + d[j]) % 1000000007; } for (int j = 0; j <= k; j++) { d[j] = f[j + k]; } for (int j = k + 1; j <= shu * 2; j++) { d[j] = (f[j + k] - f[j - 1 - k] + 1000000007) % 1000000007; } } for (int i = shu - a + b + 1; i <= shu * 2; i++) { suan = (suan + d[i]) % 1000000007; } cout << suan; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_4_V
`define SKY130_FD_SC_HDLL__NOR3B_4_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_BLACKBOX_V
`define SKY130_FD_SC_HS__AND4B_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4b (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_SYMBOL_V
`define SKY130_FD_SC_LS__A41O_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a41o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const long long int N = 1000005; struct segmenttree { vector<long long int> st; void init(long long int _n) { st.clear(); st.resize(4 * _n); } void build(long long int l, long long int r, long long int node) { if (l == r) { return; } long long int mid = (l + r) / 2; build(l, mid, node * 2 + 1); build(mid + 1, r, node * 2 + 2); st[node] = max(st[2 * node + 1], st[2 * node + 2]); } void update(long long int l, long long int r, long long int indup, long long int val, long long int node) { if (l == r) { st[node] = val; return; } else { long long int mid = (l + r) / 2; if (indup >= l && indup <= mid) { update(l, mid, indup, val, node * 2 + 1); } else { update(mid + 1, r, indup, val, node * 2 + 2); } st[node] = max(st[2 * node + 1], st[2 * node + 2]); } } long long int query(long long int si, long long int se, long long int l, long long int r, long long int node) { if (se < l || si > r || l > r) { return INT_MIN; } if (si >= l && se <= r) { return st[node]; } long long int mid = (si + se) / 2; long long int q1 = query(si, mid, l, r, node * 2 + 1); long long int q2 = query(mid + 1, se, l, r, node * 2 + 2); return max(q1, q2); } }; segmenttree tree[N]; long long int sz[N], res[N], mx[N], n, m; vector<long long int> pos[N]; long long int give(long long int row, long long int pos) { long long int mn, mx, ret; if (pos < sz[row]) { mn = max(0ll, pos - (m - sz[row])), mx = pos; if ((m - 1) - pos >= sz[row]) ret = 0; else ret = INT_MIN; } else { pos = sz[row] - (m - pos); mn = pos, mx = max(sz[row] - 1, pos + (m - sz[row])); if (pos >= sz[row]) ret = INT_MIN; else ret = 0; } return max(ret, tree[row].query(0, sz[row] - 1, mn, mx, 0)); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); { long long int i, j, k, ans = 0, cnt = 0, sum = 0; cin >> n >> m; for (i = 0; i < n; i++) { cin >> sz[i]; tree[i].init(sz[i]); for (j = 0; j < sz[i]; j++) { long long int x; cin >> x; mx[i] = max(mx[i], x); tree[i].update(0, sz[i] - 1, j, x, 0); } for (j = 0; j < sz[i]; j++) pos[j].push_back(i); for (j = max(sz[i], (m - sz[i])); j < m; j++) pos[j].push_back(i); } for (i = 0; i < n; i++) { ans += mx[i]; } for (i = 0; i < m; i++) { res[i] = ans; for (auto x : pos[i]) { res[i] -= mx[x]; res[i] += give(x, i); } } for (i = 0; i < m; i++) { cout << res[i] << ; } } } |
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-8; const long double INF = 1e12; const long double PI = acos(-1); struct L : array<complex<long double>, 2> { L(const complex<long double>& a, const complex<long double>& b) { at(0) = a; at(1) = b; } L() {} }; namespace std { bool operator<(const complex<long double>& a, const complex<long double>& b) { return !(abs((a.real()) - (b.real())) < EPS) ? a.real() < b.real() : a.imag() + EPS < b.imag(); } bool operator==(const complex<long double>& a, const complex<long double>& b) { return abs(a - b) < EPS; } } // namespace std long double dot(complex<long double> a, complex<long double> b) { return (conj(a) * b).real(); } long double cross(complex<long double> a, complex<long double> b) { return (conj(a) * b).imag(); } bool intersectLP(const L& l, const complex<long double>& p) { return abs(cross(l[1] - p, l[0] - p)) < EPS; } bool strictItsLS(const L& l, const L& s) { return cross(l[1] - l[0], s[0] - l[0]) * cross(l[1] - l[0], s[1] - l[0]) < -EPS; } bool isParallel(const complex<long double>& a, const complex<long double>& b) { return abs(cross(a, b)) < EPS; } bool isParallel(const L& a, const L& b) { return isParallel(a[1] - a[0], b[1] - b[0]); } complex<long double> crosspointLL(const L& l, const L& m) { long double A = cross(l[1] - l[0], m[1] - m[0]); long double B = cross(l[1] - l[0], l[1] - m[0]); return m[0] + B / A * (m[1] - m[0]); } long double getarea(const vector<complex<long double> >& poly) { long double ret = 0; for (int i = 0; i < (int)poly.size(); i++) { ret += cross(poly[i], poly[(i + 1) % poly.size()]); } return ret * 0.5; } bool in_corner(const complex<long double>& p, const vector<complex<long double> >& v) { bool s1 = cross(v[1] - v[0], p - v[0]) > -EPS; bool s2 = cross(v[2] - v[1], p - v[1]) > -EPS; return (cross(v[1] - v[0], v[2] - v[0]) > -EPS) ? s1 and s2 : s1 or s2; } long double solve(vector<complex<long double> >& v, L cut) { int n = v.size(); complex<long double> cdir = cut[1] - cut[0]; vector<complex<long double> > cps; for (int i = 0; i < n; i++) { L edge(v[i], v[(i + 1) % n]); if (strictItsLS(cut, edge) and !isParallel(cut, edge)) { cps.push_back(crosspointLL(cut, edge)); } if (intersectLP(cut, v[i])) { vector<complex<long double> > p{v[(i - 1 + n) % n], v[i], v[(i + 1) % n]}; if (in_corner(p[1] + cdir, p) != in_corner(p[1] - cdir, p)) { cps.push_back(v[i]); } } } sort(cps.begin(), cps.end()); long double res = 0; for (int i = 0; i < (int)cps.size() - 1; i += 2) { res += abs(cps[i + 1] - cps[i]); } return res; } int main() { int n, m; cin >> n >> m; vector<complex<long double> > v(n); for (int i = 0; i < n; i++) { long double x, y; cin >> x >> y; v[i] = complex<long double>(x, y); } if (getarea(v) < 0) { reverse(v.begin(), v.end()); } cout << fixed << setprecision(10); for (int i = 0; i < m; i++) { long double xs, ys, xt, yt; cin >> xs >> ys >> xt >> yt; cout << solve(v, L(complex<long double>(xs, ys), complex<long double>(xt, yt))) << endl; } return 0; } |
/*
* CameraOneFrame architecture
*
* Copyright (c) 2014,
* Luca Maggiani <>,
* Scuola Superiore Sant'Anna (http://www.sssup.it) and
* Consorzio Nazionale Interuniversitario per le Telecomunicazioni
* (http://www.cnit.it).
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module matrix_prod(
clk_i,
reset_n_i,
sclr_i,
pix01_i,
pix10_i,
pix12_i,
pix21_i,
sin_i,
cos_i,
dv0_i,
dv1_i,
dv2_i,
data_o
);
parameter DATA_WIDTH = 8;
parameter COEF_WIDTH = 9;
input clk_i;
input reset_n_i;
input dv0_i;
input dv1_i;
input dv2_i;
input sclr_i;
input [DATA_WIDTH-1:0] pix01_i, pix10_i, pix12_i, pix21_i;
input [COEF_WIDTH-1:0] sin_i;
input [COEF_WIDTH-1:0] cos_i;
output [((COEF_WIDTH + DATA_WIDTH)+1):0] data_o;
/* Internal register definitions */
reg signed [DATA_WIDTH:0] tmpsin;
reg signed [DATA_WIDTH:0] tmpcos;
reg signed [(COEF_WIDTH + DATA_WIDTH):0] multsin;
reg signed [(COEF_WIDTH + DATA_WIDTH):0] multcos;
reg signed [((COEF_WIDTH + DATA_WIDTH)+1):0] finaladd;
//~ reg dv_d1, dv_d2;
/* Internal wire definitions */
wire signed [COEF_WIDTH-1:0] sin_wire;
wire signed [COEF_WIDTH-1:0] cos_wire;
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
tmpsin <= {(DATA_WIDTH+1){1'b0}};
else if (dv0_i)
tmpsin <= pix21_i - pix01_i;
else
tmpsin <= tmpsin;
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
tmpcos <= {(DATA_WIDTH+1){1'b0}};
else if (dv0_i)
tmpcos <= pix10_i - pix12_i;
else
tmpcos <= tmpcos;
//~ always@(posedge clk_i or negedge reset_n_i)
//~ if (reset_n_i == 0)
//~ begin
//~ dv_d1 <= 0;
//~ dv_d2 <= 0;
//~ end
//~ else if (dv_i)
//~ begin
//~ dv_d1 <= dv_i;
//~ dv_d2 <= dv_d1;
//~ end
assign sin_wire = sin_i;
assign cos_wire = cos_i;
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
begin
multsin <= {(COEF_WIDTH + DATA_WIDTH + 1){1'b0}};
multcos <= {(COEF_WIDTH + DATA_WIDTH + 1){1'b0}};
end
else if (dv1_i)
begin
multsin <= tmpsin * sin_wire;
multcos <= tmpcos * cos_wire;
end
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
begin
finaladd <= {((COEF_WIDTH + DATA_WIDTH)+2){1'b0}};
end
else if (dv2_i)
begin
finaladd <= multsin + multcos;
end
assign data_o = (finaladd > 0) ? finaladd : (~finaladd + 1'b1);
endmodule
|
// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: coincidence_counter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module coincidence_counter (
aclr,
clock,
cnt_en,
q);
input aclr;
input clock;
input cnt_en;
output [21:0] q;
wire [21:0] sub_wire0;
wire [21:0] q = sub_wire0[21:0];
lpm_counter LPM_COUNTER_component (
.aclr (aclr),
.clock (clock),
.cnt_en (cnt_en),
.q (sub_wire0),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.clk_en (1'b1),
.cout (),
.data ({22{1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.sset (1'b0),
.updown (1'b1));
defparam
LPM_COUNTER_component.lpm_direction = "UP",
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
LPM_COUNTER_component.lpm_width = 22;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "22"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "22"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: q 0 0 22 0 OUTPUT NODEFVAL "q[21..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: q 0 0 22 0 @q 0 0 22 0
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL coincidence_counter_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module displaysigned();
reg signed [7:0] foo;
reg [7:0] bar;
initial begin
foo = -8'sd2;
bar = foo;
$display("foo=%0d bar=%0d $signed(bar)=%0d",
foo, bar, $signed(bar));
$finish(0);
end
endmodule
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2011
//
// fetches video data for renderer
module video_fetch(
input wire clk, // 28 MHz clock
input wire cend, // general
input wire pre_cend, // synchronization
input wire vpix, // vertical window
input wire fetch_start, // fetching start and stop
input wire fetch_end, //
output reg fetch_sync, // 1 cycle after cend
input wire [15:0] video_data, // video data receiving from dram arbiter
input wire video_strobe, //
output reg video_go, // indicates need for data
output reg [63:0] pic_bits // picture bits -- data for renderer
// currently, video_fetch assigns that there are only 1/8 and 1/4
// bandwidth. !!needs correction for higher bandwidths!!
);
reg [3:0] fetch_sync_ctr; // generates fetch_sync to synchronize
// fetch cycles (each 16 dram cycles long)
// fetch_sync coincides with cend
reg [1:0] fetch_ptr; // pointer to fill pic_bits buffer
reg fetch_ptr_clr; // clears fetch_ptr
reg [15:0] fetch_data [0:3]; // stores data fetched from memory
// fetch window
always @(posedge clk)
if( fetch_start && vpix )
video_go <= 1'b1;
else if( fetch_end )
video_go <= 1'b0;
// fetch sync counter
always @(posedge clk) if( cend )
begin
if( fetch_start )
fetch_sync_ctr <= 0;
else
fetch_sync_ctr <= fetch_sync_ctr + 1;
end
// fetch sync signal
always @(posedge clk)
if( (fetch_sync_ctr==1) && pre_cend )
fetch_sync <= 1'b1;
else
fetch_sync <= 1'b0;
// fetch_ptr clear signal
always @(posedge clk)
if( (fetch_sync_ctr==0) && pre_cend )
fetch_ptr_clr <= 1'b1;
else
fetch_ptr_clr <= 1'b0;
// buffer fill pointer
always @(posedge clk)
if( fetch_ptr_clr )
fetch_ptr <= 0;
else if( video_strobe )
fetch_ptr <= fetch_ptr + 1;
// store fetched data
always @(posedge clk) if( video_strobe )
fetch_data[fetch_ptr] <= video_data;
// pass fetched data to renderer
always @(posedge clk) if( fetch_sync )
begin
pic_bits[ 7:0 ] <= fetch_data[0][15:8 ];
pic_bits[15:8 ] <= fetch_data[0][ 7:0 ];
pic_bits[23:16] <= fetch_data[1][15:8 ];
pic_bits[31:24] <= fetch_data[1][ 7:0 ];
pic_bits[39:32] <= fetch_data[2][15:8 ];
pic_bits[47:40] <= fetch_data[2][ 7:0 ];
pic_bits[55:48] <= fetch_data[3][15:8 ];
pic_bits[63:56] <= fetch_data[3][ 7:0 ];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvpwrvgnd (
VPWR,
VGND
);
// Module ports
input VPWR;
input VGND;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long read() { long long sign = 1, x = 0; char s = getchar(); while (s > 9 || s < 0 ) { if (s == - ) sign = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = (x << 3) + (x << 1) + s - 0 ; s = getchar(); } return x * sign; } void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x / 10) write(x / 10); putchar(x % 10 + 0 ); } int n, k; int a[(100 + 5)]; int main() { int kase; cin >> kase; while (kase--) { cin >> n; if (n == 1 || n == 2) { cout << 1 << endl; continue; } int ans = (n + 1) / 2; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100001]; int main() { ios::sync_with_stdio(0); int n, mn = 1e9; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; mn = min(mn, a[i]); } int last = -1; int ans = n + 1e1; for (int i = 1; i <= n; ++i) { if (a[i] == mn) { if (last != -1) { ans = min(ans, i - last); } last = i; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long power(long long a, long long b, long long m = mod) { long long x = 1; while (b) { if (b & 1) { x = 1ll * x * a % m; } a = 1ll * a * a % m; b /= 2; } return x; } const int N = 5e5 + 9; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tt; cin >> tt; while (tt--) { int n; cin >> n; vector<vector<int>> g(n + 1); map<pair<int, int>, vector<int>> gg; vector<vector<int>> a(n + 1, vector<int>(3)); map<pair<int, int>, int> ed1; for (int i = 1; i <= n - 2; i++) { for (int j = 0; j < 3; j++) { cin >> a[i][j]; } for (int j = 0; j < 3; j++) { int u = a[i][j]; int v = a[i][(j + 1) % 3]; if (u > v) swap(u, v); g[u].push_back(v); g[v].push_back(u); gg[{u, v}].push_back(i); ed1[{u, v}]++; } } vector<vector<int>> gp(n + 1); for (auto it : ed1) { if (it.second == 1) { int u = it.first.first, v = it.first.second; gp[u].push_back(v); gp[v].push_back(u); } } vector<int> poly; vector<int> vis(n + 1); map<pair<int, int>, int> ed; vis[1] = 1; poly.push_back(1); for (int i = 1;;) { int pi = i; for (int v : gp[i]) { if (vis[v] == 0) { vis[v] = 1; i = v; ed[{min(pi, i), max(pi, i)}]++; break; } } if (i == pi) { ed[{1, pi}]++; break; } poly.push_back(i); } vector<int> cnt(n + 2); for (int i : poly) cout << i << ; cout << n ; if (n == 3) { cout << 1 n ; continue; } function<pair<int, int>(int)> get_corner = [&](int i) { int cc = 0, tu; for (int j = 0; j < 3; j++) cnt[a[i][j]] = 0; for (int j = 0; j < 3; j++) { int u = a[i][j]; int v = a[i][(j + 1) % 3]; if (u > v) swap(u, v); if (ed.count({u, v})) { cc++; cnt[u]++; cnt[v]++; if (cnt[u] > cnt[v]) tu = u; else tu = v; } } return make_pair(tu, cc); }; int cur = 1; set<pair<int, int>> ss; for (int i = 1; i <= n - 2; i++) { auto r = get_corner(i); if (r.second == 2) { cur = i; ss.insert({-r.second, i}); } } while ((int)ss.size() > 1) { auto it = *ss.begin(); ss.erase(ss.begin()); cur = it.second; auto r = get_corner(cur); cout << cur << ; int x = -1, y = -1; for (int j = 0; j < 3; j++) { int v = a[cur][j]; if (v != r.first) { if (x == -1) x = v; else y = v; } } if (x > y) swap(x, y); int ind = 0; auto tmp = gg[{x, y}]; if (tmp.empty()) { return 0; } if (tmp[ind] == cur) ind++; ed[{x, y}]++; cur = tmp[ind]; r = get_corner(cur); ss.erase({-r.second + 1, cur}); ss.insert({-r.second, cur}); } cout << ss.begin()->second << n ; } return 0; } |
#include <bits/stdc++.h> int main() { char a[1000005]; scanf( %s , a); int i; long long ans = 0, b = 0; for (i = strlen(a) - 1; i >= 0; i--) { if (a[i] == b ) b++; else if (a[i] == a ) { ans += b; b <<= 1; } ans %= 1000000007; b %= 1000000007; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, x, y, s1, s2, i, j, a, b, c, r = 0; cin >> n >> s1 >> s2; long long x1[n + 1], x2[n + 1], y1[n + 1], y2[n + 1]; for (i = 1; i <= n; i++) { cin >> x >> y; x1[i] = min(x, s1), x2[i] = max(x, s1), y1[i] = min(y, s2), y2[i] = max(y, s2); } vector<pair<long long, long long> > v1; if (s1 - 1 >= 0) v1.push_back({s1 - 1, s2}); if (s1 + 1 <= 1e9) v1.push_back({s1 + 1, s2}); if (s2 - 1 >= 0) v1.push_back({s1, s2 - 1}); if (s2 + 1 <= 1e9) v1.push_back({s1, s2 + 1}); for (i = 0; i < v1.size(); i++) { x = v1[i].first, y = v1[i].second, c = 0; for (j = 1; j <= n; j++) { if (x >= x1[j] && x <= x2[j] && y >= y1[j] && y <= y2[j]) c++; } if (c >= r) r = c, a = x, b = y; } cout << r << n ; cout << a << << b << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKINVLP_SYMBOL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinvlp (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int DIM = 1e5 + 5; int szt[DIM], ans[DIM]; vector<int> edg[DIM]; map<int, int> son, par, out; void dfs1(int x, int sz) { szt[x] = 1; for (int y : edg[x]) { dfs1(y, sz); szt[x] += szt[y]; } out[szt[x]]++; ans[x] = sz - 1; return; } void add(map<int, int> &mmp, int x, int val) { mmp[x] += val; out[x] -= val; if (!mmp[x]) mmp.erase(x); if (!out[x]) out.erase(x); return; } void bns(map<int, int> &mmp, int x, int le, int ri, int mnm, int aux) { int val = ri, sol = ri; while (le <= ri) { int md = (le + ri) >> 1; map<int, int>::iterator it = mmp.lower_bound(val - md + aux); if (it == mmp.end() || it->first + mnm > md + aux) le = md + 1; else ri = md - 1, sol = min(sol, md); } ans[x] = min(ans[x], sol); return; } void dfs3(int x, int val, int pos) { add(son, szt[x], val); for (int y : edg[x]) if (y != pos) dfs3(y, val, pos); return; } void dfs2(int x, int sz, bool oki) { int mxm1(-1), mxm2(-1), pos(-1), mnm(sz - 1); add(par, szt[x], 1); for (int y : edg[x]) { mnm = min(mnm, szt[y]); if (mxm1 < szt[y]) mxm2 = mxm1, mxm1 = szt[y], pos = y; else mxm2 = max(mxm2, szt[y]); } if (szt[x] != sz) mnm = min(mnm, sz - szt[x]); for (int y : edg[x]) if (y != pos) dfs2(y, sz, false); if (pos != -1) dfs2(pos, sz, true); if (mxm1 >= sz - szt[x]) { mxm2 = max(mxm2, sz - szt[x]); if (mnm != sz - 1) bns(son, x, mxm2, mxm1, mnm, 0); } dfs3(x, 1, pos); add(par, szt[x], -1); if (mxm1 <= sz - szt[x] && mnm != sz - 1) { bns(par, x, mxm1, sz - szt[x], mnm, szt[x]); bns(out, x, mxm1, sz - szt[x], mnm, 0); } if (!oki) dfs3(x, -1, -1); return; } int main(void) { int n, r(-1); scanf( %d , &n); for (int i = 1; i <= n; ++i) { int x, y; scanf( %d %d , &x, &y); if (x == 0) r = y; else edg[x].push_back(y); } dfs1(r, n); dfs2(r, n, true); for (int i = 1; i <= n; ++i) printf( %d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; struct point { int x, y; } a[200005]; bool cmp(struct point A, struct point B) { if (A.x != B.x) return A.x < B.x; return A.y < B.y; } int m; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { scanf( %d , &a[i].x); a[i].y = i + 1; } int num = 0; for (int i = n; i < 2 * n; i++) { scanf( %d , &a[i].x); a[i].y = i + 1 - n; if (a[i].x == a[i - n].x) num++; } n *= 2; a[n].x = 1e9 + 1; n++; sort(a, a + n, cmp); cin >> m; long long ans = 1; int count = 1; for (int i = 1; i < n; i++) { if (a[i].x == a[i - 1].x) { count++; ans = (ans * count); while (num && ans % 2 == 0) { ans /= 2; num--; } ans %= m; } else count = 1; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int powe(long long int d, long long int s) { if (s == 1) return d; else if (s == 0) return 1; else { long long int u, v = d; for (u = 1; u < s; u++) { d = d * v; } return d; } } bool isprime(long long int n) { long long int i; for (i = 2; i * i <= n; i++) { if (n % i == 0) { return false; } } return true; } long long int a[2000005], c[10000005]; int main() { map<int, int> b; long long int i, p, y, mx = -1, j, q; cin >> p >> y; for (i = y; i > p; i--) { q = 1; for (j = 2; j * j <= i && j <= p; j++) { if (i % j == 0) { q = 0; break; } } if (q == 1) { cout << i; return 0; } } cout << -1; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
(* X_CORE_INFO = "xlconcat,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlconcat_1_1,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlconcat_1_1,xlconcat,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=7,IN1_WIDTH=16,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_W\
IDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=24,NUM_PORTS=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconcat_1_1 (
In0,
In1,
In2,
dout
);
input wire [6 : 0] In0;
input wire [15 : 0] In1;
input wire [0 : 0] In2;
output wire [23 : 0] dout;
xlconcat #(
.IN0_WIDTH(7),
.IN1_WIDTH(16),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(24),
.NUM_PORTS(3)
) inst (
.In0(In0),
.In1(In1),
.In2(In2),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFL = 0x3f3f3f3f3f3f3f3fLL; struct Edge { int src, dst; int weight; Edge(int src_, int dst_, int weight_) : src(src_), dst(dst_), weight(weight_) {} Edge(int dst_, int weight_) : src(-2), dst(dst_), weight(weight_) {} }; bool operator<(const Edge &e, const Edge &f) { return e.weight != f.weight ? e.weight > f.weight : e.dst < f.dst; } void dijkstra(const vector<vector<Edge> > &g, int start, vector<int> &dist) { int n = g.size(); dist.assign(n, INF); dist[start] = 0; vector<int> prev(n, -1); priority_queue<Edge> q; for (q.push(Edge(-2, start, 0)); !q.empty();) { Edge e = q.top(); q.pop(); if (prev[e.dst] != -1) continue; prev[e.dst] = e.src; for (typeof((g[e.dst]).begin()) f = ((g[e.dst]).begin()); f != (g[e.dst]).end(); ++f) { if (dist[f->dst] > e.weight + f->weight) { dist[f->dst] = e.weight + f->weight; q.push(Edge(f->src, f->dst, e.weight + f->weight)); } } } } int main() { int n; int x0, y0, x1, y1; vector<pair<int, pair<int, int> > > v; cin >> y0 >> x0 >> y1 >> x1; cin >> n; for (int(i) = 0; (i) < (int)(n); ++(i)) { int o, a, b; cin >> o >> a >> b; v.push_back(make_pair((o), (make_pair((a), (b))))); } sort((v).begin(), (v).end()); map<pair<int, int>, int> m; int t = 0; static const int dy[4] = {0, -1, -1, -1}, dx[4] = {-1, 0, -1, 1}; vector<vector<Edge> > g; for (typeof((v).begin()) i = ((v).begin()); i != (v).end(); ++i) { for (int(j) = (int)(i->second.first); (j) <= (int)(i->second.second); ++(j)) { if (m.count(make_pair((i->first), (j)))) continue; int q = m[make_pair((i->first), (j))] = t++; g.push_back(vector<Edge>()); for (int(d) = 0; (d) < (int)(4); ++(d)) if (m.count(make_pair((i->first + dy[d]), (j + dx[d])))) { g[q].push_back( Edge(q, m[make_pair((i->first + dy[d]), (j + dx[d]))], 1)); } } } vector<vector<Edge> > gg(t); for (int(i) = 0; (i) < (int)(t); ++(i)) for (typeof((g[i]).begin()) j = ((g[i]).begin()); j != (g[i]).end(); ++j) { gg[j->src].push_back(Edge(j->src, j->dst, 1)); gg[j->dst].push_back(Edge(j->dst, j->src, 1)); } int r = -1; if (!m.count(make_pair((y0), (x0)))) r = -999; else if (!m.count(make_pair((y1), (x1)))) r = -999; else { vector<int> d; dijkstra(gg, m[make_pair((y0), (x0))], d); r = d[m[make_pair((y1), (x1))]]; if (r == INF) r = -1; } cout << r << endl; return 0; } |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Flow generator - generic packet generator module
*/
module fg_packet_gen #(
parameter DEST_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* Burst descriptor input
*/
input wire input_bd_valid,
output wire input_bd_ready,
input wire [DEST_WIDTH-1:0] input_bd_dest,
input wire [31:0] input_bd_burst_len,
/*
* Packet output
*/
output wire output_hdr_valid,
input wire output_hdr_ready,
output wire [DEST_WIDTH-1:0] output_hdr_dest,
output wire [15:0] output_hdr_len,
output wire [DATA_WIDTH-1:0] output_payload_tdata,
output wire [KEEP_WIDTH-1:0] output_payload_tkeep,
output wire output_payload_tvalid,
input wire output_payload_tready,
output wire output_payload_tlast,
output wire output_payload_tuser,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [15:0] payload_mtu
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_BURST = 2'd1,
STATE_FRAME = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [31:0] burst_len_reg = 0, burst_len_next;
reg [15:0] frame_len_reg = 0, frame_len_next;
reg input_bd_ready_reg = 0, input_bd_ready_next;
reg output_hdr_valid_reg = 0, output_hdr_valid_next;
reg [DEST_WIDTH-1:0] output_hdr_dest_reg = 0, output_hdr_dest_next;
reg [15:0] output_hdr_len_reg = 0, output_hdr_len_next;
reg busy_reg = 0;
// internal datapath
reg [DATA_WIDTH-1:0] output_payload_tdata_int;
reg [KEEP_WIDTH-1:0] output_payload_tkeep_int;
reg output_payload_tvalid_int;
reg output_payload_tready_int = 0;
reg output_payload_tlast_int;
reg output_payload_tuser_int;
wire output_payload_tready_int_early;
assign input_bd_ready = input_bd_ready_reg;
assign output_hdr_valid = output_hdr_valid_reg;
assign output_hdr_dest = output_hdr_dest_reg;
assign output_hdr_len = output_hdr_len_reg;
assign busy = busy_reg;
always @* begin
state_next = 0;
burst_len_next = burst_len_reg;
frame_len_next = frame_len_reg;
input_bd_ready_next = 0;
output_hdr_valid_next = output_hdr_valid_reg & ~output_hdr_ready;
output_hdr_dest_next = output_hdr_dest_reg;
output_hdr_len_next = output_hdr_len_reg;
output_payload_tdata_int = 0;
output_payload_tkeep_int = 0;
output_payload_tvalid_int = 0;
output_payload_tlast_int = 0;
output_payload_tuser_int = 0;
case (state_reg)
STATE_IDLE: begin
input_bd_ready_next = 1;
if (input_bd_ready & input_bd_valid) begin
output_hdr_dest_next = input_bd_dest;
burst_len_next = input_bd_burst_len;
state_next = STATE_BURST;
end else begin
state_next = STATE_IDLE;
end
end
STATE_BURST: begin
if (~output_hdr_valid_reg) begin
if (burst_len_reg > payload_mtu) begin
frame_len_next = payload_mtu;
burst_len_next = burst_len_reg - payload_mtu;
output_hdr_valid_next = 1;
output_hdr_len_next = payload_mtu;
end else begin
frame_len_next = burst_len_reg;
burst_len_next = 0;
output_hdr_valid_next = 1;
output_hdr_len_next = burst_len_reg;
end
state_next = STATE_FRAME;
end else begin
state_next = STATE_BURST;
end
end
STATE_FRAME: begin
if (output_payload_tready_int) begin
if (frame_len_reg > KEEP_WIDTH) begin
frame_len_next = frame_len_reg - KEEP_WIDTH;
output_payload_tkeep_int = {KEEP_WIDTH{1'b1}};
output_payload_tvalid_int = 1;
state_next = STATE_FRAME;
end else begin
frame_len_next = 0;
output_payload_tkeep_int = {KEEP_WIDTH{1'b1}} >> (KEEP_WIDTH - frame_len_reg);
output_payload_tvalid_int = 1;
output_payload_tlast_int = 1;
if (burst_len_reg > 0) begin
state_next = STATE_BURST;
end else begin
state_next = STATE_IDLE;
end
end
end else begin
state_next = STATE_FRAME;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
burst_len_reg <= 0;
frame_len_reg <= 0;
input_bd_ready_reg <= 0;
output_hdr_valid_reg <= 0;
output_hdr_dest_reg <= 0;
output_hdr_len_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
burst_len_reg <= burst_len_next;
frame_len_reg <= frame_len_next;
input_bd_ready_reg <= input_bd_ready_next;
output_hdr_valid_reg <= output_hdr_valid_next;
output_hdr_dest_reg <= output_hdr_dest_next;
output_hdr_len_reg <= output_hdr_len_next;
busy_reg <= state_next != STATE_IDLE;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_payload_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] output_payload_tkeep_reg = 0;
reg output_payload_tvalid_reg = 0;
reg output_payload_tlast_reg = 0;
reg output_payload_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_payload_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] temp_payload_tkeep_reg = 0;
reg temp_payload_tvalid_reg = 0;
reg temp_payload_tlast_reg = 0;
reg temp_payload_tuser_reg = 0;
assign output_payload_tdata = output_payload_tdata_reg;
assign output_payload_tkeep = output_payload_tkeep_reg;
assign output_payload_tvalid = output_payload_tvalid_reg;
assign output_payload_tlast = output_payload_tlast_reg;
assign output_payload_tuser = output_payload_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_payload_tready_int_early = output_payload_tready | (~temp_payload_tvalid_reg & ~output_payload_tvalid_reg) | (~temp_payload_tvalid_reg & ~output_payload_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_payload_tdata_reg <= 0;
output_payload_tkeep_reg <= 0;
output_payload_tvalid_reg <= 0;
output_payload_tlast_reg <= 0;
output_payload_tuser_reg <= 0;
output_payload_tready_int <= 0;
temp_payload_tdata_reg <= 0;
temp_payload_tkeep_reg <= 0;
temp_payload_tvalid_reg <= 0;
temp_payload_tlast_reg <= 0;
temp_payload_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_payload_tready_int <= output_payload_tready_int_early;
if (output_payload_tready_int) begin
// input is ready
if (output_payload_tready | ~output_payload_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_payload_tdata_reg <= output_payload_tdata_int;
output_payload_tkeep_reg <= output_payload_tkeep_int;
output_payload_tvalid_reg <= output_payload_tvalid_int;
output_payload_tlast_reg <= output_payload_tlast_int;
output_payload_tuser_reg <= output_payload_tuser_int;
end else begin
// output is not ready, store input in temp
temp_payload_tdata_reg <= output_payload_tdata_int;
temp_payload_tkeep_reg <= output_payload_tkeep_int;
temp_payload_tvalid_reg <= output_payload_tvalid_int;
temp_payload_tlast_reg <= output_payload_tlast_int;
temp_payload_tuser_reg <= output_payload_tuser_int;
end
end else if (output_payload_tready) begin
// input is not ready, but output is ready
output_payload_tdata_reg <= temp_payload_tdata_reg;
output_payload_tkeep_reg <= temp_payload_tkeep_reg;
output_payload_tvalid_reg <= temp_payload_tvalid_reg;
output_payload_tlast_reg <= temp_payload_tlast_reg;
output_payload_tuser_reg <= temp_payload_tuser_reg;
temp_payload_tdata_reg <= 0;
temp_payload_tkeep_reg <= 0;
temp_payload_tvalid_reg <= 0;
temp_payload_tlast_reg <= 0;
temp_payload_tuser_reg <= 0;
end
end
end
endmodule
|
module ADT7310P32S16 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPreset_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i(SPICounterPreset_i)
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i})
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen () ////
//// - Tadej Markovic () ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:06 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_1_0_stub.v
// Design : design_1_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 8991 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w7936,
w7967,
w1024,
w8991;
assign w1 = i_data0;
assign w1024 = w1 << 10;
assign w31 = w32 - w1;
assign w32 = w1 << 5;
assign w7936 = w31 << 8;
assign w7967 = w31 + w7936;
assign w8991 = w7967 + w1024;
assign o_data0 = w8991;
//multiplier_block area estimate = 4547.18884368088;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, s, p; int main() { scanf( %d %d %d , &t, &s, &p); int l = t; int x1 = 0, x2 = s; int co = 1; while (x1 < l) { x1 = x1 + p; x2 = x2 + p - 1; if (x1 >= l && x2 >= l) break; else if (x1 >= x2) { x1 = 0; co++; } } cout << co << endl; return 0; } |
#include <bits/stdc++.h> const int base = 1000000000; const int base_digits = 9; struct bigint { std::vector<int> z; int sign; bigint() : sign(1) {} bigint(long long v) { *this = v; } bigint(const std::string &s) { read(s); } void operator=(const bigint &v) { sign = v.sign; z = v.z; } void operator=(long long v) { sign = 1; if (v < 0) sign = -1, v = -v; z.clear(); for (; v > 0; v = v / base) z.push_back(v % base); } bigint operator+(const bigint &v) const { if (sign == v.sign) { bigint res = v; for (int i = 0, carry = 0; i < (int)std::max(z.size(), v.z.size()) || carry; ++i) { if (i == (int)res.z.size()) res.z.push_back(0); res.z[i] += carry + (i < (int)z.size() ? z[i] : 0); carry = res.z[i] >= base; if (carry) res.z[i] -= base; } return res; } return *this - (-v); } bigint operator-(const bigint &v) const { if (sign == v.sign) { if (abs() >= v.abs()) { bigint res = *this; for (int i = 0, carry = 0; i < (int)v.z.size() || carry; ++i) { res.z[i] -= carry + (i < (int)v.z.size() ? v.z[i] : 0); carry = res.z[i] < 0; if (carry) res.z[i] += base; } res.trim(); return res; } return -(v - *this); } return *this + (-v); } void operator*=(int v) { if (v < 0) sign = -sign, v = -v; for (int i = 0, carry = 0; i < (int)z.size() || carry; ++i) { if (i == (int)z.size()) z.push_back(0); long long cur = z[i] * (long long)v + carry; carry = (int)(cur / base); z[i] = (int)(cur % base); } trim(); } bigint operator*(int v) const { bigint res = *this; res *= v; return res; } friend std::pair<bigint, bigint> divmod(const bigint &a1, const bigint &b1) { int norm = base / (b1.z.back() + 1); bigint a = a1.abs() * norm; bigint b = b1.abs() * norm; bigint q, r; q.z.resize(a.z.size()); for (int i = a.z.size() - 1; i >= 0; i--) { r *= base; r += a.z[i]; int s1 = b.z.size() < r.z.size() ? r.z[b.z.size()] : 0; int s2 = b.z.size() - 1 < r.z.size() ? r.z[b.z.size() - 1] : 0; int d = ((long long)s1 * base + s2) / b.z.back(); r -= b * d; while (r < 0) r += b, --d; q.z[i] = d; } q.sign = a1.sign * b1.sign; r.sign = a1.sign; q.trim(); r.trim(); return std::make_pair(q, r / norm); } friend bigint sqrt(const bigint &a1) { bigint a = a1; while (a.z.empty() || a.z.size() % 2 == 1) a.z.push_back(0); int n = a.z.size(); int firstDigit = (int)sqrt((double)a.z[n - 1] * base + a.z[n - 2]); int norm = base / (firstDigit + 1); a *= norm; a *= norm; while (a.z.empty() || a.z.size() % 2 == 1) a.z.push_back(0); bigint r = (long long)a.z[n - 1] * base + a.z[n - 2]; firstDigit = (int)sqrt((double)a.z[n - 1] * base + a.z[n - 2]); int q = firstDigit; bigint res; for (int j = n / 2 - 1; j >= 0; j--) { for (;; --q) { bigint r1 = (r - (res * 2 * base + q) * q) * base * base + (j > 0 ? (long long)a.z[2 * j - 1] * base + a.z[2 * j - 2] : 0); if (r1 >= 0) { r = r1; break; } } res *= base; res += q; if (j > 0) { int d1 = res.z.size() + 2 < r.z.size() ? r.z[res.z.size() + 2] : 0; int d2 = res.z.size() + 1 < r.z.size() ? r.z[res.z.size() + 1] : 0; int d3 = res.z.size() < r.z.size() ? r.z[res.z.size()] : 0; q = ((long long)d1 * base * base + (long long)d2 * base + d3) / (firstDigit * 2); } } res.trim(); return res / norm; } bigint operator/(const bigint &v) const { return divmod(*this, v).first; } bigint operator%(const bigint &v) const { return divmod(*this, v).second; } void operator/=(int v) { if (v < 0) sign = -sign, v = -v; for (int i = (int)z.size() - 1, rem = 0; i >= 0; --i) { long long cur = z[i] + rem * (long long)base; z[i] = (int)(cur / v); rem = (int)(cur % v); } trim(); } bigint operator/(int v) const { bigint res = *this; res /= v; return res; } int operator%(int v) const { if (v < 0) v = -v; int m = 0; for (int i = z.size() - 1; i >= 0; --i) m = (z[i] + m * (long long)base) % v; return m * sign; } void operator+=(const bigint &v) { *this = *this + v; } void operator-=(const bigint &v) { *this = *this - v; } void operator*=(const bigint &v) { *this = *this * v; } void operator/=(const bigint &v) { *this = *this / v; } bool operator<(const bigint &v) const { if (sign != v.sign) return sign < v.sign; if (z.size() != v.z.size()) return z.size() * sign < v.z.size() * v.sign; for (int i = z.size() - 1; i >= 0; i--) if (z[i] != v.z[i]) return z[i] * sign < v.z[i] * sign; return false; } bool operator>(const bigint &v) const { return v < *this; } bool operator<=(const bigint &v) const { return !(v < *this); } bool operator>=(const bigint &v) const { return !(*this < v); } bool operator==(const bigint &v) const { return !(*this < v) && !(v < *this); } bool operator!=(const bigint &v) const { return *this < v || v < *this; } void trim() { while (!z.empty() && z.back() == 0) z.pop_back(); if (z.empty()) sign = 1; } bool isZero() const { return z.empty() || (z.size() == 1 && !z[0]); } bigint operator-() const { bigint res = *this; res.sign = -sign; return res; } bigint abs() const { bigint res = *this; res.sign *= res.sign; return res; } long long longValue() const { long long res = 0; for (int i = z.size() - 1; i >= 0; i--) res = res * base + z[i]; return res * sign; } friend bigint gcd(const bigint &a, const bigint &b) { return b.isZero() ? a : gcd(b, a % b); } friend bigint lcm(const bigint &a, const bigint &b) { return a / gcd(a, b) * b; } void read(const std::string &s) { sign = 1; z.clear(); int pos = 0; while (pos < (int)s.size() && (s[pos] == - || s[pos] == + )) { if (s[pos] == - ) sign = -sign; ++pos; } for (int i = s.size() - 1; i >= pos; i -= base_digits) { int x = 0; for (int j = std::max(pos, i - base_digits + 1); j <= i; j++) x = x * 10 + s[j] - 0 ; z.push_back(x); } trim(); } friend std::istream &operator>>(std::istream &stream, bigint &v) { std::string s; stream >> s; v.read(s); return stream; } friend std::ostream &operator<<(std::ostream &stream, const bigint &v) { if (v.sign == -1) stream << - ; stream << (v.z.empty() ? 0 : v.z.back()); for (int i = (int)v.z.size() - 2; i >= 0; --i) stream << std::setw(base_digits) << std::setfill( 0 ) << v.z[i]; return stream; } static std::vector<int> convert_base(const std::vector<int> &a, int old_digits, int new_digits) { std::vector<long long> p(std::max(old_digits, new_digits) + 1); p[0] = 1; for (int i = 1; i < (int)p.size(); i++) p[i] = p[i - 1] * 10; std::vector<int> res; long long cur = 0; int cur_digits = 0; for (int i = 0; i < (int)a.size(); i++) { cur += a[i] * p[cur_digits]; cur_digits += old_digits; while (cur_digits >= new_digits) { res.push_back(int(cur % p[new_digits])); cur /= p[new_digits]; cur_digits -= new_digits; } } res.push_back((int)cur); while (!res.empty() && res.back() == 0) res.pop_back(); return res; } static std::vector<long long> karatsubaMultiply( const std::vector<long long> &a, const std::vector<long long> &b) { int n = a.size(); std::vector<long long> res(n + n); if (n <= 32) { for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) res[i + j] += a[i] * b[j]; return res; } int k = n >> 1; std::vector<long long> a1(a.begin(), a.begin() + k); std::vector<long long> a2(a.begin() + k, a.end()); std::vector<long long> b1(b.begin(), b.begin() + k); std::vector<long long> b2(b.begin() + k, b.end()); std::vector<long long> a1b1 = karatsubaMultiply(a1, b1); std::vector<long long> a2b2 = karatsubaMultiply(a2, b2); for (int i = 0; i < k; i++) a2[i] += a1[i]; for (int i = 0; i < k; i++) b2[i] += b1[i]; std::vector<long long> r = karatsubaMultiply(a2, b2); for (int i = 0; i < (int)a1b1.size(); i++) r[i] -= a1b1[i]; for (int i = 0; i < (int)a2b2.size(); i++) r[i] -= a2b2[i]; for (int i = 0; i < (int)r.size(); i++) res[i + k] += r[i]; for (int i = 0; i < (int)a1b1.size(); i++) res[i] += a1b1[i]; for (int i = 0; i < (int)a2b2.size(); i++) res[i + n] += a2b2[i]; return res; } bigint operator*(const bigint &v) const { std::vector<int> a6 = convert_base(this->z, base_digits, 6); std::vector<int> b6 = convert_base(v.z, base_digits, 6); std::vector<long long> a(a6.begin(), a6.end()); std::vector<long long> b(b6.begin(), b6.end()); while (a.size() < b.size()) a.push_back(0); while (b.size() < a.size()) b.push_back(0); while (a.size() & (a.size() - 1)) a.push_back(0), b.push_back(0); std::vector<long long> c = karatsubaMultiply(a, b); bigint res; res.sign = sign * v.sign; for (int i = 0, carry = 0; i < (int)c.size(); i++) { long long cur = c[i] + carry; res.z.push_back((int)(cur % 1000000)); carry = (int)(cur / 1000000); } res.z = convert_base(res.z, 6, base_digits); res.trim(); return res; } }; bigint lastans; const int maxn = 6e5 + 222; const int mask = (1 << 30); using ll = long long; int q, s[maxn], nxt[maxn], pre[maxn], w[maxn]; std::map<int, int> cnt; std::vector<int> stk; char t[10]; ll sum = 0; int query(int x) { return w[*std::lower_bound(stk.begin(), stk.end(), x)]; } int main() { scanf( %d , &q); scanf( %s%d , t + 1, &w[1]); s[1] = t[1] - a ; lastans = w[1]; stk.push_back(1); std::cout << lastans << n ; for (int n = 2, j = 0; n <= q; ++n) { scanf( %s%d , t + 1, &w[n]); int c = (lastans + t[1] - a ) % 26; s[n] = c; w[n] = w[n] ^ (lastans % mask); while (j && s[j + 1] != s[n]) j = nxt[j]; if (s[j + 1] == s[n]) j++; nxt[n] = j; if (s[nxt[n - 1] + 1] == s[n]) pre[n - 1] = pre[nxt[n - 1]]; else pre[n - 1] = nxt[n - 1]; int x = nxt[n - 1]; while (x) { if (s[x + 1] == s[n]) x = pre[x]; else { int w = query(n - x); cnt[w]--; sum -= w; x = nxt[x]; } } while (stk.size() && w[stk.back()] >= w[n]) stk.pop_back(); stk.push_back(n); int cw = 0; for (auto it = cnt.upper_bound(w[n]); it != cnt.end();) { sum -= (ll)it->second * (it->first - w[n]); cw += it->second; auto nw = std::next(it); cnt.erase(it); it = nw; } cnt[w[n]] += cw; if (s[1] == s[n]) { cnt[w[n]]++; sum += w[n]; } lastans += sum + w[stk[0]]; std::cout << lastans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; using ll = long long; void solve() { string s; int a; cin >> a >> s; int sum = 0; vector<int> v; v.push_back(0); for (int i = s.size() - 1; i >= 0; i--) { if (s[i] == P ) sum++; else { v.push_back(sum); sum = 0; } } cout << *max_element(v.begin(), v.end()) << endl; } int main() { int t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; const int N = 203600; pair<pair<int, int>, int> p[N]; int n; vector<int> ans; int main() { cin >> n; for (int i = (0); i < (int)(n); i++) { cin >> p[i].first.first >> p[i].first.second; p[i].second = i + 1; } sort(p, p + n); for (int i = (0); i < (int)(n); i++) { int cur = -1e9; bool ok = 1; for (int j = (0); j < (int)(n); j++) if (j != i) { if (p[j].first.first < cur) ok = 0; else cur = p[j].first.second; } if (ok) ans.push_back(p[i].second); } sort((ans).begin(), (ans).end()); printf( %d n , (int)ans.size()); for (int i = (0); i < (int)(ans.size()); i++) printf( %d%s , ans[i], i + 1 == ans.size() ? n : ); } |
// megafunction wizard: %LPM_CONSTANT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_constant
// ============================================================
// File Name: lpm_constant2.v
// Megafunction Name(s):
// lpm_constant
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module lpm_constant2 (
result);
output [2:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "ConL"
// Retrieval info: PRIVATE: Radix NUMERIC "10"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Value NUMERIC "7"
// Retrieval info: PRIVATE: nBit NUMERIC "3"
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "7"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ConL"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: result 0 0 3 0 OUTPUT NODEFVAL result[2..0]
// Retrieval info: CONNECT: result 0 0 3 0 @result 0 0 3 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`include "../lib/mux_2to1.v"
module mux32bit_2to1(input [31:0] i0, i1,
input s,
output [31:0] z);
mux_2to1 mux0 (.i0(i0[0 ]), .i1(i1[0 ]), .z(z[0 ]), .s(s));
mux_2to1 mux1 (.i0(i0[1 ]), .i1(i1[1 ]), .z(z[1 ]), .s(s));
mux_2to1 mux2 (.i0(i0[2 ]), .i1(i1[2 ]), .z(z[2 ]), .s(s));
mux_2to1 mux3 (.i0(i0[3 ]), .i1(i1[3 ]), .z(z[3 ]), .s(s));
mux_2to1 mux4 (.i0(i0[4 ]), .i1(i1[4 ]), .z(z[4 ]), .s(s));
mux_2to1 mux5 (.i0(i0[5 ]), .i1(i1[5 ]), .z(z[5 ]), .s(s));
mux_2to1 mux6 (.i0(i0[6 ]), .i1(i1[6 ]), .z(z[6 ]), .s(s));
mux_2to1 mux7 (.i0(i0[7 ]), .i1(i1[7 ]), .z(z[7 ]), .s(s));
mux_2to1 mux8 (.i0(i0[8 ]), .i1(i1[8 ]), .z(z[8 ]), .s(s));
mux_2to1 mux9 (.i0(i0[9 ]), .i1(i1[9 ]), .z(z[9 ]), .s(s));
mux_2to1 mux10(.i0(i0[10]), .i1(i1[10]), .z(z[10]), .s(s));
mux_2to1 mux11(.i0(i0[11]), .i1(i1[11]), .z(z[11]), .s(s));
mux_2to1 mux12(.i0(i0[12]), .i1(i1[12]), .z(z[12]), .s(s));
mux_2to1 mux13(.i0(i0[13]), .i1(i1[13]), .z(z[13]), .s(s));
mux_2to1 mux14(.i0(i0[14]), .i1(i1[14]), .z(z[14]), .s(s));
mux_2to1 mux15(.i0(i0[15]), .i1(i1[15]), .z(z[15]), .s(s));
mux_2to1 mux16(.i0(i0[16]), .i1(i1[16]), .z(z[16]), .s(s));
mux_2to1 mux17(.i0(i0[17]), .i1(i1[17]), .z(z[17]), .s(s));
mux_2to1 mux18(.i0(i0[18]), .i1(i1[18]), .z(z[18]), .s(s));
mux_2to1 mux19(.i0(i0[19]), .i1(i1[19]), .z(z[19]), .s(s));
mux_2to1 mux20(.i0(i0[20]), .i1(i1[20]), .z(z[20]), .s(s));
mux_2to1 mux21(.i0(i0[21]), .i1(i1[21]), .z(z[21]), .s(s));
mux_2to1 mux22(.i0(i0[22]), .i1(i1[22]), .z(z[22]), .s(s));
mux_2to1 mux23(.i0(i0[23]), .i1(i1[23]), .z(z[23]), .s(s));
mux_2to1 mux24(.i0(i0[24]), .i1(i1[24]), .z(z[24]), .s(s));
mux_2to1 mux25(.i0(i0[25]), .i1(i1[25]), .z(z[25]), .s(s));
mux_2to1 mux26(.i0(i0[26]), .i1(i1[26]), .z(z[26]), .s(s));
mux_2to1 mux27(.i0(i0[27]), .i1(i1[27]), .z(z[27]), .s(s));
mux_2to1 mux28(.i0(i0[28]), .i1(i1[28]), .z(z[28]), .s(s));
mux_2to1 mux29(.i0(i0[29]), .i1(i1[29]), .z(z[29]), .s(s));
mux_2to1 mux30(.i0(i0[30]), .i1(i1[30]), .z(z[30]), .s(s));
mux_2to1 mux31(.i0(i0[31]), .i1(i1[31]), .z(z[31]), .s(s));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n < 998) cout << n + 2; else cout << n - 2; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V |
//TODO: make memory do... something... when given an address not in range 0x80020000 -> (0x80020000 + Memory Size)
module mips_memory (clk, addr, din, dout, access_size, rw, busy, enable);
parameter MEMSIZE = 1024;
parameter START_ADDR = 32'h8002_0000; // h80020000
// input
input clk;
input [31:0] addr;
input [31:0] din;
input [1:0] access_size;
input rw; //1 is write, 0 is read
input enable;
// output
output busy;
output [31:0] dout;
reg [31:0] dout_driver;
wire [31:0] dout = dout_driver;
wire busy;
// memory
reg [7:0] mem[0:MEMSIZE];
// local variables
wire should_respond; // = enable & !busy
wire [4:0] cycles_remaining; // = 1, 4, 8, 16 for rw = 00, 01, 10, 11
reg [7:0] cycle_counter = 0;
reg operating;
reg [31:0] current_addr = 0; // increment by 1 after each cycle
reg current_rw = 0; // saves rw status for cycles to come
// combinational
assign should_respond = (enable & !busy);
assign cycles_remaining = (access_size == 2'b00) ? 1 : ((access_size == 2'b01) ? 4 : ((access_size == 2'b10) ? 8 : ((access_size == 2'b11) ? 16 : 0 )));
assign busy = (cycles_remaining != cycle_counter) & (cycle_counter != 0) & (cycles_remaining > 1);
// set up
/*integer i;
initial
begin
cycle_counter = 0;
current_addr = 0;
current_rw = 0;
for (i=0; i<180; i=i+1)
mem[i] <= 0;
end*/
// procedural
// do r/w, use local variables
always @(posedge clk)
begin
// if first cycle, set address + cycle + rw
if (should_respond == 1'b1)
begin
current_rw = rw;
current_addr = (addr - START_ADDR); //Convert to internal addresses
cycle_counter = 0;
operating = 1;
end
end
always @(negedge clk)
begin
if (cycle_counter != cycles_remaining && operating == 1)
begin
if (current_rw == 1'b1)
begin
//Do write, needs to support various "access_size"
mem[current_addr] <= din[31:24]; // MSB
mem[current_addr+1] <= din[23:16];
mem[current_addr+2] <= din[15:8];
mem[current_addr+3] <= din[7:0]; // LSB
end
else
begin
//Do read, needs to support various "access_size"
dout_driver[31:24] <= mem[current_addr]; // MSB
dout_driver[23:16] <= mem[current_addr+1];
dout_driver[15:8] <= mem[current_addr+2];
dout_driver[7:0] <= mem[current_addr+3]; // LSB
end
cycle_counter = cycle_counter + 1;
current_addr = current_addr + 4;
end
else
begin
operating = 0;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_thrcmpl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_thrcmpl
// Description:
// The thread completion block processes the completion signals fomr
// the different cpu blocks and generates a unified completion
// signal.
*/
module sparc_ifu_thrcmpl(/*AUTOARG*/
// Outputs
completion, wm_imiss, wm_other,
// Inputs
clk, se, si, reset, fcl_ifq_icmiss_s1, erb_dtu_ifeterr_d1,
sw_cond_s, en_spec_g, atr_s, dtu_fcl_thr_active, ifq_dtu_thrrdy,
ifq_dtu_pred_rdy, exu_lop_done, branch_done_d, fixedop_done,
ldmiss, spec_ld_d, trap, retr_thr_wakeup, flush_wake_w2,
ldhit_thr, spec_ld_g, clear_wmo_e, wm_stbwait, stb_retry,
rst_thread, trap_thrrdy, thr_s2, thr_e, thr_s1, fp_thrrdy,
lsu_ifu_ldst_cmplt, sta_done_e, killed_inst_done_e
);
input clk, se, si, reset;
input fcl_ifq_icmiss_s1;
input erb_dtu_ifeterr_d1;
input sw_cond_s;
input en_spec_g;
input atr_s;
input [3:0] dtu_fcl_thr_active;
input [3:0] ifq_dtu_thrrdy, // I$ miss completion
ifq_dtu_pred_rdy,
exu_lop_done, // mul, div, wrpr, sav, rest
branch_done_d,
fixedop_done; // br, rdsr, wrs/pr,
input [3:0] ldmiss,
spec_ld_d,
trap,
retr_thr_wakeup,
flush_wake_w2,
ldhit_thr,
spec_ld_g;
input clear_wmo_e;
input [3:0] wm_stbwait,
stb_retry;
input [3:0] rst_thread,
trap_thrrdy;
input [3:0] thr_s2,
thr_e,
thr_s1;
input [3:0] fp_thrrdy;
input [3:0] lsu_ifu_ldst_cmplt; // sta local, ld and atomic done
input sta_done_e,
killed_inst_done_e; // long lat op was killed
// .. Other completion signals needed
// 1. STA completion from LSU -- real mem done 10/03, local TBD
// 2. Atomic completion -- done
// 3. membar completion (lsu) -- done
// 4. flush completion (lsu)
// 5. FP op completion (ffu)
//
output [3:0] completion;
output [3:0] wm_imiss;
output [3:0] wm_other;
// local signals
wire [3:0] wm_imiss,
wm_other,
wmi_nxt,
wmo_nxt;
wire [3:0] clr_wmo_thr_e;
wire [3:0] ldst_thrrdy,
ld_thrrdy,
sta_thrrdy,
killed_thrrdy,
fp_thrrdy,
pred_ifq_rdy,
imiss_thrrdy,
other_thrrdy;
// wire [3:0] can_imiss;
//----------------------------------------------------------------------
// Code begins here
//----------------------------------------------------------------------
// Thread completion
// Since an imiss can overlap with anything else, have to make sure
// the imiss condition has been cleared.
// Imiss itself has to make sure ALL OTHER conditions have been
// cleared. In this code, I am not checking for branches being
// cleared, since Imiss is assumed to take much longer than a branch.
// -- may not be a valid assumption, since milhits could be faster
// assign can_imiss = fcl_ifq_canthr;
// & (wm_imiss | ({4{fcl_ifq_icmiss_s1}} & thr_s1));
dffr_s #(4) wmi_ff(.din (wmi_nxt),
.clk (clk),
.q (wm_imiss),
.rst (reset),
.se (se), .si(), .so());
dffr_s #(4) wmo_ff(.din (wmo_nxt),
.clk (clk),
.q (wm_other),
.rst (reset),
.se (se), .si(), .so());
assign wmi_nxt = ({4{fcl_ifq_icmiss_s1}} & thr_s1) | // set
({4{erb_dtu_ifeterr_d1}} & thr_e) |
(wm_imiss & ~imiss_thrrdy); // reset
// clear wm_other when we have a retracted store
assign clr_wmo_thr_e = {4{clear_wmo_e}} & thr_e;
assign wmo_nxt = (({4{sw_cond_s}} & thr_s2 & ~clr_wmo_thr_e) |
trap | ldmiss) & dtu_fcl_thr_active |
rst_thread | // set
wm_other & dtu_fcl_thr_active &
~(other_thrrdy | spec_ld_d | clr_wmo_thr_e); // reset
// A load hit signal is always for the load which is being filled
// to the RF. If speculation is enabled, the load would have
// completed even before the hit signal. So need to suppress the
// completions signal.
// load miss, st buf hit, ld/st alternate completion
assign ldst_thrrdy = lsu_ifu_ldst_cmplt & ~spec_ld_g;
assign ld_thrrdy = ldhit_thr & {4{~en_spec_g}};
assign sta_thrrdy = thr_e & {4{sta_done_e}};
assign killed_thrrdy = thr_e & {4{killed_inst_done_e}};
// everthing else
assign other_thrrdy = (ldst_thrrdy | // ld, sta local, atomic
branch_done_d | // br
ld_thrrdy | // load hit without spec
exu_lop_done | // mul, div, win mgmt
fixedop_done | // rdsr, wrspr
killed_thrrdy | // ll op was anulled
retr_thr_wakeup | // retract cond compl
flush_wake_w2 | // wake up after ecc
fp_thrrdy | // fp completion
sta_thrrdy | // sta to real memory
trap_thrrdy); // trap
// Imiss predicted ready
assign pred_ifq_rdy = ifq_dtu_pred_rdy & {4{~atr_s}} & dtu_fcl_thr_active;
assign imiss_thrrdy = pred_ifq_rdy | ifq_dtu_thrrdy;
// assign completion = imiss_thrrdy & (~(wm_other | wm_stbwait) |
// other_thrrdy) | //see C1
// other_thrrdy & (~(wm_imiss | wmi_nxt));
// assign completion = (imiss_thrrdy & ~(wm_other | wm_stbwait) |
// other_thrrdy & ~(wm_stbwait | wm_imiss) |
// stb_retry & ~(wm_other | wm_imiss) |
// imiss_thrrdy & other_thrrdy & ~wm_stbwait |
// imiss_thrrdy & stb_retry & ~wm_other |
// stb_retry & other_thrrdy & ~wm_imiss);
assign completion = ((imiss_thrrdy | ~wm_imiss) &
(other_thrrdy | ~wm_other) &
(stb_retry | ~wm_stbwait) &
(wm_imiss | wm_other | wm_stbwait));
// C1: should we do ~(wm_other | wmo_nxt)??
// When an imiss is pending, we cannot be doing another fetch, so I
// don't think so. It seems nice and symmetric to put it in
// though, unfortunately this results in a timing problem on swc_s
// and trap
endmodule // sparc_ifu_thrcmpl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_SYMBOL_V
`define SKY130_FD_SC_LP__BUSHOLD_SYMBOL_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold (
//# {{data|Data Signals}}
inout X ,
//# {{control|Control Signals}}
input RESET
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_SYMBOL_V
|
// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to unmerge all axis 'data' signals from payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_0_util_vector2axis
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_vdma_v6_2_8_axis_infrastructure_v1_0_util_vector2axis #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_TDATA_WIDTH = 32,
parameter integer C_TID_WIDTH = 1,
parameter integer C_TDEST_WIDTH = 1,
parameter integer C_TUSER_WIDTH = 1,
parameter integer C_TPAYLOAD_WIDTH = 44,
parameter [31:0] C_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// outputs
input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD,
// inputs
output wire [C_TDATA_WIDTH-1:0] TDATA,
output wire [C_TDATA_WIDTH/8-1:0] TSTRB,
output wire [C_TDATA_WIDTH/8-1:0] TKEEP,
output wire TLAST,
output wire [C_TID_WIDTH-1:0] TID,
output wire [C_TDEST_WIDTH-1:0] TDEST,
output wire [C_TUSER_WIDTH-1:0] TUSER
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_vdma_v6_2_8_axis_infrastructure_v1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8];
end
if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8];
end
if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ;
end
endgenerate
endmodule
`default_nettype wire
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : pixel panning
// File : pixel_panning.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module realizes pixel panning both in text
// and Graphics mode. THe pixel shifting to the left
// or right is based on pixel panning control signals
// and mode 13 control signals.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module pixel_panning
(
input din,
input clk, // dot clock
input clk_en, // dot clock
input [3:0] pp_ctl, // pixel panning control signals
input mode_13_ctl,
input r_n,
input by_4_syn_cclk,
output dout,
output dout_1
);
reg [8:0] shift_ff;
reg [7:0] mux_ctl; // mux control signals
wire [7:0] int_d;
wire [7:0] mux_ctl_8_f_op;
assign int_d[7] = mux_ctl[7] ? din : shift_ff[8];
assign int_d[6] = mux_ctl[6] ? din : shift_ff[7];
assign int_d[5] = mux_ctl[5] ? din : shift_ff[6];
assign int_d[4] = mux_ctl[4] ? din : shift_ff[5];
assign int_d[3] = mux_ctl[3] ? din : shift_ff[4];
assign int_d[2] = mux_ctl[2] ? din : shift_ff[3];
assign int_d[1] = mux_ctl[1] ? din : shift_ff[2];
assign int_d[0] = mux_ctl[0] ? din : shift_ff[1];
// Inferring 9 flops
always@(posedge clk or negedge r_n) begin
if(~r_n) shift_ff[8:0] <= 8'b0;
else if (clk_en) begin
shift_ff[8] <= din;
shift_ff[7] <= int_d[7];
shift_ff[6] <= int_d[6];
shift_ff[5] <= int_d[5];
shift_ff[4] <= int_d[4];
shift_ff[3] <= int_d[3];
shift_ff[2] <= int_d[2];
shift_ff[1] <= int_d[1];
shift_ff[0] <= int_d[0];
end
end
assign mux_ctl_8_f_op = mode_13_ctl ? 8'b0001_0000 : 8'b0000_0000;
// Realizing mux control signals
always @(pp_ctl or mode_13_ctl or mux_ctl_8_f_op or by_4_syn_cclk) begin
case(pp_ctl) // synopsys parallel_case
4'h0: mux_ctl = (by_4_syn_cclk) ? 8'b0000_1000 : 8'b1000_0000;
4'h1: mux_ctl = 8'b0100_0000;
4'h2: mux_ctl = (mode_13_ctl) ? 8'b0100_0000 : 8'b0010_0000;
4'h3: mux_ctl = 8'b0001_0000;
4'h4: mux_ctl = (mode_13_ctl) ? 8'b0010_0000 : 8'b0000_1000;
4'h5: mux_ctl = 8'b0000_0100;
4'h6: mux_ctl = (mode_13_ctl) ? 8'b0001_0000 : 8'b0000_0010;
4'h7: mux_ctl = 8'b0000_0001;
4'h8: mux_ctl = mux_ctl_8_f_op;
4'h9: mux_ctl = mux_ctl_8_f_op;
4'ha: mux_ctl = mux_ctl_8_f_op;
4'hb: mux_ctl = mux_ctl_8_f_op;
4'hc: mux_ctl = mux_ctl_8_f_op;
4'hd: mux_ctl = mux_ctl_8_f_op;
4'he: mux_ctl = mux_ctl_8_f_op;
4'hf: mux_ctl = mux_ctl_8_f_op;
endcase
end
assign dout = shift_ff[0];
assign dout_1 = int_d[0];
endmodule
|
// Quartus Prime Verilog Template
// Single port RAM with single read/write address and initial contents
// specified with an initial block
module phyIniCommand0_and
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
// Specify the initial contents. You can also use the $readmemb
// system task to initialize the RAM variable from a text file.
// See the $readmemb template page for details.
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps/ram_init0_and.txt", ram);
end
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; vector<int> vec[N], fenw[N]; int n, k, x[N], r[N], f[N], id[N], rev[N]; void update(int who, int p, int v) { while (p < fenw[who].size()) fenw[who][p] += v, p += p & -p; } int pref(int who, int p) { int ret = 0; while (p) ret += fenw[who][p], p -= p & -p; return ret; } inline int get(int who, int l, int r) { if (l > r) return 0; return pref(who, r) - (l ? pref(who, l - 1) : 0); } int main() { cin >> n >> k; for (int i = 1; i <= n; ++i) { scanf( %d %d %d , x + i, r + i, f + i); id[i] = i, vec[f[i]].emplace_back(i); } for (int i = 0; i < N; ++i) { if (vec[i].empty()) continue; vec[i].emplace_back(0); sort(vec[i].begin(), vec[i].end(), [](int p, int q) { return x[p] < x[q]; }); fenw[i].resize(vec[i].size(), 0); for (int j = 0; j < vec[i].size(); ++j) { rev[vec[i][j]] = j, vec[i][j] = x[vec[i][j]]; } } sort(id + 1, id + n + 1, [](int i, int j) { return r[i] > r[j]; }); long long ans = 0; for (int it = 1; it <= n; ++it) { int i = id[it]; for (int oth = max(0, f[i] - k); oth <= f[i] + k; ++oth) { if (vec[oth].empty()) continue; int lt = lower_bound(vec[oth].begin(), vec[oth].end(), x[i] - r[i]) - vec[oth].begin(); int rt = upper_bound(vec[oth].begin(), vec[oth].end(), x[i] - 1) - vec[oth].begin() - 1; ans += get(oth, lt, rt); lt = lower_bound(vec[oth].begin(), vec[oth].end(), x[i] + 1) - vec[oth].begin(); rt = upper_bound(vec[oth].begin(), vec[oth].end(), x[i] + r[i]) - vec[oth].begin() - 1; ans += get(oth, lt, rt); } update(f[i], rev[i], 1); } cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4B_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4b (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n, k, s = 0, m; vector<pair<int, int> > v(110); scanf( %d , &n); scanf( %d , &k); for (i = 0; i < n; ++i) { scanf( %d , &v[i].first); v[i].second = i + 1; } sort(v.begin(), v.begin() + n); for (i = 0; s <= k && i < n; ++i) s = s + v[i].first; m = i; if (s > k) --m; printf( %d n , m); for (i = 0; i < m; ++i) printf( %d , v[i].second); } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) constexpr auto INF = 9223372036854775807; using namespace std; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; inline long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int mod_power(long long int x, long long int y) { long long int res = 1; x = x % 1000000007; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % 1000000007; y = y >> 1; x = (x * x) % 1000000007; } return res; } long long modInverse(long long n) { return mod_power(n, 1000000007 - 2); } long long nCrModPFermat(long long n, long long int r) { if (r == 0) return 1; vector<long long int> fac(n + 1, 0); fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % 1000000007; return (fac[n] * modInverse(fac[r]) % 1000000007 * modInverse(fac[n - r]) % 1000000007) % 1000000007; } bool isprime(long long int n) { if (n == 2) return true; if (n % 2 == 0 || n == 1) { return false; } for (long long int j = 3; j <= sqrt(n); j += 2) { if (n % j == 0) { return false; } } return true; } vector<vector<long long int>> arr; vector<bool> visited; vector<long long int> out_time; vector<long long int> pre_time_vertex; vector<long long int> vertex_pre_time; vector<long long int> in_time; vector<long long int> depth; long long int cnt = 1, d = 0, cnt2 = 1; void dfs(long long int u) { pre_time_vertex[cnt] = u; vertex_pre_time[u] = cnt; in_time[u] = cnt2; cnt2++; cnt++; visited[u] = true; for (long long int i : arr[u]) { if (!visited[i]) { depth[i] = depth[u] + 1; dfs(i); } } out_time[u] = cnt2; cnt2++; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long int n, q; cin >> n >> q; vector<long long int> parent(n + 1, -1); for (long long int i = (long long int)2; i < (long long int)n + 1; i += 1) { cin >> parent[i]; } arr.resize(n + 1, vector<long long int>()); visited.resize(n + 1, false); pre_time_vertex.resize(n + 1, 0); vertex_pre_time.resize(n + 1, 0); out_time.resize(n + 1, 0); in_time.resize(n + 1, 0); depth.resize(n + 1, 0); for (long long int i = (long long int)2; i < (long long int)n + 1; i += 1) { arr[parent[i]].push_back(i); arr[i].push_back(parent[i]); } for (long long int i = (long long int)1; i < (long long int)n + 1; i += 1) { sort(arr[i].begin(), arr[i].end()); } dfs(1); for (long long int i = (long long int)0; i < (long long int)q; i += 1) { long long int u, k; cin >> u >> k; long long int req_pre = vertex_pre_time[u] + k - 1; if (k == 1) { cout << u << n ; } else if (req_pre <= n && depth[pre_time_vertex[req_pre]] > depth[u]) { long long int vertex = pre_time_vertex[req_pre]; if (out_time[u] > out_time[vertex]) cout << pre_time_vertex[req_pre] << n ; else cout << -1 << n ; } else { cout << -1 << n ; } } return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_ELU_MINodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_ELU_MINodr
// File Name: d_KES_PE_ELU_MINodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Error Locator Update module, minimum order
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_ELU_MINodr // error locate update module: minimum order
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_ELU,
input wire [`D_KES_GF_ORDER-1:0] i_delta_2im2,
output reg [`D_KES_GF_ORDER-1:0] o_v_2i_X,
output reg o_v_2i_X_deg_chk_bit,
output reg [`D_KES_GF_ORDER-1:0] o_k_2i_X
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_ELU_RST = 2'b01; // reset
parameter PE_ELU_OUT = 2'b10; // output buffer update
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_A;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X;
wire [`D_KES_GF_ORDER-1:0] w_k_2ip2_X;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_ELU_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_ELU_RST: begin
r_nxt_state <= (i_EXECUTE_PE_ELU)? (PE_ELU_OUT):(PE_ELU_RST);
end
PE_ELU_OUT: begin
r_nxt_state <= PE_ELU_RST;
end
default: begin
r_nxt_state <= PE_ELU_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ONE[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= 1;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ONE[`D_KES_GF_ORDER-1:0];
end
else begin
case (r_nxt_state)
PE_ELU_RST: begin // hold original data
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
PE_ELU_OUT: begin // output update only
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= w_v_2ip2_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= |(w_v_2ip2_X[`D_KES_GF_ORDER-1:0]);
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= w_k_2ip2_X[`D_KES_GF_ORDER-1:0];
end
default: begin
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_delta_2im2_FFM_v_2i_X (
.i_poly_form_A (i_delta_2im2[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (o_v_2i_X[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0]));
assign w_v_2ip2_X[`D_KES_GF_ORDER-1:0] = w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0];
assign w_k_2ip2_X[`D_KES_GF_ORDER-1:0] = D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
endmodule
|
module FSM_Ctrol (
input RST, // Reset maestro
input CLK, // Reloj maestro
input STM, // Iniciar multiplicacion
output reg[7:0] ENa, // Habilitaciones Ra
output reg[7:0] ENb, // Habilitaciones Rb
output reg[7:0] ENc, // Habilitaciones Rc
output reg[7:0] SEL, // Selectores Mux
output reg EOM // Fin de multiplicacion
);
reg[2:0] Qp,Qn;
always @ *
begin : Combinacional
case (Qp)
3'b000 : begin // Idle
if (STM)
Qn = 3'b001;
else
Qn = Qp;
ENa = 8'b00001111;
ENb = 8'b00001111;
ENc = 8'b00000000;
SEL = 8'b00000000;
EOM = 1'b1;
end
3'b001 : begin
Qn = 3'b010;
ENa = 8'b11110000;
ENb = 8'b11110000;
ENc = 8'b00000000;
SEL = 8'b00000000;
EOM = 1'b0;
end
3'b010 : begin
Qn = 3'b011;
ENa = 8'b01011010;
ENb = 8'b00000000;
ENc = 8'b00000000;
SEL = 8'b10010101;
EOM = 1'b0;
end
3'b011 : begin
Qn = 3'b100;
ENa = 8'b00000000;
ENb = 8'b00111100;
ENc = 8'b00000000;
SEL = 8'b01101010;
EOM = 1'b0;
end
3'b100 : begin
Qn = 3'b000;
ENa = 8'b00000000;
ENb = 8'b00000000;
ENc = 8'b11111111;
SEL = 8'b01101010;
EOM = 1'b0;
end
endcase
end
always @ (posedge RST or posedge CLK)
begin : Secuencial
if (RST)
Qp <= 0;
else
Qp <= Qn;
end
endmodule
|
Require Import JMeq ProofIrrelevance FunctionalExtensionality.
Require Export Notations SpecializedCategory Category.
Require Import Common StructureEquality FEqualDep.
Set Implicit Arguments.
Generalizable All Variables.
Set Asymmetric Patterns.
Set Universe Polymorphism.
Local Infix "==" := JMeq.
Section SpecializedFunctor.
Context `(C : @SpecializedCategory objC).
Context `(D : @SpecializedCategory objD).
(**
Quoting from the lecture notes for 18.705, Commutative Algebra:
A map of categories is known as a functor. Namely, given
categories [C] and [C'], a (covariant) functor [F : C -> C'] is a rule that assigns to
each object [A] of [C] an object [F A] of [C'] and to each map [m : A -> B] of [C] a map
[F m : F A -> F B] of [C'] preserving composition and identity; that is,
(1) [F (m' ○ m) = (F m') ○ (F m)] for maps [m : A -> B] and [m' : B -> C] of [C], and
(2) [F (id A) = id (F A)] for any object [A] of [C], where [id A] is the identity morphism of [A].
**)
Record SpecializedFunctor :=
{
ObjectOf :> objC -> objD;
MorphismOf : forall s d, C.(Morphism) s d -> D.(Morphism) (ObjectOf s) (ObjectOf d);
FCompositionOf : forall s d d' (m1 : C.(Morphism) s d) (m2: C.(Morphism) d d'),
MorphismOf _ _ (Compose m2 m1) = Compose (MorphismOf _ _ m2) (MorphismOf _ _ m1);
FIdentityOf : forall x, MorphismOf _ _ (Identity x) = Identity (ObjectOf x)
}.
End SpecializedFunctor.
Section Functor.
Variable C : Category.
Variable D : Category.
Definition Functor := SpecializedFunctor C D.
End Functor.
Bind Scope functor_scope with SpecializedFunctor.
Bind Scope functor_scope with Functor.
Create HintDb functor discriminated.
Identity Coercion Functor_SpecializedFunctor_Id : Functor >-> SpecializedFunctor.
Definition GeneralizeFunctor objC C objD D (F : @SpecializedFunctor objC C objD D) : Functor C D := F.
Coercion GeneralizeFunctor : SpecializedFunctor >-> Functor.
(* try to always unfold [GeneralizeFunctor]; it's in there
only for coercions *)
Arguments GeneralizeFunctor [objC C objD D] F /.
Hint Extern 0 => unfold GeneralizeFunctor : category functor.
Arguments SpecializedFunctor {objC} C {objD} D.
Arguments Functor C D.
Arguments ObjectOf {objC%type C%category objD%type D%category} F%functor c%object : rename, simpl nomatch.
Arguments MorphismOf {objC%type} [C%category] {objD%type} [D%category] F%functor [s%object d%object] m%morphism : rename, simpl nomatch.
Arguments FCompositionOf [objC C objD D] F _ _ _ _ _ : rename.
Arguments FIdentityOf [objC C objD D] F _ : rename.
Hint Resolve @FCompositionOf @FIdentityOf : category functor.
Hint Rewrite @FIdentityOf : category.
Hint Rewrite @FIdentityOf : functor.
Ltac functor_hideProofs :=
repeat match goal with
| [ |- context[{|
ObjectOf := _;
MorphismOf := _;
FCompositionOf := ?pf0;
FIdentityOf := ?pf1
|}] ] =>
hideProofs pf0 pf1
end.
Ltac functor_tac_abstract_trailing_props F tac :=
let F' := (eval hnf in F) in
let F'' := (tac F') in
let H := fresh in
pose F'' as H;
hnf in H;
revert H; clear; intro H; clear H;
match F'' with
| @Build_SpecializedFunctor ?objC ?C
?objD ?D
?OO
?MO
?FCO
?FIO =>
refine (@Build_SpecializedFunctor objC C objD D
OO
MO
_
_);
[ abstract exact FCO | abstract exact FIO ]
end.
Ltac functor_abstract_trailing_props F := functor_tac_abstract_trailing_props F ltac:(fun F' => F').
Ltac functor_simpl_abstract_trailing_props F := functor_tac_abstract_trailing_props F ltac:(fun F' => let F'' := eval simpl in F' in F'').
Section Functors_Equal.
Lemma Functor_contr_eq' objC C objD D (F G : @SpecializedFunctor objC C objD D)
(D_morphism_proof_irrelevance
: forall s d (m1 m2 : Morphism D s d) (pf1 pf2 : m1 = m2),
pf1 = pf2)
: forall HO : ObjectOf F = ObjectOf G,
match HO in (_ = f) return forall s d, Morphism C s d -> Morphism D (f s) (f d) with
| eq_refl => MorphismOf F
end = MorphismOf G
-> F = G.
intros.
destruct F, G; simpl in *.
subst.
f_equal;
repeat (apply functional_extensionality_dep; intro);
trivial.
Qed.
Lemma Functor_contr_eq objC C objD D (F G : @SpecializedFunctor objC C objD D)
(D_object_proof_irrelevance
: forall (x : D) (pf : x = x),
pf = eq_refl)
(D_morphism_proof_irrelevance
: forall s d (m1 m2 : Morphism D s d) (pf1 pf2 : m1 = m2),
pf1 = pf2)
: forall HO : (forall x, ObjectOf F x = ObjectOf G x),
(forall s d (m : Morphism C s d),
match HO s in (_ = y) return (Morphism D y _) with
| eq_refl =>
match HO d in (_ = y) return (Morphism D _ y) with
| eq_refl => MorphismOf F m
end
end = MorphismOf G m)
-> F = G.
intros HO HM.
apply Functor_contr_eq' with (HO := (functional_extensionality_dep F G HO));
try assumption.
repeat (apply functional_extensionality_dep; intro).
rewrite <- HM; clear HM.
generalize_eq_match.
destruct F, G; simpl in *; subst.
subst_eq_refl_dec.
reflexivity.
Qed.
Lemma Functor_eq' objC C objD D : forall (F G : @SpecializedFunctor objC C objD D),
ObjectOf F = ObjectOf G
-> MorphismOf F == MorphismOf G
-> F = G.
destruct F, G; simpl; intros; specialize_all_ways; repeat subst;
f_equal; apply proof_irrelevance.
Qed.
Lemma Functor_eq objC C objD D :
forall (F G : @SpecializedFunctor objC C objD D),
(forall x, ObjectOf F x = ObjectOf G x)
-> (forall s d m, MorphismOf F (s := s) (d := d) m == MorphismOf G (s := s) (d := d) m)
-> F = G.
intros; cut (ObjectOf F = ObjectOf G); intros; try apply Functor_eq'; destruct F, G; simpl in *; repeat subst;
try apply eq_JMeq;
repeat (apply functional_extensionality_dep; intro); trivial;
try apply JMeq_eq; trivial.
Qed.
Lemma Functor_JMeq objC C objD D objC' C' objD' D' :
forall (F : @SpecializedFunctor objC C objD D) (G : @SpecializedFunctor objC' C' objD' D'),
objC = objC'
-> objD = objD'
-> C == C'
-> D == D'
-> ObjectOf F == ObjectOf G
-> MorphismOf F == MorphismOf G
-> F == G.
simpl; intros; intuition; repeat subst; destruct F, G; simpl in *;
repeat subst; JMeq_eq.
f_equal; apply proof_irrelevance.
Qed.
End Functors_Equal.
Ltac functor_eq_step_with tac :=
structures_eq_step_with_tac ltac:(apply Functor_eq || apply Functor_JMeq) tac.
Ltac functor_eq_with tac := repeat functor_eq_step_with tac.
Ltac functor_eq_step := functor_eq_step_with idtac.
Ltac functor_eq := functor_hideProofs; functor_eq_with idtac.
Ltac functor_tac_abstract_trailing_props_with_equality_do tac F thm :=
let F' := (eval hnf in F) in
let F'' := (tac F') in
let H := fresh in
pose F'' as H;
hnf in H;
revert H; clear; intro H; clear H;
match F'' with
| @Build_SpecializedFunctor ?objC ?C
?objD ?D
?OO
?MO
?FCO
?FIO =>
let FCO' := fresh in
let FIO' := fresh in
let FCOT' := type of FCO in
let FIOT' := type of FIO in
let FCOT := (eval simpl in FCOT') in
let FIOT := (eval simpl in FIOT') in
assert (FCO' : FCOT) by abstract exact FCO;
assert (FIO' : FIOT) by (clear FCO'; abstract exact FIO);
exists (@Build_SpecializedFunctor objC C objD D
OO
MO
FCO'
FIO');
expand; abstract (apply thm; reflexivity) || (apply thm; try reflexivity)
end.
Ltac functor_tac_abstract_trailing_props_with_equality tac :=
pre_abstract_trailing_props;
match goal with
| [ |- { F0 : SpecializedFunctor _ _ | F0 = ?F } ] =>
functor_tac_abstract_trailing_props_with_equality_do tac F @Functor_eq'
| [ |- { F0 : SpecializedFunctor _ _ | F0 == ?F } ] =>
functor_tac_abstract_trailing_props_with_equality_do tac F @Functor_JMeq
end.
Ltac functor_abstract_trailing_props_with_equality := functor_tac_abstract_trailing_props_with_equality ltac:(fun F' => F').
Ltac functor_simpl_abstract_trailing_props_with_equality := functor_tac_abstract_trailing_props_with_equality ltac:(fun F' => let F'' := eval simpl in F' in F'').
Section FunctorComposition.
Context `(B : @SpecializedCategory objB).
Context `(C : @SpecializedCategory objC).
Context `(D : @SpecializedCategory objD).
Context `(E : @SpecializedCategory objE).
Variable G : SpecializedFunctor D E.
Variable F : SpecializedFunctor C D.
Definition ComposeFunctors' : SpecializedFunctor C E
:= Build_SpecializedFunctor C E
(fun c => G (F c))
(fun _ _ m => G.(MorphismOf) (F.(MorphismOf) m))
(fun _ _ _ m1 m2 =>
match FCompositionOf G _ _ _ (MorphismOf F m1) (MorphismOf F m2) with
| eq_refl =>
match
FCompositionOf F _ _ _ m1 m2 in (_ = y)
return
(MorphismOf G (MorphismOf F (Compose m2 m1)) =
MorphismOf G y)
with
| eq_refl => eq_refl
end
end)
(fun x =>
match FIdentityOf G (F x) with
| eq_refl =>
match
FIdentityOf F x in (_ = y)
return
(MorphismOf G (MorphismOf F (Identity x)) =
MorphismOf G y)
with
| eq_refl => eq_refl
end
end).
Hint Rewrite @FCompositionOf : functor.
Definition ComposeFunctors : SpecializedFunctor C E.
refine (Build_SpecializedFunctor C E
(fun c => G (F c))
(fun _ _ m => G.(MorphismOf) (F.(MorphismOf) m))
_
_);
abstract (
intros; autorewrite with functor; reflexivity
).
Defined.
End FunctorComposition.
Section IdentityFunctor.
Context `(C : @SpecializedCategory objC).
(** There is an identity functor. It does the obvious thing. *)
Definition IdentityFunctor : SpecializedFunctor C C
:= Build_SpecializedFunctor C C
(fun x => x)
(fun _ _ x => x)
(fun _ _ _ _ _ => eq_refl)
(fun _ => eq_refl).
End IdentityFunctor.
Section IdentityFunctorLemmas.
Context `(C : @SpecializedCategory objC).
Context `(D : @SpecializedCategory objD).
Lemma LeftIdentityFunctor (F : SpecializedFunctor D C) : ComposeFunctors (IdentityFunctor _) F = F.
functor_eq.
Qed.
Lemma RightIdentityFunctor (F : SpecializedFunctor C D) : ComposeFunctors F (IdentityFunctor _) = F.
functor_eq.
Qed.
End IdentityFunctorLemmas.
Hint Rewrite @LeftIdentityFunctor @RightIdentityFunctor : category.
Hint Rewrite @LeftIdentityFunctor @RightIdentityFunctor : functor.
Hint Immediate @LeftIdentityFunctor @RightIdentityFunctor : category functor.
Section FunctorCompositionLemmas.
Context `(B : @SpecializedCategory objB).
Context `(C : @SpecializedCategory objC).
Context `(D : @SpecializedCategory objD).
Context `(E : @SpecializedCategory objE).
Lemma ComposeFunctorsAssociativity (F : SpecializedFunctor B C) (G : SpecializedFunctor C D) (H : SpecializedFunctor D E) :
ComposeFunctors (ComposeFunctors H G) F = ComposeFunctors H (ComposeFunctors G F).
functor_eq.
Qed.
End FunctorCompositionLemmas.
Hint Resolve @ComposeFunctorsAssociativity : category functor.
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = n - 1; i >= 0; --i) { int temp = i % 2 != 0 ? -a[i] : a[i]; cout << temp << ; } cout << endl; } } |
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