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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_TB_V
`define SKY130_FD_SC_MS__EDFXBP_TB_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__edfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; long long bit[65], f[65][120][2]; inline long long dp(long long s, int tot, int h1, int h2) { memset(f, 0, sizeof f); f[0][0][0] = 1; int ed = log2(s); for (int i = 1; i <= ed; ++i) { long long d = (s >> i) & 1; int ed = i * 2 - 2; for (int j = 0; j <= ed; ++j) for (int k = 0; k <= 1; ++k) for (int p1 = 0; p1 <= 1; ++p1) for (int p2 = 0; p2 <= 1; ++p2) if ((i < h1 || p1 == 0) && (i < h2 || p2 == 0) && (p1 + p2 + k) % 2 == d) f[i][j + p1 + p2][(k + p1 + p2) / 2] += f[i - 1][j][k]; } return f[ed][tot][0]; } int main() { long long x, s, res, ans = 0; int ed = 0; scanf( %lld , &s); bit[0] = 1; while (bit[ed] <= s) bit[++ed] = bit[ed - 1] << 1; for (int i = 1; i <= ed; ++i) { if (bit[i] - 1 > s) break; x = s % (bit[i] - 1); for (int j = i; j >= 1; --j) if (x >= bit[j] - 1) x -= bit[j] - 1; if (!x) ++ans; } for (int h1 = 1; h1 <= ed - 1; ++h1) { for (int h2 = 1; bit[h2] - 1 <= s && h2 < ed; ++h2) { x = (s - bit[h2] + 1) / (bit[h1 + 1] + bit[h2 + 1] - 3); if (x > 0) { res = (s - bit[h2] + 1) % (bit[h1 + 1] + bit[h2 + 1] - 3); if (res == 0) { ++ans; continue; } if (h1 == 1 && h2 == 1) { ans += (s == x * 5 + 1); continue; } for (int i = 1; i <= h1 + h2; ++i) if ((res + i) % 2 == 0) ans += dp(res + i, i, h1, h2); } } } printf( %lld , ans); } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement
`timescale 1ps/1ps
module ad_intp2_4 (
clk,
data,
// outputs
intp2_0,
intp2_1,
intp2_2,
intp2_3);
input clk;
input [15:0] data;
// outputs
output [15:0] intp2_0;
output [15:0] intp2_1;
output [15:0] intp2_2;
output [15:0] intp2_3;
// internal registers
reg [15:0] data_s0 = 'd0;
reg [15:0] data_s1 = 'd0;
reg [15:0] data_s2 = 'd0;
reg [15:0] data_s3 = 'd0;
reg [15:0] data_s4 = 'd0;
reg [15:0] data_s5 = 'd0;
reg [15:0] data_s6 = 'd0;
reg [15:0] data_s7 = 'd0;
// internal signals
wire [15:0] intp2_0_s;
wire [15:0] intp2_1_s;
// delay registers
always @(posedge clk) begin
data_s0 <= data_s2;
data_s1 <= data_s3;
data_s2 <= data_s4;
data_s3 <= data_s5;
data_s4 <= data_s6;
data_s5 <= data_s7;
data_s6 <= intp2_0_s;
data_s7 <= intp2_1_s;
end
// interpolators (stage-2)
ad_mac_1 i_mac_1_0 (
.clk (clk),
.data_s0 (data_s0),
.data_s1 (data_s1),
.data_s2 (data_s2),
.data_s3 (data_s3),
.data_s4 (data_s4),
.data_s5 (data_s5),
.mac_data_0 (intp2_0),
.mac_data_1 (intp2_1));
// interpolators (stage-2)
ad_mac_1 i_mac_1_1 (
.clk (clk),
.data_s0 (data_s1),
.data_s1 (data_s2),
.data_s2 (data_s3),
.data_s3 (data_s4),
.data_s4 (data_s5),
.data_s5 (data_s6),
.mac_data_0 (intp2_2),
.mac_data_1 (intp2_3));
// interpolators (stage-1)
ad_intp2_2 i_intp2_2 (
.clk (clk),
.data (data),
.intp2_0 (intp2_0_s),
.intp2_1 (intp2_1_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[10000], i, sum = 0; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a[i]); } int maxv = a[0]; int minv = a[0]; for (i = 1; i < n; ++i) { if (maxv < a[i]) { maxv = a[i]; sum++; } else if (minv > a[i]) { minv = a[i]; sum++; } } printf( %d n , sum); } |
#include <bits/stdc++.h> using namespace std; vector<vector<int>> g; vector<int> vis, d; void dfs(int v, int c) { d[v] = c; vis[v] = true; for (int u : g[v]) { if (!vis[u]) dfs(u, c + 1); } } void solve() { int n, m; cin >> n >> m; g.resize(n + 1, vector<int>()); vis.resize(n + 1, false); d.resize(n + 1, -1); while (m--) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } dfs(1, 0); int u = max_element(d.begin(), d.end()) - d.begin(); vis.clear(); vis.resize(n + 1, false); dfs(u, 0); cout << (*max_element(d.begin(), d.end())) << n ; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int T = 1; while (T--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int const MAXN = 2e5 + 10; int n; int a[MAXN], L[MAXN * 30], R[MAXN * 30]; struct Trie { int tot = 1; int trie[MAXN * 30][2]; void insert(int pos) { int x = 1; for (int i = 30;; i--) { int dir = (a[pos] >> i) & 1; L[x] = min(L[x], pos), R[x] = max(R[x], pos); if (i < 0) break; if (!trie[x][dir]) trie[x][dir] = ++tot; x = trie[x][dir]; } return; } long long query(int x, int now, int dep) { if (dep < 0) return 0ll; int dir = (x >> dep) & 1; if (trie[now][dir]) return query(x, trie[now][dir], dep - 1); else return query(x, trie[now][dir ^ 1], dep - 1) + (1ll << dep); } long long dfs(int now, int dep) { if (dep < 0) return 0; if (trie[now][0] && trie[now][1]) { long long ans = 1ll << 30; for (int i = L[trie[now][0]]; i <= R[trie[now][0]]; i++) { ans = min(ans, (long long)query(a[i], trie[now][1], dep - 1)); } ans += dfs(trie[now][0], dep - 1); ans += dfs(trie[now][1], dep - 1); ans += (1 << dep); return ans; } else if (trie[now][0]) { return dfs(trie[now][0], dep - 1); } else if (trie[now][1]) { return dfs(trie[now][1], dep - 1); } return 0ll; } } trie; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); memset(L, 0x3f, sizeof(L)); for (int i = 1; i <= n; i++) trie.insert(i); printf( %lld n , trie.dfs(1, 30)); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxint = -1u >> 1; template <class T> bool get_max(T& a, const T& b) { return b > a ? a = b, 1 : 0; } template <class T> bool get_min(T& a, const T& b) { return b < a ? a = b, 1 : 0; } const int maxn = 1000000 + 5; int n, m, r1, r2, sv[maxn]; void output() { for (int i = n; i >= 0; i--) { for (int j = 0; j < sv[i]; j++) { printf( 7 ); } if (i) printf( 4 ); } printf( n ); } int main() { scanf( %d%d%d%d , &n, &m, &r1, &r2); memset(sv, 0, sizeof(sv)); for (int i = 1; i < n; i++) { if (r1 && r2) { if (!m) { printf( -1 n ); return 0; } else { r1--; r2--; sv[i]++; m--; } } } if (r1) { if (!m) { printf( -1 n ); return 0; } else { r1--; sv[0]++; m--; } } if (r2) { if (!m) { printf( -1 n ); return 0; } else { r2--; sv[n]++; m--; } } if (r1 + r2 != 0) { printf( -1 n ); return 0; } if (sv[0]) { sv[0] += m; } else { sv[1] += m; } output(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100000, LOG = 20; vector<vector<int>> g(N), p(N, vector<int>(LOG)); vector<int> d(N), tin(N), tout(N); int f = 1; void dfs(int u, int pr, int depth) { p[u][0] = pr; tin[u] = f++; for (int i = 1; i < LOG; i++) { p[u][i] = p[p[u][i - 1]][i - 1]; } d[u] = depth; for (auto v : g[u]) { if (v != pr) { dfs(v, u, depth + 1); } } tout[u] = f++; } bool is_ancestor(int u, int v) { return tin[u] <= tin[v] && tout[u] >= tout[v]; } int lca(int u, int v) { if (is_ancestor(u, v)) { return u; } if (is_ancestor(v, u)) { return v; } for (int i = LOG - 1; i >= 0; i--) { if (!is_ancestor(p[u][i], v)) { u = p[u][i]; } } return p[u][0]; } int dist(int u, int v) { int a = lca(u, v); return d[u] + d[v] - 2 * d[a]; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d %d , &u, &v); g[--u].push_back(--v); g[v].push_back(u); } dfs(0, 0, 0); int q; scanf( %d , &q); for (int i = 0; i < q; i++) { int a, b, x, y, k; scanf( %d %d %d %d %d , &x, &y, &a, &b, &k); --a, --b, --x, --y; int distance = dist(a, b); if (distance <= k && distance % 2 == k % 2) { puts( yes ); continue; } distance = dist(a, x) + 1; distance += dist(b, y); if (distance <= k && distance % 2 == k % 2) { puts( yes ); continue; } distance = dist(a, y) + 1; distance += dist(b, x); if (distance <= k && distance % 2 == k % 2) { puts( yes ); continue; } puts( no ); } } |
#include <bits/stdc++.h> using namespace std; const int SIZE = 20 + 5; const int Mod = 1e9 + 7; int inv[SIZE], n; long long a[SIZE], m, ans; inline long long read() { char ch = getchar(); long long f = 1, x = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } inline int Qpow(int b, int p) { long long ans = 1, t = b; for (; p; p >>= 1, t = t * t % Mod) if (p & 1) ans = ans * t % Mod; return ans % Mod; } inline int C(long long y, int x) { if (y < 0 || x < 0 || y < x) return 0; y %= Mod; if (y == 0 || x == 0) return 1; int ans = 1; for (int i = 0; i < x; i++) ans = (long long)ans * (y - i) % Mod; for (int i = 1; i <= x; i++) ans = (long long)ans * inv[i] % Mod; return ans; } int main() { for (int i = 1; i <= 20; i++) inv[i] = Qpow(i, Mod - 2); std::cin >> n >> m; for (int i = 1; i <= n; i++) a[i] = read(); for (int x = 0; x < (1 << n); x++) { if (!x) ans = (ans + C(n + m - 1, n - 1)) % Mod; else { long long t = n + m; int p = 0; for (int i = 0; i < n; i++) { if (x >> i & 1) { p++; t -= a[i + 1]; } } t -= p + 1; if (p & 1) ans = (ans - C(t, n - 1)) % Mod; else ans = (ans + C(t, n - 1)) % Mod; } } printf( %lld , (ans + Mod) % Mod); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_1_V
`define SKY130_FD_SC_MS__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_1_V
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=32 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:04:27:18:06:48:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgc6m
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [31:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [31:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [31:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 32,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgc6m
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_4_V
`define SKY130_FD_SC_LP__A221OI_4_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_4_V
|
#include <bits/stdc++.h> using namespace std; const int maxN = 100 * 1000 + 5; int Q; map<int, int> POS; struct range { int s, e; long long siz; long long mod[5]; range(int s = -1, int e = -1) : s(s), e(e) { memset(mod, 0, sizeof mod); siz = 0; } } t[1 << 18]; inline void build(int x) { if (t[x].e <= t[x].s) return; int mid = (t[x].s + t[x].e) / 2; int l = (x << 1); int r = l + 1; t[l] = range(t[x].s, mid); t[r] = range(mid + 1, t[x].e); build(l); build(r); } inline void add(int root, int pos, int val) { range &now = t[root]; now.siz++; if (now.s == now.e) { now.mod[1] = val; return; } int l = (root << 1), r = (root << 1) + 1; if (pos <= t[l].e) add(l, pos, val); else add(r, pos, val); for (int i = 0; i < 5; i++) { int tmp = (i - t[l].siz) % 5; tmp = (tmp + 5) % 5; now.mod[i] = t[l].mod[i] + t[r].mod[tmp]; } } inline void del(int root, int pos, int val) { range &now = t[root]; now.siz--; if (now.s == now.e) { now.mod[1] = 0; return; } int l = (root << 1), r = (root << 1) + 1; if (pos <= t[l].e) del(l, pos, val); else del(r, pos, val); for (int i = 0; i < 5; i++) { int tmp = (i - t[l].siz) % 5; tmp = (tmp + 5) % 5; now.mod[i] = t[l].mod[i] + t[r].mod[tmp]; } } int main() { scanf( %d , &Q); vector<pair<int, int> > qq; vector<int> num; for (int i = 1; i <= Q; i++) { char test[5]; scanf( %s , test); if (test[0] == a ) { int tmp; scanf( %d , &tmp); qq.push_back(pair<int, int>(0, tmp)); num.push_back(tmp); } else if (test[0] == d ) { int tmp; scanf( %d , &tmp); qq.push_back(pair<int, int>(1, tmp)); } else qq.push_back(pair<int, int>(2, -1)); } sort(num.begin(), num.end()); int uni = 0; for (int i = 0; i < (int)num.size(); i++) { if (POS[num[i]] == 0) POS[num[i]] = ++uni; } t[1] = range(1, uni); build(1); for (int i = 0; i < (int)qq.size(); i++) { if (qq[i].first == 0) add(1, POS[qq[i].second], qq[i].second); else if (qq[i].first == 1) del(1, POS[qq[i].second], qq[i].second); else printf( %I64d n , t[1].mod[3]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int ppr = 257; const long long INF = 2e18; const int inf = 2e9; const int mod = 1e9 + 7; const int N = 1e6 + 123; const long double pi = 3.141592653589793238462643; const int dx[] = {1, 0, -1, 0}; const int dy[] = {0, 1, 0, -1}; int n, dp[55][55][55][55], a[55][55], p[55][55]; bool u[55][55][55][55]; inline int get(int x1, int aza_ibagaliev, int x2, int y2) { return p[x2][y2] - p[x2][aza_ibagaliev - 1] - p[x1 - 1][y2] + p[x1 - 1][aza_ibagaliev - 1]; } int calc(int x1, int aza_ibagaliev, int x2, int y2) { if (u[x1][aza_ibagaliev][x2][y2]) return dp[x1][aza_ibagaliev][x2][y2]; u[x1][aza_ibagaliev][x2][y2] = 1; dp[x1][aza_ibagaliev][x2][y2] = max((x2 - x1 + 1), (y2 - aza_ibagaliev + 1)) * (get(x1, aza_ibagaliev, x2, y2) > 0); for (int i = x1; i < x2; i++) { dp[x1][aza_ibagaliev][x2][y2] = min( dp[x1][aza_ibagaliev][x2][y2], calc(x1, aza_ibagaliev, i, y2) + calc(i + 1, aza_ibagaliev, x2, y2)); } for (int i = aza_ibagaliev; i < y2; i++) { dp[x1][aza_ibagaliev][x2][y2] = min(dp[x1][aza_ibagaliev][x2][y2], calc(x1, aza_ibagaliev, x2, i) + calc(x1, i + 1, x2, y2)); } return dp[x1][aza_ibagaliev][x2][y2]; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { char c; cin >> c; a[i][j] = (c == # ); p[i][j] = p[i - 1][j] + p[i][j - 1] - p[i - 1][j - 1] + a[i][j]; } cout << calc(1, 1, n, n); return 0; } |
#include <bits/stdc++.h> using namespace std; void reverseStr(string& str); void reverseQueue(queue<int>& Queue); void print_queue(queue<int>& q); int n, a[250], sum, num; int main() { cin >> n; for (int i = 0; i < n * 2; i++) cin >> a[i]; for (int i = 0; i < n * 2; i++) { for (int j = i + 2; j < n * 2; j++) { if (a[i] == a[j]) { sum += j - i - 1; for (int l = j; l > i; l--) { swap(a[l], a[l - 1]); } } } } cout << sum; } void reverseStr(string& str) { int n = str.length(); for (int i = 0; i < n / 2; i++) swap(str[i], str[n - i - 1]); } void reverseQueue(queue<int>& Queue) { stack<int> Stack; while (!Queue.empty()) { Stack.push(Queue.front()); Queue.pop(); } while (!Stack.empty()) { Queue.push(Stack.top()); Stack.pop(); } } void print_queue(queue<int>& q) { while (!q.empty()) { cout << q.front() << ; q.pop(); } cout << endl; } |
#include <bits/stdc++.h> using namespace std; const long long int maxn = 1e3 + 2; const long long int mod = 1e3 + 2; vector<long long int> d; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, x, ans = INT_MAX; cin >> n >> x; long long int minx = x, maxx = x, a[maxn]; memset(a, 0, sizeof(a)); for (long long int i = 0; i < n; i++) { long long int start, stop; cin >> start >> stop; if (stop < start) swap(start, stop); for (long long int j = start; j <= stop; j++) ++a[j]; } for (long long int i = 0; i <= 1003; i++) if (a[i] == n) ans = min(abs(x - i), ans); if (ans == INT_MAX) cout << -1 << endl; else cout << ans << endl; return 0; } |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2016 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
#include <bits/stdc++.h> using namespace std; vector<int> E[100005]; int head, tail, A[300], B[300]; int N, M, H, T, marked[100005]; bool ok; void checkHydra(int x) { int heads = 0; for (int i = 0; i < int(E[x].size()); ++i) marked[E[x][i]] = 1, ++heads; if (heads >= H) { for (vector<int>::iterator it = E[x].begin(); it != E[x].end() && !ok; ++it) { --heads; int tails = 0; int common = 0; for (vector<int>::iterator jt = E[*it].begin(); jt != E[*it].end() && !ok; ++jt) { if (*jt == x) continue; ++tails; if (marked[*jt]) ++common; if (heads >= H && tails >= T && heads + tails - common >= H + T) { ok = true; head = x; tail = *it; } } ++heads; } } for (int i = 0; i < int(E[x].size()); ++i) marked[E[x][i]] = 0; } int main() { cin >> N >> M >> H >> T; for (int i = 0; i < M; ++i) { int x, y; cin >> x >> y; E[x].push_back(y); E[y].push_back(x); } ok = false; for (int i = 1; i <= N && !ok; ++i) checkHydra(i); if (!ok) { cout << NO ; return 0; } cout << YES n ; cout << head << << tail << n ; for (auto &it : E[head]) if (it != tail) marked[it]++; for (auto &it : E[tail]) if (it != head) marked[it]++; N = M = 0; for (auto &it : E[head]) if (marked[it] == 1) if (N < H) { A[N++] = it; marked[it] = 0; } for (auto &it : E[tail]) if (marked[it] == 1) if (M < T) { B[M++] = it; marked[it] = 0; } for (auto &it : E[head]) if (marked[it] == 2) if (N < H) { A[N++] = it; marked[it] = 0; } for (auto &it : E[tail]) if (marked[it] == 2) if (M < T) { B[M++] = it; marked[it] = 0; } for (int i = 0; i < H; ++i) cout << A[i] << ; cout << n ; for (int i = 0; i < T; ++i) cout << B[i] << ; cout << n ; } |
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.0
// \ \ Description : Xilinx Functional and Timing Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_DIFF_OUT.v
// \ \ / \ Timestamp : Tue May 26 17:09:31 PDT 2009
// \___\/\___\
//
// Revision:
// 05/26/09 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_DIFF_OUT (O, OB, IO, IOB, I, TM, TS);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
output OB;
inout IO;
inout IOB;
input I;
input TM;
input TS;
wire t1, t2;
reg DQS_BIAS_BINARY = 1'b0;
tri0 GTS = glbl.GTS;
reg O_out, OB_out;
or O1 (t1, GTS, TM);
bufif0 B1 (IO, I, t1);
or O2 (t2, GTS, TS);
notif0 N2 (IOB, I, t2);
assign O = O_out;
assign OB = OB_out;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase // case(IBUF_LOW_PWR)
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
$finish;
end
endcase
end
always @(IO or IOB or DQS_BIAS_BINARY) begin
if (IO == 1'b1 && IOB == 1'b0) begin
O_out <= IO;
OB_out <= ~IO;
end
else if (IO == 1'b0 && IOB == 1'b1) begin
O_out <= IO;
OB_out <= ~IO;
end
else if ((IO === 1'bz || IO == 1'b0) && (IOB === 1'bz || IOB == 1'b1)) begin
if (DQS_BIAS_BINARY == 1'b1) begin
O_out <= 1'b0;
OB_out <= 1'b1;
end else begin
O_out <= 1'bx;
OB_out <= 1'bx;
end
end
else begin
O_out <= 1'bx;
OB_out <= 1'bx;
end
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(TM => O) = (0:0:0, 0:0:0);
(TM => OB) = (0:0:0, 0:0:0);
(TM => IO) = (0:0:0, 0:0:0);
(TM => IOB) = (0:0:0, 0:0:0);
(TS => O) = (0:0:0, 0:0:0);
(TS => OB) = (0:0:0, 0:0:0);
(TS => IO) = (0:0:0, 0:0:0);
(TS => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => OB) = (0:0:0, 0:0:0);
(IO => IO) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => OB) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IOB => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 5/11/2010
Design Name: isolator
*******************************************************************/
`timescale 1ns/1ns
module isolator
(
//-- to/from reconfiguration-add-ons----
input rc_ackn_rr ,
output rc_ackn ,
//-- to/from producer/consumer ----
output p_prdy ,
output [31:0] p_data ,
output c_crdy ,
output c_cerr ,
input p_prdy_rr ,
input [31:0] p_data_rr ,
input c_crdy_rr ,
input c_cerr_rr ,
//-- to/from reconfiguration controller----
input is_reconfn
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
assign rc_ackn = (~is_reconfn)? 1'b1: rc_ackn_rr;
assign p_prdy = (~is_reconfn)? 1'b0: p_prdy_rr;
assign p_data = (~is_reconfn)? 32'h0: p_data_rr;
assign c_crdy = (~is_reconfn)? 1'b0: c_crdy_rr;
// set error signal to default 1'b1 to indicate that the region
// is undergoing partial reconfiguration.
assign c_cerr = (~is_reconfn)? 1'b1: c_cerr_rr;
endmodule
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: acl_int_divs.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_div32s (
enable,
clock,
denom,
numer,
quotient,
remain);
input enable;
input clock;
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] remain = sub_wire0[31:0];
wire [31:0] quotient = sub_wire1[31:0];
lpm_divide LPM_DIVIDE_component (
.clock (clock),
.clken (enable),
.denom (denom),
.numer (numer),
.remain (sub_wire0),
.quotient (sub_wire1),
.aclr (1'b0));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_pipeline = 32,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 32,
LPM_DIVIDE_component.lpm_widthn = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "FALSE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
// Retrieval info: CONNECT: remain 0 0 32 0 @remain 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> int main() { int m, n, a; scanf( %d %d , &n, &m); if (m % 2 == 0 || n % 2 == 0) printf( %d , m * n / 2); else if (n >= m) printf( %d , (n - 1) * m / 2 + (m - 1) / 2); else if (n < m) printf( %d , (m - 1) * n / 2 + (n - 1) / 2); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_8_V
`define SKY130_FD_SC_LP__EBUFN_8_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_8_V
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000007; const long long int inf = 0x3f3f3f3f3f3f3f3fLL; const double eps = 1e-9; const double PI = acos(-1); long long int i, j, k; void solve(void); inline bool equal(double a, double b) { return fabs(a - b) < eps; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout << fixed << setprecision(10); int t = 1; while (t--) solve(); return 0; } long long int m; unordered_map<long long int, long long int> f; long long int fib(long long int n) { if (n == 0) return 0; if (n == 1 || n == 2) return (f[n] = 1) % m; if (f[n]) return f[n]; long long int k = (n & 1) ? (n + 1) / 2 : n / 2; f[n] = (n & 1) ? ((fib(k) * fib(k)) % m + (fib(k - 1) * fib(k - 1)) % m) % m : (((2 * fib(k - 1)) % m + fib(k)) % m * fib(k)) % m; return f[n]; } void solve() { long long int l, r, k; cin >> m >> l >> r >> k; long long int d = (r - l) / (k - 1); while (d > 1) { if (1 + r / d - (l + d - 1) / d >= k) break; long long int N = 1 + r / d; d -= ((N * d - r) + (N - 1)) / N; } cout << fib(d) << n ; } |
//
// Paul Gao 03/2019
//
// This is an output DDR PHY
//
// Output clock is center-aligned to output data
// Theoretically clk_r_o is always centered to data_r_o, because negedge of clk_i
// has 90-degree phase delay to posedge of clk_i.
// Need output delay constraint(s) to ensure clock and data delay are same
//
// Waveform of all signals when going out of reset:
/******************************************************************************************
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
clk_i | | | | | | | | | | | | | | | | | | |
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
+--------+
reset_i |
+----------------------------------------------------------------------+
+----------------+
reset_i_r |
+--------------------------------------------------------------+
+-------+ +-------+ +-------+ +-------+
clk_r | | | | | | | |
+--------------------+ +-------+ +-------+ +-------+ +---
+-------+ +-------+ +-------+ +-------+
odd_r | | | | | | | |
+----------------+ +-------+ +-------+ +-------+ +-------
+----------------+ +-------+ +-------+ +-------+ +-------
ready_o | | | | | | | |
+-------+ +-------+ +-------+ +-------+
+--------+-----------------------------------------------------------------------
data_i | | d1d0 | | d1d0 | | d1d0 | | d1d0 | | d1d0
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
data_i_r | | d1d0 | d1d0 | d1d0 | d1d0
+----------------+---------------------------------------------------------------
+-------+ +-------+ +-------+ +---
clk_o | | | | | | |
+----------------------------+ +-------+ +-------+ +-------+
+--------------------------------+---------------+---------------+---------------
data_o | | d0 | d1 | d0 | d1 | d0 | d1 | d0
+------------------------+-------+-------+-------+-------+-------+-------+-------
******************************************************************************************/
//
// Schematic and more information: (Google Doc)
// https://docs.google.com/document/d/1lmkOxvlAvxrk_MM5W8xv3ho2DS26xbOMTCqUIyS6di8/edit?ts=5cf76063#heading=h.o6ptt6mn49us
//
//
`include "bsg_defines.v"
module bsg_link_oddr_phy
#(parameter `BSG_INV_PARAM(width_p ))
(// reset, data and ready signals synchronous to clk_i
// no valid signal required (assume valid_i is constant 1)
input reset_i
,input clk_i
,input [1:0][width_p-1:0] data_i
,output ready_o
// output clock and data
,output logic [width_p-1:0] data_r_o
,output logic clk_r_o
);
logic odd_r, clk_r, reset_i_r;
logic [1:0][width_p-1:0] data_i_r;
// ready to accept new data every two cycles
assign ready_o = ~odd_r;
// register 2x-wide input data in flops
always_ff @(posedge clk_i)
if (~odd_r)
data_i_r <= data_i;
// odd_r signal (mux select bit)
always_ff @(posedge clk_i)
if (reset_i)
odd_r <= 1'b0;
else
odd_r <= ~odd_r;
// reset_i is sync to posedge of clk_i, while clk_r is sync to negedge.
// This will potentially become critical path (only 1/2 period max delay).
// Add an extra flop for clk_r reset.
always_ff @(posedge clk_i)
reset_i_r <= reset_i;
// clock output
always_ff @(negedge clk_i)
begin
if (reset_i_r)
clk_r <= 1'b0;
else
clk_r <= ~clk_r;
// Logically, clk_o launch flop is not necessary
// Add launch flop for clk_o signal for two reasons:
// 1. Easier to center-align with data bits on ASIC (symmetric to data launch flops)
// 2. Pack-up register into IOB on FPGA
clk_r_o <= clk_r;
end
// data launch flops
// odd_r is not a reset; should not need to put a reset in here
always_ff @(posedge clk_i)
if (odd_r)
data_r_o <= data_i_r[0];
else
data_r_o <= data_i_r[1];
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_oddr_phy)
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { char c = a + i % k; cout << c; } cout << endl; } return 0; } |
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
//
//
// This file instantiates a 16 bit quadrature counter. This is primarily used to handle the output
// of a motor tach wheel encoder, linear optical encoder, or other source of quadrature signals.
//
// The main module to instantiate in a higher level file is qc16.
//
module digitalfilter(output out, input clk, input ce, input in);
reg [5:0] taps = 6'b000000;
reg result = 0;
assign out = result;
always @(posedge clk)
begin
if(ce)
begin
taps[5] <= taps[4];
taps[4] <= taps[3];
taps[3] <= taps[2];
taps[2] <= taps[1];
taps[1] <= taps[0];
taps[0] <= in;
end
if(taps[2] & taps[3] & taps[4] & taps[5])
result <= 1;
if(~taps[2] & ~taps[3] & ~taps[4] & ~taps[5])
result <= 0;
end
endmodule
//
// Convert 2 bit gray code into a series of up or down pulses one clock period wide
//
// Pulses the up output if the count direction is up, otherwise pulses the
// down output if the count direction is down. Does nothing if there was no
// change, or an invalid state
// Module to do primitive digital filtering
//
// Uses a 4 bit shift register and and output register to
// filter an incoming signal on the in pin.
//
// The first two bits of the shift register are used to synchronize
// the input signal to the clock.
// If the signa is low for 2 clock enables, the output will go low.
// If the signal is high for 2 clock enables, the output will go high
//
module graycode2(
output up,
output down,
input clk,
input freeze,
input [1:0] tach);
reg [1:0] last = 0;
reg u = 0;
reg d = 0;
wire [3:0] encodedstate;
assign encodedstate = {tach, last};
assign up = u;
assign down = d;
always @(posedge clk) begin
u <= 0;
d <= 0;
if(~freeze) begin
case(encodedstate)
4'b0000, // Do nothing states
4'b1111,
4'b1010,
4'b0101:
begin
end
4'b0100, // Increment state
4'b1101,
4'b1011,
4'b0010:
begin
last <= tach;
u <= 1;
d <= 0;
end
4'b0001, // Decrement State
4'b0111,
4'b1110,
4'b1000:
begin
last <= tach;
u <= 0;
d <= 1;
end
4'b0011, // Error states
4'b1100,
4'b0110,
4'b1001:
begin
end
default: // Catch all for bad inputs
begin
u <= 1'bx;
d <= 1'bx;
end
endcase
end
end
endmodule
//
// 16 bit synchronous up down counter
//
module udcounter16(
output [15:0] counter,
input clk,
input up,
input down);
reg [15:0] result = 16'h0000;
assign counter = result;
always@(posedge clk) begin
if(up) begin
result <= result + 1;
end
if(down) begin
result <= result - 1;
end
end
endmodule
// 16 bit quadrature counter
//
// counth output High byte of tach counter
// countl output Low byte of tach counter
// tach input 2 bit tach input
// clk input Clock
// freeze input Freezes the counter when high
// invphase input Inverts the phase of the incoming tach signals
//
module qc16(
output [7:0] counth,
output [7:0] countl,
input [1:0] tach,
input clk,
input freeze,
input invphase);
wire [15:0] counter;
wire up;
wire down;
reg [1:0] adjtach;
// Swap tach signals if invphase is true
always @(*) begin
if(invphase) begin
adjtach[0] = tach[1];
adjtach[1] = tach[0];
end
else begin
adjtach[0] = tach[0];
adjtach[1] = tach[1];
end
end
graycode2 gc2(
.clk(clk),
.freeze(freeze),
.up(up),
.down(down),
.tach(adjtach));
udcounter16 udc16(
.clk(clk),
.up(up),
.down(down),
.counter(counter));
// Assign the 16 bit counter to the high and low bytes
assign counth = counter[15:8];
assign countl = counter[7:0];
endmodule
// Top level module for this file
module tachcounter(
output [7:0] countl,
output [7:0] counth,
input clk,
input filterce,
input freeze,
input invphase,
input [1:0] tach);
wire [1:0] filttach;
qc16 q16(
.clk(clk),
.tach(filttach),
.freeze(freeze),
.invphase(invphase),
.countl(countl),
.counth(counth));
digitalfilter filterph0(
.clk(clk),
.ce(filterce),
.in(tach[0]),
.out(filttach[0]));
digitalfilter filterph1(
.clk(clk),
.ce(filterce),
.in(tach[1]),
.out(filttach[1]));
endmodule
|
//////////////////////////////////////////////////////////////////
////
////
//// AES CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa,
//// Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module aes_core
(
//OUTPUTS
output [31:0] col_out,
output [31:0] key_out,
output [31:0] iv_out,
output end_aes,
//INPUTS
input [31:0] bus_in,
input [ 3:0] iv_en,
input [ 3:0] iv_sel_rd,
input [ 3:0] key_en,
input [ 1:0] key_sel_rd,
input [ 1:0] data_type,
input [ 1:0] addr,
input [ 1:0] op_mode,
input [ 1:0] aes_mode,
input start,
input disable_core,
input write_en,
input read_en,
input first_block,
input rst_n,
input clk
);
wire [ 1:0] rk_sel;
wire [ 1:0] key_out_sel;
wire [ 3:0] round;
wire [ 2:0] sbox_sel;
wire [ 3:0] col_en_host;
wire [ 3:0] iv_en_host;
wire [ 3:0] col_en_cnt_unit;
wire [ 3:0] key_en_host;
wire [ 3:0] key_en_cnt_unit;
wire [ 1:0] col_sel;
wire key_sel;
wire bypass_rk;
wire bypass_key_en;
wire last_round;
wire iv_cnt_en;
wire iv_cnt_sel;
wire mode_ctr;
wire mode_cbc;
wire key_init;
wire key_gen;
wire [1:0] col_addr_host;
assign col_en_host = (4'b0001 << addr) & {4{write_en}};
assign col_addr_host = addr & {2{read_en}};
assign iv_en_host = iv_en;
assign key_en_host = key_en;
datapath AES_CORE_DATAPATH
(
.col_bus ( col_out ),
.key_bus ( key_out ),
.iv_bus ( iv_out ),
.bus_in ( bus_in ),
.end_aes ( end_aes ),
.data_type ( data_type ),
.rk_sel ( rk_sel ),
.key_out_sel ( key_out_sel ),
.round ( round ),
.sbox_sel ( sbox_sel ),
.iv_en ( iv_en_host ),
.iv_sel_rd ( iv_sel_rd ),
.col_en_host ( col_en_host ),
.col_en_cnt_unit ( col_en_cnt_unit ),
.key_host_en ( key_en_host ),
.key_en ( key_en_cnt_unit ),
.key_sel_rd ( key_sel_rd ),
.col_sel_host ( col_addr_host ),
.col_sel ( col_sel ),
.key_sel ( key_sel ),
.bypass_rk ( bypass_rk ),
.bypass_key_en ( bypass_key_en ),
.first_block ( first_block ),
.last_round ( last_round ),
.iv_cnt_en ( iv_cnt_en ),
.iv_cnt_sel ( iv_cnt_sel ),
.enc_dec ( enc_dec ),
.mode_ctr ( mode_ctr ),
.mode_cbc ( mode_cbc ),
.key_init ( key_init ),
.key_gen ( key_gen ),
.key_derivation_en ( key_derivation_en ),
.end_comp ( end_comp ),
.rst_n ( rst_n ),
.clk ( clk )
);
control_unit AES_CORE_CONTROL_UNIT
(
.end_comp ( end_comp ),
.sbox_sel ( sbox_sel ),
.rk_sel ( rk_sel ),
.key_out_sel ( key_out_sel ),
.col_sel ( col_sel ),
.key_en ( key_en_cnt_unit ),
.col_en ( col_en_cnt_unit ),
.round ( round ),
.bypass_rk ( bypass_rk ),
.bypass_key_en ( bypass_key_en ),
.key_sel ( key_sel ),
.last_round ( last_round ),
.iv_cnt_en ( iv_cnt_en ),
.iv_cnt_sel ( iv_cnt_sel ),
.mode_ctr ( mode_ctr ),
.mode_cbc ( mode_cbc ),
.key_init ( key_init ),
.encrypt_decrypt ( enc_dec ),
.key_gen ( key_gen ),
.operation_mode ( op_mode ),
.aes_mode ( aes_mode ),
.start ( start ),
.key_derivation_en ( key_derivation_en ),
.disable_core ( disable_core ),
.clk ( clk ),
.rst_n ( rst_n )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, k; cin >> t; while (t--) { cin >> n >> k; for (int i = 0; i < n; ++i) cout << (char)(i % k + a ); cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); for (int i = 1, j = n; i <= n / 2; ++i, --j) printf( %d %d , i, j); if (n % 2 == 1) printf( %d , n / 2 + 1); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); int n, k; std::cin >> n >> k; int64_t s1 = 0; int s2 = 0; for (int i = 0; i < k; ++i) { int a, b; std::cin >> a >> b; s1 += b; s2 = (s2 + 1ll * a * b) % n; } if (s1 > n) { std::cout << -1 << n ; } else if (s1 < n) { std::cout << 1 << n ; } else if (1ll * n * (n - 1) / 2 % n == s2) { std::cout << 1 << n ; } else { std::cout << -1 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int inv(long long int k) { long long int vl = 1000000007 - 2; long long int val = 1; long long int b = k; for (int i = 0; i < 63; i++) { if ((vl >> i) & 1) { val *= b; val %= 1000000007; } b = b * b; b %= 1000000007; } return val; } int main() { string s; cin >> s; long long int l = s.size(); vector<long long int> vr(l + 1), op(l + 1); vr[0] = 1; for (int i = 1; i <= l; i++) { vr[i] = i * vr[i - 1]; vr[i] %= 1000000007; } for (int i = 0; i < l; i++) { if (s[i] == ( ) op[i + 1]++; op[i + 1] += op[i]; } long long int ans = 0; for (int i = 0; i < l; i++) { if (s[i] == ) ) continue; long long int v = op[i + 1]; long long int v1 = op[l] - op[i + 1]; v1 = l - i - 1 - v1; if (v1 == 0) continue; long long int n = v + v1 - 1; long long int k = v; k = (vr[k] * vr[n - k]) % 1000000007; k = inv(k); k = (vr[n] * k) % 1000000007; ans += k; ans %= 1000000007; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; int n; cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; i++) cout << 400 << ; cout << endl; } } |
#include <bits/stdc++.h> long long a[100000], b[100000]; using namespace std; bool isnp(long long n, long long k, long long t) { long long magic = 0; for (long long i = 0; i < t; i++) { if (a[i] * n > b[i]) magic += a[i] * n - b[i]; if (magic > k) return false; } return true; } int32_t main() { long long n, k; cin >> n >> k; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { cin >> b[i]; } long long l = 0, r = 2000000001; while (r - l != 1) { if (isnp((r + l) / 2, k, n)) l = (r + l) / 2; else r = (r + l) / 2; } cout << l; return 0; } |
// -*- Mode: Verilog -*-
// Filename : pb_timer.v
// Description : Picoblaze Timer
// Author : Philip Tracton
// Created On : Thu May 28 22:25:06 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 28 22:25:06 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module pb_timer (/*AUTOARG*/
// Outputs
data_out, interrupt,
// Inputs
clk, reset, port_id, data_in, read_strobe, write_strobe, watchdog
) ;
parameter BASE_ADDRESS = 8'h00;
input clk;
input reset;
input [7:0] port_id;
input [7:0] data_in;
output [7:0] data_out;
input read_strobe;
input write_strobe;
output interrupt;
input watchdog;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] timer_count; // From regs of timer_regs.v
wire timer_enable; // From regs of timer_regs.v
wire timer_interrupt; // From timer0 of timer.v
wire timer_interrupt_clear; // From regs of timer_regs.v
// End of automatics
//
// Registers
//
timer_regs regs (/*AUTOINST*/
// Outputs
.data_out (data_out[7:0]),
.interrupt (interrupt),
.timer_enable (timer_enable),
.timer_count (timer_count[31:0]),
.timer_interrupt_clear(timer_interrupt_clear),
// Inputs
.clk (clk),
.reset (reset),
.port_id (port_id[7:0]),
.data_in (data_in[7:0]),
.read_strobe (read_strobe),
.write_strobe (write_strobe),
.timer_interrupt (timer_interrupt));
//
// Timer
//
timer timer0(/*AUTOINST*/
// Outputs
.timer_interrupt (timer_interrupt),
// Inputs
.clk (clk),
.timer_count (timer_count[31:0]),
.timer_enable (timer_enable),
.timer_interrupt_clear (timer_interrupt_clear));
endmodule // pb_timer
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; const int N = 1e5 + 10, INF = 0x3f3f3f3f, MOD = 1e9 + 7; int n, a[55][55], ans[55]; int main() { ios_base::sync_with_stdio(0); while (scanf( %d , &n) == 1) { for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) scanf( %d , &a[i][j]); for (int i = 1; i <= n; ++i) { set<int> s; for (int j = 1; j <= n; ++j) s.insert(a[i][j]); if (s.size() != n) continue; for (int j = 1; j <= n; ++j) ans[j] = a[i][j] ? a[i][j] : n; bool ok = true; for (int j = 1; j <= n; ++j) { for (int k = 1; k <= n; ++k) { if (j == k) continue; if (min(ans[j], ans[k]) != a[j][k]) { ok = false; break; } } if (!ok) break; } if (ok) break; } for (int i = 1; i <= n; ++i) printf( %d%c , ans[i], n [i == n]); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long N, K, L, R; long long G, A; long long ans; void run(int use, long long ntot) { if (N <= 500000) { for (int nplus = 0; nplus <= N - 1; nplus++) { long long rr = (N + nplus + use); long long rv = G + (1 + use); long long nbefore = ((ntot - rv) % rr + rr) % rr; long long nafter = nplus - nbefore; if (nbefore >= 0 && nbefore <= G && nafter >= 0 && nafter <= A) ans = max(ans, (long long)nplus + use); } } else { if (G + 1 + use <= ntot) { long long rv = ntot - G - 1 - use; if (rv <= G) ans = max(ans, rv + use + A); } for (int nrun = 1; nrun * N <= ntot; nrun++) { long long nstart = (nrun * (N + use)) + (G + 1 + use); long long nleft = ntot - nstart; if (nleft >= 0) { long long nbefore = nleft % nrun; long long nafter = (nleft - ((nrun + 1) * (nbefore))) / nrun; if (nafter > A) { long long ndrop = (nafter - A + nrun) / (nrun + 1); nafter -= ndrop * (nrun + 1); nbefore += ndrop * nrun; } if (nafter >= 0 && nafter <= A && nbefore >= 0 && nbefore <= G) ans = max(ans, nbefore + nafter + use); } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> N >> L >> R >> K; G = (R - L + N) % N; A = (N - 1 - G); ans = -1; for (int i = 0; i <= 1; i++) { for (int j = 0; j <= i; j++) { run(i, K + j); } } cout << ans << n ; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
data_out,
// Inputs
wr, wa, rst_l, rd, ra, data_in, clk
);
input clk;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] data_in; // To sub of reg_1r1w.v
input [7:0] ra; // To sub of reg_1r1w.v
input rd; // To sub of reg_1r1w.v
input rst_l; // To sub of reg_1r1w.v
input [7:0] wa; // To sub of reg_1r1w.v
input wr; // To sub of reg_1r1w.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] data_out; // From sub of reg_1r1w.v
// End of automatics
reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8))
sub
(/*AUTOINST*/
// Outputs
.data_out (data_out[31:0]),
// Inputs
.data_in (data_in[31:0]),
.ra (ra[7:0]),
.wa (wa[7:0]),
.wr (wr),
.rd (rd),
.clk (clk),
.rst_l (rst_l));
endmodule
module reg_1r1w
#(
parameter WIDTH=32,
parameter ADRWID=10,
parameter DEPTH=1024,
parameter RST=0
)
(/*AUTOARG*/
// Outputs
data_out,
// Inputs
data_in, ra, wa, wr, rd, clk, rst_l
);
input [WIDTH-1:0] data_in;
input [ADRWID-1:0] ra;
input [ADRWID-1:0] wa;
input wr;
input rd;
input clk;
input rst_l;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] array [0:DEPTH-1];
reg [ADRWID-1:0] ra_r, wa_r;
reg [WIDTH-1:0] data_in_r;
reg wr_r;
reg rd_r;
integer x;
// Message 679
always @(posedge clk) begin
int tmp = x + 1;
if (tmp !== x + 1) $stop;
end
always @(posedge clk or negedge rst_l) begin
if (!rst_l) begin
for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE
if (RST == 1) begin
array[x] <= 0;
end
end
ra_r <= 0;
wa_r <= 0;
wr_r <= 0;
rd_r <= 0;
data_in_r <= 0;
end
else begin
ra_r <= ra;
wa_r <= wa;
wr_r <= wr;
rd_r <= rd;
data_in_r <= data_in;
if (wr_r) array[wa_r] <= data_in_r;
end
end
endmodule
// Local Variables:
// verilog-auto-inst-param-value: t
// End:
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 5; int a[maxn], n, x; int main() { int k; cin >> k; while (k--) { cin >> n >> x; int sum = 0; bool f = 1, f1 = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; if (a[i] != x) f = 0; if (a[i] == x) f1 = 1; } if (f == 1) cout << 0 << endl; else if (sum == n * x || f1 == 1) cout << 1 << endl; else cout << 2 << endl; } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : pcie_gt_wrapper_top.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
// Description : Top-level wrapper for Rocket IO Transceivers that
// instantiates GTP/GTX transceivers based upon the Virtex-5 family chosen
//
//-----------------------------------------------------------------------------
module pcie_gt_wrapper_top #
(
parameter NO_OF_LANES = 1,
parameter SIM = 0,
parameter USE_V5FXT = 0,
parameter REF_CLK_FREQ = 1, // use 0 or 1
parameter TXDIFFBOOST = "FALSE",
parameter GTDEBUGPORTS = 0
)
(
output wire [7:0] gt_rx_elec_idle,
output wire [23:0] gt_rx_status,
output wire [63:0] gt_rx_data,
output wire [7:0] gt_rx_phy_status,
output wire [7:0] gt_rx_data_k,
output wire [7:0] gt_rx_valid,
output wire [7:0] gt_rx_chanisaligned,
input wire [NO_OF_LANES-1:0] gt_rx_n,
input wire [NO_OF_LANES-1:0] gt_rx_p,
output wire [NO_OF_LANES-1:0] gt_tx_n,
output wire [NO_OF_LANES-1:0] gt_tx_p,
input wire [63:0] gt_tx_data,
input wire [7:0] gt_tx_data_k,
input wire [7:0] gt_tx_elec_idle,
input wire [7:0] gt_tx_detect_rx_loopback,
input wire [7:0] gt_tx_compliance,
input wire [7:0] gt_rx_polarity,
input wire [15:0] gt_power_down,
input wire [7:0] gt_deskew_lanes,
input wire [7:0] gt_pipe_reset,
input wire [7:0] gt_rx_present,
input wire gsr,
input wire gtreset,
input wire refclk,
output wire refclkout_bufg,
output wire gtclk_bufg,
output wire [7:0] resetdone,
output wire [3:0] plllkdet_out,
input wire gt_usrclk,
input wire gt_usrclk2,
input wire txsync_clk,
output wire [7:0] rxbyteisaligned,
output wire [7:0] rxchanbondseq,
output wire pcie_reset,
input wire clock_lock,
input wire trn_lnk_up_n,
// GTP register ports
input wire gt_dclk,
input wire [NO_OF_LANES*7-1:0] gt_daddr,
input wire [NO_OF_LANES-1:0] gt_den,
input wire [NO_OF_LANES-1:0] gt_dwen,
input wire [NO_OF_LANES*16-1:0] gt_di,
output wire [NO_OF_LANES*16-1:0] gt_do,
output wire [NO_OF_LANES-1:0] gt_drdy,
input wire [2:0] gt_txdiffctrl_0,
input wire [2:0] gt_txdiffctrl_1,
input wire [2:0] gt_txbuffctrl_0,
input wire [2:0] gt_txbuffctrl_1,
input wire [2:0] gt_txpreemphesis_0,
input wire [2:0] gt_txpreemphesis_1
);
generate
// Instantiate wrapper for Rocket IO GTX transceivers if V5 FXT is used,
// else instantiate wrapper for Rocket IO GTP transceivers
if (USE_V5FXT == 0) begin
pcie_gt_wrapper#
(
.NO_OF_LANES(NO_OF_LANES),
.SIM(SIM),
// REF_CLK_FREQ is 0 for 100 MHz, 1 for 250 MHz
.PLL_DIVSEL_FB(REF_CLK_FREQ ? 1 : 5),
.PLL_DIVSEL_REF(REF_CLK_FREQ ? 1 : 2),
.CLK25_DIVIDER(REF_CLK_FREQ ? 10 : 4),
.TXDIFFBOOST(TXDIFFBOOST)
)
pcie_gt_wrapper_i
(
.gt_rx_elec_idle (gt_rx_elec_idle),
.gt_rx_status (gt_rx_status),
.gt_rx_data (gt_rx_data),
.gt_rx_phy_status (gt_rx_phy_status),
.gt_rx_data_k (gt_rx_data_k),
.gt_rx_valid (gt_rx_valid),
.gt_rx_chanisaligned (gt_rx_chanisaligned),
.gt_rx_n (gt_rx_n),
.gt_rx_p (gt_rx_p),
.gt_tx_n (gt_tx_n),
.gt_tx_p (gt_tx_p),
.gt_tx_data (gt_tx_data),
.gt_tx_data_k (gt_tx_data_k),
.gt_tx_elec_idle (gt_tx_elec_idle),
.gt_tx_detect_rx_loopback(gt_tx_detect_rx_loopback),
.gt_tx_compliance (gt_tx_compliance),
.gt_rx_polarity (gt_rx_polarity),
.gt_power_down (gt_power_down),
.gt_deskew_lanes (gt_deskew_lanes),
.gt_pipe_reset (gt_pipe_reset),
.gt_rx_present (gt_rx_present),
.gsr (gsr),
.gtreset (gtreset),
.refclk (refclk),
.refclkout_bufg (refclkout_bufg),
.gtclk_bufg (gtclk_bufg),
.plllkdet_out (plllkdet_out),
.resetdone (resetdone),
.gt_usrclk (gt_usrclk2),
.rxbyteisaligned (rxbyteisaligned),
.rxchanbondseq (rxchanbondseq),
.pcie_reset (pcie_reset),
.clock_lock (clock_lock),
// GTP register ports
.gt_dclk (gt_dclk),
.gt_daddr (gt_daddr),
.gt_den (gt_den),
.gt_dwen (gt_dwen),
.gt_di (gt_di),
.gt_do (gt_do),
.gt_drdy (gt_drdy),
.gt_txdiffctrl_0 (gt_txdiffctrl_0),
.gt_txdiffctrl_1 (gt_txdiffctrl_1),
.gt_txbuffctrl_0 (gt_txbuffctrl_0),
.gt_txbuffctrl_1 (gt_txbuffctrl_1),
.gt_txpreemphesis_0 (gt_txpreemphesis_0),
.gt_txpreemphesis_1 (gt_txpreemphesis_1)
);
end else begin
pcie_gtx_wrapper#
(
.NO_OF_LANES(NO_OF_LANES),
.SIM(SIM),
.PLL_DIVSEL_FB(REF_CLK_FREQ ? 2 : 5), // REF_CLK_FREQ is 0 for 100 MHz, 1 for 250 MHz
.PLL_DIVSEL_REF(REF_CLK_FREQ ? 1 : 1),
.CLK25_DIVIDER(REF_CLK_FREQ ? 10 : 4),
.TXDIFFBOOST(TXDIFFBOOST),
.GTDEBUGPORTS(GTDEBUGPORTS)
)
pcie_gt_wrapper_i
(
.gt_rx_elec_idle (gt_rx_elec_idle),
.gt_rx_status (gt_rx_status),
.gt_rx_data (gt_rx_data),
.gt_rx_phy_status (gt_rx_phy_status),
.gt_rx_data_k (gt_rx_data_k),
.gt_rx_valid (gt_rx_valid),
.gt_rx_chanisaligned (gt_rx_chanisaligned),
.gt_rx_n (gt_rx_n),
.gt_rx_p (gt_rx_p),
.gt_tx_n (gt_tx_n),
.gt_tx_p (gt_tx_p),
.gt_tx_data (gt_tx_data),
.gt_tx_data_k (gt_tx_data_k),
.gt_tx_elec_idle (gt_tx_elec_idle),
.gt_tx_detect_rx_loopback(gt_tx_detect_rx_loopback),
.gt_tx_compliance (gt_tx_compliance),
.gt_rx_polarity (gt_rx_polarity),
.gt_power_down (gt_power_down),
.gt_deskew_lanes (gt_deskew_lanes),
.gt_pipe_reset (gt_pipe_reset),
.gt_rx_present (gt_rx_present),
.gsr (gsr),
.gtreset (gtreset),
.refclk (refclk),
.refclkout_bufg (refclkout_bufg),
.gtclk_bufg (gtclk_bufg),
.plllkdet_out (plllkdet_out),
.resetdone (resetdone),
.gt_usrclk (gt_usrclk),
.gt_usrclk2 (gt_usrclk2),
.txsync_clk (txsync_clk),
.rxbyteisaligned (rxbyteisaligned),
.rxchanbondseq (rxchanbondseq),
.pcie_reset (pcie_reset),
.clock_lock (clock_lock),
.trn_lnk_up_n (trn_lnk_up_n),
// GTP register ports
.gt_dclk (gt_dclk),
.gt_daddr (gt_daddr),
.gt_den (gt_den),
.gt_dwen (gt_dwen),
.gt_di (gt_di),
.gt_do (gt_do),
.gt_drdy (gt_drdy),
.gt_txdiffctrl_0 (gt_txdiffctrl_0),
.gt_txdiffctrl_1 (gt_txdiffctrl_1),
.gt_txbuffctrl_0 (gt_txbuffctrl_0),
.gt_txbuffctrl_1 (gt_txbuffctrl_1),
.gt_txpreemphesis_0 (gt_txpreemphesis_0),
.gt_txpreemphesis_1 (gt_txpreemphesis_1)
);
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %Version
// \ \ Application: MIG
// / / Filename: circ_buffer.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:33 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Circular Buffer for synchronizing signals between clock domains. Assumes
// write and read clocks are the same frequency (but can be varying phase).
// Parameter List;
// DATA_WIDTH: # bits in data bus
// BUF_DEPTH: # of entries in circular buffer.
// Port list:
// rdata: read data
// wdata: write data
// rclk: read clock
// wclk: write clock
// rst: reset - shared between read and write sides
//Reference:
//Revision History:
// Rev 1.1 - Initial Checkin - jlogue 03/06/09
//*****************************************************************************
/******************************************************************************
**$Id: circ_buffer.v,v 1.2 2010/02/26 08:58:33 pboya Exp $
**$Date: 2010/02/26 08:58:33 $
**$Author: pboya $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/circ_buffer.v,v $
******************************************************************************/
`timescale 1ps/1ps
module circ_buffer #
(
parameter TCQ = 100,
parameter BUF_DEPTH = 5, // valid values are 5, 6, 7, and 8
parameter DATA_WIDTH = 1
)
(
output[DATA_WIDTH-1:0] rdata,
input [DATA_WIDTH-1:0] wdata,
input rclk,
input wclk,
input rst
);
//***************************************************************************
// Local parameters
//***************************************************************************
localparam SHFTR_MSB = (BUF_DEPTH-1)/2;
//***************************************************************************
// Internal signals
//***************************************************************************
reg SyncResetRd;
reg [SHFTR_MSB:0] RdCEshftr;
reg [2:0] RdAdrsCntr;
reg SyncResetWt;
reg WtAdrsCntr_ce;
reg [2:0] WtAdrsCntr;
//***************************************************************************
// read domain registers
//***************************************************************************
always @(posedge rclk or posedge rst)
if (rst) SyncResetRd <= #TCQ 1'b1;
else SyncResetRd <= #TCQ 1'b0;
always @(posedge rclk or posedge SyncResetRd)
begin
if (SyncResetRd)
begin
RdCEshftr <= #TCQ 'b0;
RdAdrsCntr <= #TCQ 'b0;
end
else
begin
RdCEshftr <= #TCQ {RdCEshftr[SHFTR_MSB-1:0], WtAdrsCntr_ce};
if(RdCEshftr[SHFTR_MSB])
begin
if(RdAdrsCntr == (BUF_DEPTH-1)) RdAdrsCntr <= #TCQ 'b0;
else RdAdrsCntr <= #TCQ RdAdrsCntr + 1;
end
end
end
//***************************************************************************
// write domain registers
//***************************************************************************
always @(posedge wclk or posedge SyncResetRd)
if (SyncResetRd) SyncResetWt <= #TCQ 1'b1;
else SyncResetWt <= #TCQ 1'b0;
always @(posedge wclk or posedge SyncResetWt)
begin
if (SyncResetWt)
begin
WtAdrsCntr_ce <= #TCQ 1'b0;
WtAdrsCntr <= #TCQ 'b0;
end
else
begin
WtAdrsCntr_ce <= #TCQ 1'b1;
if(WtAdrsCntr_ce)
begin
if(WtAdrsCntr == (BUF_DEPTH-1)) WtAdrsCntr <= #TCQ 'b0;
else WtAdrsCntr <= #TCQ WtAdrsCntr + 1;
end
end
end
//***************************************************************************
// instantiate one RAM64X1D for each data bit
//***************************************************************************
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i = i+1) begin: gen_ram
RAM64X1D #
(
.INIT (64'h0000000000000000)
)
u_RAM64X1D
(.DPO (rdata[i]),
.SPO (),
.A0 (WtAdrsCntr[0]),
.A1 (WtAdrsCntr[1]),
.A2 (WtAdrsCntr[2]),
.A3 (1'b0),
.A4 (1'b0),
.A5 (1'b0),
.D (wdata[i]),
.DPRA0 (RdAdrsCntr[0]),
.DPRA1 (RdAdrsCntr[1]),
.DPRA2 (RdAdrsCntr[2]),
.DPRA3 (1'b0),
.DPRA4 (1'b0),
.DPRA5 (1'b0),
.WCLK (wclk),
.WE (1'b1)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500001; const int sqN = 708; int ans[N]; int fre[N]; int v[N]; int block[sqN]; int answer = 0; struct query { int l; int r; int idx; } Q[N]; bool comp(query &q1, query &q2) { if (q1.l / sqN != q2.l / sqN) { return q1.l < q2.l; } if ((q1.l / sqN) & 1) { return q1.r < q2.r; } return q1.r > q2.r; } inline void add(int idx) { int val = v[idx]; fre[val]++; if (fre[val] == 1) { answer++; block[val / sqN]++; } if (fre[val] == 2) { answer--; block[val / sqN]--; } } inline void rem(int idx) { int val = v[idx]; fre[val]--; if (fre[val] == 1) { answer++; block[val / sqN]++; } if (fre[val] == 0) { answer--; block[val / sqN]--; } } inline int solve() { if (answer == 0) { return 0; } for (int i = 0; i < sqN; i++) { if (block[i] > 0) { for (int j = i * sqN; j < i * sqN + sqN; j++) { if (fre[j] == 1) { return j; } } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> v[i]; } int q, l, r; cin >> q; for (int i = 0; i < q; i++) { cin >> l >> r; l--; r--; Q[i].l = l; Q[i].r = r; Q[i].idx = i; } sort(Q, Q + q, comp); l = 0, r = -1; for (int i = 0; i < q; i++) { int L = Q[i].l; int R = Q[i].r; while (l < L) { rem(l); l++; } while (l > L) { l--; add(l); } while (r < R) { r++; add(r); } while (r > R) { rem(r); r--; } ans[Q[i].idx] = solve(); } for (int i = 0; i < q; i++) { cout << ans[i] << n ; } return 0; } |
//----------------------------------------------------------------------------
//-- Memoria ROM genérica
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Memoria con los siguientes parametros:
//-- * AW: Numero de bits de las direcciones
//-- * DW: Numero de bits de los datos
//-- * ROMFILE: Fichero a usar para cargar la memoria
//--
//-- Con este componente podemos hacer memorias rom de cualquier tamaño
//----------------------------------------------------------------------------
module genrom #( //-- Parametros
parameter AW = 5, //-- Bits de las direcciones (Adress width)
parameter DW = 4) //-- Bits de los datos (Data witdh)
( //-- Puertos
input clk, //-- Señal de reloj global
input wire [AW-1: 0] addr, //-- Direcciones
output reg [DW-1: 0] data); //-- Dato de salida
//-- Parametro: Nombre del fichero con el contenido de la ROM
parameter ROMFILE = "rom1.list";
//-- Calcular el numero de posiciones totales de memoria
localparam NPOS = 2 ** AW;
//-- Memoria
reg [DW-1: 0] rom [0: NPOS-1];
//-- Lectura de la memoria
always @(posedge clk) begin
data <= rom[addr];
end
//-- Cargar en la memoria el fichero ROMFILE
//-- Los valores deben estan dados en hexadecimal
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
|
/*
Code for Setting up ADF4158 PLL Module
By Hsiang-Yi Chung
February, 2016
*/
module PLL_ADF4158(
input clk,
input reset_n,
output reg writeData,
output reg loadEnable,
output pll_clk
);
localparam s0 = 2'b00;
localparam s1 = 2'b01;
localparam s2 = 2'b10;
localparam s3 = 2'b11;
localparam num_registers_to_set = 8;
reg [31:0] writeDataArray [num_registers_to_set - 1:0];
reg [31:0] current_register;
reg [1:0] nextState, state;
reg [4:0] bit_counter;
reg [2:0] register_counter;
reg dec_register_counter, dec_bit_counter;
assign pll_clk = clk;
initial begin
state = s0;
bit_counter = 31;
register_counter = num_registers_to_set - 1;
dec_register_counter = 0;
dec_bit_counter = 0;
loadEnable = 0;
writeDataArray[0] = 32'b1_0000_000011000110_000000000000_000; //reg 0
writeDataArray[1] = 32'b0000_0000000000000_000000000000_001; //reg 1
writeDataArray[2] = 32'b000_0_1111_0_1_1_0_00001_000000000001_010; //reg 2
writeDataArray[3] = 32'b0000000000000000_1_0_00_01_0_0_0_0_0_0_0_011; //reg 3
writeDataArray[4] = 32'b0_00000_0_11_00_11_000000000001_0000_100; //reg 4
writeDataArray[5] = 32'b00_0_0_00_0_0_0_0000_0010010101110010_101; //reg 5 DEV SEL = 0
writeDataArray[6] = 32'b00000000_0_00000011011010110000_110; //reg 6 STEP SEL = 0
writeDataArray[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0_111; //reg 7
end
always @ (negedge clk) begin
if(!reset_n) begin
state <= s0;
end
else begin
state <= nextState;
end
end
always @(negedge clk) begin
if(dec_register_counter == 1) begin
register_counter <= register_counter - 1;
end
if(dec_bit_counter == 1) begin
bit_counter <= bit_counter - 1;
end
end
always @ * begin
dec_bit_counter = 0;
dec_register_counter = 0;
loadEnable = 0;
current_register = writeDataArray[register_counter];
writeData = current_register[bit_counter];
case(state)
s0: begin
dec_bit_counter = 1;
nextState = s1;
end
s1: begin
if(bit_counter == 0) begin
nextState = s2;
end else begin
nextState = s1;
dec_bit_counter = 1;
end
end
s2: begin
loadEnable = 1;
if(register_counter != 0) begin
nextState = s0;
dec_register_counter = 1;
dec_bit_counter = 1;
end else begin
nextState = s3;
end
end
s3: begin
nextState = s3;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 10; int n, q, a[maxn], bit[maxn][22] = {0}, pos[maxn][22] = {0}; int main() { int i, j, l, r; ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; l = i, r = a[i]; for (j = 20; j >= 0; j--) bit[i][j] = bit[i - 1][j], pos[i][j] = pos[i - 1][j]; for (j = 20; j >= 0; j--) if (r & (1 << j)) { if (bit[i][j] == 0) { bit[i][j] = r, pos[i][j] = l; break; } if (l > pos[i][j]) { swap(l, pos[i][j]); swap(r, bit[i][j]); } r ^= bit[i][j]; } } cin >> q; while (q--) { cin >> l >> r; int num = 0; for (i = 20; i >= 0; i--) if ((num ^ bit[r][i]) > num && pos[r][i] >= l) num ^= bit[r][i]; cout << num << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { if (i % 2 == 0 && j % 2 == 0 || i % 2 == 1 && j % 2 == 1) cout << W ; else cout << B ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; void read(long long a = 0) { freopen( in , r , stdin); if (a) freopen( out , w , stdout); } vector<vector<pair<long long, long long> > > ad; long long over; long long dfs(long long a) { over = a; if (ad[a].size() == 0) return 1000000007; return min(ad[a][0].second, dfs(ad[a][0].first)); } int main() { long long n; cin >> n; long long m; ad = vector<vector<pair<long long, long long> > >(n + 1); cin >> m; bool vis[10000] = {}, good[10000] = {}; while (m--) { long long x, y, d; cin >> x >> y >> d; x--, y--; vis[y] = 1; good[x] = 1; ad[x].push_back(make_pair(y, d)); } vector<pair<pair<long long, long long>, long long> > ans; for (int i = 0; i < n; i++) { if (!vis[i] && good[i]) { pair<pair<long long, long long>, long long> tmp; tmp.first.first = i; tmp.second = dfs(i); tmp.first.second = over; ans.push_back(tmp); } } sort(ans.begin(), ans.end()); cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) cout << ans[i].first.first + 1 << << ans[i].first.second + 1 << << ans[i].second << n ; } |
//${SDB_NAME}.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:${SDB_VENDOR_ID}
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:${SDB_DEVICE_ID}
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:${SDB_CORE_VERSION}
Set the Device Name: 19 UNICODE characters
SDB_NAME:${SDB_NAME}
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:${SDB_ABI_CLASS}
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:${SDB_ABI_VERSION_MAJOR}
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:${SDB_ABI_VERSION_MINOR}
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:${SDB_MODULE_URL}
Set the date of module YYYY/MM/DD
SDB_DATE:${SDB_DATE}
Device is executable (True/False)
SDB_EXECUTABLE:${SDB_EXECUTABLE}
Device is readable (True/False)
SDB_READABLE:${SDB_READABLE}
Device is writeable (True/False)
SDB_WRITEABLE:${SDB_WRITEABLE}
Device Size: Number of Registers
SDB_SIZE:${SDB_SIZE}
*/
module ${SDB_NAME} (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_0);
o_wbs_dat <= ADDR_0;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, n, m, mis, cri; int main() { cin >> a; for (int i = 0; i < a; i++) { cin >> n >> m; if (n > m) { mis++; } else if (n < m) { cri++; } } if (mis > cri) { cout << Mishka ; } else if (cri > mis) { cout << Chris ; } else { cout << Friendship is magic!^^ ; } } |
#include <bits/stdc++.h> using namespace std; string s; int main() { int n, a, b, k; scanf( %d%d%d%d , &n, &a, &b, &k); int tot = 0; cin >> s; int prev = -1; for (int i = 0; i < n; i++) if (s[i] == 1 ) { tot += (i - prev - 1) / b; prev = i; } tot += (n - prev - 1) / b; int ans = tot - a + 1; printf( %d n , ans); int cnt = 0; for (int i = 0; i < n; i++) { if (s[i] == 1 ) { cnt = 0; } else { cnt++; } if (cnt == b && ans) { ans--; printf( %d , i + 1); cnt = 0; } } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t, sum = 0, x; cin >> n >> x; while (n--) { cin >> t; sum += t; } if (sum < 0) sum *= -1; int ans = sum / x + bool(sum % x); cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, a[100010]; int la, ra; void update(int i, int delta) { for (; i < n; i = i | (i + 1)) { a[i] += delta; } } int get(int fr, int to) { int res = 0; for (int i = to; i >= 0; i = (i & (i + 1)) - 1) { res += a[i]; } for (int i = fr - 1; i >= 0; i = (i & (i + 1)) - 1) { res -= a[i]; } return res; } int main(void) { int q; scanf( %d%d , &n, &q); for (int i = 0; i < n; ++i) { update(i, 1); } int la = 0; int ra = n; for (int i = 0; i < q; ++i) { int t; scanf( %d , &t); if (t == 1) { int p, len, mid; scanf( %d , &p); if (la < ra) { len = ra - la; mid = la + p; } else { len = la - ra; mid = la - p; } if (p > len / 2) { swap(la, ra); p = len - p; } if (la < ra) { for (int i = 0; i < p; ++i) { update(mid + i, get(mid - 1 - i, mid - 1 - i)); } } else { for (int i = 0; i < p; ++i) { update(mid - 1 - i, get(mid + i, mid + i)); } } la = mid; } else { int l, r; scanf( %d%d , &l, &r); if (la < ra) { l += la; r += la; } else { l = la - l; r = la - r; swap(l, r); } printf( %d n , get(l, r - 1)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; set<string> normal; set<string> grumpy; void build_normal() { normal.insert( great! ); normal.insert( don t think so ); normal.insert( don t touch me ); normal.insert( not bad ); normal.insert( cool ); } void build_grumpy() { grumpy.insert( no way ); grumpy.insert( don t even ); grumpy.insert( are you serious? ); grumpy.insert( go die in a hole ); grumpy.insert( worse ); grumpy.insert( terrible ); } int main() { build_normal(); build_grumpy(); for (int i = 0; i < 10; i++) { cout << i << endl; string s; getline(cin, s); if (normal.count(s)) { cout << normal << endl; return 0; } else if (grumpy.count(s)) { cout << grumpy << endl; return 0; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_TB_V
`define SKY130_FD_SC_HS__EDFXBP_TB_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__edfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 DE = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 DE = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 DE = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 DE = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_TB_V
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for renderer.
`include "registers.vh"
`include "tile_registers.vh"
`include "sprite_registers.vh"
`define DISPLAY_HCOUNT_WIDTH 10
`define DISPLAY_VCOUNT_WIDTH 10
module Renderer_Test;
reg clk; // System clock
reg reset; // System reset
wire [`DISPLAY_HCOUNT_WIDTH-1:0] h_pos;
wire [`DISPLAY_VCOUNT_WIDTH-1:0] v_pos;
DisplayController #(.HCOUNT_WIDTH(`DISPLAY_HCOUNT_WIDTH),
.VCOUNT_WIDTH(`DISPLAY_VCOUNT_WIDTH))
display(.clk(clk),
.reset(reset),
.v_pos(v_pos),
.h_pos(h_pos));
wire h_sync, v_sync;
reg [127:0] spr_values [255:0];
reg [127:0] spr_data;
reg [127:0] spr_data_reg;
wire [7:0] spr_addr;
wire spr_clk;
// Simulate the reading of sprite RAM.
always @ (posedge spr_clk)
spr_data <= spr_values[spr_addr];
// Renderer
Renderer renderer(.clk(clk),
.reset(reset),
.reg_values(0),
.tile_reg_values(0),
.spr_clk(spr_clk),
.spr_addr(spr_addr),
.spr_data(spr_data),
.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(h_sync),
.v_sync(v_sync));
// Generate clock.
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
// Reset
#5 reset = 1;
#1 reset = 0;
// Set up sprite register values.
for (i = 0; i < `NUM_SPRITES; i = i + 1) begin
if (i < 4) begin
// Enable the first four registers.
spr_values[i * 2] = 1 | ((15-i)) << 16;
// Also give them x/y offsets.
spr_values[i * 2 + 1] = (i * 8) | ((i * 8) << 16);
end else begin
spr_values[i * 2] = 0;
spr_values[i * 2 + 1] = 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; long long ans, i, l, n, d, m; int main() { cin >> n >> m; for (i = 1; i < n; i++) { cin >> s; } cin >> s; for (i = 1; i < s.size(); i++) { if (s[i] != s[i - 1]) ans++; } if (ans % 2 == 0) { ans /= 2; if (s[0] == B ) ans++; } else { ans++; ans /= 2; } cout << ans; } |
// -*- Mode: Verilog -*-
// Filename : cpu.v
// Description : Complete Picoblaze Design
// Author : Philip Tracton
// Created On : Thu May 21 22:33:37 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 21 22:33:37 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
module cpu (/*AUTOARG*/
// Outputs
port_id, out_port, write_strobe, read_strobe, interrupt_ack,
// Inputs
clk, in_port, interrupt, kcpsm6_sleep, cpu_reset
) ;
input clk;
input [7:0] in_port;
output [7:0] port_id;
output [7:0] out_port;
output write_strobe;
output read_strobe;
input interrupt; //See note above
output interrupt_ack;
input kcpsm6_sleep;
input cpu_reset;
/*AUTOWIRE*/
/*AUTOREG*/
//
// Signals for connection of KCPSM6 and Program Memory.
//
wire [11:0] address;
wire [17:0] instruction;
wire [7:0] out_port;
wire [7:0] port_id;
wire bram_enable;
wire k_write_strobe;
wire kcpsm6_reset; //See note above
wire interrupt_ack;
wire read_strobe;
wire write_strobe;
//
// Some additional signals are required if your system also needs to reset KCPSM6.
//
//
// When interrupt is to be used then the recommended circuit included below requires
// the following signal to represent the request made from your system.
//
wire int_request;
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
//
// If your design also needs to be able to reset KCPSM6 the arrangement below should be
// used to 'OR' your signal with 'rdl' from the program memory.
//
uart_echo_pb_rom
program_rom ( //Name to match your PSM file
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
assign kcpsm6_reset = cpu_reset;
endmodule // cpu
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > ad; vector<int> cam(0); vector<bool> vis; bool k = false; void dfs(const int &m) { vis[m] = true; if (m == ad.size() - 1) { k = true; } else for (int i = 0; i < ad[m].size(); i++) { if (!vis[ad[m][i]]) dfs(ad[m][i]); if (k) break; } if (k) { cam.push_back(m); } } int main() { int n; cin >> n; ad.resize(n + 1, vector<int>(0)); vis.resize(n + 1, false); for (int i = int(2); i < int(n + 1); i += int(1)) { int x; cin >> x; ad[i].push_back(x); ad[x].push_back(i); } dfs(1); for (int i = cam.size() - 1; i >= 0; i--) cout << cam[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2 * 100 * 1000 + 10; bool f1[maxn], f2[maxn]; int n, dis[maxn], dis2[maxn], barg[maxn], mxdis, mxdis2, jj1, j2, h1, h2; vector<int> e[maxn], e2[maxn]; vector<pair<int, int> > v1, v2; void barg2(int v, int p, int t) { f2[v] = true; dis2[v] = t; for (int i = 0; i < e[v].size(); i++) { int u = e[v][i]; if (u != p && u != h2) barg2(u, v, t + 1); } } void barg1(int v, int p, int t) { f1[v] = true; dis[v] = t; for (int i = 0; i < e[v].size(); i++) { int u = e[v][i]; if (u != p && u != h1) barg1(u, v, t + 1); } } int hazf2(int v, int p) { if (v == jj1) return jj1; for (int i = 0; i < e2[v].size(); i++) { int u = e2[v][i]; if (u != p) { int x = hazf2(u, v); if (x != -1) return u; } } return -1; } int hazf1(int v, int p) { if (v == j2) return j2; for (int i = 0; i < e2[v].size(); i++) { int u = e2[v][i]; if (u != p) { int x = hazf1(u, v); if (x != -1) return u; } } return -1; } int dfs4(int v, int p) { int mx1 = 0, mx2 = 0; for (int i = 0; i < e[v].size(); i++) { int u = e[v][i]; if (u != p) { int mx3 = dfs4(u, v); if (mx3 > mx2) mx2 = mx3; if (mx2 > mx1) swap(mx2, mx1); } } barg[v] = mx2 + mx1; return barg[v] + 1; } void dfs3(int v, int p, int t) { dis2[v] = t; for (int i = 0; i < e2[v].size(); i++) { int u = e2[v][i]; if (u != p) dfs3(u, v, t + 1); } return; } void dfs2(int v, int p, int t) { dis[v] = t; for (int i = 0; i < e2[v].size(); i++) { int u = e2[v][i]; if (u != p) dfs2(u, v, t + 1); } return; } bool dfs(int v, int p) { bool f = true; if (e[v].size() > 2) f = false; for (int i = 0; i < e[v].size(); i++) { int u = e[v][i]; if (u != p) if (dfs(u, v) == false) { f = false; e2[v].push_back(u); e2[u].push_back(v); } } return f; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) f1[i] = false, f2[i] = false; for (int i = 0; i < n - 1; i++) { int v, u; cin >> v >> u; v--, u--; e[v].push_back(u); e[u].push_back(v); } int v; for (int i = 0; i < n; i++) if (e[i].size() > 2) { v = i; break; } dfs(v, -1); for (int i = 0; i < n; i++) if (e2[i].size() > 0) { v = i; break; } dfs2(v, -1, 0); dfs4(v, -1); mxdis = dis[v]; for (int i = 0; i < n; i++) if (e2[i].size() > 0 && dis[i] > mxdis) { mxdis = dis[i]; v = i; } for (int i = 0; i < n; i++) if (e2[i].size() > 0 && dis[i] == mxdis) v1.push_back({barg[i], i}); dfs3(v, -1, 0); mxdis2 = dis2[v]; for (int i = 0; i < n; i++) if (e2[i].size() > 0 && dis2[i] > mxdis2) mxdis2 = dis2[i]; for (int i = 0; i < n; i++) if (e2[i].size() > 0 && dis2[i] == mxdis2) v2.push_back({barg[i], i}); sort(&v1[0], &v1[v1.size()]); sort(&v2[0], &v2[v2.size()]); reverse(&v1[0], &v1[v1.size()]); reverse(&v2[0], &v2[v2.size()]); if (v1[0].second == v2[0].second) if (v2.size() == 1 || v1[1].first > v2[1].first) jj1 = v1[1].second, j2 = v2[0].second; else jj1 = v1[0].second, j2 = v2[1].second; else jj1 = v1[0].second, j2 = v2[0].second; h1 = hazf1(jj1, -1); h2 = hazf2(j2, -1); barg1(jj1, -1, 0); barg2(j2, -1, 0); mxdis = -1; for (int i = 0; i < n; i++) if (f1[i] == true && dis[i] > mxdis) { mxdis = dis[i]; v = i; } f1[v] = false; cout << v + 1 << ; mxdis = -1; for (int i = 0; i < n; i++) if (f2[i] == true && dis2[i] > mxdis) { mxdis = dis2[i]; v = i; } f2[v] = false; cout << v + 1 << n ; mxdis = -1; for (int i = 0; i < n; i++) if (f1[i] == true && e[i].size() == 1 && dis[i] > mxdis) { mxdis = dis[i]; v = i; } cout << v + 1 << ; mxdis = -1; for (int i = 0; i < n; i++) if (f2[i] == true && e[i].size() == 1 && dis2[i] > mxdis) { mxdis = dis2[i]; v = i; } cout << v + 1 << n ; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) #pragma GCC optimize( O2 ) using namespace std; const int maxn = 1e4 + 123; int n, k; int a[maxn]; vector<int> ve[4]; long long sum; int main(int argc, char const *argv[]) { std::cin >> n; for (int i = 0; i < n; i++) { char s[3]; int val; std::cin >> s >> val; int id = 2 * (s[0] - 0 ) + (s[1] - 0 ); ve[id].push_back(val); } if (ve[1].size() < ve[2].size()) { swap(ve[1], ve[2]); } for (int i = 0; i <= 3; i++) { sort(ve[i].begin(), ve[i].end()); } long long cur = (long long)ve[3].size(); while (ve[3].size() > 0) { sum += ve[3][(long long)ve[3].size() - 1]; ve[3].pop_back(); } while (ve[2].size() > 0) { sum += ve[2][ve[2].size() - 1] + ve[1][(long long)ve[1].size() - 1]; ve[1].pop_back(); ve[2].pop_back(); } for (int i = 0; i < (int)ve[1].size(); i++) { ve[0].push_back(ve[1][i]); } sort(ve[0].begin(), ve[0].end()); while (cur > 0 && ve[0].size() > 0) { sum += ve[0][ve[0].size() - 1]; ve[0].pop_back(); cur--; } std::cout << sum << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_2_V
`define SKY130_FD_SC_LS__NAND3B_2_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_2 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_2 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_2_V
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//To debug : g++ -g file.cpp -o code //to flush output : fflush(stdout) or cout.flush() //cout<<setprecision(p)<<fixed<<var //use 1LL<<i to for 64 bit shifting , (ll)2 because by default 2 is ll //take care of precedence rule of operators //do not forget to change the sizes of arrays and value of contants and other things after debugging #include<bits/stdc++.h> using namespace std; #define ll long long #define rep(i,a,n) for(i=a;i<n;++i) #define irep(i,n,a) for(i=n;i>a;--i) #define mod 1000000007 #define pb push_back #define big 9223372036854775807 #define big1 LONG_MAX #define big2 ll_MAX #define big3 1000000000 #define sma1 LONG_MIN #define sma2 ll_MIN #define sma3 -1000000000 #define mp make_pair #define dub double #define ivec vector<ll> #define lvec vector<long long> #define cvec vector<char> #define svec vector<string> #define mt make_tuple #define MOD 998244353 #define ld long double #define pi acos(-1.0) #define SZ(x) (ll)(x.size()) //comment the below if not required /* #define ss second.second #define ff first.first #define f first #define s second #define sf second.first #define fs first.second */ #define IOS std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL) //cout<< Case # <<c<< : <<ans<< n ; const ll N = 150001; ll a[5][N],n[5],x,y,temp,val,i,j,ans=LLONG_MAX; set<pair<ll,ll>> m; vector<ll> v[5][N]; int main() { IOS; rep(i,1,5) cin>>n[i]; rep(i,1,5) rep(j,1,n[i]+1) cin>>a[i][j]; rep(i,1,4) { cin>>val; rep(j,1,val+1) { cin>>x>>y; v[i+1][y].pb(x); } } rep(i,2,5) { m.clear(); rep(j,1,n[i-1]+1) { if(a[i-1][j]!=-1) m.insert({a[i-1][j],j}); } rep(j,1,n[i]+1) { for(auto u : v[i][j]) { if(a[i-1][u]!=-1) { auto it = m.find({a[i-1][u],u}); m.erase(it); } } if(SZ(m)) { auto it = m.begin(); a[i][j]+=(*it).first; } else a[i][j]=-1; for(auto u : v[i][j]) { if(a[i-1][u]!=-1) m.insert({a[i-1][u],u}); } } } rep(i,1,n[4]+1){ if(a[4][i]==-1) continue; ans = min(ans,a[4][i]); } if(ans==LLONG_MAX) ans = -1; cout<<ans<< n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int b, d, ans, l, h; char a[105], c[105]; bool letter[30]; int lena, lenc; int ll[105], yy[105]; char aa[105 * 105]; inline int ok() { memset(letter, 0, sizeof(letter)); for (char *p = a; *p; ++p) letter[*p - a ] = 1; for (char *p = c; *p; ++p) if (letter[*p - a ] == 0) return 0; return 1; } inline int init() { for (int i = 0; i < 105; ++i) strcpy(aa + i * lena, a); for (int i = 0; i < lena; ++i) { char *p = aa + i, *q = c; while (*p && *q) { while (*p && *p != *q) ++p; if (*p != *q) return 0; ++p, ++q; } if (*q != 0) return 0; ll[i] = p - (aa + i); yy[i] = (p - aa) % lena; } return 1; } inline int test(int p) { p = p * d; long long pos = 0; long long vst[105], cnt[105]; memset(vst, -1, sizeof(vst)); for (int i = 0; i < p; ++i) { if (pos >= lena * b) return 0; if (vst[pos % lena] > -1) { long long tmp = pos - vst[pos % lena]; long long tem = i - cnt[pos % lena]; pos += tmp * ((p - i) / tem); i = (p - i) / tem * tem + i - 1; memset(vst, -1, sizeof(vst)); continue; } if (i) { vst[pos % lena] = pos; cnt[pos % lena] = i; } pos += ll[pos % lena]; } if (pos - 1 >= lena * b) return 0; return 1; } int main(int argc, char **argv) { scanf( %d%d , &b, &d); scanf( %s%s , a, c); lena = strlen(a), lenc = strlen(c); if (!ok() || !init()) puts( 0 ); else { ans = 0, l = 1, h = lena * b / (lenc * d); while (l <= h) { int mid = (l + h) >> 1; if (test(mid)) ans = mid, l = mid + 1; else h = mid - 1; } printf( %d n , ans); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_1_V
`define SKY130_FD_SC_HS__A221OI_1_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a221oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_1_V
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3 ) #pragma GCC target( avx,avx2,sse,sse2,sse3,sse4,popcnt,fma ) #pragma GCC optimize( unroll-loops ) const long long int MAXN = 2e5 + 5; const long long int mod = 1000000007; const long long int N = 200005; void solve() { map<pair<int, int>, vector<int>> mpX, mpY; int n, m, k; cin >> n >> m >> k; vector<int> xec(n), yec(m); map<int, int> haveX, haveY; for (int i = 0; i < n; i++) { cin >> xec[i], haveX[xec[i]] += 1; } for (int i = 0; i < m; i++) { cin >> yec[i], haveY[yec[i]] += 1; } for (int i = 0; i < k; i++) { int x, y; cin >> x >> y; if (haveX[x] && haveY[y]) continue; if (haveX[x]) { int idx = lower_bound(yec.begin(), yec.end(), y) - yec.begin(); mpX[{yec[idx - 1], yec[idx]}].push_back(x); } if (haveY[y]) { int idx = lower_bound(xec.begin(), xec.end(), x) - xec.begin(); mpY[{xec[idx - 1], xec[idx]}].push_back(y); } } long long int ans = 0; for (auto [a, b] : mpX) { sort(b.begin(), b.end()); map<int, int> mpTemp; int total = b.size(); for (auto x : b) { mpTemp[x] += 1; } for (auto [c, d] : mpTemp) { ans += (long long int)d * (long long int)(total - d); } } for (auto [a, b] : mpY) { sort(b.begin(), b.end()); map<int, int> mpTemp; int total = b.size(); for (auto y : b) { mpTemp[y] += 1; } for (auto [c, d] : mpTemp) { ans += (long long int)d * (long long int)(total - d); } } cout << ans / 2ll << n ; return; } int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; cin >> t; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
* size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
|
#include <bits/stdc++.h> using namespace std; constexpr int MAXWHITE = 20; constexpr int MINBLACK = 40; int64_t dp[110][MAXWHITE + 5][MINBLACK + 5]; int vis[110]; int par[110]; vector<vector<int>> adj; int N, K; int64_t MOD = (int64_t)1e9 + 7LL; int64_t Get(int u, int max_white, int min_black) { return dp[u][max_white + 1][min_black + 1]; } void Set(int u, int max_white, int min_black, int64_t val) { dp[u][max_white + 1][min_black + 1] = val; } void ClearTemp() { for (int i = 0; i <= MAXWHITE + 1; ++i) { for (int j = 0; j <= MINBLACK + 1; ++j) { dp[109][i][j] = 0; } } } void SetTemp(int max_white, int min_black, int64_t val) { Set(109, max_white, min_black, val); } int64_t GetTemp(int max_white, int min_black) { return Get(109, max_white, min_black); } void Flush(int u) { for (int i = 0; i <= MAXWHITE + 1; ++i) { for (int j = 0; j <= MINBLACK + 1; ++j) { dp[u][i][j] = dp[109][i][j]; } } ClearTemp(); } void Update(int u) { int first_one = true; for (int i = 0; i < adj[u].size(); ++i) { int v = adj[u][i]; if (par[u] == v) continue; if (first_one) { first_one = false; for (int a = -1; a <= MAXWHITE; ++a) { for (int b = -1; b <= MINBLACK; ++b) { if (a == b && b == -1) continue; if (a == -1) { Set(u, (b + 1 <= K ? a : a + 1), b + 1, Get(v, a, b)); } else if (b == -1) { Set(u, a + 1, b, Get(v, a, b)); } else { Set(u, a + 1, b + 1, Get(v, a, b)); } } } int64_t black_way = 0; for (int a = -1; a <= MAXWHITE; ++a) { if (a + 1 > K) continue; for (int b = -1; b <= MINBLACK; ++b) { black_way += Get(v, a, b); black_way %= MOD; } } Set(u, -1, 0, black_way); continue; } for (int a = -1; a <= MAXWHITE; ++a) { for (int b = -1; b <= MINBLACK; ++b) { if (a == b && b == -1) continue; for (int c = -1; c <= MAXWHITE; ++c) { for (int d = -1; d <= MINBLACK; ++d) { if (c == d && d == -1) continue; int max_white = (a == -1 ? c + 1 : (c == -1 ? a : max(a, c + 1))); int min_black = (b == -1 ? d + 1 : (d == -1 ? b : min(b, d + 1))); if (a == c && c == -1) { max_white = -1; } if (b == d && d == -1) { min_black = -1; } if (max_white != -1 && min_black != -1) { if (min_black + max_white <= K) { max_white = -1; } } if (max_white <= MAXWHITE && min_black <= MINBLACK) { int64_t x = Get(u, a, b); int64_t y = Get(v, c, d); x = (x * y) % MOD; x = (x + GetTemp(max_white, min_black)) % MOD; SetTemp(max_white, min_black, x); } } } } } Flush(u); } } void Dfs(int u) { vis[u] = 1; bool leaf = true; for (int i = 0; i < adj[u].size(); ++i) { int v = adj[u][i]; if (!vis[v]) { leaf = false; par[v] = u; Dfs(v); } } if (leaf) { Set(u, -1, 0, 1); Set(u, 0, -1, 1); return; } Update(u); } int main() { scanf( %d%d , &N, &K); int u, v; adj.resize(N); for (int i = 0; i < N - 1; ++i) { scanf( %d%d , &u, &v); --u; --v; adj[u].push_back(v); adj[v].push_back(u); } Dfs(0); int64_t ans = 0; for (int max_white = -1; max_white <= MAXWHITE; ++max_white) { for (int min_black = -1; min_black <= MINBLACK; ++min_black) { if ((max_white == -1 && min_black <= K) || (min_black != -1 && min_black + max_white <= K)) { ans += Get(0, max_white, min_black); ans %= MOD; } } } cout << ans << endl; return 0; } |
`timescale 1ns / 1ps
module jt12_test;
reg rst;
reg clk;
wire s1_enters, s2_enters, s3_enters, s4_enters;
`include "../common/dump.vh"
initial begin
clk = 0;
forever #10 clk=~clk;
end
reg test_eg;
// envelope configuration
reg [10:0] fnum;
reg [ 2:0] block;
reg [ 3:0] mul_V;
reg [ 2:0] dt1_II; // same as JT51's DT1
reg keyon_VI;
initial begin
rst = 0;
fnum = 11'd500;
block = 3'd2;
mul_V = 5'd1;
dt1_II= 3'd0;
#5 rst = 1;
#20 rst = 0;
#(1*1000*1000) $finish;
end
integer cycles;
reg [4:0] cnt24;
wire zero = cnt24==5'd0;
reg keyon_done;
always @(posedge clk)
if( rst ) begin
cycles <= 0;
keyon_VI <= 1'b0;
end else begin
cycles <= cycles + 1;
if( cycles==100 ) keyon_VI<=1'b1;
if( cycles==101 ) keyon_VI<=1'b0;
end
always @(posedge clk)
if( rst ) begin
cnt24 <= 0;
end else begin
if( cnt24 == 5'd23 )
cnt24 <= 5'd0;
else
cnt24 <= cnt24 + 1;
end
wire [ 9:0] phase_VIII;
jt12_pg u_uut(
.clk ( clk ),
// Channel frequency
.fnum ( fnum ),
.block ( block ),
// Operator multiplying
.mul_V ( mul_V ),
// Operator detuning
.dt1_II ( dt1_II ), // same as JT51's DT1
// phase operation
.keyon_VI ( keyon_VI ),
.keycode_III( keycode_III ),
.phase_VIII ( phase_VIII )
);
wire [9:0] phase_ch0op0;
wire [9:0] rest_and, rest_or;
jt12_opsync u_opsync(
.rst ( rst ),
.clk ( clk ),
.clk6 ( clk6 ),
.s1_enters ( s1_enters ),
.s2_enters ( s2_enters ),
.s3_enters ( s3_enters ),
.s4_enters ( s4_enters )
);
sep24 #(.width(10),.pos0(7)) sep(
.clk ( clk ),
.mixed ( phase_VIII ),
.cnt ( cnt24 ),
.ch0op0 ( phase_ch0op0 ),
.alland ( rest_and ),
.allor ( rest_or ),
.mask ( ~24'b1 )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int func(char c) { if (c >= a && c <= z ) { return 1; } if (c >= A && c <= Z ) { return 2; } return 0; } void solve() { string s; cin >> s; long long int lw = 0; long long int up = 0; long long int nm = 0; string str = s; long long int mp[3] = {0}; for (long long int i = 0; i < s.length(); i++) { mp[func(s[i])]++; } long long int cn = 0; for (long long int i = 0; i < 3; i++) { if (!mp[i]) cn++; } if (!cn) { cout << s << endl; return; } if (cn == 1) { for (long long int i = 0; i < s.length(); i++) { if (mp[func(s[i])] > 1) { long long int index = 0; for (long long int id = 0; id < 3; id++) { if (!mp[id]) index = id; } if (index == 0) { s[i] = 0 ; break; } else if (index == 1) { s[i] = a ; break; } else { s[i] = A ; break; } } } cout << s << endl; } else { long long int index; for (long long int i = 0; i < 3; i++) { if (mp[i]) { index = i; break; } } if (index == 1) { s[0] = A ; s[1] = 0 ; } else if (index == 0) { s[0] = A ; s[1] = a ; } else { s[0] = 0 ; s[1] = a ; } cout << s << endl; } } int main() { long long int t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 15; const int maxt = 235; const int MOD = 1e9 + 7; inline void upd(int &a, int b) { a += b; if (a >= MOD) a -= MOD; } int n, T; int dp[maxt][1 << maxn][3], t[maxn], g[maxn]; int main() { scanf( %d%d , &n, &T); for (int(i) = (0); (i) <= ((n)-1); (i)++) { scanf( %d%d , t + i, g + i); g[i]--; } for (int(i) = (0); (i) <= ((n)-1); (i)++) dp[t[i]][1 << i][g[i]] = 1; for (int(i) = (1); (i) <= (T - 1); (i)++) for (int(mask) = (0); (mask) <= ((1 << n) - 1); (mask)++) for (int(k) = (0); (k) <= ((n)-1); (k)++) if ((mask & (1 << k)) == 0 && t[k] + i <= T) for (int(j) = (0); (j) <= ((3) - 1); (j)++) if (j != g[k]) upd(dp[i + t[k]][mask | (1 << k)][g[k]], dp[i][mask][j]); int ans = 0; for (int(mask) = (0); (mask) <= ((1 << n) - 1); (mask)++) for (int(i) = (0); (i) <= ((3) - 1); (i)++) upd(ans, dp[T][mask][i]); printf( %d , ans); } |
// memoria dual port - single clk que permite escrita e leitura
// simultaneas em portas distintas
module mem_dport_sclk(
clk, // clk
we_a, // write enable - porta A
we_b, // write enable - porta B
data_a, // dados in - porta A
data_b, // dados in - porta B
addr_a, // endereco - porta A
addr_b, // endereco - porta B
out_a, // saida - porta A
out_b // saida - porta B
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// declaracao de entrada / saida
input clk, we_a, we_b;
input signed [DATA_WIDTH-1:0] data_a, data_b;
input [MEM_WIDTH-1:0] addr_a, addr_b;
output reg [DATA_WIDTH-1:0] out_a, out_b;
// declaracao da memoria RAM
reg [DATA_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];
// Port A
always @ (posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
out_a <= data_a;
end else begin
out_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
out_b <= data_b;
end else begin
out_b <= ram[addr_b];
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long int get(long long int s, long long int w, long long int cs, long long int cw, long long int p) { if (s > w) return get(w, s, cw, cs, p); if (s * cs >= p) return p / s; return cs + min(cw, (p - s * cs) / w); }; void solve() { long long int p, f; cin >> p >> f; long long int cs, cw; cin >> cs >> cw; long long int s, w; cin >> s >> w; long long int mx = 0; for (long long int x = 0; x <= cs; ++x) { if (x * s <= p) { long long int y = min(cw, (p - x * s) / w); mx = max(mx, x + y + get(s, w, cs - x, cw - y, f)); } } cout << mx << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long int T = 1; cin >> T; for (long long int i = 1; i <= T; ++i) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T BMOD(T p, T e, T m) { T ret = 1; while (e) { if (e & 1) ret = (ret * p) % m; p = (p * p) % m; e >>= 1; } return (T)ret; } template <typename T> inline T POW(T B, T P) { if (P == 0) return 1; if (P & 1) return B * POW(B, P - 1); else return SQR(POW(B, P / 2)); } template <typename T> inline T ModInv(T b, T m) { return BMOD(b, m - 2, m); } template <typename T> inline T ABS(T a) { if (a < 0) return -a; else return a; } template <typename T> inline T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } template <typename T> inline T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } int dx[] = {-1, -1, -1, 0, 0, 1, 1, 1}; int dy[] = {-1, 0, 1, -1, 1, -1, 0, 1}; int n, x, trck[200005], arr[100005]; int main() { scanf( %d%d , &n, &x); for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]); trck[arr[i]]++; } long long int res = 0; for (int i = 1; i <= 100000; i++) { int nm = i ^ x; if (trck[nm] && trck[i]) { long long int cnt = (long long int)trck[nm] * trck[i]; if (x == 0) cnt = (long long int)trck[nm] * (trck[i] - 1); res += cnt; } } res /= 2; printf( %lld , res), puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const long long LINF = 1e17; const double DINF = numeric_limits<double>::max(); const int ITER = 300; const int MOD = 1e9 + 7; const double EPS = 1e-10; const int MAXN = 1e5 + 10; int n; vector<int> g[MAXN]; int B[MAXN]; int dp[MAXN][2]; void mod(int v) { for (int i = 0; i < 2; i++) dp[v][i] %= MOD; } void dfs(int v) { dp[v][0] = 1 - B[v]; dp[v][1] = B[v]; for (int u : g[v]) { int old[2]; old[0] = dp[v][0]; old[1] = dp[v][1]; dp[v][0] = dp[v][1] = 0; dfs(u); dp[v][0] += (1ll * old[0] * dp[u][1]) % MOD; dp[v][1] += (1ll * old[1] * dp[u][1]) % MOD; mod(v); dp[v][1] += (1ll * old[1] * dp[u][0]) % MOD; mod(v); dp[v][1] += (1ll * old[0] * dp[u][1]) % MOD; mod(v); dp[v][0] += (1ll * old[0] * dp[u][0]) % MOD; mod(v); } } void solve() { cin >> n; for (int i = 1; i < n; i++) { int p; cin >> p; g[p].push_back(i); } for (int i = 0; i < n; i++) { cin >> B[i]; } dfs(0); cout << dp[0][1] << endl; } int main() { cout << setprecision(12) << fixed; ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; long long a[100010]; long long dif[100010]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i <= n - 1; i++) { dif[i] = a[i + 1] - a[i]; } long long d = 0; for (int i = 1; i <= n - 1; i++) if (dif[i] > 0) d += dif[i]; int q; scanf( %d , &q); printf( %lld n , ((a[1] + d) % 2) ? (((a[1] + d) >> 1) + 1) : (a[1] + d) >> 1); for (int i = 0; i < q; i++) { int l, r; long long x; scanf( %d%d%lld , &l, &r, &x); if (l == 1) a[1] += x; if (l != 1) { dif[l - 1] += x; if (dif[l - 1] > 0) d += dif[l - 1] - (dif[l - 1] - x > 0 ? (dif[l - 1] - x) : (0)); else d -= ((dif[l - 1] - x) > 0 ? (dif[l - 1] - x) : (0)); } if (r != n) { dif[r] -= x; if (dif[r] > 0) d += dif[r] - (dif[r] + x > 0 ? (dif[r] + x) : (0)); else d -= (dif[r] + x > 0 ? (dif[r] + x) : (0)); } printf( %lld n , ((a[1] + d) % 2) ? (((a[1] + d) >> 1) + 1) : (a[1] + d) >> 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxN = 1e5 + 5; const long long mod = 1e18 + 5; struct makeEdge { long long weight; long long left; long long right; long long vertex; }; struct makeEdge piece; vector<makeEdge> query2; vector<makeEdge> query3; long long start; long long cnt; long long n; long long a[maxN]; long long tree[maxN * 4]; long long l[maxN * 4]; long long r[maxN * 4]; long long ans[maxN]; vector<pair<long long, long long>> vc[maxN * 10]; void direct(long long i, long long j) { vc[i].push_back(pair<long long, long long>(0, j)); } void newpath(long long i, long long j, long long anewweight) { vc[i].push_back(pair<long long, long long>(anewweight, j)); } void buildTree(long long node, long long left, long long right) { l[node] = left; r[node] = right; if (left == right) return; long long mid = (left + right) / 2; buildTree(node * 2, left, mid); buildTree(node * 2 + 1, mid + 1, right); } void update2(long long node, long long left, long long right, long long wei, long long emit) { if (l[node] == left && r[node] == right) { newpath(emit, ((node) + n), wei); return; } if (left > r[node * 2]) { update2(node * 2 + 1, left, right, wei, emit); return; } if (right < l[node * 2 + 1]) { update2(node * 2, left, right, wei, emit); return; } update2(node * 2, left, r[node * 2], wei, emit); update2(node * 2 + 1, l[node * 2 + 1], right, wei, emit); return; } void update3(long long node, long long left, long long right, long long wei, long long emit) { if (l[node] == left && r[node] == right) { newpath(((node) + n * 5 - 1), emit, wei); return; } if (left > r[node * 2]) { update3(node * 2 + 1, left, right, wei, emit); return; } if (right < l[node * 2 + 1]) { update3(node * 2, left, right, wei, emit); return; } update3(node * 2, left, r[node * 2], wei, emit); update3(node * 2 + 1, l[node * 2 + 1], right, wei, emit); return; } void solve() { for (long long i = 1; i <= n; i++) { ans[i] = mod; } priority_queue<pair<long long, long long>, vector<pair<long long, long long>>, greater<pair<long long, long long>>> pq; pq.push(pair<long long, long long>(0, start)); ans[start] = 0; while (!pq.empty()) { pair<long long, long long> front = pq.top(); pq.pop(); long long node = front.second; long long dist = front.first; if (dist != ans[node]) continue; for (long long i = 0; i < vc[node].size(); i++) { long long child = vc[node][i].second; if (dist + vc[node][i].first < ans[child]) { ans[child] = dist + vc[node][i].first; pq.push(pair<long long, long long>(ans[child], child)); } } } } long long t, x, y, www; signed main() { cin >> n; long long o; cin >> o; cin >> start; buildTree(1, 1, n); while (o--) { cin >> t; if (t == 1) { cin >> x >> y >> www; vc[x].push_back(pair<long long, long long>(www, y)); } else { cin >> piece.vertex; cin >> piece.left; cin >> piece.right; cin >> piece.weight; if (t == 2) query2.push_back(piece); if (t == 3) query3.push_back(piece); } } buildTree(1, 1, n); for (long long i = 1; i <= n * 4 - 1; i++) { if (l[i] == 0) continue; if (l[i] == r[i]) direct(((i) + n), l[i]); else { direct(((i) + n), ((i * 2) + n)); direct(((i) + n), ((i * 2 + 1) + n)); } } for (long long i = 0; i < query2.size(); i++) { update2(1, query2[i].left, query2[i].right, query2[i].weight, query2[i].vertex); } buildTree(1, 1, n); for (long long i = 1; i <= n * 4 - 1; i++) { if (l[i] == 0) continue; if (l[i] == r[i]) direct(l[i], ((i) + n * 5 - 1)); else { direct(((i * 2 + 1) + n * 5 - 1), ((i) + n * 5 - 1)); direct(((i * 2) + n * 5 - 1), ((i) + n * 5 - 1)); } } for (long long i = 0; i < query3.size(); i++) { update3(1, query3[i].left, query3[i].right, query3[i].weight, query3[i].vertex); } n = n * 9 - 2; solve(); n = (n + 2) / 9; for (long long i = 1; i <= n; i++) { if (ans[i] == mod) cout << -1 ; else cout << ans[i] << ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__EDFXBP_PP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k; cin >> n >> k; string fir; cin >> fir; vector<long long> v; for (long long i = 0; i < fir.size(); ++i) { if (fir[i] == 0 ) { v.push_back(i); } } long long ans = pow(10, 7); long long m = 0; for (long long l = 0; l < v.size() - k; ++l) { long long r = l + k; ; while (v[m] - v[l] < v[r] - v[m]) { ++m; } ans = min(ans, max(v[m] - v[l], v[r] - v[m])); ans = min(ans, max(v[m - 1] - v[l], v[r] - v[m - 1])); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; inline int in() { int32_t x; scanf( %d , &x); return x; } inline string get() { char ch[1000010]; scanf( %s , ch); return ch; } const int MAX_LG = 60; const long long maxn = 1e6 + 100; const long long base = 29; const long long mod = 1e9 + 7; const long long INF = 1e18 + 100; struct state { long long a = 0, b = 0, tp = 0; state() {} state(long long a, long long b, long long tp) : a(a), b(b), tp(tp) {} }; long long cnt[maxn]; long long di[51][51][2]; long long C[51][51]; long long ways[51][51][2]; queue<state> q; int32_t main() { long long n = in(), k = in(); for (long long i = 0; i < n; i++) cnt[in() / 51]++; q.push({cnt[0], cnt[1], 0}); for (long long i = 0; i <= 50; i++) for (long long j = 0; j <= 50; j++) di[i][j][0] = di[i][j][1] = INF; for (long long i = 0; i <= 50; i++) { for (long long j = 0; j <= i; j++) { if (j == 0) C[i][j] = 1; else C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } } di[cnt[0]][cnt[1]][0] = 0; ways[cnt[0]][cnt[1]][0] = 1; while (q.empty() == false) { state now = q.front(); q.pop(); long long a2 = cnt[0] - now.a; long long b2 = cnt[1] - now.b; for (long long i = 0; i <= now.a; i++) { for (long long j = 0; j <= now.b; j++) { if (i + j == 0) continue; if (i * 50 + j * 100 > k) continue; long long d2 = di[now.a][now.b][now.tp] + 1; long long *d3 = &di[a2 + i][b2 + j][now.tp ^ 1]; if (*d3 == INF) { *d3 = d2; q.push({a2 + i, b2 + j, now.tp ^ 1}); } if (*d3 == d2) { ways[a2 + i][b2 + j][now.tp ^ 1] += ways[now.a][now.b][now.tp] * C[now.a][i] % mod * C[now.b][j] % mod; if (ways[a2 + i][b2 + j][now.tp ^ 1] > mod) ways[a2 + i][b2 + j][now.tp ^ 1] -= mod; } } } } if (ways[cnt[0]][cnt[1]][1] == 0) return cout << -1 << n << 0 << n , 0; else { cout << di[cnt[0]][cnt[1]][1] << n ; cout << ways[cnt[0]][cnt[1]][1] << n ; } } |
`default_nettype none
module baudgen(
input wire clk,
input wire resetq,
input wire [31:0] baud,
input wire restart,
output wire ser_clk);
parameter CLKFREQ = ;
wire [38:0] aclkfreq = CLKFREQ;
reg [38:0] d;
wire [38:0] dInc = d[38] ? ({4'd0, baud}) : (({4'd0, baud}) - aclkfreq);
wire [38:0] dN = restart ? 0 : (d + dInc);
wire fastclk = ~d[38];
assign ser_clk = fastclk;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
d <= 0;
end else begin
d <= dN;
end
end
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk, // System clock
input wire resetq,
// Outputs
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
// Inputs
input wire [31:0] baud,
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i // 8-bit data
);
parameter CLKFREQ = ;
reg [3:0] bitcount;
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
wire starting = uart_wr_i & ~uart_busy;
baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
.clk(clk),
.resetq(resetq),
.baud(baud),
.restart(1'b0),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (starting) begin
shifter <= { uart_dat_i[7:0], 1'b0 };
bitcount <= 1 + 8 + 1;
end
if (sending & ser_clk) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire [31:0] baud,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
parameter CLKFREQ = ;
reg [4:0] bitcount;
reg [7:0] shifter;
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
.clk(clk),
.baud({baud[30:0], 1'b0}),
.resetq(resetq),
.restart(startbit),
.ser_clk(ser_clk));
assign valid = (bitcount == 18);
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (bitcount > 2) & bitcount[0] & !valid & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire [31:0] baud,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
parameter CLKFREQ = ;
rxuart #(.CLKFREQ(CLKFREQ)) _rx (
.clk(clk),
.resetq(resetq),
.baud(baud),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart #(.CLKFREQ(CLKFREQ)) _tx (
.clk(clk),
.resetq(resetq),
.baud(baud),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m, k; unordered_map<int, vector<int> > g; map<pair<int, int>, int> weights; map<pair<int, int>, int> idx; unordered_map<int, bool> used; struct elem { int prev; int u; long long dist; elem(int prev, int u, long long dist) : prev(prev), u(u), dist(dist) {} friend bool operator<(const elem& lh, const elem& rh) { return lh.dist > rh.dist; } }; int main() { ios_base::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 1; i <= m; ++i) { int u, v, w; cin >> u >> v >> w; g[u].push_back(v); g[v].push_back(u); weights[make_pair(u, v)] = w; weights[make_pair(v, u)] = w; idx[make_pair(u, v)] = i; idx[make_pair(v, u)] = i; } vector<int> res; priority_queue<elem> q; q.push(elem(0, 1, 0)); int taken = 0; int mx = min(n, k); while (!q.empty() && mx != taken) { int prev = q.top().prev; int u = q.top().u; long long dist = q.top().dist; q.pop(); if (used[u]) continue; used[u] = true; if (prev) { res.push_back(idx[make_pair(prev, u)]); ++taken; } for (int v : g[u]) if (!used[v]) { q.push(elem(u, v, dist + weights[make_pair(u, v)])); } } cout << res.size() << endl; for (int i : res) cout << i << ; cout << endl; return 0; } |
#include <bits/stdc++.h> int main() { char ch[116]; int i, j = 1, k, m, n, c, s, e; scanf( %d %d , &n, &m); while (j <= n) { scanf( %s , ch); for (i = 0; ch[i] != 0 ; i++) { if (ch[i] == B ) { s = i; while (ch[++i] == B ) ; e = i - 1; c = (e - s + 1) / 2; printf( %d %d , j + c, s + 1 + c); return 0; } } j++; } } |
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Audio Processing Unit.
***************************************************************************************************/
module apu
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire [ 3:0] mute_in, // disable specific audio channels
input wire [15:0] a_in, // addr input bus
input wire [ 7:0] d_in, // data input bus
input wire r_nw_in, // read/write select
output wire audio_out, // pwm audio output
output wire [ 7:0] d_out // data output bus
);
localparam [15:0] PULSE0_CHANNEL_CNTL_MMR_ADDR = 16'h4000;
localparam [15:0] PULSE1_CHANNEL_CNTL_MMR_ADDR = 16'h4004;
localparam [15:0] TRIANGLE_CHANNEL_CNTL_MMR_ADDR = 16'h4008;
localparam [15:0] NOISE_CHANNEL_CNTL_MMR_ADDR = 16'h400C;
localparam [15:0] STATUS_MMR_ADDR = 16'h4015;
localparam [15:0] FRAME_COUNTER_CNTL_MMR_ADDR = 16'h4017;
// CPU cycle pulse. Ideally this would be generated in rp2a03 and shared by the apu and cpu.
reg [5:0] q_clk_cnt;
wire [5:0] d_clk_cnt;
wire cpu_cycle_pulse;
wire apu_cycle_pulse;
wire e_pulse;
wire l_pulse;
wire f_pulse;
reg q_pulse0_en;
wire d_pulse0_en;
reg q_pulse1_en;
wire d_pulse1_en;
reg q_triangle_en;
wire d_triangle_en;
reg q_noise_en;
wire d_noise_en;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_clk_cnt <= 6'h00;
q_pulse0_en <= 1'b0;
q_pulse1_en <= 1'b0;
q_triangle_en <= 1'b0;
q_noise_en <= 1'b0;
end
else
begin
q_clk_cnt <= d_clk_cnt;
q_pulse0_en <= d_pulse0_en;
q_pulse1_en <= d_pulse1_en;
q_triangle_en <= d_triangle_en;
q_noise_en <= d_noise_en;
end
end
assign d_clk_cnt = (q_clk_cnt == 6'h37) ? 6'h00 : q_clk_cnt + 6'h01;
assign d_pulse0_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[0] : q_pulse0_en;
assign d_pulse1_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[1] : q_pulse1_en;
assign d_triangle_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[2] : q_triangle_en;
assign d_noise_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[3] : q_noise_en;
assign cpu_cycle_pulse = (q_clk_cnt == 6'h00);
apu_div #(.PERIOD_BITS(1)) apu_pulse_gen(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse),
.reload_in(1'b0),
.period_in(1'b1),
.pulse_out(apu_cycle_pulse)
);
//
// Frame counter.
//
wire frame_counter_mode_wr;
apu_frame_counter apu_frame_counter_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.apu_cycle_pulse_in(apu_cycle_pulse),
.mode_in(d_in[7:6]),
.mode_wr_in(frame_counter_mode_wr),
.e_pulse_out(e_pulse),
.l_pulse_out(l_pulse),
.f_pulse_out(f_pulse)
);
assign frame_counter_mode_wr = ~r_nw_in && (a_in == FRAME_COUNTER_CNTL_MMR_ADDR);
//
// Pulse 0 channel.
//
wire [3:0] pulse0_out;
wire pulse0_active;
wire pulse0_wr;
apu_pulse #(.CHANNEL(0)) apu_pulse0_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_pulse0_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(pulse0_wr),
.pulse_out(pulse0_out),
.active_out(pulse0_active)
);
assign pulse0_wr = ~r_nw_in && (a_in[15:2] == PULSE0_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Pulse 1 channel.
//
wire [3:0] pulse1_out;
wire pulse1_active;
wire pulse1_wr;
apu_pulse #(.CHANNEL(1)) apu_pulse1_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_pulse1_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(pulse1_wr),
.pulse_out(pulse1_out),
.active_out(pulse1_active)
);
assign pulse1_wr = ~r_nw_in && (a_in[15:2] == PULSE1_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Triangle channel.
//
wire [3:0] triangle_out;
wire triangle_active;
wire triangle_wr;
apu_triangle apu_triangle_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_triangle_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(triangle_wr),
.triangle_out(triangle_out),
.active_out(triangle_active)
);
assign triangle_wr = ~r_nw_in && (a_in[15:2] == TRIANGLE_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Noise channel.
//
wire [3:0] noise_out;
wire noise_active;
wire noise_wr;
apu_noise apu_noise_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_noise_en),
.apu_cycle_pulse_in(apu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(noise_wr),
.noise_out(noise_out),
.active_out(noise_active)
);
assign noise_wr = ~r_nw_in && (a_in[15:2] == NOISE_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Mixer.
//
apu_mixer apu_mixer_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.mute_in(mute_in),
.pulse0_in(pulse0_out),
.pulse1_in(pulse1_out),
.triangle_in(triangle_out),
.noise_in(noise_out),
.audio_out(audio_out)
);
assign d_out = (r_nw_in && (a_in == STATUS_MMR_ADDR)) ?
{ 4'b0000, noise_active, triangle_active, pulse1_active, pulse0_active } : 8'h00;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200010; const int MOD = 1e9 + 7; int read() { int x = 0, ch; while (isspace(ch = getchar())) ; do x = x * 10 + ch - 0 ; while (isdigit(ch = getchar())); return x; } int n; map<int, int> idx, idy; int nid; namespace G { int head[MAXN], nxt[MAXN], to[MAXN], m; void init() { memset(head, -1, sizeof head); } void adde(int u, int v) { to[m] = v, nxt[m] = head[u], head[u] = m++; to[m] = u, nxt[m] = head[v], head[v] = m++; } } // namespace G int fpow(int a, int b) { int c = 1; while (b) { if (b & 1) c = int(1LL * c * a % MOD); a = int(1LL * a * a % MOD); b >>= 1; } return c; } int vis[MAXN]; queue<int> q; int solve(int s) { using namespace G; int e = 0, o = 0; vis[s] = 1, q.push(s); while (!q.empty()) { int u = q.front(); q.pop(); ++o; for (int i = head[u]; ~i; i = nxt[i], ++e) if (!vis[to[i]]) vis[to[i]] = 1, q.push(to[i]); } e >>= 1; return e == o - 1 ? (fpow(2, o) - 1 + MOD) % MOD : fpow(2, o); } int main() { n = read(); G::init(); for (int i = 0; i < n; ++i) { int x = read(), y = read(); if (!idx[x]) idx[x] = ++nid; if (!idy[y]) idy[y] = ++nid; G::adde(idx[x], idy[y]); } int ans = 1; for (int i = 1; i <= nid; ++i) if (!vis[i]) ans = int(1LL * ans * solve(i) % MOD); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int S[2][500005 * 4], pre[500005], suf[500005]; long long hpr1[3][500005], hpr2[3][500005], hsf1[3][500005], hsf2[3][500005], pww[3][500005]; int n, m, k; long long pr[3] = {79, 103, 211}; bool flag; char a[500005], b[500005]; vector<int> sss[500005], ppp[500005]; int get(int node, int bas, int son, int x, int y, int w) { if (bas > y || son < x) return (w ? -1 : 1900000000); if (bas >= x && son <= y) { if (bas == son) { if (S[w][node]) { flag = true; return bas; } return 1900000000; } if (w) { if (S[w][node * 2 + 1]) return get(node * 2 + 1, ((bas + son) / 2) + 1, son, x, y, w); else if (S[w][node * 2]) return get(node * 2, bas, ((bas + son) / 2), x, y, w); else return -1; } else { if (S[w][node * 2]) return get(node * 2, bas, ((bas + son) / 2), x, y, w); else if (S[w][node * 2 + 1]) return get(node * 2 + 1, ((bas + son) / 2) + 1, son, x, y, w); else return 1900000000; } } if (w) { int res = get(node * 2 + 1, ((bas + son) / 2) + 1, son, x, y, w); if (flag) return res; return get(node * 2, bas, ((bas + son) / 2), x, y, w); } else { int res = get(node * 2, bas, ((bas + son) / 2), x, y, w); if (flag) return res; return get(node * 2 + 1, ((bas + son) / 2) + 1, son, x, y, w); } } void up(int node, int bas, int son, int x, int val, int w) { if (bas > x || son < x) return; if (bas == x && son == x) { S[w][node] = val; return; } up(node * 2, bas, ((bas + son) / 2), x, val, w); up(node * 2 + 1, ((bas + son) / 2) + 1, son, x, val, w); S[w][node] = S[w][node * 2] + S[w][node * 2 + 1]; } void build(int node, int bas, int son, int w) { if (bas == son) { S[w][node] = 1; return; } build(node * 2, bas, ((bas + son) / 2), w); build(node * 2 + 1, ((bas + son) / 2) + 1, son, w); S[w][node] = S[w][node * 2] + S[w][node * 2 + 1]; } pair<pair<long long, long long>, long long> suf2(int bas, int son) { return {{hsf2[0][son] - hsf2[0][bas + 1] * pww[0][bas - son + 1], hsf2[1][son] - hsf2[1][bas + 1] * pww[1][bas - son + 1]}, hsf2[2][son] - hsf2[2][bas + 1] * pww[2][bas - son + 1]}; } pair<pair<long long, long long>, long long> suf1(int bas, int son) { return {{hsf1[0][son] - hsf1[0][bas + 1] * pww[0][bas - son + 1], hsf1[1][son] - hsf1[1][bas + 1] * pww[1][bas - son + 1]}, hsf1[2][son] - hsf1[2][bas + 1] * pww[2][bas - son + 1]}; } pair<pair<long long, long long>, long long> pre2(int bas, int son) { return {{hpr2[0][son] - hpr2[0][bas - 1] * pww[0][son - bas + 1], hpr2[1][son] - hpr2[1][bas - 1] * pww[1][son - bas + 1]}, hpr2[2][son] - hpr2[2][bas - 1] * pww[2][son - bas + 1]}; } pair<pair<long long, long long>, long long> pre1(int bas, int son) { return {{hpr1[0][son] - hpr1[0][bas - 1] * pww[0][son - bas + 1], hpr1[1][son] - hpr1[1][bas - 1] * pww[1][son - bas + 1]}, hpr1[2][son] - hpr1[2][bas - 1] * pww[2][son - bas + 1]}; } void hashsuf() { for (int i = n; i >= 1; i--) { for (int j = 0; j < 3; j++) { hsf1[j][i] = hsf1[j][i + 1] * pr[j] + a[i] - a + 1; } } for (int i = m; i >= 1; i--) { for (int j = 0; j < 3; j++) { hsf2[j][i] = hsf2[j][i + 1] * pr[j] + b[i] - a + 1; } } } void hashpre() { for (int i = 1; i <= n; i++) { for (int j = 0; j < 3; j++) { hpr1[j][i] = hpr1[j][i - 1] * pr[j] + a[i] - a + 1; } } for (int i = 1; i <= m; i++) { for (int j = 0; j < 3; j++) { hpr2[j][i] = hpr2[j][i - 1] * pr[j] + b[i] - a + 1; } } } pair<int, int> getsuf(int from, int len) { flag = false; int pos = get(1, 1, n, from + len - 1, n - (k - len), 1); int be = pos - len + 1; int en = pos + (k - len); if (be < from || en > n) return {1900000000, 1900000000}; return {be, en}; } int main() { scanf( %d %d %d , &n, &m, &k); scanf( %s , a + 1); scanf( %s , b + 1); hashpre(); hashsuf(); pww[0][0] = pww[1][0] = pww[2][0] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j < 3; j++) pww[j][i] = pww[j][i - 1] * pr[j]; for (int i = 1; i <= n; i++) { int bas = 1, son = min(m, n - i + 1); while (bas <= son) { if (pre1(i, i + ((bas + son) / 2) - 1) == pre2(1, ((bas + son) / 2))) bas = ((bas + son) / 2) + 1; else son = ((bas + son) / 2) - 1; } pre[i] = son; ppp[son].push_back(i); bas = 1, son = min(m, i); while (bas <= son) { if (suf1(i, i - ((bas + son) / 2) + 1) == suf2(m, m - ((bas + son) / 2) + 1)) bas = ((bas + son) / 2) + 1; else son = ((bas + son) / 2) - 1; } suf[i] = son; sss[son].push_back(i); } for (int i = 1; i <= n; i++) { if (pre[i] == m && m <= k) { int mxen = min(n, i + k - 1); int mnbe = max(1, i - k + 1); if (mxen - 2 * k + 1 >= 1) { printf( Yes n%d %d , mxen - 2 * k + 1, mxen - k + 1); return 0; } if (mnbe + 2 * k - 1 <= n) { printf( Yes n%d %d , mnbe, mnbe + k); return 0; } } } build(1, 1, n, 0); for (int i = 0; i <= min(k, m); i++) { for (int j = 0; j < (int)sss[m - i].size(); j++) up(1, 1, n, sss[m - i][j], 1, 1); flag = false; int pos = get(1, 1, n, k - i + 1, n, 0); for (int j = 0; j < (int)ppp[i].size(); j++) up(1, 1, n, ppp[i][j], 0, 0); if (m - i > k) continue; int en = pos + i - 1; int be = en - k + 1; if (en > n || be < 1) continue; pair<int, int> res = getsuf(en + 1, m - i); if (res.first < en + 1 || res.second > n) continue; printf( Yes n%d %d , be, res.first); return 0; } printf( No ); } |
#include <bits/stdc++.h> #pragma warning(disable : 4786) using namespace std; int a[200000]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } a[n + 1] = a[1]; int y = 0; for (int i = 2; i <= n + 1; i++) { if (a[i] < a[i - 1]) { if (y != 0) { printf( -1 n ); return 0; } else { y = i; } } } if (y == 0) y = n + 1; printf( %d , n - y + 1); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [7:0] crc;
genvar g;
wire [7:0] out_p1;
wire [15:0] out_p2;
wire [7:0] out_p3;
wire [7:0] out_p4;
paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1));
paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2));
paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3));
gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4));
wire [7:0] out_ef;
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n", $time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
end
else if (cyc==1) begin
end
else if (cyc==3) begin
if (out_p1 !== 8'h2d) $stop;
if (out_p2 !== 16'h2d2d) $stop;
if (out_p3 !== 8'h78) $stop;
if (out_p4 !== 8'h44) $stop;
if (out_ef !== 8'hda) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module gencase (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter MODE = 0;
input [7:0] in;
output [7:0] out;
generate // : genblk1
begin
case (MODE)
2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]}));
default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]}));
endcase
end
endgenerate
endmodule
module paramed (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter WIDTH = 1;
parameter MODE = 0;
input [WIDTH-1:0] in;
output [WIDTH-1:0] out;
generate
if (MODE==0) initial $write("Mode=0\n");
// No else
endgenerate
`ifndef NC // for(genvar) unsupported
`ifndef ATSIM // for(genvar) unsupported
generate
// Empty loop body, local genvar
for (genvar j=0; j<3; j=j+1) begin end
// Ditto to make sure j has new scope
for (genvar j=0; j<5; j=j+1) begin end
endgenerate
`endif
`endif
generate
endgenerate
genvar i;
generate
if (MODE==0) begin
// Flip bitorder, direct assign method
for (i=0; i<WIDTH; i=i+1) begin
assign out[i] = in[WIDTH-i-1];
end
end
else if (MODE==1) begin
// Flip using instantiation
for (i=0; i<WIDTH; i=i+1) begin
integer from = WIDTH-i-1;
if (i==0) begin // Test if's within a for
mbuf m0 (.q(out[i]), .a(in[from]));
end
else begin
mbuf ma (.q(out[i]), .a(in[from]));
end
end
end
else begin
for (i=0; i<WIDTH; i=i+1) begin
mbuf ma (.q(out[i]), .a(in[i^1]));
end
end
endgenerate
endmodule
module mbuf (
input a,
output q
);
assign q = a;
endmodule
module enflop (clk, oe_e1, a,q);
parameter WIDTH=1;
input clk;
input oe_e1;
input [WIDTH-1:0] a;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] oe_r;
reg [WIDTH-1:0] q_r;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits
enflop_one enflop_one
(.clk (clk),
.d (a[i]),
.q_r (q_r[i]));
always @(posedge clk) oe_r[i] <= oe_e1;
assign q[i] = oe_r[i] ? q_r[i] : 1'bx;
end
endgenerate
endmodule
module enflop_one (
input clk,
input d,
output reg q_r
);
always @(posedge clk) q_r <= d;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: efc_saed.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: Efuse Cluster
// Unit Name: efc_saed (synchronizer and edge detector)
// Files that must be included: none
//
//
//-----------------------------------------------------------------------------
`include "sys.h"
`include "iop.h"
module efc_saed (/*AUTOARG*/
// Outputs
rise_det, fall_det,
// Inputs
async_in, clk
);
//-----------------------------------------------------------------------------
// I/O declarations
//-----------------------------------------------------------------------------
// Chip Primary Inputs/Globals
output rise_det;
output fall_det;
input async_in;
input clk;
//-----------------------------------------------------------------------------
// Wire/reg declarations
//-----------------------------------------------------------------------------
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
wire snc1_ff;
wire snc2_ff;
wire hist_ff;
//-----------------------------------------------------------------------------
// Module Body
//-----------------------------------------------------------------------------
bw_u1_syncff_4x snc1_reg(
.so(),
.q (snc1_ff),
.ck (clk),
.d (async_in),
.sd(),
.se(1'b0));
dff_ns #(1) snc2_reg (.din(snc1_ff), .q(snc2_ff), .clk(clk));
dff_ns #(1) hist_reg (.din(snc2_ff), .q(hist_ff), .clk(clk));
assign rise_det = !hist_ff && snc2_ff;
assign fall_det = hist_ff && !snc2_ff;
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O21A_PP_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_PP_SYMBOL_V
|
#include <bits/stdc++.h> #pragma optimization_level 3 #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math,O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) using namespace std; const long long N = 1e6 + 5; const long long mod = 1e9 + 7; const long long INF = 0x7f7f7f7f7f7f7f7f; const int INFi = 0x7f7f7f7f; long long test = 1, n, m, a[N], sz = 0, tot, ch[N]; string second = 0 ; long long tree[N] = {}; void update(int idx, int val) { idx++; while (idx <= N - 1) { tree[idx] += val; idx += idx & (-idx); } } long long query(int idx) { idx++; long long sum = 0; while (idx > 0) { sum += tree[idx]; idx -= idx & (-idx); } return sum; } int bs(int x) { int l = 1, r = N - 1, ans = 0; while (l <= r) { int mid = (l + r) / 2; if (query(mid) >= x) { ans = mid; r = mid - 1; } else l = mid + 1; } return ans; } void solve() { cin >> n >> m; for (int i = 1; i <= m; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { int x; cin >> x; if (x == -1) { vector<long long> v; for (int i = 1; i <= m; i++) { if (a[i] > sz) break; v.push_back(bs(a[i])); } sz -= v.size(); for (auto it : v) ch[it] = 0, update(it, -1); } else { second += x + 0 ; sz++, tot++; update(tot, 1); ch[tot] = 1; } } if (sz == 0) cout << Poor stack! << n ; else { for (int i = 1; i <= tot; i++) { if (ch[i] == 1) cout << second[i]; } cout << n ; ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed; cout << setprecision(15); ; for (int i = 1; i <= test; i++) { solve(); } } |
`timescale 1ns / 1ps
module hankel_matrixd_d #(
parameter ROW = 4,
parameter COL = 4,
parameter WIDTH = 16,
parameter ADDR = 8
)(
input clk,
input start,
input [WIDTH-1:0] data,
output reg [ADDR-1:0] addr,
output reg rd
);
reg [WIDTH-1:0] mat [0:ROW-1] [0:COL-1];
reg [7:0] r,c,r_i,c_i,state;
reg [WIDTH-1:0] data_i;
reg [ADDR-1:0] addr_i;
parameter
IDLE = 2'b00,
INIT = 2'b01,
COPY = 2'b10,
WRITE= 2'b11;
initial begin
c <= 0;
r <= 0;
addr <=0;
//addr_i <=0;
rd<=0;
state <= IDLE;
end
always@(posedge clk) begin
case(state)
IDLE: begin
if(start)
state <= INIT;
rd <=1;
r<=0;
c<=0;
addr <=0;
end
INIT: begin
if(r==0) begin
mat[r][c] <= data;
c <= c+1;
addr <= addr+1;
if(c==COL-1) begin
c <= 0;
state <= COPY;
r <= r+1;
end
end
end
COPY: begin
if(r!=0) begin
mat[r][c] <= mat[r-1][c+1];
c <= c+1;
if(c==COL-2)begin
state <= WRITE;
rd <= 1;
addr <= addr+1;
end
end
end
WRITE: begin
mat[r][c]<= data;
state <= COPY;
r <= r+1;
c<=0;
if(r==ROW-1)
state <= IDLE;
end
endcase
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM pipeline bridge
//
// Optionally registers Avalon-MM command and response signals
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input clk,
input reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
// --------------------------------------
// Registers & signals
// --------------------------------------
reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount;
reg [DATA_WIDTH-1:0] cmd_writedata;
reg [HDL_ADDR_WIDTH-1:0] cmd_address;
reg cmd_write;
reg cmd_read;
reg [BYTEEN_WIDTH-1:0] cmd_byteenable;
wire cmd_waitrequest;
reg cmd_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount;
reg [DATA_WIDTH-1:0] wr_writedata;
reg [HDL_ADDR_WIDTH-1:0] wr_address;
reg wr_write;
reg wr_read;
reg [BYTEEN_WIDTH-1:0] wr_byteenable;
reg wr_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount;
reg [DATA_WIDTH-1:0] wr_reg_writedata;
reg [HDL_ADDR_WIDTH-1:0] wr_reg_address;
reg wr_reg_write;
reg wr_reg_read;
reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable;
reg wr_reg_waitrequest;
reg wr_reg_debugaccess;
reg use_reg;
wire wait_rise;
reg [DATA_WIDTH-1:0] rsp_readdata;
reg rsp_readdatavalid;
// --------------------------------------
// Command pipeline
//
// Registers all command signals, including waitrequest
// --------------------------------------
generate if (PIPELINE_COMMAND == 1) begin
// --------------------------------------
// Waitrequest Pipeline Stage
//
// Output waitrequest is delayed by one cycle, which means
// that a master will see waitrequest assertions one cycle
// too late.
//
// Solution: buffer the command when waitrequest transitions
// from low->high. As an optimization, we can safely assume
// waitrequest is low by default because downstream logic
// in the bridge ensures this.
//
// Note: this implementation buffers idle cycles should
// waitrequest transition on such cycles. This is a potential
// cause for throughput loss, but ye olde pipeline bridge did
// the same for years and no one complained. Not buffering idle
// cycles costs logic on the waitrequest path.
// --------------------------------------
assign s0_waitrequest = wr_reg_waitrequest;
assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest;
always @(posedge clk, posedge reset) begin
if (reset) begin
wr_reg_waitrequest <= 1'b1;
// --------------------------------------
// Bit of trickiness here, deserving of a long comment.
//
// On the first cycle after reset, the pass-through
// must not be used or downstream logic may sample
// the same command twice because of the delay in
// transmitting a falling waitrequest.
//
// Using the registered command works on the condition
// that downstream logic deasserts waitrequest
// immediately after reset, which is true of the
// next stage in this bridge.
// --------------------------------------
use_reg <= 1'b1;
wr_reg_burstcount <= 1'b1;
wr_reg_writedata <= 0;
wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}};
wr_reg_address <= 0;
wr_reg_write <= 1'b0;
wr_reg_read <= 1'b0;
wr_reg_debugaccess <= 1'b0;
end else begin
wr_reg_waitrequest <= cmd_waitrequest;
if (wait_rise) begin
wr_reg_writedata <= s0_writedata;
wr_reg_byteenable <= s0_byteenable;
wr_reg_address <= s0_address;
wr_reg_write <= s0_write;
wr_reg_read <= s0_read;
wr_reg_burstcount <= s0_burstcount;
wr_reg_debugaccess <= s0_debugaccess;
end
// stop using the buffer when waitrequest is low
if (~cmd_waitrequest)
use_reg <= 1'b0;
else if (wait_rise) begin
use_reg <= 1'b1;
end
end
end
always @* begin
wr_burstcount = s0_burstcount;
wr_writedata = s0_writedata;
wr_address = s0_address;
wr_write = s0_write;
wr_read = s0_read;
wr_byteenable = s0_byteenable;
wr_debugaccess = s0_debugaccess;
if (use_reg) begin
wr_burstcount = wr_reg_burstcount;
wr_writedata = wr_reg_writedata;
wr_address = wr_reg_address;
wr_write = wr_reg_write;
wr_read = wr_reg_read;
wr_byteenable = wr_reg_byteenable;
wr_debugaccess = wr_reg_debugaccess;
end
end
// --------------------------------------
// Master-Slave Signal Pipeline Stage
//
// One notable detail is that cmd_waitrequest is deasserted
// when this stage is idle. This allows us to make logic
// optimizations in the waitrequest pipeline stage.
//
// Also note that cmd_waitrequest is deasserted during reset,
// which is not spec-compliant, but is ok for an internal
// signal.
// --------------------------------------
wire no_command;
assign no_command = ~(cmd_read || cmd_write);
assign cmd_waitrequest = m0_waitrequest & ~no_command;
always @(posedge clk, posedge reset) begin
if (reset) begin
cmd_burstcount <= 1'b1;
cmd_writedata <= 0;
cmd_byteenable <= {BYTEEN_WIDTH{1'b1}};
cmd_address <= 0;
cmd_write <= 1'b0;
cmd_read <= 1'b0;
cmd_debugaccess <= 1'b0;
end
else begin
if (~cmd_waitrequest) begin
cmd_writedata <= wr_writedata;
cmd_byteenable <= wr_byteenable;
cmd_address <= wr_address;
cmd_write <= wr_write;
cmd_read <= wr_read;
cmd_burstcount <= wr_burstcount;
cmd_debugaccess <= wr_debugaccess;
end
end
end
end // conditional command pipeline
else begin
assign s0_waitrequest = m0_waitrequest;
always @* begin
cmd_burstcount = s0_burstcount;
cmd_writedata = s0_writedata;
cmd_address = s0_address;
cmd_write = s0_write;
cmd_read = s0_read;
cmd_byteenable = s0_byteenable;
cmd_debugaccess = s0_debugaccess;
end
end
endgenerate
assign m0_burstcount = cmd_burstcount;
assign m0_writedata = cmd_writedata;
assign m0_address = cmd_address;
assign m0_write = cmd_write;
assign m0_read = cmd_read;
assign m0_byteenable = cmd_byteenable;
assign m0_debugaccess = cmd_debugaccess;
// --------------------------------------
// Response pipeline
//
// Registers all response signals
// --------------------------------------
generate if (PIPELINE_RESPONSE == 1) begin
always @(posedge clk, posedge reset) begin
if (reset) begin
rsp_readdatavalid <= 1'b0;
rsp_readdata <= 0;
end
else begin
rsp_readdatavalid <= m0_readdatavalid;
rsp_readdata <= m0_readdata;
end
end
end // conditional response pipeline
else begin
always @* begin
rsp_readdatavalid = m0_readdatavalid;
rsp_readdata = m0_readdata;
end
end
endgenerate
assign s0_readdatavalid = rsp_readdatavalid;
assign s0_readdata = rsp_readdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int vv[3003] = {0}, vvv[3003] = {0}; int n, v, m = -1, k; cin >> n >> v; while (n--) { int a, b; cin >> a >> b; vv[a] += b; vvv[a + 1] += b; m = max(m, a + 1); } int ans = 0, mm; for (int i = 0; i <= m; i++) { mm = v; if (vvv[i]) { if (vvv[i] < mm) { ans += vvv[i]; mm -= vvv[i]; } else { ans += mm; mm = 0; } } if (mm) { if (vv[i] < mm) { ans += vv[i]; vvv[i + 1] -= vv[i]; } else { ans += mm; vvv[i + 1] -= mm; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> const long long LL_INF = (long long)2e18 + 5; using namespace std; const long long N = 2e5 + 10; void solve() { long long n, a0, a, b0, b, k; cin >> n; vector<long long> v(n), pref(n + 1); ; { for (auto &i : v) cin >> i; } sort(v.begin(), v.end()), reverse(v.begin(), v.end()); for (long long i = (long long)(1); i < (long long)(n + 1); i++) pref[i] = pref[i - 1] + v[i - 1]; cin >> a0 >> a >> b0 >> b >> k; if (a0 < b0) swap(a0, b0), swap(a, b); auto sum = [&](long long l, long long r) { return pref[r] - pref[l]; }; long long ctall = 0, cta = 0, ctb = 0; for (long long i = (long long)(1); i < (long long)(n + 1); i++) { if (i % a == 0 and i % b == 0) ctall++; else if (i % a == 0) cta++; else if (i % b == 0) ctb++; if (sum(0, ctall) * (a0 + b0) / 100 + sum(ctall, ctall + cta) * a0 / 100 + sum(ctall + cta, ctall + cta + ctb) * b0 / 100 >= k) { cout << i << n ; return; } } cout << -1 n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long tt; cin >> tt; while (tt--) solve(); } |
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; char c = getchar(); int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x *= f; } const int N = 505000; int n, a[N], ans[N]; int main() { read(n); for (int i = 1; i <= n; i++) read(a[i]); for (int i = 0; i <= n - 2; i++) { if ((n - i) & 1) ans[i] = max(min(a[(1 + n - i) / 2], max(a[(1 + n - i) / 2 + 1], a[(1 + n - i) / 2 - 1])), min(a[(1 + n + i) / 2], max(a[(1 + n + i) / 2 + 1], a[(1 + n + i) / 2 - 1]))); else ans[i] = max(a[(n - i + 1) / 2], a[(n + i + 2) / 2]); if ((n & 1) && i == 1) ans[i] = max(ans[i], a[n / 2 + 1]); if (i - 2 >= 0) ans[i] = max(ans[i], ans[i - 2]); } for (int i = 1; i <= n; i++) ans[n - 1] = max(ans[n - 1], a[i]); for (int i = 0; i <= n - 1; i++) printf( %d , ans[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_BLACKBOX_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:55:30 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_xbar_0_stub.v
// Design : ip_design_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[191:0],m_axi_awprot[17:0],m_axi_awvalid[5:0],m_axi_awready[5:0],m_axi_wdata[191:0],m_axi_wstrb[23:0],m_axi_wvalid[5:0],m_axi_wready[5:0],m_axi_bresp[11:0],m_axi_bvalid[5:0],m_axi_bready[5:0],m_axi_araddr[191:0],m_axi_arprot[17:0],m_axi_arvalid[5:0],m_axi_arready[5:0],m_axi_rdata[191:0],m_axi_rresp[11:0],m_axi_rvalid[5:0],m_axi_rready[5:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [191:0]m_axi_awaddr;
output [17:0]m_axi_awprot;
output [5:0]m_axi_awvalid;
input [5:0]m_axi_awready;
output [191:0]m_axi_wdata;
output [23:0]m_axi_wstrb;
output [5:0]m_axi_wvalid;
input [5:0]m_axi_wready;
input [11:0]m_axi_bresp;
input [5:0]m_axi_bvalid;
output [5:0]m_axi_bready;
output [191:0]m_axi_araddr;
output [17:0]m_axi_arprot;
output [5:0]m_axi_arvalid;
input [5:0]m_axi_arready;
input [191:0]m_axi_rdata;
input [11:0]m_axi_rresp;
input [5:0]m_axi_rvalid;
output [5:0]m_axi_rready;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [125:0] a;
wire q;
sub sub (
.q (q),
.a (a),
.clk (clk));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 126'b1000;
end
if (cyc==2) begin
a <= 126'h1001;
end
if (cyc==3) begin
a <= 126'h1010;
end
if (cyc==4) begin
a <= 126'h1111;
if (q !== 1'b0) $stop;
end
if (cyc==5) begin
if (q !== 1'b1) $stop;
end
if (cyc==6) begin
if (q !== 1'b0) $stop;
end
if (cyc==7) begin
if (q !== 1'b0) $stop;
end
if (cyc==8) begin
if (q !== 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (
input clk,
input [125:0] a,
output reg q
);
// verilator public_module
reg [125:0] g_r;
wire [127:0] g_extend = { g_r, 1'b1, 1'b0 };
reg [6:0] sel;
wire g_sel = g_extend[sel];
always @ (posedge clk) begin
g_r <= a;
sel <= a[6:0];
q <= g_sel;
end
endmodule
|
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