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#include <bits/stdc++.h> using namespace std; long long gcd(long long u, long long v) { while (v != 0) { long long r = u % v; u = v; v = r; } return u; } typedef struct State { char cnt[21]; char top[3]; } State; inline bool operator<(const State &a, const State &b) { return memcmp(&a, &b, sizeof(State)) < 0; } int nways[3]; int need[3][16], gain[3][16]; char color[3] = { B , G , R }; char name[21][4] = { B , G , R , BBB , BBG , BBR , BGB , BGG , BGR , BRB , BRG , BRR , GBG , GBR , GGG , GGR , GRG , GRR , RBR , RGR , RRR }; void init() { memset(nways, 0, sizeof(nways)); for (int i = (0); i < (3); ++i) { int x = name[i][0] == B ? 0 : name[i][0] == G ? 1 : 2; need[x][nways[x]] = i; gain[x][nways[x]] = -1; ++nways[x]; } for (int i = (3); i < (21); ++i) for (int j = (0); j < (3); ++j) { if (j == 2 && name[i][0] == name[i][2]) continue; int x = name[i][j] == B ? 0 : name[i][j] == G ? 1 : 2; int y = name[i][2 - j] == B ? 0 : name[i][2 - j] == G ? 1 : 2; need[x][nways[x]] = i; gain[x][nways[x]] = j == 1 ? -1 : y; ++nways[x]; } for (int i = (0); i < (3); ++i) assert(nways[i] == 16); } int encode(char s[3]) { for (int i = (3); i < (21); ++i) if (s[0] == name[i][0] && s[1] == name[i][1] && s[2] == name[i][2]) return i; assert(false); return -1; } map<State, double> mem; double go(State &s) { map<State, double>::iterator retit = mem.find(s); if (retit != mem.end()) return retit->second; char oldtop[3]; int gaintop = -1; bool fulltop = true; for (int k = (0); k < (3); ++k) if (s.top[k] == ? ) fulltop = false; if (fulltop) { for (int k = (0); k < (3); ++k) oldtop[k] = s.top[k]; gaintop = encode(s.top); for (int k = (0); k < (3); ++k) s.top[k] = ? ; } int nwait = 1; double sum = 0; for (int i = (0); i < (3); ++i) { int times = i == 2 ? 1 : 2; bool any = false; double best = -1; for (int j = (0); j < (nways[i]); ++j) if (s.cnt[need[i][j]] > 0) for (int k = (0); k < (3); ++k) { if (s.top[k] != ? || k == 2 && s.top[0] == ? ) continue; s.top[k] = color[i]; bool swaptop = false; if (k == 2 && s.top[0] > s.top[2]) { swaptop = true; swap(s.top[0], s.top[2]); } --s.cnt[need[i][j]]; if (gain[i][j] != -1) ++s.cnt[gain[i][j]]; if (gaintop != -1) ++s.cnt[gaintop]; double cur = go(s); if (!any || cur < best) any = true, best = cur; if (gaintop != -1) --s.cnt[gaintop]; if (gain[i][j] != -1) --s.cnt[gain[i][j]]; ++s.cnt[need[i][j]]; if (swaptop) swap(s.top[0], s.top[2]); s.top[k] = ? ; } if (!any) nwait += times; else sum += times * best; } if (fulltop) { for (int k = (0); k < (3); ++k) s.top[k] = oldtop[k]; } double ret = nwait == 6 ? 0.0 : (6 + sum) / (6 - nwait); return mem[s] = ret; } char sinit[6][3]; void run() { int n; scanf( %d , &n); for (int i = (0); i < (n); ++i) for (int j = (0); j < (3); ++j) scanf( %c , &sinit[i][j]); for (int i = (0); i < (n); ++i) if (sinit[i][0] > sinit[i][2]) swap(sinit[i][0], sinit[i][2]); State init; for (int j = (0); j < (21); ++j) init.cnt[j] = 0; for (int i = (0); i < (n - 1); ++i) init.cnt[encode(sinit[i])]++; for (int k = (0); k < (3); ++k) init.top[k] = sinit[n - 1][k]; double ret = go(init); printf( %.9lf n , ret); } int main() { init(); run(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int inf = 1e9 + 9; const long long int MOD = 1e9 + 696969; const long long INF = 4LL * 1000000LL * 1000000LL * 1000000LL; template <class T> int size(T &&x) { return int(x.size()); } template <class A, class B> ostream &operator<<(ostream &out, const pair<A, B> &p) { return out << ( << p.first << , << p.second << ) ; } template <class T> auto operator<<(ostream &out, T &&x) -> decltype(x.begin(), out) { out << { ; for (auto it = x.begin(); it != x.end(); ++it) out << *it << (it == prev(x.end()) ? : , ); return out << } ; } void dump() {} template <class T, class... Args> void dump(T &&x, Args... args) { cerr << x << ; ; dump(args...); } mt19937_64 rng(0); int random(int l, int r) { return uniform_int_distribution<int>(l, r)(rng); } inline void addmod(int &x, int val) { x += val; while (x >= mod) x -= mod; } const int maxn = 300100; int dr[maxn]; int n, m, tab[maxn]; int N; int temp[maxn]; inline void add(int p, int val) { for (; p <= n; p += p & (-p)) dr[p] += val; } inline int get(int p) { if (p == 0) return 0; int res = 0; for (; p > 0; p -= p & (-p)) res += dr[p]; return res; } map<long long, long long> M; vector<pair<int, int> > skal; int cnt = 0; long long inversions(int base) { if (M.find(base) != M.end()) return M[base]; skal.resize(n); ++cnt; for (int i = (1); i <= (n); ++i) skal[i - 1] = make_pair(tab[i] ^ base, i); sort(skal.begin(), skal.end()); for (int i = 0; i < n; ++i) temp[skal[i].second] = i + 1; long long res = 0; fill(dr, dr + n + 1, 0); for (int i = n; i > 0; --i) { res += get(temp[i]); add(temp[i], 1); } M[base] = res; return res; } void solveone() { cin >> n; for (int i = (1); i <= (n); ++i) { cin >> tab[i]; } int b = 0; for (int bit = 29; bit >= 0; --bit) { if (inversions(b) > inversions(b + (1 << bit))) b += (1 << bit); } cout << inversions(b) << << b << n ; } int main() { { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); }; int tests; tests = 1; for (int _ = (1); _ <= (tests); ++_) solveone(); } |
#include <bits/stdc++.h> using namespace std; struct res { double l, r, w; } T[800000]; double x[210000], s[210000], p, c, ans, w; int N, M, i, l, r; int init(int i, int l, int r, int x, double w) { if (x < l || r < x) return 0; if (l == r) { T[i].w = T[i].l = T[i].r = w; return 0; } int mid = l + r >> 1; init(i * 2, l, mid, x, w); init(i * 2 + 1, mid + 1, r, x, w); } int build(int i, int l, int r) { if (l == r) return 0; int mid = l + r >> 1, ls = i << 1, rs = (i << 1) + 1; build(ls, l, mid); build(rs, mid + 1, r); T[i].l = max(T[ls].l, s[mid] - s[l - 1] + T[rs].l); T[i].r = max(T[rs].r, T[ls].r + s[r] - s[mid]); T[i].w = max(T[ls].r + T[rs].l, max(max(T[ls].w, T[rs].w), max(T[i].l, T[i].r))); } res get(int i, int l, int r, int x, int y) { if (x <= l && r <= y) return T[i]; int mid = l + r >> 1, ls = i << 1, rs = (i << 1) + 1; res X; if (y <= mid) X = get(ls, l, mid, x, y); else if (mid < x) X = get(rs, mid + 1, r, x, y); else { res L = get(ls, l, mid, x, mid); res R = get(rs, mid + 1, r, mid + 1, y); X.w = max(max(L.w, R.w), L.r + R.l); X.l = max(L.l, s[mid] - s[x - 1] + R.l); X.r = max(R.r, s[y] - s[mid] + L.r); } return X; } int main() { scanf( %d%d%lf , &N, &M, &c); for (i = 1; i <= N; i++) scanf( %lf , &x[i]); --N; for (i = 1; i <= N; i++) { scanf( %lf , &p); w = (x[i + 1] - x[i]) / 2.0 - p * c / 100.0; s[i] = s[i - 1] + w; init(1, 1, N, i, w); } build(1, 1, N); while (M--) { scanf( %d%d , &l, &r); res delta = get(1, 1, N, l, r - 1); ans += max(0.0, delta.w); } printf( %.8lf n , ans); } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long int md[500]; signed main() { ios ::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long int n; cin >> n; for (long long int i = 0; i < 500; i++) md[i] = -1; for (long long int i = 0; i <= 8; i++) { for (long long int j = 0; j <= 48; j++) { long long int val = 4 * i + 9 * j; val %= 49; if (i + j > n) continue; md[val] = max(md[val], n - i - j); } } long long int ans = 0; for (long long int i = 0; i < 500; i++) { ans += md[i] + 1; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; void fre() { freopen( c://test//input.in , r , stdin); freopen( c://test//output.out , w , stdout); } template <class T1, class T2> inline void gmax(T1 &a, T2 b) { if (b > a) a = b; } template <class T1, class T2> inline void gmin(T1 &a, T2 b) { if (b < a) a = b; } const int N = 1e5 + 10, inf = 0x3f3f3f3f; int n, Z; long long mul[N]; long long inv[N]; vector<pair<int, int> > a[N]; int sz[N]; int mxp[N]; bool done[N]; int root; int treesz; map<int, int> mop; int getsz(int x, int fa) { sz[x] = 1; for (int i = a[x].size() - 1; ~i; --i) { int y = a[x][i].first; if (y == fa || done[y]) continue; sz[x] += getsz(y, x); } return sz[x]; } void getroot(int x, int fa) { mxp[x] = treesz - sz[x]; for (auto &it : a[x]) { int y = it.first; if (y == fa || done[y]) continue; getroot(y, x); gmax(mxp[x], sz[y]); } if (mxp[x] < mxp[root]) root = x; } long long ans, sig; void dfs1(int x, int fa, int val, int dep) { sig += (val == 0); ans += mop[(Z - val) * inv[dep] % Z]; for (auto &it : a[x]) { if (it.first == fa || done[it.first]) continue; dfs1(it.first, x, (val * 10ll + it.second) % Z, dep + 1); } } void dfs2(int x, int fa, int val, int dep) { sig += (val == 0); ++mop[val]; for (auto &it : a[x]) { if (it.first == fa || done[it.first]) continue; dfs2(it.first, x, (val + it.second * mul[dep]) % Z, dep + 1); } } void cal(int x) { mop.clear(); for (auto &it : a[x]) { int y = it.first; if (done[y]) continue; int z = it.second; dfs1(y, x, z, 1); dfs2(y, x, z, 1); } reverse(a[x].begin(), a[x].end()); mop.clear(); for (auto &it : a[x]) { int y = it.first; if (done[y]) continue; int z = it.second; dfs1(y, x, z, 1); dfs2(y, x, z, 1); } } void dfz(int x) { treesz = getsz(x, 0); getroot(x, root = 0); cal(root); done[root] = 1; for (auto &it : a[root]) if (!done[it.first]) dfz(it.first); } void exgcd(long long a, long long b, long long &d, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; d = a; } else { exgcd(b, a % b, d, y, x); y -= a / b * x; } } long long INV(long long a, long long Z) { long long x, y, d; exgcd(a, Z, d, x, y); if (d == 1) return (x % Z + Z) % Z; else return -1; } int main() { mxp[0] = inf; while (~scanf( %d%d , &n, &Z)) { mul[0] = 1; mul[1] = 10 % Z; inv[0] = 1; inv[1] = INV(10, Z); for (int i = 2; i <= n; ++i) { mul[i] = mul[i - 1] * 10 % Z; inv[i] = inv[i - 1] * inv[1] % Z; } for (int i = 1; i <= n; ++i) { a[i].clear(); done[i] = 0; } for (int i = 1; i < n; ++i) { int x, y, z; scanf( %d%d%d , &x, &y, &z); ++x; ++y; z %= Z; a[x].push_back({y, z}); a[y].push_back({x, z}); } ans = sig = 0; treesz = n; dfz(1); printf( %lld n , ans + sig / 2); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5, M = 2e3 + 5; const long long INF = 1e18 + 5; inline long long read() { long long sum = 0, fh = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fh = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum * fh; } inline int read2() { char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); return c - 0 ; } inline int read3() { char c = getchar(); while (c < a || c > z ) { c = getchar(); } return c - a ; } inline void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } inline int gcd(int x, int y) { return y == 0 ? x : gcd(y, x % y); } inline long long ab(long long x) { return x < 0 ? -x : x; } inline long long fpow(long long qwe, long long asd, long long zxc) { if (asd < 0) return 0; long long a = qwe, b = 1, c = asd; while (c) { if (c & 1) b = b * a % zxc; a = a * a % zxc; c >>= 1; } return b; } struct miaow { int f, t, l; long long c; miaow(int f = 0, int t = 0, long long c = 0, int l = 0) : f(f), t(t), c(c), l(l) {} } imap[N * 2 + 5]; int str[N * 2 + 5] = {0}, cou = 2; inline void jb(int f, int t, long long c = 0) { imap[cou] = miaow(f, t, c, str[f]); str[f] = cou++; imap[cou] = miaow(t, f, c, str[t]); str[t] = cou++; } struct meow { long long t, x, y; meow(long long t = 0, long long x = 0, long long y = 0) : t(t), x(x), y(y) {} inline bool operator<(const meow& qwe) const { return t == qwe.t ? x < qwe.x : t > qwe.t; } }; int sy[N][2]; long long dp[N][2], zz[N], p = 1e9 + 7, ans = 0; priority_queue<meow> qwe; int main() { int n = read(), m = read(); long long q = read(), ny = fpow(2, p - 2, p); meow zxczxc = (0, 0, 0); for (int i = 1; i <= m; ++i) { int x = read(), y = read(), z = read(); jb(x, y, z); zxczxc = min(zxczxc, meow(z, x, y)); } sy[1][0] = 1; int cs = 1; for (int i = 1; i <= min(q, m * 2 + (long long)1); ++i) { for (int j = 1; j <= n; ++j) dp[i][cs] = sy[i][cs] = 0, zz[i] = 0; long long sum = 0; for (int j = 2; j < cou; ++j) { int f = imap[j].f, t = imap[j].t; long long c = imap[j].c; if (sy[f][cs ^ 1]) { sy[t][cs] = 1; if (dp[t][cs] < dp[f][cs ^ 1] + c) { dp[t][cs] = dp[f][cs ^ 1] + c; zz[t] = c; } else if (dp[t][cs] == dp[f][cs ^ 1] + c && c > zz[t]) zz[t] = c; sum = max(sum, dp[t][cs]); } } cs ^= 1; if (i != m * 2 + 1ll || i == q) ans = (ans + sum) % p; } long long t = m * 2 + 1, x = 0, y = 0; vector<meow> zzz; for (int i = 1; i <= n; ++i) { long long y1 = zz[i], x1 = dp[i][1]; if (x1 > x) { x = x1, y = y1; } else if (x1 == x && y1 > y) y = y1; for (int j = i + 1; j <= n; ++j) { long long y2 = zz[j], x2 = dp[j][1]; long long x3 = x1, y3 = y1; if (y2 < y3) { if (x2 <= x3) continue; swap(y3, y2), swap(x3, x2); } else if (y2 > y3) { if (x2 >= x3) continue; } else continue; long long tt = (x3 - x2) / (y2 - y3); qwe.push(meow(t + tt + 1, x2 + (tt + 1) * y2, y2)); if (x2 + (tt + 1) * y2 < 0) exit(1); } } long long ttt = t, aaa = ans, xxx = x, yyy = y; if (t > q) { cout << ans << endl; return 0; } qwe.push(meow(q, 0, 0)); long long tbj = 0; while (t < q) { meow asd = qwe.top(); qwe.pop(); long long t2 = asd.t, x2 = asd.x, y2 = asd.y; if (t2 < t) continue; if (t2 != t) ans = (ans + (x + x + (t2 - t - 1) * y) % p * (t2 - t) % p * ny % p) % p; x = x + y * (t2 - t); if (x < x2) { if (!tbj) tbj = t2; x = x2, y = y2; } else if (x == x2 && y < y2) { if (!tbj) tbj = t2; y = y2; } t = t2; } ans = (ans + x) % p; if (ans == 30604365) { for (int i = 0; i < zzz.size(); ++i) cout << zzz[i].t << << zzz[i].x << << zzz[i].y << endl; } if (ans == 30604365) cout << x << << y << << t << << tbj << endl; if (ans == 30604365) cout << xxx << << yyy << << ttt << << aaa << endl; cout << ans << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// Module block_sync_sm
// Generated by Xilinx Aurora 64B66B
`timescale 1 ps / 1 ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_BLOCK_SYNC_SM #
(
parameter SH_CNT_MAX = 16'd64,
parameter SH_INVALID_CNT_MAX = 10'd16
)
(
// User Interface
BLOCKSYNC_OUT,
RXGEARBOXSLIP_OUT,
RXHEADER_IN,
RXHEADERVALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations*******************************
// User Interface
output BLOCKSYNC_OUT;
output RXGEARBOXSLIP_OUT;
input [1:0] RXHEADER_IN;
input RXHEADERVALID_IN;
// System Interface
input USER_CLK;
input SYSTEM_RESET;
//***************************External Register Declarations***************************
reg BLOCKSYNC_OUT;
reg RXGEARBOXSLIP_OUT;
//**************************** Wire Declarations ******************************
reg next_begin_c;
reg next_sh_invalid_c;
reg next_sh_valid_c;
reg next_slip_c;
reg next_sync_done_c;
reg next_test_sh_c;
wire sh_count_equals_max_i;
wire sh_invalid_cnt_equals_max_i;
wire sh_invalid_cnt_equals_zero_i;
wire slip_done_i;
wire sync_found_i;
//***************************External Register Declarations***************************
reg begin_r;
reg sh_invalid_r;
reg sh_valid_r;
reg [15:0] slip_count_i;
reg slip_r;
reg sync_done_r;
reg [15:0] sync_header_count_i;
reg [9:0] sync_header_invalid_count_i;
reg test_sh_r;
reg system_reset_r;
reg system_reset_r2;
//**************************** Main Body of Code *******************************
assign sync_found_i = (RXHEADER_IN == 2'b01) || (RXHEADER_IN == 2'b10);
// Double Synchronize SYSTEM_RESET wrt USER_CLK
always @(posedge USER_CLK)
begin
system_reset_r <= `DLY SYSTEM_RESET;
system_reset_r2 <= `DLY system_reset_r;
end
//________________________________ State machine __________________________
// State registers
always @(posedge USER_CLK)
if(system_reset_r2)
{begin_r,test_sh_r,sh_valid_r,sh_invalid_r,slip_r,sync_done_r} <= `DLY 6'b100000;
else
begin
begin_r <= `DLY next_begin_c;
test_sh_r <= `DLY next_test_sh_c;
sh_valid_r <= `DLY next_sh_valid_c;
sh_invalid_r <= `DLY next_sh_invalid_c;
slip_r <= `DLY next_slip_c;
sync_done_r <= `DLY next_sync_done_c;
end
/*
// Next state logic
assign next_begin_c = sync_done_r
| (slip_r && slip_done_i)
| (sh_valid_r && sh_count_equals_max_i && !sh_invalid_cnt_equals_max_i)
| (sh_invalid_r && sh_count_equals_max_i && !sh_invalid_cnt_equals_max_i && BLOCKSYNC_OUT);
assign next_test_sh_c = begin_r
| (test_sh_r && !RXHEADERVALID_IN)
| (sh_valid_r && !sh_count_equals_max_i)
| (sh_invalid_r && !sh_count_equals_max_i && !sh_invalid_cnt_equals_max_i && BLOCKSYNC_OUT);
assign next_sh_valid_c = (test_sh_r && RXHEADERVALID_IN && sync_found_i);
assign next_sh_invalid_c = (test_sh_r && RXHEADERVALID_IN && !sync_found_i);
assign next_slip_c = (sh_invalid_r && (sh_invalid_cnt_equals_max_i || !BLOCKSYNC_OUT))
| (slip_r && !slip_done_i);
assign next_sync_done_c = (sh_valid_r && sh_count_equals_max_i && sh_invalid_cnt_equals_zero_i);
*/
// FSM is same as above, but recoded as priority muxes
localparam BEGIN_R_ST = 6'b100000,
TEST_SH_ST = 6'b010000,
SH_VALID_ST = 6'b001000,
SH_INVALID_ST = 6'b000100,
SLIP_R_ST = 6'b000010,
SYNC_DONE_R_ST = 6'b000001;
always @(*)
begin
{next_begin_c,next_test_sh_c,next_sh_valid_c,next_sh_invalid_c,next_slip_c,next_sync_done_c} = 6'b000000;
case({begin_r,test_sh_r,sh_valid_r,sh_invalid_r,slip_r,sync_done_r})
BEGIN_R_ST:
begin
next_test_sh_c = 1'b1;
end
TEST_SH_ST:
begin
if(RXHEADERVALID_IN)
begin
if(sync_found_i)
next_sh_valid_c = 1'b1;
else
next_sh_invalid_c = 1'b1;
end
else
next_test_sh_c = 1'b1;
end
SH_VALID_ST:
begin
if(sh_count_equals_max_i)
begin
if(sh_invalid_cnt_equals_zero_i)
next_sync_done_c = 1'b1;
else if((sh_invalid_cnt_equals_max_i | !BLOCKSYNC_OUT))
next_slip_c = 1'b1;
else
next_begin_c = 1'b1;
end
//check_me if(sh_count_equals_max_i)
//check_me begin
//check_me if(sh_invalid_cnt_equals_zero_i)
//check_me next_sync_done_c = 1'b1;
//check_me else if(!sh_invalid_cnt_equals_max_i)
//check_me next_begin_c = 1'b1;
//check_me end
else
next_test_sh_c = 1'b1;
end
SH_INVALID_ST:
begin
if(sh_invalid_cnt_equals_max_i)
next_slip_c = 1'b1;
else
begin
if(!BLOCKSYNC_OUT)
next_slip_c = 1'b1;
else if(sh_count_equals_max_i)
next_begin_c = 1'b1;
else
next_test_sh_c = 1'b1;
end
end
SLIP_R_ST:
begin
if(slip_done_i)
next_begin_c =1'b1;
else
next_slip_c = 1'b1;
end
SYNC_DONE_R_ST:
begin
next_begin_c = 1'b1;
end
default:
begin
next_begin_c = 1'b1;
end
endcase
end
//________________ Counter keep track of sync headers counted _____________
always @(posedge USER_CLK)
if(begin_r)
begin
sync_header_count_i <= `DLY 16'd0;
end
else if (sh_valid_r || sh_invalid_r)
begin
sync_header_count_i <= `DLY sync_header_count_i + 16'd1;
end
assign sh_count_equals_max_i = (sync_header_count_i==SH_CNT_MAX);
//________________ Counter keep track of invalid sync headers ____________
always @(posedge USER_CLK)
if(begin_r)
begin
sync_header_invalid_count_i <= `DLY 10'd0;
end
else if (sh_invalid_r)
begin
sync_header_invalid_count_i <= `DLY sync_header_invalid_count_i + 10'd1;
end
// signal to indicate max number of invalid sync headers has been reached
assign sh_invalid_cnt_equals_max_i = (sync_header_invalid_count_i==SH_INVALID_CNT_MAX);
// signal to indicate no invalid sync headers
assign sh_invalid_cnt_equals_zero_i = (sync_header_invalid_count_i==0);
//_______ Counter wait for 16 cycles to ensure that slip is complete _______
wire slip_pulse_i = next_slip_c && !slip_r;
always @(posedge USER_CLK)
RXGEARBOXSLIP_OUT <= slip_pulse_i;
//_____________ Ouput assignment to indicate block sync complete _________
always @(posedge USER_CLK)
if(!slip_r) slip_count_i <= `DLY 16'h0000;
else slip_count_i <= `DLY {slip_count_i[14:0],RXGEARBOXSLIP_OUT};
assign slip_done_i = slip_count_i[15];
//_____________ Pulse GEARBOXSLIP port to slip the data by 1 bit _________
always @(posedge USER_CLK)
if(system_reset_r2 || slip_r) BLOCKSYNC_OUT <= `DLY 1'b0;
else if (sync_done_r) BLOCKSYNC_OUT <= `DLY 1'b1;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:25 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_stub.v
// Design : ip_design_nco_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "nco,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB, s_axi_AXILiteS_WVALID, s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP, s_axi_AXILiteS_BVALID, s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR, s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA, s_axi_AXILiteS_RRESP, s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY, ap_clk, ap_rst_n)
/* synthesis syn_black_box black_box_pad_pin="s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n" */;
input [5:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [31:0]s_axi_AXILiteS_WDATA;
input [3:0]s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
output [1:0]s_axi_AXILiteS_BRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
input [5:0]s_axi_AXILiteS_ARADDR;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
output [31:0]s_axi_AXILiteS_RDATA;
output [1:0]s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
input ap_clk;
input ap_rst_n;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLRBP_BEHAVIORAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000010; unordered_map<int, vector<pair<int, int> > > rows; unordered_map<int, vector<pair<int, int> > > cols; int n, m; int cnum; map<pair<int, int>, int> id; map<pair<int, int>, vector<pair<int, int> > > adj1; unordered_map<int, vector<int> > adj2; int dp[MAXN]; void fgreat(const vector<pair<int, int> >& v, int row, int col) { int sz = v.size(); for (int i = 0; i < (sz - 1); ++i) if (v[i].first < v[i + 1].first) { if (row == -1) { adj2[id[make_pair(v[i + 1].second, col)]].push_back( id[make_pair(v[i].second, col)]); } else { adj2[id[{row, v[i + 1].second}]].push_back( id[make_pair(row, v[i].second)]); } } } void fequal(const vector<pair<int, int> >& v, int row, int col) { int sz = v.size(); for (int i = 0; i < (sz - 1); ++i) if (v[i].first == v[i + 1].first) { if (row == -1) { adj1[{v[i].second, col}].push_back(make_pair(v[i + 1].second, col)); adj1[{v[i + 1].second, col}].push_back(make_pair(v[i].second, col)); } else { adj1[{row, v[i].second}].push_back(make_pair(row, v[i + 1].second)); adj1[{row, v[i + 1].second}].push_back(make_pair(row, v[i].second)); } } } void dfs(int sx, int sy) { id[{sx, sy}] = cnum; const auto& v = adj1[{sx, sy}]; for (__typeof((v).begin()) it = (v).begin(); it != (v).end(); ++it) if (!id.count(*it)) { dfs(it->first, it->second); } } int solve(int id) { int& ans = dp[id]; if (ans != -1) return ans; ans = 0; const auto& v = adj2[id]; for (__typeof((v).begin()) it = (v).begin(); it != (v).end(); ++it) ans = max(ans, solve(*it)); return ++ans; } int main() { scanf( %d %d , &(n), &(m)); for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) { int x; scanf( %d , &(x)); rows[i].push_back(make_pair(x, j)); cols[j].push_back(make_pair(x, i)); } for (__typeof((rows).begin()) it = (rows).begin(); it != (rows).end(); ++it) { auto& v = it->second; sort(v.begin(), v.end()); } for (__typeof((cols).begin()) it = (cols).begin(); it != (cols).end(); ++it) { auto& v = it->second; sort(v.begin(), v.end()); } for (__typeof((rows).begin()) it = (rows).begin(); it != (rows).end(); ++it) { fequal(it->second, it->first, -1); } for (__typeof((cols).begin()) it = (cols).begin(); it != (cols).end(); ++it) { fequal(it->second, -1, it->first); } for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) if (!id.count({i, j})) { dfs(i, j); ++cnum; } for (__typeof((rows).begin()) it = (rows).begin(); it != (rows).end(); ++it) { fgreat(it->second, it->first, -1); } for (__typeof((cols).begin()) it = (cols).begin(); it != (cols).end(); ++it) { fgreat(it->second, -1, it->first); } memset(dp, -1, sizeof(dp)); for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) { if (j) printf( ); printf( %d , solve(id[{i, j}])); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, q, a[int(2e5)], sz; set<pair<int, int> > st; int main() { cin >> n >> k >> q; for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = 0; i < q; ++i) { int x, y; cin >> x >> y; if (x == 1) { st.insert(make_pair(a[y - 1], y)); sz++; if (sz > k) { st.erase(st.begin()); sz--; } } else { if (st.find(make_pair(a[y - 1], y)) != st.end()) { cout << YES n ; } else { cout << NO n ; } } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLYGATE4SD2_BEHAVIORAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD2_BEHAVIORAL_PP_V |
//
// Copyright (c) 2002 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic reg form
//
//
module basicreg ( clk, d, q);
input clk, d;
output [2:0] q;
reg [2:0] q;
always @(posedge clk)
begin
q <= d + d;
end
endmodule
module test ;
reg clk, d;
wire [2:0] q;
basicreg u_reg (clk,d,q);
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
clk = 0;
d = 0;
# 1;
clk = 1;
# 1;
if (q !== 3'b0)
begin
$display("FAILED - Q isn't 0 on first edge");
$finish;
end
d = 1;
# 1;
clk = 0;
# 1;
if (q !== 3'b0)
begin
$display("FAILED - Q isn't 0 after first falling edge");
$finish;
end
# 1;
clk = 1;
# 1;
if (q !== 3'b010)
begin
#1 ;
$display("FAILED - Q isn't 2 2nd raising edge");
$finish;
end
# 1;
clk = 0;
# 1;
if (q !== 3'b010)
begin
$display("FAILED - Q isn't 2 after 2nd falling edge");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename flow_t = int, typename cost_t = int> struct mcSFlow { struct Edge { cost_t c; flow_t f; int to, rev; Edge(int _to, cost_t _c, flow_t _f, int _rev) : c(_c), f(_f), to(_to), rev(_rev) {} }; const cost_t INFCOST = numeric_limits<cost_t>::max() / 2; const cost_t INFFLOW = numeric_limits<flow_t>::max() / 2; cost_t epsilon; int N, S, T; vector<vector<Edge> > G; vector<unsigned int> isEnqueued, state; mcSFlow(int _N, int _S, int _T) : epsilon(0), N(_N), S(_S), T(_T), G(_N) {} void add_edge(int a, int b, cost_t cost, flow_t cap) { if (a == b) { assert(cost >= 0); return; } cost *= N; epsilon = max(epsilon, abs(cost)); assert(a >= 0 && a < N && b >= 0 && b < N); G[a].emplace_back(b, cost, cap, G[b].size()); G[b].emplace_back(a, -cost, 0, G[a].size() - 1); } flow_t calc_max_flow() { vector<flow_t> dist(N), state(N); vector<Edge *> path(N); auto cmp = [](Edge *a, Edge *b) { return a->f < b->f; }; flow_t addFlow, retflow = 0; ; do { fill(dist.begin(), dist.end(), -1); dist[S] = 0; auto head = state.begin(), tail = state.begin(); for (*tail++ = S; head != tail; ++head) { for (Edge const &e : G[*head]) { if (e.f && dist[e.to] == -1) { dist[e.to] = dist[*head] + 1; *tail++ = e.to; } } } addFlow = 0; fill(state.begin(), state.end(), 0); auto top = path.begin(); Edge dummy(S, 0, INFFLOW, -1); *top++ = &dummy; while (top != path.begin()) { int n = (*prev(top))->to; if (n == T) { auto next_top = min_element(path.begin(), top, cmp); flow_t flow = (*next_top)->f; while (--top != path.begin()) { Edge &e = **top, &f = G[e.to][e.rev]; e.f -= flow; f.f += flow; } addFlow = 1; retflow += flow; top = next_top; continue; } for (flow_t &i = state[n], i_max = G[n].size(), need = dist[n] + 1;; ++i) { if (i == i_max) { dist[n] = -1; --top; break; } if (dist[G[n][i].to] == need && G[n][i].f) { *top++ = &G[n][i]; break; } } } } while (addFlow); return retflow; } vector<flow_t> excess; vector<cost_t> h; void push(Edge &e, flow_t amt) { if (e.f < amt) amt = e.f; e.f -= amt; excess[e.to] += amt; G[e.to][e.rev].f += amt; excess[G[e.to][e.rev].to] -= amt; } void relabel(int vertex) { cost_t newHeight = -INFCOST; for (unsigned int i = 0; i < G[vertex].size(); ++i) { Edge const &e = G[vertex][i]; if (e.f && newHeight < h[e.to] - e.c) { newHeight = h[e.to] - e.c; state[vertex] = i; } } h[vertex] = newHeight - epsilon; } const int scale = 2; pair<flow_t, cost_t> minCostFlow() { cost_t retCost = 0; for (int i = 0; i < N; ++i) { for (Edge &e : G[i]) { retCost += e.c * (e.f); } } flow_t retFlow = calc_max_flow(); excess.resize(N); h.resize(N); queue<int> q; isEnqueued.assign(N, 0); state.assign(N, 0); for (; epsilon; epsilon >>= scale) { fill(state.begin(), state.end(), 0); for (int i = 0; i < N; ++i) for (auto &e : G[i]) if (h[i] + e.c - h[e.to] < 0 && e.f) push(e, e.f); for (int i = 0; i < N; ++i) { if (excess[i] > 0) { q.push(i); isEnqueued[i] = 1; } } while (!q.empty()) { int cur = q.front(); q.pop(); isEnqueued[cur] = 0; while (excess[cur] > 0) { if (state[cur] == G[cur].size()) { relabel(cur); } for (unsigned int &i = state[cur], max_i = G[cur].size(); i < max_i; ++i) { Edge &e = G[cur][i]; if (h[cur] + e.c - h[e.to] < 0) { push(e, excess[cur]); if (excess[e.to] > 0 && isEnqueued[e.to] == 0) { q.push(e.to); isEnqueued[e.to] = 1; } if (excess[cur] == 0) break; } } } } if (epsilon > 1 && epsilon >> scale == 0) { epsilon = 1 << scale; } } for (int i = 0; i < N; ++i) { for (Edge &e : G[i]) { retCost -= e.c * (e.f); } } return make_pair(retFlow, retCost / 2 / N); } flow_t getFlow(Edge const &e) { return G[e.to][e.rev].f; } }; const int N = 260, M = 30, inf = 1e5 + 42; int a[N]; char var[N]; int val[M]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; int act_source = 0, source = 1, sink = 2 * n + 2; mcSFlow<long long, long long> mf(sink + 1, act_source, sink); mf.add_edge(act_source, source, 0, m); mf.add_edge(source, sink, 0, inf); for (int i = 1; i <= n; ++i) { cin >> a[i]; mf.add_edge(source, 2 * i, __builtin_popcount(a[i]), inf); mf.add_edge(2 * i, 2 * i + 1, -inf, 1); mf.add_edge(2 * i + 1, sink, 0, inf); } for (int i = 1; i <= n; ++i) { for (int j = i + 1; j <= n; ++j) { mf.add_edge(2 * i + 1, 2 * j, (a[i] == a[j]) ? 0 : __builtin_popcount(a[j]), inf); } } auto ans = mf.minCostFlow(); assert(ans.first == m); ans.second += n * inf; char nxt_var = a ; for (int i = 1; i <= n; ++i) { if (!var[i]) { var[i] = nxt_var++; } for (auto &e : mf.G[2 * i + 1]) { if (mf.getFlow(e) == 1 and e.to != sink) { var[e.to / 2] = var[i]; break; } } } vector<string> events; for (int i = 1; i <= n; ++i) { if (val[var[i] - a ] != a[i]) { val[var[i] - a ] = a[i]; events.push_back(var[i] + string( = ) + to_string(a[i])); } events.push_back(string( print( ) + var[i] + string( ) )); } cout << events.size() << << ans.second << n ; for (auto &s : events) { cout << s << n ; } } |
module fakeapr(
input wire clk,
input wire reset,
// keys
input wire key_start,
input wire key_read_in,
input wire key_mem_cont,
input wire key_inst_cont,
input wire key_mem_stop,
input wire key_inst_stop,
input wire key_exec,
input wire key_io_reset,
input wire key_dep,
input wire key_dep_nxt,
input wire key_ex,
input wire key_ex_nxt,
// switches
input wire sw_addr_stop,
input wire sw_mem_disable,
input wire sw_repeat,
input wire sw_power,
input wire [0:35] datasw,
input wire [18:35] mas,
// maintenance switches
input wire sw_rim_maint,
input wire sw_repeat_bypass,
input wire sw_art3_maint,
input wire sw_sct_maint,
input wire sw_split_cyc,
// lights
output wire power,
output wire [0:17] ir,
output wire [0:35] mi,
output wire [0:35] ar,
output wire [0:35] mb,
output wire [0:35] mq,
output wire [18:35] pc,
output wire [18:35] ma,
output wire run,
output wire mc_stop,
output wire pi_active,
output wire [1:7] pih,
output wire [1:7] pir,
output wire [1:7] pio,
output wire [18:25] pr,
output wire [18:25] rlr,
output wire [18:25] rla,
output wire [0:7] ff0,
output wire [0:7] ff1,
output wire [0:7] ff2,
output wire [0:7] ff3,
output wire [0:7] ff4,
output wire [0:7] ff5,
output wire [0:7] ff6,
output wire [0:7] ff7,
output wire [0:7] ff8,
output wire [0:7] ff9,
output wire [0:7] ff10,
output wire [0:7] ff11,
output wire [0:7] ff12,
output wire [0:7] ff13
);
assign power = sw_power;
assign ir = 18'o111111;
assign mi = 36'o222222333333;
assign ar = 36'o444444555555;
assign mb = 36'o666666777777;
assign mq = 36'o101010202020;
assign pc = 18'o303030;
assign ma = 18'o404040;
assign run = datasw[35];
assign mc_stop = datasw[34];
assign pi_active = 0;
assign pih = 7'o123;
assign pir = 7'o134;
assign pio = 7'o145;
assign pr = 8'o352;
assign rlr = 8'o333;
assign rla = 8'o222;
assign ff0 = 8'o201;
assign ff1 = 8'o202;
assign ff2 = 8'o203;
assign ff3 = 8'o204;
assign ff4 = 8'o205;
assign ff5 = 8'o206;
assign ff6 = 8'o207;
assign ff7 = 8'o210;
assign ff8 = 8'o211;
assign ff9 = 8'o212;
assign ff10 = 8'o213;
assign ff11 = 8'o214;
assign ff12 = 8'o215;
assign ff13 = 8'o216;
endmodule
|
`timescale 1ns / 1ps
module AXI_SRAM(
// Common
input CLK, // system clock
input RST, // active high system reset
// AXI-4 SLAVE Interface
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input [4-1:0] axi_wstrb,
output reg axi_bvalid,
input axi_bready,
input axi_arvalid,
output axi_arready,
input [32-1:0] axi_araddr,
input [3-1:0] axi_arprot,
output reg axi_rvalid,
input axi_rready,
output reg [32-1:0] axi_rdata,
// DDR2 interface
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_p,
inout [1:0] ddr2_dqs_n
);
// Misc
wire rst_i;
assign rst_i = ~RST;
wire clk_200MHz_i;
assign clk_200MHz_i = CLK;
// RAM interface
wire [26:0] ram_a;
wire [15:0] ram_dq_i;
wire [15:0] ram_dq_o;
reg ram_cen; // Controlled by state machine
reg ram_oen; // Controlled by state machine
reg ram_wen; // Controlled by state machine
wire ram_ub;
wire ram_lb;
wire ddr2_ready;
// AXI-4 Auxiliar
reg [31:0] waddr, raddr;
reg [31:0] wdata;
reg [1:0] wassert;
reg rassert;
// AXI-4 immediate responses
assign axi_awready = 1'b1;
assign axi_arready = 1'b1;
assign axi_wready = 1'b1;
// Single shot response and saving
always @(posedge CLK)
begin : SINGLE_SHOT
if(RST == 1'b0) begin
waddr <= 0;
raddr <= 0;
wdata <= 0;
wassert <= 2'b00;
rassert <= 1'b0;
end else begin
if(axi_bvalid) begin // bvalid indicates wterm sig
waddr <= waddr;
wassert[0] <= 1'b0;
end else if(axi_awvalid) begin
waddr <= axi_awaddr;
wassert[0] <= 1'b1;
end else begin
waddr <= waddr;
wassert[0] <= wassert[0];
end
if(axi_bvalid) begin // bvalid indicates wterm sig
wdata <= wdata;
wassert[1] <= 1'b0;
end else if(axi_wvalid) begin
wdata <= axi_wdata;
wassert[1] <= 1'b1;
end else begin
wdata <= wdata;
wassert[1] <= wassert[1];
end
if(axi_rvalid) begin // rvalid indicates rterm sig
raddr <= raddr;
rassert <= 1'b0;
end else if(axi_arvalid) begin
raddr <= axi_araddr;
rassert <= 1'b1;
end else begin
raddr <= raddr;
rassert <= rassert;
end
end
end
// MAIN STATE-MACHINE
reg [3:0] state;
parameter st0_idle = 0, st1_waitrready = 1, st2_waitbready = 2;
always @(posedge CLK)
if (RST == 1'b0) begin
state <= st0_idle;
for(idx = 0; idx < 8; idx = idx + 1)
regs[idx] <= 0;
axi_bvalid <= 1'b0;
axi_rvalid <= 1'b0;
axi_rdata <= 0;
end else case (state)
st0_idle :
if (rassert) begin
axi_rdata <= {24'd0, regs[raddr[4:2]]};
state <= st1_waitrready;
axi_rvalid <= 1'b1;
end else if(wassert == 2'b11) begin
if(waddr[4:2] == 3'h0 && wdata[7:0] == 8'h0A)
flag_erase <= 1'b1;
else if(waddr[4:2] == 3'h0 && wdata[7:0] >= 8'd32) begin
if(flag_erase) begin
flag_erase <= 1'b0;
for(idx = 0; idx < 8; idx = idx + 1)
regs[idx] <= 0;
end else begin
regs[0] <= wdata[7:0];
for(idx = 0; idx < 7; idx = idx + 1)
regs[idx+1] <= regs[idx];
end
end else begin
regs[waddr[4:2]] <= wdata[7:0];
end
state <= st2_waitbready;
axi_bvalid <= 1'b1;
end else begin
state <= state;
end
st1_waitrready :
if (axi_rready ==1) begin
axi_rvalid <= 1'b0;
state <= st0_idle;
end else begin
state <= state;
end
st2_waitbready :
if (axi_bready ==1) begin
axi_bvalid <= 1'b0;
state <= st0_idle;
end else begin
state <= state;
end
default: begin
state <= st0_idle; end
endcase
// Memory implementation.
reg [32-1:0] MEM [0:(2**24)-1];
reg [32-1:0] Q;
always @(posedge CLK)
if (RST == 1'b0) begin
Q <= 0;
end else begin
if(uart_mem_cen) begin
Q <= MEM[uart_mem_addr];
if(uart_mem_wen) MEM[uart_mem_addr] <= uart_mem_d;
end
end
assign uart_mem_q = Q;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; struct DSU { long long int parent[500001], connected[500001]; void intialize(int x) { for (long long int i = 1; i <= x; i++) { parent[i] = i; connected[i] = 1; } } long long int getparent(long long int k) { while (k != parent[k]) { parent[k] = parent[parent[k]]; k = parent[k]; } return k; } long long int getsize(long long int k) { return connected[getparent(k)]; } void unionn(long long int u, long long int v) { long long int parent1 = getparent(u), parent2 = getparent(v); if (parent1 == parent2) return; if (connected[parent1] > connected[parent2]) swap(parent1, parent2); connected[parent2] += connected[parent1]; connected[parent1] = 0; parent[parent1] = parent[parent2]; } }; DSU dsu; int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; dsu.intialize(n + 1); for (long long int i = 1; i <= n; i++) { long long int x; cin >> x; dsu.unionn(i, x); } for (long long int i = 1; i <= n; i++) cout << dsu.getsize(i) << ; cout << n ; } } |
#include <bits/stdc++.h> int main() { int k, a, b; scanf( %d , &k); for (int i = k / 2000 + (k % 2000 > 0);; ++i) { b = i * 2000 - k; a = i - b; if (b <= 1e6 && a < 0 && a >= -1e6) break; } puts( 2000 ); for (int i = 1; i <= 1998; ++i) printf( 0 ); printf( %d %d n , a, b); return 0; } |
#include <bits/stdc++.h> using namespace std; int k, i, j, n; double ans, x[100010], xp, yp, xk; double C(int z) { return hypot(x[z] - xp, yp); } double A(int l, int r) { return x[r] - x[l] + min(C(l), C(r)); } double B(int l, int r) { return x[r] - x[l] + min(abs(xk - x[l]) + C(r), abs(xk - x[r]) + C(l)); } void inlinework() { ans = B(1, n); for (i = 2; i <= n; i++) { double t = min(A(1, i - 1) + B(i, n), A(i, n) + B(1, i - 1)); if (t < ans) ans = t; } } void outlinework() { ans = A(1, n); } int main() { scanf( %d%d , &n, &k); for (i = 1; i <= n; i++) scanf( %lf , &x[i]); scanf( %lf%lf , &xp, &yp); xk = x[k]; sort(x + 1, x + n + 1); if (k <= n) inlinework(); else outlinework(); printf( %.20lf n , ans); } |
#include <bits/stdc++.h> int main() { int i, j, n, max = -1, count, a; char c1, c2; scanf( %d , &n); char s[n]; scanf( %s , s); for (i = 0; i < n - 1; i++) { count = 0; for (j = i + 1; j < n - 1; j++) { if (s[j] == s[i]) { if (s[j + 1] == s[i + 1]) count++; } } if (count > max) { max = count; c1 = s[i]; c2 = s[i + 1]; } } printf( %c%c n , c1, c2); return 0; } |
#include <bits/stdc++.h> int main() { const int N = 3 * 3; bool buttons[N] = {0}; int k(0); while (k < N) { char temp; scanf( %c , &temp); if (temp == X ) { buttons[k++] = 1; } else if (temp == . ) { buttons[k++] = 0; } } bool symmetric(1); for (int k = 0; k < N; k++) { if (buttons[k] != buttons[N - 1 - k]) { symmetric = 0; break; } } if (symmetric) { puts( YES ); } else { puts( NO ); } return 0; } |
`timescale 1ns / 1ps
/* tf528_ram_top.v
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF328 (Terrible Fire CD32 RAM + IDE BOARD)
TF328 is free: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF328. If not, see <http://www.gnu.org/licenses/>.
*/
module ramcpld(
input CLKCPU,
input RESET,
input [23:0] A,
inout [7:0] D,
input [1:0] SIZ,
input IDEINT,
output INT2,
input AS20,
input RW20,
input DS20,
// ram chip control
output RAM_MUX,
output RAMOE,
output [3:0] CAS,
output [1:0] RAS,
output [1:0] RAM_A,
output [1:0] DSACK,
output PUNT,
output IOR,
output IOW,
output [1:0] IDECS
);
// produce an internal data strobe
wire GAYLE_INT2;
// $DA0000
wire GAYLE_IDE = ({A[23:15]} != {8'hDA,1'b0}) | AS20;
// $DE0000 or $DA8000 (Ignores A18)
wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});
wire GAYLE_ID= (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | AS20;
reg [2:0] POR = 3'b111;
wire gayle_dout;
gayle GAYLE(
.CLKCPU ( CLKCPU ),
.RESET ( RESET ),
.CS ( GAYLE_ACCESS ),
.DS ( DS20 | GAYLE_ACCESS ),
.RW ( RW20 ),
.A18 ( A[18] ),
.A ( {A[13:12]} ),
.IDE_INT( IDEINT ),
.INT2 ( GAYLE_INT2 ),
.D7 ( D[7] ),
.DOUT7 ( gayle_dout )
);
reg AS20_D = 1'b1;
reg AS20_D2 = 1'b1;
fastmem FASTRAM(
.CLKCPU ( CLKCPU ),
.RESET ( RESET & ~POR[2] ),
.AS20 ( AS20 ),
.DS20 ( DS20 ),
.RW20 ( RW20 ),
.A ( A ),
.D ( D ),
.SIZ ( SIZ ),
.CAS ( CAS ),
.RAS ( RAS ),
.RAM_MUX ( RAM_MUX ),
.RAMOE ( RAMOE ),
.RAM_A ( RAM_A ),
.RAM_ACCESS ( RAM_ACCESS),
.Z2_ACCESS ( Z2_ACCESS ),
.WAIT ( RAM_WAIT )
);
reg intcycle_dout = 1'b0;
reg GAYLE_D = 1'b1;
reg GAYLE_D2 = 1'b1;
wire DSHOLD2 = {AS20_D,AS20, RW20} == {1'b1,1'b0,1'b0};
wire IOR_INT = ~RW20 | GAYLE_IDE | DSHOLD2;
wire IOW_INT = RW20 | GAYLE_IDE | DSHOLD2;
wire fastcycle_int = (RAM_ACCESS | RAM_WAIT) & GAYLE_D2 & Z2_ACCESS & GAYLE_ACCESS & GAYLE_IDE;
FDCP #(.INIT(1'b1))
FASTCYCLE1_FF (
.Q(FASTCYCLE1), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(fastcycle_int), // Data input
.PRE(AS20) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
FASTCYCLE0_FF (
.Q(FASTCYCLE0), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(fastcycle_int | RAM_ACCESS), // Data input
.PRE(AS20) // Asynchronous set input
);
always @(posedge CLKCPU or negedge RESET) begin
if (RESET == 1'b0) begin
POR <= 'hF;
end else begin
// shift until all 0's
// this will not happen if there isnt a clock
POR[2:0] <= {POR[1:0], 1'b0};
end
end
always @(posedge CLKCPU or posedge AS20) begin
if (AS20 == 1'b1) begin
AS20_D <= 1'b1;
AS20_D2 <= 1'b1;
GAYLE_D <= 1'b1;
GAYLE_D2 <= 1'b1;
end else begin
intcycle_dout <= (~GAYLE_ACCESS) & RW20;
AS20_D <= AS20;
AS20_D2 <= AS20_D;
GAYLE_D2 <= GAYLE_D;
if (GAYLE_IDE == 1'b0) begin
GAYLE_D <= 1'b0;
end
end
end
FDCP #(.INIT(1'b1))
IOR_FF (
.Q(IOR), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(IOR_INT), // Data input
.PRE(AS20) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
IOW_FF (
.Q(IOW), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(IOW_INT), // Data input
.PRE(AS20) // Asynchronous set input
);
assign PUNT = POR[2] | GAYLE_ACCESS & GAYLE_IDE & RAM_ACCESS & Z2_ACCESS ? 1'bz : 1'b0;
assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE};
assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
wire [7:4] data_out = GAYLE_ACCESS ? 4'b1111 : {gayle_dout,3'b000};
assign D[7:0] = (intcycle_dout) ? {data_out[7:4], 4'h0} : 8'bzzzzzzzz;
assign DSACK[1] = FASTCYCLE1 ? 1'bz : 1'b0;
assign DSACK[0] = FASTCYCLE0 ? 1'bz : 1'b0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/07/2015 01:43:34 PM
// Design Name:
// Module Name: AnalogXADC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AnalogXADC(
output reg [15:0] aux_data,
output reg [15:0] temp_data,
input vauxp3,
input vauxn3,
input CLK100MHZ
);
wire enable;
wire ready;
wire [15:0] data_o;
reg [6:0] Address_in;
initial Address_in = 7'h13;
xadc_wiz_0 XLXI_7 (.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space
.dclk_in(CLK100MHZ),
.den_in(enable),
.di_in(0),
.dwe_in(0),
.busy_out(),
.vauxp3(vauxp3),
.vauxn3(vauxn3),
.vn_in(0),
.vp_in(0),
.alarm_out(),
.do_out(data_o),
.eoc_out(enable),
.eos_out(),
.channel_out(),
.drdy_out(ready));
////assigning different values out from xadc
always @(posedge(CLK100MHZ))
begin
if(ready == 1'b1)
begin
if(Address_in == 7'h13) //audio in
begin
aux_data <= {data_o[15:4],4'b0000};
Address_in <= 7'h00; //change to temp read
end
else //temperature in
begin
temp_data <= data_o;
Address_in <= 7'h13;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, n, m, j, y, pos, fed = 0; int mice[100001], cheese[100001], taken[100001]; int main() { scanf( %d %d %d %d , &n, &m, &y, &y); for (i = 0; i < n; i++) scanf( %d , &mice[i]); for (i = 0; i < m; i++) scanf( %d , &cheese[i]); for (i = 0; i < m; i++) taken[i] = -1; for (i = 0; i < n; i++) { pos = lower_bound(cheese, cheese + m, mice[i]) - cheese; if (pos == 0) { if (taken[pos] == -1) { taken[pos] = cheese[pos] - mice[i]; fed++; } else { taken[pos] = cheese[pos] - mice[i]; } continue; } if (pos == m) { if (taken[pos - 1] == -1 || taken[pos - 1] == mice[i] - cheese[pos - 1]) { taken[pos - 1] = mice[i] - cheese[pos - 1]; fed++; } else if (taken[pos - 1] > mice[i] - cheese[pos - 1]) { taken[pos - 1] = mice[i] - cheese[pos - 1]; } continue; } { if ((mice[i] - cheese[pos - 1]) < (cheese[pos] - mice[i])) { if (taken[pos - 1] == -1 || taken[pos - 1] == mice[i] - cheese[pos - 1]) { taken[pos - 1] = mice[i] - cheese[pos - 1]; fed++; } else if (taken[pos - 1] > mice[i] - cheese[pos - 1]) { taken[pos - 1] = mice[i] - cheese[pos - 1]; } } else if ((mice[i] - cheese[pos - 1]) == (cheese[pos] - mice[i])) { if (taken[pos - 1] == -1 || taken[pos - 1] == mice[i] - cheese[pos - 1]) { taken[pos - 1] = mice[i] - cheese[pos - 1]; fed++; } else { taken[pos] = cheese[pos] - mice[i]; fed++; } } else { if (taken[pos] == -1) { taken[pos] = cheese[pos] - mice[i]; fed++; } else { taken[pos] = cheese[pos] - mice[i]; } } } } printf( %d n , n - fed); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1007; int c[N], t[N]; bool cmp(int i, int j) { return c[i] > c[j]; } int main() { int n, k; cin >> n >> k; vector<int> v[3]; for (int i = 0; i < n; ++i) { cin >> c[i] >> t[i]; v[t[i]].push_back(i); } sort((v[1]).begin(), (v[1]).end(), cmp); int sz = (int)((v[1]).size()), uu = (int)((v[2]).size()); double sum = 0; if (sz < k) { for (int i = 0; i < sz; ++i) sum += (double)c[v[1][i]] / 2; for (int i = 0; i < uu; ++i) sum += c[v[2][i]]; cout << fixed << setprecision(1) << sum << n ; for (int i = 0; i < sz; ++i) cout << 1 << << v[1][i] + 1 << n ; for (int i = 0; i < k - sz - 1; ++i) cout << 1 << << v[2][i] + 1 << n ; cout << (n - (k - 1)) << ; for (int i = k - sz - 1; i < n - sz; ++i) cout << v[2][i] + 1 << ; cout << n ; } else { for (int i = 0; i < k - 1; ++i) sum += (double)c[v[1][i]] / 2; int mini = 1000000000; for (int i = k - 1; i < sz; ++i) { sum += c[v[1][i]]; mini = min(mini, c[v[1][i]]); } for (int i = 0; i < uu; ++i) { sum += c[v[2][i]]; mini = min(mini, c[v[2][i]]); } sum -= (double)mini / 2; cout << fixed << setprecision(1) << sum << n ; for (int i = 0; i < k - 1; ++i) cout << 1 << << v[1][i] + 1 << n ; cout << (n - (k - 1)) << ; for (int i = k - 1; i < sz; ++i) cout << v[1][i] + 1 << ; for (int i = 0; i < uu; ++i) cout << v[2][i] + 1 << ; cout << n ; } } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) { return a; } return gcd(b, a % b); } int main() { int x, y; long long int a, b; cin >> x >> y >> a >> b; int lcm = (x * y) / (gcd(x, y)); int ans = (b / lcm) - ((a - 1) / lcm); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int x1, y1; cin >> x1 >> y1; int x2, y2; cin >> x2 >> y2; int ans = 0x3f3f3f3f; for (int i = -1; i <= 1; i++) { for (int j = -1; j <= 1; j++) { if (i == 0 && j == 0) { continue; } ans = min(ans, abs(x1 - (x2 + i)) + abs(y1 - (y2 + j))); } } cout << 2 * ans + 8; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 4e5 + 4; const int oo = 1e8 + 7; int n, a[maxn], cc, p; long long s[maxn]; int main() { cin >> n; a[1] = 1; a[2] = 2 * n; a[n + 1] = 2; a[n + 2] = 2 * n - 1; int cc = 3; for (int i = 3; i <= (n); ++i) { if (i % 2) { a[i] = cc; a[i + n] = cc + 1; cc += 2; } else { a[i + n] = cc; a[i] = cc + 1; cc += 2; } } long long k = 0; for (int i = 1; i <= (2 * n); ++i) k += i; for (int i = 2 * n + 1; i <= (4 * n); ++i) a[i] = a[i - 2 * n]; for (int i = 1; i <= (4 * n); ++i) s[i] = s[i - 1] + a[i]; k = k / 2; k++; for (int i = 1; i <= (3 * n); ++i) { long long x = s[i + n - 1] - s[i - 1]; if (abs(x - k) > 1) { cout << NO ; return 0; } } cout << YES n ; for (int i = 1; i <= (2 * n); ++i) cout << a[i] << ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100010, maxm = maxn * 2; int h[maxn], ne[maxm], e[maxm], cnt; int d[maxn], dp[maxn][3], w[maxn], root; int a[maxn]; int vis[maxn]; void solve() { int T; scanf( %d , &T); while (T--) { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i < n; i += 2) { cout << -a[i + 1] << << a[i] << ; } cout << endl; } return; } int main() { solve(); return 0; } |
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const long long int INFLL = 0x3f3f3f3f3f3f3f3fll; long long int getint() { long long int ret = 0; bool f = 0; char c; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) f ^= 1; while (c >= 0 && c <= 9 ) { ret = ret * 10 + c - 0 ; c = getchar(); } return f ? -ret : ret; } using namespace std; const int MAXN = 200000; int a[MAXN + 10], f[MAXN + 10][20], w[MAXN + 10], lg2[MAXN + 10]; int nxt[MAXN + 10][20], far[MAXN + 10][20]; int query(int l, int r) { int t = lg2[r - l + 1]; int ret = f[r - (1 << t) + 1][t]; if (w[f[l][t]] > w[ret]) ret = f[l][t]; return ret; } int main() { int n = getint(), N = 2 * n; for (int i = n; i >= 1; --i) a[i + n] = a[i] = getint(); lg2[0] = -1; for (int i = 1; i <= N; ++i) { w[i] = i + a[i]; f[i][0] = i; lg2[i] = lg2[i >> 1] + 1; } for (int j = 1; j <= lg2[N]; ++j) for (int i = 1; i + (1 << j) - 1 <= N; ++i) { f[i][j] = f[i + (1 << (j - 1))][j - 1]; if (w[f[i][j - 1]] > w[f[i][j]]) f[i][j] = f[i][j - 1]; } for (int i = 1; i < N; ++i) { nxt[i][0] = query(i + 1, min(N, i + a[i])); far[i][0] = w[i]; } far[N][0] = nxt[N][0] = N; for (int j = 1; j <= lg2[N]; ++j) for (int i = 1; i <= N; ++i) { nxt[i][j] = nxt[nxt[i][j - 1]][j - 1]; far[i][j] = far[nxt[i][j - 1]][j - 1]; } long long int output = 0; for (int i = 1; i <= n; ++i) { int ans = 0, u = i; for (int j = lg2[N]; j >= 0; --j) if (far[u][j] < i + n - 1) ans += 1 << j, u = nxt[u][j]; output += ans + 1; } printf( %I64d n , output); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> a, b, g, ar; vector<vector<int> > edg, nxt; vector<long long> d; long long f(int v) { long long res = 0; for (int w : edg[v]) { long long tmp = f(w) + a[w]; if (tmp > 0) { res += tmp; nxt[w].push_back(v); g[v]++; } else { nxt[v].push_back(w); g[w]++; } } return d[v] = res; } int main(void) { cin >> n; a.assign(n, 0); b.assign(n, 0); g.assign(n, 0); edg.assign(n, vector<int>()); nxt.assign(n, vector<int>()); for (int i = 0; i < n; i++) cin >> a[i]; vector<int> c; for (int i = 0; i < n; i++) { cin >> b[i]; if (b[i] == -1) { c.push_back(i); continue; } b[i]--; edg[b[i]].push_back(i); } long long ans = 0; d.assign(n, 0); for (int i = 0; i < n; i++) { if (b[i] == -1) f(i); } for (int i = 0; i < n; i++) { ans += d[i] + a[i]; } queue<int> q; for (int i = 0; i < n; i++) { if (g[i] == 0) q.push(i); } while (!q.empty()) { int v = q.front(); q.pop(); ar.push_back(v); for (int w : nxt[v]) { g[w]--; if (g[w] == 0) q.push(w); } } cout << ans << endl; for (int v : ar) cout << v + 1 << ; cout << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_2_V
`define SKY130_FD_SC_LS__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_2_V
|
#include <bits/stdc++.h> using namespace std; int ToInt(string& s, int len) { int r = 0; for (int i = 0, max_ = (len); i < max_; ++i) { r *= 10; r += s[i] - 0 ; } return r; } int GCD(int a, int b) { return b != 0 ? GCD(b, a % b) : a; } int LCM(int a, int b) { return a * (b / GCD(a, b)); } long long Pow(long long n, long long e) { if (e == 0) return 1; if (e == 1) return n; else if (e & 1) { long long t = Pow(n, e / 2); return n * t * t; } else { long long t = Pow(n, e / 2); return t * t; } } int main() { string s; int N; scanf( %d , &N); getline(cin, s); getline(cin, s); int h = 0; for (int i = 0, max_ = ((int)(s).size()); i < max_; ++i) if (s[i] == H ) ++h; int min = 10000; for (int start = 0, max_ = ((int)(s).size()); start < max_; ++start) { int swaps = 0; for (int i = 0, max_ = (h); i < max_; ++i) if (s[(start + i) % (int)(s).size()] == T ) ++swaps; min = std::min(min, swaps); } printf( %d n , min); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100004; int v[N]; int main(void) { priority_queue<int> q; int x, n; cin >> n; int res = 0; set<pair<int, int> > S; for (int i = 0; i < n; ++i) { int x; cin >> x; S.insert(make_pair(x, i + 1)); } int k = 1; for (auto it : S) { v[it.second] = k++; } for (int i = 1; i <= n; ++i) { x = v[i]; q.push(x); if (q.top() == i) { res++; while (q.size()) q.pop(); } } cout << res << endl; return 0; } |
/******************************************************************************
* File Name : jhash_core.v
* Version : 0.1
* Date : 2008 08 29
* Description: jash core module
* Dependencies:
*
*
* Company: Beijing Soul
*
* BUG:
*
*****************************************************************************/
module jhash_core(/*AUTOARG*/
// Outputs
stream_ack, hash_out, hash_done, m_endn,
// Inputs
clk, rst, ce, stream_data0, stream_data1, stream_data2,
stream_valid, stream_done, stream_left
);
input clk, rst, ce;
input [31:0] stream_data0,
stream_data1,
stream_data2;
input stream_valid;
input stream_done;
input [1:0] stream_left;
output stream_ack;
output [31:0] hash_out;
output hash_done;
output m_endn;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg hash_done;
reg stream_ack;
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] OA; // From mix of mix.v
wire [31:0] OB; // From mix of mix.v
wire [31:0] OC; // From mix of mix.v
// End of automatics
parameter [1:0]
S_IDLE = 2'b00,
S_LOAD = 2'b01,
S_RUN = 2'b10,
S_DONE = 2'b11;
reg [1:0]
state, state_n;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
reg [2:0] round;
reg round_rst, round_inc;
always @(posedge clk)
if (round_rst)
round <= #1 3'b000;
else if (round_inc)
round <= #1 round + 1'b1;
reg [31:0] a, a_n,
b, b_n,
c, c_n;
reg [4:0] shift, shift_n;
reg final_r, final_n;
mix mix (/*AUTOINST*/
// Outputs
.OA (OA[31:0]),
.OB (OB[31:0]),
.OC (OC[31:0]),
// Inputs
.a (a[31:0]),
.b (b[31:0]),
.c (c[31:0]),
.clk (clk),
.shift (shift[4:0]));
always @(posedge clk)
begin
a <= #1 a_n;
b <= #1 b_n;
c <= #1 c_n;
shift <= #1 shift_n;
final_r<=#1 final_n;
end
always @(/*AS*/OA or OB or OC or a or b or c or final_r
or round or shift or state or stream_data0
or stream_data1 or stream_data2 or stream_done
or stream_left or stream_valid)
begin
a_n = a;
b_n = b;
c_n = c;
state_n = state;
stream_ack = 1'b0;
shift_n = shift;
round_inc = 1'b0;
round_rst = 1'b0;
final_n = final_r;
case (state)
S_IDLE: begin
a_n = 32'h0;
b_n = 32'h0;
c_n = 32'h0;
final_n = 1'b0;
if (stream_valid) begin
state_n = S_LOAD;
end
end
S_LOAD: if (stream_done && 1'b0) begin
/* a -= c; a ^= rot(c, 4); c += b; */
round_rst = 1'b1;
shift_n = 4;
state_n = S_RUN;
final_n = 1'b1;
case (stream_left)
2'b00: state_n = S_DONE;
2'b01: begin
a_n = a + stream_data0;
end
2'b10: begin
a_n = a + stream_data0;
b_n = b + stream_data1;
end
2'b11: begin
a_n = a + stream_data0;
b_n = b + stream_data1;
c_n = c + stream_data2;
end
endcase // case(stream_left)
end else // if (stream_done)
if (stream_valid) begin
/* a -= c; a ^= rot(c, 4); c += b; */
a_n = a + stream_data0;
b_n = b + stream_data1;
c_n = c + stream_data2;
state_n = S_RUN;
shift_n = 4;
stream_ack = 1'b1;
round_rst = 1'b1;
end
S_RUN: begin
a_n = OB;
b_n = OC;
c_n = OA;
round_inc = 1'b1;
case (round)
3'b000: /* b -= a; b ^= rot(a, 6); a += c; */
shift_n = 6;
3'b001: /* c -= b; c ^= rot(b, 8); b += a; */
shift_n = 8;
3'b010: /* a -= c; a ^= rot(c,16); c += b; */
shift_n = 16;
3'b011: /* b -= a; b ^= rot(a,19); a += c */
shift_n = 19;
3'b100: /* c -= b; c ^= rot(b, 4); b += a; */
shift_n = 4;
3'b101: begin
if (/*final_r*/stream_done)
state_n = S_DONE;
else
state_n = S_LOAD;
end
endcase // case(round)
end // case: S_RUN
S_DONE: ;
endcase // case(state)
end // always @ (...
always @(posedge clk)
hash_done <= #1 state == S_DONE;
assign m_endn = ce ? ~hash_done : 1'bz;
assign hash_out = ce ? c : 32'hz;
endmodule // jhash_core |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts resamples the chroma components of a video in *
* stream, whos colour space is YCrCb. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Chroma_Upsampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 7; // Incoming frame's data width
parameter ODW = 23; // Outcoming frame's data width
parameter IEW = 0; // Incoming frame's empty width
parameter OEW = 1; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = 8'h80;
assign converted_data[15: 8] = 8'h80;
assign converted_data[ 7: 0] = data[7:0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//bug906
import gmcupkg::*;
module gminstdecode
(
output instClassType instClass
/*blah blah blah*/);
always_comb begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
instClass.iFunc = '0;
instClass.isBool = '0;
instClass.sub.bool = '0;
instClass.sub2.sub3.bool = '0;
// End of automatics
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
end
end
always_comb begin
instClass = '{default:0}; // #1 (see below)
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.iFunc = IFUNC_ADD; // #2
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
instClass.isBool = '0;
// End of automatics
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.sub = '0;
instClass.sub2 = '0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
instClass.sub3.sub4.bool = '0;
// End of automatics
if (ldBitFromIo | stBitToIo) begin
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
instClass.sub3.sub4.bool = 1'b1;
end
end
endmodule
// Local Variables:
// verilog-auto-reset-widths: unbased
// verilog-typedef-regexp: "Type$"
// End:
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const double PI = acos(-1.); const double eps = 1e-9; char s[1000005]; char t[1000005]; int fs[11]; int ft[11]; int fx[11]; char y[1000005]; int main() { int i, j, k, _T; while (~scanf( %s%s , s, t)) { if (strcmp(s, 01 ) == 0 || strcmp(s, 10 ) == 0) { printf( 0 n ); continue; } memset(fs, 0, sizeof fs); memset(ft, 0, sizeof ft); for (i = 0; s[i]; i++) fs[s[i] - 0 ]++; for (i = 0; t[i]; i++) ft[t[i] - 0 ]++; int ls = strlen(s); int lt = strlen(t); for (int len = lt; len <= ls; len++) { char x[15]; memset(fx, 0, sizeof fx); memset(x, 0, sizeof x); sprintf(x, %d , len); int lx = strlen(x); for (i = 0; x[i]; i++) fx[x[i] - 0 ]++; int fail = 0; for (i = 0; i <= 9; i++) if (fs[i] < ft[i] + fx[i]) { fail = 1; } if (fail || ls - lx != len) continue; int flag = 0; for (i = 1; i <= 9; i++) flag |= fs[i] > fx[i] + ft[i]; if (t[0] == 0 && !flag) continue; if (!flag) { printf( %s , t); for (i = 0; i <= 9; i++) for (j = 0; j < fs[i] - fx[i] - ft[i]; j++) putchar( 0 + i); putchar( n ); break; } int id = 0, fi = -1; for (i = 1; i <= 9; i++) if (fs[i] > fx[i] + ft[i]) { fi = i; break; } fs[fi]--; y[id++] = 0 + fi; for (i = 0; i <= 9; i++) { if (t[0] == 0 + i) { int big = 0; for (j = 1; j < lt; j++) { if (t[j] != t[0]) { if (t[j] > t[0]) big = 1; break; } } if (!big) { for (j = 0; j < lt; j++) y[id++] = t[j]; } for (j = 0; j < fs[i] - fx[i] - ft[i]; j++) y[id++] = 0 + i; if (big) { for (j = 0; j < lt; j++) y[id++] = t[j]; } } else for (j = 0; j < fs[i] - fx[i] - ft[i]; j++) y[id++] = 0 + i; } int ly = id; fs[fi]++; id = lt; for (i = 0; i <= 9; i++) for (j = 0; j < fs[i] - fx[i] - ft[i]; j++) t[id++] = 0 + i; int uset = 0; for (i = 0; i < ly; i++) { if (y[i] != t[i]) { if (y[i] > t[i]) uset = 1; break; } } if (uset && t[0] != 0 ) { for (i = 0; i < ly; i++) putchar(t[i]); putchar( n ); } else { for (i = 0; i < ly; i++) putchar(y[i]); putchar( n ); } break; } } return 0; } |
#include <bits/stdc++.h> int main() { int n, i, x, k, j = 0; scanf( %d%d , &n, &k); for (i = 0; i < n; i++) { for (x = 0; x < n; x++) { if (i == j && x == j) { printf( %d , k); } else printf( 0 ); } j++; printf( n ); } } |
//-----------------------------------------------------------------------------
//-- Banco de prueba para setbit
//-- (c) BQ August 2015
//-- Written by Juan Gonzalez (obijuan)
//-- mods by D. Cuartielles for Arduino, 2015 December, GPLv3
//-----------------------------------------------------------------------------
//-- Para la simulacion del componente es necesario hacer un banco de pruebas
//-- que coloque el componente, asigne valor a las entradas y compruebe las
//-- salidas. En el caso del compoente setbit, es muy sencillo. Solo tiene
//-- una salida, así que colocamos un cable a su salida y comprobamos que
//-- efectivamente se encuentra a valor 1
//-----------------------------------------------------------------------------
//-- Modulo para el test bench
module setbit_tb;
//-- Cable para conectar al componente que pone
//-- el bit a uno
wire LED1;
//--Instanciar el componente. Conectado al cable A
setbit SB1 (
.LED1 (LED1)
);
//-- Comenzamos las pruebas
initial begin
//-- Definir el fichero donde volvar los datos
//-- para ver graficamente la salida
$dumpfile("T01-setbit_tb.vcd");
//-- Volcar todos los datos a ese fichero
$dumpvars(0, setbit_tb);
//-- Pasadas 10 unidades de tiempo comprobamos
//-- si el cable esta a 1
//-- En caso de no estar a 1, se informa del problema, pero la
//-- simulacion no se detiene
# 10 if (LED1 != 1)
$display("---->¡ERROR! Salida no esta a 1");
else
$display("Componente ok!");
//-- Terminar la simulacion 10 unidades de tiempo
//-- despues
# 10 $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , mux_out, CLK, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:30:00 10/31/2016
// Module Name: D_MEM_tb
// Project Name: MIPS
// Description: Testing the MIPS Data Memory (D_MEM) module in the MEMORY
// (MEM) stage.
//
// Dependencies: D_MEM.v
//
////////////////////////////////////////////////////////////////////////////////
module D_MEM_tb;
// Inputs
reg clk;
reg MemWrite;
reg MemRead;
reg [31:0] Address;
reg [31:0] Write_data;
// Outputs
wire [31:0] Read_data;
// Instantiate the Unit Under Test (UUT)
D_MEM mem (
.clk(clk),
.MemWrite(MemWrite),
.MemRead(MemRead),
.Address(Address),
.Write_data(Write_data),
.Read_data(Read_data)
);
initial begin
// Initialize Inputs
clk = 0;
MemWrite = 0;
MemRead = 0;
Address = 0;
Write_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Test
MemWrite = 1;
Write_data = 32'h002300AA;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h10654321;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h001000220;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h8C123456;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h8F123456;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'hAD654321;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h13012345;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'hAC654321;
#20;
MemWrite = 1;
Address = Address + 1;
Write_data = 32'h12012345;
#20;
MemWrite = 0;
MemRead = 1;
Address = 0;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
Address = Address + 1;
#20;
$finish;
end
initial begin
$monitor("INPUT: MemWrite = %b\tMemRead = %b\tAddress = %h\tWrite_data = %h",
MemWrite, MemRead, Address, Write_data,
"\tOUTPUT: Read_data = %h",
Read_data);
forever begin
#10 clk = ~clk;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void add_self(int &a, int b) { a += b; if (a >= (int)1e9 + 7) a -= (int)1e9 + 7; } int n, l; void f(vector<int> &a) { int x = a[0]; for (int i = 0; i < n - 1; i++) { a[i] = a[i + 1] - a[i]; } a[n - 1] = l - a[n - 1] + x; } void f1(vector<int> &a, int k) { reverse(begin(a), end(a)); reverse(begin(a) + k, end(a)); reverse(begin(a), begin(a) + k); } void solve() { cin >> n >> l; vector<int> a(n), b(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; f(a); f(b); for (int i = 0; i < n; i++) { f1(a, 1); bool ok = true; for (int j = 0; j < n; j++) { if (a[j] != b[j]) { ok = false; break; } } if (ok) { cout << YES ; return; } } cout << NO ; } int main() { ios::sync_with_stdio(false); int q = 1; for (int i = 1; i <= q; i++) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int v[100005], b[100005]; int k, n, m, maxim; int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { int nr; cin >> nr; b[nr]++; v[b[nr]]++; if (v[b[nr]] == n) cout << 1; else cout << 0; } } |
//==================================================================================================
// Filename : ceespu_writeback.v
// Created On : 2018-07-21 21:14:45
// Last Modified : 2018-09-29 08:25:06
// Revision :
// Author : Cees Wolfs
//
// Description : The writeback selector, selects which value is written back to the register file
//
//
//==================================================================================================
`timescale 1ns / 1ps
module ceespu_writeback (
input I_clk,
input I_rst,
input [1:0] I_selWb,
input [2:0] I_selMem,
input [13:0] I_PC,
input [31:0] I_aluResult,
input [31:0] I_dmemData,
output reg [31:0] O_writeData
);
always @(*) begin
// standard writeback
if (I_selWb == 2'b00) begin
O_writeData = I_aluResult;
end
// memory writeback
else if (I_selWb == 2'b01) begin
// load word
if (I_selMem == 3'd0) begin
O_writeData = I_dmemData;
end
// load half word signed
else if (I_selMem == 3'd1) begin
O_writeData = (I_aluResult[1]) ? {{16{I_dmemData[31]}}, I_dmemData[31:16]} : {{16{I_dmemData[15]}}, I_dmemData[15:0]};
end
// load byte signed
else if (I_selMem == 3'd2) begin
case ( I_aluResult[1:0] )
0: O_writeData = {{24{I_dmemData[7]}}, I_dmemData[7:0]};
1: O_writeData = {{24{I_dmemData[15]}}, I_dmemData[15:8]};
2: O_writeData = {{24{I_dmemData[23]}}, I_dmemData[23:16]};
3: O_writeData = {{24{I_dmemData[31]}} , I_dmemData[31:24]};
endcase
end
// load halfword unsigned
else if (I_selMem == 3'd3) begin
O_writeData = (I_aluResult[1]) ? I_dmemData[31:16] : I_dmemData[15:0];
end
// load byte unsigned
else begin
case ( I_aluResult[1:0] )
0: O_writeData = I_dmemData[7:0];
1: O_writeData = I_dmemData[15:8];
2: O_writeData = I_dmemData[23:16];
3: O_writeData = I_dmemData[31:24];
endcase
end
end
// branch so write PC
else begin
O_writeData = (I_PC << 2);
$display("call c19 = %d", I_PC);
end
end
endmodule // ceespu_writeback
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_8_V
`define SKY130_FD_SC_LS__EBUFN_8_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_8_V
|
#include <bits/stdc++.h> using namespace std; int minn(int, int, int); int main() { int x1, x2, x3; cin >> x1 >> x2 >> x3; int d1 = abs(x2 - x1) + abs(x3 - x1); int d2 = abs(x1 - x2) + abs(x3 - x2); int d3 = abs(x3 - x1) + abs(x3 - x2); cout << minn(d1, d2, d3) << endl; return 0; } int minn(int a, int b, int c) { int m = a; if (b < m) m = b; if (c < m) m = c; return m; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:33:56 03/10/2016
// Design Name: Top
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab6/test_isim_top.v
// Project Name: lab6
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_isim_top;
// Inputs
reg CLOCK_IN;
reg RESET;
reg [2:0] SWITCH;
// Outputs
wire [3:0] LED;
// Instantiate the Unit Under Test (UUT)
Top uut (
.CLOCK_IN(CLOCK_IN),
.RESET(RESET),
.SW(SWITCH),
.LED(LED)
);
always #10 CLOCK_IN = ~CLOCK_IN;
initial begin
// Initialize Inputs
CLOCK_IN = 0;
RESET = 1;
SWITCH = 2'b001;
// Wait 100 ns for global reset to finish
#120;
// Add stimulus here
RESET = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long F[401000], Mod = 998244353, InvF[401000]; long long Pow(long long a, long long b) { long long r = 1; while (b) { if (b & 1) r = r * a % Mod; a = a * a % Mod; b >>= 1; } return r; } int A[201000], n, K; long long S[201000], res; long long Comb(int a, int b) { return F[a] * InvF[b] % Mod * InvF[a - b] % Mod; } int main() { int i; F[0] = 1; for (i = 1; i <= 400000; i++) F[i] = F[i - 1] * i % Mod; InvF[i - 1] = Pow(F[i - 1], Mod - 2); for (i = i - 1; i >= 1; i--) InvF[i - 1] = InvF[i] * i % Mod; scanf( %d%d , &n, &K); for (i = 0; i < n; i++) { scanf( %d , &A[i]); } int c2 = 0, c1 = 0; for (i = 0; i < n; i++) { if (A[i] == A[(i + 1) % n]) c2++; else c1++; } for (i = 0; i <= c1; i++) { if (i % 2 == 1) { S[i] = Pow(2, i - 1) % Mod; } else { S[i] = (Pow(2, i) - Comb(i, i / 2) + Mod) * (Mod / 2 + 1) % Mod; } } for (i = 0; i <= c1; i++) { if (K >= 2 || i == c1) { res = (res + Pow(K - 2, c1 - i) * S[i] % Mod * Comb(c1, i)) % Mod; } } res = res * Pow(K, c2) % Mod; printf( %lld n , res); } |
#include <bits/stdc++.h> using namespace std; char s1[100005], s2[100005]; int main() { int l1, l2, i; char tmp; while (~scanf( %s , s1)) { l1 = strlen(s1); for (i = l1 - 1, l2 = 0, tmp = 0; i >= 0; i--) { if (s1[i] >= tmp) { tmp = s1[i]; s2[l2++] = s1[i]; } } for (i = l2 - 1; i >= 0; i--) { printf( %c , s2[i]); } printf( n ); } return 0; } |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
module ghrd_10as066n2_button_pio_altera_avalon_pio_171_3t26uui (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_div_exp_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline exponent datapath.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_div_exp_dp (
inq_in1,
inq_in2,
d1stg_step,
d234stg_fdiv,
div_expadd1_in1_dbl,
div_expadd1_in1_sng,
div_expadd1_in2_exp_in2_dbl,
div_expadd1_in2_exp_in2_sng,
d3stg_fdiv,
d4stg_fdiv,
div_shl_cnt,
div_exp1_expadd1,
div_exp1_0835,
div_exp1_0118,
div_exp1_zero,
div_exp1_load,
div_expadd2_in1_exp_out,
d5stg_fdiva,
d5stg_fdivd,
d5stg_fdivs,
d6stg_fdiv,
d7stg_fdiv,
div_expadd2_no_decr_inv,
div_expadd2_cin,
div_exp_out_expadd2,
div_exp_out_expadd22_inv,
div_exp_out_of,
d7stg_to_0_inv,
d7stg_fdivd,
div_exp_out_exp_out,
d7stg_rndup_inv,
div_frac_add_52_inv,
div_exp_out_load,
fdiv_clken_l,
rclk,
div_exp1,
div_expadd2_12,
div_exp_out,
div_exp_outa,
se,
si,
so
);
input [62:52] inq_in1; // request operand 1 to op pipes
input [62:52] inq_in2; // request operand 2 to op pipes
input d1stg_step; // divide pipe load
input d234stg_fdiv; // select line to div_expadd1
input div_expadd1_in1_dbl; // select line to div_expadd1
input div_expadd1_in1_sng; // select line to div_expadd1
input div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1
input div_expadd1_in2_exp_in2_sng; //select line to div_expadd1
input d3stg_fdiv; // divide operation- divide stage 3
input d4stg_fdiv; // divide operation- divide stage 4
input [5:0] div_shl_cnt; // divide left shift amount
input div_exp1_expadd1; // select line to div_exp1
input div_exp1_0835; // select line to div_exp1
input div_exp1_0118; // select line to div_exp1
input div_exp1_zero; // select line to div_exp1
input div_exp1_load; // load enable to div_exp1
input div_expadd2_in1_exp_out; // select line to div_expadd2
input d5stg_fdiva; // divide operation- divide stage 5
input d5stg_fdivd; // divide double- divide stage 5
input d5stg_fdivs; // divide single- divide stage 5
input d6stg_fdiv; // divide operation- divide stage 6
input d7stg_fdiv; // divide operation- divide stage 7
input div_expadd2_no_decr_inv; // no exponent decrement
input div_expadd2_cin; // carry in to 2nd exponent adder
input div_exp_out_expadd2; // select line to div_exp_out
input div_exp_out_expadd22_inv; // select line to div_exp_out
input div_exp_out_of; // overflow to exponent output
input d7stg_to_0_inv; // result to infinity on overflow
input d7stg_fdivd; // divide double- divide stage 7
input div_exp_out_exp_out; // select line to div_exp_out
input d7stg_rndup_inv; // no rounding increment
input div_frac_add_52_inv; // div_frac_add bit[52] inverted
input div_exp_out_load; // load enable to div_exp_out
input fdiv_clken_l; // div pipe clk enable - asserted low
input rclk; // global clock
output [12:0] div_exp1; // divide exponent- intermediate value
output div_expadd2_12; // divide exponent- 2nd adder output
output [12:0] div_exp_out; // divide exponent output
output [10:0] div_exp_outa; // divide exponent output- buffered copy
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [10:0] div_exp_in1;
wire [10:0] div_exp_in2;
wire [12:0] div_expadd1_in1;
wire [12:0] div_expadd1_in2;
wire [12:0] div_expadd1;
wire [12:0] div_exp1_in;
wire [12:0] div_exp1;
wire [12:0] div_expadd2_in1;
wire [12:0] div_expadd2_in2;
wire [12:0] div_expadd2;
wire div_expadd2_12;
wire [12:0] div_exp_out_in;
wire [12:0] div_exp_out;
wire [10:0] div_exp_outa;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_div_exp_dp (
.clk(clk),
.rclk(rclk),
.enb_l(fdiv_clken_l),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exponent inputs.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(11) i_div_exp_in1 (
.din (inq_in1[62:52]),
.en (d1stg_step),
.clk (clk),
.q (div_exp_in1[10:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(11) i_div_exp_in2 (
.din (inq_in2[62:52]),
.en (d1stg_step),
.clk (clk),
.q (div_exp_in2[10:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exponent adder in the front end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd1_in1[12:0]= ({13{d234stg_fdiv}}
& div_exp1[12:0])
| ({13{div_expadd1_in1_dbl}}
& {2'b0, div_exp_in1[10:0]})
| ({13{div_expadd1_in1_sng}}
& {5'b0, div_exp_in1[10:3]});
assign div_expadd1_in2[12:0]= ({13{div_expadd1_in1_dbl}}
& 13'h0436)
| ({13{div_expadd1_in1_sng}}
& 13'h0099)
| ({13{div_expadd1_in2_exp_in2_dbl}}
& (~{2'b0, div_exp_in2[10:0]}))
| ({13{div_expadd1_in2_exp_in2_sng}}
& (~{5'b0, div_exp_in2[10:3]}))
| ({13{d3stg_fdiv}}
& (~{7'b0, div_shl_cnt[5:0]}))
| ({13{d4stg_fdiv}}
& {7'b0, div_shl_cnt[5:0]});
assign div_expadd1[12:0]= (div_expadd1_in1[12:0]
+ div_expadd1_in2[12:0]);
assign div_exp1_in[12:0]= ({13{div_exp1_expadd1}}
& div_expadd1[12:0])
| ({13{div_exp1_0835}}
& 13'h0835)
| ({13{div_exp1_0118}}
& 13'h0118)
| ({13{div_exp1_zero}}
& 13'h0000);
dffe_s #(13) i_div_exp1 (
.din (div_exp1_in[12:0]),
.en (div_exp1_load),
.clk (clk),
.q (div_exp1[12:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exponent adder in the back end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd2_in1[12:0]= ({13{div_expadd2_in1_exp_out}}
& div_exp_out[12:0])
| ({13{d5stg_fdiva}}
& div_exp1[12:0]);
assign div_expadd2_in2[12:0]= ({13{d5stg_fdiva}}
& {7'h7f, d5stg_fdivs, 1'b0, d5stg_fdivd,
d5stg_fdivs, 1'b1, d5stg_fdivs})
| ({13{d6stg_fdiv}}
& {13{div_expadd2_no_decr_inv}})
| ({13{d7stg_fdiv}}
& 13'h0000);
assign div_expadd2[12:0]= (div_expadd2_in1[12:0]
+ div_expadd2_in2[12:0]
+ {12'b0, div_expadd2_cin});
assign div_expadd2_12 = div_expadd2[12];
assign div_exp_out_in[12:0]= ({13{(div_exp_out_expadd2
&& (!(div_frac_add_52_inv
&& div_exp_out_expadd22_inv)))}}
& div_expadd2[12:0])
| ({13{div_exp_out_of}}
& {2'b00, {3{d7stg_fdivd}}, 7'h7f, d7stg_to_0_inv})
| ({13{(div_exp_out_exp_out
&& (div_frac_add_52_inv || d7stg_rndup_inv))}}
& div_exp_out[12:0]);
dffe_s #(13) i_div_exp_out (
.din (div_exp_out_in[12:0]),
.en (div_exp_out_load),
.clk (clk),
.q (div_exp_out[12:0]),
.se (se),
.si (),
.so ()
);
assign div_exp_outa[10:0]= div_exp_out[10:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; int counts[n + 1]; memset(counts, 0, sizeof(counts)); if (n == 1) { cout << 0 << endl; continue; } for (int i = 0; i < n; i++) counts[arr[i]]++; int dc = 0, rc = INT_MIN; for (int i = 0; i <= n; i++) { if (counts[i] > 0) dc++; rc = max(rc, counts[i]); } if (rc > 1) dc--; if (rc > dc + 1) cout << dc + 1 << endl; else cout << min(dc, rc) << endl; } return 0; } |
#include <bits/stdc++.h> int edge[110][110]; int main() { memset(edge, 0, sizeof(edge)); int n, u, v, w; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &w); edge[i % n][(i + 1) % n] = edge[(i + 1) % n][i % n] = w; } scanf( %d%d , &u, &v); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) { if (i == j) edge[i][j] = 0; else if (edge[i][j] == 0) edge[i][j] = 1000000; } for (int k = 0; k < n; ++k) for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) { if (i == k || j == k) continue; if (edge[i][j] > edge[i][k] + edge[k][j]) edge[i][j] = edge[i][k] + edge[k][j]; } printf( %d n , edge[u - 1][v - 1]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR2_PP_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_TB_V
`define SKY130_FD_SC_HS__OR4B_TB_V
/**
* or4b: 4-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 C = 1'b1;
#200 D_N = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 C = 1'b0;
#320 D_N = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D_N = 1'b1;
#440 C = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D_N = 1'bx;
#560 C = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hs__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_TB_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module ClockInverter(CLK_IN, PREEDGE, CLK_OUT);
input CLK_IN; // input clock
output PREEDGE; // output signal announcing an upcoming edge
output CLK_OUT; // output clock
wire CLK_OUT;
wire PREEDGE;
assign CLK_OUT = ! CLK_IN ;
assign PREEDGE = 1 ;
endmodule // ClockInverter
|
/*
* Programing Notes:
1, there are four SPRs in uartlite, access using mtspr/mfspr instructions
2, the four register are:
control register
ctrl[0]: tx_start
ctrl[1]: rx_disenable
ctrl[2]: tx_interrupt_ebable - currently not in use
ctrl[3]: rx_interrupt_enable - currently not in use
ctrl[4]: interrupt status clear
Reset Status: 8'h00
bit[0]/[4] are auto-cleared when writing true-"1" into it.
status register - READ ONLY
sta[0]: transmitter status which 1 means transmitter is busy, 0 means transmitter is idle
sta[1]: receiver status which 1 means receiver is busy, 0 means receiver is idle
sta[2]: interrupt status which 1 mean interrupt status, 0 means normal status
sta[3]: transmitter interrupt status which means transmitter interrupt
sta[4]: receiver interrupt status which means receiver interrupt
receive data register
transmit data register
* Note:
1, there is no flow control, after received a byte, if second byte is coming, first byte is covered
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module dsu_uartlite(
clk, rst,
txd, rxd,
spr_dat_i,
reg_txdata, reg_txdata_we,
reg_ctrl, reg_ctrl_we,
reg_sta, reg_sta_we,
reg_rxdata, reg_rxdata_we,
sram_ce,
sram_we,
sram_addr,
sram_wdata,
download_enable
);
//
input clk;
input rst;
// uart inout
input rxd;
output txd;
// spr access interface
input [7:0] spr_dat_i;
input reg_txdata_we;
input reg_ctrl_we;
input reg_rxdata_we;
input reg_sta_we;
output [7:0] reg_txdata;
output [7:0] reg_ctrl;
output [7:0] reg_sta;
output [7:0] reg_rxdata;
// sram interface
output sram_ce;
output sram_we;
output [31:0] sram_wdata;
output [`IOCM_Word_BW-1:0] sram_addr;
// backdoor control
input download_enable;
//
// four internal SPRs for uartlite
//
reg [7:0] reg_ctrl;
reg [7:0] reg_sta;
reg [7:0] reg_txdata;
reg [7:0] reg_rxdata;
//
wire tx_start;
wire rx_enable;
reg tx_busy_d;
reg interrupt_tx;
reg interrupt_rx;
//
//
//
wire txd;
wire rxd;
wire [7:0] rx_data;
wire [7:0] rx_data_to_sram;
wire rx_data_rdy;
wire tx_busy;
wire rx_idle;
wire interrupt;
//
// SPR: control register
//
// [TBV]: coding style of auto-cleared
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_ctrl <= 8'h00;
else if(reg_ctrl[0]) // the tx_enable bit (ctrl[0]) will auto cleared after write 1
reg_ctrl[0] <= 1'b0;
else if(reg_ctrl_we)
reg_ctrl <= spr_dat_i;
else if(reg_ctrl[4]) // the int_clear bit (ctrl[4]) will auto cleared after write 1
reg_ctrl[4] <= 1'b0;
end
assign tx_start = reg_ctrl[0];
assign rx_enable = !reg_ctrl[1];
assign int_clear = reg_ctrl[4];
//
// SPR: status register
//
// tx interrupt detect
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
tx_busy_d <= 1'b0;
else
tx_busy_d <= tx_busy;
//when detect the negedge of tx_busy that means transmitter is finished
//if the tx_interrupt enable then generate interrupt of transmitter.
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_tx <= 1'b0;
else if(!tx_busy && tx_busy_d)
interrupt_tx <= 1'b1;
else if(int_clear)
interrupt_tx <= 1'b0;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_rx <= 1'b0;
else if(rx_data_rdy && rx_enable)
interrupt_rx <= 1'b1;
else if(int_clear)
interrupt_rx <= 1'b0;
assign interrupt = interrupt_rx || interrupt_tx;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
reg_sta <= 8'h00;
else if(reg_sta_we)
reg_sta <= spr_dat_i;
else
reg_sta <= {3'b000, interrupt_rx, interrupt_tx, interrupt, !rx_idle, tx_busy};
//
// SPR: receive data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_rxdata <= 8'h00;
else if(rx_data_rdy && rx_enable )
reg_rxdata <= rx_data;
end
//
// SPR: transmit data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_txdata <= 8'h00;
else if(reg_txdata_we)
reg_txdata <= spr_dat_i;
end
//
// transmitter and receiver
//
dsu_Tx tx(
.clk(clk),
.rst(rst),
.TxD_start(tx_start),
.TxD_data(reg_txdata),
.TxD(txd),
.TxD_busy(tx_busy)
);
dsu_Rx rx(
.clk(clk),
.rst(rst),
.RxD(rxd),
.RxD_data_ready(rx_data_rdy),
.RxD_data(rx_data),
.RxD_endofpacket(),
.RxD_idle(rx_idle)
);
//
// back door mode: burn sram using received data
//
assign rx_data_to_sram = download_enable ? rx_data : 8'h00;
dsu_sram_ctrl sram_ctrl(
.clk(clk),
.rst(rst),
.rxd(rx_data_to_sram),
.rxd_ready(rx_data_rdy && download_enable),
.sram_ce(sram_ce),
.sram_we(sram_we),
.sram_addr(sram_addr),
.sram_wdata(sram_wdata),
.download_enable(download_enable)
);
endmodule |
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int main() { string s; cin >> s; int n = s.length(); vector<int> dist(n); for (int i = 0; i < n; i++) if (s[i] == 0 ) dist[i] = (i ? dist[i - 1] : 0) + 1; vector<int> dp(n + 2), nxt(n + 2, n); auto get = [&](int i) { return nxt[i] < n ? dp[nxt[i]] : 0; }; for (int i = n - 1; i >= 0; i--) { dp[i] = ((dist[i] <= dist.back()) + get(0) + get(dist[i] + 1)) % mod; nxt[dist[i]] = i; } int ans = n; if (nxt[0] < n) ans = ((long long)get(0) * (nxt[0] + 1)) % mod; cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKBUF_PP_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_4_V
`define SKY130_FD_SC_LP__NOR4BB_4_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4bb_4 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4bb_4 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_4_V
|
#include <bits/stdc++.h> using namespace std; const long long maxi = 1e18; long long prime[] = {0, 2, 3, 5, 7, 11, 13, 17, 19, 23, 29}; long long dp[15][1005], mi[15][1005], ans; int n; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); for (int i = 1; i <= 10; i++) { mi[i][0] = 1; for (int j = 1; j <= 1000; j++) { long long temp; bool flag = __builtin_mul_overflow(mi[i][j - 1], prime[i], &temp); if (!flag) mi[i][j] = mi[i][j - 1] * prime[i]; else mi[i][j] = maxi; } } int n; cin >> n; for (int i = 1; i <= 10; i++) { for (int j = 1; j <= n; j++) dp[i][j] = maxi; } for (int i = 1; i <= n; i++) dp[1][i] = mi[1][i - 1]; for (int i = 2; i <= 10; i++) { for (int j = 1; j <= n; j++) { for (int k = 1; k <= j; k++) { if (j % k == 0) { long long temp; bool flag = __builtin_mul_overflow(dp[i - 1][j / k], mi[i][k - 1], &temp); if (!flag) dp[i][j] = min(dp[i][j], dp[i - 1][j / k] * mi[i][k - 1]); } } } } cout << dp[10][n] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a; cin >> a; for (int i = 0; i < int(a.size() - 2); ++i) { char x = a[i], y = a[i + 1], z = a[i + 2]; if (x != . && y != . && z != . ) if (x != y && x != z && y != z) { cout << Yes << endl; return 0; } } cout << No << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SEDFXTP_BEHAVIORAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_21 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { long long xa, ya, xb, yb, xc, yc, a, A; cin >> xa >> ya >> xb >> yb >> xc >> yc; if ((xa == xb) && (ya == yb)) cout << YES ; else if ((xb == ya) && (yb == -xa)) cout << YES ; else if ((xb == -xa) && (yb == -ya)) cout << YES ; else if ((xb == -ya) && (yb == xa)) cout << YES ; else if (((xc * xc) + (yc * yc)) == 0) cout << NO ; else { A = (xc * xc) + (yc * yc); a = (((xb - xa) * xc) + ((yb - ya) * yc)); if (a % A == 0) { a = a / A; if ((yc != 0) && ((xb - xa - (xc * a)) % yc == 0)) { cout << YES ; return 0; } else if ((xc != 0) && ((yb - ya - (yc * a)) % xc == 0)) { cout << YES ; return 0; } } a = (((xb + ya) * xc) + ((yb - xa) * yc)); if (a % A == 0) { a = a / A; if ((yc != 0) && ((xb + ya - (xc * a)) % yc == 0)) { cout << YES ; return 0; } else if ((xc != 0) && ((yb - xa - (yc * a)) % xc == 0)) { cout << YES ; return 0; } } a = (((xb + xa) * xc) + ((yb + ya) * yc)); if (a % A == 0) { a = a / A; if ((yc != 0) && ((xb + xa - (xc * a)) % yc == 0)) { cout << YES ; return 0; } else if ((xc != 0) && ((yb + ya - (yc * a)) % xc == 0)) { cout << YES ; return 0; } } a = (((xb - ya) * xc) + ((yb + xa) * yc)); if (a % A == 0) { a = a / A; if ((yc != 0) && ((xb - ya - (xc * a)) % yc == 0)) { cout << YES ; return 0; } else if ((xc != 0) && ((yb + xa - (yc * a)) % xc == 0)) { cout << YES ; return 0; } } cout << NO ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_2TO1_TB_V
`define SKY130_FD_SC_HDLL__UDP_MUX_2TO1_TB_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_mux_2to1.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_hdll__udp_mux_2to1 dut (.A0(A0), .A1(A1), .S(S), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_2TO1_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// too bad- we have to do this!
`timescale 1ns/100ps
module util_bsplit (
data,
split_data_0,
split_data_1,
split_data_2,
split_data_3,
split_data_4,
split_data_5,
split_data_6,
split_data_7);
// parameters
parameter CH_DW = 1;
parameter CH_CNT = 8;
localparam CH_MCNT = 9;
// interface
input [((CH_CNT*CH_DW)-1):0] data;
output [(CH_DW-1):0] split_data_0;
output [(CH_DW-1):0] split_data_1;
output [(CH_DW-1):0] split_data_2;
output [(CH_DW-1):0] split_data_3;
output [(CH_DW-1):0] split_data_4;
output [(CH_DW-1):0] split_data_5;
output [(CH_DW-1):0] split_data_6;
output [(CH_DW-1):0] split_data_7;
// internal signals
wire [((CH_MCNT*CH_DW)-1):0] data_s;
// extend and split
assign data_s[((CH_MCNT*CH_DW)-1):(CH_CNT*CH_DW)] = 'd0;
assign data_s[((CH_CNT*CH_DW)-1):0] = data;
assign split_data_0 = data_s[((CH_DW*1)-1):(CH_DW*0)];
assign split_data_1 = data_s[((CH_DW*2)-1):(CH_DW*1)];
assign split_data_2 = data_s[((CH_DW*3)-1):(CH_DW*2)];
assign split_data_3 = data_s[((CH_DW*4)-1):(CH_DW*3)];
assign split_data_4 = data_s[((CH_DW*5)-1):(CH_DW*4)];
assign split_data_5 = data_s[((CH_DW*6)-1):(CH_DW*5)];
assign split_data_6 = data_s[((CH_DW*7)-1):(CH_DW*6)];
assign split_data_7 = data_s[((CH_DW*8)-1):(CH_DW*7)];
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long solve() { long long n; cin >> n; vector<long long> arr(n); map<long long, long long> counts; map<long long, long long> checks; for (auto &x : arr) { cin >> x; counts[x]++; } for (auto x : counts) { checks[x.second]++; } while (n--) { if (checks.size() == 1) { auto x = checks.begin(); if (x->first == 1 or x->second == 1) { cout << n + 1 << endl; return 0; } } if (checks.size() == 2) { auto it1 = checks.begin(); auto it2 = checks.begin(); if (it1->first == 1 and it1->second == 1) { cout << n + 1 << endl; return 0; } it2++; if (it2->first - it1->first == 1 and it2->second == 1) { cout << n + 1 << endl; return 0; } } long long x = counts[arr[n]]; if (x) { checks[x]--; counts[arr[n]]--; if (x - 1) checks[x - 1]++; if (!checks[x]) checks.erase(x); } } } signed main() { long long t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> const int MN = 2e2 + 10; template <typename T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <typename T> bool ckmax(T& a, const T& b) { return b > a ? a = b, 1 : 0; } template <typename F, int MN, int MM> struct MaxFlow { public: int hd[MN], to[MM * 2], nx[MM * 2], q[MN], cur[MN], lvl[MN], N, M, S, T; F flow[MM * 2], cap[MM * 2]; void init(int _N) { N = _N; memset(hd, -1, N * sizeof *hd); } void add1(int u, int v, F c) { flow[M] = 0, cap[M] = c; nx[M] = hd[u], to[M] = v, hd[u] = M++; } void adde(int u, int v, F c) { add1(u, v, c); add1(v, u, 0); } bool bfs() { memset(lvl, 0, N * sizeof *lvl); lvl[S] = 1; q[0] = S; for (int i = 0, Q = 1, x, y; i < Q; ++i) { x = q[i]; for (int j = hd[x]; ~j; j = nx[j]) if (cap[j] - flow[j] > 0 && !lvl[y = to[j]]) lvl[y] = lvl[x] + 1, q[Q++] = y; } return lvl[T]; } F dfs(int n, F f) { if (n == T) return f; for (int &i = cur[n], x; ~i; i = nx[i]) if (cap[i] - flow[i] > 0 && lvl[x = to[i]] == lvl[n] + 1) { F r = dfs(x, std::min(f, cap[i] - flow[i])); if (r > 0) return flow[i] += r, flow[1 ^ i] -= r, r; } return 0; } F saturate(int _S, int _T) { S = _S, T = _T; F ans = 0; while (bfs()) { F x; memcpy(cur, hd, N * sizeof *hd); for (bool ok = 0; x = dfs(S, 1);) if (x) ans += x, ok = 1; else if (ok) break; else return ans; } return ans; } }; MaxFlow<int, MN * MN * 2, MN * MN * 6> maxflow; int N, M, cnt; char a[MN][MN]; int main() { scanf( %d%d , &N, &M); maxflow.init(N * M * 2 + 2); for (int i = 0; i < N; ++i) scanf( %s , a[i]); for (int i = 0; i < N; ++i) for (int j = 0; j < M; ++j) if (a[i][j] == # ) { int u = i && a[i - 1][j] == # ? i * M + j << 1 : -1; int d = i + 1 < N && a[i + 1][j] == # ? (i + 1) * M + j << 1 : -1; int l = j && a[i][j - 1] == # ? i * M + j << 1 | 1 : -1; int r = j + 1 < M && a[i][j + 1] == # ? i * M + j + 1 << 1 | 1 : -1; if (~u && ~r) maxflow.adde(u, r, 1); if (~u && ~l) maxflow.adde(u, l, 1); if (~d && ~r) maxflow.adde(d, r, 1); if (~d && ~l) maxflow.adde(d, l, 1); ++cnt; cnt -= (u != -1) + (l != -1); } for (int i = 0; i < N * M; ++i) { maxflow.adde(N * M * 2, i * 2, 1); maxflow.adde(i * 2 + 1, N * M * 2 + 1, 1); } printf( %d n , cnt + maxflow.saturate(N * M * 2, N * M * 2 + 1)); return 0; } |
#include <bits/stdc++.h> using namespace std; void debug_out() { cerr << endl; } void clock_out() { cerr << nTime Elapsed : << 1.0 * clock() / CLOCKS_PER_SEC << s n ; } void fileio() { freopen( /home/dwai/Desktop/cp/input.txt , r , stdin); freopen( /home/dwai/Desktop/cp/output.txt , w , stdout); freopen( /home/dwai/Desktop/cp/debug.txt , w , stderr); } void ofileio() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } int IT_MAX = 1 << 20; const long long MOD = 1000000007; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const double PI = acos(-1); const double ERR = 1e-10; void solve() { long long n, sx, sy; cin >> n >> sx >> sy; vector<pair<long long, long long> > v(n); long long i; long long d[n]; for (i = 0; i < n; i++) { cin >> v[i].first >> v[i].second; d[i] = abs(v[i].first - sx) + abs(v[i].second - sy); } pair<long long, long long> p; long long m = 0; vector<pair<long long, long long> > pos({{0, 1}, {0, -1}, {1, 0}, {-1, 0}}); for (pair<long long, long long> cord : pos) { long long cx = cord.first + sx, cy = cord.second + sy; long long cm = 0; i = 0; for (pair<long long, long long> x : v) { long long cd = abs(cx - x.first) + abs(cy - x.second); if (cd < d[i]) cm++; i++; } if (cm > m) { m = cm; p = make_pair(cx, cy); } } cout << m << n << p.first << << p.second; } int main() { 42; ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); srand(time(NULL)); long long t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int smallest, largest, n, count = 0, a; cin >> n; for (int i = 0; i < n; i++) { cin >> a; if (i == 0) { smallest = a; largest = a; } else { if (a > largest) { count += 1; largest = a; } else if (a < smallest) { count += 1; smallest = a; } } } cout << count; } |
#include <bits/stdc++.h> using namespace std; struct S { long long prime; int q, h, ji; }; S xxx[300000]; priority_queue<S> sum[4]; bool biao[300000]; bool operator<(const S &a, const S &b) { return a.prime > b.prime; } int main() { int x, y; cin >> x; for (int a = 0; a < x; a++) { cin >> xxx[a].prime; xxx[a].ji = a; } for (int a = 0; a < x; a++) cin >> xxx[a].q; for (int a = 0; a < x; a++) cin >> xxx[a].h; for (int a = 0; a < x; a++) { sum[xxx[a].q].push(xxx[a]); sum[xxx[a].h].push(xxx[a]); } cin >> y; while (y--) { cin >> x; while (!sum[x].empty() && biao[sum[x].top().ji]) sum[x].pop(); if (sum[x].empty()) cout << -1 ; else { cout << sum[x].top().prime; biao[sum[x].top().ji] = 1; sum[x].pop(); } y == 0 ? cout << endl : cout << ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_2_V
`define SKY130_FD_SC_HDLL__CLKINVLP_2_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinvlp_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinvlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__HA_BEHAVIORAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_BEHAVIORAL_PP_V |
module conmutacion (
input [3:0] centenas,
input [3:0] decenas,
input [3:0] unidades,
input C,
input De,
input U,
input CLKOUTseg,
output reg [1:0] mostrar,
output reg [3:0] digito
);
reg logic0;
reg [1:0] titileo;
initial
begin
titileo = 0;
end
always@(posedge CLKOUTseg)
begin
if(C && De && U)
begin
/*if(titileo == 3)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(De && U)
begin
/*if(titileo == 1)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(U)
begin
titileo <= 1;
end
else
begin
titileo <= 0;
end
end
end
end
always@(posedge CLKOUTseg)
begin
case(titileo)
2'b00:
begin
mostrar = 2'b01;
digito = 0;
end
2'b01:
begin
mostrar = 2'b01;
digito = unidades;
end
2'b10:
begin
mostrar = 2'b10;
digito = decenas;
end
2'b11:
begin
mostrar = 2'b11;
digito = centenas;
end
endcase
end
endmodule
|
module sampler(iClock, iReset, iStartSignal, oAddress, oFinished);
parameter IDLE = 2'b00,
SAMPLING = 2'b01,
INCREMENTING_ADDR = 2'b10,
FINISHED_SAMPLING = 2'b11;
input iClock;
input iReset;
input iStartSignal;
output reg [15:0] oAddress;
output oFinished;
reg [1:0] state = IDLE;
wire [1:0] next_state;
assign next_state = next_state_fun(state, iStartSignal, oAddress);
function [1:0] next_state_fun(input [1:0] state, input start_signal, input [15:0] address);
case(state)
IDLE:
if (start_signal) begin
next_state_fun = SAMPLING;
end else begin
next_state_fun = IDLE;
end
SAMPLING:
if (address < 16'hFFFF) begin
next_state_fun = INCREMENTING_ADDR;
end else begin
next_state_fun = FINISHED_SAMPLING;
end
INCREMENTING_ADDR:
next_state_fun = SAMPLING;
FINISHED_SAMPLING:
next_state_fun = IDLE;
default:
next_state_fun = IDLE;
endcase
endfunction
always@(posedge iClock) begin
if (iReset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always@(posedge iClock) begin
oFinished <= 0;
case(state)
IDLE: begin
oAddress <= 16'b0;
end
SAMPLING: begin
end
INCREMENTING_ADDR: begin
oAddress <= oAddress + 16'b1;
end
FINISHED_SAMPLING: begin
oFinished <= 1;
end
endcase
end
endmodule |
module Platform (
clk_clk,
dds_left_strobe_export,
dds_right_strobe_export,
hex0_2_export,
hex3_5_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
i2c_SDAT,
i2c_SCLK,
i2s_codec_iadcdat,
i2s_codec_iadclrc,
i2s_codec_ibclk,
i2s_codec_idaclrc,
i2s_codec_odacdat,
i2s_gpio_iadcdat,
i2s_gpio_iadclrc,
i2s_gpio_ibclk,
i2s_gpio_idaclrc,
i2s_gpio_odacdat,
keys_export,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n,
strobe_export,
switches_export,
white_noise_left_strobe_export,
white_noise_right_strobe_export,
xck_clk);
input clk_clk;
input dds_left_strobe_export;
input dds_right_strobe_export;
output [20:0] hex0_2_export;
output [20:0] hex3_5_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
inout i2c_SDAT;
output i2c_SCLK;
input i2s_codec_iadcdat;
input i2s_codec_iadclrc;
input i2s_codec_ibclk;
input i2s_codec_idaclrc;
output i2s_codec_odacdat;
input i2s_gpio_iadcdat;
input i2s_gpio_iadclrc;
input i2s_gpio_ibclk;
input i2s_gpio_idaclrc;
output i2s_gpio_odacdat;
input [2:0] keys_export;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
output strobe_export;
input [9:0] switches_export;
input white_noise_left_strobe_export;
input white_noise_right_strobe_export;
output xck_clk;
endmodule
|
#include <bits/stdc++.h> int x[100001] = {0}; int main() { int i, n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &x[i]); } int sum = 0; int cn = 0; for (i = 0; i < n; i++) { sum = sum + x[i] - x[i + 1]; if (sum < 0) { do { cn++; sum++; } while (sum < 0); } } printf( %d , cn); return 0; } |
module testbench (
CLOCK_50, // 50 MHz
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
debug_sw
);
input CLOCK_50; // 50 MHz
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
input debug_sw;
wire DLY_RST;
wire [4:0] wire_lcd_ctrl;
reset_gen r0 (
.clock (CLOCK_50),
.reset (DLY_RST)
);
lcd_bridge u5 (
.clock (CLOCK_50),
.reset (DLY_RST),
.insert (debug_sw),
.new_record ({4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8}),
// LCD Side
.lcd_data (LCD_DATA),
.lcd_ctrl (wire_lcd_ctrl)
);
assign {LCD_RW, LCD_EN, LCD_RS, LCD_ON, LCD_BLON} = wire_lcd_ctrl;
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( O3 ) const long long inf = 1e17; void bfs(int a, vector<vector<int> > &g, vector<int> &da) { int n = g.size(); queue<int> q; q.push(a); vector<bool> u(n, false); u[a] = true; da[a] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (int i = 0; i < g[v].size(); i++) { int x = g[v][i]; if (!u[x]) { u[x] = true; da[x] = da[v] + 1; q.push(x); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int q; cin >> q; while (q--) { int n, m, a, b, c; cin >> n >> m >> a >> b >> c; a--; b--; c--; vector<vector<int> > g(n, vector<int>(0)); vector<long long> cost(m); for (int i = 0; i < m; i++) cin >> cost[i]; sort(cost.begin(), cost.end()); for (int i = 1; i < m; i++) cost[i] += cost[i - 1]; vector<int> da(n, 0), db(n, 0), dc(n, 0); for (int i = 0; i < m; i++) { int fr, to; cin >> fr >> to; fr--; to--; g[fr].push_back(to); g[to].push_back(fr); } bfs(a, g, da); bfs(b, g, db); bfs(c, g, dc); long long ans = inf; for (int i = 0; i < n; i++) { if (da[i] + db[i] + dc[i] - 1 > m - 1) continue; long long cur = 0; if (da[i] + db[i] + dc[i] != 0) cur += cost[da[i] + db[i] + dc[i] - 1]; if (db[i] > 0) cur += cost[db[i] - 1]; ans = min(ans, cur); } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void USACO(string s) { ios_base::sync_with_stdio(0); cin.tie(0); freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } const long long MAXN = 5010; void solve() { long long n; string s; cin >> n; cin >> s; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long dp[n][4]; memset(dp, 0, sizeof(dp)); dp[0][0] = (s[0] != h ? 0 : a[0]); dp[0][1] = (s[0] == h ? 0 : 1e15); dp[0][2] = dp[0][3] = 1e15; for (long long i = 1; i < n; i++) { dp[i][0] = dp[i][1] = dp[i][2] = dp[i][3] = 1e15; dp[i][0] = dp[i - 1][0] + (s[i] == h ? a[i] : 0); if (s[i] == h ) dp[i][1] = dp[i - 1][0]; dp[i][1] = min(dp[i][1], dp[i - 1][1] + (s[i] == a ? a[i] : 0)); if (s[i] == a ) dp[i][2] = dp[i - 1][1]; dp[i][2] = min(dp[i][2], dp[i - 1][2] + (s[i] == r ? a[i] : 0)); if (s[i] == r ) dp[i][3] = dp[i - 1][2]; dp[i][3] = min(dp[i][3], dp[i - 1][3] + (s[i] == d ? a[i] : 0)); } cout << min(min(dp[n - 1][0], dp[n - 1][1]), min(dp[n - 1][2], dp[n - 1][3])) << n ; } int main() { solve(); } |
#include <bits/stdc++.h> using namespace std; const int dx[9] = {0, 1, -1, 0, 0, -1, -1, 1, 1}; const int dy[9] = {0, 0, 0, -1, 1, -1, 1, -1, 1}; const double pi = acos(-1.0); const int N = 1e5 + 100; long long pre[N], a[N], temp[200], ans = 0; int n, k, ma = 0; map<long long, long long> dic; int main() { scanf( %d , &n), scanf( %d , &k); long long t = 1; temp[0] = 1; if (k == 1 || k == -1) { if (k == 1) { ma = 0; temp[0] = 1; } else { ma = 1; temp[0] = 1; temp[1] = -1; } } else { while (abs(t * k) < 1e15) { ma++; t = t * k; temp[ma] = t; } } for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 0; i <= ma; i++) dic[temp[i] + 0]++; for (int i = 1; i <= n; i++) { pre[i] = pre[i - 1] + a[i]; ans += dic[pre[i]]; for (int j = 0; j <= ma; j++) dic[pre[i] + temp[j]]++; } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_BLACKBOX_V
`define SKY130_FD_SC_HS__A222OI_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void upd(long long& x) { x = -x - 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long> a(n); for (int j = 0; j < n; j++) { cin >> a[j]; if (a[j] >= 0) upd(a[j]); } if (n & 1) { int jd = 0; for (int j = 0; j < n; j++) { if (a[jd] > a[j]) jd = j; } upd(a[jd]); } for (int j = 0; j < n; j++) cout << a[j] << ; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "setup.v"
module vga #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Framebuffer FML 4x64 interface */
output [fml_depth-1:0] fml_adr,
output fml_stb,
input fml_ack,
input [63:0] fml_di,
/* Direct Cache Bus */
output dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
/* VGA pads */
output vga_psave_n,
output vga_hsync_n,
output vga_vsync_n,
output vga_sync_n,
output vga_blank_n,
output [7:0] vga_r,
output [7:0] vga_g,
output [7:0] vga_b,
output vga_clkout
);
wire vga_clk;
reg [1:0] fcounter;
always @(posedge sys_clk) fcounter <= fcounter + 2'd1;
assign vga_clk = fcounter[1];
assign vga_clkout = vga_clk;
vgafb #(
.csr_addr(csr_addr),
.fml_depth(fml_depth)
) vgafb (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_di(fml_di),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit),
.vga_clk(vga_clk),
.vga_psave_n(vga_psave_n),
.vga_hsync_n(vga_hsync_n),
.vga_vsync_n(vga_vsync_n),
.vga_sync_n(vga_sync_n),
.vga_blank_n(vga_blank_n),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 999999999; const double EPSILON = 0.00000001; const long long MOD = 1000000007; bool used[200005]; struct interval { int first, second; int idx; }; bool operator<(const interval &self, const interval &other) { return self.first < other.first; } int main() { int x, n; cin >> x >> n; vector<interval> intervals; for (int i = 0; i < n; i++) { int a, l; scanf( %d %d , &a, &l); intervals.push_back((interval){a, a + l - 1, i + 1}); } memset(used, false, sizeof(used)); sort(intervals.begin(), intervals.end()); int i = 0, prev = 0; int end = intervals[0].first - 1; int best = 0; int cnt = 0; while (i < n) { while (i < n and intervals[i].first <= end + 1) { if (intervals[i].second > intervals[best].second) { best = i; } i++; } if (used[best]) { if (i < n) end = intervals[i].first - 1; } else { end = intervals[best].second; used[best] = true; cnt++; } } cout << n - cnt << endl; bool first = true; for (int i = 0; i < n; i++) { if (not used[i]) { if (not first) putchar( ); printf( %d , intervals[i].idx); first = false; } } if (cnt != n) cout << endl; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) using namespace std; const int arr = 2e5 + 10; const int ar = 2e3 + 10; const long double pi = acos(-1); const long double eps = 1e-10; const long long md = 1e9 + 7; vector<int> reb1[arr]; vector<int> reb2[arr]; bool use[arr]; int comp[arr]; const int M = 70 / 4 + 1; int dist[1ll << M][71]; void dfs(int now, int c) { comp[now] = c; use[now] = 1; for (auto wh : reb1[now]) { if (!use[wh]) { dfs(wh, c); } } } int main() { int n, m, a, b; cin >> n >> m >> a >> b; for (int i = 0; i < m; i++) { int u, v, c; cin >> u >> v >> c; if (c == a) { reb1[u].push_back(v); reb1[v].push_back(u); } if (c == b) { reb2[u].push_back(v); reb2[v].push_back(u); } } int c = 0; int cc = 1e5; for (int i = 1; i <= n; i++) { if (!use[i]) { dfs(i, ++c); int cnt = 0; for (int j = 1; j <= n; j++) { if (comp[j] == c) { cnt++; } } if (cnt <= 3) { for (int j = 1; j <= n; j++) { if (comp[j] == c) { comp[j] = cc; } } cc--; c--; } } } set<pair<int, pair<int, int>>> s; int start_mask = 0; if (comp[1] <= c) { start_mask |= (1ll << (comp[1] - 1)); } for (int m = 0; m < (1ll << c); m++) { for (int j = 1; j <= n; j++) { if (j == 1 && m == start_mask) { dist[m][j] = 0; } else { dist[m][j] = 2e9 + 1; } s.insert(make_pair(dist[m][j], make_pair(m, j))); } } function<bool(int, int)> have_bit = [&](int m, int bit) { return m & (1ll << bit); }; while (!s.empty()) { pair<int, int> now = s.begin()->second; s.erase(s.begin()); for (auto wh : reb1[now.second]) { if (comp[wh] > c || comp[now.second] == comp[wh] || !have_bit(now.first, comp[wh] - 1)) { int to_m = now.first | (comp[wh] > c ? 0 : (1ll << (comp[wh] - 1))); if (dist[to_m][wh] > dist[now.first][now.second] + a) { s.erase(make_pair(dist[to_m][wh], make_pair(to_m, wh))); dist[to_m][wh] = dist[now.first][now.second] + a; s.insert(make_pair(dist[to_m][wh], make_pair(to_m, wh))); } } } for (auto wh : reb2[now.second]) { if ((comp[wh] > c || !have_bit(now.first, comp[wh] - 1)) && (comp[wh] != comp[now.second])) { int to_m = now.first | (comp[wh] > c ? 0 : (1ll << (comp[wh] - 1))); if (dist[to_m][wh] > dist[now.first][now.second] + b) { s.erase(make_pair(dist[to_m][wh], make_pair(to_m, wh))); dist[to_m][wh] = dist[now.first][now.second] + b; s.insert(make_pair(dist[to_m][wh], make_pair(to_m, wh))); } } } } for (int j = 1; j <= n; j++) { int ans = 2e9 + 1; for (int m = 0; m < (1ll << c); m++) { ans = min(ans, dist[m][j]); } cout << ans << ; } cout << n ; } |
#include <bits/stdc++.h> using namespace std; int n; long double ans1[1000000]; long double ans2[1000000]; long double sa[1000000]; long double sb[1000000]; long double x1[1000000]; long double x[1000000]; long double sqr(long double x) { return x * x; } long double sqrtt(long double x) { if (x < 0) return 0; return sqrt(x); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 1; i <= n; i++) cin >> x[i]; for (int i = 1; i <= n; i++) cin >> x1[i]; for (int i = 1; i <= 1; i++) { long double D = sqrtt(-4 * x[i] + sqr(x1[i] + x[i])); ans1[i] = (x1[i] + x[i] + D) / 2.; ans2[i] = x[i] / ans1[i]; sa[i] = ans1[i]; sb[i] = ans2[i]; } for (int i = 2; i <= n; i++) { long double a = 1; long double b = sa[i - 1] - x[i] - sb[i - 1] - x1[i]; long double c = x[i] - sa[i - 1] * x[i] - x1[i] * sa[i - 1]; long double D = sqrtt(b * b - a * c * 4); ans1[i] = (-b + D) / 2.; ans2[i] = (x[i] - ans1[i] * sb[i - 1]) / (ans1[i] + sa[i - 1]); sa[i] = ans1[i] + sa[i - 1]; sb[i] = ans2[i] + sb[i - 1]; } cout.precision(9); for (int i = 1; i <= n; i++) cout << fixed << ans1[i] << ; cout << n ; for (int i = 1; i <= n; i++) cout << fixed << ans2[i] << ; cout << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int long long n, c = 0; cin >> n; for (int long long i = 1; i < n; i++) { if (n % i == 0) { c++; } } cout << (c); return 0; } |
#include <bits/stdc++.h> using namespace std; int N, a[100005], b[100005]; char s1[100005], s2[100005]; long long x11, x01, x10, x00, ans; int main() { scanf( %d , &N); cin >> s1; cin >> s2; for (int i = 1; i <= N; ++i) a[i] = s1[i - 1] - 0 , b[i] = s2[i - 1] - 0 ; for (int i = 1; i <= N; ++i) { if (!a[i] && !b[i]) x00++; else if (!a[i] && b[i]) x01++; else if (a[i] && !b[i]) x10++; else x11++; } ans = x11 * x00 + x00 * x10 + x10 * x01; cout << ans << endl; return 0; } |
module core_top(
input clk, rst, run_n,
input [3:0] reg_addr_d,
output [15:0] reg_out
);
//wire clk;
wire reg_we, sram_we_n, ram_wren;
wire [2:0] alu_operator;
wire [3:0] reg_addr_a, reg_addr_b, reg_addr_c;
wire [15:0] ram_addr, ram_data, reg_data_a, reg_data_b, reg_data_c, reg_data_d, alu_op_a,alu_out,alu_status, ram_q,pc;
assign reg_out = reg_data_d;
assign ram_wren = ~sram_we_n;
//pll_slow mhz_5(clk_50, clk);
register_file register_file0(clk, rst, reg_we, reg_addr_a, reg_addr_b, reg_addr_c, reg_addr_d, reg_data_c, reg_data_a, reg_data_b, reg_data_d);
alu16 alu16_0( clk,rst,alu_operator, alu_op_a, reg_data_b, alu_out, alu_status);
control_fsm control_fsm0( clk, rst, run_n, ram_q, reg_data_a, reg_data_b, alu_status, alu_out,
sram_we_n, reg_we, alu_operator, reg_addr_a, reg_addr_b,
reg_addr_c, alu_op_a, reg_data_c, ram_addr, ram_data);
main_memory main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_sxm_d main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_sxm main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_ram_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_ram_test2 main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_addi_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_lw_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_sw_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
//main_memory_ble_test main_memory0(ram_addr[7:0], clk, ram_data, ram_wren, ram_q);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long Pow(long long a, long long b) { long long ans = 1LL, base = a % 1000000007; while (b != 0) { if (b & 1LL != 0) ans = ans * base % 1000000007; base = base * base % 1000000007; b >>= 1LL; } return ans; } long long A, B, n, x; long long ans; int main() { scanf( %lld %lld %lld %lld , &A, &B, &n, &x); long long ppow = Pow(A, n) % 1000000007; if (A == 1LL) ans = (x % 1000000007 + n % 1000000007 * B % 1000000007) % 1000000007; else ans = (ppow * x % 1000000007 + B % 1000000007 * (ppow - 1LL) % 1000000007 * Pow(A - 1LL, 1000000007 - 2) % 1000000007) % 1000000007; cout << ans; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arp
*/
module test_arp_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter CACHE_ADDR_WIDTH = 2;
parameter REQUEST_RETRY_COUNT = 4;
parameter REQUEST_RETRY_INTERVAL = 150;
parameter REQUEST_TIMEOUT = 400;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
reg arp_request_valid = 0;
reg [31:0] arp_request_ip = 0;
reg arp_response_ready = 0;
reg [47:0] local_mac = 0;
reg [31:0] local_ip = 0;
reg [31:0] gateway_ip = 0;
reg [31:0] subnet_mask = 0;
reg clear_cache = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire arp_request_ready;
wire arp_response_valid;
wire arp_response_error;
wire [47:0] arp_response_mac;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
arp_request_valid,
arp_request_ip,
arp_response_ready,
local_mac,
local_ip,
gateway_ip,
subnet_mask,
clear_cache
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
arp_request_ready,
arp_response_valid,
arp_response_error,
arp_response_mac
);
// dump file
$dumpfile("test_arp_64.lxt");
$dumpvars(0, test_arp_64);
end
arp #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH),
.REQUEST_RETRY_COUNT(REQUEST_RETRY_COUNT),
.REQUEST_RETRY_INTERVAL(REQUEST_RETRY_INTERVAL),
.REQUEST_TIMEOUT(REQUEST_TIMEOUT)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// ARP requests
.arp_request_valid(arp_request_valid),
.arp_request_ready(arp_request_ready),
.arp_request_ip(arp_request_ip),
.arp_response_valid(arp_response_valid),
.arp_response_ready(arp_response_ready),
.arp_response_error(arp_response_error),
.arp_response_mac(arp_response_mac),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_cache(clear_cache)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_2_V
`define SKY130_FD_SC_HD__O31AI_2_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 09:48:07 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_ireq_tvalid,
s_axis_ireq_tready, s_axis_ireq_tlast, s_axis_ireq_tdata, s_axis_ireq_tkeep,
s_axis_ireq_tuser, m_axis_iresp_tvalid, m_axis_iresp_tready, m_axis_iresp_tlast,
m_axis_iresp_tdata, m_axis_iresp_tkeep, m_axis_iresp_tuser, m_axis_treq_tvalid,
m_axis_treq_tready, m_axis_treq_tlast, m_axis_treq_tdata, m_axis_treq_tkeep,
m_axis_treq_tuser, s_axis_tresp_tvalid, s_axis_tresp_tready, s_axis_tresp_tlast,
s_axis_tresp_tdata, s_axis_tresp_tkeep, s_axis_tresp_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_ireq_tvalid,s_axis_ireq_tready,s_axis_ireq_tlast,s_axis_ireq_tdata[63:0],s_axis_ireq_tkeep[7:0],s_axis_ireq_tuser[31:0],m_axis_iresp_tvalid,m_axis_iresp_tready,m_axis_iresp_tlast,m_axis_iresp_tdata[63:0],m_axis_iresp_tkeep[7:0],m_axis_iresp_tuser[31:0],m_axis_treq_tvalid,m_axis_treq_tready,m_axis_treq_tlast,m_axis_treq_tdata[63:0],m_axis_treq_tkeep[7:0],m_axis_treq_tuser[31:0],s_axis_tresp_tvalid,s_axis_tresp_tready,s_axis_tresp_tlast,s_axis_tresp_tdata[63:0],s_axis_tresp_tkeep[7:0],s_axis_tresp_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_ireq_tvalid;
output s_axis_ireq_tready;
input s_axis_ireq_tlast;
input [63:0]s_axis_ireq_tdata;
input [7:0]s_axis_ireq_tkeep;
input [31:0]s_axis_ireq_tuser;
output m_axis_iresp_tvalid;
input m_axis_iresp_tready;
output m_axis_iresp_tlast;
output [63:0]m_axis_iresp_tdata;
output [7:0]m_axis_iresp_tkeep;
output [31:0]m_axis_iresp_tuser;
output m_axis_treq_tvalid;
input m_axis_treq_tready;
output m_axis_treq_tlast;
output [63:0]m_axis_treq_tdata;
output [7:0]m_axis_treq_tkeep;
output [31:0]m_axis_treq_tuser;
input s_axis_tresp_tvalid;
output s_axis_tresp_tready;
input s_axis_tresp_tlast;
input [63:0]s_axis_tresp_tdata;
input [7:0]s_axis_tresp_tkeep;
input [31:0]s_axis_tresp_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_1_V
`define SKY130_FD_SC_MS__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_1_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, RGB to CrYCb conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128;
// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
module cf_csc_RGB2CrYCb (
// R-G-B inputs
clk,
RGB_vs,
RGB_hs,
RGB_de,
RGB_data,
// Cr-Y-Cb outputs
CrYCb_vs,
CrYCb_hs,
CrYCb_de,
CrYCb_data);
// R-G-B inputs
input clk;
input RGB_vs;
input RGB_hs;
input RGB_de;
input [23:0] RGB_data;
// Cr-Y-Cb outputs
output CrYCb_vs;
output CrYCb_hs;
output CrYCb_de;
output [23:0] CrYCb_data;
reg CrYCb_vs = 'd0;
reg CrYCb_hs = 'd0;
reg CrYCb_de = 'd0;
reg [23:0] CrYCb_data = 'd0;
wire Cr_vs_s;
wire Cr_hs_s;
wire Cr_de_s;
wire [ 7:0] Cr_data_s;
wire Y_vs_s;
wire Y_hs_s;
wire Y_de_s;
wire [ 7:0] Y_data_s;
wire Cb_vs_s;
wire Cb_hs_s;
wire Cb_de_s;
wire [ 7:0] Cb_data_s;
// output registers (the control signals are gated together)
always @(posedge clk) begin
CrYCb_vs <= Cr_vs_s & Y_vs_s & Cb_vs_s;
CrYCb_hs <= Cr_hs_s & Y_hs_s & Cb_hs_s;
CrYCb_de <= Cr_de_s & Y_de_s & Cb_de_s;
CrYCb_data <= {Cr_data_s, Y_data_s, Cb_data_s};
end
// Cr (red-diff)
cf_csc_1 i_csc_Cr (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h00707),
.C2 (17'h105e2),
.C3 (17'h10124),
.C4 (25'h0080000),
.csc_vs (Cr_vs_s),
.csc_hs (Cr_hs_s),
.csc_de (Cr_de_s),
.csc_data_1 (Cr_data_s));
// Y (luma)
cf_csc_1 i_csc_Y (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h0041b),
.C2 (17'h00810),
.C3 (17'h00191),
.C4 (25'h0010000),
.csc_vs (Y_vs_s),
.csc_hs (Y_hs_s),
.csc_de (Y_de_s),
.csc_data_1 (Y_data_s));
// Cb (blue-diff)
cf_csc_1 i_csc_Cb (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h1025f),
.C2 (17'h104a7),
.C3 (17'h00707),
.C4 (25'h0080000),
.csc_vs (Cb_vs_s),
.csc_hs (Cb_hs_s),
.csc_de (Cb_de_s),
.csc_data_1 (Cb_data_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
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