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#include <bits/stdc++.h> using namespace std; const long long maxN = 1e6 + 100; const long long maxM = 1e3 + 100; const long long mod = 1e9 + 7; const long long hmod = 1e16 + 7; const long double PI = 3.141592653; const long double eps = 1e-8; const long long D = 1379; const long long INF = 1e18 + 20; const long long Inf = 1e9 + 140; void NO() { cout << NO << endl; exit(0); } void YES() { cout << YES << endl; exit(0); } long long n, k; bool mrk[2][maxN], mark[2][maxN]; void dfs(long long v, long long x = 0, long long W = 0) { if (v > n) YES(); if (v <= 0 || mrk[x][v] || mark[x][v] || v <= W) return; mark[x][v] = true; W++; dfs(v + k, x ^ 1, W); dfs(v + 1, x, W); dfs(v - 1, x, W); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (long long i = 1; i <= n; i++) { char c; cin >> c; if (c == X ) mrk[0][i] = true; } for (long long i = 1; i <= n; i++) { char c; cin >> c; if (c == X ) mrk[1][i] = true; } dfs(1); NO(); } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
// the core, dac_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dac_buf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Standard functions and combinators.
* Proofs about them require functional extensionality and can be found in [Combinators].
*
* Author: Matthieu Sozeau
* Institution: LRI, CNRS UMR 8623 - UniversitÃcopyright Paris Sud
* 91405 Orsay, France *)
(* $Id$ *)
(** The polymorphic identity function. *)
Definition id {A} := fun x : A => x.
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Open Local Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Implicit Arguments prod_curry [[A] [B] [C]].
Implicit Arguments prod_uncurry [[A] [B] [C]].
|
// $Id: c_arbiter.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic arbiter
//==============================================================================
module c_arbiter
(clk, reset, active, req_pr, gnt_pr, gnt, update);
`include "c_functions.v"
`include "c_constants.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
// number fo bits required to select a port
localparam port_idx_width = clogb(num_ports);
// select type of arbiter to use
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
// for round-robin style arbiters, should state be stored in encoded form?
localparam encode_state
= (arbiter_type==`ARBITER_TYPE_ROUND_ROBIN_BINARY) ||
(arbiter_type==`ARBITER_TYPE_PREFIX_BINARY);
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// request vector
input [0:num_priorities*num_ports-1] req_pr;
// grant vector
output [0:num_priorities*num_ports-1] gnt_pr;
wire [0:num_priorities*num_ports-1] gnt_pr;
// merged grant vector
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
// update port priorities
input update;
generate
if(num_ports == 1)
begin
c_lod
#(.width(num_priorities))
gnt_lod
(.data_in(req_pr),
.data_out(gnt_pr));
assign gnt = |req_pr;
end
else if(num_ports > 1)
begin
case(arbiter_type)
`ARBITER_TYPE_ROUND_ROBIN_BINARY,
`ARBITER_TYPE_ROUND_ROBIN_ONE_HOT:
begin
c_rr_arbiter
#(.num_ports(num_ports),
.num_priorities(num_priorities),
.encode_state(encode_state),
.reset_type(reset_type))
rr_arb
(.clk(clk),
.reset(reset),
.active(active),
.req_pr(req_pr),
.gnt_pr(gnt_pr),
.gnt(gnt),
.update(update));
end
`ARBITER_TYPE_PREFIX_BINARY, `ARBITER_TYPE_PREFIX_ONE_HOT:
begin
c_prefix_arbiter
#(.num_ports(num_ports),
.num_priorities(num_priorities),
.encode_state(encode_state),
.reset_type(reset_type))
prefix_arb
(.clk(clk),
.reset(reset),
.active(active),
.req_pr(req_pr),
.gnt_pr(gnt_pr),
.gnt(gnt),
.update(update));
end
`ARBITER_TYPE_MATRIX:
begin
c_matrix_arbiter
#(.num_ports(num_ports),
.num_priorities(num_priorities),
.reset_type(reset_type))
matrix_arb
(.clk(clk),
.reset(reset),
.active(active),
.req_pr(req_pr),
.gnt_pr(gnt_pr),
.gnt(gnt),
.update(update));
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long SIZE = 1e5 + 5; const long long mod = 1e9 + 7; int main() { long long t = 0, n, x, y, z, i, j, k, g, p, q, ans = 0, sum = 0, c = 0; string s, s1, s2; scanf( %lld , &q); while (q--) { cin >> s; n = s.size(); t = 0; c = 0; p = 0; for (i = 0; i < n; i++) { if (s[i] != : ) { t++; j = i; while (s[j] != : && j < n) j++; i = j - 1; } else { if (s[i + 1] == : ) c = i + 1; } } if (c) t = 8 - t; for (i = 0; i < n; i++) { if (s[i] != : ) { j = i; x = 0; while (s[j] != : && j < n) { x++; j++; } for (y = 1; y <= 4 - x; y++) cout << 0; for (y = i; y < j; y++) cout << s[y]; p++; i = j - 1; } else { if (s[i + 1] == : && i + 1 == 1) { for (x = 1; x <= t; x++) { cout << 0000 ; p++; if (p != 8) cout << : ; } i++; continue; } cout << s[i]; if (s[i + 1] == : ) { for (x = 1; x <= t; x++) { cout << 0000 ; p++; if (p != 8) cout << : ; } i++; } } } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int q; cin >> q; while (q--) { int n; cin >> n; string s, t; cin >> s >> t; string ss = s; string tt = t; sort(ss.begin(), ss.end()); sort(tt.begin(), tt.end()); int ans; if (ss != tt) ans = -1; else { ans = INT_MAX; for (int i = 0; i < n; i++) { int k = i; for (int j = 0; j < n; j++) { if (k < n and s[j] == t[k]) k++; } ans = min(ans, n - k + i); } } cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_BLACKBOX_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int tests; scanf( %d , &tests); while (tests--) { int item; cin >> item; vector<int> v; set<int> s; int temp; for (int i = 0; i < item; i++) { scanf( %d , &temp); v.push_back(temp); s.insert(temp); } int distinct = 0; cout << s.size() << n ; } return 0; } |
`timescale 1 ns / 1 ps
`include "Volume_Pregain_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module Volume_Pregain_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void UpdateMax(T& a, T b) { if (a < b) a = b; } template <typename T> void UpdateMin(T& a, T b) { if (a > b) a = b; } template <typename T> inline void read(T& x) { x = 0; char c = getchar(); int flag = 1; while (!isdigit(c)) { if (c == - ) flag = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x *= flag; } template <typename T> void Unique(vector<T>& vec) { sort(vec.begin(), vec.end()); vec.erase(unique(vec.begin(), vec.end()), vec.end()); } template <typename T> void Relabel(vector<T>& vec, T& value) { value = lower_bound(vec.begin(), vec.end(), value) - vec.begin() + 1; } template <typename T, typename V> void Print(const pair<T, V>& x) { cout << x.first << @ << x.second << | ; } template <typename T> void Print(const T& x) { cout << x << ; } template <typename T> void Pcon(const T& x) { cout << nsize: << x.size() << endl; for (const auto& item : x) Print(item); } std::vector<int> LABS; template <typename T> void Print(const T* x, int offset, int loop) { for (int i = 0; i <= loop; i++) { cout << [ ; for (int item : LABS) cout << item - offset << , ; cout << i - offset << ]: ; cout << x[i] << ; } } template <typename T, typename... Args> void Print(const T* f, int offset, int loop, Args... args) { for (int i = 0; i <= loop; i++) { LABS.push_back(i); Print(f[i], offset, args...); cout << endl; LABS.pop_back(); } } template <typename T, typename V> bool Has(T& cluster, const V& item) { return cluster.find(item) != cluster.end(); } int Logn(long long x) { int cnt = 0; while (x) { ++cnt; x >>= 1; } return cnt; } const int MOD = 1e9 + 7; const int N = 2e5 + 5; const int dir[4][2] = {{-1, 0}, {0, -1}, {1, 0}, {1, 0}}; struct Edg { int x, y, z; friend bool operator<(const Edg& lhs, const Edg& rhs) { return lhs.z < rhs.z; } } edg[N]; bool vis[N], used[N]; clock_t start_time; int t, n, m; int f[N], a[N]; vector<int> G[N]; inline void SetClock() { start_time = clock(); } bool TimeOut(size_t ms) { if (1000 * (clock() - start_time) >= ms * ((clock_t)1000)) return true; return false; } inline pair<int, int> DeSerialize(int c) { return {(c) / m, (c) % m}; } template <typename T, typename V> inline void Add(T& v, const V& delta) { v += delta; if (v >= MOD) v -= MOD; } template <typename T, typename V> inline void Dec(T& v, const V& delta) { v -= delta; if (v < 0) v += MOD; } long long ksm(long long a, long long b) { long long cnt = 1; while (b) { if (b & 1) cnt = cnt * a % MOD; b >>= 1; a = a * a % MOD; } return cnt; } int main() { srand(time(0)); SetClock(); cin.sync_with_stdio(false); cin >> n; for (int(i) = 1; (i) <= (n); ++(i)) { cin >> a[i]; ++f[a[i]]; } for (int(i) = 1; (i) <= (100000); ++(i)) { f[i] += f[i - 1]; } long long ans = 0; for (int p = 100000; p >= 1; --p) { vector<int> facs; for (int i = 1; i * i <= p; ++i) { if (p % i == 0) { facs.emplace_back(i); if (i * i != p) { facs.emplace_back(p / i); } } } sort(facs.begin(), facs.end()); long long tmp = 1, tmp2 = 1; for (size_t i = 0; i < facs.size(); ++i) { long long t = i == facs.size() - 1 ? n - f[facs[i] - 1] : f[facs[i + 1] - 1] - f[facs[i] - 1]; if (i == facs.size() - 1) { tmp2 = (tmp * ksm(i, t)) % MOD; } tmp = (tmp * ksm(i + 1, t)) % MOD; } Dec(tmp, tmp2); Add(ans, tmp); } cout << ans << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A222O_FUNCTIONAL_PP_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire B2 and2_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X , and1_out, and0_out, and2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_LP__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND4B_PP_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long n, k; priority_queue<pair<long long, pair<long long, long long>>> pq; long long divide(long long x, long long y) { if (x < y) return 1e16; long long t = x / y, rm = x % y; t += rm / y; rm %= y; return rm * (t + 1) * (t + 1) + (y - rm) * t * t; } void solve() { cin >> n >> k; long long ans = 0; k -= n; while (n--) { long long x; cin >> x; ans += x * x; pq.push({x * x - divide(x, 2), {x, 2}}); } while (k--) { auto x = pq.top(); pq.pop(); ans -= x.first; pq.push({divide(x.second.first, x.second.second) - divide(x.second.first, x.second.second + 1), {x.second.first, x.second.second + 1}}); } cout << ans << n ; } signed main() { ios::sync_with_stdio(0); cin.tie(0); solve(); } |
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1.0); long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } bool checkprime(long long n) { long long i = 2; while (i * i <= n) { if (n % i == 0) return 0; i++; } return 1; } long long fact(long long n) { if (n == 0) return 1; return n * fact(n - 1); } long long sod(long long n) { long long sum = 0; while (n) { sum += n % 10; n /= 10; } return sum; } vector<long long> v; long long bs(long long low, long long high, long long val) { long long mid = (low + high) / 2; if (low == high) return high; if (v[mid] >= val) return bs(low, mid, val); else return bs(mid + 1, high, val); } void lucky(long long n, long long cur, long long ct4, long long ct7, long long val) { if (n == cur) { if (ct4 == ct7) { v.push_back(val); } return; } lucky(n, cur + 1, ct4 + 1, ct7, val * 10 + 4); lucky(n, cur + 1, ct4, ct7 + 1, val * 10 + 7); } long long bs(long long a[], long long low, long long high, long long val) { long long mid = (low + high) / 2; if (low > high) return -1; if (a[mid] > val) return bs(a, low, mid - 1, val); else if (a[mid] < val) return bs(a, mid + 1, high, val); else return mid; } void DJ() { long long a, b; cin >> a >> b; if (b - a < 2) cout << -1; else if (b - a == 2 && a % 2) cout << -1; else { a += a % 2; cout << a << << a + 1 << << a + 2; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) DJ(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND2B_FUNCTIONAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:11:01 10/17/2016
// Design Name:
// Module Name: num_2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module num_2(
input [2:0] in_row,
output reg [4:0] out_code
);
parameter [4:0] d_0 = 5'b01110; // XXX
parameter [4:0] d_1 = 5'b10001; // X X
parameter [4:0] d_2 = 5'b01000; // X
parameter [4:0] d_3 = 5'b00100; // X
parameter [4:0] d_4 = 5'b00010; // X
parameter [4:0] d_5 = 5'b11111; // XXXXX
always @ *
begin
case (in_row)
3'b000:
out_code = d_0;
3'b001:
out_code = d_1;
3'b010:
out_code = d_2;
3'b011:
out_code = d_3;
3'b100:
out_code = d_4;
3'b101:
out_code = d_5;
default:
out_code = 5'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; long long mul[1005], c[1005][1005], f[1005][1005][2][3], chose[1005]; long long ans; int main() { scanf( %d%d , &n, &k); mul[0] = 1; for (int i = 1; i <= n; ++i) mul[i] = mul[i - 1] * (long long)i % 1000000007; for (int i = 0; i <= 1000; ++i) c[i][0] = 1; for (int i = 1; i <= 1000; ++i) for (int j = 1; j <= 1000; ++j) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % 1000000007; for (int i = 0; i <= n; ++i) f[i][0][1][0] = 1; for (int i = 1; i <= n; ++i) for (int j = 0; j <= i; ++j) { f[i][j][0][0] = f[i - 1][j][0][0] + f[i - 1][j][0][1] + f[i - 1][j][1][0] + f[i - 1][j][1][1]; f[i][j][0][0] %= 1000000007; if (j) f[i][j][0][1] = f[i - 1][j - 1][0][0] + f[i - 1][j - 1][0][1]; f[i][j][0][1] %= 1000000007; if (j) f[i][j][0][2] = f[i - 1][j - 1][0][0] + f[i - 1][j - 1][0][1] + f[i - 1][j - 1][1][0] + f[i - 1][j - 1][1][1]; f[i][j][0][2] %= 1000000007; f[i][j][1][0] = f[i - 1][j][0][2] + f[i - 1][j][1][2]; f[i][j][1][0] %= 1000000007; if (j) f[i][j][1][1] = f[i - 1][j - 1][0][2]; f[i][j][1][1] %= 1000000007; if (j) f[i][j][1][2] = f[i - 1][j - 1][0][2] + f[i - 1][j - 1][1][2]; f[i][j][1][2] %= 1000000007; } for (int i = 0; i <= n; ++i) { chose[i] = f[n][i][0][0] + f[n][i][0][1] + f[n][i][1][0] + f[n][i][1][1]; chose[i] %= 1000000007; } for (int i = k, opt = 1; i <= n; ++i, opt = -opt) { ans += chose[i] * mul[n - i] % 1000000007 * c[i][k] % 1000000007 * opt; ans = (ans % 1000000007 + 1000000007) % 1000000007; } printf( %I64d n , ans); } |
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sample_cycle_ratio
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_7_axic_sample_cycle_ratio # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg [P_DELAY-1:0] sample_cycle_d;
(* shreg_extract = "no" *) reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end
else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
end
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= sample_cycle_d[0];
end
assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule // axisc_sample_cycle_ratio
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { solve(); } void solve() { int t; cin >> t; while (t--) { string s; cin >> s; priority_queue<int> q; int k = s.length(); int cur = (s[0] == 1 ) ? 1 : 0; for (int i = 1; i < k; i++) { if (s[i] == 1 && s[i - 1] == 0 ) { cur = 1; } if (s[i] == 1 && s[i - 1] == 1 ) { cur++; } if (s[i] == 0 ) { if (cur != 0) { q.push(cur); cur = 0; } } } if (s[k - 1] == 1 ) { if (cur != 0) { q.push(cur); cur = 0; } } int ans = 0; int qs = q.size(); for (int i = 0; i < qs; i++) { if ((i & 0x1) == 0) { ans += q.top(); } else { } q.pop(); } cout << ans << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_BLACKBOX_V
`define SKY130_FD_SC_MS__O2111AI_BLACKBOX_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GROUND_LVC_WPAD_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_GROUND_LVC_WPAD_PP_BLACKBOX_V
/**
* top_ground_lvc_wpad: Base ground I/O pad with low voltage clamp.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_ground_lvc_wpad (
G_PAD ,
AMUXBUS_A ,
AMUXBUS_B ,
SRC_BDY_LVC1,
SRC_BDY_LVC2,
OGC_LVC ,
DRN_LVC1 ,
BDY2_B2B ,
DRN_LVC2 ,
G_CORE ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
inout G_PAD ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout SRC_BDY_LVC1;
inout SRC_BDY_LVC2;
inout OGC_LVC ;
inout DRN_LVC1 ;
inout BDY2_B2B ;
inout DRN_LVC2 ;
inout G_CORE ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GROUND_LVC_WPAD_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int MOD = 1e9 + 7; vector<string> vec_splitter(string s) { s += , ; vector<string> res; while (!s.empty()) { res.push_back(s.substr(0, s.find( , ))); s = s.substr(s.find( , ) + 1); } return res; } void debug_out(vector<string> __attribute__((unused)) args, __attribute__((unused)) int idx, __attribute__((unused)) int LINE_NUM) { cerr << n ; } template <typename Head, typename... Tail> void debug_out(vector<string> args, int idx, int LINE_NUM, Head H, Tail... T) { if (idx > 0) cerr << , ; else cerr << Line( << LINE_NUM << ) ; stringstream ss; ss << H; cerr << args[idx] << = << ss.str(); debug_out(args, idx + 1, LINE_NUM, T...); } void run() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } long long gcd(long long n1, long long n2) { if (n2 != 0) return gcd(n2, n1 % n2); else return n1; } bool checkPalindrome(string s) { int n = s.size(); for (int i = 0; i < n / 2; i++) { if (s[i] != s[n - i - 1]) return false; } return true; } long long digSum(long long n) { long long sum = 0; while (n > 0) { sum += n % 10; n /= 10; } return sum; } bool compare(pair<int, int> a, pair<int, int> b) { if (a.first == a.second) return true; else if (b.first == b.second) return false; else { int adiff = a.second - a.first; int bdiff = b.second - b.first; if (adiff > bdiff) return false; else return true; } } int main() { run(); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; vector<int> v(n + 1); for (int i = 1; i <= n; i++) { cin >> v[i]; } sort(v.begin(), v.end()); long long ans = 0; int ind = n - 2 * k; int half = ind + k; for (int i = 1; i <= ind; i++) { ans += v[i]; } for (int i = ind + 1; i <= half; i++) { ans = ans + (v[i] / v[i + k]); } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; pair<int, int> c = make_pair(1, 0); int dx = 1, cover = 0, inc = 0; while (k != 1) { if (inc == 0) cout << 2 << ; if (dx == 1 && c.second + dx <= m) { c.second += dx; } else if (dx == 1) { c.first++; dx = -1; } else if (dx == -1 && c.second + dx >= 1) { c.second += dx; } else if (dx == -1) { c.first++; dx = 1; } cout << c.first << << c.second << ; inc++; if (inc == 2) { cout << endl; k--; inc = 0; } cover++; } cout << n * m - cover << ; while (cover < n * m) { if (dx == 1 && c.second + dx <= m) { c.second += dx; } else if (dx == 1) { c.first++; dx = -1; } else if (dx == -1 && c.second + dx >= 1) { c.second += dx; } else if (dx == -1) { c.first++; dx = 1; } cout << c.first << << c.second << ; cover++; } cout << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_2_V
`define SKY130_FD_SC_HVL__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { char str1[10], str2[10], str3[10]; int flag1, flag2, flag3; flag1 = 0; flag2 = 0; flag3 = 0; cin >> str1 >> str2 >> str3; if (strcmp(str1, str2) == 0) { flag1 = 1; } else if (strcmp(str2, str3) == 0) { flag2 = 1; } else if (strcmp(str3, str1) == 0) { flag3 = 1; } if ((flag1 | flag2 | flag3) == 0) { cout << ? << endl; return 0; } if ((flag1 & flag2 & flag3) == 1) { cout << ? << endl; return 0; } if (flag1 == 1) { if (strcmp(str3, rock ) == 0) { if (strcmp(str2, scissors ) == 0) { cout << S << endl; return 0; } } if (strcmp(str3, scissors ) == 0) { if (strcmp(str2, paper ) == 0) { cout << S << endl; return 0; } } if (strcmp(str3, paper ) == 0) { if (strcmp(str2, rock ) == 0) { cout << S << endl; return 0; } } } if (flag2 == 1) { if (strcmp(str1, rock ) == 0) { if (strcmp(str2, scissors ) == 0) { cout << F << endl; return 0; } } if (strcmp(str1, scissors ) == 0) { if (strcmp(str2, paper ) == 0) { cout << F << endl; return 0; } } if (strcmp(str1, paper ) == 0) { if (strcmp(str2, rock ) == 0) { cout << F << endl; return 0; } } } if (flag3 == 1) { if (strcmp(str2, rock ) == 0) { if (strcmp(str3, scissors ) == 0) { cout << M << endl; return 0; } } if (strcmp(str2, scissors ) == 0) { if (strcmp(str3, paper ) == 0) { cout << M << endl; return 0; } } if (strcmp(str2, paper ) == 0) { if (strcmp(str3, rock ) == 0) { cout << M << endl; return 0; } } } cout << ? << endl; return 0; } |
#include <bits/stdc++.h> int main() { int t, arr[110], i, l, s, m, n, j; scanf( %d , &t); l = -1; s = 1001; for (i = 0; i < t; i++) scanf( %d , &arr[i]); for (i = 0; i < t; i++) { for (j = i + 1; j < t; j++) { if (arr[j] < arr[i]) { s = arr[j]; arr[j] = arr[i]; arr[i] = s; } } } printf( %d , arr[t - 1]); for (i = 1; i < t - 1; i++) { printf( %d , arr[i]); } printf( %d n , arr[0]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f, oo = inf; inline long long read() { register long long x = 0; char f = 0; register char c = getchar(); for (; !isdigit(c); c = getchar()) f |= (c == - ); for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); return f ? -x : x; } inline double readdb() { register double x = 0, p = 0.1; register char f = 0, c = getchar(); for (; !isdigit(c); c = getchar()) f |= (c == - ); for (; isdigit(c); c = getchar()) x = x * 10 + (c ^ 48); if (c == . ) for (c = getchar(); isdigit(c); c = getchar(), p /= 10) x = x + (c ^ 48) * p; return f ? -x : x; } inline void write(long long x) { if (x < 0) x = -x, putchar( - ); if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } inline void writeln(long long x) { write(x); puts( ); } inline void writeln(long long x, char c, long long y) { write(x); putchar(c); writeln(y); } inline void writeln(long long x, char c, long long y, char d, long long z) { write(x); putchar(c); write(y); putchar(d); writeln(z); } const int maxn = 3e5 + 233; const int maxm = 6e5 + 233; struct Edge { int to, nxt, dist; Edge() {} Edge(int to, int nxt, int dist) : to(to), nxt(nxt), dist(dist) {} } edge1[maxm], edge2[maxm]; int first1[maxn], first2[maxn]; int nume1, nume2; void Addedge1(int a, int b, int c) { edge1[nume1] = Edge(b, first1[a], c); first1[a] = nume1++; } int s[maxn], dfn[maxn], low[maxn], dfsclk = 0; bool Ins[maxn]; int bel[maxn]; int val[maxn], dist[maxn]; void Tarjan(int u, int fa) { dfn[u] = low[u] = ++dfsclk; Ins[u] = true; s[++*s] = u; for (int e = first1[u]; ~e; e = edge1[e].nxt) { int v = edge1[e].to; if (v == fa) continue; if (!dfn[v]) { Tarjan(v, u); low[u] = min(low[u], low[v]); } else if (Ins[v]) { low[u] = min(low[u], dfn[v]); } } if (dfn[u] == low[u]) { bel[0]++; for (;;) { int v = s[s[0]--]; Ins[v] = false; bel[v] = *bel; if (u == v) break; } } } void Addedge2(int a, int b, int c) { edge2[nume2] = Edge(b, first2[a], c); first2[a] = nume2++; } void rebuild() { memset(val, false, sizeof(val)); for (int i = 0; i < nume1; i += 2) { int u = bel[edge1[i ^ 1].to]; int v = bel[edge1[i].to]; int w = edge1[i].dist; if (u != v) { Addedge2(u, v, w); Addedge2(v, u, w); } else if (w) { val[u] = true; } } } int front, rear, q[maxn]; void BFS(int S, int T) { memset(dist, -1, sizeof(dist)); front = rear = 0; q[rear++] = S; dist[S] = val[S]; while (front < rear) { int u = q[front++]; for (int e = first2[u]; ~e; e = edge2[e].nxt) { int v = edge2[e].to; if (dist[v] == -1) { dist[v] = dist[u] | edge2[e].dist | val[v]; q[rear++] = v; } } } if (dist[T]) { puts( YES ); } else { puts( NO ); } } int n, m; int main() { n = read(), m = read(); memset(first1, -1, sizeof(first1)); nume1 = 0; memset(first2, -1, sizeof(first2)); nume2 = 0; for (register int i = (1); i <= (m); ++i) { int a = read(), b = read(), c = read(); Addedge1(a, b, c); Addedge1(b, a, c); } memset(dfn, 0, sizeof(dfn)); *bel = 0; Tarjan(1, 0); rebuild(); int s = read(), t = read(); BFS(bel[s], bel[t]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long t, s, a, b, c; cin >> t; for (int i = 0; i < t; i++) { cin >> s >> a >> b >> c; cout << s / c + ((s / c) / a) * b << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:60000000 ) using namespace std; const long double eps = 1e-9; const int inf = (1 << 30) - 1; const long long inf64 = ((long long)1 << 62) - 1; const long double pi = 3.1415926535897932384626433832795; const string task = ; template <class T> T sqr(T x) { return x * x; } int n, m; int a[100500]; int last[100500]; char ans[100500]; int x[100500], y[100500]; void solve() { scanf( %d%d , &n, &m); for (int i = 0; i < (int)(m); i++) { scanf( %d , &a[i]); ans[i] = N ; last[i] = -1; } for (int i = 0; i < (int)(n - 1); i++) { scanf( %d%d , &x[i], &y[i]); x[i]--; if (x[i] >= 0) last[x[i]] = i; } int s = 0; bool first = 1; for (int i = 0; i < (int)(n - 1); i++) { if (first && y[i] == 1) { first = 0; int mn = inf; for (int j = 0; j < (int)(m); j++) if (a[j] <= s && last[j] < i) { ans[j] = Y ; mn = min(mn, a[j]); } s -= mn; } if (x[i] != -1) { a[x[i]]--; } else { s++; } } cerr << s << endl; for (int i = 0; i < (int)(m); i++) if (a[i] <= s) ans[i] = Y ; for (int i = 0; i < (int)(m); i++) { printf( %c , ans[i]); } printf( n ); } int main() { int tt; scanf( %d , &tt); for (int ii = 0; ii < (int)(tt); ii++) solve(); return 0; } |
`include "defines.v"
module div(
input wire clk,
input wire rst,
input wire signed_div_i,
input wire[31:0] opdata1_i,
input wire[31:0] opdata2_i,
input wire start_i,
input wire annul_i,
output reg[63:0] result_o,
output reg ready_o
);
wire[32:0] div_temp;
reg[5:0] cnt;
reg[64:0] dividend;
reg[1:0] state;
reg[31:0] divisor;
reg[31:0] temp_op1;
reg[31:0] temp_op2;
assign div_temp = {1'b0,dividend[63:32]} - {1'b0,divisor};
always @ (posedge clk) begin
if (rst == `RstEnable) begin
state <= `DivFree;
ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord,`ZeroWord};
end else begin
case (state)
`DivFree: begin //DivFree״̬
if(start_i == `DivStart && annul_i == 1'b0) begin
if(opdata2_i == `ZeroWord) begin
state <= `DivByZero;
end else begin
state <= `DivOn;
cnt <= 6'b000000;
if(signed_div_i == 1'b1 && opdata1_i[31] == 1'b1 ) begin
temp_op1 = ~opdata1_i + 1;
end else begin
temp_op1 = opdata1_i;
end
if(signed_div_i == 1'b1 && opdata2_i[31] == 1'b1 ) begin
temp_op2 = ~opdata2_i + 1;
end else begin
temp_op2 = opdata2_i;
end
dividend <= {`ZeroWord,`ZeroWord};
dividend[32:1] <= temp_op1;
divisor <= temp_op2;
end
end else begin
ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord,`ZeroWord};
end
end
`DivByZero: begin //DivByZero״̬
dividend <= {`ZeroWord,`ZeroWord};
state <= `DivEnd;
end
`DivOn: begin //DivOn״̬
if(annul_i == 1'b0) begin
if(cnt != 6'b100000) begin
if(div_temp[32] == 1'b1) begin
dividend <= {dividend[63:0] , 1'b0};
end else begin
dividend <= {div_temp[31:0] , dividend[31:0] , 1'b1};
end
cnt <= cnt + 1;
end else begin
if((signed_div_i == 1'b1) && ((opdata1_i[31] ^ opdata2_i[31]) == 1'b1)) begin
dividend[31:0] <= (~dividend[31:0] + 1);
end
if((signed_div_i == 1'b1) && ((opdata1_i[31] ^ dividend[64]) == 1'b1)) begin
dividend[64:33] <= (~dividend[64:33] + 1);
end
state <= `DivEnd;
cnt <= 6'b000000;
end
end else begin
state <= `DivFree;
end
end
`DivEnd: begin //DivEnd״̬
result_o <= {dividend[64:33], dividend[31:0]};
ready_o <= `DivResultReady;
if(start_i == `DivStop) begin
state <= `DivFree;
ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord,`ZeroWord};
end
end
endcase
end
end
endmodule |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Intel FPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board.
// Input buffer map
module \$__inpad (input I, output O);
cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //
|
#include <bits/stdc++.h> using namespace std; int n; int x[100000]; int dist(int a, int b) { return abs(a - b); } int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> x[i]; cout << dist(x[0], x[1]) << << dist(x[0], x[n - 1]) << endl; for (int i = 1; i < n - 1; i++) cout << min(dist(x[i], x[i - 1]), dist(x[i], x[i + 1])) << << max(dist(x[i], x[0]), dist(x[i], x[n - 1])) << endl; cout << dist(x[n - 1], x[n - 2]) << << dist(x[0], x[n - 1]) << endl; return 0; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// iitram9bx1k.v:
// Indirectly-indexed transposed-RAM of 9-bits patterns and 1K addresses //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module iitram9bx1k
#( parameter PIPE = 1 ) // pipelined?
( input clk , // clock
input rst , // global registers reset
input wEnb_iVld , // write enable / indicator valid
input wEnb_indx , // write enable / indicator index
input wEnb_indc , // write enable / full indicators (MLABs)
input [8 :0] mPatt , // match pattern
input [8 :0] wPatt , // write pattern
input [4 :0] wAddr_indx, // write address / index
input [4 :0] wAddr_indc, // write address / indicator (in index range)
input [4 :0] wIndx , // write index
input wIVld , // write indicator validity
input [31 :0] wIndc , // write indicator (full)
output [1023:0] mIndc ); // match indicators
// instantiate M20K
wire [31:0] iVld;
mwm20k #( .WWID (1 ), // write width
.RWID (32 ), // read width
.WDEP (16384 ), // write lines depth
.OREG (1 ), // read output reg
.INIT (1 )) // initialize to zeros
ivldram ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnb_iVld ), // write enable // input
.wAddr ({wPatt,wAddr_indx[4:0]}), // write address // input [`log2(WDEP)-1 :0]
.wData (wIVld ), // write data // input [WWID-1 :0]
.rAddr (mPatt ), // read address // input [`log2(WDEP/(RWID/WWID))-1:0]
.rData (iVld )); // read data // output [RWID-1 :0]
wire [39:0] indx [3:0];
wire [1023:0] indc;
genvar gi,gj;
generate
for (gi=0 ; gi<4 ; gi=gi+1) begin: STG
// instantiate M20K
mwm20k #( .WWID (5 ), // write width
.RWID (40 ), // read width
.WDEP (4096 ), // write lines depth
.OREG (0 ), // read output reg
.INIT (1 )) // initialize to zeros
indxram ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnb_indx && (wAddr_indx[4:3]==gi)), // write enable // input
.wAddr ({wPatt,wAddr_indx[2:0]} ), // write address // input [`log2(WDEP)-1 :0]
.wData (wIndx ), // write data // input [WWID-1 :0]
.rAddr (mPatt ), // read address // input [`log2(WDEP/(RWID/WWID))-1:0]
.rData (indx[gi] )); // read data // output [RWID-1 :0]
for (gj=0 ; gj<8 ; gj=gj+1) begin: STG
// instantiate MLAB
dpmlab #( .DWID (32 ), // data width
.DDEP (32 ), // data depth
.MRDW ("DONT_CARE" ), // mixed ports read during write mode ("NEW_DATA", "OLD_DATA", or "DONT_CARE")
.RREG (PIPE ? "ALL" : "ADDR" ), // read port registe: "ADDR" for address, "ROUT", for read output, "ALL" for both.
.INIT (1 )) // initialize to zeros
indcram ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnb_indc && (wAddr_indx[4:3]==gi) && (wAddr_indx[2:0]==gj)), // write enable // input
.wAddr (wAddr_indc ), // write address // input [`log2(DEP)-1:0]
.wData (wIndc ), // write data // input [WID-1 :0]
.rAddr (indx[gi][gj*5 +: 5] ), // read address // input [`log2(DEP)-1:0]
.rData (indc[(gi*256+gj*32) +: 32] )); // read data // output [WID-1 :0]
assign mIndc[(gi*256+gj*32) +: 32] = indc[(gi*256+gj*32) +: 32] & {32{iVld[8*gi+gj]}};
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; string express(int layers) { string ans = ; for (int i = 1; i <= layers; i++) { if (i % 2 == 1) { if (i == layers) { ans += I hate it ; } else { ans += I hate that ; } } else { if (i == layers) { ans += I love it ; } else { ans += I love that ; } } } return ans; } int main() { int layers; cin >> layers; cout << express(layers); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc = 0;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 10) begin
$strobe("[%0t] cyc=%0d", $time, cyc);
$strobe("[%0t] cyc=%0d also", $time, cyc);
end
else if (cyc == 17) begin
$strobeb(cyc, "b");
end
else if (cyc == 18) begin
$strobeh(cyc, "h");
end
else if (cyc == 19) begin
$strobeo(cyc, "o");
end
else if (cyc == 22) begin
$strobe("[%0t] cyc=%0d new-strobe", $time, cyc);
end
else if (cyc == 24) begin
$monitoroff;
end
else if (cyc == 26) begin
$monitoron;
end
else if (cyc == 30) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (1 << 20) + 69; int heap[N], idx[N], val[N]; int g, h; void dream(int curr) { while (curr < ((1 << (h - 1)) - 1) && heap[curr] > min(heap[2 * curr + 1], heap[2 * curr + 2])) { int& left = heap[2 * curr + 1]; int& right = heap[2 * curr + 2]; if (left < right) { swap(left, heap[curr]); curr = 2 * curr + 1; } else { swap(right, heap[curr]); curr = 2 * curr + 2; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; scanf( %d , &t); for (int i = 0; i < t; i++) { scanf( %d %d , &h, &g); set<int> remain; for (int j = 0; j < (1 << h) - 1; j++) { scanf( %d , &heap[j]); remain.insert(heap[j]); idx[heap[j]] = j; } for (int j = (1 << h) - 2; j >= (1 << g) - 1; j--) dream(j); for (int j = (1 << (g - 1)) - 1; j < (1 << g) - 1; j++) { val[j] = min(heap[2 * j + 1], heap[2 * j + 2]); dream(j); } for (int j = (1 << (g - 1)) - 2; j >= 0; j--) { int lbound = max(val[2 * j + 1], val[2 * j + 2]); while (heap[2 * j + 1] <= lbound) { heap[2 * j + 1] = INT_MAX; dream(2 * j + 1); } while (heap[2 * j + 2] <= lbound) { heap[2 * j + 2] = INT_MAX; dream(2 * j + 2); } val[j] = min(heap[2 * j + 1], heap[2 * j + 2]); dream(j); } long long ans1 = 0; for (int j = 0; j < (1 << g) - 1; j++) { ans1 += val[j]; remain.erase(val[j]); } printf( %I64d n , ans1); for (auto v : remain) printf( %d , idx[v] + 1); printf( n ); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long solve(int N, const vector<int>& A) { long long res = 0; vector<int> freq(32); for (int x : A) { int hsb = (sizeof(int) * 8 - 1 - __builtin_clz((x))); res += freq[hsb]; ++freq[hsb]; } return res; } int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(nullptr); int TC; cin >> TC; for (int tc = (1), _b = (TC); tc <= _b; ++tc) { int N; cin >> N; vector<int> A(N); for (int i = 0, _n = (N); i < _n; ++i) cin >> A[i]; long long res = solve(N, A); cout << res << n ; } return 0; } |
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 13: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 13: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 24: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 6: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[13 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[24 : 22]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[21 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "setup.v"
module ddram #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_clk_n,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* FML 4x64 interface */
input [`SDRAM_DEPTH-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_eack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
/* DDRAM pads */
output sdram_clk_p,
output sdram_clk_n,
output sdram_cke,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [12:0] sdram_adr,
output [1:0] sdram_ba,
output [3:0] sdram_dm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) clock_forward_p (
.Q(sdram_clk_p),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0)
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) clock_forward_n (
.Q(sdram_clk_n),
.C0(sys_clk),
.C1(sys_clk_n),
.CE(1'b1),
.D0(1'b0),
.D1(1'b1),
.R(1'b0),
.S(1'b0)
);
hpdmc #(
.csr_addr(csr_addr),
.sdram_depth(`SDRAM_DEPTH),
.sdram_columndepth(`SDRAM_COLUMNDEPTH)
) hpdmc (
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_eack(fml_eack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dm(sdram_dm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int k, a, b; cin >> k >> a >> b; string s; cin >> s; int l = s.length(); double c = (double)l / k; int c1 = floor(c); int c2 = ceil(c); int flag1 = 0, flag2 = 0; if ((l - (c1 * (k - 1))) > b || (l - (c1 * (k - 1))) < a) { flag1 = 1; } if ((l - (c2 * (k - 1))) > b || (l - (c2 * (k - 1))) < a) { flag2 = 1; } if ((flag1 == 1 || c1 < a || c1 > b) && (flag2 == 1 || c2 < a || c2 > b)) { cout << No solution ; return; } if (flag1 == 0) { int i1 = 0; int kk = 0; while (i1 <= l) { kk++; for (long long int i = i1; i < min(i1 + c1, l); i++) { cout << s[i]; } i1 += c1; if (kk == k) { for (long long int i = i1; i < l; i++) { cout << s[i]; } return; } printf( n ); } } else { int i1 = 0; int kk = 0; while (i1 <= l) { kk++; for (long long int i = i1; i < min(i1 + c2, l); i++) { cout << s[i]; } i1 += c2; if (kk == k) { for (long long int i = i1; i < l; i++) { cout << s[i]; } } printf( n ); } } } int main() { solve(); } |
#include <bits/stdc++.h> using namespace std; int mat[(int)1e3][(int)1e3], n; int dp2[(int)1e3][(int)1e3]; int dp5[(int)1e3][(int)1e3]; int changeRow[] = {1, 0}; int changeCol[] = {0, 1}; int pw2[(int)1e3][(int)1e3], pw5[(int)1e3][(int)1e3]; string dir[] = { D , R }; int pwr(int n, int k) { int ret = 0; while (n >= k and n % k == 0) { ret++; n /= k; } return ret; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int x = 0; x < n; x++) for (int y = 0; y < n; y++) cin >> mat[x][y]; bool hasZero = 0; pair<int, int> pos; for (int x = 0; x < n; x++) { for (int y = 0; y < n; y++) { if (mat[x][y] == 0) { pos = make_pair(x, y); hasZero = true; break; } } if (hasZero) break; } for (int x = 0; x < n; x++) { for (int y = 0; y < n; y++) { pw2[x][y] = pwr(mat[x][y], 2); pw5[x][y] = pwr(mat[x][y], 5); } } for (int x = 0; x < n; x++) { for (int y = 0; y < n; y++) { dp2[x][y] = 2e9; dp5[x][y] = 2e9; } } dp2[0][0] = pw2[0][0]; for (int x = 0; x < n; x++) { for (int y = 0; y < n; y++) { for (int z = 0; z < 2; z++) { int X = x + changeRow[z]; int Y = y + changeCol[z]; if (X == x and Y == y) continue; if (X >= 0 and Y >= 0 and X < n and Y < n) { dp2[X][Y] = min(dp2[X][Y], pw2[X][Y] + dp2[x][y]); } } } } dp5[0][0] = pw5[0][0]; for (int x = 0; x < n; x++) { for (int y = 0; y < n; y++) { for (int z = 0; z < 2; z++) { int X = x + changeRow[z]; int Y = y + changeCol[z]; if (X == x and Y == y) continue; if (X >= 0 and Y >= 0 and X < n and Y < n) { dp5[X][Y] = min(dp5[X][Y], pw5[X][Y] + dp5[x][y]); } } } } int res2 = dp2[n - 1][n - 1]; int res5 = dp5[n - 1][n - 1]; int res = min(res2, res5); string ans = ; if (hasZero && res > 1) { cout << 1 n ; for (int x = 0; x < pos.first; x++) cout << D ; for (int x = 0; x < pos.second; x++) cout << R ; for (int x = pos.first; x < n - 1; x++) cout << D ; for (int x = pos.second; x < n - 1; x++) cout << R ; } else if (res == res2) { cout << res << n ; int i = n - 1, j = n - 1; while (!(i == 0 and j == 0)) { for (int z = 0; z < 2; z++) { int X = i - changeRow[z]; int Y = j - changeCol[z]; if (X == i and Y == j) continue; if (X >= 0 and Y >= 0 and X < n and Y < n) { if (dp2[i][j] == dp2[X][Y] + pw2[i][j]) { ans += dir[z]; i = X; j = Y; break; } } } } assert(i == 0 and j == 0); reverse(ans.begin(), ans.end()); for (auto x : ans) cout << x; cout << n ; } else { cout << res << n ; assert(res == res5); int i = n - 1, j = n - 1; while (!(i == 0 and j == 0)) { for (int z = 0; z < 2; z++) { int X = i - changeRow[z]; int Y = j - changeCol[z]; if (X == i and Y == j) continue; if (X >= 0 and Y >= 0 and X < n and Y < n) { if (dp5[i][j] == dp5[X][Y] + pw5[i][j]) { ans += dir[z]; i = X; j = Y; break; } } } } assert(i == 0 and j == 0); reverse(ans.begin(), ans.end()); for (auto x : ans) cout << x; cout << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKINVLP_PP_BLACKBOX_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j; scanf( %d , &n); int arr[n]; for (i = 0; i < n; i++) scanf( %d , &arr[i]); int t = 0; int index = -1; for (i = 0; i < n; i++) if (arr[i] - arr[(i + 1) % n] > 0) { t++; index = i; } if (t > 1) { cout << -1 n ; return 0; } if (index == -1) cout << 0 n ; else cout << (n - index - 1) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mxn = 1e6 + 6; int n, r, c, t = 1, fr[mxn], nxt[mxn], ans[mxn]; char s[6 * mxn]; inline void dfs(int x) { if (!x) return; dfs(x >> 1); for (int i = 1; i <= n; ++i) { ans[i] = ans[ans[i]]; if (x & 1) ans[i] = nxt[ans[i]]; } } int main() { scanf( %d%d%d , &n, &r, &c); for (int i = 1; i <= n; ++i) { scanf( %s , s + fr[i]); fr[i + 1] = fr[i] + strlen(s + fr[i]); s[fr[i + 1]++] = ; } for (int i = n + 1, j = n + 1; i; nxt[ans[i] = i] = j, --i) for (; fr[j] - fr[i] > c + 1; --j) ; dfs(r); for (int i = 2; i <= n; ++i) if (ans[i] - i > ans[t] - t) t = i; for (int i = 1; i <= r; ++i, t = nxt[t], putchar( n )) for (int j = fr[t]; j + 1 < fr[nxt[t]]; j++) putchar(s[j]); } |
#include <bits/stdc++.h> using namespace std; int n, ans = 0; long long int mn = int(1e9); vector<int> c, d; vector<vector<pair<int, int>>> g; void dfs(int u, int p = 1) { d[u] = 1; for (auto v : g[u]) if (v.first != p) { dfs(v.first, u); d[u] += d[v.first]; } return; } void dfs1(int u, int p = 1, long long int dist = 0) { if (dist > c[u]) { ans += d[u]; return; } for (auto v : g[u]) if (v.first != p) dfs1(v.first, u, max(0LL, dist + v.second)); } void solve() { dfs(1); dfs1(1); cout << ans << n ; return; } void inp() { cin >> n; c.resize(n + 1), g.resize(n + 1), d.resize(n + 1); for (int i = 1; i < n + 1; i++) cin >> c[i]; for (int i = 1; i < n; i++) { int p, w; cin >> p >> w; g[i + 1].push_back(make_pair(p, w)); g[p].push_back(make_pair(i + 1, w)); } return; } int main() { clock_t beg = clock(); { cin.tie(0); ios_base::sync_with_stdio(false); }; inp(); solve(); clock_t end = clock(); fprintf(stderr, %.3f sec n , (double)(end - beg) / CLOCKS_PER_SEC); return 0; } |
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 400005; template <typename T> void cmin(T &x, const T &y) { if (y < x) x = y; } template <typename T> void cmax(T &x, const T &y) { if (y > x) x = y; } template <typename T> void read(T &x) { x = 0; char c = getchar(); bool f = 0; while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = 1, c = getchar(); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); if (f) x = -x; } int fst[MX], nxt[MX], v[MX], lnum; int ida[MX], idb[MX], on_path[MX]; int n; void addeg(int nu, int nv) { nxt[++lnum] = fst[nu]; fst[nu] = lnum; v[lnum] = nv; } void input() { read(n); for (int i = 1; i <= n; i++) read(ida[i]); for (int i = 1; i <= n; i++) read(idb[i]); for (int i = 1; i < n; i++) { int a, b; read(a), read(b); addeg(a, b); addeg(b, a); } } int dep[MX], fa[MX], usd_mov; void dfs1(int x, int f, int tar) { dep[x] = dep[f] + 1, fa[x] = f; if (x == tar) { int tmp = x; on_path[x] = 1; while (fa[tmp]) swap(ida[tmp], ida[fa[tmp]]), tmp = fa[tmp], on_path[tmp] = 1, usd_mov++; } for (int i = fst[x]; i; i = nxt[i]) { int y = v[i]; if (v[i] != f) dfs1(v[i], x, tar); } } void fuck_out(char *s) { cerr << s << endl; puts( -1 ); exit(0); } int posa[MX], posb[MX], on_cyc[MX]; void work() { int frm = 0, tar = 0; for (int i = 1; i <= n; i++) if (!ida[i]) frm = i; for (int i = 1; i <= n; i++) if (!idb[i]) tar = i; dfs1(tar, 0, frm); for (int i = 1; i <= n; i++) posa[ida[i]] = i, posb[idb[i]] = i; for (int i = 1; i <= n; i++) if (ida[i] != idb[i]) on_cyc[i] = 1; int bot1 = 0, bot2 = 0; static int vis[MX]; vector<int> cyc; for (int i = 1; i <= n; i++) if (on_cyc[i] && dep[i] > dep[bot1]) bot1 = i; for (int x = bot1; on_cyc[x]; x = fa[x]) cyc.push_back(x), vis[x] = 1; reverse(cyc.begin(), cyc.end()); if (!bot1) { printf( %d %d n , 0, usd_mov); return; } for (int i = 1; i <= n; i++) if (on_cyc[i] && dep[i] > dep[bot2] && !vis[i]) bot2 = i; for (int x = bot2; on_cyc[x]; x = fa[x]) cyc.push_back(x), vis[x] = -1; int top1 = *cyc.begin(), top2 = *cyc.rbegin(), entry = fa[top1]; if (bot2 && fa[top1] != fa[top2]) fuck_out( unconnected loop! ); for (int i = 1; i <= n; i++) if (on_cyc[i] && !vis[i]) fuck_out( not a single loop! ); int step = 0, revs = 0; for (int i = 0; i < cyc.size(); i++) if (idb[cyc[i]] == ida[cyc[0]]) step = i; for (int i = 0; i < cyc.size(); i++) if (idb[cyc[(i + step) % cyc.size()]] != ida[cyc[i]]) fuck_out( can t rearrange loop! ); for (int x = frm; x; x = fa[x]) revs += vis[x]; long long way1 = usd_mov + 1ll * step * (cyc.size() + 1); long long way2 = usd_mov + 1ll * (cyc.size() - step) * (cyc.size() + 1); if (revs > 0) way2 -= revs * 2; else way1 += revs * 2; long long ans = min(way1, way2); int adda = 0, addb = 0; if (bot1 && bot2) adda = bot1, addb = bot2; else adda = bot1, addb = entry; for (int x = entry; !on_path[x]; x = fa[x]) ans += 2; if (adda > addb) swap(adda, addb); printf( %d %d %lld n , adda, addb, ans); } int main() { input(); work(); return 0; } |
#include <bits/stdc++.h> using namespace std; int rec[2][8]; int pattern[2][5500]; int n1, n2, z; int modpow(int n, int ex) { int res = 1; while (ex > 0) { if (ex % 2 == 1) res = (res * n) % 1000000007; n = (n * n) % 1000000007; ex = ex / 2; } return res; } void solve(int i) { if (i == (n1 + n2)) { int num = 0; for (int j = (0); j < (n1); j++) { num = num + (modpow(10, j)) * rec[0][j]; } pattern[0][z] = num; num = 0; for (int j = (n1); j < (i); j++) { num = num + (modpow(10, j - n1)) * rec[0][j]; } pattern[1][z] = num; z++; return; } for (int j = (0); j < (7); j++) { if (!rec[1][j]) { rec[1][j] = 1; rec[0][i] = j; solve(i + 1); rec[1][j] = 0; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m, a = 0, b = 0, ten = 1, ans = 0; cin >> n >> m; int temp = n - 1; while (temp) { a += ten * (temp % 7); ten *= 10; temp /= 7; n1++; } ten = 1; temp = m - 1; while (temp) { b += ten * (temp % 7); ten *= 10; temp /= 7; n2++; } if (n1 == 0) n1 = 1; if (n2 == 0) n2 = 1; solve(0); if (n1 + n2 > 7) { cout << 0 << endl; } else { for (int i = (0); i < (z); i++) { if (pattern[0][i] <= a && pattern[1][i] <= b) { ans++; } } cout << ans << endl; } } |
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module mig_7series_v2_3_round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 0 ), ch = getchar(); return x; } const int N = 1e7 + 5; const long long mod = 998244353; int ksm(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = 1ll * ans * a % mod; a = 1ll * a * a % mod; b >>= 1; } return ans; } int prime[N], kth[N], cnt; bool is_not_prime[N]; void sieve(int n, int k) { is_not_prime[0] = is_not_prime[1] = 1; kth[1] = 1; for (int i = 2; i <= n; i++) { if (!is_not_prime[i]) prime[++cnt] = i, kth[i] = ksm(i, k); for (int j = 1; j <= cnt && 1ll * prime[j] * i <= n; j++) { if (i % prime[j] == 0) break; prime[i * prime[j]] = 1; kth[i * prime[j]] = 1ll * kth[i] * kth[prime[j]] % mod; } } } int inv[N]; void preinv(int n) { inv[1] = 1; for (int i = 2; i <= n; i++) inv[i] = 1ll * inv[mod % i] * (mod - mod / i) % mod; } long long n, m, k, p, q, ivq, ivp; int S[N]; int main() { n = read(), m = read(), k = read(); sieve(k, k); p = ksm(m, mod - 2), q = (1 - p + mod) % mod, ivq = ksm(q, mod - 2), ivp = ksm(p, mod - 2); preinv(k); if (m == 1) printf( %d n , ksm(n, k)); else if (n <= k) { long long ans = 0; for (int i = 0, xs1 = 1, xs2 = ksm(q, n), xs3 = 1, xs4 = 1; i <= n; i++, xs1 = 1ll * xs1 * p % mod, xs2 = 1ll * xs2 * ivq % mod, xs3 = 1ll * xs3 * (n - i + 1) % mod, xs4 = 1ll * xs4 * inv[i] % mod) ans = (ans + 1ll * xs3 * xs4 % mod * kth[i] % mod * xs1 % mod * xs2 % mod) % mod; cout << ans; } else { S[k] = 1; for (int i = k - 1, xs1 = mod - p, xs2 = 1ll * (n - i - 1) * inv[k - i] % mod; i >= 0; i--, xs1 = 1ll * xs1 * (mod - p) % mod, xs2 = 1ll * xs2 * (n - i - 1) % mod * inv[k - i] % mod) S[i] = (1ll * S[i + 1] * (1 - p + mod) % mod + 1ll * xs2 * xs1 % mod) % mod; long long ans = 0; for (int i = 0, xs1 = 1, xs2 = 1; i <= k; i++, xs1 = 1ll * xs1 * (n - i + 1) % mod * inv[i] % mod, xs2 = 1ll * xs2 * p % mod) ans = (ans + 1ll * kth[i] * xs1 % mod * S[i] % mod * xs2 % mod) % mod; cout << ans; } return 0; } |
module ExampMain
#(parameter P)
(input i, output o, inout io);
endmodule
module ExampStub (/*AUTOARG*/
// Outputs
o,
// Inouts
io,
// Inputs
i
);
/*AUTOINOUTPARAM("ExampMain")*/
// Beginning of automatic parameters (from specific module)
parameter P;
// End of automatics
/*AUTOINOUTMODULE("ExampMain")*/
// Beginning of automatic in/out/inouts (from specific module)
output o;
inout io;
input i;
// End of automatics
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o = 1'h0;
// End of automatics
// verilator lint_off UNUSED
wire _unused_ok = &{1'b0,
/*AUTOUNUSED*/
// Beginning of automatic unused inputs
i,
io,
// End of automatics
1'b0};
// verilator lint_on UNUSED
endmodule
// Local Variables:
// indent-tabs-mode: nil
// End:
|
#include <bits/stdc++.h> using namespace std; long long calc(long long n, long long k) { long long a = 1, b = 1, c; for (long long i = 1; i <= k; i++) a = a * (n - i + 1), b = b * i; if (k == 4) c = 9; else if (k == 3) c = 2; else if (k == 2) c = 1; else c = 0; return c * a / b; } int main() { long long n, k; cin >> n >> k; long long res = 0; while (k) res += calc(n, k--); cout << res + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; const long long N = 2e5 + 1; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; vector<long long> nums(n); for (long long i = 0; i < n; i++) { long long k; cin >> k; nums[i] = abs(k); } sort(nums.begin(), nums.end()); long long ans = 0; for (long long i = 0; i < n; i++) { long long cur = nums[i]; long long ub = cur * 2; if (ub == 0) { continue; } long long low = i + 1; long long high = n - 1; long long pos = -1; while (low <= high) { long long mid = low + (high - low) / 2; if (nums[mid] <= ub) { pos = mid; low = mid + 1; } else { high = mid - 1; } } if (pos != -1) { ans += (pos - i); } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int n, num[105], ans = 0, i; int main() { scanf( %d , &n); for (int j = 1; j <= n; ++j) scanf( %d , &num[j]); if (n % 2 == 0 || n < 3) { printf( -1 n ); return 0; } for (int i = n; i >= 3; i -= 2) { int max_n = max(num[i], num[i - 1]); if (max_n <= 0) continue; ans += max_n; num[i] -= max_n; num[i - 1] -= max_n; num[(i - 1) / 2] -= max_n; } if (num[1] > 0) ans += num[1]; printf( %d n , ans); } |
`include "defines.v"
`timescale 1ns/1ps
module tb(
input `control_w port0_ci,
input `data_w port0_di,
output `control_w port0_co,
output `data_w port0_do,
input `control_w port1_ci,
input `data_w port1_di,
output `control_w port1_co,
output `data_w port1_do,
input `control_w port2_ci,
input `data_w port2_di,
output `control_w port2_co,
output `data_w port2_do,
input `control_w port3_ci,
input `data_w port3_di,
output `control_w port3_co,
output `data_w port3_do,
input `control_w port4_ci,
input `data_w port4_di,
output `control_w port4_co,
output `data_w port4_do
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `data_w flit0d;
reg `control_w flit1c;
reg `data_w flit1d;
reg `control_w flit2c;
reg `data_w flit2d;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.port2_ci(flit2c), .port2_co(port2_co),
.port3_ci(port3_ci), .port3_co(port3_co),
.port4_ci(port4_ci), .port4_co(port4_co),
.port0_di(flit0d), .port0_do(port0_do),
.port1_di(flit1d), .port1_do(port1_do),
.port2_di(flit2d), .port2_do(port2_do),
.port3_di(port3_di), .port3_do(port3_do),
.port4_di(port4_di), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
clk = 0;
rst = 0;
flit0c = 22'h200001;
flit0d = 128'h0123456789abcdef0123456789abcdef;
flit1c = 22'h200802;
flit1d = 128'h0123456789abcdef0123456789abcdef;
flit2c = 22'h200c03;
flit2d = 128'h0123456789abcdef0123456789abcdef;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 22'h0;
flit0d = 128'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int maxN = (int)3e5, maxM = (int)2e3, intMax = INT_MAX, maxValue = (int)1e4, intInf = (int)1e9, mod = (int)1e9 + 7, www = 97; const long long llmax = LLONG_MAX, INF = (long long)1e9 + 1; long long nod(long long a, long long b) { while (a != 0 && b != 0) { if (a < b) b %= a; else a %= b; } return a + b; } int nod(int a, int b) { while (a != 0 && b != 0) { if (a < b) b %= a; else a %= b; } return a + b; } long long nok(long long a, long long b) { return a * b / nod(a, b); } int nok(int a, int b) { return a * b / nod(a, b); } long long modPlus(long long a, long long b) { return ((a % mod) + (b % mod)) % mod; } int modPlus(int a, int b) { return ((a % mod) + (b % mod)) % mod; } long long binPow(long long a, long long b) { long long res = 1; while (b) { if (b % 2 == 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } double binPow(double a, long long b) { double res = 1; while (b) { if (b % 2 == 1) { res *= a; while (res >= mod) res -= mod; } a *= a; while (a >= mod) a -= mod; b >>= 1; } return res; } long long mulmod(long long a, long long b) { long long res = 0; a = a % mod; while (b > 0) { if (b % 2 == 1) res = (res + a) % mod; a = (a * 2) % mod; b /= 2; } return res % mod; } pair<int, int> max(pair<int, int> a, pair<int, int> b) { if (a.first > b.first) return a; if (a.first < b.first) return b; if (a.second > b.second) return a; return b; } pair<int, int> min(pair<int, int> a, pair<int, int> b) { if (a.first < b.first) return a; if (a.first != b.first) return b; if (a.second < b.second) return a; return b; } int n, k, Q[4][maxN]; vector<tuple<int, int, int> > res; int main() { scanf( %d%d , &n, &k); int x = -1, y = -1; int count = 0; for (int i = 0; i < 4; ++i) { for (int j = 0; j < n; ++j) { scanf( %d , &Q[i][j]); if (i && i < 3) { if (Q[i][j]) count++; else { x = j; y = i - 1; } } if ((i == 1 || i == 3) && Q[i - 1][j] == Q[i][j]) { x = j; if (i == 1) y = 0; else y = 1; } } } if (x == -1) { printf( %d n , -1); fflush(stdout); return 0; } while (count) { if (y) { if (Q[1 + y][x]) { res.emplace_back(Q[1 + y][x], 4, x + 1); Q[1 + y][x] = 0; count--; } else if (x) { if (Q[1 + y][x - 1] && Q[1 + y][x - 1] != Q[2 + y][x - 1]) { res.emplace_back(Q[1 + y][x - 1], 3, x + 1); Q[1 + y][x] = Q[1 + y][x - 1]; Q[1 + y][x - 1] = 0; } x--; } else { if (Q[1][0] && Q[1][0] != Q[0][0]) { res.emplace_back(Q[1][x], 3, 1); Q[2][0] = Q[1][0]; Q[1][0] = 0; } y = !y; } } else { if (Q[1 + y][x]) { res.emplace_back(Q[1 + y][x], 1, x + 1); Q[1 + y][x] = 0; count--; } else if (x < n - 1) { if (Q[1 + y][x + 1] && Q[1 + y][x + 1] != Q[0][x + 1]) { res.emplace_back(Q[1 + y][x + 1], 2, x + 1); Q[1 + y][x] = Q[1 + y][x + 1]; Q[1 + y][x + 1] = 0; } x++; } else { if (Q[2][n - 1] && Q[2][n - 1] != Q[3][n - 1]) { res.emplace_back(Q[2][n - 1], 2, n); Q[1][n - 1] = Q[2][n - 1]; Q[2][n - 1] = 0; } y = !y; } } } printf( %d n , (int)res.size()); fflush(stdout); int a, b, c; for (auto i : res) { tie(a, b, c) = i; printf( %d %d %d n , a, b, c); } return 0; } |
#include <bits/stdc++.h> using namespace std; int root; void addEdge(vector<int> adj[], int u, int v) { if (u == -1) { root = v; return; } adj[u].push_back(v); } int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); vector<int> res; int n, ctr, c; cin >> n; vector<int> adj[n + 1]; vector<bool> vis(n + 1, false); for (int i = 0; i < n; i++) { cin >> ctr >> c; addEdge(adj, ctr, i + 1); if (c) vis[i + 1] = true; } for (int i = 1; i <= n; i++) { if (!vis[i]) continue; auto it = adj[i].begin(); for (; it != adj[i].end(); it++) { if (!vis[*it]) break; } if (it == adj[i].end()) res.push_back(i); } if (res.size() == 0) cout << -1; else for (int x : res) cout << x << ; } |
#include <bits/stdc++.h> using namespace std; map<pair<int, int>, pair<int, int> > tab; int main() { int n, v[3]; pair<int, int> ans; int maior = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%d , &v[0], &v[1], &v[2]); sort(v, v + 3); for (int j = 0; j < 3; j++) for (int k = j + 1; k < 3; k++) { pair<int, int> x = tab[make_pair(v[j], v[k])]; int ind = 3 - j - k; int aux[3] = {v[0], v[1], v[2]}; aux[ind] += x.first; sort(aux, aux + 3); if (aux[0] > maior) { maior = aux[0]; ans.first = i; ans.second = x.second; } } if (tab[make_pair(v[0], v[1])].first < v[2]) tab[make_pair(v[0], v[1])] = make_pair(v[2], i); if (tab[make_pair(v[0], v[2])].first < v[1]) tab[make_pair(v[0], v[2])] = make_pair(v[1], i); if (tab[make_pair(v[1], v[2])].first < v[0]) tab[make_pair(v[1], v[2])] = make_pair(v[0], i); } if (ans.first > ans.second) swap(ans.first, ans.second); if (ans.first) printf( 2 n%d %d n , ans.first, ans.second); else printf( 1 n%d n , ans.second); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; if (s.size() >= 1 && s.size() <= 100) { int i, j, k = 0, m = 0; for (i = 0; i < s.size(); i++) { if (s[i] >= a && s[i] <= z ) k++; if (s[i] >= A && s[i] <= Z ) m++; } if (k >= m) { for (j = 0; j < s.size(); j++) { if (s[j] >= A && s[j] <= Z ) s[j] = s[j] + 32; cout << s[j]; } } if (k < m) { for (j = 0; j < s.size(); j++) { if (s[j] >= a && s[j] <= z ) s[j] = s[j] - 32; cout << s[j]; } } } return 0; } |
module barrier_wait
(/*AUTOARG*/
// Outputs
tracemon_barrier_retire_en, fetch_wg_wfid, barrier_wait_arry,
tracemon_barrier_retire_wf_bitmap, tracemon_barrier_retire_pc,
// Inputs
clk, rst, f_decode_valid, f_decode_barrier, f_decode_wfid,
f_decode_instr_pc, fetch_wg_wgid, fetch_wg_wf_count
);
/**
* Barrier wait has to recognize a barrier instruction
* from decode and hold the wf that hits the barrier until
* all wf from that wg are decoded.
* for each workgroup:
** have a list (Bitmap) of wf that hit the barrier
** somehow keep track of the number of wf that hit the barrier
* fore each wf
** 1 bit identifies wheather it hit or not the barrier
** clear bits from all wf when all wg hit the barrier
**/
input clk,rst;
input f_decode_valid, f_decode_barrier;
input [`WF_ID_LENGTH-1:0] f_decode_wfid;
input [31:0] f_decode_instr_pc;
input [`WF_ID_LENGTH-1:0] fetch_wg_wgid;
input [3:0] fetch_wg_wf_count;
wire decode_barrier_valid;
output tracemon_barrier_retire_en;
output [`WF_ID_LENGTH-1:0] fetch_wg_wfid;
output [`WF_PER_CU-1:0] barrier_wait_arry;
output [`WF_PER_CU-1:0] tracemon_barrier_retire_wf_bitmap;
output [31:0] tracemon_barrier_retire_pc;
wire [`WF_PER_CU-1:0] curr_wg_wf_waiting, next_curr_wg_wf_waiting;
wire [`WF_PER_WG-1:0] curr_wg_wf_count, next_curr_wg_wf_count;
wire [`WF_PER_CU-1:0] barrier_wait_arry, next_barrier_wait_arry;
wire all_wf_hit_barrier, first_wf_barrier;
reg [`WF_PER_WG-1:0] wf_count_mask;
wire [`WF_PER_CU-1:0] decode_barrier_valid_decoded;
assign fetch_wg_wfid = f_decode_wfid;
// The pc of the retired instruction is always the pc of the currently decoded instruction
assign tracemon_barrier_retire_pc = f_decode_instr_pc;
reg_40xX_1r_1w #(`WF_PER_CU + `WF_PER_WG) wg_info_reg
(
.rd_addr(fetch_wg_wgid),
.rd_data({curr_wg_wf_waiting,curr_wg_wf_count}),
.wr_en(decode_barrier_valid),
.wr_addr(fetch_wg_wgid),
.wr_data({next_curr_wg_wf_waiting,
next_curr_wg_wf_count}),
.clk(clk),
.rst(rst)
);
dff_en waiting_wf_reg[`WF_PER_CU-1:0]
(
.q(barrier_wait_arry),
.d(next_barrier_wait_arry),
.en(decode_barrier_valid),
.clk(clk),
.rst(rst)
);
// Calculate next mask for wg
always @ ( fetch_wg_wf_count ) begin
case(fetch_wg_wf_count)
4'd0 : wf_count_mask <= 16'b0000_0000_0000_0001;
4'd1 : wf_count_mask <= 16'b1111_1111_1111_1111;
4'd2 : wf_count_mask <= 16'b0111_1111_1111_1111;
4'd3 : wf_count_mask <= 16'b0011_1111_1111_1111;
4'd4 : wf_count_mask <= 16'b0001_1111_1111_1111;
4'd5 : wf_count_mask <= 16'b0000_1111_1111_1111;
4'd6 : wf_count_mask <= 16'b0000_0111_1111_1111;
4'd7 : wf_count_mask <= 16'b0000_0011_1111_1111;
4'd8 : wf_count_mask <= 16'b0000_0001_1111_1111;
4'd9 : wf_count_mask <= 16'b0000_0000_1111_1111;
4'd10 : wf_count_mask <= 16'b0000_0000_0111_1111;
4'd11 : wf_count_mask <= 16'b0000_0000_0011_1111;
4'd12 : wf_count_mask <= 16'b0000_0000_0001_1111;
4'd13 : wf_count_mask <= 16'b0000_0000_0000_1111;
4'd14 : wf_count_mask <= 16'b0000_0000_0000_0111;
4'd15 : wf_count_mask <= 16'b0000_0000_0000_0011;
endcase
end
decoder_6b_40b_en barrier_valid_decoder
(
.addr_in(f_decode_wfid),
.en(decode_barrier_valid),
.out(decode_barrier_valid_decoded)
);
assign decode_barrier_valid = f_decode_valid && f_decode_barrier;
// Signal when all_wf hit the barrier and when the first
// wf hit the barrier
assign all_wf_hit_barrier
= ((curr_wg_wf_count == 16'h7fff) | (fetch_wg_wf_count == 4'd1) ) &
decode_barrier_valid ? 1'b1 : 1'b0;
assign first_wf_barrier = (curr_wg_wf_count == 16'h0000)? 1'b1 : 1'b0;
// Reset wf_count if all wf hit the barrier,
// write the mask if it is the first wf
// and shift if is another wf
assign next_curr_wg_wf_count
= (all_wf_hit_barrier)? 16'h0 :
(first_wf_barrier)? wf_count_mask :
{curr_wg_wf_count[`WF_PER_WG-2:0],1'b1};
// Mark all wf of the curr wg waiting
assign next_curr_wg_wf_waiting
= (all_wf_hit_barrier)? 40'b0 :
curr_wg_wf_waiting | decode_barrier_valid_decoded;
assign tracemon_barrier_retire_wf_bitmap = curr_wg_wf_waiting | decode_barrier_valid_decoded;
// Mark all wf waiting globally
assign next_barrier_wait_arry
= (all_wf_hit_barrier)? barrier_wait_arry & (~curr_wg_wf_waiting) :
barrier_wait_arry | decode_barrier_valid_decoded;
// Assign signals for tracemon
assign tracemon_barrier_retire_en = all_wf_hit_barrier;
endmodule
|
#include <bits/stdc++.h> using namespace std; int m; void Add(int &a, int b) { a += b; if (a >= m) a -= m; } int dp[1010][110][2]; int main() { int n, k; while (scanf( %d%d%d , &n, &k, &m) == 3) { memset(dp, 0, sizeof(dp)); dp[0][0][0] = 1; long long tmp = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < k; j++) for (int x = 0; x < 2; x++) { if (dp[i][j][x] == 0) continue; for (int y = 0; y < 10; y++) { if (i == n - 1 && y == 0) continue; int nj = (y * tmp % k + j) % k; int nx = x; if (nj == 0 && (y > 0 || j > 0)) nx = 1; Add(dp[i + 1][nj][nx], dp[i][j][x]); } } tmp = tmp * 10 % k; } int ans = 0; for (int j = 0; j < k; j++) Add(ans, dp[n][j][1]); printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a; cin >> n >> a; if (a % 2 != 0) { cout << (((a - 1) / 2) + 1) << n ; } else { cout << ((n / 2) - ((a - 2) / 2)) << n ; } } |
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { os << { ; string sep; for (const auto& x : v) os << sep << x, sep = , ; return os << } ; } template <typename T, size_t size> ostream& operator<<(ostream& os, const array<T, size>& arr) { os << { ; string sep; for (const auto& x : arr) os << sep << x, sep = , ; return os << } ; } template <typename A, typename B> ostream& operator<<(ostream& os, const pair<A, B>& p) { return os << ( << p.first << , << p.second << ) ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } namespace math { template <typename V = int32_t> inline V extGcd(V a, V b, V& x, V& y) { bool negativeA = false; if (a < 0) { negativeA = true; a = -a; } bool negativeB = false; if (b < 0) { negativeB = true; b = -b; } x = 1; y = 0; V xTmp = 0; V yTmp = 1; while (b) { V q = a / b; tie(x, xTmp) = make_tuple(xTmp, x - q * xTmp); tie(y, yTmp) = make_tuple(yTmp, y - q * yTmp); tie(a, b) = make_tuple(b, a - q * b); } if (negativeA) { x = -x; } if (negativeB) { y = -y; } return a; } template <typename V = int> inline void slightFixModInline(V& v, const V& mod) { if (v < 0) { v += mod; } if (v >= mod) { v -= mod; } } template <typename V = int> inline V invMod(V a, V mod) { V x0, x1, gcd = extGcd(a, mod, x0, x1); slightFixModInline(x0, mod); return x0; } template <typename V = int32_t, typename V_SQR = int64_t> inline void mulModInline(V& res, V x, V mod) { if (!res || !x) { res = 0; } else if (res < mod / x) { res *= x; } else { res = static_cast<V_SQR>(res) * x % mod; } } template <typename V = int32_t, typename V_SQR = int64_t> inline V mulMod(V a, V b, V mod) { mulModInline<V, V_SQR>(a, b, mod); return a; } } // namespace math template <const int& MOD> struct _m_int { int val; _m_int(int64_t v = 0) { if (v < 0) v = v % MOD + MOD; if (v >= MOD) v %= MOD; val = int(v); } _m_int(uint64_t v) { if (v >= MOD) v %= MOD; val = int(v); } _m_int(int v) : _m_int(int64_t(v)) {} _m_int(unsigned v) : _m_int(uint64_t(v)) {} static int inv_mod(int a, int m = MOD) { return math::invMod(a, m); } explicit operator int() const { return val; } _m_int& operator+=(const _m_int& other) { val -= MOD - other.val; if (val < 0) val += MOD; return *this; } _m_int& operator-=(const _m_int& other) { val -= other.val; if (val < 0) val += MOD; return *this; } static unsigned fast_mod(uint64_t x, unsigned m = MOD) { return unsigned(x % MOD); } _m_int& operator*=(const _m_int& other) { val = math::mulMod(val, other.val, MOD); return *this; } _m_int& operator/=(const _m_int& other) { return *this *= other.inv(); } friend _m_int operator+(const _m_int& a, const _m_int& b) { return _m_int(a) += b; } friend _m_int operator-(const _m_int& a, const _m_int& b) { return _m_int(a) -= b; } friend _m_int operator*(const _m_int& a, const _m_int& b) { return _m_int(a) *= b; } _m_int& operator++() { val = val == MOD - 1 ? 0 : val + 1; return *this; } _m_int operator++(int) { _m_int before = *this; ++*this; return before; } friend bool operator==(const _m_int& a, const _m_int& b) { return a.val == b.val; } friend bool operator!=(const _m_int& a, const _m_int& b) { return a.val != b.val; } _m_int inv() const { return inv_mod(val); } _m_int pow(int64_t p) const { if (p < 0) return inv().pow(-p); _m_int a = *this, result = 1; while (p > 0) { if (p & 1) result *= a; p >>= 1; if (p > 0) a *= a; } return result; } }; extern const int MOD = 998244353; using mod_int = _m_int<MOD>; template <const int& MOD> struct NTT { using ntt_int = _m_int<MOD>; vector<ntt_int> roots = {0, 1}; vector<int> bit_reverse; int max_size = -1; ntt_int root; void reset() { roots = {0, 1}; max_size = -1; } static bool is_power_of_two(int n) { return (n & (n - 1)) == 0; } static int round_up_power_two(int n) { while (n & (n - 1)) n = (n | (n - 1)) + 1; return max(n, 1); } static int get_length(int n) { assert(is_power_of_two(n)); return __builtin_ctz(n); } void bit_reorder(int n, vector<ntt_int>& values) { if (int(bit_reverse.size()) != n) { bit_reverse.assign(n, 0); int length = get_length(n); for (int i = 1; i < n; i++) bit_reverse[i] = (bit_reverse[i >> 1] >> 1) | ((i & 1) << (length - 1)); } for (int i = 0; i < n; i++) if (i < bit_reverse[i]) swap(values[i], values[bit_reverse[i]]); } void find_root() { max_size = 1 << __builtin_ctz(MOD - 1); root = 2; while (!(root.pow(max_size) == 1 && root.pow(max_size / 2) != 1)) root++; } void prepare_roots(int n) { if (max_size < 0) find_root(); assert(n <= max_size); if (int(roots.size()) >= n) return; int length = get_length(int(roots.size())); roots.resize(n); while (1 << length < n) { ntt_int z = root.pow(max_size >> (length + 1)); for (int i = 1 << (length - 1); i < 1 << length; i++) { roots[2 * i] = roots[i]; roots[2 * i + 1] = roots[i] * z; } length++; } } void fft_iterative(int n, vector<ntt_int>& values) { assert(is_power_of_two(n)); prepare_roots(n); bit_reorder(n, values); for (int len = 1; len < n; len *= 2) for (int start = 0; start < n; start += 2 * len) for (int i = 0; i < len; i++) { ntt_int even = values[start + i]; ntt_int odd = values[start + len + i] * roots[len + i]; values[start + len + i] = even - odd; values[start + i] = even + odd; } } void invert_fft(int n, vector<ntt_int>& values) { ntt_int inv_n = ntt_int(n).inv(); for (int i = 0; i < n; i++) values[i] *= inv_n; reverse(values.begin() + 1, values.end()); fft_iterative(n, values); } const int FFT_CUTOFF = 150; template <typename T> vector<T> mod_multiply(const vector<T>& _left, const vector<T>& _right) { if (_left.empty() || _right.empty()) return {}; vector<ntt_int> left(_left.begin(), _left.end()); vector<ntt_int> right(_right.begin(), _right.end()); int n = int(left.size()); int m = int(right.size()); int output_size = n + m - 1; int N = round_up_power_two(output_size); left.resize(N, 0); right.resize(N, 0); fft_iterative(N, left); fft_iterative(N, right); for (int i = 0; i < N; i++) left[i] *= right[i]; invert_fft(N, left); return vector<T>(left.begin(), left.begin() + output_size); } }; NTT<MOD> ntt; const int L_MAX = 5e5 + 5; namespace io { const int _kReadBufferSize = 1 << 15; char _readBuffer[_kReadBufferSize]; int _readPos; int _readLength; bool _ended = false; inline void _loadBuffer() { _readLength = static_cast<int>( fread(_readBuffer, sizeof(char), _kReadBufferSize, stdin)); _readPos = 0; } inline char readChar(bool advance = true) { if (_ended) { return 0; } if (_readPos >= _readLength) { _loadBuffer(); if (_readLength == 0) { _ended = true; return 0; } } return _readBuffer[advance ? _readPos++ : _readPos]; } template <typename T> inline bool readInt(T& res) { char ch; while (true) { ch = readChar(false); if (!ch) { return false; } if (!isspace(ch)) { break; } ++_readPos; } ch = readChar(false); bool negative = ch == - ; if (negative) { ++_readPos; } res = 0; while (true) { ch = readChar(false); if (!isdigit(ch)) { break; } res = (res << 3) + (res << 1) + (ch & 15); ++_readPos; } if (negative) { res = -res; } return true; } const int _kWriteBufferSize = 1 << 15; int _writePos = 0; char _writeBuffer[_kWriteBufferSize]; inline void writeChar(char x) { if (_writePos == _kWriteBufferSize) { fwrite(_writeBuffer, 1, _kWriteBufferSize, stdout); _writePos = 0; } _writeBuffer[_writePos++] = x; } struct _Flusher { inline void flush() { if (_writePos) { fwrite(_writeBuffer, 1, _writePos, stdout); _writePos = 0; } fflush(stdout); } inline ~_Flusher() { flush(); } } _flusher; template <class T> inline void writeInt(T x, int padding = 0) { static char s[32]; if (x < 0) { writeChar( - ); x = -x; } int n = 0; for (; x || !n; x /= 10) { s[n++] = 0 + x % 10; } for (int i = n; i < padding; ++i) { writeChar( 0 ); } for (; n > 0; writeChar(s[--n])) { } } } // namespace io int main() { int N, X, Y; io::readInt(N); io::readInt(X); io::readInt(Y); vector<mod_int> lines(X + 1, 0); for (int i = 0; i <= N; i++) { int a; io::readInt(a); lines[a] = 1; } vector<mod_int> rev_lines = lines; reverse(rev_lines.begin(), rev_lines.end()); vector<mod_int> product = ntt.mod_multiply(lines, rev_lines); vector<int> answers(L_MAX, -1); for (int f = Y + 1; f < L_MAX; f++) if (f - Y <= X && product[X + f - Y] != 0) for (int x = f; x < L_MAX; x += f) answers[x] = 2 * f; int Q; io::readInt(Q); for (int q = 0; q < Q; q++) { int len; io::readInt(len); len /= 2; io::writeInt(answers[len]); io::writeChar(q < Q - 1 ? : n ); } } |
#include <bits/stdc++.h> using namespace std; struct LazySegTree { int size; vector<long long> seg, delay; LazySegTree() {} LazySegTree(int size) { this->size = size; seg.resize(1 << (size + 1)); delay.resize(1 << (size + 1)); } long long Ident() { return 0; } long long ope(long long a, long long b) { return (a + b); } void init() { for (int i = 0; i < (1 << (size + 1)); i++) { seg[i] = Ident(); delay[i] = 0; } } void eval(int l, int r, int k) { if (delay[k]) { seg[k] = 0; if (l < r) { delay[k * 2] += delay[k]; delay[k * 2 + 1] += delay[k]; } delay[k] = 0; } } void update(int i, long long val) { int l = 0, r = (1 << size) - 1, k = 1; eval(l, r, k); for (int j = size - 1; j >= 0; j--) { k <<= 1; if (i & (1 << j)) { k++; l = (l + r) / 2 + 1; } else r = (l + r) / 2; eval(l, r, k); } seg[i + (1 << size)] = val; l = i, r = i, k = i + (1 << size); for (int j = 0; j < size; j++) { k /= 2, l &= ~(1 << j), r |= 1 << j; eval(l, (l + r) / 2, k * 2), eval((l + r) / 2 + 1, r, k * 2 + 1); seg[k] = ope(seg[k * 2], seg[k * 2 + 1]); } } void add(int a, int b, int k, int l, int r, long long val) { eval(l, r, k); if (b < l || r < a) return; if (a <= l && r <= b) { delay[k] += val; eval(l, r, k); return; } add(a, b, k * 2, l, (l + r) / 2, val); add(a, b, k * 2 + 1, (l + r) / 2 + 1, r, val); seg[k] = ope(seg[k * 2], seg[k * 2 + 1]); } void add(int a, int b, long long val) { if (a > b) return; add(a, b, 1, 0, (1 << size) - 1, val); } long long query(int a, int b, int k, int l, int r) { eval(l, r, k); if (b < l || r < a) return Ident(); if (a <= l && r <= b) return seg[k]; long long lval = query(a, b, k * 2, l, (l + r) / 2); long long rval = query(a, b, k * 2 + 1, (l + r) / 2 + 1, r); return ope(lval, rval); } long long query(int a, int b) { if (a > b) return Ident(); return query(a, b, 1, 0, (1 << size) - 1); } }; long long n, m; long long l[200005], r[200005], rcnt[200005]; vector<long long> vec[200005]; LazySegTree sseg[2], nseg[2]; multiset<long long> S[2]; long long dif[200005]; int main(void) { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (long long(i) = (1); (i) <= (n); (i)++) { cin >> l[i] >> r[i]; dif[l[i]]++, dif[r[i] + 1]--; l[i]--; vec[l[i]].push_back(r[i]); rcnt[r[i]]++; } for (long long(i) = (0); (i) <= (1); (i)++) { sseg[i] = LazySegTree(18), sseg[i].init(); nseg[i] = LazySegTree(18), nseg[i].init(); } for (long long(i) = (0); (i) <= (m); (i)++) sseg[i % 2].update(i, i), nseg[i % 2].update(i, 1); long long ans = 0; for (long long i = m; i >= 0; i--) { for (auto r : vec[i]) { sseg[i % 2].add(i + 1, r, 1), nseg[i % 2].add(i + 1, r, 1); if ((r - i) % 2 == 0) { sseg[0].add(r + 1, m, 1), sseg[1].add(r + 1, m, 1); nseg[0].add(r + 1, m, 1), nseg[1].add(r + 1, m, 1); } S[r % 2].erase(S[r % 2].lower_bound(r)); } long long lb = i, ub = m; for (long long(j) = (0); (j) <= (1); (j)++) if (S[j].size()) (lb) = max((lb), (*S[j].rbegin())); if (S[i % 2].size()) (ub) = min((ub), (*S[i % 2].begin())); ans += sseg[i % 2].query(lb + 1, ub); ans += sseg[(i + 1) % 2].query(i + 1, ub); ans -= i * nseg[i % 2].query(lb + 1, ub); ans -= i * nseg[(i + 1) % 2].query(i + 1, ub); for (long long(j) = (1); (j) <= (rcnt[i]); (j)++) S[i % 2].insert(i); } for (long long(i) = (1); (i) <= (m); (i)++) dif[i] += dif[i - 1]; dif[m + 1] = 1; long long cnt = 0; for (long long(i) = (1); (i) <= (m + 1); (i)++) { if (dif[i]) ans -= (cnt + 1) * cnt * (cnt + 1) / 2 - cnt * (cnt + 1) * (2 * cnt + 1) / 6, cnt = 0; else cnt++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; int n, q, fa[N]; double p[N], sum[N], ans; vector<int> son[N]; void dfs(int x, int f) { fa[x] = f; for (int i = 0; i < son[x].size(); ++i) { int y = son[x][i]; if (y == f) continue; dfs(y, x); sum[x] += 1 - p[y]; ans += p[x] * (1 - p[y]); } } int main() { scanf( %d , &n); p[0] = 1; for (int i = 1; i <= n; ++i) scanf( %lf , p + i); for (int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); ++u, ++v; son[u].push_back(v); son[v].push_back(u); } ans = 1 - p[1]; dfs(1, 0); scanf( %d , &q); while (q--) { int k; double p1; scanf( %d%lf , &k, &p1); ++k; sum[fa[k]] -= p1 - p[k]; ans += sum[k] * (p1 - p[k]) - (p1 - p[k]) * p[fa[k]]; p[k] = p1; printf( %.5lf n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod; long long power(long long a, long long p) { long long res = 1; while (p) { if (p & 1) res = res * a % mod; a = a * a % mod; p >>= 1; } return res; } long long inv(long long a) { return power(a, mod - 2); } class matrix { public: vector<vector<long long>> a; int n; matrix() {} matrix(int n) { init(n); } void init(int n) { this->n = n; a.resize(n); for (int i = 0; i < n; i++) a[i].resize(n, 0); } long long getDigonal() { long long res = 1; for (int i = 0; i < n; i++) res = res * a[i][i] % mod; return res; } }; const int dy[4] = {-1, -1, 1, 1}, dx[4] = {-1, 1, -1, 1}; const int cy[4] = {-1, -1, 0, 0}, cx[4] = {-1, 0, -1, 0}; const int bn[4] = {1, 0, 0, 1}; int n, m, vis[201][201], g = 0, arr[201][201]; char str[201][201]; bool go(int y, int x, int i, int j) { return y >= 0 && x >= 0 && y <= n && x <= m && i >= 0 && j >= 0 && i < n && j < m; } void bfs(int si, int sj) { queue<pair<int, int>> que; que.push(pair<int, int>(si, sj)); vis[si][sj] = g; while (!que.empty()) { int i = que.front().first, j = que.front().second; que.pop(); for (int k = 0; k < 4; k++) { int yy = i + dy[k], xx = j + dx[k]; int ii = i + cy[k], jj = j + cx[k]; if (go(yy, xx, ii, jj) && vis[yy][xx] == -1 && arr[ii][jj] == bn[k]) { vis[yy][xx] = g; que.push(pair<int, int>(yy, xx)); } } } } long long LU_Det(matrix a) { int n = a.n; long long res = 1; matrix U = a, L(n); for (int i = 0; i < n; i++) { for (int k = i; k < n; k++) if (U.a[k][i] != 0) { if (k != i) { swap(U.a[i], U.a[k]); res = res * (mod - 1) % mod; } break; } long long val = inv(U.a[i][i]); L.a[i][i] = U.a[i][i]; res = res * U.a[i][i] % mod; for (int j = 0; j < n; j++) U.a[i][j] = (U.a[i][j] * val) % mod; for (int k = i + 1; k < n; k++) { long long val = -U.a[k][i]; L.a[k][i] = -val; for (int j = 0; j < n; j++) { U.a[k][j] = (U.a[k][j] + U.a[i][j] * val) % mod; if (U.a[k][j] < 0) U.a[k][j] += mod; } } } return res % mod; } long long solve(int s) { int t = s; g = 0; memset(vis, -1, sizeof(vis)); for (int i = 0; i <= n; i++, t ^= 1) { for (int j = t; j <= m; j += 2) if (vis[i][j] == -1) bfs(i, j), g++; } matrix a(g); t = s; for (int i = 0; i <= n; i++, t ^= 1) { for (int j = t; j <= m; j += 2) { for (int k = 0; k < 4; k++) { int yy = i + dy[k], xx = j + dx[k]; int ii = i + cy[k], jj = j + cx[k]; if (go(yy, xx, ii, jj) && arr[ii][jj] == -1 && vis[i][j] != vis[yy][xx]) { a.a[vis[i][j]][vis[yy][xx]]--; } } } } for (int i = 0; i < g; i++) { for (int j = 0; j < g; j++) if (i != j) { a.a[i][i] -= a.a[i][j]; } for (int j = 0; j < g; j++) a.a[i][j] = (a.a[i][j] + mod) % mod; } matrix b(g - 1); for (int i = 0; i < g - 1; i++) for (int j = 0; j < g - 1; j++) b.a[i][j] = a.a[i][j]; long long ans = (LU_Det(b) % mod + mod) % mod; return ans; } int main() { scanf( %d%d%lld , &n, &m, &mod); for (int i = 0; i < n; i++) scanf( %s , str[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (str[i][j] == / ) arr[i][j] = 0; else if (str[i][j] == * ) arr[i][j] = -1; else arr[i][j] = 1; } printf( %lld n , (solve(0) + solve(1)) % mod); return 0; } |
/*
* Asynchronous read 1r1w content addressable memory module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
* - Read searches the array for any data with r_tag_i
* - Write allocates a new entry, replacing an existing entry with replacement
* scheme repl_scheme_p
* - Write with w_nuke_i flag invalidates the cam
* - Allocation happens in parallel with read, so it is possible in an LRU
* scheme for the currently-being-read item to be overwritten
* - There are no concerns about simultaneous reading and writing
* - It is generally discouraged to have multiple identical tags in the array,
* i.e. you should read the array to see if anything is there before
* writing; but if there are, then the data returned on read is the OR
* of the data. If you find that functionality useful, let us know =)
*/
`include "bsg_defines.v"
module bsg_cam_1r1w
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
// The replacement scheme for the CAM
, parameter repl_scheme_p = "lru"
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
, input w_v_i
// When w_v_i & w_nuke_i, the whole cam array is invalidated
, input w_nuke_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
localparam safe_els_lp = `BSG_MAX(els_p,1);
// The tag storage for the CAM
logic [safe_els_lp-1:0] tag_r_match_lo;
logic [safe_els_lp-1:0] tag_empty_lo;
logic [safe_els_lp-1:0] repl_way_lo;
wire [safe_els_lp-1:0] tag_w_v_li = repl_way_lo | {safe_els_lp{w_nuke_i}};
bsg_cam_1r1w_tag_array
#(.width_p(tag_width_p)
,.els_p(safe_els_lp)
)
cam_tag_array
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(tag_w_v_li)
,.w_set_not_clear_i(w_v_i & ~w_nuke_i)
,.w_tag_i(w_tag_i)
,.w_empty_o(tag_empty_lo)
,.r_v_i(r_v_i)
,.r_tag_i(r_tag_i)
,.r_match_o(tag_r_match_lo)
);
// The replacement scheme for the CAM
bsg_cam_1r1w_replacement
#(.els_p(safe_els_lp)
,.scheme_p(repl_scheme_p)
)
replacement
(.clk_i(clk_i)
,.reset_i(reset_i)
,.read_v_i(tag_r_match_lo)
,.alloc_v_i(w_v_i)
,.alloc_empty_i(tag_empty_lo)
,.alloc_v_o(repl_way_lo)
);
// The data storage for the CAM
wire [safe_els_lp-1:0] mem_w_v_li = repl_way_lo;
bsg_mem_1r1w_one_hot
#(.width_p(data_width_p)
,.els_p(safe_els_lp)
)
one_hot_mem
(.w_clk_i(clk_i)
,.w_reset_i(reset_i)
,.w_v_i(mem_w_v_li)
,.w_data_i(w_data_i)
,.r_v_i(tag_r_match_lo)
,.r_data_o(r_data_o)
);
assign r_v_o = |tag_r_match_lo;
endmodule
`BSG_ABSTRACT_MODULE(bsg_cam_1r1w)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const int mod = 1e9 + 7; void solve() { long long v1, v2, t, d; cin >> v1 >> v2 >> t >> d; long long ans = 0; for (int i = 0; i < t; i++) ans += min(v1 + d * i, v2 + (t - i - 1) * d); cout << ans << endl; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long n, k, m, f[100005][15][20]; long long count(long long x) { long long sum = 0; while (x) sum++, x -= (x & -x); return sum; } signed main() { scanf( %lld%lld%lld , &n, &k, &m); f[0][0][0] = 1; for (long long i = 0; i < n; i++) { for (long long j = 0; j <= k; j++) { for (long long s = 0; s < (1 << m); s++) { f[i + 1][j][s >> 1] = (f[i + 1][j][s >> 1] + f[i][j][s]) % mod; f[i + 1][j + 1][(s >> 1) | (1 << (m - 1))] = (f[i + 1][j + 1][(s >> 1) | (1 << (m - 1))] + (1ll + count(s)) * f[i][j][s]) % mod; } } } long long ans = 0; for (long long i = 0; i < (1 << m); i++) ans = (ans + f[n][k][i]) % mod; printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; ; int bit; cin >> bit; ; int sum = 0; bool test = false; for (int i = 1; i < n; i++) { int h; cin >> h; ; bit -= (h + 1); if (bit < 0) { cout << NO ; return 0; } } int h; cin >> h; ; bit -= h; if (bit != 0) cout << NO ; else cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3fll; const long long M = 1e9 + 7; const long long maxn = 1e5 + 7; const double eps = 0.00000001; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } int n, m; int i, j, k; int main() { scanf( %d , &n); printf( %d , (n - 1) / 2); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_BLACKBOX_V
`define SKY130_FD_SC_HS__A311OI_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_2_V
`define SKY130_FD_SC_HS__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 1e3 + 7; int n, m, tot, root[N]; long long p, ans; struct node { int ls, rs; long long sum; } t[N * 30]; void insert(int x, int &y, int l, int r, int v) { y = ++tot; t[y] = t[x]; t[y].sum++; if (l == r) return; int mid = (l + r) >> 1; if (v <= mid) insert(t[x].ls, t[y].ls, l, mid, v); else insert(t[x].rs, t[y].rs, mid + 1, r, v); } long long query(int l, int r, int x, int y, int L, int R) { if (L > R || l > r || L > r || R < l) return 0; if (l >= L && r <= R) return t[y].sum - t[x].sum; int mid = (l + r) >> 1; return query(l, mid, t[x].ls, t[y].ls, L, R) + query(mid + 1, r, t[x].rs, t[y].rs, L, R); } long long cal(long long x) { return x * (x - 1) / 2; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); insert(root[i - 1], root[i], 1, n, x); } while (m--) { int l, r, u, v; scanf( %d%d%d%d , &l, &r, &u, &v); ans = (long long)n * (long long)(n - 1) / 2; p = query(1, n, root[0], root[n], 1, r - 1); ans -= cal(p); p = query(1, n, root[0], root[n], v + 1, n); ans -= cal(p); p = query(1, n, root[0], root[l - 1], 1, n); ans -= cal(p); p = query(1, n, root[u], root[n], 1, n); ans -= cal(p); p = query(1, n, root[0], root[l - 1], 1, r - 1); ans += cal(p); p = query(1, n, root[0], root[l - 1], v + 1, n); ans += cal(p); p = query(1, n, root[u], root[n], 1, r - 1); ans += cal(p); p = query(1, n, root[u], root[n], v + 1, n); ans += cal(p); printf( %I64d n , ans); } } |
#include <bits/stdc++.h> using namespace std; long long U[10001], V[10000], dis[10000]; long long n, m; vector<long long> adj[10001]; bool bfs() { queue<long long> q; for (long long i = 1; i <= n; i++) { if (U[i] == 0) { dis[i] = 0; q.push(i); } else dis[i] = INT_MAX; } dis[0] = INT_MAX; while (!q.empty()) { long long x = q.front(); q.pop(); if (dis[x] < dis[0]) { for (long long j = 0; j < adj[x].size(); j++) { if (dis[V[adj[x][j]]] == INT_MAX) { dis[V[adj[x][j]]] = dis[x] + 1; q.push(V[adj[x][j]]); } } } } return (dis[0] != INT_MAX); } bool dfs(long long u) { if (u != 0) { for (long long j = 0; j < adj[u].size(); j++) { if (dis[V[adj[u][j]]] == (dis[u] + 1)) { if (dfs(V[adj[u][j]])) { V[adj[u][j]] = u; U[u] = adj[u][j]; return true; } } } dis[u] = INT_MAX; return false; } return true; } long long hopcroft() { for (long long i = 0; i <= 10000; i++) { U[i] = 0; V[i] = 0; } long long ans = 0; while (bfs()) { for (long long u = 1; u <= n; u++) { if (U[u] == 0 && dfs(u)) ans++; } } return ans; } void solve() { cin >> n >> m; vector<pair<long long, pair<long long, long long> > > edges; for (long long i = 0; i < m; i++) { long long a, b, c; cin >> a >> b >> c; edges.push_back({c, {a, b}}); } long long l = 0, r = 1000000000, f = -1; while (l <= r) { long long mid = (l + r) / 2; for (long long i = 1; i <= n; i++) adj[i].clear(); for (auto x : edges) { if (x.first <= mid) { adj[x.second.first].push_back(x.second.second); } } if (hopcroft() == n) { r = mid - 1; f = mid; } else l = mid + 1; } cout << f << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long test = 0, t; t = 1; while (test++ < t) { solve(); } } |
#include <bits/stdc++.h> using namespace std; vector<vector<long long int> > edge(100010); long long int vis[100010]; vector<long long int> color[2]; bool dfs(long long int a, long long int c = 2) { vis[a] = c; color[c - 1].push_back(a); for (auto x : edge[a]) { if (!vis[x] && dfs(x, 3ll - c)) { return 1; } if (vis[x] != 3ll - c) { return 1; } } return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m, x, y; cin >> n >> m; for (long long int i = 1; i <= m; i++) { cin >> x >> y; edge[x].push_back(y); edge[y].push_back(x); } for (long long int i = 1; i <= n; i++) { if (!vis[i]) { if (edge[i].size() == 0) { continue; } if (dfs(i)) { cout << -1 << endl; return 0; } } } for (long long int i = 0; i < 2; i++) { cout << color[i].size() << endl; for (auto x : color[i]) { cout << x << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f, N = 10; int ans = inf, n, k, idx[N]; char arr[N][N]; int convert(int num) { int ret = 0; for (int i = 0; i < k; ++i) { ret = (ret * 10) + (arr[num][idx[i]] - 0 ); } return ret; } int main() { cin >> n >> k; for (int i = 0; i < k; ++i) idx[i] = i; for (int i = 0; i < n; ++i) scanf( %s , arr[i]); do { int mn = inf, mx = 0; for (int i = 0; i < n; ++i) { mn = min(mn, convert(i)); mx = max(mx, convert(i)); } ans = min(ans, mx - mn); } while (next_permutation(idx, idx + k)); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int main() { ios_base::sync_with_stdio(false); while (cin >> n) { vector<int> inside(1000006, 0), ans; int stack = 0, length = 0, x, valid = 1, j = 1; unordered_map<int, int> used; for (int i = 0; i < n; ++i) { cin >> x; if ((x > 0 && inside[x]) || (x < 0 && !inside[-x]) || (x > 0 && used[x])) { valid = 0; } else if (x > 0) { ++inside[x]; ++stack; ++length; used[x] = j++; } else if (x < 0) { --inside[-x]; --stack; ++length; } if (!stack && valid) { ans.emplace_back(length); length = 0; used.clear(); } } if (stack) valid = 0; if (valid) { cout << ans.size() << endl; for (int i : ans) cout << i << ; cout << endl; } else { cout << -1 << endl; } } return 0; } |
module t (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
reg inmod;
generate
if (1) begin
// Traces as genblk1.ingen
integer ingen;
initial $display("ingen: {mod}.genblk1 %m");
end
endgenerate
integer rawmod;
initial begin
begin
integer upa;
begin : d3nameda
// %m='.d3nameda' var=_unnamed#.d3nameda.b1
integer d3a;
$display("d3a: {mod}.d3nameda %m");
end
end
end
initial begin
integer b2;
$display("b2: {mod} %m");
begin : b3named
integer b3n;
$display("b3n: {mod}.b3named: %m");
end
if (1) begin
integer b3;
$display("b3: {mod} %m");
if (1) begin
begin
begin
begin
integer b4;
$display("b4: {mod} %m");
end
end
end
end
else begin
integer b4;
$display("bb %m");
end
end
else begin
integer b4;
$display("b4 %m");
end
tsk;
$write("*-* All Finished *-*\n");
$finish;
end
task tsk;
integer t1;
$display("t1 {mod}.tsk %m");
begin
integer t2;
$display("t2 {mod}.tsk %m");
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int in() { int x; scanf( %d , &x); return x; } long long lin() { long long x; scanf( %lld , &x); return x; } int x[200010]; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) a[i] = in(); int s = 0; for (int i = 0; i < n; ++i) { if (s <= 1) { x[s++] = a[i]; } else if (x[s - 2] == x[s - 1] && x[s - 1] <= a[i]) { s -= 2; x[s++] = a[i]; } else if (x[s - 1] == a[i] && a[i] <= x[s - 2]) { s -= 1; } else { x[s++] = a[i]; } } if (s <= 1 || (s == 2 && x[0] == x[1])) { cout << YES << endl; } else { cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int l[5005], r[5005], v[105][105], t[105][105]; double res[105], c[5005], f[105][105], cc[105][105]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int a, b, x; scanf( %d%d%d , &a, &b, &x); l[i] = (--a); r[i] = (--b); c[i] = x; v[a][b] = (v[a][b] == 0) ? x : min(v[a][b], x); t[a][b]++; t[b][a]++; } int k = n - 2; for (int i = 1; i <= k; i++) { for (int j = 0; j < n; j++) { f[i][i] += t[j][i]; f[i][j] -= t[j][i]; } f[i][n - 1] = -f[i][0]; } for (int i = 1; i <= k; i++) { int t = i; while (!f[t][i] && t <= k) t++; if (t > k) continue; for (int j = i; j <= k + 1; j++) swap(f[i][j], f[t][j]); for (int j = 1; j <= k; j++) { if (j != i) { double tt = f[j][i] / f[i][i]; for (int x = 1; x <= k + 1; x++) f[j][x] -= tt * f[i][x]; } } } for (int i = 1; i <= k; i++) { if (f[i][i] == 0) continue; double x = f[i][i]; for (int j = 1; j <= k + 1; j++) f[i][j] /= x; res[i] = f[i][k + 1]; } res[0] = 1; double mn = 1e9 + 7; for (int i = 0; i < m; i++) { double x = fabs(res[l[i]] - res[r[i]]); if (x < 1e-10) continue; mn = min(mn, c[i] / x); } double ans = 0; for (int i = 0; i < m; i++) cc[l[i]][r[i]] = mn * (res[l[i]] - res[r[i]]); for (int i = 0; i < m; i++) { if (l[i] == 0) ans += cc[l[i]][r[i]]; if (r[i] == 0) ans -= cc[l[i]][r[i]]; } printf( %.5lf n , ans); for (int i = 0; i < m; i++) printf( %.5lf n , cc[l[i]][r[i]]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int cnt[1001] = {0}, a[n]; for (int i = 0; i < n; ++i) { cin >> a[i]; cnt[a[i]] = i; } int vis[1001] = {0}; vector<int> res; for (int i = 0; i < n; i++) { if (cnt[a[i]] == i) res.push_back(a[i]); } cout << res.size() << endl; for (int i = 0; i < res.size(); ++i) cout << res[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int s, n, m, t, x, y; vector<int> ord; vector<vector<int>> g; bool vis[200010]; void dfs(int c) { vis[c] = true; for (auto &v : g[c]) { if (!vis[v]) dfs(v); } ord.push_back(c); } int main() { std::istream::sync_with_stdio(false); cin >> s; while (s--) { cin >> n >> m; vector<pair<int, int>> edges; g = vector<vector<int>>(n + 1); for (int i = 0; i < m; i++) { cin >> t >> x >> y; if (t == 1) { g[x].push_back(y); } edges.emplace_back(x, y); } ord.clear(); memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; i++) { if (!vis[i]) dfs(i); } vector<int> pos(n + 1); reverse(ord.begin(), ord.end()); for (int i = 0; i < n; i++) { pos[ord[i]] = i; } bool flag = false; for (int i = 1; i <= n; i++) { for (auto &v : g[i]) { if (pos[i] > pos[v]) flag = true; } } if (flag) { cout << NO << endl; continue; } else { cout << YES << endl; for (auto &v : edges) { if (pos[v.first] < pos[v.second]) { cout << v.first << << v.second << endl; } else { cout << v.second << << v.first << endl; } } } } } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long n, a[10], C[110][110], dp[110][10], ans; inline long long add(long long x, long long y) { x += y; if (x > MOD) x -= MOD; return x; } inline long long mul(long long x, long long y) { x *= y; if (x > MOD) x %= MOD; return x; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.setf(ios::fixed); cout.precision(20); cin >> n; for (int i = 0; i < 10; ++i) cin >> a[i]; C[0][0] = 1; for (int i = 1; i <= 100; ++i) { C[i][0] = 1; for (int j = 1; j <= i; ++j) C[i][j] = add(C[i - 1][j - 1], C[i - 1][j]); } for (int i = a[9]; i <= n; ++i) dp[i][9] = 1; for (int i = 0; i <= n; ++i) { for (int j = 8; j > 0; --j) for (int k = a[j]; k <= i; ++k) dp[i][j] = add(dp[i][j], mul(dp[i - k][j + 1], C[i][k])); for (int j = a[0]; j < i; ++j) dp[i][0] = add(dp[i][0], mul(dp[i - j][1], C[i - 1][j])); } for (int i = 0; i <= n; ++i) ans = add(ans, dp[i][0]); cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200008; int n, k, l, r; char g[2][maxn]; bool f[2][maxn]; struct arr { int t, s, x; } h[maxn]; bool Add(int t, int s, int x) { if (t >= x) return 0; if (x > n) return 1; if (f[s][x]) return 0; if (g[s][x] == X ) return 0; f[s][x] = 1; ++r; h[r].t = t; h[r].s = s; h[r].x = x; return 0; } bool Work() { h[1].t = 0; h[1].s = 0; h[1].x = 1; l = 1, r = 1; f[0][1] = 1; while (l <= r) { int t = h[l].t, s = h[l].s, x = h[l].x; ++l; if (Add(t + 1, s, x + 1)) return 1; if (Add(t + 1, s, x - 1)) return 1; if (Add(t + 1, s ^ 1, x + k)) return 1; } return 0; } int main() { scanf( %d%d%*c , &n, &k); scanf( %s , &g[0][1]); scanf( %s , &g[1][1]); if (Work()) printf( YES n ); else printf( NO n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n1, n2, k1, k2; long long aa[105][105][2]; long long foo(int u, int v, int a) { if (u == 0 && v == 0) { return 1; } if (u < 0 || v < 0) { return 0; } if (aa[u][v][a] != -1) return (aa[u][v][a]); long long s = 0; if (a) { for (int i = 1; i <= k1; i++) { s += foo(u - i, v, !a) % 100000000; } } else { for (int i = 1; i <= k2; i++) { s += foo(u, v - i, !a) % 100000000; } } aa[u][v][a] = s; return s; } int main() { cin >> n1 >> n2 >> k1 >> k2; long long s; for (int i = 0; i <= 103; i++) { for (int j = 0; j <= 103; j++) { aa[i][j][0] = -1; aa[i][j][1] = -1; } } s = foo(n1, n2, 1); s += foo(n1, n2, 0); cout << s % 100000000; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > g[100010]; int N, K, in[100010], dp[100010][2]; vector<pair<int, int> > num[100010]; void dfs(int u, int fa) { for (pair<int, int>& e : g[u]) { int v = e.first, cost = e.second; if (v == fa) continue; dfs(v, u); num[u].push_back(pair<int, int>(dp[v][1] + cost, v)); } sort(num[u].begin(), num[u].end(), greater<pair<int, int> >()); dp[u][1] = 0; int sum = 0; for (size_t i = 0; (int)i < K - 1 && i < num[u].size(); i++) { dp[u][1] += num[u][i].first; sum += num[u][i].first; } if ((int)num[u].size() <= K - 1) { for (size_t i = 0; i < num[u].size(); i++) { int v = num[u][i].second; dp[u][0] = max(dp[u][0], sum - dp[v][1] + dp[v][0]); } } else { for (size_t i = 0; i < (int)K - 1; i++) { int v = num[u][i].second; dp[u][0] = max(dp[u][0], sum + num[u][K - 1].first - dp[v][1] + dp[v][0]); } for (size_t i = K - 1; i < num[u].size(); i++) { int v = num[u][i].second; dp[u][0] = max(dp[u][0], sum + num[u][i].first - dp[v][1] + dp[v][0]); } } } int main() { int u, v, c; scanf( %d%d , &N, &K); for (int i = 1; i < N; i++) { scanf( %d%d%d , &u, &v, &c); g[u].push_back(pair<int, int>(v, c)); g[v].push_back(pair<int, int>(u, c)); } dfs(0, -1); printf( %d n , max(dp[0][0], dp[0][1])); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int arr[1000000]; int main() { int n; cin >> n; long long int count = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; } long long int Min = arr[0]; long long int Max = arr[0]; for (int i = 1; i < n; i++) { if (arr[i] >= arr[i - 1]) Min = Max = arr[i]; else { int j = i; long long int mmin = arr[j - 1]; long long int mmax = arr[j - 1]; int c = 0; while (arr[j - 1] > arr[j]) { mmin = min(arr[j], mmin); mmax = max(arr[j], mmax); j++; if (j == n) break; c++; } count += mmax - mmin; i += c; } } cout << count << endl; return 0; } |
`default_nettype none
module reversed_gate (clk, ctrl, din, sel, dout);
input wire clk;
input wire [4:0] ctrl;
input wire [15:0] din;
input wire [3:0] sel;
output reg [31:0] dout;
always @(posedge clk)
case ((({(32)-((ctrl)*(sel))})+(1))-(2))
0:
dout[1:0] <= din;
1:
dout[2:1] <= din;
2:
dout[3:2] <= din;
3:
dout[4:3] <= din;
4:
dout[5:4] <= din;
5:
dout[6:5] <= din;
6:
dout[7:6] <= din;
7:
dout[8:7] <= din;
8:
dout[9:8] <= din;
9:
dout[10:9] <= din;
10:
dout[11:10] <= din;
11:
dout[12:11] <= din;
12:
dout[13:12] <= din;
13:
dout[14:13] <= din;
14:
dout[15:14] <= din;
15:
dout[16:15] <= din;
16:
dout[17:16] <= din;
17:
dout[18:17] <= din;
18:
dout[19:18] <= din;
19:
dout[20:19] <= din;
20:
dout[21:20] <= din;
21:
dout[22:21] <= din;
22:
dout[23:22] <= din;
23:
dout[24:23] <= din;
24:
dout[25:24] <= din;
25:
dout[26:25] <= din;
26:
dout[27:26] <= din;
27:
dout[28:27] <= din;
28:
dout[29:28] <= din;
29:
dout[30:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_4_V
`define SKY130_FD_SC_LS__A2111O_4_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_4 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_TB_V
`define SKY130_FD_SC_LP__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_TB_V
|
#include <bits/stdc++.h> using namespace std; int cx[] = {-1, 0, 0, 1, -1, -1, 1, 1, 0}, cy[] = {0, -1, 1, 0, -1, 1, 1, -1, 0}; int ingrid(int ii, int jj, int R, int C) { if (ii < 0 || jj < 0 || ii >= R || jj >= C) return 0; return 1; } int main() { long long n; cin >> n; long long maxx = -1, minn = (1LL << 60); for (int i = 1; i <= sqrt(n); i++) { long long a = i; if (n % a == 0) { long long c = n / a; for (int i = a; i <= sqrt(c); i++) { if (c % i == 0) { long long b = c / i; long long c = i; long long temp = (a + 1) * (b + 2) * (c + 2); minn = min(minn, temp); maxx = max(maxx, temp); temp = (b + 1) * (a + 2) * (c + 2); minn = min(minn, temp); maxx = max(maxx, temp); temp = (c + 1) * (a + 2) * (b + 2); minn = min(minn, temp); maxx = max(maxx, temp); } } } } cout << minn - n << << maxx - n << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 205, P = 1e9 + 7ll; struct node { long long x, y; node operator-(const node &t) const { node c; c.x = x - t.x; c.y = y - t.y; return c; } long long operator*(const node &t) const { return x * t.y - y * t.x; } } p[N]; long long n, dp[N][N]; long long search(long long x, long long y) { long long ans = 0; if (dp[x][y] != -1) return dp[x][y]; if (x + 1 == y) return dp[x][y] = 1; for (int i = x + 1; i < y; i++) if ((p[x] - p[i]) * (p[y] - p[i]) > 0) ans = (ans + search(x, i) * search(i, y) % P) % P; return dp[x][y] = ans; } int main() { memset(dp, -1, sizeof dp); scanf( %dll , &n); for (int i = 1; i <= n; i++) scanf( %lld%lld , &p[i].x, &p[i].y); p[n + 1] = p[1]; long long s = 0; for (int i = 1; i <= n; i++) s += p[i + 1] * p[i]; if (s < 0) for (int i = 1, j = n; i < j; swap(p[i++], p[j--])) ; printf( %lld , search(1, n)); return 0; } |
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