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#include <bits/stdc++.h> using namespace std; int n, m, k, u, v, a[200005], el, ans; vector<int> adj[200005]; queue<int> q; bool vis[200005]; int depth[200005], depthn[200005]; int main() { ios_base::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); cin >> n >> m >> k; for (int i = 1; i <= k; i++) { cin >> a[i]; } for (int i = 1; i <= m; i++) { cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } for (int i = 1; i <= n; i++) { vis[i] = 0; } q.push(1); vis[1] = 1; depth[1] = 0; int node; while (!q.empty()) { node = q.front(); q.pop(); for (int x : adj[node]) { if (vis[x]) continue; vis[x] = 1; depth[x] = depth[node] + 1; q.push(x); } } for (int i = 1; i <= n; i++) { vis[i] = 0; } q.push(n); vis[n] = 1; depthn[n] = 0; while (!q.empty()) { node = q.front(); q.pop(); for (int x : adj[node]) { if (vis[x]) continue; vis[x] = 1; depthn[x] = depthn[node] + 1; q.push(x); } } vector<pair<int, int> > v; int cek = 0, ee = 0, cekn = 0, een = 0; for (int i = 1; i <= k; i++) { if (depth[a[i]] >= depth[n]) { cek++; ee = a[i]; } if (depthn[a[i]] >= depthn[1]) { cekn++; een = a[i]; } if (cek == 2 || cekn == 2) { cout << depth[n] << endl; return 0; } if (ee != a[i] && een != a[i]) v.push_back(make_pair(depth[a[i]], a[i])); } sort(v.begin(), v.end()); int minn = 1e9; for (int i = 1; i < v.size(); i++) { minn = min(minn, v[i].first - v[i - 1].first); } if (minn < 1e9) ans = depth[n] - max(0, minn - 1); if (cek == 0 && cekn == 0) { cout << ans << endl; return 0; } if (cek == 1 && cekn == 0) { cout << max(ans, min(depth[n], v[k - 2].first + 1 + depthn[ee])) << endl; } else if (cek == 0 && cekn == 1) { cout << max(ans, min(depth[n], depthn[v[0].second] + 1 + depth[een])) << endl; } else { ans = max(ans, min(depth[een] + 1 + depthn[ee], depth[n])); if (v.size() > 0) { ans = max(ans, min(depth[n], v[k - 3].first + 1 + depthn[ee])); ans = max(ans, min(depth[n], depthn[v[0].second] + 1 + depth[een])); } cout << ans << endl; } } |
#include <bits/stdc++.h> int f[1000001]; int main() { int n; scanf( %d , &n); f[0] = 0; f[1] = 1; f[2] = 1; int i, j, k; for (i = 3;; i++) { f[i] = f[i - 1] + f[i - 2]; if (f[i] > 1000000000) break; } int idx = i; int no = 0; for (i = 0; i < idx; i++) { for (j = i; j < idx; j++) { for (k = i; k < idx; k++) { if ((long long)f[i] + (long long)f[j] + (long long)f[k] == n) { no = 1; printf( %d %d %d n , f[i], f[j], f[k]); break; } } if (no) break; } if (no) break; } if (no == 0) printf( I m too stupid to solve this problem n ); scanf( ); } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string s; cin >> s; map<char, vector<int>> ma; for (int i = 0; i < n; i++) { ma[s[i]].push_back(i + 1); } int m; cin >> m; vector<int> ans; while (m--) { string s1; cin >> s1; map<char, int> m1; for (int i = 0; i < s1.size(); i++) { m1[s1[i]]++; } int a = -1; for (auto &i : ma) { if (m1.find(i.first) != m1.end()) { int b = m1[i.first]; a = max(a, i.second[b - 1]); } } ans.push_back(a); } for (int i = 0; i < ans.size(); i++) { cout << ans[i] << n ; } } int main() { ios::sync_with_stdio(0); int t = 1; while (t--) { solve(); } } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_fe1_pre_dec
//
// Generated
// by: lutscher
// on: Tue Jun 23 11:51:21 2009
// cmd: /home/lutscher/work/MIX/mix_1.pl rs_test.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./04/01 12:48:34 wig Exp
//
// Generator: mix_1.pl Revision: 1.3 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_fe1_pre_dec
//
// No user `defines in this module
module rs_fe1_pre_dec
//
// Generated Module rs_fe1_pre_dec_i
//
(
input wire [13:0] addr_i,
output wire pre_dec_o,
output wire pre_dec_err_o
);
// Module parameters:
parameter N_DOMAINS = 2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
/* ------------------------------------------------------------
Generator information:
used package Micronas::Reg is version 1.88
this package RegViews.pm is version 1.93
use with RTL libraries (this release or higher):
ip_ocp/0002/ip_ocp_016_21Jan2009
ip_sync/0001/ip_sync_006_23jan2008
------------------------------------------------------------ */
// pre-address decoder (per clock-domain)
reg pre_dec;
reg pre_dec_err;
assign pre_dec_o = pre_dec;
assign pre_dec_err_o = pre_dec_err;
always @(addr_i) begin
pre_dec = 0;
pre_dec_err = 0;
case (addr_i[5:2])
// clock-domain #0 --> clk_a
'h0, 'h8, 'ha: pre_dec = 0;
// clock-domain #1 --> clk_f20
'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7: pre_dec = 1;
default: begin
pre_dec = 0;
pre_dec_err = 1;
end
endcase
end
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of rs_fe1_pre_dec
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; char ch[6700][3000]; char c[3000]; int vis[2000]; vector<int> ans; int len; void shift(int x, int k) { int num = 0; for (int i = len - 1; i > len - 1 - x; i--) { ch[k][num++] = ch[k - 1][i]; } for (int i = 0; i < len - x; i++) { ch[k][num++] = ch[k - 1][i]; } ch[k][num] = 0 ; } int main() { scanf( %d , &len); scanf( %s , ch[0]); while (ch[0][0] == || ch[0][0] == n || ch[0][0] == r ) scanf( %s , ch[0]); scanf( %s , c); while (c[0] == || c[0] == n || c[0] == r ) scanf( %s , c); if (strlen(c) != strlen(ch[0])) { printf( -1 ); return 0; } for (int i = 0; i < len; i++) { vis[ch[0][i]]++; vis[c[i]]--; } for (int i = a ; i <= z ; i++) { if (vis[i] != 0) { printf( -1 ); return 0; } } int num = 1; for (int i = 1; i <= len; i++) { for (int j = 0; j <= len - i; j++) { if (c[i - 1] == ch[num - 1][j]) { ans.push_back(len - j - 1); ans.push_back(1); ans.push_back(len - 1); shift(len - j - 1, num++); shift(1, num++); shift(len - 1, num++); break; } } } printf( %d n , num - 1); for (int i = 0; i < ans.size(); i++) printf( %d , ans[i]); } |
#include <bits/stdc++.h> using namespace std; int a[505], b[505], n, t; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) { cin >> n; bool ok = 1; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { cin >> b[i]; } if (n & 1) { if (a[n / 2] != b[n / 2]) { cout << NO << endl; continue; } } multiset<pair<int, int>> x, y; for (int i = 0; i < n / 2; i++) { if (a[i] > a[n - 1 - i]) swap(a[i], a[n - 1 - i]); if (b[i] > b[n - 1 - i]) swap(b[i], b[n - 1 - i]); x.insert({a[i], a[n - 1 - i]}); y.insert({b[i], b[n - 1 - i]}); } for (auto v : x) { if (x.count(v) != y.count(v)) { ok = 0; break; } } if (ok) cout << YES << endl; else cout << NO << endl; } return 0; } |
//-----------------------------------------------------------------------------
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_rx_xcorr(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
xcorr_is_848, snoop, xcorr_quarter_freq
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input xcorr_is_848, snoop, xcorr_quarter_freq;
// Carrier is steady on through this, unless we're snooping.
assign pwr_hi = ck_1356megb & (~snoop);
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
reg [2:0] fc_div;
always @(negedge ck_1356megb)
fc_div <= fc_div + 1;
(* clock_signal = "yes" *) reg adc_clk; // sample frequency, always 16 * fc
always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
if (xcorr_is_848 & ~xcorr_quarter_freq) // fc = 847.5 kHz, standard ISO14443B
adc_clk <= ck_1356megb;
else if (~xcorr_is_848 & ~xcorr_quarter_freq) // fc = 423.75 kHz
adc_clk <= fc_div[0];
else if (xcorr_is_848 & xcorr_quarter_freq) // fc = 211.875 kHz
adc_clk <= fc_div[1];
else // fc = kHz
adc_clk <= fc_div[2];
// When we're a reader, we just need to do the BPSK demod; but when we're an
// eavesdropper, we also need to pick out the commands sent by the reader,
// using AM. Do this the same way that we do it for the simulated tag.
reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
if(after_hysteresis)
begin
has_been_low_for <= 7'b0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
has_been_low_for <= has_been_low_for + 1;
end
end
// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
// so we need a 6-bit counter.
reg [5:0] corr_i_cnt;
// And a couple of registers in which to accumulate the correlations.
// We would add at most 32 times the difference between unmodulated and modulated signal. It should
// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
reg signed [11:0] corr_i_accum;
reg signed [11:0] corr_q_accum;
// we will report maximum 8 significant bits
reg signed [7:0] corr_i_out;
reg signed [7:0] corr_q_out;
// clock and frame signal for communication to ARM
reg ssp_clk;
reg ssp_frame;
always @(negedge adc_clk)
begin
corr_i_cnt <= corr_i_cnt + 1;
end
// ADC data appears on the rising edge, so sample it on the falling edge
always @(negedge adc_clk)
begin
// These are the correlators: we correlate against in-phase and quadrature
// versions of our reference signal, and keep the (signed) result to
// send out later over the SSP.
if(corr_i_cnt == 6'd0)
begin
if(snoop)
begin
// Send 7 most significant bits of tag signal (signed), plus 1 bit reader signal
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
after_hysteresis_prev_prev <= after_hysteresis;
end
else
begin
// 8 bits of tag signal
corr_i_out <= corr_i_accum[11:4];
corr_q_out <= corr_q_accum[11:4];
end
corr_i_accum <= adc_d;
corr_q_accum <= adc_d;
end
else
begin
if(corr_i_cnt[3])
corr_i_accum <= corr_i_accum - adc_d;
else
corr_i_accum <= corr_i_accum + adc_d;
if(corr_i_cnt[3] == corr_i_cnt[2]) // phase shifted by pi/2
corr_q_accum <= corr_q_accum + adc_d;
else
corr_q_accum <= corr_q_accum - adc_d;
end
// The logic in hi_simulate.v reports 4 samples per bit. We report two
// (I, Q) pairs per bit, so we should do 2 samples per pair.
if(corr_i_cnt == 6'd32)
after_hysteresis_prev <= after_hysteresis;
// Then the result from last time is serialized and send out to the ARM.
// We get one report each cycle, and each report is 16 bits, so the
// ssp_clk should be the adc_clk divided by 64/16 = 4.
if(corr_i_cnt[1:0] == 2'b10)
ssp_clk <= 1'b0;
if(corr_i_cnt[1:0] == 2'b00)
begin
ssp_clk <= 1'b1;
// Don't shift if we just loaded new data, obviously.
if(corr_i_cnt != 6'd0)
begin
corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
corr_q_out[7:1] <= corr_q_out[6:0];
end
end
// set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
// (send two frames with 8 Bits each)
if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
ssp_frame = 1'b1;
else
ssp_frame = 1'b0;
end
assign ssp_din = corr_i_out[7];
assign dbg = corr_i_cnt[3];
// Unused.
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
endmodule
|
`include "register_set.v"
`include "remap.v"
module register_block(
input logic clk,
input logic reset,
input logic wnr,
input logic [1:0] req,
input logic [7:0] address,
input logic [31:0] data_in,
output logic ack,
output logic [31:0] data_out,
output logic [15:0] sdma_address_low,
output logic [15:0] sdma_address_high,
output logic [15:0] block_size,
output logic [15:0] block_count,
output logic [15:0] argument_0,
output logic [15:0] argument_1,
output logic [15:0] response_0,
output logic [15:0] response_1,
output logic [15:0] response_2,
output logic [15:0] response_3,
output logic [15:0] response_4,
output logic [15:0] response_5,
output logic [15:0] response_6,
output logic [15:0] response_7,
output logic [15:0] buffer_data_port_0,
output logic [15:0] buffer_data_port_1,
output logic [31:0] present_state,
output logic [7:0] host_control,
output logic [7:0] power_control,
output logic [7:0] block_gap_control,
output logic [7:0] wakeup_control,
output logic [15:0] clock_control,
output logic [7:0] timeout_control,
output logic [7:0] software_reset,
output logic [15:0] normal_interrupt_status,
output logic [15:0] error_interruprt_status,
output logic [15:0] normal_interrupt_status_en,
output logic [15:0] error_interruprt_status_en,
output logic [15:0] normal_interrupt_signal_en,
output logic [15:0] error_interruprt_signal_en,
output logic [15:0] auto_cmd_12_error_status,
output logic [31:0] capabilities,
output logic [15:0] capabilities_resrv,
output logic [31:0] max_current_capabilities,
output logic [31:0] max_current_capabilities_resrv,
output logic [15:0] force_event_auto_cmd_12_error_status,
output logic [15:0] force_event_error_interrupt_status,
output logic [8:0] adma_error_status,
output logic [63:0] adma_system_address,
output logic [15:0] slot_interrupt_status,
output logic [15:0] host_controller_version
);
logic [2047:0] mem_data_out;
register_set r( /*AUTOINST*/
.clk(clk),
.reset(reset),
.wnr(wnr),
.req(req),
.address(address),
.mem_data_out(mem_data_out),
.data_out(data_out),
.ack(ack),
.data_in(data_in)
);
remap map( /*AUTOINST*/
.mem_data_out(mem_data_out),
.sdma_address_low(sdma_address_low),
.sdma_address_high(sdma_address_high),
.block_size(block_size),
.block_count(block_count),
.argument_0(argument_0),
.argument_1(argument_1),
.response_0(response_0),
.response_1(response_1),
.response_2(response_2),
.response_3(response_3),
.response_4(response_4),
.response_5(response_5),
.response_6(response_6),
.response_7(response_7),
.buffer_data_port_0(buffer_data_port_0),
.buffer_data_port_1(buffer_data_port_1),
.present_state(present_state),
.host_control(host_control),
.power_control(power_control),
.block_gap_control(block_gap_control),
.wakeup_control(wakeup_control),
.clock_control(clock_control),
.timeout_control(timeout_control),
.software_reset(software_reset),
.normal_interrupt_status(normal_interrupt_status),
.error_interruprt_status(error_interruprt_status),
.normal_interrupt_status_en(normal_interrupt_status_en),
.error_interruprt_status_en(error_interruprt_status_en),
.normal_interrupt_signal_en(normal_interrupt_signal_en),
.error_interruprt_signal_en(error_interruprt_signal_en),
.auto_cmd_12_error_status(auto_cmd_12_error_status),
.capabilities(capabilities),
.capabilities_resrv(capabilities_resrv),
.max_current_capabilities(max_current_capabilities),
.max_current_capabilities_resrv(max_current_capabilities_resrv),
.force_event_auto_cmd_12_error_status(force_event_auto_cmd_12_error_status),
.force_event_error_interrupt_status(force_event_error_interrupt_status),
.adma_error_status(adma_error_status),
.adma_system_address(adma_system_address),
.slot_interrupt_status(slot_interrupt_status),
.host_controller_version(host_controller_version)
);
endmodule // register_block
|
#include <bits/stdc++.h> using namespace std; using i128 = __int128_t; using u128 = __uint128_t; const long long MOD = 998244353; const long double PI = 3.141592653589793238; const long long pi = 31415926; const long long inf = 1000000000000000000; const long long small_inf = INT_MAX; long long int modpow(long long int x, long long int n, long long int mod = MOD) { long long int res = 1; while (n > 0) { if (n & 1) res = res * x % mod; x = x * x % MOD; n >>= 1; } return res; } long long int power(long long int x, long long int n) { long long int res = 1; while (n > 0) { if (n & 1) res = res * x; x = x * x; n >>= 1; } return res; } void init() {} void solve() { int n, m; cin >> n >> m; std::vector<int> v[2][n + 1]; vector<pair<int, pair<long long int, long long int>>> v1[2 * n + 1]; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; v[0][x].push_back(y); v[1][y].push_back(x); v1[x].push_back(make_pair(y, make_pair(0, 1))); v1[n + y].push_back(make_pair(n + x, make_pair(0, 1))); } for (int i = 1; i <= n; i++) { v1[i].push_back(make_pair(n + i, make_pair(1, 0))); v1[n + i].push_back(make_pair(i, make_pair(1, 0))); } std::vector<std::vector<long long>> dist( 2, std::vector<long long int>(n + 1, inf)); dist[0][1] = 0; for (int fu = 0; fu <= 30; fu++) { int f = fu % 2; set<pair<long long int, int>> s; for (int i = 1; i <= n; i++) { if (dist[f][i] != inf) s.insert(make_pair(dist[f][i], i)); } std::vector<int> vis(n + 1, 0); while (!s.empty()) { pair<long long int, int> p = *s.begin(); s.erase(s.begin()); int x = p.second; long long int d = p.first; if (vis[x]) continue; vis[x] = 1; for (auto y : v[f][x]) { if (!vis[y] && d + 1 < dist[f][y]) { dist[f][y] = d + 1; s.insert(make_pair(d + 1, y)); } } } for (int i = 1; i <= n; i++) { dist[f ^ 1][i] = min(dist[f ^ 1][i], dist[f][i] + power(2, fu)); } } if (dist[0][n] != inf || dist[1][n] != inf) { cout << min(dist[0][n], dist[1][n]) % MOD << endl; return; } vector<pair<long long int, long long int>> dis(2 * n + 1, make_pair(inf, inf)); { set<pair<pair<long long int, long long int>, int>> s; for (int i = 1; i <= n; i++) { if (dist[0][i] < inf) dis[i] = make_pair(0, dist[0][i]); s.insert(make_pair(dis[i], i)); } std::vector<int> vis(2 * n + 1, 0); while (!s.empty()) { pair<pair<long long int, long long int>, int> p = *s.begin(); s.erase(s.begin()); if (vis[p.second]) continue; vis[p.second] = 1; int x = p.second; long long int num = p.first.first, d = p.first.second; for (auto y : v1[x]) { if (vis[y.first] || make_pair(num + y.second.first, d + y.second.second) >= dis[y.first]) continue; dis[y.first] = make_pair(num + y.second.first, d + y.second.second); s.insert(make_pair(dis[y.first], y.first)); } } } pair<long long int, long long int> p; if (dis[n].first < dis[2 * n].first) p = dis[n]; else if (dis[2 * n].first < dis[n].first) p = dis[2 * n]; else if (dis[2 * n].second < dis[n].second) p = dis[2 * n]; else p = dis[2 * n + 1]; long long int ans = p.second % MOD; for (int i = 30; i <= 30 + p.first - 1; i++) { ans += modpow(2, i); ans %= MOD; } cout << ans << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); int t23 = 1, tt23 = 1; init(); while (tt23 <= t23) { solve(); tt23++; } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; } |
// -----------------------------------------------------------------------
module uart(
input clk,
input send,
input [7:0] tx_byte,
output [7:0] rx_byte,
output tx_ready,
output rx_ready,
output txd,
input rxd
);
parameter baud;
parameter clk_speed;
localparam prescale = clk_speed/baud;
localparam width = $clog2(prescale+1);
localparam [width-1:0] period = prescale[width-1:0] - 1'b1;
uart_tx #(
.width(width),
.period(period)
) tx(
.clk(clk),
.d(tx_byte),
.txd(txd),
.send(send),
.ready(tx_ready)
);
uart_rx #(
.width(width),
.period(period)
) rx(
.clk(clk),
.d(rx_byte),
.rxd(rxd),
.ready(rx_ready)
);
endmodule
// -----------------------------------------------------------------------
module uart_tx(
input clk,
input [7:0] d,
input send,
output ready,
output txd
);
parameter width;
parameter period;
localparam TX_IDLE = 2'd0;
localparam TX_SEND = 2'd1;
localparam TX_WAIT = 2'd2;
reg [1:0] txstate = TX_IDLE;
reg [width-1:0] divcnt;
reg [3:0] bitcnt;
reg [0:10] txbuf = {11'b11111111111};
always @ (posedge clk) begin
ready <= 0;
case (txstate)
TX_IDLE:
if (send) begin
bitcnt <= 4'd10;
txbuf <= {1'b1, 1'b1, d, 1'b0};
divcnt <= period;
txstate <= TX_WAIT;
end
TX_SEND: begin
txbuf <= {1'b1, txbuf[0:9]};
divcnt <= period;
txstate <= TX_WAIT;
end
TX_WAIT:
if (divcnt != 0) begin
divcnt <= divcnt - 1'd1;
end else begin
if (bitcnt == 1) begin
ready <= 1;
txstate <= TX_IDLE;
end else begin
bitcnt <= bitcnt - 1'd1;
txstate <= TX_SEND;
end
end
endcase
end
assign txd = txbuf[10];
endmodule
// -----------------------------------------------------------------------
module uart_rx(
input clk,
output reg [7:0] d,
output ready,
input rxd
);
parameter width;
parameter period;
localparam halfperiod = period / 2;
localparam RX_IDLE = 2'd0;
localparam RX_START = 2'd1;
localparam RX_DATA = 2'd3;
reg [1:0] rxstate = RX_IDLE;
reg [width-1:0] divcnt;
reg [3:0] bitcnt;
reg [8:0] rxbuf;
always @ (posedge clk) begin
ready <= 0;
case (rxstate)
RX_IDLE:
if (!rxd) begin
divcnt <= period;
rxstate <= RX_START;
end
RX_START:
if (rxd) begin // RXD gone high during the first half of start bit
rxstate <= RX_IDLE;
end else if (divcnt > halfperiod) begin
divcnt <= divcnt - 1'd1;
end else begin
divcnt <= period;
bitcnt <= 4'd9;
rxstate <= RX_DATA;
end
RX_DATA:
if (bitcnt == 0) begin
rxstate <= RX_IDLE;
if (rxd) begin // RXD needs to be high @ stop bit for the frame to be OK
d <= rxbuf[7:0];
ready <= 1;
end
end else if (divcnt != 0) begin
divcnt <= divcnt - 1'd1;
end else begin
divcnt <= period;
bitcnt <= bitcnt - 1'd1;
rxbuf <= {rxd, rxbuf[8:1]};
end
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; int i, ans, j, t; int num[2005]; while (scanf( %d%d , &n, &k) != EOF) { ans = 0; for (i = 0; i < n; i++) scanf( %d , &num[i]); for (i = 0; i < n; i++) for (j = 0; j < n - i - 1; j++) if (num[j] > num[j + 1]) { t = num[j]; num[j] = num[j + 1]; num[j + 1] = t; } for (i = n - 1; i >= 0; i = i - k) ans += (num[i] - 1) * 2; printf( %d n , ans); } } |
#include <bits/stdc++.h> using namespace std; void logf(istream_iterator<string> it) {} template <typename T, typename... Args> void logf(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << ; logf(++it, args...); } const double PI = acos(-1); void solve() { string s; cin >> s; ; reverse(s.begin(), s.end()); int ans = 0; int car = 0; function<void(int)> inc = [&](int idx) { if (idx == s.size()) s += 1 ; else { if (s[idx] == 1 ) { s[idx] = 0 ; inc(idx + 1); } else s[idx] = 1 ; } }; for (size_t i = 0; i + 1 < s.size(); i++) { if (s[i] == 1 ) { inc(i); ans++; } if (i + 1 < s.size()) ans++; } cout << ans << endl; } int main() { cin.tie(nullptr); std::ios::sync_with_stdio(false); solve(); } |
//
// Copyright (c) 2002 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This function captures the correctness of a non-constant delay
* that is internal to a non-blocking assignment.
*/
module main;
reg [7:0] delay = 0;
reg step;
initial begin
delay = 2;
step = 0;
step <= #(delay) 1;
#1 if (step !== 0) begin
$display("FAILED -- step=%b at time=1", step);
$finish;
end
#2 if (step !== 1) begin
$display("FAILED == step=%b at time=3", step);
$finish;
end
$display("PASSED");
end
endmodule // main
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dec_table.v when simulating
// the core, dec_table. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dec_table(
clka,
addra,
douta
);
input clka;
input [7 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("dec_table.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ms__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_ms__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_FUNCTIONAL_V |
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; using namespace std; void file(bool opt) { if (opt && fopen( in.txt , r )) freopen( in.txt , r , stdin), freopen( out.txt , w , stdout); } struct node { double x, y; } point[100000 + 5], tu[100000 + 5]; int tot = 0; int n; double multi(node p0, node p1, node p2) { return (p1.x - p0.x) * (p2.y - p0.y) - (p2.x - p0.x) * (p1.y - p0.y); } double dis(node a, node b) { return (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y); } bool cmp(node a, node b) { double x = multi(a, b, point[1]); if (x > 0 || (x == 0 && dis(a, point[1]) < dis(b, point[1]))) return 1; return 0; } void Graham() { int k = 1; for (int i = 1; i <= n; i++) if (point[i].y < point[k].y || (point[i].y == point[k].y && point[i].x < point[k].x)) k = i; swap(point[1], point[k]); sort(point + 2, point + 1 + n, cmp); tot = 2, tu[1] = point[1], tu[2] = point[2]; for (int i = 3; i <= n; i++) { while (tot >= 1 && multi(tu[tot], tu[tot - 1], point[i]) >= 0) tot--; tu[++tot] = point[i]; } } int main() { file(1); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lf%lf , &point[i].x, &point[i].y); point[i].y = point[i].y - point[i].x * point[i].x; } if (n == 1) { puts( 0 ); return 0; } Graham(); int ans = 0; for (int i = 1; i <= tot; i++) { node a = tu[i], b = tu[(i + 1) > tot ? 1 : (i + 1)], c = {0, (long long)1e15}; if (a.x != b.x) { double x = multi(a, b, c); if (x < 0) ans++; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5, Lim = 18; int tr[maxn * 19][2], nowxor, cnt = 1, siz[maxn * 19], n, m; template <typename T> inline void read(T &x) { char c; int f = 1; while (!isdigit(c = getchar())) (c == - ) && (f = -1); x = c ^ 48; while (isdigit(c = getchar())) x = x * 10 + (c ^ 48); x *= f; } void insert(int x, int u = 1, int now = Lim) { if (now == -1) return siz[u] = 1, void(); int s = x >> now & 1; if (!tr[u][s]) tr[u][s] = ++cnt; insert(x, tr[u][s], now - 1); siz[u] = siz[tr[u][0]] + siz[tr[u][1]]; } inline int query(int x = nowxor) { int u = 1, res = 0; for (int i = Lim; i >= 0; --i) { int s = x >> i & 1; if (siz[tr[u][s]] == ((1 << i))) u = tr[u][s ^ 1], res |= (1 << i); else u = tr[u][s]; if (!u) return res; } return res; } int main() { int x; read(n); read(m); for (int i = 1; i <= n; ++i) read(x), insert(x); while (m--) { read(x); nowxor ^= x; printf( %d n , query()); } return 0; int yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; yy = 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1100000; int n, m; char a[MAXN], b[MAXN]; int s[MAXN], t[MAXN]; inline int id(int x, int y) { if (x < 1 || x > n || y < 1 || y > m) return 0; return (x - 1) * m + y; } bool check(int k) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) if (i - k >= 1 && i + k <= n && j - k >= 1 && j + k <= m && s[id(i + k, j + k)] - s[id(i - k - 1, j + k)] - s[id(i + k, j - k - 1)] + s[id(i - k - 1, j - k - 1)] == 0) b[id(i, j)] = X ; else b[id(i, j)] = . ; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) t[id(i, j)] = t[id(i - 1, j)] + t[id(i, j - 1)] - t[id(i - 1, j - 1)] + (b[id(i, j)] == X ); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { int l1 = max(i - k, 1), r1 = min(i + k, n); int l2 = max(j - k, 1), r2 = min(j + k, m); if (a[id(i, j)] == X && t[id(r1, r2)] - t[id(l1 - 1, r2)] - t[id(r1, l2 - 1)] + t[id(l1 - 1, l2 - 1)] == 0) return 0; } return 1; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , a + (i - 1) * m + 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) s[id(i, j)] = s[id(i - 1, j)] + s[id(i, j - 1)] - s[id(i - 1, j - 1)] + (a[id(i, j)] != X ); int l = 0, r = min(n, m); while (l < r) { int mid = l + r + 1 >> 1; if (check(mid)) l = mid; else r = mid - 1; } printf( %d n , l); check(l); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) putchar(b[id(i, j)]); putchar( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a[101]; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); int i = 1; while (a[i] == a[i - 1] && i < n) i++; if (i == n) printf( NO n ); else printf( %d n , a[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; char s[N], t[N]; int vis[N], vs[N]; int main() { cin >> s + 1 >> t + 1; int j = 1; int n = strlen(s + 1); int m = strlen(t + 1); for (int i = 1; i <= n && j <= m; ++i) { if (s[i] == t[j]) { vis[j] = i; ++j; } } j = m; for (int i = n; i >= 1 && j >= 1; --i) { if (s[i] == t[j]) { vs[j] = i; --j; } } int ans = max(vis[1] - 1, n - vis[m]); ans = max(ans, vs[1] - 1); ans = max(ans, n - vs[m]); for (int i = 1; i <= m; ++i) { ans = max(ans, vs[i] - vis[i - 1] - 1); } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 3, M = 3e4 + 4, inf = 2e9 + 1; int m, n, s, t, cur, tim, mn; int low[N], dfn[N], vis[N], cst[M]; vector<pair<int, int> > vt[N]; vector<int> pat, rut, ans; bool dfs(int u) { vis[u] = 1; if (u == t) return 1; for (int i = 0; i < vt[u].size(); i++) { int v = vt[u][i].first; int id = vt[u][i].second; if (!vis[v] && dfs(v)) { pat.push_back(id); return 1; } } return 0; } bool tarjan(int u, int p = -1) { vis[u] = 1; bool cap = u == t; low[u] = dfn[u] = ++tim; for (int i = 0; i < vt[u].size(); i++) { int v = vt[u][i].first; int id = vt[u][i].second; if (id == cur || id == p) continue; if (vis[v]) low[u] = min(low[u], dfn[v]); else { bool flag = tarjan(v, id); cap = flag || cap; low[u] = min(low[u], low[v]); if (flag && low[v] == dfn[v]) rut.push_back(id); } } return cap; } int main() { scanf( %d%d%d%d , &n, &m, &s, &t); for (int i = 1; i < m + 1; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); vt[u].push_back(make_pair(v, i)); vt[v].push_back(make_pair(u, i)); cst[i] = w; } if (!dfs(s)) { puts( 0 n0 n ); return 0; } mn = inf; for (int i = 0; i < pat.size(); i++) { cur = pat[i]; tim = 0; memset(vis, 0, sizeof(vis)); rut.clear(); if (!tarjan(s)) if (mn > cst[cur]) { mn = cst[cur]; ans.clear(); ans.push_back(cur); } for (int j = 0; j < rut.size(); j++) { int sec = rut[j]; if (mn > cst[sec] + cst[cur]) { mn = cst[sec] + cst[cur]; ans.clear(); ans.push_back(cur); ans.push_back(sec); } } } if (mn == inf) { puts( -1 ); return 0; } int len = ans.size(); printf( %d n%d n%d , mn, len, ans[0]); if (len > 1) printf( %d n , ans[1]); else puts( ); } |
#include <bits/stdc++.h> using namespace std; int u = 1, i = 0, q1, q2, a[100001], s[200002], d[100000], f[100001]; void k(int w) { q2 = w / 2; while (a[s[q2]] > a[q1]) { s[w] = s[q2]; w = q2; q2 /= 2; } s[w] = q1; } void l() { if (i) { i--; k(d[i]); } else { k(u); u++; } } void m() { q1 = 1; q2 = 2; while ((s[q2]) || (s[q2 + 1])) if ((s[q2]) && ((!s[q2 + 1]) || (a[s[q2]] < a[s[q2 + 1]]))) { s[q1] = s[q2]; q1 = q2; q2 = q1 * 2; } else { s[q1] = s[q2 + 1]; q1 = q2 + 1; q2 = q1 * 2; } s[q1] = 0; d[i] = q1; i++; } int main() { int q, w, e, r, t, c, v, y; a[0] = -1; for (w = 0; w < 200002; w++) s[w] = 0; cin >> q >> w; e = t = 0; r = 1; while ((e) || (r <= q)) { while ((e < w) && (r <= q)) { cin >> c >> a[r]; if (t < c) t = c; q1 = r; l(); r++; e++; } y = 0; while (e) { c = a[s[1]]; t += c - y; v = 0; while (a[s[1]] == c) { f[s[1]] = t; m(); e--; v++; } t += 1 + v / 2; y = c; } t += y; } for (e = 1; e <= q; e++) cout << f[e] << ; return 0; } |
/* Module from the schematic_gui program written by Andreas Ehliar <>
This Verilog file is licensed under the CC0 license. */
module mux6 #(parameter WIREWIDTH = 1) (input wire [2:0] s,
input wire [WIREWIDTH:0] d0, d1, d2,d3, d4,d5,
output reg [WIREWIDTH:0] o);
initial begin
$schematic_boundingbox(40,280);
$schematic_polygonstart;
$schematic_coord(10,10);
$schematic_coord(30,30);
$schematic_coord(30,250);
$schematic_coord(10,270);
$schematic_polygonend;
$schematic_linestart;
$schematic_coord(20,19);
$schematic_coord(20,10);
$schematic_lineend;
$schematic_connector(d0,0,40);
$schematic_connector(d1,0,80);
$schematic_connector(d2,0,120);
$schematic_connector(d3,0,160);
$schematic_connector(d4,0,200);
$schematic_connector(d5,0,240);
$schematic_connector(o,40,140);
$schematic_connector(s,20,0);
$schematic_symboltext("0", 20,40);
$schematic_symboltext("1", 20,80);
$schematic_symboltext("2", 20,120);
$schematic_symboltext("3", 20,160);
$schematic_symboltext("4", 20,200);
$schematic_symboltext("5", 20,240);
end
always @* begin
case(s)
0: o = d0;
1: o = d1;
2: o = d2;
3: o = d3;
4: o = d4;
default: o = d5;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.141592653589793238; long long powmod(long long a, long long b) { long long res = 1; a %= 1000000007; for (; b; b >>= 1) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; } return res; } long long fac[1000005]; void factorial(int mx) { fac[0] = 1ll; for (int i = 1; i <= mx; i++) { fac[i] = fac[i - 1] * (long long)i; fac[i] %= 1000000007; } } int main() { factorial(1000005 - 5); int n, m, vol, type; long long ans, cnt = 1ll; scanf( %d , &n); scanf( %d , &m); vector<vector<int> > vec(m); for (int i = 0; i < n; i++) { scanf( %d , &vol); while (vol--) { scanf( %d , &type); vec[type - 1].push_back(i); } } for (int i = 0; i < m; i++) sort(vec[i].begin(), vec[i].end()); sort(vec.begin(), vec.end()); ans = 1ll; for (int i = 1; i <= m - 1; i++) { if (vec[i] == vec[i - 1]) ans *= ++cnt; else cnt = 1; ans %= 1000000007; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, arr[200005]; string swaps; cin >> n; for (int i = 1; i <= n; i++) cin >> arr[i]; cin >> swaps; int m = 0, flag = 0; for (int i = 1; i < n; i++) { m = max(m, arr[i]); if (swaps[i - 1] == 0 && m > i) { flag = 1; break; } } (flag) ? cout << NO n : cout << YES n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); int q; cin >> q; for (int i = 0; i < q; i++) { ll k, n, a, b; cin >> k >> n >> a >> b; if (k - n * b <= 0) { cout << -1 << n ; continue; } ll l = -1, r = n; while (r - l > 1) { ll m = (l + r) / 2; if (k - m * b - (n - m) * a > 0) { r = m; } else { l = m; } } cout << n - r << n ; } } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int INF = 1e9; using ll = long long; using ull = unsigned long long; using vi = vector<int>; using vl = vector<ll>; using vb = vector<bool>; using vc = vector<char>; using vii = vector<vi>; using vll = vector<vl>; using pii = pair<int, int>; using pll = pair<ll, ll>; using vpii = vector<pii>; using vpll = vector<pll>; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vl v(n); ll sum = 0; for (int i = (0); i < (n); i++) { cin >> v[i]; sum += v[i]; } ll m = *max_element(v.begin(), v.end()); sum -= m; if (sum > m) cout << 0 n ; else cout << m - sum + 1 << endl; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:225450978 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const long long Mod = 1000000007LL, INF = 1e9, LINF = 1e18; const long double Pi = 3.141592653589793116, EPS = 1e-9, Gold = ((1 + sqrt(5)) / 2); long long keymod[] = {1000000007LL, 1000000009LL, 1000000021LL, 1000000033LL}; long long keyCount = sizeof(keymod) / sizeof(long long); template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcountll(s); } auto TimeStart = chrono::steady_clock::now(); auto TimeEnd = chrono::steady_clock::now(); void ControlIO(int argc, char* argv[]); void TimerStart(); void TimerStop(); void Exit(); long long n, k, d1, d2; void Input() { cin >> n >> k >> d1 >> d2; } void Solve() { long long A = LINF, B = 0, C = 0; for (long long i = 0; i < 2; i++) { for (long long j = 0; j < 2; j++) { if (i) B = A - d1; else B = A + d1; if (j) C = B - d2; else C = B + d2; if ((k - A - B - C + min(A, min(B, C)) * 3) % 3 != 0 || k - A - B - C + min(A, min(B, C)) * 3 < 0) continue; if ((A + B + C + n - k) % 3 == 0 && (A + B + C + n - k) / 3 >= max(A, max(B, C))) { cout << yes n ; return; } } } cout << no n ; } int main(int argc, char* argv[]) { ControlIO(argc, argv); ios_base::sync_with_stdio(0); cin.tie(NULL); int T; cin >> T; TimerStart(); while (T--) { Input(); Solve(); } TimerStop(); return 0; } void ControlIO(int argc, char* argv[]) {} void TimerStart() {} void TimerStop() {} void Exit() { TimerStop(); exit(0); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:28 11/07/2013
// Design Name:
// Module Name: and_or_array
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module and_or_array
# (parameter width = 8, sel=1) /*Parameter permite la parametrización del modulo, donde se asigna el nombre y tamaño.*/
(input [width-1:0] a, /*declaración de entradas y salidas*/
output y);
genvar i;
wire [width-1:1] x;
generate /*Proporciona datos para producir una determinada cantidad de variables de hardware en función del valor de un parámetro.*/
if (sel==1)
for (i=1; i<width; i=i+1) begin:forloop
if (i == 1)
assign x[1] = a[0] & a[1];
else
assign x[i] = a[i] & x[i-1];
end
else
for (i=1; i<width; i=i+1) begin:forloop
if (i == 1)
assign x[1] = a[0] | a[1];
else
assign x[i] = a[i] | x[i-1];
end
endgenerate
assign y = x[width-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int d, n, a, s = 0, k; scanf( %d , &d); scanf( %d , &n); scanf( %d , &a); for (k = 1; k < n; k++) { s += d - a; scanf( %d , &a); } printf( %d n , s); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int n, m, sx, sy, vx, vy; inline long long int extgcd(long long int a, long long int b, long long int &x, long long int &y) { if (!b) { x = 1; y = 0; return a; } long long int d = extgcd(b, a % b, x, y); long long int _x = y; long long int _y = x - (a / b) * y; x = _x; y = _y; return d; } inline long long int crt(long long int a1, long long int m1, long long int a2, long long int m2) { a1 = (a1 + m1) % m1; a2 = (a2 + m2) % m2; if (a1 > a2) { swap(a1, a2); swap(m1, m2); } long long int x, y; long long int d = extgcd(m1, m2, x, y); if ((a2 - a1) % d) return -1; x *= (a2 - a1) / d; y *= -(a2 - a1) / d; x = (x - (x / (m2 / d)) * m2 / d + m2 / d) % (m2 / d); return m1 * x + a1; } signed main() { cin >> n >> m >> sx >> sy >> vx >> vy; if ((sx == 0 && sy == 0) || (sx == 0 && sy == m) || (sx == n && sy == 0) || (sx == n && sy == m)) { cout << sx << << sy << endl; return 0; } if (!vx) { if (sx == 0) { if (vy == 1) { cout << 0 << m << endl; } else { cout << 0 0 n << endl; } } else if (sx == n) { if (vy == 1) { cout << n << << m << endl; } else { cout << n << << 0 << endl; } } else { cout << -1 << endl; } return 0; } if (!vy) { if (sy == 0) { if (vx == 1) { cout << n << 0 << endl; } else { cout << 0 0 n << endl; } } else if (sy == m) { if (vx == 1) { cout << n << << m << endl; } else { cout << 0 << m << endl; } } else { cout << -1 << endl; } return 0; } long long int T = crt(n - vx * sx, n, m - vy * sy, m); if (T == -1) { cout << -1 << endl; return 0; } long long int X = sx + T * vx; long long int Y = sy + T * vy; X = (X < 0 ? -X : X); Y = (Y < 0 ? -Y : Y); cout << ((X / n) & 1) * n << << ((Y / m) & 1) * m << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Burke
// Engineer: Tom Burke
//
// Create Date: 19:39:14 08/24/2011
// Design Name:
// Module Name: qdiv.v
// Project Name: Fixed-point Math Library (Verilog)
// Target Devices:
// Tool versions: Xilinx ISE WebPack v14.7
// Description: Fixed-point division in (Q,N) format
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.02 - 25 May 2014
// Updated to fix an error
//
// Additional Comments: Based on my description on youtube:
// http://youtu.be/TEnaPMYiuR8
//
//////////////////////////////////////////////////////////////////////////////////
module qdiv #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_dividend,
input [N-1:0] i_divisor,
input i_start,
input i_clk,
output [N-1:0] o_quotient_out,
output o_complete,
output o_overflow
);
reg [2*N+Q-3:0] reg_working_quotient; // Our working copy of the quotient
reg [N-1:0] reg_quotient; // Final quotient
reg [N-2+Q:0] reg_working_dividend; // Working copy of the dividend
reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor
reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
// count to N-1+Q but, computing that number of bits requires a
// logarithm (base 2), and I don't know how to do that in a
// way that will work for everyone
reg reg_done; // Computation completed flag
reg reg_sign; // The quotient's sign bit
reg reg_overflow; // Overflow flag
initial reg_done = 1'b1; // Initial state is to not be doing anything
initial reg_overflow = 1'b0; // And there should be no woverflow present
initial reg_sign = 1'b0; // And the sign should be positive
initial reg_working_quotient = 0;
initial reg_quotient = 0;
initial reg_working_dividend = 0;
initial reg_working_divisor = 0;
initial reg_count = 0;
assign o_quotient_out[N-2:0] = reg_quotient[N-2:0]; // The division results
assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
assign o_complete = reg_done;
assign o_overflow = reg_overflow;
always @( posedge i_clk ) begin
if( reg_done && i_start ) begin // This is our startup condition
// Need to check for a divide by zero right here, I think....
reg_done <= 1'b0; // We're not done
reg_count <= N+Q-1; // Set the count
reg_working_quotient <= 0; // Clear out the quotient register
reg_working_dividend <= 0; // Clear out the dividend register
reg_working_divisor <= 0; // Clear out the divisor register
reg_overflow <= 1'b0; // Clear the overflow register
reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; // Left-align the dividend in its working register
reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; // Left-align the divisor into its working register
reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; // Set the sign bit
end
else if(!reg_done) begin
reg_working_divisor <= reg_working_divisor >> 1; // Right shift the divisor (that is, divide it by two - aka reduce the divisor)
reg_count <= reg_count - 1; // Decrement the count
// If the dividend is greater than the divisor
if(reg_working_dividend >= reg_working_divisor) begin
reg_working_quotient[reg_count] <= 1'b1; // Set the quotient bit
reg_working_dividend <= reg_working_dividend - reg_working_divisor; // and subtract the divisor from the dividend
end
//stop condition
if(reg_count == 0) begin
reg_done <= 1'b1; // If we're done, it's time to tell the calling process
reg_quotient <= reg_working_quotient; // Move in our working copy to the outside world
if (reg_working_quotient[2*N+Q-3:N]>0)
reg_overflow <= 1'b1;
end
else
reg_count <= reg_count - 1;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s, s1, s2; cin >> s >> s1 >> s2; bool lock = false; for (int i = 0; i < s.length(); i++) { if (s[i] == s2[i]) { swap(s1[i], s2[i]); } else { if (s1[i] == s2[i]) { swap(s[i], s2[i]); } else { lock = true; break; } } } if (lock) cout << NO << endl; else { if (s == s1) cout << YES << endl; else cout << NO << endl; } } return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_SYMBOL_V
`define SKY130_FD_SC_LS__BUFBUF_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const double PI = acos(-1.0); const int MOD = 1000 * 1000 * 1000 + 7; const int INF = 2000 * 1000 * 1000; const int MAXN = 200010; template <typename T> inline T sqr(T n) { return n * n; } int n, k; vector<int> g[MAXN]; long long sum[MAXN][7]; long long dp[MAXN]; long long size[MAXN][7]; void dfs(int v, int par = -1) { size[v][0] = 1; for (int to : g[v]) { if (to != par) { dfs(to, v); for (int mod = 1; mod <= k; mod++) { size[v][mod % k] += size[to][mod - 1]; sum[v][mod % k] += sum[to][mod - 1]; } sum[v][0] += size[to][k - 1]; } } for (int m2 = 0; m2 < k; m2++) { long long summ2 = 0, sizem2 = 0; for (int to : g[v]) { if (to != par) { summ2 += sum[to][m2]; sizem2 += size[to][m2]; } } for (int m1 = 0; m1 < k; m1++) { for (int to : g[v]) { if (to != par) { long long osize = sizem2 - size[to][m2]; long long isize = size[to][m1]; dp[v] += sum[to][m1] * osize + (summ2 - sum[to][m2]) * isize; dp[v] += isize * osize * ((m1 + m2 + 2 + k - 1) / k); } } } } for (int m = 0; m < k; m++) { dp[v] += 2 * (sum[v][m] + size[v][m] * (m != 0)); } for (int to : g[v]) { if (to != par) { dp[v] += dp[to]; } } } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } dfs(1); printf( %lld n , dp[1] / 2); return 0; } |
#include <bits/stdc++.h> using namespace std; int f(string s) { int ans = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == 1 ) { ans++; } } return ans; } int main() { string a, b; cin >> a >> b; int c1 = f(a); if (c1 % 2 != 0) { c1++; } if (c1 >= f(b)) { cout << YES << endl; } else { cout << NO << endl; } } |
#include <bits/stdc++.h> using namespace std; int32_t main() { long long n, k; cin >> n >> k; vector<long long> occ(255); string s; cin >> s; long long streak = 0; char curr = s[0]; for (long long i = 0; i < n; i++) { if (s[i] == curr) { streak++; if (streak == k) { occ[curr]++; streak = 0; } } else { streak = 1; curr = s[i]; } } long long mx = 0; for (long long i = 0; i < 255; i++) { mx = max(occ[i], mx); } cout << mx << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, r; long long a; map<int, long long> d; int ans[300010]; int k = 0; ans[0] = 1; cin >> n; for (int i = 1; i <= n; ++i) { scanf( %I64d , &a); if (d[a] > r) { ans[++k] = i; r = i; } else d[a] = i; } if (k) { printf( %i n%i , k, ans[0]); for (int i = 1; i < k; ++i) printf( %i n%i , ans[i], ans[i] + 1); printf( %i , n); } else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(T x) { return x * x; } template <class T> inline T parse(const string &s) { T x; stringstream ss(s); ss >> x; return x; } const double EPS = 1e-12; const int INF = 1000 * 1000 * 1000; const long long LINF = INF * 1ll * INF; const double DINF = 1e200; const double PI = 3.1415926535897932384626433832795l; int gcd(int a, int b) { return a ? gcd(b % a, a) : b; } long long gcd(long long a, long long b) { return a ? gcd(b % a, a) : b; } long long gcdex(long long a, long long b, long long &x, long long &y) { if (!a) { x = 0, y = 1; return b; } long long k = b / a; long long g = gcdex(b - k * a, a, y, x); x -= k * y; return g; } long long inv(long long a, long long m) { assert(m > 1); long long x, y, g; g = gcdex(a, m, x, y); return (x % (m / g) + m / g) % m / g; } long long crt(long long a1, long long m1, long long a2, long long m2) { long long a = (a2 - a1 % m2 + m2) % m2; long long x, y, g; g = gcdex(m1, m2, x, y); if (a % g) return -1; long long m = m1 / g * m2; assert(x + m2 >= 0); x = a / g * (x + m2) % m2; long long r = (a1 + x * m1) % m; assert(r % m1 == a1 && r % m2 == a2); return r; } long long powmod(long long a, long long p, long long m) { assert(p >= 0); long long r = 1; while (p) { if (p & 1) r = r * a % m; p >>= 1; a = a * a % m; } return r; } bool isprime(long long a) { if (a <= 1) return false; for (long long i = 2; i * i <= a; ++i) { if (a % i == 0) return false; } return true; } long long sqrtup(long long a) { if (!a) return 0; long long x = max(0ll, (long long)sqrt((double)a)); while (x * x >= a) --x; while ((x + 1) * (x + 1) < a) ++x; return x + 1; } long long isqrt(long long a) { if (a <= 0) { assert(!a); return 0; } long long x = (long long)sqrt((double)a); while (sqr(x + 1) <= a) ++x; while (x * x > a) --x; return x; } long long sgn(long long x) { return x < 0 ? -1 : x > 0 ? 1 : 0; } template <class T> ostream &operator<<(ostream &s, const vector<T> &v); template <class A, class B> ostream &operator<<(ostream &s, const pair<A, B> &p); template <class K, class V> ostream &operator<<(ostream &s, const map<K, V> &m); template <class T> ostream &operator<<(ostream &s, const set<T> &m); template <class T, size_t N> ostream &operator<<(ostream &s, const array<T, N> &a); template <class... T> ostream &operator<<(ostream &s, const tuple<T...> &t); template <class T> ostream &operator<<(ostream &s, const vector<T> &v) { s << [ ; for (int i = 0; i < (((int)(v).size())); ++i) { if (i) s << , ; s << v[i]; } s << ] ; return s; } template <class A, class B> ostream &operator<<(ostream &s, const pair<A, B> &p) { s << ( << p.first << , << p.second << ) ; return s; } template <class K, class V> ostream &operator<<(ostream &s, const map<K, V> &m) { s << { ; bool f = false; for (const auto &it : m) { if (f) s << , ; f = true; s << it.first << : << it.second; } s << } ; return s; } template <class T> ostream &operator<<(ostream &s, const set<T> &m) { s << { ; bool f = false; for (const auto &it : m) { if (f) s << , ; f = true; s << it; } s << } ; return s; } template <class T> ostream &operator<<(ostream &s, const multiset<T> &m) { s << { ; bool f = false; for (const auto &it : m) { if (f) s << , ; f = true; s << it; } s << } ; return s; } template <class T, class V, class C> ostream &operator<<(ostream &s, const priority_queue<T, V, C> &q) { auto a = q; s << { ; bool f = false; while (!a.empty()) { if (f) s << , ; f = true; s << a.top(); a.pop(); } return s << } ; } template <class T, size_t N> ostream &operator<<(ostream &s, const array<T, N> &a) { s << [ ; for (int i = 0; i < (((int)(a).size())); ++i) { if (i) s << , ; s << a[i]; } s << ] ; return s; } template <class T> ostream &operator<<(ostream &s, const deque<T> &a) { s << [ ; for (int i = 0; i < (((int)(a).size())); ++i) { if (i) s << , ; s << a[i]; } s << ] ; return s; } template <size_t n, class... T> struct put1 { static ostream &put(ostream &s, const tuple<T...> &t) { s << get<sizeof...(T) - n>(t); if (n > 1) s << , ; return put1<n - 1, T...>::put(s, t); } }; template <class... T> struct put1<0, T...> { static ostream &put(ostream &s, const tuple<T...> &t) { return s; } }; template <class... T> ostream &operator<<(ostream &s, const tuple<T...> &t) { s << ( ; put1<sizeof...(T), T...>::put(s, t); s << ) ; return s; } ostream &put3(ostream &s, const char *, bool) { return s; } template <class U, class... T> ostream &put3(ostream &s, const char *f, bool fs, U &&u, T &&...t) { while (*f == ) ++f; if (!fs) s << , ; auto nf = f; int d = 0; while (*nf && (*nf != , || d)) { if (*nf == ( ) ++d; else if (*nf == ) ) --d; ++nf; } auto nf2 = nf; while (nf2 > f && *(nf2 - 1) == ) --nf; fs = *f == ; if (!fs) { s.write(f, nf2 - f); s << = ; }; s << u; if (fs) s << ; if (*nf) ++nf; return put3(s, nf, fs, forward<T>(t)...); } vector<pair<string, string>> solve() { vector<pair<string, string>> R; R.push_back(make_pair( init carry , ddd0uuu )); const int L = 40; for (int i = 0; i < (L); ++i) { string andup = uu10dtr0uel10dddttrudtedddl ; string xordown = d10utled0r0uduuutt1ludtru ; string stepdown = d10ut ; R.push_back(make_pair( pad up , uuued0sdt0uudtddd )); R.push_back(make_pair( pad down , ddeu0sut0ddutuu )); R.push_back(make_pair( x and y , andup)); R.push_back(make_pair( x xor y , xordown)); R.push_back(make_pair( xy xor c , ddd + xordown)); R.push_back(make_pair( xy and c , andup)); R.push_back(make_pair( not1 , uuuu01dt )); R.push_back(make_pair( not2 , u01ut )); R.push_back(make_pair( carry and , d + andup)); R.push_back(make_pair( carry not , uu01ut )); R.push_back(make_pair( 6 steps down , )); for (int j = 0; j < (6); ++j) R.back().second += stepdown; R.push_back(make_pair( carry left , l10rtuuu )); } R.push_back(make_pair( go to ans , rddddd )); R.push_back(make_pair( unpad , )); for (int i = 0; i < (L); ++i) R.back().second += rlt ; return R; } string concat(const vector<pair<string, string>> &S) { string r; for (auto &p : S) r += p.second; return r; } map<pair<int, int>, char> A; void putnum(int a, int x, int y) { while (a) { A[make_pair(x, y)] = 0 + a % 2; a /= 2; --x; } } string bin(int a) { string r; while (a) { r += (char)( 0 + a % 2); a /= 2; } reverse((r).begin(), (r).end()); return r; } string readout(int x, int y) { string r; while (A.count(make_pair(x, y))) { r += A.at(make_pair(x, y)); ++x; } return r; } string sim(const vector<pair<string, string>> &S) { vector<pair<char, char>> st; int x = 0, y = 0; for (auto &sub : S) { for (char c : sub.second) { if (c == t ) { if (A.count(make_pair(x, y))) { int cnt = A.at(make_pair(x, y)) - 0 + 1; for (int qq = 0; qq < (cnt); ++qq) { if (st.empty()) break; c = st.back().first; char pr = st.back().second; st.pop_back(); if (c == 0 || c == 1 || c == e ) { if (!pr) A.erase(make_pair(x, y)); else A[make_pair(x, y)] = pr; continue; } if (c == l ) ++x; else if (c == r ) --x; else if (c == u ) --y; else if (c == d ) ++y; else assert(c == s ); } } } else { st.push_back(make_pair(c, - )); if (c == 0 || c == 1 || c == e ) { st.back().second = A[make_pair(x, y)]; if (c == e ) A.erase(make_pair(x, y)); else A[make_pair(x, y)] = c; } else if (c == l ) --x; else if (c == r ) ++x; else if (c == u ) ++y; else if (c == d ) --y; else assert(c == s ); } } } return readout(x, y); } void test() { auto S = solve(); for (int s = 2; s <= 100; ++s) { for (int a = 1; a < s; ++a) { A.clear(); putnum(a, 0, 0); putnum(s - a, 0, 1); string r = sim(S); string b = bin(s); if (r != b) { do { } while (false); return; } } } do { } while (false); } int main(int argc, char **argv) { ios_base::sync_with_stdio(false); cin.tie(0); cout.precision(20); srand(time(0)); cout << concat(solve()); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_2_V
`define SKY130_FD_SC_LP__O41A_2_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_2_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k; pair<string, int> A[11]; int main() { scanf( %i , &n); for (int i = 0; i < 7; i++) A[i].second = 2e7; for (int i = 0; i < n; i++) { string s; int p; cin >> p >> s; sort(s.begin(), s.end()); if (s == ABC ) A[0] = make_pair(s, min(A[0].second, p)); else if (s == AB ) A[1] = make_pair(s, min(A[1].second, p)); else if (s == AC ) A[2] = make_pair(s, min(A[2].second, p)); else if (s == BC ) A[3] = make_pair(s, min(A[3].second, p)); else if (s == A ) A[4] = make_pair(s, min(A[4].second, p)); else if (s == B ) A[5] = make_pair(s, min(A[5].second, p)); else if (s == C ) A[6] = make_pair(s, min(A[6].second, p)); } int ans = 2e7; for (int i = 0; i < 1 << 7; i++) { int occ[3] = {0}; int cost = 0; for (int j = 0; j < 7; j++) { if (i & 1 << j) { for (int k = 0; k < A[j].first.size(); k++) occ[A[j].first[k] - A ]++; cost += A[j].second; } } if (occ[0] && occ[1] && occ[2]) ans = min(cost, ans); } printf( %i n , ans == 2e7 ? -1 : ans); } |
#include <bits/stdc++.h> using namespace std; int n, c; int a[1 << 20], b[1 << 20]; char tp[1 << 20]; int hs[128][128]; int ne[128][128]; int li[128]; bool getDP(int l, int r) { if (hs[l][r] != -1) return hs[l][r]; if (l >= r) { return (hs[l][r] = 1); } hs[l][r] = 0; for (int k = l; k <= r; ++k) { bool ok = true; for (int i = 0; i < c; ++i) { if (a[i] == l) { if (tp[i] == L && b[i] > k) ok = false; if (tp[i] == R && b[i] <= k) ok = false; } if (a[i] > l && a[i] <= k) { if (b[i] > k) ok = false; } } if (ok) { if (getDP(l + 1, k) && getDP(k + 1, r)) { ne[l][r] = k; hs[l][r] = 1; break; } } } return hs[l][r]; } int le[1 << 20], ri[1 << 20]; void cli(int l, int r) { if (l >= r) return; li[l] = ne[l][r]; if (li[l] > l) { le[l] = l + 1; cli(l + 1, li[l]); } if (li[l] < r) { ri[l] = li[l] + 1; cli(li[l] + 1, r); } } vector<int> sl; void sol(int v) { if (le[v] != -1) sol(le[v]); sl.push_back(v); if (ri[v] != -1) sol(ri[v]); } int main() { scanf( %d %d , &n, &c); char buf[32]; for (int i = 0; i < c; i++) { scanf( %d %d %s , &a[i], &b[i], buf); tp[i] = buf[0]; if (a[i] >= b[i]) { printf( IMPOSSIBLE n ); return 0; } } memset(hs, -1, sizeof(hs)); bool ok = getDP(1, n); if (!ok) { printf( IMPOSSIBLE n ); return 0; } memset(li, -1, sizeof(li)); memset(le, -1, sizeof(le)); memset(ri, -1, sizeof(ri)); cli(1, n); sol(1); for (int i = 0; i + 1 < (int)sl.size(); i++) { printf( %d , sl[i]); } printf( %d n , sl.back()); return 0; } |
#include <bits/stdc++.h> const int LG = 21; const int N = 500005; const long long MOD = 1e9 + 7; const long long INF = 1e9; const long long INFLL = 1e18; using namespace std; void dfs(int v, int paint, vector<int> &col, vector<vector<pair<int, int> > > &graph, vector<int> &need, int &cnt0, int &cnt1, int &fl) { col[v] = paint; if (paint == -1) cnt0++; else cnt1++; if (need[v] != 0) { if (paint == need[v]) fl = 1; else fl = -1; } for (auto p : graph[v]) { if (col[p.first] == 0) { dfs(p.first, p.second * paint, col, graph, need, cnt0, cnt1, fl); } } } int root[N]; vector<int> suns[N]; int cntsame[N]; int sametoroot[N]; int fl[N]; int ans; int Root(int x) { return root[x] == x ? x : Root(root[x]); } void complete_data(int v, int FL) { int x = Root(v); if (fl[x] != 0) return; FL *= sametoroot[v]; int took_before = min(cntsame[x], (int)suns[x].size() - cntsame[x]); ans -= took_before; fl[x] = FL; if (FL == 1) ans += cntsame[x]; else ans += suns[x].size() - cntsame[x]; } void Merge(int v, int u, int w) { int x = Root(v), y = Root(u); if (x == y) return; if (suns[x].size() > suns[y].size()) { swap(v, u); swap(x, y); } w *= sametoroot[v]; w *= sametoroot[u]; if (fl[x] == 0 && fl[y] == 0) { ans -= min(cntsame[x], (int)suns[x].size() - cntsame[x]); ans -= min(cntsame[y], (int)suns[y].size() - cntsame[y]); } if (fl[x] == 0 && fl[y] != 0) { complete_data(x, fl[y] * w); } if (fl[x] != 0 && fl[y] == 0) { complete_data(y, fl[x] * w); } for (auto u : suns[x]) { suns[y].push_back(u); sametoroot[u] *= w; if (sametoroot[u] == 1) cntsame[y]++; } if (fl[x] == 0 && fl[y] == 0) { ans += min(cntsame[y], (int)suns[y].size() - cntsame[y]); } root[x] = y; } signed main() { srand(time(NULL)); ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; string s; cin >> s; vector<vector<int> > contains(n); for (int i = 0; i < k; i++) { int c; cin >> c; for (int j = 0; j < c; j++) { int x = 0; cin >> x; x--; contains[x].push_back(i); } } vector<vector<pair<int, int> > > graph(k); vector<int> need(k, 0); for (int i = 0; i < k; i++) root[i] = i; for (int i = 0; i < k; i++) suns[i].push_back(i); for (int i = 0; i < k; i++) cntsame[i] = 1; for (int i = 0; i < k; i++) sametoroot[i] = 1; for (int i = 0; i < n; i++) { if (contains[i].size() == 1) { if (s[i] == 1 ) { need[contains[i][0]] = -1; complete_data(contains[i][0], -1); } else { need[contains[i][0]] = 1; complete_data(contains[i][0], 1); } } if (contains[i].size() == 2) { if (s[i] == 0 ) { graph[contains[i][0]].push_back({contains[i][1], -1}); graph[contains[i][1]].push_back({contains[i][0], -1}); Merge(contains[i][0], contains[i][1], -1); } else { graph[contains[i][0]].push_back({contains[i][1], 1}); graph[contains[i][1]].push_back({contains[i][0], 1}); Merge(contains[i][0], contains[i][1], 1); } } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n); int ans = 0, cnt = 0; for (int i = 0; i < n; i++) { cin >> v[i]; } for (int i = 0; i < n; i++) { if (v[i] == i) ans++; else if (v[v[i]] == i) { cnt = 1; } } cout << min(ans + cnt + 1, n); return 0; } |
#include <bits/stdc++.h> using namespace std; const int LN = 18, maxn = (1 << LN); const long long mod = (long long)(998244353); int fact[maxn], inv_fact[maxn], poww_r[maxn], poww_inv_r[maxn]; int mul(long long a, long long b) { long long ret = (a * b) % mod; return (int)(ret); } int add(int a, int b) { int ret = a + b; if (ret >= mod) { ret -= mod; } return ret; } int poww(int a, int b) { int x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = mul(x, y); } y = mul(y, y); b /= 2; } return x; } void build() { fact[0] = 1; for (int i = 1; i < maxn; i++) { fact[i] = mul(fact[i - 1], i); } inv_fact[maxn - 1] = poww(fact[maxn - 1], mod - 2); for (int i = maxn - 2; i >= 0; i--) { inv_fact[i] = mul(inv_fact[i + 1], i + 1); } } int C(int n, int r) { int num = fact[n], den = mul(inv_fact[r], inv_fact[n - r]); return mul(num, den); } vector<int> upper; const int r = 3, inv_r = poww(r, mod - 2); void pre() { int zz = poww(r, (mod - 1) >> LN), curr = 1; for (int i = 0; i < maxn; i++) { poww_r[i] = curr; curr = mul(curr, zz); } for (int i = 0; i < maxn; i++) { poww_inv_r[i] = (i == 0) ? 1 : poww_r[maxn - i]; } fact[0] = 1; for (int i = 1; i < maxn; i++) { fact[i] = mul(fact[i - 1], i); } inv_fact[maxn - 1] = poww(fact[maxn - 1], mod - 2); for (int i = maxn - 2; i >= 0; i--) { inv_fact[i] = mul(inv_fact[i + 1], i + 1); } } void fft(vector<int> &a, bool invert) { int n = a.size(); for (int i = 1, j = 0; i < n; i++) { int bit = n >> 1; for (; j >= bit; bit >>= 1) { j -= bit; } j += bit; if (i < j) { swap(a[i], a[j]); } } for (int len = 2; len <= n; len <<= 1) { int additive = maxn / len; for (int i = 0; i < n; i += len) { int now = 0; for (int j = 0; j < len / 2; j++) { int u = a[i + j], v = mul(a[i + j + len / 2], invert ? poww_inv_r[now] : poww_r[now]); a[i + j] = add(u, v); a[i + j + len / 2] = add(u, mod - v); now += additive; } } } } vector<int> mult(vector<int> &a, vector<int> &b) { int sz = 1; while (sz < max(a.size(), b.size())) { sz *= 2; } sz *= 2; vector<int> fa(sz), fb(sz); for (int i = 0; i < a.size(); i++) { fa[i] = a[i]; } for (int i = 0; i < b.size(); i++) { fb[i] = b[i]; } fft(fa, false); fft(fb, false); for (int i = 0; i < sz; i++) { fa[i] = mul(fa[i], fb[i]); } fft(fa, true); int inv_sz = poww(sz, mod - 2); for (int i = 0; i < sz; i++) { fa[i] = mul(fa[i], inv_sz); } while (fa.back() == 0) { fa.pop_back(); } return fa; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); build(); pre(); int n, m, k; cin >> n >> m >> k; upper.resize(k + 1); upper[0] = 1; int last_used = n; for (int i = 1; i <= k; i++) { upper[i] = mul(upper[i - 1], last_used); last_used--; } vector<int> p1(k + 1), p2(k + 1); int curr = 1; for (int i = 0; i <= k; i++) { p1[i] = mul(poww(i, k), inv_fact[i]); p2[i] = mul(curr, inv_fact[i]); curr = mul(curr, mod - 1); } vector<int> res = mult(p1, p2); int ans = 0, inv = poww(m, mod - 2), curr_inv = inv; for (int i = 1; i <= min(n, k); i++) { int curr = mul(upper[i], curr_inv); curr = mul(curr, res[i]); ans = add(ans, curr); curr_inv = mul(curr_inv, inv); } cout << ans << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision
///////////////////////////////////////////////////////////////////////////////
module ODDR #(
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter INIT = 1'b0,
parameter SRTYPE = "SYNC"
) (
output Q,
input C,
input CE,
input D1,
input D2,
input R,
input S
);
reg q_out = INIT, qd2_posedge_int;
wire c_in;
wire ce_in;
wire d1_in;
wire d2_in;
wire gsr_in;
wire r_in;
wire s_in;
buf buf_c(c_in, C);
buf buf_ce(ce_in, CE);
buf buf_d1(d1_in, D1);
buf buf_d2(d2_in, D2);
buf buf_q(Q, q_out);
buf buf_r(r_in, R);
buf buf_s(s_in, S);
initial begin
if((INIT != 0) && (INIT != 1)) begin
$display("Attribute Syntax Error : The attribute INIT on ODDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT);
$finish;
end
if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on ODDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", DDR_CLK_EDGE);
$finish;
end
if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on ODDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end
always @(r_in, s_in) begin
if(r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b0;
assign qd2_posedge_int = 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b1;
assign qd2_posedge_int = 1'b1;
end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q_out;
deassign qd2_posedge_int;
end else if(r_in == 1'b0 && s_in == 1'b0) begin
deassign q_out;
deassign qd2_posedge_int;
end
end
always @(posedge c_in) begin
if(r_in == 1'b1) begin
q_out <= 1'b0;
qd2_posedge_int <= 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1) begin
q_out <= 1'b1;
qd2_posedge_int <= 1'b1;
end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q_out <= d1_in;
qd2_posedge_int <= d2_in;
end
end
always @(negedge c_in) begin
if(r_in == 1'b1)
q_out <= 1'b0;
else if(r_in == 1'b0 && s_in == 1'b1)
q_out <= 1'b1;
else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
if(DDR_CLK_EDGE == "SAME_EDGE")
q_out <= qd2_posedge_int;
else if(DDR_CLK_EDGE == "OPPOSITE_EDGE")
q_out <= d2_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (scanf( %d , &n) == 1) { if (n == 1) printf( -1 n ); else if (n == 2) { printf( 2 2 n ); } else if (n == 4) printf( 4 2 n ); else { int a, b; if (n % 2 == 0) { a = n - 2; b = 2; } else { a = n - 1; b = 2; } printf( %d %d n , a, b); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_1_V
`define SKY130_FD_SC_LS__O32AI_1_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_PP_SYMBOL_V
`define SKY130_FD_SC_LP__ISO0N_PP_SYMBOL_V
/**
* iso0n: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B,
input KAGND ,
input VPB ,
input VPWR ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, res[300010], c[300010], trie[300010][30], dif[300010], ans, cans; vector<vector<int> > gr; string s; void merge(int big, int small) { dif[big] = 1; for (int i = 0; i < 26; ++i) { if (trie[small][i] and trie[big][i]) { merge(trie[big][i], trie[small][i]); } else if (trie[small][i] and trie[big][i] == 0) { trie[big][i] = trie[small][i]; } dif[big] += dif[trie[big][i]]; } } void dfs(int x, int par) { dif[x] = 1; for (auto i : gr[x]) { if (i == par) { continue; } dfs(i, x); int xCh = trie[x][s[i - 1] - a ]; if (!xCh) { trie[x][s[i - 1] - a ] = i; dif[x] += dif[i]; } else { dif[x] -= dif[xCh]; merge(xCh, i); dif[x] += dif[xCh]; } } res[x] = dif[x] + c[x]; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; gr.resize(n + 1, vector<int>()); for (int i = 1; i <= n; ++i) { cin >> c[i]; } cin >> s; for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; gr[u].push_back(v); gr[v].push_back(u); } dfs(1, -1); for (int i = 1; i <= n; ++i) { ans = max(ans, res[i]); } for (int i = 1; i <= n; ++i) { if (res[i] == ans) { ++cans; } } cout << ans << n ; cout << cans; } |
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module registers(
input rst,
input clk,
input write_enable,
input [REG_WIDTH-1 : 0] rs1_offset,
input [REG_WIDTH-1 : 0] rs2_offset,
input [REG_WIDTH-1 : 0] rd_offset,
input [WIDTH-1 : 0] rd_data_in,
output [WIDTH-1 : 0] rs1_data_out,
output [WIDTH-1 : 0] rs2_data_out);
parameter REG_WIDTH = 5;
parameter WIDTH = 32;
parameter STACK_REG = 2;
parameter STACK_START = 1024; //1k
localparam REG_COUNT = 1 << REG_WIDTH;
reg [WIDTH-1 : 0] regs [0 : REG_COUNT-1];
`ifdef IVERILOG
integer i;
initial begin
for (i = 0; i < REG_COUNT; i = i + 1) begin
regs[i] = 0;
end
end
`endif
assign rs1_data_out = regs[rs1_offset];
assign rs2_data_out = regs[rs2_offset];
always @(posedge clk) begin
if (rst) begin
regs[2] <= STACK_START;
end else begin
if (write_enable && (rd_offset != 0)) begin
regs[rd_offset] <= rd_data_in;
end
end
end
endmodule
|
// This module generate M single 2*HW-1 bit vector each T time steps
module stimulus #(parameter W = 8, M = 200, MAX = 256) (
input bit clk, reset,
output reg [W-1:0] x
);
int i;
initial begin
@(negedge reset);
for (i = 0; i < M; i=i+1) begin
@(negedge clk);
x = {$random} % MAX;
end
end
endmodule
module test;
parameter M = 200; // number of test vectors
parameter W = 8; // bit width of input vecotrs
parameter T = 10; // for timing
parameter D = 8; // depth of pipeline, MAX of 8
parameter K = 10; // distance between boundaries of pipeline
parameter S = 2*M*T + 12*D;
parameter MAX = D*K;
bit clk =0, reset = 0;
wire [W-1:0] xin;
wire [W-1:0] din = K;
wire [W-1:0] dout, bout, xout;
wire [2:0] lin = 3'b111; // -1 in fact
wire [2:0] lout;
int x_gold; // for computing expected result
initial forever #T clk = ~clk;
stimulus #(W, M, MAX) stim (.clk(clk), .reset(reset), .x(xin));
diq_array #(W, D) duv (.clk(clk), .reset(reset),
.din(din), .bin(8'd0), .xin(xin), .lin(lin),
.dout(dout), .bout(bout), .xout(xout),
.lout(lout) );
initial begin: checking
@(negedge reset);
@(posedge clk);
repeat (D) @(negedge clk);
forever begin
@(posedge clk);
#1;
// checking dout
if (dout !== din) begin
$display("ERROR");
$finish;
end
// checking bout
if (bout !== MAX) begin
$display("ERROR");
$finish;
end
// checking lout
x_gold = xout-1; // dirty fix, for example xin = 30 muste be reported as 2
if (lout !== x_gold/K) begin
$display("ERROR");
$finish;
end
end
end
initial begin
doreset();
#S;
$display("PASSED");
$finish;
end
task doreset;
begin
@(negedge clk);
reset = 1;
repeat (5) @(negedge clk);
reset = 0;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_4_V
`define SKY130_FD_SC_HS__A41OI_4_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; int e = max(c, d); if (e > 2 * c || e > 2 * d || e >= b) { cout << -1; return 0; } cout << 2 * a << endl << 2 * b << endl << e; return 0; } |
module tb_sync_merge;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire a1; // From U_SYNC_MERGE of sync_merge.v
wire a2; // From U_SYNC_MERGE of sync_merge.v
wire r0; // From U_SYNC_MERGE of sync_merge.v
// End of automatics
reg r1,r2;
reg reset_n;
/* sync_merge AUTO_TEMPLATE(
); */
sync_merge U_SYNC_MERGE (
/*AUTOINST*/
// Outputs
.a1 (a1),
.a2 (a2),
.r0 (r0),
// Inputs
.r1 (r1),
.r2 (r2),
.a0 (a0),
.reset_n (reset_n));
assign #120 a0 = r0;
initial begin
$dumpfile("tb.vcd");
$dumpvars(0,tb_sync_merge);
end
initial begin
reset_n <= 'b0;
r1 <= 'b0;
r2 <= 'b0;
#100;
reset_n <= 'b1;
#1000;
r1 <= 'b1;
#1000;
r1 <= 'b0;
#1000;
r2 <= 'b1;
#1000;
r2 <= 'b0;
#1000;
$display("-I- Done !");
$finish;
end
endmodule // tb_sync_merge
/*
Local Variables:
verilog-library-directories:(
"."
".."
)
End:
*/
|
#include <bits/stdc++.h> int n, m, c[256]; int main() { int a, j; scanf( %d%d , &n, &m); memset(c, -1, sizeof(c)); for (int i = 0; i < n; ++i) { scanf( %d , &a); if (~c[a]) printf( %d , c[a]); else { j = a; while (j && !~c[j - 1] && j > a - m + 1) --j; if (j && ~c[j - 1] && a - c[j - 1] < m) c[j] = c[j - 1]; else c[j] = j; for (int k = j + 1; k <= a; ++k) c[k] = c[j]; printf( %d , c[j]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int Ans[1001], A[1001], B[1001], C[1001], D[1001], E[1001]; int value(int Arr[], int i, int j, int k) { return (Arr[j] - Arr[i]) * (Arr[k] - Arr[i]); } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> A[i] >> B[i] >> C[i] >> D[i] >> E[i]; } int index = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (j != i) { for (int k = 0; k < n; k++) { if (k != i && k != j) { if ((value(A, i, j, k) + value(B, i, j, k) + value(C, i, j, k) + value(D, i, j, k) + value(E, i, j, k)) > 0) { Ans[i] = -1; break; } } } } } } int count = 0; for (int i = 0; i < n; i++) { if (Ans[i] != -1) { count++; } } cout << count << endl; for (int i = 0; i < n; i++) { if (Ans[i] != -1) { cout << i + 1 << endl; count++; } } return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file ram_13x28_15x7.v when simulating
// the core, ram_13x28_15x7. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module ram_13x28_15x7(
clka,
dina,
addra,
wea,
douta,
clkb,
dinb,
addrb,
web,
doutb);
input clka;
input [27 : 0] dina;
input [12 : 0] addra;
input [0 : 0] wea;
output [27 : 0] douta;
input clkb;
input [6 : 0] dinb;
input [14 : 0] addrb;
input [0 : 0] web;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_8 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("ram_13x28_15x7.mif"),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(28),
.C_READ_WIDTH_B(7),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(28),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.DINA(dina),
.ADDRA(addra),
.WEA(wea),
.DOUTA(douta),
.CLKB(clkb),
.DINB(dinb),
.ADDRB(addrb),
.WEB(web),
.DOUTB(doutb),
.ENA(),
.REGCEA(),
.SSRA(),
.ENB(),
.REGCEB(),
.SSRB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram_13x28_15x7 is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; void debug_out() { cerr << endl; } template <class T> ostream& prnt(ostream& out, T v) { out << v.size() << n ; for (auto e : v) out << e << ; return out; } template <class T> ostream& operator<<(ostream& out, vector<T> v) { return prnt(out, v); } template <class T> ostream& operator<<(ostream& out, set<T> v) { return prnt(out, v); } template <class T1, class T2> ostream& operator<<(ostream& out, map<T1, T2> v) { return prnt(out, v); } template <class T1, class T2> ostream& operator<<(ostream& out, pair<T1, T2> p) { return out << ( << p.first << << p.second << ) ; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } const long double PI = acos(-1); int n, m, c, st[2 * 20005], dr[2 * 20005], a, b; bool uz[20005]; vector<int> v[2 * 20005]; bool cup(int nod) { uz[nod] = 1; for (auto it : v[nod]) { if (!dr[it]) { dr[it] = nod; st[nod] = it; return 1; } } for (auto it : v[nod]) { if (!uz[dr[it]] && cup(dr[it])) { dr[it] = nod; st[nod] = it; return 1; } } return 0; } struct edge { int a, b, c; }; vector<edge> E2; int _try(int x) { for (int i = 0; i <= 2 * n + 1; i++) { v[i].clear(); } memset(st, 0, sizeof(st)); memset(dr, 0, sizeof(dr)); for (auto it : E2) { if (it.c > x) continue; v[it.a].push_back(it.b); v[it.b].push_back(it.a); } int ok = 1; while (ok) { ok = 0; memset(uz, 0, sizeof(uz)); for (int i = 1; i <= n; i++) if (!st[i] && !uz[i]) ok |= cup(i); } int nr = 0; for (int i = 1; i <= n; i++) if (st[i]) nr++; return nr == n; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (long long i = 1; i <= m; i++) { int p, q, c; cin >> p >> q >> c; q += n; E2.push_back({p, q, c}); } int p = 1, st = 0; for (; p <= 1e9; p <<= 1) ; for (; p >= 1; p >>= 1) { if (st + p < 1e9 && !_try(st + p)) { st += p; } } st++; if (!_try(st)) { cout << -1 n ; } else cout << st << n ; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF_INTERMDISABLE (O, I, IBUFDISABLE, INTERMDISABLE);
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
wire out_val;
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE")) begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on IBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE.", SIM_DEVICE);
$finish;
end
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? I : (IBUFDISABLE == 1)? out_val : 1'bx;
end
"FALSE" : begin
assign O = I;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPVGND2_PP_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_2_V
`define SKY130_FD_SC_HS__O2111AI_2_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111ai_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_2_V
|
#include <bits/stdc++.h> using namespace std; int a, b, c, x, y, z, st; int proc(int l, int r) { if (l > r) return (l - r) / 2; return l - r; } int main() { scanf( %d%d%d , &a, &b, &c); scanf( %d%d%d , &x, &y, &z); st = 0; st += proc(a, x); st += proc(b, y); st += proc(c, z); if (st >= 0) puts( Yes ); else puts( No ); } |
// Fetch-Issue Pipeline Register
module iss_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire enable,
// PC related inputs from fetch stage
input wire[31:0] next_pc_iss_pipe_reg_i,
input wire[31:0] instr_iss_pipe_reg_i,
input wire brn_pred_iss_pipe_reg_i,
input wire[31:0] curr_pc_iss_pipe_reg_i,
input wire[31:0] next_pred_pc_iss_pipe_reg_i,
// Register outputs
output wire[31:0] next_pc_iss_pipe_reg_o,
output wire[31:0] instr_iss_pipe_reg_o,
output wire brn_pred_iss_pipe_reg_o,
output wire[31:0] curr_pc_iss_pipe_reg_o,
output wire[31:0] next_pred_pc_iss_pipe_reg_o
);
reg [31:0] next_pc_iss_pipe_reg;
reg [31:0] instr_iss_pipe_reg;
reg brn_pred_iss_pipe_reg;
reg [31:0] curr_pc_iss_pipe_reg;
reg [31:0] next_pred_pc_iss_pipe_reg;
assign next_pc_iss_pipe_reg_o = next_pc_iss_pipe_reg;
assign instr_iss_pipe_reg_o = instr_iss_pipe_reg;
assign brn_pred_iss_pipe_reg_o = brn_pred_iss_pipe_reg;
assign curr_pc_iss_pipe_reg_o = curr_pc_iss_pipe_reg;
assign next_pred_pc_iss_pipe_reg_o = next_pred_pc_iss_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
next_pc_iss_pipe_reg <= 31'b0;
instr_iss_pipe_reg <= 31'b0;
brn_pred_iss_pipe_reg <= 31'b0;
curr_pc_iss_pipe_reg <= 31'b0;
next_pred_pc_iss_pipe_reg <= 31'b0;
end
else if (~enable)
begin
next_pc_iss_pipe_reg <= next_pc_iss_pipe_reg_i;
instr_iss_pipe_reg <= instr_iss_pipe_reg_i;
brn_pred_iss_pipe_reg <= brn_pred_iss_pipe_reg_i;
curr_pc_iss_pipe_reg <= curr_pc_iss_pipe_reg_i;
next_pred_pc_iss_pipe_reg <= next_pred_pc_iss_pipe_reg_i;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_aluaddsub.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_aluaddsub
// Description: This block implements addition and subtraction.
// It takes two operands, a carry_in, plus two control signals
// (subtract and use_cin). If subtract is high, then rs2_data
// is subtracted from rs1_data. If use_cin is high, then
// carry_in is added to the sum (addition) or subtracted from
// the result (subtraction). It outputs the result of the
// specified operation. To keep the cin calculation from
// being in the critical path, it is moved into the d-stage.
// All other calculations are in the e-stage.
*/
module sparc_exu_aluaddsub
(/*AUTOARG*/
// Outputs
adder_out, spr_out, alu_ecl_cout64_e_l, alu_ecl_cout32_e,
alu_ecl_adderin2_63_e, alu_ecl_adderin2_31_e,
// Inputs
clk, se, byp_alu_rs1_data_e, byp_alu_rs2_data_e, ecl_alu_cin_e,
ifu_exu_invert_d
);
input clk;
input se;
input [63:0] byp_alu_rs1_data_e; // 1st input operand
input [63:0] byp_alu_rs2_data_e; // 2nd input operand
input ecl_alu_cin_e; // carry in
input ifu_exu_invert_d; // subtract used by adder
output [63:0] adder_out; // result of adder
output [63:0] spr_out; // result of sum predict
output alu_ecl_cout64_e_l;
output alu_ecl_cout32_e;
output alu_ecl_adderin2_63_e;
output alu_ecl_adderin2_31_e;
wire [63:0] rs2_data; // 2nd input to adder
wire [63:0] rs1_data; // 1st input to adder
wire [63:0] subtract_d;
wire [63:0] subtract_e;
wire cout64_e;
////////////////////////////////////////////
// Module implementation
////////////////////////////////////////////
assign subtract_d[63:0] = {64{ifu_exu_invert_d}};
dff_s #(64) sub_dff(.din(subtract_d[63:0]), .clk(clk), .q(subtract_e[63:0]), .se(se),
.si(), .so());
assign rs1_data[63:0] = byp_alu_rs1_data_e[63:0];
assign rs2_data[63:0] = byp_alu_rs2_data_e[63:0] ^ subtract_e[63:0];
assign alu_ecl_adderin2_63_e = rs2_data[63];
assign alu_ecl_adderin2_31_e = rs2_data[31];
sparc_exu_aluadder64 adder(.rs1_data(rs1_data[63:0]), .rs2_data(rs2_data[63:0]),
.cin(ecl_alu_cin_e), .adder_out(adder_out[63:0]),
.cout32(alu_ecl_cout32_e), .cout64(cout64_e));
assign alu_ecl_cout64_e_l = ~cout64_e;
// sum predict
sparc_exu_aluspr spr(.rs1_data(rs1_data[63:0]), .rs2_data(rs2_data[63:0]), .cin(ecl_alu_cin_e),
.spr_out(spr_out[63:0]));
endmodule // sparc_exu_aluaddsub
|
#include <bits/stdc++.h> using namespace std; const int TAM = 100000 + 15; const long long MOD = 1000000007LL; const double PI = 3.14159265359; long long add(long long x, long long y) { return (x + y + 2 * MOD) % MOD; } long long mult(long long x, long long y) { return (add(x, 0) * add(y, 0)) % MOD; } long long fast_expo(long long x, long long y) { if (x == 0) return 0; if (y == 0) return 1; long long res = 1; long long mid = fast_expo(x, y / 2); if (y % 2 != 0) res = x; return mult(mult(mid, mid), res); } long long inver(long long x) { return fast_expo(x, MOD - 2); } long long gcd(long long e1, long long e2) { if (e2 == 0) return e1; return gcd(e2, e1 % e2); } int n; map<int, int> mapa[TAM]; int color[TAM]; vector<int> G[TAM]; long long dom[TAM]; int tam[TAM]; int cant[TAM]; void dfs_tam(int u, int pd = -1) { tam[u] = 1; for (int v : G[u]) { if (v != pd) { dfs_tam(v, u); tam[u] += tam[v]; } } } void dfs(int u, int pd = -1) { int m = -1, val = -1; for (int v : G[u]) { if (v != pd) { if (tam[v] > val) { m = v; val = tam[v]; } } } if (m == -1) { mapa[u][color[u]]++; dom[u] = color[u]; cant[u] = 1; return; } for (int v : G[u]) { if (v != pd) { dfs(v, u); } } swap(mapa[u], mapa[m]); dom[u] = dom[m]; cant[u] = cant[m]; mapa[u][color[u]]++; if (mapa[u][color[u]] > cant[u]) { cant[u] = mapa[u][color[u]]; dom[u] = 1LL * color[u]; } else if (mapa[u][color[u]] == cant[u]) { dom[u] += 1LL * color[u]; } for (int v : G[u]) { if (v != pd && v != m) { int k, t; for (map<int, int>::iterator it = mapa[v].begin(); it != mapa[v].end(); it++) { k = it->first; t = it->second; mapa[u][k] += t; if (mapa[u][k] > cant[u]) { cant[u] = mapa[u][k]; dom[u] = 1LL * k; } else if (mapa[u][k] == cant[u]) { dom[u] += 1LL * k; } } } } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &color[i]); int u, v; for (int i = 0; i < n - 1; i++) { scanf( %d%d , &u, &v); G[u - 1].push_back(v - 1); G[v - 1].push_back(u - 1); } dfs_tam(0); dfs(0); for (int i = 0; i < n; i++) cout << 1LL * dom[i] << ; cout << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S2S_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLYMETAL6S2S_PP_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s2s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S2S_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { double t, n, i, x, mx, mn, f, j, s, r, y, c, m, k = 0, W, H, x1, y1, w, h, w1, h1, l, u, d, sw, sh, X, Y, X1, X2, R; cin >> t; while (t--) { cin >> W >> H; cin >> x >> y >> x1 >> y1; cin >> w >> h; w1 = abs(x - x1); h1 = abs(y - y1); sw = W - w1; sh = H - h1; if (sw < w && sh < h) cout << -1 << endl; else { r = W - x1; l = x; u = H - y1; d = y; if (max(r, l) >= w || max(u, d) >= h) printf( %0.7lf n , k); else { X = max(r, l); Y = max(u, d); X = w - X; Y = h - Y; if (X > min(r, l)) R = Y; else if (Y > min(u, d)) R = X; else R = min(X, Y); printf( %0.7lf n , R); } } } } |
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 2-11-2018
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
module jt12_pg_inc (
input [ 2:0] block,
input [10:0] fnum,
input signed [8:0] pm_offset,
output reg [16:0] phinc_pure
);
reg [11:0] fnum_mod;
always @(*) begin
fnum_mod = {fnum,1'b0} + {{3{pm_offset[8]}},pm_offset};
case ( block )
3'd0: phinc_pure = { 7'd0, fnum_mod[11:2] };
3'd1: phinc_pure = { 6'd0, fnum_mod[11:1] };
3'd2: phinc_pure = { 5'd0, fnum_mod[11:0] };
3'd3: phinc_pure = { 4'd0, fnum_mod, 1'd0 };
3'd4: phinc_pure = { 3'd0, fnum_mod, 2'd0 };
3'd5: phinc_pure = { 2'd0, fnum_mod, 3'd0 };
3'd6: phinc_pure = { 1'd0, fnum_mod, 4'd0 };
3'd7: phinc_pure = { fnum_mod, 5'd0 };
endcase
end
endmodule // jt12_pg_inc |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: msu_databuf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module msu_databuf (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [13:0] rdaddress;
input [13:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]"
// Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int n, a, b, k, q; int added[200055]; struct BIT { int dat[200055]; void add(int id, int val) { while (id < n) { dat[id] += val; id |= (id + 1); } } int sum(int id) { int ret = 0; while (id >= 0) { ret += dat[id]; id = (id & (id + 1)) - 1; } return ret; } } B1, B2; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k >> a >> b >> q; int ope, x, y; while (q--) { cin >> ope; if (ope == 1) { cin >> x >> y; x--; if (added[x] < b) { B2.add(x, min(y, b - added[x])); } if (added[x] < a) { B1.add(x, min(y, a - added[x])); added[x] = min(a, added[x] + y); } } else { cin >> x; x--; y = x + k - 1; cout << B1.sum(n - 1) - B1.sum(y) + B2.sum(x - 1) << n ; } } return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port arbitrated multiplexer (64 bit datapath)
*/
module axis_arb_mux_64_4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid,
output wire input_0_axis_tready,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid,
output wire input_1_axis_tready,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid,
output wire input_2_axis_tready,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid,
output wire input_3_axis_tready,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
wire [3:0] request;
wire [3:0] acknowledge;
wire [3:0] grant;
wire grant_valid;
wire [1:0] grant_encoded;
assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
assign request[0] = input_0_axis_tvalid & ~acknowledge[0];
assign acknowledge[1] = input_1_axis_tvalid & input_1_axis_tready & input_1_axis_tlast;
assign request[1] = input_1_axis_tvalid & ~acknowledge[1];
assign acknowledge[2] = input_2_axis_tvalid & input_2_axis_tready & input_2_axis_tlast;
assign request[2] = input_2_axis_tvalid & ~acknowledge[2];
assign acknowledge[3] = input_3_axis_tvalid & input_3_axis_tready & input_3_axis_tlast;
assign request[3] = input_3_axis_tvalid & ~acknowledge[3];
// mux instance
axis_mux_64_4 #(
.DATA_WIDTH(DATA_WIDTH)
)
mux_inst (
.clk(clk),
.rst(rst),
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid & grant[0]),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid & grant[1]),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid & grant[2]),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid & grant[3]),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
// arbiter instance
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_2_V
`define SKY130_FD_SC_HD__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_8_V
`define SKY130_FD_SC_LP__BUF_8_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_8_V
|
#include <bits/stdc++.h> using namespace std; int arr[1003][1003]; int n, m; int dp[1003][1003]; int vis[1003][1003]; int dx[4] = {0, 1, 0, -1}; int dy[4] = {1, 0, -1, 0}; int dfs(int i, int j, int x) { if (vis[i][j] == 2) { printf( Poor Inna! n ); exit(0); } if (dp[i][j] != -1) return dp[i][j]; vis[i][j] = 2; int temp2 = 0; int temp3 = 0; if (arr[i][j] == 3) temp3 = 1; for (int k = 0; k < 4; k++) { int ee = i + dx[k]; int rr = j + dy[k]; if (ee >= 0 & ee < n && rr >= 0 && rr < m && arr[ee][rr] == (x + 1) % 4) { temp2 = max(temp2, dfs(ee, rr, (x + 1) % 4)); } } temp2 += temp3; vis[i][j] = 1; if (arr[i][j] == 0) dp[i][j] = temp2; return temp2; } int main() { char temp; for (int i = 0; i < 1003; i++) for (int j = 0; j < 1003; j++) { dp[i][j] = -1; vis[i][j] = 0; } scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> temp; if (temp == D ) arr[i][j] = 0; if (temp == I ) arr[i][j] = 1; if (temp == M ) arr[i][j] = 2; if (temp == A ) arr[i][j] = 3; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (arr[i][j] == 0 && vis[i][j] == 0) { int temp1 = dfs(i, j, 0); } } int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (ans < dp[i][j]) ans = dp[i][j]; if (ans == 0) printf( Poor Dima! n ); else printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, i, j, x, k; cin >> n >> k; string s, t; cin >> s; t = s; for (i = 0; i < n; i++) { if (i - k >= 0) t[i] = t[i - k]; } if (t > s) { cout << n << n << t; return 0; } for (i = 0; i < n; i++) { if (s[i] > t[i]) { for (j = k - 1; j >= 0; j--) { if (t[j] != 9 ) break; } for (; j < n; j += k) t[j]++; break; } } for (j = 0; j < k; j++) if (s[j] < t[j]) break; for (i = j + 1; i < k; i++) { for (long long p = i; p < n; p += k) t[p] = 0 ; } cout << n << n << t; } |
#include <bits/stdc++.h> using namespace std; int cp(int a, int b) { return a > b; } int main() { int a[55], i, j, k, l, coun, flag; int n; scanf( %d%d , &n, &k); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } sort(a + 1, a + n + 1, cp); if (k <= n) { for (i = 1; i <= k; i++) { printf( 1 %d n , a[i]); } } else { for (i = 1; i <= n; i++) { printf( 1 %d n , a[i]); } coun = n; flag = 0; for (i = 2; i <= n; i++) { for (j = i; j <= n; j++) { printf( %d , i); for (l = 1; l < i; l++) { printf( %d , a[l]); } printf( %d n , a[j]); coun++; if (coun >= k) { flag = 1; break; } } if (flag == 1) { break; } } } return 0; } |
#include<bits/stdc++.h> #define ll long long #define ii pair<ll,ll> #define x first #define y second using namespace std; const long o=200005; ll n,it[2][4*o]; ii a[o]; vector<ii>p[2]; void build(long db,long x,long l,long r) { if(l==r) { it[db][x]=p[db][l].y; return; } long mid=(l+r)>>1; build(db,2*x,l,mid); build(db,2*x+1,mid+1,r); it[db][x]=min(it[db][2*x],it[db][2*x+1]); } ll get(long db,long x,long l,long r,long u,long v) { if(u>v || v<l || u>r) return 1e9; if(u<=l && r<=v) return it[db][x]; long mid=(l+r)>>1; return min(get(db,2*x,l,mid,u,v),get(db,2*x+1,mid+1,r,u,v)); } int main() { ios::sync_with_stdio(false);cin.tie(0);cout.tie(0); cin>>n; for(long i=1;i<=n;i++) cin>>a[i].x; ll kq=0; for(long i=1;i<=n;i++) { cin>>a[i].y; if(a[i].x<a[i].y)p[0].push_back({a[i].y,a[i].x}); if(a[i].x>a[i].y)p[1].push_back(a[i]); kq+=abs(a[i].x-a[i].y); } sort(p[0].begin(),p[0].end()); sort(p[1].begin(),p[1].end()); if(p[0].size()==0 || p[1].size()==0) { cout<<kq; return 0; } build(0,1,0,p[0].size()-1); build(1,1,0,p[1].size()-1); ll l=0,r=1e9; while(l<r) { ll mid=(l+r+1)>>1; bool ok=0; for(long i=0;i<p[0].size();i++) if(p[0][i].x-p[0][i].y>=mid) { long vt=lower_bound(p[1].begin(),p[1].end(),ii(p[0][i].y+mid,0))-p[1].begin(); if(get(1,1,0,p[1].size()-1,vt,p[1].size()-1)<=p[0][i].y) { ok=1; break; } } for(long i=0;i<p[1].size();i++) if(p[1][i].x-p[1][i].y>=mid) { long vt=lower_bound(p[0].begin(),p[0].end(),ii(p[1][i].y+mid,0))-p[0].begin(); if(get(0,1,0,p[0].size()-1,vt,p[0].size()-1)<=p[1][i].y) { ok=1; break; } } if(ok)l=mid; else r=mid-1; } cout<<kq-l*2; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_SYMBOL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd2 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; struct Tpoint { double x, y; Tpoint() {} Tpoint(double _x, double _y) { x = _x; y = _y; } inline void read() { scanf( %lf%lf , &x, &y); } inline void show() { printf( %lf %lf n , x, y); } inline double norm() { return sqrt(((x) * (x)) + ((y) * (y))); } }; inline Tpoint operator+(const Tpoint &a, const Tpoint &b) { return Tpoint(a.x + b.x, a.y + b.y); } inline Tpoint operator-(const Tpoint &a, const Tpoint &b) { return Tpoint(a.x - b.x, a.y - b.y); } inline Tpoint operator*(const Tpoint &a, const double &b) { return Tpoint(a.x * b, a.y * b); } inline Tpoint operator/(const Tpoint &a, const double &b) { return Tpoint(a.x / b, a.y / b); } inline double det(const Tpoint &a, const Tpoint &b) { return a.x * b.y - a.y * b.x; } inline double dot(const Tpoint &a, const Tpoint &b) { return a.x * b.x + a.y * b.y; } const int maxn = 100005; bool mark[(1 << 20) + 10]; int n, a[maxn], last[maxn][20]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } for (int i = 0; i < 20; ++i) { last[n][i] = n; } for (int i = n - 1; i >= 0; --i) { memcpy(last[i], last[i + 1], sizeof(last[i])); for (int j = 0; j < 20; ++j) { if (a[i] >> j & 1) { last[i][j] = i; } } } for (int i = 0; i < n; ++i) { int x = a[i], pos = i + 1; mark[x] = true; while (1) { int u = -1; for (int j = 0; j < 20; ++j) { if (x >> j & 1) { continue; } if (u == -1 || last[pos][j] < last[pos][u]) { u = j; } } if (u == -1 || last[pos][u] >= n) { break; } pos = last[pos][u]; x |= a[pos]; mark[x] = true; pos++; } } int res = 0; for (int i = 0; i < 1 << 20; ++i) { res += mark[i]; } printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read(void) { int sum = 0, sign = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) sign = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { sum = sum * 10 + ch - 0 ; ch = getchar(); } return sum * sign; } const int maxn = 2e5 + 5; typedef long long ll; int main() { int T = read(); for (int cas = 1; cas <= T; cas++) { string str; cin >> str; int bol = 0; for (int i = str.length() - 1; i >= 1; i--){ if (bol == 0 && str[i] == 0 && str[i - 1] == 0 ) bol = 1; if (bol == 1 && str[i] == 1 && str[i - 1] == 1 ) bol = 2; } if (bol == 2) cout << NO n ; else cout << YES n ; } return 0; } |
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "uart_defs.v"
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module uart_periph
(
// General - Clocking & Reset
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
output intr_o /*verilator public*/,
// UART
output tx_o /*verilator public*/,
input rx_i /*verilator public*/,
// Peripheral bus
input [7:0] addr_i /*verilator public*/,
output reg [31:0] data_o /*verilator public*/,
input [31:0] data_i /*verilator public*/,
input we_i /*verilator public*/,
input stb_i /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter UART_DIVISOR = 1;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [7:0] uart_tx_data_q;
wire [7:0] uart_rx_data_w;
reg uart_wr_q;
reg uart_rd_q;
wire uart_tx_busy_w;
wire uart_rx_ready_w;
wire uart_break_w;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
// UART
uart
#(
.UART_DIVISOR(UART_DIVISOR)
)
u1_uart
(
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(uart_tx_data_q),
.data_o(uart_rx_data_w),
.wr_i(uart_wr_q),
.rd_i(uart_rd_q),
.tx_busy_o(uart_tx_busy_w),
.rx_ready_o(uart_rx_ready_w),
.break_o(uart_break_w),
.rxd_i(rx_i),
.txd_o(tx_o)
);
//-----------------------------------------------------------------
// Peripheral Register Write
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
uart_tx_data_q <= 8'h00;
uart_wr_q <= 1'b0;
end
else
begin
uart_wr_q <= 1'b0;
// Write Cycle
if (we_i & stb_i)
begin
case (addr_i)
`UART_UDR :
begin
uart_tx_data_q <= data_i[7:0];
uart_wr_q <= 1'b1;
end
default :
;
endcase
end
end
end
//-----------------------------------------------------------------
// Peripheral Register Read
//-----------------------------------------------------------------
always @ *
begin
data_o = 32'h00000000;
case (addr_i[7:0])
`UART_USR :
begin
data_o[`UART_USR_RX_AVAIL] = uart_rx_ready_w;
data_o[`UART_USR_TX_BUSY] = uart_tx_busy_w;
end
`UART_UDR :
data_o[7:0] = uart_rx_data_w;
default :
data_o = 32'h00000000;
endcase
end
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
uart_rd_q <= 1'b0;
end
else
begin
// Read UART data register?
if (!we_i && stb_i && (addr_i[7:0] == `UART_UDR))
uart_rd_q <= 1'b1;
else
uart_rd_q <= 1'b0;
end
end
//-----------------------------------------------------------------
// Assignments
//-----------------------------------------------------------------
assign intr_o = uart_rx_ready_w;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int days[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; struct date { int arr[3]; void read() { string s; cin >> s; for (int i = 0; i < 3; i++) { arr[i] = (s[i * 3] - 0 ) * 10 + (s[i * 3 + 1] - 0 ); } } void next() { next_permutation(arr, arr + 3); } bool valid() { if (arr[1] > 12) return false; if (arr[0] > (days[arr[1] - 1] + (arr[1] == 2 && arr[2] % 4 == 0))) return false; return true; } bool operator<=(const date& oth) const { for (int i = 2; i >= 0; i--) { if (arr[i] != oth.arr[i]) { return arr[i] < oth.arr[i]; } } return true; } }; int main() { date a, b; a.read(); b.read(); for (int i = 0; i < 6; i++) { if (b.valid()) { b.arr[2] += 18; if (b <= a) { cout << YES n ; return 0; } b.arr[2] -= 18; } b.next(); } cout << NO n ; } |
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int test = 1; cin >> test; while (test--) { string s; cin >> s; int a = -1, b = -1, c = -1; int ans = s.size(); for (int i = 0; i < s.size(); i++) { if (s[i] == 1 ) a = i; else if (s[i] == 2 ) b = i; else c = i; if (a != -1 && b != -1 && c != -1) { int x = min(a, min(b, c)); int y = max(a, max(b, c)); ans = min(ans, y - x + 1); } } if (a != -1 && b != -1 && c != -1) cout << ans << n ; else cout << 0 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; char a[1001][1001]; int main() { long long n, m, i, j, s = 0; cin >> n >> m; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) cin >> a[i][j]; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { if (a[i][j] == f && a[i + 1][j] == a && a[i][j + 1] == c && a[i + 1][j + 1] == e ) s++; if (a[i][j] == f && a[i + 1][j] == a && a[i][j + 1] == e && a[i + 1][j + 1] == c ) s++; if (a[i][j] == f && a[i + 1][j] == c && a[i][j + 1] == a && a[i + 1][j + 1] == e ) s++; if (a[i][j] == f && a[i + 1][j] == c && a[i][j + 1] == e && a[i + 1][j + 1] == a ) s++; if (a[i][j] == f && a[i + 1][j] == e && a[i][j + 1] == c && a[i + 1][j + 1] == a ) s++; if (a[i][j] == f && a[i + 1][j] == e && a[i][j + 1] == a && a[i + 1][j + 1] == c ) s++; if (a[i][j] == a && a[i + 1][j] == f && a[i][j + 1] == c && a[i + 1][j + 1] == e ) s++; if (a[i][j] == a && a[i + 1][j] == f && a[i][j + 1] == e && a[i + 1][j + 1] == c ) s++; if (a[i][j] == a && a[i + 1][j] == c && a[i][j + 1] == f && a[i + 1][j + 1] == e ) s++; if (a[i][j] == a && a[i + 1][j] == c && a[i][j + 1] == e && a[i + 1][j + 1] == f ) s++; if (a[i][j] == a && a[i + 1][j] == e && a[i][j + 1] == f && a[i + 1][j + 1] == c ) s++; if (a[i][j] == a && a[i + 1][j] == e && a[i][j + 1] == c && a[i + 1][j + 1] == f ) s++; if (a[i][j] == c && a[i + 1][j] == f && a[i][j + 1] == a && a[i + 1][j + 1] == e ) s++; if (a[i][j] == c && a[i + 1][j] == f && a[i][j + 1] == e && a[i + 1][j + 1] == a ) s++; if (a[i][j] == c && a[i + 1][j] == a && a[i][j + 1] == f && a[i + 1][j + 1] == e ) s++; if (a[i][j] == c && a[i + 1][j] == a && a[i][j + 1] == e && a[i + 1][j + 1] == f ) s++; if (a[i][j] == c && a[i + 1][j] == e && a[i][j + 1] == f && a[i + 1][j + 1] == a ) s++; if (a[i][j] == c && a[i + 1][j] == e && a[i][j + 1] == a && a[i + 1][j + 1] == f ) s++; if (a[i][j] == e && a[i + 1][j] == f && a[i][j + 1] == c && a[i + 1][j + 1] == a ) s++; if (a[i][j] == e && a[i + 1][j] == f && a[i][j + 1] == a && a[i + 1][j + 1] == c ) s++; if (a[i][j] == e && a[i + 1][j] == c && a[i][j + 1] == f && a[i + 1][j + 1] == a ) s++; if (a[i][j] == e && a[i + 1][j] == c && a[i][j + 1] == a && a[i + 1][j + 1] == f ) s++; if (a[i][j] == e && a[i + 1][j] == a && a[i][j + 1] == f && a[i + 1][j + 1] == c ) s++; if (a[i][j] == e && a[i + 1][j] == a && a[i][j + 1] == c && a[i + 1][j + 1] == f ) s++; } cout << s; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/22/2015 09:35:04 AM
// Design Name:
// Module Name: pwm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Enable signal is assumed to synchronous; if enable transitions low during pwm pulse,
// pulse will gracefully complete
//
//////////////////////////////////////////////////////////////////////////////////
module pwm #(CLK_PERIOD = 1000)(
input clk,
input enable,
input [31:0] pwm_period,
output out
);
reg clk_out=1'b0;
reg [31:0] counter = 32'b0;
always @(posedge clk)
begin
if (enable == 1'b1)
begin
if (counter < pwm_period)
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
if (counter < (CLK_PERIOD-1))
begin
clk_out <= 1'b0;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end //end if counter < pwm_period
end //end if(enable)
else
begin
if ((counter > 0) && (counter < pwm_period) ) //gracefully end the last pwm if it has begun
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end
end
assign out = clk_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 0; i < n; i++) { cout << 1 ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const double EPS = 1e-10; inline double SQR(double x) { return x * x; } inline long long SQR(long long x) { return x * x; } inline int SQR(int x) { return x * x; } inline double SQR3(double x) { return x * x * x; } inline void DEBUG() { puts( jackie ); } inline bool zero(double x) { return abs(x) < EPS; } inline int inInt() { int x = 0, c; while ((unsigned int)((c = getchar()) - 0 ) >= 10) { if ( - == c) return -inInt(); } do { x = (x << 3) + (x << 1) + (c - 0 ); } while ((unsigned int)((c = getchar()) - 0 ) < 10); return x; } inline void outInt(int x) { if (x < 0) { putchar( - ); x = -x; } if (x >= 10) outInt(x / 10); putchar((x % 10) + 0 ); } const int MAXN = 1100000; char a[MAXN], b[MAXN]; int len; int dpa[MAXN], dpb[MAXN]; int DPb(int s); int DPa(int s) { if (-1 != dpa[s]) { return dpa[s]; } if (s == len) return 0; int ans = 0; switch (a[s]) { case 0: { ans = min(DPa(s + 1), 1 + DPb(s + 1)); break; } case 1: { ans = DPa(s + 1) + 1; break; } } dpa[s] = ans; return ans; } int DPb(int s) { if (-1 != dpb[s]) return dpb[s]; if (s == len) return 0; int ans; switch (b[s]) { case 0: { ans = min(DPa(s + 1) + 1, DPb(s + 1)); break; } case 1: { ans = DPb(s + 1) + 1; break; } } dpb[s] = ans; return dpb[s]; } int main() { a[0] = 0 ; gets(a + 1); len = strlen(a); for (int i = 0; i < len; i++) a[i] -= 0 ; for (int i = 0; i < len; i++) b[i] = 1 - a[i]; b[len - 1]++; int x = len - 1; while (b[x] > 1) { b[x] = 0; b[x - 1]++; x--; } memset(dpa, -1, sizeof(dpa)); memset(dpb, -1, sizeof(dpb)); int ans = DPa(0); printf( %d n , ans); int s = 0; int flag = 0; while (s < len) { switch (flag) { case 0: { switch (a[s]) { case 0: { if (DPa(s + 1) != DPa(s)) { flag = 1 - flag; printf( +2^%d n , len - s - 1); } break; } case 1: { printf( +2^%d n , len - s - 1); break; } } break; } case 1: { switch (b[s]) { case 0: { if (DPb(s + 1) != DPb(s)) { flag = 1 - flag; printf( -2^%d n , len - 1 - s); } break; } case 1: { printf( -2^%d n , len - 1 - s); break; } } break; } } s++; } return 0; } |
#include <bits/stdc++.h> inline int Get() { char ch; while ((ch = getchar()) < 0 || ch > 9 ) ; int Num = ch - 0 ; while ((ch = getchar()) >= 0 && ch <= 9 ) Num = (Num << 3) + (Num << 1) + ch - 0 ; return Num; } const int M = 3e3 + 5; const int m = 3000; int n, a[M][M], s[M][M], r[M][M], d[M][M]; int main() { n = Get(); for (int i = 1; i <= n; ++i) { int x0 = Get(), y0 = Get(), x1 = Get(), y1 = Get(); for (int x = x0 + 1; x <= x1; ++x) for (int y = y0 + 1; y <= y1; ++y) a[x][y] = i; } for (int i = 1; i <= m; ++i) for (int j = 1; j <= m; ++j) s[i][j] = (!a[i][j]) + s[i][j - 1] + s[i - 1][j] - s[i - 1][j - 1]; for (int i = m; ~i; --i) for (int j = m; ~j; --j) { r[i][j] = a[i][j + 1] == a[i + 1][j + 1] ? 0 : r[i][j + 1] + 1; d[i][j] = a[i + 1][j] == a[i + 1][j + 1] ? 0 : d[i + 1][j] + 1; } for (int i = 0; i < m; ++i) for (int j = 0; j < m; ++j) for (int k = 1; k <= r[i][j] && k <= d[i][j] && !(s[i + k][j + k] - s[i][j + k] - s[i + k][j] + s[i][j]); ++k) if (k <= r[i + k][j] && k <= d[i][j + k]) { std ::vector<int> ans; for (int x = i + 1; x <= i + k; ++x) for (int y = j + 1; y <= j + k; ++y) ans.push_back(a[x][y]); std ::sort(ans.begin(), ans.end()), ans.erase(std ::unique(ans.begin(), ans.end()), ans.end()); printf( YES %d n , ans.size()); for (int k = 0, sze = ans.size(); k < sze; ++k) printf( %d , ans[k]); putchar( n ); return 0; } puts( NO ); return 0; } |
//date:2016/3/13
//engineer:ZhaiShaoMin
//module name: pipeline register between id and ex
module core_id_ex(//input
clk,
rst,
// inst_lo,
wb_reg_write,
wb_memtoreg,
mem_memread,
mem_memwrite,
mem_ll_mem,
mem_sc_mem,
regdst,
aluop,
alusrc,
regread1,
regread2,
sign_extend,
reg_rs,
reg_rt,
reg_rd,
//output
// ex_inst_lo,
ex_wb_reg_write,
ex_wb_memtoreg,
ex_mem_memread,
ex_mem_memwrite,
ex_mem_ll_mem,
ex_mem_sc_mem,
ex_regdst,
ex_aluop,
ex_alusrc,
ex_regread1,
ex_regread2,
ex_sign_extend,
ex_reg_rs,
ex_reg_rt,
ex_reg_rd);
//input
input clk;
input rst;
//input [15:0] inst_lo;
input wb_reg_write;
input wb_memtoreg;
input mem_memread;
input mem_memwrite;
input mem_ll_mem;
input mem_sc_mem;
input regdst;
input [1:0] aluop;
input alusrc;
input [31:0] regread1;
input [31:0] regread2;
input [31:0] sign_extend;
input [4:0] reg_rs;
input [4:0] reg_rt;
input [4:0] reg_rd;
//outpu
//output [15:0] ex_inst_lo;
output ex_wb_reg_write;
output ex_wb_memtoreg;
output ex_mem_memread;
output ex_mem_memwrite;
output ex_mem_ll_mem;
output ex_mem_sc_mem;
output ex_regdst;
output [1:0] ex_aluop;
output ex_alusrc;
output [31:0] ex_regread1;
output [31:0] ex_regread2;
output [31:0] ex_sign_extend;
output [4:0] ex_reg_rs;
output [4:0] ex_reg_rt;
output [4:0] ex_reg_rd;
//define regs
//reg [15:0] ex_inst_lo;
reg ex_wb_reg_write;
reg ex_wb_memtoreg;
reg ex_mem_memread;
reg ex_mem_memwrite;
reg ex_mem_ll_mem;
reg ex_mem_sc_mem;
reg ex_regdst;
reg [1:0] ex_aluop;
reg ex_alusrc;
reg [31:0] ex_regread1;
reg [31:0] ex_regread2;
reg [31:0] ex_sign_extend;
reg [4:0] ex_reg_rs;
reg [4:0] ex_reg_rt;
reg [4:0] ex_reg_rd;
always@(posedge clk)
begin
if(rst)
begin
// ex_inst_lo<=15'b000000000000000;
ex_wb_reg_write<=1'b0;
ex_wb_memtoreg<=1'b0;
ex_mem_memread<=1'b0;
ex_mem_memwrite<=1'b0;
ex_mem_ll_mem<=1'b0;
ex_mem_sc_mem<=1'b0;
ex_regdst<=1'b0;
ex_aluop<=2'b00;
ex_alusrc<=1'b0;
ex_regread1<=32'h0000;
ex_regread2<=32'h0000;
ex_sign_extend<=32'h0000;
ex_reg_rs<=5'b00000;
ex_reg_rt<=5'b00000;
ex_reg_rd<=5'b00000;
end
else
begin
// ex_inst_lo<=inst_lo;
ex_wb_reg_write<=wb_reg_write;
ex_wb_memtoreg<=wb_memtoreg;
ex_mem_memread<=mem_memread;
ex_mem_memwrite<=mem_memwrite;
ex_mem_ll_mem<=mem_ll_mem;
ex_mem_sc_mem<=mem_sc_mem;
ex_regdst<=regdst;
ex_aluop<=aluop;
ex_alusrc<=alusrc;
ex_regread1<=regread1;
ex_regread2<=regread2;
ex_sign_extend<=sign_extend;
ex_reg_rs<=reg_rs;
ex_reg_rt<=reg_rt;
ex_reg_rd<=reg_rd;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; template <class T> inline bool read(T &ret) { char c; int sgn; if (c = getchar(), c == EOF) return false; while (c != - && (c < 0 || c > 9 )) c = getchar(); sgn = (c == - ) ? -1 : 1; ret = (c == - ) ? 0 : (c - 0 ); while (c = getchar(), c >= 0 && c <= 9 ) ret = ret * 10 + (c - 0 ); ret *= sgn; return true; } inline long long qmul(long long, long long, long long); inline long long qpow_qmul(long long, long long, long long); inline long long qpow(long long, long long, long long); inline long long gcd(long long, long long); const int N = 1e5 + 10; const long long INF = -0x3f3f3f3f; const long long mod = 1e9 + 7; const double PI = acos(-1.0); int boy[N], girl[N]; int main() { int n, m, num, idx, cnt, cnt1; memset(boy, 0, sizeof(boy)); memset(girl, 0, sizeof(girl)); scanf( %d%d , &n, &m); scanf( %d , &num); cnt = num; for (int i = 0; i < num; i++) scanf( %d , &idx), boy[idx] = 1; scanf( %d , &num); cnt1 = num; for (int i = 0; i < num; i++) scanf( %d , &idx), girl[idx] = 1; int x, y; for (int i = 0; i < n * m * max(n, m); i++) { x = i % n; y = i % m; if (boy[x] || girl[y]) { if (!boy[x]) cnt++; if (!girl[y]) cnt1++; boy[x] = 1; girl[y] = 1; } if (cnt == n && cnt1 == m) break; } if (cnt == n && cnt1 == m) { printf( Yes n ); } else { printf( No n ); } return 0; } inline long long qmul(long long a, long long b, long long mod) { long long ans = 0, x = a; while (b) { if (b & 1) { ans += x % mod; ans %= mod; } x *= 2; x %= mod; b >>= 1; } return ans % mod; } inline long long qpow_qmul(long long x, long long n, long long mod) { long long ans = 1, a = x % mod; while (n) { if (n & 1) { ans = qmul(ans, a, mod); ans %= mod; } a = qmul(a, a, mod); a %= mod; n >>= 1; } return ans; } inline long long qpow(long long x, long long n, long long mod) { long long ans = 1, a = x % mod; while (n) { if (n & 1) { ans *= a % mod; ans %= mod; } a *= a % mod; a %= mod; n >>= 1; } return ans; } inline long long gcd(long long m, long long n) { return n == 0 ? m : gcd(n, m % n); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:36:43 03/19/2015
// Design Name:
// Module Name: fsm2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsm2(
input clk,
input rst,
input rxd,
output [7:0] data,
output received
);
localparam STATE1 = 2'b00;
localparam STATE2 = 2'b01;
localparam STATE3 = 2'b10;
reg [1:0] state = STATE1;
reg [7:0] tmp_data = 8'b00000000;
reg tmp_received = 1'b0;
reg [2:0] index;
reg [1:0] rxd_hist = 2'b11;
always @(posedge clk)
begin
if(rst)
begin
tmp_data = 0;
tmp_received = 0;
rxd_hist = 2'b11; // dla bezpieczenstwa poczekaj 2 cykle zegara przed 1. odbiorem
state = STATE1;
end
case(state)
STATE1:
begin
if(rxd_hist == 2'b00 && rxd == 1) //bit startu
begin
rxd_hist = 2'b11;
tmp_data = 8'b00000000;
index = 3'b000;
state = STATE2;
end
end
STATE2:
begin
tmp_data[index] = rxd;
index = index + 1;
if(index == 3'b000) //odebrano 8 bitow danych
begin
tmp_received = 1'b1;
state = STATE3;
index = 3'b000;
end
end
STATE3:
begin
//obsluga flagi received
tmp_received = 1'b0;
tmp_data = 8'b00000000;
state = STATE1;
end
endcase
if(state == STATE1) rxd_hist = { rxd_hist[0], rxd };
end
assign data = tmp_data;
assign received = tmp_received;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline bool isPowerOfTwo(int x) { return (x != 0 && (x & (x - 1)) == 0); } double pi = 3.141592653589793238462643; int month[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int dx[8] = {1, 0, -1, 0, 1, -1, -1, 1}; int dy[8] = {0, 1, 0, -1, 1, 1, -1, -1}; inline int add(int a, int b, int m = 1000000007) { a += b; if (a >= m) a -= m; return a; } inline int mul(int a, int b, int m = 1000000007) { return (int)(((long long)a * (long long)b) % m); } inline bool ispalin(string &str) { int n = str.length(); for (int i = 0; i < n / 2; i++) if (str[i] != str[n - i - 1]) return false; return true; } long long expo(long long base, long long pow) { long long ans = 1; while (pow != 0) { if (pow & 1 == 1) { ans = ans * base; ans = ans % 1000000007; } base *= base; base %= 1000000007; pow /= 2; } return ans; } void swapp(int *a, int *b) { int temp = *a; *a = *b; *b = temp; } long long invt(long long x) { return expo(x, 1000000007 - 2); } int expFactor(int n, int p) { int x = p; int exponent = 0; while ((n / x) > 0) { exponent += n / x; x *= p; } return exponent; } inline int countsetbit(int n) { unsigned int count = 0; while (n) { n &= (n - 1); count++; } return count; } inline int abs(int x) { if (x < 0) return -x; return x; } bool isPal(string ss) { int len = ss.length(); for (int i = 0; i < len / 2; i++) { int comp = len - i - 1; if (ss[i] != ss[comp]) return false; } return true; } vector<long long> fact, inv; void calfal(int maxn) { fact.resize(maxn); inv.resize(maxn); fact[0] = inv[0] = inv[1] = 1; for (int i = (1); i <= (maxn - 1); ++i) fact[i] = i * fact[i - 1] % 1000000007; for (int i = (2); i <= (maxn - 1); ++i) inv[i] = (1000000007 - 1000000007 / i) * inv[1000000007 % i] % 1000000007; for (int i = (1); i <= (maxn - 1); ++i) inv[i] = inv[i] * inv[i - 1] % 1000000007; } long long ncr(int n, int r) { if (r > n) return 0; return (fact[n] * inv[r] % 1000000007) * inv[n - r] % 1000000007; } long long _sieve_size; bitset<10000010> bs; vector<int> primes; void sieve(long long upperbound) { _sieve_size = upperbound + 1; bs.set(); bs[0] = bs[1] = 0; for (long long i = 2; i <= _sieve_size; i++) if (bs[i]) { for (long long j = i * i; j <= _sieve_size; j += i) bs[j] = 0; primes.push_back((int)i); } } bool isPrime(long long N) { if (N <= _sieve_size) return bs[N]; for (int i = 0; i < (int)primes.size(); i++) if (N % primes[i] == 0) return false; return true; } double dpw[1001][1001][2], dpl1[1001][1001][2], dp[1001][1001][2]; int w, b; double fun(int turn, int ww, int bb) { if (ww >= w) { return 0; } if (bb > b) { return 0; } if (turn == 1 && bb >= b) { return 0; } if (dp[ww][bb][turn] != -1) { return dp[ww][bb][turn]; } if (turn) { double x, y; x = (w - ww) * 1.0 / (b - bb - 1 + w - ww); y = ((b - bb - 1) * 1.0 / (b - bb - 1 + w - ww)); if (bb == b - 1) { y = 0; } dp[ww][bb][turn] = (y * fun((turn + 1) % 2, ww, bb + 2) + x * fun((turn + 1) % 2, ww + 1, bb + 1)) * ((b - bb) * 1.0 / (b - bb + w - ww)); } else { dp[ww][bb][turn] = (w - ww) * 1.0 / (b - bb + w - ww) + fun((turn + 1) % 2, ww, bb + 1) * ((b - bb) * 1.0 / (b - bb + w - ww)); } return dp[ww][bb][turn]; } int main() { cin >> w >> b; if (!w) { cout << 0 << endl; return 0; } for (int i = (0); i <= (1); ++i) { for (int j = (0); j <= (w + 1); ++j) { for (int k = (0); k <= (b + 1); ++k) { dp[j][k][i] = -1; } } } printf( %.10f , fun(0, 0, 0)); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s; scanf( %d%d , &n, &s); int a, max, sum = 0; scanf( %d , &a); max = a; sum += a; for (int i = 1; i < n; i++) { scanf( %d , &a); if (a > max) max = a; sum += a; } sum -= max; if (sum <= s) printf( YES ); else printf( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m, count = 0; cin >> n >> m; int x = min(n, m); n = n - x; m = m - x; int rest = (n / 2) + (m / 2); cout << x << << rest << endl; return 0; } |
// lint_checking MODLNM OFF
module autoasciienum_onehot (
input clk,
input rst_n,
output ack
);
localparam // synopsys enum state_info
IDLE = 0,
S1 = 1,
S2 = 2,
S3 = 3,
DONE = 4;
reg [4:0] // synopsys enum state_info
cur_state, nxt_state;
always @ (*) begin
nxt_state = 5'h0;
case (1'b1)
cur_state[IDLE] : nxt_state[S1] = 1'b1;
cur_state[S1] : nxt_state[S2] = 1'b1;
cur_state[S2] : nxt_state[S3] = 1'b1;
cur_state[S3] : nxt_state[DONE] = 1'b1;
cur_state[DONE] : nxt_state[DONE] = 1'b1;
endcase
end
always @ (posedge clk or negedge rst_n)
if (rst_n == 1'b0) begin
cur_state <= 'h1;
end
else begin
cur_state <= nxt_state;
end
assign ack = cur_state[DONE];
/*AUTOASCIIENUM("cur_state", "cur_state_ascii")*/
// Beginning of automatic ASCII enum decoding
reg [31:0] cur_state_ascii; // Decode of cur_state
always @(cur_state) begin
case ({cur_state})
(5'b1<<IDLE): cur_state_ascii = "idle";
(5'b1<<S1): cur_state_ascii = "s1 ";
(5'b1<<S2): cur_state_ascii = "s2 ";
(5'b1<<S3): cur_state_ascii = "s3 ";
(5'b1<<DONE): cur_state_ascii = "done";
default: cur_state_ascii = "%Err";
endcase
end
// End of automatics
endmodule
|
#include <bits/stdc++.h> const long long INF = 0x3f3f3f3f3f3f3f3fLL; const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; const double eps = 1e-6; template <class T> inline void read(T& x) { int sign = 1; char c = getchar(); x = 0; while (c > 9 || c < 0 ) { if (c == - ) sign = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } x *= sign; } using namespace std; const int maxn = 5e6 + 10; unsigned long long ji = 1; long long dp[maxn]; unsigned long long prehash[maxn], sufhash[maxn]; char s[maxn]; inline int val(char x) { if (x >= 0 && x <= 9 ) return x - 0 ; if (x >= a && x <= z ) return x - a + 10; if (x >= A && x <= Z ) return x - Z + 36; } int main() { scanf( %s , s + 1); int len = 0; for (int i = 1; s[i]; ++i) s[i] = val(s[i]); for (int i = 1; s[i]; ++i) prehash[i] = prehash[i - 1] * 131 + 1ll * s[i]; for (int i = 1; s[i]; ++i) { sufhash[i] = sufhash[i - 1] + 1ll * s[i] * ji; ji *= 131; } long long res = 0; for (int i = 1; s[i]; ++i) { if (prehash[i] == sufhash[i]) { dp[i] = dp[i >> 1] + 1; } res += dp[i]; } printf( %lld n , res); } |
#include <bits/stdc++.h> using namespace std; int MAX = 1000000; int MIN = -1000000; int INF = 1000000000; int x4[4] = {0, 1, 0, -1}; int y4[4] = {1, 0, -1, 0}; int x8[8] = {0, 1, 1, 1, 0, -1, -1, -1}; int y8[8] = {1, 1, 0, -1, -1, -1, 0, 1}; int i, j, k; int main() { string str; cin >> str; str.push_back( 0 ); reverse(str.begin(), str.end()); str.push_back( 0 ); int indx = 1, ans = 1; while (indx < str.size()) { if (str[indx] == 1 && str[indx + 1] == 1 ) { str[indx - 1] = 1 ; for (i = indx; str[i] == 1 ; i++) str[i] = 0 ; str[i] = 1 ; indx = i; } else indx++; } int satu = 0; for (i = (0); i < (str.size()); i++) satu += (str[i] == 1 ); cout << satu << endl; { fflush(stdin); getchar(); }; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b, c, min_cost, min_a, min_b, min_c; cin >> a >> b >> c; if (b % a == 0 && c % b == 0) { cout << 0 << endl; cout << a << << b << << c << endl; } else { min_cost = 10000000; int max = 2 * c; for (int i = 1; i < max; i++) for (int j = i; j < max; j += i) for (int k = j; k < max; k += j) if (k % j == 0 && j % i == 0) { int cost = abs(a - i) + abs(b - j) + abs(c - k); if (cost < min_cost) { min_cost = cost; min_a = i; min_b = j; min_c = k; } } cout << min_cost << endl; cout << min_a << << min_b << << min_c << endl; } } } |
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