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#include <bits/stdc++.h> using namespace std; int main() { int n, x, y, z; int sum1 = 0, sum2 = 0, sum3 = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y >> z; sum1 += x; sum2 += y; sum3 += z; } if ((sum1 == 0) && (sum2 == 0) && (sum3 == 0)) { cout << YES << endl; } else { cout << NO << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; const int N = 1000005; class cmp { public: bool operator()(long long &A, long long &B) { return A > B; } }; bool by_sec(pair<long long, long long> &A, pair<long long, long long> &B) { return A.second < B.second; } bool is(pair<long long, long long> a, pair<long long, long long> b) { return !((a.first > b.second && a.second > b.second) || (a.first < b.first && a.second < b.first)); } long double dist(pair<long long, long long> p1, pair<long long, long long> p2) { return (long double)sqrt( (long double)(p1.first - p2.first) * (p1.first - p2.first) + (long double)(p1.second - p2.second) * (p1.second - p2.second)); } pair<bool, vector<long long> > is_in(vector<long long> v, long long sum) { long long n = v.size(); bool dp[30][1000]; memset(dp, 0, sizeof(dp)); ; for (int i = 0; i < sum + 1; i++) dp[0][i] = 0; for (int i = 0; i < n + 1; i++) dp[i][0] = 1; for (int i = 1; i < n + 1; i++) for (int j = 1; j < sum + 1; j++) { dp[i][j] = dp[i - 1][j]; if (v[i - 1] <= j) dp[i][j] = dp[i][j] | dp[i - 1][j - v[i - 1]]; } long long i = n; long long currSum = sum; vector<long long> set1, set2; if (!dp[n][sum]) return (make_pair(dp[n][sum], set1)); while (i > 0 && currSum >= 0) { if (dp[i - 1][currSum]) { i--; set2.push_back(v[i]); } else { i--; currSum -= v[i]; set1.push_back(v[i]); } } return make_pair(dp[n][sum], set1); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); bool mp[8000 + 5]; long long t; cin >> t; while (t--) { long long n; memset(mp, 0, sizeof(mp)); ; cin >> n; vector<long long> v(n); for (int i = 0; i < n; i++) cin >> v[i], mp[v[i]] = 1; for (int i = 0; i < n; i++) { long long s = v[i]; for (int j = i + 1; j < n; j++) { s += v[j]; if (s <= n && mp[s]) mp[s] = 0; } } long long cnt = 0; for (int i = 0; i < n; i++) if (!mp[v[i]]) cnt++; cout << cnt << n ; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:13:33 03/13/2014
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(
A,
B,
ALU_operation,
shamt,
res,
zero,
overflow
);
input wire [31: 0] A, B;
input wire [ 3: 0] ALU_operation;
input wire [ 4: 0] shamt;
output reg [31: 0] res;
output wire zero;
output wire overflow;
wire [31: 0] res_and, res_or, res_add, res_sub, res_nor, res_slt,
res_xor, res_srl, res_sll, res_addu, res_subu, res_sltu, res_lh, res_sh, res_sra, res_lhu;
reg [31: 0] mask4 = 32'h0000_ffff;
wire [31: 0] mask;
wire [31: 0] res_tmp;
assign mask = B[1] ? 32'hffff_0000 : 32'h0000_ffff;
assign res_tmp = A & mask;
always @(posedge ALU_operation[0]) mask4 = mask;
parameter one = 32'h00000001, zero_0 = 32'h00000000;
assign res_and = A & B;
assign res_or = A | B;
assign res_nor = ~(A | B);
assign res_xor = A ^ B;
assign res_srl = B >> shamt;
assign res_sll = B << shamt;
assign res_sra = $signed(B) >>> shamt;
assign res_add = $signed(A) + $signed(B);
assign res_sub = $signed(A) - $signed(B);
assign res_slt = ($signed(A) < $signed(B)) ? one : zero_0;
assign res_addu = $unsigned(A) + $unsigned(B);
assign res_subu = $unsigned(A) - $unsigned(B);
assign res_sltu = ($unsigned(A) < $unsigned(B)) ? one : zero_0;
assign res_lh = B[1] ? {{16{res_tmp[31]}}, res_tmp[31:16]} : {{16{res_tmp[15]}}, res_tmp[15:0]};
assign res_lhu = B[1] ? {16'h0, res_tmp[31:16]} : {16'h0, res_tmp[15:0]};
assign res_sh = mask4[0] ? (A&(~mask4) | {16'h0, B[15:0]}) : (A&(~mask4) | {B[15:0], 16'h0});
always @(*)
case (ALU_operation)
4'b0000: res = res_and;
4'b0001: res = res_or;
4'b0010: res = res_add;
4'b0110: res = res_sub;
4'b0100: res = res_nor;
4'b0111: res = res_slt;
4'b0011: res = res_xor;
4'b0101: res = res_srl;
4'b1000: res = res_sll;
4'b1001: res = res_addu;
4'b1010: res = res_subu;
4'b1011: res = res_sltu;
4'b1100: res = res_lh;
4'b1101: res = res_sh;
4'b1110: res = res_sra;
4'b1111: res = res_lhu;
default: res = res_add;
endcase
assign zero = (res == zero_0) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct UnionFind { vector<int> par; vector<int> rank; vector<int> sz; UnionFind(int n = 0) { if (n > 0) initialize(n); } void initialize(int n) { par.resize(n); rank.resize(n); sz.resize(n); for (int i = 0; i < n; i++) { par[i] = i; rank[i] = 0; sz[i] = 1; } } int find(int x) { if (par[x] == x) { return x; } else { return par[x] = find(par[x]); } } void unite(int x, int y) { x = find(x); y = find(y); if (x == y) return; if (rank[x] < rank[y]) { par[x] = y; sz[y] += sz[x]; } else { par[y] = x; sz[x] += sz[y]; if (rank[x] == rank[y]) rank[x]++; } } bool same(int x, int y) { return find(x) == find(y); } }; int main() { int N, M; cin >> N >> M; static pair<int64_t, int> A[200000]; for (int i = 0; i < N; i++) { int64_t a; scanf( %lld , &a); A[i] = {a, i}; } vector<vector<int64_t>> edges; for (int i = 0; i < M; i++) { int64_t x, y, w; scanf( %lld %lld %lld , &x, &y, &w); edges.push_back({w, x - 1, y - 1}); } sort(A, A + N); int64_t first = A[0].second; for (int i = 1; i < N; i++) { int64_t j = A[i].second; int64_t cost = A[0].first + A[i].first; edges.push_back({cost, first, j}); } sort(edges.begin(), edges.end()); int64_t ans = 0; UnionFind uf(N); for (auto& v : edges) { int i = v[1], j = v[2]; if (!uf.same(i, j)) { ans += v[0]; uf.unite(i, j); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char c; string s; set<char> q; int i, sum; int main() { getline(cin, s); for (i = 0; i < s.size(); i++) if (isalpha(s[i])) q.insert(s[i]); cout << q.size() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char s[105]; int main(void) { int n, f; while (cin >> n) { scanf( %s , s); f = 0; for (int l = (1); l <= (n); ++l) { for (int j = (0); j <= (n - 4 * l - 1); ++j) { if (j + 4 * l >= n) break; if (s[j] == * && s[j + l] == * && s[j + 2 * l] == * && s[j + 3 * l] == * && s[j + 4 * l] == * ) { f = 1; break; } } if (f) break; } if (f) cout << yes n ; else cout << no n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2000 + 10; int n, k, a[MAX_N], dp[MAX_N]; bool check(int x) { for (int i = 0; i < n; i++) { dp[i] = 1; for (int j = i - 1; ~j; j--) if (abs(a[i] - a[j]) <= 1LL * (i - j) * x) dp[i] = max(dp[i], dp[j] + 1); if (n - dp[i] <= k) return true; } return false; } int main() { ios_base ::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; int L = -1, R = 2e9 + 10; while (L + 1 < R) { int mid = (1LL * L + R) >> 1; check(mid) ? R = mid : L = mid; } cout << R << endl; return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Sign extension "macro"
// bits_out should be greater than bits_in
module sign_extend (in,out);
parameter bits_in=0; // FIXME Quartus insists on a default
parameter bits_out=0;
input [bits_in-1:0] in;
output [bits_out-1:0] out;
assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace io { char ibuf[(1 << 20)], *iS, *iT, obuf[(1 << 20)], *oS = obuf, *oT = oS + (1 << 20) - 1, c, qu[55]; int f, qr; inline void flush(void) { return fwrite(obuf, 1, oS - obuf, stdout), oS = obuf, void(); } inline char getch(void) { return (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, (1 << 20), stdin), (iS == iT ? EOF : *iS++)) : *iS++); } inline void putch(char x) { *oS++ = x; if (oS == oT) flush(); return; } string getstr(void) { string s = ; char c = getch(); while (c == || c == n || c == r || c == t || c == EOF) c = getch(); while (!(c == || c == n || c == r || c == t || c == EOF)) s.push_back(c), c = getch(); return s; } void putstr(string str, int begin = 0, int end = -1) { if (end == -1) end = str.size(); for (register int i = begin; i < end; i++) putch(str[i]); return; } template <typename T> inline T read() { register T x = 0; for (f = 1, c = getch(); c < 0 || c > 9 ; c = getch()) if (c == - ) f = -1; for (x = 0; c <= 9 && c >= 0 ; c = getch()) x = x * 10 + (c & 15); return x * f; } template <typename T> inline void write(const T& t) { register T x = t; if (!x) putch( 0 ); if (x < 0) putch( - ), x = -x; while (x) qu[++qr] = x % 10 + 0 , x /= 10; while (qr) putch(qu[qr--]); return; } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io::getch; using io::getstr; using io::putch; using io::putstr; using io::read; using io::write; struct LCA { int lca, x, y; }; long long f[13][(1 << 13)]; int n, m, q; vector<pair<int, int> > edges; vector<LCA> lca; long long F(int p, int S) { if (~f[p][S]) return f[p][S]; S ^= 1 << p; int sp = 0; while (!(S >> sp & 1)) sp++; f[p][S ^ (1 << p)] = 0; for (register int i = S; i; i = (i - 1) & S) { if (!(i >> sp & 1)) continue; bool pass = false; for (vector<LCA>::iterator j = lca.begin(); j != lca.end(); j++) if (j->lca == p && (i >> j->x & 1) && (i >> j->y & 1)) pass = true; if (pass) continue; for (vector<LCA>::iterator j = lca.begin(); j != lca.end(); j++) if ((i >> j->lca & 1) && (!(i >> j->x & 1) || !(i >> j->y & 1))) pass = true; if (pass) continue; for (vector<pair<int, int> >::iterator j = edges.begin(); j != edges.end(); j++) if (j->first != p && j->second != p && ((i >> j->first & 1) ^ (i >> j->second & 1))) pass = true; if (pass) continue; bool choose = false; int ppp = 0; for (vector<pair<int, int> >::iterator j = edges.begin(); j != edges.end(); j++) if (j->first == p && (i >> j->second & 1)) choose ? pass = true : (choose = true, ppp = j->second); else if (j->second == p && (i >> j->first & 1)) choose ? pass = true : (choose = true, ppp = j->first); if (pass) continue; if (choose) f[p][S ^ (1 << p)] += F(ppp, i) * F(p, S ^ i ^ (1 << p)); else for (register int j = 0; j < n; j++) if (i >> j & 1) f[p][S ^ (1 << p)] += F(j, i) * F(p, S ^ i ^ (1 << p)); } return f[p][S ^ (1 << p)]; } int main() { memset(f, -1, sizeof(f)); n = read<int>(), m = read<int>(), q = read<int>(); while (m--) edges.push_back((pair<int, int>){read<int>() - 1, read<int>() - 1}); while (q--) { int a = read<int>() - 1, b = read<int>() - 1, c = read<int>() - 1; lca.push_back((LCA){c, a, b}); } for (register int i = 0; i < n; i++) f[i][1 << i] = 1; write(F(0, (1 << n) - 1)), putch( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, p, d, x; cin >> n >> k >> d; p = n - k; for (int i = 0; i < d; i++) { cin >> x; x--; if (p <= k) { if (x % 2 == 0 && x / 2 < p) { cout << . ; } else { cout << X ; } } else { if (n % 2 == 0) { if ((x % 2 == 1) && (n - 1 - x) / 2 < k) { cout << X ; } else { cout << . ; } } else { if (x != n - 1) { if ((x % 2 == 1) && (n - 2 - x) / 2 < (k - 1)) { cout << X ; } else { cout << . ; } } else { if (k > 0) cout << X ; else cout << . ; } } } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/CAPTUREE2.v,v 1.1 2010/05/27 18:53:42 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : CAPTUREE2.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 05/09/12 - removed GSR reference (CR 659430).
// End Revision
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module CAPTUREE2 (
CAP,
CLK
);
parameter ONESHOT = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
input CAP;
input CLK;
reg [0:0] ONESHOT_BINARY;
reg notifier;
wire CAP_IN;
wire CLK_IN;
wire CAP_INDELAY;
wire CLK_INDELAY;
initial begin
case (ONESHOT)
"TRUE" : ONESHOT_BINARY = 1'b1;
"FALSE" : ONESHOT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ONESHOT on CAPTUREE2 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ONESHOT);
$finish;
end
endcase
end
buf B_CAP (CAP_IN, CAP);
buf B_CLK (CLK_IN, CLK);
specify
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP);
$setuphold (posedge CLK, posedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const long long mod = 1e9 + 7; template <typename T> inline T gcd(T a, T b) { return !b ? a : gcd(b, a % b); } template <typename T> inline T q_pow(T a, T x) { T ans = 1, tmp = a; while (x) { if (x & 1) (ans *= tmp) %= mod; (tmp *= tmp) %= mod; x >>= 1; } return ans; } template <typename T> inline void re(T &N) { int f = 1; char c; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) f = -1; N = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) N = N * 10 + c - 0 ; N *= f; } int m, n, t = 1, st, en; int a[N], b[N]; char s[N]; struct SegT { struct node { int fi, se; int cnt, tag; long long sum; } e[N << 2]; inline void push_up(int p) { int l = ((p) << 1), r = ((p) << 1 | 1); e[p].sum = e[l].sum + e[r].sum; if (e[l].fi == e[r].fi) { e[p].fi = e[l].fi; e[p].cnt = e[l].cnt + e[r].cnt; e[p].se = min(e[l].se, e[r].se); } else { e[p].fi = min(e[l].fi, e[r].fi); e[p].cnt = e[l].fi == e[p].fi ? e[l].cnt : e[r].cnt; e[p].se = min({e[l].se, e[r].se, e[l].fi == e[p].fi ? e[r].fi : e[l].fi}); } } void build(int p, int l, int r) { e[p].se = 1e9; e[p].cnt = 1; if (l == r) return; int mid = (l + r) >> 1; build(((p) << 1), l, mid); build(((p) << 1 | 1), mid + 1, r); push_up(p); } inline void push_down(int p) { int l = ((p) << 1), r = ((p) << 1 | 1); if (e[p].tag) { e[l].tag = e[r].tag = 1; if (e[l].fi < e[p].fi) { e[l].sum += 1ll * e[l].cnt * (e[p].fi - e[l].fi); e[l].fi = e[p].fi; } if (e[r].fi < e[p].fi) { e[r].sum += 1ll * e[r].cnt * (e[p].fi - e[r].fi); e[r].fi = e[p].fi; } e[p].tag = 0; } } void update(int p, int l, int r, int L, int R, int k) { if (e[p].fi >= k) return; if (L <= l && r <= R && e[p].se > k) { e[p].tag = 1; e[p].sum += 1ll * (k - e[p].fi) * e[p].cnt; e[p].fi = k; return; } push_down(p); int mid = (l + r) >> 1; if (L <= mid) update(((p) << 1), l, mid, L, R, k); if (mid < R) update(((p) << 1 | 1), mid + 1, r, L, R, k); push_up(p); } void kupdate(int p, int l, int r, int L, int R, int k) { if (L <= l && r <= R) { e[p].fi = e[p].sum = k; return; } push_down(p); int mid = (l + r) >> 1; if (L <= mid) kupdate(((p) << 1), l, mid, L, R, k); if (mid < R) kupdate(((p) << 1 | 1), mid + 1, r, L, R, k); push_up(p); } inline long long query() { return e[1].sum; } } tr; int main() { re(n); tr.build(1, 1, n); scanf( %s , s + 1); long long cnt = 0, ans = 0; for (int i = n; i >= 1; i--) { if (s[i] == 1 ) cnt++; else { for (int j = 1; j <= cnt; j++) tr.kupdate(1, 1, n, i + j, i + j, j); cnt = 0; } ans += (1 + cnt) * cnt / 2; if (i + cnt <= n) tr.update(1, 1, n, i + cnt, n, cnt); ans += tr.query(); } printf( %lld n , ans); } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 110, mod = 1e9 + 7; const long long inf = 1e18; long long a[maxn]; int b[maxn]; long long ans1, ans2, ans3; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int tot = 2; tot <= 2 * m; tot++) { int pos = max(1, tot - m), pos2 = 0, pos3 = 0, mxp = -1, lim = (tot + 1) / 2, cnt = 0; for (int j = 0; j < n; j++) { b[j] = a[j] % tot; } for (int j = 0; j < n; j++) { cnt += (b[j] >= lim); if (b[j] >= lim) pos = max(pos, tot - b[j]); else pos = max(pos, b[j] + 1); if (mxp == -1 || b[mxp] < b[j]) mxp = j; } for (int j = 0; j < n; j++) { if (j != mxp) pos2 = max(pos2, (b[j] / 2) + 1); pos3 = max(pos3, (b[j] / 2) + 1); } if (cnt & 1) ans2 += max(0, tot - 2 * max(pos, pos2) + 1); else ans3 += max(0, tot - 2 * max(pos, pos3) + 1); } ans1 = (1ll * m * m - ans2 - ans3) >> 1; return cout << ans1 << << ans1 << << ans2 << << ans3 << endl, 0; } |
`include "ShiftRegister.v"
`include "memory.v"
`include "finiteStateMachine.v"
`include "programCounter.v"
`include "serialClock.v"
`include "mosiFF.v"
`include "delayCounter.v"
module toplevel(led, gpioBank1, gpioBank2, clk, sw, btn); // possible inputs from fpga
output [7:0] led;
output [3:0] gpioBank1;
output [3:0] gpioBank2;
input clk;
input[7:0] sw;
input[3:0] btn;
parameter memBits = 10;
parameter memAddrWidth = 16;
parameter dataBits = 8;
// serialClock
wire sclk, sclkPosEdge, sclkNegEdge;
wire sclk8PosEdge;
// memory
wire writeEnable;
wire[memAddrWidth-1:0] addr;
wire[memBits-1:0] dataIn, dataOut;
// programCounter
wire[memAddrWidth-1:0] memAddr;
wire reset;
assign addr = memAddr;
// shiftRegister
wire parallelLoad, serialDataIn; //not used
wire[dataBits-1:0] parallelDataOut; // also not used
wire[dataBits-1:0] parallelDataIn;
wire serialDataOut;
assign parallelLoad = sclk8PosEdge;
assign parallelDataIn = dataOut;
// finiteStateMachine
wire[memBits-1:0] instr; // probably change this to reflect envelope diagram
wire cs, dc;
wire[dataBits-1:0] parallelData;
assign instr = dataOut;
// FFs
wire md, mq;
assign md = serialDataOut;
wire cd, cq;
assign cd = cs;
wire dd, dq;
assign dd = dc;
// delayCounter
wire delayEn, pcEn;
// OUTPUTS
assign gpioBank1[0] = mq; // mosi
assign gpioBank1[1] = cq; // chip select
assign gpioBank1[2] = dq; // data/command select
assign gpioBank1[3] = sclkPosEdge; // serialClock (positive edge)
assign led = parallelDataOut[7:0];
assign reset = btn[0];
assign gpioBank2[0] = !btn[1];
// Magic
serialClock #(3) sc(clk, sclk, sclkPosEdge, sclkNegEdge, sclk8PosEdge);
memory m(clk, writeEnable, addr, dataIn, dataOut);
programCounter pc(clk, sclkPosEdge, pcEn, memAddr, sclk8PosEdge, reset);
shiftRegister sr(clk, sclkPosEdge, parallelLoad, parallelDataIn, serialDataIn, parallelDataOut, serialDataOut, sclk8PosEdge);
finiteStateMachine fsm(clk, sclkPosEdge, instr, cs, dc, delayEn, parallelData);
mosiFF mff(clk, sclkNegEdge, md, mq);
mosiFF csff(clk, sclkNegEdge, cd, cq);
mosiFF dcff(clk, sclkNegEdge, dd, dq);
delayCounter delC(clk, delayEn, pcEn);
endmodule
module testTopLevel;
wire [7:0] led;
wire [3:0] gpioBank1;
wire[3:0] gpioBank2;
reg clk;
reg[7:0] sw;
reg[3:0] btn;
toplevel tl(led, gpioBank1, gpioBank2, clk, sw, btn);
initial clk=0;
always #10 clk=!clk;
//initial begin
//#7850 btn[0]=1;
//#10 btn[0]=0;
//end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 28490 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w2048,
w2049,
w8,
w7,
w14,
w2035,
w16280,
w14245,
w28490;
assign w1 = i_data0;
assign w14 = w7 << 1;
assign w14245 = w16280 - w2035;
assign w16280 = w2035 << 3;
assign w2035 = w2049 - w14;
assign w2048 = w1 << 11;
assign w2049 = w1 + w2048;
assign w28490 = w14245 << 1;
assign w7 = w8 - w1;
assign w8 = w1 << 3;
assign o_data0 = w28490;
//multiplier_block area estimate = 7071.92625206177;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > con[3]; vector<pair<long long, long long> > sum; int main() { for (long long i = 0; i < ((long long)3); i++) { long long n; cin >> n; for (long long j = 0; j < ((long long)n); j++) { long long x, y; cin >> x >> y; con[i].push_back(make_pair(x, y)); } } long long pos[3] = {1, 1, 1}; long long start[3] = {1, 1, 1}; for (long long i = 0; i < ((long long)3); i++) for (long long j = 0; j < ((long long)((long long)con[i].size())); j++) if (con[i][start[i]] < con[i][j]) pos[i] = start[i] = j; long long sum_x = 0; long long sum_y = 0; bool f[3] = {true, true, true}; while (pos[0] != start[0] || pos[1] != start[1] || pos[2] != start[2] || f[0] || f[1] || f[2]) { double ang[3] = {0, 0, 0}; long long next[3] = {(pos[0] + 1) % ((long long)con[0].size()), (pos[1] + 1) % ((long long)con[1].size()), (pos[2] + 1) % ((long long)con[2].size())}; for (long long i = 0; i < ((long long)3); i++) { double xx = (con[i][next[i]].first) - (con[i][pos[i]].first); double yy = (con[i][next[i]].second) - (con[i][pos[i]].second); ang[i] = (yy == 0) ? (acos(-1) / 2.0) : acos(yy / hypot(xx, yy)); if (0 < xx) ang[i] = acos(-1) * 2.0 - ang[i]; if (ang[i] == 0) ang[i] = acos(-1) * 2.0; if (pos[i] == start[i] && !f[i]) ang[i] = 365; } long long mini = 0; for (long long i = 0; i < ((long long)3); i++) if (ang[i] < ang[mini]) mini = i; pos[mini] = next[mini]; f[mini] = false; sum_x = sum_y = 0; for (long long i = 0; i < ((long long)3); i++) sum_x += (con[i][pos[i]].first); for (long long i = 0; i < ((long long)3); i++) sum_y += (con[i][pos[i]].second); sum.push_back(make_pair(sum_x, sum_y)); } vector<pair<long long, long long> > low, high; long long mini = 0, maxi = 0; long long mini_y[2], maxi_y[2]; for (long long i = 0; i < ((long long)((long long)sum.size())); i++) if (sum[i] < sum[mini]) mini = i; for (long long i = 0; i < ((long long)((long long)sum.size())); i++) if (sum[maxi] < sum[i]) maxi = i; for (int i = mini; i != maxi; i = (i + 1) % ((long long)sum.size())) low.push_back(sum[i]); for (int i = mini; i != maxi; i = (i + ((long long)sum.size()) - 1) % ((long long)sum.size())) high.push_back(sum[i]); low.push_back(sum[maxi]); high.push_back(sum[maxi]); for (long long i = 0; i < ((long long)2); i++) mini_y[i] = sum[mini].second; for (long long i = 0; i < ((long long)2); i++) maxi_y[i] = sum[maxi].second; for (long long i = 0; i < ((long long)((long long)sum.size())); i++) if (sum[i].first == sum[mini].first) { mini_y[0] = min(mini_y[0], sum[i].second); mini_y[1] = max(mini_y[1], sum[i].second); } for (long long i = 0; i < ((long long)((long long)sum.size())); i++) if (sum[i].first == sum[maxi].first) { maxi_y[0] = min(maxi_y[0], sum[i].second); maxi_y[1] = max(maxi_y[1], sum[i].second); } sort(low.begin(), low.end()); sort(high.begin(), high.end()); long long n; cin >> n; for (long long i = 0; i < ((long long)n); i++) { long long xx, yy; cin >> xx >> yy; xx *= 3; yy *= 3; if (xx == sum[maxi].first) { if (maxi_y[0] <= yy && yy <= maxi_y[1]) cout << YES << endl; else cout << NO << endl; } else if (xx == sum[mini].first) { if (mini_y[0] <= yy && yy <= mini_y[1]) cout << YES << endl; else cout << NO << endl; } else if (sum[mini].first < xx && xx < sum[maxi].first) { vector<pair<long long, long long> >::iterator lp0 = upper_bound(low.begin(), low.end(), make_pair(xx, yy)); vector<pair<long long, long long> >::iterator hp0 = upper_bound(high.begin(), high.end(), make_pair(xx, yy)); vector<pair<long long, long long> >::iterator lp1 = lp0--; vector<pair<long long, long long> >::iterator hp1 = hp0--; long long ldx = lp1->first - lp0->first; long long ldy = lp1->second - lp0->second; long long hdx = hp1->first - hp0->first; long long hdy = hp1->second - hp0->second; if (ldx * lp0->second - ldy * lp0->first + ldy * xx <= ldx * yy && hdx * yy <= hdx * hp0->second - hdy * hp0->first + hdy * xx) { cout << YES << endl; } else { cout << NO << endl; } } else { cout << NO << endl; } } } |
#include<bits/stdc++.h> using namespace std; int a[10]; int main() { int T;scanf( %d ,&T); while(T--) { int sum = 0; for(int i = 1;i <= 3;i++) { scanf( %d ,&a[i]); sum += a[i]; } if(sum % 9 == 0) { if(a[1] >= sum / 9 && a[2] >= sum / 9 && a[3] >= sum / 9) { printf( YES n ); } else { printf( NO n ); } } else { printf( NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200020; long long a; int main() { cin >> a; long long l = 1, r = 1e18; long long ans = (((9 * (5 * (9 * (2 * (long long)1e17) % a) % a) % a) % a) + 1) % a; cout << l + (a - ans) << << r + (a - ans) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; pair<int, int> point[int(2e5 + 10)]; map<int, int> mark_x, mark_y; long long res; void sol() { cin >> n; for (int i = 0; i < n; i++) { cin >> point[i].first >> point[i].second; mark_x[point[i].first]++; mark_y[point[i].second]++; } sort(point, point + n); for (int i = 0; i < n; i++) { if (i == 0 || point[i].first != point[i - 1].first) { for (int j = i; point[j].first == point[i].first && j < n; j++) { mark_y[point[j].second]--; } } mark_x[point[i].first]--; res += mark_x[point[i].first]; res += mark_y[point[i].second]; } cout << res; } int main() { std::ios::sync_with_stdio(false); cin.tie(NULL); sol(); return 0; } |
// ECE 429
//FIXME: include output port busy
module memory(clock, address, data_in, access_size, rw, enable, busy, data_out);
parameter data_width = 32;
parameter address_width = 32;
parameter depth = ;
// -1 for 0 based indexed
parameter bytes_in_word = 4-1;
parameter bits_in_bytes = 8-1;
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
input clock;
input [address_width-1:0] address;
input [data_width-1:0] data_in;
input [1:0] access_size;
input rw;
input enable;
// Output Ports
//FIXME: change to output port.
output reg busy;
output reg [data_width-1:0] data_out;
// Create a 1MB deep memory of 8-bits (1 byte) width
reg [7:0] mem[0:depth]; // should be [7:0] since its byte addressible memory
reg [7:0] data;
reg [7:0] byte[3:0];
reg [31:0] global_cur_addr;
reg [31:0] global_cur_addr_write;
reg [31:0] global_cur_addr_read;
integer cyc_ctr = 0;
integer cyc_ctr_write = 0;
integer i = 0;
integer words_written = 0;
integer words_read = 0;
integer write_total_words = 0;
integer read_total_words = 0;
integer fd;
integer status_read, status_write;
integer blah;
reg [31:0] fd_in;
reg [31:0] str;
always @(posedge clock, data_in, rw)
begin : WRITE
// rw = 1
if ((!rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(write_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
mem[address-start_addr+3] <= data_in[7:0];
mem[address-start_addr+2] <= data_in[15:8];
mem[address-start_addr+1] <= data_in[23:16];
mem[address-start_addr] <= data_in[31:24];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
write_total_words = 4;
// skip over the already written bytes
global_cur_addr_write = address-start_addr;
if (words_written < 4) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_written = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
write_total_words = 8;
global_cur_addr_write = address-start_addr;
if (words_written < 8) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
// 11: 16 words
else if (access_size == 2'b1_1) begin
write_total_words = 16;
if (words_written < 16) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
end
end
/*
00: 1 word (4-bytes)
01: 4 words (16-bytes)
10: 8 words (32-bytes)
11: 16 words (64-bytes)
*/
always @(posedge clock, address, rw)
begin : READ
if ((rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(read_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
// read 4 bytes at max in 1 clock cycle.
//assign data_out = {mem[address-start_addr], mem[address-start_addr+1], mem[address-start_addr+2], mem[address-start_addr+3]};
data_out[7:0] <= mem[address-start_addr+3];
data_out[15:8] <= mem[address-start_addr+2];
data_out[23:16] <= mem[address-start_addr+1];
data_out[31:24] <= mem[address-start_addr];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
read_total_words = 4;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 4) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
read_total_words = 8;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 8) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
// 11: 16 words
end else if (access_size == 2'b1_1) begin
read_total_words = 16;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 16) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
end
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Tawas Instruction Fetch
//
// Pick thread for each cycle and decode br and full word instructions.
//
module tawas_fetch
(
input clk,
input rst,
output ics,
output [23:0] iaddr,
input [31:0] idata,
output thread_load_en,
output [4:0] thread_load,
output [4:0] thread_decode,
output [4:0] thread_store,
input [31:0] thread_mask,
input [31:0] rcn_stall,
input rcn_load_en,
input [7:0] au_flags,
input [23:0] pc_rtn,
output rf_imm_en,
output [2:0] rf_imm_reg,
output [31:0] rf_imm,
output ls_dir_en,
output ls_dir_store,
output [2:0] ls_dir_reg,
output [31:0] ls_dir_addr,
output au_op_en,
output [14:0] au_op,
output ls_op_en,
output [14:0] ls_op
);
//
// Thread PC's : 24-bit PC + 1-bit half-word-select
//
wire pc_update_en;
wire [4:0] pc_update_sel;
wire [24:0] pc_update_addr;
reg [24:0] pc[31:0];
integer x1;
always @ (posedge clk or posedge rst)
if (rst)
for (x1 = 0; x1 < 32; x1 = x1 + 1)
pc[x1] <= x1;
else if (pc_update_en)
pc[pc_update_sel] <= pc_update_addr;
//
// Choose thread to execute
//
reg [31:0] thread_busy;
reg [31:0] thread_ready;
reg [31:0] thread_done_mask;
reg [31:0] s1_sel_mask;
reg [4:0] s1_sel;
reg s1_en;
wire thread_retire_en;
wire [4:0] thread_retire;
wire thread_abort_en;
wire [4:0] thread_abort;
integer x2;
always @ *
begin
s1_sel_mask = 32'd0;
s1_sel = 5'd0;
s1_en = 1'b0;
thread_done_mask = 32'd0;
thread_ready = (~thread_busy) & thread_mask & (~rcn_stall);
for (x2 = 0; x2 < 32; x2 = x2 + 1)
if (!s1_en && thread_ready[x2])
begin
s1_sel_mask = (32'd1 << x2);
s1_sel = x2;
s1_en = 1'b1;
end
if (thread_retire_en)
thread_done_mask = (32'd1 << thread_retire);
if (thread_abort_en)
thread_done_mask = (32'd1 << thread_abort);
end
always @ (posedge clk or posedge rst)
if (rst)
thread_busy <= 32'd0;
else
thread_busy <= (thread_busy | s1_sel_mask) & ~thread_done_mask;
//
// En/Sel pipeline
//
reg s2_en;
reg [4:0] s2_sel;
reg [24:0] s2_pc;
reg s3_en;
reg [4:0] s3_sel;
reg [24:0] s3_pc;
reg s4_en;
reg [4:0] s4_sel;
reg [24:0] s4_pc;
wire s6_halt;
reg s5_en;
reg [4:0] s5_sel;
reg s6_en;
reg [4:0] s6_sel;
reg [4:0] s7_sel;
assign ics = s2_en;
assign iaddr = s2_pc[23:0];
reg [31:0] instr;
always @ (posedge clk)
begin
s2_pc <= pc[s1_sel];
s3_pc <= s2_pc;
s4_pc <= s3_pc;
s2_sel <= s1_sel;
s3_sel <= s2_sel;
s4_sel <= s3_sel;
s5_sel <= s4_sel;
s6_sel <= s5_sel;
s7_sel <= s6_sel;
end
always @ (posedge clk)
if (s3_en)
instr <= idata;
always @ (posedge clk or posedge rst)
if (rst)
begin
s2_en <= 1'b0;
s3_en <= 1'b0;
s4_en <= 1'b0;
s5_en <= 1'b0;
s6_en <= 1'b0;
end
else
begin
s2_en <= s1_en;
s3_en <= s2_en;
s4_en <= s3_en && !thread_abort_en;
s5_en <= s4_en && !s5_halt;
s6_en <= s5_en;
end
//
// Decode Instructions
//
wire [14:0] op_high = instr[29:15];
wire [14:0] op_low = instr[14:0];
wire [12:0] op_br = instr[27:15];
wire op_high_vld = !instr[31] || !instr[30];
wire op_high_au = (instr[31:30] == 2'b00);
wire op_low_vld = !instr[31] || !instr[30] || !instr[29];
wire op_low_au = !instr[30] || (instr[31:28] == 4'b1100);
wire op_serial = !instr[31];
wire op_br_vld = (instr[31:29] == 3'b110);
wire op_is_br = op_br_vld && !op_br[12];
wire [23:0] op_br_iaddr = s4_pc[23:0] + {{12{op_br[11]}}, op_br[11:0]};
wire op_is_halt = op_br_vld && (op_br[12:0] == 13'd0);
wire op_is_br_cond = op_br_vld && op_br[12];
wire op_br_cond_true = (op_br[11]) ? !au_flags[op_br[10:8]] : au_flags[op_br[10:8]];
wire [23:0] op_br_cond_iaddr = s4_pc[23:0] + {{16{op_br[7]}}, op_br[7:0]};
wire op_is_rtn = op_br_vld && op_br[12] && (op_br[7:0] == 8'd1);
wire op_is_imm = (instr[31:28] == 4'b1110);
wire [2:0] op_imm_reg = instr[27:25];
wire [31:0] op_imm = {{8{instr[24]}}, instr[23:0]};
wire op_is_dir_ld = (instr[31:26] == 6'b111100);
wire op_is_dir_st = (instr[31:26] == 6'b111101);
wire [2:0] op_dir_reg = instr[25:23];
wire [31:0] op_daddr = {{8{instr[22]}}, instr[21:0], 2'b00};
wire op_is_jmp = (instr[31:24] == 8'b11111110);
wire op_is_call = (instr[31:24] == 8'b11111111);
wire [23:0] op_iaddr = instr[23:0];
//
// PC Update
//
wire [24:0] pc_next = (op_serial && !s4_pc[24]) ? {1'b1, s4_pc[23:0]}
: {1'b0, s4_pc[23:0] + 24'b1};
assign pc_update_en = s4_en;
assign pc_update_sel = s4_sel;
assign pc_update_addr = (op_is_call || op_is_jmp) ? {1'b0, op_iaddr} :
(op_is_rtn) ? {1'b0, pc_rtn} :
(op_is_br) ? {1'b0, op_br_iaddr} :
(op_is_br_cond && op_br_cond_true) ? {1'b0, op_br_cond_iaddr}
: pc_next;
//
// Load thread register context
//
assign thread_load_en = s3_en && !thread_abort_en;
assign thread_load = s3_sel;
assign thread_decode = s4_sel;
assign thread_store = s7_sel;
//
// Retire/abort/halt thread
//
assign thread_abort_en = rcn_load_en;
assign thread_abort = s3_sel;
assign s5_halt = op_is_halt;
assign thread_retire_en = s6_en;
assign thread_retire = s6_sel;
//
// Imm/Dir data loads
//
assign rf_imm_en = s4_en && (op_is_imm || op_is_call);
assign rf_imm_reg = (op_is_imm) ? op_imm_reg : 3'd7;
assign rf_imm = (op_is_imm) ? op_imm : {8'd0, s4_pc + 24'b1};
assign ls_dir_en = s4_en && (op_is_dir_ld || op_is_dir_st);
assign ls_dir_store = op_is_dir_st;
assign ls_dir_reg = op_dir_reg;
assign ls_dir_addr = op_daddr;
//
// LS/AU Ops
//
wire do_low = (op_serial) ? !s4_pc[24] : op_low_vld;
wire do_high = (op_serial) ? s4_pc[24] : op_high_vld;
assign au_op_en = s4_en && ((do_high && op_high_au) || (do_low && op_low_au));
assign au_op = (do_high && op_high_au) ? op_high : op_low;
assign ls_op_en = s4_en &&
((do_high && !op_high_au) || (do_low && !op_low_au) || op_is_call);
assign ls_op = (op_is_call) ? 15'h77F7 :
(do_high && !op_high_au) ? op_high : op_low;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; int v[1024]; int vv[1024]; int N; int try_it(int last) { for (int i = (0); i < (N); i++) vv[i] = v[i]; for (int i = (last); i < (N); i++) vv[i] = max(0, vv[i] - 1); vv[N] = 0; int NN = N; while (NN > 0 && vv[NN - 1] == 0) --NN; int moves = 0, p = -1; while (vv[NN - 1] > 0) { moves += 3; ++p; while (vv[p + 1] >= vv[p]) { moves += 2; ++p; } ++moves; --vv[p]; --p; while (p >= 0 && vv[p] == vv[p + 1] + 1) { --vv[p]; --p; moves++; } moves++; } return moves + N * 3 - 2 * p - last; } void do_it(int last) { for (int i = (0); i < (N); i++) vv[i] = v[i]; for (int i = (last); i < (N); i++) vv[i] = max(0, vv[i] - 1); vv[N] = 0; int NN = N; while (NN > 0 && vv[NN - 1] == 0) --NN; int p = -1; while (vv[NN - 1] > 0) { cout << ARA ; ++p; while (vv[p + 1] >= vv[p]) { cout << RA ; ++p; } cout << L ; --vv[p]; --p; while (p >= 0 && vv[p] == vv[p + 1] + 1) { --vv[p]; --p; cout << L ; } cout << A ; } while (p++ < N - 1) cout << AR ; cout << A ; while (p-- > last) cout << L ; cout << A n ; } int main() { ios::sync_with_stdio(false); cin >> N; for (int i = (0); i < (N); i++) cin >> v[i]; v[N] = 0; while (N > 0 && v[N - 1] == 0) --N; int best = try_it(0); int last = 0; for (int i = (1); i < (N); i++) { int c = try_it(i); if (c < best) { best = c; last = i; } } do_it(last); return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: moon.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module moon (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/moon.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/moon.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/moon.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 400; int x[MAXN], y[MAXN]; inline bool lt(int i, int xx, int yy) { return x[i] < xx || (x[i] == xx && y[i] < yy); } inline bool gt(int i, int xx, int yy) { return x[i] > xx || (x[i] == xx && y[i] > yy); } void mysort(int l, int r) { if (l < r) { int pivot = int((rand() / (1.0 + RAND_MAX)) * (r - l + 1)) + l; int xx = x[pivot]; int yy = y[pivot]; int i = l; int j = r; while (1) { while (lt(i, xx, yy)) ++i; while (gt(j, xx, yy)) --j; if (i <= j) { swap(x[i], x[j]); swap(y[i], y[j]); ++i; --j; } else { break; } } mysort(l, j); mysort(i, r); } } bool outside(int xx, int xlo, int xhi) { return xx < xlo || xx > xhi; } bool outside(int xx, int yy, int xlo, int xhi, int ylo, int yhi) { return outside(xx, xlo, xhi) || outside(yy, ylo, yhi); } const int MAXSTEPS = 1000000; char steps[MAXSTEPS + 1]; int dy[] = {1, 0, -1, 0}; int dx[] = {0, 1, 0, -1}; string stepcode = URDL ; const int OFFSET = 120; bool board[2 * OFFSET + 1][2 * OFFSET + 1]; int from[2 * OFFSET + 1][2 * OFFSET + 1]; int n; bool tree(int xx, int yy) { pair<int*, int*> p_ = equal_range(x, x + n, xx); int p = p_.first - x; int q = p_.second - x; cerr << tree: << xx << << yy << << p << << q << n ; if (p < n && x[p] == xx) { int i = lower_bound(y + p, y + q, yy) - y; cerr << i << n ; return (i < q && y[i] == yy); } return false; } int main() { int vx, vy, sx, sy; cin >> vx >> vy >> sx >> sy >> n; if (n == 0) { puts( -1 ); return 0; } int orig_vx = vx; int orig_vy = vy; int orig_sx = sx; int orig_sy = sy; for (int i = 0; i < n; ++i) { cin >> x[i] >> y[i]; } mysort(0, n - 1); for (int i = 0; i < n; ++i) { cerr << x[i] << << y[i] << n ; } cerr << n ; int xlo = x[0]; int xhi = x[n - 1]; int ylo = *min_element(y, y + n); int yhi = *max_element(y, y + n); int step = 0; if (!outside(vx, vy, xlo, xhi, ylo, yhi) || !outside(sx, sy, xlo, xhi, ylo, yhi)) { for (int i = 0; i < n; ++i) { (board[(x[i]) + OFFSET][(y[i]) + OFFSET]) = 1; } memset(from, 0xff, sizeof from); queue<pair<int, int> > Q; Q.push(make_pair(vx, vy)); (from[(vx) + OFFSET][(vy) + OFFSET]) = 1; while (!Q.empty()) { pair<int, int> tmp = Q.front(); Q.pop(); int u = tmp.first; int v = tmp.second; for (int d = 0; d < 4; ++d) { int r = u + dx[d]; int c = v + dy[d]; if (r + OFFSET < 0 || c + OFFSET < 0 || r > OFFSET || c > OFFSET || (from[(r) + OFFSET][(c) + OFFSET]) != -1 || (board[(r) + OFFSET][(c) + OFFSET])) { continue; } (from[(r) + OFFSET][(c) + OFFSET]) = d; if (r == sx && c == sy) { goto BFS_DONE; } Q.push(make_pair(r, c)); } } BFS_DONE:; if ((from[(sx) + OFFSET][(sy) + OFFSET]) == -1) { puts( -1 ); return 0; } vector<int> D; int xx = sx; int yy = sy; while (xx != vx || yy != vy) { D.push_back((from[(xx) + OFFSET][(yy) + OFFSET])); xx -= dx[D.back()]; yy -= dy[D.back()]; } reverse(D.begin(), D.end()); cerr << D.size() << n ; int at = 0; while ((!outside(vx, vy, xlo, xhi, ylo, yhi) || !outside(sx, sy, xlo, xhi, ylo, yhi)) && (vx != sx || vy != sy)) { assert(at < int(D.size())); cerr << at << << D[at] << n ; steps[step++] = stepcode[D[at]]; cerr << vx << << vy << << sx << << sy << n ; vx += dx[D[at]]; vy += dy[D[at]]; cerr << vx << << vy << << sx << << sy << n ; assert(!tree(vx, vy)); if (!tree(sx + dx[D[at]], sy + dy[D[at]])) { sx += dx[D[at]]; sy += dy[D[at]]; D.push_back(D[at]); } cerr << vx << << vy << << sx << << sy << n ; cerr << n ; ++at; } } if (vx != sx || vy != sy) { int d = -1; if ((vx > xhi || outside(vy, ylo, yhi)) && (sx > xhi || outside(sy, ylo, yhi))) { d = 1; } else if ((vx < xlo || outside(vy, ylo, yhi)) && (sx < xlo || outside(sy, ylo, yhi))) { d = 3; } else if ((vy > yhi || outside(vx, xlo, xhi)) && (sy > yhi || outside(sx, xlo, xhi))) { d = 0; } else { assert((vy < ylo || outside(vx, xlo, xhi)) && (vy < ylo || outside(sx, xlo, xhi))); d = 2; } vx += 500 * dx[d]; vy += 500 * dy[d]; sx += 500 * dx[d]; sy += 500 * dy[d]; for (int i = 0; i < 500; ++i) { steps[step++] = stepcode[d]; } cerr << vx << << vy << << sx << << sy << n ; if (d != 0) { if (d == 2) { for (int i = 0; i < 500; ++i) { steps[step++] = R ; } } vy += 1000; sy += 1000; for (int i = 0; i < 1000; ++i) { steps[step++] = U ; } cerr << vx << << vy << << sx << << sy << n ; if (d == 2) { for (int i = 0; i < 500; ++i) { steps[step++] = L ; } } else { d = (d + 2) % 4; cerr << bla << d << n ; cerr << vx << << vy << << sx << << sy << n ; vx += 500 * dx[d]; vy += 500 * dy[d]; sx += 500 * dx[d]; sy += 500 * dy[d]; for (int i = 0; i < 500; ++i) { steps[step++] = stepcode[d]; } cerr << vx << << vy << << sx << << sy << n ; } } } cerr << vx << << vy << << sx << << sy << n ; if (vx != sx) { if (vx > sx) { vx += 500; sx += 500; for (int i = 0; i < 500; ++i) { steps[step++] = R ; } int k = sy - y[n - 1]; vy -= k; sy -= k; for (int i = 0; i < k; ++i) { steps[step++] = D ; } while (vx != sx) { --vx; steps[step++] = L ; if (sx - 1 > x[n - 1]) { --sx; } } } else { vx -= 500; sx -= 500; for (int i = 0; i < 500; ++i) { steps[step++] = L ; } int k = sy - y[0]; vy -= k; sy -= k; for (int i = 0; i < k; ++i) { steps[step++] = D ; } while (vx != sx) { ++vx; steps[step++] = R ; if (sx + 1 < x[0]) { ++sx; } } } } cerr << vx << << vy << << sx << << sy << n ; assert(vx == sx); if (vy != sy) { if (vy > sy) { vy += 2000; sy += 2000; for (int i = 0; i < 2000; ++i) { steps[step++] = U ; } int top = 0; for (int i = 1; i < n; ++i) { if (y[i] > y[top]) { top = i; } } if (vx > x[top]) { int k = vx - x[top]; vx -= k; sx -= k; for (int i = 0; i < k; ++i) { steps[step++] = L ; } } else { int k = -(vx - x[top]); vx += k; sx += k; for (int i = 0; i < k; ++i) { steps[step++] = R ; } } while (vy != sy) { --vy; steps[step++] = D ; if (sy - 1 > y[top]) { --sy; } } } else { vy -= 2000; sy -= 2000; for (int i = 0; i < 2000; ++i) { steps[step++] = D ; } int bot = 0; for (int i = 1; i < n; ++i) { if (y[i] < y[bot]) { bot = i; } } if (vx > x[bot]) { int k = vx - x[bot]; vx -= k; sx -= k; for (int i = 0; i < k; ++i) { steps[step++] = L ; } } else { int k = -(vx - x[bot]); vx += k; sx += k; for (int i = 0; i < k; ++i) { steps[step++] = R ; } } while (vy != sy) { ++vy; steps[step++] = U ; if (sy + 1 < y[bot]) { ++sy; } } } } cerr << vx << << vy << << sx << << sy << n ; int xx = orig_vx; int yy = orig_vy; for (int s = 0; s < step; ++s) { int d = stepcode.find(steps[s]); xx += dx[d]; yy += dy[d]; } cerr << xx << << yy << expect << vx << << vy; assert(xx == vx && yy == vy); xx = orig_sx; yy = orig_sy; for (int s = 0; s < step; ++s) { int d = stepcode.find(steps[s]); xx += dx[d]; yy += dy[d]; if (tree(xx, yy)) { xx -= dx[d]; yy -= dy[d]; } } cerr << xx << << yy << expect << sx << << sy; assert(xx == sx && yy == sy); puts(steps); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1000000 + 10; long long d[maxn]; long long ans = 0; int main() { ios_base::sync_with_stdio(false); long long n, m; cin >> n >> m; for (long long i = 0; i < m; i++) { long long v, u; cin >> v >> u; d[u]++; d[v]++; } for (long long i = 1; i <= n; i++) ans += d[i] * (n - 1 - d[i]); cout << (n * (n - 1) * (n - 2)) / 6 - (ans / 2) << endl; return 0; } |
module top;
integer ival;
real rval;
initial begin
$display("--- Printing as real ---");
$display("1/0 is %f. (Should be 0 -- x prints as 0)", 1/0);
$display("1/0.0 is %f. (Should be inf)", 1/0.0);
$display("1.0/0 is %f. (Should be inf)", 1.0/0);
$display("1.0/0.0 is %f. (should be inf)", 1.0/0.0);
// Moving these two lines before the previous four lines makes 1/0 print
// a large number, but not inf!
rval = 0.0;
ival = 0;
$display("1/integer zero is %f. (Should be 0 -- x prints as 0)", 1/ival);
$display("1/real zero is %f. (should be inf)", 1/rval);
$display("1.0/integer zero is %f. (Should be inf)", 1.0/ival);
$display("1.0/real zero is %f.", 1.0/rval);
$display("\n--- Printing as integer ---");
$display("1/0 is %d (Should be x)", 1/0);
$display("1/0.0 is %d", 1/0.0);
$display("1.0/0 is %d", 1.0/0);
$display("1.0/0.0 is %d", 1.0/0.0);
$display("1/integer zero is %d. (Should be x)", 1/ival);
$display("1/real zero is %d.", 1/rval);
$display("1.0/integer zero is %d.", 1.0/ival);
$display("1.0/real zero is %d.", 1.0/rval);
end
endmodule
|
//Control circuit
`include "verilog/mips_instr_defines.v"
module control
(
input wire[5:0] instr_op_ctl_i,
input wire[5:0] instr_funct_ctl_i,
output wire reg_src_ctl_o,
output wire reg_dst_ctl_o,
output wire jump_ctl_o,
output wire branch_ctl_o,
output wire mem_read_ctl_o,
output wire mem_to_reg_ctl_o,
output wire[5:0] alu_op_ctl_o,
output wire mem_wr_ctl_o,
output wire[2:0] alu_src_ctl_o,
output wire reg_wr_ctl_o,
output wire sign_ext_ctl_o
);
wire reg_src_ctl;
wire reg_dst_ctl;
wire jump_ctl;
wire branch_ctl;
wire mem_read_ctl;
wire mem_to_reg_ctl;
wire[5:0] alu_op_ctl;
wire mem_wr_ctl;
wire[2:0] alu_src_ctl;
wire reg_wr_ctl;
wire sign_ext_ctl;
reg[17:0] controls;
assign reg_src_ctl_o = reg_src_ctl;
assign reg_dst_ctl_o = reg_dst_ctl;
assign jump_ctl_o = jump_ctl;
assign branch_ctl_o = branch_ctl;
assign mem_read_ctl_o = mem_read_ctl;
assign mem_to_reg_ctl_o = mem_to_reg_ctl;
assign alu_op_ctl_o = alu_op_ctl;
assign mem_wr_ctl_o = mem_wr_ctl;
assign alu_src_ctl_o = alu_src_ctl;
assign reg_wr_ctl_o = reg_wr_ctl;
assign sign_ext_ctl_o = sign_ext_ctl;
assign {reg_src_ctl, reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl,
alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl, sign_ext_ctl} = controls;
always @ *
begin
case (instr_op_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//alu_src_ctl:
//3'b000: sends rf port 2 value to ALU
//3'b001: sends sign_imm to ALU
//3'b010: sends zero extended shamt value to ALU
//3'b100: send 32'b0 to ALU
//reg_src_ctl, reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl, alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl, sign_ext
`ADDI : controls = 18'b0_0_0_0_0_0_000000_0_001_1_1; // I
`ADDIU : controls = 18'b0_0_0_0_0_0_000000_0_001_1_1; // I
`ANDI : controls = 18'b0_0_0_0_0_0_010000_0_001_1_0; // I
`SLTI : controls = 18'b0_0_0_0_0_0_101001_0_001_1_1; // I
`SLTIU : controls = 18'b0_0_0_0_0_0_110001_0_001_1_1; // I
`ORI : controls = 18'b0_0_0_0_0_0_001000_0_001_1_0; // I
`XORI : controls = 18'b0_0_0_0_0_0_100000_0_001_1_0; // I
`BEQ : controls = 18'b0_0_0_1_0_0_000001_0_000_0_1; // I
`BVAR : controls = 18'b0_0_0_1_0_0_000001_0_100_0_1; // I
`BGTZ : controls = 18'b0_0_0_1_0_0_000000_0_100_0_1; // I
`BLEZ : controls = 18'b0_0_0_1_0_0_000000_0_100_0_1; // I
`BNE : controls = 18'b0_0_0_1_0_0_000001_0_000_0_1; // I
`LB : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LBU : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LH : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LHU : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LUI : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LW : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`SB : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`SH : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`SW : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`J : controls = 18'b0_0_1_0_0_0_000000_0_001_0_1; // J
`JAL : controls = 18'b0_0_1_0_0_0_000000_0_001_1_1; // J
5'b00000:
case (instr_funct_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//alu_src_ctl:
//3'b000: sends rf port 2 value to ALU
//3'b001: sends sign_imm to ALU
//3'b010: sends zero extended shamt value to ALU
//3'b100: send 32'b0 to ALU
//reg_src_ctl,reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl, alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl,sign_ext_ctl
`ADD : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`ADDU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`AND : controls = 18'b0_1_0_0_0_0_010000_0_000_1_0; // R
`DIV : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`DIVU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`JALR : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`JR : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MFHI : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MFLO : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MTHI : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MTLO : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MULT : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MULTU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`NOR : controls = 18'b0_1_0_0_0_0_011000_0_000_1_0; // R
`OR : controls = 18'b0_1_0_0_0_0_001000_0_000_1_0; // R
`SLLV : controls = 18'b1_1_0_0_0_0_000010_0_010_1_0; // R
`SLT : controls = 18'b0_1_0_0_0_0_101001_0_000_1_0; // R
`SLTU : controls = 18'b0_1_0_0_0_0_110001_0_000_1_0; // R
`SRA : controls = 18'b1_1_0_0_0_0_000110_0_010_1_0; // R
`SRAV : controls = 18'b1_1_0_0_0_0_000110_0_010_1_0; // R
`SRL : controls = 18'b1_1_0_0_0_0_000100_0_010_1_0; // R
`SRLV : controls = 18'b1_1_0_0_0_0_000100_0_010_1_0; // R
`SUB : controls = 18'b0_1_0_0_0_0_000001_0_000_1_0; // R
`SUBU : controls = 18'b0_1_0_0_0_0_000001_0_000_1_0; // R
`SYSCALL: controls = 18'b0_1_0_0_0_0_000000_0_000_0_0; // R
`XOR : controls = 18'b0_1_0_0_0_0_100000_0_000_1_0; // R
`SLL : controls = 18'b1_1_0_0_0_0_000010_0_010_1_0; // R
default : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0;
endcase
default : controls = 18'b0_1_0_0_0_0_000000_0_0_0_0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> adj[100001]; vector<int> cost[3]; long long matrix[3][3] = {0}; int tree[100000]; int output[100000] = {0}; void makeTree(int a, int pos) { tree[pos] = a; for (auto &i : adj[a]) { if (pos == 0 || tree[pos - 1] != i) makeTree(i, pos + 1); } } long long calc(int a, int b, int i) { if (i == n) return 0; int c = 0 ^ 1 ^ 2 ^ a ^ b; return cost[c][tree[i] - 1] + calc(b, c, i + 1); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> n; for (int i = 0; i < int(3); i++) for (int j = 0; j < int(n); j++) { int x; cin >> x; cost[i].push_back(x); } for (int i = 0; i < int(n - 1); i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } int counter = 0; int lf; for (int i = 0; i < int(n); i++) { if (adj[i + 1].size() == 1) { lf = i + 1; counter++; } if (counter > 2) { cout << -1 ; return 0; } } makeTree(lf, 0); long long sml = pow(10, 15); int x, y; for (int i = 0; i < int(3); i++) { for (int j = 0; j < int(3); j++) { if (i == j) continue; matrix[i][j] = cost[i][tree[0] - 1] + cost[j][tree[1] - 1] + calc(i, j, 2); sml = min(sml, matrix[i][j]); if (sml == matrix[i][j]) { x = i; y = j; } } } cout << sml << n ; output[tree[0] - 1] = x; output[tree[1] - 1] = y; for (int i = 2; i < n; i++) { int c = 0 ^ 1 ^ 2 ^ x ^ y; output[tree[i] - 1] = c; x = y; y = c; } for (int i = 0; i < int(n); i++) cout << output[i] + 1 << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 5000 + 10; int n, T; double p[MAXN]; int t[MAXN]; double dp[MAXN][MAXN]; int main() { scanf( %d%d , &n, &T); for (int i = 1; i <= n; ++i) { scanf( %lf%d , &p[i], &t[i]); p[i] *= 0.01; } double ans = 0.0; dp[0][0] = 1.0; for (int i = 1; i <= n; ++i) { double sum = 0.0; double npn = pow(1.0 - p[i], t[i]); for (int j = 1; j <= T; ++j) { sum += dp[i - 1][j - 1]; if (j > t[i]) { sum -= dp[i - 1][j - t[i] - 1] * npn; } dp[i][j] += sum * p[i]; if (j >= t[i]) { dp[i][j] += dp[i - 1][j - t[i]] * npn; } sum *= 1.0 - p[i]; ans += dp[i][j]; } } printf( %.8f n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFRTN_PP_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__AND3B_BEHAVIORAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_BEHAVIORAL_V |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* XY routing
*
* Routing Function
* ================
*
* Simple XY routing
* - Function updates flit with the output port required at next router
* and modifies displacement fields as head flit gets closer to
* destination.
*
* More complex routing algorithms may be implemented by making edits here
* and to the flit's control field defn.
*
* Valid Turn?
* ===========
*
* LAG_route_valid_turn(from, to)
*
* This function is associated with the routing algorithm and is used to
* optimize the synthesis of the implementation by indicating impossible
* turns - hence superfluous logic.
*
* Valid Input PL
* ==============
*
* Does a particular input PL exist. e.g. Tile input port may only contain
* one PL buffer.
*
*/
//router_radix defined in parameters.v
function automatic bit LAG_route_valid_input_pl;
input integer port;
input integer pl;
bit valid;
begin
valid=1'b1;
if (port==`TILE) begin
if (pl>=router_num_pls_on_entry) valid=1'b0;
end
LAG_route_valid_input_pl=valid;
end
endfunction // automatic
function automatic bit LAG_route_valid_turn;
input output_port_t from;
input output_port_t to;
bit valid;
begin
valid=1'b1;
// flits don't leave on the same port as they entered
if (from==to) valid=1'b0;
`ifdef OPT_MESHXYTURNS
// Optimise turns for XY routing in a mesh
if (((from==`NORTH)||(from==`SOUTH))&&((to==`EAST)||(to==`WEST))) valid=1'b0;
`endif
LAG_route_valid_turn=valid;
end
endfunction // bit
module LAG_route (flit_in, flit_out, clk, rst_n);
input flit_t flit_in;
output flit_t flit_out;
input clk, rst_n;
function flit_t next_route;
input flit_t flit_in;
logic [4:0] route;
flit_t new_flit;
x_displ_t x_disp;
y_displ_t y_disp;
begin
new_flit = flit_in;
x_disp = x_displ_t ' (flit_in.data[router_radix + `X_ADDR_BITS : router_radix]);
y_disp = y_displ_t ' (flit_in.data[router_radix + `X_ADDR_BITS + `Y_ADDR_BITS + 1 : router_radix + `X_ADDR_BITS + 1]);
// Simple XY Routing
if (x_disp!=0) begin
if (x_disp>0) begin
route = `port5id_east;
x_disp--;
end else begin
route = `port5id_west;
x_disp++;
end
end else begin
if (y_disp==0) begin
route=`port5id_tile;
end else if (y_disp>0) begin
route=`port5id_south;
y_disp--;
end else begin
route=`port5id_north;
y_disp++;
end
end
new_flit.data[router_radix - 1 : 0] = route;
new_flit.data[router_radix + `X_ADDR_BITS : router_radix] = x_displ_t ' (x_disp);
new_flit.data[router_radix + `X_ADDR_BITS + `Y_ADDR_BITS + 1 : router_radix + `X_ADDR_BITS + 1] = y_displ_t ' (y_disp);
next_route = new_flit;
end
endfunction // flit_t
assign flit_out=next_route(flit_in);
endmodule // route
|
#include <bits/stdc++.h> using namespace std; int n; char in[100005]; int main() { scanf( %d %s , &n, in); for (int i = 1; i < n; i++) { if (in[i] == in[i - 1]) { for (int j = i;; j++) { in[j] = 1 - (in[j] - 0 ) + 0 ; if (in[j + 1] != in[j]) break; } break; } } char prv = 2 ; int cnt = 0; for (int i = 0; i < n; i++) if (in[i] != prv) { prv = in[i]; cnt++; } printf( %d , cnt); return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = (N-1)*log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
wire [bw-1:0] signal_in;
output [bw-1:0] signal_out;
wire [bw-1:0] signal_out;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
//FIXME Note that this section has pipe and diff reversed
// It still works, but is confusing
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable & strobe_out)
begin
if(strobe_in)
integrator[0] <= #1 integrator[0] + pipeline[N-1];
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
for(i=0;i<N;i=i+1)
begin
differentiator[i] <= #1 0;
pipeline[i] <= #1 0;
end
end
else if (enable && strobe_in)
begin
differentiator[0] <= #1 signal_in_ext;
pipeline[0] <= #1 signal_in_ext - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end
wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
cic_int_shifter #(bw)
cic_int_shifter(rate,signal_out_unnorm,signal_out);
endmodule // cic_interp
|
// Provides a FIFO interface for JTAG communication.
module jtag_fifo (
input rx_clk,
input [11:0] rx_data,
input wr_en, rd_en,
output [8:0] tx_data,
output tx_full, tx_empty
);
wire jt_capture, jt_drck, jt_reset, jt_sel, jt_shift, jt_tck, jt_tdi, jt_update;
wire jt_tdo;
BSCAN_SPARTAN6 # (.JTAG_CHAIN(1)) jtag_blk (
.CAPTURE(jt_capture),
.DRCK(jt_drck),
.RESET(jt_reset),
.RUNTEST(),
.SEL(jt_sel),
.SHIFT(jt_shift),
.TCK(jt_tck),
.TDI(jt_tdi),
.TDO(jt_tdo),
.TMS(),
.UPDATE(jt_update)
);
reg captured_data_valid = 1'b0;
reg [12:0] dr;
// FIFO from TCK to rx_clk
wire full;
fifo_generator_v8_2 tck_to_rx_clk_blk (
.wr_clk(jt_tck),
.rd_clk(rx_clk),
.din({7'd0, dr[8:0]}),
.wr_en(jt_update & jt_sel & !full),
.rd_en(rd_en & !tx_empty),
.dout(tx_data),
.full(full),
.empty(tx_empty)
);
// FIFO from rx_clk to TCK
wire [11:0] captured_data;
wire empty;
fifo_generator_v8_2 rx_clk_to_tck_blk (
.wr_clk(rx_clk),
.rd_clk(jt_tck),
.din({4'd0, rx_data}),
.wr_en(wr_en & !tx_full),
.rd_en(jt_capture & ~empty & ~jt_reset),
.dout(captured_data),
.full(tx_full),
.empty(empty)
);
assign jt_tdo = captured_data_valid ? captured_data[0] : dr[0];
always @ (posedge jt_tck or posedge jt_reset)
begin
if (jt_reset == 1'b1)
begin
dr <= 13'd0;
end
else if (jt_capture == 1'b1)
begin
// Capture-DR
captured_data_valid <= !empty;
dr <= 13'd0;
end
else if (jt_shift == 1'b1 & captured_data_valid)
begin
// Shift-DR
captured_data_valid <= 1'b0;
dr <= {jt_tdi, 1'b1, captured_data[11:1]};
end
else if (jt_shift == 1'b1)
begin
dr <= {jt_tdi, dr[12:1]};
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A221OI_BEHAVIORAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; int m; cin >> n >> m; vector<vector<bool>> arr(n, vector<bool>(m, 0)); long long int answ = 0; vector<int> hor(n, 0); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int temp; cin >> temp; if (!temp) { hor[i]++; } arr[i][j] = (bool)temp; } } vector<int> vert(m, 0); for (int j = 0; j < m; j++) { for (int i = 0; i < n; i++) { if (!arr[i][j]) { vert[j]++; } } } for (int i = 0; i < n; i++) { int past = 0; for (int j = 0; j < m; j++) { if (arr[i][j]) { answ += hor[i] - past; break; } else { past++; } } past = 0; for (int j = m - 1; j >= 0; j--) { if (arr[i][j]) { answ += hor[i] - past; break; } else { past++; } } } for (int j = 0; j < m; j++) { int past = 0; for (int i = 0; i < n; i++) { if (arr[i][j]) { answ += vert[j] - past; break; } else { past++; } } past = 0; for (int i = n - 1; i >= 0; i--) { if (arr[i][j]) { answ += vert[j] - past; break; } else { past++; } } } cout << answ << endl; return 0; } |
// file: timer.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1 100.000 0.000 50.0 200.000 50.000
// CLK_OUT2 100.000 0.000 50.0 200.000 50.000
//
//----------------------------------------------------------------------------
// Input Clock Input Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// primary 100.000 0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "timer,clk_wiz_v1_8,{component_name=timer,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module timer
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
assign clkfb = CLK_OUT1;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clk0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clk0));
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long mul(long long a, long long b) { return a * b % mod; } long long add(long long a, long long b) { long long res = a + b; if (res >= mod) { res -= mod; } return res; } const long long MAXN = 1e6 + 5; vector<long long> fact(MAXN); vector<long long> fact_obr(MAXN); vector<long long> pow_n(MAXN); vector<long long> pow_m(MAXN); long long n; long long m; long long fast_pow(long long a, long long b) { if (b == 0) { return 1; } else { if (b % 2 == 1) { return mul(fast_pow(a, b - 1), a); } else { long long res = fast_pow(a, b / 2); return mul(res, res); } } } void pre_calc() { fact[0] = 1; fact_obr[0] = fast_pow(fact[0], mod - 2); pow_n[0] = 1; pow_m[0] = 1; for (long long i = 1; i < MAXN; ++i) { fact[i] = mul(fact[i - 1], i); fact_obr[i] = fast_pow(fact[i], mod - 2); pow_n[i] = mul(pow_n[i - 1], n); pow_m[i] = mul(pow_m[i - 1], m); } } long long A(long long n, long long k) { return mul(fact[n], fact_obr[n - k]); } long long C(long long n, long long k) { if (k > n) { return 0; } if (n == 0 && k != 0) { return 0; } return mul(A(n, k), fact_obr[k]); } long long f(long long y) { if (y == n) { return 1; } return mul(y, pow_n[n - y - 1]); } int32_t main() { cin >> n >> m; pre_calc(); long long ans = 0; for (long long edges = 1; edges < n; ++edges) { long long _add = 1; _add = mul(_add, A(n - 2, edges - 1)); _add = mul(_add, f(edges + 1)); _add = mul(_add, C(m - 1, edges - 1)); _add = mul(_add, pow_m[n - edges - 1]); ans = add(ans, _add); } cout << ans; } |
module fourDeepRollingAverage_tc (
input clk,
input signed [12:0] in,
output reg signed [12:0] out = 13'd0);
reg [1:0] mstr_ctr = 2'b00;
reg [1:0] ctr1 = 2'b00, ctr2 = 2'b00, ctr3 = 2'b00, ctr4 = 2'b00;
reg signed [14:0] acc1 = 15'd0, acc2 = 15'd0, acc3 = 15'd0, acc4 = 15'd0;
//reg [14:0] sum = 16'd0;
always @(posedge clk) begin
if(mstr_ctr == 2'b11) mstr_ctr <= 2'b00;
else mstr_ctr <= mstr_ctr + 1'b1;
case (mstr_ctr)
2'b00: begin
ctr2 <= ctr2 + 1'b1;
ctr1 <= 2'b00;
ctr3 <= ctr3 + 1'b1;
ctr4 <= ctr4 + 1'b1;
end
2'b01: begin
ctr1 <= ctr1 + 1'b1;
ctr3 <= ctr3 + 1'b1;
ctr2 <= 2'b00;
ctr4 <= ctr4 + 1'b1;
end
2'b10: begin
ctr1 <= ctr1 + 1'b1;
ctr2 <= ctr2 + 1'b1;
ctr4 <= ctr4 + 1'b1;
ctr3 <= 2'b00;
end
2'b11: begin
ctr4 <= 2'b00;
ctr2 <= ctr2 + 1'b1;
ctr3 <= ctr3 + 1'b1;
ctr1 <= ctr1 + 1'b1;
end
endcase
if (ctr1==2'b11) begin
out <= (acc1 + in) >> 2;
acc1 <= 15'd0;
acc2 <= acc2 + in;
acc3 <= acc3 + in;
acc4 <= acc4 + in;
end else if (ctr2==2'b11) begin
out <= (acc2 + in) >> 2;
acc1 <= acc1 + in;
acc2 <= 15'd0;
acc3 <= acc3 + in;
acc4 <= acc4 + in;
end else if (ctr3==2'b11) begin
out <= (acc3 + in) >> 2;
acc1 <= acc1 + in;
acc2 <= acc2 + in;
acc3 <= 15'd0;
acc4 <= acc4 + in;
end else if (ctr4==2'b11) begin
out <= (acc4 + in) >> 2;
acc1 <= acc1 + in;
acc2 <= acc2 + in;
acc3 <= acc3 + in;
acc4 <= 15'd0;
end else begin
out <= 15'd0;
acc1 <= acc1 + in;
acc2 <= acc2 + in;
acc3 <= acc3 + in;
acc4 <= acc4 + in;
end
//assign out = sum[14:2];
end
endmodule
|
`include "bsg_cache.vh"
module bsg_test_master
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, localparam dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
, localparam ring_width_lp=`bsg_cache_pkt_width(addr_width_p, data_width_p)
, localparam rom_addr_width_lp=32
)
(
input clk_i
, input reset_i
, output logic [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o
, output logic [num_cache_p-1:0] dma_pkt_v_o
, input [num_cache_p-1:0] dma_pkt_yumi_i
, input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_ready_o
, output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_yumi_i
, output logic done_o
);
// trace replay
//
// send trace: {opcode(5), addr, data}
// recv trace: {filler(5+32), data}
//
logic [num_cache_p-1:0] tr_v_li;
logic [num_cache_p-1:0][ring_width_lp-1:0] tr_data_li;
logic [num_cache_p-1:0] tr_ready_lo;
logic [num_cache_p-1:0] tr_v_lo;
logic [num_cache_p-1:0][ring_width_lp-1:0] tr_data_lo;
logic [num_cache_p-1:0] tr_yumi_li;
logic [num_cache_p-1:0][rom_addr_width_lp-1:0] rom_addr;
logic [num_cache_p-1:0][ring_width_lp+4-1:0] rom_data;
logic [num_cache_p-1:0] tr_done_lo;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_lp)
,.rom_addr_width_p(rom_addr_width_lp)
) tr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(1'b1)
,.v_i(tr_v_li[i])
,.data_i(tr_data_li[i])
,.ready_o(tr_ready_lo[i])
,.v_o(tr_v_lo[i])
,.data_o(tr_data_lo[i])
,.yumi_i(tr_yumi_li[i])
,.rom_addr_o(rom_addr[i])
,.rom_data_i(rom_data[i])
,.done_o(tr_done_lo[i])
,.error_o()
);
bsg_trace_rom #(
.rom_addr_width_p(rom_addr_width_lp)
,.rom_data_width_p(ring_width_lp+4)
,.id_p(i)
) trace_rom (
.rom_addr_i(rom_addr[i])
,.rom_data_o(rom_data[i])
);
end
assign done_o = &tr_done_lo;
// cache
//
`declare_bsg_cache_pkt_s(addr_width_p,data_width_p);
bsg_cache_pkt_s [num_cache_p-1:0] cache_pkt;
logic [num_cache_p-1:0] cache_v_li;
logic [num_cache_p-1:0] cache_ready_lo;
logic [num_cache_p-1:0][data_width_p-1:0] cache_data_lo;
logic [num_cache_p-1:0] cache_v_lo;
logic [num_cache_p-1:0] cache_yumi_li;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_cache #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
) cache (
.clk_i(clk_i)
,.reset_i(reset_i)
,.cache_pkt_i(cache_pkt[i])
,.v_i(cache_v_li[i])
,.ready_o(cache_ready_lo[i])
,.data_o(cache_data_lo[i])
,.v_o(cache_v_lo[i])
,.yumi_i(cache_yumi_li[i])
,.dma_pkt_o(dma_pkt_o[i])
,.dma_pkt_v_o(dma_pkt_v_o[i])
,.dma_pkt_yumi_i(dma_pkt_yumi_i[i])
,.dma_data_i(dma_data_i[i])
,.dma_data_v_i(dma_data_v_i[i])
,.dma_data_ready_o(dma_data_ready_o[i])
,.dma_data_o(dma_data_o[i])
,.dma_data_v_o(dma_data_v_o[i])
,.dma_data_yumi_i(dma_data_yumi_i[i])
,.v_we_o()
);
assign cache_pkt[i] = tr_data_lo[i];
assign cache_v_li[i] = tr_v_lo[i];
assign tr_yumi_li[i] = tr_v_lo[i] & cache_ready_lo[i];
assign tr_data_li[i] = {{(ring_width_lp-data_width_p){1'b0}}, cache_data_lo[i]};
assign tr_v_li[i] = cache_v_lo[i];
assign cache_yumi_li[i] = cache_v_lo[i] & tr_ready_lo[i];
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_test_master)
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, l, m, n, p, x, y; string s1, s2, s3, s4; cin >> s1 >> s2; cin >> n; cout << s1 << << s2; cout << endl; for (i = 0; i < n; i++) { cin >> s3 >> s4; if (s3 == s1) { s1 = s4; cout << s1 << << s2; } if (s3 == s2) { s2 = s4; cout << s1 << << s2; } cout << endl; } } |
#include <bits/stdc++.h> int64_t a[400005], b[200005]; int64_t len; int n; bool check(int64_t value) { std::vector<std::pair<int64_t, int64_t>> v; for (int i = 0; i < n; ++i) { auto rg = std::make_pair(b[i] - value, b[i] + value); if (rg.first < 0) { rg.first += len; rg.second += len; } v.push_back(rg); if (rg.second < len) v.emplace_back(rg.first + len, rg.second + len); } std::sort(v.begin(), v.end()); int pa = 0, pr = 0; while (pr < (int)v.size()) { while (pa < n * 2 && (a[pa] < v[pr].first || a[pa] > v[pr].second)) ++pa; if (pa >= n * 2) return false; else { ++pa; ++pr; } } return true; } int main(int argc, char* argv[]) { scanf( %d%lld , &n, &len); for (int i = 0; i < n; ++i) scanf( %lld , &a[i]); for (int i = 0; i < n; ++i) scanf( %lld , &b[i]); std::sort(a, a + n); for (int i = 0; i < n; ++i) a[n + i] = a[i] + len; int64_t left = 0, right = len; int64_t ans = 0; while (right >= left) { int64_t mid = (left + right) / 2; if (check(mid)) { ans = mid; right = mid - 1; } else left = mid + 1; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct line { long long int a, b, c; }; int main() { long long int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; long long int n; cin >> n; vector<line> data(n); for (auto &p : data) { cin >> p.a >> p.b >> p.c; } vector<bool> s1(n), s2(n); for (int i = 0; i < n; ++i) { s1[i] = data[i].a * x1 + data[i].b * y1 + data[i].c > 0; s2[i] = data[i].a * x2 + data[i].b * y2 + data[i].c > 0; } int cnt = 0; for (int i = 0; i < n; ++i) { cnt += s1[i] ^ s2[i]; } cout << cnt << endl; return 0; } |
`timescale 1ns / 1ps
module posManager (
input wire clk,
output wire [15:0] pos11,
output wire [15:0] pos12,
output wire [15:0] pos21,
output wire [15:0] pos22,
output wire [15:0] pos_diff,
output reg [31:0] count_clk,
input wire m1,
input wire m2,
input wire [1:0] clear
);
reg m1_delay, m2_delay, m1_clean, m2_clean;
initial begin
count_clk = 32'b0;
m1_delay = 1'b0;
m2_delay = 1'b0;
m1_clean = 1'b0;
m2_clean = 1'b0;
end
always @ (posedge clk) begin
if (clear[0]) count_clk <= 32'b0;
else count_clk <= count_clk + 1'b1;
m1_delay <= m1;
m2_delay <= m2;
m1_clean <= m1_delay;
m2_clean <= m2_delay;
end
wire subtract;
assign subtract = pos12[15] | pos22[15];
reg [15:0] distance;
always @ (*) begin
if (pos12 < pos22) distance = pos12;
else distance = pos22;
end
assign pos_diff = pos12 - pos22;
posCounter pos_counter1 (
.clk(clk),
.pos1(pos11),
.pos2(pos12),
.sensor(m1_clean),
.clear(clear),
.subtract(subtract),
.distance(distance)
);
posCounter pos_counter2 (
.clk(clk),
.pos1(pos21),
.pos2(pos22),
.sensor(m2_clean),
.clear(clear),
.subtract(subtract),
.distance(distance)
);
endmodule
module posManager_testbench ();
reg clk;
wire [15:0] pos11, pos12, pos21, pos22, pos_diff;
wire [31:0] count_clk;
reg m1, m2;
reg [1:0] clear;
posManager dut (
.clk(clk),
.pos11(pos11),
.pos12(pos12),
.pos21(pos21),
.pos22(pos22),
.pos_diff(pos_diff),
.count_clk(count_clk),
.m1(m1),
.m2(m2),
.clear(clear)
);
parameter CLOCK_PERIOD = 10;
initial begin
clk <= 0;
forever #(CLOCK_PERIOD / 2) clk <= ~clk;
end
integer i;
initial begin
m1 <= 0; m2 <= 0; clear <= 2'b00; @(posedge clk);
clear <= 2'b01; @(posedge clk);
clear <= 2'b00; @(posedge clk);
m1 <= 1; @(posedge clk);
m1 <= 0; @(posedge clk);
m1 <= 1; @(posedge clk);
m1 <= 0; @(posedge clk);
m1 <= 1; @(posedge clk);
m1 <= 0; @(posedge clk);
for (i = 0; i < 16; i = i + 1) begin
m1 <= 0; m2 <= 0; @(posedge clk);
m1 <= 1; m2 <= 1; @(posedge clk);
end
clear <= 2'b01; @(posedge clk);
clear <= 2'b00; @(posedge clk);
for (i = 0; i < 32768; i = i + 1) begin
m1 <= 0; m2 <= 0; @(posedge clk);
m1 <= 1; m2 <= 1; @(posedge clk);
end
clear <= 2'b10; @(posedge clk);
clear <= 2'b00; @(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
for (i = 0; i < 16; i = i + 1) begin
m1 <= 0; m2 <= 0; @(posedge clk);
m1 <= 1; m2 <= 1; @(posedge clk);
end
clear <= 2'b11; @(posedge clk);
clear <= 2'b00; @(posedge clk);
m2 <= 0; @(posedge clk);
m2 <= 1; @(posedge clk);
m2 <= 0; @(posedge clk);
m2 <= 1; @(posedge clk);
m2 <= 0; @(posedge clk);
m2 <= 1; @(posedge clk);
m2 <= 0; @(posedge clk);
m2 <= 1; @(posedge clk);
m2 <= 0; @(posedge clk);
m2 <= 1; @(posedge clk);
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_1_V
`define SKY130_FD_SC_LS__O311AI_1_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311ai_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_1_V
|
`default_nettype none
`timescale 1ns/1ns
module tb_sys_level;
`include "../task/task_disp_branch.v"
`include "../task/task_disp_loadstore.v"
localparam PL_CORE_CYCLE = 20; //It's necessary "Core Clock == Bus Clock". This restriction is removed near future.
localparam PL_BUS_CYCLE = 20; //
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
localparam PL_GCI_SIZE = 32'h0001_0000;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
wire iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire [3:0] oMEMORY_MASK;
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
wire iMEMORY_VALID;
wire oMEMORY_BUSY;
wire [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
mist1032isa TARGET(
/****************************************
System
****************************************/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iBUS_CLOCK),
.iDPS_CLOCK(iDPS_CLOCK),
.inRESET(inRESET),
/****************************************
SCI
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(oMEMORY_REQ),
.iMEMORY_LOCK(iMEMORY_LOCK),
.oMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.oMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.oMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.iMEMORY_VALID(iMEMORY_VALID),
.oMEMORY_BUSY(oMEMORY_BUSY),
.iMEMORY_DATA(iMEMORY_DATA),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(oGCI_REQ), //Input
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ), //Output
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
.oDEBUG_PC(oDEBUG_PC),
.oDEBUG0(oDEBUG0),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
$display("Check Start");
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
//GCI Init
#(PL_BUS_CYCLE*32);
while(oGCI_BUSY) #(PL_BUS_CYCLE);
iGCI_REQ = 1'b1;
iGCI_DATA = PL_GCI_SIZE;
#(PL_BUS_CYCLE);
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
//#15000000 begin
# begin
$stop;
end
end
/******************************************************
Memory Model
******************************************************/
sim_memory_model #(1, "tb_inst_test.hex") MEMORY_MODEL(
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//Req
.iMEMORY_REQ(oMEMORY_REQ),
.oMEMORY_LOCK(iMEMORY_LOCK),
.iMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iMEMORY_MASK(oMEMORY_MASK),
.iMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.iMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.iMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.oMEMORY_VALID(iMEMORY_VALID),
.iMEMORY_LOCK(oMEMORY_BUSY),
.oMEMORY_DATA(iMEMORY_DATA)
);
always@(posedge iCORE_CLOCK)begin
if(inRESET)begin
//task_disp_branch();
task_disp_loadstore();
end
end
/******************************************************
Assertion
******************************************************/
/*
reg assert_check_flag;
reg [31:0] assert_wrong_number;
reg [31:0] assert_wrong_type;
reg [31:0] assert_result;
reg [31:0] assert_expect;
always@(posedge iCORE_CLOCK)begin
if(inRESET && oMEMORY_REQ && !iMEMORY_LOCK && oMEMORY_ORDER == 2'h2 && oMEMORY_RW)begin
//Finish Check
if(oMEMORY_ADDR == 32'h0002_0004)begin
if(!assert_check_flag)begin
$display("[SIM-ERR]Wrong Data.");
$display("[SIM-ERR]Wrong Type : %d", assert_wrong_type);
$display("[SIM-ERR]Index:%d, Expect:%x, Result:%x", assert_wrong_number, assert_expect, assert_result);
$display("[SIM-ERR]Simulation Finished.");
$finish;
end
else begin
$display("[SIM-OK]Simulation Finished.");
$finish;
end
end
//Check Flag
else if(oMEMORY_ADDR == 32'h0002_0000)begin
assert_check_flag = oMEMORY_DATA[24];
end
//Error Number
else if(oMEMORY_ADDR == 32'h0002_000c)begin
assert_wrong_number = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Type
else if(oMEMORY_ADDR == 32'h0002_0008)begin
assert_wrong_type = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Result
else if(oMEMORY_ADDR == 32'h0002_0010)begin
assert_result = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Expect
else if(oMEMORY_ADDR == 32'h0002_0014)begin
assert_expect = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
end
end
*/
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; unsigned long long int ans = 1; int main() { int i, j, k, l, c = 0, fuck = 0; string s; cin >> s; l = s.size(); s += 9 ; for (i = 0; i < l; i++) { if (fuck == 1) { if (int(s[i] - 48) + int(s[i + 1] - 48) == 9) c += 1; else { if (c % 2 != 0) ans *= (c / 2 + 1); fuck = 0; } } if (fuck == 0) { if (int(s[i] - 48) + int(s[i + 1] - 48) == 9) { fuck = 1; c = 2; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> struct Mock { Mock(int n, const std::string &s) : n(n), s(s) {} std::vector<std::string> ask(int l, int r) { if (l > r) { return {}; } std::vector<std::string> substrings; for (int i = l - 1; i < r; ++i) { for (int j = 1; i + j <= r; ++j) { auto ss = s.substr(i, j); std::shuffle(ss.begin(), ss.end(), gen); substrings.push_back(ss); } } std::shuffle(substrings.begin(), substrings.end(), gen); return substrings; } void out(const std::string &t) { assert(s == t); } int n; private: std::string s; std::mt19937 gen; }; struct IO { IO() { scanf( %d , &n); } std::vector<std::string> ask(int l, int r) { if (l > r) { return {}; } printf( ? %d %d n , l, r); fflush(stdout); std::vector<char> buf(r - l + 2); std::vector<std::string> substrings; int size = (r - l + 2) * (r - l + 1) / 2; for (int i = 0; i < size; ++i) { scanf( %s , buf.data()); substrings.push_back(buf.data()); } return substrings; } void out(const std::string &t) { printf( ! %s n , t.c_str()); fflush(stdout); } int n; }; static const int C = 26; using Count = std::array<int, C>; Count toCount(const std::string &s) { Count result; memset(result.data(), 0, sizeof(result)); for (char c : s) { result[c - a ]++; } return result; } template <typename IO> std::string solve(IO &io) { int n = io.n; if (n == 1) { return io.ask(1, 1)[0]; } int n2 = n >> 1; std::vector<int> s(n, 0); { std::map<Count, int> halfs; for (auto &&s : io.ask(1, n2)) { halfs[toCount(s)]++; } for (auto &&s : io.ask(2, n2)) { halfs[toCount(s)]--; } std::vector<std::pair<int, Count>> counts; for (auto &&kv : halfs) { if (kv.second) { int size = 0; for (int c : kv.first) { size += c; } counts.emplace_back(size, kv.first); } } std::sort(counts.begin(), counts.end()); assert(static_cast<int>(counts.size()) == n2); for (int i = 0; i < n2; ++i) { auto count = counts[i].second; for (int j = 0; j < i; ++j) { count[s[j]]--; } while (!count[s[i]]) { s[i]++; } } } { std::vector<Count> counts(n + 1); for (auto &&s : io.ask(1, n)) { auto count = toCount(s); for (int j = 0; j < C; ++j) { counts[s.length()][j] += count[j]; } } for (int i = n + 1 >> 1; i >= 1; --i) { auto count = counts[i]; for (int j = 0; j < C; ++j) { count[j] -= counts[i - 1][j]; } int left = i - 1, right = n - i; for (int j = left; j < right; ++j) { count[s[j]]--; } while (!count[s[right]]) { s[right]++; } } } std::string buf(n, ); for (int i = 0; i < n; ++i) { buf[i] = a + s[i]; } return buf; } int main() { IO io; io.out(solve(io)); } |
Require Import Int63 FloatClass.
(** * Definition of the interface for primitive floating-point arithmetic
This interface provides processor operators for the Binary64 format of the
IEEE standard. *)
(** ** Type definition for the co-domain of [compare] *)
Variant float_comparison : Set := FEq | FLt | FGt | FNotComparable.
Register float_comparison as kernel.ind_f_cmp.
Register float_class as kernel.ind_f_class.
(** ** The main type *)
(** [float]: primitive type for Binary64 floating-point numbers. *)
Primitive float := #float64_type.
(** ** Syntax support *)
Declare Scope float_scope.
Delimit Scope float_scope with float.
Bind Scope float_scope with float.
Declare ML Module "float_syntax_plugin".
(** ** Floating-point operators *)
Primitive classify := #float64_classify.
Primitive abs := #float64_abs.
Primitive sqrt := #float64_sqrt.
Primitive opp := #float64_opp.
Notation "- x" := (opp x) : float_scope.
Primitive eqb := #float64_eq.
Notation "x == y" := (eqb x y) (at level 70, no associativity) : float_scope.
Primitive ltb := #float64_lt.
Notation "x < y" := (ltb x y) (at level 70, no associativity) : float_scope.
Primitive leb := #float64_le.
Notation "x <= y" := (leb x y) (at level 70, no associativity) : float_scope.
Primitive compare := #float64_compare.
Notation "x ?= y" := (compare x y) (at level 70, no associativity) : float_scope.
Primitive mul := #float64_mul.
Notation "x * y" := (mul x y) : float_scope.
Primitive add := #float64_add.
Notation "x + y" := (add x y) : float_scope.
Primitive sub := #float64_sub.
Notation "x - y" := (sub x y) : float_scope.
Primitive div := #float64_div.
Notation "x / y" := (div x y) : float_scope.
(** ** Conversions *)
(** [of_int63]: convert a primitive integer into a float value.
The value is rounded if need be. *)
Primitive of_int63 := #float64_of_int63.
(** Specification of [normfr_mantissa]:
- If the input is a float value with an absolute value inside $[0.5, 1.)$#[0.5, 1.)#;
- Then return its mantissa as a primitive integer.
The mantissa will be a 53-bit integer with its most significant bit set to 1;
- Else return zero.
The sign bit is always ignored. *)
Primitive normfr_mantissa := #float64_normfr_mantissa.
(** ** Exponent manipulation functions *)
(** [frshiftexp]: convert a float to fractional part in $[0.5, 1.)$#[0.5, 1.)#
and integer part. *)
Primitive frshiftexp := #float64_frshiftexp.
(** [ldshiftexp]: multiply a float by an integral power of 2. *)
Primitive ldshiftexp := #float64_ldshiftexp.
(** ** Predecesor/Successor functions *)
(** [next_up]: return the next float towards positive infinity. *)
Primitive next_up := #float64_next_up.
(** [next_down]: return the next float towards negative infinity. *)
Primitive next_down := #float64_next_down.
(** ** Special values (needed for pretty-printing) *)
Definition infinity := Eval compute in div (of_int63 1) (of_int63 0).
Definition neg_infinity := Eval compute in opp infinity.
Definition nan := Eval compute in div (of_int63 0) (of_int63 0).
Register infinity as num.float.infinity.
Register neg_infinity as num.float.neg_infinity.
Register nan as num.float.nan.
(** ** Other special values *)
Definition one := Eval compute in (of_int63 1).
Definition zero := Eval compute in (of_int63 0).
Definition neg_zero := Eval compute in (-zero)%float.
Definition two := Eval compute in (of_int63 2).
(** ** Predicates and helper functions *)
Definition is_nan f := negb (f == f)%float.
Definition is_zero f := (f == zero)%float. (* note: 0 == -0 with floats *)
Definition is_infinity f := (abs f == infinity)%float.
Definition is_finite (x : float) := negb (is_nan x || is_infinity x).
(** [get_sign]: return [true] for [-] sign, [false] for [+] sign. *)
Definition get_sign f :=
let f := if is_zero f then (one / f)%float else f in
(f < zero)%float.
|
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; int n; vector<int> a[200]; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout << fixed; cin >> n; int k = (1 + sqrt(1 + 8 * n)) / 2, x = 1; cout << k << endl; for (int i = 1; i <= k; i++) { for (int j = i + 1; j <= k; j++) { a[i].push_back(x); a[j].push_back(x); x++; } } for (int i = 1; i <= k; i++) { int m = a[i].size(); for (int j = 0; j < m; j++) { cout << a[i][j] << (j == m - 1 ? n : ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; enum { DUNNO = -1, AB, BA }; vector<pair<int, int> > E[200010]; map<pair<int, int>, int> edge_id; int dir[200010]; int val[200010]; bool vis[200010]; int main() { int N, M; cin >> N >> M; memset(val, 0, sizeof(val)); memset(vis, 0, sizeof(vis)); memset(dir, DUNNO, sizeof(dir)); int a, b, c; for (int j = (1); j <= (M); ++j) { scanf( %d%d%d , &a, &b, &c); E[a].push_back(make_pair(b, c)); E[b].push_back(make_pair(a, c)); edge_id[make_pair(a, b)] = j; edge_id[make_pair(b, a)] = -j; val[a] += c; val[b] += c; } for (int i = (2); i <= (N - 1); ++i) val[i] /= 2; queue<int> Q; val[1] = 0; Q.push(1); while (!Q.empty()) { int i = Q.front(); Q.pop(); if (vis[i]) continue; vis[i] = true; assert(val[i] == 0); int numE = E[i].size(); for (int x = 0; x < (numE); ++x) { int j = E[i][x].first; int c = E[i][x].second; if (vis[j]) continue; int e = edge_id[make_pair(i, j)]; if (dir[abs(e)] != DUNNO) continue; if (e > 0) dir[e] = 0; else dir[-e] = 1; val[j] -= c; if (!val[j]) Q.push(j); } } for (int j = (1); j <= (M); ++j) cout << dir[j] << endl; } |
#include <bits/stdc++.h> using namespace std; int n, cnt; char phone[128]; int main() { scanf( %d , &n); scanf( %s , phone); cnt = 0; for (int i = 0; i < n; i++) { if (cnt == 2 and n - i >= 2) { printf( - ); cnt = 0; } printf( %c , phone[i]); cnt++; } printf( n ); return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_f2i(
input sys_clk,
input alu_rst,
input [31:0] a,
input valid_i,
output reg [31:0] r,
output reg valid_o
);
wire a_sign = a[31];
wire [7:0] a_expn = a[30:23];
wire [23:0] a_mant = {1'b1, a[22:0]};
reg [30:0] shifted;
always @(*) begin
if(a_expn >= 8'd150)
shifted = a_mant << (a_expn - 8'd150);
else
shifted = a_mant >> (8'd150 - a_expn);
end
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= valid_i;
if(a_sign)
r <= 32'd0 - {1'b0, shifted};
else
r <= {1'b0, shifted};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long num; cin >> n; set<long> s; while (n > 0) { cin >> num; while (num % 2 == 0) { num = num / 2; } while (num % 3 == 0) { num = num / 3; } s.insert(num); n--; } if (s.size() == 1) { cout << Yes ; } else { cout << No ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, cnt[100015], x[100015], y[100015], z[100015]; vector<int> a[100015]; int getpos(int i, int u) { if (x[i] == u) return 0; if (y[i] == u) return 1; if (z[i] == u) return 2; } void dfs(int u, int v) { cout << u << ; if (cnt[v] == 0) { cout << v; return; } for (int i : a[u]) if (i) { --cnt[x[i]]; --cnt[y[i]]; --cnt[z[i]]; int k = 3 - getpos(i, u) - getpos(i, v); for (int &j : a[x[i]]) if (j == i) j = 0; for (int &j : a[y[i]]) if (j == i) j = 0; for (int &j : a[z[i]]) if (j == i) j = 0; if (k == 0) dfs(v, x[i]); if (k == 1) dfs(v, y[i]); if (k == 2) dfs(v, z[i]); } } int main() { cin >> n; for (int i = 1; i <= n - 2; ++i) cin >> x[i] >> y[i] >> z[i], a[x[i]].push_back(i), a[y[i]].push_back(i), a[z[i]].push_back(i), ++cnt[x[i]], ++cnt[y[i]], ++cnt[z[i]]; for (int i = 1; i <= n; ++i) if (cnt[i] == 1) { if (cnt[x[a[i][0]]] == 2) dfs(i, x[a[i][0]]); if (cnt[y[a[i][0]]] == 2) dfs(i, y[a[i][0]]); if (cnt[z[a[i][0]]] == 2) dfs(i, z[a[i][0]]); } } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_led_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 3: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire [ 3: 0] data_in;
reg [ 3: 0] data_out;
wire [ 3: 0] out_port;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 15;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[3 : 0];
end
assign out_port = data_out;
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, S[2005]; bool mark[2005][2005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); char c; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> c; mark[i][j] = c - 0 ; if (mark[i][j]) S[j]++; } bool flag; for (int i = 1; i <= n; i++) { flag = 0; for (int j = 1; j <= m; j++) if (mark[i][j]) S[j]--; for (int j = 1; j <= m; j++) if (S[j] == 0) { flag = 1; break; } if (!flag) { cout << YES ; return 0; } for (int j = 1; j <= m; j++) if (mark[i][j]) S[j]++; } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxs = 1e6 + 5; long long root[maxs]; class cmp { bool operator()(const long long &a, const long long &b) { return a < b; } }; void init() { iota(root, root + maxs, 0); } long long find(long long u) { long long f; if (root[u] == u) return u; else { long long f = find(root[u]); root[u] = f; return f; } } void Union(long long x, long long y) { long long u = find(x); long long v = find(y); root[v] = u; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } void update(vector<long long> &BIT, long long ind, long long val) { while (ind < BIT.size()) { BIT[ind] += val; ind += (ind & (-ind)); } } long long query(vector<long long> &BIT, long long ind) { long long sum = 0; while (ind > 0) { sum += BIT[ind]; ind -= (ind & (-ind)); } return sum; } void count_factors() { long long i, j; long long numOfDivisors[maxs] = {0}; long long ans[maxs] = {0}; for (i = 1; i < maxs; i++) for (j = i; j < maxs; j += i) { numOfDivisors[j]++; ans[j]++; } for (i = 1; i < maxs; i++) for (j = i; j < maxs; j += i) if (numOfDivisors[j / i] == 4) ans[j] = min(ans[j], ans[i]); } long long get(long long x, long long y) { if (x == 0) return 1; long long cnt = 0; while (x % y == 0) { cnt++; x /= y; } return cnt; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t, n, i, k, y, x, j, m, r, l; cin >> t; while (t--) { cin >> n >> k; vector<long long> arr(n + 1); for (i = 1; i <= n; i++) { cin >> arr[i]; } vector<vector<long long>> dp(n + 1, vector<long long>(n + 1, 0)); for (i = 1; i <= n; i++) { for (j = 1; j <= i; j++) { dp[i][j] = dp[i - 1][j]; dp[i][j] = max(dp[i - 1][j - 1] + (arr[i] == j), dp[i][j]); } } long long ans = 0; for (i = 1; i <= n; i++) { if (dp[n][i] >= k) ans = i; } if (ans == 0) cout << -1 << n ; else cout << n - ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int res[100005]; int main() { long long int n; scanf( %lld , &n); if (n % 4 == 2 || n % 4 == 3) { printf( -1 ); exit(0); } long long int c = 2; for (long long int i = 0; i < n / 2; i += 2) { res[i] = c; res[i + 1] = n - i; c += 2; } c = 1; for (long long int i = n - 2; i >= n / 2; i -= 2) { res[i] = c; res[i + 1] = n - c; c += 2; } if (n % 2) res[n / 2] = n / 2 + 1; for (long long int i = 0; i < n; i++) printf( %lld , res[i]); } |
#include <bits/stdc++.h> using namespace std; vector<int> v; void solve(int n) { int m = 1; while (n > 0) { if (n & 1) v.push_back(m); n >>= 1; m++; } reverse(v.begin(), v.end()); } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n; cin >> n; solve(n); for (auto it : v) { cout << it << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 6; int main() { int n; cin >> n; string str = ; while (n) { str += ((n % 2) + 0 ); n /= 2; } reverse(str.begin(), str.end()); while (str.size() < 6) str = 0 + str; string ss = ; ss += str[0]; ss += str[5]; ss += str[3]; ss += str[2]; ss += str[4]; ss += str[1]; int ret = 0; for (auto x : ss) ret = ret * 2 + (x - 0 ); cout << ret << n ; } |
#include <bits/stdc++.h> using namespace std; template <typename INT> struct TripleDXY { INT d, x, y; TripleDXY(INT _d = 0, INT _x = 0, INT _y = 0) : d(_d), x(_x), y(_y) {} }; template <typename INT> TripleDXY<INT> egcd(INT a, INT b) { bool neg_a = a < 0; if (neg_a) a = -a; bool neg_b = b < 0; if (neg_b) b = -b; INT x = 0, lastx = 1; INT y = 1, lasty = 0; while (b != 0) { INT t = b; INT q = a / b; b = a % b; a = t; t = x; x = lastx - q * x; lastx = t; t = y; y = lasty - q * y; lasty = t; } return TripleDXY<INT>(a, neg_a ? -lastx : lastx, neg_b ? -lasty : lasty); } long long ChooseMod(int n, int k, int M) { long long res = 1; for (int i = 1; i <= k; ++i, --n) { TripleDXY<int> R = egcd(i, M); assert(R.d == 1); res = (res * n) % M; res = (res * R.x) % M; if (res < 0) res += M; } return res; } int N, K; long long A[2004]; long long R[2004]; long long F[2004]; int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> N >> K; F[0] = 1; for (int i = 1; i < N; ++i) { F[i] = ChooseMod(K - 1 + i, i, 1000000007); } for (int i = 0; i < N; ++i) cin >> A[i]; R[0] = A[0] % 1000000007; for (int i = 1; i < N; ++i) { R[i] = 0; for (int j = 0; j <= i; ++j) { R[i] += (A[j] * F[i - j]); R[i] %= 1000000007; } } for (int i = 0; i < N; ++i) cout << R[i] << ; cout << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { int a; cin >> a; arr[i] = a; } sort(arr, arr + n); for (int j = 0; j < n; j++) { cout << arr[j] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 11, inf = 1e9 + 10; char ch[4] = { D , I , M , A }; int dx[] = {1, -1, 0, 0}, dy[] = {0, 0, -1, 1}, ans = -inf, tans[N][N], n, m; char c[N][N]; bool mark[N][N], indfs[N][N]; bool isOkay(int x, int y) { return (x >= 0 && x < n && y >= 0 && y < m); } void calcans(int i, int j, int X, int Y) { tans[i][j] = max(tans[i][j], tans[X][Y]); } void dfs(int i, int j, int ind) { indfs[i][j] = true; mark[i][j] = true; bool r = false; for (int k = 0; k < 4; k++) { int X = i + dx[k], Y = j + dy[k], t = (ind + 1) % 4; if (!isOkay(X, Y) || c[X][Y] != ch[t]) continue; r = true; if (indfs[X][Y]) { tans[i][j] = inf; continue; } if (mark[X][Y]) { calcans(i, j, X, Y); continue; } dfs(X, Y, t); calcans(i, j, X, Y); } if (!r && c[i][j] != A ) tans[i][j] = -inf; else if (c[i][j] == A ) tans[i][j]++; indfs[i][j] = false; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> c[i][j]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (c[i][j] != D || mark[i][j]) continue; dfs(i, j, 0); } } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) ans = max(ans, tans[i][j]); if (ans <= 0) cout << Poor Dima! ; else if (ans >= inf) cout << Poor Inna! ; else cout << ans; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; inline bool chmax(int& a, int b) { if (a < b) { a = b; return true; } return false; } constexpr int B = 210; int q, n, e, i, j, ans, res, l, r, val, x, mid; void solve() { cin >> n; vector<vector<int>> sum(n + 1, vector<int>(B, 0)); for (i = 0; i < n; i++) { for (j = 0; j < B; j++) sum[i + 1][j] = sum[i][j]; cin >> e; sum[i + 1][e]++; } ans = 0; for (x = 0; x < B; x++) { res = 0; l = 0; r = n; val = 0; while (l < r) { mid = 0; while (l < n and sum[l][x] < val) l++; while (0 < r and sum[n][x] - sum[r][x] < val) r--; if (r <= l) break; for (i = 0; i < B; i++) chmax(mid, sum[r][i] - sum[l][i]); chmax(res, mid + sum[l][x] + sum[l][x]); val++; } chmax(ans, res); } cout << ans << n ; return; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> q; while (q--) { cin >> n; vector<vector<int>> sum(n + 1, vector<int>(B, 0)); for (i = 0; i < n; i++) { for (j = 0; j < B; j++) sum[i + 1][j] = sum[i][j]; cin >> e; sum[i + 1][e]++; } ans = 0; for (x = 0; x < B; x++) { res = 0; l = 0; r = n; val = 0; while (l < r) { mid = 0; while (l < n and sum[l][x] < val) l++; while (0 < r and sum[n][x] - sum[r][x] < val) r--; if (r < l) break; for (i = 0; i < B; i++) chmax(mid, sum[r][i] - sum[l][i]); chmax(res, mid + sum[l][x] + sum[l][x]); val++; } chmax(ans, res); } cout << ans << n ; } return 0; } |
module premuat3_8(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [27:0] o1;
reg signed [27:0] o2;
reg signed [27:0] o3;
reg signed [27:0] o4;
reg signed [27:0] o5;
reg signed [27:0] o6;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1=i_2;
o2=i_4;
o3=i_6;
o4=i_1;
o5=i_3;
o6=i_5;
end
else
begin
o1=i_4;
o2=i_1;
o3=i_5;
o4=i_2;
o5=i_6;
o6=i_3;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=i_7;
endmodule
|
#include <bits/stdc++.h> constexpr int MAXN = 1e5 + 5; using namespace std; int tot, n, cnt; unordered_map<int, int> Map; vector<int> vec; vector<pair<string, int>> opt; string s; inline void discretization() { sort(vec.begin(), vec.end()); cnt = unique(vec.begin(), vec.end()) - vec.begin(); for (int i = 0; i < cnt; i++) Map[vec[i]] = i; } struct Node { Node *lson, *rson; int cnt, l, r; long long sum[5]; } Tree[MAXN << 1]; inline Node *newNode(Node *&root) { return root = &Tree[++tot]; } inline void update(Node *root) { root->cnt = root->lson->cnt + root->rson->cnt; for (int i = 0; i < 5; i++) root->sum[i] = root->lson->sum[i] + root->rson->sum[((i - root->lson->cnt) % 5 + 5) % 5]; } inline void build(int L, int R, Node *root) { root->l = L, root->r = R; if (L == R) return; int mid = (L + R) >> 1; build(L, mid, newNode(root->lson)), build(mid + 1, R, newNode(root->rson)); } inline void modify(int pos, int val, Node *root) { if (root->l == pos && root->r == pos) { root->cnt += val, root->sum[1] += val * vec[pos]; return; } int mid = (root->l + root->r) >> 1; if (pos <= mid) modify(pos, val, root->lson); if (pos > mid) modify(pos, val, root->rson); update(root); } int main() { std::ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 1, x; i <= n; i++) { cin >> s; if (s == add ) cin >> x, opt.push_back({s, x}), vec.push_back(x); else if (s == del ) cin >> x, opt.push_back({s, x}); else opt.push_back({s, 0}); } discretization(), build(0, cnt, Tree); for (auto i : opt) { if (i.first == add ) modify(Map[i.second], 1, Tree); else if (i.first == del ) modify(Map[i.second], -1, Tree); else cout << Tree->sum[3] << endl; } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sd_spi_tb;
reg clk = 0;
always #5 clk = ~clk;
reg rst = 1;
initial #32 rst = 0;
wire sd_clk, sd_mosi, sd_miso;
wire [7:0] clk_div = 12;
wire [7:0] send_dat = 23;
wire [7:0] rcv_dat;
wire ready;
reg go = 0;
initial
begin
repeat (100)
@(posedge clk);
go <= 1;
@(posedge clk);
go <= 0;
end
sd_spi dut(.clk(clk),.rst(rst),
.sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
.clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat),
.go(go),.ready(ready) );
initial
begin
$dumpfile("sd_spi_tb.vcd");
$dumpvars(0,sd_spi_tb);
end
initial
#10000 $finish();
endmodule // sd_spi_tb
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
fastclk
);
input fastclk;
t_netlist tnetlist
(.also_fastclk (fastclk),
/*AUTOINST*/
// Inputs
.fastclk (fastclk));
endmodule
module t_netlist (/*AUTOARG*/
// Inputs
fastclk, also_fastclk
);
// surefire lint_off ASWEMB
input fastclk;
input also_fastclk;
integer _mode; initial _mode = 0;
// This entire module should optimize to nearly nothing...
// verilator lint_off UNOPTFLAT
reg [4:0] a,a2,b,c,d,e;
// verilator lint_on UNOPTFLAT
initial a=5'd1;
always @ (posedge fastclk) begin
b <= a+5'd1;
c <= b+5'd1; // Better for ordering if this moves before previous statement
end
// verilator lint_off UNOPT
always @ (d or /*AS*/a or c) begin
e = d+5'd1;
a2 = a+5'd1; // This can be pulled out of the middle of the always
d = c+5'd1; // Better for ordering if this moves before previous statement
end
// verilator lint_on UNOPT
always @ (posedge also_fastclk) begin
if (_mode==5) begin
if (a2 != 5'd2) $stop;
if (e != 5'd5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
_mode <= _mode + 1;
end
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
module regfile(input wire clock,
input wire enable,
input wire [ 4:0] rdaddress_a,
input wire [ 4:0] rdaddress_b,
// Write port
input wire wren,
input wire [ 4:0] wraddress,
input wire [31:0] data,
// Read ports
output reg [31:0] qa, // One clock cycle delayed
output reg [31:0] qb // One clock cycle delayed
);
reg [31:0] regs [31:0];
always @(posedge clock)
if (enable) begin
if (wren)
regs[wraddress] <= data;
qa <= regs[rdaddress_a];
qb <= regs[rdaddress_b];
end
reg [7:0] i;
initial begin
i = 0;
repeat (32) begin
regs[i] = 0 /*{4{i}}*/;
i = i + 1;
end
end
endmodule
|
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: squarer.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module squarer (
dataa,
result);
input [39:0] dataa;
output [79:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "40"
// Retrieval info: PRIVATE: WidthB NUMERIC "40"
// Retrieval info: PRIVATE: WidthP NUMERIC "80"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "40"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "80"
// Retrieval info: USED_PORT: dataa 0 0 40 0 INPUT NODEFVAL "dataa[39..0]"
// Retrieval info: USED_PORT: result 0 0 80 0 OUTPUT NODEFVAL "result[79..0]"
// Retrieval info: CONNECT: @data 0 0 40 0 dataa 0 0 40 0
// Retrieval info: CONNECT: result 0 0 80 0 @result 0 0 80 0
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2005
// This File is based upon: crt_op_stage.v
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Curtis Wright for use in FPGA development specifically for add-in
// boards. Any other use of this source code must be discussed with Silicon
// Spectrum and this copyright notice must be maintained.
// Silicon Spectrum does not give up the copyright to the original file or
// encumber in any way it's use except where related to Curtis Wright add-in
// board business for the period set out in the original agreement.
//
// Title : Key Output signals from CRTC.
// File : crt_op_stage.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Generates some critical signals such as composite
// display enable, blank, line clock.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crt_op_stage
(
input h_reset_n,
input c_vde, // Vertical display enable
input cr11_b4, // clear vertical interrupt
input cr11_b5, // disable vertical interrupt
input a_arx_b5, // Video enable
input m_sr01_b5, // Full band width for host
input vblank, // Vertical blank
input hblank, // Horizontal blank
input cclk_en, // char. clock
input dclk_en, // dot clock
input hde, // Horizontal display enable
input c_ahde, // advance horizontal display enable.
input int_crt_line_end, // indicates the end of current scan line
input t_crt_clk,
input a_ar10_b0,
input vga_en, // Disable screen when vga is not enabled
output c_t_crt_int, // Interrupt to indicate vertical retrace
output c_attr_de, /* This signal indicates the actual display
* enable to the attribute control */
output c_t_cblank_n, // Composite Blank to RAMDAC
output ade, // composite advance display enable
output screen_off,
output dis_en_sta
);
reg ade_ff;
reg intrpt_ff;
reg gated_hde_ff;
reg syn_cblank_ff;
reg [2:0] int_attr_de_d;
reg [4:0] int_cblank_d_dc;
reg [2:0] hde_d_cc;
reg [1:0] vde_syn_cclk;
reg [1:0] sr01_b5_syn_cclk;
wire comp_blank;
reg [3:0] comp_blank_d_cc;
wire int_cblank;
wire int_intrpt;
wire arx_b5_syn_cclk;
wire clr_intrpt_n = cr11_b4;
wire int_attr_de;
reg [1:0] sync1;
wire [4:0] h_blank_d_dc;
// generating c_attr_de. Synchronize a_arx_b5 and c_vde
// w.r.t cclk. Delay hde by 2 cclk's in Graphics and 3 cclk's in Text mode.
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) begin
hde_d_cc <= 3'b0;
sync1 <= 2'b0;
vde_syn_cclk <= 2'b0;
sr01_b5_syn_cclk <= 2'b11;
comp_blank_d_cc <= 4'b0;
end else if (cclk_en) begin
hde_d_cc <= {hde_d_cc[1:0], hde};
sync1 <= {sync1[0], a_arx_b5};
vde_syn_cclk <= {vde_syn_cclk[0], c_vde};
sr01_b5_syn_cclk <= {sr01_b5_syn_cclk[0], (m_sr01_b5 | ~vga_en)};
comp_blank_d_cc <= {comp_blank_d_cc[2:0], comp_blank};
end
assign arx_b5_syn_cclk = sync1[1];
always @(posedge t_crt_clk or negedge h_reset_n)
if (~h_reset_n) gated_hde_ff <= 1'b0;
else if (dclk_en) gated_hde_ff <= ( arx_b5_syn_cclk & hde_d_cc[2] );
assign int_attr_de = gated_hde_ff & vde_syn_cclk[1];
assign dis_en_sta = ~(hde_d_cc[2] & vde_syn_cclk[1]);
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) int_attr_de_d <= 3'b0;
else if (dclk_en) int_attr_de_d <= {int_attr_de_d[1:0], int_attr_de};
assign c_attr_de = int_attr_de_d[2];
assign screen_off = sr01_b5_syn_cclk[1];
assign comp_blank = vblank | hblank;
assign int_cblank = sr01_b5_syn_cclk[1] | comp_blank_d_cc[3];
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) int_cblank_d_dc <= 5'b0;
else if (dclk_en) int_cblank_d_dc <= {int_cblank_d_dc[3:0], int_cblank};
always @(posedge t_crt_clk or negedge h_reset_n)
if(~h_reset_n) syn_cblank_ff <= 1'b0;
else syn_cblank_ff <= int_cblank_d_dc[4];
assign c_t_cblank_n = ~syn_cblank_ff;
assign int_intrpt = ( intrpt_ff | (~c_vde) ) & cr11_b4;
always @(posedge t_crt_clk or negedge h_reset_n)
if(~h_reset_n) intrpt_ff <= 1'b0;
else if (cclk_en) intrpt_ff <= int_intrpt;
assign c_t_crt_int = intrpt_ff;
// Generating advance composite display enable
always @(posedge t_crt_clk or negedge h_reset_n)
if (~h_reset_n) ade_ff <= 1'b0;
else if (int_crt_line_end & cclk_en) ade_ff <= c_vde;
assign ade = ade_ff & c_ahde;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__EBUFN_PP_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_PP_SYMBOL_V
|
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; using namespace std; const int N = 1000100; bool isp[N]; void prep() { for (int(i) = (2); (i) < (N); ++(i)) isp[i] = true; for (int i = 2; i * i < N; i++) if (isp[i]) for (int j = i * i; j < N; j += i) isp[j] = false; } int a, b, k; bool f(int len) { if (len > b - a + 1) return false; int np = 0; for (int i = 0; i < len; i++) np += isp[a + i]; if (np < k) return false; for (int i = a + len; i <= b; i++) { np -= isp[i - len]; np += isp[i]; if (np < k) return false; } return true; } int main() { ios::sync_with_stdio(false); prep(); cin >> a >> b >> k; int lo = 1, hi = b - a + 2; while (lo != hi) { int mi = (lo + hi) / 2; if (f(mi)) hi = mi; else lo = mi + 1; } if (lo == 0 || lo > b - a + 1) lo = -1; cout << lo << n ; return 0; } |
// ----------------------------------------------------------
// Credit producer block
//
// This module produces symbol and packet credits by snooping
// on the valid, ready and eop signals.
//
// A symbol credit is added whenever symbols_per_credit symbols
// have been detected, or whenever eop is detected.
//
// Packet credits are only incremented on a valid eop.
//
// @author jyeap
// ----------------------------------------------------------
module credit_producer (
clk,
reset_n,
in_valid,
in_ready,
in_endofpacket,
symbol_credits,
packet_credits
);
parameter SYMBOLS_PER_CREDIT = 1;
parameter SYMBOLS_PER_BEAT = 1;
parameter USE_SYMBOL_CREDITS = 1;
parameter USE_PACKET_CREDITS = 1;
parameter USE_PACKETS = 1;
input clk;
input reset_n;
input in_valid;
input in_ready;
input in_endofpacket;
output reg [15 : 0] symbol_credits;
output reg [15 : 0] packet_credits;
// ----------------------------------------------------------
// Internal Signals
// ----------------------------------------------------------
reg beat;
reg eop_beat;
reg [15 : 0] sym_count;
reg [15 : 0] next_sym_count;
reg rollover;
always @* begin
beat = in_valid && in_ready;
if (USE_PACKETS)
eop_beat = beat && in_endofpacket;
else
eop_beat = 0;
end
// ----------------------------------------------------------
// Symbol Credits
// ----------------------------------------------------------
generate
// ----------------------------------------------------------
// Simplest case first: symbols_per_beat is a multiple (n) of symbols_per_credit.
//
// Because the interface is wider than a credit, each beat of data always adds
// (n) to the symbol credits.
//
// This always works for non-packetized interfaces. For packetized interfaces
// symbols_per_credit must be >= symbols_per_beat, which implies that this
// only works for symbols_per_beat == symbols_per_credit.
// ----------------------------------------------------------
if (SYMBOLS_PER_BEAT % SYMBOLS_PER_CREDIT == 0) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
symbol_credits <= 0;
else if (beat)
symbol_credits <= symbol_credits + SYMBOLS_PER_BEAT/SYMBOLS_PER_CREDIT;
end
end
// ----------------------------------------------------------
// Next case: symbols_per_credit is a multiple of symbols_per_beat
//
// We need two counters. One counts the number of symbols received,
// and resets once it has reached symbols_per_credit or endofpacket.
// The other is the symbol credit counter which increments whenever
// the first counter resets.
// ----------------------------------------------------------
else if (SYMBOLS_PER_CREDIT % SYMBOLS_PER_BEAT == 0) begin
always @* begin
next_sym_count = sym_count;
if (beat)
next_sym_count = sym_count + SYMBOLS_PER_BEAT;
end
always @* begin
rollover = (next_sym_count == SYMBOLS_PER_CREDIT) || eop_beat;
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
sym_count <= 0;
else if (rollover)
sym_count <= 0;
else
sym_count <= next_sym_count;
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
symbol_credits <= 0;
else if (rollover)
symbol_credits <= symbol_credits + 1;
end
end
endgenerate
// ----------------------------------------------------------
// Packet Credits
//
// When you see EOP, up go the packet credits. Always.
// ----------------------------------------------------------
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
packet_credits <= 0;
else if (eop_beat)
packet_credits <= packet_credits + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double x, y, z, s; int n, a, b, c, v[300010], p[300010], l[300010], r[300010]; bool cmp(int x, int y) { return v[x] < v[y]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &v[i]), l[i] = i - 1, r[i] = i + 1, p[i] = i; sort(p + 1, p + n + 1, cmp); for (int i = 1; i <= n; i++) { x = y = 0, z = 1; a = b = c = p[i]; for (int j = 1; j <= 45; j++) { if (a) x += (a - l[a]) * z, a = l[a]; if (b <= n) y += (r[b] - b) * z, b = r[b]; z /= 2; } l[r[c]] = l[c], r[l[c]] = r[c]; s += x * y * v[c] / 2; } printf( %.6f n , s / n / n); return 0; } |
`timescale 1ns / 1ns
module RegisterFile(input writeEnb,clk ,input [2:0] readReg1,readReg2,writeReg , input[7:0] writeData , output wire[7:0] readData1,readData2);
reg[7:0] registers[0:7];
initial registers[0] = 8'b0;
initial registers[1] = 8'b0;
initial registers[2] = 8'b0;
initial registers[3] = 8'b0;
initial registers[4] = 8'b0;
initial registers[5] = 8'b0;
initial registers[6] = 8'b0;
initial registers[7] = 8'b0;
always@(posedge clk)
if(writeEnb && writeReg!=3'b000)
registers[writeReg] = writeData;
assign readData1 = registers[readReg1];
assign readData2 = registers[readReg2];
endmodule
/*module RegisterFileTB();
initial begin
$dumpfile("RegisterFileTB.vcd");
$dumpvars;
#30 $finish;
end
reg clk,wre;
reg[2:0] rr1,rr2,wr;
reg[7:0] wd;
wire[7:0] rd1,rd2;
parameter delta = 5;
initial begin clk = 0; forever #delta clk = ~clk; end
RegisterFile UUT(wre,clk,rr1,rr2,wr,wd,rd1,rd2);
initial begin
wre = 1'b1;
wr = 3'b000;
wd = {8{1'b1}};
#delta
wr = 3'b010;
rr1 = 3'b010;
rr2 = 3'b000;
#delta
wre = 1'b0;
wr = 3'b011;
rr1 = 3'b011;
#delta
wre = 1'b1;
end
endmodule*/ |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 22:19:13
// Design Name:
// Module Name: Register_with_synch_reset_set_load_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register_with_synch_reset_set_load_behavior_tb(
);
reg [3:0] D;
reg Clk, reset, set, load;
wire [3:0] Q;
Register_with_synch_reset_set_load_behavior DUT (.D(D), .Clk(Clk), .reset(reset), .set(set), .load(load), .Q(Q));
initial begin
#300 $finish;
end
initial begin
D = 4'b0000; Clk = 0; reset = 0; set = 0; load = 0;
#10 Clk = 1;
#10 Clk = 0; D = 4'b0101;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; D = 4'b1001; load = 0;
#10 Clk = 1;
#10 Clk = 0; // 100ns
#10 Clk = 1;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; load = 0;
#10 Clk = 1;
#5 reset = 1;
#5 Clk = 0;
#10 Clk = 1; set = 1;
#10 Clk = 0;
#10 Clk = 1; set = 0;
#5 load = 1;
#5 Clk = 0; // 200ns
#10 Clk = 1;
#5 load = 0;
#5 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; reset = 0;
#10 Clk = 1; set = 1;
#10 Clk = 0;
#10 Clk = 1; set = 0;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; load = 0;// 300ns
end
endmodule
|
#include <bits/stdc++.h> long long n, s[2][100010], k; long long dp[100010][2]; long long ans = 1; long long p(long long a, long long b) { if (b == 0) return 1LL; if (b == 1) return a % 998244353; long long x = p(a, b >> 1); x *= x; x %= 998244353; x *= p(a, b & 1); x %= 998244353; return x; } void solve(long long *a, long long len) { long long l, r; l = 0; while (!(~a[l]) && a[l]) l++; if (l == len + 1) { ans = ans * k % 998244353 * p(k - 1, len) % 998244353; return; } ans *= p(k - 1, l); ans %= 998244353; r = len; while (r >= 0 && !(~a[r])) r--; if (r < len) ans *= p(k - 1, len - r), ans %= 998244353; r++; for (int i = l, count = 0; i <= r; i++) { if (a[i] == -1) { count++; continue; } else if (count) { if (a[i] == a[i - count - 1]) ans *= dp[count][1]; else ans *= dp[count][0]; ans %= 998244353; count = 0; } else if (i && a[i] == a[i - 1]) { ans = 0; return; } } return; } int main() { scanf( %lld%lld , &n, &k); for (int i = 0; i < n; i++) scanf( %lld , &s[i & 1][i >> 1]); dp[1][0] = k - 2; dp[1][1] = k - 1; for (int i = 2; i <= n >> 1; i++) { dp[i][0] = dp[i - 1][1] + dp[i - 1][0] * (k - 2) % 998244353; dp[i][1] = dp[i - 1][0] * (k - 1) % 998244353; dp[i][0] %= 998244353; dp[i][1] %= 998244353; } solve(s[0], n - 1 >> 1); if (!ans) { puts( 0 ); return 0; } solve(s[1], (n - 1 >> 1) - (n & 1)); printf( %lld n , ans); return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_seq(
input sys_clk,
input sys_rst,
output reg alu_rst,
input dma_en,
input dma_busy,
input dma_ack,
output reg vfirst,
output reg vnext,
input vlast,
output reg pcount_rst,
output reg c_en,
input start,
output reg busy
);
reg [1:0] state;
reg [1:0] next_state;
parameter IDLE = 2'd0;
parameter INIT = 2'd1;
parameter RUNNING = 2'd2;
parameter LASTDMA = 2'd3;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
// synthesis translate_off
always @(posedge sys_clk) begin
if(state == RUNNING) begin
if(~dma_ack) begin
$display("ERROR - Write queue acknowledge went DOWN during computation");
$finish;
end
end
end
// synthesis translate_on
always @(*) begin
next_state = state;
busy = 1'b0;
alu_rst = 1'b0;
vfirst = 1'b0;
vnext = 1'b0;
pcount_rst = 1'b0;
c_en = 1'b0;
case(state)
IDLE: begin
alu_rst = 1'b1;
pcount_rst = 1'b1;
vfirst = 1'b1;
c_en = 1'b1;
if(start)
next_state = INIT;
end
INIT: begin /* fetch isn 0 */
busy = 1'b1;
alu_rst = 1'b1;
pcount_rst = 1'b1;
if(dma_ack) begin
/* we will be able to send immediately our word
* to the DMA engine - carry on.
*/
pcount_rst = 1'b0;
next_state = RUNNING;
end
end
RUNNING: begin
busy = 1'b1;
if(dma_en) begin
pcount_rst = 1'b1;
alu_rst = 1'b1;
vnext = 1'b1;
if(vlast)
next_state = LASTDMA;
else
next_state = INIT;
end
end
LASTDMA: begin
busy = 1'b1;
alu_rst = 1'b1;
if(~dma_busy)
next_state = IDLE;
end
endcase
end
endmodule
|
/*
###########################################################################
# Function: A mailbox FIFO with a FIFO empty/full flags that can be used as
# interrupts.
#
# E_MAILBOXLO = lower 32 bits of FIFO entry
# E_MAILBOXHI = upper 32 bits of FIFO entry
#
# Notes: 1.) System should take care of not overflowing the FIFO
# 2.) Reading the E_MAILBOXHI causes a fifo rd pointer update
# 3.) The "embox_not_empty" is a "level" interrupt signal.
#
# How to use: 1.) Connect "embox_not_empty" to interrupt input line
# 2.) Write an ISR to respond to interrupt line::
# -reads E_MAILBOXLO, then
# -reads E_MAILBOXHI, then
# -finishes ISR
#
###########################################################################
*/
`include "../../elink/hdl/elink_regmap.v" // is there a better way?
module emailbox (/*AUTOARG*/
// Outputs
mi_dout, mailbox_full, mailbox_not_empty,
// Inputs
reset, wr_clk, rd_clk, emesh_access, emesh_packet, mi_en, mi_we,
mi_addr, mi_din
);
parameter DW = 32; //data width of fifo
parameter AW = 32; //data width of fifo
parameter PW = 104; //packet size
parameter RFAW = 6; //address bus width
parameter ID = 12'h000; //link id
parameter WIDTH = 104;
parameter DEPTH = 16;
/*****************************/
/*RESET */
/*****************************/
input reset; //asynchronous reset
input wr_clk; //write clock
input rd_clk; //read clock
/*****************************/
/*WRITE INTERFACE */
/*****************************/
input emesh_access;
input [PW-1:0] emesh_packet;
/*****************************/
/*READ INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr;
input [63:0] mi_din; //assumes write interface is 64 bits
output [63:0] mi_dout;
/*****************************/
/*MAILBOX OUTPUTS */
/*****************************/
output mailbox_full;
output mailbox_not_empty;
/*****************************/
/*REGISTERS */
/*****************************/
reg [63:0] mi_dout;
/*****************************/
/*WIRES */
/*****************************/
wire mailbox_read;
wire mi_rd;
wire [WIDTH-1:0] mailbox_fifo_data;
wire mailbox_empty;
wire mailbox_pop;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh__write;
/*****************************/
/*WRITE TO FIFO */
/*****************************/
assign emesh_addr[31:0] = emesh_packet[39:8];
assign emesh_din[63:0] = emesh_packet[103:40];
assign emesh_write = emesh_access &
emesh_packet[1] &
(emesh_addr[31:20]==ID) &
(emesh_addr[10:8]==3'h3) &
(emesh_addr[RFAW+1:2]==`E_MAILBOXLO);
/*****************************/
/*READ BACK DATA */
/*****************************/
assign mi_rd = mi_en & ~mi_we;
assign mailbox_pop = mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXHI); //fifo read
always @ (posedge rd_clk)
if(mi_rd)
case(mi_addr[RFAW+1:2])
`E_MAILBOXLO: mi_dout[63:0] <= mailbox_fifo_data[63:0];
`E_MAILBOXHI: mi_dout[63:0] <= {mailbox_fifo_data[2*DW-1:DW],
mailbox_fifo_data[2*DW-1:DW]};
default: mi_dout[63:0] <= 64'd0;
endcase // case (mi_addr[RFAW-1:2])
else
mi_dout[63:0] <= 64'd0;
/*****************************/
/*FIFO (64bit wide) */
/*****************************/
assign mailbox_not_empty = ~mailbox_empty;
//BUG! This fifo is currently hard coded to 16 entries
//Should be parametrized to up to 4096 entries
defparam fifo.DW = WIDTH;
defparam fifo.DEPTH = DEPTH;
fifo_async fifo(// Outputs
.dout (mailbox_fifo_data[WIDTH-1:0]),
.empty (mailbox_empty),
.full (mailbox_full),
.prog_full (),
.valid(),
//Read Port
.rd_en (mailbox_pop),
.rd_clk (rd_clk),
//Write Port
.din ({40'b0,emesh_din[63:0]}),
.wr_en (emesh_write),
.wr_clk (wr_clk),
.wr_rst (reset),
.rd_rst (reset)
);
endmodule // emailbox
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_SYMBOL_V
`define SKY130_FD_SC_HS__NAND3B_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_SYMBOL_V
|
`include "constants.vh"
`default_nettype none
module exunit_mul
(
input wire clk,
input wire reset,
input wire [`DATA_LEN-1:0] ex_src1,
input wire [`DATA_LEN-1:0] ex_src2,
input wire dstval,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,
input wire src1_signed,
input wire src2_signed,
input wire sel_lohi,
input wire issue,
input wire prmiss,
input wire [`SPECTAG_LEN-1:0] spectagfix,
output wire [`DATA_LEN-1:0] result,
output wire rrf_we,
output wire rob_we, //set finish
output wire kill_speculative
);
reg busy;
assign rob_we = busy;
assign rrf_we = busy & dstval;
assign kill_speculative = ((spectag & spectagfix) != 0) && specbit && prmiss;
always @ (posedge clk) begin
if (reset) begin
busy <= 0;
end else begin
busy <= issue;
end
end
multiplier bob
(
.src1(ex_src1),
.src2(ex_src2),
.src1_signed(src1_signed),
.src2_signed(src2_signed),
.sel_lohi(sel_lohi),
.result(result)
);
endmodule // exunit_mul
`default_nettype wire
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_timer_cpu_s0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h3D08F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 53391;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 3;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register[0];
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : PIO.v
//
// Description: Programmed I/O module. Design implements 8 KBytes of programmable
//-- memory space. Host processor can access this memory space using
//-- Memory Read 32 and Memory Write 32 TLPs. Design accepts
//-- 1 Double Word (DW) payload length on Memory Write 32 TLP and
//-- responds to 1 DW length Memory Read 32 TLPs with a Completion
//-- with Data TLP (1DW payload).
//--
//-- Module is designed to operate with 32 bit and 64 bit interfaces.
//
//------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO (
trn_clk,
trn_reset_n,
trn_lnk_up_n,
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_tdst_rdy_n,
trn_tdst_dsc_n,
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rbar_hit_n,
trn_rdst_rdy_n,
cfg_to_turnoff_n,
cfg_turnoff_ok_n,
cfg_completer_id,
cfg_bus_mstr_enable
); // synthesis syn_hier = "hard"
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input trn_clk;
input trn_reset_n;
input trn_lnk_up_n;
output [63:0] trn_td;
output [7:0] trn_trem_n;
output trn_tsof_n;
output trn_teof_n;
output trn_tsrc_rdy_n;
output trn_tsrc_dsc_n;
input trn_tdst_rdy_n;
input trn_tdst_dsc_n;
input [63:0] trn_rd;
input [7:0] trn_rrem_n;
input trn_rsof_n;
input trn_reof_n;
input trn_rsrc_rdy_n;
input trn_rsrc_dsc_n;
input [6:0] trn_rbar_hit_n;
output trn_rdst_rdy_n;
input cfg_to_turnoff_n;
output cfg_turnoff_ok_n;
input [15:0] cfg_completer_id;
input cfg_bus_mstr_enable;
// Local wires
wire req_compl;
wire compl_done;
wire pio_reset_n = ~trn_lnk_up_n;
//
// PIO instance
//
PIO_EP PIO_EP (
.clk ( trn_clk ), // I
.rst_n ( pio_reset_n ), // I
.trn_td ( trn_td ), // O [63/31:0]
.trn_trem_n ( trn_trem_n ), // O [7:0]
.trn_tsof_n ( trn_tsof_n ), // O
.trn_teof_n ( trn_teof_n ), // O
.trn_tsrc_rdy_n ( trn_tsrc_rdy_n ), // O
.trn_tsrc_dsc_n ( trn_tsrc_dsc_n ), // O
.trn_tdst_rdy_n ( trn_tdst_rdy_n ), // I
.trn_tdst_dsc_n ( trn_tdst_dsc_n ), // I
.trn_rd ( trn_rd ), // I [63/31:0]
.trn_rrem_n ( trn_rrem_n ), // I
.trn_rsof_n ( trn_rsof_n ), // I
.trn_reof_n ( trn_reof_n ), // I
.trn_rsrc_rdy_n ( trn_rsrc_rdy_n ), // I
.trn_rsrc_dsc_n ( trn_rsrc_dsc_n ), // I
.trn_rbar_hit_n ( trn_rbar_hit_n ), // I [6:0]
.trn_rdst_rdy_n ( trn_rdst_rdy_n ), // O
.req_compl_o(req_compl), // O
.compl_done_o(compl_done), // O
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable ( cfg_bus_mstr_enable ) // I
);
//
// Turn-Off controller
//
PIO_TO_CTRL PIO_TO (
.clk( trn_clk ), // I
.rst_n( pio_reset_n ), // I
.req_compl_i( req_compl ), // I
.compl_done_i( compl_done ), // I
.cfg_to_turnoff_n( cfg_to_turnoff_n ), // I
.cfg_turnoff_ok_n( cfg_turnoff_ok_n ) // O
);
endmodule // PIO
|
#include <bits/stdc++.h> using namespace std; void data() {} const int N = 1e6 + 100; const long long mod = 998244353; const long long mod2 = 1e9 + 7; map<int, int> was, was2; int main() { data(); int t; cin >> t; while (t--) { int n; cin >> n; int a[n + 1]; for (int i = 1; i <= n; i++) { cin >> a[i]; } int len = 0; for (int i = 1; i <= n - 1 && a[i] == 1; i++) { len++; } if (len % 2 == 0) { cout << First n ; } else { cout << Second n ; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DLATCH_P_BLACKBOX_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_PP_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire sleepb ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
wire and0_out_X ;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, sleepb, DESTPWR, VGND );
and and0 (and0_out_X , pwrgood_pp1_out_sleepb, pwrgood_pp0_out_A);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp2 (X , and0_out_X, DESTPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int M = (int)1e9 + 7; int a[17]; int c[107][107]; int dp[17][107]; int n; int main() { cin >> n; for (int i = 0; i < 10; i++) cin >> a[i]; for (int i = 0; i <= 100; i++) { c[i][0] = c[i][i] = 1; for (int j = 1; j < i; j++) { c[i][j] = (c[i - 1][j - 1] + c[i - 1][j]) % M; } } int ans = 0; dp[10][0] = 1; for (int dig = 9; dig >= 0; dig--) { for (int cnt = a[dig]; cnt <= n; cnt++) { for (int rem = 0; rem + cnt <= n; rem++) { dp[dig][cnt + rem] = (dp[dig][cnt + rem] + (dp[dig + 1][rem] * 1ll * c[cnt + rem - (dig ? 0 : 1)][cnt] % M)) % M; } } } for (int len = 1; len <= n; len++) ans = (ans + dp[0][len]) % M; cout << ans << n ; return 0; } |
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("50.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("100.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: driver_7segment.v
//
// *Module Description:
// Driver for the four-digit, seven-segment LED display.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module driver_7segment (
// OUTPUTs
per_dout, // Peripheral data output
seg_a, // Segment A control
seg_b, // Segment B control
seg_c, // Segment C control
seg_d, // Segment D control
seg_e, // Segment E control
seg_f, // Segment F control
seg_g, // Segment G control
seg_dp, // Segment DP control
seg_an0, // Anode 0 control
seg_an1, // Anode 1 control
seg_an2, // Anode 2 control
seg_an3, // Anode 3 control
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
output seg_a; // Segment A control
output seg_b; // Segment B control
output seg_c; // Segment C control
output seg_d; // Segment D control
output seg_e; // Segment E control
output seg_f; // Segment F control
output seg_g; // Segment G control
output seg_dp; // Segment DP control
output seg_an0; // Anode 0 control
output seg_an1; // Anode 1 control
output seg_an2; // Anode 2 control
output seg_an3; // Anode 3 control
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0090;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] DIGIT0 = 'h0,
DIGIT1 = 'h1,
DIGIT2 = 'h2,
DIGIT3 = 'h3;
// Register one-hot decoder utilities
parameter DEC_SZ = 2**DEC_WD;
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] DIGIT0_D = (BASE_REG << DIGIT0),
DIGIT1_D = (BASE_REG << DIGIT1),
DIGIT2_D = (BASE_REG << DIGIT2),
DIGIT3_D = (BASE_REG << DIGIT3);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (DIGIT0_D & {DEC_SZ{(reg_addr==(DIGIT0 >>1))}}) |
(DIGIT1_D & {DEC_SZ{(reg_addr==(DIGIT1 >>1))}}) |
(DIGIT2_D & {DEC_SZ{(reg_addr==(DIGIT2 >>1))}}) |
(DIGIT3_D & {DEC_SZ{(reg_addr==(DIGIT3 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// DIGIT0 Register
//-----------------
reg [7:0] digit0;
wire digit0_wr = DIGIT0[0] ? reg_hi_wr[DIGIT0] : reg_lo_wr[DIGIT0];
wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit0 <= 8'h00;
else if (digit0_wr) digit0 <= digit0_nxt;
// DIGIT1 Register
//-----------------
reg [7:0] digit1;
wire digit1_wr = DIGIT1[0] ? reg_hi_wr[DIGIT1] : reg_lo_wr[DIGIT1];
wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit1 <= 8'h00;
else if (digit1_wr) digit1 <= digit1_nxt;
// DIGIT2 Register
//-----------------
reg [7:0] digit2;
wire digit2_wr = DIGIT2[0] ? reg_hi_wr[DIGIT2] : reg_lo_wr[DIGIT2];
wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit2 <= 8'h00;
else if (digit2_wr) digit2 <= digit2_nxt;
// DIGIT3 Register
//-----------------
reg [7:0] digit3;
wire digit3_wr = DIGIT3[0] ? reg_hi_wr[DIGIT3] : reg_lo_wr[DIGIT3];
wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit3 <= 8'h00;
else if (digit3_wr) digit3 <= digit3_nxt;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] digit0_rd = (digit0 & {8{reg_rd[DIGIT0]}}) << (8 & {4{DIGIT0[0]}});
wire [15:0] digit1_rd = (digit1 & {8{reg_rd[DIGIT1]}}) << (8 & {4{DIGIT1[0]}});
wire [15:0] digit2_rd = (digit2 & {8{reg_rd[DIGIT2]}}) << (8 & {4{DIGIT2[0]}});
wire [15:0] digit3_rd = (digit3 & {8{reg_rd[DIGIT3]}}) << (8 & {4{DIGIT3[0]}});
wire [15:0] per_dout = digit0_rd |
digit1_rd |
digit2_rd |
digit3_rd;
//============================================================================
// 5) FOUR-DIGIT, SEVEN-SEGMENT LED DISPLAY DRIVER
//============================================================================
// Anode selection
//------------------
// Free running counter
reg [23:0] anode_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) anode_cnt <= 24'h00_0000;
else anode_cnt <= anode_cnt+24'h00_0001;
// Anode selection
wire [3:0] seg_an = (4'h1 << anode_cnt[17:16]);
wire seg_an0 = ~seg_an[0];
wire seg_an1 = ~seg_an[1];
wire seg_an2 = ~seg_an[2];
wire seg_an3 = ~seg_an[3];
// Segment selection
//----------------------------
wire [7:0] digit = seg_an[0] ? digit0 :
seg_an[1] ? digit1 :
seg_an[2] ? digit2 :
digit3;
wire seg_a = ~digit[7];
wire seg_b = ~digit[6];
wire seg_c = ~digit[5];
wire seg_d = ~digit[4];
wire seg_e = ~digit[3];
wire seg_f = ~digit[2];
wire seg_g = ~digit[1];
wire seg_dp = ~digit[0];
endmodule // driver_7segment
|
#include <bits/stdc++.h> using namespace std; int n = 0; vector<int> v; int flag[2010]; int countt = 0; int k = 0; int maxt = 0; int main() { cin >> n; cin >> k; for (int i = 0; i < n; i++) { int kari = 0; cin >> kari; v.push_back(kari); if (i == 0) { maxt = kari; } else { maxt = max(maxt, kari); } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { vector<int> u; vector<int> d; u.clear(); d.clear(); int sum = 0; for (int jj = 0; jj < n; jj++) { if (jj < i || j < jj) { d.push_back(v[jj]); } else { sum += v[jj]; u.push_back(v[jj]); } } sort(u.begin(), u.end()); sort(d.begin(), d.end()); maxt = max(maxt, sum); { int ii = 0; int jj = d.size() - 1; for (; ii < u.size() && jj >= 0 && ii < k; ii++, jj--) { sum -= u[ii]; sum += d[jj]; maxt = max(maxt, sum); } } } } cout << maxt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char N[(int)1e6 + 5], B[(int)1e6 + 5]; long long n, b, c; inline long long euler(long long n) { long long ans = n; for (int i = 2; i * i <= n; i++) { if (n % i == 0) { ans = ans / i * (i - 1); while (n % i == 0) n /= i; } } if (n > 1) ans = ans / n * (n - 1); return ans; } long long qpow(long long x, long long n, long long mod) { if (n == 0) return 1; long long ans = qpow(x, n >> 1, mod); ans = ans * ans % mod; if (n & 1) ans = ans * x % mod; return ans % mod; } int main() { cin >> B; cin >> N; int xx = strlen(N); int yy = strlen(B); cin >> c; n = 0; long long u = euler(c); if (xx < 10) { for (int i = 0; i < xx; i++) n = n * 10 + N[i] - 0 ; n--; } else { for (int i = 0; i < xx; i++) { n = n * 10 + N[i] - 0 ; n = n % u; } n = ((n - 1) + u) % u; n += u; } for (int i = 0; i < yy; i++) { b = b * 10 + B[i] - 0 ; b = b % c; } long long ans = (b - 1 + c) % c; ans = ans * qpow(b, n, c) % c; if (!ans) cout << c << endl; else cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int A[100005], P[100005]; int other_end[100005]; long long ans[100005], seg[100005]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) scanf( %d , &A[i]); for (int i = 1; i <= n; ++i) scanf( %d , &P[i]); long long res = 0; for (int i = n; i >= 1; --i) { ans[i] = res; int pos = P[i]; long long sum = A[pos]; int l = pos, r = pos; if (other_end[pos - 1] != 0) { l = other_end[pos - 1]; sum += seg[l]; } if (other_end[pos + 1] != 0) { sum += seg[pos + 1]; r = other_end[pos + 1]; } other_end[l] = r; other_end[r] = l; seg[l] = sum; if (sum > res) res = sum; } for (int i = 1; i <= n; ++i) cout << ans[i] << endl; return 0; } |
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