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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_2_V
`define SKY130_FD_SC_HD__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_2_V
|
//altera message_off 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_tracking
# (
// module parameter port list
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
// port list
ctl_clk,
ctl_reset_n,
// data burst interface
burst_ready,
burst_valid,
// burstcount counter sent to data_id_manager
burst_pending_burstcount,
burst_next_pending_burstcount,
// burstcount consumed by data_id_manager
burst_consumed_valid,
burst_counsumed_burstcount
);
// -----------------------------
// local parameter declarations
// -----------------------------
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// data burst interface
input burst_ready;
input burst_valid;
// burstcount counter sent to data_id_manager
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
// burstcount consumed by data_id_manager
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// data burst interface
wire burst_ready;
wire burst_valid;
// burstcount counter sent to data_id_manager
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
//wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_count_accepted;
// burstcount consumed by data_id_manager
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// signal declaration
// -----------------------------
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
// -----------------------------
// module definition
// -----------------------------
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e7 + 1; char used[MAXN] = {0}; int lowest_divisor[MAXN]; int numbers[2][MAXN], numbers2[2][MAXN]; void sieve() { for (int i = 2; i < MAXN; i += 2) { used[i] = 1; lowest_divisor[i] = 2; } for (long long i = 3; i < MAXN; i += 2) { if (!used[i]) { used[i] = 1; lowest_divisor[i] = i; for (long long j = i; (j * i) < MAXN; j += 2) { if (!used[i * j]) { used[i * j] = 1; lowest_divisor[i * j] = i; } } } } } void factor(int n, bool fl) { while (n > 1) { numbers[fl][lowest_divisor[n]]++; n /= lowest_divisor[n]; } } int main() { sieve(); int n, m; scanf( %d%d , &n, &m); vector<int> a, b; a.resize(n); b.resize(m); for (int i = 0; i < n; i++) { int t; scanf( %d , &t); factor(t, 0); a[i] = t; } for (int i = 0; i < m; i++) { int t; scanf( %d , &t); factor(t, 1); b[i] = t; } for (int i = 2; i < MAXN; i++) { numbers2[0][i] = numbers[0][i] - min(numbers[0][i], numbers[1][i]); numbers2[1][i] = numbers[1][i] - min(numbers[0][i], numbers[1][i]); } cout << n << << m << endl; for (int i = 0; i < n; i++) { int t = a[i]; while (t > 1) { if (numbers[0][lowest_divisor[t]] > numbers2[0][lowest_divisor[t]]) { numbers[0][lowest_divisor[t]]--; a[i] /= lowest_divisor[t]; } t /= lowest_divisor[t]; } } for (int i = 0; i < m; i++) { int t = b[i]; while (t > 1) { if (numbers[1][lowest_divisor[t]] > numbers2[1][lowest_divisor[t]]) { numbers[1][lowest_divisor[t]]--; b[i] /= lowest_divisor[t]; } t /= lowest_divisor[t]; } } for (auto it : a) { printf( %d , it); } cout << endl; for (auto it : b) { printf( %d , it); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__bufbuf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; vector<vector<pair<int, long long> > > g; int n, a[100005]; bool erased[100005]; void dfs(int cur, long long cost, long long minCost) { if (cost - minCost > 1ll * a[cur]) { erased[cur] = 1; return; } for (int i = 0; i < g[cur].size(); i++) { dfs(g[cur][i].first, cost + g[cur][i].second, min(minCost, cost)); } } int count(int u) { if (erased[u]) return 0; int ans = 1; for (int i = 0; i < g[u].size(); i++) ans += count(g[u][i].first); return ans; } int main() { scanf( %d , &n); g.assign(n, vector<pair<int, long long> >()); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) { int v, c; scanf( %d %d , &v, &c); v--; g[v].push_back(pair<int, long long>(i, c)); } memset(erased, 0, sizeof erased); dfs(0, 0ll, 0ll); printf( %d n , n - count(0)); } |
// Computer_System_VGA_Subsystem_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_VGA_Subsystem_avalon_st_adapter #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 1,
parameter inDataWidth = 30,
parameter inChannelWidth = 2,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 30,
parameter outChannelWidth = 0,
parameter outErrorWidth = 0,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [29:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
input wire in_0_startofpacket, // .startofpacket
input wire in_0_endofpacket, // .endofpacket
input wire [1:0] in_0_channel, // .channel
output wire [29:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire out_0_startofpacket, // .startofpacket
output wire out_0_endofpacket // .endofpacket
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 30)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 30)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
Computer_System_VGA_Subsystem_avalon_st_adapter_channel_adapter_0 channel_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.in_startofpacket (in_0_startofpacket), // .startofpacket
.in_endofpacket (in_0_endofpacket), // .endofpacket
.in_channel (in_0_channel), // .channel
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_startofpacket (out_0_startofpacket), // .startofpacket
.out_endofpacket (out_0_endofpacket) // .endofpacket
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The CLINT module
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_clint(
input clint_icb_cmd_valid,
output clint_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
input clint_icb_cmd_read,
input [`E203_XLEN-1:0] clint_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
//
output clint_icb_rsp_valid,
input clint_icb_rsp_ready,
output clint_icb_rsp_err,
output [`E203_XLEN-1:0] clint_icb_rsp_rdata,
output clint_tmr_irq,
output clint_sft_irq,
input aon_rtcToggle_a,
input tm_stop,
input clk,
input rst_n
);
wire aon_rtcToggle_r;
wire aon_rtcToggle;
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_aon_rtctoggle_sync(
.din_a (aon_rtcToggle_a),
.dout (aon_rtcToggle_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_clint_top u_sirv_clint_top(
.clk (clk ),
.rst_n (rst_n ),
.i_icb_cmd_valid (clint_icb_cmd_valid),
.i_icb_cmd_ready (clint_icb_cmd_ready),
.i_icb_cmd_addr (clint_icb_cmd_addr ),
.i_icb_cmd_read (clint_icb_cmd_read ),
.i_icb_cmd_wdata (clint_icb_cmd_wdata),
.i_icb_rsp_valid (clint_icb_rsp_valid),
.i_icb_rsp_ready (clint_icb_rsp_ready),
.i_icb_rsp_rdata (clint_icb_rsp_rdata),
.io_tiles_0_mtip (clint_tmr_irq),
.io_tiles_0_msip (clint_sft_irq),
.io_rtcToggle (aon_rtcToggle)
);
// We self-defined a mcounterstop CSR which contained a tm_stop field, this
// field can be use to disable different counters to save dynamic powers
// in the case where they dont really need the counters
assign aon_rtcToggle = aon_rtcToggle_r & (~tm_stop);
assign clint_icb_rsp_err = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_SYMBOL_V
`define SKY130_FD_SC_MS__OR2_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_SYMBOL_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:51:28 11/07/2015
// Design Name: TopModuleTransfLineal
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/Transflineal/Rot_tst.v
// Project Name: Transflineal
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: TopModuleTransfLineal
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Rot_tst;
// Inputs
reg clk;
reg rst;
reg enable;
reg [15:0] AcX;
reg [15:0] AcY;
reg [15:0] AcZ;
reg [15:0] sdseno;
reg [15:0] sdcoseno;
// Outputs
wire [31:0] XAc;
wire [31:0] YAc;
wire [31:0] ZAc;
wire Busy;
// Instantiate the Unit Under Test (UUT)
TopModuleTransfLineal uut (
.clk(clk),
.rst(rst),
.enable(enable),
.AcX(AcX),
.AcY(AcY),
.AcZ(AcZ),
.sdseno(sdseno),
.sdcoseno(sdcoseno),
.XAc(XAc),
.YAc(YAc),
.ZAc(ZAc),
.Busy(Busy)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
enable = 0;
AcX = 1000;
AcY = 1000;
AcZ = 0;
sdseno = 144;
sdcoseno = 8191;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#10 enable = 1;
// Add stimulus here
end
always #5 clk = !clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j, s1 = 1, s2 = 1, d = 0; cin >> n >> m; if (n == 1 && m == 1) { cout << 0 << endl; cout << 1 << << 1 << endl; cout << 1 << << 1 << endl; exit(0); } if (n == 1 && m == 2) { cout << 0 << endl; cout << 1 << << 1 << endl; cout << 1 << << 2 << endl; cout << 1 << << 1 << endl; exit(0); } if (n == 2 && m == 1) { cout << 0 << endl; cout << 1 << << 1 << endl; cout << 2 << << 1 << endl; cout << 1 << << 1 << endl; exit(0); } if (n == 1) { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; for (i = 1; i <= m; i++) { cout << 1 << << i << endl; } cout << 1 << << 1; exit(0); } if (m == 1) { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; for (i = 1; i <= n; i++) { cout << i << << 1 << endl; } cout << 1 << << 1; exit(0); } if (n % 2 != 0 && m % 2 != 0) { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; for (i = 1; i <= n; i++) { if (d == 0) { for (j = 1; j <= m; j++) { cout << i << << j << endl; } d = 1; } else { for (j = m; j >= 1; j--) { cout << i << << j << endl; } d = 0; } } cout << 1 << << 1; } else { cout << 0 << endl; cout << 1 << << 1 << endl; if (n % 2 == 0) { s2++; for (i = 1; i <= n; i++) { if (d == 0) { for (j = 2; j <= m; j++) { cout << i << << j << endl; } d = 1; } else { for (j = m; j >= 2; j--) { cout << i << << j << endl; } d = 0; } } for (i = n; i >= 1; i--) { cout << i << << 1 << endl; } } else { s2++; for (i = 1; i <= m; i++) { if (d == 0) { for (j = 2; j <= n; j++) { cout << j << << i << endl; } d = 1; } else { for (j = n; j >= 2; j--) { cout << j << << i << endl; } d = 0; } } for (i = m; i >= 1; i--) { cout << 1 << << i << endl; } } } return 0; } |
#include <bits/stdc++.h> int MakeTB(unsigned int *A, unsigned int *B, unsigned int *T, unsigned int N, unsigned int StartBit) { for (unsigned int i = 0; i < N - 1; i++) if (A[i] == 0) if (B[i] == 0) { if (i > 0 && T[i] != 0) return 0; T[i] = 0; T[i + 1] = 0; } else return 0; else if (B[i] == 0) { if (i == 0) T[i] = StartBit; T[i + 1] = !T[i]; } else { if (i > 0 && T[i] != 1) return 0; T[i] = 1; T[i + 1] = 1; } return 1; } int MakeTWB(unsigned int *A, unsigned int *B, unsigned int *T, unsigned int N) { unsigned int *a, *b, *t1, *t2; a = new unsigned int[N - 1]; b = new unsigned int[N - 1]; t1 = new unsigned int[N]; t2 = new unsigned int[N]; for (unsigned int i = 0; i < N - 1; i++) { a[i] = A[i] & 1; b[i] = B[i] & 1; } if (!(MakeTB(a, b, t1, N, 0) || MakeTB(a, b, t1, N, 1))) return 0; for (unsigned int i = 0; i < N - 1; i++) { a[i] = A[i] >> 1; b[i] = B[i] >> 1; } if (!(MakeTB(a, b, t2, N, 0) || MakeTB(a, b, t2, N, 1))) return 0; for (unsigned int i = 0; i < N; i++) T[i] = t1[i] | (t2[i] << 1); return 1; } int main(void) { unsigned int N; unsigned int *a, *b, *t; scanf( %d , &N); a = new unsigned int[N - 1]; b = new unsigned int[N - 1]; t = new unsigned int[N]; for (unsigned int i = 0; i < N - 1; i++) scanf( %d , &a[i]); for (unsigned int i = 0; i < N - 1; i++) scanf( %d , &b[i]); if (MakeTWB(a, b, t, N)) { printf( YES n ); for (unsigned int i = 0; i < N; i++) printf( %i , t[i]); } else printf( NO ); return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_channel_fifo
#(
// FIFO_DEPTH must be >=0
parameter integer FIFO_DEPTH = 16,
parameter integer DATA_W = 64, // > 0
parameter integer ADJUST_FOR_LATENCY = 0,
parameter integer ACL_PROFILE=0, // Set to 1 to enable profiling
parameter integer FIFOSIZE_WIDTH=32,
parameter integer ALMOST_FULL_VALUE=0
)
(
input logic clock,
input logic resetn,
input logic avst_in_valid,
input logic [DATA_W-1:0] avst_in_data,
output logic avst_in_ready,
output logic [FIFOSIZE_WIDTH-1:0] profile_fifosize,
input logic avst_out_ready,
output logic [DATA_W-1:0] avst_out_data,
output logic avst_out_valid,
output logic almost_full
);
wire r_o_stall;
wire r_o_valid;
wire avst_out_stall_wire;
wire [DATA_W-1:0] avst_out_data_wire;
wire avst_out_valid_wire;
acl_staging_reg
#(
.WIDTH(DATA_W)
)
asr( .clk( clock ), .reset( ~resetn ),
.i_data( avst_out_data_wire ),
.i_valid( avst_out_valid_wire ),
.o_stall( avst_out_stall_wire ),
.i_stall( ~avst_out_ready ),
.o_data( avst_out_data ),
.o_valid( avst_out_valid )
);
generate
if (FIFO_DEPTH == 0)
begin
assign avst_out_data_wire = avst_in_data;
assign avst_out_valid_wire = avst_in_valid;
assign avst_in_ready = ~avst_out_stall_wire;
assign almost_full = ~avst_in_ready;
end
else
begin
logic write;
logic read;
logic stall_out;
logic valid_out;
logic fifo_full;
logic fifo_empty;
assign write = avst_in_valid;
assign read = ~avst_out_stall_wire;
assign avst_in_ready = ~r_o_stall;
// this code is dependent on the acl_data_fifo implementations,
// and the latency of each data_fifo type.
// Changing the fifo type improves performance, since it
// balances the data fifo depth against the latency of the fifo.
logic [DATA_W-1:0] dout;
logic stall_in;
// The adjusted depth is equal to the latency of the channel fifo and
// the adjustment fifo. The adjustment is ll_reg (latency 1) and the
// channel fifo is either ll_reg or sandwich (latency 5), hence the
// values of 2 or 6 when it is used.
localparam ADJUSTED_DEPTH = (ADJUST_FOR_LATENCY == 0) ? 0 : (FIFO_DEPTH == 1) ? 0 : (FIFO_DEPTH < 6) ? 2 : 6;
localparam TYPE = (FIFO_DEPTH == 1) ? "zl_reg" : (FIFO_DEPTH <= 6 ? "ll_reg" : "sandwich");
wire [DATA_W-1:0] r_out_data;
acl_data_fifo
#(
.DATA_WIDTH(DATA_W),
.DEPTH(FIFO_DEPTH),
.IMPL(TYPE),
.ALLOW_FULL_WRITE(1),
.ALMOST_FULL_VALUE(ALMOST_FULL_VALUE)
)
fifo
(
.clock (clock),
.resetn (resetn),
.data_in ( r_out_data ),
.valid_in ( r_o_valid ),
.stall_out (stall_out),
.data_out (dout),
.stall_in (stall_in),
.valid_out (valid_out),
.empty (fifo_empty),
.full (fifo_full),
.almost_full(almost_full)
);
if (ADJUSTED_DEPTH > 0) begin
logic latency_fifo_empty;
logic latency_fifo_full;
acl_data_fifo
#(
.DATA_WIDTH(DATA_W),
.DEPTH(ADJUSTED_DEPTH),
.IMPL("ll_reg"),
.ALLOW_FULL_WRITE(1)
)
latency_adjusted_fifo
(
.clock (clock),
.resetn (resetn),
.data_in (dout),
.valid_in (valid_out),
.stall_out (stall_in),
.data_out (avst_out_data_wire),
.stall_in (~read),
.valid_out (avst_out_valid_wire),
.empty (latency_fifo_empty),
.full (latency_fifo_full)
);
end else begin
assign avst_out_data_wire = dout;
assign stall_in = ~read;
assign avst_out_valid_wire = valid_out;
end
assign r_out_data = avst_in_data;
assign r_o_valid = write;
assign r_o_stall = stall_out;
end
endgenerate
// Profiler support - keep track of FIFO size
generate
if(ACL_PROFILE==1) begin
wire inc_in;
wire inc_out;
reg [FIFOSIZE_WIDTH-1:0] fifosize;
assign inc_in = ( avst_in_valid & avst_in_ready );
assign inc_out= ( avst_out_valid & avst_out_ready );
always@(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
fifosize <= { FIFOSIZE_WIDTH{1'b0} };
end
else begin
if( inc_in & ~inc_out ) begin
fifosize <= fifosize + 1;
end
else if( ~inc_in & inc_out ) begin
fifosize <= fifosize - 1;
end
end
end
assign profile_fifosize = fifosize;
end
else begin
assign profile_fifosize = { FIFOSIZE_WIDTH{1'b0} };
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long int LINF = 0x3f3f3f3f3f3f3f3fll; int g; bool endswith(string a, string b) { if ((int)((a).size()) < (int)((b).size())) return 0; for (int i = 0; i < (int)((b).size()); i++) if (a[(int)((a).size()) - 1 - i] != b[(int)((b).size()) - 1 - i]) return 0; return 1; } bool is_adj(string second) { if (endswith(second, lios )) g = 1; else if (endswith(second, liala )) g = 2; else return 0; return 1; } bool is_noun(string second) { if (endswith(second, etr )) g = 1; else if (endswith(second, etra )) g = 2; else return 0; return 1; } bool is_verb(string second) { if (endswith(second, initis )) g = 1; else if (endswith(second, inites )) g = 2; else return 0; return 1; } int main() { ios::sync_with_stdio(false); vector<string> v; string second; while (cin >> second) v.push_back(second); if ((int)((v).size()) == 1) { if (is_adj(v[0]) or is_noun(v[0]) or is_verb(v[0])) cout << YES << endl; else cout << NO << endl; return 0; } int last = -1; int n = 0; bool masc, deu = 1; for (int i = 0; i < (int)((v).size()); i++) { if (is_adj(v[i])) { if (last > 0) deu = 0; last = 0; } else if (is_noun(v[i])) { if (last > 1) deu = 0; n++; last = 1; } else if (is_verb(v[i])) { last = 2; } else deu = 0; if (!i) masc = (g == 1); else if (masc and g == 2) deu = 0; else if (!masc and g == 1) deu = 0; } if (n != 1) deu = 0; int cu; cout << (deu ? YES : NO ) << endl; return 0; } |
/*
* Check declarations and repeat declarations in nested modules.
*/
timeunit 100us;
timeprecision 1us;
// A local time unit is OK.
module check_tu_nest;
timeunit 10us;
module nested;
timeunit 100us;
timeunit 100us;
endmodule
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp_nest;
timeprecision 10us;
module nested;
timeprecision 1us;
timeprecision 1us;
endmodule
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup_nest;
timeunit 10us;
timeprecision 10us;
module nested;
timeunit 100us;
timeprecision 1us;
timeunit 100us;
timeprecision 1us;
endmodule
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu_nest;
timeprecision 10us;
timeunit 10us;
module nested;
timeprecision 1us;
timeunit 100us;
timeprecision 1us;
timeunit 100us;
endmodule
timeprecision 10us;
timeunit 10us;
endmodule
module check2;
initial begin
$printtimescale(check_tu_nest);
$printtimescale(check_tp_nest);
$printtimescale(check_tup_nest);
$printtimescale(check_tpu_nest);
$display("");
$printtimescale(check_tu_nest.nested);
$printtimescale(check_tp_nest.nested);
$printtimescale(check_tup_nest.nested);
$printtimescale(check_tpu_nest.nested);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; const long long MD = 1e9 + 7; const double pi = acos(-1); struct segmentTree { long long tl = 1, tr = (1ll << 21); segmentTree* left = nullptr; segmentTree* right = nullptr; long long val = 0; segmentTree(long long tl, long long tr) : tl(tl), tr(tr) {} segmentTree() = default; void createSons() { long long tm = (tl + tr) / 2; if (!left) { left = new segmentTree(tl, tm); } if (!right) { right = new segmentTree(tm + 1, tr); } } void update(long long pos, long long val) { if (tl == tr) { this->val = val; return; } long long tm = (tl + tr) / 2; createSons(); if (pos <= tm) { left->update(pos, val); } else { right->update(pos, val); } this->val = (left->val) ^ (right->val); } long long get(long long l, long long r) { if (l > r) { return 0; } if (l == tl && tr == r) { return val; } long long tm = (tl + tr) / 2; createSons(); return (left->get(l, min(r, tm))) ^ (right->get(max(tm + 1, l), r)); } }; ostream& operator<<(ostream& stream, const vector<long long>& v) { for (auto i : v) { stream << i << n ; } return stream; } pair<long long, long long> operator+=(pair<long long, long long>& a, const pair<long long, long long>& b) { a.first += b.first; a.second += b.second; return a; }; long long sqr(long long a) { return a * a % MD; } long long binpow(long long a, long long b) { if (b == 0) { return 1; } if (b % 2 == 0) { return sqr(binpow(a, b / 2)); } return a * binpow(a, b - 1) % MD; } long long fact(long long a) { long long res = 1; for (long long i = 2; i <= a; i++) { res *= i; res %= MD; } return res; } struct edge { long long u, v, c; bool operator<(const edge& other) const { if (c == other.c) { if (u == other.u) { return v < other.v; } return u < other.u; } return c < other.c; } }; struct query { long long u, v, k, ind; bool operator<(const query& other) const { if (k == other.k) { if (u == other.u) { if (ind == other.ind) { return ind < other.ind; } return v < other.v; } return u < other.u; } return k < other.k; } }; vector<long long> g[100006]; long long timer = 1; long long subTreeSize[100006]; long long pred[100006]; long long tIn[100006]; long long tOut[100006]; void dfs(long long v) { tIn[v] = timer++; subTreeSize[v] = 1; for (auto i : g[v]) { if (!tIn[i]) { pred[i] = v; dfs(i); subTreeSize[v] += subTreeSize[i]; } } tOut[v] = timer++; } bool isPred(long long a, long long b) { return (tIn[a] <= tIn[b] && tOut[b] <= tOut[a]); } long long chainNumOfVertex[100006], inChainPositionOfVertex[100006], chainSize[100006], chainRoot[100006], chainsCount; vector<segmentTree> segmTrees; struct HLD { void build(long long v, long long chainNum) { chainNumOfVertex[v] = chainNum; inChainPositionOfVertex[v] = chainSize[chainNum]; chainSize[chainNum]++; if (chainSize[chainNum] == 1) { chainRoot[chainNum] = v; } long long maxChild = -1; for (auto i : g[v]) { if (i != pred[v] && (maxChild == -1 || subTreeSize[i] > subTreeSize[maxChild])) { maxChild = i; } } if (maxChild != -1) { for (auto i : g[v]) { if (i == pred[v]) { continue; } if (i == maxChild) { build(i, chainNum); } else { segmTrees.push_back(segmentTree()); build(i, ++chainsCount); } } } } long long get(long long a, long long b) { long long res = 0; for (long long i = 1; i <= 2; i++) { while (1) { if (isPred(chainRoot[chainNumOfVertex[a]], b)) { break; } segmTrees[chainNumOfVertex[a]].tl = 0; segmTrees[chainNumOfVertex[a]].tr = chainSize[chainNumOfVertex[a]]; res ^= segmTrees[chainNumOfVertex[a]].get(0, inChainPositionOfVertex[a]); a = pred[chainRoot[chainNumOfVertex[a]]]; } swap(a, b); } if (inChainPositionOfVertex[a] > inChainPositionOfVertex[b]) { swap(a, b); } segmTrees[chainNumOfVertex[a]].tl = 0; segmTrees[chainNumOfVertex[a]].tr = chainSize[chainNumOfVertex[a]]; res ^= segmTrees[chainNumOfVertex[a]].get(inChainPositionOfVertex[a] + 1, inChainPositionOfVertex[b]); return res; } void update(long long a, long long val) { segmTrees[chainNumOfVertex[a]].tl = 0; segmTrees[chainNumOfVertex[a]].tr = chainSize[chainNumOfVertex[a]]; segmTrees[chainNumOfVertex[a]].update(inChainPositionOfVertex[a], val); } void add(edge e) { if (pred[e.u] == e.v) { update(e.u, e.c); } else { update(e.v, e.c); } } }; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; string st; cin >> st; st = 0 + st; long long ans = 0; for (long long i = 1; i < st.size(); i++) { if (st[i] == 1 ) { ans = max(2 * i, ans); ans = max((n - i + 1) * 2, ans); } } cout << max(ans, n) << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> r; for (int i = 0; i < n; i++) { int tmp; cin >> tmp; r.push_back(tmp); } int m_lng = 0; for (int i = 0; i < n; i++) { int cnt = 1; int lng = 0; int sum = 0; for (int j = i; j < n; j++) { sum += r[j]; if (sum > 100 * cnt) lng = cnt; cnt++; } if (m_lng < lng) m_lng = lng; } cout << m_lng; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int i, j, ft; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long int n; cin >> n; vector<long long int> v[n]; for (i = 0; i < (n - 1); i++) { long long int b, c; cin >> b >> c; v[b - 1].push_back(c - 1); v[c - 1].push_back(b - 1); } vector<long long int> l(n, 0); queue<long long int> s; s.push(0); l[0] = 1; while (!s.empty()) { long long int front = s.front(); s.pop(); for (i = 0; i < (v[front].size()); i++) { if (!l[v[front][i]]) { s.push(v[front][i]); l[v[front][i]] = l[front] + 1; } } } long long int odd = 0, even = 0; for (i = 0; i < (n); i++) { if (l[i] % 2) odd++; else even++; } cout << odd * even - n + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int vis[5][5]; int ac[5][5], bc[5][5]; pair<int, int> sum[100]; pair<int, int> cal(int a, int b) { if (a == 1) { if (b == 1) return pair<int, int>(0, 0); else if (b == 2) return pair<int, int>(0, 1); return pair<int, int>(1, 0); } else if (a == 2) { if (b == 1) return pair<int, int>(1, 0); else if (b == 2) return pair<int, int>(0, 0); return pair<int, int>(0, 1); } else { if (b == 1) return pair<int, int>(0, 1); else if (b == 2) return pair<int, int>(1, 0); return pair<int, int>(0, 0); } } int main() { long long k, pa = 0, pb = 0; int a, b; scanf( %lld%d%d , &k, &a, &b); for (int i = 1; i <= 3; i++) for (int j = 1; j <= 3; j++) scanf( %d , &ac[i][j]); for (int i = 1; i <= 3; i++) for (int j = 1; j <= 3; j++) scanf( %d , &bc[i][j]); int sz = 1; vis[a][b] = sz++; sum[1] = cal(a, b); int last = 1; for (int i = 1; i <= k; i++) { int na = ac[a][b]; int nb = bc[a][b]; if (vis[na][nb]) { last = vis[na][nb]; break; } a = na, b = nb; vis[a][b] = sz; sum[sz] = pair<int, int>(sum[sz - 1].first + cal(a, b).first, sum[sz - 1].second + cal(a, b).second); sz++; } sz--; if (sz == k) { printf( %d %d n , sum[sz].first, sum[sz].second); return 0; } pa += sum[last - 1].first; pb += sum[last - 1].second; k -= last - 1; long long dv = k / (sz - last + 1); pa += dv * (sum[sz].first - sum[last - 1].first); pb += dv * (sum[sz].second - sum[last - 1].second); k %= (sz - last + 1); if (k != 0) { pa += (sum[last + k - 1].first - sum[last - 1].first); pb += (sum[last + k - 1].second - sum[last - 1].second); } printf( %lld %lld n , pa, pb); } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Park_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Park_Transform
// Source Path: velocityControlHdl/Transform_ABC_to_dq/Park_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Park_Transform
(
sin_coefficient,
cos_coefficient,
alpha_current,
beta_current,
direct_current,
quadrature_current
);
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
input signed [17:0] alpha_current; // sfix18_En13
input signed [17:0] beta_current; // sfix18_En13
output signed [17:0] direct_current; // sfix18_En15
output signed [17:0] quadrature_current; // sfix18_En15
wire signed [35:0] Product2_out1; // sfix36_En29
wire signed [35:0] Product3_out1; // sfix36_En29
wire signed [35:0] Add1_out1; // sfix36_En29
wire signed [17:0] D_Data_Type_out1; // sfix18_En15
wire signed [35:0] Product1_out1; // sfix36_En29
wire signed [35:0] Product_out1; // sfix36_En29
wire signed [35:0] Add_out1; // sfix36_En29
wire signed [17:0] Q_Data_Type_out1; // sfix18_En15
// Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame.
//
// Park Transform
// <S42>/Product2
assign Product2_out1 = alpha_current * cos_coefficient;
// <S42>/Product3
assign Product3_out1 = beta_current * sin_coefficient;
// <S42>/Add1
assign Add1_out1 = Product2_out1 + Product3_out1;
// <S42>/D_Data_Type
assign D_Data_Type_out1 = ((Add1_out1[35] == 1'b0) && (Add1_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 :
((Add1_out1[35] == 1'b1) && (Add1_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 :
$signed(Add1_out1[31:14])));
assign direct_current = D_Data_Type_out1;
// <S42>/Product1
assign Product1_out1 = beta_current * cos_coefficient;
// <S42>/Product
assign Product_out1 = alpha_current * sin_coefficient;
// <S42>/Add
assign Add_out1 = Product1_out1 - Product_out1;
// <S42>/Q_Data_Type
assign Q_Data_Type_out1 = ((Add_out1[35] == 1'b0) && (Add_out1[34:31] != 4'b0000) ? 18'sb011111111111111111 :
((Add_out1[35] == 1'b1) && (Add_out1[34:31] != 4'b1111) ? 18'sb100000000000000000 :
$signed(Add_out1[31:14])));
assign quadrature_current = Q_Data_Type_out1;
endmodule // velocityControlHdl_Park_Transform
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
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// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
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// -- Applications"). Customer assumes the sole risk and
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// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI4Lite Upizer
// Converts 32-bit AXI4Lite on Slave Interface to 64-bit AXI4Lite on Master Interface.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi4lite_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_axi4lite_upsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range 3 - 64.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [3-1:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [32-1:0] s_axi_wdata,
input wire [32/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [3-1:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [32-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [64-1:0] m_axi_wdata,
output wire [64/8-1:0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [64-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
reg s_axi_arready_i ;
reg m_axi_arvalid_i ;
reg m_axi_rready_i ;
reg s_axi_rvalid_i ;
reg ar_done ;
reg araddr2 ;
reg s_axi_awready_i ;
reg s_axi_bvalid_i ;
reg m_axi_awvalid_i ;
reg m_axi_wvalid_i ;
reg m_axi_bready_i ;
reg aw_done ;
reg w_done ;
generate
if (C_AXI_SUPPORTS_READ != 0) begin : gen_read
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_arready_i <= 1'b0 ;
m_axi_arvalid_i <= 1'b0 ;
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1;
ar_done <= 1'b0 ;
araddr2 <= 1'b0 ;
end else begin
s_axi_arready_i <= 1'b0 ; // end single-cycle pulse
m_axi_rready_i <= 1'b0; // end single-cycle pulse
if (s_axi_rvalid_i) begin
if (s_axi_rready) begin
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
ar_done <= 1'b0;
end
end else if (m_axi_rvalid & ar_done) begin
s_axi_rvalid_i <= 1'b1;
end else if (m_axi_arvalid_i) begin
if (m_axi_arready) begin
m_axi_arvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1 ; // begin single-cycle pulse
araddr2 <= s_axi_araddr[2];
ar_done <= 1'b1;
end
end else if (s_axi_arvalid & ~ar_done) begin
m_axi_arvalid_i <= 1'b1;
end
end
end
assign m_axi_arvalid = m_axi_arvalid_i ;
assign s_axi_arready = s_axi_arready_i ;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign s_axi_rvalid = s_axi_rvalid_i ;
assign m_axi_rready = m_axi_rready_i ;
assign s_axi_rdata = araddr2 ? m_axi_rdata[63:32] : m_axi_rdata[31:0];
assign s_axi_rresp = m_axi_rresp;
end else begin : gen_noread
assign m_axi_arvalid = 1'b0 ;
assign s_axi_arready = 1'b0 ;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_arprot = 3'b0 ;
assign s_axi_rvalid = 1'b0 ;
assign m_axi_rready = 1'b0 ;
assign s_axi_rresp = 2'b0 ;
assign s_axi_rdata = 32'b0 ;
end
if (C_AXI_SUPPORTS_WRITE != 0) begin : gen_write
always @(posedge aclk) begin
if (~aresetn) begin
m_axi_awvalid_i <= 1'b0 ;
s_axi_awready_i <= 1'b0 ;
m_axi_wvalid_i <= 1'b0 ;
s_axi_bvalid_i <= 1'b0 ;
m_axi_bready_i <= 1'b0 ;
aw_done <= 1'b0 ;
w_done <= 1'b0 ;
end else begin
m_axi_bready_i <= 1'b0; // end single-cycle pulse
if (s_axi_bvalid_i) begin
if (s_axi_bready) begin
s_axi_bvalid_i <= 1'b0;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
aw_done <= 1'b0;
w_done <= 1'b0;
end
end else if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0; // end single-cycle pulse
s_axi_bvalid_i <= 1'b1;
end else if (aw_done & w_done) begin
if (m_axi_bvalid) begin
s_axi_awready_i <= 1'b1; // begin single-cycle pulse
end
end else begin
if (m_axi_awvalid_i) begin
if (m_axi_awready) begin
m_axi_awvalid_i <= 1'b0;
aw_done <= 1'b1;
end
end else if (s_axi_awvalid & ~aw_done) begin
m_axi_awvalid_i <= 1'b1;
end
if (m_axi_wvalid_i) begin
if (m_axi_wready) begin
m_axi_wvalid_i <= 1'b0;
w_done <= 1'b1;
end
end else if (s_axi_wvalid & (m_axi_awvalid_i | aw_done) & ~w_done) begin
m_axi_wvalid_i <= 1'b1;
end
end
end
end
assign m_axi_awvalid = m_axi_awvalid_i ;
assign s_axi_awready = s_axi_awready_i ;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_wvalid = m_axi_wvalid_i ;
assign s_axi_wready = s_axi_awready_i ;
assign m_axi_wdata = {s_axi_wdata,s_axi_wdata};
assign m_axi_wstrb = s_axi_awaddr[2] ? {s_axi_wstrb, 4'b0} : {4'b0, s_axi_wstrb};
assign s_axi_bvalid = s_axi_bvalid_i ;
assign m_axi_bready = m_axi_bready_i ;
assign s_axi_bresp = m_axi_bresp;
end else begin : gen_nowrite
assign m_axi_awvalid = 1'b0 ;
assign s_axi_awready = 1'b0 ;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_awprot = 3'b0 ;
assign m_axi_wvalid = 1'b0 ;
assign s_axi_wready = 1'b0 ;
assign m_axi_wdata = 64'b0 ;
assign m_axi_wstrb = 8'b0 ;
assign s_axi_bvalid = 1'b0 ;
assign m_axi_bready = 1'b0 ;
assign s_axi_bresp = 2'b0 ;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int need, e; int mat[128][128]; bool found; int add; int v; int main() { memset(mat, 0, sizeof mat); cin >> need; e = 0; while (e < need) { found = false; for (int i = 1; i <= v && found == false; i++) for (int j = i + 1; j <= v && found == false; j++) { if (mat[i][j] == 1) continue; add = 0; for (int k = 1; k <= v; k++) { if (k == i || k == j) continue; if (mat[i][k] && mat[k][j]) add++; } if (e + add <= need) { found = true; e += add; mat[i][j] = 1; mat[j][i] = 1; } } if (found == false) v++; } cout << v << endl; for (int i = 1; i <= v; i++) { for (int j = 1; j <= v; j++) cout << mat[i][j]; cout << endl; } return 0; } |
(*
Copyright © 2006-2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export RSetoid.
Require Import Relation_Definitions.
Require Export Qpossec.
Require Import COrdFields2.
Require Import Qordfield.
Require Import QMinMax.
Require Import List.
Require Import CornTac.
Require Import stdlib_omissions.Q.
Require QnnInf.
Import QnnInf.notations.
Open Local Scope Q_scope.
Set Implicit Arguments.
(**
* Metric Space
In this version, a metric space over a setoid X is characterized by a
ball relation B where B e x y is intended to mean that the two points
x and y are within e of each other ( d(x,y)<=e ). This is characterized
by the axioms given in the record structure below.
*)
Record is_MetricSpace (X : RSetoid) (B: Qpos -> relation X) : Prop :=
{ msp_refl: forall e, Reflexive (B e)
; msp_sym: forall e, Symmetric (B e)
; msp_triangle: forall e1 e2 a b c, B e1 a b -> B e2 b c -> B (e1 + e2)%Qpos a c
; msp_closed: forall e a b, (forall d, B (e+d)%Qpos a b) -> B e a b
; msp_eq: forall a b, (forall e, B e a b) -> st_eq a b
}.
Record MetricSpace : Type :=
{ msp_is_setoid :> RSetoid
; ball : Qpos -> msp_is_setoid -> msp_is_setoid -> Prop
; ball_wd : forall (e1 e2:Qpos), (QposEq e1 e2) ->
forall x1 x2, (st_eq x1 x2) ->
forall y1 y2, (st_eq y1 y2) ->
(ball e1 x1 y1 <-> ball e2 x2 y2)
; msp : is_MetricSpace msp_is_setoid ball
}.
(* begin hide *)
Implicit Arguments ball [m].
(*This is intended to be used as a ``type cast'' that Coq won't randomly make disappear.
It is useful when defining setoid rewrite lemmas for st_eq.*)
Definition ms_id (m:MetricSpace) (x:m) : m := x.
Implicit Arguments ms_id [m].
Add Parametric Morphism (m:MetricSpace) : (@ball m) with signature QposEq ==> (@st_eq m) ==> (@st_eq m) ==> iff as ball_compat.
Proof.
exact (@ball_wd m).
Qed.
(* end hide *)
Section Metric_Space.
(*
** Ball lemmas
*)
Variable X : MetricSpace.
(** These lemmas give direct access to the ball axioms of a metric space
*)
Lemma ball_refl : forall e (a:X), ball e a a.
Proof.
apply (msp_refl (msp X)).
Qed.
Lemma ball_sym : forall e (a b:X), ball e a b -> ball e b a.
Proof.
apply (msp_sym (msp X)).
Qed.
Lemma ball_triangle : forall e1 e2 (a b c:X), ball e1 a b -> ball e2 b c -> ball (e1+e2) a c.
Proof.
apply (msp_triangle (msp X)).
Qed.
Lemma ball_closed : forall e (a b:X), (forall d, ball (e+d) a b) -> ball e a b.
Proof.
apply (msp_closed (msp X)).
Qed.
Lemma ball_eq : forall (a b:X), (forall e, ball e a b) -> st_eq a b.
Proof.
apply (msp_eq (msp X)).
Qed.
Lemma ball_eq_iff : forall (a b:X), (forall e, ball e a b) <-> st_eq a b.
Proof.
split.
apply ball_eq.
intros H e.
rewrite -> H.
apply ball_refl.
Qed.
(** The ball constraint on a and b can always be weakened. Here are
two forms of the weakening lemma.
*)
Lemma ball_weak : forall e d (a b:X), ball e a b -> ball (e+d) a b.
Proof.
intros e d a b B1.
eapply ball_triangle.
apply B1.
apply ball_refl.
Qed.
Hint Resolve ball_refl ball_triangle ball_weak : metric.
Lemma ball_weak_le : forall (e d:Qpos) (a b:X), e<=d -> ball e a b -> ball d a b.
Proof.
intros e d a b Hed B1.
destruct (Qle_lt_or_eq _ _ Hed).
destruct (Qpos_lt_plus H) as [c Hc].
rewrite <- Q_Qpos_plus in Hc.
change (QposEq d (e+c)) in Hc.
rewrite -> Hc; clear - B1.
auto with *.
change (QposEq e d) in H.
rewrite <- H.
assumption.
Qed.
End Metric_Space.
(* begin hide *)
Hint Resolve ball_refl ball_sym ball_triangle ball_weak : metric.
(* end hide *)
(** We can easily generalize ball to take the ratio from Q or QnnInf: *)
Section gball.
Context {m: MetricSpace}.
Definition gball (q: Q) (x y: m): Prop :=
match Qdec_sign q with
| inl (inl _) => False (* q < 0, silly *)
| inl (inr p) => ball (exist (Qlt 0) q p) x y (* 0 < q, normal *)
| inr _ => x[=]y (* q == 0 *)
end.
(* Program can make this definition slightly cleaner, but the resulting term is much nastier... *)
Definition gball_ex (e: QnnInf): relation m :=
match e with
| QnnInf.Finite e' => gball (proj1_sig e')
| QnnInf.Infinite => fun _ _ => True
end.
Lemma ball_gball (q: Qpos) (x y: m): gball q x y <-> ball q x y.
Proof with auto.
unfold gball.
revert q x y.
intros [q p] ??. simpl.
destruct Qdec_sign as [[A | A] | A].
exfalso.
apply (Qlt_is_antisymmetric_unfolded q 0)...
apply ball_wd; reflexivity.
exfalso.
apply (Qlt_irrefl 0).
rewrite <- A at 2...
Qed.
Global Instance gball_Proper: Proper (Qeq ==> @st_eq m ==> @st_eq m ==> iff) gball.
Proof with auto.
intros x y E a b F v w G.
unfold gball.
destruct Qdec_sign as [[A | B] | C];
destruct Qdec_sign as [[P | Q] | R].
reflexivity.
exfalso. apply (Qlt_irrefl 0). apply Qlt_trans with x... rewrite E...
exfalso. apply (Qlt_irrefl 0). rewrite <- R at 1. rewrite <- E...
exfalso. apply (Qlt_irrefl 0). apply Qlt_trans with x... rewrite E...
apply ball_wd...
exfalso. apply (Qlt_irrefl 0). rewrite <- R at 2. rewrite <- E...
exfalso. apply (Qlt_irrefl 0). rewrite <- C at 1. rewrite E...
exfalso. apply (Qlt_irrefl 0). rewrite <- C at 2. rewrite E...
rewrite F, G. reflexivity.
Qed.
Global Instance gball_ex_Proper: Proper (QnnInf.eq ==> @st_eq m ==> @st_eq m ==> iff) gball_ex.
Proof.
repeat intro.
destruct x, y. intuition. intuition. intuition.
apply gball_Proper; assumption.
Qed.
Global Instance gball_refl (e: Q): 0 <= e -> Reflexive (gball e).
Proof with auto.
repeat intro.
unfold gball.
destruct Qdec_sign as [[?|?]|?].
apply (Qlt_not_le e 0)...
apply ball_refl.
reflexivity.
Qed.
Global Instance gball_ex_refl (e: QnnInf): Reflexive (gball_ex e).
Proof.
destruct e. intuition.
apply gball_refl, proj2_sig.
Qed.
Global Instance gball_sym (e: Q): Symmetric (gball e).
Proof with auto.
unfold gball. repeat intro.
destruct Qdec_sign as [[?|?]|?]...
apply ball_sym...
symmetry...
Qed.
Lemma gball_ex_sym (e: QnnInf): Symmetric (gball_ex e).
Proof. destruct e. auto. simpl. apply gball_sym. Qed.
Lemma gball_triangle (e1 e2: Q) (a b c: m):
gball e1 a b -> gball e2 b c -> gball (e1 + e2) a c.
Proof with auto with *.
unfold gball.
intros.
destruct (Qdec_sign e1) as [[A|B]|C].
exfalso...
destruct (Qdec_sign e2) as [[?|?]|?].
intuition.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
assert (0 < e1 + e2).
apply Qplus_lt_le_0_compat...
revert H1. apply Qle_not_lt...
simpl.
setoid_replace (exist (Qlt 0) (e1 + e2) q0) with (exist (Qlt 0) e1 B + exist (Qlt 0) e2 q)%Qpos by reflexivity.
apply ball_triangle with b...
exfalso.
assert (0 < e1 + e2).
apply Qplus_lt_le_0_compat...
revert H1. rewrite q0.
apply Qlt_irrefl.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite q. rewrite Qplus_0_r. apply Qle_not_lt...
apply ball_gball. simpl. rewrite q, Qplus_0_r. rewrite <- H0. apply ball_gball in H. assumption.
exfalso.
revert q0. rewrite q. rewrite Qplus_0_r. intro. clear H. revert B. rewrite H1. apply Qlt_irrefl.
destruct (Qdec_sign e2) as [[?|?]|?].
intuition.
apply ball_gball in H0.
simpl in H0.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite C. rewrite Qplus_0_l. apply Qle_not_lt...
apply ball_gball. simpl.
rewrite C, Qplus_0_l, H...
exfalso. revert q0. rewrite C, Qplus_0_l. intro. clear H0. revert q. rewrite H1. apply Qlt_irrefl.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite C, q, Qplus_0_l. apply Qlt_irrefl.
exfalso. revert q0. rewrite C, q, Qplus_0_l. apply Qlt_irrefl.
transitivity b...
Qed. (* TODO: THE HORROR!! *)
Lemma gball_ex_triangle (e1 e2: QnnInf) (a b c: m):
gball_ex e1 a b -> gball_ex e2 b c -> gball_ex (e1 + e2)%QnnInf a c.
Proof. destruct e1, e2; auto. simpl. apply gball_triangle. Qed.
Lemma gball_0 (x y: m): gball 0 x y <-> x [=] y.
Proof. reflexivity. Qed.
Lemma gball_weak_le (q q': Q): q <= q' -> forall x y, gball q x y -> gball q' x y.
Proof with auto.
revert q q'.
intros ?? E ?? F.
unfold gball in F.
destruct Qdec_sign as [[A | B] | C].
intuition.
assert (0 < q') as q'p. apply Qlt_le_trans with q...
apply (ball_gball (exist _ q' q'p)).
apply ball_weak_le with (exist _ q B)...
rewrite F.
apply gball_refl.
rewrite <- C...
Qed.
End gball.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_TB_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_TB_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s50.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkdlybuf4s50 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_TB_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void read(T &x) { int f = 0; x = 0; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) f |= (ch == - ); for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; if (f) x = -x; } const int N = 20, mod = 998244353; int f[N][N][N][N][2][2]; int g[N][N][N][N][2][2]; int x[N], y[N], n, m; void add(int &x, int y) { x = (x + y >= mod ? x + y - mod : x + y); } int main() { read(n), read(m); for (int i = (1); i <= (n); i++) read(x[i]), read(y[i]); f[0][0][0][0][0][0] = 1; for (; m; m >>= 1) { memset(g, 0, sizeof g); for (int px = 0; px < (N); px++) for (int nx = 0; nx < (N); nx++) for (int py = 0; py < (N); py++) for (int ny = 0; ny < (N); ny++) for (int fx = 0; fx < (2); fx++) for (int fy = 0; fy < (2); fy++) { int t = f[px][nx][py][ny][fx][fy]; if (!t) continue; for (int s = 0; s < (1 << n); s++) { int Px = px, Nx = nx, Py = py, Ny = ny; for (int i = (1); i <= (n); i++) if (s >> (i - 1) & 1) { Px += max(x[i], 0); Nx -= min(x[i], 0); Py += max(y[i], 0); Ny -= min(y[i], 0); } if ((Px & 1) != (Nx & 1) || (Py & 1) != (Ny & 1)) continue; int gx = ((Px & 1) < (m & 1) ? 0 : ((Px & 1) > (m & 1) ? 1 : fx)); int gy = ((Py & 1) < (m & 1) ? 0 : ((Py & 1) > (m & 1) ? 1 : fy)); Px >>= 1, Nx >>= 1, Py >>= 1, Ny >>= 1; add(g[Px][Nx][Py][Ny][gx][gy], t); } } swap(f, g); } cout << ((f[0][0][0][0][0][0] + mod - 1) % mod) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, n, w; string s; cin >> t; while (t--) { cin >> n >> s; bool flag = 0; if (n % 2) { for (int i = 0; i < n; i += 2) { if ((s[i] - 0 ) % 2) { flag = 1; break; } } w = flag ? 1 : 2; cout << w << endl; } else { for (int i = 1; i < n; i += 2) { if ((s[i] - 0 ) % 2 == 0) { flag = 1; break; } } w = flag ? 2 : 1; cout << w << endl; } } } |
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int MAXN = 1000010; int get() { int x; bool f = 0; char c; while (!isdigit(c = getchar())) if (c == - ) f = 1; x = c - 48; while (isdigit(c = getchar())) x = (x << 1) + (x << 3) + c - 48; if (f) return -x; else return x; } int N, A[MAXN]; int add(int x, int v) { x += v; if (x >= MOD) x -= MOD; return x; } int main() { N = get(); for (int i = 1; i <= N; ++i) A[i] = get(); int F = 0, G = 0, v = 0; for (int i = 1; i <= N; ++i) { v = add(1LL * v * 2 % MOD, A[i]); F = add(G, v); G = add(G, F); } cout << F << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using std::bitset; const double Pi = acos(-1); namespace fastIO { template <class T> inline void read(T &x) { x = 0; bool fu = 0; char ch = 0; while (ch > 9 || ch < 0 ) { ch = getchar(); if (ch == - ) fu = 1; } while (ch <= 9 && ch >= 0 ) x = (x * 10 - 48 + ch), ch = getchar(); if (fu) x = -x; } inline int read() { int x = 0; bool fu = 0; char ch = 0; while (ch > 9 || ch < 0 ) { ch = getchar(); if (ch == - ) fu = 1; } while (ch <= 9 && ch >= 0 ) x = (x * 10 - 48 + ch), ch = getchar(); return fu ? -x : x; } char _n_u_m_[40]; template <class T> inline void write(T x) { if (x == 0) { putchar( 0 ); return; } T tmp = x > 0 ? x : -x; if (x < 0) putchar( - ); register int cnt = 0; while (tmp > 0) { _n_u_m_[cnt++] = tmp % 10 + 0 ; tmp /= 10; } while (cnt > 0) putchar(_n_u_m_[--cnt]); } template <class T> inline void write(T x, char ch) { write(x); putchar(ch); } } // namespace fastIO using namespace fastIO; const int MAXN = 1000005; int len[MAXN], ch[MAXN][26], fail[MAXN], cnt, lst, up[MAXN], orz[MAXN]; long long qwq[MAXN], ans[MAXN]; char c[MAXN], ccf[MAXN]; int now, n; inline void insert(int pos) { while (c[pos] != c[pos - len[lst] - 1]) lst = fail[lst]; if (!ch[lst][c[pos] - 97]) { len[++cnt] = len[lst] + 2; register int i = fail[lst]; while (c[pos] != c[pos - len[i] - 1]) i = fail[i]; fail[cnt] = ch[i][c[pos] - 97]; ch[lst][c[pos] - 97] = cnt; orz[cnt] = len[cnt] - len[fail[cnt]]; if (orz[cnt] == orz[fail[cnt]]) up[cnt] = up[fail[cnt]]; else up[cnt] = fail[cnt]; } lst = ch[lst][c[pos] - 97]; } int main() { len[1] = -1; fail[0] = 1; up[0] = 1; ans[0] = 1; cnt = 1; scanf( %s , ccf + 1); n = strlen(ccf + 1); if (n % 2) { cerr << Fuck CCF!!! << endl; cout << 0; return 0; } for (register int i = 1, iend = n / 2; i <= iend; ++i) { c[2 * i - 1] = ccf[i]; c[i << 1] = ccf[n - i + 1]; } for (register int i = 1, iend = n; i <= iend; ++i) { insert(i); for (register int j = lst; j; j = up[j]) { qwq[j] = ans[i - len[up[j]] - orz[j]]; if (up[j] != fail[j]) qwq[j] += qwq[fail[j]]; qwq[j] %= 1000000007ll; if (!(i & 1)) ans[i] += qwq[j], ans[i] %= 1000000007ll; } } cout << ans[n]; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, kov = 1; int t[502][502]; void ert(int a, int b) { t[a][b] = kov, kov++; } int main() { cin >> n; if (n <= 2) { cout << -1 << n ; return 0; } if (n == 3) { cout << 1 << << 3 << << 2 << n ; cout << 5 << << 4 << << 8 << n ; cout << 9 << << 6 << << 7 << n ; return 0; } for (int i = n - 3; i >= 1; i--) ert(i, n); for (int i = 1; i <= n - 1; i++) { for (int j = 1; j <= n - 1; j++) { if (i % 2 == n % 2) ert(i, n - j); else ert(i, j); } } t[n - 2][n] = n * n, t[n][n] = n * n - 1; ert(n, n - 2), ert(n, n - 1), ert(n - 1, n); for (int i = 1; i <= n - 3; i++) ert(n, i); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cout << t[i][j] << ; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int buff1, buff2; void solution(vector<int> v) { map<int, int> counter; for (int n : v) counter[n]++; vector<int> counts; for (auto it : counter) { counts.push_back(it.second); } sort(counts.begin(), counts.end(), greater<int>()); int cur = INT_MAX, ret = 0; for (int n : counts) { if (cur <= 1) { break; } cur = min(cur - 1, n); ret += cur; } cout << ret << endl; } int main() { int nTest; cin >> nTest; for (int i = 0; i < nTest; i++) { int N; cin >> N; vector<int> v; for (int i = 0; i < N; i++) { cin >> buff1; v.push_back(buff1); } solution(v); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, sol; multiset<int> S; multiset<int>::iterator p; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int val; scanf( %d , &val); S.insert(val); } long long s = 0; for (int i = 1; i <= n; i++) { p = S.lower_bound(s); if (p == S.end()) break; if (*p < s) p++; sol++; s += *p; S.erase(p); } printf( %d n , sol); return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x * 10) + (ch - 0 ); ch = getchar(); } return x * f; } long long Pow[25][505], n, V, ans, B; long long val[505]; void dfs2(long long i, long long b, long long a) { if ((double)b * b > V / a) { return; } if (i > n) { B = max(B, b); return; } for (register long long j = val[i]; j >= 0; --j) { dfs2(i + 1, b * Pow[i][j], a); } } long long ansA, ansB, ansC; void dfs1(long long i, long long a) { if ((double)a * a * a > V) { return; } if (i > n) { const long long t = V / a; long long Smax = 4 * a * sqrt(t) + 2 * t; if (Smax >= ans) return; B = 0, dfs2(1, 1, a); long long c = V / a / B, Ans = (a * B + B * c + c * a) << 1; if (Ans < ans) { ans = Ans; ansA = a, ansB = B, ansC = c; } return; } for (register long long j = val[i]; j >= 0; --j) { val[i] -= j; dfs1(i + 1, a * Pow[i][j]); val[i] += j; } } int main() { long long T; cin >> T; while (T--) { cin >> n; V = 1; for (register long long i = 1; i <= n; ++i) { long long a, b; cin >> a >> b; val[i] = b; Pow[i][0] = 1; for (register long long j = 1; j <= b; ++j) { Pow[i][j] = Pow[i][j - 1] * a; } V *= Pow[i][b]; } ans = 1ll << 62; dfs1(1, 1); cout << ans << << ansA << << ansB << << ansC << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPAD_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPAD_BLACKBOX_V
/**
* top_power_hvc_wpad: A power pad with an ESD high-voltage clamp.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpad (
P_PAD ,
AMUXBUS_A,
AMUXBUS_B
);
inout P_PAD ;
inout AMUXBUS_A;
inout AMUXBUS_B;
// Voltage supply signals
supply1 OGC_HVC ;
supply1 DRN_HVC ;
supply0 SRC_BDY_HVC;
supply1 P_CORE ;
supply1 VDDIO ;
supply1 VDDIO_Q ;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH ;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q ;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPAD_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XOR2_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; vector<int> graph[123490]; bool attacked[123490], visited[123490]; int n, m, parent[123490]; int dist, last; void dfs(int u, int depth) { if (attacked[u]) { if (dist < depth) { dist = depth; last = u; } else { if (dist == depth) { last = min(last, u); } } } visited[u] = true; for (int i = (int)0; i <= (int)graph[u].size() - 1; i++) { int v = graph[u][i]; if (!visited[v]) { parent[v] = u; dfs(v, depth + 1); } } } vector<int> path; void augment_path(int v) { visited[v] = true; path.push_back(v); if (parent[v] == -1) return; augment_path(parent[v]); } int all = 0; bool dfs2(int u) { visited[u] = true; int ans = 0; for (int i = (int)0; i <= (int)graph[u].size() - 1; i++) { int v = graph[u][i]; if (!visited[v]) { ans |= dfs2(v); } } if (attacked[u]) ans = 1; all += ans; return ans; } int main() { cin >> n >> m; int u, v; for (int i = (int)1; i <= (int)n - 1; i++) { cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } int tmp = 123490; for (int i = (int)1; i <= (int)m; i++) { cin >> u; attacked[u] = true; tmp = min(tmp, u); } dist = -1; dfs(tmp, 0); tmp = last; memset(parent, -1, sizeof parent); memset(visited, 0, sizeof visited); dist = -1; dfs(last, 0); cout << min(tmp, last) << endl; memset(visited, 0, sizeof visited); dfs2(tmp); cout << (all * 2) - 2 - dist << endl; return 0; } |
module TBCTRL (
input HRESETn,
input HCLK,
// input
input HREADYin,
input HREADYout,
input HWRITEin,
input HWRITEout,
input HSEL,
input HGRANT,
// Output
output MAPSn,
output MDPSn,
output DENn,
output SDPSn,
output SRSn
);
// Master
wire MasterReadData;
wire SlaveAddrPhaseSel;
wire MasterAddrPhaseSel;
reg MasterDataPhaseSel;
reg MRWSel;
reg reg_HGRANT;
// Slave
reg SlaveDataPhaseSel;
reg RWSel;
//assign DENn= MDPSn & SDPSn;
assign DENn = (MDPSn)?SDPSn:MDPSn;
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
reg_HGRANT <= 1'b0;
else
reg_HGRANT <= HGRANT;
end
// ----------------------------------------------------------
// ------ Master Control ------------------------------------
// ----------------------------------------------------------
// Control Logic
assign MAPSn = ~MasterAddrPhaseSel;
assign MDPSn = ~(MasterDataPhaseSel & MRWSel);
// Master Address Phase
assign MasterAddrPhaseSel = reg_HGRANT;
// Master Data Phase
assign MasterReadData = MasterDataPhaseSel & (~MRWSel);
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
MasterDataPhaseSel <= 1'b1;
else
begin
if (HREADYin)
MasterDataPhaseSel <= MasterAddrPhaseSel ;
end
end
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
MRWSel <= 1'b0;
else
begin
if (HREADYin)
MRWSel <= HWRITEout;
end
end
//---------END MASTER CONTROL -------------------------------
// ----------------------------------------------------------
// ------ Slave Control ------------------------------------
// ----------------------------------------------------------
// Slave Address Phase
assign SlaveAddrPhaseSel = HSEL;
assign SDPSn = ~(SlaveDataPhaseSel & RWSel);
assign SRSn = ~SlaveDataPhaseSel;
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
SlaveDataPhaseSel <= 1'b1;
else
begin
if (HREADYin)
SlaveDataPhaseSel <= SlaveAddrPhaseSel ;
else
SlaveDataPhaseSel <= SlaveDataPhaseSel;
end
end
// Read Write Select
always @(posedge HCLK or negedge HRESETn)
begin
if (!HRESETn)
RWSel <= 1'b0;
else
begin
if (HREADYin)
RWSel <= ~HWRITEin ;
else
RWSel <=RWSel;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct UnionFind { int n; vector<int> p, rank; int findSet(int i) { return (p[i] == i ? i : (p[i] = findSet(p[i]))); } bool isSameSet(int i, int j) { return (findSet(i) == findSet(j)); } void unionSet(int i, int j) { if (!isSameSet(i, j)) { int x = findSet(i); int y = findSet(j); if (rank[x] > rank[y]) { p[y] = x; } else { p[x] = y; } if (rank[x] == rank[y]) { rank[y]++; } } } UnionFind(int _n) { n = _n; for (int i = 0; i < n; i++) { p.push_back(i); rank.push_back(0); } } }; int n, m; vector<int> P; vector<int> type; vector<pair<int, int> > query; vector<pair<int, int> > t3; vector<int> H; void calculateHeight() { vector<int> inDegree(n, 0); for (int i = 0; i < n; i++) { if (P[i] != -1) { inDegree[P[i]] += 1; } } H.resize(n, -1); queue<int> q; for (int i = 0; i < n; i++) { if (inDegree[i] == 0) { H[i] = 0; q.push(i); } } while (!q.empty()) { int u = q.front(); q.pop(); if (P[u] == -1) { continue; } H[P[u]] = max(H[P[u]], H[u] + 1); inDegree[P[u]] -= 1; if (inDegree[P[u]] == 0) { q.push(P[u]); } } } set<pair<int, int> > isParent; vector<vector<int> > G; vector<vector<int> > Q; vector<int> visited; void dfs(int u) { visited[u] = true; for (int i = 0; i < Q[u].size(); i++) { int p = Q[u][i]; if (visited[p]) { isParent.insert(make_pair(p, u)); } } for (int i = 0; i < G[u].size(); i++) { dfs(G[u][i]); } visited[u] = false; } int main() { cin >> n >> m; P.resize(n, -1); G.resize(n); Q.resize(n); visited.resize(n, false); type.resize(m); query.resize(m); for (int i = 0; i < m; i++) { cin >> type[i]; if (type[i] == 1) { cin >> query[i].first >> query[i].second; query[i].first -= 1; query[i].second -= 1; P[query[i].first] = query[i].second; G[query[i].second].push_back(query[i].first); } else if (type[i] == 2) { cin >> query[i].first; query[i].first -= 1; } else { cin >> query[i].first >> query[i].second; query[i].first -= 1; query[i].second -= 1; t3.push_back(make_pair(query[i].second, i)); } } int t3i = 0; int doc = 0; sort(t3.begin(), t3.end()); for (int i = 0; i < m; i++) { if (type[i] == 2) { for (; t3i < t3.size() && t3[t3i].first == doc; t3i++) { int c = query[i].first; int p = query[t3[t3i].second].first; Q[c].push_back(p); } doc++; } } for (int i = 0; i < n; i++) { if (P[i] == -1) { dfs(i); } } UnionFind uf(n); t3i = 0; doc = 0; for (int i = 0; i < m; i++) { if (type[i] == 1) { uf.unionSet(query[i].first, query[i].second); } else if (type[i] == 2) { for (; t3i < t3.size() && t3[t3i].first == doc; t3i++) { int c = query[i].first; int p = query[t3[t3i].second].first; if (uf.isSameSet(c, p) && isParent.count(make_pair(p, c))) { query[t3[t3i].second].second = true; } else { query[t3[t3i].second].second = false; } } doc++; } } for (int i = 0; i < m; i++) { if (type[i] == 3) { if (query[i].second) { cout << YES n ; } else { cout << NO n ; } } } } |
/*
verilog cpu module.
*/
`include "defines.v"
module millcpu(
input wire clk, rst,
input wire [`REGW-1:0] ins,
output wire mem_we,
output wire [`REGW-1:0] paddr, mem_waddr, mem_wdata
);
wire gr_we, pc_we, pc_ie, zf;
wire [`STGW-1:0] cs;
wire [`REGO-1:0] gr_raddr1, gr_raddr2, gr_waddr;
wire [`REGW-1:0] rdata1, rdata2, dout;
assign mem_waddr = rdata1;
assign mem_wdata = rdata2;
/* instances */
stage_con stage_con(
.clk(clk),
.rst(rst),
.cs(cs)
);
stages stages(
.ins(ins),
.cs(cs),
.gr_raddr1(gr_raddr1),
.gr_raddr2(gr_raddr2),
.gr_waddr(gr_waddr),
.gr_we(gr_we),
.pc_we(pc_we),
.mem_we(mem_we),
.pc_ie(pc_ie),
.zf(zf)
);
pc pc(
.clk(clk),
.rst(rst),
.we(pc_we),
.ie(pc_ie),
.waddr(rdata1),
.paddr(paddr)
);
alu alu(
.ins(ins),
.din1(rdata1),
.din2(rdata2),
.dout(dout),
.zf(zf)
);
gr gr(
.clk(clk),
.rst(rst),
.we(gr_we),
.raddr1(gr_raddr1),
.raddr2(gr_raddr2),
.waddr(gr_waddr),
.wdata(dout),
.rdata1(rdata1),
.rdata2(rdata2)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(T a) { return a * a; } #pragma comment(linker, /STACK:16777216 ) int n; char s[105]; string str; int main() { gets(s); str = s; n = strlen(s); for (int i = n - 1; i > 0; --i) for (int j = 0; j <= n - i; ++j) for (int k = j + 1; k <= n - i; ++k) if (str.substr(j, i) == str.substr(k, i)) { printf( %d , i); return 0; } printf( 0 ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a; cin >> a; long long int x = a.length(); std::vector<long long int> v; long long int c = 0; long long int d = 0; for (long long int i = 0; i < x; i++) { if (a[i] == b ) { d++; } if (a[i] == a ) { if (d > 0 && c > 0) { v.push_back(c); d = 0; c = 0; } c++; d = 0; } } if (c > 0) v.push_back(c); long long int res = 1; for (long long int i = 0; i < v.size(); i++) { res = (res * (v[i] + 1)) % 1000000007; } cout << res - 1; return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// TX_LL
//
//
// Description: The TX_LL module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_TX_LL
(
// S_AXI_TX Interface
s_axi_tx_tdata,
s_axi_tx_tlast,
s_axi_tx_tkeep,
s_axi_tx_tvalid,
s_axi_tx_tready,
// Clock Compensation Interface
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SEP,
GEN_SEP7,
SEP_NB,
TX_PE_DATA_V,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK,
RESET,
TXDATAVALID_IN
);
`define DLY #1
//***********************************Port Declarations*******************************
// S_AXI_TX Interface
input [0:63] s_axi_tx_tdata;
input s_axi_tx_tvalid;
input s_axi_tx_tlast;
input [0:7] s_axi_tx_tkeep;
output s_axi_tx_tready;
// Clock Compensation Interface
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SEP;
output GEN_SEP7;
output [0:2] SEP_NB;
output TX_PE_DATA_V;
output [0:63] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
input RESET;
input TXDATAVALID_IN;
//*********************************Wire Declarations**********************************
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL_SM and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
// TX_LL_Datapath module
aurora_64b66b_25p4G_TX_LL_DATAPATH tx_ll_datapath_i
(
// S_AXI_TX Interface
.s_axi_tx_tdata (s_axi_tx_tdata),
.s_axi_tx_tlast (s_axi_tx_tlast),
.s_axi_tx_tvalid (s_axi_tx_tvalid),
.s_axi_tx_tready (s_axi_tx_tready),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.TX_PE_DATA(TX_PE_DATA),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_64b66b_25p4G_TX_LL_CONTROL_SM tx_ll_control_sm_i
(
// S_AXI_TX Interface
.s_axi_tx_tlast (s_axi_tx_tlast),
.s_axi_tx_tkeep (s_axi_tx_tkeep),
.s_axi_tx_tvalid (s_axi_tx_tvalid),
.s_axi_tx_tready (s_axi_tx_tready),
// Clock Compensation Interface
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
// Aurora Lane Interface
.GEN_SEP(GEN_SEP),
.GEN_SEP7(GEN_SEP7),
.SEP_NB(SEP_NB),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK),
.TXDATAVALID_IN(TXDATAVALID_IN)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long int n; cin >> n; int event, police = 0, ans = 0; for (int i = 0; i < n; i++) { cin >> event; if (event == -1) { if (police == 0) ans++; else police--; } else police += event; } cout << ans; } |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: cpu_dma_queue.v
// Project: NF2.1
// Description:
// a slim CPU rx_fifo and tx_fifo connecting to the DMA interface
//
// Note that both rx_fifo and tx_fifo are first-word-fall-through FIFOs.
//
///////////////////////////////////////////////////////////////////////////////
module cpu_dma_queue
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter DMA_DATA_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter DMA_CTRL_WIDTH = DMA_DATA_WIDTH/8,
parameter TX_WATCHDOG_TIMEOUT = 125000
)
(output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- DMA rd rxfifo interface
output cpu_q_dma_pkt_avail,
input cpu_q_dma_rd,
output [DMA_DATA_WIDTH-1:0] cpu_q_dma_rd_data,
output [DMA_CTRL_WIDTH-1:0] cpu_q_dma_rd_ctrl,
// DMA wr txfifo interface
output cpu_q_dma_nearly_full,
input cpu_q_dma_wr,
input [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data,
input [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl,
// Register interface
input reg_req,
input reg_rd_wr_L,
input [`MAC_GRP_REG_ADDR_WIDTH-1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_wr_data,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_rd_data,
output reg_ack,
// --- Misc
input reset,
input clk
);
// -------- Internal parameters --------------
// ------------- Wires/reg ------------------
wire tx_timeout;
// ------------- Modules -------------------
cpu_dma_queue_main
#(
.DATA_WIDTH (DATA_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.DMA_CTRL_WIDTH (DMA_CTRL_WIDTH),
.TX_WATCHDOG_TIMEOUT (TX_WATCHDOG_TIMEOUT)
) cpu_dma_queue_main (
.out_data (out_data),
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_rdy (out_rdy),
.in_data (in_data),
.in_ctrl (in_ctrl),
.in_wr (in_wr),
.in_rdy (in_rdy),
// --- DMA rd rxfifo interface
.cpu_q_dma_pkt_avail (cpu_q_dma_pkt_avail),
.cpu_q_dma_rd (cpu_q_dma_rd),
.cpu_q_dma_rd_data (cpu_q_dma_rd_data),
.cpu_q_dma_rd_ctrl (cpu_q_dma_rd_ctrl),
// DMA wr txfifo interface
.cpu_q_dma_nearly_full (cpu_q_dma_nearly_full),
.cpu_q_dma_wr (cpu_q_dma_wr),
.cpu_q_dma_wr_data (cpu_q_dma_wr_data),
.cpu_q_dma_wr_ctrl (cpu_q_dma_wr_ctrl),
// Register interface
.tx_timeout (tx_timeout),
// --- Misc
.reset (reset),
.clk (clk)
);
cpu_dma_queue_regs
#(
.TX_WATCHDOG_TIMEOUT (TX_WATCHDOG_TIMEOUT)
) cpu_dma_queue_regs (
// Interface to "main" module
.tx_timeout (tx_timeout),
// Register interface
.reg_req (reg_req),
.reg_rd_wr_L (reg_rd_wr_L),
.reg_addr (reg_addr),
.reg_wr_data (reg_wr_data),
.reg_rd_data (reg_rd_data),
.reg_ack (reg_ack),
// --- Misc
.reset (reset),
.clk (clk)
);
// -------------- Logic --------------------
endmodule // cpu_dma_queue
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_1_V
`define SKY130_FD_SC_LP__MUX4_1_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_1_V
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module lvl2;
reg r;
time t;
event e;
integer i;
task t_my;
r = 1'b0;
endtask
function f_my;
input in;
begin
f_my = !in;
end
endfunction
initial begin: init
t_my;
r = f_my(r);
r = f_my(i);
r = f_my(t);
->e;
end
endmodule
module lvl1;
lvl2 lvl2();
endmodule
module top0;
reg r;
time t;
event e;
integer i;
task t_my;
r = 1'b0;
endtask
function f_my;
input in;
begin
f_my = !in;
end
endfunction
initial begin: init
t_my;
r = f_my(r);
r = f_my(i);
r = f_my(t);
->e;
end
lvl1 lvl1_0();
lvl1 lvl1_1();
endmodule
module top1;
initial begin: init
$test;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int pos[n + 1]; for (int i = 0; i < n; i++) { int x; cin >> x; pos[x] = i; } int curIndex = 0; for (int i = 0; i < n; i++) { int x; cin >> x; if (pos[x] < curIndex) { cout << 0 ; } else { cout << pos[x] - curIndex + 1 << ; curIndex = pos[x] + 1; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_BLACKBOX_V
`define SKY130_FD_SC_HVL__EINVN_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_BLACKBOX_V
|
module FBModule(
input clk,
input store_strb,
input [1:0] sel,
input signed[12:0] ai_in,
input signed [12:0] aq_in,
input signed [12:0] bi_in,
input signed [12:0] bq_in,
input signed [12:0] ci_in,
input signed [12:0] cq_in,
input [7:0] b1_strobe_b,
input [7:0] b2_strobe_b,
input signed [12:0] q_signal,
input delay_en,
input slow_clk,
input [6:0] bpm_lut_dinb,
input [14:0] bpm_lut_addrb,
input bpm1_i_lut_web,
input bpm1_q_lut_web,
input bpm2_i_lut_web,
input bpm2_q_lut_web,
input signed [12:0] banana_corr,
input const_dac_en,
input signed [12:0] const_dac,
input [1:0] no_bunches_b,
input [3:0] no_samples_b,
input [7:0] sample_spacing_b,
output reg [12:0] fb_sgnl,
output [6:0] bpm2_i_lut_doutb,
output [6:0] bpm2_q_lut_doutb,
output [6:0] bpm1_i_lut_doutb,
output [6:0] bpm1_q_lut_doutb,
output reg dac_cond
);
wire signed [14:0] bpm1_i_reg_int, bpm1_q_reg_int,bpm2_i_reg_int,bpm2_q_reg_int;
//reg dac_cond;
reg [1:0] no_bunches_a,no_bunches;
reg [3:0] no_samples_a, no_samples;
reg [7:0] sample_spacing_a, sample_spacing;
reg [7:0] b1_strobe_a, b1_strobe;
reg [7:0] b2_strobe_a, b2_strobe;
always @ (posedge clk) begin
no_bunches_a<=no_bunches_b;
no_bunches<=no_bunches_a;
no_samples_a<=no_samples_b;
no_samples<=no_samples_a;
sample_spacing_a<=sample_spacing_b;
sample_spacing<=sample_spacing_a;
b1_strobe_a<=b1_strobe_b;
b1_strobe<=b1_strobe_a;
b2_strobe_a<=b2_strobe_b;
b2_strobe<=b2_strobe_a;
end
//parameter NO_BUNCHES=2; // Number of bunches
//parameter NO_SAMPLES=1; // Number of samples
//parameter SAMPLE_SPACING=100; // Number of samples between consecutive bunches
Timing TimingStrobes(
.no_bunches(no_bunches),
.no_samples(no_samples),
.sample_spacing(sample_spacing),
.bunch_strb(bunch_strb),
.store_strb(store_strb),
.clk(clk),
.b1_strobe(b1_strobe), // For dipole signal
.b2_strobe(b2_strobe),
.LUTcond(LUTcond)
);
MuxModule Multiplexers(
.bunch_strb(bunch_strb),
.sel(sel),
.ai_in(ai_in),
.aq_in(aq_in),
.bi_in(bi_in),
.bq_in(bq_in),
.ci_in(ci_in),
.cq_in(cq_in),
.bpm1_q_reg_int_a(bpm1_q_reg_int),
.bpm1_i_reg_int_a(bpm1_i_reg_int),
.bpm2_q_reg_int_a(bpm2_q_reg_int),
.bpm2_i_reg_int_a(bpm2_i_reg_int),
.clk(clk), // static offset to be applied to I or Q
.dac_cond(dac_cond)
);
// ***** LUT to gain scale *****
// Read out LUT when store strobe goes low
wire signed [20:0] g1_inv_q,g2_inv_q,g3_inv_q,g4_inv_q;
////reg fb_cond;
//reg [6:0] bpm1_i_lut_dinb1, bpm1_i_lut_dinb2;
//always @ (posedge clk) begin
//bpm1_i_lut_dinb2<=bpm1_i_lut_dinb;
//bpm1_i_lut_dinb1<=bpm1_i_lut_dinb2;
//end
LUTCalc LookUpTableModule(
.clk(clk),
.slow_clk(slow_clk),
.bpm1_i_lut_dinb(bpm_lut_dinb),
.bpm1_i_lut_addrb(bpm_lut_addrb),
.bpm1_i_lut_web(bpm1_i_lut_web),
.bpm1_i_lut_doutb(bpm1_i_lut_doutb),
.bpm1_q_lut_dinb(bpm_lut_dinb),
.bpm1_q_lut_addrb(bpm_lut_addrb),
.bpm1_q_lut_web(bpm1_q_lut_web),
.bpm1_q_lut_doutb(bpm1_q_lut_doutb),
.bpm2_i_lut_dinb(bpm_lut_dinb),
.bpm2_i_lut_addrb(bpm_lut_addrb),
.bpm2_i_lut_web(bpm2_i_lut_web),
.bpm2_i_lut_doutb(bpm2_i_lut_doutb),
.bpm2_q_lut_dinb(bpm_lut_dinb),
.bpm2_q_lut_addrb(bpm_lut_addrb),
.bpm2_q_lut_web(bpm2_q_lut_web),
.bpm2_q_lut_doutb(bpm2_q_lut_doutb),
.q_signal(q_signal),
.bpm1_i_lut_out(g1_inv_q),
.bpm1_q_lut_out(g2_inv_q),
.bpm2_i_lut_out(g3_inv_q),
.bpm2_q_lut_out(g4_inv_q),
.store_strb(store_strb),
.b2_strobe(b2_strobe), // for reference signal
.LUTcond(LUTcond)
);
// ***** DSP48E modules *****
// Charge and dipole signals in
// I/q + Q/q + I/q + Q/q out
//wire signed [12:0] DSPout, DSPout2, DSPout3, DSPout4;
wire signed [12:0] pout, pout2, pout3, pout4;
//wire signed [47:0] pout_a, pout2_a, pout3_a, pout4_a;
DSPCalcModule DSPModule1(
.charge_in(g1_inv_q),
.signal_in(bpm1_i_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr),
.fb_cond(fb_cond)
);
DSPCalcModule DSPModule2(
.charge_in(g2_inv_q),
.signal_in(bpm1_q_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout2),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr)
);
DSPCalcModule DSPModule3(
.charge_in(g3_inv_q),
.signal_in(bpm2_i_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout3),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr)
);
DSPCalcModule DSPModule4(
.charge_in(g4_inv_q),
.signal_in(bpm2_q_reg_int),
.delay_en(delay_en),
.clk(clk),
.store_strb(store_strb),
.pout(pout4),
.bunch_strb(bunch_strb),
.banana_corr(banana_corr)
);
// ***** Clock DAC/Assign fb_sgnl *****
reg signed [12:0] sum1, sum2;
reg output_cond1, output_cond2;
always @ (posedge clk)begin
dac_cond<=fb_cond;
sum1<=pout+pout2;
sum2<=pout3+pout4;
output_cond1<=dac_cond & !const_dac_en;
output_cond2<=dac_cond & const_dac_en;
if (output_cond1) fb_sgnl<=sum1+sum2; // If reference not delayed by two samples then increase j accordingly
else if (output_cond2) fb_sgnl<=const_dac;
//else if (output_cond2) fb_sgnl<=const_dac;
else fb_sgnl<=0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; #define int long long #define ld long double #define ll unsigned int #define endl n #define mp make_pair #define hcf __gcd #define test cout<< hello ; #define lcm(m,n) m*(n/__gcd(m,n)) #define maxa(v) *(max_element(all(v)) #define mina(v) *(min_element(all(v)) #define pb push_back #define ppb pop_back #define pf push_front #define ppf pop_front #define ff first #define ss second #define doge cout<< * #define mod (int)1e9 #define all(x) (x).begin(),(x).end() #define uniq(v) (v).erase(unique(all(v)),(v).end()) #define sz(x) (int)((x).size()) #define asort(v) sort(v.begin(),v.end()) #define dsort(v) sort(v.begin(),v.end(),greater<int>()) #define present(c,e) (c.find(e) != c.end()) #define vfind(c,e) (find(all(c),e) != c.end()) #define tr(c,it) for(typeof(c.begin()) it = c.begin(); it != c.end(); it++) ////////////////////////////////////////////////////////////////////////////////////////////////////////// bool isPrime(ll n) { if (n <= 1) return false; if (n <= 3) return true; if (n%2 == 0 || n%3 == 0) return false; for (ll i=5; i*i<=n; i=i+6) if (n%i == 0 || n%(i+2) == 0) return false; return true; } long long power(int n,int k) { if(k==0) return 1; else return (n*power(n,k-1)%1000000007); } long long nCr(int n,int r) { if(n==r) return 1; else if (r==0) return 1; else return ((nCr(n-1,r-1)+nCr(n-1,r))%998244353); } long long sumDigit(ll x) { ll ans=0; while(x) { ans+=x%10; x/=10; } return ans;vector<int> v; } int bs(int a[],int b,int l,int r) { int mid=(l+r)/2; if(l>r) return (int)-1; if(a[mid]==b||l==r) return mid; if(a[mid]>b) return bs(a,b,l,mid-1); else return bs(a,b,mid+1,r); } int divideandconquerbc(int a[],int l,int r) { if(l>=r) return 0; int mid=(l+r)/2,ans=0; ans+=divideandconquerbc(a,l,mid); ans+=divideandconquerbc(a,mid+1,r); int x=r-l+1,y=mid-l+1; int c[x]; int i=0,j=0; for(int k=0;k<x;k++) { if((a[l+i]<=a[mid+1+j]&&i<y)||j>=x-y) {c[k]=a[l+i];i++;} else {c[k]=a[mid+1+j];j++;ans+=y-i;} } for(int k=l;k<=r;k++) a[k]=c[k-l]; return ans; } long long gcd(ll a,ll b) { if (b==0) return a; return gcd(b,a%b); } //////////////////////////////////////////////////////////////////////////////////////////////////////////////// // count sum count1, cnt,cnt1 sum1 carry tip mx mn a1 a2 a3 // may the force be with us void solve(){ int n,q; cin>>n>>q; set<int>s; map<int,int>m; for (int i = 0; i < n; ++i) { int x; cin>>x; if(!present(s,x)){ m[x]=i+1; s.insert(x); } } for (int i = 0; i < q; ++i) { int z; cin>>z; cout<<m[z]<< ; for(auto i:m){ if(i.ss<m[z]){ m[i.ff]++; } } m[z]=1; } cout<<endl;} signed main(){ ios_base::sync_with_stdio(false); cin.tie(0);cout.tie(0); #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif int tsc=1; // cin>>tsc; while(tsc--) solve(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t ();
// See also t_math_width
// This shows the uglyness in width warnings across param modules
// TODO: Would be nice to also show relevant parameter settings
p #(.WIDTH(4)) p4 (.in(4'd0));
p #(.WIDTH(5)) p5 (.in(5'd0));
//====
localparam [3:0] XS = 'hx; // User presumably intended to use 'x
//====
wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax
wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is
//====
localparam WIDTH = 6;
wire one_bit;
wire [2:0] shifter = 1;
wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
//====
// We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS
wire one = 1;
wire [2:0] cnt = (one + one + one + one);
endmodule
module p
#(parameter WIDTH=64)
(input [WIDTH-1:0] in);
wire [4:0] out = in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int l; cin >> l; string s; cin >> s; if (l < 26) { cout << NO n ; return 0; } int f[26] = {}; for (int i = 0; i < l; i++) f[tolower(s[i]) - a ]++; for (int i = 0; i < 26; i++) if (f[i] == 0) { cout << NO n ; return 0; } cout << YES n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_1_V
`define SKY130_FD_SC_HD__CLKINV_1_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_1_V
|
#include <bits/stdc++.h> using namespace std; int k; long long int m, lim = 2e18; long long int dp[70][70][2]; long long int solve(string s, int pos, int k, bool f) { if (k < 0) return 0; if (pos == (int)s.size()) { return (k == 0); } if (dp[pos][k][f] != -1) return dp[pos][k][f]; long long int ret = 0; for (char c = 0 ; c <= 1 ; ++c) { if (!f and s[pos] < c) continue; ret += solve(s, pos + 1, k - (c == 1 ), f | (s[pos] > c)); } return dp[pos][k][f] = ret; } long long int get(string s) { if (s == 1 ) { if (k == 1) return 1; else return 0; } memset(dp, -1, sizeof dp); return solve(s, 0, k, 0); } string binary(long long int num) { string ret = ; while (num) { if (num & 1) ret += 1 ; else ret += 0 ; num >>= 1LL; } reverse((ret).begin(), (ret).end()); return ret; } long long int search(long long int l, long long int r) { long long int mid = (l + r) / 2LL; long long int tot = get(binary(2 * mid)) - get(binary(mid)); if (tot == m) return mid; else if (tot < m) return search(mid + 1, r); return search(l, mid - 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); while (cin >> m >> k) { long long int ans = search(1LL, lim); cout << ans << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A211OI_BEHAVIORAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; bool con = false; for (int i = 1; i < 32000; i++) { double M = 2 * n - i * (i + 1); double k = (-1.0 + sqrtl(1 + 4 * M)) / 2.0; if (k <= 0) break; if (abs((long long int)k - k) <= 1e-9) { con = true; break; } } if (con) cout << YES ; else cout << NO ; return 0; } |
`include "macros.vh"
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Module for receiving RGB565 pixel data from OV camera.
//
//##################################################################################################
// TODO Note this module reads in raw (1 byte) data
`define NUM_LINES 480
`define PIX_PER_LINE 640
module CamReader (
input pclk, // PCLK
input rst_n, // 0 - Reset.
input [7:0] din, // D0 - D7
input vsync, // VSYNC
input href, // HREF
output pixel_valid, // Indicates that a pixel has been received.
output reg [7:0] pixel, // Raw pixel
input start, // pulse
input stop, // TODO does not do anythingh
output reg [31:0] hlen,
output reg [31:0] vlen
);
reg odd;
reg frameValid;
reg href_p1;
reg href_p2;
reg href_p3;
reg vsync_p1;
reg vsync_p2;
wire real_href;
wire real_vsync;
reg real_vsync_p1;
wire vsync_posedge;
reg running;
`REG(pclk, running, 0, start ? 1'b1 : running)
`REG(pclk, frameValid, 0, (running && !frameValid && real_vsync) ? 1'b1 : frameValid)
reg [7:0] din_p1;
reg [7:0] din_p2;
`REG(pclk, din_p1[7:0], 8'hFF, din[7:0])
`REG(pclk, din_p2[7:0], 8'hFF, din_p1[7:0])
`REG(pclk, pixel[7:0], 8'hFF, din_p2[7:0])
localparam IDLE=0, HBLANK=1, HACT=2;
reg [10:0] pix_cnt_n;
reg [10:0] pix_cnt;
reg [1:0] pix_ns;
reg [1:0] pix_cs;
assign pixel_valid = (pix_cs == HACT);
always @(*) begin
case(pix_cs)
IDLE : begin
pix_ns = frameValid ? HBLANK : IDLE;
pix_cnt_n = 0;
end
HBLANK : begin
pix_ns = real_href ? HACT : HBLANK ;
pix_cnt_n = real_href ? `PIX_PER_LINE : 0;
end
HACT : begin
pix_ns = (pix_cnt == 1) ? HBLANK : HACT ;
pix_cnt_n = pix_cnt - 1'b1;
end
default : begin
pix_ns = IDLE ;
pix_cnt_n = 0;
end
endcase
end
`REG(pclk, pix_cs, IDLE, pix_ns)
`REG(pclk, pix_cnt, 0, pix_cnt_n)
assign vsync_posedge = !real_vsync_p1 && real_vsync;
assign real_href = href && href_p1 && href_p2 && !href_p3 && !real_vsync;
assign real_vsync = vsync && vsync_p1 && vsync_p2;
`REG(pclk, href_p1, 1'b0, href)
`REG(pclk, href_p2, 1'b0, href_p1)
`REG(pclk, href_p3, 1'b0, href_p2)
`REG(pclk, vsync_p1, 1'b0, vsync)
`REG(pclk, vsync_p2, 1'b0, vsync_p1)
`REG(pclk, real_vsync_p1, 1'b0, real_vsync)
reg pixel_valid_p1;
`REG(pclk, pixel_valid_p1, 0, pixel_valid)
reg [10:0] st_pix_cnt;
`REG(pclk, st_pix_cnt, 32'h0,
pixel_valid ? (st_pix_cnt+1'b1) : 0 )
`REG(pclk, hlen, 0, (frameValid && pixel_valid_p1 && !pixel_valid && (st_pix_cnt!= 640)) ? st_pix_cnt : hlen)
reg [10:0] ln_cnt;
`REG(pclk, ln_cnt, 32'h0,
real_vsync ? 32'h0 : (pixel_valid && !pixel_valid_p1 ? ln_cnt+1'b1 : ln_cnt))
`REG(pclk, vlen, 32'h0, (vsync_posedge && (ln_cnt !=480) ) ? ln_cnt : vlen)
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:26:48 02/11/2016
// Design Name:
// Module Name: GameLoader
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Module reads bytes and writes to proper address in ram.
// Done is asserted when the whole game is loaded.
// This parses iNES headers too.
module GameLoader(input clk, input reset,
input [7:0] indata, input indata_clk,
output reg [21:0] mem_addr, output [7:0] mem_data, output mem_write,
output [31:0] mapper_flags,
output reg done,
output error);
reg [1:0] state = 0;
reg [7:0] prgsize;
reg [3:0] ctr;
reg [7:0] ines[0:15]; // 16 bytes of iNES header
reg [21:0] bytes_left;
assign error = (state == 3);
wire [7:0] prgrom = ines[4]; // Number of 16384 byte program ROM pages
wire [7:0] chrrom = ines[5]; // Number of 8192 byte character ROM pages (0 indicates CHR RAM)
wire has_chr_ram = (chrrom == 0);
assign mem_data = indata;
assign mem_write = (bytes_left != 0) && (state == 1 || state == 2) && indata_clk;
wire [2:0] prg_size = prgrom <= 1 ? 0 :
prgrom <= 2 ? 1 :
prgrom <= 4 ? 2 :
prgrom <= 8 ? 3 :
prgrom <= 16 ? 4 :
prgrom <= 32 ? 5 :
prgrom <= 64 ? 6 : 7;
wire [2:0] chr_size = chrrom <= 1 ? 0 :
chrrom <= 2 ? 1 :
chrrom <= 4 ? 2 :
chrrom <= 8 ? 3 :
chrrom <= 16 ? 4 :
chrrom <= 32 ? 5 :
chrrom <= 64 ? 6 : 7;
// detect iNES2.0 compliant header
wire is_nes20 = (ines[7][3:2] == 2'b10);
// differentiate dirty iNES1.0 headers from proper iNES2.0 ones
wire is_dirty = !is_nes20 && ((ines[8] != 0)
|| (ines[9] != 0)
|| (ines[10] != 0)
|| (ines[11] != 0)
|| (ines[12] != 0)
|| (ines[13] != 0)
|| (ines[14] != 0)
|| (ines[15] != 0));
// Read the mapper number
wire [7:0] mapper = {is_dirty ? 4'b0000 : ines[7][7:4], ines[6][7:4]};
// ines[6][0] is mirroring
// ines[6][3] is 4 screen mode
assign mapper_flags = {15'b0, ines[6][3], has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
always @(posedge clk) begin
if (reset) begin
state <= 0;
done <= 0;
ctr <= 0;
mem_addr <= 0; // Address for PRG
end else begin
case(state)
// Read 16 bytes of ines header
0: if (indata_clk) begin
ctr <= ctr + 1;
ines[ctr] <= indata;
bytes_left <= {prgrom, 14'b0};
if (ctr == 4'b1111)
// Check the 'NES' header. Also, we don't support trainers.
state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] ? 1 : 3; end
1, 2: begin // Read the next |bytes_left| bytes into |mem_addr|
if (bytes_left != 0) begin
if (indata_clk) begin
bytes_left <= bytes_left - 1;
mem_addr <= mem_addr + 1;
end
end else if (state == 1) begin
state <= 2;
mem_addr <= 22'b10_0000_0000_0000_0000_0000; // Address for CHR
bytes_left <= {1'b0, chrrom, 13'b0};
end else if (state == 2) begin
done <= 1;
end
end
endcase
end
end
endmodule
|
module top;
reg pass = 1'b1;
reg in;
wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;
initial begin
// $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
if (bf1 !== 1'bx && bf2 !== 1'bx) begin
$display("Buffer failed, expected 2'bxx, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'bx && nt2 !== 1'bx) begin
$display("Inverter (not) failed, expected 2'bxx, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b0;
#1;
if (bf1 !== 1'b0 && bf2 !== 1'b0) begin
$display("Buffer failed, expected 2'b00, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b1 && nt2 !== 1'b1) begin
$display("Inverter (not) failed, expected 2'b11, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b1;
#1;
if (bf1 !== 1'b1 && bf2 !== 1'b1) begin
$display("Buffer failed, expected 2'b11, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b0 && nt2 !== 1'b0) begin
$display("Inverter (not) failed, expected 2'b00, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
buf (bf1, bf2, in);
not (nt1, nt2, in);
pulldown (pd1, pd2);
pullup (pu1, pu2);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate defparam
module main ();
reg clock;
reg q;
reg reset;
reg error;
task task_a ;
begin
# 2;
if(reset)
q = 0;
else
q = ~q ;
end
endtask
initial
begin
// Set reset to init f/f.
error = 0;
reset = 1;
task_a ; // Same as posedge reset in previous test
#4 ;
if(q != 1'b0)
begin
$display("FAILED - disable3.6B - Flop didn't clear on clock & reset");
error = 1;
end
reset = 1'b0;
task_a ; // First clock edge from orig test
# 3;
if(q != 1'b1)
begin
$display("FAILED - disable3.6B - Flop didn't set on clock");
error = 1;
end
# 3;
fork
task_a ; // Toggle f/f clock edge
begin
# 1;
disable task_a; // And disable the toggle event
end
join
if(q != 1'b1)
begin
$display("FAILED - disable3.6B - Disable task didn't stop toggle");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; char ch = getchar(); int fh = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) fh = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= fh; } struct Onfo { int nu, ne; } a[200010 * 2]; struct Info { int x, t, we, an; } v[200010]; struct seg { int l, r, ma, ta, de; } t[200010 * 4]; int b[200010], num, m, n, x, so[200010], si[200010], d[200010], f[200010], tp[200010], bi[200010], fb[200010]; vector<int> no; bool co(const Info &a, const Info &b) { if (a.t + d[a.x] != b.t + d[b.x]) return a.t + d[a.x] < b.t + d[b.x]; return a.x < b.x; } bool c1(const Info &a, const Info &b) { return a.we < b.we; } void jb(int x, int y) { a[++num].nu = y; a[num].ne = b[x]; b[x] = num; } void dfs(int x, int fa, int dep) { si[x] = 1; so[x] = 0; f[x] = fa; d[x] = dep; for (int y = b[x]; y; y = a[y].ne) { if (a[y].nu != fa) { dfs(a[y].nu, x, dep + 1); si[x] += si[a[y].nu]; if (si[a[y].nu] > si[so[x]]) so[x] = a[y].nu; } } } void dfs1(int x) { bi[x] = ++num; fb[num] = x; if (so[x] != 0) { tp[so[x]] = tp[x]; dfs1(so[x]); } for (int y = b[x]; y; y = a[y].ne) { if (a[y].nu != f[x] && a[y].nu != so[x]) { tp[a[y].nu] = a[y].nu; dfs1(a[y].nu); } } } void build(int nu, int l, int r) { t[nu].ma = -2e9; t[nu].l = l; t[nu].r = r; t[nu].ta = -2e9; if (l != r) { build(nu * 2, l, (l + r) / 2); build(nu * 2 + 1, (l + r) / 2 + 1, r); t[nu].de = t[nu * 2 + 1].de; } else { t[nu].de = d[fb[l]]; } } void ya(int nu) { if (t[nu].ta != -2e9) { if (t[nu].l != t[nu].r) { t[nu * 2].ta = t[nu].ta; t[nu * 2 + 1].ta = t[nu].ta; } t[nu].ma = t[nu].ta + t[nu].de * 2; t[nu].ta = -2e9; } } int que(int nu, int l, int r) { ya(nu); if (t[nu].l == l && t[nu].r == r) return t[nu].ma; int mid = (t[nu].l + t[nu].r) / 2; if (l > mid) return que(nu * 2 + 1, l, r); if (r <= mid) return que(nu * 2, l, r); return max(que(nu * 2, l, mid), que(nu * 2 + 1, mid + 1, r)); } void get(int nu, int l, int r) { ya(nu); if (t[nu].l == l && t[nu].r == r) { no.push_back(nu); return; } int mid = (t[nu].l + t[nu].r) / 2; if (l <= mid) get(nu * 2, l, min(mid, r)); if (r > mid) get(nu * 2 + 1, max(mid + 1, l), r); } int getans(int nu, int y) { if (t[nu].l == t[nu].r) return fb[t[nu].l]; ya(nu * 2 + 1); if (t[nu * 2 + 1].ma <= y) return getans(nu * 2, y); return getans(nu * 2 + 1, y); } int get(int x, int y) { while (x != 0) { if (que(1, bi[tp[x]], bi[x]) > y) { no.clear(); get(1, bi[tp[x]], bi[x]); for (int i = no.size() - 1; i >= 0; i--) { if (t[no[i]].ma > y) return getans(no[i], y); } } x = f[tp[x]]; } return x; } void add(int nu, int l, int r, int x) { ya(nu); if (t[nu].l == l && t[nu].r == r) { t[nu].ta = x; return; } int mid = (t[nu].l + t[nu].r) / 2; if (l <= mid) add(nu * 2, l, min(mid, r), x); if (r > mid) add(nu * 2 + 1, max(mid + 1, l), r, x); ya(nu * 2); ya(nu * 2 + 1); t[nu].ma = max(t[nu * 2].ma, t[nu * 2 + 1].ma); } void fu(int x, int y, int z) { while (tp[x] != tp[y]) { add(1, bi[tp[x]], bi[x], z); x = f[tp[x]]; } if (x != y) add(1, bi[y] + 1, bi[x], z); } int main() { read(n); read(m); for (int i = 1; i <= n; i++) { read(x); jb(x + 1, i + 1); jb(i + 1, x + 1); } n++; dfs(1, 0, 1); num = 0; tp[1] = 1; dfs1(1); build(1, 1, n); add(1, 1, 1, 2e9); for (int i = 1; i <= m; i++) { read(v[i].x); read(v[i].t); v[i].x++; v[i].we = i; } sort(v + 1, v + m + 1, co); for (int i = 1; i <= m; i++) { v[i].an = get(v[i].x, v[i].t + d[v[i].x]); fu(v[i].x, v[i].an, v[i].t + d[v[i].x] - d[v[i].an] * 2); } sort(v + 1, v + m + 1, c1); for (int i = 1; i <= m; i++) printf( %d , v[i].t + d[v[i].x] * 2 - d[v[i].an] * 2); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long ans = 0; int n, m, k = 0; scanf( %d %d , &n, &m); vector<int> v(1e7); for (int i = 0; i < n; i++) { scanf( %d , &k); ans += v[(k ^ m)]; v[k]++; } printf( %I64d , ans); } |
#include <bits/stdc++.h> using namespace std; struct dd { int k1; char k2; } a[25000]; bool cmp(struct dd q, struct dd b) { return q.k1 > b.k1; } int main() { int i, j, m, n, sum; char b[1000]; gets(b); sum = 0; char k = a ; scanf( %d , &m); for (i = 0; i < 26; i++) { scanf( %d , &a[i].k1); a[i].k2 = k; k++; } int len1 = strlen(b); for (i = 0; i < len1; i++) { sum += a[(int)b[i] - 97].k1 * (i + 1); } sort(a, a + 26, cmp); for (i = len1; i < len1 + m; i++) { sum += a[0].k1 * (i + 1); } printf( %d n , sum); } |
#include <bits/stdc++.h> using namespace std; set<string> S; string line[1010], a[1010], s; int n = 0, ans = 0, file = 0; int main() { while (getline(cin, s)) line[++n] = s; for (int i = 1; i <= n; i++) { int cur = 0; a[i] = ; for (int j = 0; j < line[i].size(); j++) { a[i] += line[i][j]; if (line[i][j] == ) cur++; if (cur == 2) break; } } for (int i = 1; i <= n; i++) { string fd = a[i]; S.clear(); int files = 0, F = 0; for (int j = 1; j <= n; j++) if (a[j] == fd) { files++; string v = ; int cur = 0; for (int k = 0; k < line[j].size(); k++) { v += line[j][k]; if (line[j][k] == ) cur++; if (line[j][k] == && cur > 2) if (!S.count(v)) S.insert(v), F++; } } ans = max(ans, F); file = max(file, files); } cout << ans << << file << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a; long long x[] = { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8092, 16184, 32368, 64736, 129472, 258944, 517888, 1035776, 2071552, 4143104, 8286208, 16572416, 33144832, 66289664, 132579328, 265158656, 530317312, 1060634624, 2121269248, 4242538496, 8485076992, 16970153984, 33940307968}; cin >> a; cout << x[a] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_4_V
`define SKY130_FD_SC_HS__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_4_V
|
#include <bits/stdc++.h> using namespace std; const int MX = 1234567; const double PI = acos(-1.0), EPS = 1e-9; long long N, arr[MX]; long long gcd(long long a, long long b) { while (a > 0 && b > 0) { if (a > b) a %= b; else b %= a; } return a + b; } int main() { cin >> N; long long g = 0; for (int i = 0; i < N; i++) cin >> arr[i]; for (int i = 0; i < N; i++) { g = gcd(g, arr[i]); } if (g != 1) { cout << YES n ; cout << 0 << n ; return 0; } int oper = 0; for (int i = 0; i < N; i++) { if (arr[i] % 2 && arr[i + 1] % 2) { i++; oper++; } else if (arr[i] % 2 && arr[i + 1] % 2 == 0) { i++; oper += 2; } } cout << YES n ; cout << oper << n ; return 0; } |
// wasca_mm_interconnect_0_avalon_st_adapter_004.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0_avalon_st_adapter_004 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int c[105], sum[105]; pair<int, int> p[105]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &c[i]); sum[i] = sum[i - 1] + c[i]; } int st = 1, tot = 0; for (int i = 1; i <= n; i++) { if (sum[i] - sum[st - 1] < 0 && (c[i + 1] > 0 || i == n)) p[++tot].first = st, p[tot].second = i, st = i + 1; else if (sum[i] - sum[st - 1] > 0 && (c[i + 1] < 0 || i == n)) p[++tot].first = st, p[tot].second = i, st = i + 1; } if (st != n + 1) printf( NO ); else { printf( YES n%d n , tot); for (int i = 1; i <= tot; i++) printf( %d %d n , p[i].first, p[i].second); } } |
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); double d, h, v, e; scanf( %lf%lf%lf%lf , &d, &h, &v, &e); if (v / (d * d * 3.1415926 / 4) > e) { printf( YES n%.10f , h / (v / (d * d * 3.1415926 / 4) - e)); } else cout << NO << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string p( / ), t; while (n--) { string foo; cin >> foo; if (foo == pwd ) { cout << p << endl; } else { string dir; cin >> dir; dir += / ; for (int i = 0; i < dir.length(); i++) { t += dir[i]; if (dir[i] == / ) { if (t == / ) p = t; else if (t == ../ ) { for (int j = p.length() - 1; j > 0 && p[j - 1] != / ; j--) { p.resize(j - 1); } } else p += t; t = ; } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } char s[500010]; int l[12], r[12]; int sz, ed; int cnt[500010], ord[500010 << 1]; struct node { int deep, fail, cnt, nxt[30], val[12]; void clear() { memset(nxt, -1, sizeof nxt); memset(val, 0, sizeof val); deep = fail = cnt = 0; } } mem[500010 << 1]; struct automaton { void init() { for (int i = 0; i < 26; i++) mem[0].nxt[i] = 1; mem[0].deep = -1; mem[1].clear(); mem[1].cnt = 1; sz = 2, ed = 1; } void insert(int c, int id) { if (~mem[ed].nxt[c]) { int p1 = mem[ed].nxt[c]; if (mem[p1].deep == mem[ed].deep + 1) { mem[p1].val[id]++; ed = p1; return; } int p2 = sz++; mem[p2] = mem[p1]; mem[p2].deep = mem[ed].deep + 1; mem[p2].cnt = 0; for (int i = 0; i < 12; i++) mem[p2].val[i] = 0; mem[p2].val[id] = 1; mem[p1].fail = p2; while (mem[ed].nxt[c] == p1) { mem[ed].nxt[c] = p2; mem[p1].cnt -= mem[ed].cnt; mem[p2].cnt += mem[ed].cnt; ed = mem[ed].fail; } ed = p2; return; } int p = sz++; mem[p].clear(); mem[p].deep = mem[ed].deep + 1; mem[p].val[id] = 1; while (mem[ed].nxt[c] == -1) { mem[ed].nxt[c] = p; mem[p].cnt += mem[ed].cnt; ed = mem[ed].fail; } int p1 = mem[ed].nxt[c]; if (mem[p1].deep == mem[ed].deep + 1) mem[p].fail = p1; else { int p2 = sz++; mem[p2] = mem[p1]; mem[p2].deep = mem[ed].deep + 1; mem[p2].cnt = 0; for (int i = 0; i < 12; i++) mem[p2].val[i] = 0; mem[p].fail = mem[p1].fail = p2; while (mem[ed].nxt[c] == p1) { mem[ed].nxt[c] = p2; mem[p1].cnt -= mem[ed].cnt; mem[p2].cnt += mem[ed].cnt; ed = mem[ed].fail; } } ed = p; } void build(int n) { memset(cnt, 0, sizeof cnt); for (int i = 1; i < sz; i++) cnt[mem[i].deep]++; for (int i = 1; i < 500010; i++) cnt[i] += cnt[i - 1]; for (int i = 1; i < sz; i++) ord[--cnt[mem[i].deep]] = i; for (int i = sz - 2; i >= 0; i--) { int cur = ord[i], prv = mem[cur].fail; for (int j = 0; j <= n; j++) mem[prv].val[j] += mem[cur].val[j]; } long long ans = 0; for (int i = 2; i < sz; i++) if (mem[i].val[n]) { int ok = 1; for (int j = 0; j < n; j++) if (mem[i].val[j] < l[j] || mem[i].val[j] > r[j]) { ok = 0; break; } if (ok) ans += mem[i].cnt; } printf( %I64d n , ans); } } sam; int main() { int n; scanf( %s %d , s, &n); sam.init(); int len = strlen(s); for (int i = 0; i < len; i++) sam.insert(s[i] - a , n); for (int i = 0; i < n; i++) { scanf( %s %d %d , s, l + i, r + i); ed = 1; len = strlen(s); for (int j = 0; j < len; j++) sam.insert(s[j] - a , i); } sam.build(n); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_SYMBOL_V
`define SKY130_FD_SC_HD__NOR3B_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_SYMBOL_V
|
module memory_tb;
// Constants
parameter data_width = 32;
parameter address_width = 32;
parameter depth = ;
parameter bytes_in_word = 4-1; // -1 for 0 based indexed
parameter bits_in_bytes = 8-1; // -1 for 0 based indexed
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
reg clock;
reg [address_width-1:0] address;
reg [data_width-1:0] data_in;
reg [1:0] access_size;
reg rw;
reg enable;
// Output Ports
wire busy;
wire [data_width-1:0] data_out;
// fileIO stuff
integer fd;
integer scan_fd;
integer status_read, status_write;
integer sscanf_ret;
integer words_read;
integer words_written;
reg [31:0] line;
reg [31:0] data_read;
// Instantiate the memory
memory M0 (
.clock (clock),
.address (address),
.data_in (data_in),
.access_size (access_size),
.rw (rw),
.enable (enable),
.busy (busy),
.data_out (data_out)
);
/*
Mapping for access size:
00: 1 word (4-bytes)
01: 4 words (16-bytes)
10: 8 words (32-bytes)
11: 16 words (64-bytes)
*/
initial begin
fd = $fopen("SumArray.x", "r");
if (!fd)
$display("Could not open");
clock = 0;
address = start_addr;
scan_fd = $fscanf(fd, "%x", data_in);
//data_in = 0;
access_size = 2'b0_0;
enable = 1;
rw = 0; // Start writing first.
words_read = 0;
words_written = 1;
end
always @(posedge clock) begin
if (rw == 0) begin
enable = 1;
//rw = 0;
scan_fd = $fscanf(fd, "%x", line);
if (!$feof(fd)) begin
data_in = line;
$display("line = %x", data_in);
address = address + 4;
words_written = words_written + 1;
end
else begin
rw = 1;
address = 32'h80020000;
end
end
else if ($feof(fd) && (words_read < words_written)) begin
// done writing, now read...
rw = 1;
enable = 1;
data_read = data_out;
$display("data_read = %x", data_read);
address = address + 4;
words_read = words_read + 1;
end
else if (words_read >= words_written) begin
// TODO: Add logic to end simulation.
end
end
always
#5 clock = ! clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 810000; inline long long read() { long long s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + (ch ^ 48), ch = getchar(); return s * w; } long long n; struct segg { long long son[N][2], siz[N], cnt = 0, val[N], rd[N], root, x, y, z, sum[N]; inline long long New_Node(long long x) { cnt++; val[cnt] = sum[cnt] = x; siz[cnt] = 1; rd[cnt] = rand(); return cnt; } inline void UpDate(long long x) { siz[x] = siz[son[x][0]] + siz[son[x][1]] + 1; sum[x] = sum[son[x][0]] + sum[son[x][1]] + val[x]; } void Split(long long root, long long k, long long &x, long long &y) { if (!root) x = y = 0; else { if (val[root] > k) { y = root; Split(son[root][0], k, x, son[root][0]); } else { x = root; Split(son[root][1], k, son[root][1], y); } UpDate(root); } } long long Merge(long long x, long long y) { if (!x || !y) return x + y; if (rd[x] < rd[y]) { son[x][1] = Merge(son[x][1], y); UpDate(x); return x; } else { son[y][0] = Merge(x, son[y][0]); UpDate(y); return y; } } void Insert(long long s) { Split(root, s, x, y); root = Merge(Merge(x, New_Node(s)), y); } void Delete(long long s) { Split(root, s, x, z); Split(x, s - 1, x, y); y = Merge(son[y][0], son[y][1]); root = Merge(Merge(x, y), z); } void Rankdx(long long s) { Split(root, s - 1, x, y); printf( %lld n , siz[x] + 1); root = Merge(x, y); } long long dk(long long root, long long k) { while (1) { if (siz[son[root][0]] >= k) root = son[root][0]; else if (siz[son[root][0]] == k - 1) return val[root]; else k -= siz[son[root][0]] + 1, root = son[root][1]; } } void Findkx(long long s) { printf( %lld n , val[dk(root, s)]); } void Findqq(long long s) { Split(root, s - 1, x, y); printf( %lld n , val[dk(x, siz[x])]); root = Merge(x, y); } void Findhz(long long s) { Split(root, s, x, y); printf( %lld n , val[dk(y, 1)]); root = Merge(x, y); } long long FindS(long long x, long long p) { if (!p) return 0; long long qwq = 0; while (1) { if (p == siz[son[x][0]] + 1) return qwq + sum[son[x][0]] + val[x]; if (p <= siz[son[x][0]]) x = son[x][0]; else qwq += sum[son[x][0]] + val[x], p = p - siz[son[x][0]] - 1, x = son[x][1]; } } } A, B; signed main() { srand((unsigned)time(NULL)); n = read(); for (register long long i = 1; i <= n; i++) { long long opt = read(), x = read(); if (!opt) { if (x > 0) A.Insert(-x); else A.Delete(x); } if (x > 0) B.Insert(-x); else B.Delete(x); long long qwq = B.sum[B.root]; long long res = B.siz[B.root] - A.siz[A.root]; if (!res) { printf( %lld n , -qwq); continue; } if (B.dk(B.root, res) < A.dk(A.root, 1)) printf( %lld n , -qwq - A.dk(A.root, 1) - B.FindS(B.root, res - 1)); else printf( %lld n , -qwq - B.FindS(B.root, res)); } return 0; } |
/*
File: synchronizer.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module synchronizer #(parameter DW=32) (/*AUTOARG*/
// Outputs
out,
// Inputs
in, clk, reset
);
//Input Side
input [DW-1:0] in;
input clk;
input reset;//asynchronous signal
//Output Side
output [DW-1:0] out;
reg [DW-1:0] sync_reg0;
reg [DW-1:0] sync_reg1;
reg [DW-1:0] out;
//Synchronization between clock domain
//We use two flip-flops for metastability improvement
always @ (posedge clk or posedge reset)
if(reset)
begin
sync_reg0[DW-1:0] <= {(DW){1'b0}};
sync_reg1[DW-1:0] <= {(DW){1'b0}};
out[DW-1:0] <= {(DW){1'b0}};
end
else
begin
sync_reg0[DW-1:0] <= in[DW-1:0];
sync_reg1[DW-1:0] <= sync_reg0[DW-1:0];
out[DW-1:0] <= sync_reg1[DW-1:0];
end
endmodule // clock_synchronizer
|
//i2s_controllerv
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "project_defines.v"
`include "i2s_defines.v"
`timescale 1 ns/1 ps
module i2s_controller (
input rst,
input clk,
input enable,
input post_fifo_wave_en,
input [31:0] clock_divider,
//memory interface
output [23:0] wfifo_size,
output [1:0] wfifo_ready,
input [1:0] wfifo_activate,
input wfifo_strobe,
input [31:0] wfifo_data,
output reg i2s_mclock,
output reg i2s_clock,
output i2s_data,
output i2s_lr
);
`define DEFAULT_MCLOCK_DIVISOR `CLOCK_RATE / (`AUDIO_RATE) / 256
//registers/wires
reg [31:0] clock_count = 0;
reg [31:0] mclock_count = 0;
wire audio_data_request;
wire audio_data_ack;
wire [23:0] audio_data;
wire audio_lr_bit;
//sub modules
i2s_mem_controller mcontroller (
.rst (rst ),
.clk (clk ),
//control
.enable (enable ),
.post_fifo_wave_en (post_fifo_wave_en ),
//clock
.i2s_clock (i2s_clock ),
.wfifo_size (wfifo_size ),
.wfifo_ready (wfifo_ready ),
.wfifo_activate (wfifo_activate ),
.wfifo_strobe (wfifo_strobe ),
.wfifo_data (wfifo_data ),
//i2s writer
.audio_data_request (audio_data_request ),
.audio_data_ack (audio_data_ack ),
.audio_data (audio_data ),
.audio_lr_bit (audio_lr_bit )
);
i2s_writer writer (
.rst (rst ),
.clk (clk ),
//control/clock
.enable (enable ),
.starved (starved ),
//i2s clock
.i2s_clock (i2s_clock ),
//i2s writer
.audio_data_request (audio_data_request ),
.audio_data_ack (audio_data_ack ),
.audio_data (audio_data ),
.audio_lr_bit (audio_lr_bit ),
//i2s audio interface
.i2s_data (i2s_data ),
.i2s_lr (i2s_lr )
);
//asynchronous logic
//`define DEFAULT_MCLOCK_DIVISOR (`CLOCK_RATE / (`AUDIO_RATE * 256)) / 2
`define DEFAULT_MCLOCK_DIVISOR 1
//synchronous logic
//clock generator
always @(posedge clk) begin
if (rst) begin
i2s_clock <= 0;
clock_count <= 0;
end
if (clock_count >= clock_divider) begin
i2s_clock <= ~i2s_clock;
clock_count <= 0;
end
else begin
clock_count <= clock_count + 1;
end
end
always @(posedge clk) begin
if (mclock_count >= `DEFAULT_MCLOCK_DIVISOR) begin
i2s_mclock <= ~i2s_mclock;
mclock_count <= 0;
end
else begin
mclock_count <= mclock_count + 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DFSBP_FUNCTIONAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_s_pg/sky130_fd_sc_hs__u_df_p_s_pg.v"
`celldefine
module sky130_fd_sc_hs__dfsbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , D, CLK, SET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, potezi = 1, bodovi = 0; scanf( %d , &n); pair<int, int> a[n]; for (int i = 0; i < n; i++) { scanf( %d %d , &a[i].second, &a[i].first); } sort(a, a + n); for (int i = n - 1; i >= 0; i--) { if (!potezi) break; potezi += a[i].first - 1; bodovi += a[i].second; } printf( %d n , bodovi); return 0; } |
#include <bits/stdc++.h> using namespace std; long long getmax(long long arr[]) { long long m = 0; for (long long i = 0; i < 26; i++) { m = max(m, arr[i]); } return m; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; string arr[n]; long long alpha[26]; long long res = 0; for (long long i = 0; i < n; i++) cin >> arr[i]; long long marks[m]; for (long long i = 0; i < m; i++) cin >> marks[i]; for (long long i = 0; i < m; i++) { memset(alpha, 0, sizeof(alpha)); for (long long j = 0; j < n; j++) { int k = arr[j][i] - A ; alpha[k]++; } long long c = getmax(alpha); res += c * marks[i]; } cout << res << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e6 + 10; int n, k, count1; int a[MAX]; int res = 1e19 + 10; int binary_search1(int x, int l, int r) { int res = 0; while (l <= r) { int mid = (l + r) >> 1; if (a[mid] <= x) { res = mid; l = mid + 1; } else r = mid - 1; } return res; } int binary_search2(int x, int l, int r) { int res = 0; while (l <= r) { int mid = (l + r) >> 1; if (a[mid] < x) { l = mid + 1; } else { res = mid; r = mid - 1; } } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; scanf( %d %d n , &n, &k); count1 = 0; for (int i = 1; i <= n; i++) { char s; scanf( %c , &s); if (s == 0 ) { a[++count1] = i; } } sort(a + 1, a + 1 + count1); k += 1; for (int i = 1; i <= count1 - k + 1; i++) { int l = i; int r = k + i - 1; int pos1 = binary_search1((a[l] + a[r]) >> 1, l, r); int pos2 = binary_search2((a[l] + a[r]) >> 1, l, r); if (pos1 != 0) { res = min(res, max(a[pos1] - a[l], a[r] - a[pos1])); } if (pos2 != 0) { res = min(res, max(a[pos2] - a[l], a[r] - a[pos2])); } } printf( %d , res); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int a[110]; long long calc(long long first) { if (first == 0) return 0; int nn = 0; while (first) { a[nn++] = first % 2; first /= 2; } reverse(a, a + nn); int r = 0, ans = 0; for (int i = 0; i < nn; i++) if (!a[i]) r++; if (r == 1) ans++; r = 0; a[nn] = 0; for (int i = 0; i <= nn; i++) if (a[i] == 0) { r = i; break; } ans += r - 1; for (int i = 1; i < nn - 1; i++) ans += i; return ans; } int main() { long long first, second; scanf( %I64d %I64d , &first, &second); printf( %I64d n , calc(second) - calc(first - 1)); } |
#include <bits/stdc++.h> using namespace std; const int N = 100010; long long f[N]; const int mod = 1000000007; int main() { string s; cin >> s; s += , ; long long ans = 1; int l = s.size(); f[0] = 1, f[1] = 1, f[2] = 2; for (int i = 3; i <= l; i++) f[i] = (f[i - 1] + f[i - 2]) % mod; long long now = 0, nn = -1; int c = 1; for (int i = 0; i < l; i++) { if (s[i] == m || s[i] == w ) { c = 0; break; } if (s[i] == u ) { if (nn == 1) now++; else { ans = ans * f[now] % mod; now = 1, nn = 1; } } else if (s[i] == n ) { if (nn == 2) now++; else { ans = ans * f[now] % mod; now = 1, nn = 2; } } else { ans = ans * f[now] % mod; now = 0, nn = -1; } } if (c == 0) cout << 0 n ; else cout << ans % mod << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int Mod = 1e9 + 7; int main() { long long N, M, ans = 0, Last = 0; scanf( %I64d%I64d , &N, &M); long long Min = min(N, M); for (long long i = 1, j; i <= Min; i = j + 1) { j = min(N / (N / i), M); long long tmp; if (j & 1LL) tmp = ((j + 1) / 2 % Mod) * (j % Mod) % Mod; else tmp = (j / 2 % Mod) * ((j + 1) % Mod) % Mod; ans = (ans + (N / i) % Mod * (((tmp - Last) % Mod + Mod) % Mod) % Mod) % Mod; Last = tmp; } ans = (((N % Mod) * (M % Mod) - ans) % Mod + Mod) % Mod; printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int getsum(string st) { int rest = 0; for (int i = 0; i < st.size(); i++) { rest += st[i] - 0 ; } return rest; } string streverse(string st) { for (int i = 0; i < st.size() / 2; i++) { char tmp = st[i]; st[i] = st[st.size() - 1 - i]; st[st.size() - 1 - i] = tmp; } return st; } string getGreater(int a, int num, string st) { int increase = a - num; for (int i = st.size() - 1; i >= 0; i--) { if (st[i] - 0 < 9) { int increment = min(9 - (st[i] - 0 ), increase); st[i] += increment; increase -= increment; } if (increase == 0) return st; } string rest = ; for (int i = 0; i < a / 9; i++) rest = rest + 9 ; if (a % 9 > 0) { rest = rest + (char)( 0 + a % 9); } return streverse(rest); } string getLess(int a, int num, string st) { int decrease = num - a; decrease++; int sum = 0; for (int i = st.size() - 1; i >= 1; i--) { sum += st[i] - 0 ; if (sum >= decrease) { if (st[i - 1] - 0 < 9) { st[i - 1]++; sum = sum - decrease; for (int j = i; j < st.size(); j++) st[j] = 0 ; int indx = st.size() - 1; while (sum > 0) { if (sum > 9) { st[indx] += 9; sum -= 9; } else { st[indx] += sum; sum = 0; } indx--; } return st; } } } st = 1 + st; for (int i = 1; i < st.size(); i++) { st[i] = 0 ; } a--; int k; for (k = 0; k < a / 9; k++) { st[st.size() - 1 - k] = 9 ; } if (a % 9) { for (int i = st.size() - 1; i >= 0; i--) { if (st[i] == 0 ) { st[i] = (char)( 0 + a % 9); break; } } } return st; } string getnum(int a, string st) { int num = getsum(st); if (a > num) { return getGreater(a, num, st); } return getLess(a, num, st); } int main() { getnum(13, 1093 ); int n; cin >> n; string pre = ; for (int i = 0; i < n; i++) { int a; cin >> a; string rest = getnum(a, pre); cout << rest << endl; pre = rest; } return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file obc_upper.v when simulating
// the core, obc_upper. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module obc_upper(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [7 : 0] addra;
input [1 : 0] dina;
output [1 : 0] douta;
input clkb;
input [0 : 0] web;
input [5 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(6),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(64),
.C_READ_WIDTH_A(2),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(64),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(2),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_TB_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_TB_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv5sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkdlyinv5sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long int inf = 1000000000000000; string s; vector<long long> prim; set<long long> prim2; void primeFactors(int n) { while (n % 2 == 0) { prim.push_back(2); prim2.insert(2); n = n / 2; } for (int i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { prim.push_back(i); prim2.insert(i); n = n / i; } } if (n > 2) { prim.push_back(n); prim2.insert(n); } } long long dp[3001][3001]; long long n; pair<long long, long long> arr[4000]; long long get_ans(long long i, long long prev) { if (i > n) { return 0; } if (dp[i][prev] != -inf) return dp[i][prev]; long long x = 0, y = 0; x = get_ans(i + 1, i) + arr[i].second; y = abs(arr[prev].first - arr[i].first) + get_ans(i + 1, prev); return dp[i][prev] = min(x, y); } void func() { cin >> n; for (int i = 1; i <= n; i++) { long long a, b; cin >> a >> b; arr[i] = {a, b}; } sort(arr + 1, arr + n + 1); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dp[i][j] = -inf; } } cout << get_ans(2, 1) + arr[1].second << n ; } int main() { { ios ::sync_with_stdio(false); cin.tie(0); cout.tie(0); } { func(); } return 0; } |
#include <bits/stdc++.h> const long long N = 50050; const long long Q = 2e18; const long long mod = 1e9 + 7; const long long MAGIC = 30; using namespace std; int a, b, c, n; void solve() { cin >> a >> b >> c >> n; if (a + b - c >= n || c > a || c > b) { cout << -1 << n ; } else { cout << n - (a + b - c) << n ; } } bool mtest = false; int main() { ios_base::sync_with_stdio(0); int TE = 1; if (mtest) cin >> TE; while (TE--) solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_4_V
`define SKY130_FD_SC_HS__DLCLKP_4_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlclkp_4 (
GCLK,
GATE,
CLK ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlclkp_4 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_4_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module mdc_mdio (
mdio_mdc,
mdio_in_w,
mdio_in_r,
speed_select,
duplex_mode);
parameter PHY_AD = 5'b10000;
input mdio_mdc;
input mdio_in_w;
input mdio_in_r;
output [ 1:0] speed_select;
output duplex_mode;
localparam IDLE = 2'b01;
localparam ACQUIRE = 2'b10;
wire preamble;
reg [ 1:0] current_state = IDLE;
reg [ 1:0] next_state = IDLE;
reg [31:0] data_in = 32'h0;
reg [31:0] data_in_r = 32'h0;
reg [ 5:0] data_counter = 6'h0;
reg [ 1:0] speed_select = 2'h0;
reg duplex_mode = 1'h0;
assign preamble = &data_in;
always @(posedge mdio_mdc) begin
current_state <= next_state;
data_in <= {data_in[30:0], mdio_in_w};
if (current_state == ACQUIRE) begin
data_counter <= data_counter + 1;
end else begin
data_counter <= 0;
end
if (data_counter == 6'h1f) begin
if (data_in[31] == 1'b0 && data_in[29:28]==2'b10 && data_in[27:23] == PHY_AD && data_in[22:18] == 5'h11) begin
speed_select <= data_in_r[16:15] ;
duplex_mode <= data_in_r[14];
end
end
end
always @(negedge mdio_mdc) begin
data_in_r <= {data_in_r[30:0], mdio_in_r};
end
always @(*) begin
case (current_state)
IDLE: begin
if (preamble == 1 && mdio_in_w == 0) begin
next_state <= ACQUIRE;
end else begin
next_state <= IDLE;
end
end
ACQUIRE: begin
if (data_counter == 6'h1f) begin
next_state <= IDLE;
end else begin
next_state <= ACQUIRE;
end
end
default: begin
next_state <= IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y, dist1, dist2; char ch[3], a; ch[0] = getchar(); a = getchar(); ch[2] = getchar(); cin >> n; n = n % 4; if (n == 1 && ((ch[0] == ^ && ch[2] == > ) || (ch[0] == > && ch[2] == v ) || (ch[0] == v && ch[2] == < ) || (ch[0] == < && ch[2] == ^ ))) cout << cw ; else if (n == 1 && ((ch[0] == ^ && ch[2] == < ) || (ch[0] == < && ch[2] == v ) || (ch[0] == v && ch[2] == > ) || (ch[0] == > && ch[2] == ^ ))) cout << ccw ; else if (n == 3 && ((ch[0] == ^ && ch[2] == < ) || (ch[0] == > && ch[2] == ^ ) || (ch[0] == v && ch[2] == > ) || (ch[0] == < && ch[2] == v ))) cout << cw ; else if (n == 3 && ((ch[0] == ^ && ch[2] == > ) || (ch[0] == < && ch[2] == ^ ) || (ch[0] == v && ch[2] == < ) || (ch[0] == > && ch[2] == v ))) cout << ccw ; else cout << undefined ; } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void pre() {} long long a[200009]; long long n, p, k; long long dp[200009]; void solve() { cin >> n >> p >> k; for (int i = 0; i < (n); ++i) cin >> a[i + 1], dp[i] = -1; sort(a + 1, a + n + 1); dp[0] = 0; long long ans = 0; for (int i = 1; i <= (n); ++i) { if (i >= k) dp[i] = min(dp[i - 1], dp[i - k]) + a[i]; else dp[i] = dp[i - 1] + a[i]; if (dp[i] <= p) ans = i; } cout << ans << n ; } int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); pre(); int t; cin >> t; for (int i = 0; i < (t); ++i) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; struct Q { int r1, r2, c1, c2, idx; }; int n, m, k, q; Q qs[200001]; vector<int> qAtRow[100001]; vector<int> qAtCol[100001]; vector<int> atCol[100001]; vector<int> atRow[100001]; bool must[200000]; bool res[200000]; int v[100001]; int Z = 400001; int seg[400001]; int at, val; void update(int n, int s, int e) { if (at < s || at > e) return; if (s == e) { if (seg[n] == (1 << 29)) seg[n] = val; else seg[n] = val; return; } update(n * 2, s, (s + e) / 2); update(n * 2 + 1, (s + e) / 2 + 1, e); seg[n] = max(seg[n * 2], seg[n * 2 + 1]); } int l, r; int get(int n, int s, int e) { if (l > e || r < s) return -1; if (s >= l && e <= r) return seg[n]; return max(get(n * 2, s, (s + e) / 2), get(n * 2 + 1, (s + e) / 2 + 1, e)); } int main() { scanf( %d%d%d%d , &n, &m, &k, &q); for (int i = 0; i < k; ++i) { int r, c; scanf( %d%d , &r, &c); atCol[c].push_back(r); atRow[r].push_back(c); } for (int i = 0; i < q; ++i) { Q &t = qs[i]; scanf( %d%d%d%d , &t.r1, &t.c1, &t.r2, &t.c2); t.idx = i; qAtCol[t.c1].push_back(i); qAtRow[t.r1].push_back(i); } for (int i = 0; i < Z; ++i) seg[i] = 1 << 29; for (int i = n; i > 0; --i) { for (int j = 0; j < atRow[i].size(); ++j) { at = atRow[i][j]; val = i; update(1, 1, m); } for (int j = 0; j < qAtRow[i].size(); ++j) { Q &t = qs[qAtRow[i][j]]; l = t.c1; r = t.c2; int a = get(1, 1, m); if (a <= 0 || a > t.r2) must[t.idx] = true; } } for (int i = 0; i < Z; ++i) seg[i] = 1 << 29; for (int i = m; i > 0; --i) { for (int j = 0; j < atCol[i].size(); ++j) { at = atCol[i][j]; val = i; update(1, 1, n); } for (int j = 0; j < qAtCol[i].size(); ++j) { Q &t = qs[qAtCol[i][j]]; l = t.r1; r = t.r2; int a = get(1, 1, n); if (must[t.idx] && (a <= 0 || a > t.c2)) res[t.idx] = true; } } for (int i = 0; i < q; ++i) if (res[i]) puts( NO ); else puts( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; string s; cin >> s; int x = 0, y = 0, pos = 0, coin = 0; if (s[0] == R ) x++; else y++; if (y > x) pos = 2; if (x > y) pos = 1; for (int i = 1; i < s.length(); i++) { if (s[i] == R ) x++; else y++; int npos = 0; if (y > x) npos = 2; if (x > y) npos = 1; if (npos != 0 && npos != pos) { coin++; pos = npos; } } cout << coin; } |
#include <bits/stdc++.h> using namespace std; const int ALPH = z - a + 1; const int W = 1000 * 1000; const int MOD = 1000 * 1000 * 1000 + 7; template <typename T> vector <int> computePrefPref(const T &s) { int n = s.size(); vector <int> res(n + 1, 0); int i = 1, t = 0; while (i < n) { while (i + t < n && s[i + t] == s[t]) { t++; } res[i] = t; int k = 1; while (k < t && res[k] != res[i] - k) { res[i + k] = min(res[k], res[i] - k); k++; } t = max(0, t - k); i += k; } res.pop_back(); return res; } template <typename T> vector <bool> findOccurences(const T &s, const T &w) { T result = w; copy(s.begin(), s.end(), back_inserter(result)); auto pref = computePrefPref(result); vector <bool> occ(s.size()); for (int i = 0; i < (int) s.size(); i++) { occ[i] = pref[i + w.size()] >= w.size(); } return occ; } int expo(int a, long long n, int mod) { int ans = 1; while (n) { if (n & 1LL) { ans = ((long long) ans * a) % mod; } n >>= 1; a = ((long long) a * a) % mod; } return ans; } int revMod(int a, int mod) { return expo(a, mod - 2, mod); } vector <long long> getPowers(int x, int n) { vector <long long> pw(n + 1); pw[0] = 1; for (int i = 1; i <= n; i++) { pw[i] = (x * pw[i - 1]) % MOD; } return pw; } int main() { ios_base::sync_with_stdio(false); int n, q; cin >> n >> q; string t; vector <string> s(1); cin >> s[0] >> t; while (s.size() <= n && s.back().size() <= W) { s.push_back(s.back() + t[(int) s.size() - 1] + s.back()); } vector <int> sLen(s.size()); for (int i = 0; i < (int) s.size(); i++) { sLen[i] = s[i].size(); } vector <vector<long long>> sumLetter(ALPH, vector <long long> (n + 1, 0)); auto pw = getPowers(2, n); auto pwRev = getPowers(revMod(2, MOD), n); for (int c = 0; c < ALPH; c++) for (int i = 1; i <= n; i++) { sumLetter[c][i] = sumLetter[c][i - 1]; if (t[i - 1] == a + c) { sumLetter[c][i] += pwRev[i - 1]; if (sumLetter[c][i] >= MOD) { sumLetter[c][i] -= MOD; } } } while (q--) { int i; string w; cin >> i >> w; int k = upper_bound(sLen.begin(), sLen.end(), w.size()) - sLen.begin(); long long ans = 0; if (i <= k) { auto occ = findOccurences(s[i], w); for (bool b : occ) { ans += b; } } else { auto occ = findOccurences(s[k], w); for (bool b : occ) { ans += b; } ans = (ans * pw[i - k]) % MOD; string result = w + s[k] + string(1, ) + s[k]; int idx = w.size() + s[k].size(); int tmpSize = result.size() - w.size(); int sn = s[k].size(); for (int c = 0; c < ALPH; c++) { result[idx] = a + c; auto pref = computePrefPref(result); long long here = 0; for (int j = sn - w.size() + 1; j <= sn; j++) { here += pref[j + w.size()] >= w.size(); } long long mul = sumLetter[c][i] - sumLetter[c][k]; if (mul < 0) { mul += MOD; } mul = (mul * pw[i - 1]) % MOD; ans = (ans + here * mul) % MOD; } } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int ins[300]; struct Rec { int n, p; int a[10]; } st[1000000]; void Print(int now) { int i, j, x, pre, ret; if (now == 0) return; pre = st[now].p; ret = st[now].a[st[now].n - 1]; for (i = 0; i < st[pre].n; i++) for (x = 2; x <= 8; x <<= 1) if (st[pre].a[i] * x == ret) { Print(pre); printf( lea e%cx, [%d*e%cx] n , st[now].n + a - 1, x, a + i); return; } for (i = 0; i < st[pre].n; i++) for (j = 0; j < st[pre].n; j++) for (x = 1; x <= 8; x <<= 1) if (st[pre].a[i] + st[pre].a[j] * x == ret) { Print(pre); printf( lea e%cx, [e%cx + %d*e%cx] n , st[now].n + a - 1, i + a , x, j + a ); return; } } int main() { int i, j, n, x, low, top, lim, ret; scanf( %d , &n); if (n == 1) { puts( 0 ); return 0; } st[0].n = 1; st[0].a[0] = 1; for (low = top = 0; low <= top; low++) { memset(ins, 0, sizeof(ins)); lim = st[low].a[st[low].n - 1]; for (i = 0; i < st[low].n; i++) for (x = 2; x <= 8; x <<= 1) { ret = st[low].a[i] * x; if (ret <= lim || ret > n) continue; ins[ret] = 1; } for (i = 0; i < st[low].n; i++) for (j = 0; j < st[low].n; j++) for (x = 1; x <= 8; x <<= 1) { ret = st[low].a[i] + st[low].a[j] * x; if (ret <= lim || ret > n) continue; ins[ret] = 1; } for (i = lim + 1; i <= n; i++) if (ins[i]) { st[++top].n = st[low].n; for (j = 0; j < st[low].n; j++) st[top].a[j] = st[low].a[j]; st[top].a[st[top].n++] = i; st[top].p = low; if (i == n) { printf( %d n , st[top].n - 1); Print(top); return 0; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, v[1005], xi, yi; int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , &v[i]); int res = 0; while (m--) { scanf( %d %d , &xi, &yi); xi--, yi--; res += min(v[xi], v[yi]); } printf( %d n , res); return 0; } |
//-----------------------------------------------------------------------------
// system_v_vid_in_axi4s_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "v_vid_in_axi4s_v2_01_a" *)
module system_v_vid_in_axi4s_0_wrapper
(
vid_in_clk,
rst,
vid_de,
vid_vblank,
vid_hblank,
vid_vsync,
vid_hsync,
vid_data,
aclk,
aresetn,
aclken,
m_axis_video_tdata,
m_axis_video_tvalid,
m_axis_video_tready,
m_axis_video_tuser,
m_axis_video_tlast,
vtd_active_video,
vtd_vblank,
vtd_hblank,
vtd_vsync,
vtd_hsync,
wr_error,
empty,
axis_enable
);
input vid_in_clk;
input rst;
input vid_de;
input vid_vblank;
input vid_hblank;
input vid_vsync;
input vid_hsync;
input [15:0] vid_data;
input aclk;
input aresetn;
input aclken;
output [15:0] m_axis_video_tdata;
output m_axis_video_tvalid;
input m_axis_video_tready;
output m_axis_video_tuser;
output m_axis_video_tlast;
output vtd_active_video;
output vtd_vblank;
output vtd_hblank;
output vtd_vsync;
output vtd_hsync;
output wr_error;
output empty;
input axis_enable;
v_vid_in_axi4s
#(
.C_M_AXIS_VIDEO_DATA_WIDTH ( 8 ),
.C_M_AXIS_VIDEO_FORMAT ( 0 ),
.VID_IN_DATA_WIDTH ( 16 ),
.C_M_AXIS_VIDEO_TDATA_WIDTH ( 16 ),
.PADDING_BITS ( 0 ),
.RAM_ADDR_BITS ( 10 ),
.HYSTERESIS_LEVEL ( 12 )
)
v_vid_in_axi4s_0 (
.vid_in_clk ( vid_in_clk ),
.rst ( rst ),
.vid_de ( vid_de ),
.vid_vblank ( vid_vblank ),
.vid_hblank ( vid_hblank ),
.vid_vsync ( vid_vsync ),
.vid_hsync ( vid_hsync ),
.vid_data ( vid_data ),
.aclk ( aclk ),
.aresetn ( aresetn ),
.aclken ( aclken ),
.m_axis_video_tdata ( m_axis_video_tdata ),
.m_axis_video_tvalid ( m_axis_video_tvalid ),
.m_axis_video_tready ( m_axis_video_tready ),
.m_axis_video_tuser ( m_axis_video_tuser ),
.m_axis_video_tlast ( m_axis_video_tlast ),
.vtd_active_video ( vtd_active_video ),
.vtd_vblank ( vtd_vblank ),
.vtd_hblank ( vtd_hblank ),
.vtd_vsync ( vtd_vsync ),
.vtd_hsync ( vtd_hsync ),
.wr_error ( wr_error ),
.empty ( empty ),
.axis_enable ( axis_enable )
);
endmodule
|
///////////////// ** reset_ctrl ** //////////////////////////////////////////
//
// This module is clocked at 40MHz. It waits for a trigger pulse synchronous to
// 40MHz before initiating one of two reset routines
//
// idelay_rst_trig causes a reset of the idelayctrl and idelay instances. The idelayctrl
// is has its asynch reset held high for 3 cycles of 40MHz (75ns - the minimum reset time is 50ns)
// Both idelay resets are then asserted (synchronous to 40MHz as req'd) for a cycle
//
// The 200MHz clock used by idelayctrl is produced with a DCM and must be stable prior
// to reset. full_rst_trig causes the DCM to be reset first using its asynch reset line
// The DCM nominally takes 10ms to lock, after which the reset must be held for a further
// 200ms to ensure stability. The idelayctrl reset must be tied to the the DCMs locked signal
//
// 210ms = 8,400,000 cycles of 40MHz (24-bit counter)
module reset_ctrl(
input clk40,
input idelay_rst_trig,
input full_rst_trig,
output reg dcm_rst = 1'b0,
output reg idelay_rst = 1'b0
);
// Ports
/*input clk40;
input idelay_rst_trig;
input full_rst_trig;
output dcm_rst;
output idelay_rst;*/
// Internal registers
//reg dcm_rst;
//reg idelay_rst;
reg rst_flag = 1'b0;
reg [23:0] rst_count = 24'd0;
always @(posedge clk40) begin
if (rst_flag) begin
//Triggered
rst_count <= rst_count + 1'd1;
case (rst_count)
24'd0: begin
//Begin resetting DCM
dcm_rst <= 1'b1;
idelay_rst <= idelay_rst;
rst_flag <= rst_flag;
end
24'd8500000: begin
//212.5ms have passed. Stop reset then reset idelayctrl
dcm_rst <= 1'b0;
idelay_rst <= idelay_rst;
rst_flag <= rst_flag;
end
24'd8500010: begin
//idelayctrl is reset. Now do idelays
idelay_rst <= 1'b1;
dcm_rst <= dcm_rst;
rst_flag <= rst_flag;
end
24'd8500020: begin
//Finished
idelay_rst <= 1'b0;
dcm_rst <= dcm_rst;
rst_flag <= 1'b0;
end
endcase
end else begin
//Not triggered yet
if (idelay_rst_trig) begin
//Trigger partial reset
rst_flag <= 1'b1;
rst_count <= 24'd8500010;
idelay_rst <= idelay_rst;
dcm_rst <= dcm_rst;
end else begin
//Trigger full reset
if (full_rst_trig) begin
rst_flag <= 1'b1;
rst_count <= 24'd0;
idelay_rst <= idelay_rst;
dcm_rst <= dcm_rst;
end
end
end
end
endmodule
|
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