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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, abc = 864197532, N = 1000001, logN = 17; vector<int> a; vector<int> d, lp; struct Seg { int l, r, m; long long int val = 0; Seg* ch[2]; Seg(int _l, int _r) : l(_l), r(_r), m(l + r >> 1) { if (r - l > 1) { ch[0] = new Seg(l, m); ch[1] = new Seg(m, r); pull(); } else { val = a[l]; } } void pull() { val = ch[0]->val + ch[1]->val; } void set(int p) { if (r - l == 1) val = d[val]; else ch[p >= m]->set(p), pull(); } long long int query(int a, int b) { if (a <= l && r <= b) return val; long long int ans = 0; if (a < m) ans += ch[0]->query(a, b); if (m < b) ans += ch[1]->query(a, b); return ans; } }; void build() { d.assign(N, 1); lp.assign(N, 0); for (int i = 2; i < N; ++i) if (lp[i] == 0) { for (int j = i; j < N; j += i) lp[j] = i; } for (int i = 2; i < N; ++i) { int p = lp[i], tmp = i, cnt = 0; while (tmp % p == 0) tmp /= p, cnt++; d[i] = d[tmp] * (cnt + 1); } } int main() { ios::sync_with_stdio(false); cin.tie(0); build(); int n, q, t, l, r; cin >> n >> q; a.resize(n); for (int i = 0; i < n; ++i) cin >> a[i]; Seg root(0, n); set<int> s; for (int i = 0; i < n; ++i) if (a[i] > 2) s.insert(i); vector<int> eras; while (q--) { cin >> t >> l >> r, l--; if (t == 1) { for (auto it = s.lower_bound(l); it != s.end() && *it < r; ++it) { int p = *it; root.set(p); a[p] = d[a[p]]; if (a[p] <= 2) eras.push_back(p); } while (eras.size()) { s.erase(eras.back()); eras.pop_back(); } } else { cout << root.query(l, r) << n ; } } } |
module autoinst_vertrees_slv
(/*AUTOARG*/
// Outputs
i2c_mst_data, i2c_read, i2c_slv_scl_out, i2c_slv_sda_out, i2c_spc_scl_state, i2c_start,
i2c_strobe, slv_bit_st, slv_put, i2c_spc_scl_fall, i2c_spc_sda_state, i2c_spc_start,
i2c_spc_stop,
// Inputs
ck_ref, i2c_slv_data, i2c_slv_scl_in, i2c_slv_sda_in, r_i2c_spc_scl_low, rpt_hold, rpt_sda,
rst_ref, test_mode
);
input ck_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input [7:0] i2c_slv_data; // To u_misc of ddc_slv_misc.v
input i2c_slv_scl_in; // To u_spc of i2c_slv_pin_ctrl.v
input i2c_slv_sda_in; // To u_spc of i2c_slv_pin_ctrl.v
input [4:0] r_i2c_spc_scl_low; // To u_spc of i2c_slv_pin_ctrl.v
input rpt_hold; // To u_misc of ddc_slv_misc.v
input rpt_sda; // To u_misc of ddc_slv_misc.v
input rst_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input test_mode; // To u_spc of i2c_slv_pin_ctrl.v
output [7:0] i2c_mst_data; // From u_misc of ddc_slv_misc.v
output i2c_read; // From u_misc of ddc_slv_misc.v
output i2c_slv_scl_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_slv_sda_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_scl_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_start; // From u_misc of ddc_slv_misc.v
output i2c_strobe; // From u_misc of ddc_slv_misc.v
output slv_bit_st; // From u_misc of ddc_slv_misc.v
output slv_put; // From u_misc of ddc_slv_misc.v
output i2c_spc_scl_fall; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_sda_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_start; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_stop; // From u_spc of i2c_slv_pin_ctrl.v
endmodule // ddc_slv
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_read_datapath(
ck,
reset_n,
check_do,
check_dm,
check_do_lfsr,
check_dm_lfsr,
check_pattern_push,
clear_error,
read_data,
read_data_valid,
error_word,
enable_ap_mode
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input [3:0] check_do;
input [2:0] check_dm;
input check_do_lfsr;
input check_dm_lfsr;
input check_pattern_push;
input enable_ap_mode;
input clear_error;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input read_data_valid;
output [DATA_WIDTH - 1 : 0] error_word;
reg [4:0] pattern_radd;
reg [4:0] pattern_wadd;
wire [4:0] pattern_radd_next;
wire [8:0] check_word_write = { check_do, check_dm, check_do_lfsr, check_dm_lfsr };
wire [8:0] check_word_read;
wire [3:0] check_do_read = check_word_read[8:5];
wire [2:0] check_dm_read = check_word_read[4:2];
wire check_do_lfsr_read = check_word_read[1];
wire check_dm_lfsr_read = check_word_read[0];
wire [DATA_BUS_SIZE - 1 : 0] do_data;
wire [NUMBER_OF_WORDS - 1 : 0] dm_data;
wire do_lfsr_step = check_do_lfsr_read & read_data_valid;
wire dm_lfsr_step = check_dm_lfsr_read & read_data_valid;
reg h_data_valid;
reg h_data_valid_r;
always @(posedge ck)
begin
if (~reset_n)
begin
h_data_valid <= 1'b0;
h_data_valid_r <= 1'b0;
end
else
begin
if (h_data_valid)
h_data_valid <= 1'b0;
else if (read_data_valid & ~h_data_valid)
h_data_valid <= 1'b1;
h_data_valid_r <= h_data_valid;
end
end
wire [DATA_BUS_SIZE - 1 : 0] h_do_data;
assign h_do_data = (h_data_valid_r & enable_ap_mode)? {DATA_BUS_SIZE {1'b0}} : do_data;
rw_manager_bitcheck bitcheck_i(
.ck(ck),
.reset_n(reset_n),
.clear(clear_error),
.enable(read_data_valid),
.read_data(read_data),
.reference_data(h_do_data),
.mask(dm_data),
.error_word(error_word)
);
defparam bitcheck_i.DATA_WIDTH = DATA_WIDTH;
defparam bitcheck_i.AFI_RATIO = AFI_RATIO;
rw_manager_write_decoder write_decoder_i(
.ck(ck),
.reset_n(reset_n),
.do_lfsr(check_do_lfsr_read),
.dm_lfsr(check_dm_lfsr_read),
.do_lfsr_step(do_lfsr_step),
.dm_lfsr_step(dm_lfsr_step),
.do_code(check_do_read),
.dm_code(check_dm_read),
.do_data(do_data),
.dm_data(dm_data)
);
defparam write_decoder_i.DATA_WIDTH = DATA_WIDTH;
defparam write_decoder_i.AFI_RATIO = AFI_RATIO;
rw_manager_pattern_fifo pattern_fifo_i(
.clock(ck),
.data(check_word_write),
.rdaddress(pattern_radd_next),
.wraddress(pattern_wadd),
.wren(check_pattern_push),
.q(check_word_read)
);
assign pattern_radd_next = pattern_radd + (read_data_valid ? 1'b1 : 1'b0);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end
else begin
if (clear_error) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end else begin
if(read_data_valid) begin
pattern_radd <= pattern_radd + 1'b1;
end
if(check_pattern_push) begin
pattern_wadd <= pattern_wadd + 1'b1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000000 + 7; const long long int N = 1000000 + 6; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int tc; tc = 1; while (tc--) { long long int n, m; cin >> n >> m; string s[n]; for (long long int i = 0; i < n; i++) cin >> s[i]; long long int d[m]; for (long long int i = 0; i < m; i++) cin >> d[i]; long long int ans = 0; for (long long int j = 0; j < m; j++) { map<char, long long int> p; long long int t = 0; for (long long int i = 0; i < n; i++) { p[s[i][j]]++; t = max(t, p[s[i][j]]); } ans += t * d[j]; } cout << ans; } } |
#include <bits/stdc++.h> using namespace std; priority_queue<pair<int, char> > pr; bool is_prime(int n) { if (n == 1) return 0; for (int i = 2; i * i <= n; i++) if (n % i == 0) return 0; return 1; } vector<int> prime, pos[1004]; map<int, int> mark, mark2; map<int, int>::iterator it; bool vis[10000]; void solve(int n, int prm, int idx) { vis[prm] = 1; int rng = n / prm; for (int j = 1; j <= rng; j++) { int x = prm * j; if (!mark2[x]) pos[idx].push_back(x); mark2[x] = 1; for (int k = 2; k * k <= x; k++) { if (x % k == 0) { while (x % k == 0) x /= k; if (!vis[k] && k <= n) solve(n, k, idx); } } if (x > 1 && !vis[x]) solve(n, x, idx); } } int main() { int n; string tmp, str; str += 1 ; cin >> tmp; str += tmp; n = tmp.size(); char ans[10000]; for (int i = 0; i <= n; i++) ans[i] = 1 ; for (int i = 2; i <= n / 2; i++) if (is_prime(i)) prime.push_back(i); bool flg = 1; int sz = 0; for (int i = 0; i < prime.size(); i++) if (!vis[prime[i]]) solve(n, prime[i], sz++); for (int i = 1; i <= n; i++) mark[str[i]]++; for (it = mark.begin(); it != mark.end(); it++) pr.push(make_pair(it->second, it->first)); for (int i = 0; i < sz; i++) { if (pos[i].size() <= pr.top().first) { for (int j = 0; j < pos[i].size(); j++) ans[pos[i][j]] = pr.top().second; int x = pr.top().first - pos[i].size(); char ch = pr.top().second; pr.pop(); pr.push(make_pair(x, ch)); } else { flg = 0; break; } } if (flg) { printf( YES n ); for (int i = 1; i <= n; i++) { if (ans[i] == 1 ) { while (!pr.top().first) pr.pop(); ans[i] = pr.top().second; int x = pr.top().first - 1; char ch = pr.top().second; pr.pop(); pr.push(make_pair(x, ch)); } } for (int i = 1; i <= n; i++) printf( %c , ans[i]); printf( n ); } else printf( NO n ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_SYMBOL_V
`define SKY130_FD_SC_HD__SEDFXBP_SYMBOL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sedfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__HA_FUNCTIONAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; vector<long long> v[100001]; int main() { int n; cin >> n; for (long long i = 1; i < n; i++) { long long a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } for (long long i = 1; i <= n; i++) { if (v[i].size() == 2) { cout << NO ; return 0; } } cout << YES ; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos_pad(oe ,bsr_si ,rst_io_l ,se ,rst_val_up ,data ,
mode_ctl ,clock_dr ,update_dr ,rst_val_dn ,hiz_l ,
shift_dr ,bso ,to_core ,pad ,por_l, vddo );
output bso ;
output to_core ;
input oe ;
input bsr_si ;
input rst_io_l ;
input se ;
input rst_val_up ;
input data ;
input mode_ctl ;
input clock_dr ;
input update_dr ;
input rst_val_dn ;
input hiz_l ;
input shift_dr ;
input por_l ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire q_up_pad ;
wire net84 ;
wire rcvr_data ;
wire bsr_dn_l ;
wire q_dn_pad_l ;
wire por ;
wire bsr_data_to_core ;
wire sel_data_n ;
wire pad_up ;
wire bsr_up ;
wire pad_dn_l ;
bw_io_cmos_edgelogic I2 (
.rcvr_data (rcvr_data ),
.to_core (to_core ),
.se (se ),
.bsr_up (q_up_pad ),
.bsr_dn_l (q_dn_pad_l ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.por_l (por_l ),
.por (por ),
.bsr_data_to_core (bsr_data_to_core ),
.bsr_mode (mode_ctl ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (bsr_dn_l ),
.bsr_up (bsr_up ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (sel_data_n ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_dtl_bscan bscan (
.bsr_data_to_core (bsr_data_to_core ),
.hiz_l (hiz_l ),
.rst_io_l (rst_io_l ),
.rst_val_dn (rst_val_dn ),
.rst_val_up (rst_val_up ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.update_dr (update_dr ),
.up_open (vdd ),
.bsr_so (bso ),
.se (se ),
.mode_ctl (mode_ctl ),
.bsr_si (bsr_si ),
.q_up_mux (bsr_up ),
.down_25 (vss ),
.sel_data_n (sel_data_n ),
.rcvr_data_to_bsr (rcvr_data ),
.q25_dn_pad_l (vdd ),
.q_dn_pad_l (q_dn_pad_l ),
.q_dn_mux_l (bsr_dn_l ),
.q25_dn_mux_l (net84 ),
.q_up_pad (q_up_pad ),
.serial_out (),
.bypass_enable (vss),
.clk (vss),
.bypass_in (vss),
.serial_in (vss),
.ps_select (vss),
.out_type (vss) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data ),
.in (pad ) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NAND2B_BEHAVIORAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; string LexicographicallyMaximumSubsequence(string text) { string localMax = ; char current = text.at(text.length() - 1); localMax += current; unsigned int size = text.length() - 2; for (int i = size; i >= 0; i--) { if (text.at(i) >= current) { localMax = text.at(i) + localMax; current = text.at(i); } } return localMax; } int main() { string text; cin >> text; cout << LexicographicallyMaximumSubsequence(text) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename X> inline X abs(const X& a) { return a < 0 ? -a : a; } template <typename X> inline X sqr(const X& a) { return a * a; } long long combine(long long n, int k) { long long ans = 1; for (int i = 0; i < k; i++) ans = (ans * (n - i)) / (i + 1); return ans; } long long pw(long long a, long long p) { long long ans = 1; for (int i = 0; i < p; i++) ans *= a; return ans; } int toint(string s) { int n = 0, k = 1; for (int i = (int)s.size() - 1; i >= 0; i--) { n += (s[i] - 0 ) * k; k *= 10; } return n; } int main() { int k, m, n, p; int a = 0, b; cin >> n >> k >> p, b = n * p; while (n > 1) { m = 1; while (2 * m <= n) m <<= 1; a += m * k + m / 2; n = n - m + m / 2; } cout << a << << b << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-8; const long long SZ = 1010, SSZ = 100010, APB = 26, one = 93, INF = 0x3f3f3f3f3f3f3f3f, mod = 1000000007; long long n, m, bg, fn, cnt; long long to[SSZ], wt[SSZ], head[SZ]; long long nex[SSZ], mk[SSZ]; long long dfn[SZ], low[SZ], tot; bool vst[SZ]; void add(long long u, long long v, long long w) { ++cnt; nex[cnt] = head[u]; head[u] = cnt; to[cnt] = v, wt[cnt] = w; } bool dfs(long long x) { vst[x] = 1; if (x == fn) return 1; for (long long i = head[x]; i != -1; i = nex[i]) { long long t = to[i]; if (!vst[t]) { mk[i] = 1; if (dfs(t)) return 1; mk[i] = 0; } } return 0; } stack<long long> stk; void tar(long long x, long long p, long long &res2, long long &eg2) { dfn[x] = low[x] = ++tot; vst[x] = 1; for (long long i = head[x]; i != -1; i = nex[i]) { if (i != (p ^ 1) && mk[i] != 2 && mk[i ^ 1] != 2) { long long t = to[i], w = wt[i]; if (!dfn[t]) { tar(t, i, res2, eg2); low[x] = min(low[x], low[t]); } else low[x] = min(low[x], low[t]); if (dfn[x] < low[t] && dfn[fn] >= dfn[t]) { if (w < res2) { res2 = w, eg2 = i; } } } } } void init() { cin >> n >> m >> bg >> fn; cnt = -1; memset(head, -1, sizeof(head)); for (long long i = 1; i <= m; ++i) { long long a, b, c; cin >> a >> b >> c; add(a, b, c); add(b, a, c); } dfs(bg); if (vst[fn] == 0) { cout << 0 << endl << 0; return; } long long res = INF, vt1 = -1, vt2; for (long long i = 0; i <= cnt; ++i) { if (mk[i]) { mk[i] = 2; memset(vst, 0, sizeof(vst)); tot = 0; memset(dfn, 0, sizeof(dfn)); memset(low, 0, sizeof(low)); long long res1 = wt[i], res2 = INF, eg1 = i, eg2; tar(bg, -1, res2, eg2); if (!vst[fn]) res2 = 0, eg2 = -5; if (res1 + res2 < res) { res = res1 + res2; vt1 = eg1 / 2 + 1, vt2 = eg2 / 2 + 1; } mk[i] = 1; } } if (vt1 == -1) { cout << -1 << endl; return; } cout << res << endl; cout << (vt2 == -1 ? 1 : 2) << endl; cout << vt1 << ; if (vt2 != -1) cout << vt2 << endl; } void work() {} int main() { std::ios::sync_with_stdio(0); long long casenum; { init(); work(); } return 0; } |
#include <bits/stdc++.h> const int G[8][2] = {{0, 4}, {1, 5}, {2, 6}, {3, 7}, {0, 2}, {1, 6}, {3, 4}, {5, 7}}; int f[(1 << 8)], g[1111]; int max(int a, int b) { return a > b ? a : b; } int min(int a, int b) { return a < b ? a : b; } int main() { int n; int i, j, k, _; f[0] = 0; memset(g, 0, sizeof g); for (i = 0; i < 8; ++i) { j = G[i][0]; k = G[i][1]; g[j] |= 1 << k; g[k] |= 1 << j; } for (i = 1; i < (1 << 8); ++i) { j = i & (i - 1); f[i] = max(f[j], f[j & ~g[__builtin_ctz(i)]] + 1); } scanf( %d , &n); n -= 2; for (i = 1, j = n; i < j; ++i, --j) g[i] = (1 << 8) - 1; if (i == j) g[i] = 0x55; for (scanf( %d , &_); _; --_) { scanf( %d%d , &i, &j); --i; --j; k = min(i, n - i + 1); g[k] &= (i == k ? ~0x44 : ~0x88); k = min(j, n - j + 1); g[k] &= (j == k ? ~0x11 : ~0x22); } for (k = 0, i = 1, j = n; i < j; ++i, --j) k += f[g[i]]; if (i == j && g[i]) ++k; printf( %d , k); return 0; } |
//////////////////////////////////////////////////////////////////
////
////
//// CRCAHB CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// crcahb IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module crc_parallel
#(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter FRAME_SIZE = 8 // Number of bits in the data block
)(
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out,
//INPUTS
input [FRAME_SIZE - 1 : 0] data_in,
input [CRC_SIZE - 1 : 0] crc_init,
input [CRC_SIZE - 1 : 0] crc_poly,
input [CRC_SIZE - 1 : 0] crc_poly_size
);
localparam ENABLE = {CRC_SIZE{1'b1}};
localparam DISABLE = {CRC_SIZE{1'b0}};
wire [CRC_SIZE - 1 : 0] crc_comb_out[0 : FRAME_SIZE];
wire [CRC_SIZE - 1 : 0] poly_sel [1 : CRC_SIZE - 1];
wire [CRC_SIZE - 1 : 0] sel_out [0 : CRC_SIZE - 1];
wire [CRC_SIZE - 1 : 0] crc_init_sel[0 : CRC_SIZE - 1];
wire [CRC_SIZE - 1 : 0] poly_mux;
wire [CRC_SIZE - 1 : 0] crc_poly_size_reversed;
wire [CRC_SIZE - 1 : 0] crc_init_justified;
assign poly_mux[0] = crc_poly[0];
generate
genvar k;
for(k = 1; k < CRC_SIZE; k = k + 1)
begin
assign poly_sel[CRC_SIZE - k] = crc_poly_size >> (k - 1);
assign poly_mux[k] = |(crc_poly & poly_sel[k]);
end
endgenerate
generate
genvar l;
for(l = 0; l < CRC_SIZE; l = l + 1)
begin
assign crc_poly_size_reversed[l] = crc_poly_size[CRC_SIZE - 1 - l];
assign sel_out[l] = crc_poly_size_reversed << l;
assign crc_out[l] = |(sel_out[l] & crc_comb_out[FRAME_SIZE]);
end
endgenerate
generate
genvar m;
for(m = CRC_SIZE - 1; m >= 0; m = m - 1)
begin
assign crc_init_sel[m] = crc_poly_size >> (CRC_SIZE - 1 - m);
assign crc_init_justified[m] = |(crc_init & crc_init_sel[m]);
end
endgenerate
assign crc_comb_out[0] = crc_init_justified;
generate
genvar i;
for(i = 0; i < FRAME_SIZE; i = i + 1)
begin
crc_comb
#(
.CRC_SIZE ( CRC_SIZE ),
.MASK ( ENABLE )
) CRC_COMB
(
.crc_out ( crc_comb_out[i + 1] ),
.data_in ( data_in[FRAME_SIZE - 1 - i] ),
.crc_in ( crc_comb_out[i] ),
.crc_poly ( poly_mux ),
.crc_poly_size ( crc_poly_size[CRC_SIZE - 2:0] )
);
end
endgenerate
endmodule
|
/*
###########################################################################
# **EMMU**
#
# This block uses the upper 12 bits [31:20] of a memory address as an index
# to read an entry from a table.
#
# The table is written from the mi_* configuration interface.
#
# The table can be configured as 12 bits wide or 44 bits wide.
#
# 32bit address output = {table_data[11:0],dstaddr[19:0]}
# 64bit address output = {table_data[43:0],dstaddr[19:0]}
#
############################################################################
*/
module emmu (/*AUTOARG*/
// Outputs
mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
// Inputs
reset, rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr,
mi_din, emesh_access_in, emesh_packet_in, emesh_rd_wait,
emesh_wr_wait
);
parameter DW = 32; //data width
parameter AW = 32; //address width
parameter PW = 104;
parameter EPW = 136; //extended by 32 bits
parameter MW = 48; //width of table
parameter MAW = 12; //memory addres width (entries = 1<<MAW)
parameter GROUP = 0;
/*****************************/
/*DATAPATH CLOCk */
/*****************************/
input reset;
input rd_clk;
input wr_clk;
/*****************************/
/*MMU LOOKUP DATA */
/*****************************/
input mmu_en; //enables mmu (static)
input mmu_bp; //bypass mmu on read response
/*****************************/
/*Register Access Interface */
/*****************************/
input mi_en; //memory access
input mi_we; //byte wise write enable
input [14:0] mi_addr; //address
input [DW-1:0] mi_din; //input data
output [DW-1:0] mi_dout; //read back (TODO?? not implemented)
/*****************************/
/*EMESH INPUTS */
/*****************************/
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
input emesh_rd_wait;
input emesh_wr_wait;
/*****************************/
/*EMESH OUTPUTS */
/*****************************/
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
output [31:0] emesh_packet_hi_out;
/*****************************/
/*REGISTERS */
/*****************************/
reg emesh_access_out;
reg [PW-1:0] emesh_packet_reg;
wire [63:0] emesh_dstaddr_out;
wire [MW-1:0] emmu_lookup_data;
wire [63:0] mi_wr_data;
wire [5:0] mi_wr_vec;
wire mi_match;
wire [MW-1:0] emmu_rd_addr;
wire write_in;
/*****************************/
/*MMU WRITE LOGIC */
/*****************************/
//write controls
assign mi_wr_vec[5:0] = (mi_en & mi_we & ~mi_addr[2]) ? 6'b001111 :
(mi_en & mi_we & mi_addr[2]) ? 6'b110000 :
6'b000000 ;
//write data
assign mi_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
//todo: implement readback? worth it?
assign mi_dout[DW-1:0] = 'b0;
/*****************************/
/*MMU READ LOGIC */
/*****************************/
//TODO: could we do with less entries?
assign write_in = emesh_packet_in[1];
assign emmu_rd_addr[MAW-1:0] = emesh_packet_in[39:28];
memory_dp #(.DW(MW),.AW(MAW)) memory_dp (
// Outputs
.rd_data (emmu_lookup_data[MW-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_en (mi_wr_vec[5:0]),
.wr_addr (mi_addr[14:3]),
.wr_data (mi_wr_data[MW-1:0]),
.rd_clk (rd_clk),
.rd_en (emesh_access_in),
.rd_addr (emmu_rd_addr[MAW-1:0])
);
/*****************************/
/*EMESH OUTPUT TRANSACTION */
/*****************************/
//pipeline to compensate for table lookup pipeline
//assumes one cycle memory access!
always @ (posedge rd_clk)
if (reset)
begin
emesh_access_out <= 1'b0;
end
else if((write_in & ~emesh_wr_wait) | (~write_in & ~emesh_rd_wait))
begin
emesh_access_out <= emesh_access_in;
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];
end
assign emesh_dstaddr_out[63:0] = (mmu_en & ~mmu_bp) ? {emmu_lookup_data[43:0], emesh_packet_reg[27:8]} :
{32'b0,emesh_packet_reg[39:8]};
//Concatenating output packet
assign emesh_packet_out[PW-1:0] = {emesh_packet_reg[PW-1:40],
emesh_dstaddr_out[31:0],
emesh_packet_reg[7:0]
};
assign emesh_packet_hi_out[31:0] = emesh_dstaddr_out[63:32];
endmodule // emmu
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; int r1, c1, r2, c2; int rook(int r1, int c1, int r2, int c2) { if (r1 == r2 || c1 == c2) { return 1; } else { return 2; } } int bishop(int r1, int c1, int r2, int c2) { if ((r1 + c1) % 2 == 0 && (r2 + c2) % 2 != 0) return 0; if ((r1 + c1) % 2 != 0 && (r2 + c2) % 2 == 0) return 0; if (abs(r1 - r2) == abs(c1 - c2)) return 1; else return 2; } int king(int r1, int c1, int r2, int c2) { return (max(abs(r1 - r2), abs(c1 - c2))); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> r1 >> c1 >> r2 >> c2; cout << rook(r1, c1, r2, c2) << ; cout << bishop(r1, c1, r2, c2) << ; cout << king(r1, c1, r2, c2) << ; } |
#include <bits/stdc++.h> using namespace std; bool vis[12][12][12]; int ans2(int x, int y, int z, char a[12][12][12], int k, int n, int m) { int cnt = 0; if (a[x][y][z] == # || vis[x][y][z]) return 0; cnt++; vis[x][y][z] = true; if (x > 1) cnt += ans2(x - 1, y, z, a, k, n, m); if (x < k) cnt += ans2(x + 1, y, z, a, k, n, m); if (y > 1) cnt += ans2(x, y - 1, z, a, k, n, m); if (y < n) cnt += ans2(x, y + 1, z, a, k, n, m); if (z > 1) cnt += ans2(x, y, z - 1, a, k, n, m); if (z < m) cnt += ans2(x, y, z + 1, a, k, n, m); return cnt; } int ans(int x, int y, int z, char a[12][12][12], int k, int n, int m) { int cnt = 0; vis[x][y][z] = true; if (a[x][y][z] == . ) cnt++; if (a[x][y][z] == . ) { if (x < k) cnt += ans2(x + 1, y, z, a, k, n, m); } if (y > 1) cnt += ans2(x, y - 1, z, a, k, n, m); if (y < n) cnt += ans2(x, y + 1, z, a, k, n, m); if (z > 1) cnt += ans2(x, y, z - 1, a, k, n, m); if (z < m) cnt += ans2(x, y, z + 1, a, k, n, m); return cnt; } int main() { int n, k, m; char a[12][12][12]; cin >> k >> n >> m; for (int i = 1; i <= k; i++) { for (int j = 1; j <= n; j++) { for (int t = 1; t <= m; t++) { cin >> a[i][j][t]; } } } int x, y; cin >> x >> y; cout << ans(1, x, y, a, k, n, m) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; int cnt = 0; for (int i = 1; i < n + 1; i++) { if (i <= b + 1 && (n - i) >= a) cnt++; } cout << cnt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rnd(51); signed main() { ios::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } deque<pair<long long, long long>> q; for (long long i = 0; i < n; i++) { if (q.size() == 0) { q.push_back({a[i], 1}); } else { if (q.back().first == a[i]) { q.back().second++; if (q.size() > 1 && q[q.size() - 2].first >= q.back().first) { long long now = q.back().second; q.pop_back(); q.back().second += now; } } else if (q.back().first > a[i]) { q.push_back({a[i], 1}); } else { if (q.back().second % 2 == 1) { cout << NO n ; return 0; } else { q.push_back({a[i], 1}); } } } } while (q.size() > 1 && ((q[q.size() - 2].second % 2 == 0 && q[q.size() - 2].first < q.back().first) || (q.back().second % 2 == 0 && q.back().first < q[q.size() - 2].first))) { long long now = q.back().second; long long mx = max(q.back().first, q[q.size() - 2].first); q.pop_back(); q.back().first = mx; q.back().second += now; } if (q.size() == 1) { cout << YES n ; } else { cout << NO n ; } return 0; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connectpr on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
******************************************************************************/
module altera_up_rs232_counters (
// Inputs
clk,
reset,
reset_counters,
// Bidirectionals
// Outputs
baud_clock_rising_edge,
baud_clock_falling_edge,
all_bits_transmitted
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // BAUD COUNTER WIDTH
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // TOTAL DATA WIDTH
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input reset_counters;
// Bidirectionals
// Outputs
output reg baud_clock_rising_edge;
output reg baud_clock_falling_edge;
output reg all_bits_transmitted;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [(CW-1):0] baud_counter;
reg [ 3: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
baud_counter <= {CW{1'b0}};
else if (reset_counters)
baud_counter <= {CW{1'b0}};
else if (baud_counter == BAUD_TICK_COUNT)
baud_counter <= {CW{1'b0}};
else
baud_counter <= baud_counter + 1;
end
always @(posedge clk)
begin
if (reset)
baud_clock_rising_edge <= 1'b0;
else if (baud_counter == BAUD_TICK_COUNT)
baud_clock_rising_edge <= 1'b1;
else
baud_clock_rising_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
baud_clock_falling_edge <= 1'b0;
else if (baud_counter == HALF_BAUD_TICK_COUNT)
baud_clock_falling_edge <= 1'b1;
else
baud_clock_falling_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
bit_counter <= 4'h0;
else if (reset_counters)
bit_counter <= 4'h0;
else if (bit_counter == TDW)
bit_counter <= 4'h0;
else if (baud_counter == BAUD_TICK_COUNT)
bit_counter <= bit_counter + 4'h1;
end
always @(posedge clk)
begin
if (reset)
all_bits_transmitted <= 1'b0;
else if (bit_counter == TDW)
all_bits_transmitted <= 1'b1;
else
all_bits_transmitted <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; using vi = vector<int>; const int Z = int(1e5 + 1); const int inf = int(2e9 + 1); const ll llinf = ll(2e18 + 1); const ll mod = ll(1e9 + 7); int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, x; cin >> n >> x; int sum = 0; for (int i = 0; i < n; i++) { int a; cin >> a; sum += a; } sum = abs(sum); cout << sum / x + int(sum % x != 0) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, Max, reg; int TIME = 0; vector<int> T, W; bool used[1010]; int p[1010], dmg[1010]; int main() { int i, j, k, l, x, y; cin >> n >> Max >> reg; for (i = 0; i < n; ++i) cin >> p[i] >> dmg[i]; int ch = Max, cd = 0; while (1) { ch -= cd; ch = min(Max, ch + reg); if (ch <= 0) break; j = -1; for (i = 0; i < n; ++i) { if (used[i] || p[i] * Max < 100 * ch) continue; if (j == -1 || dmg[j] < dmg[i]) j = i; } if (j != -1 && dmg[j] >= 0) { if (dmg[j] > cd || true) { T.push_back(TIME); W.push_back(j + 1); used[j] = true; cd += dmg[j]; } } ++TIME; if (TIME >= 10000) break; } if (ch > 0) cout << NO n ; else { cout << YES n ; cout << TIME << << T.size() << endl; for (i = 0; i < T.size(); ++i) cout << T[i] << << W[i] << endl; } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_4_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_4_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_4_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_4_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; bool check(vector<long long> a, long long m, long long n) { vector<long long> v(n + 1, 0); for (long long i = 0; i < n; i++) { v[a[i]] += 1; } set<pair<long long, long long>, greater<pair<long long, long long>>> s; for (long long i = 1; i < n + 1; i++) { if (v[i]) { s.insert({v[i], i}); } } vector<long long> b; for (long long i = 0; i < n; i++) { if (i >= m and v[b[i - m]]) { s.insert({v[b[i - m]], b[i - m]}); } if (s.empty()) return false; pair<long long, long long> p = *(s.begin()); b.push_back(p.second); s.erase(p); v[p.second] -= 1; } return true; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, m; cin >> n >> m; vector<long long> a(n), b(m); for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < m; i++) cin >> b[i]; sort(a.begin(), a.end()); sort(b.begin(), b.end()); if (a[n - 1] > b[0]) { cout << -1 n ; return 0; } long long ans = 0; for (long long i = 0; i < n; i++) ans += a[i] * m; long long g = n - 1, h = m - 1; bool is = false; for (long long i = m - 1; i >= 0; i--) { while (g >= 0 && h == 0) { g--; h = m - 1; } if (b[i] == a[n - 1]) { break; } if (g < 0) { cout << -1 n ; return 0; } ans += b[i] - a[g]; h--; } cout << ans << endl; return 0; } |
`begin_keywords "1364-2005"
`timescale 1ns/100ps
module top;
parameter pdly = 1.2;
real rdly = 1.3;
integer idly = 1;
reg in = 1'b0;
wire gi, gf, gs, gt;
wire #idly int = in;
wire #1.1 first = in;
wire #pdly second = in;
wire #rdly third = in;
buf #idly (gi, in);
buf #1.1 (gf, in);
buf #pdly (gs, in);
buf #rdly (gt, in);
initial begin
$monitor($realtime,, int,, first,, second,, third,, gi,, gf,, gs,, gt);
#0 in = 1'b1;
#2 in = 1'b0;
#4;
rdly = -6.1; // Since we are at 6 this will not wrap.
in = 1'b1;
@(third or gt) $display("Large delay: ", $realtime);
end
initial #1.1 $display("Should be 1.1: ", $realtime); // This should be 1.1
initial #pdly $display("Should be 1.2: ", $realtime); // This should be 1.2
initial begin
#0; // We need this so that rdly has a defined value.
#rdly $display("Should be 1.3: ", $realtime); // This should be 1.3
end
initial begin
#0; // We need this so that rdly has a defined value.
#idly $display("Should be 1.0: ", $realtime); // This should be 1.0
end
endmodule
`timescale 1ns/1ps
module top2;
initial #1.001 $display("Should be 1.001: ", $realtime);
endmodule
`end_keywords
|
#include <bits/stdc++.h> using namespace std; template <typename T> T nextInt() { T x = 0, p = 1; char ch; do { ch = getchar(); } while (ch <= ); if (ch == - ) { p = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + (ch - 0 ); ch = getchar(); } return x * p; } const int maxN = (int)5e2 + 10; const int INF = (int)1e9; const int mod = (int)1e9 + 7; const long long LLINF = (long long)1e18; long long a[maxN]; int n; bool ok = false; bool bad(int idx) { for (int i = 0; i < idx; ++i) { int r = 0; for (int j = 0; j < n; ++j) { if (((a[i] >> j) & 1) != ((a[idx] >> j) & 1)) { r--; } else { r++; } } if (r != 0) return true; } return false; } int cnt = 0; void print() { ok = 0; for (int i = 0; i < 30; ++i) putchar( - ); putchar( n ); char f[] = { * , + }; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cout << f[(a[i] >> j) & 1]; } cout << n ; } cout << n ; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cout << f[(a[i] >> j) & 1]; if (j == n / 2 - 1) putchar( ); } cout << n ; if (i == n / 2 - 1) putchar( n ); } cout << n ; for (int i = 0; i < 30; ++i) putchar( - ); putchar( n ); } void dfs(int idx, int n) { if (idx == n) { print(); return; } for (long long mask = 0; mask < (1LL << n) && ok; ++mask) { a[idx] = mask; if (bad(idx)) continue; dfs(idx + 1, n); } } char rev(char x) { if (x == + ) return * ; return + ; } vector<vector<char> > build(int k) { vector<vector<char> > ret(1 << k, vector<char>(1 << k, ? )); if (k == 0) { ret[0][0] = * ; return ret; } vector<vector<char> > prev = build(k - 1); int prevsz = (1 << k) / 2; for (int i = 0; i < prevsz; ++i) { for (int j = 0; j < prevsz; ++j) { ret[i][2 * j] = ret[i][2 * j + 1] = prev[i][j]; } } for (int j = prevsz - 1; j >= 0; --j) { for (int i = 0; i < prevsz; ++i) { ret[prevsz + i][2 * j + 1] = prev[i][j]; ret[prevsz + i][2 * j] = rev(prev[i][j]); } } return ret; } int main() { int k; cin >> k; vector<vector<char> > answer = build(k); for (int i = 0; i < answer.size(); ++i) { for (int j = 0; j < answer[i].size(); ++j) { putchar(answer[i][j]); } putchar( n ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapmet1 (
VPWR,
VGND
);
// Module ports
input VPWR;
input VGND;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n; long long a[305], Lcm; long long sol(long long x) { long long cnt = 0; for (long long i = 2; i * i <= x; i++) { if (x % i == 0) { cnt += 2; if (i * i == x) cnt--; } } return cnt; } int main() { int T; cin >> T; while (T--) { int ok = 1; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &a[i]); sort(a, a + n); if (n == 1) Lcm = a[0] * a[0]; else Lcm = a[0] * a[n - 1]; for (int i = 1; i < (n + 1) / 2; i++) { if (a[i] * a[n - 1 - i] != Lcm) { ok = 0; break; } } if (ok && sol(Lcm) == n) printf( %lld n , Lcm); else puts( -1 ); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_TB_V
`define SKY130_FD_SC_LS__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100010; string nick[MAX]; int ara[MAX], ord[MAX], b[MAX]; int save[MAX]; bool cmp(int a, int b) { if (ara[a] == ara[b]) return nick[a] < nick[b]; return ara[a] > ara[b]; } deque<int> D; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n; if (n == 0) { cout << 0 << << 0 << endl; return 0; } for (int i = 1; i <= n; i++) { cin >> nick[i] >> ara[i]; save[i] = ara[i]; } cin >> m; for (int i = 1; i <= m; i++) cin >> b[i], D.push_back(b[i]); sort(D.begin(), D.end()); string s; cin >> s; int id = -1; for (int i = 1; i <= n; i++) { if (s == nick[i]) { if (id == -1) id = i; else assert(false); } } for (int i = 1; i <= n; i++) ord[i] = i; sort(ord + 1, ord + n + 1, cmp); int ans1, ans2; if (m == 0) { for (int i = 1; i <= n; i++) if (ord[i] == id) { ans2 = ans1 = i; break; } cout << ans1 << << ans2 << endl; return 0; } int cur; for (int i = 1; i <= n; i++) if (ord[i] == id) cur = i; if (n == m) { ara[id] += D.front(); D.pop_front(); } int parbo = n - cur; int bad = D.size() - parbo; for (int i = cur - 1; i >= 1 and bad > 0; i--, bad--) { ara[ord[i]] += D.front(); D.pop_front(); } int need; for (int i = cur + 1; i <= n; i++) { need = (ara[id] + 1) - ara[ord[i]]; int paic = 0; while (D.size() > 0) { if (D.front() >= need) { paic = D.front(); D.pop_front(); break; } else D.pop_front(); } ara[ord[i]] += paic; } sort(ord + 1, ord + n + 1, cmp); for (int i = 1; i <= n; i++) if (ord[i] == id) ans2 = i; for (int i = 1; i <= n; i++) ara[i] = save[i]; D.clear(); for (int i = 1; i <= m; i++) D.push_back(b[i]); sort(D.begin(), D.end()); ara[id] += D.back(); D.pop_back(); sort(ord + 1, ord + n + 1, cmp); for (int i = n; i >= 1 and D.size() > 0; i--) { if (ord[i] == id) continue; ara[ord[i]] += D.back(); D.pop_back(); } sort(ord + 1, ord + n + 1, cmp); for (int i = 1; i <= n; i++) if (ord[i] == id) ans1 = i; cout << ans1 << << ans2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const double PI = 3.14159265359; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<int> facts; for (int i = 1; i * i <= n; i++) { if (!(n % i)) { facts.push_back(i); facts.push_back(n / i); } } vector<long long> ans; for (int i : facts) { long long a = (n - 1) / i; ans.push_back(a * (a + 1) * i / 2 + a + 1); } sort(ans.begin(), ans.end()); auto it = unique(ans.begin(), ans.end()); ans.resize(it - ans.begin()); for (auto i : ans) { cout << i << ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LP__LSBUF_PP_SYMBOL_V
/**
* lsbuf: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input DESTPWR,
input DESTVPB,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 2000000000; const long long infLL = 9000000000000000000; template <typename first, typename second> ostream& operator<<(ostream& os, const pair<first, second>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { os << { ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << } ; } template <typename T> ostream& operator<<(ostream& os, const set<T>& v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename T> ostream& operator<<(ostream& os, const multiset<T>& v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename first, typename second> ostream& operator<<(ostream& os, const map<first, second>& v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } void faltu() { cerr << n ; } template <typename T> void faltu(T a[], int n) { for (int i = 0; i < n; ++i) cerr << a[i] << ; cerr << n ; } template <typename T, typename... hello> void faltu(T arg, const hello&... rest) { cerr << arg << ; faltu(rest...); } int n, m; vector<pair<int, int> > vec1[105], vec2[105]; int x[1005], y[1005]; int cnt1[105], cnt2[105]; vector<pair<int, int> > store[105]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m; for (int i = 1; i <= n; ++i) cnt1[i] = cnt2[i] = 1; for (int i = 0; i < m; ++i) { cin >> x[i] >> y[i]; if (x[i] > y[i]) swap(x[i], y[i]); ++cnt1[x[i]]; ++cnt2[y[i]]; } int r1 = 1e6, c1 = 1e6; int r2 = r1 - 1, c2 = c1 + 1; for (int i = 1; i <= n; ++i) { for (int j = 0; j < cnt1[i]; ++j) { vec1[i].push_back(make_pair(r1, c1)); store[i].push_back(make_pair(r1, c1)); ++r1; } for (int j = 0; j < cnt2[i]; ++j) { vec2[i].push_back(make_pair(r2, c2)); store[i].push_back(make_pair(r2, c2)); ++c2; } reverse(vec1[i].begin(), vec1[i].end()); reverse(vec2[i].begin(), vec2[i].end()); store[i].push_back(make_pair(vec1[i].back().first, vec2[i].back().second)); vec1[i].pop_back(); vec2[i].pop_back(); --c1; --r2; } for (int i = 0; i < m; ++i) { assert(!vec1[x[i]].empty()); assert(!vec2[y[i]].empty()); store[x[i]].push_back( make_pair(vec1[x[i]].back().first, vec2[y[i]].back().second)); vec1[x[i]].pop_back(); vec2[y[i]].pop_back(); } for (int i = 1; i <= n; ++i) { cout << (int)store[i].size() << n ; for (auto x : store[i]) cout << x.first << << x.second << n ; } } |
/*
*
* Copyright (c) 2011-2013
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input sys_clk_p,
input sys_clk_n,
input uart_rx,
output uart_tx
);
//-----------------------------------------------------------------------------
// Clock Multiplier
//-----------------------------------------------------------------------------
wire hash_clk;
wire comm_clk;
`ifndef SIM
hashing_clock_multiplier hashing_clock_multiplier_blk (
.clk_in1_p (sys_clk_p),
.clk_in1_n (sys_clk_n),
.tx_hash_clk (hash_clk),
.tx_comm_clk (comm_clk)
);
`else
reg hash_clk_sim = 1'b0;
assign hash_clk = hash_clk_sim;
assign comm_clk = hash_clk_sim;
initial begin
hash_clk_sim = 1'b0;
while (1)
begin
#5 hash_clk_sim = 1'b1; #5 hash_clk_sim = 1'b0;
end
end
`endif
//-----------------------------------------------------------------------------
// DSP48E1 Hasher ---- /*ZTEX Hashers*/
//-----------------------------------------------------------------------------
reg [31:0] nonce = 32'd253, nonce2 = 32'd0;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_dsp48e1_rounds hasher (
.clk (hash_clk),
.rx_data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, comm_data}),
.rx_state (comm_midstate),
.tx_hash (hash),
.tx_midhash ()
);
sha256_dsp48e1_rounds hasher2 (
.clk (hash_clk),
.rx_data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.rx_state (256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.tx_hash (),
.tx_midhash (hash2_w)
);
/*sha256_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash)
);
sha256_pipe123 p2 (
.clk (hash_clk),
.data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash (hash2_w)
);*/
//-----------------------------------------------------------------------------
// Dummy Hasher
//-----------------------------------------------------------------------------
/*reg [31:0] hash2_w;
always @ (posedge hash_clk)
begin
hash2_w <= midstate[31:0] ^ midstate[63:32] ^ midstate[95:64] ^ midstate[127:96] ^ midstate[159:128] ^ midstate[191:160] ^ midstate[223:192] ^ midstate[255:224] ^ data[31:0] ^ data[63:32] ^ data[95:64] ^ nonce;
end*/
`ifdef SIM
reg fake_uart = 1'b1;
reg [15:0] timer = 16'd0;
reg [21:0] sequence = 22'b1100010011010010100001;
always @ (posedge comm_clk)
begin
timer <= timer + 16'd1;
if (timer == 16'd867)
begin
timer <= 0;
{fake_uart, sequence} <= {sequence, 1'b1};
end
end
`endif
//-----------------------------------------------------------------------------
// Communication Module
//-----------------------------------------------------------------------------
wire comm_new_work;
reg is_golden_ticket = 1'b0, buf_is_golden_ticket = 1'b0, buf2_is_golden_ticket = 1'b0;
reg [31:0] golden_ticket, buf_golden_ticket, buf2_golden_ticket;
comm_uart # (
.comm_clk_frequency (100000000),
.baud_rate (115200)
) comm_uart_blk (
.comm_clk (comm_clk),
`ifdef SIM
.uart_rx (fake_uart),
`else
.uart_rx (uart_rx),
`endif
.uart_tx (uart_tx),
.hash_clk (hash_clk),
.rx_new_golden_ticket (buf2_is_golden_ticket),
.rx_golden_ticket (buf2_golden_ticket),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_blockdata (comm_data)
);
//-----------------------------------------------------------------------------
// Control Unit
//-----------------------------------------------------------------------------
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~253 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
// TODO: No longer 253 cycles on DSP based design ... need to update.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 32'd503;
nonce2 <= 32'd0;
end
else
begin
nonce <= nonce + 32'd1;
nonce2 <= nonce2 + 32'd1;
end
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
is_golden_ticket <= hash2_w == 32'hA41F32E7;
if (hash2_w == 32'hA41F32E7)
golden_ticket <= nonce2;
buf_is_golden_ticket <= is_golden_ticket;
buf_golden_ticket <= golden_ticket;
{buf2_is_golden_ticket, buf2_golden_ticket} <= {buf_is_golden_ticket, buf_golden_ticket};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x = 0, xi = INT_MIN, q = 0; vector<int> v; for (int i = 0; i < n; i++) { int y; cin >> y; q = x; v.push_back(y); xi = max(x, v[i]); if (x != q) x = i; } long long ans = 0; for (int i = 0; i < n; i++) { int z = (abs(x - i) + i + x) * 2; ans += (z * v[i]); } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y, long long mod = 2e18) { long long ans = 1; x %= mod; while (y) { if (y & 1) ans = (x * ans) % mod; x = (x * x) % mod; y >>= 1; } return ans; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; cout << setprecision(20); while (t--) { long long n, k; cin >> n >> k; if (n >= 32) { cout << YES << n - 1 << endl; continue; } long long total = (pow(4, n) - 1) / 3; if (k > total) { cout << NO << endl; continue; } long long left; bool f = 0; for (long long i = n; i >= 1; i--) { left = power(2, i + 1) - (i + 2); long long curr = (2 * (i) + 1) * (power(4, n - i) / 3); if (total - curr >= k && k >= left) { cout << YES << n - i << endl; f = 1; break; } } if (!f) cout << NO n ; } return 0; } |
// chris_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
reg [31:0] reg_out;
assign avs_s0_readdata = reg_out;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] reg_value[8:0];
reg led_out;
reg [31:0] reg_status;
reg [31:0] reg_res;
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read&Reg_Status_Write;
assign LEDR = led_out;
reg reg_module_caculation_end;
reg reg_modue_caculating_start;
reg reg_module_end;
reg reg_module_start;
convolution_core instance_convolution(.clk(clock_clk),
.reset(reset_reset),
.value0(reg_value[0]),
.value1(reg_value[1]),
.value2(reg_value[2]),
.value3(reg_value[3]),
.value4(reg_value[4]),
.value5(reg_value[5]),
.value6(reg_value[6]),
.value7(reg_value[7]),
.value8(reg_value[8]),
.caculating_start(reg_modue_caculating_start),
.caculating_done(reg_module_caculation_end),
.res_done(reg_module_end),
.ret(reg_res)
);
reg [3:0] reg_current_status, reg_next_status;
parameter IDLE = 4'b0001;
parameter CALCULATING = 4'b0010;
parameter WAITTING = 4'b0100;
parameter FINISH = 4'b1000;
// machine status
always@(posedge clock_clk)
begin
if(reset_reset)
reg_current_status <= IDLE;
else
reg_current_status <= reg_next_status;
end
// machine's next status
always@(reg_current_status or reg_read_done or reg_module_caculation_end or reg_write_done or reset_reset)
begin
if(reset_reset)
reg_next_status = IDLE;
else
begin
case(reg_current_status)
IDLE:reg_next_status = reg_read_done?CALCULATING:IDLE;
CALCULATING:reg_next_status = reg_module_caculation_end?WAITTING:CALCULATING;
WAITTING:reg_next_status = reg_write_done?FINISH:WAITTING;
FINISH: reg_next_status = IDLE;
default: reg_next_status = IDLE;
endcase
end
end
always@(posedge clock_clk) begin
if (reset_reset) begin
led_out <= 1'b0;
end else begin
case(reg_current_status)
IDLE: begin
reg_module_start<= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
end
CALCULATING: begin
led_out <= 1'b1;
reg_module_start <= 1'b1;
reg_modue_caculating_start <= 1'b1;
end
WAITTING:begin
reg_modue_caculating_start <= 1'b0;
reg_module_end <= 1'b1;
end
FINISH:begin
reg_module_start <= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
led_out <= 1'b0;
end
default:begin
end
endcase
end
end
// WRITE LOGIC
//
reg reg_read_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Write <= 1'b1;
reg_value[0] <= 32'h00000000;
reg_value[1] <= 32'h00000000;
reg_value[2] <= 32'h00000000;
reg_value[3] <= 32'h00000000;
reg_value[4] <= 32'h00000000;
reg_value[5] <= 32'h00000000;
reg_value[6] <= 32'h00000000;
reg_value[7] <= 32'h00000000;
reg_value[8] <= 32'h00000000;
reg_read_done <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
case (avs_s0_address[3:0])
4'b0000: reg_value[0] <= avs_s0_writedata;
4'b0001: reg_value[1] <= avs_s0_writedata;
4'b0010: reg_value[2] <= avs_s0_writedata;
4'b0011: reg_value[3] <= avs_s0_writedata;
4'b0100: reg_value[4] <= avs_s0_writedata;
4'b0101: reg_value[5] <= avs_s0_writedata;
4'b0110: reg_value[6] <= avs_s0_writedata;
4'b0111: reg_value[7] <= avs_s0_writedata;
4'b1000:begin
reg_value[8] <= avs_s0_writedata;
reg_read_done <= 1'b1; // read done;
end
endcase
Reg_Status_Write <= 1'b1;
end else if (avs_s0_waitrequest && avs_s0_write && reg_module_start == 1'b0)begin
Reg_Status_Write <= 1'b0;
end else begin
//revert reg_read_done to 0 at here when it's done /
if(reg_module_end) begin
reg_read_done <= 1'b0;
end
Reg_Status_Write <= 1'b1;
end
//
// x and z values are don't-care's
// READ LOGIC
reg reg_write_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b1;
reg_write_done <= 1'b1;
end else if(avs_s0_waitrequest && avs_s0_read && reg_module_caculation_end) begin
case (avs_s0_address[3:0])
4'b0000: reg_out <= reg_value[0];
4'b0001: reg_out <= reg_value[1];
4'b0010: reg_out <= reg_value[2];
4'b0011: reg_out <= reg_value[3];
4'b0100: reg_out <= reg_value[4];
4'b0101: reg_out <= reg_value[5];
4'b0110: reg_out <= reg_value[6];
4'b0111: reg_out <= reg_value[7];
4'b1000: reg_out <= reg_value[8];
4'b1001: reg_out <= reg_res;
default:reg_out <= 32'hffffffff;
endcase
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b1;
if (reg_module_end) begin
reg_write_done <= 1'b0;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_top.v
// Version : 2.3
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tstrb, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tstrb, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tstrb( m_axis_rx_tstrb ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tstrb( s_axis_tx_tstrb ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_phy_10g
*/
module test_eth_phy_10g_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000/6.4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg [DATA_WIDTH-1:0] xgmii_txd = 0;
reg [CTRL_WIDTH-1:0] xgmii_txc = 0;
reg [DATA_WIDTH-1:0] serdes_rx_data = 0;
reg [HDR_WIDTH-1:0] serdes_rx_hdr = 1;
reg tx_prbs31_enable = 0;
reg rx_prbs31_enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] xgmii_rxd;
wire [CTRL_WIDTH-1:0] xgmii_rxc;
wire [DATA_WIDTH-1:0] serdes_tx_data;
wire [HDR_WIDTH-1:0] serdes_tx_hdr;
wire serdes_rx_bitslip;
wire [6:0] rx_error_count;
wire rx_bad_block;
wire rx_block_lock;
wire rx_high_ber;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
xgmii_txd,
xgmii_txc,
serdes_rx_data,
serdes_rx_hdr,
tx_prbs31_enable,
rx_prbs31_enable
);
$to_myhdl(
xgmii_rxd,
xgmii_rxc,
serdes_tx_data,
serdes_tx_hdr,
serdes_rx_bitslip,
rx_error_count,
rx_bad_block,
rx_block_lock,
rx_high_ber
);
// dump file
$dumpfile("test_eth_phy_10g_64.lxt");
$dumpvars(0, test_eth_phy_10g_64);
end
eth_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[111111]; int main() { int n, m; cin >> n >> m; vector<int> a; for (int i = 0; i < n; i++) { int x; cin >> x; a.push_back(x); } reverse(a.begin(), a.end()); set<int> b; for (int i = 0; i < n; i++) { if (b.find(a[i]) == b.end()) dp[n - i - 1]++; if (i == n - 1) break; dp[n - i - 2] = dp[n - i - 1]; b.insert(a[i]); } for (int i = 0; i < m; i++) { int x; cin >> x; cout << dp[x - 1] << n ; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:55 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_3/bram_1024_3_stub.v
// Design : bram_1024_3
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_1024_3(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A2BB2OI_PP_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_PP_SYMBOL_V
|
module anteconmutador (
input clk,
input [7:0] count,
input calculate,
output reg [3:0] centenas,
output reg [3:0] decenas,
output reg [3:0] unidades,
output reg C,
output reg De,
output reg U
);
reg [7:0] digitT;
reg i;
initial
begin
digitT = 0;
C = 0;
De = 0;
U = 0;
centenas = 0;
decenas = 0;
unidades = 0;
i = 1;
end
always@(posedge clk)
begin
if(calculate)
begin
if(i)
begin
digitT = count;
i = 0;
end
if(digitT>7'b1100011)
begin
digitT = digitT - 7'b1100100;
centenas = centenas + 1;
end
else
begin
if(digitT>7'b0001001)
begin
digitT = digitT - 7'b0001010;
decenas = decenas + 1;
end
else
begin
unidades = {digitT[3:0]};
if(centenas >= 1)
begin
C = 1;
end
if(decenas >= 1)
begin
De = 1;
end
if(unidades >= 1)
begin
U = 1;
end
end
end
end
else
begin
if(!calculate)
begin
digitT = 0;
C = 0;
De = 0;
U = 0;
i = 1;
centenas = 0;
decenas = 0;
unidades = 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> const double PI = 3.141592653589793238460; using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { long long int n; cin >> n; long long int a[n], i, sum = 0, maxi = -1000000000, mini = 1000000000; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > maxi) maxi = a[i]; else if (a[i] < mini) mini = a[i]; } for (i = 0; i < n - 1; i++) { long long int pro = a[i] * a[i + 1]; if (pro > sum) { sum = pro; } } cout << sum << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long fac[200001]; long long inv[200001]; long long modexp(long long b, long long e) { long long ans = 1; while (e > 0) { if (e & 1) { ans = (ans * b) % mod; } b = (b * b) % mod; e >>= 1; } return ans; } long long comb(long long n, long long k) { long long ans = (fac[n] * inv[k]) % mod; ans = (ans * inv[n - k]) % mod; return ans; } int main() { fac[0] = fac[1] = 1; inv[0] = inv[1] = 1; for (int i = 2; i <= 200000; i++) { fac[i] = (fac[i - 1] * i) % mod; inv[i] = modexp(fac[i], mod - 2); } int n, k; cin >> n >> k; vector<pair<int, int> > list; for (int i = 1; i <= n; i++) { int a, b; cin >> a >> b; list.push_back(make_pair(a, 1)); list.push_back(make_pair(b + 1, -1)); } sort(list.begin(), list.end()); int maintain = 0; long long ans = 0; int selisih; for (int i = 0; i < list.size(); i++) { if (i > 0 && list[i].first != list[i - 1].first) { if (maintain >= k) { ans += comb(maintain, k) * (list[i].first - selisih); ans %= mod; } } maintain += list[i].second; selisih = list[i].first; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 10010; vector<int> v[MAXN]; int childcnt[MAXN] = {0}; int main() { int n; cin >> n; for (int i = 1; i < n; i++) { int a, b; scanf( %d%d , &a, &b); v[a].push_back(b); v[b].push_back(a); } int root = 0; for (int i = 1; i <= n; i++) { if (v[i].size() == 1) { root = i; break; } } bool vis[MAXN]; memset(vis, false, sizeof(vis)); queue<int> q; q.push(root); vis[root] = true; int deep = 0; long long ans = 0; while (!q.empty()) { childcnt[deep++] = q.size(); queue<int> p; while (!q.empty()) { int cur = q.front(); q.pop(); int len = v[cur].size(); int cnt = 0; for (int i = 0; i < len; i++) { if (!vis[v[cur][i]]) { vis[v[cur][i]] = true; p.push(v[cur][i]); cnt++; } } ans += (cnt - 1) * cnt / 2; } q = p; } for (int i = 2; i < deep; i++) { ans += childcnt[i]; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int NMAX = 100005; int A[NMAX]; int main() { ios::sync_with_stdio(false); int n; cin >> n; bool ok = true; if (n % 2 == 1) { if ((n - 1) % 4 == 0) { for (int i = 1; i <= n / 2; i += 2) { A[i] = i + 1; A[i + 1] = n - i + 1; A[n - i + 1] = n - i; A[n - i] = i; } A[n / 2 + 1] = n / 2 + 1; } else { ok = false; } } else { if (n % 4 == 0) { for (int i = 1; i <= n / 2; i += 2) { A[i] = i + 1; A[i + 1] = n - i + 1; A[n - i + 1] = n - i; A[n - i] = i; } } else { ok = false; } } if (!ok) { cout << -1 n ; } else { for (int i = 1; i <= n; ++i) { cout << A[i] << ; } cout << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; bool IO_FILE = 0; ifstream ifs( input.txt ); ofstream ofs( output.txt ); int main() { if (IO_FILE) { cin.rdbuf(ifs.rdbuf()); cout.rdbuf(ofs.rdbuf()); } int n, m; cin >> n >> m; char *s = new char[m]; bool res = 1; char prev = E ; for (int i = 0; i < n; i++) { cin >> s; char p = s[0]; res = 1; if (prev != E && p == prev) { res = 0; break; } for (int j = 1; j < m; j++) if (!(res = s[j] == p)) break; if (!res) break; prev = p; } cout << (res ? YES : NO ); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_FUNCTIONAL_V |
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: chan_mux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module chan_mux (
data0x,
data1x,
data2x,
sel,
result);
input [21:0] data0x;
input [21:0] data1x;
input [21:0] data2x;
input [1:0] sel;
output [21:0] result;
wire [21:0] sub_wire0;
wire [21:0] sub_wire4 = data2x[21:0];
wire [21:0] sub_wire3 = data1x[21:0];
wire [21:0] result = sub_wire0[21:0];
wire [21:0] sub_wire1 = data0x[21:0];
wire [65:0] sub_wire2 = {sub_wire4, sub_wire3, sub_wire1};
lpm_mux LPM_MUX_component (
.data (sub_wire2),
.sel (sel),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 3,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 22,
LPM_MUX_component.lpm_widths = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "22"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: data0x 0 0 22 0 INPUT NODEFVAL "data0x[21..0]"
// Retrieval info: USED_PORT: data1x 0 0 22 0 INPUT NODEFVAL "data1x[21..0]"
// Retrieval info: USED_PORT: data2x 0 0 22 0 INPUT NODEFVAL "data2x[21..0]"
// Retrieval info: USED_PORT: result 0 0 22 0 OUTPUT NODEFVAL "result[21..0]"
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
// Retrieval info: CONNECT: @data 0 0 22 0 data0x 0 0 22 0
// Retrieval info: CONNECT: @data 0 0 22 22 data1x 0 0 22 0
// Retrieval info: CONNECT: @data 0 0 22 44 data2x 0 0 22 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: CONNECT: result 0 0 22 0 @result 0 0 22 0
// Retrieval info: GEN_FILE: TYPE_NORMAL chan_mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL chan_mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL chan_mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL chan_mux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL chan_mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL chan_mux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int arr[int(1e7 + 100)]; void aum(int i) { if (i % 2) { arr[i / 2 + 1] += arr[i]; arr[i / 2] += arr[i]; } else arr[i / 2] += 2 * arr[i]; } int main() { ios_base::sync_with_stdio(0); set<int> conj; memset(arr, 0, sizeof arr); int n, m, l, ans = int(2 * 1e9 + 100), ptr = 0; cin >> n >> m; long long cnt = n, carry = 0, slices = m; for (int i = 0; i < n; ++i) { cin >> l; carry += l; ++arr[l]; } if (carry < m) { cout << -1 n ; return 0; } for (int i = int(1e7 + 100); cnt < m; --i) { if (arr[i]) { aum(i); cnt += arr[i]; arr[i] = 0; } } long long aux = 0; for (int i = int(1e7 + 100); i >= 1; --i) { if (arr[i]) { conj.insert(i); aux += arr[i]; if (aux >= m) { ans = i; break; } } } for (int i = int(1e7 + 100); i >= 1; --i) { if (arr[i]) { int go = (i % 2 == 1 ? 1 : 0); if (i / 2 + go <= *(conj.begin())) { break; } else { aum(i); if (i % 2) conj.insert(i / 2 + 1); conj.insert(i / 2); conj.erase(i); aux += arr[i]; while (1) { int val = (*conj.begin()); if (aux - arr[val] < m) break; aux -= arr[val]; conj.erase(conj.begin()); } } } } cout << max(1, *(conj.begin())) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; long long int mul(long long int x, long long int y) { return (x * 1ll * y) % mod; } long long int add(long long int x, long long int y) { x += y; while (x >= mod) x -= mod; while (x < 0) x += mod; return x; } long long int dp[200005][3]; long long int a, b, c; long long int n, l, r; long long int fun(int i, int j) { if (i == n) { if (j == 0) return 1; else return 0; } if (dp[i][j] != -1) return dp[i][j]; dp[i][j] = add( mul(a, fun(i + 1, (j) % 3)), add(mul(b, fun(i + 1, (j + 1) % 3)), mul(c, fun(i + 1, (j + 2) % 3)))); return dp[i][j]; } int main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> n >> l >> r; long long int x = (l - 1 + 2) / 3; long long int y = (r - 1) / 3; b = y - x + 1; x = (l - 2 + 2) / 3; y = (r - 2) / 3; c = y - x + 1; x = (l + 2) / 3; y = (r) / 3; a = y - x + 1; if (l == 1 && r == 1) { a = 0, b = 1, c = 0; } memset(dp, -1, sizeof(dp)); long long int ans = 0; ans = add(ans, mul(a, fun(1, 0))); ans = add(ans, mul(b, fun(1, 1))); ans = add(ans, mul(c, fun(1, 2))); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int k, m, n1, n2; cin >> n1 >> n2 >> k >> m; vector<int> a(n1); for (int i = 0; i < a.size(); ++i) cin >> a[i]; vector<int> b(n2); for (int i = 0; i < b.size(); ++i) cin >> b[i]; if (a[k - 1] < b[n2 - m]) cout << YES n ; else cout << NO n ; return 0; } |
#include bits/stdc++.h using namespace std; #define all(x) x.begin(),x.end() #define pb push_back #define ff first #define ss second #define fast ios::sync_with_stdio(0);cin.tie(0);cout.tie(0) #define ar array #define int long long #define F(i,a,b) for(i=a;i<b;++i) #define RF(i,b,a) for(i=b;i>=a;--i) #define NL cout<< n ; #define INF LONG_LONG_MAX #define pii pair<int,int> #define vi vector<int> typedef long long ll; typedef long double ld; const ll mod=1e9+7; bool comp(ll a,ll b) { return a<b; } ll fpow(ll a, ll b) { ll res=1; while(b) { if(b&1) res=(res*a); a=(a*a); b>>=1; } return res; } ll minm(ll a,ll b){ if(a<b) return a; return b; } ll maxm(ll a,ll b){ if(a>b){ return a;} else return b; } int PHI(int k){ // This is Euler s Totient Function. //This function returns no. of coprime numbers to N in range [1,2,....,N] int ans=k; for(int i=2;i*i<=k;++i){ if(k%i==0){ ans-=ans/i; while(k%i==0){ k/=i; } } } if(k>1) ans-=ans/k; return ans; } void solve(){ int n,i; cin >> n; vector<pii>ecells; vector<pii>ocells; for(i=1;i<=n;i++){ for(int j=1;j<=n;j++){ if((i+j)%2){ ocells.pb({i,j}); } else ecells.pb({i,j}); } } // 1 even // 2,3 odd // if not possible ie all odd are filled, fill 2,3 in even int cnt=0; while(cnt<n*n){ int a; cin >> a; if(a==1){ // try to fill 2 in odd cell // if not possible , fill 3 in even if(ocells.empty()){ cout<< 3 <<ecells.back().ff<< <<ecells.back().ss<<endl; ecells.pop_back(); } else{ cout<< 2 <<ocells.back().ff<< <<ocells.back().ss<<endl; ocells.pop_back(); } ++cnt; } else if(a==2){ // fill 1 in even , if possible if(!ecells.empty()){ cout<< 1 <<ecells.back().ff<< <<ecells.back().ss<<endl; ecells.pop_back(); } else{ // fill 3 in ocells cout<< 3 <<ocells.back().ff<< <<ocells.back().ss<<endl; ocells.pop_back(); } cnt++; } else{ // fill 1 in even if possible if(!ecells.empty()){ cout<< 1 <<ecells.back().ff<< <<ecells.back().ss<<endl; ecells.pop_back(); } else{ // fill 2 in odd cout<< 2 <<ocells.back().ff<< <<ocells.back().ss<<endl; ocells.pop_back(); } cnt++; } } } signed main(void) { fast; int _=1; //cin>>_; for(int test_case=1;test_case<=_;++test_case){ solve(); } } |
#include <bits/stdc++.h> using namespace std; int vis[100005], mark[100005]; vector<int> g[100005]; int prob = 0; void dfs(int node, int k) { mark[node] = k; vis[node] = 1; for (auto i : g[node]) { if (!vis[i]) { dfs(i, 1 - k); } else { if (mark[i] == k) { prob = 1; } } } } int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; scanf( %d , &u); scanf( %d , &v); g[u].push_back(v); g[v].push_back(u); } for (int i = 1; i <= n; i++) { if (!vis[i]) dfs(i, 0); } if (prob) { cout << -1 ; return 0; } int k = 0; for (int i = 1; i <= n; i++) { if (mark[i] == 1) k++; } cout << k << n ; for (int i = 1; i <= n; i++) { if (mark[i] == 1) cout << i << ; } cout << n ; k = 0; for (int i = 1; i <= n; i++) { if (mark[i] == 0) k++; } cout << k << n ; for (int i = 1; i <= n; i++) { if (mark[i] == 0) cout << i << ; } return 0; } |
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// Combinational paths from inputs to outputs:
// read_rs1_rs1 -> read_rs1
// read_rs1_port2_rs1 -> read_rs1_port2
// read_rs2_rs2 -> read_rs2
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkGPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ;
// value method read_rs1_port2
assign read_rs1_port2 =
(read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ;
// value method read_rs2
assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_reset_loop ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs2_rs2 ;
assign regfile$ADDR_2 = read_rs1_port2_rs1 ;
assign regfile$ADDR_3 = read_rs1_rs1 ;
assign regfile$ADDR_4 = 5'h0 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = write_rd_rd ;
assign regfile$D_IN = write_rd_rd_val ;
assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkGPR_RegFile
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, x = 0, y; cin >> n; y = n * n / 2.0 + n / 2.0; cout << 6 * y + 1; return 0; } |
(**********************************************************************)
(* Equations *)
(* Copyright (c) 2009-2020 Matthieu Sozeau <> *)
(**********************************************************************)
(* This file is distributed under the terms of the *)
(* GNU Lesser General Public License Version 2.1 *)
(**********************************************************************)
From Coq Require Import Extraction CRelationClasses.
Require Import Equations.Init Equations.CoreTactics.
Set Warnings "-notation-overridden".
Require Import Equations.Type.Logic Equations.Type.Relation
Equations.Type.Relation_Properties Equations.Type.WellFounded.
Set Universe Polymorphism.
Import Id_Notations.
(** A class for well foundedness proofs.
Instances can be derived automatically using [Derive Subterm for ind]. *)
Class WellFounded {A : Type} (R : relation A) :=
wellfounded : well_founded R.
(** This class contains no-cyclicity proofs.
They can be derived from well-foundedness proofs for example.
*)
(** The proofs of [NoCycle] can be arbitrarily large, it doesn't
actually matter in the sense that they are used to prove
absurdity. *)
Cumulative
Class NoCyclePackage@{i|} (A : Type@{i}) :=
{ NoCycle : A -> A -> Type@{i};
noCycle : forall {a b}, NoCycle a b -> (a = b -> Empty) }.
(** These lemmas explains how to apply it during simplification. *)
(** We always generate a goal of the form [NoCycle x C[x]], using either
the left or right versions of the following lemma. *)
Lemma apply_noCycle_left@{i j|} {A : Type@{i}} {noconf : NoCyclePackage A}
(p q : A) {B : p = q -> Type@{j}} :
NoCycle@{i} p q -> (forall H : p = q, B H).
Proof.
intros noc eq. destruct (noCycle noc eq).
Defined.
Lemma apply_noCycle_right@{i j|} {A : Type@{i}} {noconf : NoCyclePackage A}
(p q : A) {B : p = q -> Type@{j}} :
NoCycle q p -> (forall H : p = q, B H).
Proof.
intros noc eq. destruct (noCycle noc (id_sym eq)).
Defined.
Extraction Inline apply_noCycle_left apply_noCycle_right.
(** NoCycle can be decided using the well-founded subterm relation. *)
Definition NoCycle_WellFounded {A} (R : relation A) (wfR : WellFounded R) : NoCyclePackage A :=
{| NoCycle := R;
noCycle := WellFounded.well_founded_irreflexive (wfR:=wfR) |}.
#[export]
Existing Instance NoCycle_WellFounded.
#[export]
Hint Extern 30 (@NoCycle ?A (NoCycle_WellFounded ?R ?wfr) _ _) =>
hnf; typeclasses eauto with subterm_relation : typeclass_instances.
(** The NoConfusionPackage class provides a method for solving injectivity and discrimination
of constructors, represented by an equality on an inductive type [I]. The type of [noConfusion]
should be of the form [ Π Δ, (x y : I Δ) (x = y) -> NoConfusion x y ], where
[NoConfusion x y] for constructor-headed [x] and [y] will give equality of their arguments
or the absurd proposition in case of conflict.
This gives a general method for simplifying by discrimination or injectivity of constructors.
Some actual instances are defined later in the file using the more primitive [discriminate] and
[injection] tactics on which we can always fall back.
*)
Cumulative Class NoConfusionPackage@{i|} (A : Type@{i}) := {
NoConfusion : A -> A -> Type@{i};
noConfusion : forall {a b}, NoConfusion a b -> Id a b;
noConfusion_inv : forall {a b}, Id a b -> NoConfusion a b;
noConfusion_sect : forall {a b} (e : NoConfusion a b), Id (noConfusion_inv (noConfusion e)) e;
noConfusion_retr : forall {a b} (e : Id a b), Id (noConfusion (noConfusion_inv e)) e;
}.
(** This lemma explains how to apply it during simplification. *)
Polymorphic
Lemma apply_noConfusion@{i j|} {A : Type@{i}} {noconf : NoConfusionPackage A}
(p q : A) {B : Id p q -> Type@{j}} :
(forall e : NoConfusion p q, B (noConfusion e)) -> (forall e : Id p q, B e).
Proof.
intros. generalize (noConfusion_retr e). destruct e.
intros eq. destruct eq. apply X.
Defined.
Extraction Inline apply_noConfusion.
(** Classes for types with UIP or decidable equality. *)
Class UIP@{i|} (A : Type@{i}) := uip : forall {x y : A} (e e' : x = y), e = e'.
#[export]
Instance UIP_hSet (A : Type) (H : HSet A) : UIP A := H.
Definition dec_eq {A} (x y : A) : Type := (x = y) + (x <> y).
Class EqDec@{i|} (A : Type@{i}) := eq_dec : forall x y : A, sum@{i} (x = y) (x = y -> Empty).
Class EqDecPoint (A : Type) (x : A) := eq_dec_point : forall y : A, (x = y) + (x <> y).
#[export]
Instance EqDec_EqDecPoint A `(EqDec A) (x : A) : EqDecPoint A x := eq_dec x.
(** For treating impossible cases. Equations corresponding to impossible
calls form instances of [ImpossibleCall (f args)]. *)
Class ImpossibleCall@{i} {A : Type@{i}} (a : A) : Type@{i} :=
is_impossible_call : False.
(** We have a trivial elimination operator for impossible calls. *)
Definition elim_impossible_call {A} (a : A) {imp : ImpossibleCall a} (P : A -> Type) : P a :=
match is_impossible_call with end.
(** The tactic tries to find a call of [f] and eliminate it. *)
Ltac impossible_call f := on_call f ltac:(fun t => apply (elim_impossible_call t)).
(** The [FunctionalInduction f] typeclass is meant to register functional induction
principles associated to a function [f]. Such principles are automatically
generated for definitions made using [Equations]. *)
Polymorphic
Class FunctionalInduction {A : Type} (f : A) :=
{ fun_ind_prf_ty : Type; fun_ind_prf : fun_ind_prf_ty }.
Register FunctionalInduction as equations.funind.class.
(** The [FunctionalElimination f] class declares elimination principles produced
from the functional induction principle for [f] to be used directly to eliminate
a call to [f]. This is the preferred method of proving results about a function.
[n] is the number of binders for parameters, predicates and methods of the
eliminator.
*)
Polymorphic
Class FunctionalElimination {A : Type} (f : A) (fun_elim_ty : Type) (n : nat) :=
fun_elim : fun_elim_ty.
Register FunctionalElimination as equations.funelim.class.
|
#include <bits/stdc++.h> using namespace std; int sti(const string &s) { int x; stringstream ss(s); ss >> x; return x; } string its(const int &x) { string s; stringstream ss(s); ss << x; s = ss.str(); } void sscan(string &str) { str = ; char str_c; scanf( %c , &str_c); while (!(str_c == n || str_c == )) { str += str_c; scanf( %c , &str_c); } } void sprint(const string &str) { int length = str.length(); for (int i = 0; i < length; ++i) printf( %c , str[i]); } uint64_t fact(int x) { if (x < 2) return 1; return fact(x - 1) * x; } uint64_t C(int x, int y) { uint64_t c = 1; for (int i = 0; i < y; ++i) { c *= x - i; c /= i + 1; } return c; } int main() { int n, m, t; scanf( %d %d %d , &n, &m, &t); uint64_t res = 0; for (int i = 4; i <= n && i < t; ++i) { if (t - i > m) continue; res += C(n, i) * C(m, t - i); } printf( %I64u , res); return 0; } |
#include <bits/stdc++.h> void stderr_printf(const char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } using namespace std; struct flist { int val; int pos; }; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int i, j, k; int n; cin >> n; ; int stage = 0; bool ans = true; cin >> j; ; for (i = 0; i < n - 1; i++) { int cur; cin >> cur; ; if (stage == 0) { if (cur == j) { stage = 1; } else if (cur < j) { stage = 2; } else if (cur > j) { stage = 0; } } else if (stage == 1) { if (cur == j) { stage = 1; } else if (cur < j) { stage = 2; } else if (cur > j) { ans = false; } } else { if (cur >= j) { ans = false; } } j = cur; } if (ans) { printf( YES n ); } else { printf( NO n ); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 17; int N, Q; int main() { ios_base::sync_with_stdio(false); cin >> Q; while (Q--) { cin >> N; long long mx; cin >> mx; long long diff = 0; while (--N) { long long x; cin >> x; mx = max(mx, x); diff = max(diff, mx - x); } long long ans = 0; while (diff) { ans++; diff >>= 1; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long rdtsc() { long long tmp; asm( rdtsc : =A (tmp)); return tmp; } inline int myrand() { return abs((rand() << 15) ^ rand()); } inline int rnd(int x) { return myrand() % x; } const int INF = (int)1e9 + 1; const long double EPS = 1e-9; void precalc() {} struct Line { int a, b, c; int id; int read(int _id) { id = _id; if (scanf( %d%d%d , &a, &b, &c) < 3) { return 0; } return 1; } }; long long gcd(long long a, long long b) { for (; b; a %= b, swap(a, b)) ; return a; } struct Ratio { long long a, b; Ratio() {} Ratio(long long _a, long long _b) : a(_a), b(_b) { assert(b != 0ll); normalize(); } void normalize() { long long d = gcd(a, b); a /= d, b /= d; if (b < 0) { a = -a, b = -b; } } inline bool operator<(const Ratio &r) const { if (a != r.a) { return a < r.a; } return b < r.b; } inline bool operator==(const Ratio &r) const { return a == r.a && b == r.b; } }; struct Point { Ratio x, y; Point() {} Point(Ratio _x, Ratio _y) : x(_x), y(_y) {} inline bool operator<(const Point &p) const { if (x == p.x) { return y < p.y; } return x < p.x; } inline bool operator==(const Point &p) const { return x == p.x && y == p.y; } }; bool inter(const Line &l1, const Line &l2, Point &res) { long long D = (long long)l1.a * l2.b - (long long)l1.b * l2.a; if (D == 0ll) { return 0; } long long Dx = (long long)l1.b * l2.c - (long long)l1.c * l2.b; long long Dy = (long long)l1.c * l2.a - (long long)l1.a * l2.c; res = Point(Ratio(Dx, D), Ratio(Dy, D)); return 1; } int n, k; const int maxn = (int)1e5 + 10; Line lines[maxn]; bool read() { if (scanf( %d%d , &n, &k) < 2) { return 0; } for (int i = 0; i < n; ++i) { lines[i].read(i); } return 1; } const int maxk = 5; int ans[maxk][2]; int res; Line tmp[maxn]; int used[maxn]; bool gen(int pos, int k) { if (pos == n) { return 1; } if (used[pos]) { return gen(pos + 1, k); } if (k == 0) { return 0; } { ans[res][0] = lines[pos].id + 1, ans[res][1] = -1; ++res; if (gen(pos + 1, k - 1)) { return 1; } --res; } int oks[n]; Point ps[maxk * maxk + 5]; for (int j = pos + 1; j < n; ++j) { oks[j] = 0; if (used[j]) { continue; } Point p; if (!inter(lines[pos], lines[j], p)) { continue; } oks[j] = 1; ps[j] = p; } int tmp[n]; for (int j = pos + 1; j < n; ++j) { if (!oks[j]) { continue; } ans[res][0] = lines[pos].id + 1, ans[res][1] = lines[j].id + 1; ++res; for (int k = pos + 1; k < n; ++k) { tmp[k] = used[k]; if (!oks[k]) { continue; } if (ps[j] == ps[k]) { used[k] += 1; oks[k] = 0; } } if (gen(pos + 1, k - 1)) { return 1; } --res; for (int k = pos + 1; k < n; ++k) { used[k] = tmp[k]; } } return 0; } bool solveSmall() { random_shuffle(lines, lines + n, rnd); for (int i = 0; i < n; ++i) { used[i] = 0; } return gen(0, k); } void solve() { res = 0; while (n > k * k && k > 0) { const int K = 250; pair<Point, pair<int, int> > ps[K]; int cnt = 0; bool ok = 0; for (int iter = 0; iter < K; ++iter) { int x = rnd(n), y = rnd(n); Point p; if (x == y || !inter(lines[x], lines[y], p)) { continue; } ps[cnt++] = make_pair(p, make_pair(x, y)); } sort(ps, ps + cnt); Point p; int x, y; bool found = 0; for (int i = 0; i < cnt;) { int i0 = i; while (i < cnt && ps[i].first == ps[i0].first) { ++i; } if (i - i0 > k) { found = 1; p = ps[i0].first; x = ps[i0].second.first, y = ps[i0].second.second; break; } } if (!found) { printf( NO n ); return; } { int cnt = 0, cntp = 0; for (int i = 0; i < n; ++i) { Point q; if (!inter(lines[i], lines[i == x ? y : x], q)) { continue; } if (q == p) { ++cntp; } else { tmp[cnt++] = lines[i]; } } assert(cntp > k); ans[res][0] = lines[x].id + 1, ans[res][1] = lines[y].id + 1; ++res; for (int i = 0; i < cnt; ++i) { lines[i] = tmp[i]; } n = cnt; --k; } } if (solveSmall()) { printf( YES n ); printf( %d n , res); for (int i = 0; i < res; ++i) { printf( %d %d n , ans[i][0], ans[i][1]); } } else { printf( NO n ); } } int main() { srand(rdtsc()); precalc(); while (1) { if (!read()) { break; } solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int num[maxn]; long long ret; int n; void init() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &num[i]); } void print() { for (int i = 1; i < n; i++) { int j = 0; for (; j < 30; j++) if (i + (1 << j) > n) break; j--; ret += num[i]; num[i + (1 << j)] += num[i]; printf( %I64d n , ret); } } int main() { init(); print(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> prim; const int N = 1e5 + 9; int n, dp[10000], a[N]; bool v[100000]; int pos[100000]; void pre() { for (int i = 2; i < 100000; i++) if (!v[i]) { prim.push_back(i); pos[i] = prim.size() - 1; int k = i << 1; while (k < 100000) v[k] = 1, k += i; } } int main() { pre(); int ans = 1; cin >> n; for (int i = 1, now; i <= n; i++) { cin >> now; int org = now; int tmp = 0; for (int j = 0; j < 100; j++) if (now % prim[j] == 0) { while (now % prim[j] == 0) now /= prim[j]; tmp = max(tmp, dp[j] + 1); } if (now > 1) tmp = max(tmp, dp[pos[now]] + 1); for (int j = 0; j < 100; j++) if (org % prim[j] == 0) { while (org % prim[j] == 0) org /= prim[j]; dp[j] = tmp; } if (org > 1) dp[pos[now]] = tmp; ans = max(ans, tmp); } cout << ans << endl; return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file lut_xilinx.v when simulating
// the core, lut_xilinx. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module elut_xilinx(
a,
d,
dpra,
clk,
we,
qdpo_clk,
qdpo_rst,
dpo,
qdpo
);
input [5 : 0] a;
input [0 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
input qdpo_clk;
input qdpo_rst;
output [0 : 0] dpo;
output [0 : 0] qdpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0"),
.C_DEPTH(64),
.C_FAMILY("virtex6"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(1),
.C_HAS_DPRA(1),
.C_HAS_I_CE(0),
.C_HAS_QDPO(1),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(1),
.C_HAS_QDPO_RST(1),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(0),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("no_coe_file_loaded"),
.C_MEM_TYPE(4),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(0),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(1)
)
inst (
.A(a),
.D(d),
.DPRA(dpra),
.CLK(clk),
.WE(we),
.QDPO_CLK(qdpo_clk),
.QDPO_RST(qdpo_rst),
.DPO(dpo),
.QDPO(qdpo),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QSPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.SPO(),
.QSPO()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> const int MOD = 1000000007; int64_t dp[2001][2001]; int main() { int n, m, k; std::cin >> n >> m >> k; dp[0][0] = 1; for (int i = 1; i <= 2000; ++i) { dp[i][0] = 1; for (int j = 1; j < i; ++j) { dp[i][j] = (dp[i - 1][j - 1] + dp[i - 1][j]) % MOD; } dp[i][i] = 1; } std::cout << (dp[n - 1][2 * k] * dp[m - 1][2 * k]) % MOD << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MXN = 1e6 + 1; const long long MNN = 1e3 + 1; const long long MOD = 1e9 + 7; const long long INF = 1e18; const long long MAGIC = 1000; const long double EPS = 1e-9; const long double PI = 3.1415926536; const string TIME = rovno_ushten_push_ketti ; long long n; long long cnt[MXN]; set<long long> s; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (long long i = 1; i <= n; ++i) { long long x; cin >> x; s.insert(x); ++cnt[x]; } if (s.size() == 2) { long long x = *s.begin(); s.erase(s.begin()); long long y = *s.begin(); if (cnt[x] == cnt[y]) { cout << YES n ; cout << x << << y; } else { cout << NO ; } } else { cout << NO ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int man = 2e5 + 10; const long long mod = 1e9 + 7; struct edge { int v; int w; int next; } e[man << 1]; int head[man]; int cnt; void init(int n) { memset(head, 0, sizeof(int) * (n + 5)); cnt = 0; } void add(int u, int v, int w) { e[++cnt].next = head[u]; e[cnt].v = v; e[cnt].w = w; head[u] = cnt; } int vis[man]; int dfs(int u, int fa) { int num = 0; int cnt = 0; for (int i = head[u]; i; i = e[i].next) { if (e[i].v == fa) continue; ++cnt; int tp = dfs(e[i].v, u); num += tp; vis[i] = tp; } if (!cnt) num++; return num; } struct node { long long w; int cnt, va; bool operator<(const node &a) const { return 1ll * (va / 2 + va % 2) * cnt < 1ll * (a.va / 2 + a.va % 2) * a.cnt; } }; signed main() { int t; scanf( %d , &t); while (t--) { int n; long long s = 0; long long sum = 0; scanf( %d%lld , &n, &s); for (int i = 1; i < n; ++i) { int u, v, w; scanf( %d%d%d , &u, &v, &w); add(u, v, w); add(v, u, w); } dfs(1, 1); priority_queue<node> q; for (int i = 1; i <= cnt; ++i) { if (vis[i] == 0) continue; sum += 1ll * e[i].w * vis[i]; q.push(node{1ll * e[i].w * vis[i], vis[i], e[i].w}); } if (sum <= s) { cout << 0 << n ; } else { int cnt = 0; while (q.size()) { node tp = q.top(); q.pop(); ++cnt; int tpva = tp.va / 2 + tp.va % 2; sum -= 1ll * tpva * tp.cnt; tp.va -= tpva; tp.w = 1ll * tp.cnt * tp.va; if (tp.va) q.push(tp); if (sum <= s) break; } cout << cnt << n ; } memset(vis, 0, sizeof(int) * (cnt + 5)); init(n); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 105; int N, M; int A[MAXN]; int ans[MAXN][MAXN]; void gen(int x) { if (x <= 2) { for (int i = 0; i < x; i++) { A[i] = 3 + i; } return; } else if (x == 3) { A[0] = 1; A[1] = A[2] = 2; return; } if (x % 2) { A[0] = x - 2; fill(A + 1, A + x, 2); } else { A[0] = x / 2 - 1; fill(A + 1, A + x, 1); } } int main() { if (fopen( input.txt , r )) { freopen( input.txt , r , stdin); } ios::sync_with_stdio(false); cin >> N >> M; gen(M); for (int i = 0; i < N; i++) { copy_n(A, M, ans[i]); } gen(N); for (int j = 0; j < M; j++) { for (int i = 0; i < N; i++) { ans[i][j] *= A[i]; } } for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { cout << ans[i][j] << ; } cout << n ; } } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The 1cyc_sram_ctrl module control the 1 Cycle SRAM access requests
//
// ====================================================================
module sirv_1cyc_sram_ctrl #(
parameter DW = 32,
parameter MW = 4,
parameter AW = 32,
parameter AW_LSB = 3,
parameter USR_W = 3
)(
output sram_ctrl_active,
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 1
// // This register is our self-defined CSR register to disable the
// ITCM SRAM clock gating for debugging purpose
input tcm_cgstop,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// * Cmd channel
input uop_cmd_valid, // Handshake valid
output uop_cmd_ready, // Handshake ready
input uop_cmd_read, // Read or write
input [AW-1:0] uop_cmd_addr,
input [DW-1:0] uop_cmd_wdata,
input [MW-1:0] uop_cmd_wmask,
input [USR_W-1:0] uop_cmd_usr,
// * RSP channel
output uop_rsp_valid, // Response valid
input uop_rsp_ready, // Response ready
output [DW-1:0] uop_rsp_rdata,
output [USR_W-1:0] uop_rsp_usr,
output ram_cs,
output ram_we,
output [AW-AW_LSB-1:0] ram_addr,
output [MW-1:0] ram_wem,
output [DW-1:0] ram_din,
input [DW-1:0] ram_dout,
output clk_ram,
input test_mode,
input clk,
input rst_n
);
sirv_gnrl_pipe_stage # (
.CUT_READY(0),
.DP(1),
.DW(USR_W)
) u_e1_stage (
.i_vld(uop_cmd_valid),
.i_rdy(uop_cmd_ready),
.i_dat(uop_cmd_usr),
.o_vld(uop_rsp_valid),
.o_rdy(uop_rsp_ready),
.o_dat(uop_rsp_usr),
.clk (clk ),
.rst_n(rst_n)
);
assign ram_cs = uop_cmd_valid & uop_cmd_ready;
assign ram_we = (~uop_cmd_read);
assign ram_addr= uop_cmd_addr [AW-1:AW_LSB];
assign ram_wem = uop_cmd_wmask[MW-1:0];
assign ram_din = uop_cmd_wdata[DW-1:0];
wire ram_clk_en = ram_cs | tcm_cgstop;
e203_clkgate u_ram_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (ram_clk_en),
.clk_out (clk_ram)
);
assign uop_rsp_rdata = ram_dout;
assign sram_ctrl_active = uop_cmd_valid | uop_rsp_valid;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1000001]; int main() { int n, v = 0; cin >> n; sprintf(s, %X , n); for (int i = 0; i < strlen(s); i++) { if (s[i] == 0 || s[i] == 4 || s[i] == 6 || s[i] == 9 || s[i] == A || s[i] == D ) v++; else if (s[i] == 8 || s[i] == B ) v += 2; } cout << v << endl; return 0; } |
`timescale 1ns / 1ps
module spdif_tx_t;
reg [23:0] simple_increment_ff;
reg [23:0] simple_increment_ff2;
parameter TCLK = 40;
parameter TCLK_DAI = 10;
reg clk;
reg clk_dai;
reg rst;
reg [1:0] ack_i;
reg [47:0] data_i;
spdif_tx uut(
.clk(clk), .rst(rst),
.ack_i(ack_i), .data_i(data_i),
.udata_i(192'b0), .cdata_i(192'b0));
spdif_dai dai(
.clk(clk), .rst(rst),
.clk_per_halfbit(4),
.signal_i(uut.spdif_o)
);
integer i;
initial begin
`ifndef NODUMP
$dumpfile("spdif_tx_t.lxt");
$dumpvars(0, spdif_tx_t);
`endif
simple_increment_ff = 0;
simple_increment_ff2 = 24'hffffff;
uut.data_latch = 48'b0;
uut.subframe_shiftreg = 28'b0;
clk = 1'b0;
clk_dai = 1'b0;
ack_i = 2'b00;
rst = 1'b0;
#TCLK;
rst = 1'b1;
#TCLK;
rst = 1'b0;
#TCLK;
`ifndef NODUMP
#500_000;
$finish(2);
`endif
end
always #(TCLK/2) clk = ~clk;
always #(TCLK_DAI/2) clk_dai = ~clk_dai;
always @(posedge uut.pop_o[0]) begin
#(TCLK);
data_i[47:24] = simple_increment_ff;
simple_increment_ff = simple_increment_ff + 1;
if (simple_increment_ff == 256)
$finish(2);
ack_i[1] = 1;
#(TCLK);
ack_i[1] = 0;
end
always @(posedge uut.pop_o[1]) begin
#(TCLK);
data_i[23:0] = 24'habcdef;//simple_increment_ff2;
simple_increment_ff2 = simple_increment_ff2 - 1;
ack_i[0] = 1;
#(TCLK);
ack_i[0] = 0;
end
always @(posedge clk_dai) begin
if(dai.ack_o) begin
$display("data_o: %x", dai.data_o);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long a, b, c, d; cin >> a >> b >> c >> d; bool prob[5]; for (bool& i : prob) { i = true; } if ((a == 0 && b == 0) || (a + b) % 2 == 0) { prob[1] = prob[2] = false; if (a == 0 && d == 0) { prob[4] = false; } else if (b == 0 && c == 0) { prob[3] = false; } } else { prob[3] = prob[4] = false; if (a == 0 && d == 0) { prob[1] = false; } else if (b == 0 && c == 0) { prob[2] = false; } } for (int i = 1; i <= 4; i++) { cout << (prob[i] ? Ya : Tidak ); } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, counter = 0, max = 1, a, b = -1; cin >> n; for (int i = 0; i < n; i++) { a = b; cin >> b; if (b >= a) { counter++; } else { if (counter > max) { max = counter; } counter = 1; } if (counter > max) { max = counter; } } cout << max << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int SIZE = 100005; const int MSIZE = 10000; const int INF = 1 << 30; set<int>::iterator it; int main() { int n, a, b; int p[SIZE]; set<int> fi, se; map<int, int> mp; bool flag[SIZE]; while (cin >> n >> a >> b) { fi.clear(), se.clear(), mp.clear(); memset(flag, 0, sizeof(flag)); for (int i = 0; i < n; i++) { scanf( %d , &p[i]); fi.insert(p[i]); mp[p[i]] = i; } vector<int> v; for (it = fi.begin(); it != fi.end(); it++) { if (fi.find(a - *it) == fi.end()) { se.insert(*it); v.push_back(*it); } } for (int i = 0; i < v.size(); i++) { fi.erase(v[i]); se.insert(v[i]); } bool mark = 0; while (!se.empty()) { it = se.begin(); int x = *it; if (se.find(b - x) != se.end()) { flag[mp[x]] = flag[mp[b - x]] = 1; se.erase(x); if ((x)*2 != b) se.erase(b - x); } else if (fi.find(b - x) != fi.end()) { flag[mp[x]] = flag[mp[b - x]] = 1; fi.erase(b - x); se.erase(x); if ((b - x) * 2 != a) { fi.erase(a - (b - x)); se.insert(a - (b - x)); } } else { puts( NO ); mark = 1; break; } } if (mark) continue; puts( YES ); for (int i = 0; i < n; i++) printf( %d , flag[i]); puts( ); } } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MAX = 1 << 20; bitset<MAX> dpgl, mv, dp[20]; map<char, int> to; char rv[20]; int cnt[20], le[20], ri[20], n, A, B, b; void solve(int ms) { int L = 1e9, R = -1, tot = 0; vector<int> tr, chr, oth; for(int i = 0; i < b; i++) { if(ms & (1 << i)) { L = min(L, le[i]); R = max(R, ri[i]); tot += cnt[i]; chr.push_back(i); if(dp[i][ms ^ (1 << i)]) dp[i][ms] = dpgl[ms] = 1; } else oth.push_back(i); } if(tot >= ((R - L + 1) * A + B - 1) / B) mv[ms] = 1; if(oth.empty()) return; sort(chr.begin(), chr.end(), [&](int a, int b){ return le[a] < le[b]; }); int cms = 0; for(auto c : chr) { cms |= (1 << c); if(mv[cms] && dpgl[cms] && dp[oth[0]][ms ^ cms]) { for(auto tc : oth) dp[tc][ms] = 1; return; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> A >> B; string s; cin >> s; for(auto &c : s) { if(!to.count(c)) { rv[b] = c; to[c] = b++; } } for(int i = 0; i < s.size(); i++) { cnt[to[s[i]]]++; ri[to[s[i]]] = i; } for(int i = s.size() - 1; i >= 0; i--) le[to[s[i]]] = i; dpgl[0] = mv[0] = 1; for(int i = 0; i < b; i++) { dp[i][0] = dp[i][1 << i] = 1; dpgl[1 << i] = 1; } for(int i = 1; i < (1 << b); i++) solve(i); vector<char> ans; for(int i = 0; i < b; i++) if(dp[i][(1 << b) - 1]) ans.push_back(rv[i]); sort(ans.begin(), ans.end()); cout << ans.size(); for(auto &c : ans) cout << << c; cout << n ; /*for(int i = 0; i < (1 << b); i++) { for(int j = 0; j < b; j++) cout << bitset<4>(i) << << j << << dp[j][i] << n ; } cout << n ;*/ } |
#include <bits/stdc++.h> using namespace std; int n, m, tmp = 1; int sum(int a) { int res = 0; while (a) { res += a % 10; a /= 10; } return res; } int main() { cin >> n >> m; if (2 * n > 2220) { int nn = n / 2 + n % 2; for (int i = 1; i <= nn; ++i) { cout << 2; } cout << endl; for (int i = 1; i <= nn - 1; ++i) { cout << 7; } cout << 8 << endl; return 0; } for (int i = 1; i <= n; ++i) { cout << 1; } cout << endl; for (int i = 1; i <= n - 1; ++i) { cout << 8; } cout << 9 << endl; } |
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [`WIDTH_D0:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [`WIDTH_D0:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
/* for ROM */
wire [8:0] rom_addr;
wire [27:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select
select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
rom
rom0 (clk, rom_addr, rom_q);
FSM
fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
const_
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
muxer
muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
PE
pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[`WIDTH:0], muxer0_out[`WIDTH:0], ram_b_data_in[`WIDTH:0]);
assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
endmodule
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
module muxer(from_ram, from_const, const_effective, out);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double e = 1e-2; int k; long double R, r, l; long double x, y, xl, yl, xr, yr; long double a, b, c, S; long double COS[12], SIN[12]; bool check(long double x, long double y) { long double s = 0; for (int i = 0; i < 12; i += 2) s = max(s, ((x + COS[i]) * (x + COS[i])) + ((y + SIN[i]) * (y + SIN[i]))); return s <= l + r; } bool end(long double x, long double y) { long double s = 1e+60; for (int i = 0; i < 12; i += 2) s = min(s, ((x + COS[i]) * (x + COS[i])) + ((y + SIN[i]) * (y + SIN[i]))); return s > S; } int main() { R = 1; r = sqrt(((R) * (R)) - ((0.5) * (0.5))); for (int i = 0; i < 12; i++) { COS[i] = cos(((i * 30) * M_PI / 180)); SIN[i] = sin(((i * 30) * M_PI / 180)); } scanf( %d , &k); l = k; l *= l; S = k + 3; S *= S; x = (k + 2) / 3 * 3 * COS[2]; y = (k + 2) / 3 * 3 * SIN[2]; xl = xr = x; yl = yr = y; long long ans = 0; do { long double s; s = y * xr - x * yr; while (s > 0 && abs(s) > e && !check(xr, yr)) { xr += 2 * r * COS[5]; yr += 2 * r * SIN[5]; s = y * xr - x * yr; } while (check(xr, yr)) { xr -= 2 * r * COS[5]; yr -= 2 * r * SIN[5]; } s = y * xl - x * yl; while (s < 0 && abs(s) > e && !check(xl, yl)) { xl += 2 * r * COS[11]; yl += 2 * r * SIN[11]; s = y * xl - x * yl; } while (check(xl, yl)) { xl -= 2 * r * COS[11]; yl -= 2 * r * SIN[11]; } long double L = sqrt(((xl - xr) * (xl - xr)) + ((yl - yr) * (yl - yr))); ans += max((long long)((L + r) / (2 * r)) - 1, 0LL); xl += 2 * r * COS[7]; yl += 2 * r * SIN[7]; xr += 2 * r * COS[9]; yr += 2 * r * SIN[9]; } while (!end(xr, yr) || !end(xl, yl)); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2; const int MO = 1e9 + 7; const int K = 5e8 + 4; struct Matrix { int a[N][N]; Matrix(bool ident = 0) { for (int i = int(0); i <= int((N)-1); i++) for (int j = int(0); j <= int((N)-1); j++) a[i][j] = 0; if (ident) { for (int i = int(0); i <= int((N)-1); i++) a[i][i] = 1; } } int *operator[](int i) { return a[i]; } const int *operator[](int i) const { return a[i]; } }; void add(int &x, int y) { x += y; if (x >= MO) x -= MO; } Matrix operator*(const Matrix &a, const Matrix &b) { Matrix c; for (int i = int(0); i <= int((N)-1); i++) for (int j = int(0); j <= int((N)-1); j++) for (int k = int(0); k <= int((N)-1); k++) { add(c[i][j], 1LL * a[i][k] * b[k][j] % MO); } return c; } Matrix powd(Matrix a, long long b) { Matrix ans(1); while (b) { if (b & 1) ans = ans * a; a = a * a; b >>= 1; } return ans; } int powd(int a, long long b) { int ans = 1; while (b) { if (b & 1) ans = 1LL * ans * a % MO; b >>= 1; a = 1LL * a * a % MO; } return ans; } int main() { Matrix magic; magic[0][0] = magic[1][0] = 1, magic[0][1] = 2; int n; cin >> n; Matrix now = magic; int down = 2; for (int i = int(0); i <= int((n)-1); i++) { long long x; scanf( %I64d , &x); now = powd(now, x); down = powd(down, x); } cout << 1LL * now[1][1] * K % MO << / << 1LL * down * K % MO << endl; return 0; } |
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module instantiates all the logic necessary to form tiles
and pipelines them using block RAM. In addition, it breaks out an
interface for a module higher in the design hierarchy.
*/
`include "DeepGATE_include.v"
module tile_network (
input clk_i,
input en_i, //active high, initiates processing
input [7:0] data_i, //input data
input data_rd_i, //active high, signals reading of network output data
output wire data_rd_o, //active high, signals the module is reading data_i
output wire network_idle_o, //active high if ready to accept input
output wire [7:0] data_o, //network output data
output wire proc_complete_o, //active high, indicates processing is complete
input [7:0] weight_data_i,
input [NUM_TILES - 1'b1 : 0] weight_wr_i,
output wire [NUM_TILES - 1'b1 : 0] pipeline_lock_o
);
`include "param_include.v"
genvar i,j;
generate
for(i = 0; i < NUM_TILES; i = i + 1) begin: TILES
parameter [31:0] TILE_SIZE = TILE_SIZE_ARRAY[`ID32(i)];
parameter [31:0] TILE_LOOP = TILE_LOOP_ARRAY[`ID32(i)];
parameter [31:0] TILE_PRV_SIZE = TILE_PRV_SIZE_ARRAY[`ID32(i)];
parameter [31:0] TILE_PRV_LOOP = TILE_PRV_LOOP_ARRAY[`ID32(i)];
parameter [31:0] TILE_NXT_LOOP = TILE_NXT_LOOP_ARRAY[`ID32(i)];
parameter [31:0] TILE_BIAS = TILE_BIAS_ARRAY[`ID32(i)];
wire [TILE_SIZE*WEIGHT_WIDTH - 1'b1:0] weight_bus;
wire en;
wire ram_wr;
wire ram_rd;
wire proc_unit_rst;
wire ram_full;
wire data_available;
wire [7:0] tile_data;
wire [7:0] buffer_data;
wire [$clog2(TILE_SIZE) - 1'b1:0] sig_mux_sel;
//if first tile, connect idle and route data_available to module port
if(i == 0) begin
tile_control #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.PRV_SIZE (TILE_PRV_SIZE),
.PRV_LOOP (TILE_PRV_LOOP)
)
TILE_CONTROL(
.clk_i (clk_i),
.rst_i (1'd0),
.data_available_i (en_i),
.ram_full_i (ram_full),
.pipeline_lock_i (pipeline_lock_o[i]),
.en_o (en),
.ram_wr_o (ram_wr),
.idle_o (network_idle_o),
.ram_rd_o (ram_rd),
.proc_unit_rst_o (proc_unit_rst),
.sig_mux_sel_o (sig_mux_sel)
);
end
else begin
tile_control #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.PRV_SIZE (TILE_PRV_SIZE),
.PRV_LOOP (TILE_PRV_LOOP)
)
TILE_CONTROL(
.clk_i (clk_i),
.rst_i (1'b0),
.data_available_i (TILES[PREV_INDEX[`ID32(i)]].data_available),
.ram_full_i (ram_full),
.pipeline_lock_i (pipeline_lock_o[i]),
.en_o (en),
.ram_wr_o (ram_wr),
.ram_rd_o (ram_rd),
.proc_unit_rst_o (proc_unit_rst),
.sig_mux_sel_o (sig_mux_sel)
);
end
tile_datapath #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.PRV_SIZE (TILE_PRV_SIZE),
.PRV_LOOP (TILE_PRV_LOOP),
.BIAS (TILE_BIAS),
.WEIGHT_WIDTH (WEIGHT_WIDTH)
)
TILE_DATA(
.clk_i (clk_i),
.rst_i (proc_unit_rst),
.en_i (en),
.weight_bus_i (weight_bus),
.sig_mux_sel_i (sig_mux_sel),
.data_i (i == 0 ? data_i[`ID8(0)] : TILES[PREV_INDEX[`ID32(i)]].buffer_data), //simplifies to TILES[i-1].buffer_data
.data_o (tile_data)
);
weight_RAM #(
.SIZE (TILE_SIZE_ARRAY[`ID32(i)]),
.MAX_DEPTH (MEM_MAX_DEPTH_ARRAY[`ID32(i)]),
.DIVIDER (MEM_DIVIDER_ARRAY[`ID32(i)]),
.WEIGHT_WIDTH (WEIGHT_WIDTH)
)
weight_RAM(
.clk_i (clk_i),
.rd_i (ram_rd),
.wr_i (weight_wr_i[i]),
.data_i (weight_data_i),
.pipeline_lock_o (pipeline_lock_o[i]),
.data_o (weight_bus)
);
if(i != NUM_TILES - 1'b1) begin //connect read signal differently for last layer
parameterized_RAM #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP),
.NXT_LOOP (TILE_NXT_LOOP)
)
TILE_BUFFER(
.clk_i (clk_i),
.rd_i (TILES[NEXT_INDEX[`ID32(i)]].ram_rd),
.wr_i (ram_wr),
.data_i (tile_data),
.data_o (buffer_data),
.ram_full_o (ram_full),
.data_available_o (data_available)
);
end
else begin
parameterized_RAM_last #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP)
)
TILE_BUFFER(
.clk_i (clk_i),
.rd_i (data_rd_i),
.wr_i (ram_wr),
.data_i (tile_data),
.data_o (data_o),
.ram_full_o (ram_full),
.data_available_o (proc_complete_o)
);
/*
output_arbiter #(
.SIZE (TILE_SIZE),
.LOOP (TILE_LOOP)
)
outputBuffer(
.clk (clk_i),
.read (data_rd_i),
.write (transfer),
.data_i (activatedData),
.data_o (networkOut),
.ramFull (ramFull),
.dataAvailable (proc_complete_o)
);
*/
end
end
endgenerate
assign data_rd_o = TILES[0].ram_rd;
endmodule
|
module keyed_permutation #(
parameter UNIT_WIDTH = 1
)(
input wire i_clk,
input wire [`$NUNITS`*UNIT_WIDTH-1:0] i_dat,
input wire [`$NUNITS`*INDEX_WIDTH-1:0] i_key,
input wire i_inverse,
output reg [`$NUNITS`*UNIT_WIDTH-1:0] o_dat
);
localparam NUNITS = `$NUNITS`;
localparam INDEX_WIDTH = `$INDEX_WIDTH`;
localparam KEY_WIDTH = `$KEY_WIDTH`;
function [INDEX_WIDTH-1:0] get_nth_zero_index;
input [NUNITS-1:0] in;
input [INDEX_WIDTH-1:0] index;
integer i;
reg [INDEX_WIDTH-1:0] zero_index;
reg [INDEX_WIDTH-1:0] out;
begin
out = {INDEX_WIDTH{1'bx}};
zero_index = 0;
for(i=0;i<NUNITS;i=i+1) begin
if(~in[i]) begin
if(index==zero_index) begin
out = i;
end
zero_index = zero_index + 1;
end
end
get_nth_zero_index = out;
end
endfunction
function [NUNITS*INDEX_WIDTH-1:0] compute_map;
input [KEY_WIDTH-1:0] key;
reg [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS-1:0] done;
reg [INDEX_WIDTH-1:0] outPos;
reg [NUNITS-1:0] outDone;
reg [8:0] pos;
reg [INDEX_WIDTH-1:0] index;
``if {$COMPACT_KEY} {``
begin
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
``
set remaining [expr $NUNITS-1]
for {set i 0} {$i<$NUNITS} {incr i} {
set indexWidth [binWidth $remaining]
``
index = {INDEX_WIDTH{1'b0}};
``if {$i!=$NUNITS-1} {``
index = key[pos+:`$indexWidth`] % `expr $remaining + 1`;
pos = pos + `$indexWidth`;
``}``
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
//map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=`$i`;
map[`$i`*INDEX_WIDTH+:INDEX_WIDTH]=outPos;//better synthesis results on FPGA
``
incr remaining -1
}``
``} else {``
integer i;
reg [INDEX_WIDTH:0] remaining;
begin
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
remaining = NUNITS;
for(i=0;i<NUNITS;i=i+1) begin
index = {INDEX_WIDTH{1'b0}};
if(i!=NUNITS-1) begin
index = key[pos+:INDEX_WIDTH] % remaining;
remaining = remaining - 1;
pos = pos + INDEX_WIDTH;
end
outPos = get_nth_zero_index(outDone,index);
outDone[outPos]=1'b1;
map[i*INDEX_WIDTH+:INDEX_WIDTH]=outPos;
end
``}``
compute_map = map;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] permute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[i*UNIT_WIDTH+:UNIT_WIDTH] = in[index*UNIT_WIDTH+:UNIT_WIDTH];
end
permute = out;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] unpermute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[index*UNIT_WIDTH+:UNIT_WIDTH] = in[i*UNIT_WIDTH+:UNIT_WIDTH];
end
unpermute = out;
end
endfunction
reg [NUNITS*INDEX_WIDTH-1:0] map;
always @(posedge i_clk) begin
map <= compute_map(i_key);
o_dat <= i_inverse ? unpermute(i_dat,map) : permute(i_dat,map);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int dx[] = {0, 1, 0, -1}, dy[] = {1, 0, -1, 0}; int powmod(int a, int b) { int tmp = 1; a %= (1000000007); for (; b; b >>= 1) { if (b & 1) tmp = tmp * a % (1000000007); a = a * a % (1000000007); } return tmp; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <class T> inline void R(T &xx) { xx = 0; char ch = getchar(); bool F = 0; while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) F = 1, ch = getchar(); while (ch >= 0 && ch <= 9 ) xx = xx + xx + (xx << 3) + ch - 48, ch = getchar(); if (F) xx = -xx; } template <class T> inline void add(int &x, T y) { for (x += y; x >= (1000000007); x -= (1000000007)) ; } int n, k, a[5011], f[5011][2222][2], ans; int main() { R(n); R(k); for (int i = 1; i <= n; i++) R(a[i]); f[0][0][0] = 1; for (int i = 1; i <= n; i++) { if (a[i] == 0 || a[i] == 2) for (int j = 0; j < (int)2049; j++) { int p = min(j + 2, 2048); add(f[i][p][1], f[i - 1][j][1]); add(f[i][p][0], f[i - 1][j][0]); } if (a[i] == 0 || a[i] == 4) for (int j = 0; j < (int)2049; j++) { int p = min(j + 4, 2048); if (j % 4) add(f[i][4][j >= (1 << k)], f[i - 1][j][0]), add(f[i][4][1], f[i - 1][j][1]); else add(f[i][p][0], f[i - 1][j][0]), add(f[i][p][1], f[i - 1][j][1]); } } for (int i = 0; i < (int)2049; i++) { add(ans, f[n][i][1]); if (i >= (1 << k)) add(ans, f[n][i][0]); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; vector<int> v; vector<bool> b; vector<int> u; vector<int> s; vector<int> t(m, 0); for (int i = 0; i < n + m; i++) { long long x; cin >> x; v.push_back(x); } for (int i = 0; i < n + m; i++) { long long x; cin >> x; b.push_back(x); } for (int i = 0; i < n + m; i++) { if (b[i]) s.push_back(v[i]); else u.push_back(v[i]); } for (int i = 0; i < u.size(); i++) { long long x, y; y = (upper_bound(s.begin(), s.end(), u[i]) - s.begin()); if (y == 0) t[0]++; else if (y == m) t[m - 1]++; else { x = y - 1; if (abs(s[y] - u[i]) >= abs(s[x] - u[i])) t[x]++; else t[y]++; } } for (int i = 0; i < m; i++) cout << t[i] << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; typedef struct cell { long long mx, pref, suf, total; } cell; int tam[55], vet[300000]; long long sum[55], preffix[55], suffix[55], best[55], v[300000]; long long getMax(int n) { long long ret = -1000000000000000000LL, aux = 0LL; for (int i = 0; i < n; i++) { aux += v[i]; ret = max(ret, aux); if (aux < 0) aux = 0LL; } return ret; } cell solve(int b, int e) { cell r; if (b == e) { r.mx = best[vet[b]]; r.total = sum[vet[b]]; r.pref = preffix[vet[b]]; r.suf = suffix[vet[b]]; return r; } int m = (b + e) / 2; cell p1, p2; p1 = solve(b, m); p2 = solve(m + 1, e); r.mx = max(max(p1.mx, p2.mx), p1.suf + p2.pref); r.total = p1.total + p2.total; r.pref = max(p1.pref, p1.total + p2.pref); r.suf = max(p2.suf, p1.suf + p2.total); return r; } int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> tam[i]; for (int j = 0; j < tam[i]; j++) { cin >> v[j]; } best[i] = getMax(tam[i]); sum[i] = 0LL; preffix[i] = suffix[i] = -1000000000000000000LL; for (int j = 0; j < tam[i]; j++) { sum[i] += v[j]; preffix[i] = max(preffix[i], sum[i]); } sum[i] = 0LL; for (int j = tam[i] - 1; j >= 0; j--) { sum[i] += v[j]; suffix[i] = max(suffix[i], sum[i]); } } for (int i = 0; i < m; i++) { cin >> vet[i]; vet[i]--; } cell ans = solve(0, m - 1); cout << ans.mx << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { multiset<long long> x, y; long long n, closing = 0, count = 0, i, j, pair = 0; cin >> n; string ss; for (i = 0; i < n; i++) { stack<char> s; closing = 0; cin >> ss; for (j = 0; j < ss.length(); j++) { if (ss[j] == ) && s.size() == 0) closing++; if (ss[j] == ( ) s.push(ss[j]); if (ss[j] == ) && s.size() != 0) s.pop(); } if (closing == 0 && s.size() > 0) x.insert(s.size()); if (closing > 0 && s.size() == 0) y.insert(closing); if (closing == 0 && s.size() == 0) count++; } for (auto i : x) { if (y.find(i) != y.end()) { pair++; y.erase(y.find(i)); } } cout << pair + count / 2; } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, m, x, y, f[N], fa[N], ch[N][2]; char op[5]; long long a[N], siz[N], ssiz[N], ans[N], sans[N], sqsiz[N], all[N]; bool isroot(int u) { return ch[fa[u]][0] != u && ch[fa[u]][1] != u; } int which(int u) { return u == ch[fa[u]][1]; } void pushup(int o) { int lc = ch[o][0], rc = ch[o][1]; siz[o] = siz[lc] + siz[rc] + ssiz[o]; all[o] = all[lc] + all[rc] + a[o] * ssiz[o]; ans[o] = ans[lc] + ans[rc] + sans[o]; ans[o] += (ssiz[o] * ssiz[o] - sqsiz[o]) * a[o]; ans[o] += 2 * siz[rc] * ssiz[o] * a[o]; ans[o] += 2 * all[lc] * (siz[o] - siz[lc]); } void rotate(int x) { int y = fa[x], z = fa[y], md = which(x); if (!isroot(y)) { ch[z][which(y)] = x; } fa[x] = z; ch[y][md] = ch[x][!md]; fa[ch[y][md]] = y; ch[x][!md] = y; fa[y] = x; pushup(y); pushup(x); } void splay(int u) { while (!isroot(u)) { if (!isroot(fa[u])) { rotate(which(u) == which(fa[u]) ? fa[u] : u); } rotate(u); } } void access(int u) { for (int v = 0; u; v = u, u = fa[u]) { splay(u); int rc = ch[u][1]; ssiz[u] += siz[rc]; sans[u] += ans[rc]; sqsiz[u] += siz[rc] * siz[rc]; ch[u][1] = v; ssiz[u] -= siz[v]; sans[u] -= ans[v]; sqsiz[u] -= siz[v] * siz[v]; pushup(u); } } void link(int u, int v) { access(v); splay(v); access(u); splay(u); fa[u] = v; ssiz[v] += siz[u]; sans[v] += ans[u]; sqsiz[v] += siz[u] * siz[u]; pushup(v); } void cut(int u, int v) { access(u); access(v); splay(v); splay(u); fa[u] = 0; ssiz[v] -= siz[u]; sans[v] -= ans[u]; sqsiz[v] -= siz[u] * siz[u]; pushup(v); } bool check(int u, int v) { access(v); splay(v); splay(u); if (isroot(v)) { return false; } return true; } int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) { scanf( %d , &f[i]); } for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); ans[i] = all[i] = a[i]; } for (int i = 1; i <= n; i++) { siz[i] = 1; ssiz[i] = 1; } for (int i = 2; i <= n; i++) { link(i, f[i]); } access(1); splay(1); printf( %.10lf n , 1.0 * ans[1] / n / n); scanf( %d , &m); while (m--) { scanf( %s%d%d , op, &x, &y); if (op[0] == P ) { if (check(x, y)) { swap(x, y); } cut(x, f[x]); f[x] = y; link(x, f[x]); access(1); splay(1); printf( %.10lf n , 1.0 * ans[1] / n / n); } else { access(x); splay(x); a[x] = y; pushup(x); printf( %.10lf n , 1.0 * ans[x] / n / n); } } return 0; } |
#include <bits/stdc++.h> using namespace std; void swapll(long long *a, long long *b) { long long tmp = *a; *a = *b; *b = tmp; } void swapc(char *a, char *b) { char tmp = *a; *a = *b; *b = tmp; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, t; cin >> n; cin >> t; vector<long long> v(n, 0); for (long long i = 0; i < n; i++) cin >> v[i]; ; long long count = 0; for (long long i = 0; i < n; i++) { t -= (86400 - v[i]); count++; if (t <= 0) { break; } } cout << count << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long nxt[45][3], lnk[45], pre[45][3]; string s; long long n; pair<long long, long long> sh[45][45][2]; long long dp[41][41][41][41][2]; long long sol(long long i, long long pre, long long l, long long r, long long f = 0) { if (pre == s.size()) f = 1; if (r - l + 1 == s.size()) f = 1; if (i == n) { if (f) return 1; string final; if (pre) final = s.substr(0, pre); if (r - l + 1) final += s.substr(l, r - l + 1); if (final.find(s) != string::npos) { return 1; } return 0; } if (~dp[i][pre][l][r][f]) return dp[i][pre][l][r][f]; if (r - l + 1 == i) dp[i][pre][l][r][f] = sol(i + 1, nxt[pre][0], sh[l][r][0].first, sh[l][r][0].second, f) + sol(i + 1, nxt[pre][1], sh[l][r][1].first, sh[l][r][1].second, f); else dp[i][pre][l][r][f] = sol(i + 1, nxt[pre][0], l, r, f) + sol(i + 1, nxt[pre][1], l, r, f); return dp[i][pre][l][r][f]; } void solve() { cin >> n; cin >> s; for (long long i = 0; i < s.size(); i++) { if (i > 1) { lnk[i] = nxt[lnk[i - 1]][s[i - 1] - 0 ]; } for (long long j = 0; j < 2; j++) { if (s[i] == j + 0 ) nxt[i][j] = i + 1; else if (i > 0) { nxt[i][j] = nxt[lnk[i]][j]; } } } for (long long i = 0; i < s.size(); i++) { for (long long j = 0; j < s.size(); j++) { for (long long k = 0; k < 2; k++) { string pt; if (j >= i) pt += s.substr(i, j - i + 1); pt.push_back(k + 0 ); long long x = s.find(pt); if (x != string::npos) sh[i][j][k] = {x, x + j - i + 1}; else sh[i][j][k] = {i, j}; } } } if (s.size() == 1) { long long x = s.back() - 0 ; sh[1][0][x] = {0, 0}; sh[1][0][!x] = {1, 0}; } memset(dp, -1, sizeof dp); cout << sol(0, 0, 1, 0, 0) << endl; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); long long t = 1; while (t--) { solve(); } return 0; } |
/*
Copyright 2011 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
performance counter hardware
7.7.2011
*/
module mod_pmc(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout, pmc_int, pmc_cache_miss_I, pmc_cache_miss_D, pmc_cache_access_I, pmc_cache_access_D, pmc_uart_recv, pmc_uart_send);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
input pmc_int, pmc_cache_miss_I, pmc_cache_miss_D, pmc_cache_access_I, pmc_cache_access_D, pmc_uart_recv, pmc_uart_send;
/* the counter events */
reg [31:0] count_int;
reg [31:0] count_cache_miss_I;
reg [31:0] count_cache_miss_D;
reg [31:0] count_cache_access_I;
reg [31:0] count_cache_access_D;
reg [31:0] count_uart_recv;
reg [31:0] count_uart_send;
assign iout = 0;
assign dout =
daddr == 32'h00000000 ? count_int :
daddr == 32'h00000004 ? count_cache_miss_I :
daddr == 32'h00000008 ? count_cache_miss_D :
daddr == 32'h0000000c ? count_cache_access_I :
daddr == 32'h00000010 ? count_cache_access_D :
daddr == 32'h00000014 ? count_uart_recv :
daddr == 32'h00000018 ? count_uart_send : 0;
/* all data bus activity is negative edge triggered */
always @(negedge clk) begin
if (rst) begin
count_int <= 0;
count_cache_miss_I <= 0;
count_cache_miss_D <= 0;
count_cache_access_I <= 0;
count_cache_access_D <= 0;
count_uart_recv <= 0;
count_uart_send <= 0;
end else begin
count_int <= count_int + pmc_int;
count_cache_miss_I <= count_cache_miss_I + pmc_cache_miss_I;
count_cache_miss_D <= count_cache_miss_D + pmc_cache_miss_D;
count_cache_access_I <= count_cache_access_I + pmc_cache_access_I;
count_cache_access_D <= count_cache_access_D + pmc_cache_access_D;
count_uart_recv <= count_uart_recv + pmc_uart_recv;
count_uart_send <= count_uart_send + pmc_uart_send;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR4_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef SMV
`include "ovl_ported/std_ovl_defines.h"
`else
`include "std_ovl_defines.h"
`endif
`module ovl_next (clock, reset, enable, num_cks, start_event, test_expr, fire, fire_comb);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter check_overlapping = 1;
parameter check_missing_start = 0;
parameter num_cks_max = 7;
parameter num_cks_width = 3;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [num_cks_width-1:0] num_cks;
input start_event, test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
output [`OVL_FIRE_WIDTH-1:0] fire_comb;
// Parameters that should not be edited
parameter assert_name = "OVL_NEXT";
`ifdef SMV
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_init.h"
`else
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`endif // !`ifdef SMV
`ifdef OVL_SYNTHESIS
`else
`ifndef SMV
// Sanity Checks
initial begin
if (num_cks <= 0) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value for parameter num_cks which must be set to value greater than 0");
end
if ((num_cks == 1) && (check_overlapping == 0)) begin
ovl_error_t(`OVL_FIRE_2STATE,"check_overlapping=0 is ignored when num_cks=1, recommend changing check_overlapping to 1 (identical behaviour)");
end
end
`endif // `ifndef SMV
`endif // !`ifdef OVL_SYNTHESIS
`ifdef OVL_VERILOG
`ifdef SMV
`include "./ovl_ported/vlog95/ovl_next_logic.v"
`else
`include "./vlog95/ovl_next_logic.v"
`endif
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_next_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_next_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
assign fire_comb = {2'b0, fire_2state_comb};
`endmodule // ovl_next
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// ////
//// To Do: ////
//// - add support for other RAM's ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_128x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.3 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_128x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(1'b0),
.ADDR({1'b0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(1'b0),
.ADDR({1'b0, addr}),
.DI(di[31:16]),
.EN(ce),
.WE(we),
.DO(doq[31:16])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(1'b0),
.ADDR({2'b00, addr}),
.DI(di),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO(doq),
.DOP()
);
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
addr_reg <= {aw{1'b0}};
else if (ce)
addr_reg <= addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= di;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_1_V
`define SKY130_FD_SC_MS__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_1_V
|
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