text
stringlengths 59
71.4k
|
|---|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64X1D #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.DPRA5 (sw[11]),
.DPRA4 (sw[10]),
.DPRA3 (sw[9]),
.DPRA2 (sw[8]),
.DPRA1 (sw[7]),
.DPRA0 (sw[6]),
.SPO (led[0]),
.DPO (led[1]),
.D (sw[13]),
.WE (sw[15])
);
RAM64X1D #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram4 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.DPRA5 (sw[11]),
.DPRA4 (sw[10]),
.DPRA3 (sw[9]),
.DPRA2 (sw[8]),
.DPRA1 (sw[7]),
.DPRA0 (sw[6]),
.SPO (led[2]),
.DPO (led[3]),
.D (sw[12]),
.WE (sw[15])
);
assign led[15:4] = sw[15:4];
assign tx = rx;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Query { int p, s, id; bool operator<(const Query &b) const { return (s < b.s); } }; int main() { int n; scanf( %d , &n); vector<int> a(n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); int m; scanf( %d , &m); vector<Query> q(m); for (int i = 0; i < m; ++i) { scanf( %d%d , &q[i].p, &q[i].s); --q[i].p; q[i].id = i; } sort(q.begin(), q.end()); vector<long long> ans(m, 0); int lim = sqrt(n); for (int i = 0; i < q.size(); ++i) { if (q[i].s > lim) { for (int j = q[i].p; j < n; j += q[i].s) ans[q[i].id] += a[j]; } else { int cs = q[i].s; vector<long long> sums(n, 0); for (int j = n - 1; j >= 0; --j) sums[j] = a[j] + ((j + cs < n) ? sums[j + cs] : 0); int j; for (j = i; j < q.size() && q[j].s == cs; ++j) ans[q[j].id] = sums[q[j].p]; i = j - 1; } } for (int i = 0; i < ans.size(); ++i) printf( %I64d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a[3] = {0}; cin >> n; while (n--) { cin >> a[0] >> a[1] >> a[2]; sort(a, a + 3); int ans = 0; if (a[0] > 0) { ans++; a[0]--; } if (a[1] > 0) { ans++; a[1]--; } if (a[2] > 0) { ans++; a[2]--; } if (a[1] > 0 && a[2] > 0) { ans++; a[2]--; a[1]--; } if (a[0] > 0 && a[2] > 0) { ans++; a[0]--; a[2]--; } if (a[1] > 0 && a[0] > 0) { ans++; a[1]--; a[0]--; } if (a[0] > 0 && a[1] > 0 && a[2] > 0) { ans++; } cout << ans << endl; } return 0; } |
/* Creater : ANSHUMAN MISHRA All Losses In this World Are Due To Lack Of Ability. If You Want To Curse Someone , Curse Your Own Weakness */ #include <bits/stdc++.h> using namespace std; #define ll long long #define pii pair<int,int> #define yes cout<< YES n #define no cout<< NO n const int N=1e5+5; int cnt[26][N]; signed main(){ ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); #ifndef ONLINE_JUDGE freopen( in.txt , r ,stdin); #endif int t=1;cin>>t; while(t--){ int n,m; cin>>n>>m; for (int i=0;i<m;++i) for (int j=0;j<26;++j) cnt[j][i]=0; string s; for (int i=0;i<n;++i){ cin>>s; for (int j=0;j<m;++j) cnt[s[j]- a ][j]++; } /* for (int i=0;i<m;++i){ for (int j=0;j<26;++j){ /* if (cnt[j][i]==1){ ans+= (j+ a ); break; } cout<<cnt[j][i]<< ; } cout<< n ; }*/ for (int i=0;i<n-1;++i){ cin>>s; for (int j=0;j<m;++j) cnt[s[j]- a ][j]--; } string ans= ; for (int i=0;i<m;++i){ for (int j=0;j<26;++j){ if (cnt[j][i]==1){ ans+= (j+ a ); break; } //cout<<cnt[j][i]<< ; } //cout<< n ; } cout<<ans<<endl; cout.flush(); } return 0; } |
//date:2016/3/11
//engineer:ZhaiShaoMin
//module name :regflie
module core_id_regfile(//input
clk,
rst,
raddr1,
raddr2,
rf_write,
waddr,
data,
//output
rd_data1,
rd_data2
);
//input
input clk;
input rst;
input [4:0] raddr1;
input [4:0] raddr2;
input rf_write;
input [4:0] waddr;
input [31:0] data;
//output
output [31:0] rd_data1;
output [31:0] rd_data2;
reg [31:0] regfile [31:0];
always @ (posedge clk) begin
if (rst==1'b1) begin
if((rf_write==1'b1) && (waddr!=32'h0000))
begin
regfile[waddr] <= data;
end
end
end
reg [31:0] rd_data1;
reg [31:0] rd_data2;
always @ (*) begin
if(rst==1'b1)
begin
rd_data1 <=32'h0000;
end
else if(raddr1==32'h0000)
begin
rd_data1 <= 32'h0000;
end
else if((raddr1== waddr) && (rf_write ==1'b1))
begin
rd_data1 <= data;
end
else
begin
rd_data1 <= regfile[raddr1];
end
end
always @ (*) begin
if(rst==1'b1)
begin
rd_data2 <=32'h0000;
end
else if(raddr2==32'h0000)
begin
rd_data2 <= 32'h0000;
end
else if((raddr2== waddr) && (rf_write ==1'b1))
begin
rd_data2 <= data;
end
else
begin
rd_data2 <= regfile[raddr2];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; void solve() { int n, k; cin >> n >> k; string s; cin >> s; set<char> st; for (auto i : s) st.insert(i); if (k > n) { string p = s; char ch = *st.begin(); for (int i = 0; i < k - n; i++) { p += ch; } cout << p; } else { int p = k; k--; char ch = *st.rbegin(); if (s[k] == ch) { for (; k >= 0; k--) { if (s[k] != ch) break; } for (int i = 0; i < k; i++) cout << s[i]; cout << *(st.upper_bound(s[k])); ch = *st.begin(); for (int i = 0; i < p - k - 1; i++) cout << ch; } else { for (int i = 0; i < k; i++) cout << s[i]; cout << *(st.upper_bound(s[k])); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; solve(); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const int MOD = 1000000007; int bcj[200010], siz[200010]; stack<pii> res; void init(int n) { for (int i = (0); i < (n + 2); i++) bcj[i] = i, siz[i] = 1; } int groot(int n) { return (bcj[n] == n) ? n : groot(bcj[n]); } bool merg(int u, int v) { u = groot(u), v = groot(v); if (u == v) return 0; if (siz[u] > siz[v]) swap(u, v); res.push({u, v}); bcj[u] = v; siz[v] += siz[u]; return 1; } void redact() { assert(res.size()); pii k = res.top(); res.pop(); bcj[k.first] = k.first; bcj[k.second] = k.second; siz[k.second] -= siz[k.first]; } void redact(int n) { while (res.size() != n) redact(); } struct cmd { int s, t; }; int ans[1 << 18]; vector<cmd> queries[1 << 20]; int N; void insert(int idx, int l, int r, int L, int R, cmd q) { if (r - l < 0) return; if (L <= l && r <= R) { queries[idx].push_back(q); return; } if (R < l || r < L) return; insert(2 * idx, l, (l + r) / 2, L, R, q); insert(2 * idx + 1, (l + r) / 2 + 1, r, L, R, q); } void dfs(int idx, int l, int r) { if (r - l < 0) return; int sz = res.size(); for (cmd& k : queries[idx]) { merg(k.s, k.t + N); merg(k.t, k.s + N); if (groot(k.s) == groot(k.s + N) || groot(k.t) == groot(k.t + N)) return redact(sz); } if (r - l == 0) return ans[l] = 1, void(); dfs(2 * idx, l, (l + r) / 2); dfs(2 * idx + 1, (l + r) / 2 + 1, r); redact(sz); } map<int, int> edges[100005]; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int q; cin >> N >> q; init(2 * N + 1); for (int i = (1); i < ((q) + 1); i++) { int x, y; cin >> x >> y; x--; y--; assert(x < y); if (edges[x][y] == 0) edges[x][y] = i; else { insert(1, 0, q + 3, edges[x][y], i - 1, {x, y}); edges[x][y] = 0; } } for (int i = (0); i < (N); i++) for (auto k : edges[i]) if (k.second) insert(1, 0, q + 3, k.second, q, {i, k.first}); dfs(1, 0, q + 3); for (int i = (1); i < ((q) + 1); i++) cout << (ans[i] ? YES n : NO n ); } |
#include <bits/stdc++.h> using namespace std; const long long K = 10000000000LL; vector<long long> L; void init(long long crr) { if (crr > K) return; if (crr != 0) L.push_back(crr); init(crr * 10 + 4); init(crr * 10 + 7); } bool is_lucky(long long x) { if (x == 0) return false; while (x > 0) { if (x % 10 != 4 && x % 10 != 7) return false; x /= 10; } return true; } const int MAX_M = 20; long long fact(long long k) { long long res = 1; for (int i = 1; i <= k; ++i) res *= i; return res; } vector<int> kth_permutation(int n, long long k) { vector<int> res(n), num(n); for (int i = 0; i < (int)(n); i++) num[i] = i; if (k >= fact(n)) return vector<int>(); for (int i = 0; i < (int)(n); i++) { long long f = fact(n - i - 1); res[i] = num[k / f]; num.erase(num.begin() + (k / f)); k %= f; } return res; } long long perm_n, perm_m; vector<int> perm_last; bool init_permutation(long long n, long long k) { perm_n = n; perm_last = kth_permutation(min(n, 20LL), k); if (perm_last.empty()) return false; perm_m = perm_n - perm_last.size(); return true; } long long get_permutation(long long i) { if (i < perm_m) return i; else return perm_m + perm_last[i - perm_m]; } int bruteforce(int N, int K) { vector<int> A(N); for (int i = 0; i < (int)(N); i++) A[i] = i + 1; for (int i = 0; i < (int)(K - 1); i++) next_permutation((A).begin(), (A).end()); int ans = 0; for (int i = 0; i < (int)(N); i++) if (is_lucky(i + 1) && is_lucky(A[i])) ++ans; return ans; } int main() { init(0); long long N, K; while (cin >> N >> K) { --K; if (!init_permutation(N, K)) { puts( -1 ); continue; } long long ans = 0; for (int i = 0; i < (int)(L.size()); i++) { long long l = L[i]; if (1 <= l && l <= N && is_lucky(1 + get_permutation(l - 1))) ++ans; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 7, maxm = 35 * maxn; int nxt[maxm][2], tot, a[maxn]; long long ans = 0; void ins(int x) { int now = 0; for (int i = 29; i >= 0; i--) { int go = (x >> i) & 1; if (nxt[now][go] == 0) nxt[now][go] = ++tot; now = nxt[now][go]; } } long long query(int x) { long long ret = 0; int now = 0; for (int i = 29; i >= 0; i--) { int go = (x >> i) & 1; if (nxt[now][go]) now = nxt[now][go]; else now = nxt[now][go ^ 1], ret |= (1 << i); } return ret; } void dfs(int l, int r, int dep) { if (dep == -1 || l >= r) return; int mid = l - 1; while (mid < r && (a[mid + 1] >> dep & 1) == 0) mid++; dfs(l, mid, dep - 1); dfs(mid + 1, r, dep - 1); if (mid == l - 1 || mid == r) return; for (int i = l; i <= mid; i++) ins(a[i]); long long ret = 1e18; for (int i = mid + 1; i <= r; i++) ret = min(ret, query(a[i])); ans += ret; for (int i = 0; i <= tot; i++) nxt[i][0] = nxt[i][1] = 0; tot = 0; } int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); dfs(1, n, 29); return 0 * printf( %lld n , ans); } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_memory_async (reset, enable, start_addr, end_addr, ren, raddr, rdata, wen, waddr,
wdata, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter data_width = 1;
parameter addr_width = 1;
parameter mem_size = 2;
parameter addr_check = 1;
parameter init_check = 1;
parameter one_read_check = 0;
parameter one_write_check = 0;
parameter value_check = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter wen_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter ren_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input reset, enable;
input ren, wen;
input [addr_width-1 : 0] start_addr;
input [addr_width-1 : 0] end_addr;
input [addr_width-1 : 0] raddr;
input [data_width-1 : 0] rdata;
input [addr_width-1 : 0] waddr;
input [data_width-1 : 0] wdata;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_MEMORY_ASYNC";
`ifdef OVL_EVERYTHING_OFF
// No logic if ASSERT & COVER both OFF
`else
// latch based gated clock
wire ren_gclk, wen_gclk;
reg ren_clken, wen_clken;
always @ (ren or enable) begin
if (ren == 1'b0)
ren_clken <= enable;
end
always @ (wen or enable) begin
if (wen == 1'b0)
wen_clken <= enable;
end
assign ren_gclk = (gating_type == `OVL_GATE_CLOCK) ? ren & ren_clken : ren;
assign wen_gclk = (gating_type == `OVL_GATE_CLOCK) ? wen & wen_clken : wen;
// clk (programmable edge)
wire ren_clk, wen_clk;
assign ren_clk = (ren_edge == `OVL_POSEDGE) ? ren_gclk : ~ren_gclk;
assign wen_clk = (wen_edge == `OVL_POSEDGE) ? wen_gclk : ~wen_gclk;
// reset_n (programmable polarity & optional gating)
wire reset_n;
assign reset_n = (gating_type == `OVL_GATE_RESET) ? ((reset_polarity == `OVL_ACTIVE_LOW) ? reset & enable : ~reset & enable)
: ((reset_polarity == `OVL_ACTIVE_LOW) ? reset : ~reset);
`endif
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_memory_async_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_memory_async
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; struct cell { bool up, down, right, left; int degree; cell() { up = down = left = right = degree = 0; } void reset() { up = down = left = right = degree = 0; } }; struct qcell { int x, y, degree; qcell() { x = y = -1; degree = 0; } qcell(int xx, int yy, int deg) { x = xx; y = yy; degree = deg; } }; char pitch[2001][2001]; cell info[2001][2001]; int n, m; int empty_cells = 0; bool update(int x, int y) { int degree = 0; if (x >= 0 && x < n && y >= 0 && y < m) { degree = info[x][y].degree; if (pitch[x][y] != . ) info[x][y].reset(); else { info[x][y].up = (x - 1 >= 0 && pitch[x - 1][y] == . ); info[x][y].down = (x + 1 < n && pitch[x + 1][y] == . ); info[x][y].left = (y - 1 >= 0 && pitch[x][y - 1] == . ); info[x][y].right = (y + 1 < m && pitch[x][y + 1] == . ); info[x][y].degree = (info[x][y].up + info[x][y].down + info[x][y].left + info[x][y].right); } } return degree != info[x][y].degree; } void do_push(int x, int y, queue<qcell> &q) { if (x >= 0 && x < n && y >= 0 && y < m) if (pitch[x][y] == . ) if (info[x][y].degree == 1) q.push(qcell(x, y, 1)); } void occupy(int x, int y, queue<qcell> &q) { int xx = x, yy = y; char dir = U ; if (info[x][y].down) dir = D ; if (info[x][y].left) dir = L ; if (info[x][y].right) dir = R ; if (dir == U ) { pitch[x][y] = v ; pitch[x - 1][y] = ^ ; xx = x - 1; } else if (dir == D ) { pitch[x][y] = ^ ; pitch[x + 1][y] = v ; xx = x + 1; } else if (dir == L ) { pitch[x][y] = > ; pitch[x][y - 1] = < ; yy = y - 1; } else { pitch[x][y] = < ; pitch[x][y + 1] = > ; yy = y + 1; } update(x, y); update(xx, yy); if (do_push) { if (update(x - 1, y)) do_push(x - 1, y, q); if (update(x + 1, y)) do_push(x + 1, y, q); if (update(x, y - 1)) do_push(x, y - 1, q); if (update(x, y + 1)) do_push(x, y + 1, q); if (update(xx - 1, yy)) do_push(xx - 1, yy, q); if (update(xx + 1, yy)) do_push(xx + 1, yy, q); if (update(xx, yy - 1)) do_push(xx, yy - 1, q); if (update(xx, yy + 1)) do_push(xx, yy + 1, q); } empty_cells -= 2; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> pitch[i][j]; if (pitch[i][j] == . ) empty_cells++; } queue<qcell> q; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { update(i, j); if (info[i][j].degree == 1) q.push(qcell(i, j, info[i][j].degree)); } bool unique_sol = 1; while (1) { if (q.empty()) break; qcell f = q.front(); q.pop(); if (info[f.x][f.y].degree == 0) { if (pitch[f.x][f.y] == . ) { unique_sol = false; break; } } else occupy(f.x, f.y, q); } if (unique_sol) if (empty_cells != 0) unique_sol = 0; if (!unique_sol) cout << Not unique << endl; else for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << pitch[i][j]; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long n, s1, v1, s2, v2; long long i, j, k, ans, p, q, m, num; inline long long cal_1() { return i * v1 + (n - i * s1) / s2 * v2; } inline long long cal_2() { return i * v2 + (n - i * s2) / s1 * v1; } inline long long maxn(long long a, long long b) { if (a > b) return a; else return b; } int main() { cin >> n >> v1 >> v2 >> s1 >> s2; m = lcm(s1, s2); num = n / m; if (num > 0) num--; if (v1 * s2 >= v2 * s1) { num = m / s1 * num; p = (n - num * s1) / s2; ans = num * v1 + p * v2; if (s1 >= s2) { for (i = num; i * s1 <= n; i++) ans = maxn(ans, cal_1()); } else { for (i = p; i >= 0; i--) ans = maxn(ans, cal_2()); } } else { num = m / s2 * num; p = (n - num * s2) / s1; ans = num * v2 + p * v1; if (s2 >= s1) { for (i = num; i * s2 <= n; i++) ans = maxn(ans, cal_2()); } else { for (i = p; i >= 0; i--) ans = maxn(ans, cal_1()); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { string s; cin >> s; long long int a, b; cin >> a >> b; long long int n = s.length(); vector<long long int> v1(n, -1), v2(n, -1); long long int x = 0; for (long long int i = 0; i < n; i++) { if (i == 0) { v1[i] = (s[i] - 0 ) % a; continue; } v1[i] = (v1[i - 1] * 10 + (s[i] - 0 )) % a; } long long int base = 1; for (int i = n - 1; i >= 0; i--) { if (i == n - 1) { v2[i] = (s[i] - 0 ) % b; } else v2[i] = ((s[i] - 0 ) * base + v2[i + 1]) % b; base = (base * 10) % b; } long long int index = -1; for (long long int i = 0; i < n - 1; i++) { if (v1[i] == 0 && v2[i + 1] == 0 && s[i + 1] != 0 ) { index = i; break; } } if (index == -1) cout << NO << endl; else { cout << YES << endl; cout << s.substr(0, index + 1) << endl << s.substr(index + 1, n - index - 1); } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[1 << 14], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 14, stdin), p1 == p2) ? EOF : *p1++; } inline long long read(long long &x) { x = 0; bool f = 1; char c = gc(); for (; !isdigit(c); c = gc()) { if (c == - ) f ^= 1; if (c == EOF) return EOF; } for (; isdigit(c); c = gc()) x = (x << 1) + (x << 3) + (c ^ 48); x = f ? x : -x; return 1; } inline void wr(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) wr(x / 10); putchar(x % 10 | 48); } const long long N = 1e5 + 10; long long n; long long a[N], ans; int main() { read(n); for (long long i = 1, x; i <= n; ++i) read(a[i]); sort(a + 1, a + 1 + n); for (long long i = 2; i <= n; ++i) if (a[i] - a[i - 1] > 1) ans += a[i] - a[i - 1] - 1; wr(ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int dp[2010][2010]; int main() { int n, h, i; scanf( %d%d , &n, &h); dp[0][0] = 1; for (i = 1; i <= n; i++) { int x; scanf( %d , &x); x = h - x; if (x < 0) { printf( 0 n ); return 0; } if (x >= 1) { dp[i][x] = (dp[i - 1][x] + dp[i - 1][x - 1]) % 1000000007; dp[i][x - 1] = 1LL * dp[i][x] * x % 1000000007; } else { dp[i][0] = dp[i - 1][0]; } } printf( %d n , dp[n][0]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000 + 5; const int N = 2e5 + 5; const long long oo = 1e18 + 5; const long long mod = 998244353; int a[N], b[N]; int mul(int a, int b) { return 1ll * a * b % mod; } void solve() { int n, k; cin >> n >> k; vector<int> pos(n + 2); vector<int> lv(n + 2); for (int i = 1; i <= n; ++i) { int x; cin >> x; a[i] = x; pos[x] = i; lv[i] = 0; } for (int i = 1; i <= k; ++i) { int x; cin >> x; b[i] = x; lv[pos[x]] = i; } lv[0] = lv[n + 1] = INF; int ans = 1; for (int i = 1; i <= n; ++i) { if (lv[i]) { if (lv[i] > lv[i - 1] && lv[i] > lv[i + 1]) ans = mul(ans, 2); else { if (lv[i] <= lv[i - 1] && lv[i] <= lv[i + 1]) { cout << 0 << n ; return; } } } } cout << ans << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> int main() { int n, m, a, b, t; while (scanf( %d%d%d%d , &n, &m, &a, &b) != EOF) { if (b == n) b = (n - 1) / m * m + m; a--; b--; if (a > b) while (1) ; if (a / m == b / m || m == 1) t = 1; else if (a % m == 0) { if (b % m == m - 1) t = 1; else t = 2; } else { if (b / m - a / m == 1) t = 2; else if (b % m == m - 1) t = 2; else if ((b - a + 1) % m == 0) t = 2; else t = 3; } printf( %d n , t); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> vec, ves; int main() { int n, m, f = 0, w = 0; bool p = false, t = false; cin >> n; for (int i = 0; i < n; i++) { cin >> m; if (m == 0) t = true; for (int j = 0; j < vec.size(); j++) { p = false; if (m == vec[j]) { ves[j]++; p = true; break; } } if (p == false) { vec.push_back(m); ves.push_back(1); } } for (int i = 0; i < vec.size(); i++) { if (vec[i] != 0 && ves[i] > 2) { cout << -1; return 0; } else if (ves[i] == 2 && vec[i] != 0) w++; } cout << w; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:07:09 11/04/2015
// Design Name:
// Module Name: KeyBoardControler
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KeyBoardControler(
input wire clk,
input wire PS2C,
input wire PS2D,
input wire InteAccept,
output reg[15:0] scanCode,
output reg KeyBoardInte
);
/*
reg clk;
reg PS2C;
reg PS2D;
wire InteAccept;
reg en;
assign InteAccept = KeyBoardInte & en;
initial begin
clk = 0;
PS2C = 0;
PS2D = 0;
en = 0;
#12000
en = 1;
end
//always@(posedge clk) begin
// InteAccept <= KeyBoardInte;
//end
always #10 begin
clk = ~clk;
end
always #200 begin
PS2C = ~PS2C;
end
always #330 begin
PS2D = ~PS2D;
end
*/
reg[7:0] buffer[15:0];
reg[3:0] put,get;
reg[3:0] state;
reg[22:0] count;
reg PS2Cf,PS2Df;
reg [7:0] ps2c_filter,ps2d_filter;
reg [10:0] shift1,shift2;
reg new;
initial begin
put<=0;
get<=0;
ps2c_filter<=0;
ps2d_filter<=0;
PS2Cf<=1;
PS2Df<=1;
shift1 <= 0;
shift2 <= 0;
state <= 0;
count <= 0;
new <= 0;
KeyBoardInte <= 0;
end
always @(posedge clk) begin
//¶ÔʱÖÓÏߺÍÊý¾ÝÏß½øÐйýÂË
ps2c_filter[7]<=PS2C;
ps2c_filter[6:0]<=ps2c_filter[7:1];
ps2d_filter[7]<=PS2D;
ps2d_filter[6:0]<=ps2d_filter[7:1];
if(ps2c_filter == 8'b11111111)
PS2Cf<=1;
else begin
if(ps2c_filter == 8'b00000000)
PS2Cf<=0;
end
if(ps2d_filter == 8'b11111111)
PS2Df<=1;
else begin
if(ps2d_filter == 8'b00000000)
PS2Df<=0;
end
if(PS2Df) begin
count <= count + 1;
end
else begin
count <= 1;
end
if(state == 10) begin
new <= 1;
end
if((state == 0) && new) begin
if(put != get-1) begin
buffer[put] <= shift1[8:1];
put <= put+1;
new <= 0;
end
end
if((get == put) | InteAccept) begin
KeyBoardInte <= 0;
end
else begin
if(KeyBoardInte == 0) begin
scanCode <= buffer[get];
KeyBoardInte <= 1;
end
end
if(InteAccept & (get != put)) begin
get <= get + 1;
end
end
wire rst;
assign rst = (count == 0);
//ÒÆλ¼Ä´æÆ÷£¬ÓÃÒÔ¸ù¾ÝPS2µÄʱÖӼǼPS2µÄɨÃèÂë
always @(negedge PS2Cf or posedge rst) begin
if(rst) begin
state <= 0;
end
else begin
shift1<={PS2Df,shift1[10:1]};
shift2<={shift1[0],shift2[10:1]};//ÏÈ·¢Ë͸ß×Ö½Ú£¬ÔÙ·¢Ë͵Í×Ö½Ú
if(state == 0 && PS2Df == 0) begin
state <= 1;
end
else if(state == 10) begin
state <= 0;
end
else begin
state <= state + 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans[200005]; int roots[105]; struct node { int l, r; } tree[200005 * 20]; int cnt = 0; void build(int &x, int pos, int l, int r) { if (!x) x = ++cnt; if (l == r) return; int mid = (l + r) >> 1; if (pos <= mid) build(tree[x].l, pos, l, mid); else build(tree[x].r, pos, mid + 1, r); } int merge(int &x, int &y) { if (!x) return y; if (!y) return x; tree[y].l = merge(tree[x].l, tree[y].l); tree[y].r = merge(tree[x].r, tree[y].r); return y; } void modify(int &x, int &y, int l, int r, int posl, int posr) { if (!x) return; if (l >= posl && r <= posr) { y = merge(x, y); x = 0; } if (!y) y = ++cnt; int mid = (l + r) >> 1; if (posl <= mid) modify(tree[x].l, tree[y].l, l, mid, posl, posr); if (posr > mid) modify(tree[x].r, tree[y].r, mid + 1, r, posl, posr); } void get_ans(int pos, int num, int l, int r) { if (!pos) return; if (l == r) { ans[l] = num; return; } int mid = (l + r) >> 1; get_ans(tree[pos].l, num, l, mid); get_ans(tree[pos].r, num, mid + 1, r); } int main() { int n; scanf( %d , &n); int x; for (int i = 1; i <= n; i++) { scanf( %d , &x); build(roots[x], i, 1, n); } int m; scanf( %d , &m); int l, r, y; while (m--) { scanf( %d%d%d%d , &l, &r, &x, &y); if (x == y) continue; modify(roots[x], roots[y], 1, n, l, r); } for (int i = 1; i <= 100; i++) { get_ans(roots[i], i, 1, n); } for (int i = 1; i <= n; i++) printf( %d , ans[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND2_PP_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool cmp(double a, double b) { return a > b; } int n; double a[110], x, sum, ans; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lf , &a[i]); sort(a, a + n, cmp); ans = 0; for (int i = 1; i <= n; i++) { sum = 0; for (int j = 0; j < i; j++) { x = a[j]; for (int k = 0; k < i; k++) { if (j != k) x *= 1 - a[k]; } sum += x; } ans = max(sum, ans); } printf( %.12lf n , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_2_V
`define SKY130_FD_SC_HDLL__AND4B_2_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_2 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_2 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_2_V
|
// Generator : SpinalHDL v1.1.5 git head : 0310b2489a097f2b9de5535e02192d9ddd2764ae
// Date : 02/12/2018, 10:37:58
// Component : AsyncReceiver
module Fifo (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input io_read,
input io_write,
output io_full,
output io_empty,
input clk,
input reset);
wire [7:0] _zz_5;
wire [4:0] _zz_6;
wire [4:0] _zz_7;
wire [7:0] _zz_8;
wire _zz_9;
reg [4:0] head;
reg [4:0] tail;
reg full;
reg empty;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg _zz_4;
reg [7:0] mem [0:31];
assign _zz_6 = (head + (5'b00001));
assign _zz_7 = (tail + (5'b00001));
assign _zz_8 = io_dataIn;
assign _zz_9 = ((! full) && io_write);
always @ (posedge clk) begin
if(_zz_9) begin
mem[head] <= _zz_8;
end
end
assign _zz_5 = mem[tail];
assign io_dataOut = _zz_5;
assign io_empty = empty;
assign io_full = full;
always @ (posedge clk or posedge reset) begin
if (reset) begin
head <= (5'b00000);
tail <= (5'b00000);
full <= 1'b0;
empty <= 1'b1;
end else begin
if(((io_write && (! _zz_1)) && (! io_read)))begin
if((! full))begin
head <= (head + (5'b00001));
full <= (_zz_6 == tail);
empty <= 1'b0;
end
end
if(((! io_write) && (io_read && (! _zz_2))))begin
if((! empty))begin
tail <= (tail + (5'b00001));
empty <= (_zz_7 == head);
full <= 1'b0;
end
end
if(((io_write && (! _zz_3)) && (io_read && (! _zz_4))))begin
if(full)begin
tail <= (tail + (5'b00001));
full <= 1'b0;
end
if(empty)begin
head <= (head + (5'b00001));
empty <= 1'b0;
end
if(((! full) && (! empty)))begin
tail <= (tail + (5'b00001));
head <= (head + (5'b00001));
end
end
end
end
always @ (posedge clk) begin
_zz_1 <= io_write;
_zz_2 <= io_read;
_zz_3 <= io_write;
_zz_4 <= io_read;
end
endmodule
module AsyncReceiver (
input io_enable,
input io_mem_valid,
output io_mem_ready,
input [3:0] io_mem_addr,
output [31:0] io_mem_rdata,
input io_baudClockX64,
input io_rx,
input clk,
input reset);
reg _zz_5;
reg _zz_6;
wire [7:0] _zz_7;
wire _zz_8;
wire _zz_9;
wire _zz_10;
wire _zz_11;
wire [31:0] _zz_12;
wire [0:0] _zz_13;
reg [1:0] state;
reg [5:0] bitTimer;
reg [2:0] bitCount;
reg [7:0] shifter;
reg baudClockX64Sync1;
reg baudClockX64Sync2;
reg rxSync1;
reg _zz_1;
reg _zz_2;
reg _zz_3;
reg [7:0] rdata;
reg ready;
wire busCycle;
reg _zz_4;
assign _zz_10 = (busCycle && (! _zz_4));
assign _zz_11 = (bitTimer == (6'b000000));
assign _zz_12 = {24'd0, rdata};
assign _zz_13 = (! _zz_9);
Fifo fifo_1 (
.io_dataIn(shifter),
.io_dataOut(_zz_7),
.io_read(_zz_5),
.io_write(_zz_6),
.io_full(_zz_8),
.io_empty(_zz_9),
.clk(clk),
.reset(reset)
);
always @ (*) begin
_zz_5 = 1'b0;
if(_zz_10)begin
case(io_mem_addr)
4'b0000 : begin
_zz_5 = 1'b1;
end
4'b0100 : begin
end
default : begin
end
endcase
end
end
always @ (*) begin
_zz_6 = 1'b0;
case(state)
2'b00 : begin
end
2'b01 : begin
end
2'b10 : begin
end
default : begin
if(_zz_11)begin
if((rxSync1 == 1'b1))begin
if((! _zz_8))begin
_zz_6 = 1'b1;
end
end
end
end
endcase
end
assign busCycle = (io_mem_valid && io_enable);
assign io_mem_rdata = (busCycle ? _zz_12 : (32'b00000000000000000000000000000000));
assign io_mem_ready = (busCycle ? ready : 1'b0);
always @ (posedge clk or posedge reset) begin
if (reset) begin
state <= (2'b00);
bitTimer <= (6'b000000);
bitCount <= (3'b000);
shifter <= (8'b00000000);
baudClockX64Sync1 <= 1'b0;
baudClockX64Sync2 <= 1'b0;
rxSync1 <= 1'b0;
rdata <= (8'b00000000);
ready <= 1'b0;
end else begin
baudClockX64Sync1 <= io_baudClockX64;
baudClockX64Sync2 <= baudClockX64Sync1;
rxSync1 <= io_rx;
if((baudClockX64Sync2 && (! _zz_1)))begin
bitTimer <= (bitTimer - (6'b000001));
end
case(state)
2'b00 : begin
state <= (2'b00);
if(((! rxSync1) && _zz_2))begin
state <= (2'b01);
bitTimer <= (6'b011111);
end
end
2'b01 : begin
state <= (2'b01);
if((bitTimer == (6'b000000)))begin
if((rxSync1 == 1'b0))begin
bitTimer <= (6'b111111);
state <= (2'b10);
end else begin
state <= (2'b00);
end
end
end
2'b10 : begin
state <= (2'b10);
if((baudClockX64Sync2 && (! _zz_3)))begin
if((bitTimer == (6'b000000)))begin
shifter[bitCount] <= rxSync1;
bitCount <= (bitCount + (3'b001));
if((bitCount == (3'b111)))begin
state <= (2'b11);
end
end
end
end
default : begin
state <= (2'b11);
if(_zz_11)begin
state <= (2'b00);
end
end
endcase
ready <= busCycle;
if(_zz_10)begin
case(io_mem_addr)
4'b0000 : begin
rdata <= _zz_7;
end
4'b0100 : begin
rdata <= {7'd0, _zz_13};
end
default : begin
end
endcase
end
end
end
always @ (posedge clk) begin
_zz_1 <= baudClockX64Sync2;
_zz_4 <= busCycle;
end
always @ (posedge clk) begin
_zz_2 <= rxSync1;
end
always @ (posedge clk) begin
_zz_3 <= baudClockX64Sync2;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int prime(int n) { if (n == 1) { return 0; } for (int i = 2; i * i <= n; i++) { if (n % i == 0) { return 0; } } return 1; } int main() { int n; cin >> n; int cnt = n; while (!prime(cnt)) { cnt++; } cout << cnt << endl; for (int i = 1; i <= n; i++) { cout << i << << i % n + 1 << endl; } int now = 1; while (cnt != n) { cout << now << << n - now << endl; now++; cnt--; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int main() { cin.tie(0); ios_base::sync_with_stdio(0); cin >> n >> m; int finalPos[4 * n]; memset(finalPos, -1, sizeof(finalPos)); for (int i = (2 * n) + 1, j = 0; i <= m; i++, j += 2) { finalPos[j] = i; } for (int i = 1, j = 1; i <= (2 * n) && i <= m; i++, j += 2) finalPos[j] = i; for (int i = 0; i < (4 * n); i++) { if (finalPos[i] != -1) cout << finalPos[i] << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[10] = {1, -1, 0, 0}; int dy[10] = {0, 0, 1, -1}; const long long mod = 1e9 + 7; long long cur; long long tich = 1; vector<int> G[300005]; int n, h, m; int a[105][105]; int b[105][105]; int ans; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> a[i][j]; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> b[i][j]; if (b[i][j] < a[i][j]) { int tmp = b[i][j]; b[i][j] = a[i][j]; a[i][j] = tmp; } } for (int i = 1; i < n; i++) for (int j = 1; j <= m; j++) { if (a[i][j] >= a[i + 1][j]) { cout << Impossible ; return 0; } if (b[i][j] >= b[i + 1][j]) { cout << Impossible ; return 0; } } for (int i = 1; i <= n; i++) for (int j = 1; j < m; j++) { if (a[i][j] >= a[i][j + 1]) { cout << Impossible ; return 0; } if (b[i][j] >= b[i][j + 1]) { cout << Impossible ; return 0; } } cout << Possible ; } |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:52:15 2016
/////////////////////////////////////////////////////////////
module GDA_St_N8_M8_P3 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42,
n43, n44, n45, n46, n47, n48;
NAND2X1TS U31 ( .A(in1[4]), .B(in2[4]), .Y(n38) );
CLKAND2X2TS U32 ( .A(in2[0]), .B(in1[0]), .Y(n33) );
XOR2XLTS U33 ( .A(n46), .B(n44), .Y(res[5]) );
XOR2XLTS U34 ( .A(n48), .B(n47), .Y(res[6]) );
NAND2BXLTS U35 ( .AN(n38), .B(n46), .Y(n29) );
OAI31X1TS U36 ( .A0(n43), .A1(n42), .A2(n41), .B0(n40), .Y(n44) );
OA21X1TS U37 ( .A0(in1[5]), .A1(in2[5]), .B0(n31), .Y(n46) );
OAI21X1TS U38 ( .A0(in1[6]), .A1(in2[6]), .B0(n30), .Y(n47) );
OAI21X1TS U39 ( .A0(n43), .A1(n39), .B0(n38), .Y(n45) );
OAI21X2TS U40 ( .A0(in1[4]), .A1(in2[4]), .B0(n38), .Y(n43) );
OAI21X2TS U41 ( .A0(in1[3]), .A1(in2[3]), .B0(n39), .Y(n42) );
NAND2X2TS U42 ( .A(in1[3]), .B(in2[3]), .Y(n39) );
AOI2BB1XLTS U43 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n33), .Y(res[0]) );
NAND2X1TS U44 ( .A(in1[5]), .B(in2[5]), .Y(n31) );
NAND2X1TS U45 ( .A(in1[6]), .B(in2[6]), .Y(n30) );
AOI32X1TS U46 ( .A0(n31), .A1(n30), .A2(n29), .B0(n47), .B1(n30), .Y(n32) );
CMPR32X2TS U47 ( .A(in2[7]), .B(in1[7]), .C(n32), .CO(res[8]), .S(res[7]) );
CMPR32X2TS U48 ( .A(in1[1]), .B(in2[1]), .C(n33), .CO(n34), .S(res[1]) );
CMPR32X2TS U49 ( .A(in2[2]), .B(in1[2]), .C(n34), .CO(n35), .S(res[2]) );
XNOR2X1TS U50 ( .A(n35), .B(n42), .Y(res[3]) );
NAND2X1TS U51 ( .A(in1[2]), .B(in2[2]), .Y(n41) );
OAI211XLTS U52 ( .A0(in1[2]), .A1(in2[2]), .B0(in1[1]), .C0(in2[1]), .Y(n36)
);
AOI32X1TS U53 ( .A0(n41), .A1(n39), .A2(n36), .B0(n42), .B1(n39), .Y(n37) );
XNOR2X1TS U54 ( .A(n43), .B(n37), .Y(res[4]) );
INVX2TS U55 ( .A(n45), .Y(n40) );
AOI22X1TS U56 ( .A0(in1[5]), .A1(in2[5]), .B0(n46), .B1(n45), .Y(n48) );
initial $sdf_annotate("GDA_St_N8_M8_P3_syn.sdf");
endmodule
|
`include "constants.vh"
`include "alu_ops.vh"
`default_nettype none
module exunit_alu
(
input wire clk,
input wire reset,
input wire [`DATA_LEN-1:0] ex_src1,
input wire [`DATA_LEN-1:0] ex_src2,
input wire [`ADDR_LEN-1:0] pc,
input wire [`DATA_LEN-1:0] imm,
input wire dstval,
input wire [`SRC_A_SEL_WIDTH-1:0] src_a,
input wire [`SRC_B_SEL_WIDTH-1:0] src_b,
input wire [`ALU_OP_WIDTH-1:0] alu_op,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,
input wire issue,
input wire prmiss,
input wire [`SPECTAG_LEN-1:0] spectagfix,
output wire [`DATA_LEN-1:0] result,
output wire rrf_we,
output wire rob_we, //set finish
output wire kill_speculative
);
wire [`DATA_LEN-1:0] alusrc1;
wire [`DATA_LEN-1:0] alusrc2;
reg busy;
assign rob_we = busy;
assign rrf_we = busy & dstval;
assign kill_speculative = ((spectag & spectagfix) != 0) && specbit && prmiss;
always @ (posedge clk) begin
if (reset) begin
busy <= 0;
end else begin
busy <= issue;
end
end
src_a_mux samx
(
.src_a_sel(src_a),
.pc(pc),
.rs1(ex_src1),
.alu_src_a(alusrc1)
);
src_b_mux sbmx
(
.src_b_sel(src_b),
.imm(imm),
.rs2(ex_src2),
.alu_src_b(alusrc2)
);
alu alice
(
.op(alu_op),
.in1(alusrc1),
.in2(alusrc2),
.out(result)
);
endmodule // exunit_alu
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> int main() { int a, b, c; while (~scanf( %d%d%d , &a, &b, &c)) { int max = 999999999; int a1 = (c + b) + a; max = max < a1 ? max : a1; int a2 = 2 * (c + b); max = max < a2 ? max : a2; int b1 = (c + a) * 2; max = max < b1 ? max : b1; int b2 = (b + a) * 2; max = max < b2 ? max : b2; printf( %d n , max); } return 0; } |
#include <bits/stdc++.h> int main() { int n, m, i, a; int f[105] = {0}; scanf( %d%d , &n, &m); while (m--) { scanf( %d , &a); for (i = a; i <= n; i++) if (f[i] == 0) f[i] = a; } for (i = 1; i < n; i++) printf( %d , f[i]); printf( %d n , f[n]); return 0; } |
#include <bits/stdc++.h> using namespace std; constexpr int N = 3e3 + 1; int a[N], dp[N][N], nxt[N], prv[N], lst[N]; int main() { cin.tie(0), ios::sync_with_stdio(0); int t, n; cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i], --a[i]; } memset(lst, -1, n * sizeof *lst); n = unique(a, a + n) - a; memset(prv, -1, n * sizeof *prv); memset(nxt, 127, n * sizeof *nxt); for (int i = 0; i < n; ++i) { if (lst[a[i]] != -1) { prv[i] = lst[a[i]]; nxt[lst[a[i]]] = i; } lst[a[i]] = i; } for (int le = 2; le <= n; ++le) for (int i = 0; i + le <= n; ++i) { int j = i + le - 1; dp[i][j] = max(dp[i + 1][j], dp[i][j - 1]); bool use_j = 0; if (a[i] != a[j]) { int cnti = 0, cntj = 0; for (int z = nxt[i]; z <= j; z = nxt[z]) ++cnti; for (int z = prv[j]; z >= i; z = prv[z]) ++cntj; use_j = cntj < cnti; } if (!use_j) { for (int z = nxt[i]; z <= j; z = nxt[z]) { dp[i][j] = max(dp[i][j], dp[i + 1][z - 1] + dp[z][j] + 1); } } else { for (int z = prv[j]; z >= i; z = prv[z]) { dp[i][j] = max(dp[i][j], dp[i][z] + dp[z + 1][j - 1] + 1); } } } cout << n - dp[0][n - 1] - 1 << n ; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 20:22:04
// Design Name:
// Module Name: fb_count
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fb_count(
input CP,M,D,C,B,A,LD,CLR,
output reg Qd,Qc,Qb,Qa,Qcc
);
reg [3:0] count;
always @(posedge CP or negedge CLR or negedge LD)
begin
if(CLR == 0)
begin
count = 0;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
else if(LD == 0)
begin
count = {D,C,B,A};
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
else if(M == 1)
begin
if(count ==15)
begin
count = 0;
{Qd,Qc,Qb,Qa} = count;
Qcc = 0;
end
else
begin
count = count + 1;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
end
else
begin
if(count == 0)
begin
count = 15;
{Qd,Qc,Qb,Qa} = count;
Qcc = 0;
end
else
begin
count =count - 1;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int sz = 5005; const int mod = 998244353; long long int n, a[sz], b[sz], dp[15][1005][1005], c[sz], d[sz], m, c0, d0; long long int dipi(int i, int cnt, int rem) { if (rem > n) return -100000; if (i > m) return 0; if (~dp[i][cnt][rem]) return dp[i][cnt][rem]; if (a[i] - cnt * b[i] < 0) { return dp[i][cnt][rem] = dipi(i + 1, 1, rem); } return dp[i][cnt][rem] = max({d[i] + dipi(i, cnt + 1, rem + c[i]), dipi(i + 1, 1, rem), d[i] + dipi(i + 1, 1, rem + c[i])}); } void solve() { cin >> n >> m >> c0 >> d0; memset(dp, -1, sizeof dp); c[0] = c0, d[0] = d0; a[0] = 0, b[0] = 0; for (int i = 1; i <= m; i++) { cin >> a[i] >> b[i] >> c[i] >> d[i]; } cout << dipi(0, 1, 0) << endl; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long res = 1; long long countn = 1; void solve(long long a[], long long n) { if (n == 0) { res = max(countn, res); cout << res; } else if (a[n] >= a[n - 1]) { countn++; solve(a, n - 1); } else { res = max(countn, res); countn = 1; solve(a, n - 1); } } int main() { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } solve(a, n - 1); return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_data.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Data comparison for both "non-complex" and "complex" data.
//
// Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata
// bus is compared against a fixed ones and zeros pattern, or against data
// provided on the prob_o bus.
//
// In the case of complex data, the phy_rddata data is delayed by two
// clocks to match up with the prbs_o data.
//
// For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered.
// A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ
// bus, 64 bytes are delivered on each clock.
//
// In 2:1 mode the DRAM burst is delivered on two fabric clocks. For
// an 8 byte bus, 32 bytes are delivered with each fabric clock.
//
// For the most part, this block does not use phy_rddata_en. It delivers
// its results and depends on downstream logic to know when its valid.
//
// phy_rddata_en is used for the PRBS compares when the last line of data
// needs to be carried over to a subsequent line.
//
// Since we work on a byte at a time, the comparison only works on
// one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to
// select the proper 8 bytes out of both the phy_rddata and prob_o streams.
//
// Comparisons are computed for "zero" or "rise" data, and "oneeighty" or
// "fall" data. The "oneeighty" compares assumes the rising edge clock is
// landing in the oneeighty data.
//
// For the simple data, we don't need to worry about first byte or last
// byte conditions because the sampled data is taken from the middle
// of a 4 burst segment.
//
// The complex (or PRBS) data starts and stops. And we need to be
// careful about ignoring compares that might be using invalid latched
// data. The PRBS generator provides prbs_ignore_first_byte and
// prbs_ignore_last_bytes. The comparison block is procedural. It
// first compares across the entire line, then comes back and overwrites
// any byte compare results as indicated by the _ignore_ wires.
//
// The compares generate an eight bit vector, one for each byte. The
// final step is to bitwise AND this eight bit vector. We end up
// with two sets of two bits. Zero and oneeighty for the fixed pattern
// and the prbs.
//
// complex_oclkdelay_calib_start is used to
// select between the fixed and prbs compares. The final output
// is a two bit match bus.
//
// There is a deprecated feature to mask the compare for any byte.
//
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_data #
(parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter DQS_CNT_WIDTH = 3,
parameter DQ_WIDTH = 64)
(/*AUTOARG*/
// Outputs
match,
// Inputs
clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o,
oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes,
phy_rddata_en_1
);
localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000;
input clk;
input rst;
input complex_oclkdelay_calib_start;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
reg [DQ_WIDTH-1:0] word, word_shifted;
reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r;
always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns;
always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r;
always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1;
always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns;
input prbs_ignore_first_byte, prbs_ignore_last_bytes;
reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r;
always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte;
always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes;
input phy_rddata_en_1;
reg [7:0] last_byte_r;
wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r;
wire [7:0] last_byte_ns;
generate if (nCK_PER_CLK == 4) begin
assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r;
end else begin
assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r;
end endgenerate
always @(posedge clk) last_byte_r <= #TCQ last_byte_ns;
reg second_half_ns, second_half_r;
always @(posedge clk) second_half_r <= #TCQ second_half_ns;
always @(*) begin
second_half_ns = second_half_r;
if (rst) second_half_ns = 1'b0;
else second_half_ns = phy_rddata_en_1 ^ second_half_r;
end
reg [7:0] comp0, comp180, prbs0, prbs180;
integer ii;
always @(*) begin
comp0 = 8'hff;
comp180 = 8'hff;
prbs0 = 8'hff;
prbs180 = 8'hff;
data_bytes_ns = 64'b0;
prbs_bytes_ns = 64'b0;
for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1)
begin
word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH];
word_shifted = word >> oclkdelay_calib_cnt*8;
data_bytes_ns[ii*8+:8] = word_shifted[7:0];
word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH];
word_shifted = word >> oclkdelay_calib_cnt*8;
prbs_bytes_ns[ii*8+:8] = word_shifted[7:0];
comp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00);
comp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff);
prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8];
end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1)
prbs180[0] = last_byte_r == prbs_bytes_r[7:0];
for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1)
prbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8];
if (nCK_PER_CLK == 4) begin
if (prbs_ignore_last_bytes_r) begin
prbs0[7:6] = 2'b11;
prbs180[7] = 1'b1;
end
if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;
end else begin
if (second_half_r) begin
if (prbs_ignore_last_bytes_r) begin
prbs0[3:2] = 2'b11;
prbs180[3] = 1'b1;
end
end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;
end // else: !if(nCK_PER_CLK == 4)
end // always @ (*)
wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK;
wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK;
wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK;
wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK;
output [1:0] match;
assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked};
endmodule // mig_7series_v2_3_ddr_phy_ocd_data
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO1P_FUNCTIONAL_PP_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int inf = 1000000007; int d[210][210][510][2]; short vis[210][210][510][2]; int q, n, k, b, cas; int nex[210][22], out[210]; int fal[210]; int s[210]; int dp(int pos, int len, int w, int m) { w = min(w, k + 5); if (vis[pos][len][w][m] == cas) return d[pos][len][w][m]; vis[pos][len][w][m] = cas; if (w > k) return d[pos][len][w][m] = 0; if (len == n) return d[pos][len][w][m] = 1; int res = 0; for (int i = 0; i < b; ++i) { if (m == 0 && i > s[len]) break; int nst = nex[pos][i], mm = m | i < s[len]; int ww = w + out[nst]; res += dp(nst, len + 1, ww, mm); if (res >= inf) res -= inf; } return d[pos][len][w][m] = res; } int nn; void add(int len, int w) { int pos = 0, i = 0; while (i < len) { int ii = s[i++]; if (!nex[pos][ii]) nex[pos][ii] = ++nn; pos = nex[pos][ii]; } out[pos] += w; } void bfs() { queue<int> q; q.push(0); while (!q.empty()) { int x = q.front(); q.pop(); for (int i = 0; i < b; ++i) { if (!nex[x][i]) nex[x][i] = nex[fal[x]][i]; else { int y = nex[x][i]; if (x == 0) fal[y] = 0; else fal[y] = nex[fal[x]][i]; out[y] += out[fal[y]]; q.push(y); } } } } int aa[210], bb[210]; int lena, lenb; int down() { int res = 0; for (int pos = 0, i = 0; i < lena; ++i) { pos = nex[pos][aa[i]]; res += out[pos]; } return res <= k; } int ask() { ++cas; long long ans = 0; for (int i = 1; i < s[0]; ++i) ans += dp(nex[0][i], 1, out[nex[0][i]], 1); ans += dp(nex[0][s[0]], 1, out[nex[0][s[0]]], 0); for (int i = 1; i < n; ++i) for (int j = 1; j < b; ++j) ans += dp(nex[0][j], i + 1, out[nex[0][j]], 1); return ans % inf; } int main() { scanf( %d %d %d , &q, &b, &k); scanf( %d , &lena); for (int i = 0; i < lena; ++i) scanf( %d , &aa[i]); scanf( %d , &lenb); for (int i = 0; i < lenb; ++i) scanf( %d , &bb[i]); int len, w; while (q--) { scanf( %d , &len); for (int i = 0; i < len; ++i) scanf( %d , &s[i]); scanf( %d , &w); add(len, w); } bfs(); cas = 1; n = lena; for (int i = 0; i < lena; ++i) s[i] = aa[i]; int res = ask(); cas = 2; n = lenb; for (int i = 0; i < lenb; ++i) s[i] = bb[i]; int ans = ask(); cout << (ans + down() + inf - res) % inf << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void mohammed() { ios::sync_with_stdio(0); ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); } int main() { mohammed(); int n, x, y; cin >> n; map<int, int> mp; map<int, int>::iterator it; for (int i = 0; i < n; i++) { cin >> x >> y; mp[x]++; mp[y + 1]--; } x = 0; for (it = mp.begin(); it != mp.end(); it++) { it->second += x; if (it->second > 2) { cout << NO ; return 0; } x = it->second; } cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; int trie[64 * 100005][2], uni; inline long long int bin_to_int(vector<long long int> vt) { long long int ans = 0, hudai = 1; while (vt.size()) { ans += (hudai * vt[vt.size() - 1]); hudai *= 2; vt.pop_back(); } return ans; } inline vector<long long int> int_to_bin(long long int n) { vector<long long int> ans(64), tem; while (n > 0) { tem.push_back(n % 2); n /= 2; } for (int i = 0; i < (tem.size()); i++) { ans[63 - i] = tem[i]; } return ans; } inline long long int search(vector<long long int> vt) { int cur = 1; vector<long long int> ans; for (int i = 0; i < (64); i++) { int id = (vt[i] + 1) % 2; if (trie[cur][id]) { ans.push_back(1); cur = trie[cur][id]; } else { ans.push_back(0); cur = trie[cur][vt[i]]; } } return bin_to_int(ans); } inline void insert(vector<long long int> vt) { int cur = 1; for (int i = 0; i < (64); i++) { int id = vt[i]; if (!trie[cur][id]) trie[cur][id] = ++uni; cur = trie[cur][id]; } return; } int main() { int n; scanf( %d , &n); vector<long long int> vt; uni = 1; for (int i = 0; i < (n); i++) { long long int xx; scanf( %lld , &xx); vt.push_back(xx); } vector<long long int> hudai; hudai.push_back(0); vt.push_back(0); for (int i = 0; i < (n); i++) hudai.push_back(hudai[hudai.size() - 1] ^ vt[i]); long long int maximum = 0; long long int xr = 0; for (int i = hudai.size() - 1; i >= 0; i--) { long long int xx = hudai[i]; xr = xr ^ vt[i]; vector<long long int> tem = int_to_bin(xr); insert(tem); tem = int_to_bin(xx); maximum = max(maximum, search(tem)); } printf( %lld n , maximum); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_TB_V
`define SKY130_FD_SC_LS__DECAPHE_TB_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__decaphe dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_TB_V
|
#include <bits/stdc++.h> using namespace std; long long int n, k; vector<long long int> v[100005]; vector<long long int> res; long long int ares[100005]; long long int was[100005]; int dfs(long long int ind, long long int c) { if (c > 100005) { return -1; } if (ares[ind]) return 1; if (!v[ind].size()) { ares[ind] = 1; res.push_back(ind); return 1; } for (auto i : v[ind]) { int r = dfs(i, c + 1); if (r < 0) { return -1; } } ares[ind] = 1; res.push_back(ind); return 1; } int main() { cin >> n >> k; long long int *arr = new long long int[k]; for (long long int i = 0; i < k; i++) { cin >> arr[i]; arr[i]--; } for (long long int i = 0; i < n; i++) { ares[i] = 0; long long int a, b; cin >> b; for (long long int j = 0; j < b; j++) { cin >> a; a--; v[i].push_back(a); } } for (long long int i = 0; i < k; i++) { int r = dfs(arr[i], 0); if (r < 0) { cout << -1; return 0; } } cout << res.size() << endl; for (auto i : res) { cout << (i + 1) << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { double eps = 1e-12; double y1, y2, yw, xb, yb, r; cin >> y1 >> y2 >> yw >> xb >> yb >> r; double yk = yw - r; double yt = y1 + r; double d1 = yk - yt; double d2 = yk - yb; double xk = xb * d1 / (d2 + d1); double A = yt - yk; double B = xk; double C = -B * yt; double h = fabs(B * y2 + C) / sqrt(A * A + B * B); if (r > h - eps) { cout << -1 << endl; } else { printf( %.12lf n , xk - eps); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, m, k, t, cs, n, mx, v; scanf( %d , &n), scanf( %d , &m); int cnt = 0, ppl = 0; for (i = 1; i <= n; i++) { scanf( %d , &v); if (ppl + v <= m) ppl += v; else { cnt++; ppl = v; } } if (ppl) cnt++; printf( %d n , cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; using lint = long long; bool has(int s, int x) { int i = s / 50 % 475; for (int ii = (0); ii < int(25); ++ii) { i = (i * 96 + 42) % 475; if (i + 26 == x) { return true; } } return false; } void solve(istream& cin, ostream& cout) { int p, x, y; cin >> p >> x >> y; for (int i = 0; x - i * 50 >= y; i++) { if (has(x - i * 50, p)) { cout << 0; return; } } for (int i = 1;; i++) { if (has(x + i * 100, p) || has(x + i * 100 - 50, p)) { cout << i; return; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(cin, cout); return 0; } |
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [7:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] MAPPED_ADDR,// Address to request from SRAM0
output SRAM0_HIT, // enable SRAM0
output SRAM1_HIT, // enable SRAM1
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_GAMEPAKRAM, // address mapped as gamepak RAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output gsu_enable,
output r213f_enable,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4
;
wire [23:0] SRAM_SNES_ADDR;
/* ROM (max. 2 MB) at:
Bank 0x00-0x3f, Offset 8000-ffff
Bank 0x40-0x5f, Offset 0000-ffff
XXX: higan also accepts the following:
Bank 0x00-0x3f, Offset 0000-7fff
This duplicates the mapping in the 0000-7fff range.
*/
assign IS_ROM = ((~|SNES_ADDR[23:22] & SNES_ADDR[15])
|(!SNES_ADDR[23] & SNES_ADDR[22] & !SNES_ADDR[21]));
/* Save RAM (max. 128 kB) at:
Bank 0x78-0x79, Offset 0000-ffff */
assign IS_SAVERAM = SAVERAM_MASK[0] & (!SNES_ADDR[23] & &SNES_ADDR[22:20] & SNES_ADDR[19] & ~|SNES_ADDR[18:17]);
/* Gamepak RAM (max. 128 kB) at:
Bank 0x00-0x3f, Offset 6000-7fff
Bank 0x70-0x71, Offset 0000-ffff
Bank 0x80-0xbf, Offset 6000-7fff
XXX: Hmm, this doesn't seem to be making much sense. Two of the areas are
512 kB in size! Only 16 banks of 8 kB are needed for 128 kB.
Using these instead:
Bank 0x00-0x0f, Offset 6000-7fff
Bank 0x70-0x71, Offset 0000-ffff
Bank 0x80-0x8f, Offset 6000-7fff
XXX: higan maps the gamepak RAM at:
Bank 0x60-0x7f, Offset 0000-ffff
This effectively duplicates the mapping in 0x60-0x61, 0x62-0x63, etc.
*/
assign IS_GAMEPAKRAM = ((~|SNES_ADDR[22:20] & (SNES_ADDR[15:13] == 3'b011))
|(&SNES_ADDR[22:20] & ~|SNES_ADDR[19:17]));
assign IS_WRITABLE = IS_SAVERAM | IS_GAMEPAKRAM;
/* The Save RAM, ROM and gamepak RAM are laid out in the physical RAM as follows:
Save RAM addresses:
Bank 0x78-0x79: 0111 100a xxxx xxxx xxxx xxxx mapped to:
1110 000a xxxx xxxx xxxx xxxx
ROM addresses:
Bank 0x00-0x3f: address 00aa bbbb 1xxx xxxx xxxx xxxx mapped to:
000a abbb bxxx xxxx xxxx xxxx
Bank 0x40-0x5f: address 010a bbbb xxxx xxxx xxxx xxxx mapped to:
000a bbbb xxxx xxxx xxxx xxxx
Gamepak RAM addresses:
Bank 0x00-0x0f: address 0000 aaaa 011x xxxx xxxx xxxx mapped to:
1100 000a aaax xxxx xxxx xxxx
Bank 0x70-0x71: address 0111 000a xxxx xxxx xxxx xxxx mapped to:
1100 000a xxxx xxxx xxxx xxxx
Bank 0x80-0x8f: address 1000 aaaa 011x xxxx xxxx xxxx mapped to:
1100 000a aaax xxxx xxxx xxxx
*/
assign SRAM_SNES_ADDR = IS_SAVERAM
? (24'hE00000 | SNES_ADDR[16:0] & SAVERAM_MASK)
: (IS_ROM
? (~|SNES_ADDR[23:22] & SNES_ADDR[15])
? /* Bank 0x00-0x3f, Offset 8000-ffff */
({3'b000, SNES_ADDR[21:16], SNES_ADDR[14:0]} & ROM_MASK)
: /* Bank 0x40-0x5f, Offset 0000-ffff */
({3'b000, SNES_ADDR[20:0]} & ROM_MASK)
: (IS_GAMEPAKRAM
? (~|SNES_ADDR[22:20] & (SNES_ADDR[15:13] == 3'b011))
? /* Banks 0x00-0x0f and 0x80-0x8f */
({7'b1100000, SNES_ADDR[19:16], SNES_ADDR[12:0]})
: /* Banks 0x70-0x71 */
({7'b1100000, SNES_ADDR[16:0]})
: SNES_ADDR));
assign MAPPED_ADDR = SRAM_SNES_ADDR;
assign SRAM0_HIT = IS_ROM | (!IS_GAMEPAKRAM & IS_WRITABLE);
assign SRAM1_HIT = IS_GAMEPAKRAM;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
/* GSU MMIO interface is at:
Bank 0x00-0x3f, Offset 3000-32ff
Bank 0x80-0xbf, Offset 3000-32ff */
wire gsu_enable_w = (!SNES_ADDR[22] & (SNES_ADDR[15:10] == 6'b001100) & (!SNES_ADDR[9] | !SNES_ADDR[8]));
assign gsu_enable = gsu_enable_w;
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A5A);
assign branch1_enable = (SNES_ADDR == 24'h002A13);
assign branch2_enable = (SNES_ADDR == 24'h002A4D);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_4_V
`define SKY130_FD_SC_MS__INV_4_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { vector<pair<int, int>> v; int i, a, b, index = 0, dp[1000005] = {0}, ans = INT_MIN, n; cin >> n; for (long long int i = 0; i < n; i++) { cin >> a >> b; v.push_back({a, b}); } sort((v).begin(), (v).end()); for (i = 0; i < n; i++) { while (index != v[i].first) { dp[index] = dp[max(0, index - 1)]; index++; } if (index - v[i].second - 1 < 0) dp[index] = 1; else dp[index] = dp[index - v[i].second - 1] + 1; ans = max(ans, dp[index]); index++; } cout << n - ans; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, q, step[1000000]; long long a[2 * 1000000], pref[2 * 1000000 + 1]; int calcLen(int strt) { int curr = strt, res = 0; while (curr < strt + n) curr += step[curr % n], res++; return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> q; for (int i = 0; i < (n); i++) cin >> a[i]; for (int i = 0; i < (n); i++) a[n + i] = a[i]; for (int i = 0; i < (2 * n); i++) pref[i + 1] = pref[i] + a[i]; for (int query = 0; query < (q); query++) { long long b; cin >> b; int lo = 0, hi = 0; while (lo < n) { while (lo < n && (hi == lo + n + 1 || pref[hi] > pref[lo] + b)) { step[lo] = hi - lo - 1; lo++; } hi++; } int res = INT_MAX; pair<int, int> mn = make_pair(INT_MAX, -1); for (int i = 0; i < (n); i++) if (step[(i + n - 1) % n] <= step[i]) mn = min(mn, make_pair(step[i], i)); for (int i = 0; i < (mn.first); i++) res = min(res, calcLen((mn.second + i) % n)); cout << res << n ; } } |
//------------------------------------------------------------------
// Dual port memory (one read and one write port, same width)
//------------------------------------------------------------------
module dp_ram #(
parameter adr_width = 13,
parameter dat_width = 16,
parameter mem_file_name = "none"
) (
// write port a
input clk_a,
input en_a,
input en_b,
input [adr_width-1:0] adr_a,
input [dat_width-1:0] dat_a,
// read port b
input clk_b,
input [adr_width-1:0] adr_b,
output reg [dat_width-1:0] dat_b,
output reg [dat_width-1:0] dat_a_out,
input we_a
);
parameter depth = (1 << adr_width);
// actual ram cells
reg [dat_width-1:0] ram [0:depth-1];
//------------------------------------------------------------------
// read port B
//------------------------------------------------------------------
always @(posedge clk_b)
begin
if (en_b)
dat_b <= ram[adr_b];
end
//------------------------------------------------------------------
// write port A
//------------------------------------------------------------------
always @(posedge clk_a)
begin
if (en_a) begin
if (we_a) begin
ram[adr_a] <= dat_a;
end else dat_a_out<=ram[adr_a];
end
end
initial
begin
if (mem_file_name != "none")
begin
$readmemh(mem_file_name, ram);
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module Eblock(
input [0:31] R,
output [0:47] Rout
//, input CLK
);
assign Rout = {R[31], R[0], R[1], R[2], R[3], R[4], R[3], R[4], R[5], R[6], R[7], R[8], R[7], R[8], R[9], R[10], R[11], R[12], R[11], R[12], R[13], R[14], R[15], R[16], R[15], R[16], R[17], R[18], R[19], R[20], R[19], R[20], R[21], R[22], R[23], R[24], R[23], R[24], R[25], R[26], R[27], R[28], R[27], R[28], R[29], R[30], R[31], R[0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; map<string, int> a; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; while (n--) { int temp_val; string temp_s; cin >> temp_val >> temp_s; sort(temp_s.begin(), temp_s.end()); if (a[temp_s] < 1) a[temp_s] = temp_val; else a[temp_s] = min(a[temp_s], temp_val); } int ans = INT_MAX; if (a[ A ] >= 1 && a[ B ] >= 1 && a[ C ] >= 1) ans = a[ A ] + a[ B ] + a[ C ]; if (a[ A ] >= 1 && a[ BC ] >= 1) ans = min(ans, a[ A ] + a[ BC ]); if (a[ C ] >= 1 && a[ AB ] >= 1) ans = min(ans, a[ C ] + a[ AB ]); if (a[ B ] >= 1 && a[ AC ] >= 1) ans = min(ans, a[ B ] + a[ AC ]); if (a[ AB ] >= 1 && a[ BC ] >= 1) ans = min(ans, a[ AB ] + a[ BC ]); if (a[ AC ] >= 1 && a[ AB ] >= 1) ans = min(ans, a[ AC ] + a[ AB ]); if (a[ BC ] >= 1 && a[ AC ] >= 1) ans = min(ans, a[ BC ] + a[ AC ]); if (a[ ABC ] >= 1) ans = min(ans, a[ ABC ]); if (ans == INT_MAX) cout << -1 << endl; else cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000000000 ) using namespace std; int n; double a[500001], b[500001], p, q; string st; double calc(double y1) { double y2 = 1.; for (int i = 0; i < n; i++) { y2 = min(y2, (1. - (a[i] * y1)) / b[i]); } double ret = p * y1 + q * y2; return ret; } int main() { cin >> n >> p >> q; double maxi = 0; for (int i = 0; i < n; i++) { cin >> a[i] >> b[i]; maxi = max(a[i], maxi); } double l = 0, r = 1. / maxi; for (int i = 0; i < 100; i++) { double m1 = (fabs(l - r)) / 3; double x1 = calc(l + m1), x2 = calc(r - m1); if (x1 >= x2) r = r - m1; else l = l + m1; } printf( %.10lf n , calc(l)); return 0; } |
`timescale 1ns / 100ps
module sasc_brg(/*AUTOARG*/
// Outputs
sio_ce, sio_ce_x4,
// Inputs
clk, arst_n
);
output sio_ce; // baud rate
output sio_ce_x4; // baud rate x 4
input clk;
input arst_n;
reg sio_ce;
reg sio_ce_x4;
parameter br_38400_16MHz = 103; // 16e6 / (38400*4) = 104 = 103 + 1
parameter br_31250_40MHz = 319; // 40e6 / (31250*4) = 320 = 319 + 1
parameter br_31250_60MHz = 479; // 60e6 / (31250*4) = 480 = 479 + 1
parameter br_57600_40MHz = 173; // 40e6 / (57600*4) = 174 = 173 + 1
parameter br_57600_60MHz = 260; // 60e6 / (57600*4) = 261 = 260 + 1
//`define BRX4pre &{brx4_cntr[6:5],brx4_cntr[2:0]}
//`define BRX4pre &{brx4_cntr[8],brx4_cntr[5:0]} // 31250 baud rate 40MHz
//`define BRX4pre &{brx4_cntr[7],brx4_cntr[5],brx4_cntr[3:2],brx4_cntr[0]} // 57600 baud rate 40MHz
`define BRX4pre &{brx4_cntr[8],brx4_cntr[2]} // 57600 baud rate 60MHz
reg [8:0] brx4_cntr;
reg [1:0] br_cntr;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
brx4_cntr <= 0;
else if (`BRX4pre)
brx4_cntr <= 0;
else
brx4_cntr <= brx4_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
br_cntr <= 0;
else if (`BRX4pre)
br_cntr <= br_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
begin
sio_ce_x4 <= 1'b0;
sio_ce <= 1'b0;
end
else
begin
sio_ce_x4 <= `BRX4pre;
sio_ce <= (&br_cntr) & (`BRX4pre);
end
endmodule // sasc_brg
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam_bhv.v: Behavioral description of Binary Content Addressasble Memory (BCAM)//
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module bcam_bhv
#( parameter CAMD = 512, // CAM depth
parameter CAMW = 32 , // CAM/pattern width
parameter INOM = 1 ) // binary / Initial CAM with no match (has priority over IFILE)
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CAMD)-1:0] wAddr , // write address
input [ CAMW -1:0] wPatt , // write pattern
input [ CAMW -1:0] mPatt , // patern to match
output reg match , // match indicator
output reg [`log2(CAMD)-1:0] mAddr ); // matched address
// assign memory array
reg [CAMW-1:0] mem [0:CAMD-1];
// valid bit
reg [CAMD-1:0] vld;
// initialize memory, with zeros if INOM or file if IFILE.
integer i;
initial
if (INOM)
for (i=0; i<CAMD; i=i+1)
{vld[i],mem[i]} = {1'b0,{CAMW{1'b0}}};
always @(posedge clk) begin
// write to memory
if (wEnb)
{vld[wAddr],mem[wAddr]} = {1'b1,wPatt};
// search memory
match = 0;
mAddr = 0;
match = (mem[mAddr]==mPatt) && vld[mAddr];
while ((!match) && (mAddr<(CAMD-1))) begin
mAddr=mAddr+1;
match = (mem[mAddr]==mPatt) && vld[mAddr];
end
end
endmodule
|
// Arbitrary-sized RAM.
//
// Both Lattice and Synopsis do not seem
// to be capable of infering cascaded BRAMs
// out-of-the-box, hence the mess below.
module ram #(
parameter WIDTH = 16,
parameter ADDR_WIDTH = 8
) (
input [WIDTH - 1:0] din,
input wire [ADDR_WIDTH - 1:0] addr,
input wire write_en,
input clk,
output reg [WIDTH - 1:0] dout);
localparam HI = WIDTH - 1;
localparam NWORDS = (WIDTH + 15) / 16;
localparam WIDTH_PAD = NWORDS * 16 - WIDTH;
localparam WIDTH_ALIGN = NWORDS * 16;
// Address
// addr[ADDR_WIDTH - 1:0]
// is split to 'offset' (in 16-bit words):
// offset = addr[7:0]
// and 'selector':
// sel = addr[ADDR_WIDTH - 1:8]
// The 8-bit 'offset' part can be mapped to block RAM
// and 'sel' is then implemented on top of it as mux.
localparam SEL_WIDTH = ADDR_WIDTH <= 8 ? 0 : ADDR_WIDTH - 8;
localparam NSEL = 1 << SEL_WIDTH;
wire [WIDTH_ALIGN - 1:0] din_pad;
wire [NSEL*WIDTH_ALIGN - 1:0] douts;
wire [7:0] offset;
wire [SEL_WIDTH - 1:0] sel;
assign din_pad = din;
assign offset = addr[7:0];
assign sel = NSEL == 1 ? 1'b0 : addr[ADDR_WIDTH - 1:8];
genvar i, j;
generate
for(i = 0; i < NSEL; i = i + 1) begin
for(j = 0; j < WIDTH_ALIGN; j = j + 16) begin
ram256x16 bank (
.din(din_pad[j + 15:j]),
.addr(offset),
.write_en(write_en & (sel == i)), // TODO: use decoder?
.clk(clk),
.dout(douts[i*WIDTH_ALIGN + j + 15:i*WIDTH_ALIGN + j]));
end
end
endgenerate
integer k, l;
always @* begin
dout = {WIDTH{1'bx}};
for(k = 0; k < NSEL; k = k + 1) begin
if (sel == k) // TODO: use decoder?
for (l = 0; l < WIDTH; l = l + 1)
dout[l] = douts[k*WIDTH_ALIGN + l];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { cin.sync_with_stdio(0); int t; cin >> t; string p, h; while (t--) { cin >> p >> h; int n = p.size(); int cnt[26]; memset(cnt, 0, sizeof cnt); for (int i = 0; i < n; i++) cnt[p[i] - a ]++; int m = h.size(); bool ok = 0; for (int i = 0; !ok && i <= m - n; i++) { int c2[26]; memset(c2, 0, sizeof c2); for (int j = 0; j < n; j++) { c2[h[i + j] - a ]++; } ok = 1; for (int j = 0; ok && j < 26; j++) if (cnt[j] != c2[j]) ok = 0; } if (ok) puts( YES ); else puts( NO ); } } |
`timescale 1ns / 1ps
// UART wants the LSB first
// RX modified to accept 40 MHz clock and receive at 115200 bps
// Note 40e6 / 115200 = and 347.2 / 2 = 173.6 ~= 174 cycles
// For 460800
// 40e6 / 460800 = 86.8 and 86.8 / 2 =~= 43
// For 230400
// 40e6 / 230400 = 173.6 and 173.6/2 = 86.8
// Modified for 460800 baud rate
module uart_tx (
input reset,
input clk,
input [1:0] baud_rate,
input ld_tx_data,
input [7:0] tx_data,
input tx_enable,
(* IOB = "TRUE" *) output reg tx_out,
output reg tx_empty
);
parameter ML505 = 0; //default to 0 if not specified
// Internal registers
reg [7:0] tx_reg;
//reg tx_over_run ;
reg [3:0] tx_cnt;
reg [9:0] baud_cnt;
reg baud_clk;
// UART TX Logic
always @ (posedge clk) begin
if (reset) begin
baud_clk <= 1'b0;
baud_cnt <= 10'b0;
tx_reg <= 8'd0;
tx_empty <= 1'b1;
//tx_over_run <= 0;
tx_out <= 1'b1;
tx_cnt <= 4'd0;
end else begin // if (reset)
if (ML505) begin
if (baud_cnt == 10'd868) begin
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end else begin
case(baud_rate)
2'd0: begin // 115200 Baud
if (baud_cnt == 10'd347) begin
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
2'd1: begin
if (baud_cnt == 10'd174) begin // 230400 Baud
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
2'd2: begin
if (baud_cnt == 10'd87) begin // 460800 Baud
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
default: begin // deafult to 115200 Baud
if (baud_cnt == 10'd347) begin
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
endcase
end //if (~ML505)
if (tx_enable && baud_clk) begin
if (ld_tx_data && tx_empty) begin
tx_reg <= tx_data;
tx_empty <= 1'b0;
tx_out <= 1'b0; //Send start bit immediately
tx_cnt <= tx_cnt;
//tx_over_run <= 0; // um.... ??
end else if (!tx_empty) begin
tx_reg <= tx_reg;
if (tx_cnt == 4'd8) begin
tx_cnt <= 4'd0;
tx_out <= 1'b1;
tx_empty <= 1'b1;
end else begin
tx_cnt <= tx_cnt + 1;
tx_out <= tx_reg[tx_cnt];
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end //if (~(tx_enable && baud_clk))
end //if (~reset)
end //always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_4_V
`define SKY130_FD_SC_HS__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_4_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire [3:0] sw,
input wire [3:0] btn,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* Ethernet: 100BASE-T MII
*/
output wire phy_ref_clk,
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
input wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_en,
input wire phy_col,
input wire phy_crs,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
// Internal 125 MHz clock
wire clk_mmcm_out;
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
wire clk_25mhz_mmcm_out;
wire clk_25mhz_int;
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// Divide by 40 to get output frequency of 25 MHz
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(40),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk_25mhz_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
BUFG
clk_25mhz_bufg_inst (
.I(clk_25mhz_mmcm_out),
.O(clk_25mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btn,
sw}),
.out({btn_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
assign phy_ref_clk = clk_25mhz_int;
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led0_r(led0_r),
.led0_g(led0_g),
.led0_b(led0_b),
.led1_r(led1_r),
.led1_g(led1_g),
.led1_b(led1_b),
.led2_r(led2_r),
.led2_g(led2_g),
.led2_b(led2_b),
.led3_r(led3_r),
.led3_g(led3_g),
.led3_b(led3_b),
.led4(led4),
.led5(led5),
.led6(led6),
.led7(led7),
/*
* Ethernet: 100BASE-T MII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_col(phy_col),
.phy_crs(phy_crs),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_144x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_144x256 (
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input clock;
input [143:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [143:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire [143:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [7:0] usedw = sub_wire1[7:0];
wire empty = sub_wire2;
wire [143:0] q = sub_wire3[143:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 250,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 144,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "250"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "144"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "144"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "250"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL data[143..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 144 0 OUTPUT NODEFVAL q[143..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
// Retrieval info: CONNECT: q 0 0 144 0 @q 0 0 144 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n, memo[100001]; vector<long long> a; long long x; long long rek(int pos) { long long &ret = memo[pos]; if (ret != -1) return ret; ret = rek(pos - 1) + 20; x = upper_bound(a.begin(), a.end(), a[pos] - 90) - a.begin(); if (x) ret = min(ret, rek(x - 1) + 50); else ret = min(ret, 50LL); x = upper_bound(a.begin(), a.end(), a[pos] - 1440) - a.begin(); if (x) ret = min(ret, rek(x - 1) + 120); else ret = min(ret, 120LL); return ret; } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x; a.push_back(x); } memset(memo, -1, sizeof(memo)); memo[0] = 20; rek(n - 1); for (int i = 0; i < n; i++) if (!i) cout << memo[i] << endl; else cout << memo[i] - memo[i - 1] << endl; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4.1,sse4.2,avx,avx2,popcnt,tune=native ) using namespace std; int n, m, k, ct[200010], cnt; vector<pair<int, int> > e[200010]; vector<int> mp[200010]; char bf[100000], *p1 = bf, *p2 = bf; inline int read() { int x = 0; char ch = (p1 == p2 && (p2 = (p1 = bf) + fread(bf, 1, 100000, stdin), p2 == p1) ? -1 : *p1++); for (; ch < 0 || ch > 9 ; ch = (p1 == p2 && (p2 = (p1 = bf) + fread(bf, 1, 100000, stdin), p2 == p1) ? -1 : *p1++)) ; for (; ch <= 9 && ch >= 0 ; x = x * 10 + ch - 48, ch = (p1 == p2 && (p2 = (p1 = bf) + fread(bf, 1, 100000, stdin), p2 == p1) ? -1 : *p1++)) ; return x; } int ans, O = 1; int hah, val[10][200010]; void dfs(int x, int f) { if (x == k + 1) { if (f == hah) ++ans; return; } if (mp[x].size() == 0) { dfs(x + 1, f); return; } for (auto i = (1); i <= (x); ++i) { int flag = 1; dfs(x + 1, f + val[x][i]); } } int hsh[200010]; inline void solve() { n = read(), m = read(), k = read(); for (auto i = (1); i <= (n); ++i) hsh[i] = rand(), hah += hsh[i]; for (auto i = (1); i <= (m); ++i) { int u = read(), v = read(), w = read(); e[u].push_back({w, v}); } for (auto i = (1); i <= (n); ++i) sort(e[i].begin(), e[i].end()); for (auto i = (1); i <= (n); ++i) mp[e[i].size()].push_back(i); for (auto i = (1); i <= (k); ++i) for (auto j = (1); j <= (i); ++j) { val[i][j] = 0; for (auto v : mp[i]) val[i][j] += hsh[e[v][j - 1].second]; } for (auto i = (1); i <= (k); ++i) if (mp[i].size() == 0) O *= i; dfs(1, 0); printf( %d n , ans * O); } int main() { int T = 1; while (T--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long N; cin >> N; vector<long long> V; long long Sum = N; for (long long i = 0; i < N; i++) { long long X; cin >> X; V.push_back(X); } long long L = 0; long long Cnt = 0; for (long long i = 0; i < N; i++) { if (V[i] == V[L]) Cnt++; else { if (Cnt >= 2) Sum += Cnt * (Cnt - 1) / 2; while (V[L] != V[i]) { L++; Cnt--; } Cnt++; } } if (Cnt >= 2) Sum += Cnt * (Cnt - 1) / 2; cout << Sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long n, long long lelo) { if (n == 0) return 1; if (n == 1) return a; if (n == 2) return (a * a) % lelo; if (n % 2) return (a * power(a, n - 1, lelo)) % lelo; else return power(power(a, n / 2, lelo), 2, lelo) % lelo; } void swap(long long &a, long long &b) { long long tm = a; a = b; b = tm; } const long long N = 1e+5; bool comp(const pair<long long, long long> &p1, const pair<long long, long long> &p2) { if (p1.first != p2.first) return p1.first > p2.first; else return p1.second < p2.second; } long long n, k; vector<long long> v; bool chk(long long x) { for (long long(i) = (0); (i) < (n); (i)++) if (abs(v[i] - x) > k) return 0; return 1; } void solve() { cin >> n >> k; v.resize(n); for (long long(i) = (0); (i) < (n); (i)++) cin >> v[i]; sort((v).begin(), (v).end()); long long t1 = v[0] + k, t2 = v[n - 1] - k; if (v[n - 1] - v[0] <= k) { cout << v[0] + k; return; } if (t2 > t1) { cout << -1; return; } cout << t1; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long double tt = 1.0 * clock(); long long t = 1; cin >> t; for (long long(i) = (1); (i) < (t + 1); (i)++) { solve(); if (i < t) cout << n ; } tt = 1.000000000 * (clock() - tt) / CLOCKS_PER_SEC; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module util_pmod_fmeter (
ref_clk,
square_signal,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
// physical interface
input ref_clk;
input square_signal;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal signals
wire up_clk;
wire up_rstn;
wire reset;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] signal_freq_s;
//defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_valid = 1'b1;
// frequency measurment module
util_pmod_fmeter_core i_util_pmod_fmeter_core (
.ref_clk(ref_clk),
.reset(reset),
.square_signal(square_signal),
.signal_freq(signal_freq_s));
// register map
up_pmod i_up_pmod(
.pmod_clk(ref_clk),
.pmod_rst(reset),
.pmod_signal_freq(signal_freq_s),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq_s),
.up_waddr(up_waddr_s),
.up_wdata(up_wdata_s),
.up_wack(up_wack_s),
.up_rreq(up_rreq_s),
.up_raddr(up_raddr_s),
.up_rdata(up_rdata_s),
.up_rack(up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, pos, ans; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> t; while (t--) { cin >> s; ans = pos = 0; s += R ; for (int i = 0; i < s.size(); i++) { if (s[i] == R ) { ans = max(ans, (i + 1) - pos); pos = (i + 1); } } cout << ans << n ; } return 0; } |
module nh_lcd_command (
input rst,
input clk,
output [31:0] debug,
//Control Signals
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output reg [7:0] o_cmd_data,
input i_enable,
input i_cmd_parameter,
output reg o_cmd_finished,
//Physical Signals
output o_cmd_mode,
output reg o_write,
output reg o_read,
output reg [7:0] o_data_out,
input [7:0] i_data_in,
output reg o_data_out_en
);
//Local Parameters
localparam IDLE = 4'h0;
localparam FINISHED = 4'h1;
//Registers/Wires
reg [3:0] state;
//Submodules
//Asynchronous Logic
assign o_cmd_mode = i_cmd_parameter;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
o_data_out_en <= 0;
o_data_out <= 0;
o_cmd_finished <= 0;
o_cmd_data <= 0;
o_write <= 0;
o_read <= 0;
end
else begin
//Strobes
o_cmd_finished <= 0;
//State Machine
case (state)
IDLE: begin
o_write <= 0;
o_read <= 0;
o_data_out_en <= 0;
if (i_cmd_write_stb) begin
//Change the bus to an output
o_data_out_en <= 1;
//Put the data on the bus
o_data_out <= i_cmd_data;
o_write <= 1;
state <= FINISHED;
end
else if (i_cmd_read_stb) begin
//Change the bus to an input
o_data_out_en <= 0;
o_read <= 1;
state <= FINISHED;
end
end
FINISHED: begin
o_write <= 0;
o_read <= 0;
if (!o_data_out_en) begin
//XXX: The appliction note doesn't describe how to explicitly read
//and the protocol is different from the 8080 MCU interface
o_cmd_data <= i_data_in;
end
o_cmd_finished <= 1;
state <= IDLE;
end
endcase
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2019.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Synchronizer for BUFG_GT Control Signals
// /___/ /\ Filename : BUFG_GT_SYNC.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 02/03/14 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFG_GT_SYNC
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output CESYNC,
output CLRSYNC,
input CE,
input CLK,
input CLR
);
// define constants
localparam MODULE_NAME = "BUFG_GT_SYNC";
wire CE_in;
wire CLK_in;
wire CLR_in;
assign CE_in = (CE === 1'bz) || CE; // rv 1
assign CLK_in = CLK;
assign CLR_in = (CLR !== 1'bz) && CLR; // rv 0
// begin behavioral model
assign CESYNC = CE_in;
assign CLRSYNC = CLR_in;
// end behavioral model
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int n, r = 0; cin >> n; string s; cin >> s; for (int i = 0; i < n - 1; i++) { if (s[i] == s[i + 1]) r++; } cout << r; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return b < a ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int oo = 0x3f3f3f3f; const int maxn = 1000100; int n; char a[maxn + 5]; inline bool check(int first) { vector<int> man, aster; for (int i = (0), i_end_ = (n); i < i_end_; ++i) { if (a[i] == P ) man.push_back(i); else if (a[i] == * ) aster.push_back(i); } int nman = (int((man).size())), naster = (int((aster).size())); static bool dp[maxn + 5][2]; memset(dp, 0, sizeof dp); int j = nman - 1; dp[naster][0] = dp[naster][1] = 1; for (int i = naster - 1; i >= 0; --i) { j = min((int((man).size())) - 1, j + 1); while (j >= 0 && man[j] > aster[i]) { bool ok = 0; if (man[j] - first <= aster[i]) { int tmp = man[j]; if (j && man[j - 1] > aster[i]) chkmax(tmp, man[j - 1] + first); int fir = upper_bound((aster).begin(), (aster).end(), tmp) - aster.begin(); if (fir == naster || (j + 1 < (int((man).size())) && aster[fir] > man[j + 1])) ok = dp[fir][1]; else ok = dp[fir][0]; } if (ok) { dp[i][0] = 1; break; } --j; } if (dp[i][0]) dp[i][1] = 1; else { if (j >= 0) { int tmp = man[j] + first; int fir = upper_bound((aster).begin(), (aster).end(), tmp) - aster.begin(); if (fir == naster || (j + 1 < (int((man).size())) && aster[fir] > man[j + 1])) { dp[i][1] = dp[fir][1]; } else dp[i][1] = dp[fir][0]; } } } return dp[0][1]; } int main() { scanf( %d , &n); scanf( %s , a); bool unique = 1; int p = -1; int Max = 0, Min = oo; int tot = 0, left = 0; for (int i = (0), i_end_ = (n); i < i_end_; ++i) if (a[i] == P ) { if (~p) { unique = 0; } else { left = tot; p = i; } } else if (a[i] == * ) { ++tot; chkmin(Min, i), chkmax(Max, i); } if (unique) { int right = tot - left; int left_dis = p - Min; int right_dis = Max - p; auto tmp = max(make_pair(left, -left_dis), make_pair(right, -right_dis)); tmp.second = -tmp.second; printf( %d %d n , tmp.first, tmp.second); } else { int l = 0, r = n; while (l < r) { int mid = (l + r) >> 1; if (check(mid)) r = mid; else l = mid + 1; } printf( %d %d n , tot, l); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, cnt, a[2010], b[2010], bel[2010], ans[2010 * 2010 / 2][2]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); bel[b[i]] = i; } for (int i = 1; i <= n; i++) { a[i] = bel[a[i]]; cnt += abs(a[i] - i); } cnt /= 2; printf( %d n , cnt); cnt = 0; for (int i = 1; i <= n; i++) bel[a[i]] = i; for (int i = n, now = bel[n]; i; i--, now = bel[i]) for (int j = bel[i] + 1; j <= n; j++) if (a[j] <= now) { ans[++cnt][0] = j; ans[cnt][1] = now; swap(a[now], a[j]); now = j; } printf( %d n , cnt); for (int i = 1; i <= cnt; i++) printf( %d %d n , ans[i][0], ans[i][1]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { vector<int> vec1, vec2, vec3; int n, sz; cin >> n; for (int i = 1; i <= n; ++i) { int x; cin >> x; if (x == 1) vec1.push_back(i); else if (x == 2) vec2.push_back(i); else vec3.push_back(i); } sz = min(min(vec1.size(), vec2.size()), vec3.size()); cout << sz << endl; for (int i = 0; i < sz; ++i) cout << vec1[i] << << vec2[i] << << vec3[i] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; string l = 312931303130313130313031 ; string input = ; string s = 312831303130313130313031 ; string s1 = s + s + s; string s2 = l + s + s; string s3 = s + l + s; string s4 = s + s + l; long long int i; for (i = 0; i < n; i++) { string ch; cin >> ch; input += ch; } long long int flag1 = 0, flag2 = 0, flag3 = 0, flag4 = 0; for (i = 0; i < s1.length() - 2 * n; i++) { if (input.compare(s1.substr(i, n * 2)) == 0) { flag1 = 1; } } for (i = 0; i < s2.length() - 2 * n; i++) { if (input.compare(s2.substr(i, 2 * n)) == 0) { flag2 = 1; } } for (i = 0; i < s3.length() - 2 * n; i++) { if (input.compare(s3.substr(i, 2 * n)) == 0) { flag3 = 1; } } for (i = 0; i < s4.length() - 2 * n; i++) { if (input.compare(s4.substr(i, 2 * n)) == 0) { flag4 = 1; } } if (flag1 || flag2 || flag3 || flag4) { cout << YES << endl; } else { cout << NO << endl; } return 0; } |
//
// Module: Dummy switch to debug verification environment
// Author: Lianghao Yuan
// Email:
// Date: 06/25/2015
// Copyright (C) 2015 Lianghao Yuan
//
// Usage: change the name of this file to switch.v. Notice, this is
// just a simple file to test the overall connection as well as driver /
// receiver behavior.
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
module switch(input clk,
input reset,
input data_status,
input [7:0] data,
output reg [7:0] port0,
output reg [7:0] port1,
output reg [7:0] port2,
output reg [7:0] port3,
output reg ready_0,
output reg ready_1,
output reg ready_2,
output reg ready_3,
input read_0,
input read_1,
input read_2,
input read_3,
input mem_en,
input mem_rd_wr,
input [1:0] mem_add,
input [7:0] mem_data);
initial begin
port0 <= 8'b0;
port1 <= 8'b0;
port2 <= 8'b0;
port3 <= 8'b0;
ready_0 <= 1'b0;
ready_1 <= 1'b0;
ready_2 <= 1'b0;
ready_3 <= 1'b0;
// Wait until reset and configuration is ready.
repeat(100) @ (posedge clk);
// Testing first output port
ready_0 <= 1'b1;
@ (posedge clk);
@ (posedge clk);
// Send SA, DA
port0 <= 8'b1;
repeat(2) @ (posedge clk);
// Length = 1
port0 <= 8'b1;
@ (posedge clk);
// Data = 1
port0 <= 8'b1;
@ (posedge clk);
// FCS = 1
port0 <= 8'b1;
@ (posedge clk);
ready_0 <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int pow(int a, int k) { if (k == 0) return 1; int r = pow(a, k / 2); if (k % 2 == 0) return r * r; return r * r * a; } int main() { int n, ans = 1; scanf( %d , &n); for (int i = 1; (pow(2, i) - 1) * pow(2, i - 1) <= n; i++) { int v = (pow(2, i) - 1) * pow(2, i - 1); if (n % v == 0) ans = v; } printf( %d , ans); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013.
// SPDX-License-Identifier: CC0-1.0
module t
(
input logic clk,
input logic daten,
input logic [8:0] datval,
output logic signed [3:0][3:0][35:0] datao
);
logic signed [3:0][3:0][3:0][8:0] datat;
genvar i;
generate
for (i=0; i<4; i++)begin
testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i]));
end
endgenerate
genvar j;
generate
for (i=0; i<4; i++) begin
for (j=0; j<4; j++) begin
always_comb datat[i][j][0] = daten ? 9'h0 : datval;
always_comb datat[i][j][1] = daten ? 9'h1 : datval;
always_comb datat[i][j][2] = daten ? 9'h2 : datval;
always_comb datat[i][j][3] = daten ? 9'h3 : datval;
end
end
endgenerate
endmodule
module testio
(
input clk,
input logic signed [3:0] [3:0] [8:0] arr3d_in,
output logic signed [3:0] [35:0] arr2d_out
);
logic signed [3:0] [35:0] ar2d_out_pre;
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_ff @(posedge clk) begin
if (clk)
arr2d_out <= ar2d_out_pre;
end
endmodule
|
module Abc_TEST ();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [5:0] [31:0] abc; // From u_Def of Def.v
// End of automatics
Abc #(
.No1 (6),
/*AUTOINSTPARAM*/
// Parameters
.No2 (No2),
.No3 (No3/*.[No1:0][No2-1:0]*/)) u_Abc
(
/*AUTOINST*/
// Inputs
.ck (ck),
.abc (abc/*[5:0][31:0]*/));
Def #(
.No1 (6)) u_Def
(
// Outputs
.ck (ck),
/*AUTOINST*/
// Outputs
.abc (abc/*[5:0][31:0]*/));
endmodule
module Abc
#(
parameter No1 = 6,
parameter int unsigned No2 // Parameter no. 2
= pa_Abc::No2,
parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
= pa_Abc::No3
)
(
input logic ck,
input logic [No1-1:0][31:0] abc
input logic [No1-1:0][31:0] abc
);
endmodule
module Def
#(
parameter No1 = 6
)
(
input logic ck,
output logic [No1-1:0][31:0] abc
);
endmodule
// Local Variables:
// verilog-library-extensions:(".v" ".sv")
// verilog-auto-inst-param-value:t
// End:
|
// Code your testbench here
// or browse Examples
module tb_cpu;
reg clk;
wire [31:0] addr;
wire[31:0] instruction;
wire[1:0] cu_regdst;
wire cu_jump, cu_branch, cu_memread;
wire [1:0] cu_memtoreg;
wire[1:0] cu_aluop;
wire cu_memwrite, cu_aluscr, cu_regwrite;
wire[4:0] mux1_regwrite;
wire[31:0] memdata;
wire[31:0] reg_readdata1, reg_readdata2;
wire[31:0] signext_out;
wire[31:0] mux2_out;
wire[31:0] alu_out;
wire alu_zero;
wire[3:0] aluctrl_out;
wire[31:0] dmem_readdata;
wire bBranch;
wire [31:0] j_addr;
wire [31:0] next_pc;
cpu CPU1(clk, addr, instruction, cu_regdst, cu_jump, cu_branch, cu_memread, cu_memtoreg, cu_aluop, cu_memwrite, cu_aluscr, cu_regwrite, mux1_regwrite, memdata, reg_readdata1, reg_readdata2, signext_out, mux2_out, alu_out, alu_zero, aluctrl_out, dmem_readdata, bBranch, j_addr, next_pc);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
$monitor("ADDR = %b ",addr);
clk = 0;
#100 $finish;
end
always #5 clk = !clk;
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* $Id: Basics.v 13323 2010-07-24 15:57:30Z herbelin $ *)
(** Standard functions and combinators.
Proofs about them require functional extensionality and can be found
in [Combinators].
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(** The polymorphic identity function is defined in [Datatypes]. *)
Implicit Arguments id [[A]].
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Open Local Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Implicit Arguments prod_curry [[A] [B] [C]].
Implicit Arguments prod_uncurry [[A] [B] [C]].
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, a, b, x1, y1, x2, y2, d1, d2, r1 = 10000000000000000, r2 = 10000000000000000, ans; ans = r2; r1 *= -1; r2 = r1; vector<pair<long long, pair<long long, long long> > > v1, v2; cin >> n >> x1 >> y1 >> x2 >> y2; for (int i = 0; i < n; i++) { cin >> a >> b; d1 = (y1 - b) * (y1 - b) + (x1 - a) * (x1 - a); d2 = (y2 - b) * (y2 - b) + (x2 - a) * (x2 - a); v1.push_back(make_pair(d1, make_pair(a, b))); v2.push_back(make_pair(d2, make_pair(a, b))); } v1.push_back(make_pair(0, make_pair(x1, y1))); sort(v1.begin(), v1.end()); for (int i = 0; i <= n; i++) { long long rad1 = v1[i].first, rad2 = 0, itr = 1; while (rad1 == v1[i + itr].first) itr++; for (int j = i + itr; j <= n; j++) { a = v1[j].second.first; b = v1[j].second.second; d2 = (y2 - b) * (y2 - b) + (x2 - a) * (x2 - a); rad2 = max(rad2, d2); } ans = min(rad1 + rad2, ans); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void fun() { int n, k; cin >> n >> k; map<string, int> m; string s; string a[n]; for (int i = 0; i < n; i++) { cin >> s; a[i] = s; m[s]++; } int c = 0; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) { s = ; for (int p = 0; p < k; p++) { if (a[i][p] == a[j][p]) s += a[i][p]; else s += (char)( S + E + T - a[i][p] - a[j][p]); } c += m[s]; } cout << c / 3 << endl; } int main() { { fun(); } return 0; } |
/**
* bsg_serial_in_parallel_out_dynamic.v
*
* Paul Gao 06/2019
*
*/
`include "bsg_defines.v"
module bsg_serial_in_parallel_out_dynamic
#(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(max_els_p )
,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
)
(input clk_i
,input reset_i
// Input side
,input v_i
,input [lg_max_els_lp-1:0] len_i
,input [width_p-1:0] data_i
,output ready_o
,output len_ready_o
// Output side
,output v_o
,output [max_els_p-1:0][width_p-1:0] data_o
,input yumi_i
);
genvar i;
logic yumi_lo;
assign yumi_lo = v_i & ready_o;
logic [lg_max_els_lp-1:0] count_r, count_lo, len_r, len_lo;
logic clear_li, up_li, dff_en_li, go_fifo_v_li;
logic count_r_is_zero, count_r_is_last;
// fix evaluate to Z problem in simulation
assign count_lo = count_r;
// When new packet coming, use new length, otherwise use registered length
assign len_lo = (count_r_is_zero)? len_i : len_r;
assign count_r_is_zero = (count_lo == lg_max_els_lp'(0));
assign count_r_is_last = (count_lo == len_lo );
// We accept new length when first word comes in
// At this time, counter is at initial value 0
assign len_ready_o = count_r_is_zero;
// Count up if data word is not last word of current packet.
assign up_li = yumi_lo & ~count_r_is_last;
// Clear counter when it reaches target length
assign clear_li = yumi_lo & count_r_is_last;
assign go_fifo_v_li = clear_li;
// Update length register when new packet comes in
assign dff_en_li = yumi_lo & count_r_is_zero;
// Length counter
bsg_counter_clear_up
#(.max_val_p (max_els_p-1)
,.init_val_p(0)
) ctr
(.clk_i (clk_i )
,.reset_i (reset_i )
,.clear_i (clear_li)
,.up_i (up_li )
,.count_o (count_r )
);
// Length register
bsg_dff_reset_en
#(.width_p (lg_max_els_lp)
,.reset_val_p(0)
) dff_len
(.clk_i (clk_i )
,.reset_i (reset_i )
,.en_i (dff_en_li)
,.data_i (len_i )
,.data_o (len_r )
);
// Go fifo
// Notify output side that packet is ready to send
// Must use two element fifo to match lowest word data fifo!
logic one_word_lo;
bsg_two_fifo
#(.width_p(1)
) go_fifo
(.clk_i (clk_i )
,.reset_i(reset_i )
,.ready_o(/* This fifo has same size of lowest word data fifo
No need to check ready_o here */)
,.data_i (count_r_is_zero) // Indicate whether it is single word packet
,.v_i (go_fifo_v_li )
,.v_o (v_o )
,.data_o (one_word_lo )
,.yumi_i (yumi_i )
);
logic [max_els_p-1:0] fifo_valid_li, fifo_ready_lo;
logic [max_els_p-1:0] fifo_valid_lo, fifo_yumi_li;
// Ready signal from selected fifo
assign ready_o = fifo_ready_lo[count_lo];
for (i = 0; i < max_els_p; i++)
begin: rof0
if (i == 0)
// Lowest word fifo always dequeue (packet should have at least one word)
assign fifo_yumi_li[i] = yumi_i;
else
// Rest are bsg_one_fifo, only dequeue when they have valid data
//
// Corner case: a single-word packet comes in firstly, then a
// multi-word packet comes. Use one_word_lo to determine whether
// first packet is one-word or not.
//
// Case above can be prevented if we use bsg_one_fifo everywhere, but
// there will be one-cycle bubble between packets.
assign fifo_yumi_li[i] = fifo_valid_lo[i] & yumi_i & ~one_word_lo;
end
// Trigger selected valid signal
bsg_decode_with_v
#(.num_out_p(max_els_p)
) bdwv
(.i (count_lo )
,.v_i(v_i )
,.o (fifo_valid_li)
);
// Data fifos
for (i = 0; i < max_els_p; i++)
begin: fifos
if (i == 0)
begin: twofifo
// Use two element fifo to avoid bubble
bsg_two_fifo
#(.width_p(width_p)
) fifo
(.clk_i (clk_i )
,.reset_i(reset_i)
,.ready_o(fifo_ready_lo[i])
,.data_i (data_i )
,.v_i (fifo_valid_li[i])
,.v_o (fifo_valid_lo[i])
,.data_o (data_o [i])
,.yumi_i (fifo_yumi_li [i])
);
end
else
begin: onefifo
// Must use one element fifo to work correctly!
bsg_one_fifo
#(.width_p(width_p)
) fifo
(.clk_i (clk_i )
,.reset_i(reset_i)
,.ready_o(fifo_ready_lo[i])
,.data_i (data_i )
,.v_i (fifo_valid_li[i])
,.v_o (fifo_valid_lo[i])
,.data_o (data_o [i])
,.yumi_i (fifo_yumi_li [i])
);
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out_dynamic)
|
#include <bits/stdc++.h> using namespace std; void input(long long ara[], long long n) { for (long long i = 0; i < n; i++) cin >> ara[i]; } void output(long long ara[], long long n) { for (long long i = 0; i < n; i++) cout << ara[i] << ; } long long mx1(long long ara[], long long n) { long long mx = -1; for (long long i = 0; i < n; i++) if (ara[i] > mx) mx = ara[i]; return mx; } long long mn1(long long ara[], long long n) { long long mn = 1e18; for (long long i = 1; i <= n; i++) if (ara[i] < mn) mn = ara[i]; return mn; } int maxSubArraySum(long long a[], long long size) { long long max_so_far = INT_MIN, max_ending_here = 0; for (long long i = 0; i < size; i++) { max_ending_here = max_ending_here + a[i]; if (max_so_far < max_ending_here) max_so_far = max_ending_here; if (max_ending_here < 0) max_ending_here = 0; } return max_so_far; } int main() { (ios_base::sync_with_stdio(false), cin.tie(NULL)); long long t; cin >> t; while (t--) { long long n; cin >> n; long long ara[n + 1]; input(ara, n); long long k = 0, sum = 0; for (long long i = 0; i < n; i++) { sum += ara[i]; if (sum <= 0) { k = 1; } } sum = 0; for (long long i = n - 1; i >= 0; i--) { sum += ara[i]; if (sum <= 0) { k = 1; break; } } if (k == 1) cout << NO << endl; else cout << YES << endl; } } |
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; int ans = 1; for (int i = 2; i <= n; ++i) { ans = 1LL * ans * i % M; } int two = 1; for (int i = 1; i < n; ++i) { two = (two + two) % M; } cout << (ans - two + M) % M << n ; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const long long INFLL = 2e18; const int MOD = 1e8 + 7; const int N = 4e5 + 10; int fx[8] = {+0, +0, +1, -1, +1, +1, -1, -1}; int fy[8] = {+1, -1, +0, +0, +1, -1, +1, -1}; int timer; int used[N]; int tin[N], low[N]; char bridge; vector<int> g[N]; void dfsAP(int v, int p = -1) { if (bridge) return; used[v] = 1; tin[v] = low[v] = ++timer; for (int to : g[v]) { if (p == to) continue; if (!used[to]) { dfsAP(to, v); low[v] = min(low[v], low[to]); if (tin[v] < low[to]) bridge = 1; } else { low[v] = min(low[v], tin[to]); } } used[v] = 2; } void dfsCC(int v, int p = -1) { used[v] = 1; for (int to : g[v]) { if (p == to) continue; if (!used[to]) { dfsCC(to, v); printf( %d %d n , v, to); } else if (used[to] == 1) { printf( %d %d n , v, to); } } used[v] = 2; } void solve(int n) { dfsAP(1); if (bridge) { puts( 0 ); return; } fill(used, used + n + 1, 0); dfsCC(1); } int main() { int n, m, u, v; scanf( %d %d , &n, &m); for (int i = 0; i < m; ++i) { scanf( %d %d , &u, &v); g[u].push_back(v); g[v].push_back(u); } solve(n); } |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_7_b2s_wr_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_wr_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_awready ,
input wire s_awvalid ,
output wire m_awvalid ,
input wire m_awready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
output wire b_push ,
input wire b_full ,
output wire a_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE_WAIT = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] next_state;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
end else begin
state <= next_state;
end
end
// Next state transitions.
always @( * )
begin
next_state = state;
case (state)
SM_IDLE:
if (s_awvalid) begin
next_state = SM_CMD_EN;
end else
next_state = state;
SM_CMD_EN:
if (m_awready & next_pending)
next_state = SM_CMD_ACCEPTED;
else if (m_awready & ~next_pending & b_full)
next_state = SM_DONE_WAIT;
else if (m_awready & ~next_pending & ~b_full)
next_state = SM_IDLE;
else
next_state = state;
SM_CMD_ACCEPTED:
next_state = SM_CMD_EN;
SM_DONE_WAIT:
if (!b_full)
next_state = SM_IDLE;
else
next_state = state;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_awvalid = (state == SM_CMD_EN);
assign next = ((state == SM_CMD_ACCEPTED)
| (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
assign a_push = (state == SM_IDLE);
assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
assign b_push = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ecc_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ecc_e.v,v 1.1 2006/04/10 15:42:06 wig Exp $
// $Date: 2006/04/10 15:42:06 $
// $Log: inst_ecc_e.v,v $
// Revision 1.1 2006/04/10 15:42:06 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ecc_e
//
// No user `defines in this module
module inst_ecc_e
//
// Generated module inst_ecc
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ecc_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const long long INFL = LLONG_MAX; int N, M, X[1000], a, b, c; int main() { ios_base::sync_with_stdio(0); cout.precision(15); cin >> N >> M; for (int(i) = 1; (i) <= (N); (i)++) cin >> X[i]; long double answer = 0; for (int(i) = 1; (i) <= (M); (i)++) { cin >> a >> b >> c; answer = max(answer, (long double)(X[a] + X[b]) / c); } cout << answer << endl; } |
//==============================================================================
// File: $URL: svn+ssh:///public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/Reverse.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2003-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//------------------------------------------------------------------------------
// Module: Reverse
// Desc: Parameterized bit reversal module: a fancy wire.
// Essentially this module is just a very complex set of wires, all
// it does it reverse the bits in a bus. A "group" is a group of
// "chunks" that should be reversed, "set" is the number of
// "chunks" per "group". This module will reverse the order of the
// "chunks" within each "group".
// Params: Width: This sets the input and output bus width of the module
// Chunk: This is the size of a block of wires which should
// be kept in order. The default is 1 meaning each wire
// should be treated separately.
// Set: The number of chunks in a set, the default is the
// bitwidth of the input bus, meaning that the whole input
// bus is treated as a set.
// Ex: (32,1,32) Will reverse the bit order of a 32bit bus.
// (32,1,8)Will reverse the MSb/LSb order of the bytes in a 32bit
// bus.
// (32,4,2)will reverse the MSNibble/LSNibble of each byte in a
// 32bit bus.
// Author: <a href="http://www.gdgib.com/">Greg Gibeling</a>
// Version: $Revision: 26904 $
//------------------------------------------------------------------------------
module Reverse(In, Out);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Width = 32,
Chunk = 1,
Set = Width;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Constants
//--------------------------------------------------------------------------
localparam Group = Chunk * Set;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// I/O
//--------------------------------------------------------------------------
input [Width-1:0] In;
output [Width-1:0] Out;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// A Complicated Wire
//--------------------------------------------------------------------------
genvar i;
generate for(i = 0; i < Width; i = i + 1) begin:REVERSE
assign Out[i] = In[((Set - 1 - ((i % Group) / Chunk)) * Chunk) + ((i % Group) % Chunk) + ((i / Group) * Group)];
end endgenerate
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const double eps = 1e-8; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const int seed = 131; int n, a[maxn], q; struct node { int l, r, sum, lazy; } Q[maxn << 2]; void build(int rt, int l, int r) { Q[rt].l = l, Q[rt].r = r; if (l == r) { Q[rt].sum = a[l]; return; } int mid = (l + r) / 2; build((rt << 1), l, mid); build(((rt << 1) | 1), mid + 1, r); } inline void pushdown(int rt) { if (Q[(rt << 1)].l == Q[(rt << 1)].r) Q[(rt << 1)].sum = max(Q[(rt << 1)].sum, Q[rt].lazy); else Q[(rt << 1)].lazy = max(Q[(rt << 1)].lazy, Q[rt].lazy); if (Q[((rt << 1) | 1)].l == Q[((rt << 1) | 1)].r) Q[((rt << 1) | 1)].sum = max(Q[((rt << 1) | 1)].sum, Q[rt].lazy); else Q[((rt << 1) | 1)].lazy = max(Q[((rt << 1) | 1)].lazy, Q[rt].lazy); Q[rt].lazy = 0; } void update(int rt, int p, int x) { if (Q[rt].l == Q[rt].r) { Q[rt].sum = x; return; } pushdown(rt); int mid = (Q[rt].l + Q[rt].r) / 2; if (p <= mid) update((rt << 1), p, x); else update(((rt << 1) | 1), p, x); } void show(int rt) { cout << Q[rt].l << << Q[rt].r << n ; } void query(int rt) { if (Q[rt].l == Q[rt].r) { cout << Q[rt].sum; if (Q[rt].l != n) cout << ; else cout << n ; return; } pushdown(rt); query((rt << 1)); query(((rt << 1) | 1)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); build(1, 1, n); scanf( %d , &q); int op, x, y; for (int i = 1; i <= q; i++) { scanf( %d , &op); if (op == 1) { scanf( %d %d , &x, &y); update(1, x, y); } else { scanf( %d , &x); if (n == 1) Q[1].sum = max(Q[1].sum, x); else if (n > 1 && Q[1].lazy < x) Q[1].lazy = x; } } query(1); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_16_V
`define SKY130_FD_SC_HDLL__INV_16_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_16_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& stream, const pair<T, T>& p) { return stream << ( << p.first << , << p.second << ) ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int T; cin >> T; while (T--) { int i, j, n; cin >> n; long long a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } long long mx = a[0], mxdiff = a[0] - a[1]; for (i = 1; i < n; i++) { if (mx - a[i] > mxdiff) mxdiff = mx - a[i]; mx = max(mx, a[i]); } if (mxdiff > 0) cout << (long long)(log2f(mxdiff)) + 1 << n ; else cout << 0 << n ; } return 0; } |
#include <bits/stdc++.h> int main(int argc, char const *argv[]) { int n, a, b; while (scanf( %d%d%d , &n, &a, &b) != EOF) printf( %d n , (n - a) < (b + 1) ? (n - a) : (b + 1)); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ccx_arb_srcq.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Module Name: arb_srcq.v
// Description: module for queuing logic from source, maintained
// in arbiter.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
module ccx_arb_srcq(/*AUTOARG*/
// Outputs
qfull, qsel0, qsel1, shift_x, ctl_qsel0_a, ctl_qsel1_a_l,
ctl_shift_a, q0_hold_a, atom_a,
// Inputs
req_q, atom_q, grant_a, rclk, reset_d1
);
output qfull;
output qsel0;
output qsel1;
output shift_x;
output ctl_qsel0_a,ctl_qsel1_a_l;
output ctl_shift_a;
output q0_hold_a;
output atom_a;
input req_q;
input atom_q;
input grant_a;
input rclk;
input reset_d1;
wire [1:0] qcount_decr, qcount_decr_d1, qcount_decr_r_d1;
wire [1:0] qcount_incr;
wire qsel0,qsel1_l;
wire shift_a, shift_x, q0_hold_a_l;
wire shift_hi, shift_hi_d1;
wire qfull;
wire incr_a;
wire decr;
wire atom_rqqual_x, atom_rqqual_a ;
wire req_atomqual_a;
wire req_a, atom_a, qfull_a;
//req_a generation
//The term on the rhs of '|' handles the optimisation for
// the Imiss following the load case, where the 2nd Imiss packet
// is in the output queue.
// assign atom_rqqual_q = atom_q & req_q | atom_rqqual_a & qfull;
dff_s #(1) dff_ccx_com_atom(
.din (atom_q),
.q (atom_a),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_req(
.din (req_q),
.q (req_a),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_qf(
.din (qfull),
.q (qfull_a),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
assign atom_rqqual_a = atom_a & req_a | atom_rqqual_x & qfull_a & ~reset_d1;
dff_s #(1) dff_ccx_com_atomq(
.din (atom_rqqual_a),
.q (atom_rqqual_x),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
assign req_atomqual_a = (atom_rqqual_x | req_a) & (~qfull_a & ~reset_d1);
assign incr_a = req_atomqual_a ;
//Qfull and Shift_hi generation
assign qfull = qcount_incr[1];
assign shift_hi = ~(qcount_decr[1] | qcount_decr[0]);
dff_s #(1) dff_ccx_com_shift_hi(
.din (shift_hi),
.q (shift_hi_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//Decrement Muxes
assign decr = grant_a & ~reset_d1;
mux2ds #(1) mx2ds_ccx_com_decr0(
.dout (qcount_decr[0]),
.in0 (qcount_incr[0]),
.in1 (qcount_incr[1]),
.sel0 (~decr),
.sel1 (decr));
mux2ds #(1) mx2ds_ccx_com_decr1(
.dout (qcount_decr[1]),
.in0 (qcount_incr[1]),
.in1 (1'b0),
.sel0 (~decr),
.sel1 (decr));
//Queue state flops
dff_s #(1) dff_ccx_com_decr0(
.din (qcount_decr[0]),
.q (qcount_decr_d1[0]),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
assign qcount_decr_r_d1[0] = qcount_decr_d1[0] & ~reset_d1;
dff_s #(1) dff_ccx_com_decr1(
.din (qcount_decr[1]),
.q (qcount_decr_d1[1]),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
assign qcount_decr_r_d1[1] = qcount_decr_d1[1] & ~reset_d1;
//Increment Muxes
mux2ds #(1) mx2ds_ccx_com_incr0(
.dout (qcount_incr[0]),
.in0 (qcount_decr_r_d1[0]),
.in1 (shift_hi_d1),
.sel0 (~incr_a),
.sel1 (incr_a));
mux2ds #(1) mx2ds_ccx_com_incr1(
.dout (qcount_incr[1]),
.in0 (qcount_decr_r_d1[1]),
.in1 (qcount_decr_r_d1[0]),
.sel0 (~incr_a),
.sel1 (incr_a));
//Generate Mux selects for arb dps
// assign qsel1_l = ~(qcount_incr[1] & incr_a);
assign qsel1 = (qcount_incr[1] & incr_a);
assign qsel0 = qcount_incr[0] & incr_a;
assign shift_a = qcount_incr[1] & grant_a;
dff_s #(1) dff_ccx_com_shiftx(
.din (shift_a),
.q (shift_x),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
// assign q0_hold_a_l = ~qsel0 & ~shift_x;
assign q0_hold_a = ~(~qsel0 & ~shift_x);
//Generate Mux selects for atomq ctl
assign ctl_qsel1_a_l = ~(qcount_decr_r_d1[0] & incr_a & ~grant_a);
assign ctl_qsel0_a = (qcount_incr[0] & incr_a) |
(qcount_decr_r_d1[0] & incr_a & grant_a);
assign ctl_shift_a = qcount_decr_r_d1[1] & grant_a;
// q1write - if cnt_decr=2'b01 in previous cycle and new req=1 in current cycle and grant=0
// q0write - if cnt_decr=2'b01 in previous cycle and new req=1 in current cycle and grant=1 OR
// if cnt_incr=2'b01 and new_req=1
// shift - if cnt_decr=2'b10 in previous cycle and grant=1
// qcnt is same as qcount_decr_r_d1
//
//---------------------------------------------------------
// 0 1 2 3 4
//---------------------------------------------------------
// req_a=1(R1) 1(R2)
// atm_a=0 0/1
//
// grant=0 1(R1) 1(R2) 0 0
//
// dp: qsel0=1 qsel1=1* shift=1
// q0=(R1) q0=(R1) q0=(R2)
// q1=(R2)
//
//ctl: qsel0=1 qsel0=1*
// q0=(R1) q0=(R2)
//
// qfull_a=0 0 1 0 0
//
// qcnt=0 1 1 1 0
//---------------------------------------------------------
//---------------------------------------------------------
// 0 1 2 3 4
//---------------------------------------------------------
// req_a=1(R1) 1(R2)
// atm_a=0 0/1
//
// grant=0 0 1(R1) 1(R2) 0
//
// dp: qsel0=1 qsel1=1 shift=1
// q0=(R1) q0=(R1) q0=(R1) q0=(R2)
// q1=(R2) q1=(R2)
//
//ctl: qsel0=1 qsel1=1 shift=1*
// q0=(R1) q0=(R1) q0=(R2)
// q1=(R2)
//
// qfull_a=0 0 1 1 0 <- in cycle 4, new req can be written into dp, and ctl
//
// qcnt=0 1 2 1 0
//---------------------------------------------------------
// for atomic requests 2 writes are done to ctl. The value of atomic on the sparc bus
// is "garbage" for 2nd write. This data is not used by arbiter. 1st grant for an
// atomic is remembered and request(qual_req) is not set for the 2nd grant.
// The 2nd write data will overwritten by the next new request or by shift.
endmodule
// Lopal Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { char c[51]; int n; scanf( %s , c); scanf( %d , &n); for (int i = 0; i < strlen(c); i++) { if (c[i] < a ) c[i] += a - A ; if (c[i] < 97 + n) c[i] += A - a ; } printf( %s , c); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx ) using namespace std; const int MAXN = 1e3 + 3; int n; bool dp[MAXN][10]; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> s; n = (int)s.length(); string kek = heidi ; memset(dp, 0, sizeof(dp)); for (auto i = 0; i != n; i++) { for (auto j = 0; j != 5; j++) { if (s[i] != kek[j]) continue; if (j > 0) { bool good = false; for (auto k = 0; k != i; k++) if (dp[k][j - 1]) { good = true; break; } if (!good) continue; } dp[i][j] = true; } } for (auto i = 0; i != n; i++) if (dp[i][4]) { cout << YES ; return 0; } cout << NO ; return 0; } |
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.