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//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; struct Node { int pos, id; Node(int p = 0, int i = 0) : pos(p), id(i) {} bool operator<(const Node& rhs) const { return pos < rhs.pos; } } a[MAXN], b[MAXN]; int m, n; long long c[3 * MAXN]; int ans[MAXN]; void add(int x, int y, int k) { c[x + n] += k, c[y + n] -= k; } int main() { scanf( %d%d , &m, &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i].pos); a[i].pos--, a[i].id = i + 1; } for (int i = 0; i < n; i++) { scanf( %d , &b[i].pos); b[i].pos--, b[i].id = i + 1; } sort(a, a + n); sort(b, b + n); for (int i = 0; i < n; i++) { int j = lower_bound(b, b + n, a[i]) - b - i; int p = a[i].pos + (m + 1) / 2; if (p < m) { int k = lower_bound(b, b + n, Node(p)) - b - i; add(j, k, -a[i].pos); add(k, n - i, a[i].pos + m); add(n - i, j + n, a[i].pos); } else { int k = lower_bound(b, b + n, Node(p - m)) - b - i; add(j, n - i, -a[i].pos); add(n - i, k + n, m - a[i].pos); add(k + n, j + n, a[i].pos); } } for (int i = 0; i < n; i++) { int j = i - (upper_bound(a, a + n, b[i]) - a - 1); int p = b[i].pos - (m + 1) / 2; if (p >= 0) { int k = i - (upper_bound(a, a + n, Node(p)) - a - 1); add(j, k, b[i].pos); add(k, j + n, -b[i].pos); } else { int k = i - (upper_bound(a, a + n, Node(p + m)) - a - 1); add(j, k + n, b[i].pos); add(k + n, j + n, -b[i].pos); } } for (int i = 1; i < 3 * n; i++) c[i] += c[i - 1]; for (int i = 0; i < n; i++) c[i] += c[i + n] + c[i + 2 * n]; int p = min_element(c, c + n) - c; printf( %lld n , c[p]); for (int i = 0; i < n; i++) ans[a[i].id] = b[(i + p) % n].id; for (int i = 1; i <= n; i++) printf( %d , ans[i]); putchar( n ); return 0; } |
module testbench;
localparam wide_width_lp = 16;
localparam narrow_width_lp = 4;
localparam els_lp = wide_width_lp / narrow_width_lp;
logic clk;
bsg_nonsynth_clock_gen
#(.cycle_time_p(1000))
clock_gen
(.o(clk));
logic reset;
bsg_nonsynth_reset_gen
#(.num_clocks_p(1)
,.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
)
reset_gen
(.clk_i(clk)
,.async_reset_o(reset)
);
logic [narrow_width_lp-1:0] in_data_li;
logic in_v_li, in_ready_lo;
logic [wide_width_lp-1:0] in_data_lo;
logic in_v_lo, in_yumi_li;
logic [wide_width_lp-1:0] out_data_li;
logic out_v_li, out_ready_lo;
logic [narrow_width_lp-1:0] out_data_lo;
logic out_v_lo, out_ready_li;
bsg_serial_in_parallel_out_passthrough
#(.width_p(narrow_width_lp), .els_p(els_lp))
DUT
(.clk_i(clk)
,.reset_i(reset)
,.data_i(in_data_li/els_lp)
,.v_i(in_v_li)
,.ready_and_o(in_ready_lo)
,.data_o(in_data_lo)
,.v_o(in_v_lo)
,.ready_and_i(in_yumi_li)
);
assign out_data_li = in_data_lo;
assign out_v_li = in_v_lo;
assign in_yumi_li = out_ready_lo & out_v_li;
bsg_parallel_in_serial_out
#(.width_p(narrow_width_lp), .els_p(els_lp))
reverse
(.clk_i(clk)
,.reset_i(reset)
,.data_i(out_data_li)
,.valid_i(out_v_li)
,.ready_o(out_ready_lo)
,.data_o(out_data_lo)
,.valid_o(out_v_lo)
,.yumi_i(out_ready_li & out_v_lo)
);
// Input block
initial
begin
in_data_li = '0;
in_v_li = '0;
@(posedge clk);
@(negedge reset);
@(posedge clk);
for (integer i = 0; i < 400; i++)
begin
in_v_li = 1'b1;
@(posedge clk);
in_data_li = in_data_li + (in_ready_lo & in_v_li);
if (in_ready_lo & in_v_li)
$display("Sending %x", in_data_li/els_lp);
end
end
// Checking block
logic [narrow_width_lp-1:0] match_data_li;
initial
begin
out_ready_li = '0;
match_data_li = '0;
@(posedge clk);
@(negedge reset);
@(posedge clk);
for (integer i = 0; i < 400; i++)
begin
out_ready_li = 1'b1;
match_data_li = match_data_li + (out_ready_li & out_v_lo);
@(negedge clk);
assert(~(out_ready_li & out_v_lo) || (match_data_li/els_lp == out_data_lo));
if (out_ready_li & out_v_lo)
$display("Receiving %x", out_data_lo);
end
$finish();
end
endmodule
|
// $Id: c_wf_alloc_rep.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// wavefront allocator variant which replicates the entire allocation logic for
// the different priorities and selects the result from the appropriate one
//==============================================================================
module c_wf_alloc_rep
(clk, reset, active, req_pr, gnt_pr, gnt, update);
`include "c_functions.v"
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// number of priority levels
parameter num_priorities = 1;
// width of priority selector
localparam port_idx_width = clogb(num_ports);
// when selecting next priority diagonal, skip diagonals without requests
parameter skip_empty_diags = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// request matrix
input [0:num_priorities*num_ports*num_ports-1] req_pr;
// grant matrix
output [0:num_priorities*num_ports*num_ports-1] gnt_pr;
wire [0:num_priorities*num_ports*num_ports-1] gnt_pr;
// combined grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
// update port priorities
input update;
wire [0:port_idx_width-1] prio_next;
wire [0:port_idx_width-1] prio_s, prio_q;
assign prio_s = update ? prio_next : prio_q;
c_dff
#(.width(port_idx_width),
.reset_type(reset_type))
prioq
(.clk(clk),
.reset(reset),
.active(active),
.d(prio_s),
.q(prio_q));
generate
wire [0:num_priorities*num_ports-1] first_diag_pr;
if(skip_empty_diags)
begin
wire [0:num_ports-1] first_diag;
if(num_priorities == 1)
assign first_diag = first_diag_pr;
else if(num_priorities > 1)
begin
wire [0:num_priorities-1] any_req_pr;
c_reduce_bits
#(.num_ports(num_priorities),
.width(num_ports),
.op(`BINARY_OP_OR))
any_req_pr_rb
(.data_in(first_diag_pr),
.data_out(any_req_pr));
wire [0:num_priorities-1] any_req_mod_pr;
assign any_req_mod_pr = {any_req_pr[0:num_priorities-2], 1'b1};
wire [0:num_priorities-1] sel_pr;
c_lod
#(.width(num_priorities))
sel_pr_lod
(.data_in(any_req_mod_pr),
.data_out(sel_pr));
c_select_1ofn
#(.num_ports(num_priorities),
.width(num_ports))
prio_next_sel
(.select(sel_pr),
.data_in(first_diag_pr),
.data_out(first_diag));
end
c_encode
#(.num_ports(num_ports),
.offset(1))
prio_next_enc
(.data_in(first_diag),
.data_out(prio_next));
end
else
begin
c_incr
#(.width(port_idx_width),
.min_value(0),
.max_value(num_ports-1))
prio_next_incr
(.data_in(prio_q),
.data_out(prio_next));
end
wire [0:num_priorities*num_ports*num_ports-1] gnt_intm_pr;
assign gnt = gnt_intm_pr[(num_priorities-1)*num_ports*num_ports:
num_priorities*num_ports*num_ports-1];
genvar pr;
for(pr = 0; pr < num_priorities; pr = pr + 1)
begin:prs
wire [0:num_ports*num_ports-1] req;
assign req
= req_pr[pr*num_ports*num_ports:(pr+1)*num_ports*num_ports-1];
if(skip_empty_diags)
begin
wire [0:num_ports-1] req_on_diag;
c_diag_op
#(.width(num_ports),
.op(`BINARY_OP_OR))
req_on_diag_dop
(.data_in(req),
.data_out(req_on_diag));
wire [0:num_ports-1] prio_port;
c_decode
#(.num_ports(num_ports))
prio_port_dec
(.data_in(prio_q),
.data_out(prio_port));
wire [0:num_ports-1] first_diag;
c_prefix_arbiter_base
#(.num_ports(num_ports))
first_diag_pa
(.prio_port(prio_port),
.req(req_on_diag),
.gnt(first_diag));
assign first_diag_pr[pr*num_ports:(pr+1)*num_ports-1]
= first_diag;
end
wire [0:num_ports*num_ports-1] gnt_intm_in;
if(pr == 0)
assign gnt_intm_in = {(num_ports*num_ports){1'b0}};
else if(pr > 0)
assign gnt_intm_in
= gnt_intm_pr[(pr-1)*num_ports*num_ports:
pr*num_ports*num_ports-1];
wire [0:num_ports-1] row_gnt;
c_reduce_bits
#(.num_ports(num_ports),
.width(num_ports),
.op(`BINARY_OP_OR))
row_gnt_rb
(.data_in(gnt_intm_in),
.data_out(row_gnt));
wire [0:num_ports-1] col_gnt;
c_binary_op
#(.num_ports(num_ports),
.width(num_ports),
.op(`BINARY_OP_OR))
col_gnt_bop
(.data_in(gnt_intm_in),
.data_out(col_gnt));
wire [0:num_ports*num_ports-1] mask;
c_mat_mult
#(.dim1_width(num_ports),
.dim2_width(1),
.dim3_width(num_ports),
.prod_op(`BINARY_OP_NOR),
.sum_op(`BINARY_OP_OR))
mask_mmult
(.input_a(row_gnt),
.input_b(col_gnt),
.result(mask));
wire [0:num_ports*num_ports-1] req_masked;
assign req_masked = req & mask;
wire [0:num_ports*num_ports-1] gnt;
assign gnt_pr[pr*num_ports*num_ports:(pr+1)*num_ports*num_ports-1]
= gnt;
wire [0:num_ports*num_ports-1] gnt_intm_out;
assign gnt_intm_out = gnt_intm_in | gnt;
assign gnt_intm_pr[pr*num_ports*num_ports:
(pr+1)*num_ports*num_ports-1]
= gnt_intm_out;
wire [0:num_ports*num_ports*num_ports-1] gnt_by_prio;
assign gnt
= gnt_by_prio[prio_q*num_ports*num_ports +: num_ports*num_ports];
genvar prio;
for(prio = 0; prio < num_ports; prio = prio + 1)
begin:prios
wire [0:num_ports*num_ports-1] req_int;
wire [0:num_ports*num_ports-1] gnt_int;
wire [0:num_ports*num_ports-1] y;
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
wire [0:num_ports-1] x_in, y_in;
wire [0:num_ports] x_out, y_out;
wire [0:num_ports-1] req_in;
wire [0:num_ports-1] gnt_out;
assign x_in = x_out[0:num_ports-1];
assign y_in
= y[((row+num_ports)%num_ports)*num_ports:
((row+num_ports)%num_ports+1)*num_ports-1];
assign req_in = req_int[row*num_ports:
(row+1)*num_ports-1];
assign x_out = {1'b1, (~y_in | ~req_in) & x_in};
assign y_out = {1'b1, (~x_in | ~req_in) & y_in};
assign gnt_out = req_in & x_in & y_in;
assign y[((row+num_ports+1)%num_ports)*num_ports:
((row+num_ports+1)%num_ports+1)*num_ports-1]
= y_out[0:num_ports-1];
assign gnt_int[row*num_ports:(row+1)*num_ports-1]
= gnt_out;
genvar col;
for(col = 0; col < num_ports; col = col + 1)
begin:cols
assign req_int[row*num_ports+col]
= req_masked[((prio+row)%num_ports)*num_ports +
(num_ports-row+col)%num_ports];
assign gnt_by_prio[((prio+row)%num_ports)*
num_ports +
(num_ports-row+col)%num_ports +
prio*num_ports*num_ports]
= gnt_int[row*num_ports+col];
end
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, ans, i, j, k; cin >> t; for (i = 0; i < t; i++) { cin >> n; int x[2 * n]; for (j = 0; j < 2 * n; j++) cin >> x[j]; sort(x, x + 2 * n); ans = x[n] - x[n - 1]; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2005, MOD = 1e9 + 7; int d, n, a[N], dp[N], rt; vector<int> g[N]; void dfs(int v, int pr = -1) { dp[v] = 1; for (int to : g[v]) { if (to == pr) { continue; } if (a[to] < a[rt] || a[to] > a[rt] + d) { continue; } if (a[to] == a[rt] && to > rt) { continue; } dfs(to, v); dp[v] = (1ll * dp[v] * (dp[to] + 1)) % MOD; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> d >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } int ans = 0; for (int i = 1; i <= n; i++) { rt = i; dfs(rt, -1); ans = (ans + dp[i]) % MOD; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 4e18; const long long MAX = 2e5 + 5; const long long MOD = 1e9 + 7; int n, m; void exgcd(int a, int b, long long &c, long long &d) { if (a == 0) { c = 0; d = 1; return; } exgcd(b % a, a, d, c); c -= b / a * d; } long long gcd(int a, int b) { if (a == 0) return b; return gcd(b % a, a); } int g[MAX]; bool arv[MAX], avb[MAX]; int sz[MAX]; pair<int, int> ma[MAX]; vector<int> v; vector<int> son[MAX]; void build() { for (int i = 0; i < m; i++) { g[i] = gcd(i, m); sz[g[i]]++; son[g[i]].push_back(i); } g[m] = m; int x = m; for (int i = 2; i <= sqrt(x); i++) { if (x % i == 0) v.push_back(i); while (x % i == 0) x /= i; } if (x > 1) v.push_back(x); } void read() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; build(); for (int i = 0; i < n; i++) { int x; cin >> x; avb[x] = 1; if (!x) avb[m] = 1; sz[gcd(x, m)]--; } } void dfs(long long x) { if (arv[x]) return; for (int i : v) { if (i * x > m) break; if (g[i * x] == i * x) { dfs(i * x); ma[x] = max(ma[x], {ma[i * x].first, i * x}); } } ma[x].first += sz[x]; ; arv[x] = 1; } vector<int> ans; void output() { ios_base::sync_with_stdio(0); cin.tie(0); cout << ((long long)(ans).size()) << n ; for (int i : ans) cout << i << ; cout << n ; ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); read(); for (int i = 1; i <= m; i++) if (g[i] == i && !arv[i]) dfs(i); long long now = 1, pre = 1; long long cod; while (now <= m) { ; for (long long i : son[now]) { if (!avb[i]) { long long r, y; exgcd(pre, m, r, y); if (r < 0) r += m; ans.push_back(i / gcd(pre, m) * r % m); pre = i; } } if (ma[now].second) now = ma[now].second; else break; } output(); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_181x128a.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1.191 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_181x128a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrusedw);
input aclr;
input [180:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [180:0] q;
output rdempty;
output wrempty;
output [6:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [180:0] sub_wire1;
wire sub_wire2;
wire [6:0] sub_wire3;
wire wrempty = sub_wire0;
wire [180:0] q = sub_wire1[180:0];
wire rdempty = sub_wire2;
wire [6:0] wrusedw = sub_wire3[6:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrempty (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.rdusedw (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 181,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "181"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "181"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "181"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 181 0 INPUT NODEFVAL "data[180..0]"
// Retrieval info: USED_PORT: q 0 0 181 0 OUTPUT NODEFVAL "q[180..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL "wrusedw[6..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 181 0 data 0 0 181 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 181 0 @q 0 0 181 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtp (
RESET_B,
CLK ,
D ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_2_V
`define SKY130_FD_SC_LS__A21O_2_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_2_V
|
module udp_reg_path_decode (
input reg_req,
input reg_rd_wr_L,
input [31:0] reg_addr,
input [31:0] reg_wr_data,
output reg reg_ack,
output reg [31:0] reg_rd_data,
// interface to core registers
output reg core_reg_req,
output reg core_reg_rd_wr_L,
output reg [31:0] core_reg_addr,
output reg [31:0] core_reg_wr_data,
input core_reg_ack,
input [31:0] core_reg_rd_data,
// interface to user data path
output reg udp_reg_req,
output reg udp_reg_rd_wr_L,
output reg [31:0] udp_reg_addr,
output reg [31:0] udp_reg_wr_data,
input udp_reg_ack,
input [31:0] udp_reg_rd_data,
input clk,
input reset
);
always @(posedge clk) begin
if(reset) begin
reg_ack <= 1'b0;
reg_rd_data <= 32'h0;
core_reg_req <= 1'b0;
core_reg_rd_wr_L <= 1'b1;
core_reg_addr <= 31'h0;
core_reg_wr_data <= 31'h0;
udp_reg_req <= 1'b0;
udp_reg_rd_wr_L <= 1'b1;
udp_reg_addr <= 31'h0;
udp_reg_wr_data <= 31'h0;
end
else begin
casez (reg_addr[26:24])
3'b000: begin
reg_ack <= core_reg_ack;
reg_rd_data <= core_reg_rd_data;
core_reg_req <= reg_req;
core_reg_rd_wr_L <= reg_rd_wr_L;
core_reg_addr <= reg_addr[31:2];
core_reg_wr_data <= reg_wr_data;
end
3'b01?: begin
reg_ack <= udp_reg_ack;
reg_rd_data <= udp_reg_rd_data;
udp_reg_req <= reg_req;
udp_reg_rd_wr_L <= reg_rd_wr_L;
udp_reg_addr <= reg_addr[31:2];
udp_reg_wr_data <= reg_wr_data;
end
default: begin
reg_ack <= reg_req;
reg_rd_data <= 32'h DEAD_BEEF;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> long long gi() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) f ^= ch == - , ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f ? x : -x; } std::mt19937 rnd(time(NULL)); template <class T> void cxk(T& a, T b) { a = a > b ? a : b; } template <class T> void cnk(T& a, T b) { a = a < b ? a : b; } int A[2][3], B[8], C[3]; int main() { int qwq = gi(); while (qwq--) { for (int i = 0; i < 2; ++i) for (int j = 2; ~j; --j) A[i][j] = gi(); for (int j = 7; j; --j) B[j] = gi(); int s = 0; for (int i = 1; i <= 7; ++i) if (i != (i & -i)) s += B[i]; for (int i = 0; i < 3; ++i) { int sum = A[0][i] + A[1][i]; for (int j = 1; j <= 7; ++j) if (j >> i & 1) sum -= B[j]; if (sum < 0) { puts( -1 ); goto ed; } } for (int i = 0; i < 3; ++i) C[i] = B[7 ^ (1 << i)]; for (int a = 0, b = s; a <= s; ++a, --b) { bool flg = 0; for (int i = 0; i < 3; ++i) if (std::max(0, a - A[0][i]) + std::max(0, b - A[1][i]) > C[i]) flg = 1; if (a < std::max(0, a - A[0][0]) + std::max(0, a - A[0][1]) + std::max(0, a - A[0][2])) flg = 1; if (b < std::max(0, b - A[1][0]) + std::max(0, b - A[1][1]) + std::max(0, b - A[1][2])) flg = 1; if (flg) continue; int D[8] = {0}; D[7] = a; for (int i = 0; i < 3; ++i) { int p = std::max(0, a - A[0][i]); D[7 ^ (1 << i)] = p; D[7] -= p; } for (int i = 0; i < 3; ++i) { int p = std::max( 0, std::min({D[7] - B[7], B[7 ^ (1 << i)] - D[7 ^ (1 << i)], C[i] - D[7 ^ (1 << i)] - std::max(0, b - A[1][i])})); D[7 ^ (1 << i)] += p; D[7] -= p; } for (int i = 0; i < 3; ++i) { int s = A[0][i]; for (int j = 1; j <= 7; ++j) if (j >> i & 1) s -= D[j]; D[1 << i] = std::min(s, B[1 << i]); } for (int i = 7; i; --i) printf( %d , D[i]); puts( ); for (int i = 1; i <= 7; ++i) assert(D[i] <= B[i]); for (int i = 0; i < 3; ++i) { int s1 = 0, s2 = 0; for (int j = 1; j <= 7; ++j) if (j >> i & 1) s1 += D[j], s2 += B[j] - D[j]; assert(s1 <= A[0][i] && s2 <= A[1][i]); } goto ed; } puts( -1 ); ed:; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Ryan
//
// Create Date: 06/07/2017
// Module Name: ClkDiv_20Hz
// Project Name: Joystick_Controller
// Target Devices: ICEStick
// Tool versions: iCEcube2
// Description: Converts input 12 MHz clock signal to a 20Hz "update system" clock signal
//////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module ClkDiv_20Hz(
CLK, // 12MHz onbaord clock
RST, // Reset
CLKOUT, // New clock output
CLKOUTn
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK;
input RST;
output CLKOUT;
output CLKOUTn;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
// Output register
reg CLKOUT = 1'b1;
// Value to toggle output clock at
parameter cntEndVal = 19'h493E0;
// Current count
reg [18:0] clkCount = 19'h00000;
// ===========================================================================
// Implementation
// ===========================================================================
assign CLKOUTn = ~CLKOUT;
//-------------------------------------------------
// 20Hz Clock Divider Generates timing to initiate Send/Receive
//-------------------------------------------------
always @(posedge CLK) begin
// Reset clock
if(RST == 1'b1) begin
CLKOUT <= 1'b0;
clkCount <= 0;
end
// Count/toggle normally
else begin
if(clkCount == cntEndVal) begin
CLKOUT <= ~CLKOUT;
clkCount <= 0;
end
else begin
clkCount <= clkCount + 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans, n, a[10005], cnt, f, i, j, vis[10005]; int main() { scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a[i]); } ans = 0; f = 0; cnt = 0; memset(vis, 0, sizeof vis); for (i = 0; i < n; i++) { if (!f) { for (j = 0; j < n; j++) { if (cnt >= a[j] && !vis[j]) { vis[j] = 1; cnt++; } } } else { for (j = n - 1; j >= 0; j--) { if (cnt >= a[j] && !vis[j]) { vis[j] = 1; cnt++; } } } if (cnt == n) { break; } else { ans++; } f = 1 - f; } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e8; int n, m; char s[22][22]; int x[22][22], dp[1 << 20], state[30], sum[30], maxN[30]; vector<int> sta[22]; vector<int> cost[22]; int bit[1 << 20]; void initialIt() { for (int i = 0; i < 20; i++) { bit[1 << i] = i; } for (int i = 0; i < m; i++) { memset(state, 0, sizeof(state)); memset(sum, 0, sizeof(sum)); memset(maxN, 0, sizeof(maxN)); for (int j = 0; j < n; j++) { int ch = (int)s[j][i] - a ; state[ch] |= 1 << j; sum[ch] += x[j][i]; maxN[ch] = max(maxN[ch], x[j][i]); } for (int j = 0; j < 26; j++) { for (int k = 0; k < n; k++) if ((state[j] >> k) & 1) { sta[k].push_back(state[j]); cost[k].push_back(sum[j] - maxN[j]); } } } for (int i = 0; i < n; i++) { int minCost = INF; for (int j = 0; j < m; j++) { minCost = min(minCost, x[i][j]); } sta[i].push_back(1 << i); cost[i].push_back(minCost); } } int lowBit(int x) { return x & (-x); } void calcIt() { for (int i = 0; i < (1 << n); i++) { dp[i] = INF; } dp[0] = 0; for (int i = 0; i < (1 << n); i++) { int curI = bit[lowBit(i)], curS = i; for (int j = 0; j < (int)cost[curI].size(); j++) { int C = cost[curI][j], S = sta[curI][j]; int preS = curS - (curS & S); if (dp[preS] + C < dp[curS]) { dp[curS] = dp[preS] + C; } } } int final = (1 << n) - 1; printf( %d n , dp[final]); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %s , s[i]); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %d , &x[i][j]); } } initialIt(); calcIt(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:05:40 09/06/2015
// Design Name:
// Module Name: Deco_Round_Mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Deco_Round_Mult(
input wire [1:0] round_mode,
input wire or_info, //23 less significant bits from the product of significands
input wire xor_info, //Brings information about the sign of the operation
output reg ctrl //control signal mux --- control of the rounded significand
);
always @*
case ({xor_info,or_info,round_mode})
// Round to infinity - (Round down)
//1'b0: Let pass the significand without rounding
//1'b1: Let pass the rounded significand
//Round towards - infinity
//0: positive number ; 01: Round towards - inifnity ; XX rounding bits
//Positive Number
//xor, or, round
4'b0101: ctrl <= 1'b0;
//Negative Number
4'b1101: ctrl <= 1'b1;
//Round towards + infinity
//Positive Number
4'b0110: ctrl <= 1'b1;
//Negative Number
4'b1110: ctrl <= 1'b0;
default: ctrl <= 1'b0; //Truncation
endcase
endmodule |
#include <bits/stdc++.h> using namespace std; const int MAXN = 5e5 + 5; template <typename T> void chkmax(T& x, T y) { if (y > x) x = y; } template <typename T> void chkmin(T& x, T y) { if (y < x) x = y; } int N, c[MAXN]; long long ans; int main() { scanf( %d , &N); for (int i = 1; i <= N; ++i) scanf( %d , &c[i]); for (int i = 1; i <= N; i += 2) { long long minv = 0, sum = 0; for (int j = i + 1; j <= N; ++j) { long long l = -sum - c[i], r = -sum - max(1ll, -minv); if (j % 2 == 1) chkmax(l, 1ll), chkmin(r, (long long)c[j]); else chkmax(l, (long long)-c[j]), chkmin(r, -1ll); ans += max(0ll, r - l + 1); sum += j % 2 == 1 ? c[j] : -c[j]; chkmin(minv, sum); } } printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> int main() { int a, b; scanf( %d%d , &a, &b); int c = 0; while (b) { c *= 10; c += b % 10; b /= 10; } printf( %d n , c + a); } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_icmp(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall, i_settings);
parameter DATA_WIDTH = 32;
parameter MODE_WIDTH = 4;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output reg o_dataout;
output o_dataout_valid;
input i_stall;
input [MODE_WIDTH-1:0] i_settings;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire signed [DATA_WIDTH-1:0] sdataa;
wire signed [DATA_WIDTH-1:0] sdatab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_stall);
assign sdataa = dataa;
assign sdatab = datab;
always @(*)
begin
case (i_settings)
5'h0: // EQ
begin
o_dataout <= (dataa == datab) ? 1'b1 : 1'b0;
end
5'h1: // NE
begin
o_dataout <= (dataa != datab) ? 1'b1 : 1'b0;
end
5'h2: // UGT
begin
o_dataout <= (dataa > datab) ? 1'b1 : 1'b0;
end
5'h3: // UGE
begin
o_dataout <= (dataa >= datab) ? 1'b1 : 1'b0;
end
5'h4: // ULT
begin
o_dataout <= (dataa < datab) ? 1'b1 : 1'b0;
end
5'h5: // ULE
begin
o_dataout <= (dataa <= datab) ? 1'b1 : 1'b0;
end
5'h6: // SGT
begin
o_dataout <= (sdataa > sdatab) ? 1'b1 : 1'b0;
end
5'h7: // SGE
begin
o_dataout <= (sdataa >= sdatab) ? 1'b1 : 1'b0;
end
5'h8: // SLT
begin
o_dataout <= (sdataa < sdatab) ? 1'b1 : 1'b0;
end
5'h9: // SLE
begin
o_dataout <= (sdataa <= sdatab) ? 1'b1 : 1'b0;
end
default:
begin
o_dataout <= 1'b0;
end
endcase
end
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int c, m, x; cin >> c >> m >> x; long long int y = c + m + x; y = y / 3; long long int ans = 0; if (c >= 1 && m >= 1) { long long int v = min(c, m); ans = min(v, y); } cout << ans << endl; } } |
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register4(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [3:0] out;
input [3:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 4'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register3(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [2:0] out;
input [2:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 3'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register2(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [1:0] out;
input [1:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 2'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register1(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct kmp { vector<int> lps; string pattern; void compute_lps() { int lptr = 0, rptr = 1; lps[0] = 0; while (rptr < lps.size()) { while (lptr != 0 && pattern[lptr] != pattern[rptr]) lptr = lps[lptr - 1]; if (pattern[lptr] == pattern[rptr]) lptr++; lps[rptr] = lptr; rptr++; } } kmp(string& s) { pattern = s; lps.resize(s.size()); compute_lps(); } void search(string& s) { vector<int> hits; int lptr = 0, rptr = 0; while (rptr < s.size()) { while (lptr != 0 && pattern[lptr] != s[rptr]) lptr = lps[lptr - 1]; if (pattern[lptr] == s[rptr]) lptr++; rptr++; if (lptr == pattern.size()) { hits.push_back(rptr - pattern.size()); lptr = lps[lptr - 1]; } } } }; long long mod = 1e9 + 7; long long add(long long a, long long b) { return (a + b) % mod; } long long sub(long long a, long long b) { return ((a - b) % mod + mod) % mod; } long long mul(long long a, long long b) { return (a * b) % mod; } const int maxn = 205; long long dp[maxn][maxn][maxn][2], ans; int n; string s; int getmaxlen(kmp& KMP, char t, int mptr) { if (mptr == s.size()) mptr = KMP.lps[mptr - 1]; while (s[mptr] != t && mptr != 0) mptr = KMP.lps[mptr - 1]; if (s[mptr] == t) mptr++; return mptr; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> n >> s; dp[0][0][0][0] = 1; kmp KMP(s); for (int i = 0; i < (2 * n); i++) { for (int j = 0; j <= n; j++) { for (int k = 0; k < (2 * n) && k <= s.size(); k++) { for (int l = 0; l < 2; l++) { if (dp[i][j][k][l] == 0) continue; int mptr = getmaxlen(KMP, ( , k); int matched = l; if (mptr == s.size()) matched = 1; dp[i + 1][j + 1][mptr][matched] = add(dp[i + 1][j + 1][mptr][matched], dp[i][j][k][l]); if (j != 0) { mptr = getmaxlen(KMP, ) , k); matched = l; if (mptr == s.size()) matched = 1; dp[i + 1][j - 1][mptr][matched] = add(dp[i + 1][j - 1][mptr][matched], dp[i][j][k][l]); } } } } } for (int i = 0; i <= s.size(); i++) ans = add(ans, dp[2 * n][0][i][1]); cout << ans; return 0; } |
#include <bits/stdc++.h> int main() { int n, i, a[100001]; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) while (a[i] % 2 == 0) a[i] /= 2; for (i = 1; i <= n; i++) while (a[i] % 3 == 0) a[i] /= 3; for (i = 1; i <= n - 1; i++) if (a[i] != a[i + 1]) { printf( NO ); return 0; } printf( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; int mx[4] = {1, 0, -1, 0}; int my[4] = {0, 1, 0, -1}; void dfs(int x, int y, vector<vector<char> > &b, vector<vector<int> > &val, int &c, int &v) { v++; val[x][y] = c; for (int i = 0; i < 4; i++) { int xt = x + mx[i]; int yt = y + my[i]; if (xt >= 0 && xt < b.size() && yt >= 0 && yt < b[0].size() && b[xt][yt] == . && val[xt][yt] == 0) { dfs(xt, yt, b, val, c, v); } } } int main() { int n, m; while (cin >> n >> m) { vector<vector<char> > board(n, vector<char>(m, . )); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> board[i][j]; } vector<vector<int> > values(n, vector<int>(m, 0)); int color = 1; vector<int> colors(n * m, 0); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (board[i][j] == . && values[i][j] == 0) { int val = 0; dfs(i, j, board, values, color, val); colors[color] = val; color++; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (board[i][j] == . ) { cout << . ; continue; } else { int acu = 0; set<int> valA; for (int k = 0; k < 4; k++) { int xt = i + mx[k]; int yt = j + my[k]; if (xt >= 0 && xt < board.size() && yt >= 0 && yt < board[0].size() && !valA.count(values[xt][yt])) { acu += colors[values[xt][yt]]; valA.insert(values[xt][yt]); } } cout << (acu + 1) % 10; } } cout << endl; } } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t ();
sub a (.inst(1));
sub b (.inst(2));
initial begin
a.test1;
b.test1;
a.test2;
b.test2;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input integer inst);
import "DPI-C" context function int dpic_line();
import "DPI-C" context function int dpic_save(int value);
import "DPI-C" context function int dpic_restore();
import "DPI-C" context function int unsigned dpic_getcontext();
int result;
task test1;
// Check line numbering
`ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test
result = dpic_line(); if (!result) $stop;
`else
result = dpic_line(); if (result !== `__LINE__) $stop;
//
result = dpic_line(); if (result !== `__LINE__) $stop;
`endif
// Check save-restore
result = dpic_save(23+inst);
if (result==0) $stop;
endtask
task test2;
if (dpic_restore() != 23+inst) $stop;
endtask
int unsigned cntxt1;
int unsigned cntxt2;
initial begin
cntxt1 = dpic_getcontext();
begin : caller_context
// call from a different scope - should still get the context of the function declaration
cntxt2 = dpic_getcontext();
end
// svContext should be the context of the function declaration, not the context of the function call
if (cntxt1 != cntxt2) $stop;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFBBN_BEHAVIORAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 200514; vector<int> a3[N], a4[N], mn, mx; set<int> s; int p3[N], p4[N]; int n, m, M, a[N], ct[N], l1 = 1, l2 = 1; int j, p1, p2, k1, k2; int main() { scanf( %d%d , &n, &m); p3[n + 1] = p4[n + 1] = n + 1; for (int i = (1); i <= (n); i++) scanf( %d , &a[i]); for (int i = (n); i >= (1); i--) { j = i - 1; p3[i] = p4[i] = n + 1; while (j >= 1 && a[i] == a[j]) j--; while (mn.size() && a[i] < a[mn.back()]) { if (!(--ct[mn.back()])) s.insert(mn.back()); l1 = 0; mn.pop_back(); } while (mx.size() && a[i] > a[mx.back()]) { if (!(--ct[mx.back()])) s.insert(mx.back()); l2 = 0; mx.pop_back(); } p1 = lower_bound(mn.begin(), mn.end(), i, [&](int x, int y) { return a[x] < a[y]; }) - mn.begin() - 1; p2 = lower_bound(mx.begin(), mx.end(), i, [&](int x, int y) { return a[x] > a[y]; }) - mx.begin() - 1; p3[i] = i + 1 + max(l1, l2); a3[i] = {i, p3[i] - 1, p3[i]}; if (~p1 && ~p2) { auto it = s.lower_bound(max(mn[p1], mx[p2])); if (it != s.end()) { p4[i] = *it; k1 = upper_bound(mn.begin(), mn.end(), p4[i], greater<int>()) - mn.begin(); k2 = upper_bound(mx.begin(), mx.end(), p4[i], greater<int>()) - mx.begin(); a4[i] = {i, min(mn[k1], mx[k2]), max(mn[k1], mx[k2]), p4[i]}; } } if (p3[i] > p3[i + 1]) a3[i] = a3[i + 1], p3[i] = p3[i + 1]; if (p4[i] > p4[i + 1]) a4[i] = a4[i + 1], p4[i] = p4[i + 1]; for (int k = (j + 1); k <= (i); k++) { l1++, l2++; mn.push_back(k), mx.push_back(k); ct[k] = 2; p3[k] = p3[i], p4[k] = p4[i], a3[k] = a3[i], a4[k] = a4[i]; } i = j + 1; } int x, y; for (int i = (1); i <= (m); i++) { scanf( %d%d , &x, &y); if (p4[x] <= y) { puts( 4 ); for (int l : a4[x]) printf( %d , l); puts( ); } else if (p3[x] <= y) { puts( 3 ); for (int l : a3[x]) printf( %d , l); puts( ); } else puts( 0 ); } } |
// This is a component of pluto_step_spi, a stepper driver for linuxcnc over SPI.
// based on the main.v from Jeff Epler <>
// Copyright 2013 by Matsche <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//**********************************************************************
// Open-Drain buffer
module OC_Buff(in, out);
input in;
output out;
assign out = in ? 1'bz : 1'b0;
endmodule
module pluto_spi_stepper_opendrain(clk, SCK, MOSI, MISO, SSEL, nRESET, nPE, LED, nConfig, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
input SCK, SSEL, MOSI, nRESET;
output MISO, nConfig = 1'bZ, nPE;
output LED;
input [15:0] din;
assign nConfig = nRESET;
//assign nConfig = 1'b1;
assign nPE = 1'b1;
reg Spolarity;
reg[13:0] real_dout;
output [13:0] dout = 14'bZ;
OC_Buff ocout[13:0](real_dout, dout);
wire[3:0] real_step;
output [3:0] step = 4'bZ;
OC_Buff ocstep[3:0](real_step ^ {4{Spolarity}}, step);
wire[3:0] real_dir;
output [3:0] dir = 4'bZ;
OC_Buff ocdir[3:0](real_dir, dir);
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
//**********************************************************************
// SPI zeugs
// synchronizing the handshakes
//
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
wire SCK_high = SCKr[1]; // SCK is high
// same thing for SSEL
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
wire MOSI_data = MOSI;
// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;
reg byte_received; // high when 8 bit has been received
reg [4:0] spibytecnt;
reg [7:0] data_recvd;
reg [7:0] data_sent;
reg [7:0] data_outbuf;
always @(posedge clk) begin
if(SSEL_startmessage) begin
//data_sent <= data_outbuf;
bitcnt <= 3'b000;
spibytecnt <= 5'b00000;
end
if(SSEL_active) begin
if(SCK_risingedge) begin
data_recvd <= {data_recvd[6:0], MOSI_data};
bitcnt <= bitcnt + 3'b001;
if(bitcnt==3'b000)
data_sent <= data_outbuf;
end
else if(SCK_fallingedge) begin
data_sent <= {data_sent[6:0], 1'b0};
if(bitcnt==3'b000) begin
spibytecnt <= spibytecnt + 5'b00001;
end
end
byte_received <= SCK_risingedge && (bitcnt==3'b111);
end
end
assign MISO = data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
reg [7:0] data_inbuf;
always @(posedge clk) begin
if(SSEL_active) begin
//------------------------------------------------- word 0
if(spibytecnt == 5'b00000) begin // 0
data_outbuf <= pos0[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel0[7:0]
end
else if(spibytecnt == 5'b00001) begin // 1
data_outbuf <= pos0[15:8];
if(byte_received)
vel0 <= {data_recvd,data_inbuf}; //vel0
end
else if(spibytecnt == 5'b00010) begin // 2
data_outbuf <= pos0[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel1[7:0]
end
else if(spibytecnt == 5'b00011) begin // 3
data_outbuf <= 8'b0;
if(byte_received)
vel1 <= {data_recvd,data_inbuf}; //vel1
end
//------------------------------------------------- word 1
else if(spibytecnt == 5'b00100) begin // 4
data_outbuf <= pos1[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel2[7:0]
end
else if(spibytecnt == 5'b00101) begin // 5
data_outbuf <= pos1[15:8];
if(byte_received)
vel2 <= {data_recvd,data_inbuf}; //vel2
end
else if(spibytecnt == 5'b00110) begin // 6
data_outbuf <= pos1[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel3[7:0]
end
else if(spibytecnt == 5'b00111) begin // 7
data_outbuf <= 8'b0;
if(byte_received)
vel3 <= {data_recvd,data_inbuf}; //vel3
end
//------------------------------------------------- word 2
else if(spibytecnt == 5'b01000) begin // 8
data_outbuf <= pos2[7:0];
if(byte_received)
data_inbuf <= data_recvd; //real_dout[7:0]
end
else if(spibytecnt == 5'b01001) begin // 9
data_outbuf <= pos2[15:8];
if(byte_received) begin
real_dout <= {data_recvd[5:0],data_inbuf}; //real_dout
end
end
else if(spibytecnt == 5'b01010) begin // 10
data_outbuf <= pos2[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd;
end
else if(spibytecnt == 5'b01011) begin // 11
data_outbuf <= 8'b0;
if(byte_received) begin
tap <= data_recvd[7:6];
steptime <= data_recvd[T-1:0];
Spolarity <= data_inbuf[7];
dirtime <= data_inbuf[T-1:0];
end
end
//------------------------------------------------- word 3
else if(spibytecnt == 5'b01100) data_outbuf <= pos3[7:0];
else if(spibytecnt == 5'b01101) data_outbuf <= pos3[15:8];
else if(spibytecnt == 5'b01110) data_outbuf <= pos3[W+F-1:16];
else if(spibytecnt == 5'b01111) data_outbuf <= 8'b0;
//------------------------------------------------- word 4
else if(spibytecnt == 5'b10000) data_outbuf <= din[7:0];
else if(spibytecnt == 5'b10001) data_outbuf <= din[15:8];
else if(spibytecnt == 5'b10010) data_outbuf <= 8'b0;
else if(spibytecnt == 5'b10011) data_outbuf <= 8'b0;
else data_outbuf <= spibytecnt;
end
end
assign LED = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign do_enable_wdt = data_recvd[6] & (spibytecnt == 5'b01001) & byte_received;
endmodule
|
#include <bits/stdc++.h> #define ln n #define all(dat) dat.begin(), dat.end() #define loop(i, to) for (int i = 0; i < to; ++i) #define cont(i, to) for (int i = 1; i <= to; ++i) #define circ(i, fm, to) for (int i = fm; i <= to; ++i) #define foreach(i, dat) for (__typeof(dat.begin()) i = dat.begin(); i != dat.end(); ++i) typedef long long num; using namespace std; const int nsz = 2e5; bool on[nsz + 5], vis[nsz + 5]; int n, m, rt = 1, dis[nsz + 5], ans[nsz + 5]; int pr[nsz + 5], dep[nsz + 5], siz[nsz + 5], mxs[nsz + 5]; struct graph { int sz, hd[nsz + 5]; struct edge { int nxt, to; edge() {} edge(int nxt, int to) { this->nxt = nxt, this->to = to; } } e[2 * nsz + 5]; inline edge& operator [] (int id) { return e[id]; } void inline link(int u, int v) { e[++sz] = edge(hd[u], v), hd[u] = sz; e[++sz] = edge(hd[v], u), hd[v] = sz; } }; graph g; struct fenwick_tree { int t, tr[nsz + 5], tm[nsz + 5]; void inline clear() { ++t; } void inline chg(int u) { if (tm[u] != t) tm[u] = t, tr[u] = 0; } void inline upd(int u, int w) { for (++u; u > 0; u -= u & -u) chg(u), tr[u] = max(tr[u], w); } int inline qry(int u) { int res = 0; for (++u; u <= n + 1; u += u & -u) chg(u), res = max(res, tr[u]); return res; } }; fenwick_tree tr; void inline bfs() { static int q[nsz + 5]; int ql = 0, qr = 0; cont (u, n) dis[u] = n; cont (u, n) if (on[u]) dis[u] = 0, q[qr++] = u; for (; ql != qr;) { int u = q[ql++]; for (int i = g.hd[u]; i; i = g[i].nxt) { int v = g[i].to; if (dis[v] > dis[u] + 1) dis[v] = dis[u] + 1, q[qr++] = v; } } } void dfs1(vector<int> &nd, int u, int p = -1) { siz[u] = mxs[u] = 1; nd.push_back(u); for (int i = g.hd[u]; i; i = g[i].nxt) { int v = g[i].to; if (v == p || vis[v]) continue; dfs1(nd, v, u); siz[u] += siz[v]; mxs[u] = max(mxs[u], siz[v]); } } void dfs2(int u, int p = -1) { for (int i = g.hd[u]; i; i = g[i].nxt) { int v = g[i].to; if (v == p || vis[v]) continue; dep[v] = dep[u] + 1; dfs2(v, u); } } int inline find_rt(vector<int> &nd, int u) { dfs1(nd, u); int sz = siz[u]; loop (i, nd.size()) { int u = nd[i], cur = max(mxs[u], sz - siz[u]); if (cur * 2 <= sz) return u; } return u; } void inline calc(vector<int> &nd, int u) { dep[u] = 0, dfs2(u); loop (i, nd.size()) { int u = nd[i], k = dis[u] - dep[u] - 1; if (k >= 0) tr.upd(k, dis[u]); } loop (i, nd.size()) { int u = nd[i], k = dep[u]; ans[u] = max(ans[u], tr.qry(k)); } tr.clear(); } void solve(int u = rt) { vector<int> nd; u = find_rt(nd, u); calc(nd, u); vis[u] = 1; for (int i = g.hd[u]; i; i = g[i].nxt) { int v = g[i].to; if (!vis[v]) solve(v); } } int main() { scanf( %d , &n); cont (i, n - 1) { int u, v; scanf( %d%d , &u, &v); g.link(u, v); } scanf( %d , &m); cont (i, m) { int u; scanf( %d , &u); on[u] = 1; } bfs(); solve(); cont (u, n) printf( %d%c , ans[u], n [u < n]); } |
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module: Load / Store Unit
//-----------------------------------------------------------------
module altor32_lsu
(
// Current instruction
input opcode_valid_i /*verilator public*/,
input [7:0] opcode_i /*verilator public*/,
// Load / Store pending
input load_pending_i /*verilator public*/,
input store_pending_i /*verilator public*/,
// Load dest register
input [4:0] rd_load_i /*verilator public*/,
// Load insn in WB stage
input load_wb_i /*verilator public*/,
// Memory status
input mem_access_i /*verilator public*/,
input mem_ack_i /*verilator public*/,
// Load / store still pending
output reg load_pending_o /*verilator public*/,
output reg store_pending_o /*verilator public*/,
// Insert load result into pipeline
output reg write_result_o /*verilator public*/,
// Stall pipeline due load / store / insert
output reg stall_o /*verilator public*/
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
`include "altor32_funcs.v"
//-------------------------------------------------------------------
// Outstanding memory access logic
//-------------------------------------------------------------------
reg inst_load_r;
reg inst_store_r;
always @ *
begin
load_pending_o = load_pending_i;
store_pending_o = store_pending_i;
stall_o = 1'b0;
write_result_o = 1'b0;
// Is this instruction a load or store?
inst_load_r = is_load_operation(opcode_i);
inst_store_r = is_store_operation(opcode_i);
// Store operation just completed?
if (store_pending_o & mem_ack_i & ~mem_access_i)
begin
`ifdef CONF_CORE_DEBUG
$display(" Store operation now completed");
`endif
store_pending_o = 1'b0;
end
// Load just completed (and result ready in-time for writeback stage)?
if (load_pending_o & mem_ack_i & ~mem_access_i & load_wb_i)
begin
// Load complete
load_pending_o = 1'b0;
`ifdef CONF_CORE_DEBUG
$display(" Load operation completed in writeback stage");
`endif
end
// Load just completed (later than writeback stage)?
else if (load_pending_o & mem_ack_i & ~mem_access_i)
begin
`ifdef CONF_CORE_DEBUG
$display(" Load operation completed later than writeback stage");
`endif
// Valid target register?
if (rd_load_i != 5'b00000)
begin
`ifdef CONF_CORE_DEBUG
$display(" Load result now ready for R%d", rd_load_i);
`endif
// Stall instruction and write load result to pipeline
stall_o = opcode_valid_i;
write_result_o = 1'b1;
end
else
begin
`ifdef CONF_CORE_DEBUG
$display(" Load result ready but not needed");
`endif
end
// Load complete
load_pending_o = 1'b0;
end
// If load or store in progress (and this instruction is valid)
if ((load_pending_o | store_pending_o) & opcode_valid_i)
begin
// Load or store whilst memory bus busy
if (inst_load_r | inst_store_r)
begin
`ifdef CONF_CORE_DEBUG
$display(" Data bus already busy, stall (load_pending_o=%d, store_pending_o=%d)", load_pending_o, store_pending_o);
`endif
// Stall!
stall_o = 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[201], bag[201]; int n, l, k; double mem[202][202][202]; double solve(int r, int bagwon, int prizewon) { if (mem[r][bagwon][prizewon] >= -.5) return mem[r][bagwon][prizewon]; if (r == n) return mem[r][bagwon][prizewon] = bagwon + k >= prizewon && prizewon >= l ? 1 : 0; if (bag[r] == -1) return mem[r][bagwon][prizewon] = double(p[r] * solve(r + 1, bagwon, prizewon + 1) + (100 - p[r]) * solve(r + 1, bagwon, prizewon)) / 100; else return mem[r][bagwon][prizewon] = double(p[r] * solve(r + 1, min(200, bagwon + bag[r] + 1), prizewon + 1) + (100 - p[r]) * solve(r + 1, bagwon, prizewon)) / 100; } int main() { memset(mem, -1, sizeof mem); cin >> n >> l >> k; for (int i = 0; i < n; i++) cin >> p[i]; for (int i = 0; i < n; i++) cin >> bag[i]; cout.precision(100); cout << fixed << solve(0, 0, 0) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long Max = 1e5 + 10; int T; long long n, m; long long number[Max]; int main() { cin >> T; while (T--) { cin >> n >> m; long long ans = 1; int k = 1; for (int i = 1;; i *= 2) { number[k] = number[k - 1] + i; if (number[k] > n) { ans = (ans * (n - number[k - 1] + 1) % m) % m; break; } else { ans = ans * (i + 1) % m; } k++; } cout << (ans - 1 + m) % m << endl; } return 0; } |
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_one_hot (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 32;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ONE_HOT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_one_hot_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_one_hot_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_one_hot_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_one_hot
`endif
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } const long long Mod = 1e9 + 7; const long long pre = 1e10; const double inv = pow(10, -10); double y, y2, yw, xb, yb, r; int check(long long xp) { double p = (double)xp * inv; double slope = (yw - r - yb) / (xb - p); double c = (yw - r) - slope * p; if (c >= y2) return 1; if (c <= y) return -1; bool a = (c >= y + r); bool b = (abs(y2 - c) >= r * (sqrt(1 + slope * slope))); if (a && b) return 0; else if (!a && !b) return -1; else if (!a) return -1; else return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> y >> y2 >> yw >> xb >> yb >> r; long long left = 0, right = xb * pre - 1, mid; while (left <= right) { mid = (left + right) / 2; int t = check(mid); if (t == 0) { printf( %0.10lf n , (double)mid * inv); return 0; } else if (t == 1) left = mid + 1; else if (t == -1) right = mid - 1; else { cout << -1 << endl; return 0; } } cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; using ppi = pair<pii, int>; char s[200100]; int rk[200100], sa[200100], ht[200100]; int mn[200100][22]; namespace SA { int head[200100 * 2]; ppi pos[200100 * 2], buf[200100 << 1], tbuf[200100 << 1]; int nxt[200100 * 2]; void bucket_sort(int ok, int n) { int i, u, j, deg, E, K; for (i = E = K = 0; i < max(222, n + 10); i++) head[i] = -1; for (i = 0; i < n; i++) { if (ok) u = pos[i].first.first + 1; else u = pos[i].first.second + 1; buf[E] = pos[i]; nxt[E] = head[u]; head[u] = E++; } for (int i = 0; i < max(n + 10, 222); i++) { for (deg = 0, j = head[i]; ~j; j = nxt[j]) { tbuf[deg++] = buf[j]; } while (deg) pos[K++] = tbuf[--deg]; } } void LCP(int n) { for (int i = 1; i <= n; i++) mn[i][0] = ht[i]; for (int j = 1; j < 22; j++) { for (int i = 1; i <= n; i++) { mn[i][j] = min(mn[i][j - 1], mn[min(n, i + (1 << j - 1))][j - 1]); } } } void height(int n) { int h = 0, i; for (i = 0; i < n; i++) sa[rk[i]] = i; for (i = 0; i < n; i++) { if (rk[i] == 1) continue; h = max(0, h - 1); for (int j = sa[rk[i] - 1]; s[i + h] == s[j + h]; h++) ; ht[rk[i]] = h; } } void buildSA(int n) { int i, j, cnt, u; for (i = 0; i < n; i++) rk[i] = s[i]; rk[n] = 0; for (i = 0; i < 20; i++) { for (j = 0; j < n; j++) pos[j] = ppi(pii(rk[j], rk[min(n, j + (1 << i))]), j); bucket_sort(0, n); bucket_sort(1, n); pos[n] = ppi(pii(-1, -1), -1); for (cnt = j = 0; j < n; j++) { rk[pos[j].second] = cnt + 1; cnt += (pos[j].first != pos[j + 1].first); } if (cnt == n) break; } height(n); LCP(n); } int calc(int u, int v) { if (u == v) return 100000000; u = rk[u], v = rk[v]; if (u > v) swap(u, v); u++; int l = 31 - __builtin_clz(v - u + 1); return min(mn[u][l], mn[v - (1 << l) + 1][l]); } } // namespace SA using namespace SA; using INT = long long; char vst[200100]; int cnt[200100]; int main() { int n; cin >> n; cin >> s; cin >> vst; reverse(s, s + n); buildSA(n); INT ans = 0; for (int i = 1; i <= n; i++) { int u = sa[i]; cnt[i] = cnt[i - 1]; u = n - sa[i] - 1; if (vst[u] == 0 ) { ans = max(ans, (INT)n - sa[i]); cnt[i]++; } } for (int i = 2; i <= n; i++) { int st = 0, ed = i; while (st + 1 < ed) { int md = (st + ed) >> 1; if (calc(sa[md], sa[i]) >= ht[i]) ed = md; else st = md; } int l = ed; st = i, ed = n + 1; while (st + 1 < ed) { int md = (st + ed) >> 1; if (calc(sa[md], sa[i]) >= ht[i]) st = md; else ed = md; } int r = st; ans = max(ans, (INT)ht[i] * (cnt[r] - cnt[l - 1])); } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long double PI = 4.0 * atan(1.0); void EnchomSolve() { int l; long double L; long double ans = 0.0; long double area; long double height; long double help, help2; scanf( %d , &l); L = (long double)l; help = L / sqrt(3.0); height = sqrt(L * L - help * help); help = (sqrt(3.0) / 2.0) * L; area = (help * L) / 2.0; ans += area * height / 3.0; scanf( %d , &l); L = (long double)l; help = (sqrt(2.0) / 2.0) * L; height = sqrt(L * L - help * help); area = L * L; ans += area * height / 3.0; scanf( %d , &l); L = (long double)l; help = L / (sqrt(2.0 - 2.0 * cos(72.0 * PI / 180.0))); height = sqrt(L * L - help * help); help2 = sqrt(help * help - (L / 2.0) * (L / 2.0)); area = L * help2 / 2.0; area *= 5.0; ans += area * height / 3.0; printf( %.10f n , (double)ans); return; } int main() { EnchomSolve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long d = 20; long long n, m, dsu[80], cc[80], al[40], dp[1ll << d]; long long fd(long long x) { if (dsu[x] != x) { dsu[x] = fd(dsu[x]); } return dsu[x]; } int main() { long long i, ii, k, l, mk, mk2, z[4] = {1, 1, 1, 0}; scanf( %lld%lld , &n, &m); if (!m) { printf( 0 n ); return 0; } for (i = 0; i < n * 2; i++) { dsu[i] = i; cc[i] = 1; } for (i = 0; i < m; i++) { scanf( %lld%lld , &k, &l); k--; l--; for (ii = 0; ii < 2; ii++) { if (fd(k) != fd(n + l)) { cc[fd(k)] += cc[fd(n + l)]; dsu[fd(n + l)] = fd(k); } al[k] |= 1ll << l; swap(k, l); } } for (i = 0; i < n * 2; i++) { z[0] *= i >= n || fd(i) != fd(n + i); } for (i = 0; i < n; i++) { if (fd(i) != fd(n + i)) { cc[fd(i)] += cc[fd(n + i)]; dsu[fd(n + i)] = fd(i); } } for (i = 0; i < n * 2; i++) { if (fd(i) == i) { z[0] *= 2; z[1] *= 2; z[2] *= 1 + (fd(i) == i && cc[i] == 2); } } for (mk = 0; mk < 1ll << min(d, n); mk++) { for (i = 0; i < min(d, n); i++) { if ((mk >> i & 1) && (mk & al[i])) { break; } } dp[mk] += i >= min(d, n); } for (i = 0; i < min(d, n); i++) { for (mk = (1ll << min(d, n)) - 1; mk + 1; mk--) { dp[mk] += dp[mk ^ 1ll << i] * (mk >> i & 1); } } for (mk = 0; mk < 1ll << n; mk += 1ll << min(d, n)) { for (i = min(d, n); i < n; i++) { if ((mk >> i & 1) && (mk & al[i])) { break; } } if (i < n) { continue; } mk2 = 0; for (i = 0; i < min(d, n); i++) { mk2 |= (long long)!(mk & al[i]) << i; } z[3] += dp[mk2]; } printf( %lld n , (1ll << n) - z[1] - z[3] * 2 + z[0] + z[2] * 2); } |
#include <bits/stdc++.h> using namespace std; int main() { long long a, b = 0, c = 0, n, t; cin >> t; for (int o = 1; o <= t; o++) { b = 0; c = 0; cin >> n; for (int i = 1; i <= n; i++) { cin >> a; if (a != 1) { c = 1; } else { if (c == 0) { b = b + 1; } } } if (n == 1) { cout << First ; } else { if (c == 0) { if (n % 2 == 0) { cout << Second ; } else { cout << First ; } } else { if (b % 2 == 0) { cout << First ; } else { cout << Second ; } } } cout << endl; } return 0; } |
// Copyright (C) 1991-2014 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// Pipeline (Internal) for Formal Verification ////////////
//////////////////////////////////////////////////////////////////////////////////////////
// MODEL BEGIN
module pipeline_internal_fv (
// INTERFACE BEGIN
clk, // clock
ena, // clock enable
clr, // async clear
d, // data in
piped // output
);
// INTERFACE END
//// top level parameters ////
parameter data_width = 1;
parameter latency = 1;
//// port declarations ////
// data input ports
input [data_width - 1 : 0] d;
// control signals
input clk,ena,clr;
// output ports
output [data_width - 1 : 0] piped;
wire [data_width-1 : 0] out;
wire [data_width*(latency-1) : 1] t;
wire [data_width*latency-1 : 0] d_w;
assign piped = out;
//// nets/registers ////
// IMPLEMENTATION BEGIN
generate
if(latency==0) begin
assign out = d;
end
else if(latency==1) begin
assign d_w = ena? d : out;
dff_bus #(data_width) p (.q(out), .clk(clk), .d(d_w), .clr(clr));
end
else begin
assign d_w = ena? {t,d} : {out,t};
dff_bus #(data_width) p[1:latency] (.q({out,t}), .clk(clk), .d(d_w), .clr(clr));
end
endgenerate
// IMPLEMENTATION END
endmodule
// MODEL END
module dff_bus (q, clk, d, clr);
parameter data_width = 1;
input [data_width-1 : 0] d;
input clk, clr;
output [data_width-1 : 0] q;
generate
if(data_width==1) begin
dffep reg_prim_inst (q,clk,1'b1,d,1'b0,clr);
end
else begin
dffep reg_prim_inst[data_width-1:0] (q,clk,1'b1,d,1'b0,clr);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int count = 0; int len = s.size(); bool small = false; for (int i = 0; i < len; i++) { if (s[i] < a ) { count++; } if (s[0] >= a ) { small = true; } } if (count == len || (count == len - 1 && small)) { for (int i = 0; i < len; i++) { if (i == 0 && count == len) { s[i] = s[i] + 32; } else if (i == 0 && small) { s[i] = s[i] - 32; } else { s[i] = s[i] + 32; } } } cout << s << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n; for (int k = 0; k < n; k++) { cin >> m; for (int i = 0; i < m / 2; i++) { int fir, sec; cin >> fir >> sec; if (fir > 0 && sec > 0) { cout << sec << << -fir << ; } else if (fir < 0 && sec < 0) { cout << -sec << << fir << ; } else if (fir > 0 && sec < 0) { cout << -sec << << fir << ; } else if (fir < 0 && sec > 0) { cout << sec << << -fir << ; } } cout << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_4_V
`define SKY130_FD_SC_HD__AND4BB_4_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_4_V
|
#include <bits/stdc++.h> using namespace std; double work(int x) { if (x == 0) return 1; double n = 1.000000011; double ans = 1; while (x > 0) { if ((x & 1) == 1) ans *= n; n *= n; x /= 2; } return ans; } int main() { int n, t; cin >> n >> t; printf( %0.20lf n , work(t) * n); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 61; int a[N], n; long long dp[N][2][2], k; long long Dfs(int pos, int x, int y) { if (pos < n - pos + 1) return 1; if (dp[pos][x][y] != -1) return dp[pos][x][y]; long long ans = 0; for (int i = 0; i < 2; i++) if (a[pos] == -1 || a[pos] == i) for (int j = 0; j < 2; j++) if (a[n - pos + 1] == -1 || a[n - pos + 1] == j) { if (x && (i > j) || y && (i > !j) || pos == n - pos + 1 && (i != j)) continue; ans += Dfs(pos - 1, x && (i == j), y && (i != j)); } return dp[pos][x][y] = ans; } int main() { scanf( %d%lld , &n, &k); k++; memset(dp, -1, sizeof(dp)); memset(a, -1, sizeof(a)); a[n] = 0; if (Dfs(n, 1, 1) < k) puts( -1 ); else { for (int i = n - 1; i > 0; i--) { a[i] = 0; memset(dp, -1, sizeof(dp)); long long num = Dfs(n, 1, 1); if (k > num) k -= num, a[i] = 1; } for (int i = n; i >= 1; i--) printf( %d , a[i]); puts( ); } } |
#include <bits/stdc++.h> using namespace std; const int S = (int)1e6; int dp[S]; string txt, pat; vector<int> ans; void kmp() { int i = 0, j = -1, n = ((int)(txt.size())), m = ((int)(pat.size())); dp[0] = -1; while (i < m) { while (j >= 0 and pat[i] != pat[j]) j = dp[j]; i++, j++; dp[i] = j; } } int main() { ios::sync_with_stdio(0); a: string s, s2; cin >> s >> s2; int ones = 0, zeros = 0, ones2 = 0, zeros2 = 0, ones3 = 0, zeros3 = 0; for (char c : s) (c == 0 ) ? zeros++ : ones++; pat = s2; kmp(); string res = s2, r = s2.substr(dp[((int)(s2.size()))], ((int)(s2.size())) - dp[((int)(s2.size()))]); for (char c : res) (c == 0 ) ? zeros2++ : ones2++; for (char c : r) (c == 0 ) ? zeros3++ : ones3++; if (zeros2 > zeros or ones2 > ones) cout << s << n ; else { while (1) { if (zeros2 + zeros3 > zeros or ones2 + ones3 > ones) break; res += r; zeros2 += zeros3; ones2 += ones3; } for (int i = 0; i < zeros - zeros2; i++) res += 0 ; for (int i = 0; i < ones - ones2; i++) res += 1 ; cout << res << n ; } } |
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module to_driver_sd_avs(
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input hdd_avalon_master
input wire [31:0] hdd_avalon_master_address,
input wire hdd_avalon_master_read,
output wire [31:0] hdd_avalon_master_readdata,
input wire hdd_avalon_master_write,
input wire [31:0] hdd_avalon_master_writedata,
output wire hdd_avalon_master_waitrequest,
output reg hdd_avalon_master_readdatavalid,
// input bios_loader
input wire [31:0] bios_loader_address,
input wire bios_loader_read,
output wire [31:0] bios_loader_readdata,
input wire bios_loader_write,
input wire [31:0] bios_loader_writedata,
output wire bios_loader_waitrequest,
input wire [3:0] bios_loader_byteenable,
// output driver_sd_avs
output wire [1:0] driver_sd_avs_address,
output wire driver_sd_avs_read,
input wire [31:0] driver_sd_avs_readdata,
output wire driver_sd_avs_write,
output wire [31:0] driver_sd_avs_writedata
);
assign driver_sd_avs_address = (~ao486_rst) ? hdd_avalon_master_address[3:2] : bios_loader_address[3:2];
assign driver_sd_avs_read = (~ao486_rst) ? hdd_avalon_master_read : bios_loader_read && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_write = (~ao486_rst) ? hdd_avalon_master_write : bios_loader_write && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_writedata = (~ao486_rst) ? hdd_avalon_master_writedata : bios_loader_writedata;
assign hdd_avalon_master_readdata = (~ao486_rst) ? driver_sd_avs_readdata : 0;
assign hdd_avalon_master_waitrequest = 0;
always @(posedge clk_sys) hdd_avalon_master_readdatavalid <= (~ao486_rst) ? driver_sd_avs_read : 0;
assign bios_loader_readdata = (~ao486_rst) ? 0 : driver_sd_avs_readdata;
assign bios_loader_waitrequest = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { long long res = 1; a %= 998244353; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % 998244353 % 998244353; a = a * a % 998244353; } return res; } long long gcd(long long a, long long b) { if (a < b) return gcd(b, a); if (b == 0) return a; return gcd(b, a % b); } long long n, m; long long flg = 0; vector<long long> ad[500005]; long long t[500005]; int main() { ios::sync_with_stdio(0); cin.tie(0); ; long long i, j, k, x; cin >> n >> m; for (i = 0; i < m; i++) { cin >> j >> k; ad[j].push_back(k); ad[k].push_back(j); } vector<pair<long long, long long> > ans; for (i = 1; i <= n; i++) { cin >> t[i]; ans.push_back(make_pair(t[i], i)); } sort(ans.begin(), ans.end()); for (i = 1; i <= n; i++) { set<long long> tp; for (auto x : ad[i]) { tp.insert(t[x]); } for (j = 1; j < t[i]; j++) { auto it = tp.find(j); if (it == tp.end()) { cout << -1 << n ; return 0; } else { tp.erase(j); } } auto it = tp.find(t[i]); if (it != tp.end()) { cout << -1 << n ; return 0; } } for (i = 0; i < ans.size(); i++) { cout << ans[i].second << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> int cnt[111], ans, b, d, pr[111], v[111]; int main() { scanf( %d%d , &b, &d); int k = b; for (int i = 2; k > 1; i++) { if (k % i) continue; while (k % i == 0) cnt[i]++, k /= i; } bool flag = true; k = d; for (int i = 2; k > 1; i++) { if (k % i) continue; int x = 1; while (k % i == 0) pr[i]++, k /= i, x *= i; v[x] = -i; if (cnt[i] == 0) { flag = false; continue; } int p = (pr[i] - 1) / cnt[i] + 1; if (p > ans) ans = p; } if (flag) printf( 2-type n%d n , ans); else { if (b % d == 1) printf( 3-type n ); else if ((b + 1) % d == 0) printf( 11-type n ); else { flag = true; for (int i = 2; i <= d; i++) { if (v[i] >= 0 || cnt[-v[i]] || b % i == 1 || (b + 1) % i == 0) continue; flag = false; break; } if (flag) printf( 6-type n ); else printf( 7-type n ); } } } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5; const long long mod = 998244353; long long a[N]; long long n, m, k; long long pw(long long n, long long k) { if (!k) return 1; long long res = pw(n, k >> 1); res = res * res % mod; if (k & 1) return res * n % mod; return res; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> k; for (long long i = 1; i <= m; i++) { cin >> a[i]; } long long ans = 1; for (long long i = 1; i <= m; i++) { long long num = a[i] - a[i - 1]; (ans *= pw(k, 2 * num) + pw(k, num)) %= mod; if (ans < 0) ans += mod; } (ans *= pw(k, n - 2 * a[m])) %= mod; (ans *= pw(pw(2, m), mod - 2)) %= mod; cout << ans; return 0; } |
/*
*
* Copyright (c) 2011
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 6'd4
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
wire [511:0] W;
wire [255:0] state;
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; int res = 0, cur = 0, tmp; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> tmp; res = (cur + tmp) / m; cur = (cur + tmp) % m; cout << res << ; } } |
#include <bits/stdc++.h> using namespace std; long long tab[12], pr[12]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int q; cin >> q; long long n, m, w, x; for (int z = 0; z < q; z++) { cin >> n >> m; x = 1; for (long long i = 1; i <= 11; i++) { tab[i] = (tab[i - 1] + (m % 10)) % 10; pr[i] = pr[i - 1] + tab[i]; if (tab[i] == tab[1] && i > 1) { x = i - 1; break; } } w = pr[x] * (n / (x * m)); n %= x * m; w += pr[n / m]; cout << w << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } void solve() { long long p, q; cin >> p >> q; long long g = p; long long t = q; map<long long, long long> f, l; for (long long i = 2; i * i <= t; i++) { if (t % i == 0) { while (g % i == 0) { g /= i; f[i]++; } while (t % i == 0) { t /= i; l[i]++; } } } if (t != 1) { while (g % t == 0) { g /= t; f[t]++; } l[t]++; t = 1; } long long ans = g; for (auto x : l) { long long u = p; for (int i = 0; i < max(0ll, f[x.first] - x.second + 1); i++) u /= x.first; ans = max(ans, u); } cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int q = 1; cin >> q; for (; q > 0; q--) { solve(); cout << endl; } } |
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; const long long inf = (long long)1e9; double PI = 3.14159265; double eps = 1e-9; long long t = 0; long long pow(long long a, long long b) { if (b == 0) return 1; if (b % 2 == 1) { return (pow(a, b - 1) * a); } if (b % 2 == 0) { long long c = pow(a, b / 2); return (c * c); } } vector<pair<long long, long long>> reb; long long dp[1 << 17]; long long krask[1 << 17]; vector<vector<long long>> g; vector<long long> dep; vector<vector<long long>> p; vector<vector<long long>> dep2; vector<long long> u; vector<long long> tin, tout; void dfs(long long v, long long k) { tin[v] = t++; p[v][0] = k; for (long long i = 1; i < 20; i++) { p[v][i] = p[p[v][i - 1]][i - 1]; } for (long long i = 0; i < g[v].size(); i++) { long long to = g[v][i]; if (dep[to] == -1) { dep[to] = dep[v] + 1; dep2[dep[to]].push_back(t); dfs(to, v); } } tout[v] = t; } long long parent(long long v, long long h) { for (long long i = 0; i < 20; i++) { if ((h & (1 << i))) { v = p[v][i]; } } return v; } long long lca(long long a, long long b) { if (dep[a] < dep[b]) swap(a, b); a = parent(a, dep[a] - dep[b]); if (a == b) return a; for (long long i = 19; i >= 0; i--) { if (p[a][i] != p[b][i]) { a = p[a][i]; b = p[b][i]; } } return parent(a, 1); } struct stree { vector<long long> t; int n; stree(vector<long long> a) { n = 1; while (n < a.size()) { n *= 2; } t.resize(n + n); for (int i = n; i < n + a.size(); i++) { t[i] = a[i - n]; } for (int i = n - 1; i > 0; i--) { t[i] = t[i + i] + t[i + i + 1]; } } long long sum(long long l, long long r) { long long sum = 0; for (l += n, r += n; l <= r; l /= 2, r /= 2) { if (l % 2 == 1) { sum += t[l++]; } if (r % 2 == 0) { sum += t[r--]; } } return sum; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q; cin >> n >> q; vector<long long> a; a.resize(n); for (int i = 0; i < n; i++) { cin >> a[i]; } stree d(a); vector<long long> k; k.resize(q); long long gl = 0; int pred = 0; for (int i = 0; i < q; i++) { cin >> k[i]; long long r = a.size(), l = gl - 1; while (r - l > 1) { long long mid = (l + r) / 2; long long sum = d.sum(gl, mid); if (sum > k[i] + pred) r = mid; else { l = mid; } } if (r == a.size()) { gl = 0; pred = 0; } else { if (k[i] + pred < d.sum(gl, r - 1)) { pred = k[i] + pred; } else { pred = k[i] + pred - d.sum(gl, r - 1); gl = r; } } cout << a.size() - gl << endl; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] in;
wire a,y,y_fixed;
wire b = in[0];
wire en = in[1];
pullup(a);
ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
initial in=0;
// Test loop
always @ (posedge clk) begin
in <= in + 1;
$display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed);
if (en) begin
// driving b
// a should be b
// y and yfix should also be b
if (a!=b || y != b || y_fixed != b) begin
$display ( "Expected a %d y %b yfix %b" , a, y, y_fixed);
$stop;
end
end else begin
// not driving b
// a should be 1 (pullup)
// y and yfix shold be 1
if (a!=1 || y != 1 || y_fixed != 1) begin
$display( "Expected a,y,yfix == 1");
$stop;
end
end
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module ChildA(inout A, input B, input en, output Y, output Yfix);
// workaround
wire a_in = A;
ChildB childB(.A(A), .Y(Y));
assign A = en ? B : 1'bz;
ChildB childBfix(.A(a_in),.Y(Yfix));
endmodule
module ChildB(input A, output Y);
assign Y = A;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i]; b[n - 1] = a[n - 1]; for (int j = 0; j < n - 1; j++) b[j] = a[j] + a[j + 1]; for (int k = 0; k < n; k++) cout << b[k] << ; return 0; } |
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_gpu_dma_addr.v
//
// *Module Description:
// Compute next Video-Ram address
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_gpu_dma_addr (
// OUTPUTs
vid_ram_addr_nxt_o, // Next Video-RAM address
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
display_width_i, // Display width
gfx_mode_1_bpp_i, // Graphic mode 1 bpp resolution
gfx_mode_2_bpp_i, // Graphic mode 2 bpp resolution
gfx_mode_4_bpp_i, // Graphic mode 4 bpp resolution
gfx_mode_8_bpp_i, // Graphic mode 8 bpp resolution
gfx_mode_16_bpp_i, // Graphic mode 16 bpp resolution
vid_ram_addr_i, // Video-RAM address
vid_ram_addr_init_i, // Video-RAM address initialization
vid_ram_addr_step_i, // Video-RAM address step
vid_ram_width_i, // Video-RAM width
vid_ram_win_x_swap_i, // Video-RAM X-Swap configuration
vid_ram_win_y_swap_i, // Video-RAM Y-Swap configuration
vid_ram_win_cl_swap_i // Video-RAM CL-Swap configuration
);
// OUTPUTs
//=========
output [`APIX_MSB:0] vid_ram_addr_nxt_o; // Next Video-RAM address
// INPUTs
//=========
input mclk; // Main system clock
input puc_rst; // Main system reset
input [`LPIX_MSB:0] display_width_i; // Display width
input gfx_mode_1_bpp_i; // Graphic mode 1 bpp resolution
input gfx_mode_2_bpp_i; // Graphic mode 2 bpp resolution
input gfx_mode_4_bpp_i; // Graphic mode 4 bpp resolution
input gfx_mode_8_bpp_i; // Graphic mode 8 bpp resolution
input gfx_mode_16_bpp_i; // Graphic mode 16 bpp resolution
input [`APIX_MSB:0] vid_ram_addr_i; // Video-RAM address
input vid_ram_addr_init_i; // Video-RAM address initialization
input vid_ram_addr_step_i; // Video-RAM address step
input [`LPIX_MSB:0] vid_ram_width_i; // Video-RAM width
input vid_ram_win_x_swap_i; // Video-RAM X-Swap configuration
input vid_ram_win_y_swap_i; // Video-RAM Y-Swap configuration
input vid_ram_win_cl_swap_i; // Video-RAM CL-Swap configuration
//=============================================================================
// 1) COMPUTE NEXT MEMORY ACCESS
//=============================================================================
reg [`APIX_MSB:0] vid_ram_line_addr;
reg [`LPIX_MSB:0] vid_ram_column_count;
// Detect when the current line refresh is done
wire vid_ram_line_done = vid_ram_addr_step_i & (vid_ram_column_count==(vid_ram_width_i-{{`LPIX_MSB{1'b0}}, 1'b1}));
// Mux between initialization value and display width
wire [`LPIX_MSB:0] vid_ram_length_mux = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;
// Align depending on graphic mode
wire [`LPIX_MSB+4:0] vid_ram_length_align = {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4'b0000, vid_ram_length_mux[`LPIX_MSB:0] } |
{`LPIX_MSB+5{gfx_mode_2_bpp_i }} & {3'b000, vid_ram_length_mux[`LPIX_MSB:0], 1'b0 } |
{`LPIX_MSB+5{gfx_mode_4_bpp_i }} & {2'b00, vid_ram_length_mux[`LPIX_MSB:0], 2'b00 } |
{`LPIX_MSB+5{gfx_mode_8_bpp_i }} & {1'b0, vid_ram_length_mux[`LPIX_MSB:0], 3'b000 } |
{`LPIX_MSB+5{gfx_mode_16_bpp_i}} & { vid_ram_length_mux[`LPIX_MSB:0], 4'b0000} ;
wire [`APIX_MSB:0] plus_one_val = {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4'b0000, {{`VRAM_MSB{1'b0}}, 1'b1} } |
{`APIX_MSB+1{gfx_mode_2_bpp_i }} & {3'b000, {{`VRAM_MSB{1'b0}}, 1'b1}, 1'b0 } |
{`APIX_MSB+1{gfx_mode_4_bpp_i }} & {2'b00, {{`VRAM_MSB{1'b0}}, 1'b1}, 2'b00 } |
{`APIX_MSB+1{gfx_mode_8_bpp_i }} & {1'b0, {{`VRAM_MSB{1'b0}}, 1'b1}, 3'b000 } |
{`APIX_MSB+1{gfx_mode_16_bpp_i}} & { {{`VRAM_MSB{1'b0}}, 1'b1}, 4'b0000} ;
// Zero extension for LINT cleanup
wire [`APIX_MSB*3:0] vid_ram_length_norm = {{`APIX_MSB*3-`LPIX_MSB-4{1'b0}}, vid_ram_length_align};
// Select base address for next calculation
wire [`APIX_MSB:0] next_base_addr = (vid_ram_addr_init_i | ~vid_ram_line_done) ? vid_ram_addr_i :
vid_ram_line_addr ;
// Compute next address
wire [`APIX_MSB:0] next_addr = next_base_addr
+ (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_y_swap_i & (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
- (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_y_swap_i & (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
+ (plus_one_val & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
- (plus_one_val & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}});
wire update_line_addr = vid_ram_addr_init_i | vid_ram_line_done;
wire update_pixel_addr = update_line_addr | vid_ram_addr_step_i;
// Start RAM address of currentely refreshed line
always @(posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_line_addr <= {`APIX_MSB+1{1'b0}};
else if (update_line_addr) vid_ram_line_addr <= next_addr;
// Current RAM address of the currentely refreshed pixel
assign vid_ram_addr_nxt_o = update_pixel_addr ? next_addr : vid_ram_addr_i;
// Count the pixel number in the current line
// (used to detec the end of a line)
always @(posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_column_count <= {`LPIX_MSB+1{1'b0}};
else if (vid_ram_addr_init_i) vid_ram_column_count <= {`LPIX_MSB+1{1'b0}};
else if (vid_ram_line_done) vid_ram_column_count <= {`LPIX_MSB+1{1'b0}};
else if (vid_ram_addr_step_i) vid_ram_column_count <= vid_ram_column_count + {{`LPIX_MSB{1'b0}}, 1'b1};
endmodule // ogfx_calc_vram_addr
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: city.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module city (
address,
clock,
q);
input [14:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./audio_mifs/city.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./audio_mifs/city.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL city.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL city.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL city_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = 105; int n, m; map<string, int> h; string name[N], str[N], re[N]; bool f[N][N]; int g[N][N]; void print(int x, int y) { if (x == 0) { return; } print(x - 1, g[x][y]); cout << name[y] << re[x - 1] << endl; } void work() { scanf( %d , &n); h.clear(); for (int i = 0; i < n; ++i) { cin >> name[i]; h[name[i]] = i; } scanf( %d n , &m); memset(f, 0, sizeof(f)); memset(g, 0, sizeof(g)); f[0][n] = 1; for (int i = 0; i < m; ++i) { getline(cin, str[i]); re[i].clear(); } for (int i = 0; i < m; ++i) { string usr, buf = str[i]; int p = 0; while (p < buf.size() && buf[p] != : ) { usr += buf[p++]; } int q = p; while (q < buf.size()) { re[i] += buf[q++]; } set<int> mention; while (p < buf.size()) { string word; while (p < buf.size() && isalnum(buf[p])) { word += buf[p++]; } if (h.count(word)) { mention.insert(h[word]); } if (p < buf.size()) ++p; } if (usr == ? ) { for (int j = 0; j <= n; ++j) { if (!f[i][j]) continue; for (int k = 0; k < n; ++k) { if (mention.count(k) || k == j) continue; f[i + 1][k] = 1; g[i + 1][k] = j; } } } else { if (!h.count(usr)) { puts( Impossible ); return; } int id = h[usr]; if (!mention.count(id)) { for (int j = 0; j <= n; ++j) { if (f[i][j] && id != j) { f[i + 1][id] = 1; g[i + 1][id] = j; } } } } } int x = -1; for (int i = 0; i < n; ++i) { if (f[m][i]) { x = i; } } if (x == -1) { puts( Impossible ); } else { print(m, x); } } int main() { int T; scanf( %d , &T); while (T--) { work(); } } |
#include <bits/stdc++.h> using namespace std; const int MaxN = int(2e5) + 256; const int INF = int(1e9); const int mod = (int)(1e9) + 7; const double pi = 3.1415926535897932384626433832795; long long n, m, ans, A[MaxN], k, a, b, q; long long t[MaxN * 8], t1[MaxN * 8]; void upd(int v, int l, int r, int pos, int val) { if (l == r) { t[v] += val; t1[v] += val; t[v] = min(a, t[v]); t1[v] = min(t1[v], b); return; } int m = (l + r) / 2; if (pos <= m) { upd(v + v, l, m, pos, val); } else upd(v + v + 1, m + 1, r, pos, val); t[v] = t[v + v] + t[v + v + 1]; t1[v] = t1[v + v] + t1[v + v + 1]; } long long get(int v, int l, int r, int tl, int tr) { if (l > tr || r < tl) return 0; if (tl <= l & r <= tr) return t[v]; int m = (l + r) / 2; return get(v + v, l, m, tl, tr) + get(v + v + 1, m + 1, r, tl, tr); } long long get1(int v, int l, int r, int tl, int tr) { if (l > tr || r < tl) return 0; if (tl <= l & r <= tr) return t1[v]; int m = (l + r) / 2; return get1(v + v, l, m, tl, tr) + get1(v + v + 1, m + 1, r, tl, tr); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> k >> a >> b >> q; while (q--) { int type; cin >> type; if (type == 1) { int x, y; cin >> x >> y; upd(1, 1, n, x, y); } else { int p; cin >> p; int S = 0; if (p > 1) { S = get1(1, 1, n, 1, p - 1); } int S1 = 0; if (p + k <= n) { S1 = get(1, 1, n, p + k, n); } cout << S + S1 << n ; } } return 0; } |
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length Encoder, remove zero sequences ////
//// ////
//// - Detect (15,0) (0,0) seqence ////
//// - Replace them by (0,0) ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rzs.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rzs.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rzs(clk, ena, rst, deni, dci, rleni, sizei, ampi, deno, dco, rleno, sizeo, ampo);
//
// inputs & outputs
//
input clk;
input ena;
input rst;
input deni;
input dci;
input [ 3:0] sizei;
input [ 3:0] rleni;
input [11:0] ampi;
output deno;
output dco;
output [ 3:0] sizeo;
output [ 3:0] rleno;
output [11:0] ampo;
reg deno, dco;
reg [ 3:0] sizeo, rleno;
reg [11:0] ampo;
//
// variables
//
reg [ 3:0] size;
reg [ 3:0] rlen;
reg [11:0] amp;
reg den;
reg dc;
wire eob;
wire zerobl;
reg state;
//
// module body
//
always @(posedge clk)
if(ena & deni)
begin
size <= #1 sizei;
rlen <= #1 rleni;
amp <= #1 ampi;
end
always @(posedge clk)
if(ena)
begin
sizeo <= #1 size;
rleno <= #1 rlen;
ampo <= #1 amp;
dc <= #1 dci;
dco <= #1 dc;
end
assign zerobl = &rleni & ~|sizei & deni;
assign eob = ~|{rleni, sizei} & deni & ~dci;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= #1 1'b0;
den <= #1 1'b0;
deno <= #1 1'b0;
end
else
if(ena)
case (state) // synopsys full_case parallel_case
1'b0:
begin
if (zerobl)
begin
state <= #1 1'b1; // go to zero-detection state
den <= #1 1'b0; // do not yet set data output enable
deno <= #1 den; // output previous data
end
else
begin
state <= #1 1'b0; // stay in 'normal' state
den <= #1 deni; // set data output enable
deno <= #1 den; // output previous data
end
end
1'b1:
begin
deno <= #1 1'b0;
if (deni)
if (zerobl)
begin
state <= #1 1'b1; // stay in zero-detection state
den <= #1 1'b0; // hold current zer-block
deno <= #1 1'b1; // output previous zero-block
end
else if (eob)
begin
state <= #1 1'b0; // go to 'normal' state
den <= #1 1'b1; // set output enable for EOB
deno <= #1 1'b0; // (was already zero), maybe optimize ??
end
else
begin
state <= #1 1'b0; // go to normal state
den <= #1 1'b1; // set data output enable
deno <= #1 1'b1; // oops, zero-block should have been output
end
end
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int m, n, a[2000100], b[2000100], d[2000100], ans = 1, pos[2000100]; int between(int x, int y, int z) { if (z < y) return x < z || x > y; return x > y && x < z; } int main() { memset(d, -1, sizeof(d)); cin >> m >> n; for (int i = 0; i < m; i++) scanf( %d , &a[i]); for (int i = 0; i < n; i++) scanf( %d , &b[i]), d[b[i]] = i; int M = 0; for (int i = 0; i < m; i++) if (d[a[i]] >= 0) a[M] = a[i], pos[M++] = i; swap(m, M); if (!m) { puts( 0 ); return 0; } for (int i = 0; i < m; i++) a[m + i] = a[i], pos[m + i] = pos[i] + M; int x = 1, bor = 0; for (int i = 1; i <= m * 2 - 1; i++) if (pos[i] == pos[i - 1] + 1) { x++; while (x > 2 && !between(d[a[i]], d[a[i - 1]], d[a[bor]])) bor++, x--; ans = max(ans, x); } else x = 1, bor = i; cout << min(m, ans) << endl; } |
#include <bits/stdc++.h> using namespace std; const long long MAX_N = 200 * 1000 + 24, INF = (1 << 30); int n; int a[MAX_N], cnt[MAX_N], mark[MAX_N]; vector<int> G[MAX_N], vec, avb; int main() { cin.tie(0), cout.tie(0), ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) cin >> a[i], a[i]--, cnt[a[i]]++; for (int i = 0; i < n; i++) if (cnt[i] == 0) vec.push_back(i); for (int i = 0; i < n; i++) { if (cnt[a[i]] > 1) { G[a[i]].push_back(i), avb.push_back(i); mark[a[i]] = true; } } memset(mark, 0, sizeof mark); int j = 0; for (int i = 0; i < avb.size(); i++) { int p = avb[i]; if (mark[a[p]] == false and (a[p] < vec[j] or p == G[a[p]][G[a[p]].size() - 1])) { mark[a[p]] = true; } else { a[p] = vec[j++]; } } cout << vec.size() << endl; for (int i = 0; i < n; i++) { cout << a[i] + 1 << ; } cout << endl; } |
module avr_interface(
input clk,
input rst,
input cclk,
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
output [3:0] spi_channel,
output tx,
input rx,
input [3:0] channel,
output new_sample,
output [9:0] sample,
output [3:0] sample_channel,
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
output [7:0] rx_data,
output new_rx_data
);
wire ready;
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire tx_m;
wire spi_miso_m;
reg byte_ct_d, byte_ct_q;
reg [9:0] sample_d, sample_q;
reg new_sample_d, new_sample_q;
reg [3:0] sample_channel_d, sample_channel_q;
cclk_detector cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(8'hff),
.dout(spi_dout)
);
serial_rx #(.CLK_PER_BIT(100), .CTR_SIZE(7)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(100), .CTR_SIZE(7)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
assign new_sample = new_sample_q;
assign sample = sample_q;
assign sample_channel = sample_channel_q;
assign spi_channel = ready ? channel : 4'bZZZZ;
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
always @(*) begin
byte_ct_d = byte_ct_q;
sample_d = sample_q;
new_sample_d = 1'b0;
sample_channel_d = sample_channel_q;
if (spi_ss) begin
byte_ct_d = 1'b0;
end
if (spi_done) begin
if (byte_ct_q == 1'b0) begin
sample_d[7:0] = spi_dout;
byte_ct_d = 1'b1;
end else begin
sample_d[9:8] = spi_dout[1:0];
sample_channel_d = spi_dout[7:4];
byte_ct_d = 1'b1;
new_sample_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (n_rdy) begin
byte_ct_q <= 1'b0;
sample_q <= 10'b0;
new_sample_q <= 1'b0;
end else begin
byte_ct_q <= byte_ct_d;
sample_q <= sample_d;
new_sample_q <= new_sample_d;
end
sample_channel_q <= sample_channel_d;
end
endmodule |
//////////////////////////////////////////////////////////////////
////
////
//// CRCAHB CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// crcahb IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module host_interface
(
//OUTPUTS
output [31:0] HRDATA,
output HREADYOUT,
output HRESP,
output [31:0] bus_wr,
output [ 1:0] crc_poly_size,
output [ 1:0] bus_size,
output [ 1:0] rev_in_type,
output rev_out_type,
output crc_init_en,
output crc_idr_en,
output crc_poly_en,
output buffer_write_en,
output reset_chain,
//INPUTS
input [31:0] HWDATA,
input [31:0] HADDR,
input [ 2:0] HSIZE,
input [ 1:0] HTRANS,
input HWRITE,
input HSElx,
input HREADY,
input HRESETn,
input HCLK,
input [31:0] crc_poly_out,
input [31:0] crc_out,
input [31:0] crc_init_out,
input [ 7:0] crc_idr_out,
input buffer_full,
input reset_pending,
input read_wait
);
//Reset Values
localparam RESET_CRC_CR = 6'h00;
//CRC Register Map
localparam CRC_DR = 3'h0;
localparam CRC_IDR = 3'h1;
localparam CRC_CR = 3'h2;
localparam CRC_INIT = 3'h4;
localparam CRC_POL = 3'h5;
//Transfer Type Encoding
localparam IDLE = 2'b00;
localparam BUSY = 2'b01;
localparam NON_SEQ = 2'b10;
localparam SEQ = 2'b11;
//HRESP Encoding
localparam OK = 1'b0;
localparam ERROR = 1'b1;
//Pipeline flops
reg [2:0] haddr_pp;
reg [2:0] hsize_pp;
reg [1:0] htrans_pp;
reg hwrite_pp;
reg hselx_pp;
//Flops
reg [4:0] crc_cr_ff;
//Internal Signals
wire [31:0] crc_cr_rd;
wire crc_dr_sel;
wire crc_init_sel;
wire crc_idr_sel;
wire crc_poly_sel;
wire crc_cr_sel;
wire ahb_enable;
wire write_en;
wire read_en;
wire crc_cr_en;
wire sample_bus;
wire buffer_read_en;
//Pipeline Registers for Address Phase of AHB Protocol
always @(posedge HCLK)
begin
if(!HRESETn)
begin
hselx_pp <= 1'b0;
end
else
if(sample_bus)
begin
haddr_pp <= HADDR[4:2];
hsize_pp <= HSIZE;
htrans_pp <= HTRANS;
hwrite_pp <= HWRITE;
hselx_pp <= HSElx;
end
end
//Enable Signals
assign ahb_enable = (htrans_pp == NON_SEQ);
assign write_en = hselx_pp && hwrite_pp && ahb_enable;
assign read_en = hselx_pp && !hwrite_pp && ahb_enable;
//Registers decoding
assign crc_dr_sel = (haddr_pp == CRC_DR );
assign crc_init_sel = (haddr_pp == CRC_INIT);
assign crc_idr_sel = (haddr_pp == CRC_IDR );
assign crc_poly_sel = (haddr_pp == CRC_POL );
assign crc_cr_sel = (haddr_pp == CRC_CR );
//Write Esnables Signals for Registers
assign buffer_write_en = crc_dr_sel && write_en;
assign crc_init_en = crc_init_sel && write_en;
assign crc_idr_en = crc_idr_sel && write_en;
assign crc_poly_en = crc_poly_sel && write_en;
assign crc_cr_en = crc_cr_sel && write_en;
//Indicates reading operation request to crc_dr register
assign buffer_read_en = crc_dr_sel && read_en;
//Bus Size is the output of HSIZE pipeline register
assign bus_size = hsize_pp;
//The Write Bus is not pipelined
assign bus_wr = HWDATA;
//HREADY Signal outputed to Master
assign HREADYOUT = !((buffer_write_en && buffer_full ) ||
(buffer_read_en && read_wait ) ||
(crc_init_en && reset_pending ) );
//Signal to control sampling of bus
assign sample_bus = HREADYOUT && HREADY;
//HRESP Signal outputed to Master
//This implementation never signalize bus error to master
assign HRESP = OK;
//CRC_CR Data Read
assign crc_cr_rd = {24'h0, crc_cr_ff[4:0], 3'h0};
//Mux to HRDATA
assign HRDATA = ({32{crc_dr_sel }} & crc_out ) |
({32{crc_init_sel}} & crc_init_out ) |
({32{crc_idr_sel }} & {24'h0, crc_idr_out}) |
({32{crc_poly_sel}} & crc_poly_out ) |
({32{crc_cr_sel }} & crc_cr_rd ) ;
//Control Register
always @(posedge HCLK)
begin
if(!HRESETn)
crc_cr_ff <= RESET_CRC_CR;
else
if(crc_cr_en)
crc_cr_ff <= {HWDATA[7], HWDATA[6:5], HWDATA[4:3]};
end
//Configuration Signals
assign reset_chain = (crc_cr_en && HWDATA[0]);
assign crc_poly_size = crc_cr_ff[1:0];
assign rev_in_type = crc_cr_ff[3:2];
assign rev_out_type = crc_cr_ff[4];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char c[100005]; scanf( %s , c); vector<char> v; int count[26]; int instk[26]; memset(count, 0, sizeof(count)); memset(instk, 0, sizeof(instk)); int find = 0; for (int i = 0; c[i] != 0; i++) count[c[i] - a ]++; while (count[find] == 0) find++; for (int i = 0; c[i] != 0; i++) { v.push_back(c[i]); count[c[i] - a ]--; while (count[find] == 0) find++; while (!v.empty() && v.back() - a <= find) { printf( %c , v.back()); v.pop_back(); } } while (!v.empty()) { printf( %c , v.back()); v.pop_back(); } } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemh function - comments in data file
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
$readmemh("ivltests/readmemh4.dat",array);
for(count = 0; count <= 7; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// USB CRC5 and CRC16 Modules ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_crc16.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_crc16.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.1.0.1 2001/02/28 08:10:42 rudi
// Initial Release
//
//
`include "usbf_defines.v"
///////////////////////////////////////////////////////////////////
//
// CRC16
//
///////////////////////////////////////////////////////////////////
module usbf_crc16(crc_in, din, crc_out);
input [15:0] crc_in;
input [7:0] din;
output [15:0] crc_out;
assign crc_out[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^
din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
crc_in[14] ^ crc_in[15];
assign crc_out[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^
crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15];
assign crc_out[2] = din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9];
assign crc_out[3] = din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10];
assign crc_out[4] = din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11];
assign crc_out[5] = din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12];
assign crc_out[6] = din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13];
assign crc_out[7] = din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14];
assign crc_out[8] = din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15];
assign crc_out[9] = din[7] ^ crc_in[1] ^ crc_in[15];
assign crc_out[10] = crc_in[2];
assign crc_out[11] = crc_in[3];
assign crc_out[12] = crc_in[4];
assign crc_out[13] = crc_in[5];
assign crc_out[14] = crc_in[6];
assign crc_out[15] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
crc_in[14] ^ crc_in[15];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; long long PRIME = 999727999; long long PRIME2 = 999999937; long long INF = LLONG_MAX / 4; template <class F1, class F2> ostream& operator<<(ostream& os, const pair<F1, F2>& p) { return os << p.first << << p.second; } template <class F1, class F2> istream& operator>>(istream& is, pair<F1, F2>& p) { return is >> p.first >> p.second; } template <class F> ostream& operator<<(ostream& os, const std::vector<F>& v) { for (int i = 0; i < (int)v.size(); i++) os << v[i] << ; return os; } template <class F> istream& operator>>(istream& is, std::vector<F>& v) { for (int i = 0; i < (int)v.size(); i++) is >> v[i]; return is; } vector<string> split(const std::string& s, char delim) { vector<string> e; stringstream ss(s); string item; while (getline(ss, item, delim)) e.push_back(item); return e; } long long Pow(long long a, long long b, long long Mo) { long long ans = 1; for (; b; b >>= 1, a = a * a % Mo) if (b & 1) ans = ans * a % Mo; return ans; } long long _div(long long a, long long b) { return (a * Pow(b, MOD - 2, MOD)) % MOD; } long long nCr(long long n, long long r) { static long long MAXF = 1e6; static std::vector<long long> fact(MAXF, 1); for (int i = 1; i < MAXF; ++i) fact[i] = (fact[i - 1] * i) % MOD; MAXF = 0; return (fact[n] * Pow((fact[r] * fact[n - r]) % MOD, MOD - 2, MOD)) % MOD; } vector<int> Zfunc(string& s) { int n = s.length(); vector<int> z(n, 0); for (int i = 1, l = 0, r = 0; i < n; i++) { if (i <= r) z[i] = min(z[i - l], r - i + 1); while (i + z[i] < n && s[i + z[i]] == s[z[i]]) z[i]++; if (r < i + z[i] - 1) l = i, r = i + z[i] - 1; } return z; } string s; int l; std::vector<std::vector<long long> > DP; long long getWaysAny(int c, int left) { if (c > left) return 0; return nCr(left, c); } long long getWays(int c, int takencare) { if (takencare == l) { if (c == 0) return 1; return 0; } long long& w = DP[c][takencare]; if (w != -1) return w; w = 0; if (s[takencare] == 1 ) { if (c > 0) w = (w + getWays(c - 1, takencare + 1)) % MOD; w = (w + getWaysAny(c, l - (takencare + 1))) % MOD; } else { w = (w + getWays(c, takencare + 1)) % MOD; } return w; } long long solve() { int k; cin >> s >> k; l = s.length(); if (k == 0) { return 1; } DP.resize(1002, std::vector<long long>(1002, -1)); if (k == 1) { return (getWays(1, 0) + MOD - 1) % MOD; } long long w = 0; for (int i = 2; i <= 1000; ++i) { long long needk = 0; long long i2 = i; while (i2 > 1) { i2 = __builtin_popcount(i2); needk++; } if (needk == k - 1) { w = (w + getWays(i, 0)) % MOD; } } return w; } int main(int argc, char const* argv[]) { std::ios::sync_with_stdio(false); cin.tie(0); cout << solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_21_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_21_V
/**
* sleep_pargate_plv: ????.
*
* Verilog wrapper for sleep_pargate_plv with size of 21 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_pargate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_21 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_21 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_21_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__AND2_BEHAVIORAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); long long ts, tf, t; cin >> ts >> tf >> t; int n; cin >> n; map<long long, int> T; for (int i = 0; i < n; ++i) { long long t; cin >> t; ++T[t]; } long long bt = 0, ans = ts + t; for (const auto &s : T) { if (ts + t > tf) break; if (ts < s.first) { bt = ts; break; } if (s.first > 0) { long long ta = s.first - 1; if (ts + t - ta < ans) { ans = ts + t - ta; bt = ta; } } ts += t * s.second; } if (ts + t <= tf) bt = ts; cout << bt << n ; return 0; } |
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____7.143______0.000______50.0______244.806____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct $ { $() { ios_base::sync_with_stdio(false); cin.tie(NULL); } } $; const int Maxn = 202005; class BIT { int *tree, sz; public: BIT() { sz = 202005; tree = new int[sz + 1]; } BIT(int N) { sz = N; tree = new int[N + 1]; } ~BIT() { delete[] tree; } void update(int idx, int Val) { if (idx < 1 || idx > sz) return; while (idx <= sz) { tree[idx] += Val; idx += idx & -idx; } } int read(int idx) { int Sum = 0; while (idx > 0) { Sum += tree[idx]; idx -= (idx & -idx); } return Sum; } int rangeSum(int l, int r) { int Ret = read(r) - read(l - 1); Ret = max(0, Ret); return Ret; } int readSingle(int idx) { int sum = tree[idx]; if (idx > 0) { int z = idx - (idx & -idx); idx--; while (idx != z) { sum -= tree[idx]; idx -= (idx & -idx); } } return sum; } }; int T1[Maxn], T2[Maxn]; int main() { int n, k, a, b, q, type, d, val; cin >> n >> k >> a >> b >> q; BIT B1, B2; while (q--) { cin >> type; if (type == 1) { cin >> d >> val; if (T1[d] < a) { int temp = min(val, a - T1[d]); T1[d] += temp; B1.update(d, temp); } if (T2[d] < b) { int temp = min(val, b - T2[d]); T2[d] += temp; B2.update(d, temp); } } else { cin >> d; int Ans = 0; Ans = B2.rangeSum(1, d - 1); int z = B1.rangeSum(min(d + k, Maxn - 1), Maxn - 1); Ans += z; cout << Ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, m, i, x, p = 0, kk = 100000000000000000, sum = 0; cin >> n >> k >> m; string me[n]; map<string, long long> fahim; for (i = 0; i < n; i++) { cin >> me[i]; } for (i = 0; i < n; i++) { cin >> fahim[me[i]]; } for (i = 0; i < k; i++) { cin >> x; if (x == 1) { cin >> x; continue; } if (x != 1) { long long d[x]; for (p = 0; p < x; p++) { cin >> d[p]; kk = min(kk, fahim[me[d[p] - 1]]); } for (p = 0; p < x; p++) { fahim[me[d[p] - 1]] = kk; } } kk = 100000000000000000; } string word; for (i = 0; i < m; i++) { cin >> word; sum += fahim[word]; } cout << sum; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O32A_BEHAVIORAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B1 or0_out ;
wire B1 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000007; const long long INFLL = 1000000000000000007; const long long MOD = 998244353; bool comp(long long a, long long b) { return a > b; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, k; cin >> n >> k; vector<long long> v; for (int i = 0; i < n; i++) { long long x; cin >> x; v.push_back(x); } long long ans = 0, ans1 = 1, licz = -INFLL; for (int i = 0; i < n; i++) { if (v[i] <= n - k) licz++; else { if (licz > 0) ans1 *= (licz + 1); ans1 %= MOD; ans += v[i]; licz = 0; } } cout << ans << << ans1; return 0; } |
#include <bits/stdc++.h> using namespace std; using ui32 = unsigned int; using i64 = long long; using f64 = long double; using ui64 = unsigned long long; void read(int& x) { scanf( %d , &x); } void read(int n, vector<int>& a) { for (int i = 0; i < n; i++) read(a[i]); } void read(int n, int* a) { for (int i = 0; i < n; i++) read(a[i]); } void write(int x) { printf( %d n , x); } void print(int x) { printf( %d , x); } void write(int n, vector<int> a) { for (int i = 0; i < n; i++) printf( %d n , a[i]); } void print(int n, int* a) { for (int i = 0; i < n; i++) printf( %d , a[i]); } void print(string s) { printf( %s n , s.c_str()); } i64 z[3 * 100007], lcp[3 * 100007], cnt[3 * 100007]; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s, t; cin >> s >> t; string concate = t + # + s; i64 n = (i64)(concate.size()), m = (i64)(t.size()); i64 l = 0; i64 r = 0; for (i64 i = 0; i < n; i++) { if (i > r) { l = i; r = i; while (r < n && concate[r - l] == concate[r]) { r++; } z[i] = r - l; r--; } else { i64 k = i - l; if (z[k] < r - i + 1) z[i] = z[k]; else { l = i; while (r < n && concate[r - l] == concate[r]) { r++; } z[i] = r - l; r--; } } } n = (i64)(s.size()); for (i64 i = m + 2; i < n + m + 1; i++) { cnt[z[i]]++; } for (i64 i = m; i > 0; i--) { cnt[i - 1] += cnt[i]; } l = 0; r = 1; while (r != m) { if (t[l] == t[r]) { l++; lcp[r] = l; r++; } else { if (l == 0) { lcp[r] = 0; r++; } else { l = lcp[l - 1]; } } } i64 ans = n * m; for (i64 i = 0; i < m; i++) { if (lcp[i] != 0) { ans -= cnt[i + 1 - lcp[i]]; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; vector<vector<int> > col; vector<vector<int> > adj; int color[N]; void dfs(int v, int p) { set<int> st; int toapply = 1; for (int i = 0; i < col[v].size(); i++) { int c = col[v][i]; if (color[c] != -1) st.insert(color[c]); } for (int i = 0; i < col[v].size(); i++) { int c = col[v][i]; if (color[c] != -1) continue; while (st.find(toapply) != st.end()) toapply++; color[c] = toapply; toapply++; } for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (u == p) continue; dfs(u, v); } } int main() { int n, m; scanf( %d%d , &n, &m); col.resize(n + 5); adj.resize(n + 5); memset(color, -1, sizeof(color)); int mx = 1; for (int i = 1; i <= n; i++) { int s; scanf( %d , &s); mx = max(mx, s); while (s--) { int t; scanf( %d , &t); col[i].push_back(t); } } for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } dfs(1, -1); printf( %d n , mx); for (int i = 1; i <= m; i++) if (color[i] == -1) color[i] = 1; for (int i = 1; i <= m; i++) printf( %d , color[i]); printf( n ); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; const long double pi = acos(-1); const long long int mod = 1e9 + 7; bool debug = false; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int t = 1, n, i, j, k, len, x, y, z, c, f, flag, p, q, mx, mn, l, r, sum, ans, tmp, it, pos, avg, m, cnt; string s; char ch; vector<long long int> v; vector<pair<long long int, long long int>> vec; unordered_map<long long int, long long int> mappu; pair<long long int, long long int> pr; { f = 0; sum = 0; flag = 0; ans = 0; cnt = 0; v.clear(); mappu.clear(); vec.clear(); string s2; cin >> s >> s2; if (s == s2) cout << s; else cout << 1; } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9625_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// adc interface
input adc_clk;
input adc_rst;
input [191:0] adc_data;
input adc_or;
// channel interface
output [255:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9625_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
genvar n;
generate
for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> m; map<long long, long long>::iterator it; long long ans[200500]; int main() { long long n, i, x, y, pr = -1, cur = 0; cin >> n; for (i = 0; i < n; i++) { cin >> x >> y; m[x]++; m[y + 1]--; } for (it = m.begin(); it != m.end(); it++) { if (it->second < 0) { ans[cur] += (it->first - pr); } else { if (cur != 0) { ans[cur] += (it->first - pr); } } cur += it->second; pr = it->first; } for (i = 1; i <= n; i++) { cout << ans[i] << ; } } |
#include <bits/stdc++.h> using namespace std; map<string, int> M; int eval(string s) { int c1 = 0, c2 = 0; string t; int indl = 0; while (indl < s.size() && s[indl] == & ) ++indl, ++c1; int ind2 = s.size() - 1; while (ind2 >= 0 && s[ind2] == * ) --ind2, ++c2; t = s.substr(indl, ind2 - indl + 1); if (!M.count(t)) return -1; int x = M[t]; if (x == -1) return -1; x += c2; x -= c1; if (x < 0) return -1; return x; } int main() { int n; cin >> n; M[ void ] = 0; for (int i = 0; i < n; ++i) { string ws; cin >> ws; if (ws == typeof ) { string s; cin >> s; int x = eval(s); if (x == -1) printf( errtype n ); else { printf( void ); for (int j = 0; j < x; ++j) printf( * ); printf( n ); } } else { string s, t; cin >> s >> t; M[t] = eval(s); } } return 0; } |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Last modified date: 04/08 '13
* Last modified by: Ye-sheng Kuo <>
* Last modified content: add external interrupt
* --------------------------------------------------------------------------
* IMPORTANT:
* --------------------------------------------------------------------------
* */
`timescale 1ns/1ps
`include "include/mbus_def.v"
module mbus_wire_ctrl(
input RESETn,
input DIN,
input CLKIN,
input DOUT_FROM_BUS,
input CLKOUT_FROM_BUS,
input RELEASE_ISO_FROM_SLEEP_CTRL,
output reg DOUT,
output reg CLKOUT,
input EXTERNAL_INT,
input MASTER_NODE
);
always @ *
begin
if( !RESETn )
CLKOUT <= #1 1'b1;
else if (RELEASE_ISO_FROM_SLEEP_CTRL==`IO_HOLD)
begin
if (MASTER_NODE==1'b1)
CLKOUT <= 1'b1;
else
CLKOUT <= #1 CLKIN;
end
else
CLKOUT <= #1 CLKOUT_FROM_BUS;
if ( !RESETn )
DOUT <= #1 1'b1;
else if (EXTERNAL_INT)
begin
DOUT <= #1 0;
end
else
begin
if (RELEASE_ISO_FROM_SLEEP_CTRL==`IO_HOLD)
begin
if (MASTER_NODE==1'b1)
DOUT <= #1 1'b1;
else
DOUT <= #1 DIN;
end
else
begin
DOUT <= #1 DOUT_FROM_BUS;
end
end
end
endmodule // mbus_wire_ctrl_wresetn
|
module join_fadd(
input clk,
input reset,
input [7:0] inp_a,
input inp_aValid,
output inp_aRetry,
input [7:0] inp_b,
input inp_bValid,
output inp_bRetry,
output [7:0] sum,
output sumValid,
input sumRetry
);
logic [7:0] sum_next;
always_comb begin
sum_next = inp_a + inp_b;
end
logic inpValid;
logic inpRetry;
always_comb begin
inpValid = inp_aValid && inp_bValid;
end
always_comb begin
`ifdef LAZY_OPTION
inp_bRetry = inpRetry || !inpValid;
inp_aRetry = inpRetry || !inpValid;
`else
inp_bRetry = inpRetry || (!inpValid && inp_bValid);
inp_aRetry = inpRetry || (!inpValid && inp_aValid);
//inp_bRetry = inpRetry || (!inpValid && inp_bValid) || (!inpValid && inp_aValid);
//inp_aRetry = inpRetry || (!inpValid && (inp_bValid || inp_aValid));
`endif
end
logic [7:0] sum2;
logic sum2Valid;
logic sum2Retry;
fflop #(.Size(8)) f1 (
.clk (clk),
.reset (reset),
.din (sum_next),
.dinValid (inpValid),
.dinRetry (inpRetry),
.q (sum2),
.qValid (sum2Valid),
.qRetry (sum2Retry)
);
fflop #(.Size(8)) f2 (
.clk (clk),
.reset (reset),
.din (sum2),
.dinValid (sum2Valid),
.dinRetry (sum2Retry),
.q (sum),
.qValid (sumValid),
.qRetry (sumRetry)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_V |
/*
* Super Simple Priority Interrupt Controller
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
* Copyright (C) 2010 Donna Polehn <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module simple_pic (
input clk,
input rst,
input [7:0] intv,
input inta,
output intr,
output reg [2:0] iid
);
// Registers
reg [7:0] irr;
reg inta_r;
reg int3_r;
reg int4_r;
// Continuous assignments, note that only IRQs 0,1,3 & 4 are driven atm
assign intr = irr[4] | irr[3] | irr[1] | irr[0];
// Behaviour of inta_r
always @(posedge clk) inta_r <= inta;
// irr
always @(posedge clk)
irr[0] <= rst ? 1'b0 : (intv[0] | irr[0] & !(iid == 3'b000 && inta_r && !inta));
always @(posedge clk)
irr[1] <= rst ? 1'b0 : (intv[1] | irr[1] & !(iid == 3'b001 && inta_r && !inta));
always @(posedge clk)
irr[3] <= rst ? 1'b0 : ((intv[3] && !int3_r) | irr[3] & !(iid == 3'b011 && inta_r && !inta));
always @(posedge clk) int3_r <= rst ? 1'b0 : intv[3]; // int3_r
always @(posedge clk)
irr[4] <= rst ? 1'b0 : ((intv[4] && !int4_r) | irr[4] & !(iid == 3'b100 && inta_r && !inta));
always @(posedge clk) int4_r <= rst ? 1'b0 : intv[4]; // int4_r
always @(posedge clk) // iid
iid <= rst ? 3'b0 : (inta ? iid :
(irr[0] ? 3'b000 :
(irr[1] ? 3'b001 :
(irr[3] ? 3'b011 :
(irr[4] ? 3'b100 :
3'b000
)))));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e3 + 10; int n, m, c = 0, ans = 0; vector<int> adj[maxn], bkadj[maxn], components, nodes[maxn], sink; bool mark[maxn]; int cmp[maxn], d[maxn], o[maxn]; stack<int> st; queue<int> q; void input() { cin >> n >> m; for (int i = 0; i < m; i++) { int fi, se; cin >> fi >> se; adj[fi].push_back(se); bkadj[se].push_back(fi); } } void dfs1(int x) { mark[x]++; for (int i = 0; i < adj[x].size(); i++) { int child = adj[x][i]; if (!mark[child]) dfs1(child); } st.push(x); } void dfs2(int x) { mark[x]++; nodes[cmp[x]].push_back(x); for (int i = 0; i < bkadj[x].size(); i++) { int child = bkadj[x][i]; if (!mark[child]) { cmp[child] = cmp[x]; dfs2(child); } else if (cmp[child] != cmp[x]) o[cmp[child]]++; } } int bfs(int x) { memset(mark, 0, sizeof mark); q.push(x); d[x] = 1; mark[x]++; int mi = 1e8; while (!q.empty()) { int cur = q.front(); q.pop(); for (int i = 0; i < adj[cur].size(); i++) { int child = adj[cur][i]; if (!mark[child]) { mark[child]++; d[child] = d[cur] + 1; q.push(child); } else if (child == x) mi = min(mi, d[cur]); } } return mi; } void task() { for (int i = 1; i <= n; i++) if (!mark[i]) dfs1(i); memset(mark, 0, sizeof mark); while (!st.empty()) { int x = st.top(); st.pop(); if (!mark[x]) cmp[x] = x, components.push_back(x), dfs2(x); } for (int i = 0; i < components.size(); i++) if (o[components[i]] == 0) sink.push_back(components[i]); for (int i = 0; i < sink.size(); i++) { int cm = sink[i]; if (nodes[cm].size() != 1) { c++; int mi = 1e8; for (int i = 0; i < nodes[cm].size(); i++) { int cur = nodes[cm][i]; mi = min(mi, bfs(cur)); } ans += mi; } } } void debug() { for (int i = 1; i <= n; i++) cerr << i << : << cmp[i] << endl; } int main() { input(); task(); cout << n + (ans * 998) + c << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; pair<pair<int, int>, int> a[100010]; vector<pair<long long, int> > pre[100010]; long long maxx = 0; int maxi, maxj; int c = 0; long long s = 0; long long val1, val2; void eval(int i, int j, int k, bool f) { val2 = pre[j][k].first; if (val1 + val2 > maxx) { maxx = val1 + val2; maxi = pre[i][pre[i].size() - 1].second; maxj = pre[j][k].second; if (f) swap(maxi, maxj); } } vector<int> out; int main() { int n, i; scanf( %d , &n); for (i = 0; i < n; ++i) { scanf( %d , &a[i].first.first); scanf( %d , &a[i].first.second); a[i].first.second = -a[i].first.second; a[i].second = i; } sort(a, a + n); s = -a[0].first.second; c++; pre[c].push_back(make_pair(s, 0)); for (i = 1; i < n; ++i) { if (a[i].first.first == a[i - 1].first.first) { s -= a[i].first.second; c++; } else { s = -a[i].first.second; c = 1; } pre[c].push_back(make_pair(s, i)); } for (i = 1; i < 100010; ++i) { if (pre[i].size() == 0) break; sort(pre[i].begin(), pre[i].end()); } for (i = 1; i < 100010; ++i) { if (pre[i].size() == 0) break; val1 = pre[i][pre[i].size() - 1].first; if (i > 1) { if (pre[i - 1].size()) { if (a[pre[i - 1][pre[i - 1].size() - 1].second].first.first != a[pre[i][pre[i].size() - 1].second].first.first) eval(i, i - 1, pre[i - 1].size() - 1, 0); else if (pre[i - 1].size() > 1) eval(i, i - 1, pre[i - 1].size() - 2, 0); } } if (pre[i].size() > 1) eval(i, i, pre[i].size() - 2, 0); if (pre[i + 1].size()) { if (a[pre[i + 1][pre[i + 1].size() - 1].second].first.first != a[pre[i][pre[i].size() - 1].second].first.first) eval(i, i + 1, pre[i + 1].size() - 1, 1); else if (pre[i + 1].size() > 1) eval(i, i + 1, pre[i + 1].size() - 2, 1); } } while (maxj) { if (a[maxj - 1].first.first != a[maxj].first.first) break; out.push_back(a[maxi].second + 1); out.push_back(a[maxj].second + 1); --maxi; --maxj; } out.push_back(a[maxi].second + 1); out.push_back(a[maxj].second + 1); if (maxi) { if (a[maxi - 1].first.first == a[maxi].first.first) out.push_back(a[maxi - 1].second + 1); } printf( %lld n%d n , maxx, (int)out.size()); for (i = 0; i < out.size(); ++i) printf( %d , out[i]); } |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : DCM2.v
// /___/ /\ Timestamp : 07/09/2015 13:18:59
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle H:/Firmware/font5_base_new/font5_base/font5-firmware/ipcore_dir/DCM2.xaw -st DCM2.v
//Design Name: DCM2
//Device: xc5vlx50t-3ff1136
//
// Module DCM2
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_ADV_INST = 0.055 UI
// Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.152 ns
`timescale 1ns / 1ps
module DCM2(CLKIN_IN,
RST_IN,
CLKFX_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKFX_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLK0_BUF;
wire GND_BIT;
wire [6:0] GND_BUS_7;
wire [15:0] GND_BUS_16;
assign GND_BIT = 0;
assign GND_BUS_7 = 7'b0000000;
assign GND_BUS_16 = 16'b0000000000000000;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(9), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(25.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DCM_AUTOCALIBRATION("TRUE"), .DCM_PERFORMANCE_MODE("MAX_SPEED"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IN),
.DADDR(GND_BUS_7[6:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.DO(),
.DRDY(),
.LOCKED(LOCKED_OUT),
.PSDONE());
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2) cout << contest ; else cout << home ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_TB_V
`define SKY130_FD_SC_HD__AND2B_TB_V
/**
* and2b: 2-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_hd__and2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_TB_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) f = ch == - ? -1 : 1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 48, ch = getchar(); return x * f; } const int maxn = 205; int tot; int R, G, B; int r[maxn]; int g[maxn]; int b[maxn]; int f[maxn][maxn][maxn]; struct Stick { int v, c; } a[maxn << 3]; inline bool cmp(int u, int v) { return u > v; } int main() { R = read(), G = read(), B = read(); for (int i = (1); i <= (R); i++) r[i] = read(); for (int i = (1); i <= (G); i++) g[i] = read(); for (int i = (1); i <= (B); i++) b[i] = read(); sort(r + 1, r + R + 1, cmp), sort(g + 1, g + G + 1, cmp), sort(b + 1, b + B + 1, cmp); f[1][1][0] = r[1] * g[1]; f[1][0][1] = r[1] * b[1]; f[0][1][1] = g[1] * b[1]; int ans = 0; for (int i = (0); i <= (R); i++) for (int j = (0); j <= (G); j++) for (int k = (0); k <= (B); k++) { if (i && j) f[i][j][k] = max(f[i][j][k], f[i - 1][j - 1][k] + r[i] * g[j]); if (i && k) f[i][j][k] = max(f[i][j][k], f[i - 1][j][k - 1] + r[i] * b[k]); if (j && k) f[i][j][k] = max(f[i][j][k], f[i][j - 1][k - 1] + g[j] * b[k]); ans = max(ans, f[i][j][k]); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 200005; int n, m, tot, ans; struct Node { int u, v, w; } node[M]; int vis[M], match[M]; int sum1[M], sum2[M]; int head[M], Nxt[M], ver[M]; bool v[M], flag = 0; vector<int> e[M]; inline bool dfs(long long x) { for (int i = 0; i < e[x].size(); i++) { long long y = e[x][i]; if (!vis[y]) { vis[y] = 1; if (!match[y] || dfs(match[y])) { match[y] = x; return 1; } } } return 0; } bool cmp(Node a, Node b) { return a.w > b.w; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &node[i].u, &node[i].v, &node[i].w); sum1[node[i].u]++; sum2[node[i].v]++; e[node[i].u].push_back(node[i].v); } for (int i = 1; i <= n; i++) { memset(vis, 0, sizeof(vis)); if (dfs(i)) ans++; } if (ans != n) { printf( -1 n ); return 0; } sort(node + 1, node + 1 + m, cmp); for (int i = 1; i <= m; i++) { sum1[node[i].u]--; sum2[node[i].v]--; if (sum1[node[i].u] == 0 || sum2[node[i].v] == 0) { printf( %d n , node[i].w); return 0; } } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module splitter (
input clk,
input resetn,
input s_valid,
output s_ready,
output [C_NUM_M-1:0] m_valid,
input [C_NUM_M-1:0] m_ready
);
parameter C_NUM_M = 2;
reg [C_NUM_M-1:0] acked;
assign s_ready = &(m_ready | acked);
assign m_valid = s_valid ? ~acked : {C_NUM_M{1'b0}};
always @(posedge clk)
begin
if (resetn == 1'b0) begin
acked <= {C_NUM_M{1'b0}};
end else begin
if (s_valid & s_ready)
acked <= {C_NUM_M{1'b0}};
else
acked <= acked | (m_ready & m_valid);
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_on GENCLK
reg [31:0] long;
reg [63:0] quad;
wire [31:0] longout;
wire [63:0] quadout;
wire [7:0] narrow = long[7:0];
sub sub (/*AUTOINST*/
// Outputs
.longout (longout[31:0]),
.quadout (quadout[63:0]),
// Inputs
.narrow (narrow[7:0]),
.quad (quad[63:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
long <= 32'h12345678;
quad <= 64'h12345678_abcdef12;
end
if (cyc==2) begin
if (longout !== 32'h79) $stop;
if (quadout !== 64'h12345678_abcdef13) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
// verilator public_module
`ifdef verilator
assign longout = $c32("(", narrow, "+1)");
assign quadout = $c64("(", quad, "+1)");
`else
assign longout = narrow + 8'd1;
assign quadout = quad + 64'd1;
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O31AI_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o31ai (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_BLACKBOX_V
|
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