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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> tab(n); for (int i = 0; i < n; i++) cin >> tab[i]; for (int i = 0; i < n; i++) { if (tab[i] % 2 == 0) continue; else { if (i == (n - 1) || tab[i + 1] == 0) { cout << NO ; return 0; } else tab[i + 1] -= 1; } } cout << YES ; return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Data_Mem.v when simulating
// the core, Data_Mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Data_Mem(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("Data_Mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[1010], y[1010], cnt, _cnt; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) scanf( %d %d , &x[i], &y[i]); while (true) { int cnt = 0; for (int i = 1; i <= n; i++) if ((x[i] + y[i]) & 1 == 1) cnt++; if (cnt >= 1 && cnt <= n - 1) { cout << cnt << endl; for (int i = 1; i <= n; i++) if ((x[i] + y[i]) & 1 == 1) printf( %d , i); return 0; } if (cnt == n) { for (int i = 1; i <= n; i++) x[i]--; } for (int i = 1; i <= n; i++) { cnt = (x[i] - y[i]) / 2; _cnt = (x[i] + y[i]) / 2; x[i] = cnt; y[i] = _cnt; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, k; cin >> n >> k; vector<pair<int, int>> a(n * 2); vector<pair<int, int>> ans; for (int i = 0; i < n; i++) { cin >> a[i].first >> a[n + i].first; a[n + i].second = 1; } sort(a.begin(), a.end()); int z = 0; for (int i = 0; i < n * 2; i++) if (a[i].second == 0) { z++; if (z == k) ans.push_back({a[i].first, 0}); } else { if (z == k) ans.back().second = a[i].first; z--; } cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) cout << ans[i].first << << ans[i].second << n ; return 0; } |
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_simulate.v"
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "util.v"
module fpga(
spck, miso, mosi, ncs,
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
mux_lo, mux_hi,
dbg
);
input spck, mosi, ncs;
output miso;
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output mux_lo, mux_hi;
output dbg;
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0];
4'b0010: divisor <= shift_reg[7:0];
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the low-frequency configuration:
wire lo_is_125khz;
assign lo_is_125khz = conf_word[3];
assign mux_hi = (!major_mode[2] && major_mode[1]) || (major_mode[2] && !major_mode[1]);
assign mux_lo = ~mux_hi;
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation;
assign hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848;
assign hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop;
assign hi_read_rx_xcorr_snoop = conf_word[1];
// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
wire hi_read_rx_xcorr_quarter;
assign hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
lo_read lr(
pck0, ck_1356meg, ck_1356megb,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
cross_hi, cross_lo,
lr_dbg,
lo_is_125khz, divisor
);
lo_passthru lp(
pck0, ck_1356meg, ck_1356megb,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
adc_d, lp_adc_clk,
lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
cross_hi, cross_lo,
lp_dbg, divisor
);
lo_simulate ls(
pck0, ck_1356meg, ck_1356megb,
ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
adc_d, ls_adc_clk,
ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
cross_hi, cross_lo,
ls_dbg, divisor
);
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF simulated tag (generic)
// 010 -- HF reader, transmitting to tag; modulation depth selectable
// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 100 -- HF simulated tag
// 101 -- HF ISO14443-A
// 110 -- LF passthrough
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
//module for forwarding the arithmetic instructions and preventing data hazards
module forwarding_unit
(
rf_waddr_exmem,
rf_waddr_memwb,
inst_curr_IDEX_7_4_rs,
inst_curr_IDEX_3_0_rt,
inst_curr_IDEX_11_8_rd,
rf_wen_exmem,
rf_wen_memwb,
mem2reg_memwb,
mem2reg_exmem,
dmem_wen_idex,
forwardA,
forwardB,
rdata2_sw_fcontrol,
);
input [3:0] rf_waddr_exmem;
input [3:0] rf_waddr_memwb;
input [3:0] inst_curr_IDEX_7_4_rs;
input [3:0] inst_curr_IDEX_3_0_rt;
input [3:0] inst_curr_IDEX_11_8_rd;
input rf_wen_exmem;
input rf_wen_memwb;
input mem2reg_memwb;
input mem2reg_exmem;
input dmem_wen_idex;
output [1:0] forwardA;
output [1:0] forwardB;
output [1:0] rdata2_sw_fcontrol;
//just doing it for basic arithmetic data hazards at the moment
/*assign forwardA = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_7_4_rs) && mem2reg_exmem===1'b1)? 2'b10 :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_7_4_rs))
&& (rf_waddr_memwb === inst_curr_IDEX_7_4_rs)
&& (mem2reg_memwb === 1'b1)) ? 2'b01 : 2'b00);
assign forwardB = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_3_0_rt) && mem2reg_exmem===1'b1)? 2'b10 :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_3_0_rt))
&& (rf_waddr_memwb === inst_curr_IDEX_3_0_rt)
&& (mem2reg_memwb === 1'b1)) ? 2'b01 : 2'b00);*/
assign forwardA = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_7_4_rs))? ((mem2reg_exmem!==1'b1)? 2'b10 : 2'b00) :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_7_4_rs))
&& (rf_waddr_memwb === inst_curr_IDEX_7_4_rs)
) ? ((mem2reg_memwb!==1'b1)? 2'b01: 2'b00) : 2'b00);
assign forwardB = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_3_0_rt))? ((mem2reg_exmem!==1'b1)? 2'b10 : 2'b00) :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_3_0_rt))
&& (rf_waddr_memwb === inst_curr_IDEX_3_0_rt)
) ? ((mem2reg_memwb!==1'b1)? 2'b01: 2'b00) : 2'b00);
//data forwarding for store instruction
assign rdata2_sw_fcontrol = ((dmem_wen_idex === 1'b0) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_11_8_rd)) ? ((mem2reg_exmem!==1'b1)? 2'b10: 2'b00) :
(((dmem_wen_idex === 1'b0) && (!(rf_waddr_memwb === 4'b0000))
&& (rf_waddr_memwb === inst_curr_IDEX_11_8_rd)) ? ((mem2reg_memwb!==1'b1)? 2'b01 : 2'b00) : 2'b00);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, n, m, a, b, s = 0, e1, e2, o1, o2; long long t; cin >> t; while (t--) { e1 = e2 = o1 = o2 = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a; if (a & 1) o1++; else e1++; } cin >> m; for (int i = 0; i < m; i++) { cin >> b; if (b & 1) o2++; else e2++; } cout << o1 * o2 + e1 * e2 << endl; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:45:24 07/28/2013
// Design Name:
// Module Name: UARTDemux
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//This is a 1 to 4 demux circuit of data width = 1
//The TX and RX lanes will each have one of these module instances
module BBot_UartSmartMux(
input clock,
input reset_l,
input [2:0] selectRoute,
input [N-1:0] tx3_in, tx2_in, tx1_in, tx0_in,
output reg [N-1:0] rx3_out, rx2_out, rx1_out, rx0_out
);
//Signal set 0 is XBee
//Signal set 1 is BBone
//Signal set 2 is Text to Speach Module
//Signal set 3 is undefined
//Set Width to one - this could be set to any width but
//we we only have 1 wire for TX signals (in) and 1 wire for RX signals (out)
//Code demonstrates a configurable data width for the inputs and outputs of the
//module but it's not really needed here...
parameter N = 1;
always @(posedge clock) begin
if (reset_l == 1'b0)
begin
rx3_out <= {N{1'b0}};
rx2_out <= {N{1'b0}};
rx1_out <= {N{1'b0}};
rx0_out <= {N{1'b0}};
end
else
begin
//Not using the 3'rd bit yet... use X for "don't care"
if (selectRoute == 3'bX11)
begin
//Not defined
end
if (selectRoute == 3'bX10)
begin
//Not defined
end
if (selectRoute == 3'bX01)
begin
//BBone is TX maser, voice module is slave (receiver)
rx2_out <= tx1_in;
rx1_out <= tx2_in;
end
else
begin
rx3_out <= {N{1'b0}};
rx0_out <= {N{1'b0}};
end
if (selectRoute == 3'bX00)
begin
//XBee signals are TX master, BBone is slave (RX receiver)
rx1_out <= tx0_in;
rx0_out <= tx1_in;
end
else
begin
//All other output nets not involved are asserted to 0
rx3_out <= {N{1'b0}};
rx2_out <= {N{1'b0}};
end
end
end
endmodule |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) const int nmax = 3e5 + 1; using namespace std; struct node { int ind; int cur; node() {} node(int cur, int ind) : cur(cur), ind(ind){}; }; node bolshe(node a, node b) { return (a.cur == b.cur ? (a.ind > b.ind ? a : b) : (a.cur > b.cur ? a : b)); } struct vertex { vertex *l; vertex *r; int sum; vertex(){}; vertex(int sum) : l(nullptr), r(nullptr), sum(sum){}; vertex(vertex *l, vertex *r) : l(l), r(r), sum(0) { if (l != nullptr) sum += l->sum; if (r != nullptr) sum += r->sum; }; }; struct segment_tree { node tr[nmax * 5]; int add[nmax * 5]; void build(vector<int> &a, int v, int cl, int cr) { if (cl == cr) { if (a[cl] > (cl + 1)) tr[v].cur = -1e9; else tr[v].cur = a[cl] - (cl + 1); tr[v].ind = cl; return; } int mid = (cl + cr) / 2; build(a, v * 2, cl, mid); build(a, v * 2 + 1, mid + 1, cr); tr[v] = bolshe(tr[v * 2], tr[v * 2 + 1]); } void push(int v) { add[v * 2] += add[v]; add[v * 2 + 1] += add[v]; tr[v].cur += add[v]; add[v] = 0; return; } void increase(int v, int cl, int cr, int left, int right) { if (left > right) return; if (cl == left && cr == right) { add[v] += 1; return; } push(v); int mid = (cl + cr) / 2; increase(v * 2, cl, mid, left, min(right, mid)); increase(v * 2 + 1, mid + 1, cr, max(left, mid + 1), right); tr[v] = bolshe(node(tr[v * 2].cur + add[v * 2], tr[v * 2].ind), node(tr[v * 2 + 1].cur + add[v * 2 + 1], tr[v * 2 + 1].ind)); } void decrease(int v, int cl, int cr, int left, int right, int x) { if (left > right) return; if (cl == left && cr == right) { add[v] -= x; return; } push(v); int mid = (cl + cr) / 2; decrease(v * 2, cl, mid, left, min(right, mid), x); decrease(v * 2 + 1, mid + 1, cr, max(left, mid + 1), right, x); tr[v] = bolshe(node(tr[v * 2].cur + add[v * 2], tr[v * 2].ind), node(tr[v * 2 + 1].cur + add[v * 2 + 1], tr[v * 2 + 1].ind)); } node find_max(int v, int cl, int cr, int left, int right) { if (left > right) return node(-1e9, 1e9); if (cl == left && cr == right) return node(tr[v].cur + add[v], tr[v].ind); push(v); int mid = (cl + cr) / 2; return bolshe(find_max(v * 2, cl, mid, left, min(right, mid)), find_max(v * 2 + 1, mid + 1, cr, max(left, mid + 1), right)); } }; segment_tree sg; struct segment_tree_2 { int tr[(int)(nmax * 5)]; void push(int v) { if (tr[v] != -1) tr[v * 2] = tr[v * 2 + 1] = tr[v], tr[v] = -1; } void update(int v, int cl, int cr, int left, int right, int x) { if (left > right) return; if (cl == left && cr == right) { tr[v] = x; return; } push(v); int mid = (cl + cr) / 2; update(v * 2, cl, mid, left, min(right, mid), x); update(v * 2 + 1, mid + 1, cr, max(left, mid + 1), right, x); } int get_number(int v, int cl, int cr, int pos) { if (cl == cr) return tr[v]; push(v); int mid = (cl + cr) / 2; if (pos <= mid) return get_number(v * 2, cl, mid, pos); else return get_number(v * 2 + 1, mid + 1, cr, pos); } }; segment_tree_2 sg2; struct segment_tree_3 { vector<int> tr[nmax * 5]; void build(vector<int> &a, int v, int cl, int cr) { if (cl == cr) { tr[v].push_back(a[cl]); return; } int mid = (cl + cr) / 2; build(a, v * 2, cl, mid); build(a, v * 2 + 1, mid + 1, cr); merge(tr[v * 2].begin(), tr[v * 2].end(), tr[v * 2 + 1].begin(), tr[v * 2 + 1].end(), back_inserter(tr[v])); } int get(int v, int cl, int cr, int left, int right, int x) { if (left > right) return 0; if (cl == left && cr == right) { int cur = lower_bound(tr[v].begin(), tr[v].end(), x) - tr[v].begin(); return tr[v].size() - cur; } int mid = (cl + cr) / 2; return get(v * 2, cl, mid, left, min(right, mid), x) + get(v * 2 + 1, mid + 1, cr, max(left, mid + 1), right, x); } }; segment_tree_3 sg3; int32_t main() { int n, m; cin >> n >> m; vector<int> a(n); for (int i = 0; i < n; i += 1) cin >> a[i]; sg.build(a, 1, 0, n - 1); sg2.update(1, 0, n - 1, 0, n - 1, 1e9); vector<int> pr; int lst = -1; vector<int> need(n, -1e9); while (1) { node found = sg.find_max(1, 0, n - 1, 0, n - 1); if (found.ind > n) break; if (found.cur != 0) break; int wow = sg2.get_number(1, 0, n - 1, found.ind); if (wow == 1e9) need[found.ind] = wow; else if (need[wow] == 1e9) need[found.ind] = wow; else need[found.ind] = need[wow]; pr.push_back(found.ind); sg.increase(1, 0, n - 1, found.ind + 1, n - 1); sg.decrease(1, 0, n - 1, found.ind, found.ind, 1e9); sg2.update(1, 0, n - 1, found.ind + 1, n - 1, found.ind); } sg3.build(need, 1, 0, n - 1); for (int i = 0; i < m; i += 1) { int l, r; cin >> l >> r; r = n - 1 - r; cout << sg3.get(1, 0, n - 1, l, r, l) << n ; } } |
#include <bits/stdc++.h> using namespace std; const int MX = 2020; const int MOD = 1e9 + 7; const long long INF = 1061109567; const long double EPS = 1e-9; const long double PI = acos(-1); const int MXX = 2e5 + 5; long long F[MXX + 5], iF[MXX + 5]; long long qpow(long long b, long long e) { if (!e) return 1LL; if (e & 1) return (qpow(b, e - 1) * b) % MOD; long long aux = qpow(b, e / 2); return (aux * aux) % MOD; } long long invmod(long long n) { return qpow(n, MOD - 2); } long long ways(int p, int q) { if (p == 0 || q == 0) return 1; long long ans = ((F[p + q] % MOD) * (iF[p] % MOD)) % MOD; ans = ((ans % MOD) * (iF[q] % MOD)) % MOD; return ans; } long long ways(int p, int q, int u, int v) { return ways(u - p, v - q) % MOD; } pair<int, int> pt[MX]; long long dp[MX]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); iF[0] = F[0] = iF[1] = F[1] = 1LL; for (int i = (2); i < (MXX); i++) { F[i] = ((F[i - 1] % MOD) * (i % MOD)) % MOD; iF[i] = ((iF[i - 1] % MOD) * (invmod(i) % MOD)) % MOD; } int h, w; cin >> h >> w; int n; cin >> n; n++; pt[0].first = pt[0].second = 1; for (int i = (1); i < (n); i++) { cin >> pt[i].first >> pt[i].second; } sort(pt, pt + n); for (int i = (n - 1); i >= (0); i--) { dp[i] = ways(pt[i].first, pt[i].second, h, w); for (int j = (i + 1); j < (n); j++) { if (pt[j].second < pt[i].second) continue; long long v = ways(pt[i].first, pt[i].second, pt[j].first, pt[j].second) % MOD; v = (v * dp[j]) % MOD; dp[i] = (dp[i] + MOD - v) % MOD; } } cout << dp[0]; } |
module spmc_timestamp_counter #(
parameter CLOCK_FREQUENCY = 16000000, //input clock frequency
parameter BASE_ADR = 10'h0) (
//*** Connections to SpartanMC Core (do not change) ***
input wire clk_peri, //System-Clock
input wire [17:0] do_peri, //Data Bus from MC
output wire [17:0] di_peri, //Data Bus to MC
input wire [9:0] addr_peri, //Address Bus from MC
input wire access_peri, //Peripheral Access Signal
input wire wr_peri, //Write Enable Signal
//*** Connections to SpartanMC Core which can be changed ***
input wire reset, //Reset-Signal (could be external)
//*** timestamp counter output ***
output reg [35:0] lpt_counter, //low precision counter input
output reg [35:0] hpt_counter //high precision counter input
);
//register addresses of the module
parameter LPT_LOW = 2'b00; //low precision timestamp low register
parameter LPT_HIGH = 2'b01; //low precision timestamp high register
parameter HPT_LOW = 2'b10; //high precision timestamp low register
parameter HPT_HIGH = 2'b11; //high precision timestamp high register
wire select;
// Address decoder generates the select sinal out of the upper part of the peripheral address.
pselect iCSL (
.addr ( addr_peri[9:2] ),
.activ_peri ( access_peri ),
.select ( select )
);
defparam iCSL.ADDR_WIDTH = 8;
defparam iCSL.BASE_WIDTH = 8;
defparam iCSL.BASE_ADDR = BASE_ADR >> 2; //BASE_ADR has to be divisible by 4
//counter write register
reg [35:0] lpt_counter_write;
reg [35:0] hpt_counter_write;
reg counter_write_req;
//SpartanMC peripheral interface read logic -> no read
assign di_peri = 18'b0;
//SpartanMC peripheral interface write logic
always @(posedge clk_peri) begin
if (reset) begin
counter_write_req <= 1'b0;
end else begin
if (select & wr_peri) begin
case (addr_peri[1:0])
LPT_LOW: lpt_counter_write[17:0] = do_peri[17:0];
LPT_HIGH: lpt_counter_write[35:18] = do_peri[17:0];
HPT_LOW: hpt_counter_write[17:0] = do_peri[17:0];
HPT_HIGH: begin
hpt_counter_write[35:18] = do_peri[17:0];
counter_write_req <= 1'b1;
end
endcase
end else begin
counter_write_req <= 1'b0;
end
end
end
//counter logic
always @(posedge clk_peri) begin
if (reset) begin
hpt_counter <= 18'd0; //reset counters to 0
lpt_counter <= 18'd0;
end else begin
if (counter_write_req == 1'b1)begin
hpt_counter <= hpt_counter_write;
lpt_counter <= lpt_counter_write;
end else begin
if (hpt_counter == CLOCK_FREQUENCY-1) begin
hpt_counter <= 18'd0; //reset high precision counter if max value reached
lpt_counter <= lpt_counter + 1; //increment low precision counter
end else
hpt_counter <= hpt_counter + 1; //otherwise increment high precision counter
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int m; long long int a; long long int b; set<int> s; long long int im(long long int val, int dv) { long long int z = 0; long long int U = (1LL + val / dv) * (val / dv) / 2LL; U *= dv; U -= (val / dv) * (dv - (val % dv) - 1); return U; for (int i = 0; i <= val; i++) { z += i / dv; } return z; } long long int cn(int star, int ds) { long long int ret = im(m - ds, b) - im(star - ds - 1, b); ret += m - star + 1; return ret; } int main() { cin >> m >> a >> b; long long int mx = 0; long long int cur = 0; swap(a, b); long long int ans = cn(0, 0); s.insert(0); while (true) { if (cur < a) { cur += b * ((a - cur + b - 1) / b); } mx = max(mx, cur); cur -= a; cur %= b; if (mx > m) break; if (s.count(cur)) break; s.insert(cur); ans += cn(mx, cur); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int y[50010] = {}; int t[50010] = {}; unordered_map<int, int> ha; bool cmp(int x, int y) { return x > y; } bool ff(int x) { ha.clear(); for (int i = 1; i <= n; i++) y[i] = t[i]; for (int i = 1; i <= n; i++) { if (y[i] <= x && ha[y[i]] == 0) { ha[y[i]] = 1; } else { while (1) { if (y[i] == 1) { return 0; } if (ha.find(y[i] / 2) == ha.end() && (y[i] / 2) <= x) { ha[y[i] / 2] = 1; break; } else y[i] = y[i] / 2; } } } return 1; } void ans(int x) { ha.clear(); for (int i = 1; i <= n; i++) y[i] = t[i]; for (int i = 1; i <= n; i++) { if (y[i] <= x && ha[y[i]] == 0) { ha[y[i]] = 1; printf( %d , y[i]); } else { while (1) { if (ha.find(y[i] / 2) == ha.end() && (y[i] / 2) <= x) { ha[y[i] / 2] = 1; break; } else y[i] = y[i] / 2; } printf( %d , y[i] / 2); } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &t[i]); sort(t + 1, t + n + 1, cmp); int l = 1; int r = 1000000000; while (l < r) { int mid = (l + r) / 2; if (ff(mid)) r = mid; else l = mid + 1; } ans(l); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_2_V
`define SKY130_FD_SC_LS__NAND3_2_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_2_V
|
#include <bits/stdc++.h> using namespace std; int i, a[1111], x, n, s, y, f1, f2; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> x; if (x == 0 || x == 100) a[++s] = x; else if (x < 10 && f1 == 0) a[++s] = x, f1 = 1; else if (x % 10 == 0 && f2 == 0) a[++s] = x, f2 = 1; else y = x; } if (f1 == 0 && f2 == 0 && y != 0) a[++s] = y; cout << s << n ; for (i = 1; i <= s; i++) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-12; const int inf = 2000000000; const long long int infLL = (long long int)2e18; long long int MOD = 998244353; int MOD1 = 1000000007; int MOD2 = 1000000009; inline bool checkBit(long long int n, long long int i) { return n & (1LL << i); } inline long long int setBit(long long int n, long long int i) { return n | (1LL << i); ; } inline long long int resetBit(long long int n, long long int i) { return n & (~(1LL << i)); } int dx[] = {0, 0, +1, -1}; int dy[] = {+1, -1, 0, 0}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long int year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long int &a) { a %= MOD; (a < 0) && (a += MOD); } inline long long int modMul(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a * b) % MOD; } inline long long int modAdd(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a + b) % MOD; } inline long long int modSub(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); a -= b; normal(a); return a; } inline long long int modPow(long long int b, long long int p) { long long int r = 1LL; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1LL; } return r; } inline long long int modDiv(long long int a, long long int b) { return modMul(a, modPow(b, MOD - 2)); } bool comp(const pair<long long int, pair<long long int, long long int> > &p1, const pair<long long int, pair<long long int, long long int> > &p2) { return p1.first > p2.first; } bool comp1(const pair<long long int, long long int> &p1, const pair<long long int, long long int> &p2) { if (p1.first == p2.first) { return p1.second > p2.second; } return p1.first < p2.first; } long long int converter(string a) { long long int i, mul = 1, r, t, ans = 0LL; if (a.length() == 0) return 0; for (i = a.length() - 1; i >= 0; i--) { t = a[i] - 0 ; r = t % 10; ans += (mul * r); mul = mul * 10; } return ans; } int msb(unsigned x) { union { double a; int b[2]; }; a = x; return (b[1] >> 20) - 1023; } const int MAX = (int)1e5 + 5; int n, m, a[MAX], tp[MAX], b[MAX]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int i, j, k; cin >> n >> m; for (i = 1; i <= m; ++i) { cin >> a[i]; tp[a[i]]++; } int tot = 0; for (i = 1; i <= m; ++i) { if (tp[a[i]] > 0) b[++tot] = tp[a[i]], tp[a[i]] = 0; } for (i = 1000; i >= 1; --i) { long long int xx = 0LL; for (j = 1; j <= tot; ++j) { xx += (b[j] / i); } if (xx >= n) { cout << i << n ; return 0; } } cout << 0 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a, x, b, y; cin >> n >> a >> x >> b >> y; while (a != x && b != y) { if (a == b) break; a = (a % n) + 1; if (b == 1) b = n; else b--; } if (a == b) cout << YES ; else cout << NO ; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 7,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dadd_3_full_dsp_64 ANN_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; class Matrix { public: long long m[4][4]; Matrix(){}; Matrix(long long k[4][4]) { for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) m[i][j] = k[i][j]; } }; Matrix operator*(const Matrix &a, const Matrix &b) { Matrix t; for (int i = 0; i < 4; i++) { for (int j = 0; j < 4; j++) { t.m[i][j] = 0; for (int c = 0; c < 4; c++) { t.m[i][j] += (b.m[i][c]) * (a.m[c][j]); t.m[i][j] %= MOD; } } } return t; } Matrix pow(Matrix m, int p) { if (p == 1) return m; Matrix ret = pow(m, p / 2); if (p & 1) { return (ret * ret) * m; } else return (ret * ret); } int main() { int n; long long arr[4][4]; scanf( %d , &n); for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) if (i == j) arr[i][j] = 0; else arr[i][j] = 1; Matrix g(arr); Matrix ret = pow(g, n); cout << ret.m[3][3] % MOD << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10, mod = 998244353; int n, m, x, y; vector<int> e[2][N]; inline void adde(int x, int y, int o) { e[o][x].push_back(y); } inline int read() { char ch = getchar(); int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) - 0 + ch; ch = getchar(); } return x * f; } void write(int x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) write(x / 10); putchar(x % 10 + 0 ); return; } int dis[19][N]; bool vis[19][N]; queue<pair<int, int> > q; int spfa() { memset(dis, 63, sizeof(dis)); q.push(pair<int, int>(0, 1)); dis[0][1] = 0; while (!q.empty()) { int u = q.front().second, k = q.front().first; q.pop(); vis[k][u] = 0; for (int v : e[k & 1][u]) { if (dis[k][v] > dis[k][u] + 1) { dis[k][v] = dis[k][u] + 1; if (!vis[k][v]) vis[k][v] = 1, q.push(pair<int, int>(k, v)); } } if (k < 18) { if (dis[k + 1][u] > dis[k][u] + (1 << k)) { dis[k + 1][u] = dis[k][u] + (1 << k); if (!vis[k + 1][u]) vis[k + 1][u] = 1, q.push(pair<int, int>(k + 1, u)); } } } int res = 1e9 + 7; for (int i = 0; i <= 18; ++i) res = min(res, dis[i][n]); return res; } queue<int> Q, tmp; int diss[N]; inline int qbit(int x) { int res = 1, t = 2; for (; x; x >>= 1) x & 1 ? (res = 1ll * res * t % mod) : 1, t = 1ll * t * t % mod; return res; } int main() { n = read(), m = read(); for (int i = 1; i <= m; ++i) { x = read(), y = read(); adde(x, y, 0), adde(y, x, 1); } int ans = spfa(); if (ans < 1e9) return write(ans), 0; memset(diss, 63, sizeof(diss)); diss[1] = 0, Q.push(1), tmp.push(1); for (int k = 0;; ++k) { while (!Q.empty()) { int u = Q.front(); Q.pop(); if (u == n) return write((qbit(k) - 1 + diss[u]) % mod), 0; for (int v : e[k & 1][u]) if (diss[v] > diss[u] + 1) diss[v] = diss[u] + 1, Q.push(v), tmp.push(v); } while (!tmp.empty()) Q.push(tmp.front()), tmp.pop(); } } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module pulse_gen_core
#(
parameter ABUSWIDTH = 16
)
(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire PULSE_CLK,
input wire EXT_START,
output reg PULSE
);
localparam VERSION = 3;
wire SOFT_RST;
wire START;
reg CONF_EN;
reg [31:0] CONF_DELAY;
reg [31:0] CONF_WIDTH;
reg [31:0] CONF_REPEAT;
reg CONF_DONE;
always@(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= CONF_DELAY[7:0];
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_DELAY[15:8];
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_DELAY[23:16];
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_DELAY[31:24];
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_WIDTH[7:0];
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_WIDTH[15:8];
else if(BUS_ADD == 9)
BUS_DATA_OUT <= CONF_WIDTH[23:16];
else if(BUS_ADD == 10)
BUS_DATA_OUT <= CONF_WIDTH[31:24];
else if(BUS_ADD == 11)
BUS_DATA_OUT <= CONF_REPEAT[7:0];
else if(BUS_ADD == 12)
BUS_DATA_OUT <= CONF_REPEAT[15:8];
else if(BUS_ADD == 13)
BUS_DATA_OUT <= CONF_REPEAT[23:16];
else if(BUS_ADD == 14)
BUS_DATA_OUT <= CONF_REPEAT[31:24];
else
BUS_DATA_OUT <= 8'b0;
end
end
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_DELAY <= 0;
CONF_WIDTH <= 0;
CONF_REPEAT <= 1;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
else if(BUS_ADD == 3)
CONF_DELAY[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 4)
CONF_DELAY[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 5)
CONF_DELAY[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 6)
CONF_DELAY[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 7)
CONF_WIDTH[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 8)
CONF_WIDTH[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 9)
CONF_WIDTH[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 10)
CONF_WIDTH[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 11)
CONF_REPEAT[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 12)
CONF_REPEAT[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 13)
CONF_REPEAT[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 14)
CONF_REPEAT[31:24] <= BUS_DATA_IN;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(PULSE_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(PULSE_CLK), .pulse_out(START_SYNC));
wire EXT_START_SYNC;
reg [2:0] EXT_START_FF;
always @(posedge PULSE_CLK) // first stage
begin
EXT_START_FF[0] <= EXT_START;
EXT_START_FF[1] <= EXT_START_FF[0];
EXT_START_FF[2] <= EXT_START_FF[1];
end
assign EXT_START_SYNC = !EXT_START_FF[2] & EXT_START_FF[1];
reg [31:0] CNT;
wire [32:0] LAST_CNT;
assign LAST_CNT = CONF_DELAY + CONF_WIDTH;
reg [31:0] REAPAT_CNT;
always @ (posedge PULSE_CLK) begin
if (RST_SYNC)
REAPAT_CNT <= 0;
else if(START_SYNC || (EXT_START_SYNC && CONF_EN))
REAPAT_CNT <= CONF_REPEAT;
else if(REAPAT_CNT != 0 && CNT == 1)
REAPAT_CNT <= REAPAT_CNT - 1;
end
always @ (posedge PULSE_CLK) begin
if (RST_SYNC)
CNT <= 0; //IS THIS RIGHT?
else if(START_SYNC || (EXT_START_SYNC && CONF_EN))
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT != 0)
CNT <= 1;
else if(CNT == LAST_CNT && CONF_REPEAT==0)
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT == 0)
CNT <= 0;
else if(CNT != 0)
CNT <= CNT + 1;
end
always @ (posedge PULSE_CLK) begin
if(RST_SYNC || START_SYNC || (EXT_START_SYNC && CONF_EN))
PULSE <= 0;
else if(CNT == CONF_DELAY && CNT > 0)
PULSE <= 1;
else if(CNT == LAST_CNT)
PULSE <= 0;
end
wire DONE;
assign DONE = (CNT == 0);
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
wire EXT_START_SYNC_BUS;
cdc_pulse_sync ex_start_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(EXT_START && CONF_EN), .clk_out(BUS_CLK), .pulse_out(EXT_START_SYNC_BUS));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START || EXT_START_SYNC_BUS)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int MaxN = 300005; const long long int mod = 1e9 + 7; const float pi = 3.1415926535897932384626433832795028; long long int mcd(long long int a, long long int b) { if (a == 0) return b; return mcd(b % a, a); } int arr[MaxN]; void solve() { int N, i, j, p, q; cin >> N; for (i = 1; i <= N; i++) { cin >> arr[i]; } p = 0, q = N + 1; for (i = 1; i <= N; i++) { if (arr[i] >= i - 1) { p = i; } else break; } for (i = N; i > 0; i--) { if (arr[i] >= N - i) { q = i; } else break; } if (p >= q) cout << Yes n ; else cout << No n ; } int main() { long long int t, i; cin >> t; for (i = 1; i <= t; i++) { solve(); } } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always assign reg_lvalue = boolean_expression ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4'h1)
$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\n");
else
begin
$display("PASSED\n");
$finish;
end
always assign value1 = 1'b1 && 1'b1 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { char c = getchar(); long long x = 0; bool f = 0; for (; !isdigit(c); c = getchar()) f ^= !(c ^ 45); for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); if (f) x = -x; return x; } long long n, a[300005], l[300005], r[300005]; bool vis[300005]; void work() { n = read(); for (register long long i = (1); i <= (n); ++i) a[i] = read(), vis[i] = 0; long long all = 0, now = 0, mx = 0; for (register long long i = (1); i <= (n); ++i) { if (!vis[a[i]]) vis[a[i]] = 1, l[a[i]] = i, ++all; r[a[i]] = i; } long long lst = -1; for (register long long i = (1); i <= (n); ++i) if (vis[i]) { if (!now) now = mx = 1, lst = i; else { if (l[i] > r[lst]) now++; else now = 1; lst = i; mx = max(mx, now); } } cout << all - mx << endl; } signed main() { long long T = read(); while (T--) work(); return 0; } |
#include <bits/stdc++.h> using namespace std; int Month[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int A[1000 + 1]; int B[126]; void omae_wa_mou_shindeiru() { int n, k; cin >> n >> k; string s; cin >> s; for (int i = 0; i < n; ++i) { int c = 1; while (s[i] == s[i + 1] && i < n) { ++c; ++i; } B[s[i]] += c / k; } int ans = 0; for (int i = a ; i <= z ; ++i) { ans = max(ans, B[i]); } cout << ans; } int main() { ios_base::sync_with_stdio(false); ; int t = 1; while (t--) { omae_wa_mou_shindeiru(); if (t) cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 2000 + 4, Inf = 1e9 + 10; int n, m, k; char f[M][M]; int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> f[i][j]; for (int i = 0; i < m; i++) { int ans = 0; for (int y = 2; y < n; y += 2) if (f[y][i] == U ) ans++; for (int x = i, y = 0; x >= 0 && y < n; y++, x--) if (f[y][x] == R ) ans++; for (int x = i, y = 0; x < m && y < n; y++, x++) if (f[y][x] == L ) ans++; cout << ans << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; char __buf[1 << 20], *__p1, *__p2; int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + (ch ^ 48), ch = getchar(); return s * w; } const int maxn = 710; struct Wint : vector<long long> { const static long long BIT = 1e8; Wint(long long n = 0) { push_back(n); check(); } Wint& operator=(const char* num) { int Len = strlen(num) - 1; clear(); for (int i = Len; i >= 0; i -= 9) { push_back(0); long long w = 1; for (int j = i; j > i - 9 && j >= 0; --j) back() += (num[j] ^ 48) * w, w *= 10; } return *this; } Wint& check() { while (!empty() && !back()) pop_back(); if (empty()) return *this; for (int i = 1; i < size(); ++i) (*this)[i] += (*this)[i - 1] / BIT, (*this)[i - 1] %= BIT; while (back() >= BIT) { push_back(back() / BIT); (*this)[size() - 2] %= BIT; } return *this; } }; bool operator<(Wint a, Wint b) { if (a.size() != b.size()) return a.size() < b.size(); for (int i = a.size() - 1; i >= 0; --i) if (a[i] != b[i]) return a[i] < b[i]; return 0; } bool operator>(Wint a, Wint b) { return b < a; } bool operator<=(Wint a, Wint b) { return !(a > b); } bool operator>=(Wint a, Wint b) { return !(a < b); } bool operator!=(Wint a, Wint b) { return a < b || b < a; } bool operator==(Wint a, Wint b) { return !(a < b) && !(b < a); } Wint& operator+=(Wint& a, Wint b) { if (a.size() < b.size()) a.resize(b.size()); for (int i = 0; i < b.size(); ++i) a[i] += b[i]; return a.check(); } Wint operator+(Wint a, Wint b) { return a += b; } Wint& operator-=(Wint& a, Wint b) { for (int i = 0; i < b.size(); a[i] -= b[i], ++i) if (a[i] < b[i]) { int j = i + 1; while (!a[j]) ++j; while (j > i) --a[j], a[--j] += Wint::BIT; } return a.check(); } Wint operator-(Wint a, Wint b) { return a -= b; } Wint operator*(Wint a, Wint b) { Wint n; n.assign(a.size() + b.size() - 1, 0); for (int i = 0; i < a.size(); ++i) for (int j = 0; j < b.size(); ++j) n[i + j] += a[i] * b[j]; return n.check(); } Wint& operator*=(Wint& a, Wint b) { return a = a * b; } Wint operator/(Wint a, int b) { Wint n; bool wp = 0; long long t = 0; for (int i = a.size() - 1; i >= 0; --i) { t = t * Wint::BIT + a[i]; if (wp || t / b) wp = 1, n.push_back(t / b); t %= b; } reverse(n.begin(), n.end()); return n; } Wint& operator/=(Wint& a, int b) { return a = a / b; } void writeX(Wint n) { if (n.empty()) return putchar( 0 ), void(); int Len = n.size() - 1; printf( %lld , n[Len]); for (int i = Len - 1; i >= 0; --i) printf( %08lld , n[i]); } Wint Win(long long num) { Wint t = num; return t; } vector<int> G[maxn]; Wint f[maxn][maxn], t[maxn]; int n, sz[maxn]; void add(int x, int y) { G[x].push_back(y), G[y].push_back(x); } template <class T> void Max(T& x, T y) { x = max(x, y); } void dfs(int x, int pa) { f[x][1] = Win(1), sz[x] = 1; for (int y : G[x]) if (y ^ pa) { dfs(y, x); for (int i = 1; i <= sz[x]; i++) { for (int j = 1; j <= sz[y]; j++) Max(t[i], f[x][i] * f[y][j] * Win(j)), Max(t[i + j], f[x][i] * f[y][j]); } for (int i = 1; i <= sz[x] + sz[y]; i++) f[x][i] = t[i], t[i] = Win(0); sz[x] += sz[y]; } } signed main() { n = read(); for (int i = 1; i < n; i++) add(read(), read()); dfs(1, 0); Wint ans = Win(0); for (int i = 1; i <= n; i++) ans = max(ans, f[1][i] * Win(i)); writeX(ans); return 0; } |
#include <bits/stdc++.h> using namespace std; inline void read(int &data) { data = 0; int e = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) e = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) data = data * 10 + ch - 48, ch = getchar(); data *= e; } inline void read(long long &data) { data = 0; int e = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) e = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) data = data * 10 + ch - 48, ch = getchar(); data *= e; } inline void write(int data) { if (data < 0) data = -data, putchar( - ); if (data > 9) write(data / 10); putchar(data % 10 + 48); } inline void write(long long data) { if (data < 0) data = -data, putchar( - ); if (data > 9) write(data / 10); putchar(data % 10 + 48); } bool cmp(int a, int b) { return a < b; } priority_queue<long long, vector<long long>, greater<long long> > q; long long n, x, ans = 0; int main() { read(n); for (int i = 1; i <= n; ++i) { read(x); if (q.empty() || q.top() > x) q.push(x); else { ans += x - q.top(); q.pop(); q.push(x), q.push(x); } } write(ans), puts( ); } |
#include <bits/stdc++.h> using namespace std; queue<int> que; vector<bool> init, goal; vector<bool> visited; vector<vector<int>> nodes; void calculate(int root, bool flip1, bool flip2) { const vector<int> &children = nodes[root]; visited[root] = true; if (init[root] ^ flip1 != goal[root]) { que.push(root + 1); for (auto c : children) { if (visited[c]) continue; calculate(c, flip2, !flip1); } } else { for (auto c : children) { if (visited[c]) continue; calculate(c, flip2, flip1); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; nodes.resize(n); for (int i = 0; i < n - 1; ++i) { int p, c; cin >> c >> p; nodes[p - 1].push_back(c - 1); nodes[c - 1].push_back(p - 1); } init.resize(n); for (int i = 0; i < n; ++i) { int b; cin >> b; init[i] = b; } goal.resize(n); for (int i = 0; i < n; ++i) { int b; cin >> b; goal[i] = b; } visited.resize(n, false); calculate(0, false, false); cout << que.size() << endl; while (!que.empty()) { cout << que.front() << endl; que.pop(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFKAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFKAPWR_BLACKBOX_V
/**
* bufkapwr: Buffer on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufkapwr (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFKAPWR_BLACKBOX_V
|
// Accellera Standard V2.3 Open Verification Library (OVL.
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_valid_id (clock, reset, enable, issued, issued_id, returned, returned_id, flush, flush_id, issued_count, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 1;
parameter max_cks = 1;
parameter width = 2;
parameter max_id_instances = 2;
parameter max_ids = 1;
parameter max_instances_per_id = 1;
parameter instance_count_width = 2;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input issued, returned, flush;
input [width-1 : 0] issued_id;
input [width-1 : 0] returned_id;
input [width-1 : 0] flush_id;
input [instance_count_width-1 : 0] issued_count;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_VALID_ID";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_valid_id_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_valid_id
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; string s; cin >> n >> m; int a[n][m]; int r[m]; memset(r, 0, sizeof r); for (int i = 0; i < n; i++) { cin >> s; for (int j = 0; j < m; j++) { a[i][j] = s[j] - 0 ; if (a[i][j]) { r[j]++; } } } for (int i = 0; i < n; i++) { bool u = false; for (int j = 0; j < m && !u; j++) { if (a[i][j] && r[j] == 1) u = true; } if (!u) { cout << YES n ; return 0; } } cout << NO n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000, INF = 2000000000; struct edge { int x; int y; int w; int o; }; vector<vector<edge> > G(MAXN + 1); int n, m, depth[MAXN + 1], low[MAXN + 1], s, t, previous[MAXN + 1], prevCost[MAXN + 1], cntEdges[MAXN + 1][MAXN + 1], c, sons[MAXN + 1], p1 = -1, p2; bool vis[MAXN + 1]; edge removedEdge = {0, 0, 0, -1}, e1, e2, prevEdge[MAXN + 1]; vector<edge> edgesOnPath, currentPath, allEdges; bool eq(edge a, edge b) { return a.w == b.w && min(a.x, a.y) == min(b.x, b.y) && max(a.x, a.y) == max(b.x, b.y); } void redo() { memset(prevCost, 0, sizeof(prevCost)); memset(previous, 0, sizeof(previous)); memset(vis, 0, sizeof(vis)); memset(depth, 0, sizeof(depth)); memset(low, 0, sizeof(low)); memset(sons, 0, sizeof(sons)); currentPath.clear(); } bool isBridge(edge e) { if (cntEdges[e.x][e.y] == 1) { if (low[e.x] > depth[e.y] || low[e.y] > depth[e.x]) return true; } else { if (cntEdges[e.x][e.y] != 2) return false; if (min(removedEdge.x, removedEdge.y) != min(e.x, e.y) || max(removedEdge.x, removedEdge.y) != max(e.x, e.y)) return false; if (low[e.x] > depth[e.y] || low[e.y] > depth[e.x]) return true; } return false; } int getEdgeOrder(edge e) { for (int i = 0; i < allEdges.size(); i++) if (eq(e, allEdges[i]) == true && (i + 1 != p1)) return i + 1; } void dfs(int node) { vis[node] = true; for (int i = 0; i < G[node].size(); i++) { int nextNode = G[node][i].y; if (G[node][i].o != removedEdge.o) { if (vis[nextNode] == false) { sons[node]++; depth[nextNode] = depth[node] + 1; low[nextNode] = depth[nextNode]; previous[nextNode] = node; prevCost[nextNode] = G[node][i].w; prevEdge[nextNode] = G[node][i]; dfs(nextNode); low[node] = min(low[node], low[nextNode]); } else { if (previous[node] != nextNode) low[node] = min(low[node], low[nextNode]); } } } } void findPath(int x, int y, vector<edge> &e) { int node = t; while (node != x) { e.push_back(prevEdge[node]); node = previous[node]; } } int answer = -1; void solve() { if (m == 0) { cout << 0 << endl << 0; return; } dfs(s); if (vis[t] == false) { cout << 0 << endl << 0; return; } findPath(s, t, edgesOnPath); for (int i = 0; i < edgesOnPath.size(); i++) if (isBridge(edgesOnPath[i]) == true) { if (answer == -1 || answer > edgesOnPath[i].w) { answer = edgesOnPath[i].w; c = 1; e1 = edgesOnPath[i]; } } for (int i = 0; i < edgesOnPath.size(); i++) { removedEdge = edgesOnPath[i]; redo(); dfs(s); if (vis[t] == true) findPath(s, t, currentPath); for (int j = 0; j < currentPath.size(); j++) if (isBridge(currentPath[j]) == true) { if (answer == -1 || removedEdge.w + currentPath[j].w < answer) { answer = removedEdge.w + currentPath[j].w; c = 2; e1 = removedEdge; e2 = currentPath[j]; } } } cout << answer << endl; if (c != 0) cout << c << endl; if (c == 1) cout << e1.o; if (c == 2) { cout << e2.o << << e1.o; } } void readData() { scanf( %d %d %d %d , &n, &m, &s, &t); for (int i = 1; i <= m; i++) { int x, y, w; scanf( %d %d %d , &x, &y, &w); allEdges.push_back({min(x, y), max(x, y), w, i}); if (x != y) { cntEdges[x][y]++; cntEdges[y][x]++; G[x].push_back({x, y, w, i}); G[y].push_back({y, x, w, i}); G[x][G[x].size() - 1].o = i; G[y][G[y].size() - 1].o = i; } } } int main() { readData(); solve(); return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_hdr_fifo.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_hdr_fifo module implements a simple fifo for a packet
// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
// followed by a payload. HDR_LEN indicates the length of the header in
// dwords. The ABLANKS signal indicates how many dwords should be inserted between
// the header and payload.
//
// The intended use for this module is between the interface specific tx formatter
// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
// which contains a fifo for payloads.
//
// Author: Dustin Richmond (@darichmond)
// Co-Authors:
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_hdr_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR_TX_HDR
input WR_TX_HDR_VALID,
input [(C_MAX_HDR_WIDTH)-1:0] WR_TX_HDR,
input [`SIG_LEN_W-1:0] WR_TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] WR_TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] WR_TX_HDR_PACKET_LEN,
input WR_TX_HDR_NOPAYLOAD,
output WR_TX_HDR_READY,
// Interface: RD_TX_HDR
output RD_TX_HDR_VALID,
output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
output [`SIG_LEN_W-1:0] RD_TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] RD_TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] RD_TX_HDR_PACKET_LEN,
output RD_TX_HDR_NOPAYLOAD,
input RD_TX_HDR_READY
);
`include "functions.vh"
// Size of the header, plus the three metadata signals
localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
wire RST;
wire wWrTxHdrReady;
wire wWrTxHdrValid;
wire [(C_MAX_HDR_WIDTH)-1:0] wWrTxHdr;
wire [`SIG_NONPAY_W-1:0] wWrTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wWrTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wWrTxHdrPayloadLen;
wire wWrTxHdrNoPayload;
wire wRdTxHdrReady;
wire wRdTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wRdTxHdr;
wire [`SIG_NONPAY_W-1:0] wRdTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wRdTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wRdTxHdrPayloadLen;
wire wRdTxHdrNoPayload;
assign RST = RST_IN;
pipeline
#(
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
input_pipeline_inst
(
// Outputs
.WR_DATA_READY (WR_TX_HDR_READY),
.RD_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.RD_DATA_VALID (wWrTxHdrValid),
// Inputs
.WR_DATA ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (WR_TX_HDR_VALID),
.RD_DATA_READY (wWrTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
fifo
#(
// Parameters
.C_DELAY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH_PACKETS))
fifo_inst
(
// Outputs
.RD_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_READY (wWrTxHdrReady),
.RD_VALID (wRdTxHdrValid),
// Inputs
.WR_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.WR_VALID (wWrTxHdrValid),
.RD_READY (wRdTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
output_pipeline_inst
(
// Outputs
.WR_DATA_READY (wRdTxHdrReady),
.RD_DATA ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
.RD_DATA_VALID (RD_TX_HDR_VALID),
// Inputs
.WR_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_DATA_VALID (wRdTxHdrValid),
.RD_DATA_READY (RD_TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
#include <bits/stdc++.h> using namespace std; char xB[1 << 15], *xS = xB, *xTT = xB; template <typename T> inline void rd(T& xaa) { char xchh; T f = 1; xaa = 0; while (xchh = (xS == xTT && (xTT = (xS = xB) + fread(xB, 1, 1 << 15, stdin), xS == xTT) ? 0 : *xS++), !((xchh >= 0 && xchh <= 9 ) || (xchh == - ))) ; if (xchh == - ) { f = -1; xchh = (xS == xTT && (xTT = (xS = xB) + fread(xB, 1, 1 << 15, stdin), xS == xTT) ? 0 : *xS++); } xaa = xchh - 0 ; while (xchh = (xS == xTT && (xTT = (xS = xB) + fread(xB, 1, 1 << 15, stdin), xS == xTT) ? 0 : *xS++), ((xchh >= 0 && xchh <= 9 ) || (xchh == - ))) xaa = xaa * 10 + xchh - 0 ; xaa *= f; return; } long long geta(long long x, long long y, long long a, long long b) { return x * a + y * b; } long long getb(long long x, long long y, long long a, long long b) { return x * b - y * a; } int n; long long a, b, res; int main() { rd(n); rd(a); rd(b); map<long long, vector<long long> > val; for (int i = 1; i <= n; i++) { long long e, x, y; rd(e); rd(x); rd(y); long long px = geta(x, y, 1, a), py = getb(x, y, 1, a); val[py].push_back(px); } long long res = 0; for (map<long long, vector<long long> >::iterator it = val.begin(); it != val.end(); it++) { vector<long long>& tv = it->second; sort(tv.begin(), tv.end()); long long nv = 0, nc = 0; bool st = 0; int len = static_cast<int>(tv.size()); for (vector<long long>::iterator it1 = tv.begin(); it1 != tv.end(); it1++) { if (!st) { nv = *it1; nc = 1; st = 1; } else { if (*it1 == nv) nc++; else { res += nc * (len - nc); nv = *it1; nc = 1; } } } res += nc * (len - nc); } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; unsigned long long k, n, d = 0, ans; string s; unsigned long long int sol1(int k); int main() { cin >> s; n = s.size(); cin >> k; ans = max(0ULL, min(2 * k, n + k - ((n + k) % 2))); ans = max(ans, sol1(k)); cout << ans << endl; const clock_t begin_time = clock(); return 0; } unsigned long long int sol1(int t) { int bop = 0; int anss = 0; for (int i = 0; i < n; i++) { for (int j = 1; j <= n; j++) { bop = 0; if (i + 2 * j - 1 >= n + t) { bop = 1; } else for (int k = 0; k < j; k++) { if (i + j + k < n) { if (s[i + k] != s[i + j + k]) { bop = 1; break; } } } if (bop == 0) { anss = max(anss, 2 * j); } } } return anss; } |
#include <bits/stdc++.h> using namespace std; int N, K; long long A[100100], sol; map<long long, long long> M; long long __grundy(long long n) { if (n == 0) return 0; if (((M).find(n) != (M).end())) return M[n]; long long r = __grundy(n - 1); if (n % 2 != 0) return M[n] = ((r == 0) ? 1 : 0); long long c = __grundy(n / 2); if (r != 0 && K > 0 && c != 0) return M[n] = 0; if (r != 1 && (K == 0 || c != 1)) return M[n] = 1; return M[n] = 2; } long long g0(long long n) { if (n == 0) return 0; if (n == 1) return 1; if (n == 2) return 2; return ((n % 2) == 0) ? 1 : 0; } long long g1(long long n) { if (n == 0) return 0; if (n == 1) return 1; if (n == 2) return 0; if (n == 3) return 1; if (n == 4) return 2; if ((n % 2) == 1) return 0; if (g1(n / 2) == 1) return 2; return 1; } long long grundy(long long n) { if (K) return g1(n); else return g0(n); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); K = 0; for (int I = 1; I <= 160; I++) { assert(grundy(I) == __grundy(I)); } M.clear(); K = 1; for (int I = 1; I <= 160; I++) { assert(grundy(I) == __grundy(I)); } cin >> N >> K; K %= 2; for (long long I = 0; I < N; I++) { cin >> A[I]; sol ^= grundy(A[I]); } if (sol == 0) cout << Nicky << endl; else cout << Kevin << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { long long k, sum = 0, i, j, n, cnt = 0; int a[20] = {0}, value; string s; cin >> k; cin >> s; for (i = 0; i < ((int)s.size()); ++i) { n = s[i] - 0 ; sum += n; a[n]++; } if (sum >= k) { cout << cnt << endl; return 0; } for (i = 0; i < 10; ++i) { value = 9 - i; for (j = 1; j <= a[i]; ++j) { sum += value; cnt++; if (sum >= k) { cout << cnt << endl; return 0; } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A41OI_FUNCTIONAL_PP_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, T, i, j, temp, le, ri, mid, ma = 0; cin >> n >> a >> b >> T; char str[n]; cin >> str; int r[n], l[n]; if (str[0] == h ) r[0] = 1; else r[0] = b + 1; for (i = 1; i < n; i++) { if (str[i] == h ) r[i] = r[i - 1] + a + 1; else r[i] = r[i - 1] + a + b + 1; } if (str[n - 1] == h ) l[0] = a + 1; else l[0] = a + b + 1; for (i = 1; i < n - 1; i++) { if (str[n - 1 - i] == h ) l[i] = l[i - 1] + a + 1; else l[i] = l[i - 1] + a + b + 1; } for (i = 0; i < n; i++) if (r[i] <= T) ma = max(ma, i + 1); for (i = 0; i < n - 1; i++) { temp = l[i]; if (temp >= T) continue; le = 0; ri = n - 1 - i - 1; while (ri - le > 1) { mid = (le + ri) / 2; temp = l[i] + min(i + 1, mid) * a; if (temp + r[mid] < T) le = mid; else ri = mid; } if (l[i] + r[le] + min(i + 1, le) * a <= T) ma = max(ma, i + le + 2); if (l[i] + r[ri] + min(i + 1, ri) * a <= T) ma = max(ma, i + ri + 2); } cout << ma; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 3-State Differential Signaling Output Buffer
// /___/ /\ Filename : OBUFTDS.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module OBUFTDS (O, OB, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O, OB;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 B1 (O, I, ts);
notif0 N1 (OB, I, ts);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFTDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
#1 $finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0,
0:0:0, 0:0:0,
0:0:0, 0:0:0);
(T => OB) = (0:0:0, 0:0:0,
0:0:0, 0:0:0,
0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int n, k, x, y; struct node { int L, R, e; long long int Lsum, Rsum, Ls, Rs; int mid() { return (L + R) / 2; } } a[200005 * 4]; void BuildTree(int r, int L, int R) { a[r].L = L; a[r].R = R; a[r].e = 0; a[r].Lsum = 0; a[r].Rsum = 0; a[r].Ls = 0; a[r].Rs = 0; if (L == R) return; BuildTree(r << 1 | 1, L, a[r].mid()); BuildTree(r << 1, a[r].mid() + 1, R); a[r].Lsum = a[r << 1 | 1].Lsum + a[r << 1].Lsum; a[r].Rsum = a[r << 1 | 1].Rsum + a[r << 1].Rsum; a[r].Ls = a[r << 1 | 1].Ls + a[r << 1].Ls; a[r].Rs = a[r << 1 | 1].Rs + a[r << 1].Rs; } void Update(int r, int L, int v) { if (a[r].L == a[r].R && a[r].L == L) { int kk = a[r].e; a[r].e += v; if (a[r].e >= y && kk < y) { a[r].Lsum++; a[r].Ls -= kk; } if (a[r].e >= x && kk < x) { a[r].Rs -= kk; a[r].Rsum++; } if (a[r].e < y) a[r].Ls = a[r].e; if (a[r].e < x) a[r].Rs = a[r].e; return; } if (L > a[r].mid()) Update(r << 1, L, v); else Update(r << 1 | 1, L, v); a[r].Lsum = a[r << 1 | 1].Lsum + a[r << 1].Lsum; a[r].Rsum = a[r << 1 | 1].Rsum + a[r << 1].Rsum; a[r].Ls = a[r << 1 | 1].Ls + a[r << 1].Ls; a[r].Rs = a[r << 1 | 1].Rs + a[r << 1].Rs; } long long int Qurry(int r, int L, int R, int b) { if (L > R) return 0; if (a[r].L == L && a[r].R == R) { if (b == 1) return a[r].Lsum * y + a[r].Ls; else if (b == 2) return a[r].Rsum * x + a[r].Rs; } if (L > a[r].mid()) return Qurry(r << 1, L, R, b); else if (R <= a[r].mid()) return Qurry(r << 1 | 1, L, R, b); else { long long a1 = Qurry(r << 1 | 1, L, a[r].mid(), b); long long a2 = Qurry(r << 1, a[r].mid() + 1, R, b); return a1 + a2; } } int main() { int q; while (scanf( %d , &n) != EOF) { memset(a, 0, sizeof(0)); int u, v; BuildTree(1, 1, n); scanf( %d %d %d %d , &k, &x, &y, &q); while (q--) { int kk; scanf( %d , &kk); if (kk == 1) { scanf( %d %d , &u, &v); Update(1, u, v); } else { scanf( %d , &u); long long int sum1 = Qurry(1, 1, u - 1, 1); long long int sum2 = Qurry(1, u + k, n, 2); printf( %lld n , sum1 + sum2); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int d, n, m, b[200005]; int mn[200005 << 2]; long long ans; struct node { int x; long long p; bool operator<(const node &a) const { return x < a.x; } } a[200005]; int check(int x, int y) { return a[x].p < a[y].p ? x : y; } void build(int l, int r, int rt) { if (l == r) { mn[rt] = l; return; } int mid = (l + r) >> 1; build(l, mid, rt << 1); build(mid + 1, r, rt << 1 | 1); mn[rt] = check(mn[rt << 1], mn[rt << 1 | 1]); } int get_mn(int l, int r, int rt, int L, int R) { if (L == l && R == r) return mn[rt]; int mid = (l + r) >> 1; if (R <= mid) return get_mn(l, mid, rt << 1, L, R); else if (L > mid) return get_mn(mid + 1, r, rt << 1 | 1, L, R); else return check(get_mn(l, mid, rt << 1, L, mid), get_mn(mid + 1, r, rt << 1 | 1, mid + 1, R)); } int main() { cin >> d >> n >> m; for (int i = 1; i <= m; i++) scanf( %d%I64d , &a[i].x, &a[i].p); sort(a + 1, a + m + 1); a[++m].x = d; a[0].p = 0x3f3f3f3f; build(1, m, 1); for (int i = 1; i <= m; i++) b[i] = a[i].x; int now = n, i = 0, j = 1, t, k; while (i < m) { t = upper_bound(b + 1, b + m + 1, a[i].x + n) - b - 1; if (t == i) { puts( -1 ); return 0; } t = upper_bound(b + 1, b + m + 1, a[i].x + now) - b - 1; k = (t > i ? get_mn(1, m, 1, i + 1, t) : 0); if (a[k].p <= a[i].p) { now -= (a[k].x - a[i].x); i = k; } else { t++; while (t <= m && a[t].x - a[i].x <= n) { if (a[t].p <= a[i].p) { ans = (ans + (a[t].x - a[i].x - now) * a[i].p); now = 0; i = t; break; } t++; } if (a[t].x - a[i].x > n) { t = upper_bound(b + 1, b + m + 1, a[i].x + n) - b - 1; k = get_mn(1, m, 1, i + 1, t); ans = (ans + (n - now) * a[i].p); now = (n - (a[k].x - a[i].x)); i = k; } } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { x = 0; char c = getchar(); bool flag = false; while (!isdigit(c)) { if (c == - ) flag = true; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } if (flag) x = -x; } int n, lenth, las = 1, root = 1, tot = 1; long long ans; int ch[1000010][26], fa[1000010], len[1000010], siz[1000010][15], l[1000010], r[1000010]; char s[1000010], str[1000010]; struct edge { int to, nxt; } e[1000010]; int head[1000010], edge_cnt; void add(int from, int to) { e[++edge_cnt] = (edge){to, head[from]}; head[from] = edge_cnt; } void insert(int c, int id) { int p = las, np = las = ++tot; len[np] = len[p] + 1, siz[np][id] = 1; while (p && !ch[p][c]) ch[p][c] = np, p = fa[p]; if (!p) fa[np] = root; else { int q = ch[p][c]; if (len[q] == len[p] + 1) fa[np] = q; else { int nq = ++tot; memcpy(ch[nq], ch[q], sizeof(ch[q])); len[nq] = len[p] + 1, fa[nq] = fa[q], fa[q] = fa[np] = nq; while (ch[p][c] == q) ch[p][c] = nq, p = fa[p]; } } } void dfs(int x) { for (int i = head[x]; i; i = e[i].nxt) { int y = e[i].to; dfs(y); for (int j = 0; j <= n; ++j) siz[x][j] += siz[y][j]; } } void calc(int x) { if (!siz[x][0]) return; for (int i = 1; i <= n; ++i) if (siz[x][i] < l[i] || siz[x][i] > r[i]) return; ans += len[x] - len[fa[x]]; } int main() { scanf( %s , str + 1), lenth = strlen(str + 1); for (int i = 1; i <= lenth; ++i) insert(str[i] - a , 0); read(n); for (int i = 1; i <= n; ++i) { las = 1, scanf( %s , s + 1), lenth = strlen(s + 1), read(l[i]), read(r[i]); for (int j = 1; j <= lenth; ++j) insert(s[j] - a , i); } for (int i = 2; i <= tot; ++i) add(fa[i], i); dfs(root); for (int i = 2; i <= tot; ++i) calc(i); printf( %lld , ans); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top RAT_slice_1_0_0 -prefix
// RAT_slice_1_0_0_ RAT_slice_12_3_0_stub.v
// Design : RAT_slice_12_3_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlslice,Vivado 2016.4" *)
module RAT_slice_1_0_0(Din, Dout)
/* synthesis syn_black_box black_box_pad_pin="Din[17:0],Dout[7:0]" */;
input [17:0]Din;
output [7:0]Dout;
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v11.1%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 11.1
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR311.1
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 7: 0] mem_dm;
inout [ 63: 0] mem_dq;
inout [ 7: 0] mem_dqs;
inout [ 7: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 31: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 7: 0] mem_dm;
wire [ 63: 0] mem_dq;
wire [ 7: 0] mem_dqs;
wire [ 7: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 31: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [255: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 4: 0] mem_local_size;
wire [255: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 31: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[7 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[7 : 0]),
.mem_dqsn (mem_dqsn[7 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[31 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< start europa
endmodule
|
#include <bits/stdc++.h> using namespace std; string s[555]; int dp[555], v[555], ones[555]; vector<pair<int, int> > vc[555]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, k; cin >> n >> m >> k; for (int i = 1; i <= n; i++) { cin >> s[i]; int cnt = 0; for (int j = 0; j < m; j++) { if (s[i][j] == 1 ) ones[cnt++] = j + 1; } memset(v, 0, sizeof(v)); v[cnt] = m; for (int j = 0; j < cnt; j++) { for (int k = j; k < cnt; k++) { int len = cnt - (k - j + 1); int value = m - (ones[k] - ones[j] + 1); v[len] = max(v[len], value); } } for (int j = 0; j <= k; j++) { if (v[j]) vc[i].push_back(make_pair(j, v[j])); } } for (int i = 1; i <= n; i++) { for (int j = k; j >= 0; j--) { for (int k = 0; k < vc[i].size(); k++) { if (j >= vc[i][k].first) dp[j] = max(dp[j], dp[j - vc[i][k].first] + vc[i][k].second); } } } cout << n * m - dp[k] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long leftBinarySearch(long long* color, long long size, long long target) { int l = 0; int r = size - 1; int idx = -1; while (l <= r) { int m = l + (r - l) / 2; if (color[m] <= target) { l = m + 1; idx = m; } else { r = m - 1; } } return idx; } long long rightBinarySearch(long long* color, long long size, long long target) { int l = 0; int r = size - 1; int idx = -1; while (l <= r) { int m = l + (r - l) / 2; if (color[m] >= target) { r = m - 1; idx = m; } else { l = m + 1; } } return idx; } int main() { int t; cin >> t; while (t--) { long long r, g, b; cin >> r >> g >> b; long long red[r], green[g], blue[b]; for (int i = 0; i < r; i++) cin >> red[i]; for (int i = 0; i < g; i++) cin >> green[i]; for (int i = 0; i < b; i++) cin >> blue[i]; sort(red, red + r); sort(green, green + g); sort(blue, blue + b); long long ans = LLONG_MAX; long long left, right; for (int i = 0; i < r; i++) { left = leftBinarySearch(green, g, red[i]); right = rightBinarySearch(blue, b, red[i]); if (left != -1 and right != -1) ans = min(ans, (green[left] - blue[right]) * (green[left] - blue[right]) + (red[i] - green[left]) * (red[i] - green[left]) + (red[i] - blue[right]) * (red[i] - blue[right])); left = leftBinarySearch(blue, b, red[i]); right = rightBinarySearch(green, g, red[i]); if (left != -1 and right != -1) ans = min(ans, (blue[left] - green[right]) * (blue[left] - green[right]) + (red[i] - blue[left]) * (red[i] - blue[left]) + (red[i] - green[right]) * (red[i] - green[right])); } for (int i = 0; i < g; i++) { left = leftBinarySearch(red, r, green[i]); right = rightBinarySearch(blue, b, green[i]); if (left != -1 and right != -1) ans = min(ans, (red[left] - blue[right]) * (red[left] - blue[right]) + (green[i] - red[left]) * (green[i] - red[left]) + (green[i] - blue[right]) * (green[i] - blue[right])); left = leftBinarySearch(blue, b, green[i]); right = rightBinarySearch(red, r, green[i]); if (left != -1 and right != -1) ans = min(ans, (blue[left] - red[right]) * (blue[left] - red[right]) + (green[i] - blue[left]) * (green[i] - blue[left]) + (green[i] - red[right]) * (green[i] - red[right])); } for (int i = 0; i < b; i++) { left = leftBinarySearch(red, r, blue[i]); right = rightBinarySearch(green, g, blue[i]); if (left != -1 and right != -1) ans = min(ans, (red[left] - green[right]) * (red[left] - green[right]) + (blue[i] - red[left]) * (blue[i] - red[left]) + (blue[i] - green[right]) * (blue[i] - green[right])); left = leftBinarySearch(green, g, blue[i]); right = rightBinarySearch(red, r, blue[i]); if (left != -1 and right != -1) ans = min(ans, (green[left] - red[right]) * (green[left] - red[right]) + (blue[i] - green[left]) * (blue[i] - green[left]) + (blue[i] - red[right]) * (blue[i] - red[right])); } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; bool yes; int t, n, m, len, l, sender[105]; map<string, int> msi; map<int, string> mis; string str, user[105], text[105]; set<int> mention[105]; int ans[105]; int dp[105][105]; char c; bool solve(int pos, int idx) { if (pos == m) return 1; if (dp[pos][idx] != -1) return dp[pos][idx]; if (mention[pos].find(idx) != mention[pos].end()) return 0; dp[pos][idx] = 0; if (pos + 1 < m && sender[pos + 1] != -1) { if (idx == sender[pos + 1]) return 0; dp[pos][idx] = solve(pos + 1, sender[pos + 1]); } else { for (int i = 0; i < n; ++i) { if (i != idx) { dp[pos][idx] |= solve(pos + 1, i); if (dp[pos][idx]) break; } else if (pos == m - 1) dp[pos][idx] = true; } } if (dp[pos][idx]) ans[pos] = idx; return dp[pos][idx]; } int main() { scanf( %d%c , &t, &c); while (t--) { scanf( %d%c , &n, &c); memset(sender, -1, sizeof sender); memset(dp, -1, sizeof dp); for (int i = 0; i < n; ++i) { cin >> user[i]; msi[user[i]] = i; mis[i] = user[i]; } scanf( %d%c , &m, &c); for (int i = 0; i < m; ++i) { getline(cin, str, : ); if (str.compare( ? ) == 0) sender[i] = -1; else sender[i] = msi[str]; getline(cin, text[i]); } for (int i = 0; i < m; ++i) { len = text[i].size(); for (int j = 0; j < n; ++j) { l = user[j].size(); yes = false; for (int k = 0; k < len; ++k) { if (text[i][k] == user[j][0] && k + l - 1 < len && text[i].compare(k, l, user[j]) == 0) { if (((k - 1 >= 0 && text[i][k - 1] != . && text[i][k - 1] != , && text[i][k - 1] != ! && text[i][k - 1] != ? && text[i][k - 1] != ) || (k + l < len && text[i][k + l] != . && text[i][k + l] != , && text[i][k + l] != ! && text[i][k + l] != ? && text[i][k + l] != ))) { } else { yes = true; break; } } } if (yes) mention[i].insert(msi[user[j]]); } } l = 0; if (sender[0] != -1) l |= solve(0, sender[0]); else { for (int i = 0; i < n; ++i) { l |= solve(0, i); if (l) break; } } if (!l) cout << Impossible << endl; else { for (int i = 0; i < m; ++i) { cout << user[ans[i]] << : << text[i] << endl; } } msi.clear(), mis.clear(); for (int i = 0; i < m; ++i) mention[i].clear(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 400005; int n, q, a[maxn]; namespace SGT { int Min[maxn << 2]; void modify(int l, int r, int id, int x, int y) { if (l == r) { Min[id] = y; return; } int mid = (l + r) >> 1; if (x <= mid) modify(l, mid, id << 1, x, y); else modify(mid + 1, r, id << 1 | 1, x, y); Min[id] = min(Min[id << 1], Min[id << 1 | 1]); } int query(int l, int r, int id, int L, int R) { if (L <= l && r <= R) return Min[id]; int mid = (l + r) >> 1, res = 1e9; if (L <= mid) res = min(res, query(l, mid, id << 1, L, R)); if (R > mid) res = min(res, query(mid + 1, r, id << 1 | 1, L, R)); return res; } } // namespace SGT struct query { int r1, c1, c2, id; query() {} query(int _r1, int _c1, int _c2, int _i) { r1 = _r1, c1 = _c1, c2 = _c2, id = _i; } }; int ans[maxn], now[maxn]; vector<query> Q[2][maxn]; void solve(vector<query> *Q) { static int st[maxn], num[maxn], top; top = 0; for (int i = 1; i <= n; i++) { while (top && num[top] >= a[i]) top--; st[++top] = i; num[top] = a[i]; SGT ::modify(1, n, 1, top, -2 * i + a[i]); for (auto u : Q[i]) { int r1 = u.r1, c1 = u.c1, r2 = i, c2 = u.c2, id = u.id; int res = r2 - r1 + c2 + 1; int L = lower_bound(st + 1, st + top + 1, r1) - st, R = top; now[id] = min(c1, num[L]); res = min(res, r2 - r1 + abs(c2 - now[id])); int pos = lower_bound(num + L, num + R + 1, c2) - num; if (pos <= R) res = min(res, r2 - r1 + 1 + abs(c2 - num[pos])); if (pos > L) res = min(res, r2 - r1 + 1 + abs(c2 - num[pos - 1])); else { assert(pos == L); pos = upper_bound(num + 1, num + R + 1, c2) - num - 1; if (pos && st[pos] <= r1) res = min(res, r1 + r2 - 2 * st[pos] + (c1 < num[pos]) + abs(c2 - num[pos])); } if (pos + 1 < L) { R = L - 1, L = pos + 1; int mid = upper_bound(num + L, num + R + 1, c1) - num; if (mid <= R) res = min(res, r1 + r2 + 1 + SGT ::query(1, n, 1, mid, R) - c2); if (L < mid) res = min(res, r1 + r2 + SGT ::query(1, n, 1, L, mid - 1) - c2); } ans[id] = res; } } top = 0; for (int i = n; i >= 1; i--) { while (top && num[top] >= a[i]) top--; st[++top] = i; num[top] = a[i]; SGT ::modify(1, n, 1, top, 2 * i + a[i]); for (auto u : Q[i]) { int r1 = u.r1, r2 = i, c2 = u.c2, id = u.id; int pos = upper_bound(num + 1, num + top + 1, c2) - num - 1, res = 1e9; if (pos) res = -(r1 + r2) + 2 * st[pos] + (now[id] < num[pos]) + abs(c2 - num[pos]); if (pos + 1 <= top) { int L = pos + 1, R = top; int mid = upper_bound(num + L, num + R + 1, now[id]) - num; if (mid <= R) res = min(res, -(r1 + r2) + 1 + SGT ::query(1, n, 1, mid, R) - c2); if (L < mid) res = min(res, -(r1 + r2) + SGT ::query(1, n, 1, L, mid - 1) - c2); } ans[id] = min(ans[id], res); } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &q); for (int i = 1, r1, c1, r2, c2; i <= q; i++) { scanf( %d%d%d%d , &r1, &c1, &r2, &c2); if (r1 <= r2) Q[0][r2].push_back(query(r1, c1, c2, i)); else Q[1][n - r2 + 1].push_back(query(n - r1 + 1, c1, c2, i)); } solve(Q[0]); reverse(a + 1, a + n + 1); solve(Q[1]); for (int i = 1; i <= q; i++) printf( %d n , ans[i]); return 0; } |
//////////////////////////////////////////////////////////////////
// //
// Wishbone master interface port buffer //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// This is a sub-module of the Amber wishbone master //
// interface. The wishbone master interface connects a number //
// of internal amber ports to the wishbone bus. The ports //
// are; //
// instruction cache read accesses //
// data cache read and write accesses (cached) //
// data cache read and write accesses (uncached) //
// //
// The buffer module buffers a single port. For write //
// requests, this allows the processor core to continue //
// executing withont having to wait for the wishbone write //
// operation to complete. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a25_wishbone_buf (
input i_clk,
// Core side
input i_req,
input i_write,
input [127:0] i_wdata,
input [15:0] i_be,
input [31:0] i_addr,
output [127:0] o_rdata,
output o_ack,
// Wishbone side
output o_valid,
input i_accepted,
output o_write,
output [127:0] o_wdata,
output [15:0] o_be,
output [31:0] o_addr,
input [127:0] i_rdata,
input i_rdata_valid
);
// ----------------------------------------------------
// Signals
// ----------------------------------------------------
reg [1:0] wbuf_used_r = 'd0;
reg [127:0] wbuf_wdata_r [1:0];
reg [31:0] wbuf_addr_r [1:0];
reg [15:0] wbuf_be_r [1:0];
reg [1:0] wbuf_write_r = 'd0;
reg wbuf_wp_r = 'd0; // write buf write pointer
reg wbuf_rp_r = 'd0; // write buf read pointer
reg busy_reading_r = 'd0;
reg wait_rdata_valid_r = 'd0;
wire in_wreq;
reg ack_owed_r = 'd0;
// ----------------------------------------------------
// Access Buffer
// ----------------------------------------------------
assign in_wreq = i_req && i_write;
assign push = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted));
assign pop = o_valid && i_accepted && wbuf_used_r != 2'd0;
always @(posedge i_clk)
if (push && pop)
wbuf_used_r <= wbuf_used_r;
else if (push)
wbuf_used_r <= wbuf_used_r + 1'd1;
else if (pop)
wbuf_used_r <= wbuf_used_r - 1'd1;
always @(posedge i_clk)
if (push && in_wreq && !o_ack)
ack_owed_r = 1'd1;
else if (!i_req && o_ack)
ack_owed_r = 1'd0;
always @(posedge i_clk)
if (push)
begin
wbuf_wdata_r [wbuf_wp_r] <= i_wdata;
wbuf_addr_r [wbuf_wp_r] <= i_addr;
wbuf_be_r [wbuf_wp_r] <= i_write ? i_be : 16'hffff;
wbuf_write_r [wbuf_wp_r] <= i_write;
wbuf_wp_r <= !wbuf_wp_r;
end
always @(posedge i_clk)
if (pop)
wbuf_rp_r <= !wbuf_rp_r;
// ----------------------------------------------------
// Output logic
// ----------------------------------------------------
assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata;
assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write;
assign o_addr = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr;
assign o_be = wbuf_used_r != 2'd0 ? wbuf_be_r [wbuf_rp_r] : i_write ? i_be : 16'hffff;
assign o_ack = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop);
assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r;
assign o_rdata = i_rdata;
always@(posedge i_clk)
if (o_valid && !o_write)
busy_reading_r <= 1'd1;
else if (i_rdata_valid)
busy_reading_r <= 1'd0;
always@(posedge i_clk)
if (o_valid && !o_write && i_accepted)
wait_rdata_valid_r <= 1'd1;
else if (i_rdata_valid)
wait_rdata_valid_r <= 1'd0;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:47:43 03/06/2017
// Design Name: MUX32
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testMUX32.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MUX32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testMUX32;
// Inputs
reg [31:0] in;
reg [4:0] sel;
// Outputs
wire out;
// Instantiate the DESIGN Under Test (DUT)
MUX32 dut (
.in(in),
.sel(sel),
.out(out)
);
/*
//integer i;
initial begin
// Initialize Inputs
in = 0;
sel = 0;
for(sel=0;sel<=4'b1111 ;sel=sel+1) begin
// Wait 100 ns for global reset to finish
for(in=0;in<=32'hEEEEEEEE ;in=in+1) begin
#30;
end
end
// Add stimulus here
end
*/
initial begin
// Initialize Inputs
in = 0;
sel = 0;
#30;
in=32'hEEEEEEEE ;
sel=4'b1111 ;
#30;
in=32'hEE0E5EA0 ;
sel=4'b0010 ;
#30;
in=32'hEEEE5EEE ;
sel=4'b1011 ;
#30;
in=32'h000050A0 ;
sel=4'b1000 ;
#30;
in=32'hEE3EEEEE ;
sel=4'b1011 ;
#30;
in=32'h0AB000A0 ;
sel=4'b1011 ;
#30;
in=32'hEE0E5EEE ;
sel=4'b1001 ;
#30;
in=32'h0AB000B0 ;
sel=4'b0011 ;
#30;
in=32'hEE0E5EAE ;
sel=4'b0011 ;
#30;
in=32'hEA003070 ;
sel=4'b1111 ;
#30;
in=32'h100200E5 ;
sel=4'b0110 ;
#30;
in=32'hD0D020E0 ;
sel=4'b1001 ;
#30;
in=32'h0607A061 ;
sel=4'b0001 ;
#30;
in=32'h09005E00 ;
sel=4'b1000 ;
end
endmodule
|
module unified_mem(clk,rst_n,addr,re,we,wdata,rd_data,rdy);
/////////////////////////////////////////////////////////////////////
// Unified memory with 4-clock access times for reads & writes. //
// Organized as 16384 64-bit words (i.e. same width a cache line //
//////////////////////////////////////////////////////////////////
input clk,rst_n;
input re,we;
input [14:0] addr; // 2 LSB's are dropped since accessing as four 18-bit words
input [31:0] wdata;
output reg [31:0] rd_data;
output reg rdy; // deasserted when memory operation completed
reg [15:0] mem[0:65535]; // entire memory space at 16-bits wide
//////////////////////////
// Define states of SM //
////////////////////////
localparam IDLE = 2'b00;
localparam WRITE = 2'b01;
localparam READ = 2'b10;
reg [14:0] addr_capture; // capture the address at start of read
reg [1:0] state,nxt_state; // state register
reg [1:0] wait_state_cnt; // counter for 4-clock access time
reg clr_cnt,int_we,int_re; // state machine outputs
////////////////////////////////
// initial load of instr.hex //
//////////////////////////////
initial
$readmemh("instr.hex",mem);
/////////////////////////////////////////////////
// Capture address at start of read or write //
// operation to ensure address is held //
// stable during entire access time. //
/////////////////////////////////////////////
always @(posedge clk)
if (re | we)
addr_capture <= addr; // this is actual address used to access memory
//////////////////////////
// Model memory writes //
////////////////////////
always @(clk,int_we)
if (clk & int_we) // write occurs on clock high during 4th clock cycle
begin
mem[{addr_capture,1'b0}] <= wdata[15:0];
mem[{addr_capture,1'b1}] <= wdata[31:16];
end
/////////////////////////
// Model memory reads //
///////////////////////
always @(clk,int_re)
if (clk & int_re) // reads occur on clock high during 4th clock cycle
rd_data = {mem[{addr_capture,1'b1}],mem[{addr_capture,1'b0}]};
////////////////////////
// Infer state flops //
//////////////////////
always @(posedge clk, negedge rst_n)
if (!rst_n)
state <= IDLE;
else
state <= nxt_state;
/////////////////////////
// wait state counter //
///////////////////////
always @(posedge clk, negedge rst_n)
if (!rst_n)
wait_state_cnt <= 2'b00;
else
if (clr_cnt)
wait_state_cnt <= 2'b00;
else
wait_state_cnt <= wait_state_cnt + 1;
always @(state,re,we,wait_state_cnt)
begin
////////////////////////////
// default outputs of SM //
//////////////////////////
clr_cnt = 1; // hold count in reset
int_we = 0; // wait till 4th clock
int_re = 0; // wait till 4th clock
nxt_state = IDLE;
case (state)
IDLE : if (we) begin
clr_cnt = 0;
rdy = 0;
nxt_state = WRITE;
end
else if (re) begin
clr_cnt = 0;
rdy = 0;
nxt_state = READ;
end
else rdy = 1;
WRITE : if (&wait_state_cnt) begin
int_we = 1; // write completes and next state is IDLE
rdy = 1;
end
else begin
clr_cnt = 0;
rdy = 0;
nxt_state = WRITE;
end
default : if (&wait_state_cnt) begin // this state is READ
int_re = 1; // read completes and next state is IDLE
rdy = 1;
end
else begin
clr_cnt = 0;
rdy = 0;
nxt_state = READ;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long f[6][10010], b = 1; int main() { for (int i = 1; i <= 5; ++i) for (int j = 1; j <= (i == 5 ? 1 : 10000); ++j) { long long now = f[i - 1][j]; for (int k = 1; k <= j; ++k) now += f[i - 1][min(now + j + 1, 10000ll)] + 1; f[i][j] = now; } for (int i = 5, d; i >= 1; --i) { long long now = 0; printf( %lld , min(b, 10000ll)); for (int j = 1; j <= min(b, 10000ll); ++j) { now += f[i - 1][min(b + now, 10000ll)]; printf( %lld , b + now); ++now; } printf( n ); fflush(stdout); scanf( %d , &d); if (d == -1) break; else { now = 0; for (int j = 1; j <= d; ++j) now += f[i - 1][min(b + now, 10000ll)] + 1; b += now; } } } |
#include <bits/stdc++.h> using namespace std; void setIO(string NAME) {} inline long long gI() { char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); long long flag = 1, p = 0; if (c == - ) flag = -1, c = getchar(); while (c >= 0 && c <= 9 ) p = p * 10 + (c - 0 ), c = getchar(); return p * flag; } int gs(char* C) { char c = getchar(); while (c == || c == n ) c = getchar(); int l = 0; while (c != && c != n ) C[l++] = c, c = getchar(); C[l] = 0; return l; } template <class T> void debug(const T a, const int& n) { for (int i = 0; i < n; ++i) printf( %d%c , a[i], (i == n - 1) ? n : ); } const int inf = ~0U >> 1, maxn = 100000 + 10; int n, m; long long a[maxn]; vector<long long> b[maxn]; int main() { setIO( test ); n = gI(), m = gI(); long long ans = 0; for (int i = 0; i < m; ++i) { a[i] = gI(); if (i) ans += abs(a[i] - a[i - 1]); } long long MAX = 0; for (int i = 0; i < m; ++i) { if (i && a[i - 1] != a[i]) b[a[i]].push_back(a[i - 1]); if (i < m - 1 && a[i] != a[i + 1]) b[a[i]].push_back(a[i + 1]); } for (int i = 1; i <= n; ++i) if (b[i].size()) { sort(b[i].begin(), b[i].end()); int sz = b[i].size(); int m = (sz - 1) / 2; long long origin = 0, now = 0; for (int j = 0; j < sz; ++j) { origin += abs((long long)b[i][j] - i); now += abs(b[i][j] - b[i][m]); } MAX = max(MAX, origin - now); } ans -= MAX; cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFBBN_PP_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_PP_BLACKBOX_V
|
// bsg_delay_line
//
// new settings are delivered via bsg_tag_i
//
// the clock is designed to be atomically updated
// between any of its values without glitching.
//
// the order of components is:
//
// ADT, CDT, FDT --> feedback (and buffer to outside world)
//
// All three stages invert their outputs.
//
// All of the modules have delay circuits that clock their config
// flops right after the signal has passed through. All of them are
// configured to grab the new value after a negedge enters the beginning of
// of the ADT, but of course since the signal is inverted at each stage
// ADT and FDT do it on posege and CDT does it on negedge.
//
// We employ a MUXI4 that is part of the standard cell library
// that we verify to be glitch-free using spice simulation (presumably because it is based on a
// t-gate design). If the MUXI4 were made out of AND-OR circuits, care
// would have to be taken to make sure that the transitions occur when
// either all inputs are 0 or 1 to the MUXI4, depending on the implementation.
// For example, if the mux is AOI, triggered on negedge edge of input clock would
// be okay. Fortunately, we don't have to worry about this (and confirmed by spice.)
//
// We have verified this in TSMC 40 by running with sdf annotations.
//
// Gen 2 specific info (starting with 40nm) MBT 5-26-2018
//
// This Gen 2 clock generator has been slight redesigned in order to address the races
// in the gen 1 design that prevented automation.
//
// We use the bsg_tag_client_unsync implementation in order to reduce the load on
// the internally generated clock. Additionally, we separate out the we_r trigger
// signal so that it is explicitly set. This means that to set the frequency
// on average, three packets will need to be sent. First, a packet will be sent
// to set clock configuration bits. Then a packet will be sent to enable the we_r
// signal. Finally a packet will be sent to clear the we_r signal.
// This applies only for the oscillator programming.
//
// The trigger is synchronized inside the ADT; and then the synchronized signal
// is buffered and passed on to the CDT and then to the FDT, mirroring the
// flow of the clock signal through the units.
//
// The goal of this approach is to ensure that a new value is latched into the
// oscillator's configuration registers atomically, and during the first negative
// clock phase after a positive edge.
//
//
// The downsampler uses the normal interface.
//
//
// Gen 1 specific info (for reference)
//
// There is an implicit race between the bsg_tag's output fb_we_r (clocked on
// positive edge of FDT output) and these config flops that cannot be addressed
// in ICC because we cannot explicitly control timing between ICC-managed
// clocks and our internal oscillator clocks.
//
// A final check must be made on the 5 flops inside the adt / cdt / fdt
// to see that async reset drops and data inputs do not come too close
// to the appropriate clock edge. This could be verified via a script that
// processes the SDF file, but for now we pull the test trace up in DVE and
// manually check these points. Typically, the ADT is the closest
// call, where in MAX timing mode, the data changes about 481 ps before the
// positive edge of the flop's clock. With a setup time on the order of
// 261 ps, there is a slack of 220 ps. This path was originally a problem
// and it fixed by sending the clock out to the BTC at the beginning of
// the FDT as opposed to at the end. This gives more time for propagate
// through the ICC-generate clock tree for the BTC.
//
//
//
//
`timescale 1ps/1ps
`include "bsg_clk_gen.vh"
module bsg_dly_line
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input bsg_tag_s bsg_tag_i
,input bsg_tag_s bsg_tag_trigger_i
,input async_reset_i
,input clk_i
,output clk_o
);
wire fb_clk;
wire async_reset_neg = ~async_reset_i;
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s tag_r_async;
wire tag_trigger_r_async;
wire adt_to_cdt_trigger_lo, cdt_to_fdt_trigger_lo;
// this is a raw interface; and wires will toggle
// as the bits shift in. the wires are also
// unsynchronized with respect to the target domain.
bsg_tag_client_unsync
#(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(1)
) btc
(.bsg_tag_i(bsg_tag_i)
,.data_async_r_o(tag_r_async)
);
bsg_tag_client_unsync
#(.width_p(1)
,.harden_p(1)
) btc_trigger
(.bsg_tag_i(bsg_tag_trigger_i)
,.data_async_r_o(tag_trigger_r_async)
);
wire adt_lo, cdt_lo;
wire fb_clk_del;
// this adds some delay in the loop for RTL simulation
// should be ignored in synthesis
assign #4000 fb_clk_del = fb_clk;
wire clk_inv;
assign clk_inv = ~clk_i;
bsg_rp_clk_gen_atomic_delay_tuner adt
(.i(clk_inv)
,.we_async_i (tag_trigger_r_async )
,.we_inited_i(bsg_tag_trigger_i.en )
,.async_reset_neg_i(async_reset_neg )
,.sel_i(tag_r_async.adg[0] )
,.we_o(adt_to_cdt_trigger_lo )
,.o(adt_lo )
);
// instantatiate CDT (coarse delay tuner)
// this one inverts the output
// captures config state on negative edge of input clock
bsg_rp_clk_gen_coarse_delay_tuner cdt
(.i (adt_lo)
,.we_i (adt_to_cdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg )
,.sel_i (tag_r_async.cdt )
,.we_o (cdt_to_fdt_trigger_lo)
,.o (cdt_lo)
);
// instantiate FDT (fine delay tuner)
// captures config state on positive edge of (inverted) input clk
// non-inverting
bsg_rp_clk_gen_fine_delay_tuner fdt
(.i (cdt_lo)
,.we_i (cdt_to_fdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg)
,.sel_i (tag_r_async.fdt)
,.o (fb_clk) // in the actual critical loop
,.buf_o (clk_o) // outside this module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule // bsg_clk_gen_osc
`BSG_ABSTRACT_MODULE(bsg_dly_line)
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int n, q; string s; int dp[251][251][251]; int nxt[26][112345]; int len[3]; int chs[3][250]; template <class T, class U> inline void smax(T &a, U b) { a = a > b ? a : b; } template <class T, class U> inline void smin(T &a, U b) { a = a < b ? a : b; } int main() { std::ios::sync_with_stdio(false), std::cin.tie(0); cin >> n >> q; cin >> s; for (int i = 0; i < 26; i++) { nxt[i][n] = nxt[i][n + 1] = n; for (int j = n - 1; j >= 0; j--) if (s[j] == a + i) nxt[i][j] = j; else nxt[i][j] = nxt[i][j + 1]; } dp[0][0][0] = -1; for (int t = 0; t < q; t++) { char c; int group; cin >> c >> group; group -= 1; if (c == + ) { char ch; cin >> ch; chs[group][len[group]] = ch - a ; len[group]++; int i[3]; for (i[0] = group == 0 ? len[0] : 0; i[0] <= len[0]; i[0]++) for (i[1] = group == 1 ? len[1] : 0; i[1] <= len[1]; i[1]++) for (i[2] = group == 2 ? len[2] : 0; i[2] <= len[2]; i[2]++) { if (!i[0] && !i[1] && !i[2]) continue; dp[i[0]][i[1]][i[2]] = n; for (int k = 0; k < 3; k++) { if (i[k] > 0) { smin(dp[i[0]][i[1]][i[2]], nxt[chs[k][i[k] - 1]] [dp[i[0] - (0 == k)][i[1] - (1 == k)][i[2] - (2 == k)] + 1]); } } } } else { len[group]--; } cout << ((dp[len[0]][len[1]][len[2]] < n) ? Yes : No ) << n ; } cout << flush; return 0; } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module decodes video input streams on the DE boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_decoder_0 (
// Inputs
clk,
reset,
TD_CLK27,
TD_DATA,
TD_HS,
TD_VS,
clk27_reset,
stream_out_ready,
// Bidirectional
// Outputs
TD_RESET,
overflow_flag,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 7;
parameter OW = 15;
parameter FW = 17;
parameter PIXELS = 1280;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
input TD_VS;
input clk27_reset;
input stream_out_ready;
// Bidirectional
// Outputs
output TD_RESET;
output reg overflow_flag;
output [OW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire video_clk;
wire video_clk_reset;
wire [OW: 0] decoded_pixel;
wire decoded_startofpacket;
wire decoded_endofpacket;
wire decoded_valid;
wire [FW: 0] data_from_fifo;
wire [ 6: 0] fifo_used_words;
wire [ 6: 0] wrusedw;
wire wrfull;
wire rdempty;
// Internal Registers
reg reached_start_of_frame;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
overflow_flag <= 1'b0;
else if (decoded_valid & reached_start_of_frame & wrfull)
overflow_flag <= 1'b1;
end
// Internal Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
reached_start_of_frame <= 1'b0;
else if (decoded_valid & decoded_startofpacket)
reached_start_of_frame <= 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign TD_RESET = 1'b1;
assign stream_out_data = data_from_fifo[OW: 0];
assign stream_out_startofpacket = data_from_fifo[(FW - 1)];
assign stream_out_endofpacket = data_from_fifo[FW];
assign stream_out_empty = 1'b0;
assign stream_out_valid = ~rdempty;
// Internal Assignments
assign video_clk = TD_CLK27;
assign video_clk_reset = clk27_reset;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// NTSC Video In Decoding
altera_up_video_itu_656_decoder ITU_R_656_Decoder (
// Inputs
.clk (video_clk),
.reset (video_clk_reset),
.TD_DATA (TD_DATA),
.ready (decoded_valid & ~wrfull),
// Bidirectionals
// Outputs
.data (decoded_pixel),
.startofpacket (decoded_startofpacket),
.endofpacket (decoded_endofpacket),
.valid (decoded_valid)
);
altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (
// Inputs
.wrclk (video_clk),
.wrreq (decoded_valid & reached_start_of_frame & ~wrfull),
// .data ({1'b0, decoded_startofpacket, decoded_pixel}),
.data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}),
.rdclk (clk),
.rdreq (stream_out_valid & stream_out_ready),
// Bidirectionals
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (data_from_fifo),
.rdusedw (fifo_used_words),
.rdempty (rdempty)
);
defparam
Video_In_Dual_Clock_FIFO.DW = (FW + 1);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_4_V
`define SKY130_FD_SC_LP__NAND3_4_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_BLACKBOX_V
`define SKY130_FD_SC_LS__XOR3_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_BLACKBOX_V
|
/*64 bit wide byte addressable memory*/
module ememory(/*AUTOARG*/
// Outputs
wait_out, access_out, packet_out,
// Inputs
clk, reset, access_in, packet_in, wait_in
);
parameter DW = 32;
parameter AW = 32;
parameter MAW = 10;
parameter PW = 104;
//Basic Interface
input clk;
input reset;
//incoming read/write
input access_in;
input [PW-1:0] packet_in;
output wait_out; //pushback
//back to mesh (readback data)
output access_out;
output [PW-1:0] packet_out;
input wait_in; //pushback
wire [MAW-1:0] addr;
wire [63:0] din;
wire [63:0] dout;
wire en;
wire mem_rd;
wire mem_wr;
reg [7:0] wen;
//State
reg access_out;
reg write_out;
reg [1:0] datamode_out;
reg [3:0] ctrlmode_out;
reg [AW-1:0] dstaddr_out;
wire [AW-1:0] srcaddr_out;
wire [AW-1:0] data_out;
reg hilo_sel;
wire write_in;
wire [1:0] datamode_in;
wire [3:0] ctrlmode_in;
wire [AW-1:0] dstaddr_in;
wire [DW-1:0] data_in;
wire [AW-1:0] srcaddr_in;
packet2emesh p2e (
.access_out (),
.write_out (write_in),
.datamode_out (datamode_in[1:0]),
.ctrlmode_out (ctrlmode_in[3:0]),
.dstaddr_out (dstaddr_in[AW-1:0]),
.data_out (data_in[DW-1:0]),
.srcaddr_out (srcaddr_in[AW-1:0]),
.packet_in (packet_in[PW-1:0])
);
//Access-in
assign mem_rd = (access_in & ~write_in & ~wait_in);
assign mem_wr = (access_in & write_in );
assign en = mem_rd | mem_wr;
//Pushback Circuit (pass through problems?)
assign wait_out = access_in & wait_in;
//Address-in (shifted by three bits, 64 bit wide memory)
assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];
//Data-in (hardoded width)
assign din[63:0] =(datamode_in[1:0]==2'b11) ? {srcaddr_in[31:0],data_in[31:0]}:
{data_in[31:0],data_in[31:0]};
//Write mask
always@*
casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
//Byte
6'b100000 : wen[7:0] = 8'b00000001;
6'b100001 : wen[7:0] = 8'b00000010;
6'b100010 : wen[7:0] = 8'b00000100;
6'b100011 : wen[7:0] = 8'b00001000;
6'b100100 : wen[7:0] = 8'b00010000;
6'b100101 : wen[7:0] = 8'b00100000;
6'b100110 : wen[7:0] = 8'b01000000;
6'b100111 : wen[7:0] = 8'b10000000;
//Short
6'b10100? : wen[7:0] = 8'b00000011;
6'b10101? : wen[7:0] = 8'b00001100;
6'b10110? : wen[7:0] = 8'b00110000;
6'b10111? : wen[7:0] = 8'b11000000;
//Word
6'b1100?? : wen[7:0] = 8'b00001111;
6'b1101?? : wen[7:0] = 8'b11110000;
//Double
6'b111??? : wen[7:0] = 8'b11111111;
default : wen[7:0] = 8'b00000000;
endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
//Single ported memory
defparam mem.DW=2*DW;//TODO: really fixed to 64 bits
defparam mem.AW=MAW;
memory_sp mem(
// Inputs
.clk (clk),
.en (en),
.wen (wen[7:0]),
.addr (addr[MAW-1:0]),
.din (din[63:0]),
.dout (dout[63:0])
);
//Outgoing transaction
always @ (posedge clk)
access_out <= mem_rd;
//Other emesh signals "dataload"
always @ (posedge clk)
if(mem_rd)
begin
write_out <= 1'b1;
hilo_sel <= dstaddr_in[2];
datamode_out[1:0] <= datamode_in[1:0];
ctrlmode_out[3:0] <= ctrlmode_in[3:0];
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
end
assign srcaddr_out[AW-1:0] = (datamode_out[1:0]==2'b11) ? dout[63:32] :
32'b0;
assign data_out[DW-1:0] = hilo_sel ? dout[63:32] :
dout[31:0];
//Concatenate
emesh2packet e2p (.packet_out (packet_out[PW-1:0]),
.access_in (access_out),
.write_in (write_out),
.datamode_in (datamode_out[1:0]),
.ctrlmode_in (ctrlmode_out[3:0]),
.dstaddr_in (dstaddr_out[AW-1:0]),
.data_in (data_out[DW-1:0]),
.srcaddr_in (srcaddr_out[AW-1:0])
);
endmodule // emesh_memory
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; int n, k; int a[105], C[105]; double f[105][105], s1[105][105], s2[105][105], s3[105][105]; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) f = -1; ch = getchar(); if (ch == -1) return 0; } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline void write(int x) { if (x < 0) { putchar( - ); x = -x; } if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } double ans; int main() { n = read(), k = read(), k = min(k, 900); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) f[i][j] = a[i] > a[j]; for (int i = 1; i <= n; i++) C[i] = C[i - 1] + i; while (k--) { for (int j = 1; j <= n; j++) { for (int i = 1; i <= j - 1; i++) s1[i][j] = s1[i - 1][j] + f[i][j]; for (int i = 1; i <= j - 1; i++) s1[i][j] += s1[i - 1][j]; } for (int i = n; i >= 1; i--) { for (int j = n; j >= i + 1; j--) s2[i][j] = s2[i][j + 1] + f[i][j]; for (int j = n; j >= i + 1; j--) s2[i][j] += s2[i][j + 1]; } for (int j = 0; j <= n - 1; j++) { for (int i = 1; i <= n - j; i++) s3[i][j] = s3[i - 1][j] + f[i][i + j]; for (int i = 1; i <= n - j; i++) s3[i][j] += s3[i - 1][j]; } for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) f[i][j] *= C[i - 1] + C[j - i - 1] + C[n - j], f[i][j] += s1[j - 1][j] - s1[j - i - 1][j] - s1[i - 1][j] + s2[i][i + 1] - s2[i][j + 1] - s2[i][n + 2 - j + i] - s3[n + i - j][j - i] + s3[n - j][j - i] + s3[i - 1][j - i], f[i][j] = (f[i][j] + i * (n + 1 - j)) / C[n]; } for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) ans += f[i][j]; printf( %.9lf n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007LL; const int N = 10; char str[N][N]; int n = 8, ans, way[4][2] = {2, 2, 2, -2, -2, 2, -2, -2}; int flag[N][N][N][N]; void dfs(int x, int y, int u, int v) { flag[x][y][u][v] = 1; if (x == u && v == y && str[x][y] != # ) { ans = 1; return; } if (ans) return; for (int i = 0; i < 4; i++) { int xx = x + way[i][0]; int yy = y + way[i][1]; if (xx >= 0 && xx < n && yy >= 0 && yy < n) { for (int j = 0; j < 4; j++) { int uu = u + way[j][0]; int vv = v + way[j][1]; if (uu >= 0 && uu < n && vv >= 0 && vv < n) { if (!flag[xx][yy][uu][vv]) { dfs(xx, yy, uu, vv); } } } } } } int main() { int t; cin >> t; while (t--) { int x = -1, y = -1, u = -1, v = -1; for (int i = 0; i < n; i++) { cin >> str[i]; for (int j = 0; j < n; j++) { if (str[i][j] == K ) { if (x == -1) { x = i; y = j; } else u = i, v = j; str[i][j] = . ; } } } ans = 0; memset(flag, 0, sizeof(flag)); dfs(x, y, u, v); puts(ans ? YES : NO ); } return 0; } |
#include <bits/stdc++.h> using namespace std; void optIO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const long long mod = 1e9 + 7, mod2 = 998244353, mod3 = 1e9 + 9; long long p[5020], pp = 31, hh[5020]; long long p2[5020], pp2 = 37, hh2[5020]; int dp[5020]; bool can[5020][5020]; map<long long, bool> ms; void solve() { int n, a, b; cin >> n >> a >> b; string s; cin >> s; p[0] = 1; p2[0] = 1; for (int i = 1; i < n + 1; ++i) { p[i] = (p[i - 1] * pp) % mod; p2[i] = (p2[i - 1] * pp2) % mod2; hh[i] = (hh[i - 1] + (s[i - 1] - a + 1) * p[i]) % mod; hh2[i] = (hh2[i - 1] + (s[i - 1] - a + 1) * p2[i]) % mod2; } for (int j = 1; j < n + 1; ++j) { for (int i = 1; i < n + 1; ++i) { if (i - 2 * j < 0) continue; long long y = ((hh[i - j] - hh[i - 2 * j] + mod) % mod * p[n - (i - j)]) % mod; long long y2 = ((hh2[i - j] - hh2[i - 2 * j] + mod2) % mod2 * p2[n - (i - j)]) % mod2; ms[y * mod2 + y2] = 1; long long x = ((hh[i] - hh[i - j] + mod) % mod * p[n - i]) % mod; long long x2 = ((hh2[i] - hh2[i - j] + mod2) % mod2 * p2[n - i]) % mod2; if (ms.find(x * mod2 + x2) != ms.end()) can[i][j] = 1; } ms.clear(); } for (int i = 1; i < n + 1; ++i) { dp[i] = dp[i - 1] + a; for (int j = 1; j < i + 1; ++j) { if (can[i][j]) dp[i] = min(dp[i], dp[i - j] + b); } } cout << dp[n] << n ; } int main() { optIO(); int t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) using namespace std; template <typename T1, typename T2> void ckmin(T1 &a, T2 b) { if (a > b) a = b; } template <typename T1, typename T2> void ckmax(T1 &a, T2 b) { if (a < b) a = b; } int read() { int x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f |= ch == - , ch = getchar(); while (isdigit(ch)) x = 10 * x + ch - 0 , ch = getchar(); return f ? -x : x; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) print(x / 10); putchar(x % 10 + 0 ); } template <typename T> void print(T x, char let) { print(x), putchar(let); } const int mod = 998244353; const int G = 3, Gi = 332748118; int add(int x, int y) { if ((x += y) >= mod) x -= mod; return x; } int sub(int x, int y) { if ((x -= y) < 0) x += mod; return x; } int qpow(int a, int b = mod - 2) { int res = 1; while (b > 0) { if (b & 1) res = 1ll * res * a % mod; a = 1ll * a * a % mod; b >>= 1; } return res; } namespace Poly { vector<int> Rev, W; int lim, L; void getR(int len) { lim = 1, L = 0; while (lim <= len) lim <<= 1, L++; Rev.resize(lim), W.resize(lim), W[0] = 1; for (int i = 0; i < lim; i++) Rev[i] = (Rev[i >> 1] >> 1) | ((i & 1) << L - 1); } void wf(vector<int> &a) { int n = a.size(); for (int i = 0; i < n; i++) a[i] = 1ll * (i + 1) * a[i + 1] % mod; a[n - 1] = 0; } void jf(vector<int> &a) { int n = a.size(); for (int i = n - 1; i >= 1; i--) a[i] = 1ll * a[i - 1] * qpow(i) % mod; a[0] = 0; } void NTT(vector<int> &a, int opt) { for (int i = 0; i < lim; i++) if (i < Rev[i]) swap(a[i], a[Rev[i]]); for (int mid = 1; mid < lim; mid <<= 1) { int Wn = qpow(opt == 1 ? G : Gi, (mod - 1) / (mid << 1)); for (int k = 1; k < mid; k++) W[k] = 1ll * W[k - 1] * Wn % mod; for (int j = 0; j < lim; j += mid << 1) { for (int k = 0; k < mid; k++) { int x = a[j + k], y = 1ll * W[k] * a[j + k + mid] % mod; a[j + k] = add(x, y); a[j + k + mid] = sub(x, y); } } } if (opt == -1) { int linv = qpow(lim); for (int i = 0; i < lim; i++) a[i] = 1ll * a[i] * linv % mod; } } vector<int> operator*(vector<int> a, vector<int> b) { int len = a.size() + b.size() - 1; getR(len); a.resize(lim), b.resize(lim); NTT(a, 1), NTT(b, 1); for (int i = 0; i < lim; i++) a[i] = 1ll * a[i] * b[i] % mod; NTT(a, -1); a.resize(len); return a; } vector<int> Inv(vector<int> a) { if ((int(a.size())) == 1) return vector<int>(1, qpow(a[0])); int len = a.size(); vector<int> ta = a; ta.resize((len + 1) / 2); vector<int> tb = Inv(ta); getR(2 * len), a.resize(lim), tb.resize(lim); NTT(a, 1), NTT(tb, 1); for (int i = 0; i < lim; i++) tb[i] = 1ll * tb[i] * (mod + 2 - 1ll * a[i] * tb[i] % mod) % mod; NTT(tb, -1); tb.resize(len); return tb; } vector<int> Ln(vector<int> a) { vector<int> ta = a; wf(ta); int len = a.size(); a = ta * Inv(a), jf(a); a.resize(len); return a; } vector<int> Exp(vector<int> a) { if ((int(a.size())) == 1) return vector<int>(1, 1); int len = a.size(); vector<int> ta = a; ta.resize((len + 1) / 2); vector<int> tb = Exp(ta); tb.resize(len); vector<int> Lnb = Ln(tb); assert(Lnb.size() == len); for (int i = 0; i < len; i++) Lnb[i] = (a[i] - Lnb[i] + mod) % mod; Lnb[0] = (Lnb[0] + 1) % mod; tb = tb * Lnb; tb.resize(len); return tb; } } // namespace Poly using namespace Poly; const int N = 250005; const int B = 15; vector<int> adj[N]; int n; int son[N]; void dfs1(int u, int fa) { for (auto v : adj[u]) { if (v == fa) continue; son[u]++; dfs1(v, u); } } int two[N], len; vector<int> solve(int l, int r) { if (l > r) return {1}; if (l == r) return {1, mod - two[l]}; int mid = l + r >> 1; return solve(l, mid) * solve(mid + 1, r); } int fac[N], inv[N]; int fuck[N]; int main() { n = read(); inv[1] = 1; for (int i = 2; i <= n; i++) inv[i] = 1ull * (mod - mod / i) * inv[mod % i] % mod; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = 1ull * fac[i - 1] * i % mod; for (int i = 1; i <= n - 1; i++) { int u = read(), v = read(); adj[u].push_back(v), adj[v].push_back(u); } dfs1(1, 0); vector<int> ONE(n + 1); for (int i = 1; i <= n; i++) { if (son[i] > B) { two[++len] = son[i]; } else { fuck[son[i]]++; } } for (int i = 1; i <= B; i++) { int coef = 1; for (int j = 1; j <= n; j++) { coef = 1ull * coef * i % mod; ONE[j] = sub(ONE[j], 1ull * fuck[i] * coef % mod * inv[j] % mod); } } ONE = Exp(ONE); vector<int> TWO = solve(1, len); vector<int> f = ONE * TWO; int ans = 0; for (int i = 0; i <= n - 1; i++) ans = (ans + 1ll * fac[n - i] * f[i]) % mod; print(ans, n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_SIZE = 200010; pair<int, int> arr[MAX_SIZE], backup[MAX_SIZE]; long long prefix[MAX_SIZE]; int N; void sortX(int l, int r) { if (l >= r) return; int mi = (l + r) / 2; sortX(l, mi); sortX(mi + 1, r); int i = l, j = mi + 1, k = l; while (i <= mi && j <= r) { if (arr[i] < arr[j]) { backup[k++] = arr[i++]; } else { backup[k++] = arr[j++]; } } while (i <= mi) { backup[k++] = arr[i++]; } while (j <= r) { backup[k++] = arr[j++]; } for (int i = l; i <= r; i++) { arr[i] = backup[i]; } } int lowerBound(int l, int r, int val) { while (l <= r) { int mi = (l + r) / 2; if (arr[mi].second <= val) { l = mi + 1; } else { r = mi - 1; } } int mi = (l + r) / 2; if (mi >= l && arr[mi].second > val) return mi - 1; return mi; } long long mergeSortV(int l, int r) { if (l >= r) return 0; int mi = (l + r) / 2; long long left = mergeSortV(l, mi); long long right = mergeSortV(mi + 1, r); long long mix = 0LL; prefix[l] = 0LL; for (int i = l; i <= mi; i++) { prefix[i + 1] = prefix[i] + (long long)arr[i].first; } for (int i = mi + 1; i <= r; i++) { int pos = lowerBound(l, mi, arr[i].second); long long cnt = pos - l + 1; mix += ((long long)arr[i].first * cnt - (prefix[pos + 1] - prefix[l])); } int i = l, j = mi + 1, k = l; while (i <= mi && j <= r) { if (arr[i].second < arr[j].second) { backup[k++] = arr[i++]; } else { backup[k++] = arr[j++]; } } while (i <= mi) { backup[k++] = arr[i++]; } while (j <= r) { backup[k++] = arr[j++]; } for (i = l; i <= r; i++) { arr[i] = backup[i]; } return left + right + mix; } long long solveBruteforce() { long long sum = 0LL; for (int i = 0; i < N; i++) { for (int j = i + 1; j < N; j++) { if (arr[i].second > arr[j].second) { sum += (long long)max(arr[i].first - arr[j].first, 0); } else if (arr[i].second < arr[j].second) { sum += (long long)max(arr[j].first - arr[i].first, 0); } else { sum += (long long)max(arr[j].first - arr[i].first, arr[i].first - arr[j].first); } } } return sum; } int main() { cin >> N; for (int i = 0; i < N; i++) { int x; cin >> x; arr[i].first = x; } for (int i = 0; i < N; i++) { int v; cin >> v; arr[i].second = v; } sortX(0, N - 1); cout << mergeSortV(0, N - 1) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<pair<long long, long long>, int> > island; set<pair<long long, long long> > bridge; int ans[200100]; int main() { int n, m; long long l, r, prevl, prevr, a; cin >> n >> m; cin >> prevl >> prevr; for (int i = 1; i < n; i++) { cin >> l >> r; island.push_back(pair<pair<long long, long long>, int>( pair<long long, long long>(r - prevl, l - prevr), i - 1)); prevl = l; prevr = r; } sort(island.begin(), island.end()); for (int i = 0; i < m; i++) { cin >> a; bridge.insert(pair<long long, long long>(a, i + 1)); } bridge.insert(pair<long long, long long>(1e19, -1)); set<pair<long long, long long> >::iterator point; long long lastl, lastr; int idx; for (vector<pair<pair<long long, long long>, int> >::iterator it = island.begin(); it != island.end(); ++it) { lastr = it->first.first; lastl = it->first.second; idx = it->second; point = bridge.lower_bound(pair<long long, long long>(lastl, -1)); if (point->first > lastr) { cout << No ; return 0; } else { ans[idx] = point->second; bridge.erase(point); } } cout << Yes n ; for (int i = 0; i < n - 1; i++) { cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int limite = 1000000; int n; long long int a[limite]; long long int suma[limite]; map<long long int, int> cuantos; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i + n] = a[i]; } for (int i = 1; i <= 2 * n; i++) suma[i] = suma[i - 1] + a[i]; for (int i = 1; i <= n; i++) cuantos[suma[i]]++; int sol = n; for (int i = 1; i <= n; i++) { sol = min(sol, n - cuantos[suma[i - 1]]); cuantos[suma[i]]--; cuantos[suma[i + n]]++; } cout << sol << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); vector<int> vet, mat; int n, x; cin >> n; for (int i = 0; i < n; i++) { cin >> x; if (x != 0) vet.push_back(x); } for (int i = 0; i < n; i++) { cin >> x; if (x != 0) mat.push_back(x); } int aux = 0; if (n <= 3) { cout << YES ; } else { int r; for (int i = 0; i < n - 1; i++) { if (mat[i] == vet[0]) { r = i; break; } } for (int i = 0; i < n - 1; i++) { int l = r + i; if (l >= n - 1) l -= (n - 1); if (vet[i] != mat[l]) { aux = 1; break; } } if (aux) { cout << NO ; } else cout << YES ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 5; const long long linf = 1e18 + 5; const int mod = 1e9 + 7; const int N = 100 + 5; const int M = 10; int n, a[M], C[N][N], dp[M][N]; int f(int cur, int n) { if (cur == M) return !n; int &r = dp[cur][n]; if (r != -1) return r; r = 0; for (int i = a[cur]; i <= n; i++) r = (r + (long long)f(cur + 1, n - i) * C[n][i] % mod) % mod; return r; } int main() { ios ::sync_with_stdio(0); memset(dp, -1, sizeof(dp)); C[0][0] = 1; for (int i = 1; i <= N - 1; i++) { C[i][0] = 1; for (int j = 1; j <= N - 1; j++) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % mod; } cin >> n; for (int i = 0; i <= 9; i++) cin >> a[i]; int st = a[0]; int ans = 0; for (int i = 1; i <= n; i++) { a[0] = st; memset(dp, -1, sizeof(dp)); ans += f(0, i); if (a[0]) a[0]--; memset(dp, -1, sizeof(dp)); ans -= f(0, i - 1); ans = (ans % mod + mod) % mod; } cout << ans << n ; return 0; } |
//----------------------------------------------------------------------------
//-- Ejemplo de uso del receptor serie
//-- Se hace eco de todos los caracteres recibidos. Ademas los 4 bits menos
//-- significativos se sacan por los leds de la IceStick
//----------------------------------------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Top design
module echo(input wire clk, //-- Reloj del sistema
input wire rx, //-- Linea de recepcion serie
output wire tx //-- Linea de transmision serie
);
//-- Parametro: Velocidad de transmision
localparam BAUD = `B115200;
//-- Señal de dato recibido
wire rcv;
//-- Datos recibidos
wire [7:0] data;
//-- Señal de reset
reg rstn = 0;
//-- Señal de transmisor listo
wire ready;
//-- Inicializador
always @(posedge clk)
rstn <= 1;
//-- Instanciar la unidad de recepcion
uart_rx #(BAUD)
RX0 (.clk(clk), //-- Reloj del sistema
.rstn(rstn), //-- Señal de reset
.rx(rx), //-- Linea de recepción de datos serie
.rcv(rcv), //-- Señal de dato recibido
.data(data) //-- Datos recibidos
);
//-- Instanciar la unidad de transmision
uart_tx #(BAUD)
TX0 ( .clk(clk), //-- Reloj del sistema
.rstn(rstn), //-- Reset global (activo nivel bajo)
.start(rcv), //-- Comienzo de transmision
.data(data), //-- Dato a transmitir
.tx(tx), //-- Salida de datos serie (hacia el PC)
.ready(ready) //-- Transmisor listo / ocupado
);
endmodule
|
#include <bits/stdc++.h> const int mod = 1e9 + 7; const int p_mod = 998244353; using namespace std; long long fast_pow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % mod; b >>= 1; a = (a * a) % mod; } return res % mod; } const int N = 1e5 + 5; stack<char> s; char str[N]; int cnt = 0; int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); cin >> (str + 1); int len = strlen(str + 1); for (int i = 1; i <= len; i++) { if (!s.empty() && s.top() == str[i]) { s.pop(); cnt++; } else s.push(str[i]); } if (cnt % 2) { cout << Yes << endl; } else cout << No << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, l, r, x, y, o, e, w, z, b[50000], aa, bb, ans; vector<int> vec; map<int, int> ma; int main() { ios_base ::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> l >> r >> x >> y; if (y % x != 0) { cout << 0 << endl; return 0; } else y /= x; for (int i = 2; i * i <= y; i++) if (y % i == 0) { vec.push_back(i); while (y % i == 0) { y /= i; ma[i]++; } } if (y > 1) { vec.push_back(y); ma[y]++; } z = vec.size(); for (int i = 0; i < (1 << z); i++) { w = i; for (int j = 0; j < z; j++) b[j] = 0; o = 0; while (w) { b[o] = w & 1; w >>= 1; o++; } aa = bb = 1; for (int j = 0; j < z; j++) if (b[j] == 1) { e = ma[vec[j]]; for (int h = 1; h <= e; h++) aa *= vec[j]; } else { e = ma[vec[j]]; for (int h = 1; h <= e; h++) bb *= vec[j]; } if (l <= aa * x && aa * x <= r && l <= bb * x && bb * x <= r) ans++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; #define all(x) (x).begin(), (x).end() #define fast ios::sync_with_stdio(false);cin.tie(0); typedef long long ll; typedef long double ld; typedef unsigned long long ull; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); map<pair<int,int>,bool> e[3]; int main(){ fast vector<int> n(4); for(int i=0;i<4;i++)cin>>n[i]; vector<vector<int>> c(4); for(int i=0;i<4;i++){ c[i].resize(n[i]); for(int j=0;j<n[i];j++)cin>>c[i][j]; } for(int i=0;i<3;i++){ int m; cin>>m; for(int j=0;j<m;j++){ int a,b; cin>>a>>b; a--;b--; // cerr << i << << a << << b << n ; e[i][{a,b}] = true; } } vector<pair<ll,int>> dp,nxt; for(int i=0;i<n[3];i++)dp.push_back({c[3][i],i}); for(int lvl=2;lvl>=0;lvl--){ sort(all(dp)); for(int i=0;i<n[lvl];i++){ for(int j=0;j<dp.size();j++){ if(e[lvl][{i,dp[j].second}])continue; nxt.push_back({c[lvl][i] + dp[j].first , i}); break; } } dp = nxt; nxt.clear(); } sort(all(dp)); if(dp.empty())cout << -1 << n ; else cout << dp[0].first << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 200200; int n; long long b[N], c[N]; long long a[N]; int dg[32]; void solve() { memset((dg), (0), sizeof(dg)); long long sum = 0, suma = 0; for (int i = (int)0; i < (int)n; ++i) sum += b[i] + c[i]; suma = sum / (n + n); bool flag = 1; for (int i = (int)0; i < (int)n; ++i) { a[i] = (b[i] + c[i] - suma) / n; if (a[i] < 0) flag = 0; } if (!flag) { cout << -1 ; return; } for (int i = (int)0; i < (int)n; ++i) { int t = 0; for (long long x = a[i]; x; x >>= 1) dg[t++] += (x & 1); } for (int i = (int)0; i < (int)n; ++i) { long long x = a[i], sumi = 0; for (int j = (int)0; j < (int)32; ++j) if ((x >> j) & 1) sumi += (1 << j) * dg[j]; if (sumi != b[i]) { flag = 0; break; } } if (!flag) { cout << -1 ; return; } for (int i = (int)0; i < (int)n; ++i) { long long x = a[i], sumi = 0; for (int j = (int)0; j < (int)32; ++j) { if ((x >> j) & 1) sumi += (1 << j) * n; else sumi += (1 << j) * dg[j]; } if (sumi != c[i]) { flag = 0; break; } } if (!flag) { cout << -1 ; return; } for (int i = (int)0; i < (int)n; ++i) cout << a[i] << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = (int)0; i < (int)n; ++i) cin >> b[i]; for (int i = (int)0; i < (int)n; ++i) cin >> c[i]; solve(); return 0; } |
`include "alu_ops.vh"
`include "rv32_opcodes.vh"
`default_nettype none
module alu(
input wire [`ALU_OP_WIDTH-1:0] op,
input wire [`XPR_LEN-1:0] in1,
input wire [`XPR_LEN-1:0] in2,
output reg [`XPR_LEN-1:0] out
);
wire [`SHAMT_WIDTH-1:0] shamt;
assign shamt = in2[`SHAMT_WIDTH-1:0];
always @(*) begin
case (op)
`ALU_OP_ADD : out = in1 + in2;
`ALU_OP_SLL : out = in1 << shamt;
`ALU_OP_XOR : out = in1 ^ in2;
`ALU_OP_OR : out = in1 | in2;
`ALU_OP_AND : out = in1 & in2;
`ALU_OP_SRL : out = in1 >> shamt;
`ALU_OP_SEQ : out = {31'b0, in1 == in2};
`ALU_OP_SNE : out = {31'b0, in1 != in2};
`ALU_OP_SUB : out = in1 - in2;
`ALU_OP_SRA : out = $signed(in1) >>> shamt;
`ALU_OP_SLT : out = {31'b0, $signed(in1) < $signed(in2)};
`ALU_OP_SGE : out = {31'b0, $signed(in1) >= $signed(in2)};
`ALU_OP_SLTU : out = {31'b0, in1 < in2};
`ALU_OP_SGEU : out = {31'b0, in1 >= in2};
default : out = 0;
endcase // case op
end
endmodule // alu
`default_nettype wire
|
/**
* @module MEM_WB
* @author sabertazimi
* @email
* @brief MEM_WB pipeline register
* @input clk clock signal
* @input rst reset signal
* @input en load enable signal
* @input MEM_PC PC value in MEM stage
* @input MEM_IR instruction value in MEM stage
* @input MEM_writetolo writetolo signal in MEM stage
* @input MEM_regwe regwe signal in MEM stage
* @input MEM_ramtoreg ramtoreg signal in MEM stage
* @input MEM_lotoreg lotoreg signal in MEM stage
* @input MEM_syscall syscall signal in MEM stage
* @input MEM_ramdata ramdata value in MEM stage
* @input MEM_result result value in MEM stage
* @input MEM_RW RW value in MEM stage
* @output WB_PC PC value in WB stage
* @output WB_IR instruction value in WB stage
* @output WB_writetolo writetolo signal in WB stage
* @output WB_regwe regwe signal in WB stage
* @output WB_ramtoreg ramtoreg signal in WB stage
* @output WB_lotoreg lotoreg signal in WB stage
* @output WB_syscall syscall signal in WB stage
* @output WB_ramdata ramdata value in WB stage
* @output WB_result result value in WB stage
* @output WB_RW RW value in WB stage
*/
module MEM_WB
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input [DATA_WIDTH-1:0] MEM_PC,
input [DATA_WIDTH-1:0] MEM_IR,
input MEM_writetolo,
input MEM_regwe,
input MEM_ramtoreg,
input MEM_lotoreg,
input MEM_syscall,
input [DATA_WIDTH-1:0] MEM_ramdata,
input [DATA_WIDTH-1:0] MEM_result,
input [4:0] MEM_RW,
output [DATA_WIDTH-1:0] WB_PC,
output [DATA_WIDTH-1:0] WB_IR,
output WB_writetolo,
output WB_regwe,
output WB_ramtoreg,
output WB_lotoreg,
output WB_syscall,
output [DATA_WIDTH-1:0] WB_ramdata,
output [DATA_WIDTH-1:0] WB_result,
output [4:0] WB_RW
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) PC (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_PC),
.dout(WB_PC)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) IR (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_IR),
.dout(WB_IR)
);
register #(
.DATA_WIDTH(1)
) writetolo (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_writetolo),
.dout(WB_writetolo)
);
register #(
.DATA_WIDTH(1)
) regwe (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_regwe),
.dout(WB_regwe)
);
register #(
.DATA_WIDTH(1)
) ramtoreg (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_ramtoreg),
.dout(WB_ramtoreg)
);
register #(
.DATA_WIDTH(1)
) lotoreg (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_lotoreg),
.dout(WB_lotoreg)
);
register #(
.DATA_WIDTH(1)
) syscall (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_syscall),
.dout(WB_syscall)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) ramdata (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_ramdata),
.dout(WB_ramdata)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) result (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_result),
.dout(WB_result)
);
register #(
.DATA_WIDTH(5)
) RW (
.clk(clk),
.rst(rst),
.en(en),
.din(MEM_RW),
.dout(WB_RW)
);
endmodule // MEM_WB
|
#include <bits/stdc++.h> using namespace std; string itosm(long long x) { if (x == 0) return 0 ; string ans = ; while (x > 0) { ans += ((x % 10) + 0 ); x /= 10; } reverse(ans.begin(), ans.end()); return ans; } long long stoim(string str) { long long ans = 0; long long k = 1; for (int i = str.length() - 1; i >= 0; i--) { ans += (str[i] - 0 ) * k; k *= 10; } return ans; } const long long infll = 1e18 + 3; const int inf = 1009000999; const double eps = 1e-6; const int maxn = 1e6 + 77; const int baseint = 1000200013; const long long basell = 1e18 + 3; const long double PI = acos(-1.0); int main() { srand(228228); ios_base::sync_with_stdio(0); ; string t, s, p = ; cin >> t >> s; int n = s.length(); while (p.length() != n) p += 0 ; int cnt = 0; for (int i = (0); i < (n); i++) { if (s[i] == t[i]) p[i] = s[i]; else cnt++; } if (cnt % 2) { cout << impossible ; return 0; } cnt = 0; for (int i = (0); i < (n); i++) { if (s[i] != t[i]) { if (cnt <= 0) { p[i] = s[i]; cnt++; } else { p[i] = t[i]; cnt--; } } } cout << p; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:17:23 10/24/2016
// Module Name: ALU_CONTROL_tb
// Project Name: MIPS
// Description: Testing MIPS ALU_CONTROL module in the EXECUTE stage.
//
// Dependencies: ALU_CONTROL.v
//
////////////////////////////////////////////////////////////////////////////////
module ALU_CONTROL_tb;
// Inputs
reg [5:0] funct;
reg [1:0] alu_op;
// Outputs
wire [2:0] select;
// Instantiate the module.
ALU_CONTROL alu_control(.funct(funct), .alu_op(alu_op), .select(select));
initial begin
// Initialize Inputs
funct = 0;
alu_op = 0;
// Wait 100 ns for global reset to finish
#100;
alu_op = 2'b00;
funct = 6'b100000;
$monitor("ALUop = %b\tfunct = %b\tselect = %b", alu_op, funct, select);
#1
alu_op = 2'b01;
funct = 6'b100000;
#1
alu_op = 2'b10;
funct = 6'b100000;
#1
funct = 6'b100010;
#1
funct = 6'b100100;
#1
funct = 6'b100101;
#1
funct = 6'b101010;
#1
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, ans; string a; int main() { cin >> a; ans = a.size(); long long t = 0; for (int i = 0; i < a.size(); i++) { if (a[i] == ) ) t--; else t++; if (t < 0) { t = 0; ans--; } } cout << ans - t << endl; return 0; } |
`timescale 1ns/1ns
module ddr2_ctrl(
sys_rst_n,
ddr2_clk,
local_init_done,
local_ready,
local_address,
local_read_req,
local_write_req,
local_wdata,
local_be,
local_size,
local_rdata,
local_rdata_valid,
local_burstbegin,
um2ddr_wrclk,
um2ddr_wrreq,
um2ddr_data,
um2ddr_ready,
um2ddr_command_wrreq,
um2ddr_command,
ddr2um_rdclk,
ddr2um_rdreq,
ddr2um_rdata,
ddr2um_valid_rdreq,
ddr2um_valid_rdata,
ddr2um_valid_empty
);
input sys_rst_n;
input ddr2_clk;
input local_ready;
input [31:0] local_rdata;
input local_rdata_valid;
input local_init_done;
output[25:0] local_address;
output local_write_req;
output local_read_req;
output local_burstbegin;
output[31:0] local_wdata;
output[3:0] local_be;
output[3:0] local_size;
input um2ddr_wrclk;
input um2ddr_wrreq;
input [127:0] um2ddr_data;
output um2ddr_ready;
input um2ddr_command_wrreq;
input [33:0] um2ddr_command;
input ddr2um_rdclk;
input ddr2um_rdreq;
output[127:0] ddr2um_rdata;
input ddr2um_valid_rdreq;
output[6:0] ddr2um_valid_rdata;
output ddr2um_valid_empty;
ddr2_ctrl_input ddr2_ctrl_input(
.sys_rst_n(sys_rst_n),
.ddr2_clk(ddr2_clk),
.local_init_done(local_init_done),
.local_ready(local_ready),
.local_address(local_address),
.local_read_req(local_read_req),
.local_write_req(local_write_req),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_burstbegin(local_burstbegin),
.um2ddr_wrclk(um2ddr_wrclk),
.um2ddr_wrreq(um2ddr_wrreq),
.um2ddr_data(um2ddr_data),
.um2ddr_ready(um2ddr_ready),
.um2ddr_command_wrreq(um2ddr_command_wrreq),
.um2ddr_command(um2ddr_command),
.rd_ddr2_size(rd_ddr2_size),
.rd_ddr2_size_wrreq(rd_ddr2_size_wrreq),
.read_permit(read_permit)
);
wire[6:0] rd_ddr2_size;
wire rd_ddr2_size_wrreq;
wire read_permit;
ddr2_ctrl_output ddr2_ctrl_output(
.sys_rst_n(sys_rst_n),
.ddr2_clk(ddr2_clk),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.ddr2um_rdclk(ddr2um_rdclk),
.ddr2um_rdreq(ddr2um_rdreq),
.ddr2um_rdata(ddr2um_rdata),
.ddr2um_valid_rdreq(ddr2um_valid_rdreq),
.ddr2um_valid_rdata(ddr2um_valid_rdata),
.ddr2um_valid_empty(ddr2um_valid_empty),
.rd_ddr2_size(rd_ddr2_size),
.rd_ddr2_size_wrreq(rd_ddr2_size_wrreq),
.read_permit(read_permit)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_71x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_71x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [70:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [70:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [70:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [70:0] q = sub_wire2[70:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 71,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "71"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "71"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "71"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 71 0 INPUT NODEFVAL data[70..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 71 0 OUTPUT NODEFVAL q[70..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 71 0 data 0 0 71 0
// Retrieval info: CONNECT: q 0 0 71 0 @q 0 0 71 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_71x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin >> n; vector<long long> q(1000100, 0); for (long long i = 0; i < n; i++) { long long t; cin >> t; q[t]++; } long long ans = 0; for (long long i = 0; (i < 1000100 - 1); ++i) { if (q[i] % 2 == 1) ans++; q[i + 1] += q[i] / 2; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { ~debug() { cerr << endl; } template <class c> typename enable_if<sizeof dud<c>(0) != 1, debug&>::type operator<<(c i) { cerr << boolalpha << i; return *this; } template <class c> typename enable_if<sizeof dud<c>(0) == 1, debug&>::type operator<<(c i) { return *this << range(begin(i), end(i)); } template <class c, class b> debug& operator<<(pair<b, c> d) { return *this << ( << d.first << , << d.second << ) ; } template <class c> debug& operator<<(rge<c> d) { *this << [ ; for (auto it = d.b; it != d.e; ++it) *this << , + 2 * (it == d.b) << *it; return *this << ] ; } }; long long mod = 1e9 + 7; int INF = 1e9; long long INF64 = 1e18; long long binpow(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) { res = res * a % m; } a = a * a % m; b >>= 1; } return res; } vector<vector<int>> adj(2e5 + 5); vector<int> ord; vector<int> pos(2e5 + 5); vector<int> ending(2e5 + 5); void dfs(int node, int par) { pos[node] = ord.size(); ord.push_back(node); for (int i : adj[node]) { if (i == par) continue; dfs(i, node); } ending[node] = ord.size(); } void test_case(int tnum) { int n, q; cin >> n >> q; for (int i = 2; i <= n; i++) { int u; cin >> u; adj[u].push_back(i); adj[i].push_back(u); } dfs(1, -1); for (int i = 0; i < q; i++) { int u, k; cin >> u >> k; if (pos[u] + k - 1 >= ending[u]) { cout << -1 << n ; } else { cout << ord[pos[u] + k - 1] << n ; } } } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); int t = 1; for (int i = 1; i <= t; i++) { test_case(t); } } |
#include <bits/stdc++.h> using namespace std; template <class T> inline bool uin(T& a, T b) { return a > b ? (a = b, true) : false; } template <class T> inline bool uax(T& a, T b) { return a < b ? (a = b, true) : false; } const int nax = 5123; pair<int, int> edge[nax]; vector<int> g[nax]; int col[nax]; int N, M; bool cycle_found = false; int dfs_num[nax]; void dfs(int v) { dfs_num[v] = 1; for (int i : g[v]) { int ch = edge[i].first ^ edge[i].second ^ v; if (dfs_num[ch] == 2) { continue; } else if (dfs_num[ch] == 1) { col[i] = 1; cycle_found = true; continue; } dfs(ch); } dfs_num[v] = 2; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> N >> M; for (int u, v, i = 0; i < M; ++i) { cin >> u >> v; --u, --v; edge[i] = make_pair(u, v); g[u].push_back(i); } for (int i = 0; i < N; ++i) if (dfs_num[i] != 2) dfs(i); cout << (cycle_found ? 2 : 1) << n ; for (int i = 0; i < M; ++i) cout << col[i] + 1 << n [i == M - 1]; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: FIFO_SUM_IN_SQUARED.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_SUM_IN_SQUARED (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [25:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [25:0] q;
wire sub_wire0;
wire sub_wire1;
wire [25:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [25:0] q = sub_wire2[25:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 26,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "26"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "26"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL "data[25..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL "q[25..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) { return a; } return gcd(b, a % b); } long long lcm(long long a, long long b) { return ((a * b) / gcd(a, b)); } const long long maxn = 1e5; long long n, k; vector<long long> freq(maxn, 0); vector<long long> arr(maxn); vector<long long> ans(maxn, 0); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; cin >> n >> k; for (long long i = 0; i < n; i++) { cin >> arr[i]; freq[arr[i]]++; } long long counter = 0; for (long long i = 0; i < 1e4 + 1; i++) { if (freq[i] > 0) { for (long long j = i; j < 1e4 + 1; j++) { if (freq[j] == 0) { continue; } long long now = i ^ j; if (__builtin_popcount(now) == k) { if (i == j) { counter += ((freq[i] * (freq[i] - 1)) / 2); continue; } counter += ((freq[i] * freq[j])); } } } } cout << counter; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR4_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct node { long long x; int c; friend bool operator<(node x, node y) { return x.x < y.x; } } a[400001]; long long leftdata[400001], rightdata[400001]; int n; long long ans; long long max1, max2, l1, r1, ttt; void work1() { long long tans; l1 = 0; for (int i = 1; i <= n; ++i) if (a[i].c == 0) { tans = ans; if (l1 != 0) ans += a[i].x - l1; l1 = a[i].x; } l1 = 0; for (int i = 1; i <= n; ++i) if (a[i].c == 1) { tans = ans; if (l1 != 0) ans += a[i].x - l1; l1 = a[i].x; } cout << ans << endl; } void work2() { long long tans; long long f1 = 0, f2 = 0; int sum = 0; for (int i = 1; i <= n; ++i) { if (a[i].c == 2) { max2 = max(a[i].x - r1, max2); max1 = max(a[i].x - l1, max1); sum++; if (sum == 1) { tans = ans; if (f1 != 0) ans = ans + a[i].x - f1; if (f2 != 0) ans = ans + a[i].x - f2; } else { long long t1 = a[i].x + a[i].x - ttt - ttt; long long t2 = (a[i].x + a[i].x - ttt - ttt) - max1 + (a[i].x - ttt) - max2; long long yzc = min(t1, t2); ans = ans + yzc; } l1 = r1 = ttt = a[i].x; max1 = 0; max2 = 0; } else if (a[i].c == 0) { if (f1 == 0) f1 = a[i].x; if (max1 < a[i].x - l1) max1 = a[i].x - l1; l1 = a[i].x; } else { if (f2 == 0) f2 = a[i].x; if (max2 < a[i].x - r1) max2 = a[i].x - r1; r1 = a[i].x; } } f1 = 0; f2 = 0; for (int i = n; i >= 1; --i) { if (a[i].c == 2) { tans = ans; if (f1 != 0) ans = ans + f1 - a[i].x; if (f2 != 0) ans = ans + f2 - a[i].x; break; } else if (a[i].c == 0) { if (f1 == 0) f1 = a[i].x; } else { tans = ans; if (f2 == 0) f2 = a[i].x; } } cout << ans << endl; } int main() { scanf( %d , &n); char tmp[123]; int sumx = 0; for (int i = 1; i <= n; ++i) { long long x; scanf( %lld , &x); scanf( %s , tmp); a[i].x = x; if (tmp[0] == R ) a[i].c = 0; else if (tmp[0] == B ) a[i].c = 1; else a[i].c = 2, sumx++; } sort(a + 1, a + n + 1); ans = max1 = max2 = l1 = r1 = ttt = 0; if (sumx == 0) work1(); else work2(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O2BB2A_PP_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_PP_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: template_periph_16b.v
//
// *Module Description:
// 16 bit peripheral template.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module template_periph_16b (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0190;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 3;
// Register addresses offset
parameter [DEC_WD-1:0] CNTRL1 = 'h0,
CNTRL2 = 'h2,
CNTRL3 = 'h4,
CNTRL4 = 'h6;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2),
CNTRL3_D = (BASE_REG << CNTRL3),
CNTRL4_D = (BASE_REG << CNTRL4);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}}) |
(CNTRL3_D & {DEC_SZ{(reg_addr == CNTRL3 )}}) |
(CNTRL4_D & {DEC_SZ{(reg_addr == CNTRL4 )}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// CNTRL1 Register
//-----------------
reg [15:0] cntrl1;
wire cntrl1_wr = reg_wr[CNTRL1];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl1 <= 16'h0000;
else if (cntrl1_wr) cntrl1 <= per_din;
// CNTRL2 Register
//-----------------
reg [15:0] cntrl2;
wire cntrl2_wr = reg_wr[CNTRL2];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl2 <= 16'h0000;
else if (cntrl2_wr) cntrl2 <= per_din;
// CNTRL3 Register
//-----------------
reg [15:0] cntrl3;
wire cntrl3_wr = reg_wr[CNTRL3];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl3 <= 16'h0000;
else if (cntrl3_wr) cntrl3 <= per_din;
// CNTRL4 Register
//-----------------
reg [15:0] cntrl4;
wire cntrl4_wr = reg_wr[CNTRL4];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl4 <= 16'h0000;
else if (cntrl4_wr) cntrl4 <= per_din;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}};
wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}};
wire [15:0] cntrl3_rd = cntrl3 & {16{reg_rd[CNTRL3]}};
wire [15:0] cntrl4_rd = cntrl4 & {16{reg_rd[CNTRL4]}};
wire [15:0] per_dout = cntrl1_rd |
cntrl2_rd |
cntrl3_rd |
cntrl4_rd;
endmodule // template_periph_16b
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#include <bits/stdc++.h> using namespace std; int main() { long long i, j, n, m, d, f, x, d1, ans = 1e9; cin >> n >> m; long long a[n], b[n]; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < n; i++) cin >> b[i]; sort(a, a + n); sort(b, b + n); for (i = 0; i < n; i++) { x = i; d = (b[0] - a[i % n] + m) % m; f = 1; for (j = 1; j < n; j++) { x++; d1 = (b[j] - a[x % n] + m) % m; if (d1 != d) { f = 0; break; } } if (f) ans = min(ans, d); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 60; const int M = 40010; const int OFF = 20005; int n, m; int lt[N], rt[N]; set<int> cnt; bitset<N> ll[M], rr[M]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> lt[i]; } for (int i = 0; i < m; i++) { cin >> rt[i]; for (int j = 0; j < n; j++) { cnt.insert(lt[j] + rt[i] + OFF); ll[lt[j] + rt[i] + OFF].set(j); rr[lt[j] + rt[i] + OFF].set(i); } } int m1 = 0; for (auto cc1 : cnt) { for (auto cc2 : cnt) { bitset<N> unl = ll[cc1] | ll[cc2]; bitset<N> unr = rr[cc1] | rr[cc2]; m1 = max(m1, int(unl.count() + unr.count())); } } printf( %d n , m1); return 0; } |
// trigger_top.v
`timescale 1 ns / 1 ps
module trigger
(
input clk,
input sclk,
input sync,
input reset,
input ctrl_write,
input [31:0]ctrl_writedata,
input [3:0]ctrl_address,
// async trigger input
input trigger_in,
// trigger data in/out
input evin,
output evout,
// pattern generator input
input pg_trg,
input pg_rsr,
input pg_rst,
input pg_cal,
input pg_tin,
output deser_ena,
// ROC/module
output roc_ctr,
output roc_tin,
input roc_tout,
output daq_write,
output [15:0]daq_data
);
// --- control signals begin --------
wire sel_async;
wire sel_sync;
wire sel_single;
wire sel_gen;
wire sel_pg;
wire sel_dir_async;
wire sel_dir_sync;
wire sel_dir_single;
wire sel_dir_gen;
wire sel_dir_pg;
wire sel_chain;
wire sel_sync_out;
wire [4:0]send_trig;
wire gen_sel_random;
wire [31:0]gen_rate;
wire [7:0]trg_delay;
wire [15:0]token_timeout;
wire enable_tout_delay;
// --- control signals end ----------
wire [19:0]dummy20;
wire [26:0]dummy27;
wire [30:0]dummy31;
wire [23:0]dummy24;
wire [15:0]dummy16;
trigger_interface port
(
.clk(clk),
.sync(sync),
.reset(reset),
.write(ctrl_write),
.writedata(ctrl_writedata),
.address(ctrl_address),
.reg0({dummy20,
sel_dir_async, sel_dir_sync, sel_dir_gen,
sel_async, sel_sync, sel_single, sel_gen, sel_pg,
sel_dir_single, sel_dir_pg, sel_chain, sel_sync_out}),
.reg1({dummy27, send_trig}),
.reg2({dummy31, gen_sel_random}),
.reg3(gen_rate),
.reg4({dummy24, trg_delay}),
.reg5({dummy16, token_timeout}),
.reg6({dummy31, enable_tout_delay})
);
// === sources ====================================================
wire [4:0]trig_async_in;
wire [3:0]trig_async_pos;
trigger_in_async trg_in_async
(
.clk80(clk),
.clk400(sclk),
.sync(sync),
.reset(reset),
.trigger_in(trigger_in),
.trigger_out(trig_async_in),
.trigger_pos(trig_async_pos)
);
wire trig_del_sig;
wire [4:0]trig_del_out;
wire [4:0]trig_del = trig_del_out & {5{trig_del_sig}};
wire [3:0]trig_del_pos;
trigger_delay #(9) trg_del
(
.clk(clk),
.sync(sync),
.reset(reset),
.delay(trg_delay),
.trg_in(|trig_async_in),
.data_in({trig_async_pos, trig_async_in}),
.trg_out(trig_del_sig),
.data_out({trig_del_pos, trig_del_out})
);
wire [4:0]trig_gen;
trigger_generator trg_gen
(
.clk(clk),
.sync(sync),
.reset(reset),
.sel_random(gen_sel_random),
.rate(gen_rate),
.trg(trig_gen)
);
wire [4:0]trig_sync_in;
wire sync_bridge_in;
trigger_in_sync trg_data_in
(
.clk(clk),
.sync(sync),
.reset(reset),
.din(evin),
.trigger_out(trig_sync_in),
.direct_in(sync_bridge_in)
);
// === sinks ======================================================
wire [4:0]trig_sync_out;
wire sync_bridge_out;
trigger_out_sync trg_data_out
(
.clk(clk),
.sync(sync),
.reset(reset),
.trigger_in(trig_sync_out),
.direct_out(sync_bridge_out),
.dout(evout)
);
wire [4:0]trig_tbm;
wire [3:0]trig_tbm_pos;
wire [4:0]trig_ctr;
wire deser_ena_tbm;
wire roc_tin_tbm;
assign deser_ena = deser_ena_tbm
|| !(sel_async || sel_sync || sel_single || sel_gen || sel_pg);
soft_tbm tbm
(
.clk(clk),
.sync(sync),
.reset(reset),
.trg_in_tbm(trig_tbm),
.trg_in_ctr(trig_ctr),
.trg_pos(trig_tbm_pos),
.tin(roc_tin_tbm),
.tout(roc_tout),
.deser_ena(deser_ena_tbm),
.ctr(roc_ctr),
.daq_write(daq_write),
.daq_data(daq_data),
.token_timeout(token_timeout),
.enable_tout_delay(enable_tout_delay)
);
assign roc_tin = roc_tin_tbm || (pg_tin && sel_dir_pg);
// === switch =====================================================
trigger_control switch
(
.clk(clk),
.sync(sync),
.reset(reset),
// control
.sel_async(sel_async),
.sel_sync(sel_sync),
.sel_single(sel_single),
.sel_gen(sel_gen),
.sel_pg(sel_pg),
.sel_dir_async(sel_dir_async),
.sel_dir_sync(sel_dir_sync),
.sel_dir_single(sel_dir_single),
.sel_dir_gen(sel_dir_gen),
.sel_dir_pg(sel_dir_pg),
.sel_chain(sel_chain),
.sel_sync_out(sel_sync_out),
// sources
.src_async(trig_del),
.src_async_pos(trig_del_pos),
.src_sync(trig_sync_in),
.src_sync_direct(sync_bridge_in),
.src_single(send_trig),
.src_gen(trig_gen),
.src_pg({pg_cal, pg_rst, pg_rsr, pg_trg, 1'b0}),
// sinks
.dst_tbm(trig_tbm),
.dst_tbm_pos(trig_tbm_pos),
.dst_sync(trig_sync_out),
.dst_sync_direct(sync_bridge_out),
.dst_dir(trig_ctr)
);
endmodule
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//==================================================================================================
// Filename : Priority_Codec_32.v
// Created On : 2016-10-17 18:21:34
// Last Modified : 2016-10-17 19:20:05
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : New LZD version
//
//
//==================================================================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
parameter SWR = 26;
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
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