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//--------------------------------------------------------------------------------
//
// timer.v
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// 36-bit timer for advanced triggers. Gives range from 10ns to ~670 seconds.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module timer (
clk, reset, wrenb, wraddr, config_data,
update_timers, fsm_start_timer, fsm_clear_timer, fsm_stop_timer,
timer_elapsed);
input clk, reset;
input wrenb, wraddr;
input [31:0] config_data;
input update_timers;
input fsm_start_timer, fsm_clear_timer, fsm_stop_timer;
output timer_elapsed;
reg [35:0] timer, next_timer;
reg [35:0] timer_limit, next_timer_limit; // 10ns to 687 seconds
reg timer_active, next_timer_active;
reg timer_elapsed, next_timer_elapsed;
//
// 10ns resolution timer's...
//
initial
begin
timer = 36'h0;
timer_active = 1'b0;
timer_elapsed = 1'b0;
timer_limit = 36'h0;
end
always @ (posedge clk)
begin
timer = next_timer;
timer_active = next_timer_active;
timer_elapsed = next_timer_elapsed;
timer_limit = next_timer_limit;
end
always @*
begin
next_timer = (timer_elapsed) ? 36'h0 : timer;
next_timer_active = timer_active;
next_timer_elapsed = timer_elapsed;
next_timer_limit = timer_limit;
if (timer_active)
begin
next_timer = timer+1'b1;
if (timer >= timer_limit)
begin
next_timer_elapsed = 1'b1;
next_timer_active = 1'b0;
end
end
if (update_timers)
begin
if (fsm_start_timer) next_timer_active=1'b1;
if (fsm_clear_timer) begin next_timer=0; next_timer_elapsed=1'b0; end
if (fsm_stop_timer) next_timer_active=1'b0;
end
if (wrenb)
case (wraddr)
1'b0 : next_timer_limit[31:0] = config_data;
1'b1 : next_timer_limit[35:32] = config_data[3:0];
endcase
if (reset)
begin
next_timer = 0;
next_timer_active = 0;
next_timer_elapsed = 0;
end
end
endmodule
|
/* verilator lint_off WIDTH */
/* verilator lint_off UNUSED */
module output_data(
input clock,
// meta data
input isDrawAreaVGA,
input isOsdTextArea,
input isCharPixel,
input isOsdBgArea,
input isScanline,
input [8:0] scanline_intensity,
// ...
input [23:0] data,
output reg [23:0] data_out
);
localparam ONE_TO_ONE = 9'd_256;
`ifdef OSD_BACKGROUND_ALPHA
localparam OSD_BACKGROUND_ALPHA = `OSD_BACKGROUND_ALPHA;
`else
localparam OSD_BACKGROUND_ALPHA = 9'd_64;
`endif
reg [23:0] alpha_data;
reg [8:0] alpha_alpha;
wire [23:0] alpha_out;
alpha_calc ac (
.clock(clock),
.data(alpha_data),
.alpha(alpha_alpha),
.data_out(alpha_out)
);
function [8:0] trunc_osdbg(
input[16:0] value
);
trunc_osdbg = value[16:8];
endfunction
reg [8:0] osd_alpha;
reg isCharPixel_q, isOsdTextArea_q, isOsdBgArea_q, isDrawAreaVGA_q, isScanline_q;
reg [23:0] data_q;
always @(posedge clock) begin
data_q <= data;
osd_alpha <= OSD_BACKGROUND_ALPHA * scanline_intensity;
{ isCharPixel_q, isOsdTextArea_q, isOsdBgArea_q, isDrawAreaVGA_q, isScanline_q } <= { isCharPixel, isOsdTextArea, isOsdBgArea, isDrawAreaVGA, isScanline };
case ({ isOsdTextArea_q, isOsdBgArea_q, isDrawAreaVGA_q })
3'b_001: begin
alpha_data <= data_q;
alpha_alpha <= (isScanline_q ? scanline_intensity : ONE_TO_ONE);
end
3'b_011: begin
alpha_data <= data_q;
alpha_alpha <= (isScanline_q ? trunc_osdbg(osd_alpha) : OSD_BACKGROUND_ALPHA);
end
3'b_111: begin
if (isCharPixel_q) begin
alpha_data <= 24'hFFFFFF;
alpha_alpha <= ONE_TO_ONE;
end else begin
alpha_data <= data_q;
alpha_alpha <= (isScanline_q ? trunc_osdbg(osd_alpha) : OSD_BACKGROUND_ALPHA);
end
end
default: begin
alpha_data <= 24'h00;
alpha_alpha <= ONE_TO_ONE;
end
endcase
data_out <= alpha_out;
end
endmodule
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz
*/
input wire CLOCK_50,
/*
* GPIO
*/
input wire [3:0] KEY,
input wire [17:0] SW,
output wire [8:0] LEDG,
output wire [17:0] LEDR,
output wire [6:0] HEX0,
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wire [6:0] HEX4,
output wire [6:0] HEX5,
output wire [6:0] HEX6,
output wire [6:0] HEX7,
output wire [35:0] GPIO,
/*
* Ethernet: 1000BASE-T RGMII
*/
output wire ENET0_GTX_CLK,
output wire [3:0] ENET0_TX_DATA,
output wire ENET0_TX_EN,
input wire ENET0_RX_CLK,
input wire [3:0] ENET0_RX_DATA,
input wire ENET0_RX_DV,
output wire ENET0_RST_N,
input wire ENET0_INT_N,
output wire ENET1_GTX_CLK,
output wire [3:0] ENET1_TX_DATA,
output wire ENET1_TX_EN,
input wire ENET1_RX_CLK,
input wire [3:0] ENET1_RX_DATA,
input wire ENET1_RX_DV,
output wire ENET1_RST_N,
input wire ENET1_INT_N
);
// Clock and reset
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire pll_rst = ~KEY[3];
wire pll_locked;
wire clk90_int;
altpll #(
.bandwidth_type("AUTO"),
.clk0_divide_by(2),
.clk0_duty_cycle(50),
.clk0_multiply_by(5),
.clk0_phase_shift("0"),
.clk1_divide_by(2),
.clk1_duty_cycle(50),
.clk1_multiply_by(5),
.clk1_phase_shift("2000"),
.compensate_clock("CLK0"),
.inclk0_input_frequency(20000),
.intended_device_family("Cyclone IV E"),
.operation_mode("NORMAL"),
.pll_type("AUTO"),
.port_activeclock("PORT_UNUSED"),
.port_areset("PORT_USED"),
.port_clkbad0("PORT_UNUSED"),
.port_clkbad1("PORT_UNUSED"),
.port_clkloss("PORT_UNUSED"),
.port_clkswitch("PORT_UNUSED"),
.port_configupdate("PORT_UNUSED"),
.port_fbin("PORT_UNUSED"),
.port_inclk0("PORT_USED"),
.port_inclk1("PORT_UNUSED"),
.port_locked("PORT_USED"),
.port_pfdena("PORT_UNUSED"),
.port_phasecounterselect("PORT_UNUSED"),
.port_phasedone("PORT_UNUSED"),
.port_phasestep("PORT_UNUSED"),
.port_phaseupdown("PORT_UNUSED"),
.port_pllena("PORT_UNUSED"),
.port_scanaclr("PORT_UNUSED"),
.port_scanclk("PORT_UNUSED"),
.port_scanclkena("PORT_UNUSED"),
.port_scandata("PORT_UNUSED"),
.port_scandataout("PORT_UNUSED"),
.port_scandone("PORT_UNUSED"),
.port_scanread("PORT_UNUSED"),
.port_scanwrite("PORT_UNUSED"),
.port_clk0("PORT_USED"),
.port_clk1("PORT_USED"),
.port_clk2("PORT_UNUSED"),
.port_clk3("PORT_UNUSED"),
.port_clk4("PORT_UNUSED"),
.port_clk5("PORT_UNUSED"),
.port_clkena0("PORT_UNUSED"),
.port_clkena1("PORT_UNUSED"),
.port_clkena2("PORT_UNUSED"),
.port_clkena3("PORT_UNUSED"),
.port_clkena4("PORT_UNUSED"),
.port_clkena5("PORT_UNUSED"),
.port_extclk0("PORT_UNUSED"),
.port_extclk1("PORT_UNUSED"),
.port_extclk2("PORT_UNUSED"),
.port_extclk3("PORT_UNUSED"),
.self_reset_on_loss_lock("ON"),
.width_clock(5)
)
altpll_component (
.areset(pll_rst),
.inclk({1'b0, CLOCK_50}),
.clk({clk90_int, clk_int}),
.locked(pll_locked),
.activeclock(),
.clkbad(),
.clkena({6{1'b1}}),
.clkloss(),
.clkswitch(1'b0),
.configupdate(1'b0),
.enable0(),
.enable1(),
.extclk(),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.fbmimicbidir(),
.fbout(),
.fref(),
.icdrclk(),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasedone(),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scandataout(),
.scandone(),
.scanread(1'b0),
.scanwrite(1'b0),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~pll_locked),
.out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [17:0] sw_int;
debounce_switch #(
.WIDTH(4+18),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({~KEY,
SW}),
.out({btn_int,
sw_int})
);
fpga_core #(
.TARGET("ALTERA")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.ledg(LEDG),
.ledr(LEDR),
.hex0(HEX0),
.hex1(HEX1),
.hex2(HEX2),
.hex3(HEX3),
.hex4(HEX4),
.hex5(HEX5),
.hex6(HEX6),
.hex7(HEX7),
.gpio(GPIO),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy0_rx_clk(ENET0_RX_CLK),
.phy0_rxd(ENET0_RX_DATA),
.phy0_rx_ctl(ENET0_RX_DV),
.phy0_tx_clk(ENET0_GTX_CLK),
.phy0_txd(ENET0_TX_DATA),
.phy0_tx_ctl(ENET0_TX_EN),
.phy0_reset_n(ENET0_RST_N),
.phy0_int_n(ENET0_INT_N),
.phy1_rx_clk(ENET1_RX_CLK),
.phy1_rxd(ENET1_RX_DATA),
.phy1_rx_ctl(ENET1_RX_DV),
.phy1_tx_clk(ENET1_GTX_CLK),
.phy1_txd(ENET1_TX_DATA),
.phy1_tx_ctl(ENET1_TX_EN),
.phy1_reset_n(ENET1_RST_N),
.phy1_int_n(ENET1_INT_N)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_4_V
`define SKY130_FD_SC_HS__A311O_4_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_4_V
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.1415926535; double squared(double n) { return n * n; } typedef struct { int cx; int cy; int r; int R; } circle_t; bool isBlack(double x, double y, circle_t c) { double val = squared(x - (double)c.cx) + squared(y - (double)c.cy); if (val > squared(c.R)) { return false; } else if (val >= squared(c.r)) { return true; } else { return false; } } int returnOkNum(circle_t c, circle_t c2) { int blackOutNum = 0; int blackInNum = 0; int ret = 0; const int DIVIDE = 100000; for (int i = 0; i < DIVIDE; ++i) { double xOut = (double)c.R * cos(2.0 * PI * i / DIVIDE) + c.cx; double yOut = (double)c.R * sin(2.0 * PI * i / DIVIDE) + c.cy; double xIn = (double)c.r * cos(2.0 * PI * i / DIVIDE) + c.cx; double yIn = (double)c.r * sin(2.0 * PI * i / DIVIDE) + c.cy; if (isBlack(xOut, yOut, c2)) { ++blackOutNum; } if (isBlack(xIn, yIn, c2)) { ++blackInNum; } } if (blackOutNum <= 3) { ++ret; } if (blackInNum <= 3) { ++ret; } return ret; } int main(void) { vector<circle_t> cs(2); for (int i = 0; i < 2; ++i) { cin >> cs[i].cx >> cs[i].cy >> cs[i].r >> cs[i].R; } int ret = returnOkNum(cs[0], cs[1]); ret += returnOkNum(cs[1], cs[0]); cout << ret << endl; return 0; } |
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_extra_leds (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 4: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 4: 0] data_out;
wire [ 4: 0] out_port;
wire [ 4: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {5 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[4 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; vector<int> g[201010]; int tin[201010], tout[201010]; int n, a[201010], m, timer; int is[201010], lvl[201010]; void dfs(int v) { tin[v] = ++timer; for (auto to : g[v]) if (!tin[to]) { lvl[to] = lvl[v] ^ 1; dfs(to); } tout[v] = timer; } int t[2][801010]; void upd(int l, int r, int x, bool tp, int v = 1, int tl = 1, int tr = n) { if (tl > r || tr < l) return; if (tl >= l && tr <= r) { t[tp][v] += x; t[tp ^ 1][v] -= x; return; } int tm = (tl + tr) / 2; upd(l, r, x, tp, v * 2, tl, tm); upd(l, r, x, tp, v * 2 + 1, tm + 1, tr); } int get(int x, bool tp, int v = 1, int tl = 1, int tr = n) { if (tl == tr) return t[tp][v]; int tm = (tl + tr) / 2; if (x <= tm) return t[tp][v] + get(x, tp, v * 2, tl, tm); else return t[tp][v] + get(x, tp, v * 2 + 1, tm + 1, tr); } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1, u, v; i < n; i++) { cin >> u >> v; g[v].push_back(u); g[u].push_back(v); } dfs(1); for (int i = 1, x, val, tt; i <= m; i++) { cin >> tt >> x; if (tt == 2) { cout << a[x] + get(tin[x], lvl[x]) << n ; continue; } cin >> val; upd(tin[x], tout[x], val, lvl[x]); } } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; int n, m; int f[2][25][25][25][25][2][2]; int x[6], y[6]; int tpx[1 << 6], tqx[1 << 6], tpy[1 << 6], tqy[1 << 6]; inline void update(int &x, int y) { x = x + y >= mod ? x + y - mod : x + y; } inline bool check(int now, int px, int qx, int py, int qy) { for (int a = 0; a < 2; a++) for (int b = 0; b < 2; b++) if (f[now][px][qx][py][qy]) return true; return false; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d %d , &x[i], &y[i]); for (int s = 0; s < (1 << n); s++) for (int j = 1; j <= n; j++) if (s >> j - 1 & 1) { if (x[j] > 0) tpx[s] += x[j]; else tqx[s] -= x[j]; if (y[j] > 0) tpy[s] += y[j]; else tqy[s] -= y[j]; } int now = 0, lim = (1 << n) - 1; f[now][0][0][0][0][1][1] = 1; for (int i = 31; i >= 1; i--) { now ^= 1; memset(f[now], 0, sizeof(f[now])); int v = m >> i - 1 & 1; for (int px = 0; px <= tpx[lim]; px++) for (int qx = 0; qx <= tqx[lim]; qx++) for (int py = 0; py <= tpy[lim]; py++) for (int qy = 0; qy <= tqy[lim]; qy++) { if (!check(now ^ 1, px, qx, py, qy)) continue; for (int s = 0; s <= lim; s++) for (int a = 0; a < 2; a++) for (int b = 0; b < 2; b++) { int res = f[now ^ 1][px][qx][py][qy][a][b], na, nb; if (!res) continue; int npx = px * 2 - tpx[s], nqx = qx * 2 - tqx[s], npy = py * 2 - tpy[s], nqy = qy * 2 - tqy[s]; if (npx > tpx[lim] || nqx > tqx[lim] || npy > tpy[lim] || nqy > tqy[lim]) continue; if (npx >= 0 && nqx >= 0 && npy >= 0 && nqy >= 0) { na = a & (v == 0), nb = b & (v == 0); update(f[now][npx][nqx][npy][nqy][na][nb], res); } bool f1 = a & (v == 0), f2 = b & (v == 0); if (!f1 && npx + 1 >= 0 && nqx + 1 >= 0 && npy >= 0 && nqy >= 0) { na = a & (v == 1), nb = b & (v == 0); update(f[now][npx + 1][nqx + 1][npy][nqy][na][nb], res); } if (!f2 && npx >= 0 && nqx >= 0 && npy + 1 >= 0 && nqy + 1 >= 0) { na = a & (v == 0), nb = b & (v == 1); update(f[now][npx][nqx][npy + 1][nqy + 1][na][nb], res); } if (!f1 && !f2 && npx + 1 >= 0 && nqx + 1 >= 0 && npy + 1 >= 0 && nqy + 1 >= 0) { na = a & (v == 1), nb = b & (v == 1); update(f[now][npx + 1][nqx + 1][npy + 1][nqy + 1][na][nb], res); } } } } int ans = mod - 1; for (int a = 0; a < 2; a++) for (int b = 0; b < 2; b++) update(ans, f[now][0][0][0][0][a][b]); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MaxN = 1e5; const int Inf = 1 << 30; double a[105]; int main() { int n, cnt; double pos, pp, ans, sum; while (~scanf( %d , &n)) { sum = 0; pos = 4.5; pos *= n; for (int i = 1; i <= n; i++) { scanf( %lf , &a[i]); sum += a[i]; } cnt = 0; sort(a + 1, a + 1 + n); while (sum < pos) { cnt++; sum += 5 - a[cnt]; } printf( %d n , cnt); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Hasan Hassan
//
// Create Date: 08/24/2015 06:51:37 PM
// Design Name:
// Module Name: pcie_data_sender
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "riffa.vh"
module pcie_data_sender #(parameter C_PCI_DATA_WIDTH = 128, INPUT_DATA_WIDTH = 8) (
input clk,
input rst,
//Collector Interface
output coll_ready,
input coll_data_valid,
input[7:0] coll_data,
//RIFFA TX Interface
output CHNL_TX,
input CHNL_TX_ACK,
output CHNL_TX_LAST,
output[`SIG_CHNL_LENGTH_W - 1:0] CHNL_TX_LEN,
output[30:0] CHNL_TX_OFF,
output[C_PCI_DATA_WIDTH - 1:0] CHNL_TX_DATA,
output reg CHNL_TX_DATA_VALID,
input CHNL_TX_DATA_REN,
input[`SIG_CHNL_LENGTH_W - 1:0] dna_len,
output idle,
input en
);
localparam DATA_PER_TX = C_PCI_DATA_WIDTH/INPUT_DATA_WIDTH; //number of data chunk that can with in C_PCI_DATA_WIDTH
parameter IT_BITS = $clog2(DATA_PER_TX);
reg state = STATE_IDLE;
localparam STATE_IDLE = 1'b0;
localparam STATE_SENDING = 1'b1;
reg[`SIG_CHNL_LENGTH_W - 1:0] dna_len_r, send_len;
reg tx_issued;
//state transition logic
always@(posedge clk) begin
if(rst) begin
state <= STATE_IDLE;
dna_len_r <= 0;
send_len <= 0;
end
else begin
case(state)
STATE_IDLE: begin
if(en) begin
dna_len_r <= (dna_len - 1) >> 4;
send_len <= (dna_len - 1) >> 2;
state <= STATE_SENDING;
end
end //STATE_IDLE
STATE_SENDING: begin
if(tx_issued) begin
dna_len_r <= dna_len_r - 1;
if(dna_len_r == 1) begin
state <= STATE_IDLE;
end
end
end //STATE_SENDING
endcase
end
end
assign idle = (state == STATE_IDLE);
//Register Input Data
reg[INPUT_DATA_WIDTH - 1:0] data_r;
reg data_valid_r;
wire fetch_input = coll_ready;
always@(posedge clk) begin
if(rst) begin
data_r <= 0;
data_valid_r <= 0;
end
else begin
if(fetch_input) begin
data_r <= coll_data;
data_valid_r <= coll_data_valid;
end
end
end
//Put data chuck in tx buffer
reg[IT_BITS - 1:0] iter = 0;
reg[C_PCI_DATA_WIDTH - 1:0] tx_buffer;
reg tx_buffer_valid = 0;
always@(posedge clk) begin
if(rst) begin
tx_buffer <= 0;
tx_buffer_valid <= 0;
end
else begin
if(data_valid_r && coll_ready) begin
tx_buffer[iter*INPUT_DATA_WIDTH +:INPUT_DATA_WIDTH] <= data_r;
iter <= iter + 1'b1;
tx_buffer_valid <= &iter;
end
else if(tx_issued) begin
tx_buffer_valid <= 1'b0;
end
end
end
//TODO: consider adding one more register stage for better timing
//Send tx buffer to RIFFA
assign CHNL_TX_LEN = send_len; //C_PCI_DATA_WIDTH/32;
assign CHNL_TX_LAST = 1'b1; //(dna_len_r == 1);
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = tx_buffer;
assign CHNL_TX = (state == STATE_SENDING);
always@* begin
tx_issued = 1'b0;
CHNL_TX_DATA_VALID = 1'b0;
if(state == STATE_SENDING) begin
if(tx_buffer_valid) begin
CHNL_TX_DATA_VALID = 1'b1;
if(CHNL_TX_DATA_REN) begin
tx_issued = 1'b1;
end
end //tx_buffer_valid
end
end
assign coll_ready = ~tx_buffer_valid || (tx_buffer_valid && tx_issued);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [6:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_falling & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100000; const long long INF = 1000000000000000; int a[N]; int main() { int t; cin >> t; for (int q = 0; q < t; q++) { int n, k; cin >> n >> k; for (int j = 0; j < n; j++) { cin >> a[j]; } long long answer = -INF; for (long long j = 1; j < n; j++) { long long i = j - 1; while (i >= 0 and (i + 1) * (j + 1) - k * a[j] > answer) { long long result = (i + 1) * (j + 1) - k * (a[i] | a[j]); answer = max(answer, result); i--; } } cout << answer << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int t, n; int cnt, num, maxx; int a[maxn]; int vis[maxn]; int m1[maxn]; int m2[maxn]; void init() { num = 0; maxx = 0; memset(vis, 0, sizeof(vis)); } int main() { scanf( %d , &t); while (t--) { cnt = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) m1[i] = 0, m2[i] = 0; init(); for (int i = 1; i <= n; i++) { maxx = max(maxx, a[i]); if (!vis[a[i]]) { num++; vis[a[i]] = 1; } else break; if (num == maxx) m1[i] = 1; else m1[i] = 0; } init(); for (int i = n; i >= 1; i--) { maxx = max(maxx, a[i]); if (!vis[a[i]]) { num++; vis[a[i]] = 1; } else break; if (num == maxx) { m2[i] = 1; if (i > 1 && m1[i - 1]) cnt++; } else m2[i] = 0; } printf( %d n , cnt); for (int i = 1; i < n; i++) if (m1[i] && m2[i + 1]) printf( %d %d n , i, n - i); } return 0; } |
#include <bits/stdc++.h> int query(int aa[][150 + 1], int l0, int l1, int r0, int r1) { return l0 > l1 || r0 > r1 ? 0 : ((long long)aa[l1][r1] - aa[l0 - 1][r1] - aa[l1][r0 - 1] + aa[l0 - 1][r0 - 1]) % 1000000007; } void add(int aa[][150 + 1], int l, int r, int a) { aa[l][r] = (aa[l][r] + a) % 1000000007; } int main() { static int dp00[150 + 1][150 + 1], dp01[150 + 1][150 + 1], dp10[150 + 1][150 + 1], dp11[150 + 1][150 + 1]; static int dq00[150 + 1][150 + 1], dq01[150 + 1][150 + 1], dq10[150 + 1][150 + 1], dq11[150 + 1][150 + 1]; int n, m, l, r, ans; scanf( %d%d , &n, &m); ans = 0; while (n--) { for (l = 1; l <= m; l++) for (r = 1; r <= m; r++) { dp00[l][r] = (dp00[l][r] + dp00[l][r - 1]) % 1000000007; dp01[l][r] = (dp01[l][r] + dp01[l][r - 1]) % 1000000007; dp10[l][r] = (dp10[l][r] + dp10[l][r - 1]) % 1000000007; dp11[l][r] = (dp11[l][r] + dp11[l][r - 1]) % 1000000007; } for (l = 1; l <= m; l++) for (r = 1; r <= m; r++) { dp00[l][r] = (dp00[l][r] + dp00[l - 1][r]) % 1000000007; dp01[l][r] = (dp01[l][r] + dp01[l - 1][r]) % 1000000007; dp10[l][r] = (dp10[l][r] + dp10[l - 1][r]) % 1000000007; dp11[l][r] = (dp11[l][r] + dp11[l - 1][r]) % 1000000007; } for (l = 1; l <= m; l++) for (r = 1; r <= m; r++) dq00[l][r] = dq01[l][r] = dq10[l][r] = dq11[l][r] = 0; for (l = 1; l <= m; l++) for (r = l; r <= m; r++) { dq00[l][r] = 1; add(dq00, l, r, query(dp00, l, m, 1, r)); add(dq01, l, r, query(dp01, l, r, r, m)); add(dq01, l, r, query(dp00, l, r, r + 1, m)); add(dq10, l, r, query(dp10, 1, l, l, r)); add(dq10, l, r, query(dp00, 1, l - 1, l, r)); add(dq11, l, r, query(dp11, 1, l, r, m)); add(dq11, l, r, query(dp01, 1, l - 1, r, m)); add(dq11, l, r, query(dp10, 1, l, r + 1, m)); add(dq11, l, r, query(dp00, 1, l - 1, r + 1, m)); ans = (ans + (long long)dq00[l][r] + dq01[l][r] + dq10[l][r] + dq11[l][r]) % 1000000007; } for (l = 0; l <= m; l++) for (r = 0; r <= m; r++) { dp00[l][r] = dq00[l][r]; dp01[l][r] = dq01[l][r]; dp10[l][r] = dq10[l][r]; dp11[l][r] = dq11[l][r]; } } if (ans < 0) ans += 1000000007; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { double m, R; cin >> m >> R; double answer = (m * (m + 1) * (m + 2) / 3 - m) * 2; answer += (sqrt(2.0) - 2) * ((m * m - m) + (m * m - m - (m - 1) * 2)); answer /= (m * m); answer *= R; cout << setprecision(7) << answer << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFGCE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFGCE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "BUFGCE_dr.v"
`else
localparam [40:1] CE_TYPE_REG = CE_TYPE;
localparam [0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam [0:0] IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire O_out;
wire CE_in;
wire I_in;
`ifdef XIL_TIMING
wire CE_dly;
wire I_dly;
assign CE_in = (CE === 1'bz) || (CE_dly ^ IS_CE_INVERTED_BIN); // rv 1
assign I_in = I_dly ^ IS_I_INVERTED_BIN;
`else
assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_BIN); // rv 1
assign I_in = I ^ IS_I_INVERTED_BIN;
`endif
assign O = O_out;
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CE_TYPE_REG != "SYNC") &&
(CE_TYPE_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CE_INVERTED_REG !== 1'b0) && (IS_CE_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-102] IS_CE_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_I_INVERTED_REG !== 1'b0) && (IS_I_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-103] IS_I_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
`ifdef XIL_TIMING
reg notifier;
wire sh_i_en_p;
wire sh_i_en_n;
assign sh_i_en_p = ~IS_I_INVERTED_BIN;
assign sh_i_en_n = IS_I_INVERTED_BIN;
specify
(CE => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_n,sh_i_en_n, I_dly, CE_dly);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_n,sh_i_en_n, I_dly, CE_dly);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_p,sh_i_en_p, I_dly, CE_dly);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_p,sh_i_en_p, I_dly, CE_dly);
$width (negedge CE, 0:0:0, 0, notifier);
$width (posedge CE, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
// The Arithmetic/Logic Unit (ALU) is responsible for performing the arithmetic
// and bitwise logical operations the computer depends upon to calculate
// everything from effective addresses for looking stuff up in memory, all the
// way to medical imaging. (OK, the latter might have some help from floating
// point units later on, but I digress.)
//
// This file implements the exact same ALU as was used in the KCP53000 CPU.
module alu(
input [63:0] inA_i,
input [63:0] inB_i,
input cflag_i,
input sum_en_i,
input and_en_i,
input xor_en_i,
input invB_en_i,
input lsh_en_i,
input rsh_en_i,
input ltu_en_i, // See issue https://github.com/KestrelComputer/polaris/issues/18
input lts_en_i, // See issue https://github.com/KestrelComputer/polaris/issues/18
output [63:0] out_o,
output cflag_o,
output vflag_o,
output zflag_o
);
wire [63:0] b = inB_i ^ ({64{invB_en_i}});
wire [63:0] sumL = inA_i[62:0] + b[62:0] + {62'b0, cflag_i};
wire c62 = sumL[63];
wire [64:63] sumH = inA_i[63] + b[63] + c62;
wire [63:0] rawSums = {sumH[63], sumL[62:0]};
wire [63:0] sums = sum_en_i ? rawSums : 64'd0;
assign zflag_o = ~(|out_o);
assign vflag_o = sumH[64] ^ sumL[63];
assign cflag_o = sumH[64];
wire [63:0] ands = and_en_i ? (inA_i & b) : 64'd0;
wire [63:0] xors = xor_en_i ? (inA_i ^ b) : 64'd0;
wire [63:0] lsh32 = inB_i[5] ? {inA_i[31:0], 32'd0} : inA_i;
wire [63:0] lsh16 = inB_i[4] ? {lsh32[47:0], 16'd0} : lsh32;
wire [63:0] lsh8 = inB_i[3] ? {lsh16[55:0], 8'd0} : lsh16;
wire [63:0] lsh4 = inB_i[2] ? {lsh8[59:0], 4'd0} : lsh8;
wire [63:0] lsh2 = inB_i[1] ? {lsh4[61:0], 2'd0} : lsh4;
wire [63:0] lsh1 = inB_i[0] ? {lsh2[62:0], 1'd0} : lsh2;
wire [63:0] lshs = lsh_en_i ? lsh1 : 0;
wire [63:32] sx5 = cflag_i ? {32{inA_i[63]}} : 0;
wire [63:0] rsh32 = inB_i[5] ? {sx5, inA_i[63:32]} : inA_i;
wire [63:48] sx4 = cflag_i ? {16{rsh32[63]}} : 0;
wire [63:0] rsh16 = inB_i[4] ? {sx4, rsh32[63:16]} : rsh32;
wire [63:56] sx3 = cflag_i ? {8{rsh16[63]}} : 0;
wire [63:0] rsh8 = inB_i[3] ? {sx3, rsh16[63:8]} : rsh16;
wire [63:60] sx2 = cflag_i ? {4{rsh8[63]}} : 0;
wire [63:0] rsh4 = inB_i[2] ? {sx2, rsh8[63:4]} : rsh8;
wire [63:62] sx1 = cflag_i ? {2{rsh4[63]}} : 0;
wire [63:0] rsh2 = inB_i[1] ? {sx1, rsh4[63:2]} : rsh4;
wire sx0 = cflag_i & rsh2[63];
wire [63:0] rsh1 = inB_i[0] ? {sx0, rsh2[63:1]} : rsh2;
wire [63:0] rshs = rsh_en_i ? rsh1 : 0;
wire isLTS = lts_en_i ? {63'd0, rawSums[63] ^ vflag_o} : 0;
wire isLTU = ltu_en_i ? {63'd0, ~cflag_o} : 0;
assign out_o = sums | ands | xors | lshs | rshs | isLTS | isLTU;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.49d
// \ \ Application: netgen
// / / Filename: v6_emac_v2_2.v
// /___/ /\ Timestamp: Thu Mar 28 10:57:26 2013
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/v6_emac_v2_2.ngc ./tmp/_cg/v6_emac_v2_2.v
// Device : 6vlx240tff1156-1
// Input file : ./tmp/_cg/v6_emac_v2_2.ngc
// Output file : ./tmp/_cg/v6_emac_v2_2.v
// # of Modules : 1
// Design Name : v6_emac_v2_2
// Xilinx : D:\Xilinx\14.4\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module v6_emac_v2_2 (
rx_axi_clk, glbl_rstn, rx_axis_mac_tuser, gmii_col, gmii_crs, gmii_tx_en, tx_axi_rstn, gmii_tx_er, tx_collision, rx_axi_rstn, tx_axis_mac_tlast,
tx_retransmit, tx_axis_mac_tuser, rx_axis_mac_tvalid, rx_statistics_valid, tx_statistics_valid, rx_axis_mac_tlast, speed_is_10_100, gtx_clk,
rx_reset_out, tx_reset_out, tx_axi_clk, gmii_rx_dv, gmii_rx_er, tx_axis_mac_tready, tx_axis_mac_tvalid, pause_req, tx_statistics_vector, pause_val,
rx_statistics_vector, gmii_rxd, tx_ifg_delay, tx_axis_mac_tdata, rx_axis_mac_tdata, gmii_txd
)/* synthesis syn_black_box syn_noprune=1 */;
input rx_axi_clk;
input glbl_rstn;
output rx_axis_mac_tuser;
input gmii_col;
input gmii_crs;
output gmii_tx_en;
input tx_axi_rstn;
output gmii_tx_er;
output tx_collision;
input rx_axi_rstn;
input tx_axis_mac_tlast;
output tx_retransmit;
input tx_axis_mac_tuser;
output rx_axis_mac_tvalid;
output rx_statistics_valid;
output tx_statistics_valid;
output rx_axis_mac_tlast;
output speed_is_10_100;
input gtx_clk;
output rx_reset_out;
output tx_reset_out;
input tx_axi_clk;
input gmii_rx_dv;
input gmii_rx_er;
output tx_axis_mac_tready;
input tx_axis_mac_tvalid;
input pause_req;
output [31 : 0] tx_statistics_vector;
input [15 : 0] pause_val;
output [27 : 0] rx_statistics_vector;
input [7 : 0] gmii_rxd;
input [7 : 0] tx_ifg_delay;
input [7 : 0] tx_axis_mac_tdata;
output [7 : 0] rx_axis_mac_tdata;
output [7 : 0] gmii_txd;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:512000000 ) using namespace std; void solve(bool); void precalc(); clock_t start; int main() { start = clock(); int t = 1; cout.sync_with_stdio(0); cin.tie(0); precalc(); cout.precision(10); cout << fixed; int testNum = 1; while (t--) { solve(true); } cout.flush(); return 0; } template <typename T> T binpow(T q, T w, T mod) { if (!w) return 1 % mod; if (w & 1) return q * 1LL * binpow(q, w - 1, mod) % mod; return binpow(q * 1LL * q % mod, w / 2, mod); } template <typename T> T gcd(T q, T w) { while (w) { q %= w; swap(q, w); } return q; } template <typename T> T lcm(T q, T w) { return q / gcd(q, w) * w; } template <typename T> void make_unique(vector<T>& a) { sort(a.begin(), a.end()); a.erase(unique(a.begin(), a.end()), a.end()); } template <typename T> void relax_min(T& cur, T val) { cur = min(cur, val); } template <typename T> void relax_max(T& cur, T val) { cur = max(cur, val); } void precalc() {} const long long C = 100500; long long mod; long long phi; long long rem[C]; long long rev_rem[C]; vector<long long> primes, degs; long long n; long long get_deg(long long n, long long p) { long long res = 0; while (n) { res += n / p; n /= p; } return res; } long long getC(long long n, long long k) { if (n < k) { return 0; } long long res = rem[n] * rev_rem[k] % mod * rev_rem[n - k] % mod; for (long long i = 0; i < primes.size(); ++i) { long long deg = get_deg(n, primes[i]) - get_deg(k, primes[i]) - get_deg(n - k, primes[i]); res = res * binpow(primes[i], deg, mod) % mod; } return res; } long long get_res(long long l) { long long res = 0; for (long long par = 0; par < 2; ++par) { for (long long cur = 0; 2 * cur + par <= n; ++cur) { long long m = 2 * cur + par; long long cur_l = l; if ((cur_l + par) % 2) { ++cur_l; } long long now_c = (m + cur_l) / 2; res += getC(n, m) * getC(m, now_c); res %= mod; } } return res; } void solve(bool read) { long long l, r; cin >> n >> mod >> l >> r; rem[0] = 1; long long M = mod; phi = mod; for (long long p = 2; p * p <= M; ++p) { if (M % p == 0) { phi = phi * (p - 1) / p; primes.push_back(p); degs.push_back(0); while (M % p == 0) { M /= p; ++degs.back(); } } } if (M > 1) { phi = phi * (M - 1) / M; primes.push_back(M); degs.push_back(1); } for (long long i = 1; i < C; ++i) { long long cur = i; for (long long p : primes) { while (cur % p == 0) { cur /= p; } } rem[i] = rem[i - 1] * cur % mod; } for (long long i = 0; i < C; ++i) { rev_rem[i] = binpow(rem[i], phi - 1, mod); } long long res = get_res(l) - get_res(r + 1); res %= mod; if (res < 0) { res += mod; } cout << res << endl; } |
#include <bits/stdc++.h> namespace my_std { using namespace std; inline int read() { char c = getchar(); int ans = 0, f = 1; while (c > 9 || c < 0 ) { f ^= (c == - ); c = getchar(); } for (; c <= 9 && c >= 0 ; c = getchar()) ans = (ans << 1) + (ans << 3) + (c ^ 48); return f ? ans : -ans; } const int mod = 1e9 + 7, N = 5010; inline void inc(int &x, const int &y) { x += y; if (x >= mod) x -= mod; } inline int ksm(int x, long long y) { int res = 1; for (; y; y >>= 1, x = 1ll * x * x % mod) if (y & 1) res = 1ll * res * x % mod; return res; } inline int gcd(int x, int y) { if (x > y) swap(y, x); return y ? gcd(y, x % y) : x; } } // namespace my_std using namespace my_std; vector<int> e[N << 1]; int n, m, d, lv[N], ans[N], wt[N << 1], vis[N << 1]; struct People_CF1139E { int pot, cl, lf; } st[N]; inline bool find(int u) { register int v; for (register int i = (0); i <= (int(e[u].size()) - 1); ++i) { v = e[u][i]; if (vis[v]) continue; vis[v] = 1; if (wt[v] == -1 || find(wt[v])) { wt[v] = u; return 1; } } return 0; } int main() { n = read(), m = read(); for (register int i = (1); i <= (n); ++i) st[i].pot = read(); for (register int i = (1); i <= (n); ++i) st[i].cl = read(); d = read(); for (register int i = (1); i <= (d); ++i) lv[i] = read(), st[lv[i]].lf = 1; for (register int i = (1); i <= (n); ++i) { if (!st[i].lf && st[i].pot <= m) { e[st[i].pot].push_back(st[i].cl + m); e[st[i].cl + m].push_back(st[i].pot); } } memset(wt, -1, sizeof(wt)); for (register int i = (d); i >= (1); --i) { for (register int j = (ans[i + 1]); j <= (m); ++j) { memset(vis, 0, sizeof(vis)); if (!find(j)) { ans[i] = j; break; } } if (st[lv[i]].pot > m) continue; e[st[lv[i]].pot].push_back(st[lv[i]].cl + m); e[st[lv[i]].cl + m].push_back(st[lv[i]].pot); } for (register int i = (1); i <= (d); ++i) printf( %d n , ans[i]); return 0; } |
// sprite priority logic module
// this module checks the playfields and sprites video status and
// determines if playfield or sprite data must be sent to the video output
// sprite/playfield priority is configurable through the bplcon2 bits
module denise_spritepriority
(
input [5:0] bplcon2, // playfields vs sprites priority setting
input [2:1] nplayfield, // playfields video status
input [7:0] nsprite, // sprites video status
output reg sprsel // sprites select signal output
);
// local signals
reg [2:0] sprcode; // sprite code
wire [3:0] sprgroup; // grouped sprites
wire pf1front; // playfield 1 is on front of sprites
wire pf2front; // playfield 2 is on front of sprites
// group sprites together
assign sprgroup[0] = (nsprite[1:0]==2'd0) ? 1'b0 : 1'b1;
assign sprgroup[1] = (nsprite[3:2]==2'd0) ? 1'b0 : 1'b1;
assign sprgroup[2] = (nsprite[5:4]==2'd0) ? 1'b0 : 1'b1;
assign sprgroup[3] = (nsprite[7:6]==2'd0) ? 1'b0 : 1'b1;
// sprites priority encoder
always @(*)
if (sprgroup[0])
sprcode = 3'd1;
else if (sprgroup[1])
sprcode = 3'd2;
else if (sprgroup[2])
sprcode = 3'd3;
else if (sprgroup[3])
sprcode = 3'd4;
else
sprcode = 3'd7;
// check if playfields are in front of sprites
assign pf1front = sprcode[2:0]>bplcon2[2:0] ? 1'b1 : 1'b0;
assign pf2front = sprcode[2:0]>bplcon2[5:3] ? 1'b1 : 1'b0;
// generate final playfield/sprite select signal
always @(*)
begin
if (sprcode[2:0]==3'd7) // if no valid sprite data, always select playfields
sprsel = 1'b0;
else if (pf1front && nplayfield[1]) // else if pf1 in front and valid data, select playfields
sprsel = 1'b0;
else if (pf2front && nplayfield[2]) // else if pf2 in front and valid data, select playfields
sprsel = 1'b0;
else // else select sprites
sprsel = 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const long long LLINF = 9223372036854775807LL; const int ST = 100010; const int ST1 = 1000010; const long long MOD = 1000000007; long long ABS(long long a) { if (a < 0) return a * (-1); else return a; } int mas[30]; bool ans = true; void bad() { cout << NO ; exit(0); } vector<vector<int> > ppp; int sz = 0; void per(vector<int> &t) { if ((int)((t).size()) == sz) { ppp.push_back(t); } else { t.push_back(0); per(t); t.pop_back(); t.push_back(1); per(t); t.pop_back(); } } void per(vector<int> val, int ed, vector<int> zap) { if ((int)((val).size()) == 0) { if (ed == 0) { cout << YES ; exit(0); } else return; } vector<vector<int> > pp; vector<int> em; sz = (int)((zap).size()); ppp.clear(); per(em); pp = ppp; int tek = val[(int)((val).size()) - 1] - 1; val.pop_back(); int ost = 0; for (int i = 0; i < (int)((pp).size()); i++) { vector<int> next; next.push_back(tek + 1); ost = 0; int kk = 0; for (int j = 0; j < (int)((pp[i]).size()); j++) { if (pp[i][j] == 1) { ost += zap[j]; kk++; } else next.push_back(zap[j]); } if (ost <= tek) { int s = tek - ost; if (s > ed) continue; kk += s; if (kk == 1) continue; per(val, ed - s, next); } } } int main() { int n; cin >> n; if (n == 1) { cout << YES ; return 0; } int kk = 0; for (int i = 0; i < n; i++) { cin >> mas[i]; if (mas[i] == 2) bad(); if (mas[i] == 1) kk++; } sort(mas, mas + n); int mn = n / 2; if (kk < mn) bad(); vector<int> t; int nol = 0; for (int i = 0; i < n; i++) if (mas[i] != 1) t.push_back(mas[i]); else nol++; vector<int> em; reverse(t.begin(), t.end()); per(t, nol, em); cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, s, arr[4005][4005] = {}, x = 2000, ex[9][4], song[100005], res = 0; int main() { cin >> n >> m >> k >> s; for (int i = 0; i < 9; i++) { ex[i][0] = -999999999; ex[i][1] = 999999999; ex[i][2] = -999999999; ex[i][3] = 999999999; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> arr[i + j][i - j + x]; int c = arr[i + j][i - j + x] - 1; for (int k = 0; k < 9; k++) { ex[c][0] = max(ex[c][0], i + j); ex[c][1] = min(ex[c][1], i + j); ex[c][2] = max(ex[c][2], i - j + x); ex[c][3] = min(ex[c][3], i - j + x); } } } for (int i = 0; i < s; i++) cin >> song[i], song[i]--; for (int i = 1; i < s; i++) { int a = song[i - 1], b = song[i]; res = max(res, max(max(ex[a][0] - ex[b][1], ex[b][0] - ex[a][1]), max(ex[a][2] - ex[b][3], ex[b][2] - ex[a][3]))); } cout << res; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); map<pair<string, string>, int> map_count; vector<int> cost_list; int n, a, b, k, f; string s, t, prv = ; cin >> n >> a >> b >> k >> f; for (int cost, i = 0; i < n; i++) { cin >> s >> t; if (s == prv) { cost = b; } else { cost = a; } prv = t; if (s > t) { swap(s, t); } map_count[make_pair(s, t)] += cost; } for (auto& pkv : map_count) { cost_list.push_back(pkv.second); } sort(cost_list.begin(), cost_list.end(), greater<int>()); int res = 0; for (int i = 0; i < cost_list.size(); i++) { if (i < k && cost_list[i] > f) { res += f; } else { res += cost_list[i]; } } cout << res; return 0; } |
`timescale 1ns/10ps
module audio_clock_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("12.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("3.072000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("1.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
module dcache_top
(
// System clock, reset and stall
clk_i,
rst_i,
// to Data Memory interface
mem_data_i,
mem_ack_i,
mem_data_o,
mem_addr_o,
mem_enable_o,
mem_write_o,
// to CPU interface
p1_data_i,
p1_addr_i,
p1_MemRead_i,
p1_MemWrite_i,
p1_data_o,
p1_stall_o
);
//
// System clock, start
//
input clk_i;
input rst_i;
//
// to Data Memory interface
//
input [256-1:0] mem_data_i;
input mem_ack_i;
output [256-1:0] mem_data_o;
output [32-1:0] mem_addr_o;
output mem_enable_o;
output mem_write_o;
//
// to core interface
//
input [32-1:0] p1_data_i;
input [32-1:0] p1_addr_i;
input p1_MemRead_i;
input p1_MemWrite_i;
output [32-1:0]p1_data_o;
output p1_stall_o;
//
// to SRAM interface
//
wire [4:0] cache_sram_index;
wire cache_sram_enable;
wire [23:0] cache_sram_tag;
wire [255:0] cache_sram_data;
wire cache_sram_write;
wire [23:0] sram_cache_tag;
wire [255:0] sram_cache_data;
// cache
wire sram_valid;
wire sram_dirty;
// controller
parameter STATE_IDLE = 3'h0,
STATE_READMISS = 3'h1,
STATE_READMISSOK = 3'h2,
STATE_WRITEBACK = 3'h3,
STATE_MISS = 3'h4;
reg [2:0] state;
reg mem_enable;
reg mem_write;
reg cache_we;
wire cache_dirty;
reg write_back;
// regs & wires
wire [4:0] p1_offset;
wire [4:0] p1_index;
wire [21:0] p1_tag;
wire [255:0] r_hit_data;
wire [21:0] sram_tag;
wire hit;
reg [255:0] w_hit_data;
wire write_hit;
wire p1_req;
reg [31:0] p1_data;
// project1 interface
assign p1_req = p1_MemRead_i | p1_MemWrite_i;
assign p1_offset = p1_addr_i[4:0];
assign p1_index = p1_addr_i[9:5];
assign p1_tag = p1_addr_i[31:10];
assign p1_stall_o = ~hit & p1_req;
assign p1_data_o = p1_data;
// SRAM interface
assign sram_valid = sram_cache_tag[23];
assign sram_dirty = sram_cache_tag[22];
assign sram_tag = sram_cache_tag[21:0];
assign cache_sram_index = p1_index;
assign cache_sram_enable = p1_req;
assign cache_sram_write = cache_we | write_hit;
assign cache_sram_tag = {1'b1, cache_dirty, p1_tag};
assign cache_sram_data = (hit) ? w_hit_data : mem_data_i;
// memory interface
assign mem_enable_o = mem_enable;
assign mem_addr_o = (write_back) ? {sram_tag, p1_index, 5'b0} : {p1_tag, p1_index, 5'b0};
assign mem_data_o = sram_cache_data;
assign mem_write_o = mem_write;
assign write_hit = hit & p1_MemWrite_i;
assign cache_dirty = write_hit;
// tag comparator
assign hit = (sram_tag == p1_tag && sram_valid)? 1'b1 :1'b0;
assign r_hit_data = sram_cache_data;
// read data : 256-bit to 32-bit
always@(p1_offset or r_hit_data) begin
p1_data =hit ? r_hit_data[(p1_offset>>2)*32 +: 32] : 32'b0;
end
// write data : 32-bit to 256-bit
always@(p1_offset or r_hit_data or p1_data_i) begin
w_hit_data={ p1_offset == 28 ? p1_data_i : r_hit_data[255:224],
p1_offset == 24 ? p1_data_i : r_hit_data[223:192],
p1_offset == 20 ? p1_data_i : r_hit_data[191:160],
p1_offset == 16 ? p1_data_i : r_hit_data[159:128],
p1_offset == 12 ? p1_data_i : r_hit_data[127:96],
p1_offset == 8 ? p1_data_i : r_hit_data[95:64],
p1_offset == 4 ? p1_data_i : r_hit_data[63:32],
p1_offset == 0 ? p1_data_i : r_hit_data[31:0]};
end
// controller
always@(posedge clk_i or negedge rst_i) begin
if(~rst_i) begin
state <= STATE_IDLE;
mem_enable <= 1'b0;
mem_write <= 1'b0;
cache_we <= 1'b0;
write_back <= 1'b0;
end
else begin
case(state)
STATE_IDLE: begin
if(p1_req && !hit) begin //wait for request
state <= STATE_MISS;
end
else begin
state <= STATE_IDLE;
end
end
STATE_MISS: begin
if(sram_dirty) begin //write back if dirty
mem_enable<=1'b1;
mem_write <=1'b1;
write_back<=1'b1;
state <= STATE_WRITEBACK;
end
else begin //write allocate: write miss = read miss + write hit; read miss = read miss + read hit
mem_enable<=1'b1;
mem_write<=1'b0;
write_back<=1'b0;
state <= STATE_READMISS;
end
end
STATE_READMISS: begin
if(mem_ack_i) begin //wait for data memory acknowledge
mem_enable<=1'b0;
cache_we<=1'b1;
state <= STATE_READMISSOK;
end
else begin
state <= STATE_READMISS;
end
end
STATE_READMISSOK: begin //wait for data memory acknowledge
cache_we<=1'b0;
state <= STATE_IDLE;
end
STATE_WRITEBACK: begin
if(mem_ack_i) begin //wait for data memory acknowledge
write_back<=1'b0;
mem_write <=1'b0;
state <= STATE_READMISS;
end
else begin
state <= STATE_WRITEBACK;
end
end
endcase
end
end
//
// Tag SRAM 0
//
dcache_tag_sram dcache_tag_sram
(
.clk_i(clk_i),
.addr_i(cache_sram_index),
.data_i(cache_sram_tag),
.enable_i(cache_sram_enable),
.write_i(cache_sram_write),
.data_o(sram_cache_tag)
);
//
// Data SRAM 0
//
dcache_data_sram dcache_data_sram
(
.clk_i(clk_i),
.addr_i(cache_sram_index),
.data_i(cache_sram_data),
.enable_i(cache_sram_enable),
.write_i(cache_sram_write),
.data_o(sram_cache_data)
);
endmodule |
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& out, vector<T>& v) { out << [ ; for (auto k : v) out << k << ; out << ] ; return out; } vector<int> g[500]; string color; bool posible = true; void DFS(int n, int p, char c) { if (color[n] != - && color[n] != c) { posible = false; return; } if (color[n] != - ) return; color[n] = c; char nc = 1 - c + 0 ; for (auto k : g[n]) if (k != p) DFS(k, n, nc); } int main() { int n; string in; cin >> n >> in; color.resize(n, - ); for (int i = 0; i < int(n); i++) { for (int j = int(i + 1); j < int(n); j++) { if (in[i] > in[j]) { g[i].push_back(j); g[j].push_back(i); } } } for (int i = 0; i < int(n); i++) if (color[i] == - ) DFS(i, -1, 0 ); if (posible) cout << YES << endl << color << endl; else cout << NO << endl; } |
module butterfly_16(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8 ,
o_9 ,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [25:0] i_0;
input signed [25:0] i_1;
input signed [25:0] i_2;
input signed [25:0] i_3;
input signed [25:0] i_4;
input signed [25:0] i_5;
input signed [25:0] i_6;
input signed [25:0] i_7;
input signed [25:0] i_8;
input signed [25:0] i_9;
input signed [25:0] i_10;
input signed [25:0] i_11;
input signed [25:0] i_12;
input signed [25:0] i_13;
input signed [25:0] i_14;
input signed [25:0] i_15;
output signed [26:0] o_0 ;
output signed [26:0] o_1 ;
output signed [26:0] o_2 ;
output signed [26:0] o_3 ;
output signed [26:0] o_4 ;
output signed [26:0] o_5 ;
output signed [26:0] o_6 ;
output signed [26:0] o_7 ;
output signed [26:0] o_8 ;
output signed [26:0] o_9 ;
output signed [26:0] o_10;
output signed [26:0] o_11;
output signed [26:0] o_12;
output signed [26:0] o_13;
output signed [26:0] o_14;
output signed [26:0] o_15;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [26:0] b_0;
wire signed [26:0] b_1;
wire signed [26:0] b_2;
wire signed [26:0] b_3;
wire signed [26:0] b_4;
wire signed [26:0] b_5;
wire signed [26:0] b_6;
wire signed [26:0] b_7;
wire signed [26:0] b_8;
wire signed [26:0] b_9;
wire signed [26:0] b_10;
wire signed [26:0] b_11;
wire signed [26:0] b_12;
wire signed [26:0] b_13;
wire signed [26:0] b_14;
wire signed [26:0] b_15;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_15;
assign b_1=i_1+i_14;
assign b_2=i_2+i_13;
assign b_3=i_3+i_12;
assign b_4=i_4+i_11;
assign b_5=i_5+i_10;
assign b_6=i_6+i_9;
assign b_7=i_7+i_8;
assign b_8=i_7-i_8;
assign b_9=i_6-i_9;
assign b_10=i_5-i_10;
assign b_11=i_4-i_11;
assign b_12=i_3-i_12;
assign b_13=i_2-i_13;
assign b_14=i_1-i_14;
assign b_15=i_0-i_15;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
endmodule
|
`define IDLE 3'b000
`define STATE_RD 3'b001
`define STATE_EX1 3'b010
`define STATE_EX2 3'b011
`define STATE_EX3 3'b100
`define STATE_EX4 3'b101
module alu_fsm (
in_alu_select,
out_alu_start,
in_valu_done,
out_alu_ready,
RD,
EX,
WB,
clk,
rst
);
input in_alu_select;
input in_valu_done;
output out_alu_start;
output out_alu_ready;
output RD;
output EX;
output WB;
input clk;
input rst;
reg out_alu_ready;
reg RD;
reg WB;
reg [2:0] next_state;
reg next_EX;
reg next_alu_start;
wire [2:0] current_state;
dff state_flop[2:0] (.q(current_state), .d(next_state), .clk(clk), .rst(rst));
dff EX_flop (.q(EX), .d(next_EX), .clk(clk), .rst(rst));
dff alu_start_flop (.q(out_alu_start), .d(next_alu_start), .clk(clk), .rst(rst));
always @ (current_state or in_alu_select or in_valu_done) begin
casex({current_state, in_alu_select, in_valu_done})
{`IDLE, 1'b0, 1'b0} :
begin
next_state <= `IDLE;
out_alu_ready <= 1'b1;
RD <= 1'b0;
next_EX <= 1'b0;
next_alu_start <= 1'b0;
WB <= 1'b0;
end
{`IDLE, 1'b1, 1'b0} :
begin
next_state <= `STATE_EX1;
out_alu_ready <= 1'b0;
RD <= 1'b1;
next_EX <= 1'b1;
next_alu_start <= 1'b1;
WB <= 1'b0;
end
{`STATE_RD, 1'b0, 1'b?} :
begin
next_state <= `STATE_EX1;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b0;
WB <= 1'b0;
end
{`STATE_EX1, 1'b0, 1'b0} :
begin
next_state <= `STATE_EX1;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b0;
WB <= 1'b0;
end
{`STATE_EX1, 1'b0, 1'b1} :
begin
next_state <= `STATE_EX2;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b1;
WB <= 1'b0;
end
{`STATE_EX2, 1'b0, 1'b0} :
begin
next_state <= `STATE_EX2;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b0;
WB <= 1'b0;
end
{`STATE_EX2, 1'b0, 1'b1} :
begin
next_state <= `STATE_EX3;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b1;
WB <= 1'b0;
end
{`STATE_EX3, 1'b0, 1'b0} :
begin
next_state <= `STATE_EX3;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b0;
WB <= 1'b0;
end
{`STATE_EX3, 1'b0, 1'b1} :
begin
next_state <= `STATE_EX4;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b1;
WB <= 1'b0;
end
{`STATE_EX4, 1'b0, 1'b0} :
begin
next_state <= `STATE_EX4;
out_alu_ready <= 1'b0;
RD <= 1'b0;
next_EX <= 1'b1;
next_alu_start <= 1'b0;
WB <= 1'b0;
end
{`STATE_EX4, 1'b0, 1'b1} :
begin
next_state <= `IDLE;
out_alu_ready <= 1'b1;
RD <= 1'b0;
next_EX <= 1'b0;
next_alu_start <= 1'b0;
WB <= 1'b1;
end
default :
begin
next_state <= 3'bxxx;
out_alu_ready <= 1'bx;
RD <= 1'bx;
next_EX <= 1'bx;
next_alu_start <= 1'bx;
WB <= 1'bx;
end
endcase
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always force reg_lvalue = boolean_expr ;
// D: This is an infinite loop - thus compile only
// SJW - rework from akways3.1.3E to make it runnable.
module main ;
reg [3:0] value1 ;
initial
begin
#15;
if(value1 !== 4'b1)
$display("FAILED - 3.1.3E always force reg_lvalue = boolean_expr;");
else
$display("PASSED");
$finish;
end
always #10 force value1 = 1'b1 & 1'b1 ;
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/07/14
// Module Name : mapping
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// This module maps the data received from the SircHandler to the puf.
// Does all singal mappings to input, interconnect and output networks.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module mapping #(
parameter CHALLENGE_WIDTH = 32,
parameter PDL_CONFIG_WIDTH = 128,
parameter RESPONSE_WIDTH = 6
)(
input wire clk,
input wire reset,
input wire trigger,
input wire [CHALLENGE_WIDTH-1:0] challenge,
input wire [PDL_CONFIG_WIDTH-1:0] pdl_config,
output reg done,
output wire [RESPONSE_WIDTH-1:0] raw_response,
output wire xor_response
);
//FSM States
localparam IDLE = 0;
localparam COMPUTE = 1;
//State Register
reg mp_state;
//Actual challenge after transformation
wire [CHALLENGE_WIDTH-1:0] actual_challenge;
///////////// Input network /////////////
(* KEEP_HIERARCHY="TRUE" *)
pufInputNetwork #(.Width(CHALLENGE_WIDTH))
pin(
.dataIn(challenge[CHALLENGE_WIDTH-1:0]),
.dataOut(actual_challenge[CHALLENGE_WIDTH-1:0])
);
//////////// Interconnect network & PUF ///////////////
(* KEEP_HIERARCHY="TRUE" *)
pufInterconNetwork picn (
.CHALLENGE(actual_challenge[CHALLENGE_WIDTH-1:0]),
.PDL_CONFIG(pdl_config[PDL_CONFIG_WIDTH-1:0]),
.RESPONSE(raw_response),
.trigger(trigger),
.reset(reset)
);
//////////// Output network ///////////////
(* KEEP_HIERARCHY="TRUE" *)
pufOutputNetwork pon (
.response(raw_response),
.xor_response(xor_response)
);
endmodule
|
// Periferico del modulo ultrasónico. El módulo transforma el tiempo que Signal permanece encendido en milímetros.
// Signal entra desde el modulo físico del ultrasonico, las demás señales pertenecen a la interaccion que tiene con el J1
// Solo hay lectura de datos. una vez se desactiva el estado de reset, el módulo se prepara para recibir la señal y hacer el conteo
module peripheral_mult(
input clk,
input rst,
input [15:0] d_in, // Dato de entrada
input cs, //
input [3:0] addr, // 4 LSB from j1_io_addr
input rd, // Para leer
input wr, // Comando para escribir
input signal, // Del dispositivo físico
output reg [15:0] d_out // Dato de salida
);
//------------------------------------ regs and wires-------------------------------
reg [1:0] s; // Selector
wire [15:0] value ;
wire done ;
reg enable ;
//------------------------------------ regs and wires-------------------------------
always @(*) begin// Selector de modo
case (addr)
4'h0: s = (cs && wr) ? 4'b0001 : 4'b000 ; // Enable
4'h2: s = (cs && rd) ? 4'b0010 : 4'b000 ; // Busy
4'h4: s = (cs && rd) ? 4'b0100 : 4'b000 ; // Value [7:0]
4'h6: s = (cs && rd) ? 4'b1000 : 4'b000 ; // Value [15:8]
default: s = 4'b000 ;
endcase
end
always @(negedge clk) begin // Multiplexa entradas del periferico
case (s)
4'b0001: enable = 1 ;
default: d_out = 0 ;
endcase
end
always @(negedge clk) begin // Multiplexa salidas del periferico
case (s)
4'b0010: d_out[0] = done ;
4'b0100: d_out = value[7:0] ;
4'b1000: d_out = value[15:8] ;
default: d_out = 0 ;
endcase
end
ultrasonic ult (
.clk(clk),
.enable(enable),
.signal(signal) ,
.value(value) ,
.done(done)
);
endmodule
|
module RegisterFileTestBench_nogenerate;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] Rd,Mem,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
RegisterFile_nogenerate RF(Rd,Mem,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
//Clk 0
Clk = 0 ; RESET = 0 ; Pcin = 32'bz ; Rd = 32'bz ; Mem = 32'bz ; LOADPC = 0 ; LOAD = 0 ; IR_CU = 0 ; RSLCT = 0 ;
//Clk 1 (Rising Edge)
#1 Pcin = 32'bz ; #1 Rd = 1 ; #1 Mem = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;
//Clk 0 (Falling Edge)
#2 Pcin = 32'bz ; #2 Rd = 1 ; #2 Mem = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;
//Clk 1 (Rising Edge)
#3 Pcin = 32'bz ; #3 Rd = 1 ; #3 Mem = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#4 Pcin = 32'bz ; #4 Rd = 1 ; #4 Mem = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;
//Clk 1 (Rising Edge)
#5 Pcin = 32'bz ; #5 Rd = 1 ; #5 Mem = 32'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#6 Pcin = 32'bz ; #6 Rd = 1 ; #6 Mem = 32'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("RegisterFileTestBench_nogenerate.vcd");
$dumpvars(0,RegisterFileTestBench_nogenerate);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , Rd = %3d , Mem = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, Rd, Mem, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile_nogenerate.v RegisterFileTestBench_nogenerate.v |
#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> n >> m; int a[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> a[i][j]; } int b[m][n]; bool flag = false; int index = -1; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cin >> b[i][j]; if (b[i][j] == a[0][0] && !flag) { flag = true; index = i; } } } for (int i = 0; i < n; i++) { int curr = b[index][i]; for (int j = 0; j < n; j++) { if (a[j][0] == curr) { for (int k = 0; k < m; k++) cout << a[j][k] << ; cout << endl; } } } } int main() { long long int t = 1; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; long long N, f[3001][3001]; struct Node { long long x, val; } P[3001]; inline bool cmp(const Node &a, const Node &b) { return a.x < b.x; } int main() { scanf( %I64d , &N); for (long long i = 1; i <= N; i++) scanf( %I64d%I64d , &P[i].x, &P[i].val); sort(P + 1, P + N + 1, cmp); memset(f, 0x7f, sizeof(f)); f[1][1] = P[1].val; for (long long i = 2; i <= N; i++) for (long long j = 1; j <= i; j++) { f[i][j] = min(f[i][j], f[i - 1][j] + P[i].x - P[j].x); f[i][i] = min(f[i][i], f[i - 1][j] + P[i].val); } long long ans = (unsigned)(-1) >> 1; for (long long i = 1; i <= N; i++) ans = min(ans, f[N][i]); printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); mt19937 rnf(2106); const int N = 200005; int n, m; int x[N], y[N]; int d[N]; queue<int> q[N]; int dist(int x1, int y1, int x2, int y2) { return abs(x1 - x2) + abs(y1 - y2); } int ans[N]; bool stg(int s) { for (int i = 1; i <= m; ++i) { while (!q[d[i]].empty()) q[d[i]].pop(); } for (int i = 1; i <= m; ++i) q[d[i]].push(i); for (int i = 0; i < n; ++i) ans[i] = -1; for (int i = s; i < n; i += 2) { int dd = dist(x[i], y[i], x[(i - 1 + n) % n], y[(i - 1 + n) % n]) + dist(x[i], y[i], x[(i + 1) % n], y[(i + 1) % n]); if (q[dd].empty()) return false; ans[i] = q[dd].front(); q[dd].pop(); } } void solv() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %d%d , &x[i], &y[i]); for (int i = 1; i <= m; ++i) { scanf( %d , &d[i]); } if (stg(0)) { printf( YES n ); for (int i = 0; i < n; ++i) printf( %d , ans[i]); printf( n ); } else if (stg(1)) { printf( YES n ); for (int i = 0; i < n; ++i) printf( %d , ans[i]); printf( n ); } else printf( NO n ); } int main() { solv(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_BLACKBOX_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$P (
Q ,
D ,
CLK
);
output Q ;
input D ;
input CLK;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a[4], i, j, min = 1000, x, y; for (i = 0; i < 4; i++) { cin >> a[i]; if (min > a[i]) min = a[i]; } cin >> x >> y; if (x >= min) { cout << 0; return 0; } else if (y < min) { cout << y - x + 1; } else { cout << min - x; } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e3 * 3 + 10; int n, k, m; vector<int> graph[2][MAXN]; int p[2][MAXN]; int sum; void read_input() { scanf( %d , &n); scanf( %d , &k); int v; for (int i = 0; i < k - 1; i++) { sum++; scanf( %d , &v); graph[0][n + i + 2].push_back(v + n); graph[0][v + n].push_back(n + i + 2); p[0][n + i + 2] = v + n; } for (int i = 0; i < n; i++) { scanf( %d , &v); graph[0][i + 1].push_back(v + n); graph[0][v + n].push_back(i + 1); p[0][i + 1] = n + v; } scanf( %d , &m); for (int i = 0; i < m - 1; i++) { sum++; scanf( %d , &v); graph[1][n + i + 2].push_back(v + n); graph[1][v + n].push_back(n + i + 2); p[1][n + i + 2] = v + n; } for (int i = 0; i < n; i++) { scanf( %d , &v); graph[1][i + 1].push_back(v + n); graph[1][v + n].push_back(i + 1); p[1][i + 1] = n + v; } } int timer; int in[2][MAXN], out[2][MAXN]; int depth[2][MAXN]; void dfs(int v, int p, int r, int dt = 0) { in[r][v] = timer++; depth[r][v] = dt; for (auto x : graph[r][v]) { if (in[r][x] == 0 && x != p) { dfs(x, v, r, dt + 1); } } out[r][v] = timer++; } int lca[2][MAXN][MAXN]; const int INF = 1e9; int _abs(int f) { if (f < 0) return -f; return f; } int T[MAXN][MAXN]; int rec(int l, int r) { int temp = max(l, r) + 1; if (temp > n) return 0; if (T[l][r]) return T[l][r]; int ans = INF; int add = 0; if (l != 0) { int LCA = lca[0][l][temp]; add = _abs(depth[0][LCA] - depth[0][temp]) - 1; ans = min(ans, rec(temp, r) + add); } else { ans = rec(temp, r) + depth[0][temp] - 1; } if (r != 0) { int LCA = lca[1][r][temp]; add = _abs(depth[1][LCA] - depth[1][temp]) - 1; ans = min(ans, rec(l, temp) + add); } else { ans = min(ans, rec(l, temp) + depth[1][temp] - 1); } return T[l][r] = ans; } void solve() { timer = 1; dfs(n + 1, n + 1, 0); for (int i = 0; i < n; i++) { int temp = i + 1; int LCA = temp; for (int j = i + 1; j < n; j++) { int tr = j + 1; while (in[0][tr] > out[0][LCA] || out[0][tr] < in[0][LCA]) LCA = p[0][LCA]; lca[0][temp][tr] = lca[0][tr][temp] = LCA; } } timer = 1; dfs(n + 1, n + 1, 1); for (int i = 0; i < n; i++) { int temp = i + 1; int LCA = temp; for (int j = i + 1; j < n; j++) { int tr = j + 1; while (in[1][tr] > out[1][LCA] || out[1][tr] < in[1][LCA]) LCA = p[1][LCA]; lca[1][temp][tr] = lca[1][tr][temp] = LCA; } } printf( %d n , sum - rec(0, 0)); } int main() { read_input(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int ara[1000]; int rf[1000]; int main() { int n, i, f, w, cnt = 0, m, r; char str[1000001]; scanf( %d %d , &n, &m); scanf( %s , str); for (i = 0; i < n; i++) { r = str[i]; ara[r] = ara[r] + 1; } for (i = 0; i < n; i++) { r = str[i]; if (rf[r] == 0) { cnt++; rf[r] = 1; if (cnt > m) { printf( YES ); return 0; } } ara[r] = ara[r] - 1; if (ara[r] == 0) { cnt--; } } printf( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; long long now = 0; long long mx = -1; while (true) { long long rem = (n - (now * 7)); if (rem < 0) { break; } else { if (rem % 4 == 0) { mx = max(mx, now); } } now++; } if (mx == -1) { cout << -1; return 0; } else { long long four = n - (mx * 7); four /= 4; for (long long i = 0; i < four; i++) { cout << 4; } for (long long i = 0; i < mx; i++) { cout << 7; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_1_V
`define SKY130_FD_SC_HDLL__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_1_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module blk_mem_gen_0 (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [15 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [15 : 0] douta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *)
input wire [0 : 0] web;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [13 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *)
input wire [15 : 0] dinb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [15 : 0] doutb;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(2),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("blk_mem_gen_0.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_READ_WIDTH_A(16),
.C_WRITE_DEPTH_A(16384),
.C_READ_DEPTH_A(16384),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(16),
.C_READ_WIDTH_B(16),
.C_WRITE_DEPTH_B(16384),
.C_READ_DEPTH_B(16384),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("7"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 22.1485 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(web),
.addrb(addrb),
.dinb(dinb),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(16'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_TB_V
`define SKY130_FD_SC_LP__BUFINV_TB_V
/**
* bufinv: Buffer followed by inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__bufinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_TB_V
|
#pragma GCC optimize( O3 , Ofast , unroll-loops , omit-frame-pointer , inline ) //Optimization flags #pragma GCC option( arch=native , tune=native , no-zero-upper ) //Enable AVX // #pragma GCC target( avx2 ) //Enable AVX #include <bits/stdc++.h> #define int long long using namespace std; #ifdef LOCAL #include /media/brayand/BrayanD/debugger.h #else #define db(...) false #define dbl(...) false #define dbg(...) false #define dbm(...) false #define dbs(...) false #define dbas(...) false #endif const int oo = 1e18; const int MAXN = 4e4+100; int ST[MAXN*4]; int lazy[MAXN*4]; int dp[MAXN][120]; void prop(int nodo) { if(lazy[nodo] != 0) { ST[nodo] += lazy[nodo]; if(nodo*2 < MAXN*4) { lazy[nodo*2] += lazy[nodo]; } if(nodo*2+1 < MAXN*4) { lazy[nodo*2+1] += lazy[nodo]; } lazy[nodo] = 0; } } void build(int nodo, int l, int r, int k) { lazy[nodo] = 0; if(l == r) { ST[nodo] = dp[l][k]; return; } int mid = (l+r)/2; build(nodo*2,l,mid,k); build(nodo*2+1,mid+1,r,k); ST[nodo] = max(ST[nodo*2], ST[nodo*2+1]); } void update(int nodo, int l, int r, int a, int b, int x) { prop(nodo); if(r < a || l > b)return; if(a <= l && r <= b) { lazy[nodo] += x; prop(nodo); return; } int mid = (l+r)/2; update(nodo*2,l,mid,a,b,x); update(nodo*2+1,mid+1,r,a,b,x); ST[nodo] = max(ST[nodo*2], ST[nodo*2+1]); } int query(int nodo, int l, int r, int a, int b) { prop(nodo); if(r < a || l > b)return -oo; if(a <= l && r <= b) { return ST[nodo]; } int mid = (l+r)/2; return max(query(nodo*2,l,mid,a,b), query(nodo*2+1,mid+1,r,a,b)); } int A[MAXN]; vector<int> arr[MAXN]; int T[MAXN]; vector<int> ins[MAXN]; vector<int> del[MAXN]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); int N, K; cin >> N >> K; K--; for(int i = 1 ; i <= N ; i++) { cin >> A[i]; arr[A[i]].push_back(i); } if(N == 1) { cout << 0 << n ; return 0; } vector<pair<int,int>> vect; int sum = 0; for(int i = 1 ; i <= N ; i++) { for(int j = 1 ; j < arr[i].size() ; j++) { vect.push_back({arr[i][j-1],arr[i][j]-1}); } if(arr[i].size()) { sum += arr[i].back()-arr[i][0]; } } for(auto x : vect) { int d = x.second-x.first+1; T[x.first] += d; T[x.second+1] -= d; } for(int i = 1 ; i <= N ; i++) { T[i] += T[i-1]; } for(int i = 0 ; i < MAXN ; i++) { for(int j = 0 ; j < 120 ; j++) { dp[i][j] = -oo; } } for(int i = 1 ; i < N ; i++) { dp[i][0] = 0; dp[i][1] = T[i]; } for(int i = 0 ; i < vect.size() ; i++) { ins[vect[i].first].push_back(i); del[vect[i].second+1].push_back(i); } for(int j = 2 ; j <= K ; j++) { build(1,1,N-1,j-1); for(int i = 1 ; i < N ; i++) { for(auto x : ins[i]) { int v = vect[x].second-vect[x].first+1; update(1,1,N-1,vect[x].first, vect[x].second, -v); } for(auto x : del[i]) { int v = vect[x].second-vect[x].first+1; update(1,1,N-1,vect[x].first, vect[x].second, v); } if(i >= j)dp[i][j] = query(1,1,N-1,1,i-1) + T[i]; } } int res = 0; for(int i = 1 ; i < N ; i++) { res = max(res, dp[i][K]); } cout << sum - res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int dx8[8] = {1, -1, 0, 0, 1, 1, -1, -1}; int dy8[8] = {0, 0, 1, -1, 1, -1, 1, -1}; void file() {} void fast() { std::ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); } int main() { file(); int n, s; cin >> n >> s; if (n == 1 && s == 0) { cout << 0 0 << endl; return 0; } if (n * 9 < s || s == 0) { cout << -1 -1 << endl; return 0; } int sum = s; vector<int> mx, mn; for (int i = 0; i < n; i++) { if (sum >= 9) mx.push_back(9), sum -= 9; else mx.push_back(sum), sum = 0; } sum = s; for (int i = n - 1; i > 0; i--) { mn.push_back(min(sum - 1, 9)); sum -= min(sum - 1, 9); } mn.push_back(sum); reverse(((mn).begin()), ((mn).end())); int zeros = n - mn.size(); for (int i = 0; i < mn.size(); i++) { cout << mn[i]; if (i == 0) { for (int j = 0; j < zeros; j++) cout << 0; } } cout << ; for (int i = 0; i < n; i++) cout << mx[i]; cout << endl; } |
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module seg_7 (
input [3:0] num,
input en,
output reg [6:0] seg
);
// Behaviour
always @(num or en)
if (!en) seg <= 7'h3f;
else
case (num)
4'h0: seg <= {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
4'h1: seg <= {1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b1};
4'h2: seg <= {1'b0,1'b1,1'b0,1'b0,1'b1,1'b0,1'b0};
4'h3: seg <= {1'b0,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0};
4'h4: seg <= {1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b1};
4'h5: seg <= {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,1'b0};
4'h6: seg <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0};
4'h7: seg <= {1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0};
4'h8: seg <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
4'h9: seg <= {1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0};
4'ha: seg <= {1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0};
4'hb: seg <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
4'hc: seg <= {1'b0,1'b1,1'b0,1'b0,1'b1,1'b1,1'b1};
4'hd: seg <= {1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1};
4'he: seg <= {1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b0};
4'hf: seg <= {1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0};
endcase
endmodule
|
/**
* The Hack CPU (Central Processing unit), consisting of an ALU,
* two registers named A and D, and a program counter named PC.
* The CPU is designed to fetch and execute instructions written in
* the Hack machine language.
* In particular, functions as follows:
* Executes the inputted instruction according to the Hack machine
* language specification.
* The D and A in the language specification
* refer to CPU-resident registers,
* while M refers to the external memory location addressed by A,
* i.e. to Memory[A].
* The inM input holds the value of this location.
*
* If the current instruction needs
* to write a value to M, the value is placed in outM, the address
* of the target location is placed in the addressM output, and the
* writeM control bit is asserted. (When writeM==0, any value may
* appear in outM).
* The outM and writeM outputs are combinational:
* they are affected instantaneously by the execution of the current
* instruction. The addressM and pc outputs are clocked: although they
* are affected by the execution of the current instruction, they commit
* to their new values only in the next time step. If reset==1 then the
* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
* than to the address resulting from executing the current instruction.
*
*
* IN inM[16], // M value input (M = contents of RAM[A])
* instruction[16], // Instruction for execution
* reset; // Signals whether to re-start the current
* // program (reset==1) or continue executing
* // the current program (reset==0).
*
* OUT outM[16], // M value output
* writeM, // Write to M?
* addressM[15], // Address in data memory (of M)
* pc[15]; // address of next instruction
*/
module cpu (
input clk,
input reset,
input [15:0] instruction,
input [15:0] inM,
output [15:0] outM,
output [14:0] addressM,
output writeM,
output [14:0] pc,
output [15:0] areg,
output [15:0] dreg
);
// Fastest = 2
//parameter SPEED = 32'd2500000;
parameter SPEED = 32'd5;
reg [15:0] r_outM = 16'b0;
reg [14:0] r_addressM = 15'b0;
reg r_writeM = 0;
reg pc_inc = 0;
reg pc_load = 0;
reg [15:0] pc_in = 0;
wire [15:0] pc_out;
reg [15:0] alu_y = 16'b0;
wire [15:0] alu_out;
wire alu_zr, alu_ng;
assign pc = pc_out[14:0];
assign outM = r_outM;
assign writeM = r_writeM;
assign addressM = r_addressM;
reg [15:0] DRegister = 16'b0;
reg [15:0] ARegister = 16'b0;
assign dreg = DRegister;
assign areg = ARegister;
program_counter program_counter_inst (
.clk(clk),
.reset(reset),
.inc(pc_inc),
.load(pc_load),
.in(pc_in),
.out(pc_out)
);
alu alu_inst(
.x(DRegister),
.y(alu_y),
.zx(instruction[11]),
.nx(instruction[10]),
.zy(instruction[9]),
.ny(instruction[8]),
.f(instruction[7]),
.no(instruction[6]),
.out(alu_out),
.zr(alu_zr),
.ng(alu_ng)
);
// Cpu speed, timer compare must be at least 2
// as three clock cycles are needed per instuction.
reg [31:0] timer = 32'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
timer <= 32'b0;
end else begin
if (timer == SPEED) begin
timer <= 32'd0;
end else begin
timer <= timer + 32'b1;
end
end
end
always @(*) begin
if (timer == 3'd0) begin
// If d3 (instruction[3]) == 1 then write the output of the alu to M (RAM).
if (instruction[15] == 1 && instruction[3] == 1) begin
r_writeM = 1'b1;
end else begin
r_writeM = 1'b0;
end
// Jump instructions
pc_load = 1'b0;
if (instruction[15] == 1) begin
case (instruction[2:0])
3'b001: if (!alu_ng && !alu_zr) pc_load = 1'b1; // JGT alu_out > 0
3'b010: if (alu_zr) pc_load = 1'b1; // JEQ alu_out == 0
3'b011: if (!alu_ng || alu_zr) pc_load = 1'b1; // JGE alu_out >= 0
3'b100: if (alu_ng) pc_load = 1'b1; // JLT alu_out < 0
3'b101: if (!alu_zr) pc_load = 1'b1; // JNE alu_out != 0
3'b110: if (alu_ng || alu_zr) pc_load = 1'b1; // JLE alu_out <= 0
3'b111: pc_load = 1'b1; // JMP
default: pc_load = 1'b0;
endcase
end
pc_inc = 1'b1;
end else begin
pc_inc = 1'b0;
pc_load = 1'b0;
r_writeM = 1'b0;
end
r_addressM = ARegister[14:0];
pc_in = ARegister;
r_outM = alu_out;
end
always @(posedge clk) begin
// Alu_y input: If bit[12], the "a" bit is 1 then use M (inM) otherwise use A register content.
if (instruction[15] == 1 && instruction[12] == 1) begin
alu_y = inM;
end else begin
alu_y = ARegister;
end
end
always @(posedge clk) begin
if (timer == 3'd0) begin
if (instruction[15] == 0) begin
// A instruction
ARegister = {1'b0, instruction[14:0]};
end else begin
// C instruction
if (instruction[5] == 1) begin
ARegister = alu_out;
end
// If bit[4] "d2" is 1 then store ALU out (outM) in the D register
if (instruction[4] == 1) begin
DRegister = alu_out;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_1_V
`define SKY130_FD_SC_HD__NAND2_1_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_1_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int INF = 1e9 + 5; const long long LINF = LLONG_MAX; int main() { int t; cin >> t; while (t--) { int n; cin >> n; if (360 % (180 - n) == 0) cout << YES n ; else cout << NO n ; } } |
#include <bits/stdc++.h> using namespace std; bool field[100][100][100]; int n, m, k; bool check(int x, int y, int z) { return (x >= 0 && x < n && y >= 0 && y < m && z >= 0 && z < k && field[x][y][z]); } int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int x = 0; x < k; x++) { char v; cin >> v; field[i][j][x] = (v == 1 ); } } } int answer = 0; for (int x = 0; x < n; x++) { for (int y = 0; y < m; y++) { for (int z = 0; z < k; z++) { if (check(x, y, z)) { if ((check(x - 1, y, z) && check(x + 1, y, z)) || (check(x, y - 1, z) && check(x, y + 1, z)) || (check(x, y, z - 1) && check(x, y, z + 1))) { answer++; continue; } if (check(x - 1, y, z) && ((check(x, y + 1, z) && !check(x - 1, y + 1, z)) || (check(x, y, z + 1) && !check(x - 1, y, z + 1)))) { answer++; continue; } if (check(x, y - 1, z) && ((check(x + 1, y, z) && !check(x + 1, y - 1, z)) || (check(x, y, z + 1) && !check(x, y - 1, z + 1)))) { answer++; continue; } if (check(x, y, z - 1) && ((check(x, y + 1, z) && !check(x, y + 1, z - 1)) || (check(x + 1, y, z) && !check(x + 1, y, z - 1)))) { answer++; continue; } } } } } cout << answer << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFBBP_PP_BLACKBOX_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, t, b, c, m, n, ck = 0, ans = 0, sum = 0; cin >> t; cin.ignore(); while (t--) { ck = 0; cin >> a; cin.ignore(); string s; cin >> s; b = a - 10; for (int i = 0; i < b; i++) { if (s[i] == 8 ) { ck = 1; } } if (ck == 1) { cout << YES << endl; } else { cout << NO << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) #pragma comment(linker, /STACK:20000007 ) #pragma GCC optimize( unroll-loops ) const int N = (int)1e6 + 100; const int maxn = (int)1e3 + 100; const int base = (int)1e9; const int mod = (int)1e9 + 7; const int inf = INT_MAX; const long long ll_inf = LLONG_MAX; const long double PI = acos((long double)-1.0); const long double eps = 1e-8; int n, m, k; char ch[1003][1003]; bool mark[1003][1003]; int d[1003][1003]; int x, y, x1, y2; vector<int> dx = {1, 0, -1, 0}; vector<int> dy = {0, -1, 0, 1}; void bfs(int x, int y) { d[x][y] = 1; queue<pair<int, int> > Q; Q.push(make_pair(x, y)); while (!Q.empty()) { auto P = Q.front(); Q.pop(); int x, y; tie(x, y) = P; mark[x][y] = true; if (x == x1 && y == y2) return; for (int i = 0; i < 4; ++i) { for (int j = 1; j <= k; ++j) { int r = x, c = y; r += dx[i] * j; c += dy[i] * j; if (r < 1 || c < 1 || c > m || r > n || (ch[r][c] == # || (d[r][c] && d[r][c] <= d[x][y]))) break; if (d[r][c] > d[x][y] + 1) { d[r][c] = min(d[r][c], d[x][y] + 1); Q.push({r, c}); } else if (!d[r][c]) { d[r][c] = d[x][y] + 1; Q.push({r, c}); } } } } } void solve() { cin >> n >> m >> k; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> ch[i][j]; } } cin >> x >> y >> x1 >> y2; bfs(x, y); cout << --d[x1][y2] << n ; } int main() { int T = 1; for (; T; --T) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; enum { AABB, ABAB, ABBA, AAAA }; int n, k; string s1, s2, s3, s4; bool isvow(char c) { return (c == a || c == e || c == i || c == o || c == u ); } string suf(string s) { static int sp = 0; auto i = s.end(), beg = s.begin(); int tk = 0; while (tk < k && i > beg) { --i; tk += isvow(*i); } string res(i, s.end()); if (tk < k) { res = string(sp++, ); } return res; } void foo() { cout << NO n ; exit(0); } int main(void) { int i; cin >> n >> k; int ans = AAAA; for (i = 0; i < n; ++i) { cin >> s1 >> s2 >> s3 >> s4; auto suf1 = suf(s1), suf2 = suf(s2), suf3 = suf(s3), suf4 = suf(s4); if (suf1 == suf2 && suf2 == suf3 && suf3 == suf4) { } else if (suf1 == suf2 && suf3 == suf4) { if (ans == AAAA || ans == AABB) { ans = AABB; } else { foo(); } } else if (suf1 == suf3 && suf2 == suf4) { if (ans == AAAA || ans == ABAB) { ans = ABAB; } else { foo(); } } else if (suf1 == suf4 && suf2 == suf3) { if (ans == AAAA || ans == ABBA) { ans = ABBA; } else { foo(); } } else { foo(); } } switch (ans) { case AABB: cout << aabb n ; break; case ABAB: cout << abab n ; break; case ABBA: cout << abba n ; break; case AAAA: cout << aaaa n ; break; default: foo(); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// XTEA IP Core ////
//// ////
//// This file is part of the xtea project ////
//// http://www.opencores.org/projects.cgi/web/xtea/overview ////
//// ////
//// An implementation of the XTEA encryption algorithm. ////
//// ////
//// TODO: ////
//// * Write a spec ////
//// * Wishbone compliance ////
//// ////
//// Author: David Johnson, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006 David Johnson ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, write to the ////
//// Free Software Foundation, Inc., 51 Franklin Street, Fifth ////
//// Floor, Boston, MA 02110-1301 USA ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
module xtea(clock, reset, mode, data_in1, data_in2, key_in, data_out1, data_out2, all_done);
parameter s0 = 8'd0, s1 = 8'd1, s2 = 8'd2, s3 = 8'd3, s4 = 8'd4, s5 = 8'd5, s6 = 8'd6, s7 = 8'd7, s8 = 8'd8, s9 = 8'd9, s10 = 8'd10,
s11 = 8'd11, s12 = 8'd12, s13 = 8'd13, s14 = 8'd14, s15 = 8'd15, s16 = 8'd16, s17 = 8'd17;
input clock, reset, mode;
input[31:0] data_in1, data_in2;
input[127:0] key_in;
output[31:0] data_out1, data_out2;
output all_done;
wire clock, reset;
wire[31:0] data_in1, data_in2;
wire[127:0] key_in;
reg all_done, while_flag, modereg;
reg[1:0] selectslice;
reg[7:0] state;
reg[7:0] x;
reg[31:0] data_out1, data_out2, sum, workunit1, workunit2, delta;
always @(posedge clock or posedge reset)
begin
if (reset)
//reset state
state = s0;
else begin
case (state)
s0: state = s1;
s1: state = s2;
s2: state = s3;
s3: state = while_flag ? s4 : s14;
s4: state = modereg ? s10 : s5;
s5: state = s6;
s6: state = s7;
s7: state = s8;
s8: state = s9;
s9: state = s2;
s10: state = s11;
s11: state = s12;
s12: state = s13;
s13: state = s14;
s14: state = s2;
s15: state = s16;
s16: state = s17;
s17: state = s17;
default: state = 4'bxxxx;
endcase
end
end
always @(posedge clock or posedge reset)
begin
if (reset) begin
//reset all our outputs and registers
data_out1 = 32'h00000000;
data_out2 = 32'h00000000;
x = 8'b00000000;
sum = 32'h00000000;
while_flag = 1'b0;
workunit1 = 32'h00000000;
workunit2 = 32'h00000000;
selectslice = 1'b0;
all_done = 1'b0;
delta = 32'h00000000;
modereg = 1'b0;
end
else begin
case (state)
s1: begin
//store input values to registers in case they're not stable
workunit1 = data_in1;
workunit2 = data_in2;
delta = 32'h9E3779B9;
sum = 32'hc6ef3720;
modereg = mode;
end
s2: if (x < 8'd32) while_flag = 1'b1; else while_flag = 1'b0;
s3: begin
//This null state was necessary to fix a timing issue.
//s2 sets while_flag and previously the control path read it in the same state
//(but in the next clock cycle), however the reg wasn't set when we tried to
//read it, so this state was inserted to add a delay. This was when running @25MHz.
//FIXME: there's got to be a better solution to this...
end
s4: begin
//This state does nothing in the data path; it's used for an if statement in the
//control path.
end
/* States 5-9 used for decipher operations */
s5: selectslice = (sum >> 32'd11 & 32'd3);
s6: case (selectslice)
2'b00: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
2'b01: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
2'b10: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
2'b11: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
s7: sum = sum - delta;
s8: selectslice = (sum & 32'd3);
s9: begin
case (selectslice)
2'b00: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
2'b01: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
2'b10: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
2'b11: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
x = x + 1'b1;
end
/* States 10-14 used for encipher operations */
s10: selectslice = (sum & 32'd3);
s11: case (selectslice)
2'b00: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
2'b01: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
2'b10: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
2'b11: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
s12: sum = sum + delta;
s13: selectslice = (sum >> 32'd11 & 32'd3);
s14: begin
case (selectslice)
2'b00: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
2'b01: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
2'b10: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
2'b11: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
x = x + 1'b1;
end
s15: begin
//This state was added to fix a timing issue.
//Same issue as above - trying to read workunit1 & workunit2 before they've settled.
end
s16: begin
//set the outputs to the working registers
data_out1 = workunit1;
data_out2 = workunit2;
end
s17: all_done = 1'b1;
default: begin
data_out1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
data_out2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 101; int N, Q, freq[11]; char commands[MAXN], commands2[MAXN]; void solve(int l, int r) { l--; r--; for (int i = 0; i < N; i++) commands2[i] = commands[i]; for (int i = 0; i < 10; i++) freq[i] = 0; int cur = l; int dir = 1; int prev; while (cur >= l && cur <= r) { if (commands2[cur] == 0) cur += dir; else if (commands2[cur] == > ) { prev = cur; dir = 1; cur += dir; while (cur >= l && cur <= r && commands2[cur] == 0) cur += dir; if (cur < l || cur > r) break; if (commands2[cur] == < || commands2[cur] == > ) commands2[prev] = 0; } else if (commands2[cur] == < ) { prev = cur; dir = -1; cur += dir; while (cur >= l && cur <= r && commands2[cur] == 0) cur += dir; if (cur < l || cur > r) break; if (commands2[cur] == < || commands2[cur] == > ) commands2[prev] = 0; } else { freq[commands2[cur] - 0 ]++; commands2[cur]--; if (commands2[cur] < 0 ) commands2[cur] = 0; cur += dir; } } for (int i = 0; i < 10; i++) { printf( %d , freq[i]); if (i == 9) printf( n ); else printf( ); } } int main() { scanf( %d %d , &N, &Q); scanf( %s , commands); for (int i = 0; i < Q; i++) { int L, R; scanf( %d %d , &L, &R); solve(L, R); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_BLACKBOX_V
`define SKY130_FD_SC_LS__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, multiplier. This is a simple partial product adder
// that generates the product of the two inputs.
`timescale 1ps/1ps
module cf_mul (
// data_p = data_a (signed) * data_b (unsigned)
clk,
data_a,
data_b,
data_p,
// ddata_out is internal pipe-line matched for ddata_in
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
parameter DW = DELAY_DATA_WIDTH - 1;
input clk;
input [16:0] data_a;
input [ 7:0] data_b;
output [24:0] data_p;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
reg p1_sign = 'd0;
reg [DW:0] p1_ddata = 'd0;
reg [23:0] p1_data_p_0 = 'd0;
reg [23:0] p1_data_p_1 = 'd0;
reg [23:0] p1_data_p_2 = 'd0;
reg [23:0] p1_data_p_3 = 'd0;
reg [23:0] p1_data_p_4 = 'd0;
reg p2_sign = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [23:0] p2_data_p_0 = 'd0;
reg [23:0] p2_data_p_1 = 'd0;
reg p3_sign = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [23:0] p3_data_p_0 = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [24:0] data_p = 'd0;
wire [16:0] p1_data_a_1p_17_s;
wire [16:0] p1_data_a_1n_17_s;
wire [23:0] p1_data_a_1p_s;
wire [23:0] p1_data_a_1n_s;
wire [23:0] p1_data_a_2p_s;
wire [23:0] p1_data_a_2n_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_a_1p_17_s = {1'b0, data_a[15:0]};
assign p1_data_a_1n_17_s = ~p1_data_a_1p_17_s + 1'b1;
assign p1_data_a_1p_s = {{7{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s};
assign p1_data_a_1n_s = {{7{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s};
assign p1_data_a_2p_s = {{6{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s, 1'b0};
assign p1_data_a_2n_s = {{6{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s, 1'b0};
// pipe line stage 1, get the partial products
always @(posedge clk) begin
p1_sign <= data_a[16];
p1_ddata <= ddata_in;
case (data_b[1:0])
2'b11: p1_data_p_0 <= p1_data_a_1n_s;
2'b10: p1_data_p_0 <= p1_data_a_2n_s;
2'b01: p1_data_p_0 <= p1_data_a_1p_s;
default: p1_data_p_0 <= 24'd0;
endcase
case (data_b[3:1])
3'b011: p1_data_p_1 <= {p1_data_a_2p_s[21:0], 2'd0};
3'b100: p1_data_p_1 <= {p1_data_a_2n_s[21:0], 2'd0};
3'b001: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b010: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b101: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
3'b110: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
default: p1_data_p_1 <= 24'd0;
endcase
case (data_b[5:3])
3'b011: p1_data_p_2 <= {p1_data_a_2p_s[19:0], 4'd0};
3'b100: p1_data_p_2 <= {p1_data_a_2n_s[19:0], 4'd0};
3'b001: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b010: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b101: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
3'b110: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
default: p1_data_p_2 <= 24'd0;
endcase
case (data_b[7:5])
3'b011: p1_data_p_3 <= {p1_data_a_2p_s[17:0], 6'd0};
3'b100: p1_data_p_3 <= {p1_data_a_2n_s[17:0], 6'd0};
3'b001: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b010: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b101: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
3'b110: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
default: p1_data_p_3 <= 24'd0;
endcase
case (data_b[7])
1'b1: p1_data_p_4 <= {p1_data_a_1p_s[15:0], 8'd0};
default: p1_data_p_4 <= 24'd0;
endcase
end
// pipe line stage 2, get the sum (intermediate 5 -> 2)
always @(posedge clk) begin
p2_sign <= p1_sign;
p2_ddata <= p1_ddata;
p2_data_p_0 <= p1_data_p_0 + p1_data_p_1 + p1_data_p_4;
p2_data_p_1 <= p1_data_p_2 + p1_data_p_3;
end
// pipe line stage 2, get the sum (final 2 -> 1)
always @(posedge clk) begin
p3_sign <= p2_sign;
p3_ddata <= p2_ddata;
p3_data_p_0 <= p2_data_p_0 + p2_data_p_1;
end
// output registers (truncation occurs after addition, see cf_add.v)
always @(posedge clk) begin
ddata_out <= p3_ddata;
data_p <= {p3_sign, p3_data_p_0};
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int a[n]; vector<int> ans; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); ans.push_back(a[0]); for (int i = 1; i < n; i++) { if (a[i] != ans.back()) ans.push_back(a[i]); } bool got = false; int len = ans.size(); for (int i = 0; i < len - 2; i++) { if ((ans[i + 1] - ans[i] < 3 && ans[i + 2] - ans[i] < 3 && ans[i + 2] - ans[i + 1] < 3)) { got = true; break; } } cout << (got ? YES n : NO n ); return 0; } |
`timescale 1 ps / 1 ps
(* message_disable = "14320" *) module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8,
REGISTER_OUTPUT = 0
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
localparam BUFFER_REGISTER_OUTPUT = (REGISTER_OUTPUT) ? "CLOCK0" : "UNREGISTERED";
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = BUFFER_REGISTER_OUTPUT,
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[1002], l, n; scanf( %d %d , &n, &l); for (int i = 0; i < n; i++) scanf( %d , a + i); sort(a, a + n); double d = max(a[0] - 0, l - a[n - 1]); for (int i = n - 1; i > 0; i--) d = max(d, double(a[i] - a[i - 1]) / 2); printf( %0.10lf , d); } |
#include <bits/stdc++.h> using namespace std; template <typename T> void display(T a[], int size) { for (int i = 0; i < size; i++) { cout << a[i] << ; } cout << endl; } void display(vector<pair<int, int> > a) { for (int i = 0; i < a.size(); i++) { cout << ( << a[i].first << , << a[i].second << ) << ; } cout << endl; } void display(vector<int> a) { for (int i = 0; i < a.size(); i++) { cout << a[i]; if (i == a.size() - 1) cout << endl; else cout << ; } } template <typename T> void initialise(T a[], T value, int length) { for (int i = 0; i < length; i++) a[i] = value; } template <typename T> void initialise(vector<T>& a, T value) { for (int i = 0; i < a.size(); i++) a[i] = value; } bool compare(pair<int, int> a, pair<int, int> b) { if (a.first != b.first) return a.first < b.first; else return a.second < b.second; } int max(int a[], int n) { int max = -1000000000; for (int i = 0; i < n; i++) { if (a[i] > max) max = a[i]; } return max; } bool find(string a[], string s, int n) { int left = 0; int right = n - 1; while (left < right) { int mid = (left + right) / 2; if (s.compare(a[mid]) == 0) return true; else if (s.compare(a[mid]) < 0) { right = mid; } else { left = mid + 1; } } return false; } void factor(int a[], int base, int num, int n) { for (int i = n - 1; i >= 0; i--) { a[i] = num % base; num = num / base; } } int findLength(int n, int base) { int i = 0; while (n > 0) { i++; n = n / base; } return i; } int gcd(int a, int b) { while (a % b != 0 && b % a != 0) { if (b > a) { b = b % a; } else if (a > b) { a = a % b; } } if (a <= b) return a; else return b; } int main() { int n, m; cin >> n >> m; list<int> son[n]; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; son[u - 1].push_back(v - 1); son[v - 1].push_back(u - 1); } int side[n]; initialise(side, -1, n); for (int i = 0; i < n; i++) { if (side[i] != -1) continue; queue<int> q; q.push(i); side[i] = 0; while (!q.empty()) { int current = q.front(); q.pop(); for (auto fil : son[current]) { if (side[fil] == -1) { side[fil] = 1 - side[current]; q.push(fil); } else if (side[fil] == side[current]) { cout << -1 << endl; return 0; } else continue; } } } vector<int> zero; vector<int> one; for (int i = 0; i < n; i++) { if (side[i] == 0) zero.push_back(i + 1); else one.push_back(i + 1); } cout << zero.size() << endl; for (int i = 0; i < zero.size(); i++) { cout << zero[i]; if (i == zero.size() - 1) cout << endl; else cout << ; } cout << one.size() << endl; for (int i = 0; i < one.size(); i++) { cout << one[i]; if (i == one.size() - 1) cout << endl; else cout << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename S> inline T smax(T &a, const S &b) { return a < b ? a = b : a; } int n, s, m, k, a[int(1500 + 20)], l[int(1500 + 20)], r[int(1500 + 20)], id[int(1500 + 20)]; int psum[int(1500 + 20)], dp[int(1500 + 20)][int(1500 + 20)], pos[int(1500 + 20)]; inline bool check(int val) { for (int i = 1; i <= n; i++) { psum[i] = psum[i - 1] + ((a[i] <= val) ? 1 : 0); for (int j = 1; j <= m; j++) { dp[i][j] = dp[i - 1][j]; if (!~pos[i]) continue; int L = l[pos[i]]; smax(dp[i][j], dp[L - 1][j - 1] + psum[i] - psum[L - 1]); L = r[id[pos[i]]]; smax(dp[i][j], dp[L][j - 1] + psum[i] - psum[L]); } } return dp[n][m] >= k; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.tie(0); cin >> n >> s >> m >> k; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 0; i < s; i++) cin >> l[i] >> r[i]; memset(id, -1, sizeof(id)); memset(pos, -1, sizeof(pos)); for (int i = 0; i < s; i++) { if (!~pos[r[i]] || l[pos[r[i]]] > l[i]) pos[r[i]] = i; for (int j = 0; j < s; j++) if (r[j] <= r[i] && r[j] >= l[i]) if (!~id[i] || l[id[i]] > l[j]) id[i] = j; } int lo = 0, hi = 1e9 + 2; while (lo != hi - 1) { int mid = (long long)lo + hi >> 1; if (check(mid)) hi = mid; else lo = mid; } if (!check(hi)) hi = -1; cout << hi << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:33:33 08/26/2015
// Design Name:
// Module Name: VerificadorSentidoMovimiento
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
*Módulo encargado de decidir el movimiendo y la dirección del ascensor mediante
*lógica combinacional entre el valor del registro de solicitudes y el piso actual.
*Tiene como entradas los 10 bits del registro de solicitudes y los 3 bits del código
*Grey identificador de cada piso y el clock. Tiene como salidas 2 bits que idicarán la
*habilitación del motor (MSB) 0=apagado, 1=activado y la dirección(LSB) 0=subir, 1=bajar .
*/
module VerificadorSentidoMovimiento(
_clk_,
FSM_ready_in,
piso_actual,
solicitud_ps,
solicitud_p1,
solicitud_p2,
solicitud_p3,
solicitud_p4,
accion,
clear_solicitud_ps,
clear_solicitud_p1,
clear_solicitud_p2,
clear_solicitud_p3,
clear_solicitud_p4
);
input [2:0] piso_actual;
input [1:0] solicitud_ps, solicitud_p1, solicitud_p2, solicitud_p3, solicitud_p4;
input _clk_, FSM_ready_in;
output reg [1:0] accion;
always @(posedge _clk_)
begin
//acciones para el sotano
if (piso_actual == 3'b000)
begin
if (solicitud_ps == 2'bx1) //No realiza accion
accion <= 2'b00;
if (solicitud_ps == 2'bx0)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_p1 == 2'bx0 | solicitud_p2 == 2'bx0 | solicitud_p3 == 2'bx0 | solicitud_p4 == 2'bx0)
accion <= 2'b10;
end
//acciones para el piso1
else if (piso_actual == 3'b001)
begin
if (solicitud_p1 == 2'bxx)
accion <= 01;
if (solicitud_ps == 2'bx1)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_p2 == 2'b1x)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_p3 == 2'b1x | solicitud_p4 == 2'b1x)
accion <= 2'b10;
else if (solicitud_p3 == 2'bx1 | solicitud_p4 == 2'bx1)
accion <= 2'b11;
end
//acciones para el piso2
else if (piso_actual == 3'b010)
begin
if (solicitud_p2 == 2'bxx)
accion <= 01;
if (solicitud_p1 == 2'bx1)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_p3 == 2'b1x)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_ps == 2'b1x | solicitud_p3 == 2'b1x)
accion <= 2'b10;
else if (solicitud_ps == 2'bx1 | solicitud_p3 == 2'bx1)
accion <= 2'b11;
end
//acciones para el piso3
else if (piso_actual == 3'b011)
begin
if (solicitud_p3 == 2'bxx)
accion <= 01;
if (solicitud_p2 == 2'bx1)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_p4 == 2'b1x)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_ps == 2'b1x | solicitud_p1 == 2'b1x)
accion <= 2'b10;
else if (solicitud_ps == 2'bx1 | solicitud_p1 == 2'bx1)
accion <= 2'b11;
end
//acciones para el piso 4
else if (piso_actual == 3'b100)
begin
if (solicitud_p4 == 2'b1x) //No realiza accion
accion <= 2'b00;
if (solicitud_p4 == 2'b0x)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_ps == 2'b0x | solicitud_p1 == 2'b0x | solicitud_p2 == 2'b0x | solicitud_p3 == 2'b0x)
accion <= 2'b11;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { while (b) b ^= a ^= b ^= a %= b; return a; } template <class T> inline T lcm(T a, T b) { a = abs(a); b = abs(b); return (a / gcd(a, b)) * b; } template <class T> inline T my_strrev(T array) { int N = strlen(array); for (int i = 0; i < N / 2; ++i) swap(array[i], array[N - i - 1]); } template <class T> inline T my_revara(T array, int N) { for (int i = 0; i < N / 2; ++i) swap(array[i], array[N - i - 1]); } int fx[8] = {0, -1, 1, 1, 1, 0, -1, -1}; int fy[8] = {1, 0, 1, -1, 0, -1, -1, 1}; int main() { string str1, str2; cin >> str1; cin >> str2; int len = str1.length(); int flag = 0; for (int i = 0; i < len; i++) { if (flag == 1) { if (str2[i] != a ) { str2[i] = str2[i] - 1; cout << str2 << endl; return 0; } if (str1[i] != z ) { str1[i] = str1[i] + 1; cout << str1 << endl; return 0; } } if (str2[i] > str1[i]) { if (str2[i] - str1[i] > 1) { str1[i] = str1[i] + 1; cout << str1 << endl; return 0; } flag = 1; } } printf( No such string n ); return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
module avconf ( // Host Side
CLOCK_50,
reset,
// I2C Side
I2C_SCLK,
I2C_SDAT );
// Host Side
input CLOCK_50;
input reset;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
wire iRST_N = !reset;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
parameter USE_MIC_INPUT = 1'b0;
parameter AUD_LINE_IN_LC = 9'd24;
parameter AUD_LINE_IN_RC = 9'd24;
parameter AUD_LINE_OUT_LC = 9'd119;
parameter AUD_LINE_OUT_RC = 9'd119;
parameter AUD_ADC_PATH = 9'd17;
parameter AUD_DAC_PATH = 9'd6;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'd77;
parameter AUD_SAMPLE_CTRL = 9'd0;
parameter AUD_SET_ACTIVE = 9'h001;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 50;
// Audio Data Index
parameter SET_LIN_L = 0;
parameter SET_LIN_R = 1;
parameter SET_HEAD_L = 2;
parameter SET_HEAD_R = 3;
parameter A_PATH_CTRL = 4;
parameter D_PATH_CTRL = 5;
parameter POWER_ON = 6;
parameter SET_FORMAT = 7;
parameter SAMPLE_CTRL = 8;
parameter SET_ACTIVE = 9;
// Video Data Index
parameter SET_VIDEO = 10;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge CLOCK_50 or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
if(LUT_INDEX<SET_VIDEO)
mI2C_DATA <= {8'h34,LUT_DATA};
else
mI2C_DATA <= {8'h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
SET_LIN_L : LUT_DATA <= {7'h0, AUD_LINE_IN_LC};
SET_LIN_R : LUT_DATA <= {7'h1, AUD_LINE_IN_RC};
SET_HEAD_L : LUT_DATA <= {7'h2, AUD_LINE_OUT_LC};
SET_HEAD_R : LUT_DATA <= {7'h3, AUD_LINE_OUT_RC};
A_PATH_CTRL : LUT_DATA <= {7'h4, AUD_ADC_PATH} + (16'h0004 * USE_MIC_INPUT);
D_PATH_CTRL : LUT_DATA <= {7'h5, AUD_DAC_PATH};
POWER_ON : LUT_DATA <= {7'h6, AUD_POWER};
SET_FORMAT : LUT_DATA <= {7'h7, AUD_DATA_FORMAT};
SAMPLE_CTRL : LUT_DATA <= {7'h8, AUD_SAMPLE_CTRL};
SET_ACTIVE : LUT_DATA <= {7'h9, AUD_SET_ACTIVE};
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h503f; // 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h503f; // 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h2778; // 16'h503f; // 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0860;
SET_VIDEO+31: LUT_DATA <= 16'h0a18;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df8;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int INF = (long long int)1e9 + 10; const long long int INFLL = (long long int)1e18 + 10; const long double EPS = 1e-8; const long double EPSLD = 1e-18; const long long int MOD = 1e9 + 7; template <class T> T &chmin(T &a, const T &b) { return a = min(a, b); } template <class T> T &chmax(T &a, const T &b) { return a = max(a, b); } namespace std { template <class T> bool operator<(const complex<T> &a, const complex<T> &b) { return a.real() == b.real() ? a.imag() < b.imag() : a.real() < b.real(); } } // namespace std long long int dot(complex<long long int> a, complex<long long int> b) { return (conj(a) * b).real(); } long long int cross(complex<long long int> a, complex<long long int> b) { return (conj(a) * b).imag(); } long long int ccw(complex<long long int> a, complex<long long int> b, complex<long long int> c) { b -= a, c -= a; if (cross(b, c) > 0) return +1; if (cross(b, c) < 0) return -1; if (dot(b, c) < 0) return +2; if (norm(b) < norm(c)) return -2; return 0; } inline bool cross(const complex<long long int> &a, const complex<long long int> &b, const complex<long long int> &c, const complex<long long int> &d) { return ccw(a, c, b) * ccw(a, d, b) == -1 && ccw(c, a, d) * ccw(c, b, d) == -1; } vector<complex<long long int> > convex_hull( vector<complex<long long int> > ps) { int n = ((long long int)(ps).size()); int k = 0; sort((ps).begin(), (ps).end()); vector<complex<long long int> > ch(2 * n); for (int i = 0; i < n; ch[k++] = ps[i++]) while (k >= 2 && ccw(ch[k - 2], ch[k - 1], ps[i]) <= 0) k--; for (int i = n - 2, t = k + 1; i >= 0; ch[k++] = ps[i--]) while (k >= t && ccw(ch[k - 2], ch[k - 1], ps[i]) <= 0) k--; ch.resize(k - 1); return ch; } enum { OUT, ON, IN }; int contains(const vector<complex<long long int> > pol, const complex<long long int> p) { bool in = false; for (int i = 0; i < pol.size(); ++i) { complex<long long int> a = pol[i] - p, b = pol[(i + 1) % pol.size()] - p; if (imag(a) > imag(b)) swap(a, b); if (imag(a) <= 0 && 0 < imag(b)) if (cross(a, b) < 0) in = !in; if (cross(a, b) == 0 && dot(a, b) <= 0) return ON; } return in ? IN : OUT; } long long int n, r; long long int ansv; vector<complex<long long int> > ans; vector<complex<long long int> > cp; vector<complex<long long int> > ps; void dfs(long long int c, long long int k, long long int res) { if (c == n) { if (ansv < res) { ansv = res; ans = cp; } return; } for (long long int i = (k); i < (long long int)(((long long int)(ps).size())); i++) { long long int nres = res; for (long long int j = (0); j < (long long int)(c); j++) nres += norm(ps[i] - cp[j]); cp.emplace_back(ps[i]); dfs(c + 1, i, nres); cp.pop_back(); } } int main() { scanf( %lld %lld , &n, &r); for (long long int i = (-r); i < (long long int)(r + 1); i++) for (long long int j = (-r); j < (long long int)(r + 1); j++) if (i * i + j * j <= r * r) ps.emplace_back(complex<long long int>(i, j)); ps = convex_hull(ps); if (n % 2 == 0) ps = {complex<long long int>(r, 0), complex<long long int>(-r, 0)}; dfs(0, 0, 0); printf( %lld n , ansv); for (auto &w : ans) printf( %lld %lld n , w.real(), w.imag()); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; __int128 read() { __int128 x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void print(__int128 x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) print(x / 10); putchar(x % 10 + 0 ); } __int128 gcd(__int128 a, __int128 b) { return b ? gcd(b, a % b) : a; } __int128 ex_gcd(__int128 a, __int128 b, __int128& x, __int128& y) { if (b == 0) { x = 1; y = 0; return a; } __int128 d = ex_gcd(b, a % b, x, y); __int128 temp = x; x = y; y = temp - a / b * y; return d; } bool liEu(__int128 a, __int128 b, __int128 c, __int128& x, __int128& y) { __int128 d = ex_gcd(a, b, x, y); if (c % d != 0) return 0; __int128 k = c / d; x *= k; y *= k; return 1; } signed main() { __int128 n, p, w, d; n = read(); p = read(); w = read(); d = read(); __int128 x, y; if (!liEu(w, d, p, x, y)) return (std::cout << -1 n , 0); __int128 t = d / gcd(w, d); __int128 xt = (x % t + t) % t; __int128 yt = (p - w * xt) / d; if (xt >= 0 && yt >= 0 && xt + yt <= n) { print(xt); printf( ); print(yt); printf( ); print(n - xt - yt); printf( n ); return 0; } t = w / gcd(w, d); yt = (y % t + t) % t; xt = (p - d * yt) / w; if (xt >= 0 && yt >= 0 && xt + yt <= n) { print(xt); printf( ); print(yt); printf( ); print(n - xt - yt); printf( n ); return 0; } std::cout << -1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; bool matrix[5205][5205]; char inp[1305]; vector<int> divivi; int func(char c) { if (c >= 0 && c <= 9 ) return c - 0 ; else return c - A + 10; } bool check(int x, int n) { int i, j, r, c, ini; for (r = 0; r < n / x; r++) { for (c = 0; c < n / x; c++) { ini = matrix[r * x][c * x]; for (i = 0; i < x; i++) for (j = 0; j < x; j++) if (matrix[r * x + i][c * x + j] != ini) return 0; } } return 1; } int main() { int n, i, j, cal; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s n , inp); for (j = 0; j < n / 4; j++) { cal = func(inp[j]); matrix[i][j * 4] = (cal & 8); matrix[i][j * 4 + 1] = (cal & 4); matrix[i][j * 4 + 2] = (cal & 2); matrix[i][j * 4 + 3] = (cal & 1); } } for (i = 1; i <= n; i++) if (n % i == 0) divivi.push_back(i); for (i = divivi.size() - 1; i >= 1; i--) if (check(divivi[i], n)) { printf( %d n , divivi[i]); return 0; } printf( %d n , divivi[0]); return 0; } |
#include <bits/stdc++.h> using namespace std; struct EDGE { int to, next, w, co; } e[100000]; int head[100], top, vis[100000]; void add(int u, int v, int w, int co) { e[top].to = v; e[top].w = w; e[top].co = co; e[top].next = head[u]; head[u] = top++; } struct _ { int max_flow, co; }; int dis[100], vvis[100], prep[100], pree[100]; queue<int> q; deque<int> node; void spfa(int s) { memset(dis, 63, sizeof(dis)); memset(vvis, 0, sizeof(vvis)); dis[s] = 0; q.push(s); int i; while (!q.empty()) { s = q.front(); q.pop(); vvis[s] = 0; int i; for (i = head[s]; ~i; i = e[i].next) { if (!e[i].w) continue; if (dis[s] + e[i].co < dis[e[i].to]) { dis[e[i].to] = dis[s] + e[i].co; pree[e[i].to] = i; prep[e[i].to] = s; if (vvis[e[i].to]) continue; vvis[e[i].to] = 1; q.push(e[i].to); } } } } _ dfs(int s, int t, int rest) { int flow = 998244353, co = 0; int temp = t; _ rv; while (t != s) { flow = min(flow, e[pree[t]].w); co += e[pree[t]].co; t = prep[t]; } if (co > 0) flow = min(flow, rest / co); if (flow == 0) return rv = (_){0, 0}; t = temp; while (t != s) { temp = pree[t]; e[temp].w -= flow; e[temp ^ 1].w += flow; t = prep[t]; } rv = (_){flow, co}; return rv; } long long EK(int s, int t, int rest) { long long sum = 0; _ _; while (1) { spfa(s); if (dis[t] > 998244353) break; _ = dfs(s, t, rest); if (_.max_flow == 0) break; sum += _.max_flow; rest -= _.max_flow * _.co; } return sum; } int main() { memset(head, 255, sizeof(head)); int n, k; scanf( %d%d , &n, &k); int i, j, t; for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { scanf( %d , &t); if (t) { add(i, j, t, 0); add(j, i, 0, 0); add(i, j, k, 1); add(j, i, 0, -1); } } } long long ans = EK(1, n, k); printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-12; const int inf = 2000000000; const long long int infLL = (long long int)1e18; long long int MOD = 1000000007; int MOD1 = 1000000007; int MOD2 = 1000000009; inline bool checkBit(long long int n, long long int i) { return n & (1LL << i); } inline long long int setBit(long long int n, long long int i) { return n | (1LL << i); ; } inline long long int resetBit(long long int n, long long int i) { return n & (~(1LL << i)); } int dx[] = {0, 0, +1, -1}; int dy[] = {+1, -1, 0, 0}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long int year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long int &a) { a %= MOD; (a < 0) && (a += MOD); } inline long long int modMul(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a * b) % MOD; } inline long long int modAdd(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a + b) % MOD; } inline long long int modSub(long long int a, long long int b) { a %= MOD, b %= MOD; normal(a), normal(b); a -= b; normal(a); return a; } inline long long int modPow(long long int b, long long int p) { long long int r = 1LL; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1LL; } return r; } inline long long int modDiv(long long int a, long long int b) { return modMul(a, modPow(b, MOD - 2)); } bool comp(const pair<long long int, pair<long long int, long long int> > &p1, const pair<long long int, pair<long long int, long long int> > &p2) { return p1.first > p2.first; } bool comp1(const pair<long long int, long long int> &p1, const pair<long long int, long long int> &p2) { if (p1.first == p2.first) { return p1.second > p2.second; } return p1.first < p2.first; } long long int converter(string a) { long long int i, mul = 1LL, r, t, ans = 0LL; if (a.length() == 0) return 0; for (i = a.length() - 1; i >= 0; i--) { t = a[i] - 0 ; r = t % 10; ans += (mul * r); mul = mul * 10; } return ans; } int msb(unsigned x) { union { double a; int b[2]; }; a = x; return (b[1] >> 20) - 1023; } const int MAX = 400005; long long int n, b, a[MAX]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cout.unsetf(ios::floatfield); cout.precision(20); cout.setf(ios::fixed, ios::floatfield); ; cin >> n >> b; memset(a, -1, sizeof(a)); for (int i = 1; i <= n; ++i) cin >> a[i]; long long int tol = (b * 8LL) / n; long long int k = pow(2LL, tol); sort(a + 1, a + n + 1); int d = 0, len = 0, i = 1, j = 0, maxi = 0; while (i <= n) { while (1) { if ((d == k && a[j] != a[j + 1]) || (j == n)) break; else { if (a[j] != a[j + 1]) ++d; ++len; ++j; } } maxi = max(maxi, len); int savei = i; while (1) { if (a[i] == a[savei]) ++i, --len; else { --d; break; } } } cout << n - maxi << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e2 + 1; int n, m, q, ans[MAX][MAX], t[MAX][MAX][2]; int main() { ios_base::sync_with_stdio(0); cin >> n >> m >> q; for (int i = 1; i < n + 1; i++) for (int j = 1; j < m + 1; j++) { t[i][j][0] = i; t[i][j][1] = j; } while (q--) { int ty; cin >> ty; if (ty == 1) { int x; cin >> x; int x1 = t[x][1][0], y1 = t[x][1][1]; for (int i = 1; i < m; i++) { t[x][i][0] = t[x][i + 1][0]; t[x][i][1] = t[x][i + 1][1]; } t[x][m][0] = x1; t[x][m][1] = y1; } else if (ty == 2) { int x; cin >> x; int x1 = t[1][x][0], y1 = t[1][x][1]; for (int i = 1; i < n; i++) { t[i][x][0] = t[i + 1][x][0]; t[i][x][1] = t[i + 1][x][1]; } t[n][x][0] = x1; t[n][x][1] = y1; } else { int x, y, z; cin >> x >> y >> z; ans[t[x][y][0]][t[x][y][1]] = z; } } for (int i = 1; i < n + 1; i++) { for (int j = 1; j < m + 1; j++) cout << ans[i][j] << ; cout << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_BLACKBOX_V
`define SKY130_FD_SC_HVL__A21O_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a21o (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int N; scanf( %d , &N); int P; scanf( %d , &P); vector<int> As, Bs; long long SA = 0, SB = 0; for (decltype(N) _i = 0, _n = (N); _i < _n; _i++) { int A; scanf( %d , &A); int B; scanf( %d , &B); As.push_back(A); Bs.push_back(B); SA += A; SB += B; } auto check = [&](double t) { double tmp = 0.0; for (decltype(N) i = 0, _n = (N); i < _n; i++) { tmp += max(As[i] * t - Bs[i], 0.0) / P; } return tmp <= t; }; if (SA <= P) { printf( -1 n ); } else { double l = 0.0, r = SB * 2.0; int cnt = 0; while (1e-10 < (r - l) and cnt < 1000) { cnt++; double c = (l + r) / 2; if (check(c)) { l = c; } else { r = c; } } printf( %f , l); } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module ram32_2sum (input clock, input write,
input [4:0] wr_addr, input [15:0] wr_data,
input [4:0] rd_addr1, input [4:0] rd_addr2,
output reg [15:0] sum);
reg [15:0] ram_array [0:31];
wire [16:0] sum_int;
always @(posedge clock)
if(write)
ram_array[wr_addr] <= #1 wr_data;
assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
always @(posedge clock)
sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
endmodule // ram32_2sum
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: memidxrng.v,v 1.1 2001/09/29 05:03:41 sib4 Exp $
// $Log: memidxrng.v,v $
// Revision 1.1 2001/09/29 05:03:41 sib4
// add memidxrng.v: memory address range check
//
module memidxrng;
reg mem[12:2];
reg [7:0] i;
integer errs = 0;
initial
begin
for (i=0; i<255; i=i+1) mem[i] <= ^i;
#1;
for (i=0; i<17; i=i+1)
$display("mem[%d] = %b \%b", i, mem[i], ^i);
if (mem[13] !== 1'bx)
begin
$display("FAILED: mem[13] = %b, expect x", mem[14]);
errs = errs + 1;
end
if (mem[1] !== 1'bx)
begin
$display("FAILED: mem[1] = %b, expect x", mem[1]);
errs = errs + 1;
end
if (errs===0)
$display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1111], x, n, s, y, o, oo; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x; if (x == 0 || x == 100) a[s++] = x; else if (x < 10 && o == 0) a[s++] = x, o = 1; else if (x % 10 == 0 && oo == 0) a[s++] = x, oo = 1; else y = x; } if (o == 0 && oo == 0 && y != 0) a[s++] = y; cout << s << endl; for (int i = 0; i < s; i++) cout << a[i] << ; return 0; } |
// LUT and DFF are combined to a GENERIC_SLICE
module LUT #(
parameter K = 4,
parameter [2**K-1:0] INIT = 0
) (
input [K-1:0] I,
output Q
);
wire [K-1:0] I_pd;
genvar ii;
generate
for (ii = 0; ii < K; ii = ii + 1'b1)
assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
endgenerate
assign Q = INIT[I_pd];
endmodule
module DFF (
input CLK, D,
output reg Q
);
initial Q = 1'b0;
always @(posedge CLK)
Q <= D;
endmodule
module GENERIC_SLICE #(
parameter K = 4,
parameter [2**K-1:0] INIT = 0,
parameter FF_USED = 1'b0
) (
input CLK,
input [K-1:0] I,
output F,
output Q
);
wire f_wire;
LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
assign F = f_wire;
endmodule
module GENERIC_IOB #(
parameter INPUT_USED = 1'b0,
parameter OUTPUT_USED = 1'b0,
parameter ENABLE_USED = 1'b0
) (
inout PAD,
input I, EN,
output O
);
generate if (OUTPUT_USED && ENABLE_USED)
assign PAD = EN ? I : 1'bz;
else if (OUTPUT_USED)
assign PAD = I;
endgenerate
generate if (INPUT_USED)
assign O = PAD;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int LIM = 200 * 1000, MAXN = 300 * 1000; int fen[MAXN]; void add(int pos, int val) { pos++; while (pos < MAXN) { fen[pos] += val; pos += pos & -pos; } } int sum(int pos) { pos++; int tot = 0; while (pos) { tot += fen[pos]; pos -= pos & -pos; } return tot; } bool by_id(pair<pair<int, int>, pair<int, int> > a, pair<pair<int, int>, pair<int, int> > b) { return a.second.first < b.second.first; } vector<int> occ[MAXN]; int pt[MAXN], a[MAXN], n, q; pair<pair<int, int>, pair<int, int> > seg[MAXN]; int main() { cin >> n >> q; for (int i = 0; i < int(n); i++) { cin >> a[i]; if (a[i] < LIM) occ[a[i]].push_back(i); } for (int i = 1; i < int(LIM); i++) if (i <= (int((occ[i]).size()))) { pt[i] = i - 1; add(occ[i][pt[i]], 1); if (pt[i] + 1 < (int((occ[i]).size()))) add(occ[i][pt[i] + 1], -1); } else pt[i] = (int((occ[i]).size())); cerr << Salam :) << endl; for (int i = 0; i < int(q); i++) { seg[i].second.first = i; cin >> seg[i].first.first >> seg[i].first.second; seg[i].first.first--; seg[i].first.second--; } sort(seg, seg + q); int cur = 0; for (int i = 0; i < int(n); i++) { while (cur < q && seg[cur].first.first == i) { seg[cur].second.second = sum(seg[cur].first.second); cur++; } int x = a[i]; if (x < LIM && pt[x] < (int((occ[x]).size()))) { add(occ[x][pt[x]], -1); if (pt[x] + 1 < (int((occ[x]).size()))) add(occ[x][pt[x] + 1], +1); pt[x]++; if (pt[x] < (int((occ[x]).size()))) { add(occ[x][pt[x]], 1); if (pt[x] + 1 < (int((occ[x]).size()))) add(occ[x][pt[x] + 1], -1); } } } sort(seg, seg + q, by_id); for (int i = 0; i < int(q); i++) cout << seg[i].second.second << endl; return 0; } |
/***********************************************
Module Name: CORDIC
Feature: CORDIC algorithm
An example for the GEM Projects
Coder: Garfield
Organization: xxxx Group, Department of Architecture
------------------------------------------------------
Input ports: clk: System clock
Reset_n: System reset
opernd: input number to be calculated
Output Ports: results: results of operation
------------------------------------------------------
History:
06-21-2016: First Version by Garfield
06-21-2016: Verified by CORDIC_Test
***********************************************/
`define ORDER 12
// CORDIC order by simulation
`define WIDTH 15
//CORDIC ports bit width by simulatation
`define K 14'h26DD
module CORDIC
#(parameter MODE = 1)
//CORDIC Mode
(
CLK,
RESET_n,
operand,
results
);
localparam PORT_WIDTH = (MODE == 3) ? (7 + `WIDTH) : ( (MODE == 2) ? (2 + `WIDTH) :(`WIDTH));
localparam IN_WIDTH = 2 * PORT_WIDTH;
localparam OUT_WIDTH = 2 * PORT_WIDTH;
localparam ONE = 15'd16384;
input CLK;
input RESET_n;
input signed[(IN_WIDTH - 1) : 0] operand;
output signed[(OUT_WIDTH - 1) : 0] results;
wire[(PORT_WIDTH-1):0] x[(`ORDER+1):0];
wire[(PORT_WIDTH-1):0] y[(`ORDER+1):0];
wire[(PORT_WIDTH-1):0] z[(`ORDER+1):0];
//middle signals
generate
begin
case(MODE)
1:
begin
assign x[0] = `K;
assign y[0] = 14'h0;
assign z[0] = operand[PORT_WIDTH -1 : 0];
end
2:
begin
assign x[0] = ONE;
assign y[0] = operand[PORT_WIDTH -1 : 0];
assign z[0] = 14'h0;
end
3:
begin
assign x[0] = operand[PORT_WIDTH -1 : 0];
assign y[0] = operand[2*PORT_WIDTH -1 : PORT_WIDTH];
assign z[0] = 14'h0;
end
default:
begin
assign x[0] = `K;
assign y[0] = 14'h0;
assign z[0] = operand[PORT_WIDTH -1 : 0];
end
endcase
end
endgenerate
generate
begin
case(MODE)
1:
begin
assign results = {x[13], y[13]};
end
2:
begin
assign results = {{(PORT_WIDTH){1'b0}}, z[13]};
end
3:
begin
assign results = {{(PORT_WIDTH){1'b0}}, x[13]};
end
default:
begin
assign results = {x[13], y[13]};
end
endcase
end
endgenerate
//CORDIC pipeline
//Connection to the modules
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h3243), .ORDER(0), .MODE(MODE) )
CE0 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[0]), .y_k(y[0]), .z_k(z[0]),
.x_k1(x[1]), .y_k1(y[1]), .z_k1(z[1]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h1DAC), .ORDER(1), .MODE(MODE) )
CE1 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[1]), .y_k(y[1]), .z_k(z[1]),
.x_k1(x[2]), .y_k1(y[2]), .z_k1(z[2]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0FAD), .ORDER(2), .MODE(MODE) )
CE2 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[2]), .y_k(y[2]), .z_k(z[2]),
.x_k1(x[3]), .y_k1(y[3]), .z_k1(z[3]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h07F5), .ORDER(3) , .MODE(MODE) )
CE3 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[3]), .y_k(y[3]), .z_k(z[3]),
.x_k1(x[4]), .y_k1(y[4]), .z_k1(z[4]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h03FE), .ORDER(4) , .MODE(MODE) )
CE4 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[4]), .y_k(y[4]), .z_k(z[4]),
.x_k1(x[5]), .y_k1(y[5]), .z_k1(z[5]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h01FF), .ORDER(5) , .MODE(MODE) )
CE5 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[5]), .y_k(y[5]), .z_k(z[5]),
.x_k1(x[6]), .y_k1(y[6]), .z_k1(z[6]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h00FF), .ORDER(6) , .MODE(MODE) )
CE6 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[6]), .y_k(y[6]), .z_k(z[6]),
.x_k1(x[7]), .y_k1(y[7]), .z_k1(z[7]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h007F), .ORDER(7) , .MODE(MODE) )
CE7 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[7]), .y_k(y[7]), .z_k(z[7]),
.x_k1(x[8]), .y_k1(y[8]), .z_k1(z[8]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h003F), .ORDER(8) , .MODE(MODE) )
CE8 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[8]), .y_k(y[8]), .z_k(z[8]),
.x_k1(x[9]), .y_k1(y[9]), .z_k1(z[9]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h001F), .ORDER(9) , .MODE(MODE) )
CE9 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[9]), .y_k(y[9]), .z_k(z[9]),
.x_k1(x[10]), .y_k1(y[10]), .z_k1(z[10]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h000F), .ORDER(10) , .MODE(MODE) )
CE10 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[10]), .y_k(y[10]), .z_k(z[10]),
.x_k1(x[11]), .y_k1(y[11]), .z_k1(z[11]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0007), .ORDER(11) , .MODE(MODE) )
CE11 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[11]), .y_k(y[11]), .z_k(z[11]),
.x_k1(x[12]), .y_k1(y[12]), .z_k1(z[12]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0003), .ORDER(12) , .MODE(MODE) )
CE12 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[12]), .y_k(y[12]), .z_k(z[12]),
.x_k1(x[13]), .y_k1(y[13]), .z_k1(z[13]) );
endmodule |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: PA.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PA (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long i, j, k, m, n, t, x; string s, u; int main() { for (scanf( %lld , &t); t--;) { i = 1; cin >> x >> s; for (; s.size() < x; i++) { if (s[i - 1] > 49) { u = s.substr(i); for (k = s[i - 1] - 48; --k;) s += u; } } m = s.size(); for (; i <= x; i++) m = (m + (s[i - 1] - 49) * (m - i + 1000000007)) % 1000000007; cout << m << endl; } } |
#include <bits/stdc++.h> int read() { int x = 0, y = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) y = -1; ch = getchar(); } while (ch <= 9 && ch >= 0 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return x * y; } void print(int x) { if (x < 0) { putchar( 0 ); return; } if (x < 10) { putchar(x + 0 ); return; } print(x / 10); putchar(x % 10 + 0 ); } int n, x, maxx; int main() { n = read(); for (int _ = 0; _ < n; _++) x = read(), maxx = maxx > x ? maxx : x; print(maxx - 25); return 0; } |
(* src = "../../verilog/extadc.v:1", top = 1 *)
module ExtADC (
(* intersynth_port = "Reset_n_i", src = "../../verilog/extadc.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/extadc.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/extadc.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/extadc.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:11" *)
output SensorPower_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:13" *)
output SensorStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "Inputs_i", src = "../../verilog/extadc.v:15" *)
input SensorReady_i,
(* intersynth_conntype = "Bit", intersynth_port = "AdcDoConvert_o", src = "../../verilog/extadc.v:17" *)
output AdcStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "AdcConvComplete_i", src = "../../verilog/extadc.v:19" *)
input AdcDone_i,
(* intersynth_conntype = "Word", intersynth_port = "AdcValue_i", src = "../../verilog/extadc.v:21" *)
input[15:0] AdcValue_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/extadc.v:23" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/extadc.v:25" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/extadc.v:27" *)
input[15:0] Threshold_i
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$extract$\AddSubCmp_Greater_Direct$728.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$extract$\Counter_RV1_Timer$725.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$extract$\Counter_RV1_Timer$725.Overflow_s ;
(* src = "../../verilog/extadc.v:167" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/extadc.v:43" *)
wire StoreNewValue;
(* src = "../../verilog/extadc.v:41" *)
wire TimerEnable;
(* src = "../../verilog/extadc.v:39" *)
wire TimerOvfl;
(* src = "../../verilog/extadc.v:40" *)
wire TimerPreset;
wire TRFSM0_1_Out7_s;
wire TRFSM0_1_Out8_s;
wire TRFSM0_1_Out9_s;
wire TRFSM0_1_CfgMode_s;
wire TRFSM0_1_CfgClk_s;
wire TRFSM0_1_CfgShift_s;
wire TRFSM0_1_CfgDataIn_s;
wire TRFSM0_1_CfgDataOut_s;
AbsDiff \$extract$\AbsDiff$726 (
.A_i(AdcValue_i),
.B_i(SensorValue_o),
.D_o(AbsDiffResult)
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$extract$\AddSubCmp_Greater_Direct$728.ThisAddSubCmp (
.A_i(AbsDiffResult),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Greater_Direct$728.Carry_s ),
.D_o(\$extract$\AddSubCmp_Greater_Direct$728.D_s ),
.Overflow_o(\$extract$\AddSubCmp_Greater_Direct$728.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Greater_Direct$728.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Greater_Direct$728.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$extract$\Counter_RV1_Timer$725.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$extract$\Counter_RV1_Timer$725.D_s ),
.Direction_i(1'b1),
.Enable_i(TimerEnable),
.Overflow_o(\$extract$\Counter_RV1_Timer$725.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(TimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(TimerOvfl)
);
WordRegister \$extract$\WordRegister$727 (
.Clk_i(Clk_i),
.D_i(AdcValue_i),
.Enable_i(StoreNewValue),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
TRFSM0 TRFSM0_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(AdcDone_i),
.In1_i(Enable_i),
.In2_i(SensorReady_i),
.In3_i(TimerOvfl),
.In4_i(\$extract$\AddSubCmp_Greater_Direct$728.Carry_s ),
.In5_i(\$extract$\AddSubCmp_Greater_Direct$728.Zero_s ),
.Out0_o(CpuIntr_o),
.Out1_o(SensorStart_o),
.Out2_o(StoreNewValue),
.Out3_o(AdcStart_o),
.Out4_o(SensorPower_o),
.Out5_o(TimerEnable),
.Out6_o(TimerPreset),
.Out7_o(TRFSM0_1_Out7_s),
.Out8_o(TRFSM0_1_Out8_s),
.Out9_o(TRFSM0_1_Out9_s),
.CfgMode_i(TRFSM0_1_CfgMode_s),
.CfgClk_i(TRFSM0_1_CfgClk_s),
.CfgShift_i(TRFSM0_1_CfgShift_s),
.CfgDataIn_i(TRFSM0_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM0_1_CfgDataOut_s)
);
assign TRFSM0_1_CfgMode_s = 1'b0;
assign TRFSM0_1_CfgClk_s = 1'b0;
assign TRFSM0_1_CfgShift_s = 1'b0;
assign TRFSM0_1_CfgDataIn_s = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; class Data { public: long long lazy, val; Data() { lazy = -1; val = 0; } }; long long pr = 107; long long c_pr[100010]; Data tree[4 * 100010]; long long ara[100010]; void updval(int node, int le_ran, int ri_ran, long long lazy) { long long poo = c_pr[ri_ran] - c_pr[le_ran - 1]; poo %= 1000000007; if (poo < 0) { poo = (poo + 1000000007) % 1000000007; } tree[node].val = poo * lazy; tree[node].val %= 1000000007; tree[node].lazy = lazy; } void update(int node, int le_ran, int ri_ran) { if (tree[node].lazy != -1) { if (le_ran != ri_ran) { int mid = (le_ran + ri_ran) / 2; updval(node * 2, le_ran, mid, tree[node].lazy); updval((node * 2) + 1, mid + 1, ri_ran, tree[node].lazy); } tree[node].lazy = -1; } } void update_range(int node, int le_ran, int ri_ran, int le, int ri, long long val) { if ((ri_ran < le) || (le_ran > ri)) { return; } if ((le_ran >= le) && (ri_ran <= ri)) { updval(node, le_ran, ri_ran, val); return; } update(node, le_ran, ri_ran); int mid = (le_ran + ri_ran) / 2; update_range(node * 2, le_ran, mid, le, ri, val); update_range((node * 2) + 1, mid + 1, ri_ran, le, ri, val); tree[node].val = tree[node * 2].val + tree[(node * 2) + 1].val; tree[node].val %= 1000000007; } long long query(int node, int le_ran, int ri_ran, int le, int ri) { if ((ri_ran < le) || (le_ran > ri)) { return 0; } if ((le_ran >= le) && (ri_ran <= ri)) { return tree[node].val; } update(node, le_ran, ri_ran); int mid = (le_ran + ri_ran) / 2; long long ans = 0; ans += query(node * 2, le_ran, mid, le, ri); ans %= 1000000007; ans += query((node * 2) + 1, mid + 1, ri_ran, le, ri); ans %= 1000000007; return ans; } string str; int n, q; long long bm(long long base, long long power) { if (power == 0) { return 1; } if (power % 2 == 0) { long long ret = bm(base, power / 2); return (ret * ret) % 1000000007; } else { return (base * bm(base, power - 1)) % 1000000007; } } long long mod_inv(long long num) { return bm(num, 1000000007 - 2); } long long get_hash(int l, int r) { long long yo = query(1, 1, n, l, r); yo %= 1000000007; if (yo < 0) { yo = (yo + 1000000007) % 1000000007; } yo = yo * mod_inv(bm(pr, l)); yo %= 1000000007; return yo; } int main() { std::ios_base::sync_with_stdio(false); int m, k; cin >> n >> m >> k; q = m + k; long long tmp_pr = 1; for (int i = 1; i <= n; i++) { c_pr[i] = c_pr[i - 1] + tmp_pr; c_pr[i] %= 1000000007; tmp_pr = tmp_pr * pr; tmp_pr %= 1000000007; } cin >> str; for (int i = 0; i <= n - 1; i++) { update_range(1, 1, n, i + 1, i + 1, str[i] - 0 ); } for (int i = 1; i <= q; i++) { int cmd; cin >> cmd; int l, r, val; cin >> l >> r >> val; if (cmd == 1) { update_range(1, 1, n, l, r, val); } else { if (get_hash(l, r - val) == get_hash(l + val, r)) { cout << YES n ; } else { cout << NO n ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 110000, MAXM = MAXN * 2; const int inf = 10000000; struct eglist { int other[MAXM], succ[MAXM], last[MAXM], sum; void addEdge(int a, int b) { other[++sum] = b, succ[sum] = last[a], last[a] = sum; other[++sum] = a, succ[sum] = last[b], last[b] = sum; } void clear(int n) { for (int i = 0; i <= n; i++) last[i] = 0; sum = 0; } } e; int fa[MAXN]; pair<int, int> down1[MAXN], down2[MAXN]; int up[MAXN], ans = 0; queue<int> q; int visit[MAXN] = {}; int n, m, d; void dfsDown(int x, int fa) { if (visit[x]) { down1[x] = make_pair(0, 0); down2[x] = make_pair(0, 0); } else { down1[x].first = -inf, down2[x].first = -inf; } for (int i = e.last[x]; i; i = e.succ[i]) { int y = e.other[i]; if (y == fa) continue; dfsDown(y, x); pair<int, int> tmp = down1[y]; tmp.first++; tmp.second = y; if (tmp > down1[x]) { down2[x] = down1[x]; down1[x] = tmp; } else if (tmp > down2[x]) down2[x] = tmp; } } void dfsUp(int x, int fa) { up[x] = visit[x] ? 0 : -inf; if (fa == 0) { if (down1[x].first <= d) ans++; } else { up[x] = max(up[x], up[fa] + 1); if (down1[fa].second == x) up[x] = max(up[x], down2[fa].first + 1); else up[x] = max(up[x], down1[fa].first + 1); if (max(up[x], down1[x].first) <= d) ans++; } for (int i = e.last[x]; i; i = e.succ[i]) { int y = e.other[i]; if (y == fa) continue; dfsUp(y, x); } } int main() { scanf( %d %d %d , &n, &m, &d); for (int i = 1; i <= m; i++) { int p; scanf( %d , &p); visit[p] = 1; } e.clear(n); for (int i = 1; i < n; i++) { int a, b; scanf( %d %d , &a, &b); e.addEdge(a, b); } dfsDown(1, 0); dfsUp(1, 0); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, x, y, sum, mbit; int Ask(vector<int> vec) { int ret = 0; printf( ? %d , vec.size()); for (int i = 0; i < vec.size(); i++) printf( %d , vec[i]); puts( ); fflush(stdout); scanf( %d , &ret); return ret; } int Solve(vector<int> a) { vector<int> tmp; int l = 0, r = a.size() - 1, ans = 0; sort(a.begin(), a.end()); while (l <= r) { int mid = (l + r) >> 1; for (int i = 0; i <= mid; i++) tmp.push_back(a[i]); int ret = Ask(tmp); tmp.clear(); if (ret == y || ret == (y ^ x)) ans = mid, r = mid - 1; else l = mid + 1; } return a[ans]; } int main() { vector<int> vec; scanf( %d%d%d , &n, &x, &y); for (int i = 0; i <= 9; i++) { for (int j = 1; j <= n; j++) if (j >> i & 1) vec.push_back(j); if (!vec.size()) break; int ret = Ask(vec); vec.clear(); if (ret == y || ret == (y ^ x)) sum |= (1 << i), mbit = i; } vector<int> ta, tb; for (int i = 1; i <= n; i++) if (i >> mbit & 1) ta.push_back(i); else tb.push_back(i); if (ta.size() > tb.size()) swap(ta, tb); int pos1 = Solve(ta), pos2 = (sum ^ pos1); if (pos1 > pos2) swap(pos1, pos2); printf( ! %d %d n , pos1, pos2); fflush(stdout); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRBP_1_V
`define SKY130_FD_SC_MS__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRBP_1_V
|
module mult_wrap (
input ck,
input [63:0] i_a, i_b,
input [8:0] i_htId,
input i_vld,
output [63:0] o_res,
output [8:0] o_htId,
output o_vld
);
// Wires & Registers
wire [63:0] c_t19_res;
wire [8:0] c_t1_htId;
wire c_t1_vld;
reg [8:0] r_t2_htId, r_t3_htId, r_t4_htId, r_t5_htId, r_t6_htId, r_t7_htId, r_t8_htId, r_t9_htId, r_t10_htId, r_t11_htId, r_t12_htId, r_t13_htId, r_t14_htId, r_t15_htId, r_t16_htId, r_t17_htId, r_t18_htId, r_t19_htId;
reg r_t2_vld, r_t3_vld, r_t4_vld, r_t5_vld, r_t6_vld, r_t7_vld, r_t8_vld, r_t9_vld, r_t10_vld, r_t11_vld, r_t12_vld, r_t13_vld, r_t14_vld, r_t15_vld, r_t16_vld, r_t17_vld, r_t18_vld, r_t19_vld;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
r_t2_htId <= c_t1_htId;
r_t2_vld <= c_t1_vld;
r_t3_htId <= r_t2_htId;
r_t3_vld <= r_t2_vld;
r_t4_htId <= r_t3_htId;
r_t4_vld <= r_t3_vld;
r_t5_htId <= r_t4_htId;
r_t5_vld <= r_t4_vld;
r_t6_htId <= r_t5_htId;
r_t6_vld <= r_t5_vld;
r_t7_htId <= r_t6_htId;
r_t7_vld <= r_t6_vld;
r_t8_htId <= r_t7_htId;
r_t8_vld <= r_t7_vld;
r_t9_htId <= r_t8_htId;
r_t9_vld <= r_t8_vld;
r_t10_htId <= r_t9_htId;
r_t10_vld <= r_t9_vld;
r_t11_htId <= r_t10_htId;
r_t11_vld <= r_t10_vld;
r_t12_htId <= r_t11_htId;
r_t12_vld <= r_t11_vld;
r_t13_htId <= r_t12_htId;
r_t13_vld <= r_t12_vld;
r_t14_htId <= r_t13_htId;
r_t14_vld <= r_t13_vld;
r_t15_htId <= r_t14_htId;
r_t15_vld <= r_t14_vld;
r_t16_htId <= r_t15_htId;
r_t16_vld <= r_t15_vld;
r_t17_htId <= r_t16_htId;
r_t17_vld <= r_t16_vld;
r_t18_htId <= r_t17_htId;
r_t18_vld <= r_t17_vld;
r_t19_htId <= r_t18_htId;
r_t19_vld <= r_t18_vld;
end
// Black box instantiation
mul_64b_int multiplier (.clk(ck), .a(i_a), .b(i_b), .p(c_t19_res));
// Inputs
assign c_t1_htId = i_htId;
assign c_t1_vld = i_vld;
// Outputs
assign o_res = c_t19_res;
assign o_htId = r_t19_htId;
assign o_vld = r_t19_vld;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_SYMBOL_V
`define SKY130_FD_SC_HD__A41OI_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_SYMBOL_V
|
/**
# SmallLpf2nd - 2-pole IIR Low-Pass Filter #
Small 2-Pole IIR low-pass filter, made using just adders and bit shifts. Set
the frequency using the K0_SHIFT and K1_SHIFT parameters. It can be slowed down by
strobing the `en` bit to run at a lower rate.
By using power of two feedback terms, this filter is alsways stable and is
immune to limit cycling.
Clamping is necessary if the full input range will be used. Clamping is
unnecessary if the input word will never go beyond '+/- (2^(WIDTH-2)-1)'. Keep
in mind that clamping will cause nonlinear distortion in high-amplitude signals.
## Design Equations ##
Let w0 be the desired cutoff frequency in radians/second, let f_clk be the
filter run rate (defined by clk and en), and let Q be the desired quality
factor.
```
w0^2
H(s) = -----------------------
s^2 + (w0/Q)*s + w0^2
w0 = 2*pi*f0
K0_SHIFT = -log2(w0/Q / f_clk)
K1_SHIFT = -log2(w0*Q / f_clk)
w0/Q = 2^-K0_SHIFT * f_clk
w0*Q = 2^-K1_SHIFT * f_clk
w0 = sqrt(2^-K0_SHIFT * 2^-K1_SHIFT * f_clk^2)
Q = sqrt(2^-K1_SHIFT / 2^-K0_SHIFT)
```
Since the SHIFT parameters must be integers, the final filter will not perfectly
match the desired one. The true filter response will also be different from the
continuous-time approximation.
## Block Diagram ##
Key:
- ACCUM: accumulator
- SUB: subtract signal on bottom from the signal on the left
- 2^-X: Right arithmetic shift by X
```
dataIn --->(SUB)--->(SUB)--->[ACCUM]--->[2^-K0_SHIFT]--\
^ ^ |
| | |
| +--------------------------------+
| |
| \----->[ACCUM]--->[2^-K1_SHIFT]--+-> dataOut
| |
\-----------------------------------------/
```
*/
module SmallLpf2nd #(
parameter K0_SHIFT = 8, ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 8, ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16, ///< Width of data path
parameter CLAMP = 1 ///< Set to 1 to clamp the accumulators
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous & active high
input en, ///< Filter strobe
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter input
);
reg signed [WIDTH+K0_SHIFT-1:0] acc0;
reg signed [WIDTH+K1_SHIFT-1:0] acc1;
reg signed [WIDTH+1:0] forwardIn;
wire signed [WIDTH-1:0] acc0Out;
wire signed [WIDTH+K0_SHIFT:0] acc0In;
wire signed [WIDTH+K1_SHIFT:0] acc1In;
assign acc0In = acc0 + forwardIn;
assign acc1In = acc1 + acc0Out;
always @(posedge clk) begin
if (rst) begin
forwardIn <= 'd0;
acc0 <= 'd0;
acc1 <= 'd0;
end
else if (en) begin
forwardIn <= dataIn - acc0Out - dataOut;
if (CLAMP) begin
acc0 <= (^acc0In[WIDTH+K0_SHIFT-:2])
? {acc0In[WIDTH+K0_SHIFT], {(WIDTH+K0_SHIFT-1){acc0In[WIDTH+K0_SHIFT-1]}}}
: acc0In;
acc1 <= (^acc1In[WIDTH+K1_SHIFT-:2])
? {acc1In[WIDTH+K1_SHIFT], {(WIDTH+K1_SHIFT-1){acc1In[WIDTH+K1_SHIFT-1]}}}
: acc1In;
end
else begin
acc0 <= acc0In;
acc1 <= acc1In;
end
end
end
assign acc0Out = acc0 >>> K0_SHIFT;
assign dataOut = acc1 >>> K1_SHIFT;
// Test Code: Check to see if clamping ever occurs
/*
reg clamp0;
reg clamp1;
always @(posedge clk) begin
if (rst) begin
clamp0 <= 1'b0;
clamp1 <= 1'b0;
end
else begin
clamp0 <= clamp0 | (^acc0In[WIDTH+K0_SHIFT-:2]);
clamp1 <= clamp1 | (^acc1In[WIDTH+K1_SHIFT-:2]);
end
end
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ull = unsigned long long; const double PI = acos(-1.0); const int EPS = (1e-10); const int N = 1e5 * 2 + 10; const int inf = 1e9 * 2 + 10; const ll INF = 1e18 * 2 + 10; const int MOD = 1e9 + 7; int nxt() { int x; cin >> x; return x; } int fcmp(double a, double b) { return (fabs(a - b) < EPS ? 0 : a > b ? 1 : -1); } bool prime[N]; vector<int> adj[N]; int sz[N], link[N]; void sieve() { fill(&prime[0], &prime[0] + N, 1); prime[0] = 0; prime[1] = 1; for (int i = 2; i * i <= N; ++i) if (prime[i]) { for (int j = i * i; j < N; j += i) prime[j] = 0; } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); sieve(); string s; cin >> s; map<char, int> mp; for (int i = (0); i <= ((int)(s).size() - 1); ++i) mp[s[i]]++; s = 0 + s; char k = 0; for (int i = (0); i <= (256); ++i) if (mp[k] < mp[i]) k = i; prime[1] = 1; for (int i = 2; i + i <= (int)(s).size() - 1; ++i) prime[i] = 0; for (int i = (1); i <= ((int)(s).size() - 1); ++i) if (!prime[i]) { if (mp[k] == 0) { cout << NO n ; return 0; } mp[s[i] = k]--; } for (int i = (1); i <= ((int)(s).size() - 1); ++i) if (prime[i]) { bool ok = false; for (int j = (0); j <= (256); ++j) if (mp[j] > 0) { mp[s[i] = j]--; ok = true; break; } if (ok) continue; else { cout << NO n ; return 0; } } s.erase(0, 1); cout << YES n << s; return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, int> lc, rc, pr; set<int> nodes; set<int>::iterator it; vector<int> v; int main() { int n; cin >> n; int root; cin >> root; nodes.insert(root); for (int i = 1; i < n; ++i) { int x; cin >> x; v.push_back(x); it = nodes.upper_bound(x); if (it == nodes.end()) { it--; rc[*it] = x; pr[x] = (*it); } else if (it == nodes.begin()) { lc[*it] = x; pr[x] = (*it); } else { int ul = (*it); it--; int ll = (*it); if (lc[ul]) rc[ll] = x, pr[x] = ll; else lc[ul] = x, pr[x] = ul; } nodes.insert(x); } for (int i = 0; i < v.size(); ++i) { cout << pr[v[i]] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 1e5 + 5; int n, k; vector<pair<int, int> > g[M]; int ans; int dp[M][2]; void dfs(int u, int Pa) { vector<pair<int, int> > ch; for (auto p : g[u]) { int v = p.first, w = p.second; if (v == Pa) continue; dfs(v, u); ch.push_back(make_pair(dp[v][0] + w, dp[v][1] + w)); } bool flag = ch.size() > 0; if (flag) { sort(ch.begin(), ch.end(), [&](pair<int, int> a, pair<int, int> b) { return a.second > b.second; }); } for (int i = 0; i < k - 1 && i < ch.size(); i++) { dp[u][1] += ch[i].second; } if (ch.size() <= k) { for (auto p : ch) { dp[u][0] += p.second; } if (flag) { sort(ch.begin(), ch.end(), [&](pair<int, int> a, pair<int, int> b) { return a.first - a.second > b.first - b.second; }); dp[u][0] += ch[0].first - ch[0].second; } } else { int max_val = -1e9; for (int i = k; i < ch.size(); i++) { max_val = max(max_val, ch[i].first); } int sum = 0; for (int i = 0; i < k; i++) { sum += ch[i].second; } for (int i = 0; i < k; i++) { dp[u][0] = max(dp[u][0], sum - ch[i].second + max(max_val, ch[i].first)); } } } int main() { scanf( %d%d , &n, &k); for (int i = 1; i < n; i++) { int u, v, c; scanf( %d%d%d , &u, &v, &c); u++, v++; g[u].push_back(make_pair(v, c)); g[v].push_back(make_pair(u, c)); } dfs(1, 0); printf( %d n , dp[1][0]); } |
#include <bits/stdc++.h> struct state { int n : 24; int c : 8; state const *prev; }; state b[128][128][128] = {}; void print(state const &s) { if (s.n) { state const &p = *s.prev; print(p); if (p.n < s.n) printf( %c , s.c); } } int main() { char s1[128]; char s2[128]; char sv[128]; scanf( %s%s%s , s1, s2, sv); unsigned int n1 = strlen(s1); unsigned int n2 = strlen(s2); unsigned int nv = strlen(sv); unsigned int fail[128] = {}; for (unsigned int i = 1, j = 0; i < nv;) if (sv[i] == sv[j]) fail[i++] = 1 + j++; else if (0 < j) j = fail[j - 1]; else fail[i++] = 0; b[0][0][0].n = 0; for (unsigned int i = 1; i <= nv; ++i) b[0][0][i].n = -4200; for (unsigned int i = 1; i <= n1; ++i) { for (unsigned int j = 1; j <= n2; ++j) { for (unsigned int k = 0; k < nv; ++k) { b[i][j][k] = b[i - 1][j][k]; if (b[i][j][k].n < b[i][j - 1][k].n) b[i][j][k] = b[i][j - 1][k]; } if (s1[i - 1] == s2[j - 1]) { for (unsigned int k = 0; k < nv; ++k) { unsigned int v = k; while (1) { if (s1[i - 1] == sv[v]) { ++v; break; } if (0 < v) v = fail[v - 1]; else break; } if (b[i][j][v].n < b[i - 1][j - 1][k].n + 1) { b[i][j][v].n = b[i - 1][j - 1][k].n + 1; b[i][j][v].c = s1[i - 1]; b[i][j][v].prev = &b[i - 1][j - 1][k]; } } } } } unsigned int v = 0; for (unsigned int i = 1; i < nv; ++i) if (b[n1][n2][v].n < b[n1][n2][i].n) v = i; if (0 < b[n1][n2][v].n) { print(b[n1][n2][v]); printf( n ); } else printf( 0 n ); } |
#include <bits/stdc++.h> using namespace std; int n, k, x, y, l, r, fact[200001], inv[200001], mod = 1e9 + 7; map<int, int> m; int powlog(int a, int b) { if (b == 0) return 1; int ret = powlog(a, b / 2); if (b % 2) return 1LL * ret * ret % mod * a % mod; return 1LL * ret * ret % mod; } int C(int n, int r) { return 1LL * fact[n] * inv[r] % mod * inv[n - r] % mod; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); fact[0] = inv[0] = 1; for (int i = 1; i <= 200000; i++) { fact[i] = 1LL * i * fact[i - 1] % mod; inv[i] = powlog(fact[i], mod - 2); } cin >> n >> k; for (int i = 0; i < n && cin >> x >> y; i++) m[x]++, m[y + 1]--; long long ans = 0; int prev = 0, lines = 0; for (auto &i : m) { if (lines >= k) ans = (ans + 1LL * (i.first - prev) * C(lines, k) % mod) % mod; lines += i.second; prev = i.first; } cout << ans << endl; return 0; } |
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