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#include <bits/stdc++.h> using namespace std; int marked[1000006]; int f(int i, int j) { if (j == 1) { return marked[i]; } return f(marked[i], j - 1); } vector<int> v; int main() { int n, a, b; scanf( %d %d %d , &n, &a, &b); int cut = -1; for (int i = 0; i <= n; i++) { if (i % a == 0 && (n - i) % b == 0) { cut = i; break; } } if (cut == -1) { printf( -1 n ); return 0; } int cnt = 0; for (int i = 1; i <= cut; i++) { cnt++; v.push_back(i); if (cnt == a) { if ((int)v.size() >= 2) { rotate(v.begin(), v.begin() + 1, v.end()); } for (int j = 0; j < v.size(); j++) { printf( %d , v[j]); } cnt = 0; v.clear(); } } cnt = 0; for (int i = cut + 1; i <= n; i++) { cnt++; v.push_back(i); if (cnt == b) { if ((int)v.size() >= 2) { rotate(v.begin(), v.begin() + 1, v.end()); } for (int j = 0; j < v.size(); j++) { printf( %d , v[j]); } cnt = 0; v.clear(); } } } |
#include <bits/stdc++.h> using namespace std; int n, m, t; set<pair<int, int> > s; string s1; vector<int> v, v1; int kek[100000]; int main() { cin >> n >> m >> t; for (int i = 1; i <= n; i++) { cin >> s1; int cur = 0; cur += 60 * 60 * 10 * (s1[0] - 0 ); cur += 60 * 60 * (s1[1] - 0 ); cur += 60 * 10 * (s1[3] - 0 ); cur += 60 * (s1[4] - 0 ); cur += 10 * (s1[6] - 0 ); cur += (s1[7] - 0 ); v.push_back(cur); } s.clear(); int cur = 0; int ans = 0; int mx = 0; for (int i = 0; i < v.size(); i++) { while (!s.empty()) { set<pair<int, int> >::iterator it = (--s.end()); if (-(*it).first < v[i]) s.erase(it); else break; cur--; } if (cur < m) { ans++; kek[i] = ans; cur++; s.insert(make_pair(-(v[i] + t - 1), ans)); } else { kek[i] = (*s.begin()).second; s.erase(s.begin()); s.insert(make_pair(-(v[i] + t - 1), kek[i])); } mx = max(mx, cur); } if (mx != m) { cout << No solution ; return 0; } cout << ans << n ; for (int i = 0; i < v.size(); i++) cout << kek[i] << n ; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
//////////////////////////////////////////////////////////////////
// Megawizard Generated FIFO
//////////////////////////////////////////////////////////////////
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: altpcierd_tx_ecrc_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Internal Build 134 08/15/2007 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcierd_tx_ecrc_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [31:0] q;
wire sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2;
wire empty = sub_wire0;
wire [31:0] q = sub_wire1[31:0];
wire full = sub_wire2;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.empty (sub_wire0),
.q (sub_wire1),
.full (sub_wire2)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.sclr (),
.usedw ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / D Flip-Flop with Clock Enable and Synchronous Reset
// /___/ /\ Filename : FDRE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 12/08/11 - add MSGON and XON attributes (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDRE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_R_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input D,
input R
);
reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED;
reg [0:0] IS_R_INVERTED_REG = IS_R_INVERTED;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
wire D_dly, C_dly, CE_dly;
wire R_dly;
`endif
// begin behavioral model
reg Q_out;
assign #100 Q = Q_out;
always @(glblGSR)
if (glblGSR)
assign Q_out = INIT;
else
deassign Q_out;
`ifdef XIL_TIMING
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C_dly)
if (((R_dly ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C_dly)
if (((R_dly ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end
endgenerate
`else
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C)
if (((R ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C)
if (((R ^ IS_R_INVERTED_REG) && (R !== 1'bz)) || (R === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end
endgenerate
`endif
`ifdef XIL_TIMING
reg notifier;
wire notifier1;
`endif
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nrst;
wire in_clk_enable, in_clk_enable_p, in_clk_enable_n;
wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n;
reg init_enable = 1'b1;
wire rst_clk_enable, rst_clk_enable_p, rst_clk_enable_n;
`endif
`ifdef XIL_TIMING
not (ngsr, glblGSR);
xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out);
not (nrst, (R_dly ^ IS_R_INVERTED_REG) && (R !== 1'bz));
and (in_clk_enable, ngsr, nrst, CE || (CE === 1'bz));
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG);
always @(negedge nrst) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1);
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1);
assign rst_clk_enable_n = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b1);
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0);
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0);
assign rst_clk_enable_p = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b0);
`endif
// end behavioral model
`ifdef XIL_TIMING
specify
(C => Q) = (100:100:100, 100:100:100);
$period (negedge C &&& CE, 0:0:0, notifier);
$period (posedge C &&& CE, 0:0:0, notifier);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (negedge C, negedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,C_dly,R_dly);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (negedge C, posedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,C_dly,R_dly);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$setuphold (posedge C, negedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,C_dly,R_dly);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$setuphold (posedge C, posedge R, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,C_dly,R_dly);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge R &&& init_enable, 0:0:0, 0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge R &&& init_enable, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int oo = 0x3f3f3f3f; const int Mod = 1e9 + 7; const int maxn = 500000; struct edge { int id, nxt; edge() {} edge(int _id, int _nxt) : id(_id), nxt(_nxt) {} }; edge e[(maxn << 1) + 5]; int st[maxn + 5], en = 0; inline void add_edge(int first, int second) { e[en] = edge(second, st[first]), st[first] = en++; } int n; set<pair<int, int> > all[maxn + 5]; int id[maxn + 5]; int sz[maxn + 5]; int dep[maxn + 5]; int ans = 0; void dfs(int first, int f = -1) { id[first] = first; for (int i = st[first]; i != -1; i = e[i].nxt) { int second = e[i].id; if (second == f) continue; dep[second] = dep[first] + 1; dfs(second, first); if (f == -1) { chkmax(ans, (--all[id[second]].end())->first - 1); continue; } if (sz[first] < sz[second]) swap(id[first], id[second]); sz[first] += sz[second]; for (auto u : all[id[second]]) { for (int v = (u.second), _end_ = (u.first); v < _end_; ++v) { auto t = all[id[first]].lower_bound(make_pair(v, oo)); if (t == all[id[first]].end() || t->second > v) all[id[first]].insert(make_pair(v + 1, v)); else { auto t0 = t; int from = t->second, to = t->first; while (1) { auto pre = t0++; if (t0 == all[id[first]].end()) break; if (pre->first < t0->second) break; to = t0->first; } all[id[first]].erase(t, t0); all[id[first]].insert(make_pair(to + 1, from)); } } } } if (!(int((all[id[first]]).size()))) all[id[first]].insert(make_pair(dep[first] + 1, dep[first])), sz[first] = 1; } int main() { memset(st, -1, sizeof st), en = 0; scanf( %d , &n); for (int i = (0), _end_ = (n - 1); i < _end_; ++i) { int first, second; scanf( %d%d , &first, &second), --first, --second; add_edge(first, second), add_edge(second, first); } dfs(0); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct subject { long long a, b; int c, r, s; bool operator<(subject const &T) const { return c < T.c; } }; int n, m, rex, rey, fx[55][55][105], fy[55][55][105]; long long rat, val, tmp, old, dp[55][55][105], ret; subject a[55]; void trace(int x, int y, int z) { if (y) trace(fx[x][y][z], y - 1, fy[x][y][z]); printf( %d %I64d n , a[x].r, a[x].a + z); } int main() { scanf( %d%d%I64d , &n, &m, &rat); for (int i = 0; i < m; i++) { scanf( %I64d%I64d%d , &a[i].a, &a[i].b, &a[i].c); a[i].r = i + 1; a[i].s = a[i].b - a[i].a; } sort(a, a + m); memset(dp, -1, sizeof(dp)); for (int i = 0; i < m; i++) { for (int j = 0; j <= a[i].s; j++) { dp[i][0][j] = val = a[i].a + j; for (int k = 1; k <= i; k++) { for (int l = 0; l < i; l++) { if (a[l].c == a[i].c) continue; if (val % rat == 0) { tmp = val / rat - a[l].a; if (0 <= tmp && tmp <= a[l].s) { old = dp[l][k - 1][tmp]; if (old != -1 && dp[i][k][j] < old + val) { dp[i][k][j] = old + val; fx[i][k][j] = l; fy[i][k][j] = tmp; } } } if (val > rat) { tmp = val - rat - a[l].a; if (0 <= tmp && tmp <= a[l].s) { old = dp[l][k - 1][tmp]; if (old != -1 && dp[i][k][j] < old + val) { dp[i][k][j] = old + val; fx[i][k][j] = l; fy[i][k][j] = tmp; } } } } } if (dp[i][n - 1][j] > ret) ret = dp[i][n - 1][j], rex = i, rey = j; } } if (ret) { printf( YES n , ret); trace(rex, n - 1, rey); } else printf( NO n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int II() { int n; scanf( %d , &n); return n; } int table[100][100]; char message[100][200]; string names[100]; void recprint(int m, int s) { if (m < 0) return; recprint(m - 1, table[m][s]); cout << names[s]; printf( :%s n , message[m]); } int main() { int T = II(); while (T--) { set<std::string> usernames; int N = II(); for (int x = 0; x < N; x++) { string s; cin >> s; usernames.insert(s); } for (auto it = usernames.begin(); it != usernames.end(); it++) names[distance(usernames.begin(), it)] = *it; int M = II(); int sa = N, sb = N; for (int m = 0; m < M; m++) { for (int x = 0; x < N; x++) table[m][x] = N; string user; user.clear(); char c = getchar(); while (c < 32) c = getchar(); while (c != : ) { user += c; c = getchar(); } int it = distance(usernames.begin(), usernames.find(user)); if (it < N) for (int x = 0; x < N; x++) if (x != it) table[m][x] = -1; user.clear(); char *msg = message[m]; c = getchar(); while (true) { bool ended = false; if (c == ! || c == ? || c == . || c == , || c == || c == 10) { int it = distance(usernames.begin(), usernames.find(user)); if (it < N) table[m][it] = -1; ended = true; } if (c == 10) break; *msg = c; msg++; user += c; if (ended) user.clear(); c = getchar(); } *msg = 0; for (int x = 0; x < N; x++) if (table[m][x] != -1) table[m][x] = (x == sa ? sb : sa); sa = sb = -1; for (int x = 0; x < N; x++) if (table[m][x] != -1) sa = x; for (int x = 0; x < N; x++) if (table[m][x] != -1) if (x != sa) sb = x; } if (sa == -1) printf( Impossible n ); else recprint(M - 1, sa); } } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e5 + 10; struct Seg { long long mn, id; }; long long arr[maxn], N, P, ans[maxn]; Seg seg[maxn << 2]; inline Seg pushup(long long cur) { Seg l = seg[cur << 1], r = seg[cur << 1 | 1]; if (l.mn == r.mn) { return l; } else if (l.mn < r.mn) { Seg mer; mer.id = l.id, mer.mn = l.mn; return mer; } else { Seg mer; mer.id = r.id, mer.mn = r.mn; return mer; } } long long query(long long cur, long long L, long long R, long long l, long long r) { if (L > R) return -1; if (l >= L && r <= R) { return seg[cur].id; } long long mid = (l + r) >> 1; long long lid = -1, rid = -1; if (mid >= L) lid = query(cur << 1, L, R, l, mid); if (mid < R) rid = query(cur << 1 | 1, L, R, mid + 1, r); if (lid == -1) return rid; else if (rid == -1) return lid; else { return arr[lid] > arr[rid] ? rid : lid; } } long long query2(long long cur, long long l, long long r, const long long x) { if (l == r) { return l; } long long mid = (l + r) >> 1; if (seg[cur << 1].mn <= x) { return query2(cur << 1, l, mid, x); } return query2(cur << 1 | 1, mid + 1, r, x); } void build(long long l, long long r, long long cur) { seg[cur].id = l, seg[cur].mn = arr[l]; if (l == r) return; long long mid = (l + r) >> 1; build(l, mid, cur << 1); build(mid + 1, r, cur << 1 | 1); seg[cur] = pushup(cur); } void update(long long pos, long long l, long long r, long long cur, long long x) { if (l == r) { seg[cur].mn = x; arr[pos] = x; return; } long long mid = (l + r) >> 1; if (mid >= pos) { update(pos, l, mid, cur << 1, x); } else { update(pos, mid + 1, r, cur << 1 | 1, x); } seg[cur] = pushup(cur); } signed main() { ios::sync_with_stdio(false); cin >> N >> P; for (register long long i = 1; i <= N; ++i) { cin >> arr[i]; } build(1, N, 1); long long cnt = 0, cur = 0; while (cnt < N) { cur = max(cur, seg[1].mn); long long x = query2(1, 1, N, cur); ans[x] = cur += P; ++cnt; update(x, 1, N, 1, 0x3f3f3f3f3f3f3f3f); while (cnt < N) { x = query(1, 1, x - 1, 1, N); if (x == -1 || arr[x] > cur) break; ans[x] = cur += P, ++cnt; update(x, 1, N, 1, 0x3f3f3f3f3f3f3f3f); } } for (register long long i = 1; i <= N; ++i) { cout << ans[i] << ; } return 0; } |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: gsu_cache.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_cache (
address,
clock,
data,
wren,
q);
input [8:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int n, m; int cnta[10], cntb[10]; int a[15][2], b[15][2]; int one_common(int x, int y) { if (a[x][0] == b[y][0] && a[x][1] != b[y][1]) return a[x][0]; if (a[x][1] == b[y][0] && a[x][0] != b[y][1]) return a[x][1]; if (a[x][0] == b[y][1] && a[x][1] != b[y][0]) return a[x][0]; if (a[x][1] == b[y][1] && a[x][0] != b[y][0]) return a[x][1]; return 0; } int main() { scanf( %d%d , &n, &m); int x, y; for (int i = 0; i < n; i++) { scanf( %d%d , &x, &y); cnta[x]++; cnta[y]++; a[i][0] = x; a[i][1] = y; } for (int i = 0; i < m; i++) { scanf( %d%d , &x, &y); cntb[x]++; cntb[y]++; b[i][0] = x; b[i][1] = y; } set<int> num; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (one_common(i, j)) num.insert(one_common(i, j)); } } if (num.size() == 1) { printf( %d n , *num.begin()); return 0; } for (int i = 0; i < n; i++) { set<int> num; for (int j = 0; j < m; j++) if (one_common(i, j)) num.insert(one_common(i, j)); if (num.size() > 1) { printf( -1 n ); return 0; } } for (int i = 0; i < m; i++) { set<int> num; for (int j = 0; j < n; j++) if (one_common(j, i)) num.insert(one_common(j, i)); if (num.size() > 1) { printf( -1 n ); return 0; } } printf( 0 n ); return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 1753 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w8,
w7,
w56,
w55,
w1760,
w1753;
assign w1 = i_data0;
assign w1753 = w1760 - w7;
assign w1760 = w55 << 5;
assign w55 = w56 - w1;
assign w56 = w7 << 3;
assign w7 = w8 - w1;
assign w8 = w1 << 3;
assign o_data0 = w1753;
//multiplier_block area estimate = 5388.76785242206;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[2005], b[2005]; vector<pair<long long, pair<int, int> > > bb; long long diff = 0L; bool good(long long x, int place) { if (place >= bb.size()) return false; else return diff + 2 * (bb[place].first - x) <= 0; } int find_(long long x) { int place = -1, jump = bb.size(); while (jump > 0) { if (good(x, place + jump)) place += jump; jump /= 2; } while (good(x, place + 1)) place++; return place; } bool sorter(pair<long long, pair<int, int> > a, pair<long long, pair<int, int> > b) { return a.first < b.first; } int main() { int n; scanf( %i , &n); for (int e = 0; e < n; e++) scanf( %I64d , &a[e]); int m; scanf( %i , &m); for (int e = 0; e < m; e++) scanf( %I64d , &b[e]); for (int e = 0; e < n; e++) diff += a[e]; for (int e = 0; e < m; e++) diff -= b[e]; long long acc = diff; vector<pair<int, int> > rr; for (int e = 0; e < n; e++) { for (int ee = 0; ee < m; ee++) { if (abs(diff + 2 * (b[ee] - a[e])) < abs(acc)) { acc = diff + 2 * (b[ee] - a[e]); rr.clear(); rr.push_back(make_pair(e, ee)); } } } for (int e = 0; e < m; e++) { for (int ee = e + 1; ee < m; ee++) { bb.push_back(make_pair(b[e] + b[ee], make_pair(e, ee))); } } sort(bb.begin(), bb.end(), sorter); for (int e = 0; e < n; e++) { for (int ee = e + 1; ee < n; ee++) { long long itm = a[e] + a[ee]; int pl = find_(itm); if (pl < (int)bb.size() - 1) { if (abs(diff + 2 * (bb[pl + 1].first - itm)) < abs(acc)) { acc = diff + 2 * (bb[pl + 1].first - itm); rr.clear(); rr.push_back(make_pair(e, bb[pl + 1].second.first)); rr.push_back(make_pair(ee, bb[pl + 1].second.second)); } } if (pl > -1) { if (abs(diff + 2 * (bb[pl].first - itm)) < abs(acc)) { acc = diff + 2 * (bb[pl].first - itm); rr.clear(); rr.push_back(make_pair(e, bb[pl].second.first)); rr.push_back(make_pair(ee, bb[pl].second.second)); } } } } printf( %I64d n%i n , abs(acc), rr.size()); for (auto e : rr) printf( %i %i n , e.first + 1, e.second + 1); return 0; } |
#include <bits/stdc++.h> int main() { int n, v, pre, rotting, a[4005], b[4005], i, j, bag, collect, day, v2; while (scanf( %d%d , &n, &v) != EOF) { day = 0; bag = 0; for (i = 0; i < n; i++) { scanf( %d%d , &a[i], &b[i]); if (a[i] > day) day = a[i]; } rotting = 0; day += 2; for (i = 1; i < day; i++) { pre = 0; for (j = 0; j < n; j++) { if (a[j] == i) { pre += b[j]; } } if (rotting > v) { bag += v; v2 = 0; } else { bag += rotting; v2 = v - rotting; } if (pre > v2) { bag += v2; pre -= v2; } else { bag += pre; pre = 0; } rotting = pre; } printf( %d n , bag); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_SYMBOL_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29452 $
// $Date: 2012-08-27 22:01:48 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A synchronization module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous,
// while deassertion is synchronized to the clock.
module SyncResetA (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
reg [RSTDELAY:0] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK or `BSV_RESET_EDGE IN_RST )
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY {RSTDELAY+1 {`BSV_RESET_VALUE}} ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
end
end // always @ ( posedge CLK or `BSV_RESET_EDGE IN_RST )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // SyncResetA
|
module vfabric_multiport_lsu_streaming_read(clock, resetn, base_address, size,
i_datain_valid, o_datain_stall,
avm_readdata, avm_readdatavalid, avm_waitrequest,
avm_address, avm_read, avm_write,
avm_writeack, avm_writedata, avm_byteenable,
avm_burstcount,
o_dataouta, o_dataouta_valid, i_dataouta_stall,
o_dataoutb, o_dataoutb_valid, i_dataoutb_stall,
o_dataoutc, o_dataoutc_valid, i_dataoutc_stall,
o_dataoutd, o_dataoutd_valid, i_dataoutd_stall);
parameter LSU_AWIDTH = 32;
parameter WIDTH_BYTES = 16;
parameter DATAOUT_WIDTH = 32;
input clock, resetn;
input [LSU_AWIDTH-1:0] base_address;
input [DATAOUT_WIDTH-1:0] size;
input i_datain_valid;
output o_datain_stall;
input [255:0] avm_readdata;
input avm_readdatavalid;
input avm_waitrequest;
output [31:0] avm_address;
output avm_read;
output avm_write;
input avm_writeack;
output [255:0] avm_writedata;
output [31:0] avm_byteenable;
output [5:0] avm_burstcount;
output [DATAOUT_WIDTH-1:0] o_dataouta;
output [DATAOUT_WIDTH-1:0] o_dataoutb;
output [DATAOUT_WIDTH-1:0] o_dataoutc;
output [DATAOUT_WIDTH-1:0] o_dataoutd;
input i_dataouta_stall, i_dataoutb_stall, i_dataoutc_stall, i_dataoutd_stall;
output o_dataouta_valid, o_dataoutb_valid, o_dataoutc_valid, o_dataoutd_valid;
wire [8*WIDTH_BYTES-1:0] lsu_dataout;
wire lsu_dataout_valid;
wire lsu_dataout_stall;
wire [8*WIDTH_BYTES-1:0] mega_dataout;
lsu_streaming_read lsu0 (.clk(clock), .resetn(resetn),
.i_nop( 1'b0 ), .base_address(base_address), .size(size),
.i_valid(i_datain_valid), .o_stall(o_datain_stall),
.o_readdata(lsu_dataout), .o_valid(lsu_dataout_valid),
.i_stall(lsu_dataout_stall),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_readdatavalid(avm_readdatavalid),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest),
.avm_address(avm_address),
.avm_burstcount(avm_burstcount) );
defparam lsu0.AWIDTH = LSU_AWIDTH;
defparam lsu0.WIDTH_BYTES=WIDTH_BYTES;
fanout_splitter mega_splitter(.clock(clock), .resetn(resetn), .i_datain(lsu_dataout), .i_datain_valid(lsu_dataout_valid),
.o_datain_stall(lsu_dataout_stall), .o_dataout(mega_dataout),
.i_dataout_stall({i_dataoutd_stall, i_dataoutc_stall, i_dataoutb_stall, i_dataouta_stall}),
.o_dataout_valid({o_dataoutd_valid, o_dataoutc_valid, o_dataoutb_valid, o_dataouta_valid}));
defparam mega_splitter.DATA_WIDTH = DATAOUT_WIDTH*WIDTH_BYTES/4;
defparam mega_splitter.NUM_FANOUTS = WIDTH_BYTES/4;
assign o_dataouta[DATAOUT_WIDTH-1:0] = mega_dataout[DATAOUT_WIDTH-1:0];
assign o_dataoutb[DATAOUT_WIDTH-1:0] = mega_dataout[2*DATAOUT_WIDTH-1:DATAOUT_WIDTH];
assign o_dataoutc[DATAOUT_WIDTH-1:0] = mega_dataout[3*DATAOUT_WIDTH-1:2*DATAOUT_WIDTH];
assign o_dataoutd[DATAOUT_WIDTH-1:0] = mega_dataout[4*DATAOUT_WIDTH-1:3*DATAOUT_WIDTH];
endmodule
module vfabric_multiport_lsu_streaming_write(clock, resetn, base_address, size,
i_dataa, i_dataa_valid, o_dataa_stall, i_datab, i_datab_valid, o_datab_stall,
i_datac, i_datac_valid, o_datac_stall, i_datad, i_datad_valid, o_datad_stall,
avm_readdata, avm_readdatavalid, avm_waitrequest,
avm_address, avm_read, avm_write,
avm_writeack, avm_writedata, avm_byteenable,
avm_burstcount, o_dataout_valid, i_dataout_stall);
parameter LSU_AWIDTH = 32;
parameter WIDTH_BYTES = 16;
parameter DATA_WIDTH = 32;
parameter LSU_DATA_WIDTH = 128;
input clock, resetn;
input [LSU_AWIDTH-1:0] base_address;
input [DATA_WIDTH-1:0] size;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input [DATA_WIDTH-1:0] i_datac;
input [DATA_WIDTH-1:0] i_datad;
input i_dataa_valid, i_datab_valid, i_datac_valid, i_datad_valid;
output o_dataa_stall, o_datab_stall, o_datac_stall, o_datad_stall;
input [255:0] avm_readdata;
input avm_readdatavalid;
input avm_waitrequest;
output [31:0] avm_address;
output avm_read;
output avm_write;
input avm_writeack;
output [255:0] avm_writedata;
output [31:0] avm_byteenable;
output [5:0] avm_burstcount;
input i_dataout_stall;
output o_dataout_valid;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire [DATA_WIDTH-1:0] datac;
wire [DATA_WIDTH-1:0] datad;
wire fifo_a_valid_out;
wire fifo_b_valid_out;
wire fifo_c_valid_out;
wire fifo_d_valid_out;
wire are_fifos_valid;
wire are_fifos_stalled;
wire is_lsu_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn), .data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( fifo_a_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = 16;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn), .data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( fifo_b_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = 16;
vfabric_buffered_fifo fifo_c ( .clock(clock), .resetn(resetn), .data_in(i_datac), .data_out(datac), .valid_in(i_datac_valid),
.valid_out( fifo_c_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_datac_stall) );
defparam fifo_c.DATA_WIDTH = DATA_WIDTH;
defparam fifo_c.DEPTH = 16;
vfabric_buffered_fifo fifo_d ( .clock(clock), .resetn(resetn), .data_in(i_datad), .data_out(datad), .valid_in(i_datad_valid),
.valid_out( fifo_d_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_datad_stall) );
defparam fifo_d.DATA_WIDTH = DATA_WIDTH;
defparam fifo_d.DEPTH = 16;
assign are_fifos_valid = fifo_a_valid_out & fifo_b_valid_out & fifo_c_valid_out & fifo_d_valid_out;
assign are_fifos_stalled = ~(fifo_a_valid_out & fifo_b_valid_out & fifo_c_valid_out & fifo_d_valid_out & ~is_lsu_stalled);
lsu_streaming_write lsu0 (.clk(clock), .resetn(resetn),
.i_nop( 1'b0 ), .base_address(base_address), .size(size),
.i_writedata({datad, datac, datab, dataa}),
.i_valid(are_fifos_valid), .o_stall(is_lsu_stalled),
.o_valid(o_dataout_valid),
.i_stall(i_dataout_stall),
.avm_write(avm_write),
.avm_writeack(avm_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest),
.avm_address(avm_address),
.avm_burstcount(avm_burstcount));
defparam lsu0.AWIDTH = LSU_AWIDTH;
defparam lsu0.WIDTH_BYTES=WIDTH_BYTES;
endmodule
|
module adc08d1020_serial(
output wire sclk, // typical 15MHz, limit 19MHz
output reg sdata,
output reg scs,
input wire [15:0] w_data,
input wire [3:0] w_addr,
input wire commit,
output wire busy,
input wire clk12p5
);
reg [15:0] l_data;
reg [3:0] l_addr;
reg l_commit;
reg l_busy;
reg [5:0] cycle;
reg [31:0] shifter;
reg commit_d;
reg commit_pulse; // get the rising edge only of commit
assign busy = l_busy;
// register i2c bus signals into local clock domain to ease timing
always @(posedge clk12p5) begin
l_data <= w_data;
l_addr <= w_addr;
l_commit <= commit;
// busy whenever the cycle counter isn't at 0
l_busy <= (cycle[5:0] != 6'b0);
end
// turn commit into a locally timed pulse
always @(posedge clk12p5) begin
commit_d <= l_commit;
commit_pulse <= !commit_d && l_commit;
end
// forward the clock net
ODDR2 sclk_oddr2 (
.D0(1'b1),
.D1(1'b0),
.C0(clk12p5),
.C1(!clk12p5),
.CE(1'b1),
.R(1'b0),
.S(1'b0),
.Q(sclk) );
// main shifter logic
always @(posedge clk12p5) begin
if( commit_pulse && (cycle[5:0] == 6'b0) ) begin
shifter[31:0] <= {12'b0000_0000_0001,l_addr[3:0],l_data[15:0]};
cycle[5:0] <= 6'b10_0000;
end else if( cycle[5:0] != 6'b0 ) begin
cycle[5:0] <= cycle[5:0] - 6'b1;
shifter[31:0] <= {shifter[30:0], 1'b0};
end else begin
cycle[5:0] <= 6'b0;
shifter[31:0] <= 32'b0;
end
end
// output stage logic
always @(posedge clk12p5) begin
sdata <= shifter[31];
scs <= !(cycle[5:0] != 6'b0);
end
endmodule // adc08d1020_serial
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } const int N = 1e3 + 10; const double eps = 1e-5; int n; struct Tarr { long long tarr[N][N]; Tarr() { for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { tarr[i][j] = 0; } } } static int lowbit(int x) { return x & -x; } void add(int x, int y, long long val) { while (x <= n) { int p = y; while (p <= n) { tarr[x][p] ^= val; p += lowbit(p); } x += lowbit(x); } } long long query(int x, int y) { long long res = 0; while (x) { int p = y; while (p) { res ^= tarr[x][p]; p -= lowbit(p); } x -= lowbit(x); } return res; } }; Tarr an, ai, aj, aij; long long query(int x, int y) { return (((x + 1) * (y + 1) % 2) * an.query(x, y)) ^ (((x + 1) % 2) * ai.query(x, y)) ^ (((y + 1) % 2) * aj.query(x, y)) ^ aij.query(x, y); } long long query(int x1, int y1, int x2, int y2) { return query(x2, y2) ^ query(x1 - 1, y2) ^ query(x2, y1 - 1) ^ query(x1 - 1, y1 - 1); } void add(int x, int y, long long val) { an.add(x, y, val); ai.add(x, y, (y % 2) * val); aj.add(x, y, (x % 2) * val); aij.add(x, y, (x * y % 2) * val); } void add(int x1, int y1, int x2, int y2, long long val) { add(x1, y1, val); add(x1, y2 + 1, val); add(x2 + 1, y1, val); add(x2 + 1, y2 + 1, val); } int main() { std::ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int m; cin >> n >> m; for (int i = 1; i <= m; i++) { int op; cin >> op; if (op == 2) { int x1, y1, x2, y2; long long v; cin >> x1 >> y1 >> x2 >> y2 >> v; add(x1, y1, x2, y2, v); } else { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; cout << query(x1, y1, x2, y2) << n ; } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; ; scanf( %d , &n); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if ((j + i) % 2 == 0) printf( W ); else printf( B ); } printf( n ); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////
// File name : SATA_TOP.v
// Note : This is the top module of SATA2 Host Controller
// Test/Verification Environment
// Dependencies : Nil
//////////////////////////////////////////////////////////////////////////////
module SATA_TOP#(
parameter integer CHIPSCOPE = 0
)
(
input TILE0_REFCLK_PAD_P_IN, // Input differential clock pin P 150MHZ
input TILE0_REFCLK_PAD_N_IN, // Input differential clock pin N 150MHZ
input GTPRESET_IN, // Reset input for GTP initialization
output TILE0_PLLLKDET_OUT, // GTP PLL Lock detected output
output TXP0_OUT, // SATA Connector TX P pin
output TXN0_OUT, // SATA Connector TX N pin
input RXP0_IN, // SATA Connector RX P pin
input RXN0_IN, // SATA Connector RX N pin
output DCMLOCKED_OUT, // PHY Layer DCM locked
output LINKUP, // SATA PHY initialisation completed LINK UP
output GEN2, // 1 when a SATA2 device detected, 0 when SATA1 device detected
output PHY_CLK_OUT, // PHY layer clock out
output CLK_OUT, // LINK and Transport Layer clock out CLK_OUT = PHY_CLK_OUT / 2
input HOST_READ_EN, // Read enable from host / user logic for Shadow register and PIO data
input HOST_WRITE_EN, // Write enable from host / user logic for Shadow register and PIO data
input [4:0] HOST_ADDR_REG, // Address bus for Shadow register
input [31:0] HOST_DATA_IN, // Data in bus for Shadow register and PIO data
output [31:0] HOST_DATA_OUT, // Data out bus for Shadow register and PIO data
output RESET_OUT, // Reset out for User logic this is from GTP reset out
output WRITE_HOLD_U, // Write HOLD signal for PIO and DMA write
output READ_HOLD_U, // Read HOLD signal for PIO and DMA read
input PIO_CLK_IN, // Clock in for PIO read / write
input DMA_CLK_IN, // Clock in for DMA read / write
input DMA_RQST, // DMA request. This should be 1 for DMA operation and 0 for PIO operation
output [31:0] DMA_RX_DATA_OUT, // DMA read data out bus
input DMA_RX_REN, // DMA read enable
input [31:0] DMA_TX_DATA_IN, // DMA write data in bus
input DMA_TX_WEN, // DMA write enable
input CE, // Chip enable
output IPF, // Interrupt pending flag
output DMA_TERMINATED, // This signal becomes 1 when a DMA terminate primitive get from Device (SSD)
output R_ERR, // set 1 when R_ERR Primitive received from disk
output ILLEGAL_STATE, // set 1 when illegal_state transition detected
input RX_FIFO_RESET, // reset signal for Receive data fifo
input TX_FIFO_RESET // reset signal for Transmit data fifo
);
wire [15:0] phy_rx_data_out;
wire [1:0] phy_rx_charisk_out;
wire [15:0] link_tx_data_out;
wire link_tx_charisk_out;
wire linkup_int;
wire phy_clk;
wire logic_reset;
wire [1:0] align_count;
wire clk;
//wire for link layer
wire [31:0] trnsp_tx_data_out;
wire [31:0] link_rx_data_out;
wire pmreq_p_t;
wire pmreq_s_t;
wire pm_en;
wire lreset;
wire data_rdy_t;
wire phy_detect_t;
wire illegal_state_t;
wire escapecf_t;
wire frame_end_t;
wire decerr;
wire tx_termn_t_o;
wire rx_fifo_rdy;
wire rx_fail_t;
wire crc_err_t;
wire valid_crc_t;
wire fis_err;
wire good_status_t;
wire unrecgnzd_fis_t;
//wire tx_termn_t_i;
wire r_ok_t;
wire r_err_t;
wire sof_t;
wire eof_t;
wire tx_rdy_ack_t;
wire data_out_vld_t;
wire r_ok_sent_t;
//for transport layer
wire dma_init;
wire dma_end;
wire stop_dma;
wire rx_fifo_empty;
wire hold_L;
wire cmd_done;
wire dma_tx_fifo_full;
wire dma_rx_fifo_empty;
wire data_in_rd_en_t;
wire x_rdy_sent_t;
wire tx_rdy_t;
assign PHY_CLK_OUT = phy_clk;
assign CLK_OUT = clk;
assign RESET_OUT = logic_reset;
assign R_ERR = r_err_t;
assign ILLEGAL_STATE = illegal_state_t;
sata_phy #(
.CHIPSCOPE (CHIPSCOPE)
)
PHY(
.TILE0_REFCLK_PAD_P_IN (TILE0_REFCLK_PAD_P_IN),
.TILE0_REFCLK_PAD_N_IN (TILE0_REFCLK_PAD_N_IN),
.GTPRESET_IN (GTPRESET_IN),
.TILE0_PLLLKDET_OUT (TILE0_PLLLKDET_OUT),
.TXP0_OUT (TXP0_OUT),
.TXN0_OUT (TXN0_OUT),
.RXP0_IN (RXP0_IN),
.RXN0_IN (RXN0_IN),
.DCMLOCKED_OUT (DCMLOCKED_OUT),
.LINKUP (linkup_int),
.logic_clk (phy_clk),
.GEN2 (GEN2),
.tx_data_in (link_tx_data_out),
.tx_charisk_in (link_tx_charisk_out),
.rx_data_out (phy_rx_data_out),
.rx_charisk_out (phy_rx_charisk_out),
.logic_reset (logic_reset),
.align_count (align_count),
.div2_logic_clock (clk)
);
assign LINKUP = linkup_int;
sata_link #(
.CHIPSCOPE (CHIPSCOPE)
)
LINK(
.CLK (clk),
.RESET (logic_reset),
.LINKUP (linkup_int),
.PHY_CLK (phy_clk),
.TX_DATA_OUT (link_tx_data_out),
.TX_CHARISK_OUT (link_tx_charisk_out),
.RX_DATA_IN (phy_rx_data_out),
.RX_CHARISK_IN (phy_rx_charisk_out),
.ALIGN_COUNT (align_count),
.TX_DATA_IN_DW (trnsp_tx_data_out),
.RX_DATA_OUT_DW (link_rx_data_out),
.PMREQ_P_T (1'b0), //pmreq_p_t),
.PMREQ_S_T (1'b0), //pmreq_s_t),
.PM_EN (1'b0),
.LRESET (1'b0), //lreset),
.DATA_RDY_T (data_rdy_t),
.PHY_DETECT_T (phy_detect_t),
.ILLEGAL_STATE_T (illegal_state_t),
.ESCAPECF_T (escapecf_t),
.FRAME_END_T (frame_end_t),
.DECERR (0),
.TX_TERMN_T_O (tx_termn_t_o),
.RX_FIFO_RDY (rx_fifo_rdy),
.RX_FAIL_T (rx_fail_t),
.CRC_ERR_T (crc_err_t),
.VALID_CRC_T (valid_crc_t),
.FIS_ERR (fis_err),
.GOOD_STATUS_T (good_status_t),
.UNRECGNZD_FIS_T (unrecgnzd_fis_t),
.TX_TERMN_T_I (1'b0), //(tx_termn_t_i),
.R_OK_T (r_ok_t),
.R_ERR_T (r_err_t),
.SOF_T (sof_t),
.EOF_T (eof_t),
.TX_RDY_ACK_T (tx_rdy_ack_t),
.DATA_OUT_VLD_T (data_out_vld_t),
.TX_RDY_T (tx_rdy_t),
.R_OK_SENT_T (r_ok_sent_t),
.DATA_IN_RD_EN_T (data_in_rd_en_t),
.X_RDY_SENT_T (x_rdy_sent_t),
.DMA_TERMINATED (DMA_TERMINATED)
);
sata_transport TRANSPORT (
.clk (clk),
.reset (logic_reset),
.DMA_RQST (DMA_RQST),
.data_in (HOST_DATA_IN), //output interface
.addr_reg (HOST_ADDR_REG), //output interface
.data_link_in (link_rx_data_out),
.LINK_DMA_ABORT (tx_termn_t_o),
.link_fis_recved_frm_dev (sof_t),
.phy_detect (phy_detect_t),
.H_write (HOST_WRITE_EN), //output interface
.H_read (HOST_READ_EN), //output interface
.link_txr_rdy (tx_rdy_ack_t),
.r_ok (r_ok_t),
.r_error (r_err_t),
.illegal_state (illegal_state_t),
.end_status (eof_t),
.data_link_out (trnsp_tx_data_out),
.FRAME_END_T (frame_end_t),
.hold_L (hold_L),
.WRITE_HOLD_U (WRITE_HOLD_U),
.READ_HOLD_U (READ_HOLD_U),
.txr_rdy (tx_rdy_t),
.data_out (HOST_DATA_OUT),
.EscapeCF_T (escapecf_t),
.UNRECGNZD_FIS_T (unrecgnzd_fis_t),
.IPF (IPF),
.FIS_ERR (fis_err),
.Good_status_T (good_status_t),
.RX_FIFO_RDY (rx_fifo_rdy),
.cmd_done (cmd_done),
.DMA_TX_DATA_IN (DMA_TX_DATA_IN),
.DMA_TX_WEN (DMA_TX_WEN),
.DMA_RX_DATA_OUT (DMA_RX_DATA_OUT),
.DMA_RX_REN (DMA_RX_REN),
.VALID_CRC_T (valid_crc_t),
.data_out_vld_T (data_out_vld_t),
.CRC_ERR_T (crc_err_t),
.DMA_INIT (1'b 0),
.DMA_END (dma_end),
.DATA_RDY_T (data_rdy_t),
.data_link_rd_en_t (data_in_rd_en_t),
.PIO_CLK_IN (PIO_CLK_IN),
.DMA_CLK_IN (DMA_CLK_IN),
.CE (CE),
.RX_FIFO_RESET (RX_FIFO_RESET),
.TX_FIFO_RESET (TX_FIFO_RESET)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200100; vector<pair<int, int> > d[2]; vector<int> S[2]; int n, v; int main() { cin >> n >> v; int sum = 0; for (int i = 0; i < n; i++) { int t, s; cin >> t >> s; sum += s; d[t - 1].push_back(make_pair(s, i + 1)); } for (int i = 0; i < 2; i++) { sort(d[i].begin(), d[i].end()); reverse(d[i].begin(), d[i].end()); S[i].push_back(0); for (auto x : d[i]) { S[i].push_back(S[i].back() + x.first); } } int ans = 0; int I = 0; for (int i = 0; i * 2 <= v && i <= d[1].size(); i++) { int cur = S[1][i]; if (v - 2 * i >= d[0].size()) { cur += S[0].back(); } else { cur += S[0][v - 2 * i]; } if (cur > ans) { ans = cur; I = i; } } cout << ans << n ; for (int i = 0; i < I; i++) { cout << d[1][i].second << ; } for (int i = 0; i < v - 2 * I && i < d[0].size(); i++) { cout << d[0][i].second << ; } return 0; } |
// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is Gary
// It is the equivalent of Gary in a real Amiga
// Gary handles the address decoding and cpu/chip bus multiplexing
// Gary handles kickstart area and bootrom overlay
// Gary handles CIA e clock synchronization
//
// 20-12-2005 - started coding
// 21-12-2005 - done more coding
// 25-12-2005 - changed blitter nasty handling
// 15-01-2006 - fixed sensitivity list
// 12-11-2006 - debugging for new Minimig rev1.0 board
// 17-11-2006 - removed debugging and added decode for $C0000 ram
// ----------
// JB:
// 2008-10-06 - added decoders for IDE and GAYLE register range
// 2008-10-15 - signal name change cpuok -> dbr
// 2009-05-23 - better timing model for CIA interface
// 2009-05-24 - clean-up & renaming
// 2009-05-25 - ram, cpu and custom chips bus multiplexer
// 2009-09-01 - fixed sel_kick
// 2010-08-15 - clean-up
//
// SB:
// 2010-10-18 - added special memory config like in A500 Rev.6 with 512kb + 512kb of memory
//
// AMR:
// 2012-03-23 - Added select for Akiko
module gary
(
input [23:1] cpu_address_in, //cpu address bus input
input [20:1] dma_address_in, //agnus dma memory address input
output [18:1] ram_address_out, //ram address bus output
input [15:0] cpu_data_out,
output [15:0] cpu_data_in,
input [15:0] custom_data_out,
output [15:0] custom_data_in,
input [15:0] ram_data_out,
output [15:0] ram_data_in,
input a1k,
input cpu_rd, //cpu read
input cpu_hwr, //cpu high write
input cpu_lwr, //cpu low write
input cpu_hlt,
input ovl, //overlay kickstart rom over chipram
input dbr, //Agns takes the bus
input dbwe, //Agnus does a write cycle
output dbs, //data bus slow down
output xbs, //cross bridge select, active dbr prevents access
input [3:0] memory_config, //selected memory configuration
input ecs, // ECS chipset enable
input hdc_ena, //enables hdd interface
output ram_rd, //bus read
output ram_hwr, //bus high write
output ram_lwr, //bus low write
output sel_reg, //select chip register bank
output reg [3:0] sel_chip, //select chip memory
output reg [2:0] sel_slow, //select slowfast memory ($C0000)
output reg sel_kick, //select kickstart rom
output reg sel_kick1mb, // 1MB kickstart rom 'upper' half
output sel_cia, //select CIA space
output sel_cia_a, //select cia A
output sel_cia_b, //select cia B
output sel_rtc, //select $DCxxxx
output sel_ide, //select $DAxxxx
output sel_gayle //select $DExxxx
);
wire [2:0] t_sel_slow;
wire sel_xram;
wire sel_bank_1; // $200000-$3FFFFF
//--------------------------------------------------------------------------------------
assign ram_data_in = dbr ? custom_data_out : cpu_data_out;
assign custom_data_in = dbr ? ram_data_out : cpu_rd ? 16'hFFFF : cpu_data_out;
assign cpu_data_in = dbr ? 16'h00_00 : custom_data_out | ram_data_out | {16{sel_bank_1}};
//read write control signals
assign ram_rd = dbr ? ~dbwe : cpu_rd;
assign ram_hwr = dbr ? dbwe : cpu_hwr;
assign ram_lwr = dbr ? dbwe : cpu_lwr;
//--------------------------------------------------------------------------------------
// ram address multiplexer (512KB bank)
assign ram_address_out = dbr ? dma_address_in[18:1] : cpu_address_in[18:1];
//--------------------------------------------------------------------------------------
//chipram, kickstart and bootrom address decode
always @(*)
begin
if (dbr)//agnus only accesses chipram
begin
sel_chip[0] = ~dma_address_in[20] & ~dma_address_in[19];
sel_chip[1] = ~dma_address_in[20] & dma_address_in[19];
sel_chip[2] = dma_address_in[20] & ~dma_address_in[19];
sel_chip[3] = dma_address_in[20] & dma_address_in[19];
sel_slow[0] = ( ecs && memory_config==4'b0100 && dma_address_in[20:19]==2'b01) ? 1'b1 : 1'b0;
sel_slow[1] = 1'b0;
sel_slow[2] = 1'b0;
sel_kick = 1'b0;
sel_kick1mb = 1'b0;
end
else
begin
sel_chip[0] = cpu_address_in[23:19]==5'b0000_0 && !ovl ? 1'b1 : 1'b0;
sel_chip[1] = cpu_address_in[23:19]==5'b0000_1 ? 1'b1 : 1'b0;
sel_chip[2] = cpu_address_in[23:19]==5'b0001_0 ? 1'b1 : 1'b0;
sel_chip[3] = cpu_address_in[23:19]==5'b0001_1 ? 1'b1 : 1'b0;
sel_slow[0] = t_sel_slow[0];
sel_slow[1] = t_sel_slow[1];
sel_slow[2] = t_sel_slow[2];
sel_kick = (cpu_address_in[23:19]==5'b1111_1 && (cpu_rd || cpu_hlt)) || (cpu_rd && ovl && cpu_address_in[23:19]==5'b0000_0) ? 1'b1 : 1'b0; //$F80000 - $FFFFF
sel_kick1mb = (cpu_address_in[23:19]==5'b1110_0 && (cpu_rd || cpu_hlt)) ? 1'b1 : 1'b0; // $E00000 - $E7FFFF
end
end
assign t_sel_slow[0] = cpu_address_in[23:19]==5'b1100_0 ? 1'b1 : 1'b0; //$C00000 - $C7FFFF
assign t_sel_slow[1] = cpu_address_in[23:19]==5'b1100_1 ? 1'b1 : 1'b0; //$C80000 - $CFFFFF
assign t_sel_slow[2] = cpu_address_in[23:19]==5'b1101_0 ? 1'b1 : 1'b0; //$D00000 - $D7FFFF
// 512kb extra rom area at $e0 and $f0 write able only at a1k chipset mode
//assign t_sel_slow[2] = (cpu_address_in[23:19]==5'b1110_0 || cpu_address_in[23:19]==5'b1111_0) && (a1k | cpu_rd) ? 1'b1 : 1'b0; //$E00000 - $E7FFFF & $F00000 - $F7FFFF
assign sel_xram = ((t_sel_slow[0] & (memory_config[2] | memory_config[3]))
| (t_sel_slow[1] & memory_config[3])
| (t_sel_slow[2] & memory_config[2] & memory_config[3]));
assign sel_ide = hdc_ena && cpu_address_in[23:16]==8'b1101_1010 ? 1'b1 : 1'b0; //IDE registers at $DA0000 - $DAFFFF
assign sel_gayle = hdc_ena && cpu_address_in[23:12]==12'b1101_1110_0001 ? 1'b1 : 1'b0; //GAYLE registers at $DE1000 - $DE1FFF
assign sel_rtc = (cpu_address_in[23:16]==8'b1101_1100) ? 1'b1 : 1'b0; //RTC registers at $DC0000 - $DCFFFF
assign sel_reg = cpu_address_in[23:21]==3'b110 ? ~(sel_xram | sel_rtc | sel_ide | sel_gayle) : 1'b0; //chip registers at $DF0000 - $DFFFFF
assign sel_cia = cpu_address_in[23:20]==4'b1011 ? 1'b1 : 1'b0;
//cia a address decode
assign sel_cia_a = sel_cia & ~cpu_address_in[12];
//cia b address decode
assign sel_cia_b = sel_cia & ~cpu_address_in[13];
assign sel_bank_1 = cpu_address_in[23:21]==3'b001 ? 1'b1 : 1'b0;
//data bus slow down
assign dbs = cpu_address_in[23:21]==3'b000 || cpu_address_in[23:20]==4'b1100 || cpu_address_in[23:19]==5'b1101_0 || cpu_address_in[23:16]==8'b1101_1111 ? 1'b1 : 1'b0;
assign xbs = ~(sel_cia | sel_gayle | sel_ide);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long MAX = pow(2, 32) - 1; int n; cin >> n; stack<int> fors; long long val = 0; long long num = 1; int i = 0; while (i != n) { string str; cin >> str; if (str == add ) { val += num; } else if (str == for ) { int j; cin >> j; num *= j; fors.push(j); } else { num /= fors.top(); fors.pop(); } if (val > MAX) { cout << OVERFLOW!!! << endl; return 0; } if (num > MAX) { int end = 1; while (end != 0) { string s; cin >> s; if (s == add ) { cout << OVERFLOW!!! << endl; return 0; } else if (s == for ) { int k; cin >> k; end++; } else { end--; } i++; } num /= fors.top(); fors.pop(); } i++; } cout << val << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O41A_PP_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class A, class B> A cvt(B x) { stringstream ss; ss << x; A y; ss >> y; return y; } typedef struct { string name; int c; int p[3]; int size; int room; } item; typedef struct { string name; int c; int bonus; string home; } resident; int n, k; map<string, item> items; map<string, vector<string> > itres; map<string, resident> residents; int main() { cin >> n; for (int i = 0; i < n; i++) { string name, c; int a, d, r, s; cin >> name >> c >> a >> d >> r >> s; if (c == weapon ) items[name] = (item){name, 0, {a, d, r}, s, s}; if (c == armor ) items[name] = (item){name, 1, {a, d, r}, s, s}; if (c == orb ) items[name] = (item){name, 2, {a, d, r}, s, s}; } cin >> k; for (int i = 0; i < k; i++) { string name, c, home; int b; cin >> name >> c >> b >> home; if (c == gladiator ) residents[name] = (resident){name, 0, b, home}; if (c == sentry ) residents[name] = (resident){name, 1, b, home}; if (c == physician ) residents[name] = (resident){name, 2, b, home}; items[home].room--; itres[home].push_back(name); } int move = 0; for (typeof(items.begin()) it = items.begin(); it != items.end(); it++) if (it->second.room > 0) move = 1; if (!move) { vector<pair<int, pair<int, string> > > v; for (typeof(items.begin()) it = items.begin(); it != items.end(); it++) { string name = it->first; int cl = it->second.c; int val = it->second.p[cl]; for (typeof(itres[name].begin()) itr = itres[name].begin(); itr != itres[name].end(); itr++) { if (residents[*itr].c == cl) val += residents[*itr].bonus; } v.push_back(make_pair(cl, make_pair(-val, name))); } sort(v.begin(), v.end()); int i = 0; for (int t = 0; t < 3; t++) { while (v[i].first != t) i++; string name = v[i].second.second; cout << name << << itres[name].size(); for (typeof(itres[name].begin()) itr = itres[name].begin(); itr != itres[name].end(); itr++) cout << << *itr; cout << endl; } } else { vector<pair<int, string> > r[3]; for (typeof(residents.begin()) itr = residents.begin(); itr != residents.end(); itr++) { r[itr->second.c].push_back(make_pair(itr->second.bonus, itr->first)); } int sum[3][1005]; for (int t = 0; t < 3; t++) { sort(r[t].begin(), r[t].end()); reverse(r[t].begin(), r[t].end()); sum[t][0] = 0; for (int i = 1; i <= r[t].size(); i++) { sum[t][i] = sum[t][i - 1] + r[t][i - 1].first; } } pair<int, pair<int, int> > best = make_pair(-1, make_pair(-1, -1)); pair<string, vector<string> > out[3]; set<string> used; for (typeof(items.begin()) it0 = items.begin(); it0 != items.end(); it0++) if (it0->second.c == 0) for (typeof(items.begin()) it1 = items.begin(); it1 != items.end(); it1++) if (it1->second.c == 1) for (typeof(items.begin()) it2 = items.begin(); it2 != items.end(); it2++) if (it2->second.c == 2) { int sz0 = min(it0->second.size, (int)r[0].size()); int sz1 = min(it1->second.size, (int)r[1].size()); int sz2 = min(it2->second.size, (int)r[2].size()); pair<int, pair<int, int> > rez = make_pair(it0->second.p[0] + sum[0][sz0], make_pair(it1->second.p[1] + sum[1][sz1], it2->second.p[2] + sum[2][sz2])); if (rez > best) { best = rez; used.clear(); vector<string> x0, x1, x2; for (int i = 0; i < sz0; i++) { x0.push_back(r[0][i].second); used.insert(r[0][i].second); } for (int i = 0; i < sz1; i++) { x1.push_back(r[1][i].second); used.insert(r[1][i].second); } for (int i = 0; i < sz2; i++) { x2.push_back(r[2][i].second); used.insert(r[2][i].second); } out[0] = make_pair(it0->first, x0); out[1] = make_pair(it1->first, x1); out[2] = make_pair(it2->first, x2); } } for (int t = 0; t < 3; t++) { for (typeof(residents.begin()) itr = residents.begin(); itr != residents.end(); itr++) { if (out[t].second.size() == items[out[t].first].size) break; if (used.count(itr->first) == 0) { out[t].second.push_back(itr->first); used.insert(itr->first); } } cout << out[t].first << << out[t].second.size(); for (int i = 0; i < out[t].second.size(); i++) cout << << out[t].second[i]; cout << endl; } } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_dma_read_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
localparam TRANSFER_ADDR = 32'h80000000;
localparam TRANSFER_LEN = 24'h203;
reg req_valid = 1'b1;
wire req_ready;
reg [23:0] req_length = 'h03;
wire awvalid;
wire awready;
wire [31:0] araddr;
wire [7:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
wire [2:0] arprot;
wire [3:0] arcache;
wire rlast;
wire rvalid;
wire rready;
wire [1:0] rresp;
wire [31:0] rdata;
always @(posedge clk) begin
if (reset != 1'b1 && req_ready == 1'b1) begin
req_valid <= 1'b1;
req_length <= req_length + 4;
end
end
axi_read_slave #(
.DATA_WIDTH(32)
) i_write_slave (
.clk(clk),
.reset(reset),
.arvalid(arvalid),
.arready(arready),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arprot(arprot),
.arcache(arcache),
.rready(rready),
.rvalid(rvalid),
.rdata(rdata),
.rresp(rresp),
.rlast(rlast)
);
wire fifo_rd_en = 1'b1;
wire fifo_rd_valid;
wire fifo_rd_underflow;
wire [31:0] fifo_rd_dout;
reg [31:0] fifo_rd_dout_cmp = TRANSFER_ADDR;
reg fifo_rd_dout_mismatch = 1'b0;
reg [31:0] fifo_rd_dout_limit = 'h0;
axi_dmac_transfer #(
.DMA_TYPE_SRC(0),
.DMA_TYPE_DEST(2),
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32),
.FIFO_SIZE(8)
) transfer (
.m_src_axi_aclk(clk),
.m_src_axi_aresetn(resetn),
.m_axi_arvalid(arvalid),
.m_axi_arready(arready),
.m_axi_araddr(araddr),
.m_axi_arlen(arlen),
.m_axi_arsize(arsize),
.m_axi_arburst(arburst),
.m_axi_arprot(arprot),
.m_axi_arcache(arcache),
.m_axi_rready(rready),
.m_axi_rvalid(rvalid),
.m_axi_rdata(rdata),
.m_axi_rlast(rlast),
.m_axi_rresp(rresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(1'b1),
.ctrl_pause(1'b0),
.req_eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_dest_address(TRANSFER_ADDR[31:2]),
.req_src_address(TRANSFER_ADDR[31:2]),
.req_x_length(req_length),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.fifo_rd_clk(clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_dout(fifo_rd_dout)
);
always @(posedge clk) begin
if (reset == 1'b1) begin
fifo_rd_dout_cmp <= TRANSFER_ADDR;
fifo_rd_dout_mismatch <= 1'b0;
end else begin
fifo_rd_dout_mismatch <= 1'b0;
if (fifo_rd_valid == 1'b1) begin
if (fifo_rd_dout_cmp < TRANSFER_ADDR + fifo_rd_dout_limit) begin
fifo_rd_dout_cmp <= (fifo_rd_dout_cmp + 'h4);
end else begin
fifo_rd_dout_cmp <= TRANSFER_ADDR;
fifo_rd_dout_limit <= fifo_rd_dout_limit + 'h4;
end
if (fifo_rd_dout_cmp != fifo_rd_dout) begin
fifo_rd_dout_mismatch <= 1'b1;
end
end
end
end
always @(posedge clk) begin
failed <= failed | fifo_rd_dout_mismatch;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; bool valid(int x, int y) { return x >= 0 && y >= 0 && x < 3 && y < 3 ? 1 : 0; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; int arr[n]; for (int i = 0; i < n; ++i) { cin >> arr[i]; } sort(arr, arr + n); int mx = arr[n - 1], mex = 0; for (int i = 0; i < n; ++i) { if (mex == arr[i]) { ++mex; } else { break; } } if (k) { if (mex > mx) { n += k; } else { int x = mex + mx; int y = x / 2; y += (x % 2); if (!binary_search(arr, arr + n, y)) { ++n; } } } cout << n << n ; } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_bb.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No user `defines in this module
module ent_bb
//
// Generated Module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long MAX = 1e6 + 10; long long a[100005]; int main() { long long n, k, m, sum, t, len; string s, d; while (cin >> n) { int flag = 1; sum = 0; if (n % 2 == 0) { cout << n / 2 << endl; for (long long i = (1); i <= (n / 2); ++i) cout << 2 << ; cout << endl; } else { cout << (n - 3) / 2 + 1 << endl; for (long long i = (1); i <= ((n - 3) / 2); ++i) cout << 2 << ; cout << 3 << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; long long powmod(long long a, long long l, long long md) { long long res = 1; while (l) { if (l & 1) res = res * a % md; l /= 2; a = a * a % md; } return res; } long long binpow(long long a, long long l) { long long res = 1; while (l) { if (l & 1) res = res * a; l /= 2; a = a * a; } return res; } long long __set(long long b, long long i) { return b | (1 << i); } long long __unset(long long b, long long i) { return b & (~(1UL << i)); } long long __check(long long b, long long i) { return b & (1 << i); } long long mulmod(long long a, long long b, long long md) { return ((a % md) * (b % md)) % md; } long long addmod(long long a, long long b, long long md) { return (a + b) % md; } long long submod(long long a, long long b, long long md) { return (((a - b) % md) + md) % md; } long long divmod(long long a, long long b, long long md) { return mulmod(a, powmod(b, md - 2, md), md); } const long long inf = 0xFFFFFFFFFFFFFFFL; priority_queue<long long, vector<long long>, greater<long long> > pq; clock_t time_p = clock(); void time() { time_p = clock() - time_p; cerr << Time Taken : << (float)(time_p) / CLOCKS_PER_SEC << n ; } long long d[3][10]; signed main(void) { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; for (long long i = 0; i < 3; i++) { string s; cin >> s; if (s[1] == m ) { d[0][s[0] - 0 ]++; } else if (s[1] == p ) { d[1][s[0] - 0 ]++; } else { d[2][s[0] - 0 ]++; } } long long mx = 3; for (long long i = 0; i < 3; i++) { for (long long j = 1; j <= 9; j++) mx = min(mx, 3 - min(3ll, d[i][j])); for (long long j = 1; j <= 7; j++) { long long tp = 0; if (!d[i][j]) tp++; if (!d[i][j + 1]) tp++; if (!d[i][j + 2]) tp++; mx = min(mx, tp); } } cout << mx << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long modI(long long a, long long m); long long gcd(long long a, long long b); long long powM(long long x, long long y, long long m); long long swap(long long a, long long b); void swap(long long& a, long long& b) { long long tp = a; a = b; b = tp; } long long gcd(long long x, long long y) { if (x == 0) return y; return gcd(y % x, x); } long long powM(long long x, long long y, long long m) { long long ans = 1, r = 1; x %= m; while (r > 0 && r <= y) { if (r & y) { ans *= x; ans %= m; } r <<= 1; x *= x; x %= m; } return ans; } long long modI(long long a, long long m) { long long m0 = m, y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m; long long t = m; m = a % m; a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); long long tt = 1; while (tt--) { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long ans = 0; for (long long mx = 1; mx < 31; mx++) { long long dp = 0; long long tmp = 0; for (long long i = 0; i < n; i++) { if (a[i] <= mx) { dp = max((long long)0, dp + a[i]); } tmp = max(dp, tmp); } ans = max(ans, tmp - mx); } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3fll; const long long M = 1e9 + 7; const long long maxn = 1e5 + 7; const double eps = 0.00000001; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } int cnt[6]; int a[6], b[6]; int i, j, k; int sum; int num(int m, int n) { if (m * 2 > n) return 1; if (m * 4 > n) return 2; if (m * 8 > n) return 3; if (m * 16 > n) return 4; if (m * 32 > n) return 5; return 6; } int n, m; bool judge(int x) { int sum = 0, i; for (i = 1; i <= 5; i++) { if (a[i] == 0 || a[i] > b[i]) sum += num(cnt[i], n + x) * (a[i] - b[i]); else sum += num(cnt[i] + x, n + x) * (a[i] - b[i]); } return sum > 0; } int main() { scanf( %d , &n); for (i = 1; i <= 5; i++) { scanf( %d , &k); if (k != -1) cnt[i]++, a[i] = 250 - k; else a[i] = 0; } for (i = 1; i <= 5; i++) { scanf( %d , &k); if (k != -1) cnt[i]++, b[i] = 250 - k; else b[i] = 0; } for (j = 0; j < n - 2; j++) for (i = 1; i <= 5; i++) { scanf( %d , &k); if (k != -1) cnt[i]++; } for (i = 0; i <= 10000; i++) if (judge(i)) { printf( %d , i); return 0; } puts( -1 ); } |
#include <bits/stdc++.h> using namespace std; bool maxl(long long a, long long b) { return a > b; } bool minl(long long a, long long b) { return a < b; } bool cmp(int a, int b) { return a > b; } inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } int main() { int a[105], ji = 0, ou = 0, i, j, n, ans = 0; n = read(); for (i = 0; i < n; i++) { a[i] = read(); if (a[i] % 2 == 0) { ou++; } else { ji++; } ans += a[i]; } sort(a, a + n); if (ans % 2 == 1) { cout << ans << endl; } else { if (ji >= 1) { for (i = 0; i < n; i++) if (a[i] % 2 == 1) { ans -= a[i]; break; } cout << ans << endl; } else { cout << 0 << endl; } } } |
#include <bits/stdc++.h> using namespace std; void print(pair<int, int> v) { if (v.first < 10) { cout << 0 << v.first << : ; } else { cout << v.first << : ; } if (v.second < 10) { cout << 0 << v.second; } else { cout << v.second; } } int main() { int n; cin >> n; vector<pair<int, int> > v; for (int i = 0; i < n; i++) { int h, m; char d; cin >> h >> d >> m; v.push_back({h, m}); } sort(v.begin(), v.end()); v.push_back({v[0].first + 24, v[0].second}); int mans = -1; for (int i = 0; i < v.size() - 1; i++) { int m = 0; m = (v[i + 1].first - v[i].first) * 60 + (v[i + 1].second - v[i].second) - 1; mans = max(mans, m); } print({mans / 60, mans % 60}); } |
/*
*
* Copyright (c) 2011
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
#include <bits/stdc++.h> using namespace std; class ReverseBit { public: ReverseBit(int size) : bit_(size + 1, 0) {} void Add(int pos, int num); int GetMax(int pos) const; private: static int Lsb(int num) { return num & -num; } vector<int> bit_; }; void ReverseBit::Add(int pos, int num) { pos = bit_.size() - pos; while (pos < (int)bit_.size()) { bit_[pos] = max(bit_[pos], num); pos += Lsb(pos); } } int ReverseBit::GetMax(int pos) const { pos = bit_.size() - pos; int res = 0; while (pos > 0) { res = max(res, bit_[pos]); pos -= Lsb(pos); } return res; } struct Receipt { int sum; int time; }; int main() { int n; cin >> n; vector<Receipt> last_receipts(n); for (auto &r : last_receipts) { cin >> r.sum; r.time = 0; } int updates; cin >> updates; ReverseBit bit(updates + 2); for (int i = 1; i <= updates; i += 1) { int type; cin >> type; if (type == 1) { int id, sum; cin >> id >> sum; last_receipts[id - 1] = Receipt{.sum = sum, .time = i}; } else { int sum; cin >> sum; bit.Add(i, sum); } } for (const auto &r : last_receipts) { cout << max(r.sum, bit.GetMax(r.time + 1)) << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; char x[100100]; long x2[100100]; long mes[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; long wr = 0; long res, cur, repsmax = -1; long reps = 0; long tmp1, tmp2, tmp3; string s1; int compare(const void *a, const void *b) { return (*(long *)a - *(long *)b); } long check(long z) { if ((isdigit(x[z])) && (isdigit(x[z + 1])) && (isdigit(x[z + 3])) && (isdigit(x[z + 4])) && (isdigit(x[z + 6])) && (isdigit(x[z + 7])) && (isdigit(x[z + 8])) && (isdigit(x[z + 9]))) { if ((x[z + 2] == x[z + 5]) && (x[z + 2] == - )) { tmp1 = ((long)(x[z]) - (long)( 0 )) * 10 + ((long)(x[z + 1]) - (long)( 0 )); tmp2 = ((long)(x[z + 3]) - (long)( 0 )) * 10 + ((long)(x[z + 4]) - (long)( 0 )); tmp3 = ((long)(x[z + 6]) - (long)( 0 )) * 1000 + ((long)(x[z + 7]) - (long)( 0 )) * 100 + (((long)(x[z + 8]) - (long)( 0 )) * 10) + ((long)(x[z + 9]) - (long)( 0 )); if ((tmp2 <= 12) && (tmp3 <= 2015) && (tmp3 >= 2013)) { if ((tmp1 <= mes[tmp2]) && (tmp2 != 0) && (tmp1 != 0)) { x2[wr++] = tmp1 + tmp2 * 100 + tmp3 * 10000; } } } } if ((!isdigit(x[z + 9])) && (x[z + 9] != - )) { return -2; } } int main(int argc, char *argv[]) { scanf( %s , &x); long j = 0; while (check(j++) > -2) { } qsort(x2, wr - 1, sizeof(long), compare); cur = x2[0]; for (long j = 0; j < wr; j++) { if (cur == x2[j]) { reps++; } else { if (reps > repsmax) { repsmax = reps; res = cur; } cur = x2[j]; reps = 1; } } if (reps > repsmax) { repsmax = reps; res = cur; } cur = x2[j]; reps = 1; ldiv_t divresult1; divresult1 = ldiv(res, 100); if (divresult1.rem < 10) { cout << 0 ; } cout << divresult1.rem << - ; ldiv_t divresult2; divresult2 = ldiv(res, 10000); if (((divresult2.rem - divresult1.rem) / 100) < 10) { cout << 0 ; } cout << (divresult2.rem - divresult1.rem) / 100 << - ; ldiv_t divresult3; divresult3 = ldiv(res, 100000000); cout << (divresult3.rem - divresult2.rem) / 10000; return EXIT_SUCCESS; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long double EPS = 1e-6; const int N = 200020, MOD = 998244353; int n, k; long long a[N + 20], fact[N + 20], inv[N + 20]; long long qpow(long long a, long long b, long long p = MOD) { long long ans = 1; for (; b; b >>= 1) { if (b & 1) ans = ans * a % p; a = a * a % p; } return ans % p; } void prework() { fact[0] = 1; for (int i = 1; i <= N; i++) fact[i] = fact[i - 1] * i % MOD; inv[N - 1] = qpow(fact[N - 1], MOD - 2) % MOD; for (int i = N - 2; ~i; i--) inv[i] = inv[i + 1] * (i + 1) % MOD; } long long C(int n, int m) { if (n - m < 0 || m < 0) return 0; return fact[n] % MOD * inv[m] % MOD * inv[n - m] % MOD % MOD; } int main() { prework(); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; long long ans = 0; int c = 0, m = 0; a[n + 1] = a[1]; for (int i = 1; i <= n; i++) if (a[i] != a[i + 1]) m++; for (int i = 0; i <= m / 2; i++) { ans += C(m, i) % MOD * C(m - i, i) % MOD * qpow(k - 2, m - 2 * i) % MOD; ans %= MOD; } ans = (qpow(k, m) - ans + MOD) % MOD * qpow(2, MOD - 2) % MOD; cout << ans % MOD * qpow(k, n - m) % MOD << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int max = a[0]; int pos = 0; for (int i = 0; i < n; i++) { if (max < a[i]) { max = a[i]; pos = i; } } bool k = true; for (int i = pos; i > 0; i--) { if (a[i - 1] >= a[i]) { k = false; } } for (int i = pos; i < n - 1; i++) { if (a[i] <= a[i + 1]) { k = false; } } if (k == true) printf( YES n ); else printf( NO n ); return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,avx,avx2 ) const long long maxn = 64, mod = 1e9 + 7, INF = 1e9, lg = 15 + 1, SQRT = 400; int n, a[maxn], par[maxn], SZ_T[maxn], FAC[maxn], INV[maxn]; vector<int> adj1[maxn], adj2[maxn], cmp; long long dp[(1 << lg)][maxn], ans[maxn]; bool mark[maxn]; inline long long power(long long a, long long b) { long long res = 1; while (b) { if (b & 1) { res = (res * a) % mod; } b /= 2; a = (a * a) % mod; } return res; } inline void make_graph() { sort(a, a + n); for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (a[j] % a[i] == 0) { adj1[i].push_back(j); adj1[j].push_back(i); } } } } void dfs(int v) { mark[v] = 1; cmp.push_back(a[v]); for (auto u : adj1[v]) { if (!mark[u]) { dfs(u); } } } inline void get(int cnt) { memset(dp, 0, sizeof dp); sort(cmp.begin(), cmp.end()); vector<int> s, t; for (int i = 0; i < cmp.size(); ++i) { bool is = 0; for (int j = 0; j < i; ++j) { if (cmp[i] % cmp[j] == 0) is = 1; } if (!is) { s.push_back(cmp[i]); } else { t.push_back(cmp[i]); } } for (int i = 0; i < t.size(); ++i) { par[i] = 0; for (int j = 0; j < s.size(); ++j) { if (t[i] % s[j] == 0) { par[i] |= (1 << j); } } } SZ_T[cnt] = t.size(); if (!t.size()) { ans[cnt] = 1; return; } for (int i = 0; i < t.size(); ++i) { dp[par[i]][1]++; } for (int mask = 0; mask < (1 << s.size()); ++mask) { for (int i = 0; i < t.size(); ++i) { int counter = 0; for (int j = 0; j < t.size(); ++j) { if ((mask | par[j]) == mask) { counter++; } else if (mask & par[j]) { dp[mask | par[j]][i + 1] = (dp[mask][i] + dp[mask | par[j]][i + 1]) % mod; } } if (counter > i) dp[mask][i + 1] = (dp[mask][i + 1] + (dp[mask][i] * (counter - i)) % mod) % mod; } } ans[cnt] = dp[(1 << s.size()) - 1][t.size()]; } int main() { ios::sync_with_stdio(false); cin.tie(0); FAC[0] = INV[0] = 1; for (int i = 1; i < maxn; ++i) { FAC[i] = (FAC[i - 1] * i) % mod; INV[i] = power(FAC[i], mod - 2); } cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; } make_graph(); int cnt = 0; for (int i = 0; i < n; ++i) { if (!mark[i]) { dfs(i); get(cnt); cnt++; cmp.clear(); } } long long res = 1, SZ = 0; for (int i = 0; i < cnt; ++i) { res = (res * ans[i]) % mod; SZ += max(SZ_T[i] - 1, 0); } long long h = FAC[SZ]; for (int i = 0; i < cnt; ++i) { h = (h * INV[max(SZ_T[i] - 1, 0)]) % mod; } res = (res * h) % mod; cout << res << endl; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ff_24x2048_fwft_async.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ff_24x2048_fwft_async (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [23:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [23:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [23:0] sub_wire1;
wire sub_wire2;
wire [10:0] sub_wire3;
wire [10:0] sub_wire4;
wire wrfull = sub_wire0;
wire [23:0] q = sub_wire1[23:0];
wire rdempty = sub_wire2;
wire [10:0] wrusedw = sub_wire3[10:0];
wire [10:0] rdusedw = sub_wire4[10:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdusedw (sub_wire4),
.rdfull (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
dcfifo_component.lpm_numwords = 2048,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 24,
dcfifo_component.lpm_widthu = 11,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "24"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "24"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M10K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL "rdusedw[10..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw[10..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_24x2048_fwft_async.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_24x2048_fwft_async.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_24x2048_fwft_async.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_24x2048_fwft_async.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_24x2048_fwft_async_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_24x2048_fwft_async_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int a[100100], b[100100]; int n, x; multiset<int> st; multiset<int>::iterator it; int main() { scanf( %d%d , &n, &x); for (int i = 0; i < n; i++) scanf( %d , a + i); for (int i = 0; i < n; i++) { int w; scanf( %d , &w); st.insert(w); } sort(a, a + n); reverse(a, a + n); int res = 1; for (int i = 0; i < n; i++) { int w = x - a[i]; it = st.lower_bound(w); if (it != st.end()) { st.erase(it); res = i + 1; } } printf( 1 %d , res); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; set<string> s0; for (int i = 0; i < n; i++) { cin >> s; unordered_set<char> s1; s.erase(remove_if(s.begin(), s.end(), [&](char const c) { return !(s1.insert(c).second); }), s.end()); sort(s.begin(), s.end()); s0.insert(s); } cout << s0.size() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; #define FOR(i, n) for (int (i) = 0; (i) < (n); (i)++) #define FORI(i, a, b) for (int (i) = (a); (i) < (b); (i)++) #define ll long long #define mp(m, n) make_pair((m), (n)) // #define DEBUG #ifdef DEBUG template<typename T> void _debug(string s, T x) { cerr << s << : ; for (auto it = x.begin(); it != x.end(); ++it) { cerr << << *it; } cerr << endl; } template<typename T, typename K> void _debug(string s, map<T, K> x) { cerr << s << : ; for (auto it = x.begin(); it != x.end(); ++it) { cerr << << it->first << : << it->second; } cerr << endl; } template<typename T, typename K> void _debug(string s, set<T, K> x) { cerr << s << : ; for (auto it = x.begin(); it != x.end(); ++it) { cerr << << *it; } cerr << endl; } template<typename T, typename K> void _debug(string s, vector<pair<T, K> > x) { cerr << s << : ; for (auto it = x.begin(); it != x.end(); ++it) { cerr << << it->first << , << it->second; } cerr << endl; } void _debug(string s, int x) { cerr << s << : << x << endl; } void _debug(string s, long long x) { cerr << s << : << x << endl; } void _debug(string s, double x) { cerr << s << : << x << endl; } #define debug(x) _debug(#x, (x)) #else #define debug(x) #endif #define db debug const long long N = 2e3 + 4; int t[4*N] = {}; void add(int L, int R, int val, int index = 1, int l = 1, int r = N - 1) { if (L > R) return; if (r < L || l > R) return; if (L <= l && r <= R) {t[index] += val; return; } int mid = (l + r) / 2; // debug(l);debug(r);debug(mid); add(L, R, val, index * 2, l, mid); add(L, R, val, index * 2 + 1, mid + 1, r); // if (pos < l || pos > r) return; // if (l == r) { // t[index] = val; // return; // } // int mid = (l + r) / 2; // upd(pos, val, index * 2, l, mid); // upd(pos, val, index * 2 + 1, mid + 1, r); // t[index] = min(t[index * 2], t[index * 2 + 1]); } int get_val(int pos, int index = 1, int l = 1, int r = N - 1) { if (pos < l || pos > r) return 0; if (l == r) { return t[index]; } int mid = (l + r) / 2; return t[index] + get_val(pos, index * 2, l, mid) + get_val(pos, index * 2 + 1, mid + 1, r); } inline int in(int a, int b, int c, int d) { int x = max(a, c); int y = min(b, d); return max(0, y - x + 1); } int main() { ios_base::sync_with_stdio(false); std::cin.tie(0); int n, m, k; cin >> n >> m >> k; vector<int> l(m), r(m); FOR(i, m) cin >> l[i] >> r[i]; int R = 0; for (int i = 1; i + k - 1 <= n; i++) { memset(t, 0, sizeof(t)); int ans = 0; for (int j = 0; j < m; j++) { ans += in(i, i + k - 1, l[j], r[j]); int x, y; x = max(i + 1, l[j] - k + 1); y = l[j]; vector<int> vvv; vvv = {x, y, 1}; debug(vvv); add(x, y, 1); // int xx = r[j] - k + 2; // int yy = r[j] + 1; // yy = min(yy, xx + y - x); int xx = r[j] - k + 2; int yy = r[j] + 1; xx = max(i + 1, xx); yy = min(yy, xx + y - x); add(xx, yy, -1); vvv = {xx, yy, -1}; debug(vvv); } debug(i); debug(ans); R = max(R, ans); for (int j = i + 1; j + k - 1 <= n; j++) { ans += get_val(j); R = max(R, ans); debug(j); debug(ans); } } cout << R << endl; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int xa, ya; int xb, yb; int xc, yc; double k, b, y; scanf( %d %d , &xa, &ya); scanf( %d %d , &xb, &yb); scanf( %d %d , &xc, &yc); if (xa != xb) { k = (double)(yb - ya) / (xb - xa); b = ya - (double)(yb - ya) / (xb - xa) * xa; y = k * xc + b; } if (xa < xb) puts(y < yc ? LEFT : (yc < y ? RIGHT : TOWARDS )); if (xa == xb) puts(xc == xa ? TOWARDS : ((xc < xa) != (yb < ya) ? LEFT : RIGHT )); if (xa > xb) puts(y < yc ? RIGHT : (yc < y ? LEFT : TOWARDS )); return 0; } |
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output reg [WIDTH-1:0] out_data,
output reg out_nd,
output reg [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output wire error
);
reg [WIDTH-1:0] xa;
reg [WIDTH-1:0] xb;
reg [WIDTH-1:0] w;
reg [2:0] counter;
reg active;
reg x_nd;
reg [MWIDTH-1:0] bf_in_m;
wire [MWIDTH-1:0] bf_out_m;
always @ (posedge clk)
begin
// Default x_nd
x_nd <= 1'b0;
if (~rst_n)
begin
active <= 1'b0;
counter <= 2'b0;
end
else if (in_nd)
begin
if (((~active)& (in_data != {WIDTH{1'b0}})) | (counter == 2'd0))
begin
active <= 1'b1;
xa <= in_data;
counter <= 2'd1;
bf_in_m <= in_m;
end
else if (counter == 2'd1)
begin
xb <= in_data;
counter <= 2'd2;
end
else if (counter == 2'd2)
begin
w <= in_data;
counter <= 2'd0;
x_nd <= 1'b1;
end
end
end
wire [WIDTH-1:0] ya;
wire [WIDTH-1:0] yb;
reg [WIDTH-1:0] yb_old;
wire y_nd;
reg y_nd_old;
reg error_control;
wire error_bf;
assign error = error_control | error_bf;
always @ (posedge clk)
begin
// default out_nd
out_nd <= 1'b0;
y_nd_old <= y_nd;
if (~rst_n)
begin
error_control <= 1'b0;
y_nd_old <= 1'b0;
end
else if (y_nd)
begin
if (y_nd_old)
error_control <= 1'b1;
yb_old <= yb;
out_data <= ya;
out_nd <= 1'b1;
out_m <= bf_out_m;
end
else if (y_nd_old)
begin
out_data <= yb_old;
out_nd <= 1'b1;
out_m <= {MWIDTH{1'b0}};
end
end
butterfly
#(.MWIDTH (MWIDTH),
.WIDTH (WIDTH)
)
butterfly_0
(.clk (clk),
.rst_n (rst_n),
.m_in (bf_in_m),
.w (w),
.xa (xa),
.xb (xb),
.x_nd (x_nd),
.m_out (bf_out_m),
.ya (ya),
.yb (yb),
.y_nd (y_nd),
`ifdef DEBUG
.out_msg(out_msg),
.out_msg_nd(out_msg_nd),
`endif
.error(error_bf)
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef enum [3:0] {
E01 = 1,
E03 = 3,
E04 = 4
} my_t;
integer cyc = 0;
my_t e;
int arrayfits [e.num]; // Check can use as constant
string all;
// Check constification
initial begin
e = E03;
`checkh(e.first, E01);
`checkh(e.last, E04);
`checkh(e.last(), E04);
`checkh(e.next, E04);
`checkh(e.next(), E04);
`checkh(e.next(1), E04);
`checkh(e.next(1).next(1), E01);
`checkh(e.next(2), E01);
`checkh(e.next(1).next(1).next(1), E03);
`checkh(e.next(1).next(2), E03);
`checkh(e.next(3), E03);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
`checkh(e.prev(1).prev(1), E04);
`checkh(e.prev(2), E04);
`checkh(e.num, 3);
`checks(e.name, "E03");
//
all = "";
for (my_t e = e.first; e != e.last; e = e.next) begin
all = {all, e.name};
end
e = e.last;
all = {all, e.name};
`checks(all, "E01E03E04");
end
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
e <= E01;
end
else if (cyc==1) begin
`checks(e.name, "E01");
`checkh(e.next, E03);
`checkh(e.next(1), E03);
`checkh(e.next(2), E04);
`checkh(e.prev, E04);
`checkh(e.prev(1), E04);
`checkh(e.prev(2), E03);
e <= E03;
end
else if (cyc==2) begin
`checks(e.name, "E03");
`checkh(e.next, E04);
`checkh(e.next(1), E04);
`checkh(e.next(2), E01);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
`checkh(e.prev(2), E04);
e <= E04;
end
else if (cyc==3) begin
`checks(e.name, "E04");
`checkh(e.next, E01);
`checkh(e.next(1), E01);
`checkh(e.next(2), E03);
`checkh(e.prev, E03);
`checkh(e.prev(1), E03);
`checkh(e.prev(2), E01);
e <= E01;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const int M = 128; const int inf = 0x7fffffff; const long long INF = 9E18; const int mod = 1e9 + 7; int tree[maxn << 2][2], a[maxn]; int in[maxn], out[maxn], dis[maxn]; int dfs_clock = 0; vector<int> g[maxn]; void dfs(int u, int fa) { dis[u] = dis[fa] ^ 1; in[u] = ++dfs_clock; for (int i = 0; i < g[u].size(); i++) { int to = g[u][i]; if (to == fa) continue; dfs(to, u); } out[u] = dfs_clock; } void pushdown(int rt, int odd) { if (tree[rt][odd]) { tree[rt << 1 | 1][odd] += tree[rt][odd]; tree[rt << 1][odd] += tree[rt][odd]; tree[rt][odd] = 0; } } void update(int x, int y, int l, int r, int val, int odd, int rt) { if (x <= l && r <= y) { tree[rt][odd] += val; return; } pushdown(rt, odd); int mid = (l + r) >> 1; if (x <= mid) update(x, y, l, mid, val, odd, rt << 1); if (y > mid) update(x, y, mid + 1, r, val, odd, rt << 1 | 1); } int query(int p, int l, int r, int rt, int odd) { if (l == r) { return tree[rt][odd]; } pushdown(rt, odd); int mid = (l + r) >> 1; if (p <= mid) return query(p, l, mid, rt << 1, odd); else return query(p, mid + 1, r, rt << 1 | 1, odd); } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } dis[0] = 0; dfs(1, 0); for (int i = 0; i < m; i++) { int op; scanf( %d , &op); if (op == 1) { int x, val; scanf( %d%d , &x, &val); update(in[x], out[x], 1, n, val, dis[x], 1); update(in[x], out[x], 1, n, -val, dis[x] ^ 1, 1); } else { int num; scanf( %d , &num); cout << query(in[num], 1, n, 1, dis[num]) + a[num] << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; int n, q, len[N]; char name[N][20], ip[N][20]; bool dy(char ip1[], char ip2[], int len) { for (int i = 0; i < len; i++) if (ip1[i] != ip2[i]) return 0; return 1; } int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) scanf( %s%s , name[i], ip[i]), len[i] = strlen(ip[i]); while (q--) { char na[20], IP[20]; scanf( %s%s , na, IP); int L = strlen(IP) - 1; IP[L] = 0 ; for (int i = 1; i <= n; i++) if (len[i] == L && dy(IP, ip[i], L)) { printf( %s %s; #%s n , na, IP, name[i]); break; } } return 0; } |
#include <bits/stdc++.h> using namespace std; /*<DEBUG>*/ #define tem template <typename #define can_shift(_X_, ...) enable_if_t<sizeof test<_X_>(0) __VA_ARGS__ 8, debug&> operator<<(T i) #define _op debug& operator<< tem C > auto test(C *x) -> decltype(cerr << *x, 0LL); tem C > char test(...); tem C > struct itr{C begin, end; }; tem C > itr<C> get_range(C b, C e) { return itr<C>{b, e}; } struct debug{ #ifdef _LOCAL ~debug(){ cerr << endl; } tem T > can_shift(T, ==){ cerr << boolalpha << i; return *this; } tem T> can_shift(T, !=){ return *this << get_range(begin(i), end(i)); } tem T, typename U > _op (pair<T, U> i){ return *this << < << i.first << , << i.second << > ; } tem T> _op (itr<T> i){ *this << { ; for(auto it = i.begin; it != i.end; it++){ *this << , + (it==i.begin?2:0) << *it; } return *this << } ; } #else tem T> _op (const T&) { return *this; } #endif }; string _ARR_(int* arr, int sz){ string ret = { + to_string(arr[0]); for(int i = 1; i < sz; i++) ret += , + to_string(arr[i]); ret += } ; return ret; } #define exp(...) [ << #__VA_ARGS__ << : << (__VA_ARGS__) << ] /*</DEBUG>*/ typedef long long ll; typedef unsigned long long ull; typedef unsigned int uint; typedef pair<int, int> pii; //mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); #define pb push_back #define FAST ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0) #define TC int __TC__; cin >> __TC__; while(__TC__--) #define ar array const int INF = 1e9 + 7, N = 5e5; ll x, y; ll extended_euclid(ll a, ll b){ if(b == 0){ x = 1; y = 0; return a; } ll g = extended_euclid(b, a%b); ll nx, ny; nx = y; ny = x - (a/b)*y; x = nx; y = ny; return g; } ll a[N], b[N], g=0, l, sum=0; vector<ll> same; map<ll, ll> pos, issame; int main(void) { FAST; ll n, m, k; cin >> n >> m >> k; for(int i = 0; i < n; ++i) cin >> a[i]; for(int i = 0; i < m; ++i) cin >> b[i]; if(m < n){ swap(m, n); swap(a,b); } // n <= m // a is shorter than b for(int i = 0; i < m; ++i) pos[b[i]] = i; g = extended_euclid(n,m); l = n*m/g; debug() << exp(x) exp(y); ll posx, negx; if(x == 0){ x += m; y -= n; } if(x < 0){ negx = x; // n*x + m*y = g //x += m; //y -= n; ll times = (abs(x) + m)/m; x += times*m; y -= times*n; posx = x; }else{ posx = x; ll times = (x + m)/m; x -= times*m; y += times*n; negx = x; } debug() << exp(x) exp(y); // x > 0 for(ll i = 0; i < n; ++i){ if(pos.find(a[i]) != pos.end()){ ll p = pos[a[i]]; ll c = p - i; if(c == 0){ same.pb(i); issame[i] = 1; }else if(c<0 && abs(c) % g == 0){ c = abs(c); ll times = c/g; ll pos = (-negx*times)*n + i; pos %= l; same.pb(pos); issame[pos] = 1; }else if(c % g == 0){ ll times = c/g; ll pos = (posx * times) * n + i; pos %= l; same.pb(pos); issame[pos] = 1; } } } sort(same.begin(), same.end()); sum = n*(m/g) - same.size(); debug() << exp(same) exp(same.size()); ll ans = 0; ans += l*(k/sum); k = (k%sum); if(k == 0){ ans -= l; k += sum; } --k; // -> k = {0, 1, 2,..., sum-1} ll pos = k; // -> find the pos of the kth collision auto it = lower_bound(same.begin(), same.end(), k); ll diff = 0; ll mv = (it - same.begin()); while(diff < mv || issame[pos]){ if(!issame[pos]) diff++; pos++; } ans += pos+1; // off by one error?; cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; static struct FastInput { static constexpr int BUF_SIZE = 1 << 20; char buf[BUF_SIZE]; size_t chars_read = 0; size_t buf_pos = 0; FILE* in = stdin; char cur = 0; inline char get_char() { if (buf_pos >= chars_read) { chars_read = fread(buf, 1, BUF_SIZE, in); buf_pos = 0; buf[0] = (chars_read == 0 ? -1 : buf[0]); } return cur = buf[buf_pos++]; } inline void tie(int) {} inline explicit operator bool() { return cur != -1; } inline static bool is_blank(char c) { return c <= ; } inline bool skip_blanks() { while (is_blank(cur) && cur != -1) { get_char(); } return cur != -1; } inline FastInput& operator>>(char& c) { skip_blanks(); c = cur; return *this; } inline FastInput& operator>>(string& s) { if (skip_blanks()) { s.clear(); do { s += cur; } while (!is_blank(get_char())); } return *this; } template <typename T> inline FastInput& read_integer(T& n) { n = 0; if (skip_blanks()) { int sign = +1; if (cur == - ) { sign = -1; get_char(); } do { n += n + (n << 3) + cur - 0 ; } while (!is_blank(get_char())); n *= sign; } return *this; } template <typename T> inline typename enable_if<is_integral<T>::value, FastInput&>::type operator>>( T& n) { return read_integer(n); } inline FastInput& operator>>(__int128& n) { return read_integer(n); } template <typename T> inline typename enable_if<is_floating_point<T>::value, FastInput&>::type operator>>(T& n) { n = 0; if (skip_blanks()) { string s; (*this) >> s; sscanf(s.c_str(), %lf , &n); } return *this; } } fast_input; static struct FastOutput { static constexpr int BUF_SIZE = 1 << 20; char buf[BUF_SIZE]; size_t buf_pos = 0; static constexpr int TMP_SIZE = 1 << 20; char tmp[TMP_SIZE]; FILE* out = stdout; inline void put_char(char c) { buf[buf_pos++] = c; if (buf_pos == BUF_SIZE) { fwrite(buf, 1, buf_pos, out); buf_pos = 0; } } ~FastOutput() { fwrite(buf, 1, buf_pos, out); } inline FastOutput& operator<<(char c) { put_char(c); return *this; } inline FastOutput& operator<<(const char* s) { while (*s) { put_char(*s++); } return *this; } inline FastOutput& operator<<(const string& s) { for (int i = 0; i < (int)s.size(); i++) { put_char(s[i]); } return *this; } template <typename T> inline char* integer_to_string(T n) { char* p = tmp + TMP_SIZE - 1; if (n == 0) { *--p = 0 ; } else { bool is_negative = false; if (n < 0) { is_negative = true; n = -n; } while (n > 0) { *--p = (char)( 0 + n % 10); n /= 10; } if (is_negative) { *--p = - ; } } return p; } template <typename T> inline typename enable_if<is_integral<T>::value, char*>::type stringify(T n) { return integer_to_string(n); } inline char* stringify(__int128 n) { return integer_to_string(n); } template <typename T> inline typename enable_if<is_floating_point<T>::value, char*>::type stringify( T n) { sprintf(tmp, %.17f , n); return tmp; } template <typename T> inline FastOutput& operator<<(const T& n) { auto p = stringify(n); for (; *p != 0; p++) { put_char(*p); } return *this; } } fast_output; const int N = 1e6 + 3; vector<int> inq[N]; int main() { ios::sync_with_stdio(false); fast_input.tie(0); int n, m, q; fast_input >> n >> m >> q; vector<vector<int>> edge(n + 1); vector<tuple<int, int, int>> edges; for (int i = 0; i < m; i++) { int u, v, w; fast_input >> u >> v >> w; edges.emplace_back(u, v, w); edge[u].emplace_back(i); } priority_queue<pair<long long, int>> pq; const long long inf = 1e18; vector<long long> d(n + 1, inf); d[1] = 0; pq.emplace(d[1], 1); while ((int)pq.size()) { auto x = pq.top(); pq.pop(); if (-x.first != d[x.second]) continue; int v = x.second; for (auto& x : edge[v]) { int u = get<1>(edges[x]); if (d[u] > d[v] + get<2>(edges[x])) { d[u] = d[v] + get<2>(edges[x]); pq.emplace(-d[u], u); } } } vector<int> add(m); for (int i = 0; i < m; i++) { auto& x = edges[i]; add[i] = get<2>(x) - (d[get<1>(x)] - d[get<0>(x)]); } int up = 0; while (q--) { int type; fast_input >> type; if (type == 1) { int v; fast_input >> v; if (up) { vector<int> dist(n + 1, (int)1e9); dist[1] = 0; inq[0].emplace_back(1); for (int i = 0; i <= up; i++) { for (int j = 0; j < (int)inq[i].size(); j++) { int v = inq[i][j]; if (dist[v] != i) continue; for (auto& x : edge[v]) { int u = get<1>(edges[x]); if (dist[u] > dist[v] + add[x]) { dist[u] = dist[v] + add[x]; if (dist[u] <= up) inq[dist[u]].emplace_back(u); } } } inq[i].clear(); } for (int i = 1; i <= n; i++) d[i] = min(d[i] + dist[i], inf); for (int i = 0; i < m; i++) { auto& x = edges[i]; add[i] -= (dist[get<1>(x)] - dist[get<0>(x)]); } up = 0; } if (d[v] != inf) fast_output << d[v] << n ; else fast_output << -1 n ; } else { int foo; fast_input >> foo; for (int i = 0; i < foo; i++) { int x; fast_input >> x; --x; add[x]++; } up += foo; } } } |
#include <bits/stdc++.h> using namespace std; int N, V, k, y; vector<int> vec; int main() { cin >> N >> V; for (int i = 1; i <= N; i++) { cin >> k; int x = 1000000000; for (int j = 1; j <= k; j++) { cin >> y; x = min(x, y); } if (x < V) vec.push_back(i); } cout << vec.size() << endl; for (int i = 0; i < vec.size(); i++) cout << vec[i] << ; return (0); } |
#include <bits/stdc++.h> using namespace std; const long long logn = 63; const long long inf = 1e18; void upd(long long& a, const long long& b) { a = min(a, b); } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<long long> a(n), b(n); for (int i = 0; i < n; i++) cin >> a[i]; long long mx = *max_element(a.begin(), a.end()); for (int i = 0; i < n; i++) b[i] = mx - a[i]; vector<vector<long long> > dp(logn, vector<long long>(n + 1, inf)); dp[0][0] = 0; vector<int> s; for (int i = 0; i < n; i++) s.push_back(i); for (long long bit = 0; bit + 1 < logn; bit++) { if (bit) { vector<int> nws; for (int i : s) if (!(b[i] & (1ll << (bit - 1)))) nws.push_back(i); for (int i : s) if (b[i] & (1ll << (bit - 1))) nws.push_back(i); s = nws; } vector<long long> pf0(n + 1, 0), pf1(n + 1, 0); for (int i = 0; i < n; i++) { pf0[i + 1] = pf0[i], pf1[i + 1] = pf1[i]; if (b[s[i]] & (1ll << bit)) pf1[i + 1]++; else pf0[i + 1]++; } for (int sf = 0; sf <= n; sf++) { int b0ones = pf1[n - sf] + (pf0[n] - pf0[n - sf]); int b0carry = pf1[n] - pf1[n - sf]; upd(dp[bit + 1][b0carry], dp[bit][sf] + b0ones); int b1ones = pf0[n - sf] + (pf1[n] - pf1[n - sf]); int b1carry = n - pf0[n - sf]; upd(dp[bit + 1][b1carry], dp[bit][sf] + b1ones); } } cout << dp[logn - 1][0] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 9e18L; const long long mod = 1e9 + 7; long long power(long long x, long long y) { long long res = 1; int mod = 1e9 + 7; while (y > 0) { if (y & 1) (res = res * x) %= mod; (x = x * x) %= mod; y = y >> 1; } return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; long long n = s.size(); if (n <= 2) { cout << s << n ; return 0; } int cnt = 1; vector<pair<char, long long>> v; for (int i = 1; i < n; i++) { if (s[i] == s[i - 1]) cnt++; else { v.push_back({s[i - 1], cnt}); cnt = 1; } } v.push_back({s[n - 1], cnt}); int m = v.size(); for (int i = 1; i < m; i++) { if (v[i].second >= 2 && v[i - 1].second >= 2) { v[i].second = 1; v[i - 1].second = 2; } if (v[i].second > 2) v[i].second = 2; } string res = ; for (auto x : v) { long long k = min(x.second, 2LL); while (k--) res += x.first; } cout << res << n ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:27:23 04/18/2014
// Design Name:
// Module Name: pbdebounce
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pbdebounce
(input wire clk,
input wire button,
output reg pbreg);
reg [7:0] pbshift;
wire clk_1ms;
timer_1ms m0(clk, clk_1ms);
always@(posedge clk_1ms) begin
pbshift=pbshift<<1;//shift left for 1 bit
pbshift[0]=button;
if (pbshift==0)
pbreg=0;
if (pbshift==8'hFF)// pbshift is 11111111
pbreg=1;
end
endmodule
module timer_1ms
(input wire clk,
output reg clk_1ms);
reg [15:0] cnt;
initial begin
cnt [15:0] <=0;
clk_1ms <= 0;
end
always@(posedge clk)
if(cnt>=25000) begin
cnt<=0;
clk_1ms <= ~clk_1ms;
end
else begin
cnt<=cnt+1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_4_V
`define SKY130_FD_SC_LP__A21BOI_4_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_V |
module MPUC707 ( CLK,ED, DS, MPYJ,DR,DI ,DOR ,DOI );
// MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(es), .MPYJ(mpyj) ,
parameter total_bits = 32;
input CLK ;
wire CLK ;
input DS ; //data strobe
wire DS ;
input ED; //slowdown
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [total_bits-1:0] DR ;
wire signed [total_bits-1:0] DR ;
input [total_bits-1:0] DI ;
wire signed [total_bits-1:0] DI ;
output [total_bits-1:0] DOR ;
reg [total_bits-1:0] DOR ;
output [total_bits-1:0] DOI ;
reg [total_bits-1:0] DOI ;
reg signed [total_bits+1 :0] dx5;
reg signed [total_bits : 0] dt;
reg signed [total_bits-1 : 0] dii;
wire signed [total_bits+2 : 0] dx5p;
wire signed [total_bits+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [total_bits-1:0] doo ;
reg [total_bits-1:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2;
if (DS) begin
dx5<=DR+(DR <<2); //multiply by 5
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dt<=dii;
end
doo<=(dot >>>4) ;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx5>>>2); // multiply by 101101
assign dot= dx5p+(dt>>>4)+(dx5>>>12);// (dt>>>9); // multiply by 10110101000000101
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > di = {{2, 1}, {1, 2}, {-1, 2}, {-2, 1}, {-2, -1}, {-1, -2}, {1, -2}, {2, -1}}; int n, m; int X1, Y1, X2, Y2; queue<pair<int, int> > q1, q2; bool isValid(pair<int, int> cell) { return (1 <= cell.first && cell.first <= n && 1 <= cell.second && cell.second <= m); } int dist1[1009][1009]; int dist2[1009][1009]; pair<int, int> dad1[1009][1009]; pair<int, int> dad2[1009][1009]; bool was1[1009][1009]; bool was2[1009][1009]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; cin >> X1 >> Y1 >> X2 >> Y2; q1.push({n / 2, m / 2}); dist1[n / 2][m / 2] = 0; was1[n / 2][m / 2] = true; while (!q1.empty()) { pair<int, int> cur = q1.front(); q1.pop(); for (pair<int, int> d : di) { pair<int, int> neighbour; neighbour.first = cur.first + d.first; neighbour.second = cur.second + d.second; if (!isValid(neighbour)) continue; if (was1[neighbour.first][neighbour.second]) continue; dist1[neighbour.first][neighbour.second] = dist1[cur.first][cur.second] + 1; dad1[neighbour.first][neighbour.second] = cur; was1[neighbour.first][neighbour.second] = true; q1.push(neighbour); } } q2.push({n / 2 + 1, m / 2}); dist2[n / 2 + 1][m / 2] = 0; was2[n / 2 + 1][m / 2] = true; while (!q2.empty()) { pair<int, int> cur = q2.front(); q2.pop(); for (pair<int, int> d : di) { pair<int, int> neighbour; neighbour.first = cur.first + d.first; neighbour.second = cur.second + d.second; if (!isValid(neighbour)) continue; if (was2[neighbour.first][neighbour.second]) continue; dist2[neighbour.first][neighbour.second] = dist2[cur.first][cur.second] + 1; dad2[neighbour.first][neighbour.second] = cur; was2[neighbour.first][neighbour.second] = true; q2.push(neighbour); } } if (dist1[X1][Y1] < dist1[X2][Y2] && dist1[X1][Y1] <= dist2[X2][Y2]) { cout << WHITE << endl; fflush(stdout); while (1) { pair<int, int> uj = dad1[X1][Y1]; X1 = uj.first; Y1 = uj.second; cout << X1 << << Y1 << endl; fflush(stdout); if (X1 == n / 2 && Y1 == m / 2) return 0; cin >> X2 >> Y2; if (X2 == -1 && Y2 == -1) return 0; } } if (dist2[X2][Y2] + 1 < dist2[X1][Y1] && dist2[X2][Y2] < dist1[X1][Y1]) { cout << BLACK << endl; fflush(stdout); cin >> X1 >> Y1; if (X1 == -1 && Y1 == -1) return 0; while (1) { pair<int, int> uj = dad2[X2][Y2]; X2 = uj.first; Y2 = uj.second; cout << X2 << << Y2 << endl; fflush(stdout); if (X2 == n / 2 + 1 && Y2 == m / 2) return 0; cin >> X1 >> Y1; if (X1 == -1 && Y1 == -1) return 0; } } if ((X1 + Y1) % 2 != (X2 + Y2) % 2) { cout << WHITE << endl; fflush(stdout); bool reached = false; if (X1 == n / 2 + 1 && Y1 == m / 2) { reached = true; } while (1) { if (reached) break; pair<int, int> uj = dad2[X1][Y1]; X1 = uj.first; Y1 = uj.second; cout << X1 << << Y1 << endl; fflush(stdout); if (X1 == X2 && Y1 == Y2) return 0; if (X1 == n / 2 + 1 && Y1 == m / 2) break; cin >> X2 >> Y2; if (X2 == -1 && Y2 == -1) return 0; } if (!reached) cin >> X2 >> Y2; int ddx = abs(X1 - X2); int ddy = abs(Y1 - Y2); if ((ddx == 1 && ddy == 2) || (ddx == 2 && ddy == 1)) { cout << X2 << << Y2 << endl; fflush(stdout); return 0; } cout << (n / 2) << << (m / 2) + 2 << endl; fflush(stdout); if (n / 2 == X2 && m / 2 + 2 == Y2) return 0; cin >> X2 >> Y2; cout << (n / 2) + 2 << << (m / 2) + 1 << endl; fflush(stdout); if (n / 2 + 2 == X2 && m / 2 + 1 == Y2) return 0; cin >> X2 >> Y2; cout << (n / 2) << << (m / 2) << endl; fflush(stdout); return 0; } else { cout << BLACK << endl; fflush(stdout); cin >> X1 >> Y1; if (X1 == -1 && Y1 == -1) return 0; int dx = abs(X2 - (n / 2 + 1)); int dy = abs(Y2 - m / 2); if ((dx == 1 && dy == 2) || (dx == 2 && dy == 1)) { cout << n / 2 + 1 << << m / 2 << endl; fflush(stdout); return 0; } bool reached = false; if (X2 == n / 2 && Y2 == m / 2) { reached = true; } while (1) { if (reached) break; pair<int, int> uj = dad1[X2][Y2]; X2 = uj.first; Y2 = uj.second; cout << X2 << << Y2 << endl; fflush(stdout); if (X1 == X2 && Y1 == Y2) return 0; if (X2 == n / 2 && Y2 == m / 2) break; cin >> X1 >> Y1; if (X1 == -1 && Y1 == -1) return 0; } if (!reached) cin >> X1 >> Y1; int ddx = abs(X1 - X2); int ddy = abs(Y1 - Y2); if ((ddx == 1 && ddy == 2) || (ddx == 2 && ddy == 1)) { cout << X1 << << Y1 << endl; fflush(stdout); return 0; } cout << (n / 2) + 2 << << (m / 2) + 1 << endl; fflush(stdout); if (n / 2 + 2 == X1 && m / 2 + 1 == Y1) return 0; cin >> X1 >> Y1; cout << (n / 2) << << (m / 2) + 2 << endl; fflush(stdout); if (n / 2 == X1 && m / 2 + 2 == Y1) return 0; cin >> X1 >> Y1; cout << (n / 2) + 1 << << (m / 2) << endl; fflush(stdout); return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, int> nums; int liking[7][7]; bool usable[7]; int team[7]; vector<int> members[3]; int mindifference, maxliking; int a, b, c; void teaming(int currteam, int memberno) { int i, j, t; if (currteam == 2 && memberno == 7) { int exp1 = a / members[0].size(), exp2 = b / members[1].size(), exp3 = c / members[2].size(); int minexp = min(exp1, min(exp2, exp3)); int maxexp = max(exp1, max(exp2, exp3)); int diff = maxexp - minexp; int lliking = 0; for (t = 0; t < 3; t++) { for (i = 0; i < members[t].size(); i++) { for (j = 0; j < 7; j++) { if (liking[members[t][i]][j] == 1 && team[j] == t && team[members[t][i]] == t) lliking++; } } } if (diff < mindifference || (diff == mindifference && lliking > maxliking)) { mindifference = diff; maxliking = lliking; } return; } if (memberno >= 7) return; for (i = 0; i < 7; i++) if (usable[i]) { usable[i] = false; team[i] = currteam; members[currteam].push_back(i); teaming(currteam, memberno + 1); members[currteam].pop_back(); if (currteam < 2 && members[currteam].size() > 0) { team[i] = currteam + 1; members[currteam + 1].push_back(i); teaming(currteam + 1, memberno + 1); members[currteam + 1].pop_back(); } team[i] = -1; usable[i] = true; } } int main() { int i, j, n; nums.insert(make_pair( Anka , 0)); nums.insert(make_pair( Chapay , 1)); nums.insert(make_pair( Cleo , 2)); nums.insert(make_pair( Troll , 3)); nums.insert(make_pair( Dracul , 4)); nums.insert(make_pair( Snowy , 5)); nums.insert(make_pair( Hexadecimal , 6)); scanf( %d , &n); for (i = 0; i < 7; i++) for (j = 0; j < 7; j++) liking[i][j] = 0; for (i = 0; i < 7; i++) { usable[i] = true; team[i] = -1; } for (i = 0; i < n; i++) { char name1[30], tmp[30], name2[30]; scanf( %s %s %s , name1, tmp, name2); liking[nums[name1]][nums[name2]] = 1; } scanf( %d %d %d , &a, &b, &c); mindifference = 2000000000; maxliking = 0; teaming(0, 0); printf( %d %d , mindifference, maxliking); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; bool lucky[10010]; int n, m; int a[N]; int t[N + N]; void init() { memset(lucky, false, sizeof(lucky)); lucky[0] = true; for (int i = 1; i <= 10000; i++) if (i % 10 == 4 || i % 10 == 7) lucky[i] = lucky[i / 10]; } void update(int i, int v) { if (!v) return; i += n; while (i >= 1) { t[i] += v; i >>= 1; } } int query(int Left, int Right) { int res = 0; Left += n; Right += n; while (Left <= Right) { if (Left % 2) res += t[Left]; if ((~Right) % 2) res += t[Right]; Left = (Left + 1) >> 1; Right = (Right - 1) >> 1; } return res; } int main() { init(); scanf( %d%d , &n, &m); memset(t, 0, sizeof(t)); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); update(i, lucky[a[i]]); } char x[10]; int Left, Right, temp; while (m--) { scanf( %s , &x); if (strcmp(x, count ) == 0) { scanf( %d%d , &Left, &Right); Left--; Right--; printf( %d n , query(Left, Right)); } else { scanf( %d%d%d , &Left, &Right, &temp); Left--; Right--; for (int i = Left; i <= Right; i++) { a[i] += temp; update(i, lucky[a[i]] - lucky[a[i] - temp]); } } } return 0; } |
// __ // _______ / _|_ _ _ __ _ _ ___ // |_ / _ |_| | | | __| | | / __| created on // / / __/ _| |_| | | | |_| __ 18 Mar 2021 00:06:00 // /___ ___|_| __, |_| __,_|___/ // |___/ #include<bits/stdc++.h> using namespace std; #define int long long #define deb(...) cerr << [ << #__VA_ARGS__ << ] : [ , DBG(__VA_ARGS__) void DBG() { cerr << ] n ;} template<typename T, typename ...Args> void DBG(T first, Args... args) {cerr << first; if(sizeof...(args))cerr<< , ; DBG(args...); } class Math{ private: int size; std::vector<int> prime,spf,square_of_a_prime; public: Math(int size_):size(size_){ /* prime.resize(size); */ spf.resize(size); /* square_of_a_prime.resize(size); */ } std::vector<int> seive(){ for(int i=2;i<size;i++)prime[i]=1; for(int i=2;i<size;i++){ if(prime[i]){ if(i*i<size)square_of_a_prime[i*i]=1; for(int j=2;j<size;j++){ if(i*j<size) prime[i*j]=0; else break; } } } return prime; } void smallest_prime_factor(){ spf.assign(size,-1); spf[1]=1; for(int i=2; i<size; i++){ if(spf[i]==-1){ spf[i] = i; for(int j = 2; j*i<size; j++){ if(spf[i*j]==-1){ spf[i*j] = i; } } } } } int SPF(int x){ return spf[x]; } int count_no_of_factors(int x){ // complexity is O(n^1/3)... seive(); int ans = 1; for(int i=0;i<size;i++){ if(prime[i]){ if(i*i*i > x)break; int count = 1; while(x%i==0){ count++; x/=i; } ans *= count; } } if(prime[x])ans*=2; else if(square_of_a_prime[x])ans*=3; else if(x!=1)ans*=4; return ans; } std::vector<int> prime_factorize(int x){ // complexity is O(n^1/2) std::vector<int> ff(size,0); while(x%2==0){ ff[2]++; x/=2; } for(int i=3;i*i<=x;i+=2){ while(x%i==0){ ff[i]++; x/=i; } } if(x>2)ff[x]++; return ff; } std::vector<int> prime_factorize_using_seive(int x){ smallest_prime_factor(); std::vector<int> ff(size,0); while(x!=1){ ff[spf[x]]++; x/=spf[x]; } return ff; } int phi(int n){ int result = n; for(int i=2; i*i<=n; i++){ if (n%i==0) { while(n%i==0) n/=i; result-=result/i; } } if (n>1) result-=result/n; return result; } std::vector<int> phi_1_to_n(int n){ std::vector<int> phi(n+1); phi[0] = 0; phi[1] = 1; for (int i=2; i<=n; i++) phi[i]=i; for (int i = 2; i <= n; i++) { if (phi[i]==i) { for (int j=i; j<=n; j+=i) phi[j] -= phi[j]/i; } } return phi; } }; int32_t main(){ ios_base:: sync_with_stdio(false); cin.tie(0); int t=1; cin >> t; Math m((int)1e7); m.smallest_prime_factor(); for(int tt=1;tt<=t;tt++){ int ans= 0; int n; cin >> n; int k; cin >> k; map<int,int> f; for(int i=0;i<n;i++){ int x; cin >> x; int y=1; map<int,int> used; while(x!=1){ int num = m.SPF(x); while(x%num==0){ x/=num; used[num]++; } } for(auto ele : used){ if(ele.second&1) y*=ele.first; } if(f.count(y)){ ans++; f.clear(); f[y]++; } else{ f[y]++; } } cout << ans+1 << n ; } } |
#include <bits/stdc++.h> using namespace std; long long spf[101]; long long fac[101]; void sieve() { spf[1] = 1; for (long long i = 2; i < 101; i++) spf[i] = i; for (long long i = 4; i < 101; i += 2) spf[i] = 2; for (long long i = 3; i * i < 101; i++) { if (spf[i] == i) { for (long long j = i * i; j < 101; j += i) if (spf[j] == j) spf[j] = i; } } } map<long long, long long> getfactor(long long a) { map<long long, long long> m; while (a > 1) { m[spf[a]]++; a /= spf[a]; } return m; } long long power(long long x, long long y, long long p) { long long res = 1; x = x; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } long long inverse(long long a, long long p) { return power(a, p - 2, p); } long long ncr(long long n, long long r, long long p) { if (r == 0) return 1; return (fac[n] * inverse(fac[r], p) % p * inverse(fac[n - r], p) % p) % p; } long long pre1[200000] = {0}, pre2[200000] = {0}; void solve() { long long n; cin >> n; for (long long i = 1; i <= n; i++) { long long x; cin >> x; pre1[i] += pre1[i - 1] + (x == 1); pre2[i] += pre2[i - 1] + (x == 2); } for (long long i = n + 1; i <= 150000; i++) { pre1[i] += pre1[i - 1] + 1; pre2[i] += pre2[i - 1] + 1; } vector<pair<long long, long long> > v; for (long long i = 1; i <= n; i++) { long long j = 0; long long count1 = 0, count2 = 0; long long counter = 0; while (1) { long long g = lower_bound(pre1 + j, pre1 + 140000, pre1[j] + i) - pre1; long long l = lower_bound(pre2 + j, pre2 + 140000, pre2[j] + i) - pre2; if (g == n && l > n) { count1++; if (count1 > count2) { v.push_back(make_pair(count1, i)); break; } } if (l == n && g > n) { count2++; if (count2 > count1) { v.push_back(make_pair(count2, i)); break; } } if (l > n && g > n) break; if (l < g) { count2++; j = l; } else { count1++; j = g; } } } sort(v.begin(), v.end()); cout << v.size() << n ; for (auto it : v) cout << it.first << << it.second << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int dr[] = {-1, 0, 1, 0, -1, -1, 1, 1}; const int dc[] = {0, -1, 0, 1, -1, 1, -1, 1}; long long ax, ay, bx, by, cx, cy; long long dist(long long x1, long long y1, long long x2, long long y2) { return ((x1 - x2) * (x1 - x2)) + ((y1 - y2) * (y1 - y2)); } int main() { cin >> ax >> ay >> bx >> by >> cx >> cy; if (dist(ax, ay, bx, by) != dist(bx, by, cx, cy)) { cout << No n ; return 0; } if (ax - bx == bx - cx && ay - by == by - cy) cout << No n ; else if (ax - cx == cx - bx && ay - cy == cy - by) cout << No n ; else if (bx - ax == ax - cx && by - ay == ay - cy) cout << No n ; else if (bx - cx == cx - ax && by - cy == cy - ay) cout << No n ; else if (cx - ax == ax - cx && cy - ay == ay - cy) cout << No n ; else if (cx - bx == bx - cx && cy - by == by - cy) cout << No n ; else cout << Yes n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, nxt[402][26]; string s, t; int dp[401][401]; bool solve2(string t1, string t2) { dp[0][0] = -1; for (int i = 0; i <= t1.size(); ++i) { for (int j = 0; j <= t2.size(); ++j) { if (!i && !j) continue; dp[i][j] = n; if (i) dp[i][j] = min(dp[i][j], nxt[dp[i - 1][j] + 1][t1[i - 1] - a ]); if (j) dp[i][j] = min(dp[i][j], nxt[dp[i][j - 1] + 1][t2[j - 1] - a ]); } } return dp[t1.size()][t2.size()] < n; } void solve() { cin >> s >> t; n = s.size(); m = t.size(); for (int i = 0; i < 26; ++i) nxt[n][i] = nxt[n + 1][i] = n; for (int i = n - 1; ~i; --i) { memcpy(nxt[i], nxt[i + 1], sizeof(nxt[0])); nxt[i][s[i] - a ] = i; } for (int i = 0; i < m; ++i) if (solve2(t.substr(0, i), t.substr(i))) { cout << YES n ; return; } cout << NO n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; long long l_occ_1 = -1, l_occ_2 = -1, l_occ_3 = -1; long long maxi = s.length() + 1, mini; for (long long i = 0; i < s.length(); i++) { if (s[i] == 1 ) l_occ_1 = i; if (s[i] == 2 ) l_occ_2 = i; if (s[i] == 3 ) l_occ_3 = i; if (!(l_occ_1 == -1 || l_occ_2 == -1 || l_occ_3 == -1)) { long long x = max(abs(l_occ_1 - l_occ_3), abs(l_occ_2 - l_occ_3)); mini = max(x, abs(l_occ_1 - l_occ_2)); maxi = min(maxi, mini); } } if (l_occ_1 == -1 || l_occ_2 == -1 || l_occ_3 == -1) maxi = -1; cout << maxi + 1 << n ; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// bug998
interface intf
#(parameter PARAM = 0)
();
logic val;
function integer func (); return 5; endfunction
endinterface
module t1(intf mod_intf);
initial begin
$display("%m %d", mod_intf.val);
end
endmodule
module t();
generate
begin : TestIf
intf #(.PARAM(1)) my_intf ();
assign my_intf.val = '0;
t1 t (.mod_intf(my_intf));
// initial $display("%0d", my_intf.func());
end
endgenerate
generate
begin
intf #(.PARAM(1)) my_intf ();
assign my_intf.val = '1;
t1 t (.mod_intf(my_intf));
// initial $display("%0d", my_intf.func());
end
endgenerate
localparam LP = 1;
logic val;
generate begin
if (LP) begin
intf #(.PARAM(2)) my_intf ();
assign my_intf.val = '1;
assign val = my_intf.val;
end else begin
intf #(.PARAM(3)) my_intf ();
assign my_intf.val = '1;
assign val = my_intf.val;
end
end endgenerate
initial begin
$display("%0d", val);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 4e6 + 10; int n, m; int a[N]; int find(int x) { for (int i = 1; i <= n; i++) { if (a[i] == x) return i; } } vector<int> v; signed main() { int x, y, z, T; cin >> T; while (T--) { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); bool f = 0; for (int i = 1; i <= n; i += 2) if (a[i] % 2 == 0) f = 1; if (f) { puts( -1 ); continue; } v.clear(); for (int i = n; i >= 1; i -= 2) { if (i == 1) continue; int l = find(i), r = find(i - 1); if (l == i && r == i - 1) continue; if (l == 1 && r == 2) { v.push_back(i); reverse(a + 1, a + 1 + i); continue; } v.push_back(l); reverse(a + 1, a + 1 + l); l = 1, r = find(i - 1); if (l == 1 && r == 2) { v.push_back(i); reverse(a + 1, a + 1 + i); continue; } v.push_back(r - 1); reverse(a + 1, a + 1 + r - 1); v.push_back(r + 1); reverse(a + 1, a + 1 + r + 1); v.push_back(3); reverse(a + 1, a + 1 + 3); v.push_back(i); reverse(a + 1, a + 1 + i); } cout << v.size() << endl; for (int i : v) cout << i << ; cout << endl; } return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEV",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEV",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_1_V
`define SKY130_FD_SC_HDLL__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_1_V
|
#include<bits/stdc++.h> #define mx 100005 #define lli long long int #define ulli unsigned long long int #define mset(a,b) memset(a, b, sizeof(a)) #define infile freopen( in.txt , r , stdin); #define outfile freopen ( out.txt , w ,stdout); #define fileclose fclose (stdin); fclose (stdout); #define test_case lli T; cin>>T;for(lli t=1;t<=T;t++) #define scani(x) scanf( %d ,&x); #define printi(x) printf( %d n ,x); #define scanli(x) scanf( %lld ,&x); #define printli(x) printf( %lld n ,x); #define frep(i,from,to) for(lli i=from;i<=to;i++) #define frev(i,from,to) for(lli i=from;i>=to;i--) using namespace std; int main() { //infile //outfile test_case { lli n; lli x,mini=2000000000,mi; scanli(n); frep(i,1,n) { cin>>x; if(x<mini) { mi=i; mini=x; } } cout<<n-1<< n ; frep(j,1,n) { if(mi!=j) cout<<mi<< <<j<< <<mini<< <<abs(mi-j)+mini<< n ; } } fileclose } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, cnt, Max, head[N]; struct Edge { int to, nxt, val; } e[N << 1]; int read() { int x = 0, flg = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) flg = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return x * flg; } void add(int x, int y, int w) { e[++cnt].to = y; e[cnt].val = w; e[cnt].nxt = head[x]; head[x] = cnt; } void dfs(int x, int fa, int dis) { Max = max(Max, dis); for (int i = head[x]; i; i = e[i].nxt) { int u = e[i].to; if (u == fa) continue; dfs(u, x, dis + e[i].val); } } int main() { n = read(); int x, y, w; long long sum = 0; for (int i = 2; i <= n; ++i) { x = read(), y = read(), w = read(); add(x, y, w); add(y, x, w); sum += 2 * w; } dfs(1, 0, 0); printf( %lld n , sum - Max); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long n, m; while (cin >> n >> m) { long c = 0; if (n * 2 >= m) { for (int i = 0; i < m; i++) { cout << i + 1 << ; } } else { c = 1; for (int i = 2 * n + 1; i <= m; i++) { cout << i << << c << ; c++; } for (int i = c; i <= 2 * n; i++) { cout << i << ; } } } return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_to_hw_sig (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 1: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] data_out;
wire [ 1: 0] out_port;
wire [ 1: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[1 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <cstdio> #include <algorithm> #define ll long long int using namespace std; const int MAX = 1e7+10; int t, c; int ans[MAX]; int prime[MAX], pcount; bool vis[MAX]; ll d[MAX], f[MAX]; void eular() { for (int i = 1; i <= MAX; i++) ans[i] = MAX; ans[1] = 1; for (int i = 2; i < MAX; i++) { if (!vis[i]) { vis[i] = 1; prime[pcount++] = i; d[i] = f[i] = i + 1; if (ans[i + 1] > i) ans[i + 1] = i; } for (int j = 0; j < pcount && (ll)prime[j] * i < MAX; j++) { vis[prime[j] * i] = 1; if (i % prime[j] == 0) { f[prime[j] * i] = f[i] * prime[j] + 1; d[prime[j] * i] = d[i] / f[i] * f[prime[j] * i]; } else { f[prime[j] * i] = f[prime[j]]; d[prime[j] * i] = d[i] * f[prime[j] * i]; } if (d[prime[j] * i] < MAX && ans[d[prime[j] * i]] > prime[j] * i) ans[d[prime[j] * i]] = prime[j] * i; if (i % prime[j] == 0) break; } } } int main() { eular(); scanf( %d , &t); while(t--) { scanf( %d , &c); if (ans[c] != MAX) printf( %d n , ans[c]); else printf( -1 n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[100005]; int main() { long long n; scanf( %lld , &n); for (long long i = 0; i < n; i++) scanf( %lld , &a[i]); sort(a, a + n); long long sm = 0; for (long long i = 0; i < n / 2; i++) { sm = ((sm % 10007) + ((a[i] % 10007) * (a[n - i - 1] % 10007)) % 10007) % 10007; } sm = (sm * 2) % 10007; if (n % 2 == 1) sm = ((sm % 10007) + ((a[n / 2] % 10007) * (a[n / 2] % 10007)) % 10007) % 10007; cout << sm << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long t, n; long long qpow(long long a, long long b) { long long x = 1, base = a; while (b) { if (b & 1) { x = (x * base) % 1000000007; } base = (base * base) % 1000000007; b >>= 1; } return x % 1000000007; } int main() { ios::sync_with_stdio(0); cin >> n; long long ans = (qpow(4, ((1ll << n) - 2)) * 6) % 1000000007; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int n; vector<long long> v(100005); vector<int> cache(1e5 + 10, -1); int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; map<int, int> mp; for (long long i = 0; i < n; i++) { int x; cin >> x; set<int> st; for (int k = 2; k * k <= x; k++) { if (x % k == 0) { st.insert(k); while (x % k == 0) { x = x / k; } } } int mx = 0; if (x > 1) { st.insert(x); } for (auto it : st) { mp[it]++; mx = max(mx, mp[it]); } for (auto it : st) { mp[it] = mx; } } int maxi = 1; for (auto it : mp) maxi = max(maxi, it.second); cout << maxi << n ; } |
#include <bits/stdc++.h> using namespace std; struct segment { int pos; int len; int type; }; struct lengthComparator { bool operator()(const segment &a, const segment &b) const { if (a.len != b.len) return a.len > b.len; else return a.pos < b.pos; } }; struct positionComparator { bool operator()(const segment &a, const segment &b) const { return a.pos < b.pos; } }; set<segment, lengthComparator> lengthSet; set<segment, positionComparator> positionSet; void add_segment(segment s) { lengthSet.insert({s}); positionSet.insert({s}); } void remove_segment(segment s) { lengthSet.erase({s}); positionSet.erase({s}); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } a.push_back(-1); int start = 0; for (int i = 0; i < a.size(); i++) { if (i > 0 and a[i] != a[i - 1]) { segment s = {start, (i - 1) - start + 1, a[i - 1]}; lengthSet.insert(s); positionSet.insert(s); start = i; } } int sol = 0; while (!lengthSet.empty()) { segment s = *lengthSet.begin(); segment left, right; bool leftExists = false, rightExists = false; auto lbIterator = positionSet.find(s); if (lbIterator != positionSet.begin()) { left = *(--lbIterator); leftExists = true; } auto ubIterator = positionSet.find(s); if (++ubIterator != positionSet.end()) { right = *ubIterator; rightExists = true; } if (leftExists and rightExists and left.type == right.type) { segment merged = {left.pos, left.len + right.len, left.type}; remove_segment(left); remove_segment(right); add_segment(merged); } remove_segment(s); sol++; } cout << sol << n ; return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_1024x8.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_1024x8(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 8;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x8_bist artisan_ssp(
`else
art_hssp_1024x8 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp(
`else
vs_hdsp_1024x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
.WE(we),
.DO(doq[3:0])
);
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
.WE(we),
.DO(doq[7:4])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_key (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 1: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] d1_data_in;
reg [ 1: 0] d2_data_in;
wire [ 1: 0] data_in;
reg [ 1: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 1: 0] edge_detect;
wire irq;
reg [ 1: 0] irq_mask;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({2 {(address == 0)}} & data_in) |
({2 {(address == 2)}} & irq_mask) |
({2 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[1 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; struct no { int x, y, r; }; no A, B, b, a; int dist(no u, no v) { return (u.x - v.x) * (u.x - v.x) + (u.y - v.y) * (u.y - v.y); } bool contido(no v, no u) { if (u.r < v.r) return 0; if ((sqrt(dist(v, u)) + (double)((v.r)) - 1e-2 < (double)(u.r))) return 1; return 0; } bool disjunto(no v, no u) { if (sqrt(dist(u, v)) > (double)(v.r + u.r) - 1e-2) return 1; return 0; } int main() { cin >> a.x >> a.y >> a.r >> A.r; A.x = a.x, A.y = a.y; cin >> b.x >> b.y >> b.r >> B.r; B.x = b.x, B.y = b.y; if (B.r < A.r) { swap(B, A); swap(a, b); } int ans; if (contido(A, B)) { if (contido(A, b)) ans = 4; else if (contido(a, b) || contido(b, a)) ans = 2; else if (disjunto(b, A)) ans = 2; else ans = 1; } else if (disjunto(A, B)) { ans = 4; } else { if (contido(a, b) || contido(b, a)) ans = 1; else { ans = 0; if (disjunto(a, B)) ans++; if (disjunto(b, A)) ans++; } } cout << ans << endl; return 0; } |
module recepcion_TB;
reg rx=1;
wire avail;
reg clk_in;
wire clk_div;
reg reset=0;
wire [7:0] dout;
recepcion rec(.rx(rx),.clk_in(clk_in),.reset(reset),.dout(dout),.avail(avail),.clk_div(clk_div));
reg [3:0] bitpos = 0;
reg [3:0] counter = 0;
reg [7:0] data = 8'b10101010;
always #1 clk_in = ~clk_in;
initial begin
clk_in=0;
reset=0;
end
always @(posedge clk_div)begin
counter <= counter+1;
if (counter >=4)begin
if(bitpos<=7)begin
rx<=data[bitpos];
bitpos<=bitpos+1;
end
else begin
rx<=1;
if (avail==1)begin
counter<=0;
bitpos<=0;
end
end
end
else if (counter<3)
rx=1;
else if (counter==3)
rx=0;
end
initial begin: TEST_CASE
$dumpfile("recepcion_TB.vcd");
$dumpvars(0, recepcion_TB);
$display("FIN de la simulacion");
# $finish;
end
endmodule
|
`timescale 1ns/1ns
module usb_tx_ack
(input c,
input start,
output [7:0] sie_d,
output sie_dv);
`include "usb_pids.v"
localparam ST_IDLE = 3'd0;
localparam ST_SYNC = 3'd1;
localparam ST_PID = 3'd2;
localparam SW=4, CW=2;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire sie_d_sel;
wire [7:0] sie_mux_z;
gmux #(.DWIDTH(8), .SELWIDTH(1)) sie_d_gmux
(.d({PID_ACK, 8'b10000000}), .sel(sie_d_sel), .z(sie_mux_z));
wire [7:0] sie_d_i = sie_dv_i ? sie_mux_z : 8'h0;
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_SYNC , 2'b01 };
else ctrl = { ST_IDLE , 2'b00 };
ST_SYNC: ctrl = { ST_PID , 2'b11 };
ST_PID: ctrl = { ST_IDLE , 2'b00 };
default: ctrl = { ST_IDLE , 2'b00 };
endcase
end
wire sie_dv_i = ctrl[0];
assign sie_d_sel = ctrl[1];
// help timing a bit
d1 #(8) sie_d1_d_r (.c(c), .d(sie_d_i ), .q(sie_d ));
d1 sie_d1_dv_r(.c(c), .d(sie_dv_i), .q(sie_dv));
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1, 1, 1, -1, -1}; int dy[] = {1, -1, 0, 0, 1, -1, 1, -1}; int a[33]; string s; int main() { for (int i = 0; i < 26; ++i) scanf( %d , &a[i]); cin >> s; int len = s.length(); vector<long long> v(len + 1); for (int i = 0; i < len; ++i) { v[i + 1] = a[s[i] - a ] + v[i]; } map<pair<int, long long>, int> m; long long res = 0; for (int i = 0; i < len; i++) { if (m[make_pair(s[i] - a , v[i + 1])]) { res += m[make_pair(s[i] - a , v[i + 1])]; } m[make_pair(s[i] - a , v[i + 1] + a[s[i] - a ])]++; } cout << res << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTN_2_V
`define SKY130_FD_SC_MS__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTN_2_V
|
#include <bits/stdc++.h> using namespace std; int n, k, q; vector<int> style; vector<vector<int> > place; vector<int> base; vector<vector<int> > t; void read() { cin >> n >> k; style.resize(n + 1); place.resize(100001); base.resize(n + 1); t.resize(n * 4 + 4); for (int i = 1; i < n + 1; i++) cin >> style[i]; cin >> q; } void build(int v, int tl, int tr) { if (tl == tr) { t[v] = vector<int>(1, base[tl]); } else { int tm = (tl + tr) / 2; build(v * 2, tl, tm); build(v * 2 + 1, tm + 1, tr); merge(t[v * 2].begin(), t[v * 2].end(), t[v * 2 + 1].begin(), t[v * 2 + 1].end(), back_inserter(t[v])); } } int query(int v, int tl, int tr, int l, int r, int x) { if (l > r) return 0; if (tl == l && tr == r) { vector<int>::iterator pos = lower_bound(t[v].begin(), t[v].end(), x); return pos - t[v].begin(); } else { int tm = (tl + tr) / 2; return (query(v * 2, tl, tm, l, min(tm, r), x) + query(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r, x)); } } int main() { int x, y, last = 0; int l, r; read(); for (int i = 1; i < n + 1; i++) place[style[i]].push_back(i); for (int i = 1; i < 100001; i++) { for (int j = 0; j < place[i].size(); j++) { if (j >= k) base[place[i][j]] = place[i][j - k]; else base[place[i][j]] = -1; } } place.clear(); style.clear(); build(1, 1, n); while (q--) { cin >> x >> y; l = ((x + last) % n) + 1; r = ((y + last) % n) + 1; if (l > r) swap(l, r); last = query(1, 1, n, l, r, l); cout << last << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_TB_V
`define SKY130_FD_SC_LS__DLRTN_TB_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_ls__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_TB_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module FIFO_image_filter_src1_data_stream_1_V
#(parameter
MEM_STYLE = "block",
DATA_WIDTH = 8,
ADDR_WIDTH = 15,
DEPTH = 20000
)
(
// system signal
input wire clk,
input wire reset,
// write
output wire if_full_n,
input wire if_write_ce,
input wire if_write,
input wire [DATA_WIDTH-1:0] if_din,
// read
output wire if_empty_n,
input wire if_read_ce,
input wire if_read,
output wire [DATA_WIDTH-1:0] if_dout
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
(* ram_style = MEM_STYLE *)
reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];
reg [DATA_WIDTH-1:0] q_buf = 1'b0;
reg [ADDR_WIDTH-1:0] waddr = 1'b0;
reg [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire push;
wire pop;
reg [ADDR_WIDTH-1:0] usedw = 1'b0;
reg full_n = 1'b1;
reg empty_n = 1'b0;
reg [DATA_WIDTH-1:0] q_tmp = 1'b0;
reg show_ahead = 1'b0;
reg [DATA_WIDTH-1:0] dout_buf = 1'b0;
reg dout_valid = 1'b0;
//------------------------Instantiation------------------
//------------------------Task and function--------------
//------------------------Body---------------------------
assign if_full_n = full_n;
assign if_empty_n = dout_valid;
assign if_dout = dout_buf;
assign push = full_n & if_write_ce & if_write;
assign pop = empty_n & if_read_ce & (~dout_valid | if_read);
assign wnext = !push ? waddr :
(waddr == DEPTH - 1) ? 1'b0 :
waddr + 1'b1;
assign rnext = !pop ? raddr :
(raddr == DEPTH - 1) ? 1'b0 :
raddr + 1'b1;
// waddr
always @(posedge clk) begin
if (reset == 1'b1)
waddr <= 1'b0;
else
waddr <= wnext;
end
// raddr
always @(posedge clk) begin
if (reset == 1'b1)
raddr <= 1'b0;
else
raddr <= rnext;
end
// usedw
always @(posedge clk) begin
if (reset == 1'b1)
usedw <= 1'b0;
else if (push & ~pop)
usedw <= usedw + 1'b1;
else if (~push & pop)
usedw <= usedw - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1)
full_n <= 1'b1;
else if (push & ~pop)
full_n <= (usedw != DEPTH - 1);
else if (~push & pop)
full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1)
empty_n <= 1'b0;
else if (push & ~pop)
empty_n <= 1'b1;
else if (~push & pop)
empty_n <= (usedw != 1'b1);
end
// mem
always @(posedge clk) begin
if (push)
mem[waddr] <= if_din;
end
// q_buf
always @(posedge clk) begin
q_buf <= mem[rnext];
end
// q_tmp
always @(posedge clk) begin
if (reset == 1'b1)
q_tmp <= 1'b0;
else if (push)
q_tmp <= if_din;
end
// show_ahead
always @(posedge clk) begin
if (reset == 1'b1)
show_ahead <= 1'b0;
else if (push && usedw == pop)
show_ahead <= 1'b1;
else
show_ahead <= 1'b0;
end
// dout_buf
always @(posedge clk) begin
if (reset == 1'b1)
dout_buf <= 1'b0;
else if (pop)
dout_buf <= show_ahead? q_tmp : q_buf;
end
// dout_valid
always @(posedge clk) begin
if (reset == 1'b1)
dout_valid <= 1'b0;
else if (pop)
dout_valid <= 1'b1;
else if (if_read_ce & if_read)
dout_valid <= 1'b0;
end
endmodule
|
/* Aligns data before writing.
* Incoming data is aligned to lsb's
*/
module emesh_wralign (/*AUTOARG*/
// Outputs
data_out,
// Inputs
datamode, data_in
);
input [1:0] datamode;
input [63:0] data_in;
output [63:0] data_out;
wire [3:0] data_size;
assign data_size[0]= (datamode[1:0]==2'b00);//byte
assign data_size[1]= (datamode[1:0]==2'b01);//short
assign data_size[2]= (datamode[1:0]==2'b10);//word
assign data_size[3]= (datamode[1:0]==2'b11);//double
//B0(0)
assign data_out[7:0] = data_in[7:0];
//B1(16 NAND2S,8 NOR2S)
assign data_out[15:8] = {(8){data_size[0]}} & data_in[7:0] |
{(8){(|data_size[3:1])}} & data_in[15:8] ;
//B2(16 NAND2S,8 NOR2S)
assign data_out[23:16] = {(8){(|data_size[1:0])}} & data_in[7:0] |
{(8){(|data_size[3:2])}} & data_in[23:16] ;
//B3(24 NAND2S,8 NOR3S)
assign data_out[31:24] = {(8){data_size[0]}} & data_in[7:0] |
{(8){data_size[1]}} & data_in[15:8] |
{(8){(|data_size[3:2])}} & data_in[31:24] ;
//B4(24 NAND2S,8 NOR3S)
assign data_out[39:32] = {(8){(|data_size[2:0])}} & data_in[7:0] |
{(8){data_size[3]}} & data_in[39:32] ;
//B5(24 NAND2S,8 NOR3S)
assign data_out[47:40] = {(8){data_size[0]}} & data_in[7:0] |
{(8){(|data_size[2:1])}} & data_in[15:8] |
{(8){data_size[3]}} & data_in[47:40] ;
//B6(24 NAND2S,8 NOR3S)
assign data_out[55:48] = {(8){(|data_size[1:0])}} & data_in[7:0] |
{(8){data_size[2]}} & data_in[23:16] |
{(8){data_size[3]}} & data_in[55:48] ;
//B7(32 NAND2S,16 NOR2S)
assign data_out[63:56] = {(8){data_size[0]}} & data_in[7:0] |
{(8){data_size[1]}} & data_in[15:8] |
{(8){data_size[2]}} & data_in[31:24] |
{(8){data_size[3]}} & data_in[63:56] ;
endmodule // memory_wralign
|
#include <bits/stdc++.h> using namespace std; const int N = 5e4 + 5, inf = 0x3f3f3f3f; int n, front, x, ans = -inf, nxt; vector<int> interact(int _) { printf( ? %d n , _); fflush(stdout); int a, b; scanf( %d%d , &a, &b); return vector<int>({a, b}); } void give(int _) { printf( ! %d n , _); fflush(stdout); } int seed, seed2; void srand(int x, int y) { seed = x; seed2 = y; } int frand() { return (seed *= 19260817) += ((seed2 += 114514) ^= 1919810); } int rand() { int res = frand(); while (res <= 0) res += n; return res; } int main() { srand(998244353, 1000000007); scanf( %d%d%d , &n, &front, &x); nxt = front; for (int(i) = (1); (i) <= (min(n, 1000) - 1); (i)++) { int pos = rand() % n + 1; vector<int> res = interact(pos); if (res[0] <= x && res[0] > ans) nxt = res[1], ans = res[0]; } if (ans == x) return give(x), 0; for (int(i) = (1); (i) <= (1000); (i)++) { if (nxt == -1) break; vector<int> res = interact(nxt); if (res[0] >= x) return give(res[0]), 0; ans = res[0]; nxt = res[1]; } give(ans >= x ? ans : -1); return 0; int lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; lll = 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e7 + 9, MAXN = 1e6; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; unsigned long long int k, x; cin >> n; while (n--) { cin >> k >> x; cout << x + 9 * (k - 1) << endl; } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_sc_3_rep2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_sc_3_rep2(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_buf, dram_scbuf_ecc_r2_buf,
scbuf_dram_wr_data_r5_buf, scbuf_dram_data_vld_r5_buf,
scbuf_dram_data_mecc_r5_buf, sctag_dram_rd_req_buf,
sctag_dram_rd_dummy_req_buf, sctag_dram_rd_req_id_buf,
sctag_dram_addr_buf, sctag_dram_wr_req_buf, dram_sctag_rd_ack_buf,
dram_sctag_wr_ack_buf, dram_sctag_chunk_id_r0_buf,
dram_sctag_data_vld_r0_buf, dram_sctag_rd_req_id_r0_buf,
dram_sctag_secc_err_r2_buf, dram_sctag_mecc_err_r2_buf,
dram_sctag_scb_mecc_err_buf, dram_sctag_scb_secc_err_buf,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_buf;
output [27:0] dram_scbuf_ecc_r2_buf;
// scbuf to dram TOp
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// BOTTOM
output [63:0] scbuf_dram_wr_data_r5_buf;
output scbuf_dram_data_vld_r5_buf;
output scbuf_dram_data_mecc_r5_buf;
// sctag_dramsctag signals INputs
// @ the TOp.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
// sctag_dram BOTTOM
output sctag_dram_rd_req_buf;
output sctag_dram_rd_dummy_req_buf;
output [2:0] sctag_dram_rd_req_id_buf;
output [39:5] sctag_dram_addr_buf;
output sctag_dram_wr_req_buf;
// Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
// outputs BOTTOM
output dram_sctag_rd_ack_buf;
output dram_sctag_wr_ack_buf;
output [1:0] dram_sctag_chunk_id_r0_buf;
output dram_sctag_data_vld_r0_buf;
output [2:0] dram_sctag_rd_req_id_r0_buf;
output dram_sctag_secc_err_r2_buf ;
output dram_sctag_mecc_err_r2_buf ;
output dram_sctag_scb_mecc_err_buf;
output dram_sctag_scb_secc_err_buf;
// The placement of pins on the top and bottom should be identical to
// the placement of the data column of pins in dram_l2_buf1.v
assign dram_scbuf_data_r2_buf = dram_scbuf_data_r2 ;
assign dram_scbuf_ecc_r2_buf = dram_scbuf_ecc_r2 ;
assign scbuf_dram_wr_data_r5_buf = scbuf_dram_wr_data_r5 ;
assign scbuf_dram_data_vld_r5_buf = scbuf_dram_data_vld_r5 ;
assign scbuf_dram_data_mecc_r5_buf = scbuf_dram_data_mecc_r5 ;
assign dram_sctag_rd_ack_buf = dram_sctag_rd_ack ;
assign dram_sctag_wr_ack_buf = dram_sctag_wr_ack ;
assign dram_sctag_chunk_id_r0_buf = dram_sctag_chunk_id_r0 ;
assign dram_sctag_data_vld_r0_buf = dram_sctag_data_vld_r0;
assign dram_sctag_rd_req_id_r0_buf = dram_sctag_rd_req_id_r0;
assign dram_sctag_secc_err_r2_buf = dram_sctag_secc_err_r2;
assign dram_sctag_mecc_err_r2_buf = dram_sctag_mecc_err_r2;
assign dram_sctag_scb_mecc_err_buf = dram_sctag_scb_mecc_err;
assign dram_sctag_scb_secc_err_buf = dram_sctag_scb_secc_err;
assign sctag_dram_rd_req_buf = sctag_dram_rd_req ;
assign sctag_dram_rd_dummy_req_buf = sctag_dram_rd_dummy_req ;
assign sctag_dram_rd_req_id_buf = sctag_dram_rd_req_id ;
assign sctag_dram_addr_buf = sctag_dram_addr ;
assign sctag_dram_wr_req_buf = sctag_dram_wr_req ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd2 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VGND!=0
* UDP_OUT :=UDP_IN when VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood$l_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_G_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_1_V
`define SKY130_FD_SC_HDLL__AND3_1_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_1_V
|
/**************************************************************
********波特率计数模块
**1：确定发送数据和接收数据的有效范围
**2：进行分频计数（此例中波特率9600bps，时钟50MHz，则分频计数为5207）
**************************************************************/
module Bps_select(
input clk, //系统时钟50MHz
input rst_n, //低电平复位
input en, //使能信号：串口接收活发送开始
output reg sel_data, //波特率计数中心点（采集数据的使能信号）
output reg [3:0] num //一帧数据bit0~bit9
);
parameter bps_div = 13'd5207, //(1/9600**1000/20)
bps_div2 = 13'd2603;
//发送/接收标志位：接收到使能信号en后，将标志位flag拉高，当计数信号num记完一帧数据后将flag拉低
reg flag;
always @(posedge clk or negedge rst_n)
if(!rst_n)
flag <= 0;
else
if(en)
flag <= 1;
else
if(num == 4'd10) //计数完成？
flag <= 0;
//波特率计数
reg [12:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt <= 13'd0;
else
if(flag && cnt < bps_div)
cnt <= cnt + 1'b1;
else
cnt <= 13'd0;
//规定发送数据和接收数据的范围：一帧数据为10bit：1bit开始位+8bit数据位+1bit停止位
always @(posedge clk or negedge rst_n)
if(!rst_n)
num <= 4'd0;
else
if(flag && sel_data)
num <= num +1'b1;
else
if(num == 4'd10)
num <= 1'd0;
//数据在波特率的中间部分采集，即：发送/接收数据的使能信号
always @(posedge clk or negedge rst_n)
if(!rst_n)
sel_data <= 1'b0;
else
if(cnt == bps_div2) //中间取数是为了产生尖峰脉冲，尖峰脉冲为采集数据使能信号，用来把握速率
sel_data <= 1'b1;
else
sel_data <= 1'b0;
endmodule
/*
parameter bps9600 = 5207, //波特率为9600bps
bps19200 = 2603, //波特率为19200bps
bps38400 = 1301, //波特率为38400bps
bps57600 = 867, //波特率为57600bps
bps115200 = 433; //波特率为115200bps
parameter bps9600_2 = 2603,
bps19200_2 = 1301,
bps38400_2 = 650,
bps57600_2 = 433,
bps115200_2 = 216;
*/ |
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