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#include <bits/stdc++.h> using namespace std; using lint = long long; const lint linf = 1e18 + 7; const lint inf = 1e9 + 7; const int MOD = 1000000007; void press(vector<long long>& x) { map<int, int> memo; int n = x.size(); for (int i = 0; i < n; ++i) { memo[x[i]] += 1; } int cur = 1; for (auto& val : memo) { val.second = cur; ++cur; } for (int i = 0; i < n; ++i) { x[i] = memo[x[i]]; } } void solve() { int n; cin >> n; vector<lint> a(n, 0); for (int i = 0; i < n; ++i) cin >> a[i]; auto b = a; press(b); vector<vector<int>> dp(n + 5, vector<int>(3, 0)); vector<int> cnt(n + 5, 0); for (int i = 0; i < n; ++i) cnt[b[i]] += 1; int res = n - 1; for (int i = 0; i < n; ++i) { if (dp[b[i]][0] == 0) { dp[b[i]][0] = max(dp[b[i] - 1][1], dp[b[i] - 1][2]) + 1; } if (dp[b[i]][1] + 1 < cnt[b[i]]) ++dp[b[i]][1]; else { dp[b[i]][2] = dp[b[i]][0] + dp[b[i]][1]; res = min(res, n - dp[b[i]][2]); dp[b[i]][1] += 1; } int hoge = dp[b[i]][1] + cnt[b[i] + 1] - dp[b[i] + 1][1]; res = min(res, n - hoge); hoge = cnt[b[i]] - dp[b[i]][1] + dp[b[i] - 1][2] + 1; res = min(res, n - hoge); } cout << res << n ; } signed main() { cin.tie(0); ios::sync_with_stdio(false); int t; cin >> t; for (int i = 0; i < t; ++i) { solve(); } return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ROM (
address,
clock,
q);
input [13:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "agc.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 14,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "agc.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "agc.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; char s[200001], s1[200001]; int n, m, sum, gang, ans[200001], cnt; int main() { scanf( %s , s1 + 1); m = strlen(s1 + 1); for (int i = 1; i <= m; i++) { if (s1[i] == ( || s1[i] == ) ) s[++n] = s1[i]; if (s1[i] == # ) { s[++n] = ) ; s[++n] = # ; cnt++; } } sum = 0; int now = cnt + 1; for (int i = n; i; i--) { if (s[i] == ) ) { gang++; } if (s[i] == ( ) { if (gang) gang--; else sum++; } if (s[i] == # ) { if (sum > 0) ans[now] = sum; sum = 0; now--; } if ((now > cnt) && (sum > 0)) exit(puts( -1 )); } if (gang) exit(puts( -1 )); ans[now] = sum; sum = 0; for (int i = 1; i <= cnt; i++) printf( %d n , ans[i] + 1); } |
#include <bits/stdc++.h> using namespace std; const int N = 1.5e3 + 5; const int T = 1e5 + 5; const int mod = 1e9 + 7; int n, m, a, b, p, t; int fac[T], inv[T], res; int P[N], F[N], SP[N], SPL[N], S[N][N], L[N][N]; namespace _ { inline int mul(int x, int y) { return 1ll * x * y % mod; } inline int dec(int x, int y) { x -= y; if (x < 0) x += mod; return x; } inline int add(int x, int y) { x += y; if (x >= mod) x -= mod; return x; } inline int modpow(int x, int y, int res = 1) { for (; y; y >>= 1, x = mul(x, x)) if (y & 1) res = mul(res, x); return res; } inline int C(int n, int m) { if (m > n) return 0; return mul(fac[n], mul(inv[m], inv[n - m])); } template <typename _Tp> inline void IN(_Tp& x) { char ch; bool flag = 0; x = 0; while (ch = getchar(), !isdigit(ch)) if (ch == - ) flag = 1; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); if (flag) x = -x; } } // namespace _ using namespace _; int main() { fac[0] = inv[0] = 1; IN(n), IN(m), IN(a), IN(b), IN(t), p = mul(a, modpow(b, mod - 2)); for (int i = 1; i <= t; ++i) fac[i] = mul(fac[i - 1], i); for (int i = 1; i <= t; ++i) inv[i] = modpow(fac[i], mod - 2); for (int i = 0; i <= m; ++i) if (i <= t) P[i] = mul(C(t, i), mul(modpow(p, i), modpow(dec(1, p), t - i))); for (int i = 0; i <= m; ++i) SP[i] = i ? add(P[i], SP[i - 1]) : P[i]; S[0][m] = F[0] = 1; for (int i = 1; i <= n; ++i) { for (int r = 1; r <= m; ++r) { res = dec(mul(SP[r - 1], dec(F[i - 1], L[i - 1][m - r + 1])), SPL[r]); S[i][r] = mul(P[m - r], res), L[i][r + 1] = add(L[i][r], S[i][r]); SPL[r] = add(SPL[r - 1], mul(P[r - 1], L[i][r])); } for (int r = 1; r <= m; ++r) F[i] = add(F[i], S[i][r]); } printf( %d n , F[n]); return 0; } |
#include <bits/stdc++.h> using namespace std; bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; string direc = RDLU ; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int &x, int y, int mod = 1000000007) { assert(y >= 0); x += y; if (x >= mod) x -= mod; assert(x >= 0 && x < mod); } void et() { puts( -1 ); exit(0); } long long fastPow(long long x, long long y, int mod = 1000000007) { long long ans = 1; while (y > 0) { if (y & 1) ans = (x * ans) % mod; x = x * x % mod; y >>= 1; } return ans; } long long gcd1(long long x, long long y) { long long z = y; while (x % y != 0) { z = x % y; x = y; y = z; } return z; } int a[33]; int dp[(1 << 22) + 5], mn[(1 << 22) + 5], bs; void fmain(int ID) { scanf( %d%d , &n, &m); for (int(i) = 1; (i) <= (int)(m); (i)++) { int u, v; scanf( %d%d , &u, &v); u--; v--; a[u] |= 1 << v; a[v] |= 1 << u; } bs = (1 << n) - 1; for (int(i) = 0; (i) < (int)(n); (i)++) dp[1 << i] = 1; for (int(i) = 0; (i) < (int)(n); (i)++) a[i] |= 1 << i; int cc = 0; for (int(i) = 0; (i) < (int)(n); (i)++) if (a[i] == (1 << n) - 1) { cc++; } if (cc == n) { puts( 0 ); return; } for (int s = 0; s < (1 << n); s++) if (dp[s]) { int tmp = 0; for (int(j) = 0; (j) < (int)(n); (j)++) if (s & (1 << j)) { tmp |= a[j]; } for (int(j) = 0; (j) < (int)(n); (j)++) if (tmp & (1 << j)) { dp[s | (1 << j)] = 1; } if (tmp == (1 << n) - 1) { if (__builtin_popcount(s) < __builtin_popcount(bs)) { bs = s; } } } printf( %d n , __builtin_popcount(bs)); for (int(j) = 0; (j) < (int)(n); (j)++) if (bs & (1 << j)) printf( %d , j + 1); } int main() { int t = 1; for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; long long int M, k, Q, sum = 0, a = 1, W; vector<int> x; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld , &W); for (int j = 0; j < W; j++) { x.push_back(i); } } scanf( %lld , &M); for (k = 1; k <= M; k++) { scanf( %lld , &Q); printf( %d n , x[Q - 1]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int n, m, k; int q(int x) { return x * (x + 1) / 2; } int p[200005]; int b[200005]; int u[200005]; int dfs(int v) { u[v] = 1; if (!u[p[v]]) return dfs(p[v]) + 1; else return 1; } int solve() { int n; cin >> n; for (int i = 0; i < n; ++i) { scanf( %d , &p[i + 1]); } int c = 0; for (int i = 0; i < n; ++i) { scanf( %d , &b[i + 1]); c += b[i + 1]; } if (n == 1) { cout << (c + 1) % 2; return 0; } int res = 0; int ones = 0; for (int i = 1; i <= n; ++i) if (!u[i]) { int k = dfs(i); if (k == 1) ++ones; else ++res; } if (res == 1 && ones == 0) { cout << (c + 1) % 2; return 0; } if (res == 0) cout << ones + (c + 1) % 2; else if (ones == 0) cout << res + (c + 1) % 2; else cout << res + ones + (c + 1) % 2; return 0; } int main() { int t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 10; const int mod = 1e9 + 7; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + c - 0 , c = getchar(); return x * f; } int inc(int x, int y) { return (x + y >= mod) ? (x + y - mod) : (x + y); } int del(int x, int y) { return (x - y < 0) ? (x - y + mod) : (x - y); } int qpow(int a, int x, int mo) { int res = 1; while (x) { if (x & 1) res = 1ll * res * a % mo; a = 1ll * a * a % mod; x >>= 1; } return res; } vector<pair<int, int> > g[N]; long long dp[N][N]; map<int, long long> mp; int q[N]; int main() { int n = read(), m = read(), Q = read(); for (int i = 0; i < m; i++) { int u = read(), v = read(), w = read(); g[u].push_back(make_pair(v, w)); g[v].push_back(make_pair(u, w)); } for (int i = 0; i <= m; i++) for (int j = 1; j <= n; j++) dp[i][j] = -2e18; dp[0][1] = 0; int ans = 0; for (int i = 1; i <= m; i++) { long long res = 0; for (int j = 1; j <= n; j++) for (int t = 0; t < g[j].size(); t++) { pair<int, int> now = g[j][t]; int u = now.first, v = j; dp[i][u] = max(dp[i - 1][v] + now.second, dp[i][u]); if (i == m) mp[now.second] = max(dp[i - 1][v] + now.second, mp[now.second]); res = max(res, dp[i][u]); } ans = inc(ans, res % mod); } vector<pair<int, int> > p; for (auto it : mp) { p.push_back(it); } int head = 1, tail = 0; int Inv2 = qpow(2, mod - 2, mod); for (int i = 0; i < p.size(); i++) { while (head <= tail && p[q[tail]].second <= p[i].second) tail--; q[++tail] = i; } Q -= m; int cnt = 0; int pre = 1; for (int i = 2; i <= tail; i++) { pair<int, int> now = p[q[pre]]; pair<int, int> nxt = p[q[i]]; bool ok = 1; long long k = (now.second - nxt.second) / (nxt.first - now.first); for (int j = i + 1; j <= tail; j++) { pair<int, int> o = p[q[j]]; if ((now.second - o.second) / (o.first - now.first) <= k) { ok = 0; break; } } k -= cnt; if (k <= 0 || ok == 0) continue; if (Q <= k) k = Q; ans = inc(ans, inc(1ll * k * (1 + k) % mod * Inv2 % mod * now.first % mod, 1ll * (now.second + 1ll * cnt * now.first % mod) % mod * k % mod)); Q -= k; cnt += k; pre = i; if (Q == 0) break; } pair<int, int> now = p[q[tail]]; if (Q > 0) ans = inc(ans, inc(1ll * Q * (1 + Q) % mod * Inv2 % mod * now.first % mod, 1ll * (now.second + 1ll * cnt * now.first % mod) % mod * Q % mod)); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n; cin >> n; long long int a[n], b[n]; long long int sum_1 = 0, sum_2 = 0, c = 0; for (long long int i = 0; i <= n - 1; i++) { cin >> a[i] >> b[i]; sum_1 += a[i]; sum_2 += b[i]; } if (sum_1 % 2 == 0 && sum_2 % 2 == 0) { cout << 0 << n ; } else if (n == 1) { cout << -1 << n ; } else { for (long long int i = 0; i <= n - 1; i++) { sum_1 -= a[i]; sum_1 += b[i]; sum_2 -= b[i]; sum_2 += a[i]; c++; if (sum_1 % 2 == 0 && sum_2 % 2 == 0) { cout << c << n ; return 0; } c--; sum_1 -= b[i]; sum_1 += a[i]; sum_2 -= a[i]; sum_2 += b[i]; } cout << -1 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; string s; int sz; cin >> n; cin >> s; sz = s.size(); int count = 0; bool valid = true; for (int i = 0; i < sz; i++) { if (s[i] == 1 ) { if (i < sz - 1 && s[i + 1] == 1 ) { valid = false; } count++; } else { if ((i == 0 || s[i - 1] == 0 )) { if (i == sz - 1 || s[i + 1] == 0 ) { valid = false; } } } } if (valid == true && count > 0) { cout << Yes << endl; } else { cout << No << endl; } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; int n; vector<long long> a(200013); bool f(long long m) { long long l = (long long)(a[0] + 2 * m), r = (long long)(a[n - 1] - 2 * m); if (l >= r) { return 1; } if ((r - l) <= 2 * m) { return 1; } long long ll = a[int(upper_bound(a.begin(), a.begin() + n, l) - a.begin())] + 2 * m; long long rr = a[int(upper_bound(a.begin(), a.begin() + n, ll) - a.begin())]; if (rr == 0) { return 1; } return (rr >= r); } int main() { cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; a[i] *= 2; } sort(a.begin(), a.begin() + n); long long l = 0, r = 2000000000; while (l + 1 < r) { long long m = (l + r) / 2; if (!f(m)) { l = m; } else { r = m; } } if (!f(l)) l++; cout.setf(ios::fixed); cout.precision(6); cout << (double)l / 2.0 << endl << (double)(a[0] + l) / 2.0 << << (double)(a[n - 1] - l) / 2.0 << ; long long ll = (long long)(a[0] + 2 * l); long long lll = a[int(upper_bound(a.begin(), a.begin() + n, ll) - a.begin())]; cout << (double)(lll + l) / 2.0; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: udp_reg_master.v 1965 2007-07-18 01:24:21Z grg $
//
// Module: udp_reg_master.v
// Project: NetFPGA
// Description: User data path register master
//
// Note: Set TIMEOUT_RESULT to specify the return value on timeout.
// This can be used to identify broken rings.
//
// Result: ack_in -> data_in
// timeout -> TIMEOUT_RESULT
// loop complete && !ack_in -> deadbeef
//
///////////////////////////////////////////////////////////////////////////////
module udp_reg_master
#(
parameter SRC_ADDR = 0,
parameter TIMEOUT = 127,
parameter TIMEOUT_RESULT = 'h dead_0000,
parameter UDP_REG_SRC_WIDTH = 2
)
(
// Core register interface signals
input core_reg_req,
output reg core_reg_ack,
input core_reg_rd_wr_L,
input [`UDP_REG_ADDR_WIDTH - 1:0] core_reg_addr,
output reg [`CPCI_NF2_DATA_WIDTH - 1:0]core_reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] core_reg_wr_data,
// UDP register interface signals (output)
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH - 1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH - 1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH - 1:0] reg_src_out,
// UDP register interface signals (input)
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH - 1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH - 1:0] reg_src_in,
//
input clk,
input reset
);
localparam WAIT = 'd0;
localparam PROCESSING = 'd1;
localparam DONE = 'd2;
reg [1:0] state;
reg [7:0] count;
wire result_valid = reg_req_in && reg_src_in == SRC_ADDR;
// ==============================================
// State machine for core signals
always @(posedge clk)
begin
if (reset) begin
core_reg_ack <= 1'b0;
core_reg_rd_data <= 'h0;
state <= WAIT;
count <= 'h0;
end
else begin
case (state)
WAIT : begin
if (core_reg_req && !reg_req_in) begin
state <= PROCESSING;
count <= TIMEOUT;
end
end
PROCESSING : begin
if (!core_reg_req) begin
state <= WAIT;
end
else if (result_valid || count == 'h0) begin
state <= DONE;
core_reg_ack <= 1'b1;
if (result_valid && reg_ack_in)
core_reg_rd_data <= reg_data_in;
else if (count == 'h0)
core_reg_rd_data <= TIMEOUT_RESULT;
else
core_reg_rd_data <= 'h dead_beef;
end
count <= count - 'h1;
end
DONE : begin
core_reg_ack <= 1'b0;
if (!core_reg_req)
state <= WAIT;
end
default : begin
// synthesis translate_off
if ($time > 3000)
$display($time, " ERROR: invalid state: %x", state);
// synthesis translate_on
end
endcase
end
end
// ==============================================
// State machine for UDP signals
always @(posedge clk)
begin
if (reset) begin
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= 1'b0;
reg_addr_out <= 'h0;
reg_data_out <= 'h0;
reg_src_out <= 'h0;
end
else begin
// Forward requests that aren't destined to us
if (reg_req_in && reg_src_in != SRC_ADDR) begin
reg_req_out <= reg_req_in;
reg_ack_out <= reg_ack_in;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_data_out <= reg_data_in;
reg_src_out <= reg_src_in;
end
// Put new requests on the bus
else if (state == WAIT && core_reg_req && !reg_req_in) begin
reg_req_out <= 1'b1;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= core_reg_rd_wr_L;
reg_addr_out <= core_reg_addr;
reg_data_out <= core_reg_wr_data;
reg_src_out <= SRC_ADDR;
end
// Twiddle our thumbs -- nothing to do
else begin
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= 1'b0;
reg_addr_out <= 'h0;
reg_data_out <= 'h0;
reg_src_out <= 'h0;
end
end
end
endmodule // unused_reg
|
#include <bits/stdc++.h> int main() { int i = 0, z, flag = 0, even = 0; char str[100002], temp; scanf( %s , str); int size = strlen(str); char x = str[size - 1]; for (i = 0; i < size; i++) { if (str[i] % 2 == 0) { even = 1; if (str[i] < x) { flag = 1; str[size - 1] = str[i]; str[i] = x; break; } else { z = i; } } } if (i >= size && even == 1) { flag = 1; str[size - 1] = str[z]; str[z] = x; } if (flag == 1) { printf( %s , str); } else printf( -1 ); return 0; } |
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
parameter SRL_COUNT = 4;
parameter PRESCALER = 4; // 100000
// UART loopback
assign tx = rx;
// ============================================================================
// Reset
reg [3:0] rst_sr;
wire rst;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign rst = rst_sr[0];
// ============================================================================
// Clock prescaler
reg [32:0] ps_cnt = 0;
wire ps_tick = ps_cnt[32];
always @(posedge clk)
if (rst || ps_tick)
ps_cnt <= PRESCALER - 2;
else
ps_cnt <= ps_cnt - 1;
// ============================================================================
// SRL32 testers
wire sim_error = sw[2];
wire [SRL_COUNT-1:0] srl_q;
wire [SRL_COUNT-1:0] srl_q31;
wire [SRL_COUNT-1:0] error;
genvar i;
generate for(i=0; i<SRL_COUNT; i=i+1) begin
wire [4:0] srl_a;
wire srl_d;
wire srl_sh;
srl_shift_tester tester
(
.clk (clk),
.rst (rst),
.ce (ps_tick),
.srl_sh (srl_sh),
.srl_d (srl_d),
.srl_q (srl_q[i] ^ sim_error),
.srl_a (srl_a),
.error (error[i])
);
SRLC32E srl
(
.CLK (clk),
.CE (srl_sh),
.A (srl_a),
.D (srl_d),
.Q (srl_q[i]),
.Q31 (srl_q31[i])
);
end endgenerate
// ============================================================================
// Error latch
reg [SRL_COUNT-1:0] error_lat = 0;
always @(posedge clk)
if (rst)
error_lat <= 0;
else
error_lat <= error_lat | error;
// ============================================================================
// Create a non-GND/VCC source for additional LED outputs.
// This is a side affect of the ROI disallowing GND/VCC connections to synth
// IO pads.
wire net_0;
LUT2 #(.INIT(4'hC)) lut_0 (.I0(|sw), .I1(&sw), .O(net_0));
// LEDs
genvar j;
generate for(j=0; j<8; j=j+1) begin
if (j < SRL_COUNT) begin
assign led[j ] = (sw[1]) ? error_lat[j] : error[j];
assign led[j+8] = srl_q[j];
end else begin
assign led[j ] = net_0;
assign led[j+8] = net_0;
end
end endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__OR2B_FUNCTIONAL_PP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> int main() { long long t, i, l, k, j, b[23132], s, n; char ch[1000000]; while (gets(ch)) { l = strlen(ch); for (k = 0; k < 124; k++) b[k] = 0; for (k = 0; k < l; k++) { b[ch[k] - 48]++; } s = 0; for (j = 0; j < 124; j++) { if (0 < b[j]) s += b[j] * b[j]; } printf( %lld n , s); } return 0; } |
module top(
input in_clk_12_mhz,
output [7:0] out_leds,
// VGA666
output out_vga_r,
output out_vga_g,
output out_vga_b,
output out_vga_hsync,
output out_vga_vsync,
// Controller 0
output out_controller0_pulse,
output out_controller0_latch,
input in_controller0_data,
// SDRAM
output out_sdram_cle,
output out_sdram_cs,
output out_sdram_cas,
output out_sdram_ras,
output out_sdram_we,
output out_sdram_dqm,
output [1:0] out_sdram_ba,
output [11:0] out_sdram_a,
inout [7:0] inout_sdram_dq
);
// Clock stuff
wire w_vga_clock;
wire w_sdram_clock;
mod_clock_master clock_master(
.in_clk_12_mhz( in_clk_12_mhz ),
.out_clk_25_175_mhz( w_vga_clock ),
.out_clk_166_mhz( w_sdram_clock ),
);
// VGA Display Interface
wire [9:0] w_vga_pix_x;
wire [9:0] w_vga_pix_y;
// Wire from grid -> next overlay
wire [7:0] w_grid_r;
wire [7:0] w_grid_g;
wire [7:0] w_grid_b;
// Grid Overlay
mod_grid_display grid_display(
.in_pix_clk( w_vga_clock ),
.in_pix_x( w_vga_pix_x ),
.in_pix_y( w_vga_pix_y ),
.in_pixel_r( 8'b11111111 ),
.in_pixel_g( 8'b00000000 ),
.in_pixel_b( 8'b00000000 ),
.out_pixel_r( w_grid_r ),
.out_pixel_g( w_grid_g ),
.out_pixel_b( w_grid_b )
);
// Wire from hex output -> next overlay
wire [7:0] w_hex_r;
wire [7:0] w_hex_g;
wire [7:0] w_hex_b;
// Hex Digit Overlay
wire w_hex_display_pixel_on;
mod_hex_display hex_display(
.in_pix_clk( w_vga_clock ),
.in_pix_x( w_vga_pix_x ),
.in_pix_y( w_vga_pix_y ),
.in_latch( out_vga_vsync ),
.in_data0( counter[63:56] ),
.in_data1( counter[55:48] ),
.in_data2( counter[47:40] ),
.in_data3( counter[39:32] ),
.in_data4( counter[31:24] ),
.in_data5( counter[23:16] ),
.in_data6( counter[15:8] ),
.in_data7( controller0_buttons[7:0] ),
.in_pixel_r( w_grid_r ),
.in_pixel_g( w_grid_g ),
.in_pixel_b( w_grid_b ),
.out_pixel_r( w_hex_r ),
.out_pixel_g( w_hex_g ),
.out_pixel_b( w_hex_b )
);
// VGA Output
// Input pixel values are latched on pixel clock edge
// Pixel coordinate outputs indicate position of next clock cycle, not current
// cycle
mod_vga_encoder vga_encoder(
.in_clk_25_175_mhz( w_vga_clock ),
.in_vga_r( w_hex_r ),
.in_vga_g( w_hex_g ),
.in_vga_b( w_hex_b ),
.out_vga_r( { out_vga_r } ),
.out_vga_g( { out_vga_g } ),
.out_vga_b( { out_vga_b } ),
.out_vga_hsync( out_vga_hsync ),
.out_vga_vsync( out_vga_vsync ),
.out_vga_next_x( w_vga_pix_x ),
.out_vga_next_y( w_vga_pix_y )
);
wire [7:0] controller0_buttons;
mod_controller controller0(
.in_clk_controller( counter[8] ),
.in_vsync( out_vga_vsync ),
.in_controller_data( in_controller0_data ),
.out_controller_latch( out_controller0_latch ),
.out_controller_pulse( out_controller0_pulse ),
.out_controller_buttons( controller0_buttons )
);
mod_sdram_controller sdram_controller(
.in_sdram_clk(w_sdram_clock),
.in_rst(1'b0),
.out_sdram_cle(out_sdram_cle),
.out_sdram_cs(out_sdram_cs),
.out_sdram_cas(out_sdram_cas),
.out_sdram_ras(out_sdram_ras),
.out_sdram_we(out_sdram_we),
.out_sdram_dqm(out_sdram_dqm),
.out_sdram_ba(out_sdram_ba),
.out_sdram_a(out_sdram_a),
.inout_sdram_dq(inout_sdram_dq),
.in_addr(22'b0000000000001000100100),
.in_rw(readOrWrite),
.in_data(counter),
.out_data(mem_read),
.out_busy(busy),
.in_valid(start),
.out_valid(done)
);
reg [31:0] mem_read;
reg readOrWrite = 0;
wire busy;
reg start = 0;
wire done;
// Some internal state, used to update an on-screen counter
reg [63:0] counter;
always @(posedge in_clk_12_mhz) begin
counter <= counter + 1;
end
// Hardware Output
assign out_leds[7:0] = controller0_buttons[7:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ans[200005]; vector<vector<pair<long long, long long> > > G(200005); int main() { long long i, j, n, m, a, b, c; priority_queue<pair<long long, long long> > pq; scanf( %lld %lld , &n, &m); for (i = 0; i < m; i++) { scanf( %lld %lld %lld , &a, &b, &c); G[a].push_back({b, c}); G[b].push_back({a, c}); } for (i = 1; i <= n; i++) { scanf( %lld , &ans[i]); pq.push({-ans[i], i}); } while (!pq.empty()) { pair<long long, long long> tp = pq.top(); pq.pop(); tp.first *= -1; if (tp.first > ans[tp.second]) continue; ans[tp.second] = tp.first; for (pair<long long, long long> next : G[tp.second]) { long long poss = next.second * 2 + tp.first; if (poss < ans[next.first]) { pq.push({-poss, next.first}); } } } for (i = 1; i <= n; i++) printf( %lld , ans[i]); printf( n ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5.2e3 + 5; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } char s[MAXN]; bool a[MAXN][MAXN]; int main(void) { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %s , s + 1); for (int j = 1; s[j]; ++j) { if (s[j] >= 0 && s[j] <= 9 ) s[j] -= 0 ; else s[j] = s[j] - A + 10; for (int k = 0; k < 4; ++k) a[i][(j << 2) - k] = (s[j] >> k) & 1; } } int x = 0; for (int i = 1; i <= n && x != 1; ++i) for (int l = 1, r = 1; l <= n && x != 1; l = r) { while (r <= n && a[i][r] == a[i][l]) ++r; x = gcd(x, r - l); } for (int j = 1; j <= n && x != 1; ++j) for (int l = 1, r = 1; l <= n && x != 1; l = r) { while (r <= n && a[r][j] == a[l][j]) ++r; x = gcd(x, r - l); } printf( %d , x); return 0; } |
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave
*******************************************************************************/
module spi_slave_freertos(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'hFF;
else begin
if(byte_received)
cnt<=cnt - 8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'hFF;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= 1'b1;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_BLACKBOX_V
`define SKY130_FD_SC_HDLL__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; using P = pair<int, int>; constexpr int INF = 1 << 30; template <typename Monoid> struct SegmentTree { private: using F = function<Monoid(Monoid, Monoid)>; int N; vector<Monoid> node; F f; Monoid e; public: SegmentTree() {} SegmentTree(F f, Monoid e) : f(f), e(e) {} void init(int sz) { N = 1; while (N < sz) N <<= 1; node.assign(2 * N - 1, e); } void build(vector<Monoid>& v) { int sz = int(v.size()); init(sz); for (int i = 0; i < sz; i++) { node[i + N - 1] = v[i]; } for (int i = N - 2; i >= 0; i--) { node[i] = f(node[i * 2 + 1], node[i * 2 + 2]); } } void update(int k, Monoid x) { k += N - 1; node[k] = x; while (k > 0) { k = (k - 1) / 2; node[k] = f(node[2 * k + 1], node[2 * k + 2]); } } Monoid query(int a, int b) { return query(a, b, 0, 0, N); } Monoid query(int a, int b, int k, int l, int r) { if (b <= l || r <= a) return e; if (a <= l && r <= b) return node[k]; Monoid vl, vr; vl = query(a, b, 2 * k + 1, l, (l + r) / 2); vr = query(a, b, 2 * k + 2, (l + r) / 2, r); return f(vl, vr); } }; SegmentTree<int> seg([](int a, int b) { return max(a, b); }, -INF); vector<vector<int> > g; vector<int> a; int main() { int n; scanf( %d , &n); g.resize(n); a.resize(n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d %d , &u, &v); u--; v--; g[u].push_back(v); g[v].push_back(u); } seg.build(a); int ans = INF; for (int i = 0; i < n; i++) { int maxi = a[i]; g[i].push_back(i); sort(g[i].begin(), g[i].end()); int pre = 0; for (auto j : g[i]) { if (j != i) maxi = max(maxi, a[j] + 1); maxi = max(maxi, seg.query(pre, j) + 2); pre = j + 1; } maxi = max(maxi, seg.query(pre, n) + 2); ans = min(ans, maxi); } printf( %d n , ans); return 0; } |
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file data_mem.v when simulating
// the core, data_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module data_mem(
clka,
wea,
addra,
dina,
douta);
input clka;
input [0 : 0] wea;
input [5 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(6),
.C_ADDRB_WIDTH(6),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("data_mem.mif"),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(64),
.C_READ_DEPTH_B(64),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(64),
.C_WRITE_DEPTH_B(64),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of data_mem is "black_box"
endmodule
|
//-----------------------------------------------------
// Design Name : hw2_B
// File Name : hw2_B.v
// Function : This program designs a Stream Filter.
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
module hw2_B (
input in,
input clk,
input rst_n,
output reg out
);
reg [1:0]state, nextState;
reg nextOut;
parameter S0 = 0;
parameter S1 = 1;
parameter S2 = 2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out <= 0;
state <= 0;
end else begin
state <= nextState;
out <= nextOut;
end // end of if-else block
end // end of always
always @(state or in) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
nextState <= S0;
end else begin // 0 -> 1 => 0
nextState <= S1;
end
end
S1: begin // previous input is 1
if (in == 0) begin // 1 -> 0 => 1
nextState <= S0;
end else begin // 1 -> 1 => 0
nextState <= S2;
end
end
S2: begin
if (in == 0) begin // 1 -> 1 -> 0 => 1
nextState <= S0;
end else begin // 1 -> 1 -> 1 => 1
nextState <= S2;
end
end
endcase
end
always @(state or in) begin
case (state)
S0: begin // previous input is 0
nextOut <= 0;
end
S1: begin // previous input is 1
if (in == 0) begin // 1 -> 0 => 1
nextOut <= 1;
end else begin // 1 -> 1 => 0
nextOut <= 0;
end
end
S2: begin
nextOut <= 1;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
out <= 0;
end else begin
out <= nextOut;
end // end of if-else block
end // end of always
endmodule // endmodule of hw2_B
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; int n, m; int fw[N][N], fb[N][N]; int dx[8] = {-2, -2, 2, 2, 1, 1, -1, -1}; int dy[8] = {1, -1, 1, -1, 2, -2, 2, -2}; queue<pair<int, int> > q; void bfs(int x, int y, int f[][N]) { for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) f[i][j] = -1; f[x][y] = 0; q.push(pair<int, int>(x, y)); while (!q.empty()) { pair<int, int> h = q.front(); q.pop(); int x = h.first, y = h.second; for (int i = 0; i < 8; ++i) { int xx = x + dx[i], yy = y + dy[i]; if (xx <= 0 || xx > n || yy <= 0 || yy > m) continue; if (f[xx][yy] == -1) { f[xx][yy] = f[x][y] + 1; q.push(pair<int, int>(xx, yy)); } } } } void go(int x, int y, int f[][N]) { while (f[x][y]) { for (int i = 0; i < 8; ++i) { int xx = x + dx[i], yy = y + dy[i]; if (xx <= 0 || xx > n || yy <= 0 || yy > m) continue; if (f[xx][yy] != -1 && f[xx][yy] < f[x][y]) { x = xx, y = yy; printf( %d %d n , x, y); fflush(stdout); break; } } } } int main() { int xw, yw, xb, yb, hn, hm; scanf( %d%d , &n, &m); scanf( %d%d%d%d , &xw, &yw, &xb, &yb); hn = n >> 1, hm = m >> 1; bfs(hn, hm, fw); bfs(hn + 1, hm, fb); double tw = fw[xw][yw]; double tb = fb[xb][yb] + 0.5; double twb = fb[xw][yw]; double tbb = fw[xb][yb] + 0.5; if (((xw + yw) & 1) ^ ((xb + yb) & 1)) { if (tw < tb) { puts( WHITE ); go(xw, yw, fw); } else if (twb < tb + 1) { puts( WHITE ); if (fb[xw][yw]) { go(xw, yw, fb); } else { printf( %d %d n , xw - 2, yw - 1); printf( %d %d n , xw, yw); } go(hn + 1, hm, fw); } else { puts( BLACK ); go(xb, yb, fb); } } else { if (tb < tw) { puts( BLACK ); go(xb, yb, fb); } else if (tbb < tw + 1) { puts( BLACK ); if (fw[xb][yb]) { go(xb, yb, fw); } else { printf( %d %d n , xb - 2, yb - 1); printf( %d %d n , xb, yb); } go(hn, hm, fb); } else { puts( WHITE ); go(xw, yw, fw); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:11:43 02/19/2014
// Design Name:
// Module Name: WcaCicInterp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// CIC Interpolator, 3-Stages
module WcaCicInterp
(
input wire clock,
input wire reset,
input wire enable,
input wire strobe_cic,
input wire strobe_if,
input wire [3:0] log2_rate,
input wire [15:0] data_in,
output wire [15:0] data_out
);
//integ2 => #1 integ2 + {{8{integ1[15]}}, integ1}
// Comb (differentiator) registers
reg [24+15:0] comb1;
reg [24+15:0] comb2;
reg [24+15:0] comb3;
// Pipeline registers for combs
reg [24+15:0] pipe1;
reg [24+15:0] pipe2;
reg [24+15:0] pipe3;
// Integrating (accumulator) registers
// Each integrator stage can grow by as much as 8 bits
// assuming a max interpolation rate of 256
reg [24+15:0] integ1;
reg [24+15:0] integ2;
reg [24+ 15:0] integ3;
//***********************************
// Cascading Combs with Pipeline Regs
//***********************************
always @(posedge clock)
if(reset | ~enable)
begin
pipe1 <= #1 0;
pipe2 <= #1 0;
pipe3 <= #1 0;
comb1 <= #1 0;
comb2 <= #1 0;
comb3 <= #1 0;
end
else if (strobe_cic)
begin
comb1 <= #1 data_in;
pipe1 <= #1 data_in - comb1;
comb2 <= #1 pipe1;
pipe2 <= #1 pipe1 - comb2;
comb3 <= #1 pipe2;
pipe3 <= #1 pipe2 - comb3;
end
//***********************************
// Cascading Integrators
//***********************************
reg [15:0] data_store;
always @(posedge clock)
if(reset | ~enable)
begin
integ1 <= #1 0;
integ2 <= #1 0;
integ3 <= #1 0;
end
else if (strobe_if)
begin
integ1 <= #1 integ1 + pipe3;//{{8{pipe3[15]}}, pipe3};
integ2 <= #1 integ2 + integ1;//{{8{integ1[23]}}, integ1};
integ3 <= #1 integ3 + integ2;//{{8{integ2[31]}}, integ2};
// Scale the output by log2 of interpolation rate
case(log2_rate)
4'h1: data_store = integ3[18:3];
4'h2: data_store = integ3[21:6];
4'h3: data_store = integ3[24:9];
4'h4: data_store = integ3[27:12];
4'h5: data_store = integ3[30:15];
4'h6: data_store = integ3[33:18];
4'h7: data_store = integ3[36:21];
4'h8: data_store = integ3[39:24];
default: data_store = integ3[15:0];
endcase
end
// Assign the final value coming out of CIC
assign data_out = data_store;
endmodule
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:28:10 02/03/2015
// Design Name: sha256_core
// Project Name: crypto_sha256
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sha256_core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sha256_core_tb;
// Inputs
reg clk;
reg rst_i;
reg load_i;
reg [511:0] data_i;
reg [255:0] state_i;
reg [255:0] test_val;
// Outputs
wire [255:0] state_o;
wire busy_o;
// Instantiate the Unit Under Test (UUT)
sha256_core uut (
.clk(clk),
//.rst_i(rst_i),
.load_i(load_i),
.data_i(data_i),
.state_i(state_i),
.state_o(state_o),
.busy_o(busy_o)
);
initial begin
// Initialize Inputs
clk = 0;
rst_i = 1;
load_i = 0;
data_i = 0;
state_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst_i = 0;
state_i = {
32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a,
32'h510e527f, 32'h9b05688c, 32'h1f83d9ab, 32'h5be0cd19
};
data_i = {
32'h61626380, 32'h00000000, 32'h00000000, 32'h00000000,
32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000,
32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000,
32'h00000000, 32'h00000000, 32'h00000000, 32'h00000018
};
test_val = {
32'hba7816bf, 32'h8f01cfea, 32'h414140de, 32'h5dae2223,
32'hb00361a3, 32'h96177a9c, 32'hb410ff61, 32'hf20015ad
};
load_i = 1;
while(!busy_o) #1;
load_i = 0;
while(busy_o) #1;
if(test_val != state_o)
begin
$display("test #1 fail");
$stop;
end
$display("sha256_core passed");
$finish;
end
always #10 clk <= ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long int, long long int> > arr; bool fun(pair<long long int, long long int> fi, pair<long long int, long long int> se) { if (fi.first < se.first) { return true; } else return false; } void solve() { long long int i, j, k, l, m, n, x; cin >> n; for (i = 0; i < n; i++) { cin >> x; arr.push_back(make_pair(x, i + 1)); } sort(arr.begin(), arr.end(), fun); if (n <= 3) { cout << 1 << endl; return; } long long int d = arr[1].first - arr[0].first; long long int count = 0; long long int index = arr[0].second; for (i = 0; i < n; i++) { if (arr[i].first != arr[0].first + (i - count) * d) { count++; index = arr[i].second; if (count > 1) { break; } } } if (count <= 1) { cout << index << endl; return; } d = arr[2].first - arr[0].first; count = 1; index = arr[1].second; for (i = 3; i < n; i++) { if (arr[i].first != arr[0].first + (i - count) * d) { count++; index = arr[i].second; if (count > 1) { break; } } } if (count <= 1) { cout << index << endl; return; } d = arr[2].first - arr[1].first; count = 1; index = arr[0].second; for (i = 3; i < n; i++) { if (arr[i].first != arr[1].first + (i - count) * d) { count++; index = arr[i].second; if (count > 1) { break; } } } if (count <= 1) { cout << index << endl; return; } cout << -1 << endl; return; } int main() { long long int t = 1; while (t--) { solve(); } } |
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench axis_mt19937_64
*/
module test_axis_mt19937_64;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] seed_val = 0;
reg seed_start = 0;
reg output_axis_tready = 0;
// Outputs
wire [63:0] output_axis_tdata;
wire output_axis_tvalid;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
seed_val,
seed_start,
output_axis_tready
);
$to_myhdl(
output_axis_tdata,
output_axis_tvalid,
busy
);
// dump file
$dumpfile("test_axis_mt19937_64.lxt");
$dumpvars(0, test_axis_mt19937_64);
end
axis_mt19937_64
UUT (
.clk(clk),
.rst(rst),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
// Configuration
.seed_val(seed_val),
.seed_start(seed_start),
// Status
.busy(busy)
);
endmodule
|
/**
* @module data_to_segment
* @author sabertazimi
* @email
* @brief raw data to segment encoder
* @param DATA_WIDTH data width
* @input data raw decimal data
* @output seg_data bit data for cnodes
*/
module data_to_segment
#(parameter DATA_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
output [(DATA_WIDTH*2)-1:0] seg_data
);
integer_to_segment trans1 (
.int_data(data[3:0]),
.seg_data(seg_data[7:0])
);
integer_to_segment trans2 (
.int_data(data[7:4]),
.seg_data(seg_data[15:8])
);
integer_to_segment trans3 (
.int_data(data[11:8]),
.seg_data(seg_data[23:16])
);
integer_to_segment trans4 (
.int_data(data[15:12]),
.seg_data(seg_data[31:24])
);
integer_to_segment trans5 (
.int_data(data[19:16]),
.seg_data(seg_data[39:32])
);
integer_to_segment trans6 (
.int_data(data[23:20]),
.seg_data(seg_data[47:40])
);
integer_to_segment trans7 (
.int_data(data[27:24]),
.seg_data(seg_data[55:48])
);
integer_to_segment trans8 (
.int_data(data[31:28]),
.seg_data(seg_data[63:56])
);
endmodule
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//The following module effects the IO of the DDC chain.
//By default, this entire module is a simple pass-through.
module dsp_rx_glue
#(
//the dsp unit number: 0, 1, 2...
parameter DSPNO = 0,
//frontend bus width
parameter WIDTH = 24
)
(
//control signals
input clock, input reset, input clear, input enable,
//user settings bus, controlled through user setting regs API
input set_stb, input [7:0] set_addr, input [31:0] set_data,
//full rate inputs directly from the RX frontend
input [WIDTH-1:0] frontend_i,
input [WIDTH-1:0] frontend_q,
//full rate outputs directly to the DDC chain
output [WIDTH-1:0] ddc_in_i,
output [WIDTH-1:0] ddc_in_q,
//strobed samples {I16,Q16} from the RX DDC chain
input [31:0] ddc_out_sample,
input ddc_out_strobe, //high on valid sample
output ddc_out_enable, //enables DDC module
//strobbed baseband samples {I16,Q16} from this module
output [31:0] bb_sample,
output bb_strobe, //high on valid sample
//debug output (optional)
output [31:0] debug
);
generate
if (DSPNO==0) begin
`ifndef RX_DSP0_MODULE
assign ddc_in_i = frontend_i;
assign ddc_in_q = frontend_q;
assign bb_sample = ddc_out_sample;
assign bb_strobe = ddc_out_strobe;
assign ddc_out_enable = enable;
`else
`RX_DSP0_MODULE #(.WIDTH(WIDTH)) rx_dsp0_custom
(
.clock(clock), .reset(reset), .clear(clear), .enable(enable),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.frontend_i(frontend_i), .frontend_q(frontend_q),
.ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
.ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
.bb_sample(bb_sample), .bb_strobe(bb_strobe)
);
`endif
end
else begin
`ifndef RX_DSP1_MODULE
assign ddc_in_i = frontend_i;
assign ddc_in_q = frontend_q;
assign bb_sample = ddc_out_sample;
assign bb_strobe = ddc_out_strobe;
assign ddc_out_enable = enable;
`else
`RX_DSP1_MODULE #(.WIDTH(WIDTH)) rx_dsp1_custom
(
.clock(clock), .reset(reset), .clear(clear), .enable(enable),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.frontend_i(frontend_i), .frontend_q(frontend_q),
.ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
.ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
.bb_sample(bb_sample), .bb_strobe(bb_strobe)
);
`endif
end
endgenerate
endmodule //dsp_rx_glue
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_arbiter_2
*/
module test_wb_arbiter_2;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = (DATA_WIDTH/8);
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm0_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm0_dat_i = 0;
reg wbm0_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm0_sel_i = 0;
reg wbm0_stb_i = 0;
reg wbm0_cyc_i = 0;
reg [ADDR_WIDTH-1:0] wbm1_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm1_dat_i = 0;
reg wbm1_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm1_sel_i = 0;
reg wbm1_stb_i = 0;
reg wbm1_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm0_dat_o;
wire wbm0_ack_o;
wire wbm0_err_o;
wire wbm0_rty_o;
wire [DATA_WIDTH-1:0] wbm1_dat_o;
wire wbm1_ack_o;
wire wbm1_err_o;
wire wbm1_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wbm0_adr_i,
wbm0_dat_i,
wbm0_we_i,
wbm0_sel_i,
wbm0_stb_i,
wbm0_cyc_i,
wbm1_adr_i,
wbm1_dat_i,
wbm1_we_i,
wbm1_sel_i,
wbm1_stb_i,
wbm1_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i
);
$to_myhdl(
wbm0_dat_o,
wbm0_ack_o,
wbm0_err_o,
wbm0_rty_o,
wbm1_dat_o,
wbm1_ack_o,
wbm1_err_o,
wbm1_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o
);
// dump file
$dumpfile("test_wb_arbiter_2.lxt");
$dumpvars(0, test_wb_arbiter_2);
end
wb_arbiter_2 #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
.wbm0_adr_i(wbm0_adr_i),
.wbm0_dat_i(wbm0_dat_i),
.wbm0_dat_o(wbm0_dat_o),
.wbm0_we_i(wbm0_we_i),
.wbm0_sel_i(wbm0_sel_i),
.wbm0_stb_i(wbm0_stb_i),
.wbm0_ack_o(wbm0_ack_o),
.wbm0_err_o(wbm0_err_o),
.wbm0_rty_o(wbm0_rty_o),
.wbm0_cyc_i(wbm0_cyc_i),
.wbm1_adr_i(wbm1_adr_i),
.wbm1_dat_i(wbm1_dat_i),
.wbm1_dat_o(wbm1_dat_o),
.wbm1_we_i(wbm1_we_i),
.wbm1_sel_i(wbm1_sel_i),
.wbm1_stb_i(wbm1_stb_i),
.wbm1_ack_o(wbm1_ack_o),
.wbm1_err_o(wbm1_err_o),
.wbm1_rty_o(wbm1_rty_o),
.wbm1_cyc_i(wbm1_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O2111A_BEHAVIORAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 2005; const long long mod = 1e9 + 7; const long long INF = 1e18 + 1; long long goal, n, m; long long umbrella[N], rain[N], cache[N][N]; pair<long long, long long> a[N], b[N]; long long dp(long long x, long long y) { if (x == goal) return 0; long long &ans = cache[x][y]; if (ans != -1) return ans; ans = INF; if (umbrella[x]) ans = dp(x, x); if (rain[x] and y == goal + 1) return ans; if (rain[x]) { ans = min(ans, umbrella[y] + min(dp(x + 1, y), dp(x + 1, goal + 1))); } else ans = min({ans, dp(x + 1, goal + 1), umbrella[y] + min(dp(x + 1, y), dp(x + 1, goal + 1))}); return ans; } void solve() { memset(cache, -1, sizeof(cache)); cin >> goal >> n >> m; for (long long i = 1; i < n + 1; i++) { cin >> a[i].first >> a[i].second; for (long long j = a[i].first; j < a[i].second; j++) rain[j] = 1; } for (long long i = 1; i < m + 1; i++) { cin >> b[i].first >> b[i].second; if (umbrella[b[i].first] == 0) umbrella[b[i].first] = b[i].second; else umbrella[b[i].first] = min(b[i].second, umbrella[b[i].first]); } sort(a + 1, a + n + 1); sort(b + 1, b + m + 1); if (a[1].first < b[1].first) { cout << -1; return; } cout << dp(0, goal + 1); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, A = 1e5 + 2; bool v[20][20]; long long dp[20][1 << 20]; int n, m, start = 0; long long solve(int node, int mask) { if (~dp[node][mask]) return dp[node][mask]; long long ret = 0; if (v[node][start] && __builtin_popcount(mask) > 2) ret++; for (int i = start + 1; i < n; i++) { if (!(mask >> i & 1) && v[node][i]) ret += solve(i, mask | (1 << i)); } return dp[node][mask] = ret; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--, y--; v[x][y] = v[y][x] = 1; } long long ans = 0; memset(dp, -1, sizeof dp); for (int i = 0; i < n; i++) start = i, ans += solve(i, 1 << i); cout << ans / 2; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, M = 1e6 + 10; struct node { int a, b, w; } e[M]; int fa[N]; bool cmp(node a, node b) { return a.w < b.w; } int find(int x) { if (fa[x] != x) fa[x] = find(fa[x]); return fa[x]; } int du[N]; int main() { int n, m; cin >> n >> m; int a1, b1, w1; for (int i = 1; i <= m; ++i) { scanf( %d%d%d , &e[i].a, &e[i].b, &e[i].w); if (i == 1) { a1 = e[i].a; b1 = e[i].b; } } for (int i = 1; i <= n; ++i) fa[i] = i; sort(e + 2, e + 1 + m, cmp); for (int i = 2; i <= m; ++i) { int f1 = find(e[i].a); int f2 = find(e[i].b); if (f1 == f2) continue; fa[f1] = f2; if (find(a1) == find(b1)) { printf( %d n , e[i].w); return 0; } } printf( 1000000000 n ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLRTP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; vector<int> e[maxn], re[maxn], List; int n, m, id[maxn], tt, cnt[maxn], ans; bool vis[maxn]; void input() { scanf( %d%d , &n, &m); for (int u, v, i = 1; i <= m; i++) { scanf( %d%d , &u, &v); e[u].push_back(v); re[v].push_back(u); } } void dfs(int u) { vis[u] = 1; for (vector<int>::iterator it = e[u].begin(); it != e[u].end(); it++) { if (!vis[*it]) { dfs(*it); } } List.push_back(u); } void rdfs(int u, int k) { id[u] = k; cnt[k]++; for (vector<int>::iterator it = re[u].begin(); it != re[u].end(); it++) { if (!id[*it]) { rdfs(*it, k); } } } void scc() { tt = 0; for (int i = 1; i <= n; i++) if (!vis[i]) dfs(i); reverse(List.begin(), List.end()); for (vector<int>::iterator it = List.begin(); it != List.end(); it++) if (!id[*it]) { tt++; rdfs(*it, tt); } } void bfs(int u) { queue<int> q; while (!q.empty()) q.pop(); q.push(u); vis[u] = 1; int c = 0, x = 0; bool ok = 0; while (!q.empty()) { u = q.front(); q.pop(); if (cnt[id[u]]) { c += cnt[id[u]] - 1; x++; if (cnt[id[u]] > 1) ok = 1; cnt[id[u]] = 0; } for (vector<int>::iterator it = e[u].begin(); it != e[u].end(); it++) { if (!vis[*it]) { vis[*it] = 1; q.push(*it); } } for (vector<int>::iterator it = re[u].begin(); it != re[u].end(); it++) { if (!vis[*it]) { vis[*it] = 1; q.push(*it); } } } ans += c + x - 1; if (ok) ans++; } void solve() { memset(vis, 0, sizeof vis); for (int i = 1; i <= n; i++) if (!vis[i]) { bfs(i); } printf( %d , ans); } int main() { input(); scc(); solve(); } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_switch (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& s, vector<T> t) { for (int i = 0; i < (int)(t.size()); i++) s << (i ? : ) << t[i]; return s; } template <typename T> istream& operator>>(istream& s, vector<T>& t) { for (int i = 0; i < (int)(t.size()); i++) s >> t[i]; return s; } template <typename T, typename U> ostream& operator<<(ostream& s, pair<T, U> t) { s << ( << t.first << , << t.second << ) ; return s; } template <typename T, typename U> istream& operator>>(istream& s, pair<T, U>& t) { s >> t.first >> t.second; return s; } typedef pair<double, double> it; const double EPS = 1e-15; it intersect(it a, it b) { if (a.first == -1 || b.first == -1) return {-1, -1}; it res = {max(a.first, b.first), min(a.second, b.second)}; if (res.first + EPS >= res.second) return {-1, -1}; return res; } it get1D(double r, double v, double x1, double x2) { if (v == 0) { if (r > x1 && r < x2) return {0, 1e18}; else return {-1, -1}; } double t1 = (x1 - r) / v, t2 = (x2 - r) / v; if (t2 < t1) swap(t1, t2); if (t2 < 0) return {-1, -1}; if (t1 < 0) t1 = 0; return {t1, t2}; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; double x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; it res = {0, 1e18}; for (int i = 0; i < (int)(n); i++) { double rx, ry, vx, vy; cin >> rx >> ry >> vx >> vy; it xi = get1D(rx, vx, x1, x2); it yi = get1D(ry, vy, y1, y2); it cur = intersect(xi, yi); res = intersect(res, cur); } cout << fixed << setprecision(9); if (res.first == -1) { cout << -1 << endl; } else { cout << res.first << endl; } } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int MOD = 1e9 + 7; const int MAXN = 1e6 + 3; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } long long power(long long x, long long y) { long long res = 1; while (y > 0) { if (y & 1) res = res * x; y = y >> 1; x = x * x; } return res; } long long n; const int maxn = 1e3 + 3; long long dp1[2 * maxn][2 * maxn]; long long dp2[2 * maxn][2 * maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; n *= 2; dp1[0][0] = 0ll; dp2[0][0] = 1ll; for (long long i = 1; i <= n; i++) { for (long long j = 0; j <= i; j++) { if (j == 0) { dp2[i][j] = (1 + dp1[i - 1][j + 1]) % MOD; dp1[i][j] = max(dp1[i - 1][j + 1], dp2[i - 1][j + 1]); } else if (j == i) { dp2[i][j] = (1 + dp1[i - 1][j - 1]) % MOD; dp1[i][j] = max(dp1[i - 1][j - 1], dp2[i - 1][j - 1]); } else { dp2[i][j] = (1 + dp1[i - 1][j - 1] + dp1[i - 1][j + 1]) % MOD; dp1[i][j] = max(dp1[i - 1][j - 1] + dp2[i - 1][j + 1], dp1[i - 1][j + 1] + dp2[i - 1][j - 1]) % MOD; } } } cout << dp1[n][0] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { float H, L; cin >> H >> L; float x; x = ((L * L) - (H * H)) / (2 * H); printf( %0.6f , x); return 0; } |
/*
*
* Copyright (c) 2011
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 6'd4
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
wire [511:0] W;
wire [255:0] state;
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
reg [511:0] w_buf = 0, w_buf2 = 0;
reg [255:0] state_buf = 0, state_buf2 = 0;
always @ (posedge clk)
begin
w_buf[511:480] <= new_w;
w_buf[479:0] <= rx_w[511:32];
state_buf[`IDX(7)] <= rx_state[`IDX(6)];
state_buf[`IDX(6)] <= rx_state[`IDX(5)];
state_buf[`IDX(5)] <= rx_state[`IDX(4)];
state_buf[`IDX(4)] <= rx_state[`IDX(3)] + t1;
state_buf[`IDX(3)] <= rx_state[`IDX(2)];
state_buf[`IDX(2)] <= rx_state[`IDX(1)];
state_buf[`IDX(1)] <= rx_state[`IDX(0)];
state_buf[`IDX(0)] <= t1 + t2;
{w_buf2, state_buf2} <= {w_buf, state_buf};
{tx_w, tx_state} <= {w_buf2, state_buf2};
end
endmodule
|
#include <bits/stdc++.h> int const MOD = 998244353; int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); int n, nopt; std::cin >> n >> nopt; std::vector<int> h; h.reserve(n + 1); h.resize(n); for (int& hi : h) std::cin >> hi; h.push_back(h[0]); std::vector<int> f{1}; f.reserve(n * 2 + 1); std::vector<int> g; g.reserve(n * 2 + 1); for (int i = 0; i < n; ++i) { if (h[i] == h[i + 1]) { for (auto& fi : f) fi = int(fi * (int64_t)nopt % MOD); f.insert(begin(f), 0); f.push_back(0); } else { g.assign(begin(f), end(f)); g.push_back(0); g.push_back(0); assert(nopt - 2 >= 0); std::transform(begin(f), end(f), ++begin(g), ++begin(g), [nopt](int fi, int gi) { return int((gi + fi * int64_t(nopt - 2)) % MOD); }); std::transform(begin(f), end(f), ++ ++begin(g), ++ ++begin(g), [](int fi, int gi) { return gi + fi >= MOD ? gi + fi - MOD : gi + fi; }); std::swap(f, g); } } std::cout << std::accumulate(begin(f) + n + 1, end(f), 0LL) % MOD << n ; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx2 ) using namespace std; const int MX = 1005; int n, a, b; vector<int> adj[2 * MX][2]; int leaf[MX][2]; int pos[2 * MX][2]; int siz[2 * MX][2]; int best[MX][MX][2]; int ans[MX][2]; pair<int, int> rang[2 * MX][2]; void dfs(int v, int p, int d) { if (pos[v][d] != -1) rang[v][d] = {pos[v][d], pos[v][d]}; siz[v][d] = 1; for (int to : adj[v][d]) { if (to != p) { dfs(to, v, d); siz[v][d] += siz[to][d]; rang[v][d].first = min(rang[v][d].first, rang[to][d].first); rang[v][d].second = max(rang[v][d].second, rang[to][d].second); } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> a; for (int i = 0; i < a; i++) pos[i][0] = -1, rang[i][0] = {1e9, -1e9}; for (int i = 0; i < a - 1; i++) { int p; cin >> p; adj[p - 1][0].push_back(i + 1); } for (int i = 0; i < n; i++) { cin >> leaf[i][0], leaf[i][0]--; pos[leaf[i][0]][0] = i; } cin >> b; for (int i = 0; i < b; i++) pos[i][1] = -1, rang[i][1] = {1e9, -1e9}; for (int i = 0; i < b - 1; i++) { int p; cin >> p; adj[p - 1][1].push_back(i + 1); } for (int i = 0; i < n; i++) { cin >> leaf[i][1], leaf[i][1]--; pos[leaf[i][1]][1] = i; } dfs(0, -1, 0); dfs(0, -1, 1); for (int i = 0; i < a; i++) { auto cur = rang[i][0]; best[cur.first][cur.second][0] = max(best[cur.first][cur.second][0], siz[i][0] - (i == 0)); } for (int i = 0; i < b; i++) { auto cur = rang[i][1]; best[cur.first][cur.second][1] = max(best[cur.first][cur.second][1], siz[i][1] - (i == 0)); } for (int c = 0; c < 2; c++) { for (int len = 2; len < n + 1; len++) { for (int st = 0; st < n; st++) { if (st + len - 1 < n) { int l = st, r = st + len - 1; for (int k = l; k < r + 1; k++) { if (k < r) best[l][r][c] = max(best[l][r][c], best[l][k][c] + best[k + 1][r][c]); } } } } } for (int i = 0; i < n + 1; i++) ans[i][0] = -1e9, ans[i][1] = -1e9; ans[0][0] = 0, ans[0][1] = 0; for (int i = 1; i < n + 1; i++) { for (int j = 0; j < i; j++) { ans[i][0] = max(ans[i][0], ans[j][1] + best[j][i - 1][1]); ans[i][1] = max(ans[i][1], ans[j][0] + best[j][i - 1][0]); } } cout << max(ans[n][0], ans[n][1]) << n ; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The module to implement the core's debug control and relevant CSRs
//
// ===========================================================================
`include "e203_defines.v"
module sirv_debug_csr
#(
parameter PC_SIZE = 32
)(
// The interface with commit stage
input [PC_SIZE-1:0] cmt_dpc,
input cmt_dpc_ena,
input [3-1:0] cmt_dcause,
input cmt_dcause_ena,
input dbg_irq_r,
// The interface with CSR control
input wr_dcsr_ena ,
input wr_dpc_ena ,
input wr_dscratch_ena,
input [32-1:0] wr_csr_nxt ,
output[32-1:0] dcsr_r ,
output[PC_SIZE-1:0] dpc_r ,
output[32-1:0] dscratch_r,
output dbg_mode,
output dbg_halt_r,
output dbg_step_r,
output dbg_ebreakm_r,
output dbg_stopcycle,
input clk,
input rst_n
);
// Implement DPC reg
wire dpc_ena = wr_dpc_ena | cmt_dpc_ena;
wire [PC_SIZE-1:0] dpc_nxt;
assign dpc_nxt[PC_SIZE-1:1] =
cmt_dpc_ena ? cmt_dpc[PC_SIZE-1:1]
: wr_csr_nxt[PC_SIZE-1:1];
assign dpc_nxt[0] = 1'b0;
sirv_gnrl_dfflr #(PC_SIZE) dpc_dfflr (dpc_ena, dpc_nxt, dpc_r, clk, rst_n);
// Implement Dbg Scratch reg
wire dscratch_ena = wr_dscratch_ena;
wire [32-1:0] dscratch_nxt;
assign dscratch_nxt = wr_csr_nxt;
sirv_gnrl_dfflr #(32) dscratch_dfflr (dscratch_ena, dscratch_nxt, dscratch_r, clk, rst_n);
// We dont support the HW Trigger Module yet now
// Implement dcsr reg
//
// The ndreset field
wire ndreset_ena = wr_dcsr_ena & wr_csr_nxt[29];
wire ndreset_nxt;
wire ndreset_r;
assign ndreset_nxt = wr_csr_nxt[29];
sirv_gnrl_dfflr #(1) ndreset_dfflr (ndreset_ena, ndreset_nxt, ndreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The fullreset field
wire fullreset_ena = wr_dcsr_ena & wr_csr_nxt[28];
wire fullreset_nxt;
wire fullreset_r;
assign fullreset_nxt = wr_csr_nxt[28];
sirv_gnrl_dfflr #(1) fullreset_dfflr (fullreset_ena, fullreset_nxt, fullreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The cause field
wire dcause_ena = cmt_dcause_ena;
wire [3-1:0] dcause_r;
wire [3-1:0] dcause_nxt = cmt_dcause;
sirv_gnrl_dfflr #(3) dcause_dfflr (dcause_ena, dcause_nxt, dcause_r, clk, rst_n);
//
// The halt field
wire halt_ena = wr_dcsr_ena;
wire halt_nxt;
wire halt_r;
assign halt_nxt = wr_csr_nxt[3];
sirv_gnrl_dfflr #(1) halt_dfflr (halt_ena, halt_nxt, halt_r, clk, rst_n);
//
// The step field
wire step_ena = wr_dcsr_ena;
wire step_nxt;
wire step_r;
assign step_nxt = wr_csr_nxt[2];
sirv_gnrl_dfflr #(1) step_dfflr (step_ena, step_nxt, step_r, clk, rst_n);
//
// The ebreakm field
wire ebreakm_ena = wr_dcsr_ena;
wire ebreakm_nxt;
wire ebreakm_r;
assign ebreakm_nxt = wr_csr_nxt[15];
sirv_gnrl_dfflr #(1) ebreakm_dfflr (ebreakm_ena, ebreakm_nxt, ebreakm_r, clk, rst_n);
//
// // The stopcycle field
//wire stopcycle_ena = wr_dcsr_ena;
//wire stopcycle_nxt;
//wire stopcycle_r;
//assign stopcycle_nxt = wr_csr_nxt[10];
//sirv_gnrl_dfflr #(1) stopcycle_dfflr (stopcycle_ena, stopcycle_nxt, stopcycle_r, clk, rst_n);
// //
// // The stoptime field
//wire stoptime_ena = wr_dcsr_ena;
//wire stoptime_nxt;
//wire stoptime_r;
//assign stoptime_nxt = wr_csr_nxt[9];
//sirv_gnrl_dfflr #(1) stoptime_dfflr (stoptime_ena, stoptime_nxt, stoptime_r, clk, rst_n);
assign dbg_stopcycle = 1'b1;
assign dcsr_r [31:30] = 2'd1;
assign dcsr_r [29:16] = 14'b0;
assign dcsr_r [15:12] = {4{ebreakm_r}};// we replicated the ebreakm for all ebreakh/s/u
assign dcsr_r [11] = 1'b0;
assign dcsr_r [10] = dbg_stopcycle;// Not writeable this bit is constant
assign dcsr_r [9] = 1'b0;//stoptime_r; Not use this bit same as rocket implmementation
assign dcsr_r [8:6] = dcause_r;
assign dcsr_r [5] = dbg_irq_r;
assign dcsr_r [4] = 1'b0;
assign dcsr_r [3] = halt_r;
assign dcsr_r [2] = step_r;
assign dcsr_r [1:0] = 2'b11;
assign dbg_mode = ~(dcause_r == 3'b0);
assign dbg_halt_r = halt_r;
assign dbg_step_r = step_r;
assign dbg_ebreakm_r = ebreakm_r;
endmodule
|
#include <bits/stdc++.h> int min(int a, int b) { return a > b ? b : a; } int max(int a, int b) { return a < b ? b : a; } int main() { int n, a, b, c, d, i, pos; int sum, next; while (~scanf( %d , &n)) { int ans = 0; for (i = 1; i <= 4; i++) { scanf( %d%d%d%d , &a, &b, &c, &d); a = min(a, b); b = max(a, b); c = min(c, d); d = max(c, d); if (a + c <= n) { ans = 1; pos = i; next = a; } } if (ans) printf( %d %d %d n , pos, next, n - next); else printf( -1 n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int Maxs = 300 * 1000 + 5, Maxn = 300 * 1000 + 5; int n, dp[Maxs]; string s, t; long long ans; vector<pair<int, string> > adj[Maxn]; void kmp() { dp[0] = -1; for (int i = 0; i < t.size(); i++) { int pt = i; while (dp[pt] != -1 && t[dp[pt]] != t[i]) pt = dp[pt]; dp[i + 1] = dp[pt] + 1; } } double now; void dfs(int v, int indt) { for (auto u : adj[v]) { int indt2 = indt; for (int j = 0; j < u.second.size(); ++j) { if (clock() - now == CLOCKS_PER_SEC * 0.990) { cout << ans << endl; exit(0); } if (indt2 == t.size()) ans++, indt2 = dp[indt2]; if (indt2 >= 0 && indt2 < t.size() && u.second[j] == t[indt2]) indt2++; else if (indt2 != 0 && indt2 >= 0) indt2 = dp[indt2], j--; } if (indt2 == t.size()) ans++, indt2 = dp[indt2]; dfs(u.first, indt2); } } int main() { now = clock(); cin >> n; int par; for (int i = 1; i < n; i++) cin >> par >> s, par--, adj[par].push_back(make_pair(i, s)); cin >> s; t = s; kmp(); dfs(0, 0); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long dx[] = {-2, -1, 1, 2, -2, 1, -1, 2}; const long long dy[] = {-1, -2, 2, 1, 1, -2, 2, -1}; const long long Mod = 1e9 + 7; const long long N = 5e5; const long long inf = 1e9 + 1; const long long N_N = 1e2; long long n, m, x, y, cnt; int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> x >> y; cnt = max(cnt, y + x); } cout << max(cnt, m); return 0; } |
`timescale 1ns/10ps
module master_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked,
// interface 'reconfig_to_pll'
input wire [63:0] reconfig_to_pll,
// interface 'reconfig_from_pll'
output wire [63:0] reconfig_from_pll
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.pll_fractional_cout(32),
.pll_dsm_out_sel("1st_order"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("26.600985 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("Cyclone V"),
.pll_subtype("Reconfigurable"),
.m_cnt_hi_div(54),
.m_cnt_lo_div(54),
.n_cnt_hi_div(4),
.n_cnt_lo_div(3),
.m_cnt_bypass_en("false"),
.n_cnt_bypass_en("false"),
.m_cnt_odd_div_duty_en("false"),
.n_cnt_odd_div_duty_en("true"),
.c_cnt_hi_div0(15),
.c_cnt_lo_div0(14),
.c_cnt_prst0(1),
.c_cnt_ph_mux_prst0(0),
.c_cnt_in_src0("ph_mux_clk"),
.c_cnt_bypass_en0("false"),
.c_cnt_odd_div_duty_en0("true"),
.c_cnt_hi_div1(1),
.c_cnt_lo_div1(1),
.c_cnt_prst1(1),
.c_cnt_ph_mux_prst1(0),
.c_cnt_in_src1("ph_mux_clk"),
.c_cnt_bypass_en1("true"),
.c_cnt_odd_div_duty_en1("false"),
.c_cnt_hi_div2(1),
.c_cnt_lo_div2(1),
.c_cnt_prst2(1),
.c_cnt_ph_mux_prst2(0),
.c_cnt_in_src2("ph_mux_clk"),
.c_cnt_bypass_en2("true"),
.c_cnt_odd_div_duty_en2("false"),
.c_cnt_hi_div3(1),
.c_cnt_lo_div3(1),
.c_cnt_prst3(1),
.c_cnt_ph_mux_prst3(0),
.c_cnt_in_src3("ph_mux_clk"),
.c_cnt_bypass_en3("true"),
.c_cnt_odd_div_duty_en3("false"),
.c_cnt_hi_div4(1),
.c_cnt_lo_div4(1),
.c_cnt_prst4(1),
.c_cnt_ph_mux_prst4(0),
.c_cnt_in_src4("ph_mux_clk"),
.c_cnt_bypass_en4("true"),
.c_cnt_odd_div_duty_en4("false"),
.c_cnt_hi_div5(1),
.c_cnt_lo_div5(1),
.c_cnt_prst5(1),
.c_cnt_ph_mux_prst5(0),
.c_cnt_in_src5("ph_mux_clk"),
.c_cnt_bypass_en5("true"),
.c_cnt_odd_div_duty_en5("false"),
.c_cnt_hi_div6(1),
.c_cnt_lo_div6(1),
.c_cnt_prst6(1),
.c_cnt_ph_mux_prst6(0),
.c_cnt_in_src6("ph_mux_clk"),
.c_cnt_bypass_en6("true"),
.c_cnt_odd_div_duty_en6("false"),
.c_cnt_hi_div7(1),
.c_cnt_lo_div7(1),
.c_cnt_prst7(1),
.c_cnt_ph_mux_prst7(0),
.c_cnt_in_src7("ph_mux_clk"),
.c_cnt_bypass_en7("true"),
.c_cnt_odd_div_duty_en7("false"),
.c_cnt_hi_div8(1),
.c_cnt_lo_div8(1),
.c_cnt_prst8(1),
.c_cnt_ph_mux_prst8(0),
.c_cnt_in_src8("ph_mux_clk"),
.c_cnt_bypass_en8("true"),
.c_cnt_odd_div_duty_en8("false"),
.c_cnt_hi_div9(1),
.c_cnt_lo_div9(1),
.c_cnt_prst9(1),
.c_cnt_ph_mux_prst9(0),
.c_cnt_in_src9("ph_mux_clk"),
.c_cnt_bypass_en9("true"),
.c_cnt_odd_div_duty_en9("false"),
.c_cnt_hi_div10(1),
.c_cnt_lo_div10(1),
.c_cnt_prst10(1),
.c_cnt_ph_mux_prst10(0),
.c_cnt_in_src10("ph_mux_clk"),
.c_cnt_bypass_en10("true"),
.c_cnt_odd_div_duty_en10("false"),
.c_cnt_hi_div11(1),
.c_cnt_lo_div11(1),
.c_cnt_prst11(1),
.c_cnt_ph_mux_prst11(0),
.c_cnt_in_src11("ph_mux_clk"),
.c_cnt_bypass_en11("true"),
.c_cnt_odd_div_duty_en11("false"),
.c_cnt_hi_div12(1),
.c_cnt_lo_div12(1),
.c_cnt_prst12(1),
.c_cnt_ph_mux_prst12(0),
.c_cnt_in_src12("ph_mux_clk"),
.c_cnt_bypass_en12("true"),
.c_cnt_odd_div_duty_en12("false"),
.c_cnt_hi_div13(1),
.c_cnt_lo_div13(1),
.c_cnt_prst13(1),
.c_cnt_ph_mux_prst13(0),
.c_cnt_in_src13("ph_mux_clk"),
.c_cnt_bypass_en13("true"),
.c_cnt_odd_div_duty_en13("false"),
.c_cnt_hi_div14(1),
.c_cnt_lo_div14(1),
.c_cnt_prst14(1),
.c_cnt_ph_mux_prst14(0),
.c_cnt_in_src14("ph_mux_clk"),
.c_cnt_bypass_en14("true"),
.c_cnt_odd_div_duty_en14("false"),
.c_cnt_hi_div15(1),
.c_cnt_lo_div15(1),
.c_cnt_prst15(1),
.c_cnt_ph_mux_prst15(0),
.c_cnt_in_src15("ph_mux_clk"),
.c_cnt_bypass_en15("true"),
.c_cnt_odd_div_duty_en15("false"),
.c_cnt_hi_div16(1),
.c_cnt_lo_div16(1),
.c_cnt_prst16(1),
.c_cnt_ph_mux_prst16(0),
.c_cnt_in_src16("ph_mux_clk"),
.c_cnt_bypass_en16("true"),
.c_cnt_odd_div_duty_en16("false"),
.c_cnt_hi_div17(1),
.c_cnt_lo_div17(1),
.c_cnt_prst17(1),
.c_cnt_ph_mux_prst17(0),
.c_cnt_in_src17("ph_mux_clk"),
.c_cnt_bypass_en17("true"),
.c_cnt_odd_div_duty_en17("false"),
.pll_vco_div(1),
.pll_cp_current(20),
.pll_bwctrl(10000),
.pll_output_clk_frequency("771.428571 MHz"),
.pll_fractional_division("1"),
.mimic_fbclk_type("none"),
.pll_fbclk_mux_1("glb"),
.pll_fbclk_mux_2("m_cnt"),
.pll_m_cnt_in_src("ph_mux_clk"),
.pll_slf_rst("false")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.reconfig_to_pll (reconfig_to_pll),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk),
.reconfig_from_pll (reconfig_from_pll)
);
endmodule
|
#include <bits/stdc++.h> int f[10005], c, d, n, m, k; inline int min(int x, int y) { return x < y ? x : y; } int main() { scanf( %d %d %d %d %d , &c, &d, &n, &m, &k); if (n * m <= k) { puts( 0 ); return 0; } memset(f, 0x3f, sizeof(f)); f[0] = 0; for (int i = 1; i <= n * m; ++i) { if (i >= n) f[i] = f[i - n] + c; f[i] = min(f[i], f[i - 1] + d); } int ans = 0x3f3f3f3f; for (int i = n * m - k; i <= n * m; ++i) if (f[i] < ans) ans = f[i]; printf( %d n , ans); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/10/30 12:54:50 mohor
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
`include "timescale.v"
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
);
parameter Tp = 1;
input MTxClk;
input Reset;
input ExcessiveDefer;
input CarrierSense;
input [6:0] NibCnt;
input [6:0] IPGT;
input [6:0] IPGR1;
input [6:0] IPGR2;
input FullD;
input TxStartFrm;
input TxEndFrm;
input TxUnderRun;
input Collision;
input UnderRun;
input StartTxDone;
input TooBig;
input NibCntEq7;
input NibCntEq15;
input MaxFrame;
input Pad;
input CrcEn;
input NibbleMinFl;
input RandomEq0;
input ColWindow;
input RetryMax;
input NoBckof;
input RandomEqByteCnt;
output StateIdle; // Idle state
output StateIPG; // IPG state
output StatePreamble; // Preamble state
output [1:0] StateData; // Data state
output StatePAD; // PAD state
output StateFCS; // FCS state
output StateJam; // Jam state
output StateJam_q; // Delayed Jam state
output StateBackOff; // Backoff state
output StateDefer; // Defer state
output StartFCS; // FCS state will be activated in next clock
output StartJam; // Jam state will be activated in next clock
output StartBackoff; // Backoff state will be activated in next clock
output StartDefer; // Defer state will be activated in next clock
output DeferIndication;
output StartPreamble; // Preamble state will be activated in next clock
output [1:0] StartData; // Data state will be activated in next clock
output StartIPG; // IPG state will be activated in next clock
wire StartIdle; // Idle state will be activated in next clock
wire StartPAD; // PAD state will be activated in next clock
reg StateIdle;
reg StateIPG;
reg StatePreamble;
reg [1:0] StateData;
reg StatePAD;
reg StateFCS;
reg StateJam;
reg StateJam_q;
reg StateBackOff;
reg StateDefer;
reg Rule1;
// Defining the next state
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
| ~Collision & StatePAD & NibbleMinFl & CrcEn;
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
| StateIdle & CarrierSense
| StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
| StateBackOff & (TxUnderRun | RandomEqByteCnt)
| StartTxDone | TooBig;
assign DeferIndication = StateIdle & CarrierSense;
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
StateIPG <= #Tp 1'b0;
StateIdle <= #Tp 1'b0;
StatePreamble <= #Tp 1'b0;
StateData[1:0] <= #Tp 2'b0;
StatePAD <= #Tp 1'b0;
StateFCS <= #Tp 1'b0;
StateJam <= #Tp 1'b0;
StateJam_q <= #Tp 1'b0;
StateBackOff <= #Tp 1'b0;
StateDefer <= #Tp 1'b1;
end
else
begin
StateData[1:0] <= #Tp StartData[1:0];
StateJam_q <= #Tp StateJam;
if(StartDefer | StartIdle)
StateIPG <= #Tp 1'b0;
else
if(StartIPG)
StateIPG <= #Tp 1'b1;
if(StartDefer | StartPreamble)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartData[0] | StartJam)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartFCS | StartJam)
StatePAD <= #Tp 1'b0;
else
if(StartPAD)
StatePAD <= #Tp 1'b1;
if(StartJam | StartDefer)
StateFCS <= #Tp 1'b0;
else
if(StartFCS)
StateFCS <= #Tp 1'b1;
if(StartBackoff | StartDefer)
StateJam <= #Tp 1'b0;
else
if(StartJam)
StateJam <= #Tp 1'b1;
if(StartDefer)
StateBackOff <= #Tp 1'b0;
else
if(StartBackoff)
StateBackOff <= #Tp 1'b1;
if(StartIPG)
StateDefer <= #Tp 1'b0;
else
if(StartDefer)
StateDefer <= #Tp 1'b1;
end
end
// This sections defines which interpack gap rule to use
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Rule1 <= #Tp 1'b0;
else
begin
if(StateIdle | StateBackOff)
Rule1 <= #Tp 1'b0;
else
if(StatePreamble | FullD)
Rule1 <= #Tp 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> bool is_prime(int n) { if (n < 2) { return false; } for (int d = 2; d * d <= n; d++) { if (n % d == 0) { return false; } } return true; } int main() { int n; std::cin >> n; int m = n, cross = 0; while (!is_prime(m + cross)) { cross++; } assert(2 * cross <= n); std::cout << m + cross << std::endl; for (int i = 1; i <= n; i++) { std::cout << i << << i % n + 1 << std::endl; } int jump = std::max(2, cross); for (int i = 1; i <= cross; i++) { assert(i < 1 + jump); assert(i + jump <= n); std::cout << i << << i + jump << std::endl; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_rp/bg_rp_stub.v
// Design : bg_rp
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bg_rp(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[7:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [7:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int l = s.length(); if ((s[l - 1] - 48) % 2 == 0) { int temp = s[l - 2] * 10 + s[l - 1]; if (temp % 4 == 0) { cout << 4 << endl; } else { cout << 0 << endl; } } else { cout << 0 << endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:18:20 PM
// Design Name:
// Module Name: Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_Array
#(parameter SWR=26, parameter EWR=5)
(
input wire clk,
input wire rst,
input wire load_i,
input wire [EWR-1:0] Shift_Value_i,
input wire [SWR-1:0] Data_i,
input wire FSM_left_right_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
////
wire [SWR-1:0] Data_array[EWR+1:0];
//////////////////7
genvar k;//Level
///////////////////77777
Rotate_Mux_Array #(.SWR(SWR)) first_rotate(
.Data_i(Data_i),
.select_i(FSM_left_right_i),
.Data_o(Data_array [0][SWR-1:0])
);
generate for (k=0; k < 3; k=k+1) begin
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array[k]),
.select_i(Shift_Value_i[k]),
.bit_shift_i(bit_shift_i),
.Data_o(Data_array[k+1])
);
end
endgenerate
RegisterAdd #(.W(SWR)) Mid_Reg(
.clk(clk),
.rst(rst),
.load(1'b1),
.D(Data_array[3]),
.Q(Data_array[4])
);
generate for (k=3; k < EWR; k=k+1) begin
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array[k+1]),
.select_i(Shift_Value_i[k]),
.bit_shift_i(bit_shift_i),
.Data_o(Data_array[k+2])
);
end
endgenerate
Rotate_Mux_Array #(.SWR(SWR)) last_rotate(
.Data_i(Data_array[EWR+1]),
.select_i(FSM_left_right_i),
.Data_o(Data_o)
);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Framebuffer FML 4x64 interface */
output [fml_depth-1:0] fml_adr,
output fml_stb,
input fml_ack,
input [63:0] fml_di,
/* Direct Cache Bus */
output dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
/* VGA pixel clock */
input vga_clk,
/* VGA signal pads */
output vga_psave_n,
output reg vga_hsync_n,
output reg vga_vsync_n,
output vga_sync_n,
output vga_blank_n,
output reg [7:0] vga_r,
output reg [7:0] vga_g,
output reg [7:0] vga_b,
output [1:0] vga_clk_sel
);
/*
* Control interface
*/
wire vga_rst;
wire [10:0] hres;
wire [10:0] hsync_start;
wire [10:0] hsync_end;
wire [10:0] hscan;
wire [10:0] vres;
wire [10:0] vsync_start;
wire [10:0] vsync_end;
wire [10:0] vscan;
wire [fml_depth-1:0] baseaddress;
wire baseaddress_ack;
wire [17:0] nbursts;
vgafb_ctlif #(
.csr_addr(csr_addr),
.fml_depth(fml_depth)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.vga_rst(vga_rst),
.hres(hres),
.hsync_start(hsync_start),
.hsync_end(hsync_end),
.hscan(hscan),
.vres(vres),
.vsync_start(vsync_start),
.vsync_end(vsync_end),
.vscan(vscan),
.baseaddress(baseaddress),
.baseaddress_ack(baseaddress_ack),
.nbursts(nbursts),
.vga_clk_sel(vga_clk_sel)
);
/*
* Generate signal data
*/
reg hsync_n;
reg vsync_n;
wire pixel_valid;
wire [15:0] pixel_fb;
wire pixel_ack;
wire [15:0] pixel;
wire fifo_full;
reg hactive;
reg vactive;
wire active = hactive & vactive;
assign pixel = active ? pixel_fb : 16'h0000;
wire generate_en;
reg [10:0] hcounter;
reg [10:0] vcounter;
always @(posedge sys_clk) begin
if(vga_rst) begin
hcounter <= 10'd0;
vcounter <= 10'd0;
hactive <= 1'b0;
hsync_n <= 1'b1;
vactive <= 1'b0;
vsync_n <= 1'b1;
end else begin
if(generate_en) begin
hcounter <= hcounter + 10'd1;
if(hcounter == 10'd0) hactive <= 1'b1;
if(hcounter == hres) hactive <= 1'b0;
if(hcounter == hsync_start) hsync_n <= 1'b0;
if(hcounter == hsync_end) hsync_n <= 1'b1;
if(hcounter == hscan) begin
hcounter <= 10'd0;
if(vcounter == vscan)
vcounter <= 10'd0;
else
vcounter <= vcounter + 10'd1;
end
if(vcounter == 10'd0) vactive <= 1'b1;
if(vcounter == vres) vactive <= 1'b0;
if(vcounter == vsync_start) vsync_n <= 1'b0;
if(vcounter == vsync_end) vsync_n <= 1'b1;
end
end
end
assign generate_en = ~fifo_full & (~active | pixel_valid);
assign pixel_ack = ~fifo_full & active & pixel_valid;
vgafb_pixelfeed #(
.fml_depth(fml_depth)
) pixelfeed (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.vga_rst(vga_rst),
.nbursts(nbursts),
.baseaddress(baseaddress),
.baseaddress_ack(baseaddress_ack),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_di(fml_di),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit),
.pixel_valid(pixel_valid),
.pixel(pixel_fb),
.pixel_ack(pixel_ack)
);
/*
* System clock to VGA clock domain crossing is
* acheived by an asynchronous FIFO.
*
* Bits 0-15 are RGB565 pixel data
* Bit 16 is negated Horizontal Sync
* Bit 17 is negated Verical Sync
*/
wire [17:0] fifo_do;
vgafb_asfifo #(
.DATA_WIDTH(18),
.ADDRESS_WIDTH(6)
) fifo (
.Data_out(fifo_do),
.Empty_out(),
.ReadEn_in(1'b1),
.RClk(vga_clk),
.Data_in({vsync_n, hsync_n, pixel}),
.Full_out(fifo_full),
.WriteEn_in(generate_en),
.WClk(sys_clk),
.Clear_in(vga_rst)
);
/*
* Drive the VGA pads.
* RGB565 -> RGB888 color space conversion is also performed here
* by bit shifting and replicating the most significant bits of
* the input into the least significant bits of the output left
* undefined by the shifting.
*/
assign vga_sync_n = 1'b0; /* Sync-on-Green is not implemented */
assign vga_psave_n = 1'b1;
assign vga_blank_n = 1'b1;
always @(posedge vga_clk) begin
vga_vsync_n <= fifo_do[17];
vga_hsync_n <= fifo_do[16];
vga_r <= {fifo_do[15:11], fifo_do[15:13]};
vga_g <= {fifo_do[10:5], fifo_do[10:9]};
vga_b <= {fifo_do[4:0], fifo_do[4:2]};
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_width (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 1;
parameter max_cks = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WIDTH";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if ((max_cks > 0) && (min_cks > max_cks)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal parameter values set where min_cks > max_cks");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_width_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_width_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_width_psl_logic.v"
`else
`endmodule // ovl_width
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int p1 = 0, q1 = 0, r1 = 0, s1 = 0; int ans = 1; int a = 0, b = 0, c = 0, d = 0; vector<int> v; int sum = 0; for (int j = 0; j < s.length(); j++) { if (s[j] == R ) { if ((q1 > 0)) { ans++; v.push_back(j); q1 = 0; r1 = 0; s1 = 0; } p1++; } if (s[j] == L ) { if ((p1 > 0)) { ans++; v.push_back(j); p1 = 0; r1 = 0; s1 = 0; } q1++; } if (s[j] == U ) { if (s1 > 0) { ans++; v.push_back(j); q1 = 0; p1 = 0; s1 = 0; } r1++; } if (s[j] == D ) { if ((r1 > 0)) { ans++; v.push_back(j); q1 = 0; r1 = 0; p1 = 0; } s1++; } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)(1e2 + 5); int n, m, k; int grid[N][N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m >> k; for (int(i) = (1); (i) <= (n); (i)++) for (int(j) = (1); (j) <= (m); (j)++) cin >> grid[i][j]; int score = 0, updates = 0; for (int(j) = (1); (j) <= (m); (j)++) { int col_score = 0; int col_update = 0; int update = 0; for (int(i) = (1); (i) <= (n); (i)++) { if (i - 1 >= 1) update += grid[i - 1][j]; if (grid[i][j] == 1) { int temp_score = 0; for (int q = i; q < i + k && q <= n; q++) temp_score += grid[q][j]; if (temp_score > col_score) { col_score = temp_score; col_update = update; } } } score += col_score; updates += col_update; } cout << score << << updates; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; using namespace std; string s; long long ispalindroma[2005][2005]; long long ispalindrome(long long i, long long j) { if (i > j) return (1); if (i == j) return (1); if (ispalindroma[i][j] != -1) return (ispalindroma[i][j]); long long ans = 0; if (s[i] == s[j]) { ans = ispalindrome(i + 1, j - 1); } return (ispalindroma[i][j] = ans); } int solve() { cin >> s; long long sum[2005], dp[2005]; dp[0] = sum[0] = 0; for (long long i = 0; i < 2005; i++) { for (long long j = 0; j < 2005; j++) ispalindroma[i][j] = -1; } long long a1 = ispalindrome(0, s.size() - 1); for (long long i = 0; i < s.size(); i++) { long long c = 0; for (long long j = 0; j <= i; j++) { if (ispalindrome(j, i)) c++; } sum[i + 1] = sum[i] + c; } for (long long i = 0; i < s.size(); i++) { long long ans = 0; for (long long j = 0; j <= i; j++) { if (ispalindrome(j, i)) ans = ans + sum[j]; } dp[i + 1] = dp[i] + ans; } cout << dp[s.size()] << n ; return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e17 + 10; const int N = 1e6 + 10; const long long mod = 998244353; map<string, int> ml; long long b[N], vis[N], po[N], num[N], t, n, m, x, y, k, a[N]; long long ex, ey, cnt, ans, sum, flag; long long dist[N]; long long dp[N]; vector<int> v[N]; map<int, int> mp; priority_queue<pair<int, int> > q; priority_queue<pair<int, int> > tq; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; string s; cin >> s; for (int i = 0; s[i]; i++) { a[i] = cnt; if (s[i] == ( ) cnt++; else cnt--; if (a[i - 1] < 0) a[i] = -1; } cnt = 0; for (int i = n - 1; i >= 0; i--) { b[i] = cnt; if (s[i] == ) ) cnt++; else cnt--; if (b[i + 1] < 0) b[i] = -1; } for (int i = 0; s[i]; i++) { if (a[i] < 0 && b[i] < 0) return cout << 0 << endl, 0; num[i] = a[i] - b[i]; if (s[i] == ( && num[i] == 1 && a[i] >= 0 && b[i] >= 0) ans++; if (s[i] == ) && num[i] == -1 && a[i] >= 0 && b[i] >= 0) ans++; } cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_1_V
`define SKY130_FD_SC_LP__DLRBP_1_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_1_V
|
#include <bits/stdc++.h> using namespace std; int p[300002], pi; bool tag[300002]; int main() { int n, x; long long cnt; while (scanf( %d , &n) != EOF) { memset(tag, false, sizeof(tag)); pi = 0; for (int i = 0; i < n; i++) { scanf( %d , &x); if (x < 1 || x > n || tag[x]) p[pi++] = x; else tag[x] = true; } sort(p, p + pi); cnt = 0; for (int i = 0, j = 1; i < pi; i++, j++) { while (tag[j]) j++; cnt += (long long)abs(p[i] - j); } printf( %I64d n , cnt); } return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long l, r; cin >> l >> r; long long ans = 0; for (long long i = 1; i <= r; i *= 2) { long long cur = i; while (cur <= r) { if (cur >= l) ans++; cur *= 3; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i, x, t; char card, ha; map<int, pair<int, int> > mh; map<int, pair<int, int> > ma; map<int, pair<int, int> >::iterator it; string h, a; cin >> h >> a; cin >> n; for (i = 0; i < n; i++) { cin >> t >> ha; getchar(); cin >> x >> card; getchar(); if (ha == a ) { for (it = ma.begin(); it != ma.end(); it++) { if ((it->second).first == x) break; } if (it == ma.end() && card == y ) ma[t] = make_pair(x, 1); else if (it == ma.end() && card == r ) ma[t] = make_pair(x, 2); else if (it != ma.end() && (it->second).second == 1) { ma[t] = make_pair(x, 2); ma.erase(it); } } if (ha == h ) { for (it = mh.begin(); it != mh.end(); it++) { if ((it->second).first == x) break; } if (it == mh.end() && card == y ) mh[t] = make_pair(x, 1); else if (it == mh.end() && card == r ) mh[t] = make_pair(x, 2); else if (it != ma.end() && (it->second).second == 1) { mh[t] = make_pair(x, 2); mh.erase(it); } } } for (i = 0; i <= 90; i++) { if (ma[i].second == 2) cout << a << << ma[i].first << << i << endl; if (mh[i].second == 2) cout << h << << mh[i].first << << i << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, x, y; long int v[1001]; long int ans; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { scanf( %ld , &v[i]); } for (int i = 0; i < m; i++) { scanf( %d%d , &x, &y); if (v[x] > v[y]) ans += v[y]; else ans += v[x]; } cout << ans; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:04:36 05/24/2015
// Design Name:
// Module Name: binary_to_BCD_eight_bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: implements the standard shift and add 3 algorithm
//
//////////////////////////////////////////////////////////////////////////////////
module binary_to_BCD_eight_bit(
input [7:0] in,
output [3:0] ones,
output [3:0] tens,
output [1:0] hundreds
);
wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,in[7:5]};
assign d2 = {c1[2:0],in[4]};
assign d3 = {c2[2:0],in[3]};
assign d4 = {1'b0,c1[3],c2[3],c3[3]};
assign d5 = {c3[2:0],in[2]};
assign d6 = {c4[2:0],c5[3]};
assign d7 = {c5[2:0],in[1]};
add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);
assign ones = {c7[2:0],in[0]};
assign tens = {c6[2:0],c7[3]};
assign hundreds = {c4[3],c6[3]};
endmodule
|
#include <bits/stdc++.h> const double eps = 1e-9; const double PI = acos(-1); const long long MOD = 1e9 + 7; using namespace std; vector<string> powers; pair<string, string> solution(string s) { string order; reverse(s.begin(), s.end()); map<char, int> mp; for (char c : s) { if (!mp[c]) { order.push_back(c); } mp[c]++; } int m = order.length(); int original_size = 0; for (int i = 0; i < m; i++) { original_size += mp[order[i]] / (m - i); } reverse(order.begin(), order.end()); return {string(s.rbegin(), s.rbegin() + original_size), order}; } string check(pair<string, string> p) { string result = p.first; for (auto c : p.second) { string tmp; for (auto d : p.first) { if (d != c) { tmp.push_back(d); result.push_back(d); } } p.first = tmp; } return result; } void solve() { string s; cin >> s; auto it = solution(s); auto res = check(it); if (res == s) { cout << it.first << << it.second << endl; } else { cout << -1 << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); for (long long i = 1; i <= 2e18; i *= 2) { powers.push_back(to_string(i)); } long long t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, q; cin >> n >> q; set<int> s; multiset<int> d; auto Add = [&](int x) { auto ret = s.insert(x); auto it = ret.first; if (next(it) != s.end() && it != s.begin()) { d.erase(d.find(*next(it) - *prev(it))); } if (it != s.begin()) { d.insert(*it - *prev(it)); } if (next(it) != s.end()) { d.insert(*next(it) - *it); } }; auto Remove = [&](int x) { auto it = s.find(x); if (it != s.begin()) { d.erase(d.find(*it - *prev(it))); } if (next(it) != s.end()) { d.erase(d.find(*next(it) - *it)); } if (next(it) != s.end() && it != s.begin()) { d.insert(*next(it) - *prev(it)); } s.erase(it); }; for (int i = 0; i < n; i++) { int foo; cin >> foo; Add(foo); } for (int i = 0; i <= q; i++) { if (d.empty()) { cout << 0 << n ; } else { cout << *prev(s.end()) - *s.begin() - *prev(d.end()) << n ; } if (i == q) { break; } int c, x; cin >> c >> x; if (c) { Add(x); } else { Remove(x); } } return 0; } |
`timescale 1 ps / 1 ps
// lib IP_Integrator_Lib
module zc702_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
zc702 zc702_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
#include <bits/stdc++.h> #define f(c,a,b) for(int c=a; c<=b; c++) #define N 5000010 #define pii pair<int,int> #define mp make_pair #define fi first #define se second #define sl (u<<1) #define sr ((u<<1)+1) #define pb push_back using namespace std; typedef double db; typedef long long ll; struct node{ int u,v,x; bool operator < (const node& a) const{ return x<a.x; } }b[N]; int k[N]; bool ask(int i,int j){ cout<< ? <<i<< <<j<<endl; string ans; cin>>ans; if(ans== Yes ) return true; else return false; } int main(){ // freopen( owo.in , r ,stdin); // ios::sync_with_stdio(false); // cin.tie(nullptr); int n; cin >> n; f(i,1,n) cin>>k[i]; int id=0; f(i,1,n){ f(j,i+1,n){ b[++id] = (node){ i,j,abs(k[i]-k[j]) }; } } sort(b+1,b+id+1); for(int i=id; i>=1; i--) { int ti=b[i].u, tj=b[i].v; if(k[ti]>k[tj]) { if(ask(ti,tj)){ cout<< ! <<ti<< <<tj<<endl; return 0; } }else{ if(ask(tj,ti)){ cout<< ! <<ti<< <<tj<<endl; return 0; } } } cout<< ! <<0<< <<0<<endl; return 0; } |
//======================================================================
//
// tb_mkmif_spi.v
// --------------
// Testbench for the mkmif SPI module.
//
//
// Copyright (c) 2016, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_mkmif_spi();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] test_ctr;
reg [31 : 0] error_ctr;
reg tb_clk;
reg tb_reset_n;
wire tb_spi_sclk;
wire tb_spi_cs_n;
reg tb_spi_do;
wire tb_spi_di;
reg tb_set;
reg tb_start;
reg [2 : 0] tb_length;
reg [15 : 0] tb_divisor;
wire tb_ready;
reg [55 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
reg tb_dump_state;
//----------------------------------------------------------------
// mkmif device under test.
//----------------------------------------------------------------
mkmif_spi dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.spi_sclk(tb_spi_sclk),
.spi_cs_n(tb_spi_cs_n),
.spi_do(tb_spi_di),
.spi_di(tb_spi_di),
.set(tb_set),
.start(tb_start),
.length(tb_length),
.divisor(tb_divisor),
.ready(tb_ready),
.wr_data(tb_write_data),
.rd_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
// Monitor for observing the inputs and outputs to the dut.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
end // dut_monitor
//----------------------------------------------------------------
// inc_test_ctr
//----------------------------------------------------------------
task inc_test_ctr;
begin
test_ctr = test_ctr +1;
end
endtask // inc_test_ctr
//----------------------------------------------------------------
// inc_error_ctr
//----------------------------------------------------------------
task inc_error_ctr;
begin
error_ctr = error_ctr +1;
end
endtask // inc_error_ctr
//----------------------------------------------------------------
// dump_ports
// Dump the status of the dut ports.
//----------------------------------------------------------------
task dump_ports;
begin
$display("");
end
endtask // dump_ports
//----------------------------------------------------------------
// dump_state
// Dump the internal MKMIF state to std out.
//----------------------------------------------------------------
task dump_state;
begin
$display("Dut state:");
$display("data_reg: 0x%014x", dut.data_reg);
$display("clk_ctr: 0x%08x", dut.clk_ctr_reg);
$display("bit_ctr: 0x%02x", dut.bit_ctr_reg);
$display("ctrl: 0x%02x, done: 0x%01x, ready: 0x%01x",
dut.spi_ctrl_reg, dut.bit_ctr_done, tb_ready);
$display("Output:");
$display("en: 0x%01x, sclk: 0x%01x, di: 0x%01x, do: 0x%01x",
tb_spi_cs_n, tb_spi_sclk, tb_spi_di, tb_spi_di);
$display("read data: 0x%08x", tb_read_data);
$display("");
end
endtask // dump_state
//----------------------------------------------------------------
// wait_ready()
//
// Wait for ready word to be set in the DUT API.
//----------------------------------------------------------------
task wait_ready;
reg ready;
begin
ready = 0;
while (tb_ready == 0)
begin
#(CLK_PERIOD);
dump_state();
end
end
endtask // read_word
//----------------------------------------------------------------
// tb_init
// Initialize varibles, dut inputs at start.
//----------------------------------------------------------------
task tb_init;
begin
test_ctr = 0;
error_ctr = 0;
cycle_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_spi_do = 0;
tb_set = 0;
tb_start = 0;
tb_length = 3'h7;
tb_divisor = 16'h0008;
tb_write_data = 32'haa55aa55;
tb_dump_state = 0;
end
endtask // tb_init
//----------------------------------------------------------------
// toggle_reset
// Toggle the reset.
//----------------------------------------------------------------
task toggle_reset;
begin
$display(" -- Toggling reset.");
dump_state();
#(2 * CLK_PERIOD);
tb_reset_n = 0;
#(10 * CLK_PERIOD);
@(negedge tb_clk)
tb_reset_n = 1;
dump_state();
$display(" -- Toggling of reset done.");
end
endtask // toggle_reset
//----------------------------------------------------------------
// transmit_data
// Test case for testing that the dut will transmit data
// on the interface.
//----------------------------------------------------------------
task transmit_data;
begin
$display(" -- Trying to transmit data.");
tb_set = 1;
tb_write_data = 56'hdeadbeeff18244;
#(2 * CLK_PERIOD);
$display("Contents of data reg in dut after set: 0x%14x",
dut.data_reg);
#(2 * CLK_PERIOD);
tb_divisor = 16'h8;
tb_length = 3'h4;
tb_start = 1;
#(2 * CLK_PERIOD);
tb_start = 0;
wait_ready();
$display(" -- Transmit data test done..");
end
endtask // transmit_data
//----------------------------------------------------------------
// mkmif_spi_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : mkmif_spi_test
$display(" -- Test of mkmif spi started --");
tb_init();
toggle_reset();
transmit_data();
$display("");
$display(" -- Test of mkmif spi completed --");
$display("Tests executed: %04d", test_ctr);
$display("Tests failed: %04d", error_ctr);
$finish;
end // mkmif_spi_test
endmodule // tb_mkmif_spi
//======================================================================
// EOF tb_mkmif_spi.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DLCLKP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long MOD(long long, long long); void doublesetprecision(double, int); bool isEven(long long); int gcd(int, int); int n, m, o, ans, k; int a[1000000]; void solve() { string s, t; cin >> s >> t; if (s == t) { cout << yes ; return; } if (s.size() != t.size()) { cout << no ; return; } int hs[26] = {0}, ht[26] = {0}; for (long long i = 0; i < s.size(); i++) hs[s[i] - a ]++; for (long long i = 0; i < t.size(); i++) ht[t[i] - a ]++; for (long long i = 0; i < 26; i++) { if (ht[i] > 0 && hs[i] > 0) { cout << yes ; return; } } cout << no ; } int main() { int t = 1; scanf( %d , &t); while (t--) { solve(); cout << n ; } return 0; } bool isEven(long long n) { if (n % 2 == 0) return 1; return 0; } void doublesetprecision(double x, int p) { cout << fixed << setprecision(p) << x; } long long MOD(long long x, long long M) { x = x % M; if (x < 0) x += M; return x; } int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } |
//move some stuff to minitests/ncy0
`define SEED 32'h12345678
module top(input clk, stb, di, output do);
localparam integer DIN_N = 42;
localparam integer DOUT_N = 79;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N))
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
parameter integer DIN_N = -1;
parameter integer DOUT_N = -1;
picorv32 picorv32 (
.clk(clk),
.resetn(din[0]),
.mem_valid(dout[0]),
.mem_instr(dout[1]),
.mem_ready(din[1]),
.mem_addr(dout[33:2]),
.mem_wdata(dout[66:34]),
.mem_wstrb(dout[70:67]),
.mem_rdata(din[33:2])
);
randluts randluts (
.din(din[41:34]),
.dout(dout[78:71])
);
endmodule
module randluts(input [7:0] din, output [7:0] dout);
localparam integer N = 250;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos2_term_dn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_cmos2_term_dn (
vddo, out
);
inout out;
input vddo;
endmodule
|
// DESCRIPTION: Verilator: Verilog example module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// ======================================================================
// This is intended to be a complex example of several features, please also
// see the simpler examples/make_hello_c.
module top
(
// Declare some signals so we can see how I/O works
input clk,
input reset_l,
output wire [1:0] out_small,
output wire [39:0] out_quad,
output wire [69:0] out_wide,
input [1:0] in_small,
input [39:0] in_quad,
input [69:0] in_wide
);
// Connect up the outputs, using some trivial logic
assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
// And an example sub module. The submodule will print stuff.
sub sub (/*AUTOINST*/
// Inputs
.clk (clk),
.reset_l (reset_l));
// Print some stuff as an example
initial begin
if ($test$plusargs("trace") != 0) begin
$display("[%0t] Tracing to logs/vlt_dump.vcd...\n", $time);
$dumpfile("logs/vlt_dump.vcd");
$dumpvars();
end
$display("[%0t] Model running...\n", $time);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int cnt = 1, T[N * 31][2], n; long long t, a[N * 31]; void insert(long long x) { int u = 0; for (int i = 30; i >= 0; i--) { int v = (x >> i) & 1; if (!T[u][v]) { memset(T[cnt], 0, sizeof(T[cnt])); a[cnt] = 0; T[u][v] = cnt++; } u = T[u][v]; } a[u] = x; } long long dfs(int p, int k) { if (!T[p][0] && !T[p][1]) return 0; if (!T[p][0]) return dfs(T[p][1], k - 1); if (!T[p][1]) return dfs(T[p][0], k - 1); return (1LL << k) + min(dfs(T[p][0], k - 1), dfs(T[p][1], k - 1)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld , &t); insert(t); } printf( %lld n , dfs(0, 30)); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9 + 7; template <class X, class Y> void minimize(X &x, const Y &y) { if (x > y) x = y; } template <class X, class Y> void maximize(X &x, const Y &y) { if (x < y) x = y; } vector<int> adj[5050]; int nLeaf[5050]; int f[5050][5050][2]; int tmp[5050][2]; int n; void loadTree(void) { scanf( %d , &n); for (int love = 0, _n = (n - 1); love < _n; love = love + 1) { int u, v; scanf( %d%d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } if (n == 2) { printf( 1 n ); exit(0); } memset(f, 0x3f, sizeof f); } void dfs(int u, int p) { bool leaf = true; for (__typeof((adj[u]).begin()) it = (adj[u]).begin(); it != (adj[u]).end(); it++) if (*it != p) { int v = *it; dfs(v, u); leaf = false; } if (leaf) { nLeaf[u] = 1; for (int i = 0, _n = (2); i < _n; i = i + 1) f[u][i][i] = 0; return; } for (int i = 0, _n = (2); i < _n; i = i + 1) f[u][0][i] = 0; for (__typeof((adj[u]).begin()) it = (adj[u]).begin(); it != (adj[u]).end(); it++) if (*it != p) { int v = *it; for (int i = 0, _n = (nLeaf[u] + 1); i < _n; i = i + 1) for (int j = 0, _n = (2); j < _n; j = j + 1) { tmp[i][j] = f[u][i][j]; f[u][i][j] = INF; } for (int i = 0, _n = (nLeaf[u] + 1); i < _n; i = i + 1) for (int j = 0, _n = (2); j < _n; j = j + 1) for (int k = 0, _n = (nLeaf[v] + 1); k < _n; k = k + 1) for (int l = 0, _n = (2); l < _n; l = l + 1) minimize(f[u][i + k][j], tmp[i][j] + f[v][k][l] + (j != l)); nLeaf[u] += nLeaf[v]; } } void process(void) { for (int i = (1), _b = (n); i <= _b; i = i + 1) if (adj[i].size() > 1) { dfs(i, -1); printf( %d n , min(f[i][nLeaf[i] / 2][0], f[i][nLeaf[i] / 2][1])); return; } assert(false); } int main(void) { loadTree(); process(); return 0; } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: FIFO_WRITE.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module FIFO_WRITE (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = 450, inf = 1e8; int n1, n2, m, r, b, node, s, t, S, T, a[N], id[N]; char col1[N], col2[N]; int head[N], ce = 1, inq[N], dis[N], maxflow, mincost, need; struct edge { int to, nxt, cap, flow, w; } e[5000]; void lnk(int a, int b, int c, int w) { e[++ce] = (edge){b, head[a], c, 0, w}, head[a] = ce; e[++ce] = (edge){a, head[b], 0, 0, -w}, head[b] = ce; } bool bfs() { for (int i = 1; i <= node; ++i) dis[i] = inf, inq[i] = 0; dis[s] = 0, inq[s] = 1; queue<int> q; q.push(s); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (e[i].cap > e[i].flow && dis[v] > dis[u] + e[i].w) { dis[v] = dis[u] + e[i].w; if (!inq[v]) q.push(v), inq[v] = 1; } } inq[u] = 0; } return dis[t] < inf; } int dfs(int u, int lim) { if (u == t) return mincost += dis[t] * lim, lim; int tag = 0; inq[u] = 1; for (int i = head[u]; i; i = e[i].nxt) if (e[i].cap > e[i].flow && dis[e[i].to] == dis[u] + e[i].w && !inq[e[i].to]) { int d = dfs(e[i].to, min(lim - tag, e[i].cap - e[i].flow)); tag += d, e[i].flow += d, e[i ^ 1].flow -= d; if (tag == lim) { inq[u] = 0; return tag; } } return tag; } int main() { scanf( %d%d%d%d%d , &n1, &n2, &m, &r, &b); scanf( %s , col1 + 1); scanf( %s , col2 + 1); node = n1 + n2, S = ++node, T = ++node, s = ++node, t = ++node; for (int i = 1; i <= n1; ++i) if (col1[i] == R ) ++a[i], --a[S], lnk(S, i, inf, 0); else if (col1[i] == B ) --a[i], ++a[T], lnk(i, T, inf, 0); else lnk(S, i, inf, 0), lnk(i, T, inf, 0); for (int i = 1; i <= n2; ++i) if (col2[i] == R ) --a[i + n1], ++a[T], lnk(i + n1, T, inf, 0); else if (col2[i] == B ) ++a[i + n1], --a[S], lnk(S, i + n1, inf, 0); else lnk(S, i + n1, inf, 0), lnk(i + n1, T, inf, 0); for (int i = 1; i <= T; ++i) if (a[i] > 0) lnk(s, i, a[i], 0), need += a[i]; else if (a[i] < 0) lnk(i, t, -a[i], 0); lnk(T, S, inf, 0); for (int i = 1, u, v; i <= m; ++i) scanf( %d%d , &u, &v), id[i] = ce + 1, lnk(u, v + n1, 1, r), lnk(v + n1, u, 1, b); while (bfs()) maxflow += dfs(s, inf); if (maxflow < need) { puts( -1 ); return 0; } printf( %d n , mincost); for (int i = 1; i <= m; ++i) if (e[id[i]].flow) putchar( R ); else if (e[id[i] + 2].flow) putchar( B ); else putchar( U ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_M_V
`define SKY130_FD_SC_LP__A32OI_M_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32oi_m (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32oi_m (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_M_V
|
#include<bits/stdc++.h> using namespace std; typedef long long int ll; void solve() { ll n; cin>>n; vector<ll> v; for(int i=0;i<n;i++) { ll x; cin>>x; v.push_back(x); } sort(v.begin(),v.end()); ll cost=0; for(ll i=2; i<n; ++i) { ll j=lower_bound(v.begin(),v.end(),v[i]-2)-v.begin(); ll x=(i-j); cost+=(x*(x-1))/2; }cout<<cost<< n ; } int main() { int t; cin>>t; while(t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; vector<int> eum; int w[100005]; int Euler(int num) { int p = 2, ans = 1; while (p * p <= num) { int ct = 1; while (num % p == 0) { ct *= p; num /= p; } if (ct > 1) ct = ct / p * (p - 1); ans *= ct; p++; } if (num > 1) ans *= num - 1; return ans; } long long power(int x, int t, long long m) { if (t == 0) return 1; long long cc = power(x, t >> 1, m); cc = cc * cc % m; if (t & 1) cc = cc * x % m; return cc; } int gcd(int m, int n) { return n == 0 ? m : gcd(n, m % n); } int solve(int l, int r, int mid) { if (l > r) return 1; if (eum[mid] == 1) return 0; vector<int> cc; for (int k = l + 1; k <= r && k <= l + 4; k++) cc.push_back(w[k]); cc.push_back(1); for (int k = 0; k < (cc.size()); k++) if (cc[k] == 1) { long long cur = 1LL; for (int j = k - 1; j >= 0; j--) { if (cc[j] >= 30 || cc[j] >= 4 && cur >= 4) { cur = 30LL; break; } cur = power(cc[j], cur, 1LL << 62); if (cur > 30LL) { cur = 30LL; break; } } if (cur < 30LL) return power(w[l], cur, eum[mid]) % eum[mid]; else return power(w[l], solve(l + 1, r, mid + 1) + eum[mid + 1], eum[mid]); } } int main() { int n, m, q, x, l, r; scanf( %d%d , &n, &m); eum.push_back(m); while ((x = eum.back()) > 1) eum.push_back(Euler(x)); for (int k = 0; k < (n); k++) scanf( %d , &w[k]); scanf( %d , &q); for (int k = 0; k < (q); k++) { scanf( %d%d , &l, &r); l--; r--; printf( %d n , solve(l, r, 0)); } return 0; } |
//deps: fifo.v, uart.v
`timescale 1ns/1ps
module uart_controller(
input rx,
input clk,
input en,
input rst,
input wr_en,
input read,
input baud_wr_en,
input [15:0] data,
output [7:0] data_out,
output reg [7:0] status_out = 0,
output tx,
output reg uart_wait = 0);
parameter FIFO_WIDTH = 8;
parameter CLOCK_FREQUENCY = 50_000_000;
parameter BAUD_RATE = 115200;
parameter CLOCK_DIVIDE = CLOCK_FREQUENCY/(BAUD_RATE*4);
/*AUTOWIRE*/
wire empty; // From tx_fifo of fifo.v, ...
wire full; // From tx_fifo of fifo.v, ...
wire [FIFO_WIDTH-1:0] output_data; // From tx_fifo of fifo.v, ...
wire [7:0] rx_input;
reg [7:0] tx_input = 0;
wire [7:0] tx_output;
wire [7:0] rx_output;
reg tx_rd = 0,tx_wr = 0,rx_rd = 0,rx_wr = 0,transmit = 0;
wire tx_empty, tx_full, rx_empty, rx_full;
wire received, is_receiving, recv_error, is_transmitting;
reg [15:0] clk_div_in;
fifo tx_fifo(
// Outputs
.output_data (tx_output[FIFO_WIDTH-1:0]),
.empty (tx_empty),
.full (tx_full),
// Inputs
.clk (clk),
.rst (rst),
.rd (tx_rd),
.wr (tx_wr),
.input_data (tx_input[FIFO_WIDTH-1:0]));
fifo rx_fifo(
// Outputs
.output_data (data_out[FIFO_WIDTH-1:0]),
.empty (rx_empty),
.full (rx_full),
// Inputs
.clk (clk),
.rst (rst),
.rd (rx_rd),
.wr (received),
.input_data (rx_input[FIFO_WIDTH-1:0]));
uart #(
.CLOCK_DIVIDE(CLOCK_DIVIDE))
uart(
// Outputs
.tx (tx),
.received (received),
.rx_byte (rx_input[7:0]),
.is_receiving (is_receiving),
.is_transmitting (is_transmitting),
.recv_error (recv_error),
// Inputs
.clk (clk),
.rst (rst),
.rx (rx),
.transmit (transmit),
.tx_byte (tx_output),
.clk_div_in (clk_div_in));
always @(posedge clk) begin
if(rst == 1) begin
status_out <= 0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
tx_input <= 8'h0;
tx_wr <= 1'h0;
uart_wait <= 0;
clk_div_in <= CLOCK_DIVIDE;
// End of automatics
end
else begin
status_out[0] <= !tx_full;
status_out[1] <= tx_empty;
status_out[2] <= !rx_empty;
status_out[3] <= rx_full;
//CPU side
//TX
if(wr_en == 1) begin
if(!tx_full) begin
tx_input <= data[7:0];
tx_wr <= 1;
uart_wait <= 0;
end
else
uart_wait <= 1;
end
if(tx_wr == 1)
tx_wr <= 0;
if(read) begin
rx_rd <= 1;
uart_wait <= 1;
end
if(baud_wr_en)begin
clk_div_in <= data;
end
if(rx_rd == 1) begin
rx_rd <= 0;
uart_wait <= 0;
end
//UART side
//TX
if(tx_empty == 0 && is_transmitting == 0) begin
tx_rd <= 1;
transmit <= 1;
end
if(tx_rd == 1) begin
tx_rd <= 0;
transmit <= 0;
$display("Wrote char: %c\n",tx_output);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int A[20][6], n, B[4]; bool check(int l) { int a0 = 0, a1 = 0, i, j; for (i = 0; i < 4; i++) for (j = i + 1; j < 4; j++) if (B[i] == B[j]) return 0; for (i = 0; i < 4; i++) { a0 += (int)(B[i] == A[l][i + 2]); for (j = 0; j < 4; j++) a1 += (int)(B[i] == A[l][j + 2]); } a1 -= a0; return (a1 == A[l][1] && a0 == A[l][0]); } int main() { int res = 0, ans = 0, i, j, tmp; bool fl = 1; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d%d%d , &tmp, &A[i][0], &A[i][1]); for (j = 0; j < 4; j++) A[i][j + 2] = tmp % 10, tmp /= 10; } for (B[0] = 0; B[0] < 10; B[0]++) for (B[1] = 0; B[1] < 10; B[1]++) for (B[2] = 0; B[2] < 10; B[2]++) for (B[3] = 0; B[3] < 10; B[3]++) { fl = 1; for (i = 0; i < n; i++) { fl = (fl && check(i)); } if (fl == 1) res++, ans = B[0] + B[1] * 10 + B[2] * 100 + B[3] * 1000; } if (res == 1) { if (ans >= 1000) printf( %d n , ans); else printf( 0%d n , ans); } if (res > 1) puts( Need more data ); if (res == 0) puts( Incorrect data ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long r(long long a) { long long i = 0; while (a % 2 == 0) { a /= 2; ++i; } return i; } void one_case() { long long a, b; cin >> a >> b; auto ra = r(a); auto rb = r(b); a /= (1ll << ra); b /= (1ll << rb); if (a != b) { cout << -1 n ; return; } cout << (abs(ra - rb) + 2) / 3 << n ; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); int t = 1; cin >> t; while (t--) { one_case(); } return 0; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_rd_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 read requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.size(); n = (s[n - 2] - 48) * 10 + (s[n - 1] - 48); if (n % 4) cout << 0 ; else cout << 4 ; } |
#include <bits/stdc++.h> #define int long long #define f(i,a,n) for (int i = a; i < n; ++i) #define f1(i,a,n) for(int i=n-1;i>=a;i--) #define ff first #define ss second #define pb push_back #define mp make_pair #define all(x) x.begin(), x.end() #define sortall(x) sort(all(x)) #define fastio ios_base::sync_with_stdio(false), cin.tie(NULL); #define w1 solve(); #define mod (int)(1e9 + 7) #define prq priority_queue #define gcd __gcd #define sz(x) (int)x.size() #define w(t) int t; cin>>t; while (t--) { solve(); } #define N 1000001 using namespace std; void __print(int x) {cerr << x;} void __print(float x) {cerr << x;} void __print(double x) {cerr << x;} void __print(long double x) {cerr << x;} void __print(char x) {cerr << << x << ;} void __print(const char *x) {cerr << << x << ;} void __print(const string &x) {cerr << << x << ;} void __print(bool x) {cerr << (x ? true : false );} template<typename T, typename V> void __print(const pair<T, V> &x) {cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ;} template<typename T> void __print(const T &x) {int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ;} void _print() {cerr << ] n ;} template <typename T, typename... V> void _print(T t, V... v) {__print(t); if (sizeof...(v)) cerr << , ; _print(v...);} #ifdef Avash_Local_Machine #define debug(x...) cerr << [ << #x << ] = [ ; _print(x) #else #define debug(x...) #endif typedef vector<int> vi; typedef pair<int, int> pii; typedef vector<pii> vpi; typedef vector<string> vs; typedef vector<char> vc; const int INF = (int)(1e17); const double PI = 3.141592653589793; int dx[4] = { -1, 0, 1, 0}; int dy[4] = {0, 1, 0, -1}; string path = URDL ; void solve() { int q; cin >> q; char c; int n , id = 1; set<pii> set1, set2; //set1 for price,id //set2 for id,price while (q--) { cin >> c; if (c == 1 ) { cin >> n; set1.insert(mp(n, id)); set2.insert(mp(id, n)); ++id; } if (c == 2 ) { auto it = *set2.begin(); cout << it.ff << n ; auto ind = set1.lower_bound(mp(it.ss, it.ff)); set1.erase(ind); set2.erase(set2.begin()); } if (c == 3 ) { auto it = *set1.rbegin(); // debug(it); auto ind = set1.lower_bound(mp(it.ff, -INF)); // debug(ind); cout << (*ind).ss << n ; auto ind1 = set2.lower_bound(mp((*ind).ss, (*ind).ff)); // debug(*ind1); set2.erase(ind1); set1.erase(ind); // debug(set2); } } } int32_t main() { fastio w1 // w(t) return 0; } |
#include <bits/stdc++.h> using namespace std; int i, j, k, l, x, y, z, m, n, ans, dir, s, f, current, p, q; pair<int, int> a; pair<int, pair<int, int> > spies[300000]; int main() { scanf( %d %d %d %d , &n, &m, &s, &f); for (i = 0; i < m; i++) { scanf( %d %d %d , &x, &y, &z); a = make_pair(y, z); spies[i] = make_pair(x, a); } if (s > f) dir = -1; else dir = 1; current = s; i = 0; j = 1; while (current != f) { a = spies[i].second; x = spies[i].first; if (x == j) { i++; y = a.first; z = a.second; p = current; q = current + dir; if ((p >= y && p <= z) || (q >= y && q <= z)) { printf( X ); } else { current = current + dir; if (dir == 1) printf( R ); else printf( L ); } } else { current = current + dir; if (dir == 1) printf( R ); else printf( L ); } j++; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; const int MOD = 1e9 + 7; vector<pair<int, int> > G[maxn]; int vis[maxn]; int dp[maxn]; int dfs(int x, int v) { vis[x] = 1; dp[x] = v; for (pair<int, int> e : G[x]) { int a = e.first; int b = 1 - e.second; if (vis[a]) { if (dp[a] != (dp[x] ^ b)) return 0; } else { if (!dfs(a, v ^ b)) return 0; } } return 1; } int main() { int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { int x, y, v; scanf( %d%d%d , &x, &y, &v); G[x].push_back(make_pair(y, v)); G[y].push_back(make_pair(x, v)); } long long ans = 0; for (int i = 1; i <= n; i++) { if (!vis[i]) { if (!dfs(i, 0)) { puts( 0 ); return 0; } else { if (!ans) ans = 1; else ans = ans * 2 % MOD; } } } cout << ans << endl; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1 ns / 1 ps
module tb_sie();
reg usb_clk;
initial usb_clk = 1'b0;
always #10 usb_clk = ~usb_clk;
reg usb_clk_rx;
initial usb_clk_rx = 1'b0;
always #10 usb_clk_rx = ~usb_clk_rx;
reg usb_rst;
task waitclock;
begin
@(posedge usb_clk);
#1;
end
endtask
reg [7:0] tx_data;
reg tx_valid;
wire tx_ready;
wire txp;
wire txm;
wire txoe;
softusb_tx tx(
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.generate_reset(1'b0),
.txp(txp),
.txm(txm),
.txoe(txoe),
.low_speed(1'b1),
.generate_eop(1'b0)
);
reg rxreset;
softusb_rx rx(
.usb_clk(usb_clk_rx),
.rxreset(rxreset),
.rx(txp),
.rxp(txp),
.rxm(txm),
.rx_data(),
.rx_valid(),
.rx_active(),
.low_speed(1'b1)
);
initial begin
$dumpfile("softusb_sie.vcd");
$dumpvars(0, tx);
$dumpvars(0, rx);
usb_rst = 1'b1;
rxreset = 1'b1;
tx_valid = 1'b0;
waitclock;
waitclock;
usb_rst = 1'b0;
@(posedge usb_clk);
@(posedge usb_clk);
rxreset = 1'b0;
tx_data = 8'h80;
tx_valid = 1'b1;
#3000;
tx_data = 8'h2d;
#9000;
tx_valid = 1'b0;
#40000;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[4], b[4]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); sort(a, a + n); if (!n) puts( YES n1 n1 n3 n3 ); else if (n == 1) printf( YES n%d n%d n%d n , a[0] << 1, a[0] << 1, a[0] + (a[0] << 1)); else if (n == 2) { if (a[0] * 3 == a[1]) printf( YES n%d n%d n , a[0] << 1, a[0] << 1); else if (a[1] < a[0] * 3) printf( YES n%d n%d n , a[0] * 3, a[0] * 4 - a[1]); else puts( NO ); } else if (n == 4) { if (a[0] + a[3] == a[1] + a[2] && (a[3] - a[0]) << 1 == a[1] + a[2]) puts( YES ); else puts( NO ); } else { int i; for (i = 1; i <= 1000000; ++i) { for (int j = 0; j < 3; ++j) b[j] = a[j]; b[3] = i; sort(b, b + 4); if (b[0] + b[3] == b[1] + b[2] && (b[3] - b[0]) << 1 == b[1] + b[2]) break; } if (i <= 1000000) printf( YES n%d n , i); else puts( NO ); } return 0; } |
`timescale 1 ns / 1 ps
`include "n64_cart_cntlr_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module n64_cart_cntlr_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
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