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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_4_V
`define SKY130_FD_SC_HDLL__EINVN_4_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_4_V
|
#include <bits/stdc++.h> using namespace std; char a[11]; bool ok = true; bool check(char a[]) { for (int i = 0; i < 7; i++) if (a[i] == a[i + 1]) return false; return true; } int main() { for (int i = 1; i <= 8; i++) { scanf( %s , a); ok &= check(a); } if (ok) puts( YES ); else puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long int n, i, t; cin >> n; long int a[n]; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (a[0] == 0) a[0] = a[1]; if (n >= 2) { if (a[n - 2] - a[0] < a[n - 1] - a[1]) t = a[n - 2] - a[0]; else t = a[n - 1] - a[1]; cout << t; } else cout << 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:268435456,268435456 ) using namespace std; int above[41][41], dp[41][41][41][41]; char s[42]; int main() { int n, m, q, s1, s2, s3, s4; scanf( %d %d %d , &n, &m, &q); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); for (int j = 1; j <= m; j++) if (s[j] == 0 ) above[i][j] += above[i - 1][j] + 1; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) for (int k = i; k <= n; k++) for (int l = j; l <= m; l++) { dp[i][j][k][l] = dp[i][j][k - 1][l] + dp[i][j][k][l - 1] - dp[i][j][k - 1][l - 1]; int temp = min(above[k][l], k - i + 1); dp[i][j][k][l] += temp; for (int z = l - 1; z >= j; z--) { temp = min(temp, above[k][z]); if (temp == 0) break; else dp[i][j][k][l] += temp; } } for (int i = 0; i < q; i++) scanf( %d %d %d %d , &s1, &s2, &s3, &s4), printf( %d n , dp[s1][s2][s3][s4]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); char str[1000][1000]; int i; for (i = 0; i < n; i++) { scanf( %[^ n] , str[i]); } int cnt = 0; int j; for (i = 0; i < n; i++) { if (strcmp(str[i], -1 ) == 0) continue; cnt++; int flag = 0; for (j = i + 1; j < n; j++) { if (strcmp(str[j], -1 ) == 0) continue; if (strcmp(str[i], str[j]) == 0) { strcpy(str[j], -1 ); } } } printf( %d n , cnt); return 0; } |
module sdcard_interface(
output sclk,
output mosi,
input miso,
input clk,
input rst,
input [9:0] sram_a,
input [15:0] sram_d_in,
output [15:0] sram_d_out,
input sram_cs,
input sram_oe,
input [1:0] sram_wstrb,
output sram_wait,
output [7:0] dma_data,
output [8:0] dma_addr,
output dma_strobe
);
wire [7:0] spi_data_in;
wire [7:0] spi_data_out;
wire start, finished;
wire spi_crc_in_bit, spi_crc_out_bit, spi_crc_strobe;
wire crc16_x, crc7_x;
reg [7:0] divider_d, divider_q;
reg [4:0] bits_d, bits_q;
reg [7:0] latch_d, latch_q;
reg avail_d, avail_q;
reg [8:0] dma_counter_d, dma_counter_q;
reg dma_mode_d, dma_mode_q, dma_trigger_d, dma_trigger_q;
reg [15:0] crc16_d, crc16_q;
reg [6:0] crc7_d, crc7_q;
assign spi_data_in = (dma_mode_q? 8'hff : sram_d_in[7:0]);
assign start = (dma_mode_q? dma_trigger_q : (sram_cs & sram_wstrb[0] & (sram_a[4:2] == 3'b001)));
assign sram_wait = 1'b0;
assign dma_data = latch_q;
assign dma_addr = dma_counter_q;
assign dma_strobe = avail_q & dma_mode_q;
reg [15:0] sram_d;
assign sram_d_out = sram_d;
assign crc16_x = crc16_q[15]^spi_crc_in_bit;
assign crc7_x = crc7_q[6]^spi_crc_out_bit;
sdcard_spi spi_inst(.sclk(sclk), .mosi(mosi), .miso(miso),
.rst(rst), .clk(clk), .data_in(spi_data_in),
.data_out(spi_data_out), .divider(divider_q),
.bits(bits_q), .start(start), .finished(finished),
.crc_in_bit(spi_crc_in_bit), .crc_out_bit(spi_crc_out_bit),
.crc_strobe(spi_crc_strobe));
always @(*) begin
sram_d = 16'h0000;
case (sram_a[4:2])
3'b000: sram_d[7:0] = {avail_q, dma_mode_q, 1'b0, bits_q};
3'b001: sram_d[7:0] = latch_q;
3'b010: sram_d[7:0] = divider_q;
3'b100: sram_d = crc16_q;
3'b101: sram_d[7:0] = { crc7_q, 1'b1 };
endcase
end
always @(*) begin
divider_d = divider_q;
bits_d = bits_q;
avail_d = avail_q;
latch_d = latch_q;
dma_counter_d = dma_counter_q;
dma_mode_d = dma_mode_q;
dma_trigger_d = 1'b0;
crc16_d = crc16_q;
crc7_d = crc7_q;
if (sram_cs & sram_wstrb[0]) begin
case (sram_a[4:2])
3'b000: begin
bits_d = sram_d_in[4:0];
if (sram_d_in[6]) begin
dma_mode_d = 1'b1;
dma_trigger_d = 1'b1;
dma_counter_d = 9'h000;
end else begin
dma_mode_d = 1'b0;
end
avail_d = sram_d_in[7];
end
3'b001: avail_d = 1'b0;
3'b010: divider_d = sram_d_in[7:0];
3'b100: crc16_d[7:0] = sram_d_in[7:0];
3'b101: crc7_d = sram_d_in[7:1];
endcase
end
if (sram_cs & sram_wstrb[1]) begin
case (sram_a[4:2])
3'b100: crc16_d[15:8] = sram_d_in[15:8];
endcase // case (sram_a[4:2])
end
if (finished) begin
avail_d = 1'b1;
latch_d = spi_data_out;
end
if (avail_q & dma_mode_q) begin
avail_d = 1'b0;
dma_counter_d = dma_counter_q + 1;
if (dma_counter_q == 9'h1ff)
dma_mode_d = 1'b0;
else
dma_trigger_d = 1'b1;
end
if (spi_crc_strobe) begin
crc16_d = {crc16_q[14:0],1'b0}^{3'b000,crc16_x,6'b000000,crc16_x,4'b0000,crc16_x};
crc7_d = {crc7_q[6:0],1'b0}^{3'b000,crc7_x,2'b00,crc7_x};
end
end // always @ (*)
always @(posedge clk) begin
if (rst) begin
divider_q <= 8'h00;
bits_q <= 5'h00;
avail_q <= 1'b0;
latch_q <= 8'h00;
dma_counter_q <= 8'h00;
dma_mode_q <= 1'b0;
dma_trigger_q <= 1'b0;
crc16_q <= 16'h0000;
crc7_q <= 7'h00;
end else begin
divider_q <= divider_d;
bits_q <= bits_d;
avail_q <= avail_d;
latch_q <= latch_d;
dma_counter_q <= dma_counter_d;
dma_mode_q <= dma_mode_d;
dma_trigger_q <= dma_trigger_d;
crc16_q <= crc16_d;
crc7_q <= crc7_d;
end
end
endmodule // sdcard_interface
|
module alt_vipitc131_common_generic_count
#( parameter WORD_LENGTH = 12,
parameter MAX_COUNT = 1280,
parameter RESET_VALUE = 0,
parameter TICKS_WORD_LENGTH = 1,
parameter TICKS_PER_COUNT = 1
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire enable_ticks,
input wire [WORD_LENGTH-1:0] max_count, // -1
output reg [WORD_LENGTH-1:0] count,
input wire restart_count,
input wire [WORD_LENGTH-1:0] reset_value,
output wire enable_count,
output wire start_count,
output wire [TICKS_WORD_LENGTH-1:0] cp_ticks
);
generate
if(TICKS_PER_COUNT == 1) begin
assign start_count = 1'b1;
assign enable_count = enable;
assign cp_ticks = 1'b0;
end else begin
reg [TICKS_WORD_LENGTH-1:0] ticks;
always @(posedge clk or negedge reset_n)
if (!reset_n)
ticks <= {TICKS_WORD_LENGTH{1'b0}};
else
ticks <= (restart_count) ? {TICKS_WORD_LENGTH{1'b0}} :
(enable) ? (ticks >= TICKS_PER_COUNT - 1) ? {TICKS_WORD_LENGTH{1'b0}} : ticks + 1'b1 : ticks;
assign start_count = ticks == {TICKS_WORD_LENGTH{1'b0}} || !enable_ticks;
assign enable_count = enable && ((ticks >= TICKS_PER_COUNT - 1) || !enable_ticks);
assign cp_ticks = ticks & {TICKS_WORD_LENGTH{enable_ticks}};
end
endgenerate
always @(posedge clk or negedge reset_n)
if (!reset_n)
count <= RESET_VALUE[WORD_LENGTH-1:0];
else
count <= (restart_count) ? reset_value :
(enable_count) ? (count < max_count) ? count + 1'b1 : {(WORD_LENGTH){1'b0}} : count;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_2_V
`define SKY130_FD_SC_MS__O21BAI_2_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_2_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:35 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: chbond_count_dec_gtp.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// CHBOND_COUNT_DEC
//
//
// Description: This module decodes the GTP's RXSTATUS signals. RXSTATUS[5] indicates
// that Channel Bonding is complete
//
// * Supports GTP
//
`timescale 1 ns / 10 ps
module aurora_201_CHBOND_COUNT_DEC (
RX_STATUS,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 6'b100111; // Status bus code: Channel Bond load complete
//***********************************Port Declarations*******************************
input [5:0] RX_STATUS;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_STATUS == CHANNEL_BOND_LOAD_CODE);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s = ; for (int i = 1; i < 1000; i++) { s += to_string(i); } int n; cin >> n; cout << s[n - 1]; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j, k; string s; while (cin >> n >> s) { int sum = 0; int left = 0, right = 0, up = 0, down = 0; for (i = 0; i < n; i++) { if (s[i] == R ) { if (left == 1) { sum++; left = 0; up = 0; down = 0; } right = 1; } else if (s[i] == L ) { if (right == 1) { sum++; right = 0; up = 0; down = 0; } left = 1; } else if (s[i] == U ) { if (down == 1) { sum++; down = 0; left = 0; right = 0; } up = 1; } else if (s[i] == D ) { if (up == 1) { sum++; up = 0; left = 0; right = 0; } down = 1; } } cout << sum + 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; pair<long long, long long> dp[1100][20]; int bitcnt[1100]; long long p10[21]; string a; int n, k; pair<long long, long long> dfs(int bi, int pos, int flag, int leading) { if (pos == -1) return make_pair(0, 1); if (dp[bi][pos].second != -1 && !flag && !leading) { return dp[bi][pos]; } long long ans = 0; long long cnt = 0; int upper = (flag ? a[n - pos - 1] - 0 : 9); for (int i = 0; i <= upper; i++) { int nextstate = (bi | (1 << i)); if ((bi & (1 << i)) == 0 && !(leading && i == 0)) { if (bitcnt[nextstate] > k) continue; pair<long long, long long> p = dfs(nextstate, pos - 1, flag && (i == upper), leading && (i == 0)); cnt = (cnt + p.second) % 998244353; ans = (ans + ((((p.second * i) % 998244353) * p10[pos]) % 998244353 + p.first) % 998244353) % 998244353; } else { pair<long long, long long> p = dfs(bi, pos - 1, flag && (i == upper), leading && (i == 0)); cnt = (cnt + p.second) % 998244353; ans = (ans + ((((p.second * i) % 998244353) * p10[pos]) % 998244353 + p.first) % 998244353) % 998244353; } } if (!flag && !leading) { dp[bi][pos] = make_pair(ans % 998244353, cnt % 998244353); } return make_pair(ans % 998244353, cnt % 998244353); } long long solve(long long num) { a = to_string(num); n = (int)a.length(); pair<long long, long long> p = dfs(0, n - 1, 1, 1); return p.first % 998244353; } int main() { long long l, r; int i, j; p10[0] = 1; for (i = 1; i <= 20; i++) { p10[i] = (p10[i - 1] * 10) % 998244353; } for (i = 0; i < 1100; i++) { for (j = 0; j < 20; j++) { dp[i][j] = make_pair(0, -1); } } bitcnt[0] = 0; bitcnt[1] = 1; for (i = 2; i < 1100; i++) bitcnt[i] = bitcnt[i - (i & -i)] + 1; cin >> l >> r >> k; cout << (solve(r) - solve(l - 1) + 998244353) % 998244353 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; bool comp(pair<long long, long long> a, pair<long long, long long> b) { return a.first > b.first; } long long findBest(vector<pair<long long, long long> >& ps, long long x) { long long res = 0; for (long long i = 0; i < ps.size(); i++) { long long num = ps[i].second; long long diff = ps[i].first; if (x - num >= 0) { res += (num * diff); x -= num; } else { res += (x * diff); break; } } return res; } int main() { long long n, s; cin >> n >> s; vector<pair<long long, long long> > ps; long long total = 0; long long positives = 0; long long pieces = 0; for (long long i = 0; i < n; i++) { long long num, a, b; cin >> num >> a >> b; ps.push_back(make_pair(a - b, num)); total += num * b; pieces += num; if (a - b > 0) { positives += num; } } sort(ps.begin(), ps.end(), comp); long long pizzas = (pieces % s == 0) ? (pieces / s) : (pieces / s + 1); long long extra = pizzas * s - pieces; long long best = total; if (positives > 0) { best = max(best, findBest(ps, positives / s * s) + total); if (positives % s != 0) { long long x = max(positives, (positives / s + 1) * s - extra); best = max(best, findBest(ps, x) + total); } } cout << best << endl; return 0; } |
// Texas A&M University //
// cpsc350 Computer Architecture //
//Alan Achtenberg??
//Project 2//
`define OPCODE_ADD 6'b000000
`define OPCODE_SUB 6'b000000
`define OPCODE_ADDU 6'b000000
`define OPCODE_SUBU 6'b000000
`define OPCODE_AND 6'b000000
`define OPCODE_OR 6'b000000
`define OPCODE_SLL 6'b000000
`define OPCODE_SRA 6'b000000
`define OPCODE_SRL 6'b000000
`define OPCODE_SLT 6'b000000
`define OPCODE_SLTU 6'b000000
`define OPCODE_XOR 6'b000000
`define OPCODE_JR 6'b000000
//I-Type (All opcodes except 000000, 00001x, and 0100xx)
`define OPCODE_ADDI 6'b001000
`define OPCODE_ADDIU 6'b001001
`define OPCODE_ANDI 6'b001100
`define OPCODE_BEQ 6'b000100
`define OPCODE_BNE 6'b000101
`define OPCODE_BLEZ 6'b000110
`define OPCODE_BLTZ 6'b000001
`define OPCODE_ORI 6'b001101
`define OPCODE_XORI 6'b001110
`define OPCODE_NOP 6'b110110
`define OPCODE_LUI 6'b001111
`define OPCODE_SLTI 6'b001010
`define OPCODE_SLTIU 6'b001011
`define OPCODE_LB 6'b100000
`define OPCODE_LW 6'b100011
`define OPCODE_SB 6'b101000
`define OPCODE_SW 6'b101011
// J-Type (Opcode 00001x)
`define OPCODE_J 6'b000010
`define OPCODE_JAL 6'b000011
`define ADD 4'b0111 // 2's compl add
`define ADDU 4'b0001 // unsigned add
`define SUB 4'b0010 // 2's compl subtract
`define SUBU 4'b0011 // unsigned subtract
`define AND 4'b0100 // bitwise AND
`define OR 4'b0101 // bitwise OR
`define XOR 4'b0110 // bitwise XOR
`define SLT 4'b1010 // set result=1 if less than 2's compl
`define SLTU 4'b1011 // set result=1 if less than unsigned
`define NOP 4'b0000 // do nothing
// Top Level Architecture Model //
`include "Control.v"
`include "IdealMemory.v"
`include "PC.v"
`include "RegisterFile.v"
`include "mux.v"
`include "ALU_bhav.v"
`include "signextend.v"
`include "ALUControl.v"
/*-------------------------- CPU -------------------------------
* This module implements a single-cycle
* CPU similar to that described in the text book
* (for example, see Figure 5.19).
*
*/
//
// Input Ports
// -----------
// clock - the system clock (m555 timer).
//
// reset - when asserted by the test module, forces the processor to
// perform a "reset" operation. (note: to reset the processor
// the reset input must be held asserted across a
// negative clock edge).
//
// During a reset, the processor loads an externally supplied
// value into the program counter (see startPC below).
//
// startPC - during a reset, becomes the new contents of the program counter
// (starting address of test program).
//
// Output Port
// -----------
// dmemOut - contains the data word read out from data memory. This is used
// by the test module to verify the correctness of program
// execution.
//-------------------------------------------------------------------------
module SingleCycleProc(CLK, Reset_L, startPC, dmemOut);
input Reset_L, CLK;
input [31:0] startPC;
output [31:0] dmemOut;
wire [31:0] PC;
wire [31:0] Instr;
//
// INSERT YOUR CPU MODULES HERE
ProgramCounter PC1(PC, PC, Reset_L, startPC,CLK);
InstrMem IM1(PC, Instr);
wire RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend;
wire [3:0]ALUOp;
Control_Unit C1(RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend, ALUOp, Instr[31:26]);
wire [3:0] ALUctrl;
ALUControl AC1(ALUctrl, ALUOp,Instr[5:0]);
wire [4:0] Waddr;
MUX5_2to1 mux1(Instr[20:16], Instr[15:11], RegDst, Waddr );
wire [31:0]Read1, Read2, Writedata;
RegisterFile RF1(Read1, Read2, Writedata, Instr[25:21],Instr[20:16], Waddr, RegWrite, CLK, Reset_L);
wire [31:0]Immediate; //Sign extended value
SIGN_EXTEND SE1(Instr[15:0], Immediate);
wire [31:0] ALUin, Result; //
wire Zero;
MUX32_2to1 mux2(Read2, Immediate, ALUSrc, ALUin);
ALU_behav ALU1( Read1, ALUin, ALUctrl, Writedata, Overflow, 1'b0, Carry_out, Zero );
//
// Debugging
//
/*
always @(RegDst or Waddr)
begin
$display("RegDst %b Waddr %d" , RegDst, Waddr );
end
*/
//Monitor changes in the program counter
/* always @(PC)
begin
#10 $display($time," PC=%d Instr: op=%d rs=%d rt=%d rd=%d imm16=%d funct=%d",
PC,Instr[31:26],Instr[25:21],Instr[20:16],Instr[15:11],Instr[15:0],Instr[5:0]);
end
*/
/* Monitors memory writes
always @(MemWrite)
begin
#1 $display($time," MemWrite=%b clock=%d addr=%d data=%d",
MemWrite, clock, dmemaddr, rportb);
end
*/
/*always @(Instr)
begin
#10 $display($time,"OPCODE=%b, ALUctrl=%b , ALUOp=%b", Instr[31:26],ALUctrl, ALUOp);
end
*/
endmodule // CPU
module m555 (CLK);
parameter StartTime = 0, Ton = 50, Toff = 50, Tcc = Ton+Toff; //
output CLK;
reg CLK;
initial begin
#StartTime CLK = 0;
end
// The following is correct if clock starts at LOW level at StartTime //
always begin
#Toff CLK = ~CLK;
#Ton CLK = ~CLK;
end
endmodule
module testCPU(Reset_L, startPC, testData);
input [31:0] testData;
output Reset_L;
output [31:0] startPC;
reg Reset_L;
reg [31:0] startPC;
initial begin
// Your program 1
Reset_L = 0; startPC = 0 * 4;
#101 // insures reset is asserted across negative clock edge
Reset_L = 1;
#1000; // allow enough time for program 1 to run to completion
Reset_L = 0;
// #1 $display ("Program 1: Result: %d", testData);
// Your program 2
//startPC = 14 * 4;
//#101 Reset_L = 1;
//#10000;
//Reset_L = 0;
//#1 $display ("Program 2: Result: %d", testData);
// etc.
// Run other programs here
$finish;
end
endmodule // testCPU
module TopProcessor;
wire reset, CLK, Reset_L;
wire [31:0] startPC;
wire [31:0] testData;
m555 system_clock(CLK);
SingleCycleProc SSProc(CLK, Reset_L, startPC, testData);
testCPU tcpu(Reset_L, startPC, testData);
endmodule // TopProcessor |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t, n, k, c = 0, d = 0; cin >> n >> k; map<long long, long long> m; for (int i = 0; i < n; ++i) { cin >> t; m[t]++; } auto it2 = m.begin(); for (auto it = m.begin(); it != m.end(); ++it) { it2 = it; it2++; t = it->first; if (it2 == m.end()) { c += it->second; break; } d = it2->first; if (t + k < d) c += it->second; } cout << c; return 0; } |
#include <bits/stdc++.h> using namespace std; bool flag = 0; int work(int a, int n, int p) { int t = a * 1ll * n / p; if (!t) { if (!flag) return a; return max(a, p - a * n); } flag = 1; int a1, n1, p1; a1 = min(p % a, a - (p % a)); n1 = t; p1 = a; if (a * 1ll * n % p < a * 1ll * (p / a - 1)) n1--; return work(a1, n1, p1); } int main() { int t; scanf( %d , &t); while (t--) { int a, n, p, h; scanf( %d%d%d%d , &a, &n, &p, &h); flag = 0; if (work(a % p, n, p) <= h) printf( YES n ); else printf( NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; set<pair<int, int> > s0, s; int K; long long xx[200010], yy[200010]; void func(long long x, long long y) { while (K > 0 && yy[K - 1] < y) K--; while (K >= 2) { long long tmp = (x - xx[K - 2]) * (yy[K - 1] - yy[K - 2]) - (xx[K - 1] - xx[K - 2]) * (y - yy[K - 2]); if (tmp < 0) K--; else break; } xx[K] = x; yy[K] = y; K++; } int main(void) { int N, M, x, y, i; cin >> N >> M >> x >> y; for ((i) = 0; (i) < (int)(N); (i)++) { scanf( %d%d , &x, &y); s0.insert(make_pair(x, y)); s.insert(make_pair(x, -y)); } for ((i) = 0; (i) < (int)(M); (i)++) { scanf( %d%d , &x, &y); s.insert(make_pair(x, -y)); } for (__typeof((s).begin()) itr = (s).begin(); itr != (s).end(); itr++) { x = (*itr).first; y = (*itr).second; func(x, -y); } int tp; string ans = Min ; for ((i) = 0; (i) < (int)(K); (i)++) { if (s0.find(make_pair(xx[i], yy[i])) != s0.end()) ans = Max ; } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_PP_V |
`define MEM_SIZE 256
`define INIT "../lib/initRegisters.txt"
`define VAL "../lib/regVals.txt"
module im (
input clk,
input [31:0] addr,
output [31:0] data
);
reg [31:0] mem [0:`MEM_SIZE-1];
reg [7:0] test_begin, test_end, regVals_begin, regVals_end;
`ifdef R_TYPE
parameter path = "../program/r_type.txt";
`elsif I_TYPE
parameter path = "../program/i_type.txt";
`elsif BRANCH
parameter path = "../program/branch.txt";
`elsif BRANCHN
parameter path = "../program/branchn.txt";
`elsif JUMP
parameter path = "../program/jump.txt";
`elsif JAL
parameter path = "../program/jal.txt";
`elsif LOOP
parameter path = "../program/loop.txt";
`else
parameter path = "../program/test.txt";
`endif
parameter initRegisters = `INIT;
parameter regVals = `VAL;
initial begin
/*
test_begin = 31;
test_end = 30+`CODE_SIZE;
regVals_begin = 30+`CODE_SIZE+1;
regVals_end = 30+`CODE_SIZE+32;
*/
$readmemh(path, mem, 1, `MEM_SIZE-33 );
// $readmemh(initRegisters, mem, 0 , 30 );
// $readmemh(path , mem, 31 , `MEM_SIZE-33);
// $readmemh(regVals , mem, `MEM_SIZE-32, `MEM_SIZE-1);
end
assign data = mem[addr];
endmodule
|
#include <bits/stdc++.h> using namespace std; int dis(char a, char b) { if (a > b) swap(b, a); return min(b - a, a + 26 - b); } string tmp = ACTG ; int main() { int n; scanf( %d , &n); string s; cin >> s; int mn = INT_MAX; for (int i = 0; i + 4 - 1 < n; i++) { int now = 0; for (int j = i, k = 0; k < 4; j++, k++) { now += dis(s[j], tmp[k]); } mn = min(mn, now); } printf( %d n , mn); return 0; } |
#include <bits/stdc++.h> using namespace std; const int Max_n = 2e5 + 10; const int Max_m = 4e5 + 10; int f[Max_n]; struct A { long long val; int pos; bool operator<(const A &a) const { return val < a.val; } } a[Max_n]; struct Edge { int u, v; long long cost; bool operator<(const Edge &edge) const { return cost < edge.cost; } } edge[Max_m * 2]; int Find(int v) { if (f[v] == v) return v; return f[v] = Find(f[v]); } bool Merge(int m, int n) { int t1 = Find(m); int t2 = Find(n); if (t1 != t2) { f[t1] = t2; return true; } return false; } int main() { int n, m; scanf( %d%d , &n, &m); int cnt = 0; for (int i = 1; i <= n; i++) f[i] = i; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i].val); a[i].pos = i; } sort(a + 1, a + n + 1); for (int i = 2; i <= n; i++) { edge[cnt].u = a[1].pos; edge[cnt].v = a[i].pos; edge[cnt++].cost = a[1].val + a[i].val; edge[cnt].u = a[i].pos; edge[cnt].v = a[1].pos; edge[cnt++].cost = a[1].val + a[i].val; } for (int i = 1; i <= m; i++) { int u, v; long long cost; scanf( %d%d%lld , &u, &v, &cost); edge[cnt].u = u; edge[cnt].v = v; edge[cnt++].cost = cost; edge[cnt].u = v; edge[cnt].v = u; edge[cnt++].cost = cost; } sort(edge, edge + cnt); long long ans = 0; int edgeCnt = 0; for (int i = 0; i < cnt; i++) { if (Merge(edge[i].u, edge[i].v)) { ans += edge[i].cost; edgeCnt++; } if (edgeCnt == n - 1) break; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void FAST(); long long int big_mod(long long int val, long long int pow, long long int mod); long long int mod_inverse(long long int val, long long int mod); int main() { FAST(); int m, n; scanf( %d %d , &n, &m); if (m < 2) { printf( 1 ); } else { if (n & 1 == 0) { if (m >= n / 2) { printf( %d , n - m); } else { printf( %d , m); } } else { if (m > n / 2) { printf( %d , n - m); } else { printf( %d , m); } } } return 0; } void FAST() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } long long int big_mod(long long int val, long long int pow, long long int mod) { long long int res = 1; val = val % mod; while (pow > 0) { if (pow & 1) { res = (res * val) % mod; } pow = pow >> 1; val = (val * val) % mod; } return res; } long long int mod_inverse(long long int val, long long int mod) { long long int mod1 = mod; if (mod == 1) { return 0; } long long int y = 0; long long int x = 1; long long int quotient, temp; while (val > 1) { quotient = val / mod; temp = mod; mod = val % mod; val = temp; temp = y; y = x - quotient * y; x = temp; } if (x < 0) { x += mod1; } return x; } |
#include <bits/stdc++.h> int main() { long int l, r; scanf( %ld %ld , &l, &r); if (l == r) printf( %ld n , r); else printf( 2 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long K, statc; int qc; bool query(long long l, long long r) { qc++; assert(qc <= 4499); cout << l << << r << n ; fflush(stdout); string ans; cin >> ans; if (l == r && ans[0] == Y ) { exit(0); } if (ans[0] == B ) { exit(0); } return ans[0] == Y ; } long long randrange(long long l, long long r) { long long mod = r - l + 1; return l + rand() % mod; } long long extl(long long x) { return max(1LL, x - K); } long long extr(long long x) { return min(statc, x + K); } int main() { srand(time(NULL)); ios::sync_with_stdio(false); cin >> statc >> K; long long l = 1, r = statc; while (true) { long long w = r - l + 1; if (w <= 7 * K) { long long guess = randrange(l, r); query(guess, guess); } else { long long mid = (l + r) / 2; if (query(l, mid)) { r = mid; } else { l = mid + 1; } } l = extl(l); r = extr(r); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxbp (
CLK ,
D ,
Q ,
Q_N ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_PP_BLACKBOX_V
|
#include <iostream> #include <vector> #include <array> #define vi vector<int> #define pii pair<int, int> #define fst first #define snd second using namespace std; const int SZ = (1 << 19) + 5, INF = (1e9) + 7; int N, ans[200001]; vi idx[200001]; array<int, 4> seg[2][SZ]; int lz[2][SZ]; array<int, 4> merge(const array<int, 4>& L, const array<int, 4>& R) { return {min(L[0], R[0]), max(L[1], R[1]), min(L[2], R[2]), max(L[3], R[3])}; } inline void prop(int t, int idx, int L, int R) { if (lz[t][idx]) { for (int i = 0; i < 4; i++) { if (seg[t][idx][i] > -INF && seg[t][idx][i] < INF) seg[t][idx][i] += lz[t][idx]; } if (L < R) { lz[t][2 * idx] += lz[t][idx]; lz[t][2 * idx + 1] += lz[t][idx]; } lz[t][idx] = 0; } } void build(int t, int idx, int L, int R) { seg[t][idx][0] = seg[t][idx][2] = INF; seg[t][idx][1] = seg[t][idx][3] = -INF; if (L == R) { seg[t][idx][(L & 1) << 1] = 0; seg[t][idx][(L & 1) << 1 | 1] = 0; } else if (L < R) { int M = L + R >> 1; build(t, 2 * idx, L, M); build(t, 2 * idx + 1, M + 1, R); seg[t][idx] = merge(seg[t][2 * idx], seg[t][2 * idx + 1]); } } void upd(int t, int idx, int L, int R, int l, int r, int v) { l = max(L, l); r = min(R, r); prop(t, idx, L, R); if (l <= r) { if (L == l && R == r) {lz[t][idx] += v; prop(t, idx, L, R);} else { int M = L + R >> 1; upd(t, 2 * idx, L, M, l, r, v); upd(t, 2 * idx + 1, M + 1, R, l, r, v); seg[t][idx] = merge(seg[t][2 * idx], seg[t][2 * idx + 1]); } } } array<int, 4> qry(int t, int idx, int L, int R, int l, int r) { l = max(L, l); r = min(R, r); if (l <= r) { prop(t, idx, L, R); if (L == l && R == r) {return seg[t][idx];} else { int M = L + R >> 1; return merge(qry(t, 2 * idx, L, M, l, r), qry(t, 2 * idx + 1, M + 1, R, l, r)); } } return {INF, -INF, INF, -INF}; } int main() { cin >> N; for (int i = 1; i <= N; i++) { int x; cin >> x; idx[x].push_back(i); } build(0, 1, 0, N); build(1, 1, 0, N); for (int i = 1; i <= N; i++) { upd(i & 1, 1, 0, N, i, N, -1); } for (int i = 1; i <= N; i++) { for (const auto &x : idx[i]) { for (int j = 0; j < 2; j++) { array<int, 4> A = qry(j, 1, 0, N, 0, x - 1), B = qry(j, 1, 0, N, x, N); ans[x] = max(ans[x], max(B[1], B[3]) - A[j << 1]); ans[x] = max(ans[x], A[j << 1 | 1] - min(B[0], B[2])); } } for (const auto &x : idx[i]) { for (int j = 0; j < 2; j++) upd(j, 1, 0, N, x, N, 1); } for (const auto &x : idx[i]) { for (int j = 0; j < 2; j++) { upd(j, 1, 0, N, x, N, -1); array<int, 4> A = qry(j, 1, 0, N, 0, x - 1), B = qry(j, 1, 0, N, x, N); ans[x] = max(ans[x], max(B[1], B[3]) - A[j << 1]); ans[x] = max(ans[x], A[j << 1 | 1] - min(B[0], B[2])); upd(j, 1, 0, N, x, N, 1); } } } for (int i = 1; i <= N; i++) { cout << ans[i] << n [i == N]; } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / OBUFDS_GTM
// /___/ /\ Filename : OBUFDS_GTM.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTM #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter integer REFCLK_ICNTL_TX = 0
)(
output O,
output OB,
input CEB,
input I
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTM";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTM_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [31:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
`endif
`ifdef XIL_XECLIB
wire [3:0] REFCLK_ICNTL_TX_BIN;
`else
reg [3:0] REFCLK_ICNTL_TX_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
reg glblGTS = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
tri0 glblGTS = glbl.GTS;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
`else
always @ (trig_attr) begin
#1;
REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((REFCLK_ICNTL_TX_REG != 0) &&
(REFCLK_ICNTL_TX_REG != 1) &&
(REFCLK_ICNTL_TX_REG != 3) &&
(REFCLK_ICNTL_TX_REG != 7) &&
(REFCLK_ICNTL_TX_REG != 15))) begin
$display("Error: [Unisim %s-102] REFCLK_ICNTL_TX attribute is set to %d. Legal values for this attribute are 0, 1, 3, 7 or 15. Instance: %m", MODULE_NAME, REFCLK_ICNTL_TX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
// =====================
// Generate O
// =====================
assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I;
assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I;
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
// end behavioral model
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 25.06.2017 19:20:37
// Design Name:
// Module Name: conversor_num_16b
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module conversor_num_16b(
input [19:0] numeros,
output [15:0] operador
);
localparam exp4= 16'd10000;
localparam exp3= 16'd1000;
localparam exp2= 16'd100;
localparam exp1= 16'd10;
localparam exp0= 16'd1;
wire [15:0] num_exp4,num_exp3,num_exp2,num_exp1,num_exp0;
assign num_exp4={12'b0,numeros[19:16]}*exp4;
assign num_exp3={12'b0,numeros[15:12]}*exp3;
assign num_exp2={12'b0,numeros[11:8]}*exp2;
assign num_exp1={12'b0,numeros[7:4]}*exp1;
assign num_exp0={12'b0,numeros[3:0]}*exp0;
assign operador=num_exp0+num_exp1+num_exp2+num_exp3+num_exp4;
endmodule
|
#include <bits/stdc++.h> using namespace std; void xx(int *a, int n) { for (int j = 1; j < n; ++j) for (int i = j; i <= n; ++i) if (a[j] < a[i]) { int t = a[i]; a[i] = a[j]; a[j] = t; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t, n; cin >> t; for (int i = 1; i <= t; ++i) { cin >> n; int a[n]; for (int j = 1; j <= n; ++j) cin >> a[j]; xx(a, n); for (int j = 1; j <= n; ++j) cout << a[j] << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> const int N = 110000; using namespace std; set<pair<int, int> > elements; set<pair<int, int> >::iterator it; int n; int ar[N]; int next_lucky[N], prev_lucky[N]; bool is_lucky[N]; vector<int> luck; long long ans; long long BIN[N]; set<int> banned_set; set<pair<int, int> > seg; int banned[N]; long long cur_cnt; long long bin_sum[N]; bool lucky(int x) { if (x == 0) return 1; if (x % 10 != 4 && x % 10 != 7) return 0; return lucky(x / 10); } void add_segment(int l, int r) { cur_cnt += BIN[r - l + 1]; cur_cnt %= 5000000000000000000ll; } void remove_segment(int l, int r) { cur_cnt -= BIN[r - l + 1]; if (cur_cnt < 0) cur_cnt += 5000000000000000000ll; } void ban_position(int ps) { set<int>::iterator it; it = banned_set.lower_bound(ps); int r = (*it); --it; int l = (*it); remove_segment(l + 1, r - 1); if (l < ps - 1) add_segment(l + 1, ps - 1); if (r > ps + 1) add_segment(ps + 1, r - 1); banned_set.insert(ps); } void show_intervals() { set<pair<int, int> >::iterator it; for (it = seg.begin(); it != seg.end(); ++it) { pair<int, int> P = (*it); cout << P.first << << P.second << endl; } } int main() { ios_base::sync_with_stdio(0); for (int i = 1; i <= 100000; i++) BIN[i] = (i + 1) * 1ll * i / 2, BIN[i] %= 5000000000000000000ll; for (int i = 1; i <= 100000; i++) { bin_sum[i] = bin_sum[i - 1] + BIN[i]; bin_sum[i] %= 5000000000000000000ll; } cin >> n; for (int i = 1; i <= n; i++) { cin >> ar[i]; elements.insert(make_pair(ar[i], i)); if (lucky(ar[i])) { is_lucky[i] = 1; luck.push_back(i); } } next_lucky[n + 1] = n + 1; for (int i = n; i; --i) { if (is_lucky[i]) next_lucky[i] = i; else next_lucky[i] = next_lucky[i + 1]; } for (int i = 1; i <= n; i++) { int cnt1 = next_lucky[i] - i; ans += cnt1 * BIN[i - 1] % 5000000000000000000ll, ans %= 5000000000000000000ll; } for (int i = 1; i <= n; i++) { if (is_lucky[i]) prev_lucky[i] = i; else prev_lucky[i] = prev_lucky[i - 1]; } for (int i = 0; i < luck.size(); i++) { int id = luck[i]; seg.clear(); cur_cnt = 0; add_segment(1, id - 1); for (int j = 0; j < luck.size(); j++) banned[j] = 0; banned_set.clear(); banned_set.insert(id); banned_set.insert(0); for (int j = i; j < luck.size(); j++) { int id = luck[j]; int val = ar[id]; int pp = -1; while (true) { pair<int, int> P = make_pair(val, pp + 1); it = elements.lower_bound(P); if (it == elements.end()) break; pair<int, int> P2 = (*it); if (P2.first != P.first) break; if (P2.second >= luck[i]) break; if (banned_set.find(P2.second) != banned_set.end()) break; ban_position(P2.second); pp = P2.second; } int bound = n + 1; if (j + 1 < luck.size()) bound = luck[j + 1]; long long ways = cur_cnt; int prev = 0; if (i) prev = luck[i - 1]; ways = ways * (luck[i] - prev) % 5000000000000000000ll; set<int>::iterator it; it = banned_set.lower_bound(luck[i]); int Q1, Q2; if (it == banned_set.begin()) Q1 = 0; else { --it; Q1 = (*it); } Q2 = luck[i]; ways -= (BIN[Q2 - Q1 - 1]) * (luck[i] - prev) % 5000000000000000000ll; if (ways < 0) ways += 5000000000000000000ll; int cut; if (i == 0) cut = 0; else cut = luck[i - 1]; ways += bin_sum[Q2 - Q1 - 1] - bin_sum[cut - Q1 - 1]; ways %= 5000000000000000000ll; if (ways < 0) ways += 5000000000000000000ll; ways = ways * (bound - luck[j]) % 5000000000000000000ll; ; ans += ways; ans %= 5000000000000000000ll; } } cout << ans << endl; cin.get(); cin.get(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, z, x, c, sum, a[101][101], us[101][101]; char cc, stl; set<long long> s; void dfs(long long i, long long j) { if (a[i][j] == 0 || us[i][j] == 1 || i > n || j > m || i < 1 || j < 1) return; us[i][j] = 1; if (s.count(a[i][j]) == 0) sum++, s.insert(a[i][j]); if (a[i][j] == stl - A + 1) { dfs(i + 1, j); dfs(i - 1, j); dfs(i, j + 1); dfs(i, j - 1); } } int main() { cin >> n >> m >> stl; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> cc; if (cc != . ) a[i][j] = cc - A + 1; if (cc == stl) z = i, x = j; } } s.insert((int)stl - A + 1); dfs(z, x); cout << sum << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n, m; int a[20]; int main() { cin >> n >> m; for (int t, i = 1; i <= n; i++) { cin >> t; a[t]++; } int ans = 0; for (int i = 1; i <= m; i++) for (int j = i + 1; j <= m; j++) ans += a[i] * a[j]; cout << ans; } |
module project2_top (
input _CLOCK_27,
input _CLOCK_50,
input switch_mute,
output led_switch_mute,
input switch_marquee,
output led_switch_marquee,
input switch_ticking_sound,
output led_switch_ticking_sound,
inout _I2C_SDAT, // I2C Data
output _I2C_SCLK, // I2C Clock
inout _AUD_ADCLRCK, // Audio CODEC ADC LR Clock
inout _AUD_DACLRCK, // Audio CODEC DAC LR Clock
input _AUD_ADCDAT, // Audio CODEC ADC Data
output _AUD_DACDAT, // Audio CODEC DAC Data
inout _AUD_BCLK, // Audio CODEC Bit-Stream Clock
output _AUD_XCK, // Audio CODEC Chip Clock
output _TD_RESET, // TV Decoder Reset
// buttons and indicators
input start_pause_key,
output start_pause_led,
input lap_key,
output lap_led,
input reset_key,
output reset_led,
input clear_key,
output clear_led,
output timer_running,
output lcd_updating,
// 7-segment displays
output [6:0] m_sec_1, m_sec_0,
output [6:0] second_1, second_0,
output [6:0] minute_1, minute_0,
output [6:0] hour_1, hour_0,
// lcd module interface
output [7:0] lcd_data,
output lcd_rw, lcd_en, lcd_rs,
output lcd_on, lcd_blon,
output [10:0] marquee_led
);
genvar i;
/*
* Internal wires and registers.
*/
wire wire_global_reset;
wire [3:0] keys_nodb = { start_pause_key, lap_key, reset_key, clear_key };
wire [3:0] keys;
wire [6:0] seg_disp [0:3][0:1];
/*
* Global reset generation.
*/
reset_gen r0 (
.clock (_CLOCK_50),
.reset (wire_global_reset)
);
/*
* Debouncers.
*/
generate
for (i = 0; i < 4; i = i+1) begin: DB_BTN
debouncer db_key (
.clock (_CLOCK_50),
.key_in (keys_nodb[i]),
.active_low (1'b1),
.key_out (keys[i])
);
end
endgenerate
// preview the debounced output
assign { start_pause_led, lap_led, reset_led, clear_led } = keys;
// preview the switch output
assign { led_switch_marquee, led_switch_ticking_sound, led_switch_mute }
= { switch_marquee, switch_ticking_sound, switch_mute};
/*
* State machine.
*/
wire run_timer, reset_timer;
wire insert_value, clear_value;
wire timer_busy_wire;
key_logic_fsm fsm (
.clock (_CLOCK_50),
.reset (1'b0),
// input from the keys
.k (keys),
// internal busy state
.lcd_busy (lcd_busy),
.reg_busy (timer_busy_wire),
// timer control
.run_timer (run_timer),
.reset_timer (reset_timer),
// lcd control
.insert_value (insert_value),
.clear_value (clear_value)
);
assign timer_running = run_timer;
/*
* Internal timer logic.
*/
// 4 time units: hour, minute, second, m_sec
localparam time_units = 4;
wire [7*time_units-1:0] timestamp_flat;
internal_timer timer (
.clock (_CLOCK_50),
.run (run_timer),
.reset (reset_timer),
.timestamp (timestamp_flat),
.reg_busy (timer_busy_wire)
);
/*
* Expand the timestamp.
*/
wire [6:0] timestamp [0:3];
parameter [1:0] M_SEC = 2'd0,
SECOND = 2'd1,
MINUTE = 2'd2,
HOUR = 2'd3;
generate
for (i = 0; i < 4; i = i+1) begin: EXP_FLAT_TIMESTAMP
assign timestamp[i] = timestamp_flat[7*(i+1)-1 -: 7];
end
endgenerate
/*
* 7-segment display conversions.
*/
wire [3:0] bcd [0:3][0:1];
generate
for (i = 0; i < 4; i = i+1) begin: SEG_CONV
bin2bcd conv_bin (
.bin (timestamp[i]),
.bcd1 (bcd[i][1]),
.bcd0 (bcd[i][0])
);
bcd2seg conv_bcd1 (
.bcd (bcd[i][1]),
.blank (1'b0),
.active_low (1'b1),
.seven_segment (seg_disp[i][1])
);
bcd2seg conv_bcd0 (
.bcd (bcd[i][0]),
.blank (1'b0),
.active_low (1'b1),
.seven_segment (seg_disp[i][0])
);
end
endgenerate
assign {m_sec_0, m_sec_1} = {seg_disp[M_SEC][0], seg_disp[M_SEC][1]};
assign {second_0, second_1} = {seg_disp[SECOND][0], seg_disp[SECOND][1]};
assign {minute_0, minute_1} = {seg_disp[MINUTE][0], seg_disp[MINUTE][1]};
assign {hour_0, hour_1} = {seg_disp[HOUR][0], seg_disp[HOUR][1]};
/*
* Marquee Blinker LED Red
*/
generate
for (i = 0; i < 10; i = i+1) begin: MARQUEE
assign marquee_led[i] = switch_marquee &
((bcd[0][1] == i && ~ bcd[1][0][0]) || (bcd[0][1] == (10 - i) && bcd[1][0][0]));
end
endgenerate
assign marquee_led[10] = switch_marquee & (bcd[0][1] == 4'd0 && bcd[1][0][0]);
/*
* Flatten the BCD representations.
*/
wire [2*4*4-1:0] flat_bcd;
generate
for (i = 0; i < 4; i = i+1) begin: FLAT_BCD
assign flat_bcd[8*i +: 8] = {bcd[3-i][0], bcd[3-i][1]};
end
endgenerate
/*
* LCM driver.
*/
wire [7:0] lcd_data_wire;
wire [4:0] lcd_ctrl_wire;
assign lcd_data = lcd_data_wire;
assign {lcd_rw, lcd_en, lcd_rs, lcd_on, lcd_blon} = lcd_ctrl_wire;
lcd_bridge lcd_bridge (
.clock (_CLOCK_50),
.reset (wire_global_reset),
.insert (insert_value),
.new_record (flat_bcd),
.clear (clear_value),
.busy (lcd_busy),
// lcd module interface
.lcd_data (lcd_data_wire),
.lcd_ctrl (lcd_ctrl_wire)
);
assign lcd_updating = lcd_busy;
/*
* Synthesizer module.
*/
wire is_1sec = (bcd[0][1] == 4'b0000) && timer_running && switch_ticking_sound;
DE2_synthesizer synthesizer (
.CLOCK_27 (_CLOCK_27),
.CLOCK_50 (_CLOCK_50),
//////////////////// Push Button ////////////////////
.START_KEY1 (start_pause_key & lap_key & reset_key & ~is_1sec),
.START_KEY2 (clear_key),
//////////////////// DPDT Switch ////////////////////
.SW_MUTE (switch_mute),
//////////////////// I2C ////////////////////////////
.I2C_SDAT (_I2C_SDAT),
.I2C_SCLK (_I2C_SCLK),
//////////////// Audio CODEC ////////////////////////
.AUD_ADCLRCK (_AUD_ADCLRCK),
.AUD_ADCDAT (_AUD_ADCDAT),
.AUD_DACLRCK (_AUD_DACLRCK),
.AUD_DACDAT (_AUD_DACDAT),
.AUD_BCLK (_AUD_BCLK),
.AUD_XCK (_AUD_XCK),
.TD_RESET (_TD_RESET)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module select1 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("select1.mif"),
.C_INIT_FILE("select1.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(2071),
.C_READ_DEPTH_A(2071),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(2071),
.C_READ_DEPTH_B(2071),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.822999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void MACRO_VAR_Scan(T& t) { cin >> t; } template <typename First, typename... Rest> void MACRO_VAR_Scan(First& first, Rest&... rest) { cin >> first; MACRO_VAR_Scan(rest...); } template <typename T> void MACRO_VEC_ROW_Init(int n, T& t) { t.resize(n); } template <typename First, typename... Rest> void MACRO_VEC_ROW_Init(int n, First& first, Rest&... rest) { first.resize(n); MACRO_VEC_ROW_Init(n, rest...); } template <typename T> void MACRO_VEC_ROW_Scan(int p, T& t) { cin >> t[p]; } template <typename First, typename... Rest> void MACRO_VEC_ROW_Scan(int p, First& first, Rest&... rest) { cin >> first[p]; MACRO_VEC_ROW_Scan(p, rest...); } void _main(); signed main() { cin.tie(0); ios::sync_with_stdio(false); _main(); } inline long long toInt(std::string s) { long long v; std::istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } template <class T> inline T sqr(T x) { return x * x; } template <typename A, typename B> inline void chmin(A& a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A& a, B b) { if (a < b) a = b; } long long qp(long long a, long long b) { long long ans = 1ll; do { if (b & 1) ans = 1ll * ans * a; a = 1ll * a * a; } while (b >>= 1); return ans; } long long qpmod(long long a, long long b, long long mo) { long long ans = 1ll; do { if (b & 1) ans = 1ll * ans * a % mo; a = 1ll * a * a % mo; } while (b >>= 1); return ans; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline bool valid(int x, int h) { return 0 <= x && x < h; } const double EPS = 1e-10; const double PI = acos(-1.0); const int INF = (int)(1e9) + 7; const long long MOD = (long long)(1e9) + 7; const long long MOD2 = (long long)(1e18) + 9; const long long INF2 = (long long)(1e18); const long long INTMAX = (0x7FFFFFFFL); const long long LLMAX = (0x7FFFFFFFFFFFFFFFL); const int N4 = (int)1e4 + 10; const int N5 = (int)1e5 + 10; int dx[8] = {1, 0, -1, 0, 1, -1, -1, 1}; int dy[8] = {0, 1, 0, -1, -1, -1, 1, 1}; long long ans, cnt, ret, cur, f; void _main() { map<int, int> ma; int n; MACRO_VAR_Scan(n); ; vector<int> v(n); for (auto& i : v) cin >> i; ; for (auto& x : v) ma[x]++; for (auto& x : ma) chmax(ret, x.second); cout << ret << endl; ; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int mini, c; const int MAXN = 2e3 + 3; long long dp[2][MAXN][MAXN]; long long go(int lft, int cur, bool f) { if (lft == 0 and !f) return 1; if (dp[f][lft][cur] != -1) return dp[f][lft][cur]; long long ret = 0; if (f) { if (mini >= 0 and lft >= c + cur) ret += go(lft, cur + c, false); if (ret >= MOD) ret -= MOD; if (mini < 0 and abs(mini) <= cur and lft >= c + cur) ret += go(lft, cur + c, false); if (ret >= MOD) ret -= MOD; if (lft) ret += go(lft - 1, cur + 1, f); if (ret >= MOD) ret -= MOD; if (cur != 0 and lft) ret += go(lft - 1, cur - 1, f); if (ret >= MOD) ret -= MOD; } else { if (cur != 0 and lft) ret += go(lft - 1, cur - 1, f); if (ret >= MOD) ret -= MOD; if (lft - 1 >= cur + 1 and lft) ret += go(lft - 1, cur + 1, f); if (ret >= MOD) ret -= MOD; } return dp[f][lft][cur] = ret; } int main() { int n, m; cin >> n >> m; string str; cin >> str; mini = 1e9; c = 0; for (int i = 0; i < ((int)str.size()); i++) { if (str[i] == ( ) ++c; else --c; mini = min(mini, c); } memset(dp, -1, sizeof(dp)); cout << go(n - m, 0, true) << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 14:48:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_pll_0_0 -prefix
// system_vga_pll_0_0_ system_vga_pll_0_0_stub.v
// Design : system_vga_pll_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_pll,Vivado 2016.4" *)
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 10005; long long n, m, a[maxn], b[maxn]; int k; long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } long long exgcd(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1, y = 0; return a; } long long r = exgcd(b, a % b, x, y), x0 = x; x = y; y = x0 - (a / b) * y; return r; } long long CRT(long long *m, long long *a) { long long lcm = 1, X = m[1], Y = a[1]; for (int i = 1; i <= k; i++) lcm = lcm / gcd(lcm, m[i]) * m[i]; for (int i = 2; i <= k; i++) { long long A = X, B = m[i], d, x, y, c = a[i] - Y; d = exgcd(A, B, x, y); if (c % d) return -1; long long mod = m[i] / d; long long K = ((x * c / d) % mod + mod) % mod; Y = X * K + Y; X = X * m[i] / d; } if (Y == 0) return lcm; return Y; } bool check() { long long I = CRT(a, b), J; if (I > n || I <= 0) return 0; for (int i = 1; i <= k; i++) b[i] = 1 - i; J = CRT(a, b); if (J + k - 1 > m || J <= 0) return 0; for (int i = 1; i <= k; i++) if (gcd(I, J + i - 1) != a[i]) return 0; return 1; } int main() { cin >> n >> m >> k; for (int i = 1; i <= k; i++) cin >> a[i]; if (check()) cout << YES << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void swap(int ar[], int i, int j) { int aux = ar[j]; ar[j] = ar[i]; ar[i] = ar[j]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; int Ma[n][m]; int Mb[n][m]; for (int i = 0; i < n; i++) for (int k = 0; k < m; k++) cin >> Ma[i][k]; for (int i = 0; i < n; i++) for (int k = 0; k < m; k++) { int aux; cin >> aux; if (aux <= Ma[i][k]) { int aux2 = Ma[i][k]; Ma[i][k] = aux; Mb[i][k] = aux2; } else Mb[i][k] = aux; } for (int i = 0; i < n; i++) for (int k = 1; k < m; k++) if (Ma[i][k] <= Ma[i][k - 1] || Mb[i][k] <= Mb[i][k - 1]) { cout << Impossible ; return 0; } for (int k = 0; k < m; k++) for (int i = 1; i < n; i++) if (Ma[i][k] <= Ma[i - 1][k] || Mb[i][k] <= Mb[i - 1][k]) { cout << Impossible ; return 0; } cout << Possible ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long arr[330]; set<long long> st; map<long long, bool> mp; int main() { long long t, n, i, j, k, l, m; ios_base::sync_with_stdio(0); cin.tie(0); long long p; cin >> t; while (t--) { cin >> n; for (i = 1; i <= n; i++) cin >> arr[i], mp[arr[i]] = 1; sort(arr + 1, arr + n + 1); i = 1, j = n; while (i <= j) { long long op = arr[i] * arr[j]; st.insert(op); i++; j--; } if (st.size() == 1) { bool flag = 1; long long ans = *(st.begin()); for (i = 2; i <= sqrt(ans); i++) { if (ans % i == 0) { if (mp.find(i) == mp.end() || mp.find(ans / i) == mp.end()) flag = false; } } if (flag) cout << *(st.begin()) << n ; else cout << -1 << n ; } else cout << -1 << n ; st.clear(); mp.clear(); } return 0; } |
module trng_apbif (
//SFRs read values
output reg sfr_CTRL_ENABLE,
output reg sfr_CTRL_READY,
output reg sfr_CTRL_PP,
output reg sfr_CTRL_FIFO,
output reg [32-1:0] sfr_RNDDAT,
output reg [32-1:0] sfr_PPCONF,
output reg [32-1:0] sfr_SRCCONF,
output reg [128-1:0] sfr_SRCINIT,
output reg [32-1:0] sfr_SPYSEL,
//signals for SFRs updated by hardware or read/write sensitive
input wire sfr_CTRL_READY_wr,
input wire sfr_CTRL_READY_wren,
input wire [32-1:0] sfr_RNDDAT_wr,
input wire sfr_RNDDAT_wren,
output reg sfr_RNDDAT_read,
//APB inputs
input wire i_clk,
input wire i_apb_clk_en,
input wire PRESETn,
input wire PSEL,
input wire [11:0] PADDR,
input wire PENABLE,
input wire PWRITE,
input wire [3:0] PSTRB,
input wire [31:0] PWDATA,
//APB outputs
output reg [31:0] PRDATA,
output reg PREADY,
output reg PSLVERR
);
//bitfields mapping to full SFR words
wire [32-1:0] sfr_CTRL = {{28{1'b0}}
,sfr_CTRL_FIFO
,sfr_CTRL_PP
,sfr_CTRL_READY
,sfr_CTRL_ENABLE
};
wire sfr_valid_access = PSEL & (PADDR < 36);
assign PSLVERR = 1'b0;
assign PREADY = 1'b1;
wire sfr_write_access = sfr_valid_access & PENABLE & PWRITE & i_apb_clk_en;
wire sfr_read_access = sfr_valid_access & ~PWRITE;
wire sfr_read_access_1st_cycle = sfr_read_access & ~PENABLE;
wire sfr_read_access_2nd_cycle = sfr_read_access & PENABLE;
reg [9:0] word_address;
always @(posedge i_clk) if(i_apb_clk_en) word_address <= PADDR[11:2];
//////////////////////////////////////////////////////////////////////////////////////////////////
// Read registers
//////////////////////////////////////////////////////////////////////////////////////////////////
reg read_gate;//high during 1 cycle of i_clk
always @(posedge i_clk) begin
read_gate <= i_apb_clk_en & sfr_read_access_1st_cycle;
end
reg [31:0] sfr_read_value;
always @* begin
if(read_gate) PRDATA = sfr_read_value;
end
reg sfr_RNDDAT_read_apb;
always @* sfr_RNDDAT_read = read_gate & sfr_RNDDAT_read_apb;
always @* begin
sfr_read_value = 32'hDEADBEEF;
{sfr_RNDDAT_read_apb} = {1{1'b0}};
if (sfr_read_access) begin
case(word_address)
0: sfr_read_value = sfr_CTRL;
1: begin
sfr_read_value = sfr_RNDDAT;
sfr_RNDDAT_read_apb = 1'b1;
end
2: sfr_read_value = sfr_PPCONF;
3: sfr_read_value = sfr_SRCCONF;
4: sfr_read_value = sfr_SRCINIT[0*32+:32];
5: sfr_read_value = sfr_SRCINIT[1*32+:32];
6: sfr_read_value = sfr_SRCINIT[2*32+:32];
7: sfr_read_value = sfr_SRCINIT[3*32+:32];
8: sfr_read_value = sfr_SPYSEL;
endcase
end
end
//////////////////////////////////////////////////////////////////////////////////////////////////
// Write registers
//////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge i_clk or negedge PRESETn) begin
if(~PRESETn) begin
sfr_CTRL_ENABLE <= 0;
sfr_CTRL_READY <= 0;
sfr_CTRL_PP <= 0;
sfr_CTRL_FIFO <= 0;
sfr_RNDDAT <= 0;
sfr_PPCONF <= 0;
sfr_SRCCONF <= 0;
sfr_SRCINIT <= 0;
sfr_SPYSEL <= 0;
end else begin
if(sfr_write_access) begin
case(word_address)
0: begin
if (PSTRB[0]) sfr_CTRL_ENABLE <= PWDATA[0*8+0+:1];
if (PSTRB[0]) sfr_CTRL_PP <= PWDATA[0*8+2+:1];
if (PSTRB[0]) sfr_CTRL_FIFO <= PWDATA[0*8+3+:1];
end
1: begin
end
2: begin
if (PSTRB[0]) sfr_PPCONF[0*8+:8] <= PWDATA[0*8+:8];
if (PSTRB[1]) sfr_PPCONF[1*8+:8] <= PWDATA[1*8+:8];
if (PSTRB[2]) sfr_PPCONF[2*8+:8] <= PWDATA[2*8+:8];
if (PSTRB[3]) sfr_PPCONF[3*8+:8] <= PWDATA[3*8+:8];
end
3: begin
if (PSTRB[0]) sfr_SRCCONF[0*8+:8] <= PWDATA[0*8+:8];
if (PSTRB[1]) sfr_SRCCONF[1*8+:8] <= PWDATA[1*8+:8];
if (PSTRB[2]) sfr_SRCCONF[2*8+:8] <= PWDATA[2*8+:8];
if (PSTRB[3]) sfr_SRCCONF[3*8+:8] <= PWDATA[3*8+:8];
end
4: begin
if (PSTRB[0]) sfr_SRCINIT[0*32+0*8+:8] <= PWDATA[0*8+:8];
if (PSTRB[1]) sfr_SRCINIT[0*32+1*8+:8] <= PWDATA[1*8+:8];
if (PSTRB[2]) sfr_SRCINIT[0*32+2*8+:8] <= PWDATA[2*8+:8];
if (PSTRB[3]) sfr_SRCINIT[0*32+3*8+:8] <= PWDATA[3*8+:8];
end
5: begin
if (PSTRB[0]) sfr_SRCINIT[1*32+0*8+:8] <= PWDATA[0*8+:8];
if (PSTRB[1]) sfr_SRCINIT[1*32+1*8+:8] <= PWDATA[1*8+:8];
if (PSTRB[2]) sfr_SRCINIT[1*32+2*8+:8] <= PWDATA[2*8+:8];
if (PSTRB[3]) sfr_SRCINIT[1*32+3*8+:8] <= PWDATA[3*8+:8];
end
6: begin
if (PSTRB[0]) sfr_SRCINIT[2*32+0*8+:8] <= PWDATA[0*8+:8];
if (PSTRB[1]) sfr_SRCINIT[2*32+1*8+:8] <= PWDATA[1*8+:8];
if (PSTRB[2]) sfr_SRCINIT[2*32+2*8+:8] <= PWDATA[2*8+:8];
if (PSTRB[3]) sfr_SRCINIT[2*32+3*8+:8] <= PWDATA[3*8+:8];
end
7: begin
if (PSTRB[0]) sfr_SRCINIT[3*32+0*8+:8] <= PWDATA[0*8+:8];
if (PSTRB[1]) sfr_SRCINIT[3*32+1*8+:8] <= PWDATA[1*8+:8];
if (PSTRB[2]) sfr_SRCINIT[3*32+2*8+:8] <= PWDATA[2*8+:8];
if (PSTRB[3]) sfr_SRCINIT[3*32+3*8+:8] <= PWDATA[3*8+:8];
end
8: begin
if (PSTRB[0]) sfr_SPYSEL[0*8+:8] <= PWDATA[0*8+:8];
if (PSTRB[1]) sfr_SPYSEL[1*8+:8] <= PWDATA[1*8+:8];
if (PSTRB[2]) sfr_SPYSEL[2*8+:8] <= PWDATA[2*8+:8];
if (PSTRB[3]) sfr_SPYSEL[3*8+:8] <= PWDATA[3*8+:8];
end
endcase
end else begin //hardware set or clear (priority to software)
//TODO: ::hw_set_ports
//TODO: ::hw_clear_ports
end
if (sfr_CTRL_READY_wren) sfr_CTRL_READY <= sfr_CTRL_READY_wr;
if (sfr_RNDDAT_wren) sfr_RNDDAT <= sfr_RNDDAT_wr;
end
end
endmodule
/*
? 288 trng
0 32 CTRL
0 1 ENABLE
1 1 READY {read_only 1} {set_by_hardware 1} {cleared_by_hardware 1}
2 1 PP
3 1 FIFO
32 32 RNDDAT {read_only 1} {set_by_hardware 1} {cleared_by_hardware 1} {read_sensitive 1}
64 32 PPCONF
96 32 SRCCONF
128 128 SRCINIT
256 32 SPYSEL
//signals declaration, instanciation template:
//SFRs read values
wire sfr_CTRL_ENABLE;
wire sfr_CTRL_READY;
wire sfr_CTRL_PP;
wire sfr_CTRL_FIFO;
wire [32-1:0] sfr_RNDDAT;
wire [32-1:0] sfr_PPCONF;
wire [32-1:0] sfr_SRCCONF;
wire [128-1:0] sfr_SRCINIT;
wire [32-1:0] sfr_SPYSEL;
//signals for SFRs updated by hardware or read/write sensitive
reg sfr_CTRL_READY_wr;
reg sfr_CTRL_READY_wren;
reg [32-1:0] sfr_RNDDAT_wr;
reg sfr_RNDDAT_wren;
wire sfr_RNDDAT_read;
u_trng_apbif trng_apbif (
.sfr_CTRL_ENABLE(sfr_CTRL_ENABLE),
.sfr_CTRL_READY(sfr_CTRL_READY),
.sfr_CTRL_PP(sfr_CTRL_PP),
.sfr_CTRL_FIFO(sfr_CTRL_FIFO),
.sfr_RNDDAT(sfr_RNDDAT),
.sfr_PPCONF(sfr_PPCONF),
.sfr_SRCCONF(sfr_SRCCONF),
.sfr_SRCINIT(sfr_SRCINIT),
.sfr_SPYSEL(sfr_SPYSEL),
.sfr_CTRL_READY_wr(sfr_CTRL_READY_wr),
.sfr_CTRL_READY_wren(sfr_CTRL_READY_wren),
.sfr_RNDDAT_wr(sfr_RNDDAT_wr),
.sfr_RNDDAT_wren(sfr_RNDDAT_wren),
.sfr_RNDDAT_read(sfr_RNDDAT_read),
.i_clk(i_clk),
.i_apb_clk_en(i_apb_clk_en),
.PRESETn(PRESETn),
.PSEL(PSEL),
.PADDR(PADDR),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PSTRB(PSTRB),
.PWDATA(PWDATA),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR)
);
*/
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; pair<char, bool> ar[100][100]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> ar[i][j].first; ar[i][j].second = false; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int k = 0; k < m; k++) { if (k == j) continue; if (ar[i][j].first == ar[i][k].first) { ar[i][j].second = true; ar[i][k].second = true; } } for (int k = 0; k < n; k++) { if (k == i) continue; if (ar[i][j].first == ar[k][j].first) { ar[i][j].second = true; ar[k][j].second = true; } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (ar[i][j].second == false) cout << ar[i][j].first; } } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y) { if (y == 0) return 1; else { long long result = power(x, y / 2) % 1000000007; if (y % 2 == 0) return (result % 1000000007 * result % 1000000007) % 1000000007; else return (result % 1000000007 * result % 1000000007 * x % 1000000007) % 1000000007; } } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } void solve() { long long n, k; cin >> n >> k; vector<long long> v(n); for (long long i = 0; i < n; i++) { cin >> v[i]; } long long start = -1; long long sum = 0; long long div = n / k; long long minsum = INT_MAX; for (long long i = 0; i < k; i++) { sum = 0; for (long long j = i; j < n; j = j + k) { sum = sum + v[j]; } if (sum < minsum) { minsum = sum; start = i + 1; } } cout << start; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c = 0; cin >> a; for (int i = 0; i < a; ++i) { cin >> b; if (b == 1) { c = 1; } } if (c == 0) { cout << EASY n ; } else { cout << HARD n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, mx = 0, my = (1 << 31) - 1, m2x = 0, m2y = (1 << 31) - 1, a, b; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d , &a, &b); mx = max(mx, a); my = min(my, b); } scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d , &a, &b); m2x = max(m2x, a); m2y = min(m2y, b); } int res = 0; if (m2x > my) res = max(res, m2x - my); if (mx > m2y) res = max(res, mx - m2y); printf( %d n , res); return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr4 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [3:0] Q,
input C0,
input C1,
input CE,
input [3:0] D0,
input [3:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr2 (
.Q(Q[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[2]),
.D1(D1[2]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr3 (
.Q(Q[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[3]),
.D1(D1[3]),
.R(R),
.S(S)
);
endmodule
|
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,da_ps7_cnt=1}" *)
module system
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
GND GND
(.G(GND_1));
system_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.TTC0_CLK0_IN(GND_1),
.TTC0_CLK1_IN(GND_1),
.TTC0_CLK2_IN(GND_1));
endmodule
|
#include <bits/stdc++.h> using namespace std; char ch[200][200]; int rp[200], cp[200]; int main() { int n; while (cin >> n) { memset(rp, 0, sizeof(rp)); memset(cp, 0, sizeof(cp)); for (int i = 1; i <= n; i++) { scanf( %s , ch[i] + 1); for (int j = 1; j <= n; j++) if (ch[i][j] == . ) rp[i] = 1; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (ch[j][i] == . ) cp[i] = 1; bool rok, cok; rok = cok = 0; int k; for (k = 1; k <= n; k++) if (rp[k] == 0) break; if (k > n) rok = 1; for (k = 1; k <= n; k++) if (cp[k] == 0) break; if (k > n) cok = 1; if (rok == 0 && cok == 0) { puts( -1 ); continue; } if (rok) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (ch[i][j] == . ) { cout << i << << j << endl; break; } } } else { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (ch[j][i] == . ) { cout << j << << i << endl; break; } } } } return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:31 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_stub.v
// Design : ip_design_zed_audio_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "i2s_ctrl,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(BCLK, LRCLK, SDATA_I, SDATA_O, S_AXI_ACLK,
S_AXI_ARESETN, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WVALID,
S_AXI_BREADY, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_RREADY, S_AXI_ARREADY, S_AXI_RDATA,
S_AXI_RRESP, S_AXI_RVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_AWREADY)
/* synthesis syn_black_box black_box_pad_pin="BCLK,LRCLK,SDATA_I,SDATA_O,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[31:0],S_AXI_AWVALID,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_BREADY,S_AXI_ARADDR[31:0],S_AXI_ARVALID,S_AXI_RREADY,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_AWREADY" */;
output BCLK;
output LRCLK;
input SDATA_I;
output SDATA_O;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input [31:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input [31:0]S_AXI_WDATA;
input [3:0]S_AXI_WSTRB;
input S_AXI_WVALID;
input S_AXI_BREADY;
input [31:0]S_AXI_ARADDR;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_ARREADY;
output [31:0]S_AXI_RDATA;
output [1:0]S_AXI_RRESP;
output S_AXI_RVALID;
output S_AXI_WREADY;
output [1:0]S_AXI_BRESP;
output S_AXI_BVALID;
output S_AXI_AWREADY;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void splitstr(const string &s, vector<T> &out) { istringstream in(s); out.clear(); copy(istream_iterator<T>(in), istream_iterator<T>(), back_inserter(out)); } template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } static void redirect(int argc, const char **argv) { ios::sync_with_stdio(false); cin.tie(NULL); if (argc > 1) { static filebuf f; f.open(argv[1], ios::in); cin.rdbuf(&f); if (!cin) { cerr << Failed to open << argv[1] << << endl; exit(1); } } if (argc > 2) { static filebuf f; f.open(argv[2], ios::out | ios::trunc); cout.rdbuf(&f); if (!cout) { cerr << Failed to open << argv[2] << << endl; } } } class UnionFind { private: mutable std::vector<int> parent; public: explicit UnionFind(int size = 0) : parent(size, -1) {} int size() const { return parent.size(); } int find(int x) const { assert(x >= 0 && x < size()); int y = x; while (parent[y] >= 0) y = parent[y]; while (parent[x] >= 0) { int nxt = parent[x]; parent[x] = y; x = nxt; } return y; } bool merge(int x, int y) { x = find(x); y = find(y); if (x == y) return false; if (-parent[x] > -parent[y]) std::swap(x, y); parent[y] += parent[x]; parent[x] = y; return true; } int component_size(int x) const { return -parent[find(x)]; } }; template <typename T, typename C, T Modulus> class MR { private: struct tag_plus {}; struct tag_minus {}; struct tag_good {}; T value; static_assert(std::numeric_limits<C>::max() / Modulus / Modulus > 0, compute type is too small ); static_assert(Modulus < std::numeric_limits<T>::max() / 2, storage type is too small ); void reduce(tag_plus) { if (value >= Modulus) value -= Modulus; } void reduce(tag_minus) { if (value < 0) value += Modulus; } void reduce(tag_good) {} public: static const T modulus = Modulus; MR() : value(0) {} MR(C value) : value(value % Modulus) { reduce(tag_minus()); } template <typename tag_t> MR(T value, tag_t tag) : value(value) { reduce(tag); } MR &operator=(C value) { this->value = value % Modulus; reduce(tag_minus()); return *this; } MR operator+(MR b) const { return MR(value + b.value, tag_plus()); } MR operator-(MR b) const { return MR(value - b.value, tag_minus()); } MR operator*(MR b) const { return MR(C(value) * C(b.value) % Modulus, tag_good()); } MR operator-() const { return MR(-value, tag_minus()); } MR &operator+=(MR b) { value += b.value; reduce(tag_plus()); return *this; } MR &operator-=(MR b) { value -= b.value; reduce(tag_minus()); return *this; } MR &operator*=(MR b) { value = C(value) * C(b.value) % Modulus; return *this; } bool operator==(MR b) const { return value == b.value; } bool operator!=(MR b) const { return value != b.value; } T get() const { return value; } }; static inline int bit(int x) { return 1 << x; } static int min_colours(const vector<int> &edges) { int N = ((long long)(edges).size()); int M = 1 << N; vector<MR<int, long long, 1000000009> > a(M); a[0] = 1; for (int i = 1; i < M; i++) { int v = __builtin_ctz(i); a[i] = a[i & ~bit(v)] + a[i & ~bit(v) & ~edges[v]]; } vector<MR<int, long long, 1000000009> > ak(M, MR<int, long long, 1000000009>(1)); for (int k = 1;; k++) { MR<int, long long, 1000000009> sum = 0; for (int i = 0; i < M; i++) { ak[i] *= a[i]; sum += __builtin_parity(i) ? ak[i] : -ak[i]; } if (sum.get() != 0) return k; } } int main(int argc, const char **argv) { redirect(argc, argv); int N; cin >> N; vector<string> matrix(N); UnionFind scc(N); for (int i = 0; i < N; i++) { cin >> matrix[i]; for (int j = 0; j < i; j++) if (matrix[i][j] == A ) scc.merge(i, j); } vector<pair<int, int> > comps; for (int i = 0; i < N; i++) if (i == scc.find(i)) comps.emplace_back(scc.component_size(i), i); sort(begin(comps), end(comps)); reverse(begin(comps), end(comps)); vector<int> cmap(N); int C = ((long long)(comps).size()); int C2 = 0; while (C2 < C && comps[C2].first >= 2) C2++; for (int i = 0; i < C; i++) cmap[comps[i].second] = i; C = C2; vector<int> edge(C); for (int i = 0; i < N; i++) for (int j = 0; j < i; j++) if (matrix[i][j] == X ) { int p = cmap[scc.find(i)]; int q = cmap[scc.find(j)]; if (p == q) { cout << -1 n ; return 0; } if (p < C && q < C) { edge[p] |= bit(q); edge[q] |= bit(p); } } int mc = C2 ? min_colours(edge) : 0; cout << N - 1 + mc << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long Ins, Del, Rep, Exc; string A; string B; int lenA, lenB; long long DP[4001][4001]; int posA[4001][26]; int posB[4001][26]; int main() { ios::sync_with_stdio(false); while (cin >> Ins >> Del >> Rep >> Exc) { cin >> A >> B; A = . + A; B = . + B; lenA = A.length() - 1; lenB = B.length() - 1; memset(posA, 0xff, sizeof(posA)); memset(posB, 0xff, sizeof(posB)); for (int i = 0; i < 26; i++) { for (int j = 1; j <= lenB; j++) if (B[j] == i + a ) posB[j][i] = j; else posB[j][i] = posB[j - 1][i]; for (int j = 1; j <= lenA; j++) if (A[j] == i + a ) posA[j][i] = j; else posA[j][i] = posA[j - 1][i]; } DP[0][0] = 0; for (int i = 0; i <= lenA; i++) for (int j = 0; j <= lenB; j++) if (i + j > 0) { DP[i][j] = 1000000000000000000LL; if (A[i] == B[j]) DP[i][j] = DP[i - 1][j - 1]; if (i >= 1 && j >= 1) DP[i][j] = min(DP[i][j], DP[i - 1][j - 1] + Rep); if (i >= 1) DP[i][j] = min(DP[i][j], DP[i - 1][j] + Del); if (j >= 1) DP[i][j] = min(DP[i][j], DP[i][j - 1] + Ins); int u = posA[i][B[j] - a ]; int v = posB[j][A[i] - a ]; if (u > 0 && v > 0 && u < i && v < j) DP[i][j] = min(DP[i][j], DP[u - 1][v - 1] + Exc + Ins * (j - v - 1) + Del * (i - u - 1)); } cout << DP[lenA][lenB] << endl; } return 0; } |
/*
* plle2_base.v: Simulates the PLLE2_BASE pll of the xilinx 7 series. This
* is just a wrapper around the actual logic found in pll.v
* author: Till Mahlburg
* year: 2019-2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
/* A reference for the interface can be found in Xilinx UG953 page 509ff */
module PLLE2_BASE #(
/* not implemented */
parameter BANDWIDTH = "OPTIMIZED",
parameter CLKFBOUT_MULT = 5,
parameter CLKFBOUT_PHASE = 0.0,
/* is ignored, but should be set */
parameter CLKIN1_PERIOD = 0.0,
parameter CLKOUT0_DIVIDE = 1,
parameter CLKOUT1_DIVIDE = 1,
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter CLKOUT0_DUTY_CYCLE = 0.5,
parameter CLKOUT1_DUTY_CYCLE = 0.5,
parameter CLKOUT2_DUTY_CYCLE = 0.5,
parameter CLKOUT3_DUTY_CYCLE = 0.5,
parameter CLKOUT4_DUTY_CYCLE = 0.5,
parameter CLKOUT5_DUTY_CYCLE = 0.5,
parameter CLKOUT0_PHASE = 0.0,
parameter CLKOUT1_PHASE = 0.0,
parameter CLKOUT2_PHASE = 0.0,
parameter CLKOUT3_PHASE = 0.0,
parameter CLKOUT4_PHASE = 0.0,
parameter CLKOUT5_PHASE = 0.0,
parameter DIVCLK_DIVIDE = 1,
/* both not implemented */
parameter REF_JITTER1 = 0.0,
parameter STARTUP_WAIT = "FALSE",
/* Setting the FPGA model and speed grade allows a more realistic
* simulation. Default values are the most restrictive */
parameter FPGA_TYPE = "ARTIX",
parameter SPEED_GRADE = "-1")(
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
/* PLL feedback output. */
output CLKFBOUT,
output LOCKED,
input CLKIN1,
/* PLL feedback input. Is ignored in this implementation, but should be connected to CLKFBOUT for internal feedback. */
input CLKFBIN,
/* Used to power down instatiated but unused PLLs */
input PWRDWN,
input RST);
wire [15:0] DO;
wire DRDY;
pll #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(0.000),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.REF_JITTER2(0.010),
.STARTUP_WAIT(STARTUP_WAIT),
.COMPENSATION("ZHOLD"),
.MODULE_TYPE("PLLE2_BASE"),
.FPGA_TYPE(FPGA_TYPE),
.SPEED_GRADE(SPEED_GRADE))
plle2_base (
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKFBOUT(CLKFBOUT),
.LOCKED(LOCKED),
.CLKIN1(CLKIN1),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.PWRDWN(PWRDWN),
.RST(RST),
.CLKFBIN(CLKFBIN),
.DADDR(7'h00),
.DCLK(1'b0),
.DEN(1'b0),
.DWE(1'b0),
.DI(16'h0),
.DO(DO),
.DRDY(DRDY)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; #define FAST ios_base::sync_with_stdio(false); cin.tie(NULL); #define prs(n) cout << fixed << setprecision(n) #define ll long long #define db double #define fo(i,m,n) for(int i = m; i <= n; i++) #define fob(i,m,n) for(int i = n; i >= m; i--) typedef pair<int, int> ii; typedef vector<ii> vii; typedef vector<vii> vvii; const int maxi=INT_MAX; const int _x[]={0,0,1,-1}; const int _y[]={1,-1,0,0}; ll n, ans, l[200007], r[200007], dp[200007][2]; vector <ll> a[200007]; void input() { int u, v; cin >> n; for (int i = 1; i <= n; i++) { cin >> l[i] >> r[i], a[i].resize(0); dp[i][1] = dp[i][0] = 0; } for (int i = 1; i < n ; i++) { cin >> u >> v; a[u].push_back(v); a[v].push_back(u); } } void dfs(int u, int f) { for (int i:a[u]) { if (i != f) { dfs(i,u); dp[u][0] += max(dp[i][0] + abs(l[u] - l[i]), dp[i][1] + abs(l[u] - r[i])); dp[u][1] += max(dp[i][0] + abs(r[u] - l[i]), dp[i][1] + abs(r[u] - r[i])); } } } void solve() { dfs(1,0); ans = max(dp[1][0], dp[1][1]); } int main() { FAST //freopen( a.INP , r , stdin); //freopen( a.OUT , w , stdout); int t; cin >> t; while (t--) { input(); solve(); cout << ans << n ; } return 0; } |
//==============================================================================
// File: $URL: svn+ssh:///public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/ParityGen.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2003-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//------------------------------------------------------------------------------
// Module: ParityGen
// Desc: RS232/16550 selectable parity bit generator.
// Params: Parity:
// 0: None
// 1: Odd
// 2: Even
// 3: Mark
// 4: Space
// Width: Input width (in bits)
//------------------------------------------------------------------------------
module ParityGen(In, Out);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Parity = 0,
Width = 8;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// I/O
//--------------------------------------------------------------------------
input [Width-1:0] In;
output reg Out;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Parity Computation
//--------------------------------------------------------------------------
always @ (In) begin
case (Parity)
1: Out = ~^In;
2: Out = ^In;
3: Out = 1;
4: Out = 0;
default: Out = 1'b0;
endcase
end
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------ |
#include <bits/stdc++.h> using namespace std; int main() { int x, y, a = 0; cin >> x >> y; for (int i = 1; i <= x; i++) { if (i % 2 == 0) { if (a == 0) { for (int k = 0; k < y - 1; k++) { cout << . ; } cout << # << endl; a++; } else { a = 0; cout << # ; for (int k = 0; k < y - 1; k++) { if (k == y - 2) { cout << . << endl; } else { cout << . ; } } } } else { for (int j = 0; j < y; j++) { if (j == y - 1) { cout << # << endl; } else { cout << # ; } } } } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using std::bitset; using namespace std; int g[302][302][302], f[302][302]; int s[10]; int n, ans; void updateg(int a, int b, int c) { int i, j, tem, t; for (i = c + 1; i < 300; i++) { g[a][b][i] = 1; g[a][c][i] = 1; g[b][c][i] = 1; } for (i = b + 1; i <= c; i++) { g[a][i][c] = 1; g[b][i][c] = 1; } for (i = a + 1; i <= b; i++) g[i][b][c] = 1; for (t = 1; c + t < 300; t++) g[a + t][b + t][c + t] = 1; } void updatef(int a, int b) { int i, j, tem, t; for (i = b + 1; i < 300; i++) { f[a][i] = 1; f[b][i] = 1; } for (i = a + 1; i <= b; i++) f[i][b] = 1; for (t = 1; b + t < 300; t++) f[a + t][b + t] = 1; } void init() { int i, j, tem; memset(g, -1, sizeof(g)); ; int a, b, c; for (a = 0; a < 300; a++) for (b = a; b < 300; b++) for (c = b; c < 300; c++) { if (g[a][b][c] == -1) { g[a][b][c] = 0; updateg(a, b, c); } } memset(f, -1, sizeof(f)); ; for (a = 0; a < 300; a++) for (b = a; b < 300; b++) { if (f[a][b] == -1) { f[a][b] = 0; updatef(a, b); } } } int main() { int i, j, tem; init(); while (scanf( %d , &n) != EOF) { memset(s, 0, sizeof(s)); ; for (i = 1; i <= n; i++) scanf( %d , &s[i]); if (n == 1) { if (s[1] != 0) printf( BitLGM n ); else printf( BitAryo n ); } else if (n == 2) { if (s[1] > s[2]) swap(s[1], s[2]); if (f[s[1]][s[2]] == 1) printf( BitLGM n ); else printf( BitAryo n ); } else { sort(s + 1, s + 1 + 3); if (g[s[1]][s[2]][s[3]] == 1) printf( BitLGM n ); else printf( BitAryo n ); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_4_V
`define SKY130_FD_SC_HD__EINVP_4_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvp_4 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvp_4 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O211A_BEHAVIORAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; void getint(int &v) { char ch, fu = 0; for (ch = * ; (ch < 0 || ch > 9 ) && ch != - ; ch = getchar()) ; if (ch == - ) fu = 1, ch = getchar(); for (v = 0; ch >= 0 && ch <= 9 ; ch = getchar()) v = v * 10 + ch - 0 ; if (fu) v = -v; } int main() { int maxmax = 0, max, x, sum = 0, n, m; long long int sumsum = 0; getint(n); if (n == 1) printf( %d n , 0), exit(0); for (int i = 0; i < n; ++i) { getint(m); max = 0; for (int j = 0; j < m; ++j) { getint(x); if (x > max) max = x; } sumsum += (long long)max * m; sum += m; if (max > maxmax) maxmax = max; } printf( %lld n , (long long)sum * (long long)maxmax - sumsum); } |
`include "defines.v"
module regfile(
input wire clk,
input wire rst,
//д¶Ë¿Ú
input wire we,
input wire[`RegAddrBus] waddr,
input wire[`RegBus] wdata,
//¶Á¶Ë¿Ú1
input wire re1,
input wire[`RegAddrBus] raddr1,
output reg[`RegBus] rdata1,
//¶Á¶Ë¿Ú2
input wire re2,
input wire[`RegAddrBus] raddr2,
output reg[`RegBus] rdata2
);
reg[`RegBus] regs[0:`RegNum-1];
always @ (posedge clk) begin
if (rst == `RstDisable) begin
if((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin
regs[waddr] <= wdata;
end
else if(rst == `RstEnable) begin
regs[0] <= `ZeroWord;
regs[1] <= `ZeroWord;
regs[2] <= `ZeroWord;
regs[3] <= `ZeroWord;
regs[4] <= `ZeroWord;
regs[5] <= `ZeroWord;
regs[6] <= `ZeroWord;
regs[7] <= `ZeroWord;
regs[8] <= `ZeroWord;
regs[9] <= `ZeroWord;
regs[10] <= `ZeroWord;
regs[11] <= `ZeroWord;
regs[12] <= `ZeroWord;
regs[13] <= `ZeroWord;
regs[14] <= `ZeroWord;
regs[15] <= `ZeroWord;
regs[16] <= `ZeroWord;
regs[17] <= `ZeroWord;
regs[18] <= `ZeroWord;
regs[19] <= `ZeroWord;
regs[20] <= `ZeroWord;
regs[21] <= `ZeroWord;
regs[22] <= `ZeroWord;
regs[23] <= `ZeroWord;
regs[24] <= `ZeroWord;
regs[25] <= `ZeroWord;
regs[26] <= `ZeroWord;
regs[27] <= `ZeroWord;
regs[28] <= `ZeroWord;
regs[29] <= `ZeroWord;
regs[30] <= `ZeroWord;
regs[31] <= `ZeroWord;
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
rdata1 <= `ZeroWord;
end else if(raddr1 == `RegNumLog2'h0) begin
rdata1 <= `ZeroWord;
end else if((raddr1 == waddr) && (we == `WriteEnable)
&& (re1 == `ReadEnable)) begin
rdata1 <= wdata;
end else if(re1 == `ReadEnable) begin
rdata1 <= regs[raddr1];
end else begin
rdata1 <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
rdata2 <= `ZeroWord;
end else if(raddr2 == `RegNumLog2'h0) begin
rdata2 <= `ZeroWord;
end else if((raddr2 == waddr) && (we == `WriteEnable)
&& (re2 == `ReadEnable)) begin
rdata2 <= wdata;
end else if(re2 == `ReadEnable) begin
rdata2 <= regs[raddr2];
end else begin
rdata2 <= `ZeroWord;
end
end
endmodule |
/*88888888 .d88888b.
888 888 888 d88P" "Y88b
888 888 888 888 888
888 888 888
888 888 888 888 888
888 888 888 888 888
888 888 888 Y88b. .d88P
888 888 "Y88888*/
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal FIFO Single Clock ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// D/L from: http://www.opencores.org/cores/generic_fifos/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLus_IED WARRANTIES, INCLUDING, BUT NOT LIMITED////
//// TO, THE IMPLus_IED WARRANTIES OF MERCHANTABILITY AND FITNESS////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLus_ARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp $
//
// $Date: 2002-09-25 05:42:06 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
//
//
//
//
//
//
`include "timescale.v"
/*
Description
===========
I/Os
----
rst low active, either sync. or async. master reset (see below how to select)
clr synchronous clear (just like reset but always synchronous), high active
re read enable, synchronous, high active
we read enable, synchronous, high active
din Data Input
dout Data Output
full Indicates the FIFO is full (combinatorial output)
full_r same as above, but registered output (see note below)
empty Indicates the FIFO is empty
empty_r same as above, but registered output (see note below)
full_n Indicates if the FIFO has space for N entries (combinatorial output)
full_n_r same as above, but registered output (see note below)
empty_n Indicates the FIFO has at least N entries (combinatorial output)
empty_n_r same as above, but registered output (see note below)
level indicates the FIFO level:
2'b00 0-25% full
2'b01 25-50% full
2'b10 50-75% full
2'b11 %75-100% full
combinatorial vs. registered status outputs
-------------------------------------------
Both the combinatorial and registered status outputs have exactly the same
synchronous timing. Meaning they are being asserted immediately at the clock
edge after the last read or write. The combinatorial outputs however, pass
through several levels of logic before they are output. The registered status
outputs are direct outputs of a flip-flop. The reason both are provided, is
that the registered outputs require quite a bit of additional logic inside
the FIFO. If you can meet timing of your device with the combinatorial
outputs, use them ! The FIFO will be smaller. If the status signals are
in the critical pass, use the registered outputs, they have a much smaller
output delay (actually only Tcq).
Parameters
----------
The FIFO takes 3 parameters:
dw Data bus width
aw Address bus width (Determines the FIFO size by evaluating 2^aw)
n N is a second status threshold constant for full_n and empty_n
If you have no need for the second status threshold, do not
connect the outputs and the logic should be removed by your
synthesis tool.
Synthesis Results
-----------------
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
at about 116 MHz (IO insertion disabled). The registered status outputs
are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
available.
Misc
----
This design assumes you will do appropriate status checking externally.
IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
empty will place the FIFO in an undefined state.
*/
// Selecting Sync. or Async Reset
// ------------------------------
// Uncomment one of the two lines below. The first line for
// synchronous reset, the second for asynchronous reset
// `define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset
`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset
module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
full, empty, full_r, empty_r,
full_n, empty_n, full_n_r, empty_n_r,
level);
parameter dw = 8;
parameter aw = 8;
parameter n = 32;
parameter max_size = 1 << aw;
input clk, rst, clr;
input we;
input re;
input [dw-1:0] din;
output full, full_r;
output empty, empty_r;
output full_n, full_n_r;
output empty_n, empty_n_r;
output [dw-1:0] dout;
output [1:0] level;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire full_n, empty_n;
wire[aw-1:0] wp_plus_one;
wire[aw-1:0] wp_plus_two;
wire[aw-1:0] rp_plus_one;
reg full_r;
reg empty_r;
reg gb;
reg gb2;
reg full_n_r, empty_n_r;
reg [aw-1:0] wp;
reg [aw-1:0] rp;
reg [aw:0] cnt;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
generic_dpram #(aw,dw) u0(
.rclk ( clk ),
.rrst ( !rst ),
.rce ( 1'b1 ),
.oe ( 1'b1 ),
.raddr ( rp ),
.do ( dout ),
.wclk ( clk ),
.wrst ( !rst ),
.wce ( 1'b1 ),
.we ( we ),
.waddr ( wp ),
.di ( din )
);
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) wp <= #1 {aw{1'b0}};
else
if(clr) wp <= #1 {aw{1'b0}};
else
if(we) wp <= #1 wp_plus_one;
assign wp_plus_one = wp + { {(aw - 1){1'b0}}, 1'b1};
assign wp_plus_two = wp + { {(aw - 2){1'b0}}, 2'b10};
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) rp <= #1 {aw{1'b0}};
else
if(clr) rp <= #1 {aw{1'b0}};
else
if(re) rp <= #1 rp_plus_one;
assign rp_plus_one = rp + { {(aw - 1){1'b0}}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) & !gb);
assign full = ((wp == rp) & gb);
// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) gb <= #1 1'b0;
else
if(clr) gb <= #1 1'b0;
else
if((wp_plus_one == rp) & we) gb <= #1 1'b1;
else
if(re) gb <= #1 1'b0;
////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//
// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) gb2 <= #1 1'b0;
else
if(clr) gb2 <= #1 1'b0;
else
if((wp_plus_two == rp) & we) gb2 <= #1 1'b1;
else
if((wp != rp) & re) gb2 <= #1 1'b0;
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) full_r <= #1 1'b0;
else
if(clr) full_r <= #1 1'b0;
else
if(we & ((wp_plus_one == rp) & gb2) & !re) full_r <= #1 1'b1;
else
if(re & ((wp_plus_one != rp) | !gb2) & !we) full_r <= #1 1'b0;
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) empty_r <= #1 1'b1;
else
if(clr) empty_r <= #1 1'b1;
else
if(we & ((wp != rp_plus_one) | gb2) & !re) empty_r <= #1 1'b0;
else
if(re & ((wp == rp_plus_one) & !gb2) & !we) empty_r <= #1 1'b1;
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full_n & Empty_n Flags
//
assign empty_n = cnt < n;
assign full_n = !(cnt < (max_size - n + 1));
assign level = {2{cnt[aw]}} | cnt[aw - 1:aw - 2];
// N entries status
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) cnt <= #1 {aw + 1{1'b0}};
else
if(clr) cnt <= #1 {aw + 1{1'b0}};
else
if( re & !we) cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
else
if(!re & we) cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Registered Full_n & Empty_n Flags
//
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) empty_n_r <= #1 1'b1;
else
if(clr) empty_n_r <= #1 1'b1;
else
if(we & (cnt >= (n - 1) ) & !re) empty_n_r <= #1 1'b0;
else
if(re & (cnt <= n ) & !we) empty_n_r <= #1 1'b1;
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) full_n_r <= #1 1'b0;
else
if(clr) full_n_r <= #1 1'b0;
else
if(we & (cnt >= (max_size - n) ) & !re) full_n_r <= #1 1'b1;
else
if(re & (cnt <= (max_size - n + 1)) & !we) full_n_r <= #1 1'b0;
////////////////////////////////////////////////////////////////////
//
// Sanity Check
//
// synopsys translate_off
always @(posedge clk)
if(we & full)
$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
always @(posedge clk)
if(re & empty)
$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
// synopsys translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FAHCIN_PP_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n; vector<pair<int, int> > arr; long long solve1(vector<pair<int, int> > tab) { multiset<int> S; int W = 0; for (int i = 0; i < n; i++) { W += tab[i].first; S.insert(tab[i].second); } for (int j = 0; j < n / 2; j++) { int id = -1; long long best = 0; for (int i = 0; i < n; i++) { multiset<int>::iterator it = S.end(); it--; long long cur = W * 1LL * (*it); S.erase(S.find(tab[i].second)); it = S.end(); it--; long long tmp = max((*it), tab[i].first) * 1LL * (W - tab[i].first + tab[i].second); if (cur - tmp > best) { best = cur - tmp; id = i; } S.insert(tab[i].second); } if (id == -1) break; S.erase(S.find(tab[id].second)); S.insert(tab[id].first); W = W - tab[id].first + tab[id].second; swap(tab[id].first, tab[id].second); } multiset<int>::iterator it = S.end(); it--; long long result = W * 1LL * (*it); return result; } long long solve2(vector<pair<int, int> > tab) { sort(tab.begin(), tab.end(), [](pair<int, int> A, pair<int, int> B) { return A.first - A.second > B.first - B.second; }); for (int i = 0; i < n / 2; i++) swap(tab[i].first, tab[i].second); int W = 0; int H = 0; for (int i = 0; i < n; i++) { W += tab[i].first; H = max(H, tab[i].second); } long long res1 = W * 1LL * H; for (int i = 0; i < n / 2; i++) swap(tab[i].first, tab[i].second); sort(tab.begin(), tab.end(), [](pair<int, int> A, pair<int, int> B) { if (A.second == B.second) { return A.first < B.first; } else { return A.second > B.second; } }); for (int i = 0; i < n / 2; i++) swap(tab[i].first, tab[i].second); W = 0; H = 0; for (int i = 0; i < n; i++) { W += tab[i].first; H = max(H, tab[i].second); } long long res2 = W * 1LL * H; return min(res1, res2); } int main() { ios_base::sync_with_stdio(0); cin >> n; arr.resize(n); for (int i = 0; i < n; i++) cin >> arr[i].first >> arr[i].second; long long res1 = solve1(arr); long long res2 = solve2(arr); cout << min(res1, res2) << endl; } |
// Test implicit casts during procedural continuous (net) assignments.
`ifdef __ICARUS__
`define SUPPORT_REAL_NETS_IN_IVTEST
`define SUPPORT_TWO_STATE_NETS_IN_IVTEST
`endif
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
wire real dst_r;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
wire bit unsigned [3:0] dst_u2s;
wire bit signed [3:0] dst_s2s;
wire bit unsigned [11:0] dst_u2l;
wire bit signed [11:0] dst_s2l;
`endif
wire logic unsigned [3:0] dst_u4s;
wire logic signed [3:0] dst_s4s;
wire logic unsigned [11:0] dst_u4l;
wire logic signed [11:0] dst_s4l;
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8'bx0z00111;
src_sx = 8'bx0z00111;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
$display("cast to real");
force dst_r = src_r; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
force dst_r = src_u2; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
force dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
force dst_r = src_u4; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
force dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
force dst_r = src_ux; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
force dst_r = src_sx; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
`endif
`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST
$display("cast to small unsigned bit");
force dst_u2s = src_r; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
force dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
force dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
force dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
force dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
force dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
force dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
$display("cast to small signed bit");
force dst_s2s = src_r; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
force dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
force dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
force dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
force dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
force dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
force dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
$display("cast to large unsigned bit");
force dst_u2l = src_r; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
force dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
force dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
force dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
force dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
force dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
force dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
$display("cast to large signed bit");
force dst_s2l = src_r; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
force dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
force dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
force dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
force dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
force dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
force dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
`endif
$display("cast to small unsigned logic");
force dst_u4s = src_r; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
force dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
force dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
force dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
force dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
force dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
force dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
$display("cast to small signed logic");
force dst_s4s = src_r; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
force dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
force dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
force dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
force dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
force dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
force dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
$display("cast to large unsigned logic");
force dst_u4l = src_r; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
force dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
force dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
force dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
force dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
force dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
force dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
force dst_s4l = src_r; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
force dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
force dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
force dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
force dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
force dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1;
force dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; vector<string> notes, names(55); for (int i = 0; i <= n - k; i++) { string m; cin >> m; notes.push_back(m); } for (int i = 0; i < 26; i++) { names[i] = (i + A ); } if (n >= 26) { for (int i = 26; i <= n; i++) { names[i] = names[i - 26] + a ; } } for (int i = 0; i <= n - k; i++) { if (notes[i] == NO ) names[i + k - 1] = names[i]; } for (int i = 0; i < n; i++) { cout << names[i] << ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP ;
wire and0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X, SLEEP_B, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long unsigned int n; long long unsigned int val(long long unsigned int x, long long unsigned int k) { if (x >= 1e10) return n + 1; long long unsigned int ans = x * (x - 1); ans /= 2; long long unsigned int kt = k; if (ans > n) return n + 1; while (k--) { x *= 2; if (x > 1e19) return n + 1; } for (int i = 1; i <= kt; i++) { ans = ans + x / 2; if (ans > n) return n + 1; x /= 2; } if (ans > n) return n + 1; return ans; } long long unsigned int calc(long long unsigned int k) { long long unsigned int lo = 0; long long unsigned int hi = 1e10; long long unsigned int mid; while (hi - lo > 1) { mid = (hi + lo) / 2; if (val(2 * mid - 1, k) >= n) hi = mid; else lo = mid; } if (val(2 * hi - 1, k) == n) { return (2 * hi - 1) * (1LL << k); } return 0; } int main() { cin >> n; long long unsigned int g; vector<long long unsigned int> ans; for (int i = 0; i <= 60; i++) { g = calc(i); if (g != 0) ans.push_back(g); } sort(ans.begin(), ans.end()); for (auto x : ans) { cout << x << ; } if (ans.size() == 0) cout << -1; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { long long n, l, r, x; cin >> n >> l >> r >> x; long long c[n]; for (long long i = 0; i < n; i++) cin >> c[i]; long long ans = 0; for (long long i = 0; i < (1 << n); i++) { long long mn = INT_MAX; long long mx = 0; bool ok = true; long long dif = 0; for (long long j = 0; j < n; j++) { if (i & (1 << j)) { mx = max(mx, c[j]); mn = min(mn, c[j]); dif += c[j]; } } ans += (dif >= l && dif <= r && mx - mn >= x); } cout << ans << n ; } |
`include "defines.v"
`timescale 1ns/1ps
module tb(
input `control_w port0_ci,
input `data_w port0_di,
output `control_w port0_co,
output `data_w port0_do,
input `control_w port1_ci,
input `data_w port1_di,
output `control_w port1_co,
output `data_w port1_do,
input `control_w port2_ci,
input `data_w port2_di,
output `control_w port2_co,
output `data_w port2_do,
input `control_w port3_ci,
input `data_w port3_di,
output `control_w port3_co,
output `data_w port3_do,
input `control_w port4_ci,
input `data_w port4_di,
output `control_w port4_co,
output `data_w port4_do
);
wire injrd;
reg clk, rst;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(port0_ci), .port0_co(port0_co),
.port1_ci(port1_ci), .port1_co(port1_co),
.port2_ci(port2_ci), .port2_co(port2_co),
.port3_ci(port3_ci), .port3_co(port3_co),
.port4_ci(port4_ci), .port4_co(port4_co),
.port0_di(port0_di), .port0_do(port0_do),
.port1_di(port1_di), .port1_do(port1_do),
.port2_di(port2_di), .port2_do(port2_do),
.port3_di(port3_di), .port3_do(port3_do),
.port4_di(port4_di), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
clk = 0;
rst = 0;
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
end
endmodule
|
/*
* phase_shift_check_tb.v: Test bench for phase_shift_check.v
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef DESIRED_SHIFT
`define DESIRED_SHIFT 45
`endif
`ifndef CLK_PERIOD
`define CLK_PERIOD 20
`endif
module phase_shift_check_tb ();
reg rst;
reg clk;
wire clk_shifted;
reg LOCKED;
wire fail;
integer shift;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 4;
phase_shift_check dut (
.desired_shift_1000(`DESIRED_SHIFT * 1000),
.clk_period_1000(`CLK_PERIOD * 1000),
.clk_shifted(clk_shifted),
.clk(clk),
.rst(rst),
.LOCKED(LOCKED),
.fail(fail));
phase_shift ps (
.PWRDWN(1'b0),
.RST(rst),
.clk(clk),
.shift(shift),
.clk_period_1000(`CLK_PERIOD * 1000),
.duty_cycle(50),
.clk_shifted(clk_shifted));
initial begin
$dumpfile("phase_shift_check_tb.vcd");
$dumpvars(0, phase_shift_check_tb);
rst = 0;
shift = `DESIRED_SHIFT;
clk = 0;
LOCKED = 0;
pass_count = 0;
fail_count = 0;
#10;
rst = 1;
#10;
if (fail == 1'b0) begin
$display("PASSED: rst");
pass_count = pass_count + 1;
end else begin
$display("FAILED: rst");
fail_count = fail_count + 1;
end
rst = 0;
#(`CLK_PERIOD * 2);
if (fail == 1'b0) begin
$display("PASSED: LOCKED");
pass_count = pass_count + 1;
end else begin
$display("FAILED: LOCKED");
fail_count = fail_count + 1;
end
LOCKED = 1;
#`WAIT_INTERVAL;
if (fail == 1'b0) begin
$display("PASSED: shifts match");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shifts match");
fail_count = fail_count + 1;
end
shift = shift + 45;
#`WAIT_INTERVAL;
if (fail == 1'b1) begin
$display("PASSED: shifts don't match");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shifts don't match");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #(`CLK_PERIOD / 2.0) clk <= ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, arr[26], s, k, fuck[19], ans; vector<pair<long long, long long> > v1; map<pair<long long, long long>, long long> maph; void rek(long long x, long long r, long long z, long long o, bool p) { if (x >= r) { if (!p) v1.push_back({z, o}); else maph[{z, o}]++; return; } if (arr[x] + z <= s) rek(x + 1, r, z + arr[x], o, p); if (o < k and arr[x] <= 18 and z + fuck[arr[x]] <= s) rek(x + 1, r, z + fuck[arr[x]], o + 1, p); rek(x + 1, r, z, o, p); } int main() { cin >> n >> k >> s; fuck[0] = 1; for (int i = 1; i <= 18; i++) fuck[i] = fuck[i - 1] * i; for (int i = 0; i < n; i++) cin >> arr[i]; rek(0, n / 2, 0, 0, 0), rek(n / 2, n, 0, 0, 1); for (int i = 0; i < v1.size(); i++) { for (int j = 0; j <= k - v1[i].second; j++) { if (maph.find({s - v1[i].first, j}) != maph.end()) ans += maph[{s - v1[i].first, j}]; } } cout << ans; } |
/*
* Read rotary/quadrature encoder using no clock
*
* Implementation of https://github.com/theapi/hdd_rotary_encoder/blob/master/HDDRotaryEncoder/HDDRotaryEncoder.ino
*
*/
module quadrature_decode(
reset,
quadA,
quadB,
count
);
input reset, quadA, quadB;
output [7:0] count;
reg [3:0] combined; // previous & current readings
reg [7:0] total;
reg [2:0] num;
always @ ( * )
begin
if (reset) begin
combined = 4'b0000;
total = 0;
num = 0;
end
else begin
// combine current with previous
// left shift
combined = combined << 2;
combined = combined | {quadA, quadB};
num = 0;
case (combined)
4'b0000 : num = 2'd0;
4'b0001 : num = -2'd1;
4'b0010 : num = 2'd1;
4'b0011 : num = 2'd0;
4'b0100 : num = 2'd1;
4'b0101 : num = 2'd0;
4'b0110 : num = 2'd0;
4'b0111 : num = -2'd1;
4'b1000 : num = -2'd1;
4'b1001 : num = 2'd0;
4'b1010 : num = 2'd0;
4'b1011 : num = 2'd1;
4'b1100 : num = 2'd0;
4'b1101 : num = 2'd1;
4'b1110 : num = -2'd1;
4'b1111 : num = 2'd0;
endcase
total = $signed(total) + $signed(num);
end
end
assign count = total;
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifndef PICORV32_REGS
`ifdef PICORV32_V
`error "picosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
`endif
module picosoc (
input clk,
input resetn,
output iomem_valid,
input iomem_ready,
output [ 3:0] iomem_wstrb,
output [31:0] iomem_addr,
output [31:0] iomem_wdata,
input [31:0] iomem_rdata,
input irq_5,
input irq_6,
input irq_7,
output ser_tx,
input ser_rx,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
reg [31:0] irq;
wire irq_stall = 0;
wire irq_uart = 0;
always @* begin
irq = 0;
irq[3] = irq_stall;
irq[4] = irq_uart;
irq[5] = irq_5;
irq[6] = irq_6;
irq[7] = irq_7;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire spimem_ready;
wire [31:0] spimem_rdata;
reg ram_ready;
wire [31:0] ram_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
wire [31:0] spimemio_cfgreg_do;
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(1),
.COMPRESSED_ISA(1),
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_IRQ_QREGS(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.irq (irq )
);
spimemio spimemio (
.clk (clk),
.resetn (resetn),
.valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
.ready (spimem_ready),
.addr (mem_addr[23:0]),
.rdata (spimem_rdata),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.cfgreg_we(spimemio_cfgreg_sel ? mem_wstrb : 4'b 0000),
.cfgreg_di(mem_wdata),
.cfgreg_do(spimemio_cfgreg_do)
);
simpleuart simpleuart (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
.reg_div_di (mem_wdata),
.reg_div_do (simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
picosoc_mem #(.WORDS(MEM_WORDS)) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),
.wdata(mem_wdata),
.rdata(ram_rdata)
);
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
module picosoc_mem #(
parameter integer WORDS = 256
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output reg [31:0] rdata
);
reg [31:0] mem [0:WORDS-1];
always @(posedge clk) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_top.v
// Version : 1.10
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_core_axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_core_axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_core_axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> divi[2002]; long long dp[2002][2002]; int main() { int n, k; cin >> k >> n; int i, j; for (i = 1; i <= k; i++) { for (j = i; j <= k; j += i) divi[i].push_back(j); } for (i = 1; i <= n; i++) { for (j = 1; j <= k; j++) { if (i == 1) dp[i][j] = 1; else { for (int x : divi[j]) dp[i][j] += dp[i - 1][x], dp[i][j] %= 1000000007; } } } long long ans = 0; for (i = 1; i <= k; i++) ans += dp[n][i], ans %= 1000000007; cout << ans << n ; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:55:53 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */;
output [0:0]dout;
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); #pragma GCC optimize( Ofast ) #pragma GCC optimize( -O3 ) #pragma GCC optmize( sse, sse2, sse3, sse4, avx, abx, avx2, sse4.1 ) #pragma GCC optmize( fast-math ) #pragma GCC optimize( unroll-loops ) const int N = 1e5 + 100; const int INF = 1e9; vector<pair<int, int>> g[N]; int res[N]; bool used[N]; int col[N]; vector<int> comp; int h[N]; void ex() { cout << NO ; exit(0); } void dfs(int v) { comp.push_back(v); used[v] = true; for (auto u : g[v]) { if (!used[u.first]) { h[u.first] = h[v] + 1; dfs(u.first); } } } void push(int v) { for (auto u : g[v]) { if (res[u.first] == INF) { res[u.first] = u.second - res[v]; push(u.first); } } } vector<pair<int, int>> p; int eat[N]; bool bfs(int st) { vector<int> q; q.push_back(st); int ptr = 0; int v1 = -1; int v2 = -1; int last = 0; while (ptr < q.size() && v1 == -1) { int v = q[ptr++]; for (auto u : g[v]) { if (u.first == p[v].first) continue; if (p[u.first].first == -1 && u.first != st) { col[u.first] = 1 - col[v]; p[u.first].first = v; p[u.first].second = u.second; q.push_back(u.first); } else if (col[u.first] == col[v]) { v1 = v; v2 = u.first; last = u.second; break; } } } if (v1 == -1) return false; vector<int> p1; vector<int> d1; int bv1 = v1; while (v1 != -1) { p1.push_back(v1); if (p[v1].first != -1) d1.push_back(p[v1].second); v1 = p[v1].first; } vector<int> p2; vector<int> d2; while (p[v2].first != -1) { p2.push_back(v2); d2.push_back(p[v2].second); v2 = p[v2].first; } reverse(p2.begin(), p2.end()); reverse(d2.begin(), d2.end()); for (int &x : d2) d1.push_back(x); for (int &i : p2) p1.push_back(i); int s = 0; int sgn = 1; for (int i = (int)d1.size() - 1; i >= 0; --i) { s += (sgn * d1[i]); sgn *= (-1); } res[bv1] = (last - s) / 2; push(bv1); return true; } void iterate(int v) { res[v] = 0; push(v); vector<int> s; for (int &i : comp) { if (h[i] % 2 == 0) s.push_back(res[i]); else s.push_back(-res[i]); } sort(s.begin(), s.end()); for (int &i : comp) res[i] = INF; res[v] = -s[s.size() / 2]; push(v); } signed main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); ; cout.precision(18); int n, m; cin >> n >> m; auto cmp = [](pair<pair<int, int>, int> a, pair<pair<int, int>, int> b) { if (a.first != b.first) return a.first < b.first; return a.second < b.second; }; set<pair<pair<int, int>, int>, decltype(cmp)> s(cmp); fill(res, res + n, INF); vector<pair<pair<int, int>, int>> que; for (int i = 0; i < m; ++i) { int a, b, c; cin >> a >> b >> c; que.push_back({{a - 1, b - 1}, c * 2}); if (a == b) { res[--b] = c; continue; } if (s.count({{a, b}, c}) || s.count({{b, a}, c})) continue; int f1 = 1; if (c == 1) f1 = 2; if (s.count({{a, b}, f1}) || s.count({{b, a}, f1})) ex(); s.insert({{a, b}, c}); g[--a].push_back({--b, c * 2}); g[b].push_back({a, c * 2}); } fill(used, used + n, false); fill(col, col + n, 0); p.resize(n, {-1, 0}); for (int i = 0; i < n; ++i) { for (auto z : g[i]) eat[i] += z.second; } for (int i = 0; i < n; ++i) { if (!used[i]) { comp.clear(); dfs(i); int id = -1; for (int &j : comp) { if (res[j] != INF) id = j; } if (id != -1) { push(id); continue; } bool f = bfs(i); if (f) continue; iterate(i); } } for (auto z : que) { if (res[z.first.first] + res[z.first.second] != z.second) ex(); } cout << YES n ; for (int i = 0; i < n; ++i) cout << ((double)res[i] / 2.0) << ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFXTP_PP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int Q, cnt = 1; int par[400010][21], nxt[400010][21], len[400010]; long long w[400010], sum[400010][21]; long long mx[400010][21]; int find_first_bigger(int u, int W) { if (mx[u][0] >= W) return u; for (int i = 18; i >= 0; i--) if (mx[u][i + 1] >= W && mx[u][i] < W) u = par[u][i]; return mx[u][0] >= W ? u : 0; } void add(int R, int W) { int u = ++cnt; w[u] = W; int fb = find_first_bigger(R, W); len[u] = len[fb] + 1; nxt[u][0] = fb; sum[u][0] = W; par[u][0] = R; mx[u][0] = w[u]; for (int i = 1; i < 21; i++) { nxt[u][i] = nxt[nxt[u][i - 1]][i - 1]; sum[u][i] = sum[nxt[u][i - 1]][i - 1] + sum[u][i - 1]; par[u][i] = par[par[u][i - 1]][i - 1]; mx[u][i] = max(mx[par[u][i - 1]][i - 1], mx[u][i - 1]); } } long long getsum(long long u, long long k) { if (!k) return 0; long long ret = 0; for (int i = 0; k; i++, k >>= 1) if (k & 1) { ret += sum[u][i]; u = nxt[u][i]; } return ret; } long long query(long long u, long long x) { long long lo = 1, hi = len[u]; while (lo < hi) { long long mid = (lo + hi) >> 1; long long s = getsum(u, mid); if (s > x) hi = mid; else lo = mid + 1; } if (getsum(u, lo) <= x) return lo; else if (getsum(u, lo - 1) > x) return 0; return lo - 1; } int main() { for (int i = 0; i < 400010; i++) for (int j = 0; j < 21; j++) mx[i][j] = -4e18; for (int i = 0; i < 21; i++) mx[1][0] = 0; len[1] = 1; scanf( %d , &Q); long long last = 0; while (Q--) { long long tt, p, q; scanf( %lld%lld%lld , &tt, &p, &q); if (tt == 1) { long long R = p ^ last, W = q ^ last; add(R, W); } else { long long R = p ^ last, X = q ^ last; printf( %lld n , last = query(R, X)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int x, t, a, b, da, db, i, j, p, ans = 0; int main() { scanf( %d %d %d %d %d %d , &x, &t, &a, &b, &da, &db); i = 0; for (i = 0; i < t; i++) for (j = 0; j < t; j++) { if (a - i * da + b - j * db == x) ans = 1; } for (i = 0; i < t; i++) if (a - i * da == x || b - i * db == x) ans = 1; if (ans == 1 || x == 0) printf( YES ); else printf( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long dp[int(1e5 + 2)][2]; int a[int(1e5 + 2)]; vector<int> v[2]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int mod = 998244353; int t; cin >> t; while (t--) { v[0].clear(); v[1].clear(); for (int i = 0; i < int(1e5 + 2); i++) dp[i][0] = dp[i][1] = 0; int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; long long ans = 0; for (int i = n - 1; i >= 0; i--) { int one = i % 2; dp[a[i]][one] = 1; v[one].push_back(a[i]); for (auto x : v[1 - one]) { int k = a[i] / x; if (a[i] % x != 0) k++; int x_ = a[i] / k; if (dp[x_][one] == 0) v[one].push_back(x_); dp[x_][one] += dp[x][1 - one]; ans = (ans + (i + 1) * dp[x][1 - one] * (k - 1)) % mod; dp[x][1 - one] = 0; } v[1 - one].clear(); } cout << ans << n ; } } |
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: 6850RX.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ()
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
//
////////////////////////////////////////////////////////////////////////////////
module UART_RX(
RESET_N,
BAUD_CLK,
RX_DATA,
RX_BUFFER,
//RX_READY,
RX_WORD,
RX_PAR_DIS,
RX_PARITY,
PARITY_ERR,
//OVERRUN,
FRAME,
READY
);
input RESET_N;
input BAUD_CLK;
input RX_DATA;
output [7:0] RX_BUFFER;
reg [7:0] RX_BUFFER;
input RX_WORD;
input RX_PAR_DIS;
input RX_PARITY;
output PARITY_ERR;
reg PARITY_ERR;
output FRAME;
reg FRAME;
output READY;
reg READY;
reg [5:0] STATE;
reg [2:0] BIT;
reg RX_DATA0;
reg RX_DATA1;
always @ (posedge BAUD_CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
RX_BUFFER <= 8'h00;
STATE <= 6'b000000;
FRAME <= 1'b0;
BIT <= 3'b000;
RX_DATA0 <= 1'b1;
RX_DATA1 <= 1'b1;
READY <= 1'b0;
end
else
begin
RX_DATA0 <= RX_DATA;
RX_DATA1 <= RX_DATA0;
case (STATE)
6'b000000:
begin
BIT <= 3'b000;
if(~RX_DATA1)
STATE <= 6'b000001;
end
6'b001111: // End of start bit, flag data not ready
begin // If data is not retrieved before this, then overrun
READY <= 1'b0;
STATE <= 6'b010000;
end
6'b010111: // Middle of data bits
begin
RX_BUFFER[BIT] <= RX_DATA1;
STATE <= 6'b011000;
end
6'b011111: // End of data bit
begin
if(BIT == 3'b111)
STATE <= 6'b100000;
else
begin
if((BIT == 3'b110) && !RX_WORD)
STATE <= 6'b100000;
else
begin
BIT <= BIT + 1'b1;
STATE <= 6'b010000;
end
end
end
6'b100000: // Start of parity bit, if enabled
begin
if(RX_PAR_DIS)
STATE <= 6'b110001; // get stop
else
STATE <= 6'b100001; // get parity
end
6'b100111: //39 middle of parity bit
begin
PARITY_ERR <=((((RX_BUFFER[0] ^ RX_BUFFER[1])
^ (RX_BUFFER[2] ^ RX_BUFFER[3]))
^ ((RX_BUFFER[4] ^ RX_BUFFER[5])
^ (RX_BUFFER[6] ^ (RX_BUFFER[7] & RX_WORD)))) // clear bit #8 if only 7 bits
^ (RX_PARITY ^ RX_DATA1));
STATE <= 6'b101000;
end
6'b110111: //55 middle of stop bit
begin
READY <= 1'b1; // This is the last info we need, so signal ready
FRAME <= !RX_DATA1; // if data != 1 then not stop bit
STATE <= 6'b111000;
end
// In case of a framing error, wait until data is 1 then start over
6'b111000:
begin
if(RX_DATA1) // wait until data = 1
STATE <= 6'b000000;
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long int n, a, b, c, d, e, f, g, h, i, j, x, y, count = 0; cin >> n >> x >> y; n = n / 2; if ((x == n || x == n + 1) && (y == n || y == n + 1)) cout << NO ; else cout << YES ; return 0; } |
`timescale 1ns / 1ps
module MasterDataUnitI2C_tb;
reg WriteLoad, ReadorWrite, ShiftorHold, Select, BaudEnable;
reg [7:0] SentData;
reg StartStopAck, Reset, clock;
reg [19:0] BaudRate;
reg [29:0] ClockFrequency;
wire [7:0] ReceivedData;
wire SCL, SDA;
wire ClockI2C=uut.ClockI2C;
MasterDataUnitI2C uut(BaudRate,ClockFrequency,SentData,BaudEnable,clock,ReadorWrite,Reset,Select,ShiftorHold,StartStopAck,WriteLoad,ReceivedData,SCL,SDA);
initial begin
WriteLoad = 0;
ReadorWrite = 0;
ShiftorHold = 0;
Select = 0;
BaudEnable = 0;
SentData = 0;
StartStopAck = 0;
Reset = 0;
clock = 0;
BaudRate = 0;
ClockFrequency = 0;
end
always #4 clock=~clock;
initial fork
#0 Reset = 1; #13 Reset = 0;
#0 BaudRate = 2;
#0 ClockFrequency = 12;
#0 WriteLoad = 0; #15 WriteLoad = 1; #23 WriteLoad = 0;
#0 SentData = 8'b11001010;
#0 Select = 0; #34 Select = 1; #484 Select = 0;
#0 StartStopAck = 1; #21 StartStopAck = 0; #34 StartStopAck = 1; #484 StartStopAck = 0;
#494 StartStopAck = 1;
#0 BaudEnable = 0; #30 BaudEnable = 1; #484 BaudEnable = 0;
#0 ReadorWrite = 0; #430 ReadorWrite = 1; #484 ReadorWrite = 0;
#0 ShiftorHold = 0; #90 ShiftorHold = 1; #442 ShiftorHold = 0;
#510 $stop;
join
endmodule |
module inicial ( botao, aberto, fechado, motor, sentido, ledVerde, ledVermelho, display, clock );
input botao, aberto, fechado, motor, sentido, clock;
output ledVerde, ledVermelho;
output [6:0] display;
reg [1:0] estado;
reg [4:0] entrada;
reg [6:0] tmpDisplay;
reg tmpLedVerde, tmpLedVermelho;
parameter Fechado = 2'b00, Abrindo = 2'b01, Aberto = 2'b10, Fechando = 2'b11;
initial estado = Fechado;
always @(posedge clock)begin
entrada[4] = botao;
entrada[3] = aberto;
entrada[2] = fechado;
entrada[1] = motor;
entrada[0] = sentido;
case( estado )
Fechado: begin
tmpDisplay = 7'b0001110;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b10110 ) // botao = 1 & aberto = 0 & fechado = 1 & motor = 1 & sentido = 0
estado = Abrindo;
end
Abrindo: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 1;
tmpLedVermelho = 0;
if( entrada == 5'b10010 ) // botao = 1 & aberto = 0 & fechado = 0 && motor = 1 & sentido = 0
estado = Aberto;
if( entrada == 5'b00010 ) // botao = 0 & aberto = 0 & fechado = 0 & motor = 1 & sentido == 0
estado = Fechando;
end
Aberto: begin
tmpDisplay = 7'b0001000;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b01011 ) // botao = 0 & aberto = 1 & fechado = 0 & motor = 1 & sentido = 1
estado = Fechando;
end
Fechando: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 0;
tmpLedVermelho = 1;
if( entrada == 5'b10011 ) // botao = 1 & aberto = 0 & fechado = 0 & motor = 1 & sentido = 1
estado = Abrindo;
if( entrada == 5'b00011 ) // botao = 0 & aberto = 0 & fechado = 0 & motor = 1 & sentido = 1
estado = Fechado;
end
default: estado = Fechado;
endcase
end
assign display= tmpDisplay;
assign ledVerde = tmpLedVerde;
assign ledVermelho = tmpLedVermelho;
endmodule
module maquina( SW, LEDG, LEDR, HEX0, CLK );
input [4:0] SW;
input CLK;
output [0:0] LEDG, LEDR;
output [6:0] HEX0;
inicial a( SW[4], SW[3], SW[2], SW[1], SW[0], LEDG[0], LEDR[0], HEX0, CLK);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int64_t>> board, vis, diag1, diag2; int main() { ios::sync_with_stdio(false), cin.tie(nullptr); int64_t n; cin >> n; for (int64_t i = 0; i < n; i++) { vector<int64_t> temp; vector<int64_t> zero; for (int64_t j = 0; j < n; j++) { int64_t t; cin >> t; temp.push_back(t); zero.push_back(0); } board.push_back(temp); vis.push_back(zero); diag1.push_back(zero); diag2.push_back(zero); } for (int64_t i = 0; i < n; i++) { for (int64_t j = 0; j < n; j++) { if (vis[i][j]) continue; int64_t t1 = i, t2 = j, s = 0; while (1) { vis[t1][t2] = 1; s += board[t1][t2]; t1 -= -1; t2 -= -1; if (t1 >= n || t2 >= n) break; } t1 = i, t2 = j; while (1) { diag1[t1][t2] = s; t1 -= -1; t2 -= -1; if (t1 >= n || t2 >= n) break; } } } for (int64_t i = 0; i < n; i++) for (int64_t j = 0; j < n; j++) vis[i][j] = 0; for (int64_t i = 0; i < n; i++) { for (int64_t j = 0; j < n; j++) { if (vis[i][j]) continue; int64_t t1 = i, t2 = j, s = 0; while (1) { vis[t1][t2] = 1; s += board[t1][t2]; t1 -= -1; t2 += -1; if (t1 >= n || t2 < 0) break; } t1 = i, t2 = j; while (1) { diag2[t1][t2] = s; t1 -= -1; t2 += -1; if (t1 >= n || t2 < 0) break; } } } int64_t m1 = 0, m2 = 0, x1 = 0, x2 = 0, y1 = 0, y2 = 0; for (int64_t i = 0; i < n; i++) { for (int64_t j = 0; j < n; j++) { int64_t tmp = diag1[i][j] + diag2[i][j] - board[i][j]; if ((i + j) % 2) { if (tmp >= m1) { m1 = tmp; x1 = i + 1; y1 = j + 1; } } else { if (tmp >= m2) { m2 = tmp; x2 = i + 1; y2 = j + 1; } } } } cout << m1 + m2 << endl; cout << x1 << << y1 << << x2 << << y2; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 105; int a[maxn]; long long n, k; bool ok(long long d) { long long ret = 0; for (int i = 0; i < n; ++i) { ret += (a[i] - 1 + d) / d; } return ret * d <= k; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; for (int i = 0; i < n; ++i) cin >> a[i], k += a[i]; long long ans = 0; for (long long i = 1; i <= sqrt(k) + 1; ++i) { if (ok(i)) ans = max(ans, i); if (ok(k / i)) ans = max(ans, k / i); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 5; int n, m, k; int a[maxn], c[maxn]; int ans, tmp, cnt, rt, sum, ma; int flag; char s[maxn]; bool ok[maxn]; vector<int> vc[maxn], vv[maxn]; template <typename T> inline void read(T &X) { X = 0; int w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) X = (X << 3) + (X << 1) + (ch ^ 48), ch = getchar(); if (w) X = -X; } pair<int, int> query(int id) { printf( ? %d , vv[id].size()); for (int i = 0; i < vv[id].size(); i++) { printf( %d , vv[id][i]); } puts( ); fflush(stdout); int x, y; read(x); read(y); return make_pair(x, y); } void dfs(int u, int fa, int dep) { ma = max(ma, dep); vv[dep].push_back(u); for (int i = 0; i < vc[u].size(); i++) { int v = vc[u][i]; if (v == fa) continue; dfs(v, u, dep + 1); } } int jud(int as) { pair<int, int> k = query(as); if (k.second > sum) return 1; rt = k.first; return 0; } int main() { int T, cas = 1; cin >> T; while (T--) { read(n); ans = 0; for (int i = (0); i <= (n + 1); i++) { vc[i].clear(); vv[i].clear(); } for (int i = (1); i <= (n - 1); i++) { int x, y; read(x); read(y); vc[x].push_back(y); vc[y].push_back(x); vv[n + 1].push_back(i); } vv[n + 1].push_back(n); pair<int, int> tp = query(n + 1); rt = tp.first; sum = tp.second; ma = 0; dfs(rt, -1, 0); ma = min(ma, sum); int l = (sum + 1) / 2, r = ma + 1, tmp; while (l < r) { int mid = (l + r) >> 1; if (jud(mid)) { r = mid; } else { l = mid + 1; tmp = mid; } } for (int i = (0); i <= (n); i++) vv[i].clear(); dfs(rt, -1, 0); tp = query(sum); printf( ! %d %d n , rt, tp.first); fflush(stdout); scanf( %s , s); } return 0; } |
#include <bits/stdc++.h> using namespace std; int lim; char c[1000]; int g[1000][1000]; int f[1000][1000], pre[1000][1000]; void back(int v, int k) { int p = pre[v][k]; if (p) { back(p, k - 1); printf( + ); } int i1 = p + 1; int j1 = v; for (; i1 < j1; i1++, j1--) if (c[i1 - 1] != c[j1 - 1]) c[j1 - 1] = c[i1 - 1]; for (int i = p + 1; i <= v; i++) printf( %c , c[i - 1]); } int main() { scanf( %s , c); scanf( %d , &lim); for (int i = 1; i < strlen(c); i++) for (int j = i + 1; j <= strlen(c); j++) { int i1 = i; int j1 = j; for (; i1 < j1; i1++, j1--) if (c[i1 - 1] != c[j1 - 1]) g[i][j]++; } memset(f, 127, sizeof(f)); f[0][0] = 0; for (int i = 1; i <= strlen(c); i++) for (int j = 0; j < i; j++) for (int k = 0; k < lim && k <= j; k++) if (f[j][k] + g[j + 1][i] < f[i][k + 1]) f[i][k + 1] = f[j][k] + g[j + 1][i], pre[i][k + 1] = j; int min = 2000000000; int pos = lim + 1; for (int i = 0; i <= lim; i++) if (f[strlen(c)][i] < min) { min = f[strlen(c)][i], pos = i; } printf( %d n , min); back(strlen(c), pos); printf( n ); } |
#include <bits/stdc++.h> using namespace std; int lastr, lastc; int n, m, a, b; int row1[10], rcnt, ans; int main() { int i, j, k; while (scanf( %d%d%d%d , &n, &m, &a, &b) != EOF) { if (m == 1) { printf( 1 n ); continue; } lastr = (n + m - 1) / m; lastc = n % m; lastc = lastc == 0 ? m : lastc; ans = 0, rcnt = 0; row1[++rcnt] = (a + m - 1) / m; if ((b + m - 1) / m != (a + m - 1) / m) { if ((b + m - 1) / m == (a + m - 1) / m + 1) row1[++rcnt] = (b + m - 1) / m; else row1[++rcnt] = row1[1] + 1, row1[++rcnt] = (b + m - 1) / m; } int ta = a % m, tb = b % m; if (ta == 0) ta = m; if (tb == 0) tb = m; if (rcnt == 1) printf( 1 n ); else if (rcnt == 2) { if (ta == 1 && (row1[2] != lastr && tb == m || row1[2] == lastr && tb == lastc)) printf( 1 n ); else printf( 2 n ); } else { if (ta == 1 && (row1[3] != lastr && tb == m || row1[3] == lastr && tb == lastc)) printf( 1 n ); else if (ta == 1 || tb == m || ta - 1 == tb || (lastr == row1[3] && lastc == tb)) printf( 2 n ); else printf( 3 n ); } } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long x, y, n, m, t, q, a, b, count = 0; cin >> n; long long arr[n]; for (x = 0; x < n; x++) cin >> arr[x]; long long cop[n]; for (x = 0; x < n; x++) cop[x] = arr[x]; sort(cop, cop + n); vector<long long> v; for (x = 0; x < n; x++) if (arr[x] != cop[x]) count++, v.push_back(x); if (count <= 2) cout << YES ; else cout << NO ; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic 32x32 multiplier ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generic 32x32 multiplier with pipeline stages. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.4 2001/12/04 05:02:35 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.3 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
`ifdef OR1200_GENERIC_MULTP2_32X32
`define OR1200_W 32
`define OR1200_WW 64
module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );
input [`OR1200_W-1:0] X;
input [`OR1200_W-1:0] Y;
input CLK;
input RST;
output [`OR1200_WW-1:0] P;
reg [`OR1200_WW-1:0] p0;
reg [`OR1200_WW-1:0] p1;
integer xi;
integer yi;
//
// Conversion unsigned to signed
//
always @(X)
xi <= X;
//
// Conversion unsigned to signed
//
always @(Y)
yi <= Y;
//
// First multiply stage
//
always @(posedge CLK or posedge RST)
if (RST)
p0 <= `OR1200_WW'b0;
else
p0 <= #1 xi * yi;
//
// Second multiply stage
//
always @(posedge CLK or posedge RST)
if (RST)
p1 <= `OR1200_WW'b0;
else
p1 <= #1 p0;
assign P = p1;
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; bool myfunction(int i, int j) { return (i < j); } int main() { int n, a, b, h; cin >> n >> a >> b; vector<int> myvector(n); for (int i = 0; i < n; ++i) { cin >> h; myvector.at(i) = h; } sort(myvector.begin(), myvector.end(), myfunction); cout << myvector.at(b) - myvector.at(b - 1) << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:23:37 11/08/2015
// Design Name:
// Module Name: Integradorv2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Integradorv2(
input [15:0] a,
input [15:0] dt,
input enable,
input rst,
input clk,
output reg [15:0] v,
output reg busy
);
wire ready;
reg en;
reg [15:0] pv;
reg [15:0] vd;
reg [15:0] pvd;
reg [15:0] varI;
wire [31:0] varS;
reg rest;
initial rest <= 1'b1;
booth_mult Multi(.clk(clk),.rst(rest), .en(en),.A(dt),.B(varI),.busy(ready),.R(varS));
//--------------------------------Modulo states
localparam
reset = 5'd0,
ini = 5'd1,
mulv = 5'd2,
check_1 = 5'd3,
afterv = 5'd4,
end_state= 5'd5;
// State Machine Regs
reg[4:0] state;
reg[4:0] next_state;
initial state = 0;
initial next_state = 0;
always @(posedge clk)begin
if(rst) state <= reset;
else state <= next_state;
end
always @(*)begin
case(state)
reset: begin
v <= 1'd0;
pv <= 1'd0;
busy <= 1'd1;
en <= 1'd0;
varI <= 1'd0;
rest <= 1'd1;
next_state <= ini;
end
ini: begin
busy <= 1'd0;
v <= vd;
pv <= pvd;
en <= 1'd0;
varI <= 1'd0;
rest <= 1'd1;
if (!enable) next_state <= ini;
else next_state <= mulv;
end
mulv: begin
v <= vd;
pv <= pvd;
busy <= 1'd1;
en <= 1'b1;
rest <=1'b0;
varI <= a;
next_state <= check_1;
end
check_1: begin
v <= vd;
busy <= 1'd1;
en <= 1'b1;
rest <= 1'b0;
varI <= a;
if (!ready) begin
next_state <= afterv;
pv <= v + varS;
end
else begin
pv <= pvd;
next_state <= check_1;
end
end
afterv: begin
v <= vd;
pv <= pvd;
busy <= 1'd1;
varI <= a;
rest <= 1'b1;
en <= 1'd0;
next_state <= end_state;
end
end_state:begin
pv <= pvd;
en <= 1'd0;
rest <=1'b1;
varI <= a;
v <= pv;
busy <= 1'd0;
if (!enable) next_state <= end_state;
else next_state <= ini;
end
default: begin
pv <= pvd;
en <= 1'd0;
rest <= 1'b1;
varI <= a;
v <= vd;
busy <= 1'd0;
next_state <= ini;
end
endcase
end
always @(negedge clk)begin
pvd <= pv;
vd <= v;
end
endmodule
|
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_cdma_ast_msi.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module construct of the Avalon Streaming receive port for the
// chaining DMA application MSI signals.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ast_msi (
input clk_in,
input rstn,
input app_msi_req,
output reg app_msi_ack,
input[2:0] app_msi_tc,
input[4:0] app_msi_num,
input stream_ready,
output reg [7:0] stream_data,
output reg stream_valid);
reg stream_ready_del;
reg app_msi_req_r;
wire [7:0] m_data;
assign m_data[7:5] = app_msi_tc[2:0];
assign m_data[4:0] = app_msi_num[4:0];
//------------------------------------------------------------
// Input register boundary
//------------------------------------------------------------
always @(negedge rstn or posedge clk_in) begin
if (rstn == 1'b0)
stream_ready_del <= 1'b0;
else
stream_ready_del <= stream_ready;
end
//------------------------------------------------------------
// Arbitration between master and target for transmission
//------------------------------------------------------------
// tx_state SM states
always @(negedge rstn or posedge clk_in) begin
if (rstn == 1'b0) begin
app_msi_ack <= 1'b0;
stream_valid <= 1'b0;
stream_data <= 8'h0;
app_msi_req_r <= 1'b0;
end
else begin
app_msi_ack <= stream_ready_del & app_msi_req;
stream_valid <= stream_ready_del & app_msi_req & ~app_msi_req_r;
stream_data <= m_data;
app_msi_req_r <= stream_ready_del ? app_msi_req : app_msi_req_r;
end
end
endmodule
|
#include <bits/stdc++.h> int a, b, c, d, n; char s[4 << 20]; void output() { for (int i = 0; i < n; ++i) if (s[i] == 4 ) a--; else b--; for (int i = 0; i < n; ++i) if (s[i] == 4 ) { while (a) { printf( 4 ); a--; } printf( 4 ); } else { while ((i + 2 >= n) && b) { printf( 7 ); b--; } printf( 7 ); } printf( n ); exit(0); } void look(char c4, char c7, int a, int b, int c, int d) { n = 0; while (c) { if (n) d--; s[n++] = c4; s[n++] = c7; a--; b--; c--; } if (d > 0) { s[n++] = c4; a--; d--; } if ((a < 0) || (b < 0) || (c != 0) || (d != 0)) return; output(); } int main() { scanf( %d%d%d%d , &a, &b, &c, &d); look( 4 , 7 , a, b, c, d); look( 7 , 4 , b, a, d, c); printf( -1 n ); return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: qdr_rld_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:36:29 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: QDRII+ SRAM / RLDRAM II SDRAM
//Purpose: Phase shift address/commands to center w.rto K/K# clocks at memory
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_LEN = 4, //Burst Length
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3636, // Internal clock period (in ps) - for a 550 MHz clk(clk period-1818ps), fabric clk period is 3636ps
parameter N_CTL_LANES = 3 // Number of control byte lanes
)
(
input clk, // half or quarter rate core clock
input rst, // half or quarter rate core clk reset
input cmd_delay_start,
//input phy_ctl_ready, // PHY Control Block is ready for operation
output reg [5:0] ctl_lane_cnt, // The control byte lane Phaser_Out
// being accessed
output reg po_stg2_f_incdec,// Inc/dec Phaser_Out fine delay line
output reg po_en_stg2_f, // Enable Phaser_Out fine delay inc/dec
output po_ck_addr_cmd_delay_done // Completed delaying Ck,addr,
// cmd and ctl Phaser_Outs
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (CLK_PERIOD > 5000 ? 4 :
CLK_PERIOD > 2500 ? 2 : 1);
localparam real FREQ_REF_PS = CLK_PERIOD/FREQ_REF_DIV;
localparam integer PHASER_TAP_RES = ((FREQ_REF_PS/2)/64);
// No. of Phaser taps for 1/4 of memory clock period
localparam CALC_TAP_CNT = (CLK_PERIOD / (4 * PHASER_TAP_RES));
//For now make sure our TAP_CNT calculation doesn't overflow
localparam TAP_CNT = (CALC_TAP_CNT > TAP_CNT_LIMIT) ?
TAP_CNT_LIMIT : CALC_TAP_CNT;
// // Quarter memory clock cycle in ps
// localparam DIV4_CK
// = ((CLK_PERIOD/nCK_PER_CLK)/4);
//
// // Determine the number of Phaser_Out taps required to delay by 300 ps
// // 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// localparam TAP_CNT = (300 + ((CLK_PERIOD/nCK_PER_CLK)/64) - 1)/
// ((CLK_PERIOD/nCK_PER_CLK)/64);
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] delay_cnt_r;
assign po_ck_addr_cmd_delay_done = (BURST_LEN == 2)? cmd_delay_start : delay_done_r4;
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst || ~cmd_delay_start || delay_done || (delay_cnt_r == 6'd1)) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end else if (((delay_cnt_r == 6'd0) || (delay_cnt_r == TAP_CNT)) && (ctl_lane_cnt < N_CTL_LANES)) begin
po_stg2_f_incdec <= #TCQ 1'b1;
po_en_stg2_f <= #TCQ 1'b1;
end
end
// delay counter to count TAP_CNT cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_CNT
if (rst || ~cmd_delay_start ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt < N_CTL_LANES)))
delay_cnt_r <= #TCQ TAP_CNT;
else if (po_en_stg2_f && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delay_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delay_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// when all the ctl_lanes have their output phase shifted by 1/4 cycle, delay shifting is done.
always @(posedge clk) begin
if (rst ) begin
delay_done <= #TCQ 1'b0;
//end else if (((delay_cnt_r == 6'd2) && (ctl_lane_cnt == N_CTL_LANES-1)) || (BURST_LEN == 2)) begin
end else if ((delay_cnt_r == 6'd2) && (ctl_lane_cnt == N_CTL_LANES-1)) begin
delay_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long int ll; typedef unsigned long long int ull; #define pii acos(-1) #define sc(n) scanf( %d ,&n) #define sc2(n,x) scanf( %d%d ,&n,&x) #define pr(n) printf( %d ,n) #define scl(n) scanf( %I64d ,&n) #define scl2(n,m) scanf( %I64d%I64d ,&n,&m) #define prl(n) printf( %I64d ,n) #define loop(x,n) for(int i=x;i<n;i++) #define mp make_pair #define pb push_back #define nl printf( n ) #define mod 998244353 #define lv -100000000 typedef pair<int,int> pi; #define fastio ios_base::sync_with_stdio(false);cin.tie(nullptr);cout.tie(nullptr) using namespace std; int a[300005],c[300005]; int main() { int t,n,k; cin>>t; while(t--) { cin>>n>>k; for(int i=0;i<n;i++) { cin>>a[i]; } for(int i=0;i<k;i++) { cin>>c[i]; } sort(a,a+n); ll ans=0; int l=0,flag=0; for(int i=n-1;i>=0;i--) { if(flag==0 && c[l]<=c[a[i]-1]&&l<k) { ans+=c[l]; l++; //cout<< YES <<endl; } else { flag++; ans+=c[a[i]-1]; } } cout<<ans<<endl; } } |
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