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//-----------------------------------------------------------------------------
// system_tb.v
//-----------------------------------------------------------------------------
`timescale 1 ps / 100 fs
`uselib lib=unisims_ver
// START USER CODE (Do not remove this line)
// User: Put your directives here. Code in this
// section will not be overwritten.
// END USER CODE (Do not remove this line)
module system_tb
(
);
// START USER CODE (Do not remove this line)
// User: Put your signals here. Code in this
// section will not be overwritten.
// END USER CODE (Do not remove this line)
real sys_clk_PERIOD = 10000.000000;
real sys_rst_LENGTH = 160000;
reg sys_clk;
reg sys_rst;
wire Bus2IP_Clk;
wire Bus2IP_Reset;
reg [0:31] IP2Bus_Data;
reg IP2Bus_WrAck;
reg IP2Bus_RdAck;
reg IP2Bus_AddrAck;
reg IP2Bus_Error;
wire [0:31] Bus2IP_Addr;
wire [0:31] Bus2IP_Data;
wire Bus2IP_RNW;
wire [0:3] Bus2IP_BE;
wire Bus2IP_Burst;
wire [0:7] Bus2IP_BurstLength;
wire Bus2IP_CS;
wire Bus2IP_WrReq;
wire Bus2IP_RdReq;
wire Bus2IP_RdCE;
wire Bus2IP_WrCE;
reg IP2Bus_MstRd_Req;
reg IP2Bus_MstWr_Req;
reg [0:31] IP2Bus_Mst_Addr;
reg [0:3] IP2Bus_Mst_BE;
reg IP2Bus_Mst_Lock;
reg IP2Bus_Mst_Reset;
wire Bus2IP_Mst_CmdAck;
wire Bus2IP_Mst_Cmplt;
wire Bus2IP_Mst_Error;
wire Bus2IP_Mst_Rearbitrate;
wire Bus2IP_Mst_Cmd_Timeout;
wire [0:31] Bus2IP_MstRd_d;
wire Bus2IP_MstRd_src_rdy_n;
reg [0:31] IP2Bus_MstWr_d;
wire Bus2IP_MstWr_dst_rdy_n;
wire tx_interrupt;
wire rx_interrupt;
reg DCR_Read;
reg DCR_Write;
reg [0:9] DCR_ABus;
reg [0:31] DCR_Sl_DBus;
wire Sl_dcrAck;
wire [0:31] Sl_dcrDBus;
wire Sl_dcrTimeoutWait;
system
dut (
.sys_clk ( sys_clk ),
.sys_rst ( sys_rst ),
.Bus2IP_Clk ( Bus2IP_Clk ),
.Bus2IP_Reset ( Bus2IP_Reset ),
.IP2Bus_Data ( IP2Bus_Data ),
.IP2Bus_WrAck ( IP2Bus_WrAck ),
.IP2Bus_RdAck ( IP2Bus_RdAck ),
.IP2Bus_AddrAck ( IP2Bus_AddrAck ),
.IP2Bus_Error ( IP2Bus_Error ),
.Bus2IP_Addr ( Bus2IP_Addr ),
.Bus2IP_Data ( Bus2IP_Data ),
.Bus2IP_RNW ( Bus2IP_RNW ),
.Bus2IP_BE ( Bus2IP_BE ),
.Bus2IP_Burst ( Bus2IP_Burst ),
.Bus2IP_BurstLength ( Bus2IP_BurstLength ),
.Bus2IP_CS ( Bus2IP_CS ),
.Bus2IP_WrReq ( Bus2IP_WrReq ),
.Bus2IP_RdReq ( Bus2IP_RdReq ),
.Bus2IP_RdCE ( Bus2IP_RdCE ),
.Bus2IP_WrCE ( Bus2IP_WrCE ),
.IP2Bus_MstRd_Req ( IP2Bus_MstRd_Req ),
.IP2Bus_MstWr_Req ( IP2Bus_MstWr_Req ),
.IP2Bus_Mst_Addr ( IP2Bus_Mst_Addr ),
.IP2Bus_Mst_BE ( IP2Bus_Mst_BE ),
.IP2Bus_Mst_Lock ( IP2Bus_Mst_Lock ),
.IP2Bus_Mst_Reset ( IP2Bus_Mst_Reset ),
.Bus2IP_Mst_CmdAck ( Bus2IP_Mst_CmdAck ),
.Bus2IP_Mst_Cmplt ( Bus2IP_Mst_Cmplt ),
.Bus2IP_Mst_Error ( Bus2IP_Mst_Error ),
.Bus2IP_Mst_Rearbitrate ( Bus2IP_Mst_Rearbitrate ),
.Bus2IP_Mst_Cmd_Timeout ( Bus2IP_Mst_Cmd_Timeout ),
.Bus2IP_MstRd_d ( Bus2IP_MstRd_d ),
.Bus2IP_MstRd_src_rdy_n ( Bus2IP_MstRd_src_rdy_n ),
.IP2Bus_MstWr_d ( IP2Bus_MstWr_d ),
.Bus2IP_MstWr_dst_rdy_n ( Bus2IP_MstWr_dst_rdy_n ),
.tx_interrupt ( tx_interrupt ),
.rx_interrupt ( rx_interrupt ),
.DCR_Read ( DCR_Read ),
.DCR_Write ( DCR_Write ),
.DCR_ABus ( DCR_ABus ),
.DCR_Sl_DBus ( DCR_Sl_DBus ),
.Sl_dcrAck ( Sl_dcrAck ),
.Sl_dcrDBus ( Sl_dcrDBus ),
.Sl_dcrTimeoutWait ( Sl_dcrTimeoutWait )
);
// Clock generator for sys_clk
initial
begin
sys_clk = 1'b0;
forever #(sys_clk_PERIOD/2.00)
sys_clk = ~sys_clk;
end
// Reset Generator for sys_rst
initial
begin
sys_rst = 1'b0;
#(sys_rst_LENGTH) sys_rst = ~sys_rst;
end
// START USER CODE (Do not remove this line)
wire [0:31] IP2Bus_Data_i;
wire IP2Bus_WrAck_i;
wire IP2Bus_RdAck_i;
wire IP2Bus_AddrAck_i;
wire IP2Bus_Error_i;
wire IP2Bus_MstRd_Req_i;
wire IP2Bus_MstWr_Req_i;
wire [0:31] IP2Bus_Mst_Addr_i;
wire [0:3] IP2Bus_Mst_BE_i;
wire IP2Bus_Mst_Lock_i;
wire IP2Bus_Mst_Reset_i;
wire [0:31] IP2Bus_MstWr_d_i;
wire DCR_Read_i;
wire DCR_Write_i;
wire [0:9] DCR_ABus_i;
wire [0:31] DCR_Sl_DBus_i;
always @(*)
begin
IP2Bus_Data = IP2Bus_Data_i;
IP2Bus_WrAck = IP2Bus_WrAck_i;
IP2Bus_RdAck = IP2Bus_RdAck_i;
IP2Bus_AddrAck = IP2Bus_AddrAck_i;
IP2Bus_Error = IP2Bus_Error_i;
IP2Bus_MstRd_Req=IP2Bus_MstRd_Req_i;
IP2Bus_MstWr_Req=IP2Bus_MstWr_Req_i;
IP2Bus_Mst_Addr=IP2Bus_Mst_Addr_i;
IP2Bus_Mst_BE=IP2Bus_Mst_BE_i;
IP2Bus_Mst_Lock=IP2Bus_Mst_Lock_i;
IP2Bus_Mst_Reset=IP2Bus_Mst_Reset_i;
IP2Bus_MstWr_d=IP2Bus_MstWr_d_i;
DCR_Sl_DBus = DCR_Sl_DBus_i;
DCR_ABus = DCR_ABus_i;
DCR_Read = DCR_Read_i;
DCR_Write = DCR_Write_i;
end
lldma_tb
lldma_tb (
.rx_interrupt(rx_interrupt),
.tx_interrrupt(tx_interrupt),
.Bus2IP_Clk ( Bus2IP_Clk ),
.Bus2IP_Reset ( Bus2IP_Reset ),
.IP2Bus_Data ( IP2Bus_Data_i ),
.IP2Bus_WrAck ( IP2Bus_WrAck_i ),
.IP2Bus_RdAck ( IP2Bus_RdAck_i ),
.IP2Bus_AddrAck ( IP2Bus_AddrAck_i ),
.IP2Bus_Error ( IP2Bus_Error_i ),
.Bus2IP_Addr ( Bus2IP_Addr ),
.Bus2IP_Data ( Bus2IP_Data ),
.Bus2IP_RNW ( Bus2IP_RNW ),
.Bus2IP_BE ( Bus2IP_BE ),
.Bus2IP_Burst ( Bus2IP_Burst ),
.Bus2IP_BurstLength ( Bus2IP_BurstLength ),
.Bus2IP_CS ( Bus2IP_CS ),
.Bus2IP_WrReq ( Bus2IP_WrReq ),
.Bus2IP_RdReq ( Bus2IP_RdReq ),
.Bus2IP_RdCE ( Bus2IP_RdCE ),
.IP2Bus_MstRd_Req ( IP2Bus_MstRd_Req_i ),
.IP2Bus_MstWr_Req ( IP2Bus_MstWr_Req_i ),
.IP2Bus_Mst_Addr ( IP2Bus_Mst_Addr_i ),
.IP2Bus_Mst_BE ( IP2Bus_Mst_BE_i ),
.IP2Bus_Mst_Lock ( IP2Bus_Mst_Lock_i ),
.IP2Bus_Mst_Reset ( IP2Bus_Mst_Reset_i ),
.Bus2IP_Mst_CmdAck ( Bus2IP_Mst_CmdAck ),
.Bus2IP_Mst_Cmplt ( Bus2IP_Mst_Cmplt ),
.Bus2IP_Mst_Error ( Bus2IP_Mst_Error ),
.Bus2IP_Mst_Rearbitrate ( Bus2IP_Mst_Rearbitrate ),
.Bus2IP_Mst_Cmd_Timeout ( Bus2IP_Mst_Cmd_Timeout ),
.Bus2IP_MstRd_d ( Bus2IP_MstRd_d ),
.Bus2IP_MstRd_src_rdy_n ( Bus2IP_MstRd_src_rdy_n ),
.IP2Bus_MstWr_d ( IP2Bus_MstWr_d_i ),
.Bus2IP_MstWr_dst_rdy_n ( Bus2IP_MstWr_dst_rdy_n ),
.DCR_Read ( DCR_Read_i ),
.DCR_Write ( DCR_Write_i ),
.DCR_ABus ( DCR_ABus_i ),
.DCR_Sl_DBus ( DCR_Sl_DBus_i ),
.Sl_dcrAck ( Sl_dcrAck ),
.Sl_dcrDBus ( Sl_dcrDBus ),
.Sl_dcrTimeoutWait ( Sl_dcrTimeoutWait )
);
// END USER CODE (Do not remove this line)
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; char ar[n]; for (int i = 0; i < n; ++i) { cin >> ar[i]; } int co = 0; vector<int> po; for (int i = 0; i < n - 1; ++i) { if (ar[i] == W ) { ar[i] = B ; co++; po.push_back(i + 1); if (ar[i + 1] == B ) { ar[i + 1] = W ; } else { ar[i + 1] = B ; } } } if (ar[n - 1] == B ) { cout << co << endl; for (int i = 0; i < po.size(); ++i) { cout << po[i] << ; } cout << endl; } else { if (n % 2 == 0) { cout << -1 << endl; } else { cout << co + (n - 1) / 2 << endl; for (int i = 0; i < po.size(); ++i) { cout << po[i] << ; } for (int i = 0; i < (n - 1) / 2; ++i) { cout << 2 * i + 1 << ; } cout << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_TB_V
`define SKY130_FD_SC_LP__DLRTN_TB_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_lp__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_TB_V
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [5:0] cond;
reg [2:1] expr;
integer result;
always @(cond or expr) begin
casex (cond)
6'b01_??10 : result = 1;
{2'b10, 4'b??10} : result = 2;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{expr[1:0], 4'b??01} : result = 3;
expr[11:6] : result = 4;
`else
{expr[1], 1'bx, 4'b??01} : result = 3;
6'bxxxxxx : result = 4;
`endif
default : result = 0;
endcase
end
initial begin
pass = 1'b1;
expr = 2'b10;
cond = 6'b01_xx10;
#1 if (result != 1) begin
$display("Failed case expr 1 test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'bxx_xxxx;
#1 if (result != 1) begin
$display("Failed case expr 1a test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'b10_zz10;
#1 if (result != 2) begin
$display("Failed case expr 2 test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'b0x_zz01;
#1 if (result != 3) begin
$display("Failed case expr 3 test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'b11_1111;
#1 if (result != 4) begin
$display("Failed case expr 1a test, got expr %0d", result);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> using min_pq = priority_queue<T, vector<T>, greater<T>>; template <typename T> using max_pq = priority_queue<T>; const int inf = 2e9 + 5; const long long l_inf = 2e18 + 5; const int mod_v = 1e9 + 7; const int max_n = 1e5 + 5; const int dx[4] = {-1, 0, 1, 0}; const int dy[4] = {0, 1, 0, -1}; template <typename T> T gcd(T a, T b) { while (b) { T temp = a % b; a = b; b = temp; } return a; } template <typename T> tuple<T, T, T> egcd(T a, T b) { T x1 = 1, x2 = 0, y1 = 0, y2 = 1; while (b) { T q = a / b, r = a % b; T new_x = x1 - q * x2, new_y = y1 - q * y2; x1 = x2, y1 = y2, x2 = new_x, y2 = new_y; a = b, b = r; } return make_tuple(a, x1, y1); } inline long long lcm(long long a, long long b) { return a * b / gcd(a, b); } template <typename T> inline T mod(T a, T b = mod_v) { return (a % b + b) % b; } template <typename T> inline T mod_inv(T a, T b = mod_v) { return mod(get<1>(egcd(a, b)), b); } template <typename T> inline T sum(T a, T b, T m = mod_v) { return mod(mod(a, m) + mod(b, m), m); } template <typename T> inline T difference(T a, T b, T m = mod_v) { return mod(mod(a, m) - mod(b, m), m); } inline long long product(long long a, long long b, long long m = mod_v) { return mod(mod(a, m) * mod(b, m), m); } inline long long quotient(long long a, long long b, long long m = mod_v) { return mod(mod(a, m) * mod_inv(b, m), m); } template <typename T, typename T2> ostream &operator<<(ostream &s, const pair<T, T2> &p) { return s << p.first << << p.second << ; } template <typename T, typename T2> istream &operator>>(istream &s, pair<T, T2> &p) { return s >> p.first >> p.second; } template <typename T> ostream &operator<<(ostream &s, const vector<T> &v) { for (auto it : v) s << it << ; return s; } template <typename T> istream &operator>>(istream &s, vector<T> &v) { for (auto it = (v).begin(), it_ = (v).end(); it != it_; ++it) s >> *it; return s; } template <typename T> void read_range(T beg, T end) { while (beg != end) cin >> *beg++; } template <typename T> void print_range(T beg, T end) { while (beg != end) cout << *beg++ << ; } struct reader { template <typename T> reader &operator,(T &v) { cin >> v; return *this; } } rdr; struct debugger { template <typename T> debugger &operator,(const T &v) { cerr << v << , ; return *this; } } dbg; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int x[2]; cin >> x[0] >> x[1]; int a[2] = {0, 0}; for (int i = 0;; ++i) { int n_a; if (i / 2 % 2) n_a = a[i % 2] - (i / 2 + 1); else n_a = a[i % 2] + (i / 2 + 1); if (a[1 - i % 2] == x[1 - i % 2] and ((x[i % 2] >= a[i % 2] and x[i % 2] <= n_a) or (x[i % 2] <= a[i % 2] and x[i % 2] >= n_a))) { cout << i; return 0; } a[i % 2] = n_a; } return 0; } |
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: gamma_module
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV and Cyclone 10 LP devices
// Tool versions: Altera Quartus Prime
// Description: gamma correction (nDSYNC synchronuous)
//
//////////////////////////////////////////////////////////////////////////////////
module gamma_module(
VCLK,
nRST,
gammaparams_i,
vdata_valid_i,
vdata_i,
vdata_valid_o,
vdata_o
);
`include "vh/n64adv_vparams.vh"
`include "vh/n64adv_ppuconfig.vh"
input VCLK;
input nRST;
input [ 3:0] gammaparams_i;
input vdata_valid_i;
input [`VDATA_I_FU_SLICE] vdata_i;
output reg vdata_valid_o;
output reg [`VDATA_I_FU_SLICE] vdata_o = {vdata_width_i{1'b0}};
// translate gamma table
wire en_gamma_boost = ~(gammaparams_i == `GAMMA_TABLE_OFF);
wire [3:0] gamma_rom_page_tmp = (gammaparams_i < `GAMMA_TABLE_OFF) ? gammaparams_i :
gammaparams_i - 1'b1;
wire [2:0] gamma_rom_page = gamma_rom_page_tmp[2:0];
// connect data tables (output has delay of two)
wire [`VDATA_I_CO_SLICE] gamma_vdata_out;
reg [1:0] vdata_i_cnt = 2'b00;
reg [color_width_i-1:0] gamma_vdata_i = {color_width_i{1'b0}};
wire [color_width_i-1:0] gamma_vdata_o;
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_i_cnt <= 2'b00;
gamma_vdata_i <= {color_width_i{1'b0}};
end else begin
if (vdata_valid_i) begin
vdata_i_cnt <= 2'b01;
gamma_vdata_i <= vdata_i[`VDATA_I_RE_SLICE];
end else begin
if (vdata_i_cnt == 2'b01)
gamma_vdata_i <= vdata_i[`VDATA_I_GR_SLICE];
if (vdata_i_cnt == 2'b10)
gamma_vdata_i <= vdata_i[`VDATA_I_BL_SLICE];
vdata_i_cnt <= vdata_i_cnt + 2'b01;
end
end
gamma_table gamma_table_re_u(
.VCLK(VCLK),
.nRST(nRST),
.gamma_val(gamma_rom_page),
.vdata_in(gamma_vdata_i),
.nbypass(en_gamma_boost),
.vdata_out(gamma_vdata_o)
);
// delay of remaining components
reg vdata_valid_L[0:2];
reg [3:0] vdata_sync_L[0:2];
integer int_idx;
initial begin
for (int_idx = 0; int_idx < 3; int_idx = int_idx+1) begin
vdata_valid_L[int_idx] = 1'b0;
vdata_sync_L[int_idx] = 4'h0;
end
end
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
for (int_idx = 0; int_idx < 3; int_idx = int_idx+1) begin
vdata_valid_L[int_idx] <= 1'b0;
vdata_sync_L[int_idx] <= 4'h0;
end
end else begin
vdata_valid_L[2] <= vdata_valid_L[1];
vdata_valid_L[1] <= vdata_valid_L[0];
vdata_valid_L[0] <= vdata_valid_i;
vdata_sync_L[2] <= vdata_sync_L[1];
vdata_sync_L[1] <= vdata_sync_L[0];
vdata_sync_L[0] <= vdata_i[`VDATA_I_SY_SLICE];
end
// collect outputs
reg [1:0] vdata_o_cnt = 2'b00;
reg [`VDATA_I_FU_SLICE] vdata_o_pre = {vdata_width_i{1'b0}};
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_o_cnt <= 2'b00;
vdata_o_pre <= {vdata_width_i{1'b0}};
end else begin
if (vdata_valid_L[2]) begin
vdata_o_cnt <= 2'b01;
vdata_o_pre[`VDATA_I_SY_SLICE] <= vdata_sync_L[2];
vdata_o_pre[`VDATA_I_RE_SLICE] <= gamma_vdata_o;
end else begin
if (vdata_o_cnt == 2'b01)
vdata_o_pre[`VDATA_I_GR_SLICE] <= gamma_vdata_o;
if (vdata_o_cnt == 2'b10)
vdata_o_pre[`VDATA_I_BL_SLICE] <= gamma_vdata_o;
vdata_o_cnt <= vdata_o_cnt + 2'b01;
end
end
// registered output
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_o <= {vdata_width_i{1'b0}};
end else begin
vdata_valid_o <= vdata_valid_L[2];
if (vdata_valid_L[2])
vdata_o <= vdata_o_pre;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 21 11:58:18 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[31:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[31:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [63:0]probe8;
input [31:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [7:0]probe13;
input [63:0]probe14;
input [31:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [0:0]probe19;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000000000 ) using namespace std; int n, l[30], m[30], w[30]; int tw[30], P1, P2; map<pair<long long, long long>, pair<long long, long long> > mp; long long best = -(1ll << 58), msk1, msk2; void rec(int p, int msk, long long L, long long M, long long W) { if (p == P1) { pair<long long, long long> tmp = make_pair(L - M, L - W); if (mp.find(tmp) == mp.end()) mp[tmp] = make_pair(L, msk); else if (mp[tmp].first < L) { mp[tmp] = make_pair(L, msk); } return; } rec(p + 1, msk * 3, L, M + m[p], W + w[p]); rec(p + 1, msk * 3 + 1, L + l[p], M, W + w[p]); rec(p + 1, msk * 3 + 2, L + l[p], M + m[p], W); } void rec2(int p, int msk, long long L, long long M, long long W) { if (p == n) { pair<long long, long long> tmp = make_pair(-(L - M), -(L - W)); if (mp.find(tmp) == mp.end()) return; pair<long long, long long> tmp2 = mp[tmp]; long long sum = L + tmp2.first; if (sum < best) return; best = sum; msk1 = tmp2.second; msk2 = msk; return; } rec2(p + 1, msk * 3, L, M + m[p], W + w[p]); rec2(p + 1, msk * 3 + 1, L + l[p], M, W + w[p]); rec2(p + 1, msk * 3 + 2, L + l[p], M + m[p], W); } void print(int x, int msk) { if (x == 0) return; print(x - 1, msk / 3); if (msk % 3 == 0) printf( MW n ); else if (msk % 3 == 1) printf( LW n ); else printf( LM n ); } int main() { for (int i = 0; i < 30; i++) tw[i] = 1 << i; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d %d , &l[i], &m[i], &w[i]); } P1 = n / 2, P2 = n - P1; rec(0, 0, 0, 0, 0); rec2(P1, 0, 0, 0, 0); if (best == -(1ll << 58)) printf( Impossible n ); else { print(P1, msk1); print(P2, msk2); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { if (x < 0) return -x; return x; } template <class T> T sqr(T a) { return a * a; } const double pi = acos(-1.0); const double eps = 1e-8; int i, n, cnt; char s1[110], s2[110]; void fun1() { if (s1[i + 1] == 0 ) { s1[i + 1] = X ; cnt++; } else if (s2[i + 1] == 0 ) { s2[i + 1] = X ; cnt++; } } void fun2() { if (s1[i + 1] == 0 && s2[i + 1] == 0 ) { s1[i + 1] = X ; s2[i + 1] = X ; cnt++; } } int main() { while (2 == scanf( %s%s , &s1, s2)) { cnt = 0; n = strlen(s1); for (i = 0; i < n - 1; i++) { if (s1[i] == 0 && s2[i] == 0 ) fun1(); if (s1[i] == 0 || s2[i] == 0 ) fun2(); } printf( %d n , cnt); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; string s; int pre[N], nxt0[N], now = 100002; int ans[N]; int n; void init() { vector<int> v; for (int i = n - 1; i >= 1; i--) { int p = s[i] - 0 ; int pos = upper_bound(v.begin(), v.end(), -p) - v.begin(); if (pos == v.size()) { v.push_back(-p); } else { v[pos] = -p; } ans[i] = v.size(); } } int main() { ios::sync_with_stdio(false); cin >> s; s = * + s; n = s.length(); init(); for (int i = 1; i < n; i++) pre[i] = pre[i - 1] + (s[i] == 1 ); for (int i = n - 1; i >= 1; i--) { nxt0[i] = now; if (s[i] == 0 ) now = i; } for (int i = 1; i <= n; i++) { if (s[i] == 0 ) continue; if (s[i - 1] == 1 ) continue; int zuo1 = pre[i - 1], you1 = pre[n - 1] - pre[i], you0 = (n - 1 - i) - you1; int youmx = ans[nxt0[i]]; if (youmx <= you1) { s[i] = 0 ; } } for (int i = 1; i < n; i++) cout << s[i]; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_PP_SYMBOL_V
`define SKY130_FD_SC_LS__MUX2I_PP_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_2_V
`define SKY130_FD_SC_HD__OR3_2_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_2_V
|
#include <bits/stdc++.h> int main(void) { int n; char s[102]; scanf( %d n , &n); gets(s); if (s[0] == S && s[n - 1] == F ) { printf( YES ); } else { printf( NO ); } } |
`default_nettype none
module execute_forwarding_register(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Writeback - General Register
input wire iWB_GR_VALID,
input wire [31:0] iWB_GR_DATA,
input wire [4:0] iWB_GR_DEST,
input wire iWB_GR_DEST_SYSREG,
//Writeback - Stack Point Register
input wire iWB_SPR_VALID,
input wire [31:0] iWB_SPR_DATA,
//Writeback[AUTO] - Stack Point Register
input wire iWB_AUTO_SPR_VALID,
input wire [31:0] iWB_AUTO_SPR_DATA,
//Current - Stack Point Register
input wire [31:0] iCUUR_SPR_DATA,
//Writeback - FRCR
input wire iWB_FRCR_VALID,
input wire [63:0] iWB_FRCR_DATA,
//Current - FRCR
input wire [63:0] iCUUR_FRCR_DATA,
//Fowerding Register Output
output wire oFDR_GR_VALID,
output wire [31:0] oFDR_GR_DATA,
output wire [4:0] oFDR_GR_DEST,
output wire oFDR_GR_DEST_SYSREG,
//Fowerding Register Output
output wire oFDR_SPR_VALID,
output wire [31:0] oFDR_SPR_DATA,
//Forwerding Register Output
output wire oFDR_FRCR_VALID,
output wire [63:0] oFDR_FRCR_DATA
);
//Fowarding General Register
reg b_ex_history_valid;
reg [31:0] b_ex_history_data;
reg [4:0] b_ex_history_destination;
reg b_ex_history_destination_sysreg;
//reg [31:0] b_ex_history_pc;
//Fowarding Stack Point Register
reg b_fwdng_spr_valid;
reg [31:0] b_fwdng_spr;
//FRCR
reg b_fwdng_frcr_valid;
reg [63:0] b_fwdng_frcr;
/************************************************************************
Fowarding Register
************************************************************************/
//General Register
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ex_history_valid <= 1'h0;
b_ex_history_data <= 32'h0;
b_ex_history_destination <= 5'h0;
b_ex_history_destination_sysreg <= 1'h0;
//b_ex_history_pc <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ex_history_valid <= 1'h0;
b_ex_history_data <= 32'h0;
b_ex_history_destination <= 5'h0;
b_ex_history_destination_sysreg <= 1'h0;
//b_ex_history_pc <= 32'h0;
end
else begin
if(iWB_GR_VALID)begin
b_ex_history_valid <= iWB_GR_VALID;
b_ex_history_data <= iWB_GR_DATA;
b_ex_history_destination <= iWB_GR_DEST;
b_ex_history_destination_sysreg <= iWB_GR_DEST_SYSREG;
//b_ex_history_pc <= iWB_PCR - 32'h00000004;
end
end
end
//Stack Point Register
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_fwdng_spr_valid <= 1'h0;
b_fwdng_spr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_fwdng_spr_valid <= 1'h0;
b_fwdng_spr <= 32'h0;
end
else begin
if(iWB_SPR_VALID)begin
b_fwdng_spr_valid <= iWB_SPR_VALID;
b_fwdng_spr <= iWB_SPR_DATA;
end
else if(iWB_AUTO_SPR_VALID)begin
b_fwdng_spr_valid <= iWB_SPR_VALID;
b_fwdng_spr <= iWB_AUTO_SPR_DATA;
end
else begin
b_fwdng_spr_valid <= 1'b1;
b_fwdng_spr <= iCUUR_SPR_DATA;
end
end
end
//FRCR
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_fwdng_frcr_valid <= 1'h0;
b_fwdng_frcr <= 64'h0;
end
else if(iRESET_SYNC)begin
b_fwdng_frcr_valid <= 1'h0;
b_fwdng_frcr <= 64'h0;
end
else begin
if(iWB_FRCR_VALID)begin
b_fwdng_frcr_valid <= iWB_FRCR_VALID;
b_fwdng_frcr <= iWB_FRCR_DATA;
end
else begin
b_fwdng_frcr_valid <= 1'h1;
b_fwdng_frcr <= iCUUR_FRCR_DATA;
end
end
end
/************************************************************************
Assign
************************************************************************/
//GR Out
assign oFDR_GR_VALID = b_ex_history_valid;
assign oFDR_GR_DATA = b_ex_history_data;
assign oFDR_GR_DEST = b_ex_history_destination;
assign oFDR_GR_DEST_SYSREG = b_ex_history_destination_sysreg;
//SPR Out
assign oFDR_SPR_VALID = b_fwdng_spr_valid;
assign oFDR_SPR_DATA = b_fwdng_spr;
//FRCR Out
assign oFDR_FRCR_VALID = b_fwdng_frcr_valid;
assign oFDR_FRCR_DATA = b_fwdng_frcr;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 100; int f[N]; struct node { int u, v, w; bool operator<(const node& a) const { return w < a.w; } }; struct qq { int id, u, v, w; bool operator<(const qq& a) const { if (a.w == w) return id < a.id; return w < a.w; } }; vector<pair<int, int> > v; qq q[N]; node pt[N]; bool vis[N]; int Find(int x, bool tmp) { if (tmp) v.push_back({x, f[x]}); return x == f[x] ? x : f[x] = Find(f[x], tmp); } int main() { int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { scanf( %d %d %d , &pt[i].u, &pt[i].v, &pt[i].w); } int qs; cin >> qs; int tot = 0; for (int i = 1; i <= qs; i++) { int k; scanf( %d , &k); for (int j = 1; j <= k; j++) { q[tot].id = i; int now; scanf( %d , &now); q[tot].u = pt[now].u; q[tot].v = pt[now].v; q[tot].w = pt[now].w; tot++; } } sort(q, q + tot); sort(pt + 1, pt + 1 + m); int cnt = 0; for (int i = 1; i <= n; i++) f[i] = i; for (int i = 1; i <= m; i++) { while (cnt < tot && q[cnt].w == pt[i].w) { queue<qq> que; que.push(q[cnt]); int tmp = q[cnt].id; for (int j = cnt + 1; j <= tot; j++) { if (q[j].w == q[j - 1].w && q[j].id == q[j - 1].id) que.push(q[j]); else { cnt = j; break; } } bool res = true; while (!que.empty()) { qq now = que.front(); que.pop(); int f1 = Find(now.u, true); int f2 = Find(now.v, true); if (f1 == f2) { res = false; break; } f[f1] = f2; v.push_back({f1, f1}); } if (res == false) vis[tmp] = true; for (int i = v.size() - 1; i >= 0; i--) { f[v[i].first] = v[i].second; } v.clear(); } int f1 = Find(pt[i].u, false); int f2 = Find(pt[i].v, false); if (f1 == f2) continue; f[f1] = f2; } int cns = 0; for (int i = 1; i <= n; i++) if (Find(i, false) == i) cns++; if (cns >= 2) { for (int i = 1; i <= qs; i++) { puts( NO ); } } else { for (int i = 1; i <= qs; i++) { if (vis[i]) puts( NO ); else puts( YES ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, x, k; cin >> n >> k; vector<long long> v; set<long long> s; map<long long, long long> m; for (long long i = 0; i < n; i++) { cin >> x; if (m[x] == 0) { m[x]++; v.insert(v.begin(), x); } if (v.size() > k) { m[v.back()] = 0; v.pop_back(); } } long long a = v.size(); cout << min((a), k) << endl; for (long long i = 0; i < v.size(); i++) { cout << v[i] << ; } } |
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A qa_wrapper with a buffer_BB.
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output reg [WDTH-1:0] out_data,
output reg out_nd
);
wire rst_n;
assign rst_n = ~reset;
reg read_delete;
wire read_full;
wire [WDTH-1:0] read_data;
wire write_error;
wire read_error;
buffer_BB #(WDTH, `BUFFER_LENGTH, `LOG_BUFFER_LENGTH)
the_buffer
(.clk(clk),
.rst_n(rst_n),
.write_strobe(in_nd),
.write_data(in_data),
.read_delete(read_delete),
.read_full(read_full),
.read_data(read_data),
.write_error(write_error),
.read_error(read_error)
);
always @ (posedge clk)
begin
if (!rst_n)
begin
read_delete <= 1'b0;
out_data <= {WDTH{1'b0}};
out_nd <= 1'b0;
end
else
if (write_error)
begin
out_nd <= 1'b1;
out_data <= `WRITEERRORCODE;
read_delete <= 1'b0;
end
else if (read_error)
begin
out_nd <= 1'b1;
out_data <= `READERRORCODE;
read_delete <= 1'b0;
end
else
begin
if (read_full)
begin
read_delete <= 1'b1;
out_nd <= 1'b1;
out_data <= read_data;
end
else
begin
read_delete <= 1'b0;
out_nd <= 1'b0;
end
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 5; const int CNTV = 105; const int LENSUFF = 11; const int K = 4; const int MOD = 1e9 + 9; struct node { int go[K], suff, p, pch, lev, cr; node() { memset(go, -1, sizeof go); suff = p = pch = cr = -1; lev = 0; } }; int sz = 1, num[256]; node a[CNTV]; inline void add(string second) { int v = 0; for (int i = 0; i < second.size(); ++i) { int c = num[second[i]]; if (a[v].go[c] == -1) { a[sz].lev = a[v].lev + 1; a[sz].p = v; a[sz].pch = c; a[v].go[c] = sz++; } v = a[v].go[c]; } a[v].cr = v; } int go(int v, int c); int sufflink(int v); int go(int v, int c) { if (a[v].go[c] != -1) return a[v].go[c]; if (v == 0) return a[v].go[c] = 0; return a[v].go[c] = go(sufflink(v), c); } int sufflink(int v) { if (v == 0 || a[v].p == 0) return a[v].suff = 0; if (a[v].suff != -1) return a[v].suff; return a[v].suff = go(sufflink(a[v].p), a[v].pch); } int cross(int v) { if (a[v].cr != -1) return a[v].cr; return a[v].cr = cross(sufflink(v)); } int n, m, dp[N][CNTV][LENSUFF]; int main() { num[ A ] = 0; num[ C ] = 1; num[ G ] = 2; num[ T ] = 3; a[0].cr = 0; cin >> n >> m; string second; for (int i = 0; i < m; ++i) { cin >> second; add(second); } dp[0][0][0] = 1; for (int len = 0; len < n; ++len) for (int v = 0; v < sz; ++v) for (int need = 0; need < 10; ++need) for (int c = 0; c < 4; ++c) { int to = go(v, c); if (a[to].lev >= need + 1) { int cr = cross(to); if (a[cr].lev >= need + 1) dp[len + 1][to][0] = (dp[len + 1][to][0] + dp[len][v][need]) % MOD; else dp[len + 1][to][need + 1] = (dp[len + 1][to][need + 1] + dp[len][v][need]) % MOD; } } int ans = 0; for (int v = 0; v < sz; ++v) ans = (ans + dp[n][v][0]) % MOD; cout << ans; return 0; } |
//======================================================================
//
// tb_coretest_test_core.v
// -----------------------
// Testbench for the coretest_test_core module.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/10ps
module tb_coretest_test_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_rxd;
wire tb_txd;
wire tb_rxd_syn;
wire [7 : 0] tb_rxd_data;
wire tb_rxd_ack;
wire tb_txd_syn;
wire [7 : 0] tb_txd_data;
wire tb_txd_ack;
wire [7 : 0] tb_debug;
reg txd_state;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
coretest_test_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.rxd(tb_rxd),
.txd(tb_txd),
.debug(tb_debug)
);
//----------------------------------------------------------------
// Concurrent assignments.
//----------------------------------------------------------------
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor
//----------------------------------------------------------------
always
begin : sys_monitor
#(CLK_PERIOD);
if (VERBOSE)
begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
// tx_monitor
//
// Observes what happens on the dut tx port and reports it.
//----------------------------------------------------------------
always @*
begin : tx_monitor
if ((!tb_txd) && txd_state)
begin
$display("txd going low.");
txd_state = 0;
end
if (tb_txd && (!txd_state))
begin
$display("txd going high");
txd_state = 1;
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dut when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("State of DUT");
$display("------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_rxd = 1;
txd_state = 1;
end
endtask // init_sim
//----------------------------------------------------------------
// transmit_byte
//
// Transmit a byte of data to the DUT receive port.
//----------------------------------------------------------------
task transmit_byte(input [7 : 0] data);
integer i;
begin
$display("*** Transmitting byte 0x%02x to the dut.", data);
#10;
// Start bit
$display("*** Transmitting start bit.");
tb_rxd = 0;
#(CLK_PERIOD * dut.uart.DEFAULT_CLK_RATE);
// Send the bits LSB first.
for (i = 0 ; i < 8 ; i = i + 1)
begin
$display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
tb_rxd = data[i];
#(CLK_PERIOD * dut.uart.DEFAULT_CLK_RATE);
end
// Send two stop bits. I.e. two bit times high (mark) value.
$display("*** Transmitting two stop bits.");
tb_rxd = 1;
#(2 * CLK_PERIOD * dut.uart.DEFAULT_CLK_RATE * dut.uart.DEFAULT_STOP_BITS);
$display("*** End of transmission.");
end
endtask // transmit_byte
//----------------------------------------------------------------
// check_transmit
//
// Transmits a byte and checks that it was captured internally
// by the dut.
//----------------------------------------------------------------
task check_transmit(input [7 : 0] data);
begin
tc_ctr = tc_ctr + 1;
transmit_byte(data);
// if (dut.core.rxd_byte_reg == data)
// begin
// $display("*** Correct data: 0x%01x captured by the dut.",
// dut.core.rxd_byte_reg);
// end
// else
// begin
// $display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.",
// dut.core.rxd_byte_reg, data);
// error_ctr = error_ctr + 1;
// end
end
endtask // check_transmit
//----------------------------------------------------------------
// test_transmit
//
// Transmit a number of test bytes to the dut.
//----------------------------------------------------------------
task test_transmit();
begin
// Send reset command.
$display("*** Sending reset command.");
check_transmit(8'h55);
check_transmit(8'h01);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to CORE ID0 in test core.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h00);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to CORE ID2 in test core.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h01);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to rw-register in test_core. 11223344.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h10);
check_transmit(8'haa);
// Send write command.
$display("*** Sending Write command to rw-register in test_core. deadbeef.");
check_transmit(8'h55);
check_transmit(8'h11);
check_transmit(8'h01);
check_transmit(8'h10);
check_transmit(8'hde);
check_transmit(8'had);
check_transmit(8'hbe);
check_transmit(8'hef);
check_transmit(8'haa);
// Send read command.
$display("*** Sending Read command to rw-register in test_core. deadbeef.");
check_transmit(8'h55);
check_transmit(8'h10);
check_transmit(8'h01);
check_transmit(8'h10);
check_transmit(8'haa);
// Send write command.
$display("*** Sending Write command to debug-register in test_core. 77.");
check_transmit(8'h55);
check_transmit(8'h11);
check_transmit(8'h01);
check_transmit(8'h20);
check_transmit(8'h00);
check_transmit(8'h00);
check_transmit(8'h00);
check_transmit(8'h77);
check_transmit(8'haa);
end
endtask // test_transmit
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// coretest_test_core
// The main test functionality.
//----------------------------------------------------------------
initial
begin : uart_test
$display(" -- Testbench for coretest_test_core started --");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
test_transmit();
$display("*** transmit done.");
#( * CLK_PERIOD);
$display("*** Wait completed.");
display_test_result();
$display("*** Simulation done.");
$finish;
end // uart_test
endmodule // tb_uart
//======================================================================
// EOF tb_coretest_test_core.v
//======================================================================
|
`timescale 1ns / 1ps
`define NULL 0
`define abs(a) ((a)<0 ? -(a):(a))
// Engineer: Jose Fernando Zazo
// Description:
// Utility to replay a packets from a pcap file over a 64-bit for use in network test benches.
// Based on the original work of Chris Shucksmith (https://github.com/shuckc/)
module pcap_parse #(
parameter pcap_filename = "none",
parameter use_custom_ifg = "TRUE",
parameter default_ifg = 6 ,
parameter play_in_loop = 0 ,
parameter n_loops = 0 ,
parameter CLOCK_FREQ_HZ = 156250000,
parameter AXIS_WIDTH = 64
) (
input pause ,
output reg [ AXIS_WIDTH-1:0] data , // .data
output reg [(AXIS_WIDTH/8)-1:0] strb , // .strb
input wire ready , // .ready
output reg valid , // .valid
output reg eop , // .endofpacket
input wire clk , // clk
output reg [ 15:0] pktcount ,
output reg pcapfinished
);
// buffers for message
reg [7:0] global_header[0:23];
reg [7:0] packet_header[0:15];
integer swapped ;
integer file ;
integer r ;
integer eof ;
integer i ;
integer j ;
integer pktSz ;
integer diskSz ;
integer nsPrecision ;
integer timestamp_msb;
integer timestamp_lsb;
integer current_loop ;
// read global header
// fields of interest are U32 so bear in mind the byte ordering when assembling
// multibyte fields
// This routine initializes the variables:
// · global_header
// · swapped
// · nsPrecision
task readGlobalHeader();
begin
// read binary global_header
r = $fread(global_header,file);
// check magic signature to determine byte ordering
if (global_header[3] == 8'hA1 && global_header[2] == 8'hB2) begin
$display(" pcap endian: swapped");
swapped = 1;
end else if (global_header[0] == 8'hA1 && global_header[1] == 8'hB2) begin
$display(" pcap endian: native");
swapped = 0;
end else begin
$display(" pcap endian: unrecognised format");
$finish;
end
if ((swapped && global_header[0] == 8'h4D && global_header[1] == 8'h3C)
|| (global_header[3] == 8'h4D && global_header[2] == 8'h3C)) begin
$display(" pcap precission: nanoseconds");
nsPrecision = 1;
end else if ((swapped && global_header[0] == 8'hD4 && global_header[1] == 8'hC3)
|| (global_header[3] == 8'hD4 && global_header[2] == 8'hC3)) begin
$display(" pcap precission: microseconds");
nsPrecision = 0;
end else begin
$display(" pcap magic number: unrecognised format");
$finish;
end
end
endtask : readGlobalHeader
// read packet header
// fields of interest are U32 so bear in mind the byte ordering when assembling
// multibyte fields
// This routine initializes the variables:
// · timestamp_msb
// · timestamp_lsb
// · pktSz
// · diskSz
task readPacketHeader();
begin
r = $fread(packet_header, file);
if (swapped == 1) begin
timestamp_msb = {packet_header[3],packet_header[2],packet_header[1],packet_header[0] };
timestamp_lsb = {packet_header[7],packet_header[6],packet_header[5],packet_header[4] };
pktSz = {packet_header[11],packet_header[10],packet_header[9] ,packet_header[8] };
diskSz = {packet_header[15],packet_header[14],packet_header[13],packet_header[12]};
end else begin
timestamp_msb = {packet_header[0],packet_header[1],packet_header[2],packet_header[3] };
timestamp_lsb = {packet_header[4],packet_header[5],packet_header[6],packet_header[7] };
pktSz = {packet_header[ 8],packet_header[ 9],packet_header[10],packet_header[11]};
diskSz = {packet_header[12],packet_header[13],packet_header[14],packet_header[15]};
end
$display("PCAP: packet %0d: incl_length %0d orig_length %0d", pktcount, pktSz, diskSz );
end
endtask : readPacketHeader
// Load into data and strb the content of a dataframe
task readPacket();
begin
for (j=0 ; j < AXIS_WIDTH/8 ; j = j+1) begin
if (diskSz < j+1) begin
data[j*8+:8] <= 8'b0;
strb[j] = 1'b0;
end else begin
data[j*8+:8] <= $fgetc(file);
strb[j] = 1'b1;
end
end
end
endtask : readPacket
initial begin
swapped = 0;
file = 0;
r = 0;
eof = 0;
i = 0;
pktSz = 0;
diskSz = 0;
nsPrecision = 0;
timestamp_msb = 0;
timestamp_lsb = 0;
pktcount = 0;
pcapfinished = 0;
pause_ifg = 0;
state_ifg = 0;
current_loop = 0;
// open pcap file
if (pcap_filename == "none") begin
$display("pcap filename parameter not set");
$finish;
end
file = $fopen(pcap_filename, "rb");
if (file == `NULL) begin
$display("can't read pcap input %s", pcap_filename);
$finish;
end
// Initialize Inputs
$display("PCAP: %m reading from %s", pcap_filename);
readGlobalHeader();
end
reg pause_ifg ;
reg [ 1:0] state_ifg ;
reg [31:0] cnt_ifg ;
integer previous_packet_timestamp_msb;
integer previous_packet_timestamp_lsb;
wire [63:0] previous_packet_real_timestamp ;
wire [63:0] real_timestamp ;
real ns_per_cycle = 1.0/CLOCK_FREQ_HZ*1e9;
assign previous_packet_real_timestamp = nsPrecision ?
previous_packet_timestamp_msb*1e9 + previous_packet_timestamp_lsb
: previous_packet_timestamp_msb*1e6 + previous_packet_timestamp_lsb;
assign real_timestamp = nsPrecision ?
timestamp_msb*1e9 + timestamp_lsb
: timestamp_msb*1e6 + timestamp_lsb;
always @(posedge clk ) begin
if(eop) begin
previous_packet_timestamp_msb <= timestamp_msb;
previous_packet_timestamp_lsb <= timestamp_lsb;
end
end
always @(posedge clk ) begin
case(state_ifg)
2'b0 : begin
if(use_custom_ifg == "TRUE" && default_ifg==0) begin // If IFG==0, do not wait for the next frame
pause_ifg <= 1'b0;
state_ifg <= 1'b0;
end else begin
if(eop) begin
if(use_custom_ifg == "TRUE") begin
pause_ifg <= 1'b1;
state_ifg <= 2'b10;
cnt_ifg <= default_ifg;
end else begin // The header of the next packect has to be read. Wait one pulse.
pause_ifg <= 1'b1;
state_ifg <= 2'b01;
end
end
end
end
2'b01 : begin // Substract the timestamps from two consecutives packets and assign the new
// ifg. Notice that one clock cycle has been consumed.
if(nsPrecision) begin
if(`abs(real_timestamp - previous_packet_real_timestamp)/ns_per_cycle > 1) begin
cnt_ifg <= $ceil(`abs(real_timestamp - previous_packet_real_timestamp)/ns_per_cycle) - 1;
state_ifg <= 2'b10;
end else begin
state_ifg <= 2'b00;
pause_ifg <= 1'b0;
end
end else begin // Time in us.
if(`abs(real_timestamp - previous_packet_real_timestamp)/ns_per_cycle > 1) begin
cnt_ifg <= $ceil((`abs(real_timestamp - previous_packet_real_timestamp)*1e3)/ns_per_cycle) - 1;
state_ifg <= 2'b10;
end else begin
state_ifg <= 2'b00;
pause_ifg <= 1'b0;
end
end
end
2'b10 : begin
if(cnt_ifg == 1) begin
state_ifg <= 2'b00;
pause_ifg <= 1'b0;
end else begin
cnt_ifg <= cnt_ifg - 1;
end
end
default : begin
pause_ifg <= 1'b0;
state_ifg <= 1'b0;
end
endcase
end
always @(posedge clk) begin
eof = $feof(file);
if(eof != 0 && (play_in_loop && current_loop<n_loops)) begin
$rewind(file);
readGlobalHeader();
readPacketHeader();
pktcount <= pktcount + 1;
eof = $feof(file);
current_loop = current_loop+1;
end
if (eof != 0) begin
pcapfinished <= 1; // terminal loop here
if(ready) begin
eop <= 0;
valid <= 0;
data <= {AXIS_WIDTH{1'b0}};
end
end else if (ready && diskSz == 0) begin
readPacketHeader();
pktcount <= pktcount + 1;
valid <= 0;
eop <= 0;
end else if ( diskSz > 0) begin
// packet content is byte-aligned, no swapping required
if (~pause && ~pause_ifg && ready) begin
readPacket();
valid <= 1;
eop <= diskSz <= AXIS_WIDTH/8;
if(diskSz <= AXIS_WIDTH/8 && use_custom_ifg=="TRUE" && default_ifg==0) begin // If we do not need to wait an IFG, update the variables pktSz, diskSz
readPacketHeader();
pktcount <= pktcount + 1;
end else begin
diskSz <= (diskSz > AXIS_WIDTH/8-1) ? diskSz - AXIS_WIDTH/8 : 0;
end
end else begin
if(ready) begin
valid <= 0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2000 + 5; const int MOD = 1000000000 + 7; int n, k; int a[maxn], e[maxn], s[maxn], t[maxn]; inline void mm(int a[], int b[]) { for (int i = 0; i < n; i++) { t[i] = 0; for (int j = 0; j <= i; j++) t[i] = ((long long)a[j] * b[i - j] + t[i]) % MOD; } for (int i = 0; i < n; i++) a[i] = t[i]; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) { scanf( %d , a + i); e[i] = 1; } s[0] = 1; while (k) { if (k & 1) mm(s, e); mm(e, e); k >>= 1; } mm(a, s); for (int i = 0; i < n; i++) printf( %d , a[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[200001]; int b[600001]; int n, L; bool chk(int d) { if (d * 2 >= L) return true; int l = 0, r = 3 * n - 1; while (b[l] < a[0] - d) l++; while (b[r] > a[0] + d) r--; for (int i = 1; i < n; i++) { l++; r++; while (b[l] < a[i] - d) l++; if (b[r] > a[i] + d) r--; } return l <= r; } void Init() { scanf( %d%d , &n, &L); for (int i = 0; i < n; i++) scanf( %d , a + i); for (int i = 0; i < n; i++) scanf( %d , b + n + i); } void Solve() { for (int i = 0; i < n; i++) { b[i] = b[i + n] - L; b[i + 2 * n] = b[i + n] + L; } sort(a, a + n); sort(b, b + 3 * n); int left = 0, right = L / 2 + 1; while (left < right) { int m = (left + right) / 2; if (chk(m)) right = m; else left = m + 1; } printf( %d n , left); } int main() { Init(); Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void REV(T *a, int n) { reverse(a + 1, a + 1 + n); } template <class T> void SRT(T *a, int n) { sort(a + 1, a + 1 + n); } template <class T> int UNI(T *a, int n) { sort(a + 1, a + 1 + n); return unique(a + 1, a + 1 + n) - (a + 1); } template <class T> int POS(T *a, int n, T v) { return lower_bound(a + 1, a + 1 + n, v) - a; } template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(long long &x) { scanf( %lld , &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } void _W(const long long &x) { printf( %lld , x); } void _W(const double &x) { printf( %.12f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T, class U> void _W(const pair<T, U> &x) { _W(x.F); putchar( ); _W(x.S); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } template <typename T> void cmin(T &x, T y) { if (y < x) x = y; } template <typename T> void cmax(T &x, T y) { if (y > x) x = y; } long long sum; int n; int a[200005]; int cnt[64]; void purin_solve() { R(sum, n); memset((cnt), 0, sizeof((cnt))); long long cursum = 0; for (int i = (1); i <= (n); ++i) { long long x; R(x); cursum += x; int c = -1; while (x) { ++c; x >>= 1; } ++cnt[c]; } if (cursum < sum) do { puts( -1 ); return; } while (false); ; long long SUM = 0; int ans = 0; for (int i = 0; i < 64; ++i) { if (SUM >= (1LL << i)) { SUM -= (1LL << i); ++cnt[i]; } if (sum >> i & 1) { int j; for (j = i; j < 64; ++j) { if (cnt[j]) break; }; if (j == 64) do { puts( -1 ); return; } while (false); while (j > i) { --cnt[j]; --j; cnt[j] += 2; ++ans; } assert(cnt[i]); --cnt[i]; } while (cnt[i]) { SUM += (1LL << i); --cnt[i]; } } W(ans); } int main() { cout << fixed << setprecision(12); cerr << fixed << setprecision(12); int t = 1; scanf( %d , &t); while (t--) purin_solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 7; int n; int a[N], b[N], x[N], y[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &a[i], &b[i]); } for (int i = 1; i <= n; i++) { scanf( %d%d , &x[i], &y[i]); } sort(a + 1, a + 1 + n); sort(b + 1, b + 1 + n); sort(x + 1, x + 1 + n); sort(y + 1, y + 1 + n); cout << a[1] + x[n] << << b[1] + y[n] << endl; return 0; } |
// test_usb_ft232.v
`timescale 1 ns / 1 ps
module test_usb_ft232;
reg clk = 0;
reg reset = 1;
// FT232 interface
wire wr_n;
wire rd_n;
wire oe_n;
wire [7:0]data;
reg txe_n = 1;
reg rxf_n = 1;
wire siwu_n;
// tx fifo interface
wire tx_read;
reg [15:0]tx_data = 16'hxx01;
reg [1:0]tx_mask = 2'b01;
reg tx_ready = 0;
// rx fifo interface
wire rx_write;
wire [15:0]rx_data;
wire [1:0]rx_mask;
reg rx_ready = 0;
// clk
always #8 clk = !clk;
initial
begin
#10 reset = 0;
@(posedge clk);
@(posedge clk);
txe_n = 0;
tx_ready = 1;
end
// === ft232 ============================================
reg [3:0]tx_ftcnt = 0;
always @(posedge clk)
begin
txe_n <= tx_ftcnt < 3;
tx_ftcnt <= tx_ftcnt + 1;
end
reg [7:0]rx_ftdata = 8'h80;
always @(posedge clk)
begin
if (!rd_n) rx_ftdata = rx_ftdata + 1;
end
initial
begin
@(posedge clk);
@(posedge clk);
@(posedge clk);
rxf_n = 0;
rx_ready = 1;
end
assign data = oe_n ? 8'hzz : rx_ftdata;
// === rxfifo ===========================================
reg [7:0]datagen = 2;
reg [3:0]txmode = 0;
always @(posedge clk)
begin
if (tx_read)
begin
txmode <= {$random} % 16;
if (txmode < 5)
begin // empty
tx_data <= 16'hxxxx;
tx_mask <= 2'bxx;
tx_ready <= 0;
@(posedge clk);
@(posedge clk);
tx_ready <= 1;
tx_mask <= 2'b11;
tx_data <= {datagen+1, datagen};
datagen <= datagen + 2;
end
else if (txmode < 6)
begin // send
tx_mask <= 2'b00;
tx_data <= 16'hxxxx;
end
else if (txmode < 13)
begin // 2 bytes
tx_mask <= 2'b11;
tx_data <= {datagen+1, datagen};
datagen <= datagen + 2;
end
else
begin // 1 byte
tx_mask <= 2'b01;
tx_data <= {8'hxx, datagen};
datagen <= datagen + 1;
end
end
end
// tx error check
event tx_error;
reg [7:0]datavalue = 1;
always @(posedge clk)
begin
if (!wr_n)
begin
if (data == datavalue); else -> tx_error;
datavalue = datavalue + 1;
end
end
usb_ft232 DUT
(
.clk(clk),
.reset(reset),
.wr_n(wr_n),
.rd_n(rd_n),
.oe_n(oe_n),
.data(data),
.txe_n(txe_n),
.rxf_n(rxf_n),
.siwu_n(siwu_n),
.tx_read(tx_read),
.tx_data(tx_data),
.tx_mask(tx_mask),
.tx_ready(tx_ready),
.rx_write(rx_write),
.rx_data(rx_data),
.rx_mask(rx_mask),
.rx_ready(rx_ready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[105]; struct Fenwick_Tree { int sz, c[305]; void init(int n) { sz = n; for (int i = 1; i <= n; i++) c[i] = 0; } int lowbit(int x) { return x & (-x); } void update(int p, int v) { for (int i = p; i <= sz; i += lowbit(i)) c[i] = max(c[i], v); } int query(int p) { int res = 0; for (int i = p; i > 0; i -= lowbit(i)) res = max(res, c[i]); return res; } } BIT; int b[200005], cnt[305]; int pre[305], suf[305]; int main() { int n, T; scanf( %d%d , &n, &T); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); if (T <= 2000) { for (int i = 0; i < T; i++) for (int j = 1; j <= n; j++) b[i * n + j] = a[j]; int ans = 0; BIT.init(300); for (int i = 1; i <= n * T; i++) { int len = BIT.query(b[i]) + 1; BIT.update(b[i], len); ans = max(ans, len); } printf( %d n , ans); } else { for (int i = 1; i <= n; i++) cnt[a[i]]++; for (int i = 0; i < 2000; i++) for (int j = 1; j <= n; j++) b[i * n + j] = a[j]; BIT.init(300); for (int i = 1; i <= 1000 * n; i++) { pre[b[i]] = BIT.query(b[i]) + 1; BIT.update(b[i], pre[b[i]]); } BIT.init(300); for (int i = 2000 * n; i > 1000 * n; i--) { suf[b[i]] = BIT.query(301 - b[i]) + 1; BIT.update(301 - b[i], suf[b[i]]); } int ans = 0; for (int i = 1; i <= 300; i++) ans = max(ans, pre[i] + suf[i] + cnt[i] * (T - 2000)); printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int tt; cin >> tt; while (tt--) { int n, l; cin >> n >> l; vector<double> flags(n); for (auto& i : flags) cin >> i; double a_s = 0, b_s = l; double a_v = 1, b_v = 1; int a_i = 0, b_i = n - 1; double t = 0; for (;;) { double a_d = a_i < n ? flags[a_i] - a_s : 1e300, b_d = b_i >= 0 ? b_s - flags[b_i] : 1e300; double a_t = a_d / a_v, b_t = b_d / b_v; double sep = b_s - a_s; double sep_t = sep / (a_v + b_v); double mn = min({a_t, b_t, sep_t}); t += mn; a_s += a_v * mn; b_s -= b_v * mn; if (a_t == mn) { a_v++; a_i++; } else if (b_t == mn) { b_v++; b_i--; } else break; } cout << fixed << t << endl; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int INF = 1e7; const long long Mod = 1e9 + 7; long long powmod(long long a, long long b) { long long res = 1; a %= Mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % Mod; a = a * a % Mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } struct haha { int pos, dat; } arr[maxn]; char st[maxn]; int sheng[maxn], xiao[2], k, res, arrnum; int main() { scanf( %s , st); k = strlen(st); res = 0; for (int i = 0; i <= k - 1; i++) { if (st[i] == 1 ) { sheng[i] = 1 + max(xiao[1], xiao[0]); xiao[1] = sheng[i]; } else { sheng[i] = ++xiao[0]; res++; } } int qian[3] = {0}; arrnum = 0; for (int i = 0; i <= k - 1; i++) { if (st[i] == 1 ) { qian[2] = sheng[i]; } else { while (arrnum > 0 && arr[arrnum].dat >= qian[2] - sheng[i]) arrnum--; arrnum++; arr[arrnum].pos = i; arr[arrnum].dat = qian[2] - sheng[i]; } } arrnum++; arr[arrnum].pos = k; arr[arrnum].dat = k * 2; int arrnow = 1; res = 0; for (int i = 0; i <= k - 1; i++) if (st[i] == 1 ) { if (qian[0] >= qian[1]) { qian[2] = sheng[i]; bool boo = true; while (arrnow <= arrnum && arr[arrnow].pos < i) arrnow++; if (arrnow > arrnum) boo = false; else { if (res >= arr[arrnow].dat) boo = false; } if (boo) { st[i] = 0 ; res++; qian[0] = sheng[i]; } } qian[1] = sheng[i]; } else { qian[0] = res + sheng[i]; } printf( %s , st); return 0; } |
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module rx_buffer_fsm (
input posedge_clk,
input rx_resetn,
input last_is_data,
input last_is_timec,
input last_is_control,
output reg rx_got_null,
output reg rx_got_nchar,
output reg rx_got_time_code
);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
else
begin
if(last_is_data == 1'b1 )
begin
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b1;
rx_got_time_code <= 1'b0;
end
else if(last_is_timec == 1'b1)
begin
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b1;
end
else if(last_is_control == 1'b1)
begin
rx_got_null <= 1'b1;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
else
begin
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int max_n = 1e5 + 10; const long long inf = 10000000000000000; vector<int> adj[max_n]; vector<long long> cst[max_n]; vector<int> arr[max_n]; vector<long long> closest[max_n]; void cmp_closest(int i) { int s = arr[i].size(); if (s > 0) { closest[i].reserve(s); closest[i][s - 1] = arr[i][s - 1] + 1; for (int j = s - 2; j >= 0; --j) { if (arr[i][j] + 1 != arr[i][j + 1]) { closest[i][j] = arr[i][j] + 1; } else { closest[i][j] = closest[i][j + 1]; } } } } int n, m; void add_edge(int a, int b, int c) { adj[a].push_back(b); cst[a].push_back(c); adj[b].push_back(a); cst[b].push_back(c); } void read() { ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < m; ++i) { int a, b, c; cin >> a >> b >> c; --a; --b; add_edge(a, b, c); } for (int i = 0; i < n; ++i) { int k; cin >> k; for (int j = 0; j < k; ++j) { long long t; cin >> t; arr[i].push_back(t); } cmp_closest(i); } } long long dist[max_n]; struct cmpl { inline bool operator()(int a, int b) const { return (dist[a] < dist[b] || (dist[a] == dist[b] && a < b)); } }; int cost(int u, size_t i) { vector<int>::iterator it = lower_bound(arr[u].begin(), arr[u].end(), dist[u]); if (it != arr[u].end() && *it == dist[u]) { return cst[u][i] + (closest[u][it - arr[u].begin()]) - dist[u]; } else { return cst[u][i]; } } set<int, cmpl> pq; int main() { read(); for (int i = 1; i < n; ++i) { dist[i] = inf; } pq.insert(0); int res = -1; while (!pq.empty()) { int curr = *pq.begin(); pq.erase(pq.begin()); if (curr == n - 1) { res = dist[curr]; break; } else { for (size_t i = 0; i < adj[curr].size(); ++i) { int v = adj[curr][i]; int c = cost(curr, i); if (dist[curr] + c < dist[v]) { pq.erase(v); dist[v] = dist[curr] + c; pq.insert(v); } } } } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int s; cin >> s; int *a = new int[s]; for (int i = 0; i < s; i++) cin >> a[i]; for (int i = s - 2; i < s; i--) { if (a[i] != a[i + 1]) { cout << i + 1 << endl; break; } } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 06:35:31 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.3 2006/06/26 07:42:19 wig Exp $
// $Date: 2006/06/26 07:42:19 $
// $Log: inst_t_e.v,v $
// Revision 1.3 2006/06/26 07:42:19 wig
// Updated io, generic and mde_tests testcases
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_4_V
`define SKY130_FD_SC_LP__O2111A_4_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_4 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_4_V
|
#include <bits/stdc++.h> using namespace std; int n, i, j, m, k; int a[2000000]; bool bo[2000000]; int l, r, ans, tot; int main() { scanf( %d%d%d , &n, &m, &k); for (i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + 1 + n); int now = 0; bo[0] = true; for (i = 1; i <= n; i++) { tot++; while (a[i] - a[now] >= m && now <= n) tot -= (!bo[now]), now++; if (tot >= k) ans++, tot--, bo[i] = true; } printf( %d , ans); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// bug1001
interface intf
#(parameter PARAM = 0)
();
logic val;
endinterface
module t();
generate
if (1) begin
intf #(.PARAM(2)) my_intf ();
assign my_intf.val = '1;
end else begin
intf #(.PARAM(3)) my_intf ();
assign my_intf.val = '0;
end
endgenerate
generate
begin
if (1) begin
intf #(.PARAM(2)) my_intf ();
assign my_intf.val = '1;
end else begin
intf #(.PARAM(3)) my_intf ();
assign my_intf.val = '0;
end
end
endgenerate
generate
begin
begin
if (1) begin
intf #(.PARAM(2)) my_intf ();
assign my_intf.val = '1;
end else begin
intf #(.PARAM(3)) my_intf ();
assign my_intf.val = '0;
end
end
end
endgenerate
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module bidir_switch_block(
input [wire_width*wire_width*12-1:0] select,
inout [wire_width-1:0] left,
inout [wire_width-1:0] right,
inout [wire_width-1:0] bottom
);
parameter wire_width = 3;
/*wire tb[2:0][2:0];
wire lr[2:0][1:0];
// First row
bidir_switch bs1(
.select(select[11:0]),
.left(left[0]),
.right(lr[0][0]),
.top(tb[0][0]),
.bottom(bottom[0])
);
bidir_switch bs2(
.select(select[23:12]),
.left(lr[0][0]),
.right(lr[0][1]),
.top(tb[0][1]),
.bottom(bottom[1])
);
bidir_switch bs3(
.select(select[35:24]),
.left(lr[0][1]),
.right(right[0]),
.top(tb[0][2]),
.bottom(bottom[2])
);
// Second row
bidir_switch bs4(
.select(select[47:36]),
.left(left[1]),
.right(lr[1][0]),
.top(tb[1][0]),
.bottom(tb[0][0])
);
bidir_switch bs5(
.select(select[59:48]),
.left(lr[1][0]),
.right(lr[1][1]),
.top(tb[1][1]),
.bottom(tb[0][1])
);
bidir_switch bs6(
.select(select[71:60]),
.left(lr[1][1]),
.right(right[1]),
.top(tb[1][2]),
.bottom(tb[0][2])
);
// Third row
bidir_switch bs7(
.select(select[83:72]),
.left(left[2]),
.right(lr[2][0]),
.top(tb[2][0]),
.bottom(tb[1][0])
);
bidir_switch bs8(
.select(select[95:84]),
.left(lr[2][0]),
.right(lr[2][1]),
.top(tb[2][1]),
.bottom(tb[1][0])
);
bidir_switch bs9(
.select(select[107:96]),
.left(lr[2][1]),
.right(right[2]),
.top(tb[2][2]),
.bottom(tb[1][2])
);*/
wire [wire_width-1:0] top;
genvar x, y;
wire lr[wire_width:0][wire_width:0];
wire tb[wire_width:0][wire_width:0];
generate
for(y = 0; y < wire_width; y = y + 1) begin
for (x = 0; x < wire_width; x = x + 1) begin
localparam s_base = (x*12)+(y*wire_width*12);
if (x == 0) begin
if (y == 0) begin // Bottom left
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( left[y] ),
.right( lr[y][x+1] ),
.top( tb[y+1][x] ),
.bottom( bottom[x] )
);
end
else if (y == wire_width-1) begin // Top left
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( left[y] ),
.right( lr[y][x+1] ),
.top( top[x] ),
.bottom( tb[y][x] )
);
end
else begin // Some left
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( left[y] ),
.right( lr[y][x+1] ),
.top( tb[y+1][x] ),
.bottom( tb[y][x] )
);
end
end
else if (x == wire_width-1) begin
if (y == 0) begin // Bottom right
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( lr[y][x] ),
.right( right[y] ),
.top( tb[y+1][x] ),
.bottom( bottom[x] )
);
end
else if (y == wire_width-1) begin // Top right
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( lr[y][x] ),
.right( right[y] ),
.top( top[x] ),
.bottom( tb[y][x] )
);
end
else begin // Some right
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( lr[y][x] ),
.right( right[y] ),
.top( tb[y+1][x] ),
.bottom( tb[y][x] )
);
end
end else begin
if (y == 0) begin // Bottom edge
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( lr[y][x] ),
.right( lr[y][x+1] ),
.top( tb[y+1][x] ),
.bottom( bottom[x] )
);
end
else if (y == wire_width-1) begin // Top edge
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( lr[y][x] ),
.right( lr[y][x+1] ),
.top( top[x] ),
.bottom( tb[y][x] )
);
end
else begin // Middle somewhere
bidir_switch bs(
.select(select[s_base+11:s_base]),
.left( lr[y][x] ),
.right( lr[y][x+1] ),
.top( tb[y+1][x] ),
.bottom( tb[y][x] )
);
end
end
/*bidir_switch bs(
.left( x==0 ? left[y] : lr[y][x] ),
.right( x == wire_width-1 ? right[y] : lr[y][x+1] ),
.top( y == wire_width-1 ? top[x] : tb[y+1][x] ),
.bottom( y == 0 ? bottom[x] : tb[y][x] )
);*/
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_PP_SYMBOL_V
`define SKY130_FD_SC_MS__TAPMET1_PP_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapmet1 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void chmax(int& a, int b) { a = max(a, b); } void chmin(int& a, int b) { a = min(a, b); } int nth_bit(int64_t num, int n) { return (num >> n) & 1; } int main() { string S; int X; cin >> S >> X; int N = S.size(); vector<int> A(N); for (int i = 0; i < N; i++) A[i] = S[i] - 0 ; vector<int> ds; for (int i = 1; i < X; i++) if (X % i == 0) ds.push_back(i); if (X == 1) { cout << count(A.begin(), A.end(), 1) << endl; return 0; } int B = 1 << (X + 1); vector<int> valid; for (int b = 0; b < B; b++) { bool ok = true; for (int i = 0; i < X; i++) if (nth_bit(b, i) && nth_bit(b, i + 1)) ok = false; if (ok) valid.push_back(b); } vector<bool> ok(B); for (int b = 0; b < B; b++) { if (nth_bit(b, X) == 0) ok[b] = true; for (int d : ds) for (int i = 0; i < X; i++) if (nth_bit(b, i) && nth_bit(b, i + d)) ok[b] = true; } vector<int> dp(B), dp2(B); auto solve = [&](vector<int>& V) -> int { int N = V.size(); for (int b : valid) dp[b] = 1e9; dp[1] = 0; for (int i = 0; i < N; i++) { for (int b : valid) dp2[b] = dp[b] + 1; for (int b : valid) { int b2 = ((b << V[i]) | 1) & (B - 1); if (ok[b2]) chmin(dp2[b2], dp[b]); } for (int b : valid) dp[b] = dp2[b]; } int ans = 1e9; for (int b : valid) chmin(ans, dp[b]); return ans; }; int ans = 0; vector<int> V; for (int i = 0; i < N; i++) { if (A[i] == 1) { if (V.size()) ans += solve(V); V.clear(); } else { V.push_back(A[i]); } } if (V.size()) ans += solve(V); cout << ans << endl; return 0; } |
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for xfcp_interface_udp
*/
module test_xfcp_interface_udp;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_eth_axis_tdata = 0;
reg s_eth_axis_tvalid = 0;
reg s_eth_axis_tlast = 0;
reg s_eth_axis_tuser = 0;
reg m_eth_axis_tready = 0;
reg [7:0] down_xfcp_in_tdata = 0;
reg down_xfcp_in_tvalid = 0;
reg down_xfcp_in_tlast = 0;
reg down_xfcp_in_tuser = 0;
reg down_xfcp_out_tready = 0;
reg [47:0] local_mac = 0;
reg [31:0] local_ip = 0;
reg [15:0] local_port = 0;
reg [31:0] gateway_ip = 0;
reg [31:0] subnet_mask = 0;
// Outputs
wire s_eth_axis_tready;
wire [7:0] m_eth_axis_tdata;
wire m_eth_axis_tvalid;
wire m_eth_axis_tlast;
wire m_eth_axis_tuser;
wire down_xfcp_in_tready;
wire [7:0] down_xfcp_out_tdata;
wire down_xfcp_out_tvalid;
wire down_xfcp_out_tlast;
wire down_xfcp_out_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_axis_tdata,
s_eth_axis_tvalid,
s_eth_axis_tlast,
s_eth_axis_tuser,
m_eth_axis_tready,
down_xfcp_in_tdata,
down_xfcp_in_tvalid,
down_xfcp_in_tlast,
down_xfcp_in_tuser,
down_xfcp_out_tready,
local_mac,
local_ip,
local_port,
gateway_ip,
subnet_mask
);
$to_myhdl(
s_eth_axis_tready,
m_eth_axis_tdata,
m_eth_axis_tvalid,
m_eth_axis_tlast,
m_eth_axis_tuser,
down_xfcp_in_tready,
down_xfcp_out_tdata,
down_xfcp_out_tvalid,
down_xfcp_out_tlast,
down_xfcp_out_tuser
);
// dump file
$dumpfile("test_xfcp_interface_udp.lxt");
$dumpvars(0, test_xfcp_interface_udp);
end
xfcp_interface_udp
UUT (
.clk(clk),
.rst(rst),
.s_eth_axis_tdata(s_eth_axis_tdata),
.s_eth_axis_tvalid(s_eth_axis_tvalid),
.s_eth_axis_tready(s_eth_axis_tready),
.s_eth_axis_tlast(s_eth_axis_tlast),
.s_eth_axis_tuser(s_eth_axis_tuser),
.m_eth_axis_tdata(m_eth_axis_tdata),
.m_eth_axis_tvalid(m_eth_axis_tvalid),
.m_eth_axis_tready(m_eth_axis_tready),
.m_eth_axis_tlast(m_eth_axis_tlast),
.m_eth_axis_tuser(m_eth_axis_tuser),
.down_xfcp_in_tdata(down_xfcp_in_tdata),
.down_xfcp_in_tvalid(down_xfcp_in_tvalid),
.down_xfcp_in_tready(down_xfcp_in_tready),
.down_xfcp_in_tlast(down_xfcp_in_tlast),
.down_xfcp_in_tuser(down_xfcp_in_tuser),
.down_xfcp_out_tdata(down_xfcp_out_tdata),
.down_xfcp_out_tvalid(down_xfcp_out_tvalid),
.down_xfcp_out_tready(down_xfcp_out_tready),
.down_xfcp_out_tlast(down_xfcp_out_tlast),
.down_xfcp_out_tuser(down_xfcp_out_tuser),
.local_mac(local_mac),
.local_ip(local_ip),
.local_port(local_port),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : MC write enable generation
// File : de3d_tc_mc_we.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is used to generate the write enable for each RAM.
// One of these is instatiated for each RAM and should be placed next
// to that RAM.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
/************************************************************************/
/************************************************************************/
module de3d_tc_mc_we
(
input mclock, // Memory controller clock */
input rstn,
input tex_push_en, // Memory controller push enable. */
input ram_sel, // Which ram to write first. */
output reg ram_wen_lo, // write enable for RAM. */
output reg ram_wen_hi // write enable for RAM. */
);
reg cs;
always @(posedge mclock, negedge rstn) begin
if(!rstn) cs <= 1'b0;
else begin
case(cs)
1'b0: if(tex_push_en) cs <= 1'b1;
else cs = 1'b0;
1'b1: if(tex_push_en) cs <= 1'b0;
else cs = 1'b1;
endcase
end
end
always @* ram_wen_lo = tex_push_en & ((~cs & ~ram_sel) | ( cs & ram_sel));
always @* ram_wen_hi = tex_push_en & (( cs & ~ram_sel) | (~cs & ram_sel));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void amin(T &a, T b) { if (a > b) a = b; } template <class T> inline void amax(T &a, T b) { if (a < b) a = b; } int gcd(int x, int y) { while (y) { x %= y; swap(x, y); } return x; } int GCD[111][111]; int N, B[111]; pair<int, int> A[111]; int best; vector<int> v, best_v; int sums[111]; void update() { int sum = 0; sum = sums[N - v.size()]; for (int i = 0; i < int(v.size()); i++) sum += abs(A[i + N - v.size()].first - v[i]); if (best > sum) { best = sum; best_v = v; } } void rec(int x) { update(); if ((int)v.size() == N || x == 59) { return; } bool ok = true; for (int i = 0; i < int(v.size()); i++) if (GCD[v[i]][x] != 1) { ok = false; break; } if (ok) { v.push_back(x); rec(x + 1); v.pop_back(); } rec(x + 1); } int main() { for (int i = 0; i < int(111); i++) for (int j = 0; j < int(111); j++) GCD[i][j] = gcd(i, j); scanf( %d , &N); for (int i = 0; i < int(N); i++) { int x; scanf( %d , &x); A[i] = make_pair(x, i); } sort(A, A + N); for (int i = 0; i < int(N); i++) sums[i + 1] = sums[i] + A[i].first; best = 1 << 29; rec(2); for (int i = 0; i < int(N); i++) B[i] = 1; for (int i = 0; i < int(best_v.size()); i++) B[A[i + N - best_v.size()].second] = best_v[i]; for (int i = 0; i < int(N); i++) printf( %d%c , B[i], i + 1 == N ? n : ); return 0; } |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ()
//Last Modified: Feb 25 2014
//Description: Layer Controller (LC) Power Gate Header (Active High)
// Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module lc_header
(
//**************************************
//Power Domain
//Input - Always On
//Output - Layer Controller Domain
//**************************************
//Signals
//Input
SLEEP
//Output
);
input SLEEP; //Active High
always @(SLEEP) begin
if (SLEEP) begin
$write("%c[1;34m",27);
$display("***********************************************");
$display("*********LAYER CONTROLLER IS POWER GATED*******");
$display("*********AT TIME:", $time);
$display("***********************************************");
$write("%c[0m",27);
end
else begin
$write("%c[1;34m",27);
$display("***********************************************");
$display("********LAYER CONTROLLER IS POWER UNGATED******");
$display("*********AT TIME:", $time);
$display("***********************************************");
$write("%c[0m",27);
end
end // always @ (SLEEP)
endmodule // lc_header
|
//////////////////////////////////////////////////////////////////////////////
/// Copyright (c) 2014, Ajit Mathew <>
/// All rights reserved.
///
// Redistribution and use in source and binary forms, with or without modification,
/// are permitted provided that the following conditions are met:
///
/// * Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// * Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation and/or
/// other materials provided with the distribution.
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
/// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
/// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
/// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
/// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
/// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
///
///
/// * http://opensource.org/licenses/MIT
/// * http://copyfree.org/licenses/mit/license.txt
///
//////////////////////////////////////////////////////////////////////////////
module uart_rx
#(
parameter DBIT = 8, // No of data bits
SB_tck = 16 // No of tcks for stop bits
)
(
input wire clk, reset,
input wire rx, s_tck,
output reg rx_done_tck,
output wire [7:0] dout
);
localparam [1:0] init_state = 2'b00,start = 2'b01,data = 2'b10,stop = 2'b11;
reg [1:0] state, state_next;
reg [3:0] s, s_next;
reg [2:0] n, n_next;
reg [7:0] b, b_next;
always @(posedge clk)
if (reset)
begin
state <= init_state;
s <= 0;
n <= 0;
b <= 0;
end
else
begin
state <= state_next;
s <= s_next;
n <= n_next;
b <= b_next;
end
always @*
begin
s_next = s;
n_next = n;
b_next = b;
state_next = state;
rx_done_tck = 1'b0;
if(state==init_state)
begin
if (~rx)
begin
s_next = 0;
state_next = start;
end
end
else if(state==start)
begin
if (s_tck)
if (s==7)
begin
state_next = data;
s_next = 0;
n_next = 0;
end
else
s_next = s + 1;
end
else if(state==data)
begin
if (s_tck)
if (s==15)
begin
s_next = 0;
b_next = {rx, b[7:1]};
if (n==(DBIT-1))
state_next = stop ;
else
n_next = n + 1;
end
else
s_next = s + 1;
end
else if(state==stop)
begin
if (s_tck)
if (s==(SB_tck-1))
begin
state_next = init_state;
rx_done_tck =1'b1;
end
else
s_next = s + 1;
end
end
assign dout = b;
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 10060 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w5,
w40,
w45,
w2560,
w2515,
w10060;
assign w1 = i_data0;
assign w10060 = w2515 << 2;
assign w2515 = w2560 - w45;
assign w2560 = w5 << 9;
assign w4 = w1 << 2;
assign w40 = w5 << 3;
assign w45 = w5 + w40;
assign w5 = w1 + w4;
assign o_data0 = w10060;
//multiplier_block area estimate = 5119.32965016029;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int S = 550; int n, q, a[N]; struct Block { int lid, rid; deque<int> que; int mp[N]; Block() {} void init() { lid = rid = 0; que.clear(); memset(mp, 0, sizeof mp); } void addf(int x) { que.push_front(x); mp[x]++; } void addb(int x) { que.push_back(x); mp[x]++; } void delf() { if (que.empty()) return; int x = que.front(); que.pop_front(); mp[x]--; } void delb() { if (que.empty()) return; int x = que.back(); que.pop_back(); mp[x]--; } } all[S]; int tot; void init() { for (int i = 0; i < S; ++i) all[i].init(); int id = 1; tot = 0; for (int i = 0; id <= n; ++i) { tot++; all[i].lid = all[i].rid = id; for (int j = 1; j <= S && id <= n; ++j) { all[i].addb(a[id]); all[i].rid++; id++; } } for (int i = 0; i < tot; ++i) all[i].rid--; } int st[N], top; void mov(int l, int r) { int sx = 0, tx = 0; for (int i = 0; i < tot; ++i) { if (all[i].lid <= l && l <= all[i].rid) { sx = i; } if (all[i].lid <= r && r <= all[i].rid) { tx = i; } } for (int i = sx + 1; i <= tx; ++i) { all[i].addf(all[i - 1].que.back()); all[i - 1].delb(); } int val = 0; top = 0; for (int i = all[tx].rid; i > r; --i) { st[top++] = all[tx].que.back(); all[tx].delb(); } val = all[tx].que.back(); all[tx].delb(); while (top > 0) all[tx].addb(st[--top]); for (int i = all[sx].lid; i < l; ++i) { st[top++] = all[sx].que.front(); all[sx].delf(); } all[sx].addf(val); while (top > 0) all[sx].addf(st[--top]); } int cal(int ip, int l, int r, int k) { int res = 0; top = 0; for (int i = 1; i <= l - 1; ++i) { st[top++] = all[ip].que.front(); all[ip].delf(); } int alx = all[ip].rid - all[ip].lid + 1; for (int i = 1; i <= alx - r; ++i) { st[top++] = all[ip].que.back(); all[ip].delb(); } res = all[ip].mp[k]; for (int i = 1; i <= alx - r; ++i) { all[ip].addb(st[--top]); } for (int i = 1; i <= l - 1; ++i) { all[ip].addf(st[--top]); } return res; } int qry(int l, int r, int k) { int res = 0; for (int i = 0; i < tot; ++i) { if (all[i].lid <= l && r <= all[i].rid) return cal(i, l - all[i].lid + 1, r - all[i].lid + 1, k); if (l <= all[i].lid && all[i].rid <= r) res += all[i].mp[k]; if (all[i].lid < l && l <= all[i].rid) { res += cal(i, l - all[i].lid + 1, all[i].rid - all[i].lid + 1, k); } if (all[i].lid <= r && all[i].rid > r) { res += cal(i, 1, r - all[i].lid + 1, k); } } return res; } int scan() { int res = 0; char ch; while ((ch = getchar()) && (ch != && ch != n )) res = res * 10 + ch - 0 ; return res; } int Run() { n = scan(); for (int i = 1; i <= n; ++i) a[i] = scan(); init(); int lans = 0; q = scan(); while (q--) { int op, l, r; op = scan(), l = scan(), r = scan(); l = (l + lans - 1) % n + 1; r = (r + lans - 1) % n + 1; if (l > r) swap(l, r); if (op == 1) { mov(l, r); } else { int k; k = scan(); k = (k + lans - 1) % n + 1; lans = qry(l, r, k); printf( %d n , lans); } } return 0; } int main() { return Run(); } |
#include <bits/stdc++.h> using namespace std; int up[200005]; void init() { memset(up, -1, sizeof(up)); } int Find(int x) { if (up[x] < 0) return x; int root = Find(up[x]); up[x] = root; return root; } void Union(int x, int y) { x = Find(x); y = Find(y); if (x == y) return; if (up[x] < up[y]) { up[x] += up[y]; up[y] = x; } else { up[y] += up[x]; up[x] = y; } } int n; int a[200005]; vector<int> can; set<int> aree; signed main() { init(); int x; scanf( %d , &n); int keep = -1; for (int i = 1; i <= n; i++) { scanf( %d , &x); if (Find(x) != Find(i)) { Union(x, i); a[i] = x; } else { if (x == i && keep == -1) { keep = 0; a[i] = x; } else { a[i] = -1; can.push_back(i); } } } if (keep == -1) { a[*(can.end() - 1)] = *(can.end() - 1); can.pop_back(); } for (int i = 1; i <= n; i++) { aree.insert(Find(i)); } for (auto i : can) { for (set<int>::iterator k = aree.begin(); k != aree.end(); k++) { int j = *k; int u, v; u = Find(j); v = Find(i); if (Find(j) != Find(i)) { a[i] = j; Union(i, j); aree.erase(v); aree.erase(u); aree.insert(Find(j)); goto lol; } } lol:; } cout << can.size() - keep << n ; for (int i = 1; i <= n; i++) { cout << a[i] << ; } } |
#include <bits/stdc++.h> using namespace std; int n; long long a[5005]; void input() { scanf( %d , &n); for (int i = 0; i < n; i++) { int x; scanf( %d , &x); a[i + 1] = a[i] + x; } } void solve() { long long outx, outy, outz, ans; ans = outx = outy = outz = 0; for (int i = 0; i <= n; i++) { long long z = a[i], lft = i; for (int j = i; j <= n; j++) { if (a[j] < z) { lft = j, z = a[j]; } if (a[i] - a[lft] + a[j] > ans) { ans = a[i] - a[lft] + a[j]; outx = i, outz = j, outy = lft; } } } printf( %lld %lld %lld , outx, outy, outz); } int main() { input(); solve(); return 0; } |
#include <bits/stdc++.h> unsigned long long c; int n, i, j, k, ks, ke, pd, pp, pa; char s[1000100]; bool f, ff, fff; int main() { scanf( %s , s); n = strlen(s); for (i = 0; i < n; i++) { if (s[i] >= a && s[i] <= z ) { k = 0, f = 1, ff = 0, fff = 0, ks = 1, ke = 0, pa = 0, pd = 0, pp = 0; for (j = i + 1; f && j < n; j++) { if (!k) { if (s[j] == @ ) ++k, pa = j; else if (!((s[j] >= a && s[j] <= z ) || (s[j] >= 0 && s[j] <= 9 ) || s[j] == _ )) f = 0; else if (s[j] >= a && s[j] <= z ) ++ks; } else if (k == 1) { if (s[j] == . ) ++k, pd = j; else if ((s[j] >= a && s[j] <= z ) || (s[j] >= 0 && s[j] <= 9 )) ff = 1; else f = 0; } else { if (s[j] >= a && s[j] <= z ) fff = 1, ++ke, pp = j; else f = 0; } } if (ff && fff) c += (unsigned long long)ks * ke; if (pa) i = pa; else if (pd) i = pd; else if (pp) i = pp - 1; else i = j - 1; } } printf( %I64u n , c); return 0; } |
`default_nettype none
module reservation_free_entry_count(
input wire iINFO0,
input wire iINFO1,
input wire iINFO2,
input wire iINFO3,
input wire iINFO4,
input wire iINFO5,
input wire iINFO6,
input wire iINFO7,
input wire iINFO8,
input wire iINFO9,
input wire iINFO10,
input wire iINFO11,
input wire iINFO12,
input wire iINFO13,
input wire iINFO14,
input wire iINFO15,
output wire [3:0] oCOUNT
);
assign oCOUNT = func_rb_free_count16(
iINFO0, iINFO1, iINFO2, iINFO3,
iINFO4, iINFO5, iINFO6, iINFO7,
iINFO8, iINFO9, iINFO10, iINFO11,
iINFO12, iINFO13, iINFO14, iINFO15
);
function [3:0] func_rb_free_count16;
input func_rb0;
input func_rb1;
input func_rb2;
input func_rb3;
input func_rb4;
input func_rb5;
input func_rb6;
input func_rb7;
input func_rb8;
input func_rb9;
input func_rb10;
input func_rb11;
input func_rb12;
input func_rb13;
input func_rb14;
input func_rb15;
reg [3:0] func_rb_tmp_count;
begin
func_rb_tmp_count = 4'h0;
if(func_rb0)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb1)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb2)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb3)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb4)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb5)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb6)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb7)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb8)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb9)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb10)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb11)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb12)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb13)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb14)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
if(func_rb15)begin
func_rb_tmp_count = func_rb_tmp_count + 4'h1;
end
func_rb_free_count16 = func_rb_tmp_count;
end
endfunction
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; long long mpow(long long a, long long b) { if (b == 1) return a; if (b == 0) return 1; return mpow(a, b - 1); } int main() { long long n; cin >> n; cout << (n / 2520); } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int Mod = 1e9 + 7; const int Mod2 = 49157; const int p = 10; inline long long Read() { long long Ans = 0; char Ch = getchar(), Las = ; while (!isdigit(Ch)) { Las = Ch; Ch = getchar(); } while (isdigit(Ch)) { Ans = (Ans << 3) + (Ans << 1) + Ch - 0 ; Ch = getchar(); } if (Las == - ) Ans = -Ans; return Ans; } inline void Write(long long x) { if (x < 0) { x = -x; putchar( - ); } if (x >= 10) Write(x / 10); putchar(x % 10 + 0 ); } unsigned long long Hash[1000010], Hash2[1000010], idx[1000010], Pow[1000010], Pow2[1000010]; unsigned long long a, b, c; unsigned long long a2, b2, c2; int Left_a, Right_a, Left_b, Right_b, Left_c, Right_c, Len; bool Flag; string s; inline void Get_Hash() { Pow[0] = 1; Pow2[0] = 1; for (int i = 1; i <= 1000010 / 2; i++) { Pow[i] = Pow[i - 1] * p % Mod; Pow2[i] = Pow2[i - 1] * p % Mod2; } idx[0] = s[0] - 0 ; Hash[0] = idx[0]; Hash2[0] = idx[0]; for (int i = 1; i < Len; i++) { idx[i] = s[i] - 0 ; Hash[i] = (Hash[i - 1] * p + idx[i]) % Mod; Hash2[i] = (Hash2[i - 1] * p + idx[i]) % Mod2; } } inline unsigned long long Cmp_Hash(int Left, int Right) { if (Left == 0) return Hash[Right]; return (Hash[Right] + Mod - (Hash[Left - 1] * Pow[Right - Left + 1]) % Mod) % Mod; } inline unsigned long long Cmp_Hash2(int Left, int Right) { if (Left == 0) return Hash2[Right]; return (Hash2[Right] + Mod2 - (Hash2[Left - 1] * Pow2[Right - Left + 1]) % Mod2) % Mod2; } int main() { cin >> s; Len = s.size(); Get_Hash(); int j; for (int i = 1; i <= Len / 2; i++) { if (i > 1 and idx[0] == 0) break; a = Cmp_Hash(0, i - 1); a2 = Cmp_Hash2(0, i - 1); if (i < Len / 3 + 1) { j = (Len - i) / 2; if (!(idx[i] == 0 and j > 1) and !(Len - i - j > 1 and idx[i + j] == 0)) { b = Cmp_Hash(i, i + j - 1); b2 = Cmp_Hash2(i, i + j - 1); c = Cmp_Hash(i + j, Len - 1); c2 = Cmp_Hash2(i + j, Len - 1); if ((a + b) % Mod == c % Mod and (a2 + b2) % Mod2 == c2 % Mod2) { Flag = 1, Left_a = 0, Right_a = i - 1, Left_b = i; Right_b = i + j - 1, Left_c = i + j, Right_c = Len - 1; break; } } j = (Len - i - 1) / 2; if (!(idx[i] == 0 and j > 1) and !(Len - i - j > 1 and idx[i + j] == 0)) { b = Cmp_Hash(i, i + j - 1); b2 = Cmp_Hash2(i, i + j - 1); c = Cmp_Hash(i + j, Len - 1); c2 = Cmp_Hash2(i + j, Len - 1); if ((a + b) % Mod == c % Mod and (a2 + b2) % Mod2 == c2 % Mod2) { Flag = 1, Left_a = 0, Right_a = i - 1, Left_b = i; Right_b = i + j - 1, Left_c = i + j, Right_c = Len - 1; break; } } } if (i > (Len - 1) / 3 - 1) { j = Len - 2 * i; if (!(idx[i] == 0 and j > 1) and !(Len - i - j > 1 and idx[i + j] == 0)) { b = Cmp_Hash(i, i + j - 1); b2 = Cmp_Hash2(i, i + j - 1); c = Cmp_Hash(i + j, Len - 1); c2 = Cmp_Hash2(i + j, Len - 1); if ((a + b) % Mod == c % Mod and (a2 + b2) % Mod2 == c2 % Mod2) { Flag = 1, Left_a = 0, Right_a = i - 1, Left_b = i; Right_b = i + j - 1, Left_c = i + j, Right_c = Len - 1; break; } } j = Len - 2 * i - 1; if (!(idx[i] == 0 and j > 1) and !(Len - i - j > 1 and idx[i + j] == 0)) { b = Cmp_Hash(i, i + j - 1); b2 = Cmp_Hash2(i, i + j - 1); c = Cmp_Hash(i + j, Len - 1); c2 = Cmp_Hash2(i + j, Len - 1); if ((a + b) % Mod == c % Mod and (a2 + b2) % Mod2 == c2 % Mod2) { Flag = 1, Left_a = 0, Right_a = i - 1, Left_b = i; Right_b = i + j - 1, Left_c = i + j, Right_c = Len - 1; break; } } } if (Flag == 1) break; } if (Flag == 1) { for (int i = Left_a; i <= Right_a; i++) Write(idx[i]); putchar( + ); for (int i = Left_b; i <= Right_b; i++) Write(idx[i]); putchar( = ); for (int i = Left_c; i <= Right_c; i++) Write(idx[i]); puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; vector<long long> V; for (long long i = 1; i * i <= n; ++i) { if (!(n % i)) { V.push_back(i); V.push_back(n / i); } } sort(V.begin(), V.end()); for (long long i = V.size() - 1; i >= 0; --i) if (i == V.size() - 1 || V[i + 1] != V[i]) cout << n * (2 + V[i] * (n / V[i] - 1)) / 2 / V[i] << ; cout << endl; } |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Power Management ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PM according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// - add support for dynamic clock gating ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_pm.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_pm(
// RISC Internal Interface
clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// Power Management Interface
pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input pic_wakeup; // Wakeup from the PIC
input spr_write; // SPR Read/Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
//
// Power Management Interface
//
input pm_cpustall; // Stall the CPU
output [3:0] pm_clksd; // Clock Slowdown factor
output pm_dc_gate; // Gate DCache clock
output pm_ic_gate; // Gate ICache clock
output pm_dmmu_gate; // Gate DMMU clock
output pm_immu_gate; // Gate IMMU clock
output pm_tt_gate; // Gate Tick Timer clock
output pm_cpu_gate; // Gate main RISC/CPU clock
output pm_wakeup; // Activate (de-gate) all clocks
output pm_lvolt; // Lower operating voltage
`ifdef OR1200_PM_IMPLEMENTED
//
// Power Management Register bits
//
reg [3:0] sdf; // Slow-down factor
reg dme; // Doze Mode Enable
reg sme; // Sleep Mode Enable
reg dcge; // Dynamic Clock Gating Enable
reg pm_cpustall_reg;
//
// Internal wires
//
wire pmr_sel; // PMR select
//
// PMR address decoder (partial decoder)
//
`ifdef OR1200_PM_PARTIAL_DECODING
assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0;
`else
assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) &&
(spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0;
`endif
//
// Write to PMR and also PMR[DME]/PMR[SME] reset when
// pic_wakeup is asserted
//
always @(posedge clk or posedge rst)
if (rst)
{dcge, sme, dme, sdf} <= 7'b0;
else if (pmr_sel && spr_write) begin
sdf <= #1 spr_dat_i[`OR1200_PM_PMR_SDF];
dme <= #1 spr_dat_i[`OR1200_PM_PMR_DME];
sme <= #1 spr_dat_i[`OR1200_PM_PMR_SME];
dcge <= #1 spr_dat_i[`OR1200_PM_PMR_DCGE];
end
else if (pic_wakeup) begin
dme <= #1 1'b0;
sme <= #1 1'b0;
end
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf;
assign spr_dat_o[`OR1200_PM_PMR_DME] = dme;
assign spr_dat_o[`OR1200_PM_PMR_SME] = sme;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
//
// Generate pm_clksd
//
assign pm_clksd = sdf;
//
// Statically generate all clock gate outputs
// TODO: add dynamic clock gating feature
//
assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
assign pm_dc_gate = pm_cpu_gate;
assign pm_ic_gate = pm_cpu_gate;
assign pm_dmmu_gate = pm_cpu_gate;
assign pm_immu_gate = pm_cpu_gate;
assign pm_tt_gate = sme & ~pic_wakeup;
//
// Assert pm_wakeup when pic_wakeup is asserted
//
assign pm_wakeup = pic_wakeup;
//
// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
//
always @(posedge clk or posedge rst)
if (rst)
pm_cpustall_reg <= 1'b0;
else
pm_cpustall_reg <= pm_cpustall;
assign pm_lvolt = pm_cpu_gate | pm_cpustall_reg;
`else
//
// When PM is not implemented, drive all outputs as would when PM is disabled
//
assign pm_clksd = 4'b0;
assign pm_cpu_gate = 1'b0;
assign pm_dc_gate = 1'b0;
assign pm_ic_gate = 1'b0;
assign pm_dmmu_gate = 1'b0;
assign pm_immu_gate = 1'b0;
assign pm_tt_gate = 1'b0;
assign pm_wakeup = 1'b1;
assign pm_lvolt = 1'b0;
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0;
assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x; cin >> x; int k = x % 4; if (k == 1) { cout << 0 << A << endl; } else if (k == 0) { cout << 1 << A << endl; } else if (k == 2) { cout << 1 << B << endl; } else { cout << 2 << A << endl; } } |
`define TAGSIM_LISTEN 3'b001
`define TAGSIM_MOD 3'b010
`define READER_LISTEN 3'b011
`define READER_MOD 3'b100
`define FAKE_READER 3'b101
`define FAKE_TAG 3'b110
`define READER_START_COMM_FIRST_CHAR 8'hc
`define READER_END_COMM_1 16'h0000
`define READER_END_COMM_2 16'hc000
`define TAG_START_COMM_FIRST_CHAR 8'hf
`define TAG_END_COMM 8'h00
module relay_mode (
clk,
data_in,
data_in_available,
hi_simulate_mod_type,
mod_type,
data_out
);
input clk, data_in_available;
input [3:0] data_in;
input [2:0] hi_simulate_mod_type;
output [2:0] mod_type;
output data_out;
reg [2:0] mod_type = 3'b0;
wire [0:0] data_out;
reg [3:0] div_counter = 4'b0;
reg [19:0] receive_buffer = 20'b0;
reg [0:0] half_byte_counter = 1'b0;
assign data_out = receive_buffer[3];
always @(posedge clk)
begin
div_counter <= div_counter + 1;
if (div_counter[3:0] == 4'b1000 && (hi_simulate_mod_type == `FAKE_READER || hi_simulate_mod_type == `FAKE_TAG))
receive_buffer = {receive_buffer[18:0], 1'b0};
if (hi_simulate_mod_type == `FAKE_READER && mod_type == 3'b0)
mod_type = `READER_LISTEN;
else if (hi_simulate_mod_type == `FAKE_TAG && mod_type == 3'b0)
mod_type = `TAGSIM_LISTEN;
// Buffer decoded signals
if (data_in_available == 1'b1 && (hi_simulate_mod_type == `FAKE_READER || hi_simulate_mod_type == `FAKE_TAG)) begin
receive_buffer[3:0] = data_in;
half_byte_counter = half_byte_counter + 1;
if (hi_simulate_mod_type == `FAKE_READER) // Fake Reader
begin
if (receive_buffer[19:0] == {16'b0, `READER_START_COMM_FIRST_CHAR})
begin
mod_type = `READER_MOD;
half_byte_counter = 1'b0;
end
else if ((receive_buffer[19:0] == {`READER_END_COMM_1, 4'b0} || receive_buffer[19:0] == {`READER_END_COMM_2, 4'b0}) && half_byte_counter == 1'd0)
begin
mod_type = `READER_LISTEN;
end
end
else if (hi_simulate_mod_type == `FAKE_TAG) // Fake Tag
begin
if (receive_buffer[19:0] == {16'b0, `TAG_START_COMM_FIRST_CHAR})
begin
mod_type = `TAGSIM_MOD;
half_byte_counter = 1'b0;
end
else if (receive_buffer[11:0] == {`TAG_END_COMM, 4'b0} && half_byte_counter == 1'd0)
begin
mod_type = `TAGSIM_LISTEN;
end
end
end
end
endmodule |
// -------------------------------------------------------------
//
// File Name: mealy_rtl\Stateflow_Mealy_example\Mealy_Chart.v
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Mealy_Chart
// Source Path: Stateflow_Mealy_example/Mealy_Subsystem/Mealy_Chart
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Mealy_Chart
(
clk,
rst_n,
enb,
a,
b
);
input clk;
input rst_n;
input enb;
output [63:0] a; // double
output [63:0] b; // double
parameter IN_FINAL = 3'd0, IN_IDLE = 3'd1, IN_INITIAL = 3'd2, IN_SEQ1 = 3'd3, IN_SEQ2 = 3'd4;
reg [2:0] is_Mealy_Chart; // uint8
real a_1; // double
real b_1; // double
real a_reg; // double
real b_reg; // double
reg [2:0] is_Mealy_Chart_next; // enum type state_type_is_Mealy_Chart (5 enums)
real a_reg_next; // double
real b_reg_next; // double
always @(posedge clk or negedge rst_n)
begin : Mealy_Chart_1_process
if (rst_n == 1'b0) begin
is_Mealy_Chart <= IN_INITIAL;
end
else begin
if (enb) begin
is_Mealy_Chart <= is_Mealy_Chart_next;
a_reg <= a_reg_next;
b_reg <= b_reg_next;
end
end
end
always @* begin
is_Mealy_Chart_next = is_Mealy_Chart;
a_reg_next = a_reg;
b_reg_next = b_reg;
case ( is_Mealy_Chart)
IN_FINAL :
begin
is_Mealy_Chart_next = IN_IDLE;
end
IN_IDLE :
begin
a_reg_next = 0.0;
is_Mealy_Chart_next = IN_SEQ1;
end
IN_INITIAL :
begin
a_reg_next = 0.0;
b_reg_next = 0.0;
is_Mealy_Chart_next = IN_IDLE;
end
IN_SEQ1 :
begin
a_reg_next = 1.0;
b_reg_next = b_reg + 1.0;
is_Mealy_Chart_next = IN_SEQ2;
end
default :
begin
is_Mealy_Chart_next = IN_FINAL;
end
endcase
end
always @* a_1 = a_reg_next;
always @* b_1 = b_reg_next;
assign a = $realtobits(a_1);
assign b = $realtobits(b_1);
endmodule // Mealy_Chart
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: recv_credit_flow_ctrl.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Monitors the receive completion credits for headers and
// data to make sure the rx_port modules don't request too
// much data from the root complex, as this could result in
// some data being dropped/lost.
// Author: Matt Jacobsen
// Author: Dustin Richmond
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module recv_credit_flow_ctrl
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w
input RX_ENG_RD_DONE, // Read completed
input TX_ENG_RD_REQ_SENT, // Read completion request issued
output RXBUF_SPACE_AVAIL // High if enough read completion credits exist to make a read completion request
);
reg rCreditAvail=0;
reg rCplDAvail=0;
reg rCplHAvail=0;
reg [12:0] rMaxRecv=0;
reg [11:0] rCplDAmt=0;
reg [7:0] rCplHAmt=0;
reg [11:0] rCplD=0;
reg [7:0] rCplH=0;
reg rInfHCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
reg rInfDCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
assign RXBUF_SPACE_AVAIL = rCreditAvail;
// Determine the completions required for a max read completion request.
always @(posedge CLK) begin
rInfHCred <= (CONFIG_MAX_CPL_HDR == 0);
rInfDCred <= (CONFIG_MAX_CPL_DATA == 0);
rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
rCplDAmt <= #1 (rMaxRecv>>4);
rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
rCreditAvail <= #1 ((rCplHAvail|rInfHCred) & (rCplDAvail | rInfDCred));
end
// Count the number of outstanding read completion requests.
always @ (posedge CLK) begin
if (RST) begin
rCplH <= #1 0;
rCplD <= #1 0;
end
else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH;
rCplD <= #1 rCplD;
end
else if (TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH + rCplHAmt;
rCplD <= #1 rCplD + rCplDAmt;
end
else if (RX_ENG_RD_DONE) begin
rCplH <= #1 rCplH - rCplHAmt;
rCplD <= #1 rCplD - rCplDAmt;
end
end
endmodule
|
#include <bits/stdc++.h> int main() { int i, gt = 0, arr[4]; char var = C ; char A[102]; for (i = 0; i < 4; i++) { scanf( %s , A); arr[i] = strlen(A) - 2; } for (i = 0; i < 4; i++) { if (i == 0) { if (arr[0] >= (2 * arr[1]) && arr[0] >= (2 * arr[2]) && arr[0] >= (2 * arr[3])) { gt++; var = A ; } else if ((2 * arr[0]) <= (arr[1]) && (2 * arr[0]) <= (arr[2]) && (2 * arr[0]) <= (arr[3])) { gt++; var = A ; } } else if (i == 1) { if (arr[1] >= (2 * arr[0]) && arr[1] >= (2 * arr[2]) && arr[1] >= (2 * arr[3])) { gt++; var = B ; } else if ((2 * arr[1]) <= (arr[0]) && (2 * arr[1]) <= (arr[2]) && (2 * arr[1]) <= (arr[3])) { gt++; var = B ; } } else if (i == 2) { if (arr[2] >= (2 * arr[1]) && arr[2] >= (2 * arr[0]) && arr[2] >= (2 * arr[3])) { gt++; var = C ; } else if ((2 * arr[2]) <= (arr[1]) && (2 * arr[2]) <= (arr[0]) && (2 * arr[2]) <= (arr[3])) { gt++; var = C ; } } else if (i == 3) { if (arr[3] >= (2 * arr[1]) && arr[3] >= (2 * arr[2]) && arr[3] >= (2 * arr[0])) { gt++; var = D ; } else if ((2 * arr[3]) <= (arr[1]) && (2 * arr[3]) <= (arr[2]) && (2 * arr[3]) <= (arr[0])) { gt++; var = D ; } } } if (gt == 1) { printf( %c , var); } else { printf( C ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int M = 1e7 + 1; ; const long long INF = 2e9 + 10; const long long MOD = 1000 * 1000 * 1000 + 7; const long double EPS = 1e-9; int a[N]; bool prime(int x) { for (int i = 2; i < (int)sqrt(x) + 1; ++i) if (x % i == 0) return false; return true; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; if (prime(n)) cout << 1; else if (prime(n - 2)) cout << 2; else if (n % 2 == 0) cout << 2; else cout << 3; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const int INF = 0x7fffffff; const long long oo = 1e18; const int N = 106; const double pi = acos(-1.0); int n, ans = 1, now; char c; int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %c , &c); now = c - 0 ; if (now) ans++; else break; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x60000000; const int MINF = -1000000000; const int mod = 1000000007; const int cons = 100001; const double pi = 3.141592653589793; const int sqrtMax = 317; const int blocks = cons / 3; const int MOD = 100000; long long dp[1000001]; int ans[5001]; int main() { int m; scanf( %d , &m); for (int n = 1; n <= 50; n++) { int cnt = 0; int sum = 0; memset(dp, 0, sizeof(dp)); for (int i = 0; i <= n; i++) { for (int j = 0; j <= n; j++) { for (int k = 0; k <= n; k++) { for (int p = 0; p <= n; p++) { if (i + j + k + p == n) { sum = i * 1 + j * 5 + k * 10 + p * 50; dp[sum]++; if (dp[sum] > 1) { } else if (dp[sum] == 1) cnt++; } } } } } ans[n] = cnt; } if (m > 50) { printf( %lld n , (long long)ans[50] + 49LL * (m - 50)); } else { printf( %d n , ans[m]); } return 0; } |
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module RegTwoA(CLK, RST, Q_OUT, D_INA, ENA, D_INB, ENB);
parameter width = 1;
parameter init = { width {1'b0 }} ;
input CLK;
input RST;
input ENA ;
input ENB;
input [width - 1 : 0] D_INA;
input [width - 1 : 0] D_INB;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK or `BSV_RESET_EDGE RST)
begin
if (RST == `BSV_RESET_VALUE)
Q_OUT <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if (ENA)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_INA;
else if (ENB)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_INB;
end // else: !if(RST == `BSV_RESET_VALUE)
end
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
Q_OUT = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datrom.v when simulating
// the core, upd77c25_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_datrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [15 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1536),
.C_READ_DEPTH_B(1536),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1536),
.C_WRITE_DEPTH_B(1536),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> int q, n; int main() { scanf( %d , &q); while (q--) { scanf( %d , &n); int b = sqrt(2 * n + 4); while ((b + 1) * (b + 2) / 2 > n) b--; int a = n - (b + 1) * (b + 2) / 2; printf( 133 ); for (int i = 1; i <= a; i++) printf( 7 ); for (int i = 1; i <= b; i++) printf( 3 ); printf( 7 n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int x, y, n; cin >> x >> y >> n; int a, b; a = n % x; b = n - a; if (b + y <= n) { cout << b + y << endl; } else { cout << b + y - x << endl; } } } |
#include <bits/stdc++.h> using namespace std; template <class X, class Y> void amax(X& x, const Y& y) { if (x < y) x = y; } template <class X, class Y> void amin(X& x, const Y& y) { if (x > y) x = y; } const int INF = 1e9 + 10; const long long INFL = 1e18 + 10; const int MAX = 1e6 + 10; int n; int a[MAX], prv[MAX], pos[MAX]; long long gt[MAX * 4], lazy[MAX * 4]; void update(int id, int l, int r, int u, int v) { if (v < l || u > r) return; if (u <= l && r <= v) { lazy[id]++; gt[id] += (r - l + 1); return; } int mid = (l + r) / 2; update(id * 2, l, mid, u, v); update(id * 2 + 1, mid + 1, r, u, v); gt[id] = gt[id * 2] + gt[id * 2 + 1] + lazy[id] * (r - l + 1); } long long query(int id, int l, int r, int u, int v) { if (v < l || u > r) return 0; if (u <= l && r <= v) return gt[id]; int mid = (l + r) / 2; return query(id * 2, l, mid, u, v) + query(id * 2 + 1, mid + 1, r, u, v) + lazy[id] * (min(r, v) - max(u, l) + 1); } void process() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { prv[i] = pos[a[i]]; pos[a[i]] = i; } long double sum = 0; long double choose = (long long)n * n; for (int i = 1; i <= n; i++) { update(1, 1, n, prv[i] + 1, i); sum = sum + (query(1, 1, n, 1, i) * 2 - 1) / choose; } cout << fixed << setprecision(10) << sum << n ; } int main() { ios_base::sync_with_stdio(false); process(); } |
#include <bits/stdc++.h> using namespace std; long double l[200006]; int main() { l[1] = 0; l[0] = 0; for (int i = 2; i < 200005; i++) { l[i] = log(i) + l[i - 1]; } int n, m, k; scanf( %d%d%d , &n, &m, &k); if (k >= m) { printf( 1.00000 n ); } else if (k + n < m) { printf( 0.00000 n ); } else { long double ans = l[n] + l[m] - l[n + k + 1] - l[m - k - 1]; ans = exp(ans); double tmp = 1.0 - ans; printf( %.10f n , tmp); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long h12, h13, h14, h23, h24, h34; long long k1, k2, k3; long long x1, x2, x3, x4, x5, x6, x7; long long min_x7, max_x7, best_x7; long long good = 0; long long len = -1; void fail() { printf( -1 n ); exit(0); } int main() { cin >> h12 >> h13 >> h14 >> h23 >> h24 >> h34; if ((h12 + h13 + h23) % 2 != 0) fail(); k1 = (h12 + h13 - h23) / 2; k2 = (h12 + h23 - h13) / 2; k3 = (h13 + h23 - h12) / 2; if (k1 < 0 || k2 < 0 || k3 < 0) fail(); if ((h14 + h34 - k1 - k3) % 2 != 0) fail(); max_x7 = (h14 + h34 - k1 - k3) / 2; if ((k2 + k3 - h24 - h34) % 2 != 0) fail(); min_x7 = -k1 - (k2 + k3 - h24 - h34) / 2; max_x7 = min(max_x7, -(k2 + k3 - h24 - h34) / 2); min_x7 = max(min_x7, (h14 + h34 - k1 - k3) / 2 - k2); if ((h14 + h24 - k1 - k2) % 2 != 0) fail(); max_x7 = min(max_x7, (h14 + h24 - k1 - k2) / 2); min_x7 = max(min_x7, (h14 + h24 - k1 - k2) / 2 - k3); if (min_x7 > max_x7) fail(); for (int i = (max(0ll, min_x7)); i < (int)(min(1000000ll, max_x7 + 1)); ++i) { x7 = i; x3 = (h14 + h34 - k1 - k3) / 2 - x7; x1 = k1 + x7 + (k2 + k3 - h24 - h34) / 2; x5 = k1 - x1 + x3 + k3 + x7 - h34; x6 = k3 - x5; x4 = k2 - x3; x2 = k1 - x1; if (x1 < 0 || x2 < 0 || x3 < 0 || x4 < 0 || x5 < 0 || x6 < 0 || x7 < 0) continue; good = 1; if (len == -1 || len > x1 + x2 + x3 + x4 + x5 + x6 + x7) { len = x1 + x2 + x3 + x4 + x5 + x6 + x7; best_x7 = x7; } } if (!good) fail(); x7 = best_x7; x3 = (h14 + h34 - k1 - k3) / 2 - x7; x1 = k1 + x7 + (k2 + k3 - h24 - h34) / 2; x5 = k1 - x1 + x3 + k3 + x7 - h34; x6 = k3 - x5; x4 = k2 - x3; x2 = k1 - x1; cout << x1 + x2 + x3 + x4 + x5 + x6 + x7 << n ; for (int(i) = 0; (i) < (int)(x1 + x2 + x3 + x4 + x5 + x6 + x7); ++(i)) printf( a ); printf( n ); for (int(i) = 0; (i) < (int)(x1 + x2 + x3 + x4); ++(i)) printf( b ); for (int(i) = 0; (i) < (int)(x5 + x6 + x7); ++(i)) printf( a ); printf( n ); for (int(i) = 0; (i) < (int)(x1 + x2); ++(i)) printf( b ); for (int(i) = 0; (i) < (int)(x3 + x4); ++(i)) printf( a ); for (int(i) = 0; (i) < (int)(x5 + x6); ++(i)) printf( b ); for (int(i) = 0; (i) < (int)(x7); ++(i)) printf( a ); printf( n ); for (int(i) = 0; (i) < (int)(x1); ++(i)) printf( b ); for (int(i) = 0; (i) < (int)(x2); ++(i)) printf( a ); for (int(i) = 0; (i) < (int)(x3); ++(i)) printf( b ); for (int(i) = 0; (i) < (int)(x4); ++(i)) printf( a ); for (int(i) = 0; (i) < (int)(x5); ++(i)) printf( b ); for (int(i) = 0; (i) < (int)(x6); ++(i)) printf( a ); for (int(i) = 0; (i) < (int)(x7); ++(i)) printf( b ); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long min(long long a, long long b) { return a < b ? a : b; } int ceil(int a, int b) { return (a + b - 1) / b; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, k; cin >> n >> k; string s; cin >> s; if (!k) { cout << s; return 0; } if (s.length() == 1) { cout << 0; return 0; } int cnt = 0; if (s[0] != 1 ) s[0] = 1 , cnt++; for (int i = 1; i <= s.length(); i++) { if (cnt == k) break; if (s[i] != 0 ) s[i] = 0 , cnt++; } cout << s; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; vector<string> S(26); for (auto ch : s) { S[ch - a ] += ch; if (S[ch - a ].size() == 100) { cout << S[ch - a ] << endl; return 0; } } int n = s.size(); int f[n + 1][n + 1]; int g[n + 1][n + 1]; for (int len = 1; len <= n; ++len) for (int i = 0; i + len - 1 < n; ++i) { if (len == 1) f[len][i] = 1; else if (len == 2 && s[i] == s[i + len - 1]) f[len][i] = 2; else { int a = f[len - 1][i] < f[len - 1][i + 1] ? f[len - 1][i + 1] : f[len - 1][i]; if (f[len - 1][i] == a) g[len][i] = 0; else g[len][i] = 1; if (len > 2 && s[i] == s[i + len - 1] && 2 + f[len - 2][i + 1] > a) { a = 2 + f[len - 2][i + 1]; g[len][i] = 2; } f[len][i] = a; } } vector<int> v; int len = n, x = 0; while (true) { if (len == 1) { v.push_back(x); break; } if (len == 2 && s[x] == s[x + len - 1]) { v.push_back(x); v.push_back(x + 1); break; } if (g[len][x] == 0) --len; else if (g[len][x] == 1) { --len; ++x; } else { v.push_back(x); v.push_back(x + len - 1); len -= 2; ++x; } } sort(v.begin(), v.end()); int take = 50; for (int i = 0; i < v.size(); ++i) if (i < take || i + take >= v.size()) cout << s[v[i]]; return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im:1.0
// IP Revision: 6
(* X_CORE_INFO = "fmrv32im,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "fmrv32im_artya7_fmrv32im_0,fmrv32im,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_0 (
RST_N,
CLK,
I_MEM_WAIT,
I_MEM_ENA,
I_MEM_ADDR,
I_MEM_RDATA,
I_MEM_BADMEM_EXCPT,
D_MEM_WAIT,
D_MEM_ENA,
D_MEM_WSTB,
D_MEM_ADDR,
D_MEM_WDATA,
D_MEM_RDATA,
D_MEM_BADMEM_EXCPT,
EXT_INTERRUPT,
TIMER_EXPIRED
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_WAIT" *)
input wire I_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ENA" *)
output wire I_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] I_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] I_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire I_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WAIT" *)
input wire D_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ENA" *)
output wire D_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WSTB" *)
output wire [3 : 0] D_MEM_WSTB;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] D_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WDATA" *)
output wire [31 : 0] D_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] D_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire D_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 EXT_INTERRUPT INTERRUPT" *)
input wire EXT_INTERRUPT;
input wire TIMER_EXPIRED;
fmrv32im #(
.MADD33_ADDON(1)
) inst (
.RST_N(RST_N),
.CLK(CLK),
.I_MEM_WAIT(I_MEM_WAIT),
.I_MEM_ENA(I_MEM_ENA),
.I_MEM_ADDR(I_MEM_ADDR),
.I_MEM_RDATA(I_MEM_RDATA),
.I_MEM_BADMEM_EXCPT(I_MEM_BADMEM_EXCPT),
.D_MEM_WAIT(D_MEM_WAIT),
.D_MEM_ENA(D_MEM_ENA),
.D_MEM_WSTB(D_MEM_WSTB),
.D_MEM_ADDR(D_MEM_ADDR),
.D_MEM_WDATA(D_MEM_WDATA),
.D_MEM_RDATA(D_MEM_RDATA),
.D_MEM_BADMEM_EXCPT(D_MEM_BADMEM_EXCPT),
.EXT_INTERRUPT(EXT_INTERRUPT),
.TIMER_EXPIRED(TIMER_EXPIRED)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_1_V
`define SKY130_FD_SC_HVL__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; int n, a[N], s1[N], s2[N], ans = 0; void judge(int x, int y, int mid) { int tmp = 0; if (x == y) tmp = s1[mid] + s2[n] - s2[mid]; else tmp = s1[x - 1] + s2[n] - s2[y] + s2[mid] - s2[x - 1] + s1[y] - s1[mid]; ans = max(ans, tmp); } int main() { scanf( %d , &n); int i, j, x, y; for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) { s1[i] = s1[i - 1]; s2[i] = s2[i - 1]; if (a[i] == 1) s1[i]++; else s2[i]++; } int mx, val, mid; for (x = 1; x <= n; x++) { if (a[x] == 1) val = -1; else val = 1; mid = x; mx = val; judge(x, x, x); judge(x, x, x - 1); for (y = x + 1; y <= n; y++) { if (a[y] == 1) val--; else val++; if (val > mx) mx = val, mid = y; judge(x, y, mid); } } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, q; int x[1000][1000]; int r[1000][1000][4]; void upd1(int j) { int i = 0; for (int k = 0; k < n; ++k) { if (x[k][j] == 0) { i = k + 1; r[k][j][0] = -1; } else r[k][j][0] = i; } i = n - 1; for (int k = n - 1; k > -1; --k) { if (x[k][j] == 0) { i = k - 1; r[k][j][1] = -1; } else r[k][j][1] = i; } } void upd2(int i) { int j = 0; for (int k = 0; k < m; ++k) { if (x[i][k] == 0) { j = k + 1; r[i][k][2] = -1; } else r[i][k][2] = j; } j = m - 1; for (int k = m - 1; k > -1; --k) { if (x[i][k] == 0) { j = k - 1; r[i][k][3] = -1; } else r[i][k][3] = j; } } int main() { cin.sync_with_stdio(false); cin >> n >> m >> q; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) cin >> x[i][j]; for (int j = 0; j < m; ++j) upd1(j); for (int i = 0; i < n; ++i) upd2(i); for (int k = 0; k < q; ++k) { int op; int i, j; cin >> op; cin >> i >> j; i--; j--; if (op == 1) { x[i][j] = 1 - x[i][j]; upd1(j); upd2(i); } else { int res = 0; if (x[i][j] != 0) { int up = 0; int down = n - 1; for (int k = j; k <= r[i][j][3]; ++k) { up = max(up, r[i][k][0]); down = min(down, r[i][k][1]); res = max(res, (down - up + 1) * (k - j + 1)); } up = 0; down = n - 1; for (int k = j; k >= r[i][j][2]; --k) { up = max(up, r[i][k][0]); down = min(down, r[i][k][1]); res = max(res, (down - up + 1) * (j - k + 1)); } int left = 0; int right = m - 1; for (int k = i; k <= r[i][j][1]; ++k) { left = max(left, r[k][j][2]); right = min(right, r[k][j][3]); res = max(res, (right - left + 1) * (k - i + 1)); } left = 0; right = m - 1; for (int k = i; k >= r[i][j][0]; --k) { left = max(left, r[k][j][2]); right = min(right, r[k][j][3]); res = max(res, (right - left + 1) * (i - k + 1)); } } cout << res << endl; } } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; int n[2], k[2]; string s[] = { First , Second }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n[0] >> n[1] >> k[0] >> k[1]; int cur = 0; while (1) { if (n[cur] == 0) break; n[cur]--; cur ^= 1; } cout << s[cur ^ 1]; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, a, b, c, ans; int main() { cin >> n >> a >> b >> c; if (n >= b) ans = (n - ((n - b) / (b - c) + 1) * (b - c)) / a + (n - b) / (b - c) + 1; cout << max(n / a, ans); } |
#include <bits/stdc++.h> int main() { int n, m; double resn, resm; scanf( %d%d , &n, &m); resn = m / (double)n; resm = log(m) / log(n); if (resn > resm) { printf( > n ); } else if (resn < resm) { printf( < n ); } else printf( = n ); return 0; } |
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_8_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2014 , Atsushi Sasaki
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: i2s_to_tdm_converter.v
//
// *Module Description:
// I2S to TDM Converter
//
// *Author(s):
// - Atsushi Sasaki,
//
//----------------------------------------------------------------------------
// $Rev: 1.00 $
// $LastChangedBy: Atsushi Sasaki $
// $LastChangedDate: 2014-06-06 $
//----------------------------------------------------------------------------
module i2s_to_tdm_comverter(
rst_i,
mck_i,
bck_i,
lrck_i,
dat_i,
sck_o,
fsync_o,
dat_o
);
//
// Parameters
//
//
// I/O Ports
//
input rst_i; // reset
input mck_i; // 256fs
input bck_i; // 64fs
input lrck_i; // fs
input [3:0] dat_i;
output sck_o; // 256fs
output fsync_o; // fs
output reg dat_o; // multi ch output
//
// Wires, Registers
//
reg rst_int;
wire rst = rst_i | rst_int;
reg [8:0] bit_cnt; // input data bit counter
wire bank = bit_cnt[8];
// reg bank; // FIFO Buffer Bank
wire sck = mck_i; // internal system clock
assign sck_o = sck;
wire [5:0] inbit_cnt = bit_cnt[7:2];
//
// module
//
// LRCK Negedge Detector
reg d_lrck_1, d_lrck_2, d_lrck_3, d_lrck_4, d_lrck_5, d_lrck_6; // Delayed LRCK
wire lrck_negedge_flag; // Frame Sync for LRCK Falling Edge
assign lrck_negedge_flag = (d_lrck_4 ^ d_lrck_6) & ~d_lrck_4;
always @ (posedge sck or posedge rst_i) begin
if(rst_i) begin
d_lrck_1 <= 1'b0;
d_lrck_2 <= 1'b0;
d_lrck_3 <= 1'b0;
d_lrck_5 <= 1'b0;
end
else begin
d_lrck_1 <= lrck_i;
d_lrck_2 <= d_lrck_1;
d_lrck_3 <= d_lrck_2;
d_lrck_5 <= d_lrck_4;
end
end
always @ (negedge sck or posedge rst_i) begin
if(rst_i) begin
d_lrck_4 <= 1'b0;
d_lrck_6 <= 1'b0;
end
else begin
d_lrck_4 <= d_lrck_3;
d_lrck_6 <= d_lrck_5;
end
end
// Internal Async Reset
always @ (negedge d_lrck_4 or posedge rst_i) begin
if(rst_i) begin
rst_int <= 1'b1;
end
else begin
if(&bit_cnt[7:0]) begin
rst_int <= 1'b0;
end
else begin
rst_int <= 1'b1;
end
end
end
// Bit counter
always @ (negedge sck or posedge rst) begin
if(rst) begin
bit_cnt <= 9'b111111111;
end
else begin
bit_cnt <= bit_cnt + 1'b1;
end
end
// Input Buffer
reg [255:0] fifo_a;
reg [255:0] fifo_b;
always @ (posedge bck_i or posedge rst) begin
if(rst) begin
fifo_a <= 256'b0;
fifo_b <= 256'b0;
end
else begin
if(!bank) begin
fifo_a[255-bit_cnt[7:2]] <= dat_i[0];
fifo_a[191-bit_cnt[7:2]] <= dat_i[1];
fifo_a[127-bit_cnt[7:2]] <= dat_i[2];
fifo_a[63-bit_cnt[7:2]] <= dat_i[3];
end
else begin
fifo_b[255-bit_cnt[7:2]] <= dat_i[0];
fifo_b[191-bit_cnt[7:2]] <= dat_i[1];
fifo_b[127-bit_cnt[7:2]] <= dat_i[2];
fifo_b[63-bit_cnt[7:2]] <= dat_i[3];
end
end
end
// TDM Generator
always @ (posedge sck or posedge rst) begin
if(rst) begin
dat_o <= 1'b0;
end
else begin
if(!bank) begin
dat_o <= fifo_b[255-bit_cnt[7:0]];
end
else begin
dat_o <= fifo_a[255-bit_cnt[7:0]];
end
end
end
assign fsync_o = &bit_cnt[7:0];
endmodule
|
// place this file in testBench folder
`timescale 1ns/100ps
`define DEBUG 1
`include "../define.v"
`include "../regfile.v"
`include "../pipeline_CPU.v"
`include "../hilo_reg.v"
`include "../BranchControl.v"
`include "../HazardControl.v"
`include "../ForwardControl.v"
`include "../IF.v"
`include "../IF_ID.v"
`include "../ID.v"
`include "../ID_EX.v"
`include "../EX.v"
`include "../ALU.v"
`include "../decoder.v"
`include "../EX_MEM.v"
`include "../MEM.v"
`include "../RM_ctrl.v"
`include "../WM_ctrl.v"
`include "../MEM_WB.v"
`include "../utilities/dffe.v"
`include "../utilities/mux2x1.v"
`include "../utilities/mux4x1.v"
`include "rom.v"
`include "memory.v"
module SOPC;
reg clk;
reg rst;
wire[`RegDataWidth-1:0] data_from_mem;
wire[`MemAddrWidth-1:0] mem_addr;
wire[3:0] mem_byte_slct;
wire[`RegDataWidth-1:0] data_to_write_mem;
wire mem_we;
wire mem_re;
wire[`InstDataWidth-1:0] inst_from_rom;
wire[`InstAddrWidth-1:0] rom_addr;
wire rom_ce;
supply1 vcc;
supply0 gnd;
pipeline_CPU CPU(
.clk(clk),
.rst(rst),
.data_from_mem(data_from_mem),
.mem_addr(mem_addr),
.mem_byte_slct(mem_byte_slct),
.data_to_write_mem(data_to_write_mem),
.mem_we(mem_we),
.mem_re(mem_re),
.inst_from_rom(inst_from_rom),
.rom_addr(rom_addr),
.rom_ce(rom_ce)
);
rom #(.InstMemNum(32)) ROM(
.rst(gnd),
.ce(rom_ce),
.addr(rom_addr),
.inst(inst_from_rom)
);
memory RAM(
.rst(rst),
.ce(mem_re),
.data_i(data_to_write_mem),
.addr_i(mem_addr),
.we(mem_we),
.byte_slct(mem_byte_slct),
.data_o(data_from_mem)
);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial begin
$dumpfile("test_info/memory/memory.vcd");
$dumpvars;
$readmemh("test_info/memory/memory.data", ROM.rom_data, 0, 19);
rst = `RstEnable;
#3 rst = ~`RstEnable;
#70 $finish;
end
endmodule |
#include <bits/stdc++.h> using namespace std; vector<int> get(int n) { if (n == 1) { return {1}; } if (n == 2) { return {3, 4}; } vector<int> a; if (n % 2 == 0) { int k = n / 2; for (int i = 1; i <= 2 * k - 1; i++) { a.push_back(1); } a.push_back(k - 1); } else { int k = n / 2; for (int i = 1; i <= 2 * k - 1; i++) { a.push_back(1); } a.push_back(2); a.push_back(k + 1); } return a; } int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<int> a = get(n), b = get(m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << a[i] * b[j] << ; } cout << n ; } } |
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> t; int get(int a) { if (t[a] == a) { return a; } else { return t[a] = get(t[a]); } } struct kek { int a; int b; int c; }; bool operator<(kek a, kek b) { return a.c < b.c; } void uni(int a, int b) { a = get(a); b = get(b); if (a != b) t[a] = b; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n + 1; i++) t.push_back(i - 1); m--; vector<kek> e(m); int a, b, c; cin >> a >> b >> c; for (int i = 0; i < m; i++) cin >> e[i].a >> e[i].b >> e[i].c; sort(e.begin(), e.end()); int sol = 0; if (m == 0) { sol = (int)1e9; } for (int i = 0; i < m; i++) { auto it = e[i]; int x = it.a; int y = it.b; int z = it.c; if (get(a) != get(b)) sol = max(sol, e[i].c); uni(x, y); int urm; if (i + 1 == m) urm = (int)1e9; else urm = max(e[i].c, e[i + 1].c - 1); if (get(a) != get(b)) sol = max(sol, urm); } cout << sol << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRBN_PP_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int sum[1010][1010]; char mp[1010][1010]; int getsum(int x1, int y1, int x2, int y2) { return sum[x1][y1] - sum[x2 + 1][y1] - sum[x1][y2 + 1] + sum[x2 + 1][y2 + 1]; } bool check(int a, int b, int x, int y) { while (1) { if (x + a - 1 > n || y + b - 1 > m) return 0; if (getsum(x, y, x + a - 1, y + b - 1) != a * b) return 0; if (getsum(x + a, y, n, y) > 0 && getsum(x, y + b, x, m) > 0) return 0; if (sum[x + a][y] == 0 && sum[x][y + b] == 0) break; if (getsum(x + a, y, n, y) > 0) { x++; if (getsum(x + a - 1, y, x + a - 1, y + b - 1) > 0 && getsum(x + a - 1, y, x + a - 1, y + b - 1) != b) return 0; } else { y++; if (getsum(x, y + b - 1, x + a - 1, y + b - 1) > 0 && getsum(x, y + b - 1, x + a - 1, y + b - 1) != a) return 0; } } return 1; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , mp[i] + 1); memset(sum, 0, sizeof(sum)); int x0, y0; x0 = y0 = 10000; for (int i = n; i >= 1; i--) for (int j = m; j >= 1; j--) { sum[i][j] = sum[i + 1][j] + sum[i][j + 1] - sum[i + 1][j + 1] + (mp[i][j] == X ); if (mp[i][j] == X ) { x0 = min(x0, i); y0 = min(y0, j); } } int ans = n * m + 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (i * j >= ans) continue; if (check(i, j, x0, y0)) ans = i * j; } if (ans > n * m) printf( -1 n ); else printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; for (int i = 0; i < q; ++i) { int n; cin >> n; vector<int> a(n); for (int j = 0; j < n; ++j) { cin >> a[j]; --a[j]; } int pos = 0; while (pos < n) { int nxt = min_element(a.begin() + pos, a.end()) - a.begin(); int el = a[nxt]; a.erase(a.begin() + nxt); a.insert(a.begin() + pos, el); if (pos == nxt) pos = nxt + 1; else pos = nxt; } for (auto it : a) cout << it + 1 << ; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; template <class T, class U> void maximize(T &x, U y) { if (x < y) x = y; } template <class T, class U> void minimize(T &x, U y) { if (x > y) x = y; } template <class T> T Abs(T x) { return (x < (T)0 ? -x : x); } namespace task { const int N = 505; bool f[N][N]; int a[N], b[N]; int n, k; long long tot = 0; void solve() { cin >> n >> k; for (int i = 1; i <= n; ++i) { cin >> a[i] >> b[i]; tot += a[i]; tot += b[i]; } f[0][0] = true; for (int i = 1; i <= n; ++i) { for (int j = 0; j < k; ++j) { f[i][j] = f[i - 1][(j - a[i] % k + k) % k]; for (int l = 0; l <= min(a[i], k - 1); ++l) { if ((a[i] - l) % k + b[i] >= k) { f[i][j] |= f[i - 1][(j - l + k) % k]; } } } } long long ans = 0; for (int i = 0; i < k; ++i) { if (f[n][i]) { maximize(ans, (tot - 1LL * i) / (1LL * k)); } } cout << ans; } } // namespace task int main(void) { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); task::solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_SYMBOL_V
`define SKY130_FD_SC_HD__NOR3_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int N, K; int arr[205]; int u[100005], v[100005], f[100005]; int lvl[205], ptr[205]; bool vis[205]; vector<int> graph[205]; vector<int> cgraph[205]; vector<vector<int>> vec; void addedge(int a, int b, int k) { u[K] = a; v[K] = b; u[K ^ 1] = b; v[K ^ 1] = a; f[K] = k; graph[a].push_back(K); graph[b].push_back(K ^ 1); K += 2; } bool bfs() { queue<int> qu; qu.push(0); fill(lvl, lvl + N + 2, 0); lvl[0] = 1; while (qu.size()) { int n = qu.front(); qu.pop(); for (int e : graph[n]) { if (f[e] && !lvl[v[e]]) { lvl[v[e]] = lvl[u[e]] + 1; qu.push(v[e]); } } } return lvl[N + 1]; } int dfs(int n, int p) { if (n == N + 1 || !p) { return p; } for (int &i = ptr[n]; i < graph[n].size(); i++) { int e = graph[n][i]; if (f[e] && lvl[v[e]] > lvl[n]) { int k = dfs(v[e], min(f[e], p)); if (!k) { continue; } f[e] -= k; f[e ^ 1] += k; return k; } } return 0; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N; for (int i = 1; i <= N; i++) { cin >> arr[i]; if (arr[i] % 2 == 1) { addedge(0, i, 2); } else { addedge(i, N + 1, 2); } } for (int i = 1; i <= N; i++) { for (int j = 1; j <= N; j++) { if (arr[i] % 2 == 1 && arr[j] % 2 == 0) { bool isp = 1; for (int k = 2; k <= sqrt(arr[i] + arr[j]); k++) { if ((arr[i] + arr[j]) % k == 0) { isp = 0; break; } } if (isp) { addedge(i, j, 1); } } } } int ans = 0; while (1) { if (!bfs()) { break; } fill(ptr, ptr + 2 + N, 0); int p; while ((p = dfs(0, INT_MAX / 2))) { ans += p; } } if (ans != N) { cout << Impossible n ; return 0; } for (int e = 1; e < K; e += 2) { if (f[e] && u[e] != 0 && v[e] != 0 && u[e] != N + 1 && v[e] != N + 1) { cgraph[v[e]].push_back(u[e]); cgraph[u[e]].push_back(v[e]); } } for (int n = 1; n <= N; n++) { if (!vis[n]) { int c = n; vector<int> temp; while (!vis[c]) { temp.push_back(c); vis[c] = 1; for (int e : cgraph[c]) { if (!vis[e]) { c = e; } } } vec.push_back(temp); } } cout << vec.size() << n ; for (auto k : vec) { cout << k.size() << ; for (int n : k) { cout << n << ; } cout << n ; } } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; template <typename T> void read(T &a) { T x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } a = x * f; } template <typename T> void print(T x) { if (!x) return; if (x < 0) putchar( - ), x = -x; print(x / 10); putchar(x % 10 + 0 ); } template <typename T, typename... Args> void read(T &t, Args &...args) { read(t); read(args...); } long long n, a[200005 << 1], res = 0, las[200005 << 1]; map<long long, long long> mp; signed main() { read(n); for (long long i = 1; i <= n; i++) read(a[i]), mp[a[i]]++; long long maxid, maxx = -1; for (map<long long, long long>::iterator it = mp.begin(); it != mp.end(); it++) { if (maxx < it->second) { maxx = it->second; maxid = it->first; } } for (map<long long, long long>::iterator it = mp.begin(); it != mp.end(); it++) { if (it->first == maxid) continue; long long sum = n; memset(las, -1, sizeof(las)); las[n] = 0; for (long long i = 1; i <= n; i++) { if (a[i] == it->first) sum--; if (a[i] == maxid) sum++; if (las[sum] != -1) res = max(res, i - las[sum]); else las[sum] = i; } } printf( %lld n , res); return 0; } |
module hex_to_7seg
(
input i_Clk,
input [3:0] i_Value,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
reg [6:0] out = 7'b0000000;
always @(posedge i_Clk)
begin
case (i_Value)
4'b0000 : out <= 7'b0000001;
4'b0001 : out <= 7'b1001111;
4'b0010 : out <= 7'b0010010;
4'b0011 : out <= 7'b0000110;
4'b0100 : out <= 7'b1001100;
4'b0101 : out <= 7'b0100100;
4'b0110 : out <= 7'b0100000;
4'b0111 : out <= 7'b0001111;
4'b1000 : out <= 7'b0000000;
4'b1001 : out <= 7'b0000100;
4'b1010 : out <= 7'b0001000;
4'b1011 : out <= 7'b1100000;
4'b1100 : out <= 7'b0110001;
4'b1101 : out <= 7'b1000010;
4'b1110 : out <= 7'b0110000;
4'b1111 : out <= 7'b0111000;
endcase
end
assign o_Segment_A = out[6];
assign o_Segment_B = out[5];
assign o_Segment_C = out[4];
assign o_Segment_D = out[3];
assign o_Segment_E = out[2];
assign o_Segment_F = out[1];
assign o_Segment_G = out[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long vec3[17][1 << 17]; long long mn(int i, int j) { int p = 31 - __builtin_clz(j - i); return min(vec3[p][i], vec3[p][j - (1 << p)]); } void mn_init(int n) { int mp = 31 - __builtin_clz(n); for (int p = 0; p < mp; ++p) for (int x = 0; x < n - (1 << p); ++x) vec3[p + 1][x] = min(vec3[p][x], vec3[p][x + (1 << p)]); } long long vec2[17][1 << 17]; long long mx(int i, int j) { int p = 31 - __builtin_clz(j - i); return max(vec2[p][i], vec2[p][j - (1 << p)]); } void mx_init(int n) { int mp = 31 - __builtin_clz(n); for (int p = 0; p < mp; ++p) for (int x = 0; x < n - (1 << p); ++x) vec2[p + 1][x] = max(vec2[p][x], vec2[p][x + (1 << p)]); } int izq[100010]; struct rmq { int MAX; long long vec[4 * 100000]; long long* init(int n) { MAX = 1 << (32 - __builtin_clz(n)); fill(vec, vec + 2 * MAX, 0); return vec + MAX; } void updall() { for (int i = MAX - 1; i >= 0; --i) vec[i] = min(vec[2 * i], vec[2 * i + 1]); } void pset(int i, long long vl) { vec[i += MAX] = vl; while (i) { i /= 2; vec[i] = min(vec[2 * i], vec[2 * i + 1]); } } long long pget(int i, int j) { return _pget(i + MAX, j + MAX); } long long _pget(int i, int j) { long long res = 100000000; if (j - i <= 0) return res; if (i % 2) res = min(res, vec[i++]); res = min(res, _pget(i / 2, j / 2)); if (j % 2) res = min(res, vec[--j]); return res; } }; rmq DP; int main() { long long n, s, l; cin >> n >> s >> l; for (int i = 0; i < n; i++) { cin >> vec3[0][i]; vec2[0][i] = vec3[0][i]; } mn_init(n); mx_init(n); for (int i = 1; i < n; i++) { if (mn(0, i) < vec3[0][i] - s) { int bot = 0, top = i; while (top - bot > 1) { int mid = (top + bot) / 2; if (mn(mid, i) < vec3[0][i] - s) bot = mid; else top = mid; } izq[i] = max(izq[i], top); } if (mx(0, i) > vec3[0][i] + s) { int bot = 0, top = i; while (top - bot > 1) { int mid = (top + bot) / 2; if (mx(mid, i) > vec3[0][i] + s) bot = mid; else top = mid; } izq[i] = max(izq[i], top); } } for (int i = 1; i < n; i++) izq[i] = max(izq[i], izq[i - 1]); for (int i = 0; i < n; ++i) izq[i]--; long long* v = DP.init(n); for (int i = 0; i < n; ++i) v[i] = 100000000; DP.updall(); for (int i = 0; i < n; ++i) { if (izq[i] == -1 && i >= l - 1) DP.pset(i, 1); else { DP.pset(i, DP.pget(izq[i], i - l + 1) + 1); } } if (DP.pget(n - 1, n) <= n) cout << DP.pget(n - 1, n) << endl; else cout << -1 << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000005; int N, M, dp[MAXN], res = 0; vector<pair<int, int>> adj[MAXN]; int check(int v) { if (dp[v]) return dp[v]; dp[v] = 1; for (auto p : adj[v]) { int n = p.first; if (check(n) + 1 > dp[v]) { dp[v] = dp[n] + 1; res = max(res, p.second); } } return dp[v]; } int main() { scanf( %d%d , &N, &M); for (int i = 0; i < M; i++) { int a, b; scanf( %d%d , &a, &b); a -= 1, b -= 1; adj[a].push_back({b, i + 1}); } for (int i = 0; i < N; i++) { if (check(i) == N) { printf( %d , res); return 0; } } printf( -1 ); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> const long long INF = 1e17, N = 2e5 + 1; using namespace std; int a[N], n, m, k, sum[N], t[N]; int getime(int idx) { return min(idx, n - idx + 1); } int getlen(int l, int r) { if (l > r) swap(l, r); int tmp = (r - l) / m; if ((r - l) % m != 0) tmp++; return tmp; } int f(int tmp) { for (int i = 1; i <= n; i++) { sum[i] = 0; } for (int i = 1; i <= n; i++) { a[i] = t[i]; } int idx = 1; for (int i = (n / 2) - tmp + 1; i <= ((n + 1) / 2) + tmp; i++) { while (sum[i] != k && idx <= n) { if (a[idx] == 0 || getlen(idx, i) > getime(i)) { idx++; } else { int tmp = min(k - sum[i], a[idx]); a[idx] -= tmp; sum[i] += tmp; } } if (sum[i] != k) { return 0; } } return 1; } int main() { cin >> n >> m >> k; for (int i = 1; i <= n; i++) { cin >> t[i]; } int l = 0, r = n / 2; while (l != r) { int mid = (l + r + 1) >> 1; if (f(mid)) { l = mid; } else { r = mid - 1; } } cout << (n / 2) - l; } |
//--------------------------------------------------------------------------------
// receiver.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Receives commands from the serial port. The first byte is the commands
// opcode, the following (optional) four byte are the command data.
// Commands that do not have the highest bit in their opcode set are
// considered short commands without data (1 byte long). All other commands are
// long commands which are 5 bytes long.
//
// After a full command has been received it will be kept available for 10 cycles
// on the op and data outputs. A valid command can be detected by checking if the
// execute output is set. After 10 cycles the registers will be cleared
// automatically and the receiver waits for new data from the serial port.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module receiver #(
parameter [31:0] FREQ = 100000000,
parameter [31:0] RATE = 115200,
parameter BITLENGTH = FREQ / RATE // 100M / 115200 ~= 868
)(
input wire clock,
input wire trxClock,
input wire reset,
input wire rx,
output wire [7:0] op,
output wire [31:0] data,
output reg execute
);
localparam [2:0]
INIT = 3'h0,
WAITSTOP = 3'h1,
WAITSTART = 3'h2,
WAITBEGIN = 3'h3,
READBYTE = 3'h4,
ANALYZE = 3'h5,
READY = 3'h6;
reg [9:0] counter, next_counter; // clock prescaling counter
reg [3:0] bitcount, next_bitcount; // count rxed bits of current byte
reg [2:0] bytecount, next_bytecount; // count rxed bytes of current command
reg [2:0] state, next_state; // receiver state
reg [7:0] opcode, next_opcode; // opcode byte
reg [31:0] databuf, next_databuf; // data dword
reg next_execute;
assign op = opcode;
assign data = databuf;
always @(posedge clock, posedge reset)
if (reset) state <= INIT;
else state <= next_state;
always @(posedge clock)
begin
counter <= next_counter;
bitcount <= next_bitcount;
bytecount <= next_bytecount;
databuf <= next_databuf;
opcode <= next_opcode;
execute <= next_execute;
end
always
begin
next_state = state;
next_counter = counter;
next_bitcount = bitcount;
next_bytecount = bytecount;
next_opcode = opcode;
next_databuf = databuf;
next_execute = 1'b0;
case(state)
INIT :
begin
next_counter = 0;
next_bitcount = 0;
next_bytecount = 0;
next_opcode = 0;
next_databuf = 0;
next_state = WAITSTOP;
end
WAITSTOP : // reset uart
begin
if (rx) next_state = WAITSTART;
end
WAITSTART : // wait for start bit
begin
if (!rx) next_state = WAITBEGIN;
end
WAITBEGIN : // wait for first half of start bit
begin
if (counter == (BITLENGTH / 2))
begin
next_counter = 0;
next_state = READBYTE;
end
else if (trxClock)
next_counter = counter + 1;
end
READBYTE : // receive byte
begin
if (counter == BITLENGTH)
begin
next_counter = 0;
next_bitcount = bitcount + 1;
if (bitcount == 4'h8)
begin
next_bytecount = bytecount + 1;
next_state = ANALYZE;
end
else if (bytecount == 0)
begin
next_opcode = {rx,opcode[7:1]};
next_databuf = databuf;
end
else
begin
next_opcode = opcode;
next_databuf = {rx,databuf[31:1]};
end
end
else if (trxClock)
next_counter = counter + 1;
end
ANALYZE : // check if long or short command has been fully received
begin
next_counter = 0;
next_bitcount = 0;
if (bytecount == 3'h5) // long command when 5 bytes have been received
next_state = READY;
else if (!opcode[7]) // short command when set flag not set
next_state = READY;
else next_state = WAITSTOP; // otherwise continue receiving
end
READY : // done, give 10 cycles for processing
begin
next_counter = counter + 1;
if (counter == 4'd10)
next_state = INIT;
else next_state = state;
end
endcase
next_execute = (next_state == READY);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string second[100]; int x[100], y[100]; vector<int> a, b; bool u[100][100]; bool uu[100][100]; bool ux[100], uy[100]; int n, m; void dfs(int x, int y) { ux[x] = uy[y] = true; u[x][y] = true; for (int i = 0; i < n; i++) if (second[i][y] == # && !u[i][y]) dfs(i, y); for (int j = 0; j < m; j++) if (second[x][j] == # && !u[x][j]) dfs(x, j); } int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> second[i]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (second[i][j] == # && !u[i][j]) { for (int i = 0; i < n; i++) ux[i] = false; for (int i = 0; i < m; i++) uy[i] = false; dfs(i, j); a.clear(); b.clear(); for (int i = 0; i < n; i++) if (ux[i]) a.push_back(i); for (int j = 0; j < m; j++) if (uy[j]) b.push_back(j); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) uu[i][j] = false; for (int i = 0; i < a.size(); i++) for (int j = 0; j < b.size(); j++) { uu[a[i]][b[j]] = true; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (ux[i] && second[i][j] == # && !uu[i][j]) { cout << No ; return 0; } if (second[i][j] == . && uu[i][j]) { cout << No ; return 0; } } } cout << Yes ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 555; long long saveori[maxn]; long long savepos[maxn]; long long tree[maxn << 2]; void update(long long nowid, long long l, long long r, long long pos, long long v) { if (l == r) { tree[nowid] = v; return; } if (pos <= ((l + r) >> 1)) update((nowid << 1), l, ((l + r) >> 1), pos, v); if (((l + r) >> 1) < pos) update(((nowid << 1) | 1), ((l + r) >> 1) + 1, r, pos, v); tree[nowid] = tree[(nowid << 1)] + tree[((nowid << 1) | 1)]; } long long query(long long nowid, long long l, long long r, long long ql, long long qr) { if (ql <= l && r <= qr) return tree[nowid]; long long res = 0; if (ql <= ((l + r) >> 1)) res += query((nowid << 1), l, ((l + r) >> 1), ql, qr); if (((l + r) >> 1) < qr) res += query(((nowid << 1) | 1), ((l + r) >> 1) + 1, r, ql, qr); return res; } long long tree1[maxn << 2]; void update1(long long nowid, long long l, long long r, long long pos, long long v) { if (l == r) { tree1[nowid] = v; return; } if (pos <= ((l + r) >> 1)) update1((nowid << 1), l, ((l + r) >> 1), pos, v); if (((l + r) >> 1) < pos) update1(((nowid << 1) | 1), ((l + r) >> 1) + 1, r, pos, v); tree1[nowid] = tree1[(nowid << 1)] + tree1[((nowid << 1) | 1)]; } long long query1(long long nowid, long long l, long long r, long long ql, long long qr) { if (ql <= l && r <= qr) return tree1[nowid]; long long res = 0; if (ql <= ((l + r) >> 1)) res += query1((nowid << 1), l, ((l + r) >> 1), ql, qr); if (((l + r) >> 1) < qr) res += query1(((nowid << 1) | 1), ((l + r) >> 1) + 1, r, ql, qr); return res; } long long n; long long getpos(long long k) { long long cnt = (k + 1) / 2; long long l = 1, r = n; long long pos = 0; while (l <= r) { long long now = query(1, 1, n, 1, ((l + r) >> 1)); now = ((l + r) >> 1) - now; if (cnt <= now) { pos = ((l + r) >> 1); r = ((l + r) >> 1) - 1; } else l = ((l + r) >> 1) + 1; } return pos; } inline long long cal1(long long a1, long long n) { return n * (n - 1) / 2; } void solve() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) { scanf( %lld , &saveori[i]); savepos[saveori[i]] = i; } vector<long long> ans; ans.push_back(0); long long l = savepos[1]; long long r = savepos[1]; for (long long i = 2; i <= n; i++) { update(1, 1, n, savepos[i], 1); update1(1, 1, n, savepos[i], savepos[i]); } long long last = 0; for (long long i = 2; i <= n; i++) { update(1, 1, n, savepos[i], 0); update1(1, 1, n, savepos[i], 0); l = min(l, savepos[i]); r = max(r, savepos[i]); long long pos = getpos(i); long long cnt = query(1, 1, n, l, pos); long long sum = query1(1, 1, n, l, pos) - cnt * l - cal1(0, cnt); cnt = query(1, 1, n, pos + 1, r); sum += (cnt * n - query1(1, 1, n, pos, r)) - cal1(0, cnt) - (n - r) * cnt; last += i - (savepos[i] - query(1, 1, n, 1, savepos[i])); ans.push_back(last + sum); } for (long long aa : ans) printf( %lld n , aa); } signed main() { solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A22O_PP_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, n, lns, t = 0, pos = -1, posl = 0; string s, ot; cin >> s; lns = s.length(); ot.clear(); for (i = 0; i < lns; ++i) { if (s[i] == a ) t++; else posl++; } if (t == lns) { cout << s; return 0; } if (posl & 1) { cout << :( ; return 0; } t = 0; for (i = 0; i < lns; ++i) { if (s[i] != a ) t++; if (t * 2 > posl) { pos = i; break; } } for (i = pos; i < lns; ++i) { if (s[i] == a ) { cout << :( ; return 0; } } i = 0; t = pos; while (i < pos) { if (s[i] == a ) i++; else if (s[i] != s[t]) { cout << :( ; return 0; } else i++, t++; } for (i = 0; i < pos; ++i) { cout << s[i]; } cout << ot; return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = 3.141592653589793; const int INF = 2000000000; const int mod = 1000000007; const int N = 100000000; const int base = 10; vector<int> read(string s) { vector<int> a; for (int i = (int)s.length(); i > 0; i -= 1) if (i < 1) a.push_back(atoi(s.substr(0, i).c_str())); else a.push_back(atoi(s.substr(i - 1, 1).c_str())); return a; } vector<int> add(vector<int> a, vector<int> b) { int carry = 0; for (size_t i = 0; i < max(a.size(), b.size()) || carry; ++i) { if (i == a.size()) a.push_back(0); a[i] += carry + (i < b.size() ? b[i] : 0); carry = a[i] >= base; if (carry) a[i] -= base; } return a; } vector<int> mul(vector<int> a, int b) { int carry = 0; for (size_t i = 0; i < a.size() || carry; ++i) { if (i == a.size()) a.push_back(0); long long cur = carry + a[i] * 1ll * b; a[i] = int(cur % base); carry = int(cur / base); } while (a.size() > 1 && a.back() == 0) a.pop_back(); return a; } vector<int> c; vector<int> a[100005], b[100005]; vector<bool> f; vector<bool> f1; int main() { vector<int> queue; int n, x, y, m; cin >> n >> m; for (int(i) = (0); (i) < (n); (i)++) { cin >> x; c.push_back(x); } for (int(i) = (0); (i) < (m); (i)++) { cin >> x >> y; x--; y--; a[x].push_back(y); b[y].push_back(x); } for (int(i) = (0); (i) < (c.size()); (i)++) if (c[i] == 1) { queue.push_back(i); f.push_back(true); } else { f.push_back(false); } for (int(i) = (0); (i) < (queue.size()); (i)++) { for (int(j) = (0); (j) < (a[queue[i]].size()); (j)++) { if (f[a[queue[i]][j]]) continue; queue.push_back(a[queue[i]][j]); f[a[queue[i]][j]] = true; } } queue.clear(); for (int(i) = (0); (i) < (c.size()); (i)++) if (c[i] == 2) { queue.push_back(i); f1.push_back(true); } else { f1.push_back(false); } for (int(i) = (0); (i) < (queue.size()); (i)++) { for (int(j) = (0); (j) < (b[queue[i]].size()); (j)++) { if (f1[b[queue[i]][j]]) continue; f1[b[queue[i]][j]] = true; if (c[b[queue[i]][j]] == 1) continue; queue.push_back(b[queue[i]][j]); } } for (int(i) = (0); (i) < (n); (i)++) if (f[i] && f1[i]) { cout << 1 << endl; } else { cout << 0 << endl; } return 0; } |
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