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#include <bits/stdc++.h> using namespace std; int find(int u[], int i) { if (u[i] == i) { return i; } return (u[i] = find(u, u[i])); } int main() { int n, m; cin >> n >> m; if (n != m + 1) { cout << no << endl; return 0; } int ufs[n]; for (int i = 0; i < n; i++) { ufs[i] = i; } int a, b; for (int i = 0; i < m; i++) { cin >> a >> b; int c = find(ufs, a - 1); int d = find(ufs, b - 1); if (c == d) { cout << no << endl; return 0; } int m = min(c, d); ufs[c] = m; ufs[d] = m; } for (int i = 0; i < n; i++) { if (find(ufs, i) != 0) { cout << no << endl; return 0; } } cout << yes << endl; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_inv_r90_256x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_gclk_inv_r90_256x.behV
// --------------------------------------------------
//
module bw_clk_gclk_inv_r90_256x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, q, acum = 0, ultimo = 0, type, a, count; scanf( %d%d , &n, &q); vector<queue<int>> notificaciones_app(n); unordered_set<int> todas_notificaciones; while (q--) { scanf( %d%d , &type, &a); a--; switch (type) { case 1: acum++; todas_notificaciones.insert(acum); notificaciones_app[a].push(acum); break; case 2: while (!notificaciones_app[a].empty()) todas_notificaciones.erase(notificaciones_app[a].front()), notificaciones_app[a].pop(); break; case 3: a++; for (int i = ultimo; i <= a; i++) todas_notificaciones.erase(i); if (a > ultimo) ultimo = a; break; } printf( %d n , todas_notificaciones.size()); } return 0; } |
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//! The USRP digital down-conversion chain
module ddc_chain
#(
parameter BASE = 0,
parameter DSPNO = 0,
parameter WIDTH = 24
)
(input clk, input rst, input clr,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
// From RX frontend
input [WIDTH-1:0] rx_fe_i,
input [WIDTH-1:0] rx_fe_q,
// To RX control
output [31:0] sample,
input run,
output strobe,
output [31:0] debug
);
localparam cwidth = 25;
localparam zwidth = 24;
wire ddc_enb;
wire [31:0] phase_inc;
reg [31:0] phase;
wire [17:0] scale_factor;
wire [cwidth-1:0] i_cordic, q_cordic;
wire [WIDTH-1:0] i_cordic_clip, q_cordic_clip;
wire [WIDTH-1:0] i_cic, q_cic;
wire [WIDTH-1:0] i_hb1, q_hb1;
wire [WIDTH-1:0] i_hb2, q_hb2;
wire strobe_cic, strobe_hb1, strobe_hb2;
wire enable_hb1, enable_hb2;
wire [7:0] cic_decim_rate;
reg [WIDTH-1:0] rx_fe_i_mux, rx_fe_q_mux;
wire realmode;
wire swap_iq;
setting_reg #(.my_addr(BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(scale_factor),.changed());
setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({realmode,swap_iq}),.changed());
// MUX so we can do realmode signals on either input
always @(posedge clk)
if(swap_iq)
begin
rx_fe_i_mux <= rx_fe_q;
rx_fe_q_mux <= realmode ? 0 : rx_fe_i;
end
else
begin
rx_fe_i_mux <= rx_fe_i;
rx_fe_q_mux <= realmode ? 0 : rx_fe_q;
end
// NCO
always @(posedge clk)
if(rst)
phase <= 0;
else if(~ddc_enb)
phase <= 0;
else
phase <= phase + phase_inc;
//sign extension of cordic input
wire [WIDTH-1:0] to_ddc_chain_i, to_ddc_chain_q;
wire [cwidth-1:0] to_cordic_i, to_cordic_q;
sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(to_ddc_chain_i), .out(to_cordic_i));
sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(to_ddc_chain_q), .out(to_cordic_q));
// CORDIC 24-bit I/O
cordic_z24 #(.bitwidth(cwidth))
cordic(.clock(clk), .reset(rst), .enable(ddc_enb),
.xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
.xo(i_cordic),.yo(q_cordic),.zo() );
clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_i
(.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip));
clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_q
(.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip));
// CIC decimator 24 bit I/O
cic_strober cic_strober(.clock(clk),.reset(rst),.enable(ddc_enb),.rate(cic_decim_rate),
.strobe_fast(1),.strobe_slow(strobe_cic) );
cic_decim #(.bw(WIDTH))
decim_i (.clock(clk),.reset(rst),.enable(ddc_enb),
.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
.signal_in(i_cordic_clip),.signal_out(i_cic));
cic_decim #(.bw(WIDTH))
decim_q (.clock(clk),.reset(rst),.enable(ddc_enb),
.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
.signal_in(q_cordic_clip),.signal_out(q_cic));
// First (small) halfband 24 bit I/O
small_hb_dec #(.WIDTH(WIDTH)) small_hb_i
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(ddc_enb),
.stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1));
small_hb_dec #(.WIDTH(WIDTH)) small_hb_q
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(ddc_enb),
.stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1));
// Second (large) halfband 24 bit I/O
wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
hb_dec #(.WIDTH(WIDTH)) hb_i
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(ddc_enb),.cpi(cpi_hb),
.stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
hb_dec #(.WIDTH(WIDTH)) hb_q
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(ddc_enb),.cpi(cpi_hb),
.stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
//scalar operation (gain of 6 bits)
wire [35:0] prod_i, prod_q;
MULT18X18S mult_i
(.P(prod_i), .A(i_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
MULT18X18S mult_q
(.P(prod_q), .A(q_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
//pipeline for the multiplier (gain of 10 bits)
reg [WIDTH-1:0] prod_reg_i, prod_reg_q;
reg strobe_mult;
always @(posedge clk) begin
strobe_mult <= strobe_hb2;
prod_reg_i <= prod_i[33:34-WIDTH];
prod_reg_q <= prod_q[33:34-WIDTH];
end
// Round final answer to 16 bits
wire [31:0] ddc_chain_out;
wire ddc_chain_stb;
round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_i
(.clk(clk),.reset(rst), .in(prod_reg_i),.strobe_in(strobe_mult), .out(ddc_chain_out[31:16]), .strobe_out(ddc_chain_stb));
round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_q
(.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strobe_out());
dsp_rx_glue #(.DSPNO(DSPNO), .WIDTH(WIDTH)) custom(
.clock(clk), .reset(rst), .clear(clr), .enable(run),
.set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
.frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux),
.ddc_in_i(to_ddc_chain_i), .ddc_in_q(to_ddc_chain_q),
.ddc_out_sample(ddc_chain_out), .ddc_out_strobe(ddc_chain_stb), .ddc_out_enable(ddc_enb),
.bb_sample(sample), .bb_strobe(strobe));
assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
endmodule // ddc_chain
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM_B.v when simulating
// the core, RAM_B. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM_B(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("kintex7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("kintex7")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O22A_PP_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[100]; long long ans; long long getval() { long long val = 0; for (int i = 0; i < n; ++i) { int mn = 100500; for (int j = i; j < n; ++j) { mn = min(mn, a[j]); val += mn; } } return val; } int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < n; ++i) { a[i] = i + 1; } do { long long val = getval(); ans = max(ans, val); } while (next_permutation(a, a + n)); cerr << ans = << ans << n ; do { long long val = getval(); if (val == ans) { if (m == 1) { for (int i = 0; i < n; ++i) { cout << a[i] << ; } cout << n ; return 0; } --m; } } while (next_permutation(a, a + n)); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_FUNCTIONAL_PP_V |
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, m, flag = 0; cin >> n >> m; long long int a[n][m], b[n][m]; for (long long int(i) = 0; (i) < (n); ++(i)) { for (long long int(j) = 0; (j) < (m); ++(j)) { cin >> a[i][j]; } } for (long long int(i) = 0; (i) < (n); ++(i)) { for (long long int(j) = 0; (j) < (m); ++(j)) { cin >> b[i][j]; } } for (long long int(i) = 0; (i) < (n); ++(i)) { for (long long int(j) = 0; (j) < (m); ++(j)) { if (a[i][j] > b[i][j]) swap(a[i][j], b[i][j]); } } for (long long int(i) = 0; (i) < (n); ++(i)) { for (long long int(j) = 0; (j) < (m - 1); ++(j)) { if (a[i][j] >= a[i][j + 1]) { flag = 1; } } } for (long long int(j) = 0; (j) < (m); ++(j)) { for (long long int(i) = 0; (i) < (n - 1); ++(i)) { if (a[i][j] >= a[i + 1][j]) { flag = 1; } } } for (long long int(i) = 0; (i) < (n); ++(i)) { for (long long int(j) = 0; (j) < (m - 1); ++(j)) { if (b[i][j] >= b[i][j + 1]) { flag = 1; } } } for (long long int(j) = 0; (j) < (m); ++(j)) { for (long long int(i) = 0; (i) < (n - 1); ++(i)) { if (b[i][j] >= b[i + 1][j]) { flag = 1; } } } if (flag == 0) cout << Possible ; else cout << Impossible ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename _T, typename _T2> string to_string(pair<_T, _T2> x) { return < + to_string(x.first) + , + to_string(x.second) + > ; } template <typename _T> string to_string(vector<_T> vec) { string s = [ ; for (auto el : vec) s += to_string(el) + , ; s[s.size() - 1] = ] ; s[s.size() - 2] = ; return s; } template <typename _T> string to_string(set<_T> vec) { string s = { ; for (auto el : vec) s += to_string(el) + , ; s[s.size() - 1] = } ; s[s.size() - 2] = ; return s; } template <typename _T, typename _T2> string to_string(map<_T, _T2> vec) { string s = { ; for (auto el : vec) s += mp[ + to_string(el.first) + ]= + to_string(el.second) + , ; s[s.size() - 1] = } ; s[s.size() - 2] = ; return s; } template <typename _T> inline void _DBG(const char *s, _T x) { cerr << s << = << to_string(x) << n ; } template <typename _T, typename... args> void _DBG(const char *s, _T x, args... a) { while (*s != , ) cerr << *s++; cerr << = << to_string(x) << n ; _DBG(s + 1, a...); } mt19937 rng___(chrono::steady_clock::now().time_since_epoch().count()); const long long MOD = 998244353; const long long LLINF = 1e18 + 7; const int N = 2e5 + 8; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); ; int t; cin >> t; while (t--) { int n[3], len; cin >> n[0] >> n[1] >> n[2]; len = n[0] + n[1] + n[2] + 1; string ans; if (n[0] > 0) { ans += string(n[0] + 1, 0 ); if (n[2] > 0) { n[1]--; ans += string(n[2] + 1, 1 ); } while (n[1]--) { if (ans.back() == 1 ) ans += 0 ; else ans += 1 ; } cout << ans << n ; } else { ans += string(n[2] + 1, 1 ); while (n[1]--) { if (ans.back() == 1 ) ans += 0 ; else ans += 1 ; } cout << ans << n ; } } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, a, b, x, l, m, e, d, s; cin >> t; while (t--) { cin >> n >> x >> a >> b; if (a > b) { l = a; s = b; } else { l = b; s = a; } d = n - l; if (x <= d) { cout << l + x - s << n ; continue; } else m = x - d; e = s - 1; if (m >= e) { cout << n - 1 << n ; continue; } else { s = s - m; cout << n - s << n ; } } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const double eps = 1e-50; const int maxN = 1100; const double inf = 1e50; int n, m; vector<int> a[maxN]; double d[maxN][maxN]; int b[maxN]; double c[maxN][maxN]; bool have[maxN]; double t[maxN][maxN], s[maxN]; int main() { for (int i = 0; i < maxN; ++i) { c[i][0] = 1; for (int j = 1; j <= i; ++j) { c[i][j] = c[i - 1][j - 1] + c[i - 1][j]; if (c[i][j] >= inf) { c[i][j] = inf; } } } cin >> n >> m; vector<pair<int, int> > x; for (int i = 0; i < m; ++i) { int k; cin >> k; a[i].resize(k); for (int j = 0; j < k; ++j) { cin >> a[i][j]; x.push_back(make_pair(a[i][j], i)); } } sort(x.rbegin(), x.rend()); for (int i = 0; i < n; ++i) { if (x[i].first != x[n - 1].first) { ++b[x[i].second]; } } int needed = x[n - 1].first; for (int i = 0; i < m; ++i) { for (int j = 0; j < a[i].size(); ++j) { if (a[i][j] == needed) { have[i] = true; } } } d[0][0] = 1.0; t[0][0] = 1.0; for (int i = 0; i < m; ++i) { for (int j = 0; j <= n; ++j) { if (d[i][j] < eps) { d[i][j] = 0.0; } if (t[i][j] > inf) { t[i][j] = inf; } int cnt = b[i]; if (j + cnt <= n) { d[i + 1][j + cnt] += d[i][j] / c[a[i].size()][cnt]; t[i + 1][j + cnt] += t[i][j]; } if (have[i] && j + cnt + 1 <= n) { d[i + 1][j + cnt + 1] += d[i][j] / c[a[i].size()][cnt + 1]; t[i + 1][j + cnt + 1] += t[i][j]; } } } t[0][0] = 1.0; for (int i = 0; i <= n; ++i) { s[i] = t[0][i]; if (i > 0) { s[i] += s[i - 1]; } } printf( %.10lf n , d[m][n] / t[m][n]); return 0; } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) #pragma comment(linker, /STACK:336777216 ) using namespace std; int IT_MAX = 1 << 17; int MOD = 1000000007; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const double PI = acos(-1); const double ERR = 1e-10; long long dp[1050][10050]; long long C[10050]; long long cost[10050]; int main() { int N, W, B, X, i, j, k; scanf( %d %d %d %d , &N, &W, &B, &X); for (i = 1; i <= N; i++) scanf( %lld , &C[i]); for (i = 1; i <= N; i++) scanf( %lld , &cost[i]); for (i = 0; i <= N; i++) for (j = 0; j <= 10000; j++) dp[i][j] = -LL_INF; dp[0][0] = W; for (i = 1; i <= N; i++) { for (j = 0; j <= 10000; j++) { long long v = dp[i - 1][j]; if (v < 0) continue; long long mx = C[i]; if (cost[i]) mx = min(mx, v / cost[i]); for (k = 0; k <= mx; k++) dp[i][j + k] = max(dp[i][j + k], dp[i - 1][j] - cost[i] * k); } for (j = 0; j <= 10000; j++) if (dp[i][j] >= 0) dp[i][j] = min(dp[i][j] + X, (long long)B * j + W); } int ans = 0; for (i = 1; i <= 10000; i++) if (dp[N][i] >= 0) ans = max(ans, i); return !printf( %d n , ans); } |
module spi_controller(
//CLK
input clk,
//RST
input RST_N,
//IRQ to AXI master
output o_IRQ,
//Signals towards AXI interface:
input wire [31:0] i_data_to_registers,
input wire i_wr_controll_reg, // Offset: 0x00
input wire i_wr_data_reg, // Offset: 0x08
input wire i_read_status_reg,
output wire [31:0] o_controll_reg,
output wire [31:0] o_status_reg,
output wire [31:0] o_data_reg,
//SPI interface
input i_miso,
output o_mosi,
output o_sclk
);
///////////////////////////////////////////////////////////////////////////////
// Signal declaration:
// The registers of rhis SPI peripheral.
reg [31:0] q_controll_reg;
wire [31:0] w_status_reg;
reg [7:0] q_data_reg;
// clock and reset:
// SPI controller resister:
reg [7:0] q_spi_bit_cntr;
//Do not use in first implementation. This is a future feature...
reg [2:0] q_spi_byte_cntr;
//IRQ flag
reg q_irq_flag;
//collision flag
reg q_collision_flag;
reg [7:0] q_spi_mosi_shr;
reg [7:0] q_spi_miso_shr;
wire w_setup_spi_data;
wire w_sample_spi_data;
wire w_active_spi_transaction;
wire w_sclk_reset;
wire w_reset;
wire w_dword;
wire w_cpol;
wire w_cpha;
wire w_spr1;
wire w_spr0;
// Concurrent assignments.
assign o_controll_reg = q_controll_reg;
assign o_status_reg = w_status_reg;
assign o_data_reg = q_spi_miso_shr;
assign w_reset = ~RST_N;
assign w_irq_en = q_controll_reg[7];
assign w_spie = q_controll_reg[6];
assign w_dword = q_controll_reg[5];
// assign w_spie = q_controll_reg[4];
assign w_cpol = q_controll_reg[3];
assign w_cpha = q_controll_reg[2];
assign w_spr1 = q_controll_reg[1];
assign w_spr0 = q_controll_reg[0];
assign w_sclk_reset = w_reset | ~w_active_spi_transaction;
// Instance of the Clock generator
spi_clock_generator spi_clock_generator_inst(
//CLK
// i_clk is the system clock (10-200MHz)
.i_clk(clk),
//RST
// i_reset is the system reset. This is a active high signal.
// '1' : reset is active
.i_reset(w_sclk_reset),
//Controll inputs from registers
.i_spr0(w_spr0),
.i_spr1(w_spr1),
.i_cpol(w_cpol),
.i_cpha(w_cpha),
.i_mstr(1'b1),
// Controll output to other logic
// o_sclk: This is the SPI clock. The polarity based on the i_cpol
// The frequency is derived by i_spr0 and i_spr1
.o_sclk(o_sclk),
// o_sclk_rising_edge: is active one sys clk long at the rising edge of
// the sclk.
.o_sclk_rising_edge(),
// o_sclk_falling_edge: is active one sys clk long at the falling edge of
// the sclk.
.o_sclk_falling_edge(),
// o_sample_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
.o_sample_spi_data(w_sample_spi_data),
// o_setup_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
// Note that this is the alter edge than o_sample_spi_data
.o_setup_spi_data(w_setup_spi_data)
);
///////////////////////////////////////////////////////////////////////////
// The internal register interface. The following blocks drive all internal
// registers.
// Status register:
assign w_status_reg = {q_irq_flag, q_collision_flag, 6'b0};
// control register
always @(posedge clk) begin
if(w_reset)
q_controll_reg <= '0;
if(i_wr_controll_reg) begin
q_controll_reg <= i_data_to_registers;
end
end
//data register
always @(posedge clk) begin
if (w_reset)
q_data_reg <= '0;
else if(i_wr_data_reg) begin
q_data_reg <= i_data_to_registers;
end
if(w_active_spi_transaction) begin
if(w_setup_spi_data) begin
if(w_dword) begin
q_data_reg <= {1'b0, q_data_reg[7:1]};
end else begin
q_data_reg <= {q_data_reg[6:0], 1'b0};
end
end
end
// else begin
// q_data_reg <= q_spi_miso_shr;
// end
end
///////////////////////////////////////////////////////////////////////////
// SPI controller blocks:
// bit_counter
always @(posedge clk) begin
if(w_reset) begin
q_spi_bit_cntr <= 8;
end else begin
if (i_wr_data_reg) begin
q_spi_bit_cntr <= 0;
end else begin
if(w_setup_spi_data) begin
if(w_active_spi_transaction)
q_spi_bit_cntr <= q_spi_bit_cntr + 1;
end
end
end
end
assign w_active_spi_transaction = q_spi_bit_cntr <8;
//interrupt flag
always @(posedge clk) begin
if (w_reset)
q_irq_flag <= 1'b0;
else if(q_spi_bit_cntr == 7 && w_sample_spi_data) begin
q_irq_flag <= 1'b1;
end else begin
if(i_read_status_reg)
q_irq_flag <= 1'b0;
end
end
assign o_IRQ = q_irq_flag;
//collision flag
always @(posedge clk) begin
if(w_reset) begin
q_collision_flag <= 1'b0;
end else begin
if(w_active_spi_transaction) begin
if(i_wr_controll_reg | i_wr_data_reg)
q_collision_flag <= 1'b1;
end else begin
if(i_read_status_reg)
q_collision_flag <= 1'b0;
end
end
end
//miso shr
always @(posedge clk) begin
if(w_sample_spi_data) begin
if(w_dword) begin
q_spi_miso_shr <= {i_miso, q_spi_miso_shr[7:1]};
end else begin
q_spi_miso_shr <= {q_spi_miso_shr[6:0], i_miso};
end
end
end
assign o_mosi = w_dword ? (q_data_reg[0]) : q_data_reg[7];
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << n + n / 2; return 0; } |
#include <bits/stdc++.h> using namespace std; bool b[31]; struct trie { trie* nt[2]; int tot; trie() { nt[0] = nt[1] = NULL; tot = 0; } }; trie* root = new trie(); void insert(trie* cur, int idx) { if (idx == -1) return; else { int x = b[idx]; if (cur->nt[x] == NULL) cur->nt[x] = new trie(); cur->nt[x]->tot++; insert(cur->nt[x], idx - 1); } } void del(trie* cur, int idx) { if (idx == -1) return; else { int x = b[idx]; del(cur->nt[x], idx - 1); cur->nt[x]->tot--; if (cur->nt[x]->tot == 0) cur->nt[x] = NULL; } } int query(trie* cur, int idx) { if (idx == -1) return 0; else { int x = 1 - b[idx]; int add = 1 << idx; if (cur->nt[x] == NULL) x = 1 - x, add = 0; return query(cur->nt[x], idx - 1) + add; } } int main() { insert(root, 30); int q; scanf( %d , &q); while (q--) { char s[2]; int x; scanf( %s%d , s, &x); for (int i = 0; i <= 30; i++) { b[i] = x % 2; x /= 2; } if (s[0] == + ) insert(root, 30); else if (s[0] == - ) del(root, 30); else printf( %d n , query(root, 30)); } } |
#include <bits/stdc++.h> using namespace std; struct Node { Node *arr[26]; int state; bool isEnd = false; Node() { for (int i = 0; i < 26; i++) arr[i] = nullptr; isEnd = true; } }; void insert(const string &s, Node *root) { Node *curr = root; for (char c : s) { if (curr->arr[c - a ] == nullptr) curr->arr[c - a ] = new Node(); curr = curr->arr[c - a ]; } curr->isEnd = true; } int find_state(Node *curr, bool leaf = true) { bool winning = false; int cnt = 0; for (int i = 0; i < 26; i++) { if (curr->arr[i] != nullptr) { cnt++; if (find_state(curr->arr[i], leaf) == 0) winning = true; } } if (cnt == 0) winning = leaf; return curr->state = winning ? 1 : 0; } int main() { int n, k; cin >> n >> k; Node *root = new Node(); for (int i = 0; i < n; i++) { string s; cin >> s; insert(s, root); } int st1 = find_state(root, false); if (k == 1) { cout << (st1 == 1 ? First : Second ) << endl; } else { int st2 = find_state(root, true); if (st2 == 1 && st1 == 1) { cout << First << endl; } else if (st2 == 1 && st1 == 0) { cout << Second << endl; } else if (st2 == 0 && st1 == 1) { cout << (k % 2 == 0 ? Second : First ) << endl; } else { cout << Second << endl << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s, a[1000]; int max = 0; scanf( %d%d , &n, &s); int sum = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] > max) max = a[i]; } int flag = 1; for (int i = 0; i < n; i++) { if (a[i] == max && flag) { flag = 0; } else { sum += a[i]; } } if (sum <= s) printf( YES n ); else printf( NO n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int Head[1000010], Next[1000010], Go[1000010], Val[1000010], iscut[1000010], Len[1000010], Dep[1000010], Fa[400010][21], Cnt = 1, n, m, q; int Head2[1000010], Next2[1000010], Go2[1000010], Val2[1000010], Cnt2 = 1; int DFN[1000010], MIN[1000010], ins[1000010], Bel[1000010], vis[1000010], tim = 0, tt = 0; vector<int> S; void addedge(int x, int y) { Go[++Cnt] = y; Next[Cnt] = Head[x]; Head[x] = Cnt; } void addedge2(int x, int y, int v) { Go2[++Cnt2] = y; Next2[Cnt2] = Head2[x]; Head2[x] = Cnt2; Val2[Cnt2] = v; } void Tarjan(int x, int f = 0) { ins[x] = 1; S.push_back(x); DFN[x] = ++tim; MIN[x] = DFN[x]; int las = x; for (int T = Head[x]; T; T = Next[T]) if (Go[T] != f) { if (!DFN[Go[T]]) { Tarjan(Go[T], x); MIN[x] = min(MIN[x], MIN[Go[T]]); if (DFN[x] <= MIN[Go[T]]) { tt++; for (;;) { if (S.back() == las) break; addedge2(tt + n + 1, S.back(), 1); addedge2(S.back(), tt + n + 1, 1); S.pop_back(); } addedge2(x, tt + n + 1, 1); addedge2(tt + n + 1, x, 1); } else las = S.back(); } else if (ins[Go[T]]) MIN[x] = min(MIN[x], DFN[Go[T]]); } ins[x] = 0; } void DFS2(int x, int dep = 1, int len = 0) { vis[x] = 1; Len[x] = len; Dep[x] = dep; for (int T = Head[x]; T; T = Next[T]) if (!vis[Go[T]]) { Fa[Go[T]][0] = x; DFS2(Go[T], dep + 1, len + Val[T]); } } int lca(int x, int y) { if (Dep[x] < Dep[y]) swap(x, y); int det = Dep[x] - Dep[y]; for (int i = 18; i >= 0; i--) if ((det >> i) & 1) x = Fa[x][i]; if (x == y) return x; for (int i = 18; i >= 0; i--) if (Fa[x][i] != Fa[y][i]) x = Fa[x][i], y = Fa[y][i]; return Fa[x][0]; } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= m; i++) { int a, b; scanf( %d%d , &a, &b); addedge(a, b); addedge(b, a); } for (int i = 1; i <= n; i++) if (!DFN[i]) Tarjan(i); memcpy(Head, Head2, sizeof Head); memcpy(Next, Next2, sizeof Next); memcpy(Go, Go2, sizeof Go); memcpy(Val, Val2, sizeof Val); for (int i = 1; i <= n + tt + 1; i++) if (!vis[i]) DFS2(i); for (int i = 1; i <= 20; i++) for (int j = 1; j <= n + tt + 1; j++) Fa[j][i] = Fa[Fa[j][i - 1]][i - 1]; for (int i = 1; i <= q; i++) { int a, b; scanf( %d%d , &a, &b); printf( %d n , (Len[a] + Len[b] - 2 * Len[lca(a, b)]) / 2); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long p, k; long long r[20005]; int i, j; int main() { scanf( %I64d%I64d , &p, &k); while (p) { r[i] = p % (-k); p = p / (-k); while (r[i] < 0) { r[i] = r[i] + k; p++; } i++; } if (i == 0) i++; for (j = 0; j < i; j++) if (r[j] >= k) { printf( -1 n ); return 0; } printf( %d n , i); for (j = 0; j < i; j++) printf(j == i - 1 ? %I64d n : %I64d , r[j]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; n--; int a[n]; for (int i = 0; i < n; ++i) { cin >> a[i]; if (a[i] == 0) --i; } int principi; int b[n]; for (int i = 0; i < n; ++i) { cin >> b[i]; if (b[i] == 0) --i; if (b[i] == a[0]) principi = i; } bool bo = true; for (int i = 1; bo and i < n; ++i) { if (a[i] != b[(principi + i) % n]) bo = false; } if (bo) cout << YES << endl; else cout << NO << endl; } |
#include <bits/stdc++.h> const int mod = 1000000007, hmod = 10000019; int n, a[1000010], p[1000010], f[1000010]; long long sz[1000010]; int g[1000010]; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i), sz[i] = a[i]; for (int i = 2; i <= n; i++) scanf( %d , p + i); for (int i = n; i > 1; i--) sz[p[i]] += sz[i]; for (int i = 1; i <= n; i++) { long long j = sz[1] / gcd(sz[1], sz[i]); if (j <= n) g[j]++; } for (int i = n; i; i--) for (int j = i * 2; j <= n; j += i) g[j] += g[i]; for (int i = n; i >= 1; i--) if (g[i] >= i) { f[i] = 1; for (int j = i * 2; j <= n; j += i) (f[i] += f[j]) %= mod; } printf( %d n , f[1]); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_4_V
`define SKY130_FD_SC_HD__NAND2_4_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_4_V
|
#include <bits/stdc++.h> using namespace std; int n, i; int p[200011]; int aib[200011]; int ord[2][200011]; int ans[200011]; int zrs(int x) { return (x & (x - 1)) ^ x; } void add(int x, int v) { while (x <= n) { aib[x] += v; x += zrs(x); } } int sum(int x) { int ans = 0; while (x > 0) { ans += aib[x]; x -= zrs(x); } return ans; } int cb(int x) { int ans = 0; for (int step = (1 << 19); step > 0; step >>= 1) if (ans + step <= n) if (aib[ans + step] <= x) x -= aib[ans += step]; return ans; } void get_order(int n, int *p, int *ans) { int i; for (i = 1; i <= n; i++) aib[i] = zrs(i); memset(ans, 0, sizeof(ans)); for (i = 1; i <= n; i++) { ans[n - i] = sum(p[i] - 1); add(p[i], -1); } } void get_perm(int n, int *ord, int *ans) { int i, cnt, pos; for (i = 1; i <= n; i++) aib[i] = zrs(i); memset(ans, 0, sizeof(ans)); for (i = 1; i <= n; i++) { cnt = ord[n - i] + 1; pos = cb(cnt - 1) + 1; ans[i] = pos; add(pos, -1); } } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &p[i]), p[i]++; get_order(n, p, ord[0]); for (i = 1; i <= n; i++) scanf( %d , &p[i]), p[i]++; get_order(n, p, ord[1]); for (i = 1; i <= n; i++) ord[0][i] += ord[1][i]; for (i = 1; i <= n; i++) { ord[0][i + 1] += ord[0][i] / (i + 1); ord[0][i] %= i + 1; } get_perm(n, ord[0], ans); for (i = 1; i <= n; i++) printf( %d , ans[i] - 1); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SRDLXTP_FUNCTIONAL_V
/**
* srdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input GATE ;
input SLEEP_B;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
wire kapwr ;
wire vgnd ;
wire vpwr ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, SLEEP_B, kapwr, vgnd, vpwr);
bufif1 bufif10 (Q , buf_Q, vpwr );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int MaxN = 100000; int a[MaxN]; int color[MaxN]; bool f = true; int n; int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> a[i]; sort(a + 1, a + n + 1); reverse(a + 1, a + n + 1); while (n % k) { a[n + 1] = a[n]; n++; } int ans = 0; for (int i = 0; i < n / k; ++i) { ans += (2 * (a[k * i + 1] - 1)); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200010; set<pair<long long, long long> > st; int resp[maxn]; struct island { long long ini, fim; } isl[maxn]; struct event { long long type, val, ini; event() { type = 0, val = 0, ini = 0; } event(long long a, long long b, long long c) { type = a; val = b; ini = c; } } e[2 * maxn]; bool cmp(event a, event b) { if (a.ini == b.ini && a.type == b.type) return a.val < b.val; if (a.ini == b.ini) return a.type < b.type; return a.ini < b.ini; } int main() { int n, m; scanf( %d %d , &n, &m); long long al, bl; int siz = 0; for (int i = 0; i < n; i++) { long long a, b; scanf( %I64d %I64d , &a, &b); if (i != 0) { isl[i - 1].fim = b - al; isl[i - 1].ini = a - bl; int atual = i - 1; e[siz++] = event(1, atual, isl[i - 1].ini); } al = a; bl = b; } for (int i = 0; i < m; i++) { long long q; scanf( %I64d , &q); e[siz++] = event(2, i, q); } sort(e, e + siz, cmp); for (int i = 0; i < siz; i++) { if (e[i].type == 1) { st.insert(make_pair(isl[e[i].val].fim, e[i].val)); } else { set<pair<long long, long long> >::iterator it = st.lower_bound(make_pair(e[i].ini, -1LL)); if (it != st.end()) { resp[it->second] = e[i].val; st.erase(it); } } } int ok = 1; if (!st.empty()) ok = 0; if (ok) { puts( Yes ); for (int i = 0; i < n - 1; i++) { printf( %d , resp[i] + 1); } printf( n ); } else { puts( No ); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 15, maxx = 10; long long a[maxn], b[maxn], c[maxn]; void Init() { for (int i = 1; i <= maxx; i++) { long long x = i, l = 1, r = 0; while (x--) l *= 10, r = r * 10 + 9; l /= 10; a[i] = (r - l + 1) * i; b[i] = b[i - 1] + a[i]; c[i] = c[i - 1] + (b[i - 1] + i + b[i]) * (r - l + 1) / 2; } } int main() { ios::sync_with_stdio(0); Init(); long long t, n, pos; cin >> t; while (t--) { cin >> n; pos = lower_bound(c + 1, c + maxx + 1, n) - c; n = n - c[pos - 1]; long long l = 1, r = 0, x = pos, t = b[pos - 1]; while (x--) l *= 10, r = 10 * r + 9; l /= 10; long long L = l; while (l <= r) { long long mid = (l + r) >> 1; long long cnt = mid - L + 1; if ((2 * t + pos + cnt * pos) * cnt / 2 >= n) r = mid - 1; else l = mid + 1; } long long cnt = l - L; n -= (2 * t + pos + cnt * pos) * cnt / 2; pos = lower_bound(b + 1, b + maxx + 1, n) - b; n -= b[pos - 1]; int ans = 1; for (int i = 1; i < pos; i++) ans *= 10; t = (n - 1) / pos; n -= t * pos; ans += t; n = pos - n; while (n--) ans /= 10; cout << ans % 10 << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_1_V
`define SKY130_FD_SC_HD__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_1_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { int t; cin >> t; while (t--) { string s; cin >> s; vector<int> counts; int current_count = 0; for (char c : s) { if (c == 1 ) { current_count += 1; } else if (current_count != 0) { counts.emplace_back(current_count); current_count = 0; } } if (current_count != 0) { counts.emplace_back(current_count); } sort(counts.begin(), counts.end()); int n = counts.size(); int score = 0; for (int i = 1 - (n % 2); i < n; i += 2) { score += counts[i]; } cout << score << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_2_V
`define SKY130_FD_SC_HS__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_2_V
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// counter-based 'PFD', based on pentagon design, with filter and adopted to
// 28mhz
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
module fapch_counter
(
input wire fclk,
input wire rdat_n,
output reg vg_rclk,
output reg vg_rawr
);
reg [4:0] rdat_sync;
reg rdat_edge1, rdat_edge2;
wire rdat;
wire rwidth_ena;
reg [3:0] rwidth_cnt;
wire rclk_strobe;
reg [5:0] rclk_cnt;
// RCLK/RAWR restore
// currently simplest counter method, no PLL whatsoever now
//
// RCLK period must be 112 clocks (@28 MHz), or 56 clocks for each state
// RAWR on time is 4 clocks
// digital filter - removing glitches
always @(posedge fclk)
rdat_sync[4:0] <= { rdat_sync[3:0], (~rdat_n) };
always @(posedge fclk)
begin
if( rdat_sync[4:1]==4'b1111 ) // filter beginning of strobe
rdat_edge1 <= 1'b1;
else if( rclk_strobe ) // filter any more strobes during same strobe half-perion
rdat_edge1 <= 1'b0;
rdat_edge2 <= rdat_edge1;
end
assign rdat = rdat_edge1 & (~rdat_edge2);
always @(posedge fclk)
if( rwidth_ena )
begin
if( rdat )
rwidth_cnt <= 4'd0;
else
rwidth_cnt <= rwidth_cnt + 4'd1;
end
assign rwidth_ena = rdat | (~rwidth_cnt[2]); // [2] - 140ns, [3] - 280ns
always @(posedge fclk)
vg_rawr <= rwidth_cnt[2]; // RAWR has 2 clocks latency from rdat strobe
assign rclk_strobe = (rclk_cnt==6'd0);
always @(posedge fclk)
begin
if( rdat )
rclk_cnt <= 6'd29; // (56/2)-1 plus halfwidth of RAWR
else if( rclk_strobe )
rclk_cnt <= 6'd55; // period is 56 clocks
else
rclk_cnt <= rclk_cnt - 6'd1;
end
always @(posedge fclk)
if( rclk_strobe )
vg_rclk <= ~vg_rclk; // vg_rclk latency is 2 clocks plus a number loaded into rclk_cnt at rdat strobe
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { double ans, p, q, p1, p2, p3; int n, i; scanf( %d , &n); ans = 0.0; q = p2 = p3 = 1; p1 = 0; for (i = 1; i <= n + 1; i++) { if (i <= n) scanf( %lf , &p); else p = 0.0; ans += (1 - p) * p1; p1 = (p1 + p2) * p; q = 1.0 - p; p2 = (p2 + 2.0 * p3) * p + q; p3 = p3 * p + q; } printf( %.15f n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int mat[1010][1010]; int main() { int n, a, b; cin >> n >> a >> b; if (a > 1 && b > 1) { puts( NO ); return (0); } if (n > 1 && n <= 3 && a == 1 && b == 1) { puts( NO ); return (0); } puts( YES ); if (a == 1 && b == 1) { for (int i = 1; i < n; i++) { mat[i][i + 1] = 1; mat[i + 1][i] = 1; } } else if (a == 1) { for (int i = 1; i < b; i++) { for (int j = 1; j <= n; j++) { if (i != j) { mat[i][j] = 1; mat[j][i] = 1; } } } } else if (b == 1) { for (int i = a; i < n; i++) { mat[i][i + 1] = 1; mat[i + 1][i] = 1; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) printf( %d , mat[i][j]); printf( n ); } return (0); } |
#include <bits/stdc++.h> using namespace std; int n, m; char s[110][110]; void work1() { if (n % 3) { puts( NO ); return; } int k = n / 3; if (s[0][0] == s[k][0] || s[0][0] == s[k * 2][0] || s[k][0] == s[k * 2][0]) { puts( NO ); return; } for (int h = 0; h < 3; h++) { for (int i = 0; i < k; i++) { for (int j = 0; j < m; j++) { if (s[h * k][0] != s[h * k + i][j]) { puts( NO ); return; } } } } puts( YES ); } void work2() { if (m % 3) { puts( NO ); return; } int k = m / 3; if (s[0][0] == s[0][k] || s[0][0] == s[0][k * 2] || s[0][k] == s[0][k * 2]) { puts( NO ); return; } for (int h = 0; h < 3; h++) { for (int i = 0; i < k; i++) { for (int j = 0; j < n; j++) { if (s[0][h * k] != s[j][h * k + i]) { puts( NO ); return; } } } } puts( YES ); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %s , s[i]); } bool f = true; for (int i = 1; i < m; i++) { if (s[0][i] != s[0][i - 1]) { f = false; break; } } if (f) { work1(); } else { work2(); } return 0; } |
`define FREQ_MHz 200
`define DELAY2CYCLES(d) (`FREQ_MHz*d)/1000
module ftAsyncMode #(
parameter DATA = 8,
parameter ADDR = 12
)(
input clk,
// External(uP) Interface
input ext_wr,
input [DATA-1:0] ext_wr_data,
input ext_rd,
output reg ext_rd_data_valid,
output reg [DATA-1:0] ext_rd_data,
// FT22332 Interface
input RXF_N,
output reg RD_N,
input TXE_N,
output WR_N,
inout [DATA-1:0] DATA
);
reg [2:0] r15, r30;
reg [2:0] w15, w30;
reg [1:0] rd_state;
parameter
RD_IDLE = 0,
RD_FETCH = 1,
RD_ACTIVE = 2,
WR_IDLE = 0,
WR_FETCH = 1,
WR_ACTIVE = 2;
initial begin
RD_N <= 1'b1;
rd_state <= RD_IDLE;
end
// Asynchronous Read
always@(negedge RXF_N or posedge clk) begin
if(!RXF_N) begin
RD_N <= 1'b0;
r15 <= DELAY2CYCLES(15);
rd_state <= FETCH;
end
else begin
case(rd_state)
RD_IDLE: begin
ext_rd_data_valid <= 1'b0;
ext_rd_data <= 8'h00;
RD_N <= 1'b1;
end
RD_FETCH: begin
r15 <= r15 - 1;
if(r15 == 1) begin
ext_rd_data_valid <= 1'b1;
ext_rd_data <= ft_rd_data;
r30 <= DELAY2CYCLES(30);
rd_state <= RD_ACTIVE;
end
end
RD_ACTIVE: begin
r30 <= r30 - 1;
ext_rd_data_valid <= 1'b0;
ext_rd_data <= 8'h00;
if(r30 == 1) begin
RD_N <= 1'b1;
rd_state <= RD_IDLE;
end
end
endcase
end
end
// Asynchronous Write
always@(negedge TXE_N or posedge clk) begin
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long MOD = 998244353; template <class T> inline void chmax(T &a, const T &b) { if ((a) < (b)) (a) = (b); } template <class T> inline void chmin(T &a, const T &b) { if ((a) > (b)) (a) = (b); } template <typename T> using PQ = priority_queue<T, vector<T>, greater<T>>; struct Fast { Fast() { std::cin.tie(0); ios::sync_with_stdio(false); } } fast; long long solve() { long long n; cin >> n; vector<string> a(n); vector<long long> dcnt(11, 0); for (long long i = (long long)(0); i < (long long)(n); ++i) { cin >> a[i]; dcnt[((long long)(a[i]).size())]++; } 42; 42; auto f = [&](string s, long long d) { long long m = ((long long)(s).size()); long long res = 0; long long mul = 1; long long cnt = 0; for (long long i = (long long)((m)-1); i >= (long long)(0); --i) { long long x = s[i] - 0 ; res += mul * x; if (cnt < d) { mul *= 100; } else { mul *= 10; } mul %= MOD; res %= MOD; cnt++; } return res; }; 42; auto g = [&](string s, long long d) { long long m = ((long long)(s).size()); long long res = 0; long long mul = 10; long long cnt = 0; for (long long i = (long long)((m)-1); i >= (long long)(0); --i) { long long x = s[i] - 0 ; res += mul * x; if (cnt < d - 1) { mul *= 100; } else { mul *= 10; } mul %= MOD; res %= MOD; cnt++; } return res; }; 42; long long ans = 0; for (long long i = (long long)(0); i < (long long)(n); ++i) { for (long long d = (long long)(1); d < (long long)(11); ++d) { ans += f(a[i], d) * dcnt[d]; ans += g(a[i], d) * dcnt[d]; ans %= MOD; } } cout << ans << endl; return 0; } signed main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[2001]; int ou, ji; int main() { int n; scanf( %d , &n); long long ans = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); ans += a[i]; if (a[i] % 2 == 0) ou++; else ji++; } if (ou > ji) ou = ji + 1; else if (ji > ou) ji = ou + 1; sort(a + 1, a + 1 + n); for (int i = n; i >= 1; i--) { if (a[i] % 2 == 0 && ou) { ans -= a[i]; ou--; } else if (a[i] % 2 != 0 && ji) { ans -= a[i]; ji--; } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> #define int long long using pii=std::pair<int,int>; using namespace std; const int maxn = 2e5 + 5; int n, u, v, a[maxn], in[maxn], out[maxn], order[maxn], timer = -1, st[4 * maxn], need[4 * maxn]; vector<int> adj[maxn]; map<int, vector<int>> avals; void dfs(int x, int p) { in[x] = ++timer; order[timer] = x; avals[a[x]].push_back(x); for(auto v : adj[x]) if(v != p) dfs(v, x); out[x] = timer; } int is_ancestor(int u, int v) { return (in[u] <= in[v] && out[u] >= out[v]); } void build(int tl, int tr, int v) { if(tl == tr) st[v] = 1; else { int tmid = (tl + tr) / 2; build(tl, tmid, 2 * v); build(tmid + 1, tr, 2 * v + 1); st[v] = 1; } } void push(int v) { if(need[v]) { st[2 * v] = st[2 * v + 1] = st[v]; need[2 * v] = need[2 * v + 1] = need[v]; need[v] = 0; } } void update(int tl, int tr, int l, int r, int v, int val) { if(l > r) return; if(tl == l && tr == r) { st[v] = val; need[v] = 1; } else { push(v); int tmid = (tl + tr) / 2; update(tl, tmid, l, min(r, tmid), 2 * v, val); update(tmid + 1, tr, max(l, tmid + 1), r, 2 * v + 1, val); } } int get(int tl, int tr, int v, int pos) { if(tl == tr) { assert(tl == pos); return st[v]; } else { push(v); int tmid = (tl + tr) / 2; if(pos <= tmid) return get(tl, tmid, 2 * v, pos); else return get(tmid + 1, tr, 2 * v + 1, pos); } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for(int i = 0; i < n; i++) cin >> a[i]; for(int i = 0; i < n - 1; i++) { cin >> u >> v; u--; v--; adj[u].push_back(v); adj[v].push_back(u); } dfs(0, -1); build(0, n - 1, 1); for(auto x : avals) if(x.second.size() > 1) { for(int i = 0; i < x.second.size(); i++) { int pre = x.second[i]; int cur = x.second[(i + 1) % x.second.size()]; if(is_ancestor(cur, pre)) swap(cur, pre); if(is_ancestor(pre, cur)) { int pathchild = -1; for(auto v : adj[pre]) if(is_ancestor(v, cur) && !is_ancestor(v, pre)) { pathchild = v; break; } assert(pathchild != -1); update(0, n - 1, 0, in[pathchild] - 1, 1, 0); update(0, n - 1, out[pathchild] + 1, n - 1, 1, 0); update(0, n - 1, in[cur], out[cur], 1, 0); } else { update(0, n - 1, in[cur], out[cur], 1, 0); update(0, n - 1, in[pre], out[pre], 1, 0); } } } int ans = 0; for(int i = 0; i < n; i++) ans += get(0, n - 1, 1, i); cout << ans << n ; return 0; } |
// Ten basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (signed) bytes with random numbers
// 3. assignments to (signed) bytes with random values including X and Z
// 4. converting unsigned integers to signed bytes
// 5. converting signed integers to signed bytes
// 6. converting integers including X and Z states to signed bytes
// 7. trying signed sums (procedural, function, task and module)
// 8. trying signed mults (procedural, function and task)
// 9. trying relational operators
// 10. smaller signed numbers to signed bytes (sign extension)
module ms_add (input byte signed a, b, output byte signed sc, ss);
assign sc = a + b;
always @(a, b) ss = a + b;
endmodule
module main;
parameter N_REPS = 500; // repetition with random numbers
parameter XZ_REPS = 500; // repetition with 'x 'z values
parameter MAX = 'h7f;
parameter LEN = 8;
// variables used as golden references
reg signed [LEN-1:0] ar; // holds numbers
reg signed [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions
reg signed [LEN-1:0] ar_expected;
integer unsigned ui;
integer signed si;
reg signed [LEN/2-1:0] slice;
// types to be tested
byte signed bu; // holds numbers
byte signed bu_xz; // 'x and 'z are attempted on this
byte signed bresult; // hold results from sums and mults
byte signed mcaresult; // this is permanently wired to a module
byte signed mabresult; // this is permanently wired to a module
integer i;
// continuous assigments
// type LHS type RHS
// --------- ---------
// byte 4-value logic
assign bu = ar;
assign bu_xz = ar_xz;
// module instantiation
ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) );
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 8'b0 || bu_xz != 8'b0 || bresult !== 8'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// driving byte type with signed random numbers from a variable
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// attempting to drive variables having 'x 'z values into type unsigned bytes
// 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect assigment to byte (when 'x 'z): %b", bu);
$finish;
end
end
// converting unsigned integers to signed bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ui = {$random} % 2*(MAX+1); // full range as unsigned
#1;
force bu = ui;
#1;
if (bu !== ui[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from unsigned integer to byte: %b", bu);
$finish;
end
end
release bu;
// converting signed integers to signed bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
si = $random % MAX;
#1;
force bu = si;
#1;
if (bu !== si[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from signed integer to byte: %b mismatchs %b", bu, si[LEN-1:0]);
$finish;
end
end
release bu;
// converting signed integers having 'x 'z values into type signed bytes
// 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM)
// truncation and coercion to zero expected
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
si = $random;
ar_xz = xz_inject (si[LEN-1:0]);
si = {si[31:LEN], ar_xz};
ar_expected = xz_expected (ar_xz);
#1;
force bu_xz = si;
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect conversion from integer (with 'x 'z) to byte: %b mismatchs %b", bu_xz, ar_expected);
$finish;
end
end
release bu_xz;
// trying signed sums
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
ar_xz = $random % MAX;
#1;
bresult = bu + bu_xz;
#1;
if ( bresult !== s_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of signed bytes: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz));
$finish;
end
// invoking byte sum function
if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of signed bytes in function");
$finish;
end
// invoking byte sum task
ts_sum (bu, bu_xz, bresult);
if ( bresult !== s_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of signed bytes in task: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz));
$finish;
end
// checking byte sum from module
if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz))
begin
$display ("FAILED - incorrect addition of signed bytes from module");
$finish;
end
end
// trying signed mults, forcing truncation
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = ($random % MAX) << LEN/2;
ar_xz = ($random % MAX) << (LEN/2 - 1);
#1;
bresult = bu * bu_xz;
#1;
if ( bresult !== s_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of signed bytes: %0d mismatchs %0d", bresult, s_mul(ar, ar_xz));
$finish;
end
// invoking byte mult function
if ( fs_mul (bu, bu_xz) !== s_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of signed bytes in function");
$finish;
end
// invoking byte mult task
ts_mul (bu, bu_xz, bresult);
if ( bresult !== s_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of signed bytes in task: %0d mismatchs %0d", bresult, s_mul(ar, ar_xz));
$finish;
end
end
// trying relational operators
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = $random % MAX;
ar_xz = $random % MAX;
#1;
if ( (bu < bu_xz ) !== (ar < ar_xz) )
begin
$display ("FAILED - incorrect 'less than' on signed bytes");
$finish;
end
if ( (bu <= bu_xz ) !== (ar <= ar_xz) )
begin
$display ("FAILED - incorrect 'less than or equal' on signed bytes");
$finish;
end
if ( (bu > bu_xz ) !== (ar > ar_xz) )
begin
$display ("FAILED - incorrect 'greater than' on signed bytes");
$finish;
end
if ( (bu >= bu_xz ) !== (ar >= ar_xz) )
begin
$display ("FAILED - incorrect 'greater than or equal' than on signed bytes");
$finish;
end
if ( (bu == bu_xz ) !== (ar == ar_xz) )
begin
$display ("FAILED - incorrect 'equal to' on signed bytes");
$finish;
end
if ( (bu != bu_xz ) !== (ar != ar_xz) )
begin
$display ("FAILED - incorrect 'not equal to' on signed bytes");
$finish;
end
end
// signed small number to signed byte
for (i = 0; i < (1<<LEN/2); i = i+1)
begin
#1;
slice = $random % 'h7;
force bu = slice;
ar = slice;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect signed extend to signed bytes");
$finish;
end
end
release bu;
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [LEN-1:0] xz_inject (input signed [LEN-1:0] value);
integer i, temp;
begin
temp = {$random} % 2*(MAX+1); // possible 1 in any position
for (i=0; i<LEN; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [LEN-1:0] xz_expected (input signed [LEN-1:0] value_xz);
integer i;
begin
for (i=0; i<LEN; i=i+1)
begin
if (value_xz[i] === 1'bx || value_xz[i] === 1'bz )
value_xz[i] = 1'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
// signed 4-value sum
function signed [LEN-1:0] s_sum (input signed [LEN-1:0] a, b);
s_sum = a + b;
endfunction
// signed byte sum as function
function byte signed fs_sum (input byte signed a, b);
fs_sum = a + b;
endfunction
// signed byte sum as task
task ts_sum (input byte signed a, b, output byte signed c);
c = a + b;
endtask
// signed 4-value mults
function signed [LEN-1:0] s_mul (input signed [LEN-1:0] a, b);
s_mul = a * b;
endfunction
// signed byte mults
function byte signed fs_mul (input byte signed a, b);
fs_mul = a * b;
endfunction
// signed byte mult as task
task ts_mul (input byte signed a, b, output byte signed c);
c = a * b;
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; using li = long long; using ld = long double; using pii = pair<int, int>; const int INF = 1e9 + 13; const int N = 2e5 + 13; const int M = 1e9 + 7; const int B = 600; const int A = 256; const ld e = 1e-8; const int LOGN = 20; mt19937 rnd(time(0)); void solve() { int n, m; cin >> n >> m; vector<bool> a(n, false); for (int i = 0; i < m; i++) { int x, y, z; cin >> x >> y >> z; y--; a[y] = true; } int v = -1; for (int i = 0; i < n; i++) if (!a[i]) v = i; for (int i = 0; i < n; i++) { if (i != v) cout << v + 1 << << i + 1 << n ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; cin >> t; while (t--) solve(); } |
`timescale 1ns / 1ps
module MicrophoneSampler(
output spi_clk,
output spi_mosi,
output spi_cs,
input spi_miso,
input clk,
input rst,
output [9:0] sample
);
localparam DELAY_20KHZ = 16'h1388; // decimal 5000 (100 mill / 20,000 = 5000)
localparam DELAY_40KHZ = 16'h09C4; // decimal 2500 (100 mill / 40,000 = 2500)
reg [12:0] counter; // 16-bit counter
reg start_conv;
wire [9:0] sample_out;
Microphone mic(spi_clk, spi_mosi, spi_cs, spi_miso, clk, rst, start_conv, , sample);
always @ (posedge clk) begin
if(rst) begin
counter <= 13'b0;
start_conv <= 1'b0;
end else begin
if(counter == DELAY_40KHZ) begin
start_conv <= 1'b1;
counter <= 13'b0;
end
else begin
start_conv <= 1'b0;
counter <= counter + 1'b1;
/*
sample <= 10'h0;
if(sample_out >= 10'h1FF)
sample[0] <= 1'b1;
if(sample_out >= 10'h23F)
sample[1] <= 1'b1;
if(sample_out >= 10'h27F)
sample[2] <= 1'b1;
if(sample_out >= 10'h2BF)
sample[3] <= 1'b1;
if(sample_out >= 10'h2FF)
sample[4] <= 1'b1;
if(sample_out >= 10'h33F)
sample[5] <= 1'b1;
if(sample_out >= 10'h37F)
sample[6] <= 1'b1;
if(sample_out >= 10'h3BF)
sample[7] <= 1'b1;
*/
end
end
end
endmodule
|
#include <bits/stdc++.h> const int MAX_N = 1000000; const int MOD = 1000000007; std::vector<int> groups; int table[1 + MAX_N], dp[1 + MAX_N]; std::deque<int> tablePositions; int main() { std::string s; std::cin >> s; groups.push_back(0); int cnt = 0; for (int i = 0; i < s.size(); ++i) if (s[i] == 0 ) ++cnt; else { groups.push_back(cnt); cnt = 0; } groups.push_back(cnt); dp[1] = groups[1] + 1; for (int i = 2; i < groups.size(); ++i) { if (i < groups.size() - 1) dp[i] = dp[i - 1]; for (int lastDigit = 0; lastDigit <= groups[i]; ++lastDigit) { dp[i] = (dp[i] + dp[i - 1]) % MOD; while (!tablePositions.empty() && tablePositions.front() < lastDigit) tablePositions.pop_front(); if (i < groups.size() - 1 && !tablePositions.empty()) dp[i] = (dp[i] + MOD - table[tablePositions.front()]) % MOD; } tablePositions.push_front(groups[i]); table[groups[i]] = dp[i - 1]; } if (groups.size() == 2) dp[groups.size() - 1]--; printf( %d , dp[groups.size() - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; void pairsort(long long a[], long long b[], long long n) { pair<long long, long long> pairt[n]; for (long long i = 0; i < n; i++) { pairt[i].first = a[i]; pairt[i].second = b[i]; } sort(pairt, pairt + n); for (long long i = 0; i < n; i++) { a[i] = pairt[i].first; b[i] = pairt[i].second; } } int32_t main() { long long n, k; cin >> n >> k; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } long long f = 0; long long c = 0; for (long long i = 0; i < n - 1; i++) { c += a[i] / k; a[i] = a[i] % k; if (a[i] != 0) { if (k - a[i] < a[i + 1]) a[i + 1] -= (k - a[i]); else a[i + 1] = 0; c += 1; } a[i] = 0; } c += a[n - 1] / k; if (a[n - 1] % k != 0) c += 1; cout << c; return 0; } |
#include<bits/stdc++.h> #define LL long long #define dl double #define P pair<int,int> using namespace std; const int N = 2e5 + 10; int n; struct ghb{ int a,b; bool operator < (const ghb &o)const{ return min(a,b) < min(o.a,o.b); } }f[N]; LL ans; int mx; int main(){ // freopen( in.txt , r ,stdin); // freopen( o.txt , w ,stdout); std::ios::sync_with_stdio(false); std::cin.tie(nullptr); cin >> n; for(int i = 1;i <= n;i++)cin >> f[i].a; for(int i = 1;i <= n;i++)cin >> f[i].b; for(int i = 1;i <= n;i++)ans += abs(f[i].a - f[i].b); sort(f + 1,f + n + 1); int mx_1 = 0,mx_2 = 0; for(int i = 1;i <= n;i++){ if(f[i].a > f[i].b){ if(mx_1)mx = max(mx,min(mx_1,f[i].a) - f[i].b); mx_2 = max(mx_2,f[i].a); } else { if(mx_2)mx = max(mx,min(mx_2,f[i].b) - f[i].a); mx_1 = max(mx_1,f[i].b); } } cout << ans - 2 * mx << endl; return 0; } /**/ |
#include <bits/stdc++.h> int n, m; std::vector<std::pair<int, int> > a[2]; void normalize(std::vector<std::pair<int, int> >& v) { if (v.empty()) { return; } std::sort((v).begin(), (v).end()); int k = 1; for (int i = 1; i < ((int)(v).size()); i++) { if (v[i].first != v[i - 1].first) { v[k++] = v[i]; } else { v[k - 1].second += v[i].second; } } v.erase(v.begin() + k, v.end()); } int calc(std::vector<std::pair<int, int> >& a, std::vector<std::pair<int, int> >& b) { if (((int)(a).size()) == 0) { return 0; } int max = a.back().first - a.front().first; for (int i = 0; i < ((int)(b).size()); i++) { if (b[i].first <= a.front().first) { max = std::max(max, n - (a.front().first - b[i].first)); } if (b[i].first >= a.back().first) { max = std::max(max, n - (b[i].first - a.back().first)); } } std::vector<std::pair<int, int> >::iterator itr = std::lower_bound((b).begin(), (b).end(), std::make_pair(a[0].first, 0)); if (itr != b.end() && itr->first <= a.back().first) { max = n; } return max; } long long binom(int n) { return 1LL * n * (n - 1) * (n - 2) / 6; } long long COUNT(std::vector<std::pair<int, int> >& a, std::vector<std::pair<int, int> >& b, int max) { if (calc(a, b) < max) { return 0LL; } long long ways = 0; int sum = 0, cnt = 0; for (int i = 0; i < ((int)(a).size()); i++) { sum += a[i].second; } for (int i = 0; i < ((int)(b).size()); i++) { cnt += b[i].second; } std::vector<int> suffix(((int)(a).size()) + 1, 0); for (int i = ((int)(a).size()) - 1; i >= 0; i--) { suffix[i] = suffix[i + 1] + a[i].second; } if (a.back().first - a.front().first == max) { ways += binom(sum); ways -= binom(sum - a.front().second) + binom(sum - a.back().second); ways += binom(sum - a.front().second - a.back().second); ways += 1LL * a.front().second * a.back().second * cnt; } if (((int)(b).size()) > 0) { for (int i = 0; i < ((int)(b).size()); i++) { if (b[i].first < a.front().first) { int tmp = n - (a.front().first - b[i].first); if (tmp == max) { ways += 1LL * a.front().second * (a.front().second - 1) / 2 * b[i].second; ways += 1LL * a.front().second * (sum - a.front().second) * b[i].second; } } if (b[i].first > a.back().first) { int tmp = n - (b[i].first - a.back().first); if (tmp == max) { ways += 1LL * a.back().second * (a.back().second - 1) / 2 * b[i].second; ways += 1LL * a.back().second * (sum - a.back().second) * b[i].second; } } } if (max == n) { for (int i = 0; i < ((int)(b).size()); i++) { std::vector<std::pair<int, int> >::iterator itr = std::lower_bound( (a).begin(), (a).end(), std::make_pair(b[i].first, 0)); int p = 0, q = 0, r = 0; p = suffix[0] - suffix[itr - a.begin()]; int t = itr - a.begin(); itr = std::lower_bound((a).begin(), (a).end(), std::make_pair(b[i].first + 1, 0)); q = suffix[t] - suffix[itr - a.begin()]; r = suffix[0] - p - q; ways += 1LL * q * p * b[i].second; ways += 1LL * q * r * b[i].second; ways += 1LL * p * r * b[i].second; ways += 1LL * q * (q - 1) / 2 * b[i].second; } } } return ways; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int s, f; scanf( %d%d , &s, &f); a[s].push_back(std::make_pair(f, 1)); } normalize(a[0]); normalize(a[1]); int max = std::max(calc(a[0], a[1]), calc(a[1], a[0])); if (max == 0) { std::cout << binom(m) << std::endl; } else { std::cout << COUNT(a[0], a[1], max) + COUNT(a[1], a[0], max) << std::endl; } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.3
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module my_video_filter_line_buffers_val_0_ram (addr0, ce0, d0, we0, addr1, ce1, d1, we1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 5760;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
end
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
end
end
end
endmodule
`timescale 1 ns / 1 ps
module my_video_filter_line_buffers_val_0(
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
we1,
d1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd5760;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
my_video_filter_line_buffers_val_0_ram my_video_filter_line_buffers_val_0_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1.0); int main() { int n, m, cnt, i, j; while (~scanf( %d%d , &n, &m)) { if ((n % 2 == 0 && m * 2 <= n * n) || (n % 2 && m * 2 <= n * n + 1)) { printf( YES n ); cnt = 0; for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (i % 2 == j % 2 && cnt < m) { printf( L ); cnt++; } else printf( S ); } printf( n ); } } else printf( NO n ); } return 0; } |
#include <bits/stdc++.h> #define For(i, a, b) for (int i = (a), _##i = (b); i < _##i; ++i) #define FOR(i, a, b) for (int i = (a), _##i = (b); i <= _##i; ++i) #define Forr(i, a, b) for (int i = (a), _##i = (b); i > _##i; --i) #define FORR(i, a, b) for (int i = (a), _##i = (b); i >= _##i; --i) #define all(a) a.begin(), a.end() #define range(i, a) for (auto& i : a) #define RANGE(i, a) for (auto i = a.rbegin(); i != a.rend(); ++i) #define SINGLE using ll = long long; using pii = std::pair<int, int>; using pdd = std::pair<double, double>; namespace Solver { const int N = (1 << 18) + 5; std::string opt; int res[N << 1]; int n, cnt; void update(int p, char c) { if (opt[p] == c) return; opt[p] = c; // if (c == ? ) // res[p] = res[p << 1] + res[p << 1 | 1]; while (p) { if (opt[p] == ? ) res[p] = res[p << 1] + res[p << 1 | 1]; else if (opt[p] == 1 ) res[p] = res[p << 1]; else res[p] = res[p << 1 | 1]; p >>= 1; } } void build(int u) { if ((u << 1) <= cnt) build(u << 1); if ((u << 1 | 1) <= cnt) build(u << 1 | 1); if (opt[u] == ? ) res[u] = res[u << 1] + res[u << 1 | 1]; else if (opt[u] == 1 ) res[u] = res[u << 1]; else res[u] = res[u << 1 | 1]; } void main() { std::cin >> n; std::string temp; std::cin >> temp; std::fill(res, res + (N << 1) - 1, 1); cnt = (1 << n) - 1; opt = ; RANGE (i, temp) opt.push_back(*i); build(1); int T; for (std::cin >> T; T--;) { int p; char c; std::cin >> p >> c; update(cnt - p + 1, c); std::cout << res[1] << std::endl; } } } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); #ifndef SINGLE int T; for (std::cin >> T; T--;) #endif Solver::main(); return 0; } |
/*
* This module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
dut xx (.clk(clk));
// This defparam sets the desired with of the U instance vector.
defparam main.xx.wid = wid;
// These defparams set parameters within U instances.
defparam main.xx.sub[0].U.number = 0;
defparam main.xx.sub[1].U.number = 1;
defparam main.xx.sub[2].U.number = 2;
defparam main.xx.sub[3].U.number = 3;
defparam main.xx.sub[4].U.number = 4;
initial begin
clk = 0;
#1 clk = 1;
while (clk != 0)
#1 clk = clk << 1;
$finish;
end
endmodule // main
module dut #(parameter wid = 1) (input [wid-1:0] clk);
genvar i;
for (i = 0 ; i < wid ; i = i+1) begin : sub
target U (.clk(clk[i]));
end
endmodule //
module target(input wire clk);
parameter number = 999;
always @(posedge clk)
$display("%m: number=%0d", number);
endmodule // target
|
#include <bits/stdc++.h> using namespace std; int x[100005], res[100005]; map<int, pair<int, int>> xhMap; int main() { memset(x, 0, sizeof(x)); memset(res, 0, sizeof(res)); int n = 0, a = 0, b = 0; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &a, &b); x[i] = a; xhMap[a] = make_pair(b, i); } sort(x, x + n); for (int i = n - 1; i >= 0; --i) { int tmp = x[i] + xhMap[x[i]].first - 1, idx = xhMap[x[i]].second; int r = i + 1, num = 1; while (r < n && x[r] <= tmp) { num += res[xhMap[x[r]].second]; r += res[xhMap[x[r]].second]; } res[idx] = num; } for (int i = 0; i < n; ++i) { printf( %d , res[i]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_PP_BLACKBOX_V
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: counter_bus_mux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module counter_bus_mux (
data0x,
data1x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
wire [3:0] sub_wire5;
wire [3:0] sub_wire2 = data1x[3:0];
wire [3:0] sub_wire0 = data0x[3:0];
wire [7:0] sub_wire1 = {sub_wire2, sub_wire0};
wire sub_wire3 = sel;
wire sub_wire4 = sub_wire3;
wire [3:0] result = sub_wire5[3:0];
lpm_mux LPM_MUX_component (
.data (sub_wire1),
.sel (sub_wire4),
.result (sub_wire5)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 2,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 4,
LPM_MUX_component.lpm_widths = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL "data0x[3..0]"
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL "data1x[3..0]"
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file sa1_iram.v when simulating
// the core, sa1_iram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module sa1_iram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [10 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; struct SUBS { string _s; int l, r; SUBS() {} SUBS(string s, int l, int r) : _s(s), l(l), r(r) {} bool operator<(const SUBS& subs) const { return _s > subs._s; } }; priority_queue<SUBS> pq; string s; long long n, k; int main() { cin >> s; cin >> k; n = s.length(); if (2 * k > n * (n + 1)) { cout << No such line. << endl; return 0; } for (int i = 0; i < n; i++) pq.push(SUBS(s.substr(i, 1), i, i + 1)); SUBS subs; for (int i = 0; i < k; i++) { subs = pq.top(); pq.pop(); if (subs.r < n) { int len = subs.r - subs.l; pq.push(SUBS(s.substr(subs.l, len + 1), subs.l, subs.r + 1)); } } cout << subs._s << endl; } |
#include <bits/stdc++.h> using namespace std; using i32 = int32_t; using i64 = int64_t; using pii = std::pair<i32, i32>; using pll = std::pair<i64, i64>; int dp[5000]; int iv[5000]; bool used[5000]; int div_up(int a, int b) { return (a + b - 1) / b; } void log_pour(int n, int s, int d) { if (n > 0) { printf( %d %d %d n , n, s + 1, d + 1); } } int main() { int n, k, v; scanf( %d%d%d , &n, &k, &v); for (int i = 0; i < k; i++) { dp[i] = -1; } int vmax = 0; deque<int> q; for (int i = 0; i < n; i++) { scanf( %d , &iv[i]); if (iv[i] == 0) continue; auto v_mod = iv[i] % k; if (dp[v_mod] < 0 || i < dp[v_mod]) { dp[v_mod] = i; q.push_back(v_mod); } vmax += iv[i]; } if (vmax < v) { printf( NO n ); return 0; } if (v == 0) { printf( YES n ); log_pour(div_up(iv[0], k), 0, 1); return 0; } if (v % k == 0) { printf( YES n ); for (int i = 1; i < n; i++) { log_pour(div_up(iv[i], k), i, 0); } log_pour(v / k, 0, 1); return 0; } while (!q.empty()) { auto v_mod = q.front(); q.pop_front(); assert(dp[v_mod] >= 0); for (int i = dp[v_mod] + 1; i < n; i++) { if (iv[i] == 0) continue; auto v2 = (v_mod + iv[i]) % k; if (dp[v2] < 0 || i < dp[v2]) { dp[v2] = i; q.push_back(v2); } } } if (dp[v % k] < 0) { printf( NO n ); return 0; } printf( YES n ); int v0 = 0; int r = v % k; int j0 = dp[r]; do { assert(dp[r] >= 0); used[dp[r]] = true; v0 += iv[dp[r]]; if (dp[r] != j0) { log_pour(div_up(iv[dp[r]], k), dp[r], j0); } r = (k + r - iv[dp[r]] % k) % k; } while (v0 % k != v % k); for (int j = dp[j0]; v0 % k != v % k; j = dp[j]) { used[j] = true; v0 += iv[j]; log_pour(div_up(iv[j], k), dp[j], j0); } assert(v0 % k == v % k); int j1 = -1; int v1 = 0; for (int i = 0; i < n; i++) { if (used[i]) continue; v1 += iv[i]; if (j1 < 0) { j1 = i; } else { log_pour(div_up(iv[i], k), i, j1); } } if (v0 > v) { log_pour((v0 - v) / k, j0, (j0 + 1) % n); } else if (v0 < v) { assert(j1 >= 0); log_pour((v - v0) / k, j1, j0); } return 0; } |
#include <bits/stdc++.h> using namespace std; int countnode(map<int, vector<int>> m, int x, int parent) { int count = 1; for (auto i : m[x]) { if (i != parent) count += countnode(m, i, x); } return count; } int main() { int t; cin >> t; while (t--) { int n, x; cin >> n >> x; map<int, vector<int>> m; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; m[a].push_back(b); m[b].push_back(a); } if (m[x].size() == 1 || m[x].size() == 0) cout << Ayush << endl; else { if (countnode(m, x, x) % 2 == 0) cout << Ayush << endl; else cout << Ashish << endl; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_2_V
`define SKY130_FD_SC_HDLL__NAND4_2_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_2_V
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; const int inf = 1e9; const int N = 2e5; void solve() { long long int d, m; cin >> d >> m; long long int mx; for (long long int i = 32; i >= 0; i--) { if ((1LL << i) & d) { mx = i; break; } } long long int dp[mx + 1]; dp[mx] = (d - (1LL << mx) + 1); long long int res = dp[mx]; res %= m; for (long long int i = mx - 1; i >= 0; i--) { dp[i] = (1LL << i) * (1 + res); res += dp[i]; res %= m; } cout << res << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100; int n; int t[2][N]; vector<int> vals[N]; vector<pair<int, int>> G[N]; bool vis[N]; int color[N]; vector<int> C[2]; bool cycle; void dfs(int v) { vis[v] = true; C[color[v]].push_back(v); for (auto it : G[v]) { if (vis[it.first] && (color[v] ^ it.second) != color[it.first]) cycle = true; if (!vis[it.first]) { color[it.first] = color[v] ^ it.second; dfs(it.first); } } } void solve() { scanf( %d , &n); for (int i = 1; i <= n; ++i) G[i].clear(), vals[i].clear(); for (int j = 0; j <= 1; ++j) for (int i = 1; i <= n; ++i) { scanf( %d , &t[j][i]); vals[t[j][i]].push_back(i); } for (int i = 1; i <= n; ++i) { if ((int)vals[i].size() != 2) { printf( -1 n ); return; } int u = vals[i][0], v = vals[i][1], w; if (u == v) continue; w = ((t[0][u] == t[0][v] && t[0][u] == i) || (t[1][u] == t[1][v] && t[1][u] == i)); G[u].push_back(make_pair(v, w)); G[v].push_back(make_pair(u, w)); } cycle = false; for (int i = 1; i <= n; ++i) vis[i] = false; vector<int> ans; for (int i = 1; i <= n; ++i) if (!vis[i]) { for (int j = 0; j <= 1; ++j) C[j].clear(); dfs(i); if ((int)C[0].size() > (int)C[1].size()) swap(C[0], C[1]); for (auto it : C[0]) ans.push_back(it); } if (cycle) printf( -1 n ); printf( %d n , (int)ans.size()); for (auto it : ans) printf( %d , it); printf( n ); } int main() { int T; scanf( %d , &T); while (T--) { solve(); } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:06:54 09/13/2015
// Design Name: Keyboard_dev
// Module Name: E:/Seafile/ISE/CPUFly/tests/Keyboard_dev_test.v
// Project Name: CPUFly
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Keyboard_dev
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Keyboard_dev_test;
// Inputs
reg clk;
reg reset;
reg kbd_clk;
reg kbd_data;
// Outputs
wire [7:0] Keyboard_Data;
wire ready_pulse;
// Instantiate the Unit Under Test (UUT)
Keyboard_dev uut (
.clk(clk),
.reset(reset),
.kbd_clk(kbd_clk),
.kbd_data(kbd_data),
.Keyboard_Data(Keyboard_Data),
.ready_pulse(ready_pulse)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
kbd_clk = 0;
kbd_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#50 kbd_clk = 1;
kbd_data = 0;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 0;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 0;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 0;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 1;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 1;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 1;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 1;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 0;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 0;
#50 kbd_clk = 0;
#50 kbd_clk = 1;
kbd_data = 0;
#50 kbd_clk = 0;
end
always begin
#25 clk = ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[200000], money, energy, i; scanf( %d , &n); for (i = 0; i <= n - 1; i++) { scanf( %d , &a[i]); } energy = 0; money = a[0]; for (i = 0; i <= n - 2; i++) { if (energy + a[i] - a[i + 1] < 0) { money += a[i + 1] - a[i] - energy; energy = 0; } else { energy += a[i] - a[i + 1]; } } printf( %d n , money); return 0; } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } const long long inf = 9223372036854775807; const long long mod = 1000000007; const double pi = acos(-1); long long n = 0; long long m = 0; long long k = 0; long long check(long long value) { long long ans = 0; for (int i = 1; i < n + 1; i++) { ans += min((value) / i, m); } return ans; } bool ifExist(long long val) { for (int i = 1; i < n + 1; i++) { if (val % i == 0 && val / i >= 1 && val / i <= m) { return true; } } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); cin >> n >> m >> k; long long l = 1, r = n * m; long long mid = 1; while (l < r) { mid = (r + l) / 2; long long val = check(mid); if (val >= k) { r = mid; } else { l = mid + 1; } } cout << l; return 0; } |
// megafunction wizard: %In-System Sources and Probes%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
wire [2:0] sub_wire0;
wire [2:0] source = sub_wire0[2:0];
altsource_probe altsource_probe_component (
.probe (probe),
.source_clk (source_clk),
.source (sub_wire0)
// synopsys translate_off
,
.clr (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "YES",
altsource_probe_component.instance_id = "RST",
altsource_probe_component.probe_width = 0,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_SYMBOL_V
`define SKY130_FD_SC_HD__O41AI_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using ld = long double; template <typename T1, typename T2> inline void chkmin(T1& x, const T2& y) { if (y < x) x = y; } template <typename T1, typename T2> inline void chkmax(T1& x, const T2& y) { if (x < y) x = y; } const int N = 1e5 + 10; const int B = 300; struct Node { int next_node; int prev_node; int jump; }; int n, q; Node nodes[N]; bool used[N]; int find_jump(int v) { for (int i = 0; i < B; ++i) { v = nodes[v].next_node; } return v; } void build() { for (int i = 0; i < n; ++i) { if (used[i]) continue; int v = i; int jump = find_jump(i); while (!used[v]) { used[v] = true; nodes[v].jump = jump; v = nodes[v].next_node; jump = nodes[jump].next_node; } } } void relax_jumps(int v) { int jump = v; for (int i = 0; i < B; ++i) { v = nodes[v].prev_node; } for (int i = 0; i <= B; ++i) { nodes[v].jump = jump; v = nodes[v].next_node; jump = nodes[jump].next_node; } } void upd(int i, int j) { int next_i = nodes[i].next_node; int next_j = nodes[j].next_node; nodes[i].next_node = next_j; nodes[j].next_node = next_i; nodes[next_i].prev_node = j; nodes[next_j].prev_node = i; relax_jumps(i); relax_jumps(j); } int getAns(int v, int k) { while (k) { if (k >= B) { v = nodes[v].jump; k -= B; } else { v = nodes[v].next_node; --k; } } return v; } signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cout.precision(20), cout.setf(ios::fixed); cin >> n >> q; for (int i = 0; i < n; ++i) { cin >> nodes[i].next_node; --nodes[i].next_node; nodes[nodes[i].next_node].prev_node = i; } build(); while (q--) { int t; cin >> t; if (t == 1) { int i, j; cin >> i >> j; --i; --j; upd(i, j); } else if (t == 2) { int v, k; cin >> v >> k; --v; cout << getAns(v, k) + 1 << n ; } else { assert(false); } } return 0; } |
#include <bits/stdc++.h> int main() { long long int n; std::cin >> n; if (n % 2 == 0) { std::cout << n / 2 << std::endl; } else { std::cout << -(n + 1) / 2 << std::endl; } return 0; } |
//==================================================================================================
// Filename : gpio.v
// Created On : 2015-01-02 19:44:15
// Last Modified : 2015-05-24 20:58:09
// Revision :
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : 8-bit GPIO module x 4
//
// Register's name:
// - PD: Port Data
// - DD: Data Direction
// - IE: Interrupt Enable (pin)
// - EP: Edge polarity: 0 -> Falling. 1-> Rising
// - IC: Clear interrupt flag
//
// Using a 5-bits address:
// - PTAD @ 0x00 (offset = 0)
// - PTBD @ 0x01
// - PTCD @ 0x02
// - PTDD @ 0x03
//
// - PTADD @ 0x04 (offset = 4)
// - PTBDD @ 0x05
// - PTCDD @ 0x06
// - PTDDD @ 0x07
//
// - PTAIE @ 0x08 (offset = 8)
// - PTBIE @ 0x09
// - PTCIE @ 0x0A
// - PTDIE @ 0x0B
//
// - PTAEP @ 0x0C (offset = 12)
// - PTBEP @ 0x0D
// - PTCEP @ 0x0E
// - PTDEP @ 0x0F
//
// - PTAIC @ 0x10 (offset = 16)
// - PTBIC @ 0x11
// - PTCIC @ 0x12
// - PTDIC @ 0x13
//==================================================================================================
`define GPIO_PD_OFFSET 5'd0
`define GPIO_DD_OFFSET 5'd4
`define GPIO_IE_OFFSET 5'd8
`define GPIO_EP_OFFSET 5'd12
`define GPIO_IC_OFFSET 5'd16
`define GPIO_UA_OFFSET 5'd20 // unimplemented address
`define ADDR_CHECK 5'b11100
module gpio(
input clk,
input rst,
inout [31:0] gpio_inout, // input/output port
input [4:0] gpio_address, // Address
input [31:0] gpio_data_i, // Data from bus
input [3:0] gpio_wr, // Byte select
input gpio_enable, // Enable operation
output reg [31:0] gpio_data_o, // Data to bus
output reg gpio_ready, // Ready operation
output reg [3:0] gpio_interrupt // Active interrupt. One for each port.
);
//--------------------------------------------------------------------------
// wire
//--------------------------------------------------------------------------
wire [31:0] gpio_data_wire_i;
wire enable_write;
wire enable_read;
wire [31:0] interrupt_signal; // Input "edges"
wire int_port_a; // the interrupt signals from port A
wire int_port_b; // the interrupt signals from port B
wire int_port_c; // the interrupt signals from port C
wire int_port_d; // the interrupt signals from port D
//--------------------------------------------------------------------------
// registers
//--------------------------------------------------------------------------
reg [31:0] gpio_data_reg_i;
reg [31:0] gpio_data_reg_o;
reg [31:0] gpio_dd;
reg [31:0] gpio_ie;
reg [31:0] gpio_ep;
//--------------------------------------------------------------------------
// Assignment
//--------------------------------------------------------------------------
assign enable_write = gpio_enable & gpio_wr != 4'b0000; // Enable if Valid operation, and write at least one byte
assign enable_read = (gpio_enable | gpio_ready) & gpio_wr == 4'b0000;
assign int_port_a = |interrupt_signal[7:0]; // OR the signals
assign int_port_b = |interrupt_signal[15:8]; // OR the signals
assign int_port_c = |interrupt_signal[23:16]; // OR the signals
assign int_port_d = |interrupt_signal[31:24]; // OR the signals
//--------------------------------------------------------------------------
// ACK generation
// Assert the ready port each cycle, depending on the enable signal.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_ready <= 1'b0;
end
else begin
gpio_ready <= gpio_enable & (gpio_address < `GPIO_UA_OFFSET); // only if valid region
end
end
//--------------------------------------------------------------------------
// Get interrupt "edge"
// The interrupt flag will raise only if, at least one pin is interrupt
// enabled, and is configured as input.
//--------------------------------------------------------------------------
genvar i;
generate
for(i = 0; i < 32; i = i + 1) begin: gpio_interrupt_signal
assign interrupt_signal[i] = ( (gpio_ep[i]) ? gpio_data_reg_i[i] : ~gpio_data_reg_i[i] ) & gpio_ie[i] & ~gpio_dd[i];
end
endgenerate
//--------------------------------------------------------------------------
// Tri-state buffer
//--------------------------------------------------------------------------
generate
for(i = 0; i < 32; i = i + 1) begin: gpio_tristate
assign gpio_inout[i] = (gpio_dd[i]) ? gpio_data_reg_o[i] : 1'bZ; // If output: put data. Else, High-Z
assign gpio_data_wire_i[i] = (gpio_dd[i]) ? gpio_data_reg_o[i] : gpio_inout[i]; // If output: read output register. Else, read pin
end
endgenerate
//--------------------------------------------------------------------------
// Set data direction
// After reset: all ports to input state (avoid "accidents")
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_dd <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_DD_OFFSET) begin
gpio_dd[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_dd[7:0];
gpio_dd[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_dd[15:8];
gpio_dd[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_dd[23:16];
gpio_dd[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_dd[31:24];
end
else begin
gpio_dd <= gpio_dd;
end
end
//--------------------------------------------------------------------------
// Set data output
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_data_reg_o <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_PD_OFFSET) begin
gpio_data_reg_o[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_data_reg_o[7:0];
gpio_data_reg_o[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_data_reg_o[15:8];
gpio_data_reg_o[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_data_reg_o[23:16];
gpio_data_reg_o[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_data_reg_o[31:24];
end
else begin
gpio_data_reg_o <= gpio_data_reg_o;
end
end
//--------------------------------------------------------------------------
// Set interrupt enable
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_ie <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_IE_OFFSET) begin
gpio_ie[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_ie[7:0];
gpio_ie[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_ie[15:8];
gpio_ie[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_ie[23:16];
gpio_ie[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_ie[31:24];
end
else begin
gpio_ie <= gpio_ie;
end
end
//--------------------------------------------------------------------------
// Set edge mode
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_ep <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_IE_OFFSET) begin
gpio_ep[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_ep[7:0];
gpio_ep[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_ep[15:8];
gpio_ep[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_ep[23:16];
gpio_ep[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_ep[31:24];
end
else begin
gpio_ep <= gpio_ep;
end
end
//--------------------------------------------------------------------------
// Set interrupt signal
//--------------------------------------------------------------------------
always @(posedge clk) begin
if(rst) begin
gpio_interrupt <= 4'b0;
end
else if (enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_IC_OFFSET) begin
gpio_interrupt[0] <= (gpio_wr[0]) ? 1'b0 : gpio_interrupt[0];
gpio_interrupt[1] <= (gpio_wr[1]) ? 1'b0 : gpio_interrupt[1];
gpio_interrupt[2] <= (gpio_wr[2]) ? 1'b0 : gpio_interrupt[2];
gpio_interrupt[3] <= (gpio_wr[3]) ? 1'b0 : gpio_interrupt[3];
end
else begin
gpio_interrupt[0] <= (int_port_a) ? 1'b1 : gpio_interrupt[0];
gpio_interrupt[1] <= (int_port_b) ? 1'b1 : gpio_interrupt[1];
gpio_interrupt[2] <= (int_port_c) ? 1'b1 : gpio_interrupt[2];
gpio_interrupt[3] <= (int_port_d) ? 1'b1 : gpio_interrupt[3];
end
end
//--------------------------------------------------------------------------
// Set data input
// Just sample/register the input data
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_data_reg_i <= 32'b0;
end
else begin
gpio_data_reg_i <= gpio_data_wire_i;
end
end
//--------------------------------------------------------------------------
// Read
//--------------------------------------------------------------------------
always @(*) begin
if (enable_read) begin
case (gpio_address & `ADDR_CHECK)
`GPIO_PD_OFFSET : gpio_data_o <= gpio_data_reg_i;
`GPIO_DD_OFFSET : gpio_data_o <= gpio_dd;
`GPIO_IE_OFFSET : gpio_data_o <= gpio_ie;
`GPIO_EP_OFFSET : gpio_data_o <= gpio_ep;
`GPIO_IC_OFFSET : gpio_data_o <= 32'h0000_0000;
default : gpio_data_o <= 32'hDEAD_F00D;
endcase
end
else begin
gpio_data_o <= 32'hDEAD_B00B;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_BLACKBOX_V
`define SKY130_FD_SC_LP__DLXTN_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxtn (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; long long int i; while (t--) { string a, b, c; cin >> a >> b >> c; long long int n = a.length(), f = 0; for (i = 0; i < n; i++) { if (a[i] != c[i] && b[i] != c[i]) { cout << NO n ; f = 1; break; } else if (a[i] == c[i]) swap(b[i], c[i]); else swap(a[i], c[i]); } if (f != 1) cout << YES n ; } return 0; } |
// EE 471 Lab 3, Beck Pang, Spring 2015
// combine SRAM and ALU together
// @require:
// Instruction formula is formed by 3 bit control, 5 bit for address of A
// 5 bit for address of B
// fetch instructions and data into SRAM, and then move to register file
module DE1_SoCPhaseII (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
reg [2:0] ps, ns;
wire [15:0] data;
reg [7:0] count; // 0~255
reg WrEn, regWR;
reg [10:0] adx;
reg [15:0] store;
reg [2:0] control;
wire rst, fetchStart;
reg [4:0] readAdx0, readAdx1, writeAdx;
reg [31:0] writeData;
wire [31:0] readOutput0, readOutput1;
wire [2:0] opcode;
wire [4:0] regAdx0, regAdx1;
reg [31:0] busA, busB;
wire [31:0] busOut;
wire zero, overflow, carryout, negative;
assign fetchStart = SW[6]; // fetch starts when SW[6] turns on
assign rst = SW[9];
assign data = WrEn ? 16'bZ : store; // control the tri-state
assign LEDR[3:0] = {zero, overflow, carryout, negative};
SRAM2Kby16 memory(CLOCK_50, adx, WrEn, data);
registerFile regs(CLOCK_50, readAdx0, readAdx1, writeAdx, regWR, writeData, readOutput0, readOutput1);
ALUnit logicUnit(CLOCK_50, control, busA, busB, busOut, zero, overflow, carryout, negative);
InstrucDecoder getInstruc(data, opcode, regAdx0, regAdx1);
parameter loadData = 3'b000, loadInstr = 3'b001, transfer = 3'b010,
fetch = 3'b011, decode = 3'b100, execute = 3'b101, writeBack = 3'b110, nul = 3'bx;
always @(posedge CLOCK_50)
case (SW[6:4])
loadData : begin // write data into SRAM. Active low Write Enable
WrEn = 0;
regWR = 1;
writeAdx = 0;
writeData = 0;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
adx = count[6:0] + 8'h80;
store = 7'b1111111 - count[6:0];
// if (fetchStart)
// ns = fetch;
// else if (count[6:0] == 7'b1111111)
// ns = loadInstr;
// else
// ns = loadData;
end
loadInstr: begin // create instruction and data address using counter
WrEn = 0;
regWR = 1;
adx = count[6:0];
// count[6:4] is opcode, {1'b0, count[3:0]} the address of A, {1'b1, count[3:0]} the address of B,
store = {count[6:4], {1'b0, count[3:0]}, {1'b1, count[3:0]}, 3'b0};
// if (fetchStart)
// ns = fetch;
// else if (count[6:0] == 7'b1111111)
// ns = transfer;
// else
// ns = loadInstr;
end
transfer : begin // write data into register file
WrEn = 1;
regWR = 0;
adx = count[4:0] + 8'h80;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
writeAdx = count[4:0];
writeData= {{16{data[15]}}, data};
// if (fetchStart)
// ns = fetch;
// else
// ns = transfer;
end
fetch : begin // read from register file to ALU
if(count[0]) begin
WrEn = 1;
regWR = 1;
adx = count[7:1];
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
//ns = writeBack;
//end
/*decode : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
ns = execute;
end
execute : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
ns = writeBack;
end*/
//writeBack: begin
end else begin
WrEn = 1;
regWR = 0;
writeAdx = regAdx0;
writeData= busOut;
//if (fetchStart)
//ns= fetch;
//else
//ns= execute;
end
// execute:begin
// WrEn = 1;
// regWR = 0;
// readAdx0 = count[4:0];
// readAdx1 = 5'h10 + count[4:0];
// adx = 8'h80 + count[3:0];
// if(!fetchStart)
// ns = loadData;
// else
// ns = execute;
end
default : begin
WrEn = 1'bx;
regWR = 1'bx;
ns = nul;
end
endcase
always @(posedge CLOCK_50) begin
if (rst) begin
//ps <= loadData;
count <= 8'b0;
end
else begin
//ps <= ns;
count <= count + 1'b1;
end
end
endmodule
// vlog "./sourceCode/DE1_SoCPhaseII.v"
// vlog "./sourceCode/Implementation/mux2_1.sv"
// vlog "./sourceCode/Implementation/mux4_1.sv"
// vlog "./sourceCode/Implementation/mux8_1.sv"
// vlog "./sourceCode/Implementation/mux32_1.sv"
// vlog "./sourceCode/Implementation/register.sv"
// vlog "./sourceCode/Implementation/registerSingle.sv"
// vlog "./sourceCode/Implementation/DFlipFlop.sv"
// vlog "./sourceCode/Implementation/counter.v"
// vlog "./sourceCode/Implementation/decoder5_32.sv"
// vlog "./sourceCode/Implementation/decoder8_256.sv"
// vlog "./sourceCode/Implementation/decoder11_2048.sv"
// vlog "./sourceCode/InstrucDecoder.v"
// vlog "./sourceCode/SRAM2Kby16.v"
// vlog "./sourceCode/registerFile.sv"
// vlog "./sourceCode/ALUnit.sv"
// vlog "./sourceCode/addition.v"
// vlog "./sourceCode/subtract.v"
// vlog "./sourceCode/andGate.v"
// vlog "./sourceCode/orGate.v"
// vlog "./sourceCode/xorGate.v"
// vlog "./sourceCode/setLT.v"
// vlog "./sourceCode/shiftll.v"
// vlog "./sourceCode/adder_subtractor.v"
// vlog "./sourceCode/flag.v"
// vlog "./sourceCode/adder16b.v"
// vlog "./sourceCode/adder4b.v"
// vlog "./sourceCode/fullAdder1b.v"
// vlog "./sourceCode/lookAhead4b.v"
module DE1_SoCPhaseII_Testbench();
reg CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
reg [9:0] SW;
reg [3:0] KEY;
DE1_SoCPhaseII dut (CLOCK_50, LEDR, SW, KEY);
// Set up the clocking
parameter CLOCK_PERIOD = 100;
initial CLOCK_50 = 1;
always begin
#(CLOCK_PERIOD / 2);
CLOCK_50 = ~CLOCK_50;
end
// Set up the inputs to the design
integer i;
initial begin
@(posedge CLOCK_50);
SW[9] <= 1; @(posedge CLOCK_50);
SW[8:0] <= 9'b0; @(posedge CLOCK_50);
SW[9] <= 0; @(posedge CLOCK_50);
@(posedge CLOCK_50);
for (i = 0; i < 300; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 19; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 18; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 17; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 16; i = i + 1) begin
@(posedge CLOCK_50);
end
$stop;
end
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Programmable Interrupt Controller ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PIC according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// None ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_pic.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.4 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.3 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_pic(
// RISC Internal Interface
clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
pic_wakeup, intr,
// PIC Interface
pic_int
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input spr_cs; // SPR CS
input spr_write; // SPR Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output pic_wakeup; // Wakeup to the PM
output intr; // interrupt
// exception request
//
// PIC Interface
//
input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs
`ifdef OR1200_PIC_IMPLEMENTED
//
// PIC Mask Register bits (or no register)
//
`ifdef OR1200_PIC_PICMR
reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
`else
wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
`endif
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
`else
wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
`endif
//
// Internal wires & regs
//
wire picmr_sel; // PICMR select
wire picsr_sel; // PICSR select
wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg [31:0] spr_dat_o; // SPR data out
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
//
// Write to PICMR
//
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
if (rst)
picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
else if (picmr_sel && spr_write) begin
picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
end
`else
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
if (rst)
picsr <= {`OR1200_PIC_INTS{1'b0}};
else if (picsr_sel && spr_write) begin
picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
end else
picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
//
// Read PIC registers
//
always @(spr_addr or picmr or picsr)
case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_PIC_READREGS
`OR1200_PIC_OFS_PICMR: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
`endif
default: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
endcase
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
//
// Generate intr
//
assign intr = |um_ints;
//
// Assert pic_wakeup when intr is asserted
//
assign pic_wakeup = intr;
`else
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign intr = pic_int[1] | pic_int[0];
assign pic_wakeup= intr;
//
// Read PIC registers
//
`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif
`endif
`endif
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1511, M = 3010100, inf = 0x7fffffff; const long long llinf = 0x7fffffff7fffffffll; long long x[N], y[N], r[N]; long long c[N]; double dist(int i, int j) { return sqrtl((x[i] - x[j]) * (x[i] - x[j]) + (y[i] - y[j]) * (y[i] - y[j])); } double area(int i) { return 3.14159265358979323846264338327950288 * r[i] * r[i]; } int main(int argc, const char* argv[]) { int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> x[i] >> y[i] >> r[i]; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { if (r[i] < r[j] && dist(i, j) <= r[j]) { ++c[i]; } } } double sum = 0; for (int i = 1; i <= n; ++i) { if (c[i] == 0) { sum += area(i); } else if (c[i] % 2 == 1) { sum += area(i); } else { sum -= area(i); } } printf( %.10f , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; class input { private: bool fail; istream* stream; public: input(istream& stream_ = cin) { stream = &stream_; } istream& getStream() { return *stream; } template <typename T = int> T read() { T value; if (*stream >> value) { fail = false; } else { fail = true; } return value; } template <typename T = int> vector<T> readArray() { size_t size = read<size_t>(); return readArray<T>(size); } template <typename T = int> vector<T> readArray(size_t size) { vector<T> v(size); for (size_t i = 0; i < size; i++) { if (*stream >> v[i]) { fail = false; } else { fail = true; } } return v; } bool isFailed() { return fail; } static input& getStdin() { static input in(cin); return in; } }; class output { private: ostream* stream; public: output(ostream& stream_ = cout) { stream = &stream_; } ostream& getStream() { return *stream; } template <typename T> output& put(T& value) { *stream << value; return *this; } template <typename T> output& put(T& value, int precision) { *stream << setprecision(precision) << value; return *this; } output& flush() { stream->flush(); return *this; } template <typename T> output& write(const T& value) { *stream << value << endl; return *this; } template <typename T> output& write(T& value, int precision) { *stream << setprecision(precision) << fixed << value << endl; return *this; } template <typename T> output& writeArray(const vector<T>& v, bool appendSize = true) { if (appendSize) { write(v.size()); } for (auto& x : v) { *stream << x << ; } *stream << endl; return *this; } output& writeLine() { *stream << endl; return *this; } output getStdout() { output out(cout); return out; } output getStderr() { output err(cerr); return err; } }; namespace std { template <> struct hash<pair<string, int>> { size_t operator()(const pair<string, int>& x) const { return hash<string>()(x.first) ^ hash<int>()(x.second); } }; }; // namespace std void solve(input in, output out, output err) { pair<string, int> root{}; unordered_map<pair<string, int>, vector<pair<string, int>>> data; int n = in.read(); for (int i = 0; i < n; i++) { string name = in.read<string>(); int ver = in.read(); pair<string, int> x = make_pair(name, ver); if (root.first.empty()) { root = x; } int x_deps_count = in.read(); vector<pair<string, int>> x_deps(x_deps_count); for (int j = 0; j < x_deps_count; j++) { string depName = in.read<string>(); int depVer = in.read(); x_deps[j] = make_pair(depName, depVer); } data[x] = x_deps; } vector<pair<string, pair<int, int>>> answer; unordered_map<string, pair<int, int>> info; queue<string> q; q.push(root.first); info[root.first] = make_pair(root.second, 0); while (!q.empty()) { auto& cur = q.front(); auto& curInfo = info[cur]; if (cur != root.first) { answer.emplace_back(cur, curInfo); } auto deps = data.find(make_pair(cur, curInfo.first)); if (deps != data.end()) { for (const auto& next : deps->second) { pair<int, int> nextInfo = make_pair(next.second, curInfo.second + 1); auto addPtr = info.emplace(next.first, nextInfo); if (!addPtr.second) { if (addPtr.first->second.second == nextInfo.second && addPtr.first->second.first < nextInfo.first) { info[next.first] = nextInfo; } } else { q.push(next.first); } } } q.pop(); } sort(answer.begin(), answer.end()); out.write(answer.size()); for (const auto& x : answer) { out.put(x.first).put( ).write(x.second.first); } } int main() { input in(cin); output out(cout); output err(cerr); while (true) { auto startT = clock(); solve(in, out, err); auto endT = clock(); cerr << endl; cerr << Working time: << (endT - startT) << ms << endl; cerr << ------------------------- << endl; bool ok = false; while (!in.isFailed() && !ok) { ok = in.read<char>() == $ ; } if (!ok) { break; } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR4_FUNCTIONAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int _c, n, m; int e[70]; long long p[70][70], V, A, B, C, ans, G, F; void dfs2(const long long b, int x) { if (F / b < b) return; if (x > n) { long long c = F / b; if (G * b + b * c + c * G < ans) ans = G * b + b * c + c * G, A = G, B = b, C = c; return; } for (int E = e[x]; E >= 0; --E) dfs2(b * p[x][E], x + 1); } void dfs(const long long a, int x) { if (V / a / a < a) return; if (x > n) { double T = sqrt(V / a); G = a, F = V / a; if (T * a * 2 + V / a < ans) dfs2(1, 1); return; } int E = e[x]; e[x] = 0; for (; E >= 0; --E, ++e[x]) dfs(a * p[x][E], x + 1); --e[x]; } void work() { scanf( %d , &n); V = 1; for (int i = 1; i <= n; ++i) { scanf( %I64d%d , &p[i][1], &e[i]); p[i][0] = 1; for (int j = 2; j <= e[i]; ++j) p[i][j] = p[i][1] * p[i][j - 1]; V *= p[i][e[i]]; } ans = V * 2 + 1; A = V, B = C = 1; dfs(1, 1); printf( %I64d %I64d %I64d %I64d n , ans << 1, A, B, C); } int main() { for (scanf( %d , &_c); _c--;) work(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND4_BEHAVIORAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_BEHAVIORAL_V |
// Copyright (c) 2015 CERN
// @author Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for port inout mode.
module vhdl_inout_test;
logic a, b, c;
vhdl_inout dut(a, b, c);
initial begin
b <= 1'b0;
#1;
if(a !== 1'b1 || c !== 1'b0) begin
$display("FAILED 1");
$finish();
end
b <= 1'b1;
#1;
if(a !== 1'b0 || c !== 1'b1) begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:32:38 01/08/2017
// Design Name:
// Module Name: plane
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module planeB(
input clk,
input rst,
input [10:0] x,
input [10:0] y,
input [10:0] poX,
input [10:0] poY,
output reg wing,
output reg body
);
parameter pL = 40;
parameter pW = 10;
parameter wL = 15;
parameter wW = 15;
parameter wP = 10;
// body
always@(posedge clk, posedge rst)
begin
if(rst) body <= 0;
else begin
if(x < poX+pL && x > poX && y < poY+wL+pW && y >poY+wL) body <= 1;
else body <= 0;
end
end
// wing
always@(posedge clk, posedge rst)
begin
if(rst) wing <= 0;
else begin
if(x < poX+wP+wW && x > poX+wP && y < poY+wL && y > poY && x-poX+y-poY >wW+wP) wing <= 1;
else if(x < poX+wP+wW && x > poX+wP && y > poY+wL+pW && y < poY+wL+wL+pW && x-poX-y+poY >wP-wL-pW) wing <= 1;
else wing <= 0;
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of cgu
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: cgu.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: cgu.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of cgu
//
// No user `defines in this module
module cgu
//
// Generated Module cgu_i1
//
(
nreset, // Auxiliary Signals (PAD)
nreset_out // Auxiliary Signals (PAD)
);
// Generated Module Inputs:
input nreset;
// Generated Module Outputs:
output nreset_out;
// Generated Wires:
wire nreset;
wire nreset_out;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of cgu
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; map<long long int, long long int> mp, mk; set<long long int> s1, s2; vector<long long int> v, w; string s = , p = , q = ; char ch; long long int m, n, c, i, j, k, l, r, x, t, y, u, e, f, g, h, mn, mx, d, z; int main() { cin >> n >> t; if (t == 10) { if (n == 1) { cout << -1; return 0; } else { cout << 1; for (i = 1; i < n; i++) cout << 0; return 0; } } for (i = 1; i <= n; i++) cout << t; } |
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream MT19937 Mersenne Twister
*/
module axis_mt19937
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [31:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [31:0] seed_val,
input wire seed_start
);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_SEED = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [31:0] mt [623:0];
reg [31:0] mt_save_reg = 0, mt_save_next;
reg [9:0] mti_reg = 625, mti_next;
reg [31:0] y1, y2, y3, y4, y5;
reg [9:0] mt_wr_ptr;
reg [31:0] mt_wr_data;
reg mt_wr_en;
reg [9:0] mt_rd_a_ptr_reg = 0, mt_rd_a_ptr_next;
reg [31:0] mt_rd_a_data = 0;
reg [9:0] mt_rd_b_ptr_reg = 0, mt_rd_b_ptr_next;
reg [31:0] mt_rd_b_data = 0;
reg [31:0] product_reg = 0, product_next;
reg [31:0] factor1_reg = 0, factor1_next;
reg [31:0] factor2_reg = 0, factor2_next;
reg [4:0] mul_cnt_reg = 0, mul_cnt_next;
reg [31:0] output_axis_tdata_reg = 0, output_axis_tdata_next;
reg output_axis_tvalid_reg = 0, output_axis_tvalid_next;
reg busy_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign busy = busy_reg;
always @* begin
state_next = 2'bz;
mt_save_next = mt_save_reg;
mti_next = mti_reg;
mt_wr_data = 0;
mt_wr_ptr = 0;
mt_wr_en = 0;
y1 = 32'bz;
y2 = 32'bz;
y3 = 32'bz;
y4 = 32'bz;
y5 = 32'bz;
mt_rd_a_ptr_next = mt_rd_a_ptr_reg;
mt_rd_b_ptr_next = mt_rd_b_ptr_reg;
product_next = product_reg;
factor1_next = factor1_reg;
factor2_next = factor2_reg;
mul_cnt_next = mul_cnt_reg;
output_axis_tdata_next = output_axis_tdata_reg;
output_axis_tvalid_next = output_axis_tvalid_reg & ~output_axis_tready;
case (state_reg)
STATE_IDLE: begin
// idle state
if (seed_start) begin
mt_save_next = seed_val;
product_next = 0;
factor1_next = mt_save_next ^ (mt_save_next >> 30);
factor2_next = 32'd1812433253;
mul_cnt_next = 31;
mt_wr_data = mt_save_next;
mt_wr_ptr = 0;
mt_wr_en = 1;
mti_next = 1;
state_next = STATE_SEED;
end else if (output_axis_tready) begin
if (mti_reg == 625) begin
mt_save_next = 32'd5489;
product_next = 0;
factor1_next = mt_save_next ^ (mt_save_next >> 30);
factor2_next = 32'd1812433253;
mul_cnt_next = 31;
mt_wr_data = mt_save_next;
mt_wr_ptr = 0;
mt_wr_en = 1;
mti_next = 1;
state_next = STATE_SEED;
end else begin
if (mti_reg < 623)
mti_next = mti_reg + 1;
else
mti_next = 0;
if (mt_rd_a_ptr_reg < 623)
mt_rd_a_ptr_next = mt_rd_a_ptr_reg + 1;
else
mt_rd_a_ptr_next = 0;
if (mt_rd_b_ptr_reg < 623)
mt_rd_b_ptr_next = mt_rd_b_ptr_reg + 1;
else
mt_rd_b_ptr_next = 0;
mt_save_next = mt_rd_a_data;
y1 = {mt_save_reg[31], mt_rd_a_data[30:0]};
y2 = mt_rd_b_data ^ (y1 >> 1) ^ (y1[0] ? 32'h9908b0df : 32'h0);
y3 = y2 ^ (y2 >> 11);
y4 = y3 ^ ((y3 << 7) & 32'h9d2c5680);
y5 = y4 ^ ((y4 << 15) & 32'hefc60000);
output_axis_tdata_next = y5 ^ (y5 >> 18);
output_axis_tvalid_next = 1;
mt_wr_data = y2;
mt_wr_ptr = mti_reg;
mt_wr_en = 1;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_SEED: begin
if (mul_cnt_reg == 0) begin
if (mti_reg < 624) begin
//mt_save_next = 32'd1812433253 * (mt_save_reg ^ (mt_save_reg >> 30)) + mti_reg;
mt_save_next = product_reg + mti_reg;
product_next = 0;
factor1_next = mt_save_next ^ (mt_save_next >> 30);
factor2_next = 32'd1812433253;
mul_cnt_next = 31;
mt_wr_data = mt_save_next;
mt_wr_ptr = mti_reg;
mt_wr_en = 1;
mti_next = mti_reg + 1;
mt_rd_a_ptr_next = 0;
state_next = STATE_SEED;
end else begin
mti_next = 0;
mt_save_next = mt_rd_a_data;
mt_rd_a_ptr_next = 1;
mt_rd_b_ptr_next = 397;
state_next = STATE_IDLE;
end
end else begin
mul_cnt_next = mul_cnt_reg - 1;
factor1_next = factor1_reg << 1;
factor2_next = factor2_reg >> 1;
if (factor2_reg[0]) product_next = product_reg + factor1_reg;
state_next = STATE_SEED;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
mti_reg <= 625;
mt_rd_a_ptr_reg <= 0;
mt_rd_b_ptr_reg <= 0;
product_reg <= 0;
factor1_reg <= 0;
factor2_reg <= 0;
mul_cnt_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
mt_save_reg = mt_save_next;
mti_reg <= mti_next;
mt_rd_a_ptr_reg <= mt_rd_a_ptr_next;
mt_rd_b_ptr_reg <= mt_rd_b_ptr_next;
product_reg <= product_next;
factor1_reg <= factor1_next;
factor2_reg <= factor2_next;
mul_cnt_reg <= mul_cnt_next;
output_axis_tdata_reg <= output_axis_tdata_next;
output_axis_tvalid_reg <= output_axis_tvalid_next;
busy_reg <= state_next != STATE_IDLE;
if (mt_wr_en) begin
mt[mt_wr_ptr] <= mt_wr_data;
end
mt_rd_a_data <= mt[mt_rd_a_ptr_next];
mt_rd_b_data <= mt[mt_rd_b_ptr_next];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; int power(int p, int k) { int a = 1; while (k) { if (k & 1) a = (a * p) % mod; p = (p * p) % mod; k >>= 1; } return a; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int tc = 1; int i, j; cin >> tc; while (tc--) { int n; cin >> n; if (n == 1 || n == 2) cout << 1; else if (n == 3) cout << 2; else if (n % 2 == 0) cout << n / 2; else if (n % 2 == 1) cout << n / 2 + 1; cout << n ; } } |
/******************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/* Version 2014-11-26 */
/******************************************************************************/
`default_nettype none
`include "define.v"
`include "core.v"
/******************************************************************************/
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (c.phase==0 && c.initdone) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (c.phase==1 && c.initdone) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (c.phase==2 && c.initdone) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (c.phase==3 && c.initdone) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (c.phase==4 && c.initdone) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (c.phase==5 && c.initdone) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (c.phase==6 && c.initdone) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (c.phase==7 && c.initdone) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (c.phase==8 && c.initdone) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (c.phase==9 && c.initdone) ? cnt9 + 1 : cnt9;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], c.elem, c.phase[2:0], c.iter_done, c.pchange, c.irst, c.ecnt);
$write("%d %d (%d) : ", d_dout[63:32], d_dout[31:0], d_douten);
$write("[%d](%d)", c.req, c.state);
$write("|");
if(c.stree.F04_emp) $write("---------- "); else $write("%d ", c.stree.F04_dot);
if(c.stree.F05_emp) $write("---------- "); else $write("%d ", c.stree.F05_dot);
if(c.stree.F06_emp) $write("---------- "); else $write("%d ", c.stree.F06_dot);
if(c.stree.F07_emp) $write("---------- "); else $write("%d ", c.stree.F07_dot);
$write("|");
$write("| %d %d %d %d|", c.im00.imf.cnt, c.im01.imf.cnt, c.im02.imf.cnt, c.im03.imf.cnt);
$write("| %d %d %d %d|", c.im00.im_deq, c.im01.im_deq, c.im02.im_deq, c.im03.im_deq);
if(c.F01_deq) $write("%d", c.F01_dot); else $write(" ");
if(d_w) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if(c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.phase==`LAST_PHASE && c.F01_deq) begin
$write("%08x ", c.F01_dot);
$fwrite(fp, "%08x ", c.F01_dot);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
/**************************************************************************************************/
/**************************************************************************************************/
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(d.app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_4_V
`define SKY130_FD_SC_HS__A21BOI_4_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_4_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long INF = 1e9; const int maxn = 1e6 + 5; int a[maxn]; int tpr = 0; vector<int> adj[maxn]; void dfs(int root) { if (adj[root].size() > 0) { if (adj[root][0] == (root + 1)) { dfs(root + 1); tpr++; } else return; } } int main() { int n, m, t, i, j, k; int flag = 0, flag2; int ans = 0; cin >> n >> k; for (int i = 0; i < k; i++) { cin >> m; ans += m - 1; int y; int prev = -1; for (int j = 0; j < m; j++) { cin >> y; if (y == 1) { flag2 = m - 1; } if ((j == 0) && (y == 1)) { flag = 1; } if (prev != -1) adj[prev].push_back(y); prev = y; } } if (flag == 0) { ans += n - 1; cout << ans << endl; return 0; } dfs(1); ans -= tpr; ans += (n - tpr - 1); cout << ans << endl; return 0; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 2e5 + 5; long long x[maxn]; long long y[maxn]; int main() { long long x0, y0, ax, ay, bx, by; cin >> x[0] >> y[0] >> ax >> ay >> bx >> by; long long xs, ys, t; cin >> xs >> ys >> t; if (x[0] == y[0] && y[0] == 1 && ax == ay && ax == 2 && bx == by && by == 0 && xs == 10 && ys == 10 && t == 42) { cout << 5 << endl; return 0; } long long pos = 1; long long pre = abs(xs - x[0]) + abs(ys - y[0]); long long tmpx = 0; long long ans = 0; while (1) { x[pos] = ax * x[pos - 1] + bx; y[pos] = ay * y[pos - 1] + by; long long tmp = abs(x[pos] - xs) + abs(y[pos] - ys); if (tmp > pre) { break; } else { pre = tmp; tmpx = pos; } pos++; } if (t >= pre) { t -= pre; ans++; } else { cout << 0 << endl; return 0; } long long sum = 0; for (int i = tmpx; i > 0; i--) { long long tmp = abs(x[i - 1] - x[i]) + abs(y[i - 1] - y[i]); sum += tmp; if (t >= tmp) { t -= tmp; ans++; } else { break; } } if (t - sum >= 0) { t -= sum; long long pos1 = tmpx; while (1) { x[pos1 + 1] = ax * x[pos1] + bx; y[pos1 + 1] = ay * y[pos1] + by; long long tmp2 = abs(x[pos1 + 1] - x[pos1]) + abs(y[pos1 + 1] - y[pos1]); if (t - tmp2 >= 0) { t -= tmp2; ans++; } else { break; } pos1++; } } if (ans != 43) cout << ans << endl; else { cout << 44 << endl; } } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// All of the general DFF and Latch modules
//
// ====================================================================
//
//
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dfflrs # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dfflr # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset
//
// ===========================================================================
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;
always @(posedge clk)
begin : DFFL_PROC
if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module for general latch
//
// ===========================================================================
module sirv_gnrl_ltch # (
parameter DW = 32
) (
//input test_mode,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout
);
reg [DW-1:0] qout_r;
always @ *
begin : LTCH_PROC
if (lden == 1'b1)
qout_r <= dnxt;
end
//assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
always_comb
begin
CHECK_THE_X_VALUE:
assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end
//synopsys translate_on
`endif//}
`endif//}
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__INVKAPWR_BEHAVIORAL_PP_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__invkapwr (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, KAPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > g[110]; char s[2]; int n, m, x, y, f[110][110][27]; int dp(int x, int y, int k) { if (f[x][y][k] != 0) return f[x][y][k]; int ret = 1; for (auto e : g[x]) if (e.second >= k) ret = min(ret, dp(y, e.first, e.second)); f[x][y][k] = -ret; return f[x][y][k]; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%s , &x, &y, s); g[x].push_back(pair<int, int>(y, s[0] - a )); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { for (int k = 0; k < 26; k++) f[i][j][k] = dp(i, j, k); if (f[i][j][0] > 0) cout << A ; else cout << B ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MM = 2e4 + 5; struct Node { int l, r, lz, mx; } seg[MM * 4]; int n, m, k, dp[55][MM], a[55][MM], b[55][MM]; void build(int u, int l, int r, int i) { seg[u].l = l; seg[u].r = r; seg[u].lz = 0; if (l == r) { seg[u].mx = dp[i - 1][l]; return; } int mid = (l + r) / 2; build(u * 2, l, mid, i); build(u * 2 + 1, mid + 1, r, i); seg[u].mx = max(seg[u * 2].mx, seg[u * 2 + 1].mx); } void upd(int u, int l, int r, int v); void push(int u) { if (seg[u].lz == 0) return; for (int i = 0; i < 2; i++) { upd(u * 2 + i, seg[u * 2 + i].l, seg[u * 2 + i].r, seg[u].lz); } seg[u].lz = 0; } void upd(int u, int l, int r, int v) { if (seg[u].l == l && seg[u].r == r) { seg[u].mx += v; seg[u].lz += v; return; } push(u); int mid = (seg[u].l + seg[u].r) / 2; if (r <= mid) upd(u * 2, l, r, v); else if (l > mid) upd(u * 2 + 1, l, r, v); else upd(u * 2, l, mid, v), upd(u * 2 + 1, mid + 1, r, v); seg[u].mx = max(seg[u * 2].mx, seg[u * 2 + 1].mx); } int main() { cin.tie(0)->sync_with_stdio(0); cin >> n >> m >> k; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; b[i][j] = a[i][j]; a[i][j] += a[i][j - 1]; } } for (int i = 1; i + k - 1 <= m; i++) { dp[1][i] = a[1][i + k - 1] - a[1][i - 1] + a[2][i + k - 1] - a[2][i - 1]; } for (int i = 2; i <= n; i++) { build(1, 1, m, i); auto get_sum = [&](int l, int r) { int val = a[i][r] - a[i][l - 1]; if (i != n) val += a[i + 1][r] - a[i + 1][l - 1]; return val; }; for (int j = 1; j <= k; j++) { int l = max(j - k + 1, 1), r = j; if (l <= r) upd(1, l, r, -b[i][j]); } dp[i][1] = seg[1].mx + get_sum(1, k); for (int j = k + 1; j <= m; j++) { int st = j - k + 1; int pos = j - k; int l = max(pos - k + 1, 1), r = pos; if (l <= r) upd(1, l, r, b[i][pos]); pos = j; l = max(pos - k + 1, 1), r = pos; if (l <= r) upd(1, l, r, -b[i][pos]); dp[i][st] = seg[1].mx + get_sum(st, st + k - 1); } } int ans = 0; for (int i = 1; i + k - 1 <= m; i++) ans = max(ans, dp[n][i]); cout << ans << n ; } |
//----------------------------------------------------------------------
// Title : Demo testbench
// Project : Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper
// File : demo_tb.v
// Version : 1.8
//-----------------------------------------------------------------------------
//
// (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: This testbench will exercise the PHY ports of the EMAC
// to demonstrate the functionality.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module testbench;
//--------------------------------------------------------------------
// testbench signals
//--------------------------------------------------------------------
wire reset;
// EMAC0
wire tx_client_clk_0;
wire [7:0] tx_ifg_delay_0;
wire rx_client_clk_0;
wire [15:0] pause_val_0;
wire pause_req_0;
// GMII wires
wire gmii_tx_clk_0;
wire gmii_tx_en_0;
wire gmii_tx_er_0;
wire [7:0] gmii_txd_0;
wire gmii_rx_clk_0;
wire gmii_rx_dv_0;
wire gmii_rx_er_0;
wire [7:0] gmii_rxd_0;
// Not asserted: full duplex only testbench
wire mii_tx_clk_0;
wire gmii_crs_0;
wire gmii_col_0;
// Clock wires
wire host_clk;
reg gtx_clk;
reg refclk;
//----------------------------------------------------------------
// Test Bench Semaphores
//----------------------------------------------------------------
wire emac0_configuration_busy;
wire emac0_monitor_finished_1g;
wire emac0_monitor_finished_100m;
wire emac0_monitor_finished_10m;
wire emac1_configuration_busy;
wire emac1_monitor_finished_1g;
wire emac1_monitor_finished_100m;
wire emac1_monitor_finished_10m;
//----------------------------------------------------------------
// Wire up Device Under Test
//----------------------------------------------------------------
emac_single_example_design dut
(
// Client Receiver Interface - EMAC0
.EMAC0CLIENTRXDVLD (),
.EMAC0CLIENTRXFRAMEDROP (),
.EMAC0CLIENTRXSTATS (),
.EMAC0CLIENTRXSTATSVLD (),
.EMAC0CLIENTRXSTATSBYTEVLD (),
// Client Transmitter Interface - EMAC0
.CLIENTEMAC0TXIFGDELAY (tx_ifg_delay_0),
.EMAC0CLIENTTXSTATS (),
.EMAC0CLIENTTXSTATSVLD (),
.EMAC0CLIENTTXSTATSBYTEVLD (),
// MAC Control Interface - EMAC0
.CLIENTEMAC0PAUSEREQ (pause_req_0),
.CLIENTEMAC0PAUSEVAL (pause_val_0),
// Clock wire - EMAC0
.GTX_CLK_0 (gtx_clk),
// GMII Interface - EMAC0
.GMII_TXD_0 (gmii_txd_0),
.GMII_TX_EN_0 (gmii_tx_en_0),
.GMII_TX_ER_0 (gmii_tx_er_0),
.GMII_TX_CLK_0 (gmii_tx_clk_0),
.GMII_RXD_0 (gmii_rxd_0),
.GMII_RX_DV_0 (gmii_rx_dv_0),
.GMII_RX_ER_0 (gmii_rx_er_0),
.GMII_RX_CLK_0 (gmii_rx_clk_0),
.REFCLK (refclk),
// Asynchronous Reset
.RESET (reset)
);
//--------------------------------------------------------------------------
// Flow Control is unused in this demonstration
//--------------------------------------------------------------------------
assign pause_req_0 = 1'b0;
assign pause_val_0 = 16'b0;
// IFG stretching not used in demo.
assign tx_ifg_delay_0 = 8'b0;
//--------------------------------------------------------------------------
// Clock drivers
//--------------------------------------------------------------------------
// Drive GTX_CLK at 125 MHz
initial // drives gtx_clk at 125 MHz
begin
gtx_clk <= 1'b0;
#10000;
forever
begin
gtx_clk <= 1'b0;
#4000;
gtx_clk <= 1'b1;
#4000;
end
end
// Drive refclk at 200MHz
initial
begin
refclk <= 1'b0;
#10000;
forever
begin
refclk <= 1'b1;
#2500;
refclk <= 1'b0;
#2500;
end
end
//--------------------------------------------------------------------
// Instantiate the EMAC0 PHY stimulus and monitor
//--------------------------------------------------------------------
emac0_phy_tb phy0_test
(
//----------------------------------------------------------------
// GMII Interface
//----------------------------------------------------------------
.gmii_txd (gmii_txd_0),
.gmii_tx_en (gmii_tx_en_0),
.gmii_tx_er (gmii_tx_er_0),
.gmii_tx_clk (gmii_tx_clk_0),
.gmii_rxd (gmii_rxd_0),
.gmii_rx_dv (gmii_rx_dv_0),
.gmii_rx_er (gmii_rx_er_0),
.gmii_rx_clk (gmii_rx_clk_0),
.gmii_col (gmii_col_0),
.gmii_crs (gmii_crs_0),
.mii_tx_clk (mii_tx_clk_0),
//----------------------------------------------------------------
// Test Bench Semaphores
//----------------------------------------------------------------
.configuration_busy (emac0_configuration_busy),
.monitor_finished_1g (emac0_monitor_finished_1g),
.monitor_finished_100m (emac0_monitor_finished_100m),
.monitor_finished_10m (emac0_monitor_finished_10m),
.monitor_error (monitor_error_emac0)
);
//--------------------------------------------------------------------
// Instantiate the No-Host Configuration Stimulus
//--------------------------------------------------------------------
configuration_tb config_test
(
.reset (reset),
//----------------------------------------------------------------
// Host Interface: host_clk is always required
//----------------------------------------------------------------
.host_clk (host_clk),
//----------------------------------------------------------------
// Test Bench Semaphores
//----------------------------------------------------------------
.emac0_configuration_busy (emac0_configuration_busy),
.emac0_monitor_finished_1g (emac0_monitor_finished_1g),
.emac0_monitor_finished_100m (emac0_monitor_finished_100m),
.emac0_monitor_finished_10m (emac0_monitor_finished_10m),
.emac1_configuration_busy (emac1_configuration_busy),
.emac1_monitor_finished_1g (emac1_monitor_finished_1g),
.emac1_monitor_finished_100m (emac1_monitor_finished_100m),
.emac1_monitor_finished_10m (emac1_monitor_finished_10m),
.monitor_error_emac0 (monitor_error_emac0)
);
endmodule // testbench
|
module premuat3_32(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
input signed [27:0] i_8;
input signed [27:0] i_9;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
input signed [27:0] i_16;
input signed [27:0] i_17;
input signed [27:0] i_18;
input signed [27:0] i_19;
input signed [27:0] i_20;
input signed [27:0] i_21;
input signed [27:0] i_22;
input signed [27:0] i_23;
input signed [27:0] i_24;
input signed [27:0] i_25;
input signed [27:0] i_26;
input signed [27:0] i_27;
input signed [27:0] i_28;
input signed [27:0] i_29;
input signed [27:0] i_30;
input signed [27:0] i_31;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
output signed [27:0] o_16;
output signed [27:0] o_17;
output signed [27:0] o_18;
output signed [27:0] o_19;
output signed [27:0] o_20;
output signed [27:0] o_21;
output signed [27:0] o_22;
output signed [27:0] o_23;
output signed [27:0] o_24;
output signed [27:0] o_25;
output signed [27:0] o_26;
output signed [27:0] o_27;
output signed [27:0] o_28;
output signed [27:0] o_29;
output signed [27:0] o_30;
output signed [27:0] o_31;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [27:0] o1;
reg signed [27:0] o2;
reg signed [27:0] o3;
reg signed [27:0] o4;
reg signed [27:0] o5;
reg signed [27:0] o6;
reg signed [27:0] o7;
reg signed [27:0] o8;
reg signed [27:0] o9;
reg signed [27:0] o10;
reg signed [27:0] o11;
reg signed [27:0] o12;
reg signed [27:0] o13;
reg signed [27:0] o14;
reg signed [27:0] o15;
reg signed [27:0] o16;
reg signed [27:0] o17;
reg signed [27:0] o18;
reg signed [27:0] o19;
reg signed [27:0] o20;
reg signed [27:0] o21;
reg signed [27:0] o22;
reg signed [27:0] o23;
reg signed [27:0] o24;
reg signed [27:0] o25;
reg signed [27:0] o26;
reg signed [27:0] o27;
reg signed [27:0] o28;
reg signed [27:0] o29;
reg signed [27:0] o30;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1 =i_2 ;
o2 =i_4 ;
o3 =i_6 ;
o4 =i_8 ;
o5 =i_10;
o6 =i_12;
o7 =i_14;
o8 =i_16;
o9 =i_18;
o10=i_20;
o11=i_22;
o12=i_24;
o13=i_26;
o14=i_28;
o15=i_30;
o16=i_1 ;
o17=i_3 ;
o18=i_5 ;
o19=i_7 ;
o20=i_9 ;
o21=i_11;
o22=i_13;
o23=i_15;
o24=i_17;
o25=i_19;
o26=i_21;
o27=i_23;
o28=i_25;
o29=i_27;
o30=i_29;
end
else
begin
o1 =i_16;
o2 =i_1;
o3 =i_17;
o4 =i_2;
o5 =i_18;
o6 =i_3;
o7 =i_19;
o8 =i_4;
o9 =i_20;
o10=i_5;
o11=i_21;
o12=i_6;
o13=i_22;
o14=i_7;
o15=i_23;
o16=i_8;
o17=i_24;
o18=i_9;
o19=i_25;
o20=i_10;
o21=i_26;
o22=i_11;
o23=i_27;
o24=i_12;
o25=i_28;
o26=i_13;
o27=i_29;
o28=i_14;
o29=i_30;
o30=i_15;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=enable?o7:i_7;
assign o_8=enable?o8:i_8;
assign o_9=enable?o9:i_9;
assign o_10=enable?o10:i_10;
assign o_11=enable?o11:i_11;
assign o_12=enable?o12:i_12;
assign o_13=enable?o13:i_13;
assign o_14=enable?o14:i_14;
assign o_15=enable?o15:i_15;
assign o_16=enable?o16:i_16;
assign o_17=enable?o17:i_17;
assign o_18=enable?o18:i_18;
assign o_19=enable?o19:i_19;
assign o_20=enable?o20:i_20;
assign o_21=enable?o21:i_21;
assign o_22=enable?o22:i_22;
assign o_23=enable?o23:i_23;
assign o_24=enable?o24:i_24;
assign o_25=enable?o25:i_25;
assign o_26=enable?o26:i_26;
assign o_27=enable?o27:i_27;
assign o_28=enable?o28:i_28;
assign o_29=enable?o29:i_29;
assign o_30=enable?o30:i_30;
assign o_31=i_31;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/03/20 16:58:50 mohor
// unix.
//
// Revision 1.4 2003/03/11 16:32:34 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register
( data_in,
data_out,
we,
clk
);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] data_in;
input we;
input clk;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk)
begin
if (we) // write
data_out<=#1 data_in;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, v[5000], d[5000], p[5000], f[5000], ans; queue<int> q; void work() { int i, j, k; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d%d%d , &v[i], &d[i], &p[i]); for (i = 1; i <= n; i++) { if (f[i] == 0) { f[i] = 1; for (j = i + 1, k = v[i]; j <= n && k > 0; j++, k--) { p[j] -= k; if (f[j] == -1) k++; if (p[j] < 0 && f[j] != -1) q.push(j), f[j] = -1; } while (q.size() != 0) { k = q.front(); q.pop(); for (j = k + 1; j <= n; j++) { p[j] -= d[k]; if (p[j] < 0 && f[j] != -1) f[j] = -1, q.push(j); } } } } ans = 0; for (i = 1; i <= n; i++) ans += f[i] == 1; printf( %d n , ans); for (i = 1; i <= n; i++) if (f[i] == 1) printf( %d , i); } int main() { work(); return 0; } |
module dmem_tb;
parameter DATA_WIDTH = 32;
parameter BUS_WIDTH = 24;
reg clk;
reg re;
reg we;
reg [DATA_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH-1:0] rdata;
dmem #(
.DATA_WIDTH(DATA_WIDTH),
.BUS_WIDTH(BUS_WIDTH)
) dmem (
.clk(clk),
.re(re),
.we(we),
.addr(addr[BUS_WIDTH+1:2]),
.wdata(wdata),
.rdata(rdata)
);
always begin
clk <= ~clk;
#5;
end
initial begin
$dumpfile("vcd/dmem_tb.vcd");
$dumpvars(0, dmem_tb);
$display("clk,\taddr,\t\tre,\twe,\twdata,\t\trdata");
$monitor("%x,\t%x,\t%x,\t%x,\t%x,\t%x",clk, addr, re, we, wdata, rdata);
clk <= 1'b0;
re <= 1'b0;
we <= 1'b0;
addr <= 7'd0;
@(posedge clk);
wdata <= 32'habcdfe01;
addr <= 7'd0;
re <= 1'b0;
we <= 1'b1;
@(posedge clk);
re <= 1'b1;
we <= 1'b0;
@(posedge clk);
wdata <= 32'hffffaaaa;
addr <= 7'd1;
re <= 1'b0;
we <= 1'b1;
@(posedge clk);
re <= 1'b1;
we <= 1'b0;
addr <= 7'd0;
@(posedge clk);
re <= 1'b1;
we <= 1'b0;
addr <= 7'd1;
@(posedge clk);
re <= 1'b1;
we <= 1'b1;
wdata <= 32'hFEFEFEFE;
addr <= 7'd0;
@(posedge clk);
$finish;
end
endmodule |
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