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#include <bits/stdc++.h> using namespace std; template <class Flow = long long, class Cost = long long> struct MinCostFlow { const Flow INF_FLOW = 1000111000; const Cost INF_COST = 1000111000111000LL; long long n, t, S, T; Flow totalFlow; Cost totalCost; vector<long long> last, visited; vector<Cost> dis; struct Edge { long long to; Flow cap; Cost cost; long long ackjalscjaowjico; Edge(long long to, Flow cap, Cost cost, long long ackjalscjaowjico) : to(to), cap(cap), cost(cost), ackjalscjaowjico(ackjalscjaowjico) {} }; vector<Edge> edges; MinCostFlow(long long n) : n(n), t(0), totalFlow(0), totalCost(0), last(n, -1), visited(n, 0), dis(n, 0) { edges.clear(); } long long addEdge(long long from, long long to, Flow cap, Cost cost) { edges.push_back(Edge(to, cap, cost, last[from])); last[from] = t++; edges.push_back(Edge(from, 0, -cost, last[to])); last[to] = t++; return t - 2; } pair<Flow, Cost> minCostFlow(long long _S, long long _T) { S = _S; T = _T; SPFA(); while (1) { while (1) { for (long long i = 0, _i = (n); i < _i; ++i) visited[i] = 0; if (!findFlow(S, INF_FLOW)) break; } if (!modifyLabel()) break; } return make_pair(totalFlow, totalCost); } private: void SPFA() { for (long long i = 0, _i = (n); i < _i; ++i) dis[i] = INF_COST; priority_queue<pair<Cost, long long> > Q; Q.push(make_pair(dis[S] = 0, S)); while (!Q.empty()) { long long x = Q.top().second; Cost d = -Q.top().first; Q.pop(); if (dis[x] != d) continue; for (long long it = last[x]; it >= 0; it = edges[it].ackjalscjaowjico) if (edges[it].cap > 0 && dis[edges[it].to] > d + edges[it].cost) Q.push(make_pair(-(dis[edges[it].to] = d + edges[it].cost), edges[it].to)); } Cost disT = dis[T]; for (long long i = 0, _i = (n); i < _i; ++i) dis[i] = disT - dis[i]; } Flow findFlow(long long x, Flow flow) { if (x == T) { totalCost += dis[S] * flow; totalFlow += flow; return flow; } visited[x] = 1; Flow now = flow; for (long long it = last[x]; it >= 0; it = edges[it].ackjalscjaowjico) if (edges[it].cap && !visited[edges[it].to] && dis[edges[it].to] + edges[it].cost == dis[x]) { Flow tmp = findFlow(edges[it].to, min(now, edges[it].cap)); edges[it].cap -= tmp; edges[it ^ 1].cap += tmp; now -= tmp; if (!now) break; } return flow - now; } bool modifyLabel() { Cost d = INF_COST; for (long long i = 0, _i = (n); i < _i; ++i) if (visited[i]) for (long long it = last[i]; it >= 0; it = edges[it].ackjalscjaowjico) if (edges[it].cap && !visited[edges[it].to]) d = min(d, dis[edges[it].to] + edges[it].cost - dis[i]); if (d == INF_COST) return false; for (long long i = 0, _i = (n); i < _i; ++i) if (visited[i]) dis[i] += d; return true; } }; signed main() { long long n; cin >> n; string s; cin >> s; s = + s; MinCostFlow<long long, long long> mcmf(n + 2); long long m; cin >> m; while (m--) { string t; long long cost; cin >> t >> cost; for (long long i = 1; i + t.size() <= s.size(); i++) { if (s.substr(i, t.size()) == t) mcmf.addEdge(i, i + t.size(), 1, -cost); } } long long x; cin >> x; for (long long i = 0; i <= n; i++) { mcmf.addEdge(i, i + 1, x, 0); } auto ans = mcmf.minCostFlow(0, n + 1); cout << -ans.second; } |
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long n) { if (a == 0) return 0; if (a == 1 || n == 0) return 1; if (n == 1) return a % 1000000007; long long t = power(a, n / 2); t = t * t % 1000000007; if (n & 1) return t * a % 1000000007; return t; } int popcount(long long a) { int c = 0; while (a) { c++; a -= a & -a; } return c; } void factorize(int a) {} void update(int tree[], int idx, int val, int maxval) { for (; idx <= maxval; idx += idx & -idx) { tree[idx] += val; } } int read(int tree[], int idx) { long long sum = 0; for (; idx > 0; idx -= idx & -idx) { sum += tree[idx]; } return sum; } struct node2 { int id, val; node2() { static int ctx = 1; id = ctx++; }; node2(int a, int b = 0, int c = 0, int d = 0, int e = 0, int f = 0) { val = a; } }; struct comp2 { bool operator()(int a, int b) { return b < a; } }; bool cmp2(int a, int b) { return b < a; } struct node { int id, val; node() { static int ctx = 1; id = ctx++; }; node(int a, int b = 0, int c = 0, int d = 0, int e = 0, int f = 0) { val = a; } }; struct comp { bool operator()(int a, int b) { return b < a; } }; bool cmp(int a, int b) { return b < a; } int n, m, a[100009], b, c, d, k, h, w, x, y, p, q, t, res, ma, mi, T, act = 0, pas = 1, cur, flag, now; int bit[33][100009]; long long ans, dp[100009][2]; char s[1]; double e, f, z; vector<int> v[100009], vec; set<int> sett; map<int, int> mapp; void print() {} void print2() {} void input() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 1; i < n + 1; i++) cin >> a[i]; for (int i = 1; i < n; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } } void init() { for (int pos = 0; pos < 30; pos++) { for (int i = 1; i < n + 1; i++) { bit[pos][i] = (((1 << pos) & a[i]) != 0); } } } void calc(int id, int par, int a[]) { dp[id][a[id]] = 1; for (auto u : v[id]) { if (u == par) continue; calc(u, id, a); if (a[id]) { dp[id][1] += dp[u][0]; dp[id][0] += dp[u][1]; ans += T * (dp[id][1] - dp[u][0]) * dp[u][0]; ans += T * (dp[id][0] - dp[u][1]) * dp[u][1]; } else { dp[id][1] += dp[u][1]; dp[id][0] += dp[u][0]; ans += T * (dp[id][1] - dp[u][1]) * dp[u][0]; ans += T * (dp[id][0] - dp[u][0]) * dp[u][1]; } } ans += T * a[id]; } void solve() { init(); int l = 0; int r = 29; for (int pos = l; pos < r + 1; pos++) { T = 1 << pos; memset(dp, 0, sizeof(dp)); calc(1, 0, bit[pos]); } } void output() { cout << ans; } int main() { input(); solve(); output(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
//bug991
module t (/*AUTOARG*/);
logic [31:0] array_assign [3:0];
logic [31:0] array_other [3:0];
logic [31:0] larray_assign [0:3];
logic [31:0] larray_other [0:3];
initial begin
array_assign[0] = 32'd1;
array_assign[3:1] = '{32'd4, 32'd3, 32'd2};
array_other[0] = array_assign[0]+10;
array_other[3:1] = array_assign[3:1];
if (array_other[0] != 11) $stop;
if (array_other[1] != 2) $stop;
if (array_other[2] != 3) $stop;
if (array_other[3] != 4) $stop;
larray_assign[0] = 32'd1;
larray_assign[1:3] = '{32'd4, 32'd3, 32'd2};
larray_other[0] = larray_assign[0]+10;
larray_other[1:3] = larray_assign[1:3];
if (larray_other[0] != 11) $stop;
if (larray_other[1] != 4) $stop;
if (larray_other[2] != 3) $stop;
if (larray_other[3] != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, p, c = 0; cin >> n >> k; vector<int> v; map<int, int> m; for (int i = 1; i <= n; i++) { cin >> p; v.push_back(p); m[p]++; } if (m[k] == 0) v.push_back(k), c++, n++; sort(v.begin(), v.end()); while (1) { int x = (n + 1) / 2; if (v[x - 1] == k) { cout << c; return 0; } else if (v[x - 1] < k) { v.push_back(100000); n++; c++; } else v.push_back(1), n++, c++; sort(v.begin(), v.end()); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A22O_FUNCTIONAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a22o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_FUNCTIONAL_PP_V |
(** * Introduction *)
Set Warnings "-extraction-opaque-accessed,-extraction".
Set Warnings "-notation-overridden,-parsing".
From QuickChick Require Import QuickChick.
Require Import List ZArith. Import ListNotations.
(* ################################################################# *)
(** * A First Taste of Testing *)
(** Consider the following definition of a function [remove], which
takes a natural number [x] and a list of nats [l] and removes [x]
from the list. *)
Fixpoint remove (x : nat) (l : list nat) : list nat :=
match l with
| [] => []
| h::t => if h =? x then t else h :: remove x t
end.
(** One possible specification for [remove] might be this property... *)
Conjecture removeP : forall x l, ~ (In x (remove x l)).
(** ...which says that [x] never occurs in the result of [remove x l]
for any [x] and [l]. ([Conjecture foo...] means the same as
[Theorem foo... Admitted.] Formally, [foo] is treated as an
axiom.) *)
(** Sadly, this property is false, as we would (eventually) discover
if we were to try to prove it. *)
(** A different -- perhaps much more efficient -- way to discover
the discrepancy between the definition and specification is
to _test_ it: *)
(* QuickChick removeP. *)
(** (Try uncommenting and evaluating the previous line.) *)
(** The [QuickChick] command takes an "executable" property (we'll see
later exactly what this means) and attempts to falsify it by
running it on many randomly generated inputs, resulting in output
like this:
0
[0, 0]
Failed! After 17 tests and 12 shrinks
This means that, if we run [remove] with [x] being [0] and [l]
being the two-element list containing two zeros, then the property
[removeP] fails. *)
(** With this example in hand, we can see that the [then] branch
of [remove] fails to make a recursive call, which means that only
one occurence of [x] will be deleted. The last line of the output
records that it took 17 tests to identify some fault-inducing
input and 12 "shrinks" to reduce it to a minimal
counterexample. *)
(** **** Exercise: 1 star (insertP) *)
(** Here is a somewhat mangled definition of a function for inserting a
new element into a sorted list of numbers: *)
Fixpoint insert x l :=
match l with
| [] => [x]
| y::t => if y <? x then insert x t else y::t
end.
(** Write a property that says "inserting a number [x] into a list [l]
always yields a list containing [x]." Make sure QuickChick finds
a counterexample. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (insertP2) *)
(** Translate the following claim into a [Conjecture] (using [In] for
list membership): "For all numbers [x] and [y] and lists [l], if
[y] is in [l] then it is also in the list that results from
inserting [x] into [l]" (i.e., [insert] preserves all the elements
already in [l]). Make sure QuickChick finds a counterexample. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Overview *)
(** Property-based random testing involves four basic ingredients:
- an _executable property_ like [removeP],
- _generators_ for random elements of the types of the inputs to
the property (here, numbers and lists of numbers),
- _printers_ for converting data structures like numbers and lists
to strings when reporting counterexamples, and
- _shrinkers_, which are used to minimize counterexamples. *)
(** We will delve into each of these in detail later on, but first we
need to make a digression to explain Coq's support for
_typeclasses_, which QuickChick uses extensively both internally
and in its programmatic interface to users. This is the
[Typeclasses] chapter.
In the [QC] chapter we'll cover the core concepts and
features of QuickChick itself.
The [TImp] chapter develops a small case study around a typed
variant of the Imp language.
The [QuickChickTool] chapter presents a command line tool,
_quickChick_, that supports larger-scale projects and mutation
testing.
The [QuickChickInterface] chapter is a complete reference
manual for QuickChick.
Finally, the [Postscript] chapter gives some suggestions for
further reading. *)
(* Tue Oct 9 11:47:30 EDT 2018 *)
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous FIFO (64 bit datapath)
*/
module axis_async_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
/*
* AXI input
*/
input wire input_clk,
input wire input_rst,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
input wire output_rst,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1;
reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray[ADDR_WIDTH] != rd_ptr_gray_sync2[ADDR_WIDTH]) &&
(wr_ptr_gray[ADDR_WIDTH-1] != rd_ptr_gray_sync2[ADDR_WIDTH-1]) &&
(wr_ptr_gray[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray == wr_ptr_gray_sync2;
wire write = input_axis_tvalid & ~full;
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_out_reg;
assign input_axis_tready = ~full;
assign output_axis_tvalid = output_axis_tvalid_reg;
// reset synchronization
always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
input_rst_sync1 <= 1;
input_rst_sync2 <= 1;
end else begin
input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1;
end
end
always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
output_rst_sync1 <= 1;
output_rst_sync2 <= 1;
end else begin
output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1;
end
end
// write
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
end else if (write) begin
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_next = wr_ptr + 1;
wr_ptr <= wr_ptr_next;
wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0;
end else begin
rd_ptr_gray_sync1 <= rd_ptr_gray;
rd_ptr_gray_sync2 <= rd_ptr_gray_sync1;
end
end
// read
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;
rd_ptr <= rd_ptr_next;
rd_ptr_gray <= rd_ptr_next ^ (rd_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
// source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; long long add(long long x, long long y, long long CMOD = MOD) { return (x + y + CMOD + CMOD) % CMOD; } long long mult(long long x, long long y, long long CMOD = MOD) { return add(x, 0) * add(y, 0) % CMOD; } long long fast_expo(long long x, long long y, long long CMOD = MOD) { if (x == 0) return 0; if (y == 0) return 1; long long ans = fast_expo(x, y / 2, CMOD); ans = mult(ans, ans, CMOD); if (y & 1) ans = mult(ans, x, CMOD); return ans; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long gen(long long x, long long y) { if (x == y) return x; return x + rng() % (y - x + 1); } const int TAM = 2e5 + 100; const long long INF = LLONG_MAX / 4; long long fact[TAM]; long long ifact[TAM]; long long n, m; void pre() { fact[0] = 1; for (int i = 1; i < TAM; i++) fact[i] = mult(fact[i - 1], i); for (int i = 0; i < TAM; i++) ifact[i] = fast_expo(fact[i], MOD - 2); } long long comb(long long x, long long y) { return mult(fact[x], mult(ifact[y], ifact[x - y])); } int main() { pre(); cin >> n >> m; if (n == 2) { puts( 0 ); return 0; } long long ans = 0; for (long long x = n - 1; x <= m; x++) { long long factor = mult(comb(x - 2, n - 3), fast_expo(2, n - 3)); ans = add(ans, mult(x - 1, factor)); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, arr[101], color, maxi, mini = 101; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> color; for (int i = 0; i < n; i++) { cin >> arr[i]; mini = min(mini, arr[i]); maxi = max(maxi, arr[i]); } if (maxi - mini > color) { cout << NO n ; return 0; } cout << YES n ; for (int i = 0; i < n; i++) { int j = 1; while (arr[i]--) { cout << j << ; if (j == color) j = 0; j++; } cout << endl; } return 0; } |
//==============================================================================
// Copyright (C) John-Philip Taylor
//
//
// This file is part of a library
//
// This file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>
//==============================================================================
module UART_Sender #(
parameter N = 5,
parameter Full = 5'd29 // Clk / BAUD - 1
)(
input Clk,
input Reset,
input [7:0]Data,
input Send,
output reg Busy,
output reg Tx // Tx line on the board.
);
//------------------------------------------------------------------------------
reg tSend;
reg [ 7:0]Temp;
reg [N-1:0]Count;
reg [ 2:0]BitCount;
//------------------------------------------------------------------------------
reg [1:0]State;
localparam Idle = 2'b00;
localparam Sending = 2'b01;
localparam StopBit = 2'b11;
localparam Done = 2'b10;
//------------------------------------------------------------------------------
reg tReset;
always @(posedge Clk) begin
tReset <= Reset;
if(tReset) begin
Busy <= 1'b0;
Tx <= 1'b1;
tSend <= 0;
Count <= 0;
BitCount <= 0;
State <= Idle;
//------------------------------------------------------------------------------
end else begin
tSend <= Send;
if(~|Count) begin
case(State)
Idle: begin
if(tSend) begin
Count <= Full;
BitCount <= 3'd7;
{Temp, Tx} <= {Data, 1'b0};
Busy <= 1'b1;
State <= Sending;
end
end
//------------------------------------------------------------------------------
Sending: begin
Count <= Full;
{Temp[6:0], Tx} <= Temp;
if(~|BitCount) State <= StopBit;
BitCount <= BitCount - 1'b1;
end
//------------------------------------------------------------------------------
StopBit: begin
Tx <= 1'b1;
Count <= Full;
State <= Done;
end
//------------------------------------------------------------------------------
Done: begin
if(~tSend) begin
Busy <= 1'b0;
Count <= 0;
State <= Idle;
end
end
//------------------------------------------------------------------------------
default:;
endcase
end else begin
Count <= Count - 1'b1;
end
end
end
//------------------------------------------------------------------------------
endmodule
|
#include <bits/stdc++.h> const int MAXN = 100100; char S[MAXN]; char T[MAXN]; int aS[MAXN], aT[MAXN]; int bS[MAXN], bT[MAXN]; bool go() { int leftS, rightS, leftT, rightT; scanf( %d %d %d %d , &leftS, &rightS, &leftT, &rightT); int lengthS = rightS - leftS + 1; int lengthT = rightT - leftT + 1; int as = aS[rightS]; if (as > lengthS) as = lengthS; int at = aT[rightT]; if (at > lengthT) at = lengthT; int bs = bS[rightS] - bS[leftS - 1]; int bt = bT[rightT] - bT[leftT - 1]; if (bs % 2 != bt % 2) { return false; } if (bs > bt) { return false; } if (as < at) { return false; } if (bs == bt) { if (as % 3 != at % 3) { return false; } } else { if (bs == 0 && as == at) { return false; } } return true; } void goA(char *s, int *ar) { int run = 0; for (int i = 1; s[i]; ++i) { if (s[i] == A ) ++run; else run = 0; ar[i] = run; } } void goB(char *s, int *ar) { int run = 0; for (int i = 1; s[i]; ++i) { if (s[i] == B || s[i] == C ) ++run; ar[i] = run; } } int main() { scanf( %s , S + 1); scanf( %s , T + 1); goA(S, aS); goA(T, aT); goB(S, bS); goB(T, bT); int q; scanf( %d , &q); for (int i = 0; i < q; ++i) { if (go()) { printf( 1 ); } else { printf( 0 ); } } printf( n ); } |
#include <bits/stdc++.h> using namespace std; int v[2000]; int a, b, n, res; int main() { scanf( %d %d %d , &n, &a, &b); for (int i = 0; i < n; i++) scanf( %d , &v[i]); sort(v, v + n); int res = v[b] - v[b - 1]; cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int n; int answer = -1; long sum_x[2] = {0}; long sum_y[2] = {0}; int nr[2] = {0}; int i; scanf( %d n , &n); for (i = 0; i < n; i++) { int t, x, y; scanf( %d %d %d n , &t, &x, &y); if (t == 1) { sum_x[0] += x; sum_y[0] += y; nr[0]++; } else { sum_x[1] += x; sum_y[1] += y; nr[1]++; } } for (i = 0; i < 2; i++) { if (sum_x[i] / nr[i] >= 5) printf( LIVE n ); else printf( DEAD n ); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire B1 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int mo = (int)1e9 + 7; const int maxn = 1000010; int n; long long fac[maxn], ans; int a[maxn], num[maxn], num1[maxn], pos[maxn], mul[maxn]; int pre[maxn], ne[maxn]; vector<int> v[maxn]; inline void init() { fac[0] = 1; for (int i = 1; i <= n + 2; ++i) fac[i] = fac[i - 1] * i % mo, mul[i] = 1; for (int i = 2; i <= n; ++i) { if (!v[i].size()) { num[n / i]++; pos[i] = n / i; for (int j = i; j <= n; j += i) v[j].push_back(i), mul[j] *= i; } } for (int i = 1; i <= n; ++i) num1[mul[i]]++; num[1]++; pos[1] = 1; v[1].push_back(1); } int main() { scanf( %d , &n); init(); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n; ++i) if (a[i]) { num1[mul[a[i]]]--; if (v[a[i]].size() != v[i].size()) return puts( 0 ), 0; for (int j = 0; j < v[i].size() - 1; j++) if (v[a[i]][j] != v[i][j]) return puts( 0 ), 0; long long x = v[a[i]].back(), y = v[i].back(); if (pos[x] != pos[y]) return puts( 0 ), 0; if (pre[x] && pre[x] != y) return puts( 0 ), 0; if (ne[y] && ne[y] != x) return puts( 0 ), 0; if (!pre[x] && !ne[y]) num[pos[x]]--; pre[x] = y; ne[y] = x; } ans = 1; for (int i = 1; i <= n; ++i) ans = ans * fac[num[i]] % mo, ans = ans * fac[num1[i]] % mo; printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 105; char mp[3][N], tmp[3][N], g[55][3][N]; bool vis[55][3][N]; int n, k; void getNext(int id) { memcpy(g[id], mp, sizeof(mp)); for (int i = int(0); i <= int((3) - 1); i++) for (int j = int(1); j <= int(n - 3); j++) tmp[i][j] = mp[i][j + 3]; for (int i = int(0); i <= int((3) - 1); i++) tmp[i][n - 2] = tmp[i][n - 1] = tmp[i][n] = . ; memcpy(mp, tmp, sizeof(tmp)); } int dx[] = {0, -1, 1}, dy[] = {0, 0, 0}; bool good(int now, int x, int y) { return x >= 0 && x < 3 && g[now][x][y] == . && g[now - 1][x][y + 1] == . ; } bool bfs(int sx, int sy) { memset(vis, 0, sizeof(vis)); int now = 0, x = sx, y = sy; queue<int> q; q.push(now), q.push(x); while (q.size()) { now = q.front(); q.pop(); x = q.front(); q.pop(); if (now > 50) { return 1; } for (int i = int(0); i <= int((3) - 1); i++) { if (g[now][x][y + 1] != . ) continue; int tx = x + dx[i]; if (good(now + 1, tx, y)) { if (!vis[now + 1][tx][y]) { q.push(now + 1), q.push(tx); vis[now + 1][tx][y] = 1; } } } } return 0; } int main() { ios::sync_with_stdio(0); int t; cin >> t; while (t--) { cin >> n >> k; for (int i = int(0); i <= int((3) - 1); i++) { cin >> (mp[i] + 1); } int sx, sy; for (int i = int(0); i <= int((3) - 1); i++) { for (int j = int(1); j <= int(n); j++) if (mp[i][j] == s ) { sx = i, sy = j; mp[i][j] = . ; } } for (int i = int(0); i <= int((54) - 1); i++) getNext(i); if (bfs(sx, sy)) puts( YES ); else puts( NO ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int MOD = 1e9 + 7; const int N = 1e6 + 5, M = 1e5 + 10, NM1 = N - 1; long long int OO = 1e18 + 8; int oo = 1e9 + 8; void readFile() {} int n, m, l, r, x, top, arr[N], st[N]; long long int sum[N]; int main() { readFile(); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , arr + i); for (int i = 1; i <= n + 1; i++) { while (arr[i] < arr[st[top]]) { l = st[top] - st[top - 1]; r = i - st[top]; sum[1] += x = arr[st[top--]]; sum[l + 1] -= x; sum[r + 1] -= x; sum[l + r + 1] += x; } st[++top] = i; } for (int i = 1; i <= n; i++) sum[i] += sum[i - 1]; for (int i = 1; i <= n; i++) sum[i] += sum[i - 1]; scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &x); printf( %0.12f n , (double)sum[x] / (n - x + 1.0)); } return 0; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpciexpav_stif_reg_fifo
#(
parameter FIFO_DEPTH = 5,
parameter DATA_WIDTH = 304
)
(
// global signals
input clk,
input rstn,
input srst,
input wrreq,
input rdreq,
input [DATA_WIDTH-1:0] data,
output [DATA_WIDTH-1:0] q,
output reg [3:0] fifo_count
);
reg [DATA_WIDTH-1:0] fifo_reg[FIFO_DEPTH-1:0];
wire [FIFO_DEPTH-1:0] fifo_wrreq;
// fifo word counter
always @(posedge clk or negedge rstn)
begin
if(~rstn)
fifo_count <= 4'h0;
else if (srst)
fifo_count <= 4'h0;
else if (rdreq & ~wrreq)
fifo_count <= fifo_count - 1;
else if(~rdreq & wrreq)
fifo_count <= fifo_count + 1;
end
generate
genvar i;
for(i=0; i< FIFO_DEPTH -1; i=i+1)
begin: register_array
assign fifo_wrreq[i] = wrreq & (fifo_count == i | (fifo_count == i + 1 & rdreq)) ;
always @(posedge clk or negedge rstn)
begin
if(~rstn)
fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if (srst)
fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if(fifo_wrreq[i])
fifo_reg[i] <= data;
else if(rdreq)
fifo_reg[i] <= fifo_reg[i+1];
end
end
endgenerate
/// the last register
assign fifo_wrreq[FIFO_DEPTH-1] = wrreq & (fifo_count == FIFO_DEPTH - 1 | (fifo_count == FIFO_DEPTH & rdreq)) ;
always @(posedge clk or negedge rstn)
begin
if(~rstn)
fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if (srst)
fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if(fifo_wrreq[FIFO_DEPTH-1])
fifo_reg[FIFO_DEPTH-1] <= data;
end
assign q = fifo_reg[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<long long, long long> A[55]; double pos[55][55]; bool comp(pair<long long, long long> a, pair<long long, long long> b) { if (a.first > b.first) return 1; else if (a.first < b.first) return 0; else { return a.second <= b.second; } } bool vis[55][55]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> A[i].first; for (int i = 1; i <= n; ++i) cin >> A[i].second; sort(A + 1, A + n + 1, comp); long long low = 0; long long high = 10000000000000; int count = 10000; while (--count) { long long mid = low + high; mid /= 2.0; for (int i = 0; i <= n; ++i) { for (int j = 0; j <= n; ++j) { vis[i][j] = 0; } } pos[0][0] = 0; vis[0][0] = 1; for (int i = 1; i <= n; ++i) { long long st = A[i].first; int u = i - 1; while (i <= n && A[i].first == st) ++i; --i; int coun = i - u; long long sum[55]; for (int j = u + 1; j <= i; ++j) sum[j - u] = 0; sum[0] = 0; for (int j = u + 1; j <= i; ++j) sum[j - u] = sum[j - u - 1] + A[j].second; long long sum2[55]; for (int j = u + 1; j <= i; ++j) sum2[j - u] = 0; sum2[0] = 0; for (int j = u + 1; j <= i; ++j) sum2[j - u] = sum2[j - u - 1] + A[j].first; for (int j = 0; j <= u; ++j) { for (int l = 0; l <= min(coun, j); ++l) { if (vis[u][j] == 0) continue; int rem = j - l + coun - l; if (vis[i][rem] == 0) { vis[i][rem] = 1; pos[i][rem] = pos[u][j] - (sum[coun] - sum[l]) * mid / 1000.0 + (sum2[coun] - sum2[l]); } else pos[i][rem] = min(pos[i][rem], pos[u][j] - (sum[coun] - sum[l]) * mid / 1000.0 + (sum2[coun] - sum2[l])); } } } bool flag = 0; for (int j = 0; j <= n; ++j) { if (pos[n][j] <= 0 && vis[n][j]) { flag = 1; } } if (flag) { high = mid; } else { low = mid + 1; } } cout << high << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int GCD(int x, int y) { return !y ? x : GCD(y, x % y); } int LCM(int x, int y) { return x * y / GCD(x, y); } long long ceilDivision(long long dividend, long long divisor) { return (dividend + divisor - 1) / divisor; } bool check(pair<long long, int> right, pair<long long, int> left) { return ((left.second > right.second) || (left.second == right.second && left.first > right.first)); } int main() { long long r, avg, sum = 0, target, counter = 0; int n, pointer = 0; cin >> n >> r >> avg; vector<pair<long long, int> > arr(n); target = avg * n; for (int i = 0; i < n; i++) cin >> arr[i].first >> arr[i].second, sum += arr[i].first; if (sum < target) { sort(arr.begin(), arr.end(), check); target -= sum; while (target) { if (arr[pointer].first < r) counter += (min(target, r - arr[pointer].first) * arr[pointer].second), target -= min(target, r - arr[pointer].first); pointer++; } } cout << counter << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; int n, m; vector<int> liga[200100]; vector<int> adj[200100]; int state[200100]; int id[200100], sz[200100]; int vis[200200]; vector<int> top; int find(int x) { if (id[x] == x) return x; return id[x] = find(id[x]); } void join(int a, int b) { a = find(a); b = find(b); if (a == b) return; if (sz[a] < sz[b]) swap(a, b); id[b] = a; sz[a] += sz[b]; } void dfs(int v) { vis[v] = 1; for (auto x : adj[v]) { if (vis[x]) continue; dfs(x); } top.push_back(v); } void dfs2(int v, int ori) { vis[v] = 1; for (auto x : adj[v]) { if (vis[x]) continue; join(ori, x); dfs2(x, ori); } } void add(int a, int b) { adj[a].push_back(b); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; for (int i = 1; i <= n; i++) cin >> state[i]; for (int i = 1; i <= 2 * m; i++) { id[i] = i; sz[i] = 1; } for (int i = 1; i <= m; i++) { int amt; cin >> amt; while (amt--) { int x; cin >> x; liga[x].push_back(i); } } for (int i = 1; i <= n; i++) { int x = liga[i][0]; int y = liga[i][1]; if (state[i]) { add(2 * x - 1, 2 * y - 1); add(2 * y, 2 * x); add(2 * y - 1, 2 * x - 1); add(2 * x, 2 * y); } else { add(2 * x, 2 * y - 1); add(2 * y, 2 * x - 1); add(2 * x - 1, 2 * y); add(2 * y - 1, 2 * x); } } for (int i = 1; i <= 2 * m; i++) if (!vis[i]) dfs(i); reverse(top.begin(), top.end()); memset(vis, 0, sizeof(vis)); for (auto x : top) if (!vis[x]) dfs2(x, x); for (int i = 1; i <= m; i++) { if (find(2 * i) == find(2 * i - 1)) { cout << NO << endl; return 0; } } cout << YES << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2000; int cubeta[MAXN + 2]; int color; int arr[MAXN + 2]; void mapea(int n) { set<int> nums; for (int i = 1; i <= n; i++) nums.insert(arr[i]); map<int, int> val; int cnt = 1; set<int>::iterator it = nums.begin(); while (it != nums.end()) { val[*it] = cnt; cnt++; it++; } for (int i = 1; i <= n; i++) arr[i] = val[arr[i]]; } int busca(int l, int n) { int r = n; while (r > l && cubeta[arr[r]] != color) { cubeta[arr[r]] = color; r--; } return r + 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> arr[i]; mapea(n); int resp = n; for (int l = 0; l <= n; l++) { color++; bool continuar = true; for (int i = 1; i <= l; i++) { if (cubeta[arr[i]] == color) continuar = false; cubeta[arr[i]] = color; } if (!continuar) break; int r = busca(l, n); resp = min(resp, r - l - 1); } cout << resp << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; int sa = 0, sb = 0; int ca, cb; char* c; int i = 0; scanf( %d , &n); c = (char*)malloc(sizeof(char) * n); while (n--) { scanf( %d %d , &ca, &cb); if (sb + cb > sa + 500) { sa = sa + ca; c[i++] = A ; } else { sb += cb; c[i++] = G ; } } c[i] = 0 ; if (abs(sb - sa) <= 500) printf( %s n , c); else printf( -1 n ); return 0; } |
// sigmadelta.v
// two channel second order sigma delta dac
// taken from Minimig
// audio data processing
// stereo sigma/delta bitstream modulator
module sd2_dac (
input clk, // bus clock
input [15:0] ldatasum, // left channel data
input [15:0] rdatasum, // right channel data
output reg left=0, // left bitstream output
output reg right=0 // right bitsteam output
);
//--------------------------------------------------------------------------------------
// local signals
localparam DW = 16;
localparam CW = 2;
localparam RW = 4;
localparam A1W = 2;
localparam A2W = 5;
wire [DW+2+0 -1:0] sd_l_er0, sd_r_er0;
reg [DW+2+0 -1:0] sd_l_er0_prev=0, sd_r_er0_prev=0;
wire [DW+A1W+2-1:0] sd_l_aca1, sd_r_aca1;
wire [DW+A2W+2-1:0] sd_l_aca2, sd_r_aca2;
reg [DW+A1W+2-1:0] sd_l_ac1=0, sd_r_ac1=0;
reg [DW+A2W+2-1:0] sd_l_ac2=0, sd_r_ac2=0;
wire [DW+A2W+3-1:0] sd_l_quant, sd_r_quant;
// LPF noise LFSR
reg [24-1:0] seed1 = 24'h654321;
reg [19-1:0] seed2 = 19'h12345;
reg [24-1:0] seed_sum=0, seed_prev=0, seed_out=0;
always @ (posedge clk) begin
if (&seed1)
seed1 <= 24'h654321;
else
seed1 <= {seed1[22:0], ~(seed1[23] ^ seed1[22] ^ seed1[21] ^ seed1[16])};
end
always @ (posedge clk) begin
if (&seed2)
seed2 <= 19'h12345;
else
seed2 <= {seed2[17:0], ~(seed2[18] ^ seed2[17] ^ seed2[16] ^ seed2[13] ^ seed2[0])};
end
always @ (posedge clk) begin
seed_sum <= seed1 + {5'b0, seed2};
seed_prev <= seed_sum;
seed_out <= seed_sum - seed_prev;
end
// linear interpolate
localparam ID=4; // counter size, also 2^ID = interpolation rate
reg [ID+0-1:0] int_cnt = 0;
always @ (posedge clk) int_cnt <= int_cnt + 'd1;
reg [DW+0-1:0] ldata_cur=0, ldata_prev=0;
reg [DW+0-1:0] rdata_cur=0, rdata_prev=0;
wire [DW+1-1:0] ldata_step, rdata_step;
reg [DW+ID-1:0] ldata_int=0, rdata_int=0;
wire [DW+0-1:0] ldata_int_out, rdata_int_out;
assign ldata_step = {ldata_cur[DW-1], ldata_cur} - {ldata_prev[DW-1], ldata_prev}; // signed subtract
assign rdata_step = {rdata_cur[DW-1], rdata_cur} - {rdata_prev[DW-1], rdata_prev}; // signed subtract
always @ (posedge clk) begin
if (~|int_cnt) begin
ldata_prev <= ldata_cur;
ldata_cur <= ldatasum; //{~ldatasum[DW-1], ldatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
rdata_prev <= rdata_cur;
rdata_cur <= rdatasum; //{~rdatasum[DW-1], rdatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
ldata_int <= {ldata_cur[DW-1], ldata_cur, {ID{1'b0}}};
rdata_int <= {rdata_cur[DW-1], rdata_cur, {ID{1'b0}}};
end else begin
ldata_int <= ldata_int + {{ID{ldata_step[DW+1-1]}}, ldata_step};
rdata_int <= rdata_int + {{ID{rdata_step[DW+1-1]}}, rdata_step};
end
end
assign ldata_int_out = ldata_int[DW+ID-1:ID];
assign rdata_int_out = rdata_int[DW+ID-1:ID];
// input gain x3
wire [DW+2-1:0] ldata_gain, rdata_gain;
assign ldata_gain = {ldata_int_out[DW-1], ldata_int_out, 1'b0} + {{(2){ldata_int_out[DW-1]}}, ldata_int_out};
assign rdata_gain = {rdata_int_out[DW-1], rdata_int_out, 1'b0} + {{(2){rdata_int_out[DW-1]}}, rdata_int_out};
// random dither to 15 bits
/*
reg [DW-1:0] ldata=0, rdata=0;
always @ (posedge clk) begin
ldata <= ldata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
rdata <= rdata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
end
*/
// accumulator adders
assign sd_l_aca1 = {{(A1W){ldata_gain[DW+2-1]}}, ldata_gain} - {{(A1W){sd_l_er0[DW+2-1]}}, sd_l_er0} + sd_l_ac1;
assign sd_r_aca1 = {{(A1W){rdata_gain[DW+2-1]}}, rdata_gain} - {{(A1W){sd_r_er0[DW+2-1]}}, sd_r_er0} + sd_r_ac1;
assign sd_l_aca2 = {{(A2W-A1W){sd_l_aca1[DW+A1W+2-1]}}, sd_l_aca1} - {{(A2W){sd_l_er0[DW+2-1]}}, sd_l_er0} - {{(A2W+1){sd_l_er0_prev[DW+2-1]}}, sd_l_er0_prev[DW+2-1:1]} + sd_l_ac2;
assign sd_r_aca2 = {{(A2W-A1W){sd_r_aca1[DW+A1W+2-1]}}, sd_r_aca1} - {{(A2W){sd_r_er0[DW+2-1]}}, sd_r_er0} - {{(A2W+1){sd_r_er0_prev[DW+2-1]}}, sd_r_er0_prev[DW+2-1:1]} + sd_r_ac2;
// accumulators
always @ (posedge clk) begin
sd_l_ac1 <= sd_l_aca1;
sd_r_ac1 <= sd_r_aca1;
sd_l_ac2 <= sd_l_aca2;
sd_r_ac2 <= sd_r_aca2;
end
// value for quantizaton
assign sd_l_quant = {sd_l_ac2[DW+A2W+2-1], sd_l_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
assign sd_r_quant = {sd_r_ac2[DW+A2W+2-1], sd_r_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
// error feedback
assign sd_l_er0 = sd_l_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
assign sd_r_er0 = sd_r_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
always @ (posedge clk) begin
sd_l_er0_prev <= (&sd_l_er0) ? sd_l_er0 : sd_l_er0+1;
sd_r_er0_prev <= (&sd_r_er0) ? sd_r_er0 : sd_r_er0+1;
end
// output
always @ (posedge clk) begin
left <= (~|ldata_gain) ? ~left : ~sd_l_er0[DW+2-1];
right <= (~|rdata_gain) ? ~right : ~sd_r_er0[DW+2-1];
end
endmodule
|
`default_nettype none
module thinpad_top(/*autoport*/
//inout
base_ram_data,
ext_ram_data,
flash_data,
sl811_data,
dm9k_data,
//output
base_ram_addr,
base_ram_be_n,
base_ram_ce_n,
base_ram_oe_n,
base_ram_we_n,
ext_ram_addr,
ext_ram_be_n,
ext_ram_ce_n,
ext_ram_oe_n,
ext_ram_we_n,
txd,
flash_address,
flash_rp_n,
flash_vpen,
flash_oe_n,
flash_ce,
flash_byte_n,
flash_we_n,
sl811_a0,
sl811_we_n,
sl811_rd_n,
sl811_cs_n,
sl811_rst_n,
sl811_drq,
dm9k_cmd,
dm9k_we_n,
dm9k_rd_n,
dm9k_cs_n,
dm9k_rst_n,
leds,
vga_pixel,
vga_hsync,
vga_vsync,
vga_clk,
vga_de,
//input
clk_in,
clk_uart_in,
rxd,
sl811_dack,
sl811_int,
dm9k_int,
dip_sw,
touch_btn);
input wire clk_in; //50MHz main clock input
input wire clk_uart_in; //11.0592MHz clock for UART
//Base memory signals
inout wire[31:0] base_ram_data;
output wire[19:0] base_ram_addr;
output wire[3:0] base_ram_be_n;
output wire base_ram_ce_n;
output wire base_ram_oe_n;
output wire base_ram_we_n;
assign base_ram_be_n=4'b0; //leave ByteEnable zero if you don't know what it is
//Extension memory signals
inout wire[31:0] ext_ram_data;
output wire[19:0] ext_ram_addr;
output wire[3:0] ext_ram_be_n;
output wire ext_ram_ce_n;
output wire ext_ram_oe_n;
output wire ext_ram_we_n;
assign ext_ram_be_n=4'b0;
//Serial port signals
output wire txd;
input wire rxd;
//Flash memory, JS28F640
output wire [21:0]flash_address;
output wire flash_rp_n;
output wire flash_vpen;
output wire flash_oe_n;
inout wire [15:0]flash_data;
output wire flash_ce;
output wire flash_byte_n;
output wire flash_we_n;
//SL811 USB controller signals
output wire sl811_a0;
inout wire[7:0] sl811_data;
output wire sl811_we_n;
output wire sl811_rd_n;
output wire sl811_cs_n;
output wire sl811_rst_n;
input wire sl811_dack;
input wire sl811_int;
output wire sl811_drq;
//DM9000 Ethernet controller signals
output wire dm9k_cmd;
inout wire[15:0] dm9k_data;
output wire dm9k_we_n;
output wire dm9k_rd_n;
output wire dm9k_cs_n;
output wire dm9k_rst_n;
input wire dm9k_int;
//LED, SegDisp, DIP SW, and BTN1~6
output wire[31:0] leds;
input wire[31:0] dip_sw;
input wire[5:0] touch_btn;
//Video output
output wire[7:0] vga_pixel;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_clk;
output wire vga_de;
//LED & DIP switches test
reg[23:0] counter;
reg[15:0] led_bits;
always@(posedge clk_in) begin
if(touch_btn[5])begin //reset
counter<=0;
led_bits[15:0] <= dip_sw[15:0]^dip_sw[31:16];
end
else begin
counter<= counter+1;
if(&counter)
led_bits[15:0] <= {led_bits[14:0],led_bits[15]};
end
end
assign leds[15:0] = led_bits;
//Serial port receive and transmit, 115200 baudrate, no parity
wire [7:0] RxD_data;
wire RxD_data_ready;
async_receiver #(.ClkFrequency(11059200),.Baud(115200))
uart_r(.clk(clk_uart_in),.RxD(rxd),.RxD_data_ready(RxD_data_ready),.RxD_data(RxD_data));
async_transmitter #(.ClkFrequency(11059200),.Baud(115200))
uart_t(.clk(clk_uart_in),.TxD(txd),.TxD_start(RxD_data_ready),.TxD_data(RxD_data)); //transmit data back
// 7-Segment display decoder
reg[7:0] number;
SEG7_LUT segL(.oSEG1({leds[23:22],leds[19:17],leds[20],leds[21],leds[16]}), .iDIG(number[3:0]));
SEG7_LUT segH(.oSEG1({leds[31:30],leds[27:25],leds[28],leds[29],leds[24]}), .iDIG(number[7:4]));
always @(posedge clk_uart_in) begin
if(RxD_data_ready)
number <= RxD_data; //show received data on segment display
end
//VGA display pattern generation
wire [2:0] red,green;
wire [1:0] blue;
assign vga_pixel = {red,green,blue};
assign vga_clk = clk_in;
vga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 (
.clk(clk_in),
.hdata(red),
.vdata({blue,green}),
.hsync(vga_hsync),
.vsync(vga_vsync),
.data_enable(vga_de)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int lbracket = s.length(), rbracket = -1, lcolon = s.length(), rcolon = -1; for (int i = 0; i < s.length(); i++) if (s[i] == [ ) { lbracket = i; break; } for (int i = lbracket; i < s.length(); i++) if (s[i] == : ) { lcolon = i; break; } for (int i = s.length() - 1; i > -1; i--) if (s[i] == ] ) { rbracket = i; break; } for (int i = rbracket; i > -1; i--) if (s[i] == : ) { rcolon = i; break; } if (lcolon < rcolon) { int ans = 4; for (int i = lcolon + 1; i < rcolon; i++) if (s[i] == | ) ans++; cout << ans; } else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i; scanf( %d%d , &n, &k); char s[n]; scanf( %s , s); for (i = 0; i < n; ++i) { if (s[i] == G ) { for (int j = i + k; j < n; j += k) { if (s[j] == # ) { printf( NO n ); return 0; } else if (s[j] == T ) { printf( YES n ); return 0; } } printf( NO n ); return 0; } else if (s[i] == T ) { for (int j = i + k; j < n; j += k) { if (s[j] == # ) { printf( NO n ); return 0; } else if (s[j] == G ) { printf( YES n ); return 0; } } printf( NO n ); return 0; } } return 0; } |
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 8
-- Description: Sbox 8 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox8
(
// -- inputs --------------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs -------------------------------------------------------- >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd13;
4'd1: sbox_dout = 4'd2;
4'd2: sbox_dout = 4'd8;
4'd3: sbox_dout = 4'd4;
4'd4: sbox_dout = 4'd6;
4'd5: sbox_dout = 4'd15;
4'd6: sbox_dout = 4'd11;
4'd7: sbox_dout = 4'd1;
4'd8: sbox_dout = 4'd10;
4'd9: sbox_dout = 4'd9;
4'd10: sbox_dout = 4'd3;
4'd11: sbox_dout = 4'd14;
4'd12: sbox_dout = 4'd5;
4'd13: sbox_dout = 4'd0;
4'd14: sbox_dout = 4'd12;
4'd15: sbox_dout = 4'd7;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd1;
4'd1: sbox_dout = 4'd15;
4'd2: sbox_dout = 4'd13;
4'd3: sbox_dout = 4'd8;
4'd4: sbox_dout = 4'd10;
4'd5: sbox_dout = 4'd3;
4'd6: sbox_dout = 4'd7;
4'd7: sbox_dout = 4'd4;
4'd8: sbox_dout = 4'd12;
4'd9: sbox_dout = 4'd5;
4'd10: sbox_dout = 4'd6;
4'd11: sbox_dout = 4'd11;
4'd12: sbox_dout = 4'd0;
4'd13: sbox_dout = 4'd14;
4'd14: sbox_dout = 4'd9;
4'd15: sbox_dout = 4'd2;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd7;
4'd1: sbox_dout = 4'd11;
4'd2: sbox_dout = 4'd4;
4'd3: sbox_dout = 4'd1;
4'd4: sbox_dout = 4'd9;
4'd5: sbox_dout = 4'd12;
4'd6: sbox_dout = 4'd14;
4'd7: sbox_dout = 4'd2;
4'd8: sbox_dout = 4'd0;
4'd9: sbox_dout = 4'd6;
4'd10: sbox_dout = 4'd10;
4'd11: sbox_dout = 4'd13;
4'd12: sbox_dout = 4'd15;
4'd13: sbox_dout = 4'd3;
4'd14: sbox_dout = 4'd5;
4'd15: sbox_dout = 4'd8;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd2;
4'd1: sbox_dout = 4'd1;
4'd2: sbox_dout = 4'd14;
4'd3: sbox_dout = 4'd7;
4'd4: sbox_dout = 4'd4;
4'd5: sbox_dout = 4'd10;
4'd6: sbox_dout = 4'd8;
4'd7: sbox_dout = 4'd13;
4'd8: sbox_dout = 4'd15;
4'd9: sbox_dout = 4'd12;
4'd10: sbox_dout = 4'd9;
4'd11: sbox_dout = 4'd0;
4'd12: sbox_dout = 4'd3;
4'd13: sbox_dout = 4'd5;
4'd14: sbox_dout = 4'd6;
4'd15: sbox_dout = 4'd11;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox8 sbox8
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/ |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_3_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_3_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_3_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_3_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m, k; cin >> n >> m >> k; int card_to_person = n / k; if (card_to_person >= m) { cout << m << n ; continue; } int tmp = (m - card_to_person) / (k - 1); if ((m - card_to_person) % (k - 1) != 0) { tmp++; } cout << card_to_person - tmp << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, m, k; int main() { cin >> n >> m >> k; cout << m * (m - 1) / 2 << endl; for (int i = 1; i <= m; i++) { for (int j = i + 1; j <= m; j++) { if (k) cout << j << << i << endl; else cout << i << << j << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; char to_da(char c) { if (c >= A && c <= Z ) return c; else return c - 32; } char to_xiao(char c) { if (c >= A && c <= Z ) return c + 32; else return c; } int main() { string s; int a; while (cin >> s >> a) { int len = s.length(); for (int i = 0; i < len; i++) { s[i] = to_xiao(s[i]); if (s[i] < a + 97) s[i] = to_da(s[i]); else s[i] = to_xiao(s[i]); } cout << s << endl; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; template <class T1, class T2> inline void remin(T1& a, T2 b) { a = min(a, (T1)b); } const int maxN = 1 << 18, maxTS = maxN * 2, INF = 1 << 30; vector<int> G[maxN]; int A[maxN], pat[maxN], whole[maxN], ile[maxN], sz[maxN], res, bord; void dfs0(int v, int fat) { sz[v] = 1; ile[v] = A[v] >= bord; for (int u : G[v]) if (u != fat) { dfs0(u, v); sz[v] += sz[u]; ile[v] += ile[u]; } } void dfs(int v, int fat) { int t[2] = {0, 0}; whole[v] = pat[v] = 1; for (int u : G[v]) if (u != fat) { dfs(u, v); if (whole[u] != 0) { if (whole[v] != 0) whole[v] += whole[u]; pat[v] += whole[u]; continue; } whole[v] = 0; if (pat[u] >= t[0]) t[1] = t[0], t[0] = pat[u]; else if (pat[u] > t[1]) t[1] = pat[u]; } if (A[v] >= bord) { pat[v] += t[0]; int prop = pat[v] + t[1]; if (sz[1] - sz[v] == ile[1] - ile[v]) prop += sz[1] - sz[v]; res = max(res, prop); } else pat[v] = whole[v] = 0; } void solve() { int n, k; scanf( %d%d , &n, &k); for (int i = (1); i < (n + 1); i++) scanf( %d , A + i); for (int i = (1); i < (n); i++) { int a, b; scanf( %d%d , &a, &b); G[a].push_back(b); G[b].push_back(a); } int a = 1, b = INF; while (b - a > 1) { bord = (a + b) / 2; res = 0; dfs0(1, 0); dfs(1, 0); res >= k ? a = bord : b = bord; } printf( %d n , a); } int main() { int t = 1; for (int tid = (1); tid < (t + 1); tid++) { solve(); } return 0; } |
#include <iostream> #include <algorithm> #include <cstring> #include <string> #include <queue> typedef long long ll; using namespace std; int main() { // what is greedy? int T; cin >> T; while (T--) { int len, a, b; cin >> len >> a >> b; string s; cin >> s; if (b > 0) cout << (a + b) * len << endl; else { // 尽量连续 char ch = s[0]; int arr[5] = { 0, 0, 0, 0, 0 }; for (int i = 0; i < len; i++) { if (s[i] != ch) { arr[ch - 0 ]++; ch = s[i]; } } // cout << s[len - 1] - 0 << endl; arr[s[len - 1] - 0 ]++; // cout << arr[0] == << arr[0] << endl; // cout << arr[1] == << arr[1] << endl; int minEle = arr[0] < arr[1] ? arr[0] : arr[1]; cout << a * len + (minEle + 1) * b << endl; } // if (a <= 0 && b <= 0) { // // 尽量连续 // char ch = s[0]; // int arr[5] = { 0, 0, 0, 0, 0 }; // for (int i = 0; i < len; i++) { // if (s[i] != ch) { // arr[ch - 0 ]++; // ch = s[i]; // } // } // int minEle = arr[0] < arr[1] ? arr[0] : arr[1]; // cout << a * len + (minEle + 1) * b << endl; // } else if (a <= 0 && b > 0) { // // 一个一个弄 // cout << (a + b) * len << endl; // } else if (a >= 0 && b <= 0) { // // 尽量连续 // char ch = s[0]; // int arr[5] = { 0, 0, 0, 0, 0 }; // for (int i = 0; i < len; i++) { // if (s[i] != ch) { // arr[ch - 0 ]++; // ch = s[i]; // } // } // int minEle = arr[0] < arr[1] ? arr[0] : arr[1]; // cout << a * len + (minEle + 1) * b << endl; // } else if (a >= 0 && b > 0) { // // 一个一个弄 // cout << (a + b) * len << endl; // } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; bool t = false; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) t = true, ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 48, ch = getchar(); return t ? -x : x; } int n, f[200200][3]; vector<int> E[200200]; void dfs(int u) { if (E[u].empty()) f[u][2] = 1; else f[u][0] = 1; for (int v : E[u]) { dfs(v); f[u][2] = (1ll * f[u][2] * (f[v][0] + f[v][2]) + 1ll * (f[u][1] + f[u][2]) * (f[v][1] + f[v][2])) % 998244353; f[u][1] = (1ll * f[u][1] * (f[v][0] + f[v][2]) + 1ll * f[u][0] * (f[v][1] + f[v][2])) % 998244353; f[u][0] = 1ll * f[u][0] * (f[v][0] + f[v][2]) % 998244353; } } int main() { n = read(); for (int i = 2; i <= n; ++i) E[read()].push_back(i); dfs(1); printf( %d n , (f[1][0] + f[1][2]) % 998244353); return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[200000 + 1], b[200000 + 1]; int c[200000 + 1], t[200000 + 1]; int n, m, k, s; vector<pair<long long, int> > v; inline int check(int p) { int i; v.clear(); long long mna = (1LL << 62), mnb = (1LL << 62); for (i = 1; i <= p; i++) { mna = min(mna, a[i]); mnb = min(mnb, b[i]); } for (i = 1; i <= m; i++) { if (t[i] == 1) v.push_back({1LL * mna * c[i], i}); else v.push_back({1LL * mnb * c[i], i}); } sort(v.begin(), v.end()); int cnt = 0; long long aux = s; for (i = 0; i < m; i++) { if (aux >= v[i].first) { aux -= v[i].first; cnt++; } } return cnt; } int main() { int i; ios::sync_with_stdio(false); cin >> n >> m >> k >> s; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) cin >> b[i]; for (i = 1; i <= m; i++) cin >> t[i] >> c[i]; int rez = 0; for (int pas = 1 << 17; pas; pas >>= 1) if (rez + pas <= n && check(rez + pas) < k) rez += pas; if (rez == n) { cout << -1; return 0; } rez++; cout << rez << endl; v.clear(); long long mna = (1LL << 62), mnb = (1LL << 62); int pa, pb; for (i = 1; i <= rez; i++) { mna = min(mna, a[i]); if (mna == a[i]) pa = i; mnb = min(mnb, b[i]); if (mnb == b[i]) pb = i; } for (i = 1; i <= m; i++) { if (t[i] == 1) v.push_back({1LL * mna * c[i], i}); else v.push_back({1LL * mnb * c[i], i}); } sort(v.begin(), v.end()); int cnt = 0; for (i = 0; i < m && cnt < k; i++) { if (s >= v[i].first) { s -= v[i].first; cnt++; if (t[v[i].second] == 1) cout << v[i].second << << pa << endl; else cout << v[i].second << << pb << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_1_V
`define SKY130_FD_SC_HD__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_1_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k, d1[200005], d2[200005], ty, re1, re2, re3; long long s, a[200005], b[200005], te; vector<pair<long long, int> > v1, v2; vector<long long> v3; void bs(int lo, int up) { int mid = (lo + up) / 2; if (lo == up) { v3.clear(); for (int i = 0; i < v2.size(); i++) v3.push_back(v2[i].first * b[mid]); for (int i = 0; i < v1.size(); i++) { if (v1[i].first * a[mid] > s) break; int k1 = upper_bound(v3.begin(), v3.end(), s - v1[i].first * a[mid]) - v3.begin(); if (i + 1 + k1 >= k) { re1 = i, re2 = k - i - 2, re3 = mid; return; } } if (v3.size() >= k && v3[k - 1] <= s) { re1 = -1, re2 = k - 1; re3 = mid; return; } } v3.clear(); for (int i = 0; i < v2.size(); i++) v3.push_back(v2[i].first * b[mid]); for (int i = 0; i < v1.size(); i++) { if (v1[i].first * a[mid] > s) break; int k1 = upper_bound(v3.begin(), v3.end(), s - v1[i].first * a[mid]) - v3.begin(); if (i + 1 + k1 >= k) { re1 = i, re2 = k - i - 2, re3 = mid; bs(lo, mid); return; } } if (v3.size() >= k && v3[k - 1] <= s) { re1 = -1, re2 = k - 1; re3 = mid; bs(lo, mid); return; } bs(mid + 1, up); } int main() { cin >> n >> m >> k >> s; a[0] = 1e9; b[0] = 1e9; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] < a[i - 1]) d1[i] = i; else a[i] = a[i - 1], d1[i] = d1[i - 1]; } v1.clear(); for (int i = 1; i <= n; i++) { cin >> b[i]; if (b[i] < b[i - 1]) d2[i] = i; else b[i] = b[i - 1], d2[i] = d2[i - 1]; } v2.clear(); for (int i = 1; i <= m; i++) { cin >> ty; if (ty == 1) { cin >> te; v1.push_back(pair<long long, int>(te, i)); } else { cin >> te; v2.push_back(pair<long long, int>(te, i)); } } sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); for (int i = 1; i < v1.size(); i++) v1[i].first += v1[i - 1].first; for (int i = 1; i < v2.size(); i++) v2[i].first += v2[i - 1].first; re3 = 1e9; v3.clear(); for (int i = 0; i < v2.size(); i++) v3.push_back(v2[i].first * b[n]); for (int i = 0; i < v1.size(); i++) { if (v1[i].first * a[n] > s) break; int k1 = upper_bound(v3.begin(), v3.end(), s - v1[i].first * a[n]) - v3.begin(); if (i + 1 + k1 >= k) { re1 = i, re2 = k - i - 2, re3 = n; break; } } if (v3.size() >= k && v3[k - 1] <= s) { re1 = -1, re2 = k - 1; re3 = n; } if (re3 != 1e9) { bs(1, n); cout << re3 << endl; for (int i = 0; i <= re1; i++) cout << v1[i].second << << d1[re3] << endl; for (int i = 0; i <= re2; i++) cout << v2[i].second << << d2[re3] << endl; } else cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 3e5; const long long P = 1e9 + 7; long long n; long long col[N], f[N], g[N]; vector<long long> a[N]; long long read(void) { long long s = 0, w = 0; char c = getchar(); while (!isdigit(c)) w |= c == - , c = getchar(); while (isdigit(c)) s = s * 10 + c - 48, c = getchar(); return w ? -s : s; } void Dfs(long long x, long long fa) { col[x] ? f[x] = 1 : g[x] = 1; for (long long i = 0; i < a[x].size(); ++i) { long long y = a[x][i]; if (y == fa) continue; Dfs(y, x); f[x] = (f[x] * (f[y] + g[y]) + g[x] * f[y]) % P; g[x] = (g[x] * (f[y] + g[y])) % P; } return; } signed main(void) { n = read(); for (long long i = 1; i < n; ++i) a[read()].push_back(i); for (long long i = 0; i < n; ++i) col[i] = read(); Dfs(0, 0); cout << f[0] << endl; return 0; } |
`timescale 1ns / 1ps
// Name: WcaDownConverter_stimulus.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
`include "../wca/hal/WcaHalRegisterDefs.vh" //grab register addresses.
`include "../containers/4ChTxRxRegisterDefs.vh"
module WcaDownConverter_stimulus;
parameter SYSCLK_PERIOD = 10.0; // 100 MHz
parameter DSPCLK_PERIOD = 1000.0/128.0; //128 MHz
parameter LIMECLK_PERIOD = 1000.0/64.0; // 64 MHz
parameter CPUCLK_PERIOD = 1000.0/32.0; // 32 MHz
parameter RESET_START = 5*CPUCLK_PERIOD;
parameter EVENT_MASK = 8'h02; // LSDP0, LSDP1;
parameter LSDP_ENABLE = 8'h20; //Enables LSDP0 and LSDP1.
parameter LSDP_RESET = 8'h02; //Resets LSDP0 and LSDP1.
parameter RF0_CTRL_FLAGS = 8'hF5; //Set the RX IQ to rx and Txd Data.,
parameter RX_SAMP_DELAY = 1; // Six nanoseconds
`define DDC0_CTRL (`WCACOMP_DSP_DDC0 + `DSP_DDUC_CTRL)
/////////////////////////////////////////
// Wires and registers
/////////////////////////////////////////
reg reset, cpuclk, dspclk, limeclk, comp_reset;
reg sysclk;
reg [23:0] iq_in;
wire [31:0] iq_out;
wire dstrobe_out;
// Bidirs
reg [11:0] rbusCtrl;
wire [7:0] rbusData;
//CPU I/O and Processing Signals
reg [7:0] adata; //Address set register
reg [7:0] rdata; //Read bus result register.
reg [7:0] wdata; //write data register.
wire [7:0] dbus; //CPU data bus
reg address, write, read; //address,write, read control lines.
//////////////////////////////////////////////////////////////////////
// WCA HAL Functions
//////////////////////////////////////////////////////////////////////
reg [11:0] rf0_rxd;
reg rf0_rxiqsel;
wire rf0_rxclk, rf0_rxen, rf0_txclk, rf0_txiqsel, rf0_txen;
wire [11:0] rf0_txd;
wire [23:0] rx0_iq;
wire [23:0] tx0_iq;
wire rx0_strobe, tx0_strobe, rx1_strobe, tx1_strobe;
//////////////////////////////////////////////////////////////////////
// Downconverter Test.
//////////////////////////////////////////////////////////////////////
WcaRegBus cpuif (
.clock(sysclk),
.reset(reset),
.address(address),
.write(write),
.read(read),
.dbus(dbus),
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
wire [7:0] ddc0_ctrl;
WcaWriteByteReg #(`DDC0_CTRL) wr_ddc0_ctrl
(.reset(reset),
.out( ddc0_ctrl),
.rbusCtrl(rbusCtrl), .rbusData(rbusData) );
// Instantiate the Unit Under Test (UUT)
WcaDownConverter uut (
.clock(dspclk),
.reset(reset),
.enable(ddc0_ctrl[0]),
.aclr( ddc0_ctrl[1]),
.dstrobe_in(rx0_strobe),
.cfgflags(ddc0_ctrl[5:2]),
.iq_in(rx0_iq),
.iq_out(iq_out),
.dstrobe_out(dstrobe_out),
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
// Lime RF#1 Interface implementation.
WcaLimeIF #( `WCAHAL_RF0_CTRL, `WCAHAL_RF0_RSSI, `WCAHAL_RF0_BIAS)
lime1_if ( .clock_dsp(dspclk), .clock_rx(limeclk), .clock_tx(limeclk), .reset(reset),
.rbusCtrl(rbusCtrl),.rbusData(rbusData),
.rf_rxclk(rf0_rxclk), .rf_rxiqsel(rf0_rxiqsel), .rf_rxen(rf0_rxen), .rf_rxdata(rf0_rxd[11:0]),
.rf_txclk(rf0_txclk), .rf_txiqsel(rf0_txiqsel), .rf_txen(rf0_txen), .rf_txdata(rf0_txd[11:0]),
.rx_strobe( rx0_strobe), .rx_iq(rx0_iq), .tx_strobe( tx0_strobe), .tx_iq( tx0_iq) );
//////////////////////////////////////////////////////////////////////
// Lime signals simulations
//////////////////////////////////////////////////////////////////////
//NOTE limeclk is used to drive these simulation timings,
//since the others are not set up during the reset.
reg [11:0] rx0_count;
always @(posedge rf0_rxclk)
begin
if(reset) rx0_count <= 12'h0;
else if( rf0_rxiqsel) rx0_count <= rx0_count + 12'h1;
end
//Simulate the RF0 iqselection.
always @(posedge rf0_rxclk)
begin
if( reset) #(RX_SAMP_DELAY)
begin
rf0_rxiqsel <= 1'h0;
rf0_rxd <= 12'h0;
end
else if( rf0_rxen) #(RX_SAMP_DELAY)
begin
rf0_rxiqsel <= ~rf0_rxiqsel;
rf0_rxd <= (rf0_rxiqsel) ? 12'h17F : 12'hF81;
end
end
//////////////////////////////////////////////////////////////////////
// Simulation
//////////////////////////////////////////////////////////////////////
initial begin
//Set initial state of clocks lime interface related regisers.
#0
sysclk = 1;
dspclk=1;
limeclk = 1;
rf0_rxiqsel <= 1'h0;
rf0_rxd <= 12'h0;
rx0_count <=12'h0;
end
initial begin
//Set initial state of CPU related registers.
#0
cpuclk = 1;
address = 0;
write = 0;
read = 0;
wdata = 8'hEF;
reset = 1'b0;
comp_reset = 1'b0;
//Reset the part.
#(RESET_START) reset = 1'b1;
#(CPUCLK_PERIOD*3) reset = 1'b0;
//Reset the HdwComponent after the main reset.
#(CPUCLK_PERIOD*10) comp_reset = 1'b1;
#(CPUCLK_PERIOD*3) comp_reset = 1'b0;
//Set the Sampling Control on RF1 to receive RF and transmit DSP.
#(CPUCLK_PERIOD * 4) adata = `WCAHAL_RF0_CTRL;
#(CPUCLK_PERIOD) address = 1'b1;
#(CPUCLK_PERIOD) address= 1'b0;
#(CPUCLK_PERIOD) wdata = RF0_CTRL_FLAGS;
#(CPUCLK_PERIOD) write = 1'b1;
#(CPUCLK_PERIOD) write = 1'b0;
end
//////////////////////////////////////////////////////////////////////
// CPU Addressing Simluator
//////////////////////////////////////////////////////////////////////
//Set up Registers for controlling and databus.
assign dbus = (address) ? adata : (write) ? wdata : 8'bz;
always @(posedge cpuclk)
begin
if( reset)
rdata <= 8'h0;
else if( read)
rdata <= dbus;
end
//////////////////////////////////////////////////////////////////////
// Clocks
//////////////////////////////////////////////////////////////////////
always @(sysclk )
#(SYSCLK_PERIOD / 2.0) sysclk <= !sysclk;
always @(cpuclk )
#(CPUCLK_PERIOD / 2.0) cpuclk <= !cpuclk;
always @(dspclk)
#(DSPCLK_PERIOD / 2.0) dspclk<= !dspclk;
always @( posedge dspclk)
limeclk <= !limeclk;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:256000000 ) using namespace std; int main() { int n; scanf( %d , &(n)); vector<int> v1(n), v2(n), v3(n); if (!(n % 2)) { printf( -1 n ); return 0; } for (int i = (0), endi = (n); i < endi; ++i) v1[i] = i; for (int i = (0), endi = (n); i < endi; ++i) v2[i] = (i + 1) % n; for (int i = (0), endi = (n); i < endi; ++i) v3[i] = (v1[i] + v2[i]) % n; for (int i = (0), endi = ((v1).size()); i < endi; ++i) { printf( %d , (v1[i])); }; printf( n ); for (int i = (0), endi = ((v2).size()); i < endi; ++i) { printf( %d , (v2[i])); }; printf( n ); for (int i = (0), endi = ((v3).size()); i < endi; ++i) { printf( %d , (v3[i])); }; printf( n ); } |
#include <bits/stdc++.h> double eps = 1e-9; using namespace std; int main() { std::ios::sync_with_stdio(false); int x, y, z, w, b, a; cin >> x >> y >> z >> w >> b >> a; cout << (2 * (2 * x + a + y) * (z + y) - (a * a + b * b + y * y + z * z)) / 2; return 0; } |
#include <bits/stdc++.h> using namespace std; using vec_i = vector<int>; using pii = pair<int, int>; using ll = long long; using vec_ii = vector<pii>; using vec_ll = vector<ll>; template <typename T> using vec = vector<T>; ll gcd(ll x, ll y) { ll m; while (y > 0) { m = x % y; x = y; y = m; } return x; } ll powm(ll x, ll n, ll m) { ll r = 1; while (n > 0) { if (n & 1) r = r * x % m; x = x * x % m; n /= 2; } return r; } static const int MOD = 1000000000 + 7; static const int P = 343434; const int PA = 257, PB = 983, MODA = 1e9 + 7, MODB = 1e9 + 9; int n, m; char ss[256][256]; int tt[256][256]; bool pal[256]; int hash_a[256], hash_b[256]; ll hash_lalaku[256]; int pa_pows[256], pb_pows[256]; inline bool is_pow2(int val) { return val != 0 && (val & (val - 1)) == 0; } inline bool is_pal(int val, bool odd) { return (odd && is_pow2(val)) || ((!odd) && (val == 0)); } int solve() { pa_pows[0] = 1; pb_pows[0] = 1; for (int i = 1; i < 256; ++i) { pa_pows[i] = pa_pows[i - 1] * 1ll * PA % MODA; pb_pows[i] = pb_pows[i - 1] * 1ll * PB % MODB; } scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { scanf( %s , ss[i] + 1); } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { int val, c; c = ss[i][j] - a + 1; val = (1 << c); tt[i][j] = tt[i][j - 1] ^ val; } } ll ans = 0; for (int i = 1; i <= m; ++i) { memset(hash_a, 0, sizeof(hash_a)); memset(hash_b, 0, sizeof(hash_b)); for (int j = i; j <= m; ++j) { bool all_same = true; for (int k = 1; k <= n; ++k) { pal[k] = is_pal(tt[k][j] ^ tt[k][i - 1], (j - i + 1) & 1); hash_a[k] += pa_pows[ss[k][j] - a + 1]; hash_b[k] += pb_pows[ss[k][j] - a + 1]; if (hash_a[k] >= MODA) hash_a[k] -= MODA; if (hash_b[k] >= MODB) hash_b[k] -= MODB; hash_lalaku[k] = ((ll)hash_a[k] << 32) | (hash_b[k]); all_same = (all_same) && pal[k] && (k == 1 || hash_lalaku[k] == hash_lalaku[k - 1]); } if (all_same) { ans += (n * (n + 1)) / 2; continue; } for (int k = 1; k <= n; ++k) { if (pal[k]) { int l = k, r = k; while (l > 1 && r < n && pal[l - 1] && pal[r + 1] && hash_lalaku[l - 1] == hash_lalaku[r + 1]) { --l; ++r; } ans += (r - l + 1 + 1) / 2; } if (k < n && pal[k + 1] && hash_lalaku[k] == hash_lalaku[k + 1]) { int l = k, r = k + 1; while (l > 1 && r < n && pal[l - 1] && pal[r + 1] && hash_lalaku[l - 1] == hash_lalaku[r + 1]) { --l; ++r; } ans += (r - l + 1) / 2; } } } } printf( %lld n , ans); return 0; } int main(int argc, char* argv[]) { ::std::ios::sync_with_stdio(false); ::std::cin.tie(0); ::std::cout.tie(0); int test_count = 1; while (test_count--) { solve(); } return 0; } |
#include <bits/stdc++.h> template <typename T> T power(T x, T y, T mod) { T res = 1; while (y > 0) { if (y & 1) res = (res * x) % mod; y /= 2; x = (x * x) % mod; } return res; } using namespace std; long long int a[2005][2005]; long long int d1[4005]; long long int d2[4005]; long long int ele[2005][2005]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n; cin >> n; for (long long int i = 0; i < n; i++) for (long long int j = 0; j < n; j++) cin >> a[i][j]; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < n; j++) { long long int b = a[i][j]; d1[j - i + n] += b; d2[n + n - i - j - 1] += b; } } long long int max1 = 0; long long int max2 = 0; long long int x1, y1, x2, y2; x1 = 1; x2 = 1; y1 = 1; y2 = 2; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < n; j++) { ele[i][j] = d1[j - i + n] + d2[2 * n - i - j - 1] - a[i][j]; if ((i + j) % 2) { if (max1 < ele[i][j]) { max1 = ele[i][j]; x1 = i + 1; y1 = j + 1; } } else { if (max2 < ele[i][j]) { max2 = ele[i][j]; x2 = i + 1; y2 = j + 1; } } } } cout << max1 + max2 << n ; cout << x1 << << y1 << << x2 << << y2 << n ; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_mul_cntl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sparc_mul_cntl(
ecl_mul_req_vld,
spu_mul_req_vld,
spu_mul_acc,
spu_mul_areg_shf,
spu_mul_areg_rst,
spu_mul_mulres_lshft,
c0_act,
spick,
byp_sel,
byp_imm,
acc_imm,
acc_actc2,
acc_actc3,
acc_actc5,
acc_reg_enb,
acc_reg_rst,
acc_reg_shf,
x2,
mul_ecl_ack,
mul_spu_ack,
mul_spu_shf_ack,
rst_l,
rclk
);
input rclk;
input rst_l; // System rest
input ecl_mul_req_vld; // Input request from EXU to MUL
input spu_mul_req_vld; // Input request from SPU to MUL
input spu_mul_acc; // 1: SPU mul op req will accumulate the ACCUM register
input spu_mul_areg_shf; // ACCUM shift right 64-bit
input spu_mul_areg_rst; // ACCUM reset; initialization of modular multiplication
input spu_mul_mulres_lshft; // For x2 of op1*op2*2 left shift
output c0_act; // cycle-0 of muliplier operation
output spick;
output byp_sel; // Bypass mux control
output byp_imm;
output acc_imm;
output acc_actc2, acc_actc3; // accumulate enable for LSB-32 and All-96
output acc_actc5; // accumulate enable for LSB-32 and All-96
output acc_reg_enb; // ACCUM register enable
output acc_reg_rst; // ACCUM register reset
output acc_reg_shf; // ACCUM register shift select
output x2;
output mul_ecl_ack; // Ack EXU multiplier operation is accepted.
output mul_spu_ack; // Ack SPU multiplier operation is accepted.
output mul_spu_shf_ack; // Ack SPU shift operation is accepted.
reg mul_ecl_ack_d;
reg mul_spu_ack_d;
reg c1_act; // Squash all mul requests from EXU and SPU if c1_act = 1
reg c2_act; // Squash bypass ACCUM mul request from SPU if c2_act = 1
reg c3_act; // Enable >>32 results back to CSA2 if c3_act = 1
reg favor_e; // Flag for alternate picker, favor to EXU if f_state = 1
reg acc_actc1, acc_actc2, acc_actc3, acc_actc4, acc_actc5;
reg acc_reg_shf, acc_reg_rst;
wire exu_req_vld, spu_req_vld;
wire epick; // Internal pick signals of exu, spu multiplier
wire nobyps; // Squash SPU bypass mul requests nobyps = 1
wire noshft; // Squash SPU bypass mul requests noshft = 1
wire acc_reg_shf_in;
wire spu_mul_byp = ~spu_mul_acc ;
wire clk;
/////////////////////////////////////////
// Requests picker and general control //
/////////////////////////////////////////
assign clk = rclk ;
assign c0_act = epick | spick ; // Cycle0 of multiplier operation
//assign c1_act = mul_ecl_ack_d | mul_spu_ack_d ; // Cycle1 of multiplier operation
assign nobyps = c1_act | acc_actc2 | acc_actc3 | acc_actc4 ; // Cycles prevent the SPU bypass
assign x2 = spick & spu_mul_mulres_lshft;
assign exu_req_vld = ecl_mul_req_vld & ~c1_act ;
assign spu_req_vld = spu_mul_req_vld & ~c1_act & ~(nobyps & spu_mul_byp);
assign epick = exu_req_vld & ( favor_e | ~spu_req_vld) ;
assign spick = spu_req_vld & (~favor_e | ~exu_req_vld) ;
// moved this one cycle earlier
assign mul_spu_ack = rst_l & spick ;
assign mul_ecl_ack = rst_l & epick ;
always @(posedge clk)
begin
mul_ecl_ack_d <= rst_l & epick ;
mul_spu_ack_d <= rst_l & spick ;
c1_act <= rst_l & c0_act ;
c2_act <= rst_l & c1_act ;
c3_act <= rst_l & c2_act ;
favor_e <= rst_l & (mul_spu_ack_d & ~mul_ecl_ack_d);
end
/////////////////////////////////////////////////
// SPU accumulate and bypass and shift control //
/////////////////////////////////////////////////
assign byp_sel = spick & spu_mul_byp ; // SPU bypass operand is picked
//////////////////////////////////////////////////////////////////////////
// No ACCUM >>= 64 allow if there are //
// 1) accumulate mul before cycle4 which need to updated ACCUM //
// 2) Any mul at cyc3 which will use the same output mux at cyc-5 //
//////////////////////////////////////////////////////////////////////////
assign noshft = acc_actc1 | acc_actc2 | c3_act | acc_actc4 ;
// Squash shifr if:
assign acc_reg_shf_in = spu_mul_areg_shf & // No shift request
~noshft & // SPU accum mul in cycle1~4 or EXU mul in cycle3
~acc_reg_shf ; // reset SPU shift request for 1-cycle for signal upate
always @(posedge clk)
begin
acc_reg_shf <= rst_l & acc_reg_shf_in ; // latch ACCUM reg shift control
acc_reg_rst <= spu_mul_areg_rst ; // latch input control of ACCUM reg reset
acc_actc1 <= rst_l & (spick & spu_mul_acc) ; // SPU MAC in cycle 1
acc_actc2 <= rst_l & acc_actc1 ; // SPU MAC in cycle 2
acc_actc3 <= rst_l & acc_actc2 ; // SPU MAC in cycle 3
acc_actc4 <= rst_l & acc_actc3 ; // SPU MAC in cycle 4
acc_actc5 <= rst_l & acc_actc4 ; // SPU MAC in cycle 5
end
assign mul_spu_shf_ack = acc_reg_shf;
assign byp_imm = acc_actc5 ;
assign acc_imm = (acc_actc2 & acc_actc4) | ((acc_actc2 | acc_actc3) & acc_actc5) ;
assign acc_reg_enb = acc_actc5 | acc_reg_shf; // enable of ACCUM registers
endmodule // sparc_mul_cntl
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, x = 0; scanf( %d , &n); for (i = 2; i <= n / 2; i += 2) { if ((n - i) % 2 == 0 && i / 2 != (n - i) / 2) x++; } printf( %d n , x); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKBUF_FUNCTIONAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_TB_V
`define SKY130_FD_SC_LP__NOR4B_TB_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__nor4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_TB_V
|
module VGA_NIOS_CTRL ( // Host Side
iDATA,
oDATA,
iADDR,
iWR,
iRD,
iCS,
iRST_N,
iCLK, // Host Clock
// Export Side
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
VGA_SYNC,
VGA_BLANK,
VGA_CLK,
iCLK_25 );
parameter RAM_SIZE = 19'h4B000;
// Host Side
output [15:0] oDATA;
input [15:0] iDATA;
input [18:0] iADDR;
input iWR,iRD,iCS;
input iCLK,iRST_N;
reg [15:0] oDATA;
// Export Side
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output VGA_HS;
output VGA_VS;
output VGA_SYNC;
output VGA_BLANK;
output VGA_CLK;
input iCLK_25;
reg [3:0] mCursor_RGB_N;
reg [9:0] mCursor_X;
reg [9:0] mCursor_Y;
reg [9:0] mCursor_R;
reg [9:0] mCursor_G;
reg [9:0] mCursor_B;
reg [9:0] mON_R;
reg [9:0] mON_G;
reg [9:0] mON_B;
reg [9:0] mOFF_R;
reg [9:0] mOFF_G;
reg [9:0] mOFF_B;
wire [18:0] mVGA_ADDR;
wire [9:0] mVGA_R;
wire [9:0] mVGA_G;
wire [9:0] mVGA_B;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mCursor_RGB_N <= 0;
mCursor_X <= 0;
mCursor_Y <= 0;
mCursor_R <= 0;
mCursor_G <= 0;
mCursor_B <= 0;
mON_R <= 0;
mON_G <= 0;
mON_B <= 0;
mOFF_R <= 0;
mOFF_G <= 0;
mOFF_B <= 0;
oDATA <= 0;
end
else
begin
if(iCS)
begin
if(iWR)
begin
case(iADDR)
RAM_SIZE+0 : mCursor_RGB_N <= iDATA;
RAM_SIZE+1 : mCursor_X <= iDATA;
RAM_SIZE+2 : mCursor_Y <= iDATA;
RAM_SIZE+3 : mCursor_R <= iDATA;
RAM_SIZE+4 : mCursor_G <= iDATA;
RAM_SIZE+5 : mCursor_B <= iDATA;
RAM_SIZE+6 : mON_R <= iDATA;
RAM_SIZE+7 : mON_G <= iDATA;
RAM_SIZE+8 : mON_B <= iDATA;
RAM_SIZE+9 : mOFF_R <= iDATA;
RAM_SIZE+10: mOFF_G <= iDATA;
RAM_SIZE+11: mOFF_B <= iDATA;
endcase
end
else if(iRD)
begin
case(iADDR)
RAM_SIZE+0 : oDATA <= mCursor_RGB_N ;
RAM_SIZE+1 : oDATA <= mCursor_X ;
RAM_SIZE+2 : oDATA <= mCursor_Y ;
RAM_SIZE+3 : oDATA <= mCursor_R ;
RAM_SIZE+4 : oDATA <= mCursor_G ;
RAM_SIZE+5 : oDATA <= mCursor_B ;
RAM_SIZE+6 : oDATA <= mON_R ;
RAM_SIZE+7 : oDATA <= mON_G ;
RAM_SIZE+8 : oDATA <= mON_B ;
RAM_SIZE+9 : oDATA <= mOFF_R ;
RAM_SIZE+10: oDATA <= mOFF_G ;
RAM_SIZE+11: oDATA <= mOFF_B ;
endcase
end
end
end
end
VGA_Controller u0 ( // Host Side
.iCursor_RGB_EN(mCursor_RGB_N),
.iCursor_X(mCursor_X),
.iCursor_Y(mCursor_Y),
.iCursor_R(mCursor_R),
.iCursor_G(mCursor_G),
.iCursor_B(mCursor_B),
.oAddress(mVGA_ADDR),
.iRed (mVGA_R),
.iGreen (mVGA_G),
.iBlue (mVGA_B),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
.oVGA_CLOCK(VGA_CLK),
// Control Signal
.iCLK_25(iCLK_25),
.iRST_N(iRST_N) );
VGA_OSD_RAM u1 ( // Read Out Side
.oRed(mVGA_R),
.oGreen(mVGA_G),
.oBlue(mVGA_B),
.iVGA_ADDR(mVGA_ADDR),
.iVGA_CLK(VGA_CLK),
// Write In Side
.iWR_DATA(iDATA),
.iWR_ADDR(iADDR),
.iWR_EN(iWR && (iADDR < RAM_SIZE) && iCS),
.iWR_CLK(iCLK),
// CLUT
.iON_R(mON_R),
.iON_G(mON_G),
.iON_B(mON_B),
.iOFF_R(mOFF_R),
.iOFF_G(mOFF_G),
.iOFF_B(mOFF_B),
// Control Signals
.iRST_N(iRST_N) );
endmodule |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i, j, x; long long m, k, x1, u1, x2, y2, x3, y3, x4, y4, x5, y5, x6, y6; bool t = 0; int main() { cin >> x1 >> u1 >> x2 >> y2 >> x3 >> y3 >> x4 >> y4 >> x5 >> y5 >> x6 >> y6; m = (x2 - x1) * (y2 - u1); if (x3 < x2 && y3 < y2 && x4 > x1 && y4 > u1) { if (x3 < x1) x3 = x1; if (y3 < u1) y3 = u1; if (x4 > x2) x4 = x2; if (y4 > y2) y4 = y2; k = (x4 - x3) * (y4 - y3); m -= k; } if (x5 < x2 && y5 < y2 && x6 > x1 && y6 > u1) { if (x5 < x1) x5 = x1; if (y5 < u1) y5 = u1; if (x6 > x2) x6 = x2; if (y6 > y2) y6 = y2; k = (x6 - x5) * (y6 - y5); m -= k; } if (x3 < x6 && x4 > x5 && y3 < y6 && y5 < y4) { if (x3 < x5) x3 = x5; if (x4 > x6) x4 = x6; if (y3 < y5) y3 = y5; if (y4 > y6) y4 = y6; k = (x4 - x3) * (y4 - y3); m += k; } if (m > 0) cout << YES << endl; else cout << NO << endl; return 0; } |
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_sub.list"
`include "top.v"
module top_test_sub;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = OUTPUT_CNT-1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output == 0) begin
$display("Subtract test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Subtract test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output - 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> x[100100], y[100100]; vector<int> p[100100], q[100100], v[100100], w[100100]; int a[100100], b[100100], c[100100]; map<pair<int, int>, int> mp; void solve() { mp.clear(); int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &a[i], &b[i]); x[a[i]].push_back(b[i]); y[b[i]].push_back(a[i]); if (a[i] + b[i] <= n + 1) { int o = a[i] - 1, oo = o + b[i]; p[oo].push_back(b[i]); } else { int oo = n - b[i], o = a[i] - oo; q[o].push_back(a[i]); } if (a[i] <= b[i]) { int o = a[i] - 1, oo = b[i] - o; v[oo].push_back(b[i]); } else { int oo = b[i], o = a[i] - oo + 1; w[o].push_back(a[i]); } } for (int i = 1; i <= n; i++) { if (x[i].size() <= 1) continue; sort(x[i].begin(), x[i].end()); for (int j = 0; j < x[i].size(); j++) { int xx = i, yy = x[i][j]; if (j == 0 || j == x[i].size() - 1) { mp[make_pair(xx, yy)]++; } else { mp[make_pair(xx, yy)] += 2; } } } for (int i = 1; i <= n; i++) { if (y[i].size() <= 1) continue; sort(y[i].begin(), y[i].end()); for (int j = 0; j < y[i].size(); j++) { int xx = y[i][j], yy = i; if (j == 0 || j == y[i].size() - 1) { mp[make_pair(xx, yy)]++; } else { mp[make_pair(xx, yy)] += 2; } } } for (int i = 1; i <= n; i++) { if (p[i].size() <= 1) continue; sort(p[i].begin(), p[i].end()); for (int j = 0; j < p[i].size(); j++) { int yy = p[i][j]; int xx = i - yy + 1; if (j == 0 || j == p[i].size() - 1) { mp[make_pair(xx, yy)]++; } else { mp[make_pair(xx, yy)] += 2; } } } for (int i = 1; i <= n; i++) { if (q[i].size() <= 1) continue; sort(q[i].begin(), q[i].end()); for (int j = 0; j < q[i].size(); j++) { int xx = q[i][j]; int yy = n - (xx - i); if (j == 0 || j == q[i].size() - 1) { mp[make_pair(xx, yy)]++; } else { mp[make_pair(xx, yy)] += 2; } } } for (int i = 1; i <= n; i++) { if (v[i].size() <= 1) continue; sort(v[i].begin(), v[i].end()); for (int j = 0; j < v[i].size(); j++) { int yy = v[i][j]; int xx = yy - i + 1; if (j == 0 || j == v[i].size() - 1) { mp[make_pair(xx, yy)]++; } else { mp[make_pair(xx, yy)] += 2; } } } for (int i = 1; i <= n; i++) { if (w[i].size() <= 1) continue; sort(w[i].begin(), w[i].end()); for (int j = 0; j < w[i].size(); j++) { int xx = w[i][j]; int yy = xx - i + 1; if (j == 0 || j == w[i].size() - 1) { mp[make_pair(xx, yy)]++; } else { mp[make_pair(xx, yy)] += 2; } } } map<pair<int, int>, int>::iterator iter; iter = mp.begin(); int s = 0; while (iter != mp.end()) { int o = iter->second; pair<int, int> v = iter->first; c[o]++; s++; iter++; } printf( %d , m - s); for (int i = 1; i < 9; i++) printf( %d , c[i]); } int main() { solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long a, b; int cnt = 0; cin >> a >> b; long long d = abs(a - b); if (d % 10 == 0) { cout << d / 10 << endl; } else { cout << d / 10 + 1 << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100005]; int t[400005]; int d[400005]; pair<int, int> p[305]; pair<int, int> cp[305]; int n; void build(int l, int r, int i) { d[i] = 0; if (l == r) t[i] = a[l]; else { int m = (l + r) / 2; int L = 2 * i; build(l, m, L); build(m + 1, r, L + 1); t[i] = (t[L] < t[L + 1] ? t[L] : t[L + 1]); } } void update(int l, int r, int p, int x, int y, int i) { if (l > y || r < x) return; if (l <= x && r >= y) { d[i] += p; t[i] += p; return; } int m = (x + y) / 2; int L = 2 * i; update(l, r, p, x, m, L); update(l, r, p, m + 1, y, L + 1); t[i] = (t[L] < t[L + 1] ? t[L] : t[L + 1]) + d[i]; } bool comp(pair<int, int> x, pair<int, int> y) { return (x.second < y.second); } int main() { ios::sync_with_stdio(false); int m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) { cin >> p[i].first >> p[i].second; p[i].first--; p[i].second--; cp[i] = p[i]; } sort(p, p + m); int v = 0, an = -1000000007; build(0, n - 1, 1); for (int j = m - 1, i = n - 1; i >= 0; i--) { if (an < a[i] - t[1]) { an = a[i] - t[1]; v = i; } while (j >= 0 && p[j].first >= i) { update(p[j].first, p[j].second, -1, 0, n - 1, 1); j--; } } sort(p, p + m, comp); build(0, n - 1, 1); for (int j = 0, i = 0; i < n; i++) { if (an < a[i] - t[1]) { an = a[i] - t[1]; v = i; } while (j < m && p[j].second <= i) { update(p[j].first, p[j].second, -1, 0, n - 1, 1); j++; } } cout << an << endl; int c = 0; for (int i = 0; i < m; i++) { if (v < p[i].first || v > p[i].second) c++; } cout << c << endl; for (int i = 0; i < m; i++) { if (v < cp[i].first || v > cp[i].second) cout << i + 1 << ; } } |
#include <bits/stdc++.h> using namespace std; int ans = 0, n; int numDistDig(int n) { vector<int> arr(10, 0); while (n > 0) { arr[n % 10]++; n /= 10; } int ans = 0, i; for (i = 0; i < 10; i++) ans += (arr[i] > 0); return ans; } void dfs(int num) { if (num > 0 && num <= n) ans++; if (ans >= 100000000) return; int i; for (i = 0; i < 10; i++) { int num2 = num * 10 + i; if (num2 > 0 && numDistDig(num2) <= 2) dfs(num2); } } int main() { scanf( %d , &n); dfs(0); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; int dp1[100010]; int dp2[100010]; int a[100010]; int main(int argc, char const *argv[]) { int n; cin >> n; for (int i = 1; i <= n; i++) { std::cin >> a[i]; } dp1[0] = 0; int sum = 0; for (int i = 1; i <= n; i++) { sum += a[i]; dp1[i] = dp1[i - 1] + a[i]; if (dp1[i] < -sum) { dp1[i] = -sum; } } dp2[n + 1] = 0; sum = 0; for (int i = n; i >= 1; --i) { sum += a[i]; dp2[i] = dp2[i + 1] + a[i]; if (dp2[i] < -sum) { dp2[i] = -sum; } } int ans = 0; for (int i = 1; i <= n + 1; i++) { ans = max(ans, dp1[i - 1] + dp2[i]); } std::cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; scanf( %lld , &n); scanf( %lld , &k); long long int i, j; long long int val = 0, val1 = 0, val2 = 1; for (i = 1; i < k; i++) { val = (val * 10) + 9; val2 = val2 * 10; } val1 = (val * 10) + 9; long long int arr[n + 5]; long long int brr[n + 5]; long long int m = n / k; for (i = 0; i < m; i++) { scanf( %lld , &arr[i]); } for (i = 0; i < m; i++) { scanf( %lld , &brr[i]); } long long int tot = 1; long long int mod = 1e9 + 7; for (i = 0; i < m; i++) { long long int t1 = val1 / arr[i]; if (brr[i] != 0) t1++; long long int t2 = (brr[i] * val2) + val; long long int t3 = t2 / arr[i]; long long int t4 = (max(0LL, brr[i] * val2 - 1)) / arr[i]; t3 = t3 - t4; long long int t5 = t1 - t3; tot *= t5; tot %= mod; } cout << tot << n ; } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_phy_10g_fifo
*/
module test_eth_mac_phy_10g_fifo;
// Parameters
parameter DATA_WIDTH = 64;
parameter HDR_WIDTH = (DATA_WIDTH/32);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000/6.4;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rx_axis_tready = 0;
reg [DATA_WIDTH-1:0] serdes_rx_data = 0;
reg [HDR_WIDTH-1:0] serdes_rx_hdr = 1;
reg [7:0] ifg_delay = 0;
reg tx_prbs31_enable = 0;
reg rx_prbs31_enable = 0;
// Outputs
wire tx_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [DATA_WIDTH-1:0] serdes_tx_data;
wire [HDR_WIDTH-1:0] serdes_tx_hdr;
wire serdes_rx_bitslip;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_bad_block;
wire rx_block_lock;
wire rx_high_ber;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tready,
serdes_rx_data,
serdes_rx_hdr,
ifg_delay,
tx_prbs31_enable,
rx_prbs31_enable
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
serdes_tx_data,
serdes_tx_hdr,
serdes_rx_bitslip,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_bad_block,
rx_block_lock,
rx_high_ber,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_phy_10g_fifo.lxt");
$dumpvars(0, test_eth_mac_phy_10g_fifo);
end
eth_mac_phy_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { long double a, b, c, p, q, r; cin >> a >> b >> c; p = b * b - 4 * a * c; if (a == 0 && b == 0 && c == 0) cout << -1 << endl; else if (a == 0 && b == 0 && c != 0) cout << 0 << endl; else if (p < 0) cout << 0 << endl; else if (a == 0) { q = -c / b; cout << 1 << endl; cout << fixed << setprecision(6) << q; } else if (p == 0) { q = -b / (2 * a); cout << 1 << endl; cout << fixed << setprecision(6) << q; } else { q = (-b - sqrt(p)) / (2 * a); r = (-b + sqrt(p)) / (2 * a); if (q < r) { cout << 2 << n << fixed << setprecision(6) << q << endl; cout << fixed << setprecision(6) << r << endl; } else { cout << 2 << n << fixed << setprecision(6) << r << endl; cout << fixed << setprecision(6) << q << endl; } } return 0; } |
<%
var _ = core();
var ir = _.logic(4);
var len = _.logic(3);
var len = {
'??00': '0001',
'1?0?': '0001',
'0001': '0010',
'0010': '0100',
'0011': '1000'
};
%>
/*
module tail_length (${ _.get.list() });
${ _.get.ports() }
${ _.get.wires() }
${ _.get.body() }
*/
module tail_length (ir, len);
input [3:0] ir;
output [3:0] len;
reg [3:0] len;
reg ir32;
/*
..00 ..01 ..10 ..11
00.. 1 0 0 0
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
len[0] = (ir[3] & !ir[1]) | (!ir[1] & !ir[0]);
..00 ..01 ..10 ..11
00.. 0 1 0 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[1] = !ir[3] & !ir[2] & !ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 0 0 1 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[2] = !ir[3] & !ir[2] & ir[1] & !ir[0];
..00 ..01 ..10 ..11
00.. 0 0 0 1
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[3] = !ir[3] & !ir[2] & ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 1 2 4 8
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
*/
always @ (ir)
begin
len = {
(ir == 4'b0011),
(ir == 4'b0010),
(ir == 4'b0001),
((ir | 4'b0101) == 4'b1101) | ((ir | 4'b1100) == 4'b1100)
};
end
// 107.89 / 121.08
// always @ (ir)
// begin
// ir32 = |ir[3:2];
// len = {
// (!ir32 & ir[1] & ir[0]),
// (!ir32 & ir[1] & !ir[0]),
// (!ir32 & !ir[1] & ir[0]),
// ((ir[3] & !ir[1]) | (!ir[1] & !ir[0]))
// };
// end
// always @ (ir)
// casez (ir)
// 4'b??00: len = 1;
// 4'b1?0?: len = 1;
// 4'b0001: len = 2;
// 4'b0010: len = 4;
// 4'b0011: len = 8;
// default len = 0;
// endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long INF = 1e18; bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long nCr(long long n, long long r) { long long res = 1; if (n < r) return -1; r = min(r, n - r); for (long long i = 0; i < r; i++) { res *= (n - i); res /= (i + 1); } return res; } long long nPr(long long n, long long r) { long long res = 1; if (n < r) return -1; for (long long i = 0; i < r; i++) res *= (n - i); return res; } void solve() { long long n, m; cin >> n >> m; vector<long long> a(n), b(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { cin >> b[i]; } sort(b.begin(), b.end()); long long ans = INF; for (long long i = 0; i < n; i++) { long long x = (b[i] - a[0] + m) % m; vector<long long> v(n); for (long long j = 0; j < n; j++) v[j] = (a[j] + x) % m; sort(v.begin(), v.end()); if (v == b) ans = min(ans, x); } cout << ans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) solve(); return 0; } |
`timescale 1ns/1ns
// $ iverilog fp16rmul.v fp16rmul_test.v
module FP16RMul_Test;
reg clk, rst;
reg [15:0] s0_arg_0;
reg [15:0] s0_arg_1;
wire s0_ret_0;
wire [4:0] s0_ret_1;
wire [4:0] s0_ret_2;
wire [11:0] s0_ret_3;
reg s1_arg_0;
reg [4:0] s1_arg_1;
reg [4:0] s1_arg_2;
reg [11:0] s1_arg_3;
wire [15:0] s1_ret_0;
reg xs;
reg [4:0] xe;
reg [9:0] xf;
reg ys;
reg [4:0] ye;
reg [9:0] yf;
wire rs;
wire [4:0] re;
wire [9:0] rf;
assign rs = s1_ret_0[15:15];
assign re = s1_ret_0[14:10];
assign rf = s1_ret_0[9:0];
FP16RMulS0Of2
inst_0(.clk(clk), .rst(rst),
.arg_0(s0_arg_0), .arg_1(s0_arg_1),
.ret_0(s0_ret_0), .ret_1(s0_ret_1), .ret_2(s0_ret_2), .ret_3(s0_ret_3));
FP16RMulS1Of2
inst_1(.clk(clk), .rst(rst),
.arg_0(s1_arg_0), .arg_1(s1_arg_1), .arg_2(s1_arg_2), .arg_3(s1_arg_3),
.ret_0(s1_ret_0));
always @(s0_ret_0 or s0_ret_1 or s0_ret_2 or s0_ret_3) begin
s1_arg_0 <= s0_ret_0;
s1_arg_1 <= s0_ret_1;
s1_arg_2 <= s0_ret_2;
s1_arg_3 <= s0_ret_3;
$display("S0: %d %d %d %d", s0_ret_0, s0_ret_1, s0_ret_2, s0_ret_3);
end
always @(xs or xe or xf or ys or ye or yf) begin
s0_arg_0 = {xs, xe, xf};
s0_arg_1 = {ys, ye, yf};
end
initial begin
clk <= 0;
rst <= 1;
#105
rst <= 0;
// 0 * 0
s0_arg_0 <= 0;
s0_arg_1 <= 0;
#1
$display("0.0*0.0= %d %s", s1_ret_0, (s1_ret_0 == 0) ? "OK" : "FAIL");
// 1.0 * 1.0
xs <= 0; xe <= 15; xf <= 0;
ys <= 0; ye <= 15; yf <= 0;
#1
$display("1.0*1.0= %d %s", s1_ret_0, (rs == 0 && re == 15 && rf == 0) ? "OK" : "FAIL");
// 1.5 * 1.5
xs <= 0; xe <= 15; xf <= 512;
ys <= 0; ye <= 15; yf <= 512;
#1
$display("1.5*1.5= %d %s", s1_ret_0, (rs == 0 && re == 16 && rf == 128) ? "OK" : "FAIL");
$display("%d %d %d", rs, re, rf);
// 1.25 * 1.25
xs <= 0; xe <= 15; xf <= 256;
ys <= 0; ye <= 15; yf <= 256;
#1
$display("1.25*1.25= %d %s", s1_ret_0, (rs == 0 && re == 15 && rf == 576) ? "OK" : "FAIL");
// 0.75 * 0.75
xs <= 0; xe <= 14; xf <= 512;
ys <= 0; ye <= 14; yf <= 512;
#1
$display("0.75*0.75= %d %s", s1_ret_0, (rs == 0 && re == 14 && rf == 128) ? "OK" : "FAIL");
// 2^-14 * 0.5
xs <= 0; xe <= 1; xf <= 0;
ys <= 0; ye <= 14; yf <= 0;
#1
$display("2^-14*0.5= %d %s", s1_ret_0, (rs == 0 && re == 0 && rf == 0) ? "OK" : "FAIL");
// 2^9 * 2^9
xs <= 0; xe <= 24; xf <= 0;
ys <= 0; ye <= 24; yf <= 0;
#1
$display("2^9*2^9= %d %s", s1_ret_0, (rs == 0 && re == 31 && rf == 0) ? "OK" : "FAIL");
// Use this line to debug a specific case.
$display("%d %d %d", rs, re, rf);
#10000
$display("test done");
$finish;
end
endmodule // FP16RMul_Test
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n, m, k; cin >> n >> m >> k; vector<pair<long long int, long long int> > F(n), S(m); long long int maxDay = 0; for (long long int i = 0; i < n; i++) { cin >> F[i].first; F[i].second = i + 1; maxDay = max(maxDay, F[i].first); } for (long long int i = 0; i < m; i++) { cin >> S[i].first; S[i].second = i + 1; } long long int f_i = 0, s_i = 0; sort(F.begin(), F.begin() + F.size()); sort(S.begin(), S.begin() + S.size()); vector<long long int> res; for (long long int i = 0; i <= maxDay; i++) { long long int use = 0; while (use < k && f_i < F.size() && F[f_i].first == i) { f_i++; use++; } if (use == k && f_i < F.size() && F[f_i].first == i) { cout << -1 ; return 0; } while (s_i < S.size() && S[s_i].first < i) s_i++; while (use < k && s_i < S.size() && S[s_i].first >= i) { res.push_back(S[s_i].second); use++; s_i++; } while (use < k && f_i < F.size() && F[f_i].first > i) { use++; f_i++; } } for (long long int i = maxDay + 1; s_i < S.size(); i++) { long long int use = 0; while (s_i < S.size() && S[s_i].first < i) s_i++; while (use < k && s_i < S.size() && S[s_i].first >= i) { res.push_back(S[s_i].second); s_i++; use++; } } cout << res.size() << n ; for (auto x : res) cout << x << ; } |
// Example module that doesn't instantiate
module appendix1 (/*AUTOARG*/
// Outputs
z,
// Inputs
i
);
input i;
output z;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg z;
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
always @ (/*AUTOSENSE*/i) begin
z = i;
end
endmodule
// Example module that does instantiate
module appendix2 (/*AUTOARG*/
// Outputs
z,
// Inputs
i
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i; // To apx10 of appendix1.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [11:10] z; // From apx10 of appendix1.v, ...
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*
appendix1 AUTO_TEMPLATE (
.z (z[@]),
);
*/
appendix1 apx10 (/*AUTOINST*/
// Outputs
.z (z[10]), // Templated
// Inputs
.i (i));
appendix1 apx11 (/*AUTOINST*/
// Outputs
.z (z[11]), // Templated
// Inputs
.i (i));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long dp[31][31]; long long solve(int n, int r) { if (n == r || r == 0) return 1; if (n < r) return 0; if (dp[n][r] != -1) { return dp[n][r]; } return dp[n][r] = solve(n - 1, r - 1) + solve(n - 1, r); } int main() { int t = 1; while (t--) { long long n, m, k; cin >> n >> m >> k; if (k == 1) { long long ans = 1; for (int i = 0; i < n; i++) { ans = (ans * m) % 1000000007; } cout << ans; } else if (k == n) { int s = n / 2; if (n % 2) s++; long long ans = 1; for (int i = 0; i < s; i++) { ans = (ans * m) % 1000000007; } cout << ans; } else if (k > n) { long long ans = 1; for (int i = 0; i < n; i++) { ans = (ans * m) % 1000000007; } cout << ans; } else { if (k % 2 == 0) { cout << m; } else { cout << m * m; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, a[101], m, ans; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> k; if (k % 2) a[++m] = k; ans += k; } if (m == 0) { cout << 0 << endl; return 0; } if (m % 2 == 0) { sort(a + 1, a + m + 1); ans -= a[1]; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, arr[100005], diff[100005], prv[100005]; bool flag[100005]; vector<int> a, d; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , arr + i); flag[arr[i]] = 1; } for (int i = 1; i <= n; ++i) { if (!flag[arr[i]]) continue; if (prv[arr[i]] && !diff[arr[i]]) diff[arr[i]] = i - prv[arr[i]]; else if (prv[arr[i]] && diff[arr[i]] != i - prv[arr[i]]) flag[arr[i]] = 0; prv[arr[i]] = i; } for (int i = 0; i < 100005; ++i) if (flag[i]) a.push_back(i), d.push_back(diff[i]); printf( %d n , a.size()); for (int i = 0; i < a.size(); ++i) printf( %d %d n , a[i], d[i]); return 0; } |
/* lcd_tb.v */
`timescale 1ns/1ps
module lcd_tb();
reg clk;
reg rst;
wire sof;
wire [ 4-1:0] r;
wire [ 4-1:0] g;
wire [ 4-1:0] b;
wire [ 16-1:0] lcd_dat;
wire lcd_cs;
wire lcd_rs;
wire lcd_wr;
wire lcd_rd;
wire lcd_res;
//// clock ////
`define CLK_HP 17.857
initial begin
clk = 0;
forever #`CLK_HP clk = ~clk;
end
//// reset ////
initial begin
rst = 1;
repeat (10) @ (posedge clk); #1;
rst = 0;
end
//// stop ////
initial begin
$display("LCD bench starting ...");
repeat(1000) @ (posedge clk);
$display("LCD bench stopping ...");
$finish;
end
initial begin
wait(lcd.init_cnt == 'd162);
repeat(10) @ (posedge clk); #1;
force sof = 1;
@ (posedge clk); #1;
release sof;
end
//// DUT ////
lcd lcd(
.clk (clk ),
.rst (rst ),
.sof (sof ),
.r (r ),
.g (g ),
.b (b ),
.lcd_dat (lcd_dat ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_res (lcd_res )
);
endmodule
|
`include "defines.v"
`timescale 1ns/1ps
module tb(
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `control_w flit1c;
reg `control_w flit2c;
wire `control_w port0_co, port1_co, port2_co, port3_co, port4_co;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.port2_ci(flit2c), .port2_co(port2_co),
.port3_ci(144'h0), .port3_co(port3_co),
.port4_ci(144'h0), .port4_co(port4_co),
.port4_ready(injrd), .port4_ack(injack)
);
initial begin
$set_toggle_region(tb.r);
$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0123456789abcdef0123456789abcdef1857; // MSHR 1; valid / seq 0; source 5; dest 7
flit1c = 144'h0123456789abcdef0123456789abcdef284c;
flit2c = 144'h0123456789abcdef0123456789abcdef3813;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 144'h0;
flit1c = 144'h0;
flit2c = 144'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$toggle_stop();
$toggle_report("./calf_backward_3.saif", 1.0e-9, "tb.r");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int t, n, c_0, c_1, h; string s; cin >> t; for (int i = 0; i < t; i++) { cin >> n >> c_0 >> c_1 >> h; cin >> s; int sum = 0; for (int j = 0; j < n; j++) { sum += s[j] - 0 ; } if (c_0 - c_1 > h) { sum = c_1 * n + (n - sum) * h; } else if (c_1 - c_0 > h) { sum = c_0 * n + sum * h; } else sum = c_1 * sum + (n - sum) * c_0; cout << sum << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; void _print(int32_t t) { cerr << t; } void _print(int64_t t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << , ; _print(p.second); cerr << } ; } template <class T> void _print(vector<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } int64_t find(int64_t mid) { int64_t ans = 0; while (mid != 0) { mid /= 2; ans++; } return ans; } void solve() { int64_t n, k; cin >> n >> k; int64_t low = 1, high = 1; for (int64_t i = 0; i < n - 1; i += 1) { high *= 2; high++; } while (low <= high) { int64_t mid = (low + high) / 2; if (mid == k) { cout << find(high - low + 1); return; } if (mid > k) { high = mid - 1; } if (mid < k) low = mid + 1; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int64_t t = 1; while (t--) { solve(); cout << n ; } } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_TO_CTRL.v
// Version : 1.7
//--
//-- Description: Turn-off Control Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff_n,
cfg_turnoff_ok_n
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff_n;
output cfg_turnoff_ok_n;
reg trn_pending;
reg cfg_turnoff_ok_n;
// * Check if completion is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i)
trn_pending <= 1'b1;
else if (compl_done_i)
trn_pending <= 1'b0;
end
end
// * Turn-off OK if requested and no transaction is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
cfg_turnoff_ok_n <= 1'b1;
end else begin
if ( !cfg_to_turnoff_n && !trn_pending)
cfg_turnoff_ok_n <= 1'b0;
else
cfg_turnoff_ok_n <= 1'b1;
end
end
endmodule // PIO_TO_CTRL
|
#include <bits/stdc++.h> using namespace std; using uint = unsigned int; using ll = long long; using ull = unsigned long long; using pii = pair<int, int>; using pll = pair<ll, ll>; template <typename T1, typename T2> ostream &operator<<(ostream &out, const pair<T1, T2> &item) { out << ( << item.first << , << item.second << ) ; return out; } template <typename T> ostream &operator<<(ostream &out, const vector<T> &v) { for (const auto &item : v) out << item << ; return out; } const int D = 510; const int S = 5010; bool dp[S][D]; pair<pii, int> prv[S][D]; queue<pii> q; string reconstruct(int s, int r) { if (prv[s][r].second == -1) return ; return reconstruct(prv[s][r].first.first, prv[s][r].first.second) + char(prv[s][r].second + 0 ); } int main() { ios_base::sync_with_stdio(false); int d, s; cin >> d >> s; memset(dp, 0, sizeof dp); memset(prv, -1, sizeof prv); q.push({0, 0}); dp[0][0] = true; while (!q.empty()) { int sd = q.front().first; int r = q.front().second; q.pop(); for (int dig = 0; dig < 10; ++dig) { int newr = (r * 10 + dig) % d; if (sd + dig > s) continue; if (!dp[sd + dig][newr]) { dp[sd + dig][newr] = true; prv[sd + dig][newr] = {{sd, r}, dig}; q.push({sd + dig, newr}); } } } if (!dp[s][0]) cout << -1 << n ; else cout << reconstruct(s, 0) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (m == 3 && n > 4) { cout << -1 << endl; return 0; } int cnt = 0, ans = 0; for (int i = 0; i < m; i++) printf( %d %d n , i, ans += (cnt++)); if (m < n) cout << m + 100000 << << ans << endl; for (int i = m + 1; i < n; i++) printf( %d %d n , i + 100000, ans -= (--cnt)); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 150000 + 10; int len, n, h; int a[MAXN], b[MAXN]; int dp[1 << 20], all[1 << 20]; inline void go(int root, int lo, int hi, int s, int e, int key) { if (hi < s || e < lo) return; if (s <= lo && hi <= e) { all[root] += key; dp[root] += key; return; } int mid = (lo + hi) / 2; go(root * 2, lo, mid, s, e, key); go(root * 2 + 1, mid + 1, hi, s, e, key); dp[root] = min(dp[root * 2], dp[root * 2 + 1]) + all[root]; } inline void build(int root, int lo, int hi) { if (lo == hi) { dp[root] = -lo; return; } int mid = (lo + hi) / 2; build(root * 2, lo, mid); build(root * 2 + 1, mid + 1, hi); dp[root] = -hi; } int main() { cin >> n >> len >> h; for (int i = 0; i < len; i++) cin >> b[i]; for (int i = 0; i < n; i++) cin >> a[i]; sort(b, b + len); int ret = 0; build(1, 0, len - 1); for (int i = 0; i < n; i++) { int poi = lower_bound(b, b + len, h - a[i]) - b; go(1, 0, len - 1, poi, len - 1, 1); if (len <= i + 1) { ret += (dp[1] > 0); poi = lower_bound(b, b + len, h - a[i - len + 1]) - b; go(1, 0, len - 1, poi, len - 1, -1); } } cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, N, Left, Right; long long seg[2000001], vs[2000001]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; char grid[n + 1][m + 1]; vs[0] = 0; set<pair<long long, long long>> d; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { cin >> grid[i][j]; } } for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { if (i > 1 && j > 1) { if (grid[i - 1][j] == X && grid[i][j - 1] == X ) { vs[j]++; } } } } for (long long i = 1; i <= m; i++) vs[i] += vs[i - 1]; long long q; cin >> q; while (q--) { cin >> Left >> Right; if (vs[Right] - vs[Left]) cout << NO ; else cout << YES ; cout << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_4_V
`define SKY130_FD_SC_HS__MAJ3_4_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; char a[100]; int main() { int i, l, c = 0; scanf( %s , a); l = strlen(a); for (i = 1; i < l; i++) { if (a[i] <= Z ) { c++; } } int t = 0; if (a[1] <= Z && c >= l - 1) t++; if (t != 0) { for (i = 0; i < l; i++) { if (a[i] >= a ) { a[i] = a[i] - a + A ; } else { a[i] = a[i] - A + a ; } } } printf( %s , a); } |
#include <bits/stdc++.h> using namespace std; const int MAX_L = 200; map<int, pair<int, int> > ds; int ops[MAX_L]; int powmod(int a, int n, int mod) { int pm = 1; while (n > 0) { if (n & 1) pm = (long long)pm * a % mod; a = (long long)a * a % mod; n >>= 1; } return pm; } bool check(int v, int u, int uc, queue<int> &q, int &mst, int &mgl) { map<int, pair<int, int> >::iterator mit = ds.find(v); if (mit != ds.end()) { if (uc * mit->second.first < 0) { if (uc > 0) mst = u, mgl = v; else mst = v, mgl = u; return true; } } else { ds[v] = pair<int, int>(uc, u); q.push(v); } return false; } int getop(int u, int v, int p) { if ((u + 1) % p == v) return 1; if ((u + p - 1) % p == v) return 2; return 3; } int main() { int st, gl, p; scanf( %d%d%d , &st, &gl, &p); if (st == gl) { puts( 2 n1 2 ); return 0; } ds[st] = pair<int, int>(1, -1); ds[gl] = pair<int, int>(-1, -1); queue<int> q; q.push(st), q.push(gl); int mst = -1, mgl = -1; while (!q.empty()) { int u = q.front(); q.pop(); pair<int, int> ud = ds[u]; int uc = ud.first, up = ud.second; if (check((u + 1) % p, u, uc, q, mst, mgl) || check((u + p - 1) % p, u, uc, q, mst, mgl) || check(powmod(u, p - 2, p), u, uc, q, mst, mgl)) break; } vector<int> vst, vgl; for (int u = mst; u >= 0; u = ds[u].second) vst.push_back(u); for (int u = mgl; u >= 0; u = ds[u].second) vgl.push_back(u); int l = 0; for (int i = vst.size() - 1; i > 0; i--) ops[l++] = getop(vst[i], vst[i - 1], p); ops[l++] = getop(mst, mgl, p); for (int i = 0; i + 1 < vgl.size(); i++) ops[l++] = getop(vgl[i], vgl[i + 1], p); printf( %d n , l); for (int i = 0; i < l; i++) printf( %d%c , ops[i], (i + 1 < l) ? : n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 21; int n; long long s, a[N], down = 1, ans; void exgcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1, y = 0; return; } exgcd(b, a % b, y, x); y -= a / b * x; } long long inv(long long x) { long long res, y; exgcd(x, 1000000007, res, y); return res; } long long C(long long u, long long d) { if (d < u) return 0; long long res = 1; for (long long i = d; i > d - u; i--) (res *= i % 1000000007) %= 1000000007; return res * down % 1000000007; } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> s; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i < n; i++) (down *= i) % 1000000007; down = inv(down); for (int i = 0; i < (1 << n); i++) { long long f = 1, d = s + n - 1, u = n - 1; for (int j = 0; j < n; j++) if (i & (1 << j)) { d -= a[j] + 1; f *= -1; } (ans += f * C(u, d)) %= 1000000007; } cout << (ans + 1000000007) % 1000000007; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_PP_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg_s/sky130_fd_sc_hdll__udp_pwrgood_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hdll__isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND, SLEEP);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_PP_V |
// synthesis verilog_version verilog_2001
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : core_wrapper_tx.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This is the complete example application for the PCI Express Reference
// Design. This has all of the application logic for the example.
//-----------------------------------------------------------------------------
// Copyright (c) 2006 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
`include "altpcierd_icm_defines.v"
module altpcierd_icm_npbypassctl # (
parameter TXCRED_WIDTH = 22
)( clk, rstn,
tx_cred, data_in, data_valid, data_ack, tx_bridge_idle,
tx_npcredh, tx_npcredd, tx_npcredh_infinite, tx_npcredd_infinite,
np_data_in, np_fifo_wrempty, np_fifo_rdempty, np_data_ack,
ena_np_bypass, tx_mask, got_cred, sending_np, sending_npd,
tx_ack, req_npbypass_pkt );
input clk;
input rstn;
input [65:0] tx_cred; // from core. available credits. this is a concatenation of info for 6 credit types
// bit 10 = means no NP header credits avail
// bit 11 = means no NP data credits avail
input [107:0] data_in; // indicates data_in is valid
input data_valid; // indicates data_in is valid
input data_ack;
input tx_bridge_idle; // means tx avalon-to-legacy bridge is not transferring a pkt. okay to switch data source.
input np_fifo_wrempty; // npbypass fifo is empty
input np_fifo_rdempty;
input[107:0] np_data_in; // data output from npbypass fifo
input np_data_ack;
input[7:0] tx_npcredh;
input[11:0] tx_npcredd;
input tx_npcredh_infinite;
input tx_npcredd_infinite;
input tx_ack;
input sending_np;
input sending_npd;
output req_npbypass_pkt;
output tx_mask; // tells app to mask out nonposted requests
output ena_np_bypass; // Control to route NP requests to npbypass fifo
output got_cred;
wire ena_np_bypass;
reg ena_np_bypass_r;
reg tx_mask;
wire sim_npreq; // for simulation only
reg got_nph_cred;
reg got_npd_cred;
wire req_npbypass_pkt;
reg[10:0] sim_count;
reg sim_sop_del;
wire got_cred;
wire got_nph_cred_c;
wire got_npd_cred_c;
reg flush_np_bypass;
reg np_tx_ack_del;
assign sim_npreq = data_in[`STREAM_NP_REQ_FLAG]; // for simulation only
//------------------------------------------------------
// Credit Check
// Bypass NP requests if core has no header credits,
// FOR NOW .. MAINTAIN STRICT ORDERING ON NP's
// NP Read requests require 1 header credit.
// NP Write requests require 1 data credit.
//-------------------------------------------------------
// assert bypass whenever there are no header credits, or whenever
// a write request is received and there are no data credits.
// release after there are enough credits to accept the next NP
// packet, and all deferred NP packets have been flushed.
// should be able to release ena_np_bypass before fifo is flushed - but leave like this for now.
assign ena_np_bypass = (data_in[`STREAM_NP_SOP_FLAG] &
(~got_nph_cred_c | (~got_npd_cred_c & data_in[`STREAM_NP_WRREQ_FLAG]))) ? 1'b1 : np_fifo_wrempty ? 1'b0 : ena_np_bypass_r; // need to account for latency in np_fifo_empty
assign req_npbypass_pkt = flush_np_bypass;
/////////////////////////////////////////////////////////////////////
// For x4/x1 core (TXCRED_WIDTH == 22), use only the LSB
// For x8 core (TXCRED_WIDTH == 66), use registered equation
////////////////////////////////////////////////////////////////////
/*
assign got_nph_cred_c = (TXCRED_WIDTH == 22) ? tx_npcredh[0] : got_nph_cred;
assign got_npd_cred_c = (TXCRED_WIDTH == 22) ? tx_npcredd[0] : got_npd_cred;
*/
// x4 work around - do not evaluate credits until 2nd cycle after tx_ack asserts
assign got_nph_cred_c = (TXCRED_WIDTH == 22) ? (tx_npcredh[0] & ~np_tx_ack_del) : got_nph_cred;
assign got_npd_cred_c = (TXCRED_WIDTH == 22) ? (tx_npcredd[0] & ~np_tx_ack_del) : got_npd_cred;
assign got_cred = 1'b0;
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
ena_np_bypass_r <= 1'b0;
tx_mask <= 1'b0;
sim_sop_del <= 1'b0;
sim_count <= 11'h0;
got_nph_cred <= 1'b0;
got_npd_cred <= 1'b0;
flush_np_bypass <= 1'b0;
np_tx_ack_del <= 1'b0;
end
else begin
ena_np_bypass_r <= ena_np_bypass;
np_tx_ack_del <= tx_ack & sending_np;
if (tx_npcredh_infinite) got_nph_cred <= 1'b1;
else if (tx_ack & sending_np) got_nph_cred <= |tx_npcredh[7:1]; // if credits=1 on this cycle, assume it is zero on next.
else got_nph_cred <= |tx_npcredh; // okay to evaluate on any non-tx_ack cycle
if (tx_npcredd_infinite) got_npd_cred <= 1'b1;
else if (tx_ack & sending_npd) got_npd_cred <= |tx_npcredd[11:1]; // if credits=1 on this cycle, assume it is zero on next.
else got_npd_cred <= |tx_npcredd; // okay to evaluate on any non-tx_ack cycle
if (np_fifo_rdempty) begin
flush_np_bypass <= 1'b0;
end
else if (np_data_in[`STREAM_NP_SOP_FLAG]) begin
flush_np_bypass <= got_nph_cred_c & (got_npd_cred_c | ~np_data_in[`STREAM_NP_WRREQ_FLAG]);
end
else begin
flush_np_bypass <= 1'b0;
end
////////////////////// FOR SIMULATION ONLY ////////////////////////////////
// COUNT # NP REQUESTS
sim_sop_del <= data_valid ? data_in[`STREAM_SOP] : sim_sop_del;
if (data_in[`STREAM_NP_REQ_FLAG] & data_in[`STREAM_SOP] & ~sim_sop_del)
sim_count <= sim_count + 1;
///////////////////////////////////////////////////////////////////////////
// assert tx_mask as soon as the first nonposted
// request requires bypassing.
// deassert when bypass fifo is empty (for now)
tx_mask <= (~got_nph_cred_c | (~got_npd_cred_c & data_in[`STREAM_NP_WRREQ_FLAG])) ? 1'b1 : np_fifo_wrempty ? 1'b0 : tx_mask;
end
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; int n, cnt; int ans[1005]; bool prime(int x) { for (int i = 2; i < x; i++) if (x % i == 0) return 0; return 1; } int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) { if (!prime(i)) continue; int p = i; while (p <= n) { ans[++cnt] = p; p *= i; } } printf( %d n , cnt); for (int i = 1; i < cnt; i++) printf( %d , ans[i]); if (cnt) printf( %d n , ans[cnt]); } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_8_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [8-1:0] cmd_repeat,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [8-1:0] repeat_cnt_pre;
reg [8-1:0] repeat_cnt;
wire [8-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 8'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 2'b01;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 8'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = cmd_id;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:42:41 03/22/2015
// Design Name: xor2
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW1/prioencoder_test.v
// Project Name: HW1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: xor2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "prioencoder8x3.v"
module prioencoder_test;
// Inputs
reg [7:0] X;
reg enable;
// Outputs
wire Y1, Y2, Y3;
// Instantiate the Unit Under Test (UUT)
prioencoder8x3bit1 bit1(Y1, enable, X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]);
prioencoder8x3bit2 bit2(Y2, enable, X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]);
prioencoder8x3bit3 bit3(Y3, enable, X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]);
initial begin
// Initialize Inputs randomly
enable = 0;
{X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = $random % 256;
// Check output when enable is not yet set.
#10 enable = 0; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = $random % 256;
// Check outputs for values randomly.
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b10100100;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b01101000;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00100110;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00010101;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00001111;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00000101;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00000010;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00000001;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00000000;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b01001000;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b01000000;
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b01111011;
// Check for all 0's specifically
#10 enable = 1; {X[7], X[6], X[5], X[4], X[3], X[2], X[1], X[0]} = 8'b00000000;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100; int p[N]; vector<int> G[N]; int mn[N], mx[N], val[N], sum[N], s[N][2], c[N][2], fa[N], mp[N]; int head; void upd(int x) { sum[x] = sum[c[x][1]] + sum[c[x][0]] + val[x]; mn[x] = min(mn[c[x][0]], min(sum[c[x][0]] + val[x], sum[c[x][0]] + val[x] + mn[c[x][1]])); mx[x] = max(mx[c[x][0]], max(sum[c[x][0]] + val[x], sum[c[x][0]] + val[x] + mx[c[x][1]])); } void rot(int x, int d) { int f = fa[x]; c[f][d ^ 1] = c[x][d]; fa[c[x][d]] = f; if (fa[f]) c[fa[f]][(c[fa[f]][1] == f)] = x; fa[x] = fa[f]; c[x][d] = f; fa[f] = x; upd(f); upd(x); } void splay(int x, int stop) { int t, d1, d2; while ((t = fa[x]) - stop) { if (fa[t] == stop) rot(x, (c[fa[x]][0] == x)); else if ((d1 = (c[fa[t]][0] == t)) ^ (d2 = (c[fa[x]][0] == x))) rot(x, d2), rot(x, d1); else rot(t, d1), rot(x, d2); } head = stop ? head : x; } int Next(int x) { splay(x, 0); for (x = c[x][1]; c[x][0]; x = c[x][0]) ; return x; } int Prev(int x) { splay(x, 0); for (x = c[x][0]; c[x][1]; x = c[x][1]) ; return x; } void ins(int r, int x) { if (!r) { head = x; return; } int f = Next(r); if (!f) { fa[x] = r; c[r][1] = x; upd(r); } else { splay(f, r); fa[x] = f; c[f][0] = x; upd(f); upd(r); } splay(x, 0); } int cut(int l, int r) { int tl = Prev(l), tr = Next(r); if (!tl && !tr) return r; else if (!tl || !tr) { int d = !tr, f = tr + tl; splay(f, 0); int u = c[f][d]; fa[u] = c[f][d] = 0; upd(f); return u; } else { splay(tr, 0); splay(tl, tr); int u = c[tl][1]; fa[u] = c[tl][1] = 0; upd(tl); upd(tr); return u; } } int lasth(int x, int h) { for (h++;;) { if (sum[c[x][0]] + val[x] + mx[c[x][1]] >= h && sum[c[x][0]] + val[x] + mn[c[x][1]] <= h) { h -= sum[c[x][0]] + val[x]; x = c[x][1]; } else if (sum[c[x][0]] + val[x] == h) return (x == s[mp[x]][0] ? mp[x] : p[mp[x]]); else x = c[x][0]; } } int dis(int a, int b) { if (a == b) return 0; int u = s[a][0], v = s[b][0]; splay(v, 0); splay(u, v); if ((c[fa[u]][1] == u) == 1) { swap(u, v); splay(v, 0); splay(u, v); } int lcah = min(sum[c[u][0]] + val[u], min(sum[u] + val[v], sum[c[u][0]] + val[u] + mn[c[u][1]])); return sum[u] + sum[c[u][0]] + val[u] + val[v] - 2 * lcah; } void reorder(int u, int h) { int x = s[u][0]; splay(x, 0); int f = lasth(c[x][0], sum[c[x][0]] + val[x] - h - 1); p[u] = f; int cuted = cut(s[u][0], s[u][1]); ins(Prev(s[f][1]), cuted); } int T = 0; void build(int u) { s[u][0] = ++T; mp[T] = u; sum[T] = val[T] = mn[T] = mx[T] = 1; ins(head, T); for (int v : G[u]) build(v); s[u][1] = ++T; mp[T] = u; sum[T] = val[T] = mn[T] = mx[T] = -1; ins(head, T); } int main() { int n, m; scanf( %d%d , &n, &m); memset(mx, -63, sizeof mx); memset(mn, 63, sizeof mn); for (int i = 0; i < n; i++) { int sz = 0; scanf( %d , &sz); for (int j = 0; j < sz; j++) { int v; scanf( %d , &v); v--; G[i].push_back(v); p[v] = i; } } build(0); for (int i = 0; i < m; i++) { int c; scanf( %d , &c); if (c == 1) { int u, v; scanf( %d%d , &u, &v); u--; v--; printf( %d n , dis(u, v)); } else if (c == 2) { int u, h; scanf( %d%d , &u, &h); u--; reorder(u, h); } else { int h; scanf( %d , &h); printf( %d n , lasth(head, h) + 1); } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k = 0; cin >> n; int r[n]; for (int i = 0; i < n; ++i) { cin >> r[i]; if (r[i] % 2 == 1) ++k; } if (k % 2 == 0) cout << n - k; else cout << k; } |
#include <bits/stdc++.h> using namespace std; int ok[1 << 20]; int F[1 << 9][1 << 9]; int d[1 << 9]; int bfs(int n) { d[0] = 0; for (int i = 1; i <= n; ++i) d[i] = -1; queue<int> Q; Q.push(0); while (!Q.empty() && d[n] == -1) { int node = Q.front(); Q.pop(); for (int i = 0; i <= n; ++i) if (d[i] == -1 && F[node][i]) Q.push(i), d[i] = node; } if (d[n] == -1) return 0; int flow = 1e9; for (int vertex = n; vertex; vertex = d[vertex]) flow = min(flow, F[d[vertex]][vertex]); for (int vertex = n; vertex; vertex = d[vertex]) F[d[vertex]][vertex] -= flow, F[vertex][d[vertex]] += flow; return flow; } vector<int> order; int mark[1 << 9]; void dfs(int node, int n, int how) { mark[node] = 1; order.push_back(node); for (int i = 1; i <= n; ++i) if (!mark[i] && (F[node][i] == how && F[i][node] != how)) dfs(i, n, 1 - how); } int Val[1 << 9]; int main(void) { int n; for (int i = 2; i <= 1e6; ++i) ok[i] = 1; for (int i = 2; i <= 1e3; ++i) if (ok[i]) for (int j = i * i; j <= 1e6; j += i) ok[j] = 0; cin >> n; vector<int> a, b, pa, pb; for (int i = 1; i <= n; ++i) { int val; cin >> val; Val[i] = val; if (val & 1) a.push_back(val), pa.push_back(i); else b.push_back(val), pb.push_back(i); } if (a.size() != b.size()) return puts( Impossible ) * 0; int sz = a.size(); for (int i = 1; i <= sz; ++i) F[0][i] = 2; for (int i = 1; i <= sz; ++i) F[i + sz][sz + sz + 1] = 2; for (int i = 0; i < sz; ++i) for (int j = 0; j < sz; ++j) if (ok[a[i] + b[j]]) F[i + 1][j + 1 + sz] = 1; int flow = 0; int cnt = 0; while ((cnt = bfs(sz + sz + 1)) != 0) flow += cnt; if (flow != sz + sz) return puts( Impossible ) * 0; vector<vector<int> > cycles; for (int i = 1; i <= sz + sz; ++i) if (!mark[i]) { order.clear(); dfs(i, sz + sz, 0); for (auto &it : order) if (it <= sz) it = pa[it - 1]; else it = pb[it - sz - 1]; cycles.push_back(order); } cout << (cycles.size()) << n ; for (auto cycle : cycles) { cout << cycle.size() << ; for (auto it : cycle) cout << it << ; cout << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_1_V
`define SKY130_FD_SC_HDLL__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_1_V
|
module main_pll (
input inclk0,
output c0
);
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
assign c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=main_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: thesis_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module thesis_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites-new/thesis_new.mif",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites-new/thesis_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites-new/thesis_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
//////////////////////////
// arithmetic //
//////////////////////////
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH: 0 ] CARRY;
assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1];
// Due to VPR limitations regarding IO connexion to carry chain,
// we generate the carry chain input signal using an intermediate adder
// since we can connect a & b from io pads, but not cin & cout
generate
adder intermediate_adder (
.cin ( ),
.cout (CARRY[0]),
.a (CI ),
.b (CI ),
.sumout ( )
);
adder first_adder (
.cin (CARRY[0]),
.cout (CARRY[1]),
.a (AA[0] ),
.b (BB[0] ),
.sumout (Y[0] )
);
endgenerate
genvar i;
generate for (i = 1; i < Y_WIDTH ; i = i+1) begin:gen3
adder my_adder (
.cin (CARRY[i] ),
.cout (CARRY[i+1]),
.a (AA[i] ),
.b (BB[i] ),
.sumout (Y[i] )
);
end endgenerate
assign X = AA ^ BB;
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.12.beta1 (build 32746, 2013-12-02)
//
// On Thu Feb 27 22:22:33 CST 2014
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// result O 32 reg
// RDY_result O 1
// CLK I 1 clock
// RST_N I 1 reset
// start_a I 32
// start_b I 32
// EN_start I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkGCD(CLK,
RST_N,
start_a,
start_b,
EN_start,
RDY_start,
result,
RDY_result);
input CLK;
input RST_N;
// action method start
input [31 : 0] start_a;
input [31 : 0] start_b;
input EN_start;
output RDY_start;
// value method result
output [31 : 0] result;
output RDY_result;
// signals for module outputs
wire [31 : 0] result;
wire RDY_result, RDY_start;
// register x
reg [31 : 0] x;
wire [31 : 0] x$D_IN;
wire x$EN;
// register y
reg [31 : 0] y;
wire [31 : 0] y$D_IN;
wire y$EN;
// inputs to muxes for submodule ports
wire [31 : 0] MUX_x$write_1__VAL_2, MUX_y$write_1__VAL_2;
// remaining internal signals
wire x_ULE_y___d3;
// action method start
assign RDY_start = y == 32'd0 ;
// value method result
assign result = x ;
assign RDY_result = y == 32'd0 ;
// inputs to muxes for submodule ports
assign MUX_x$write_1__VAL_2 = x - y ;
assign MUX_y$write_1__VAL_2 = y - x ;
// register x
assign x$D_IN = EN_start ? start_a : MUX_x$write_1__VAL_2 ;
assign x$EN = EN_start || !x_ULE_y___d3 && y != 32'd0 ;
// register y
assign y$D_IN = EN_start ? start_b : MUX_y$write_1__VAL_2 ;
assign y$EN = EN_start || x_ULE_y___d3 && y != 32'd0 ;
// remaining internal signals
assign x_ULE_y___d3 = x <= y ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
x <= `BSV_ASSIGNMENT_DELAY 32'd0;
y <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
if (y$EN) y <= `BSV_ASSIGNMENT_DELAY y$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
x = 32'hAAAAAAAA;
y = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkGCD
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "SoC_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 105; struct ANS { int xa, ya, xb, yb, xc, yc; }; struct PRE { int p1, p2, s; } pre[MAXN][2][2]; int T, n, m; int a[MAXN][MAXN]; int f[MAXN][2][2]; char s[MAXN]; vector<ANS> ans; int popcount(int v) { return v ? popcount(v - (v & -v)) + 1 : 0; } void operate(int x, int y, int nx, int ny, bool flag = 0) { if (flag) ans.push_back((ANS){0, 0, 0, 0, 0, 0}); for (int i = 0; i <= 1; i++) for (int j = 0; j <= 1; j++) if (x + i != nx || j + y != ny) { if (flag) { if (ans.back().xa) { if (ans.back().xb) { ans.back().xc = x + i; ans.back().yc = y + j; } else { ans.back().xb = x + i; ans.back().yb = y + j; } } else { ans.back().xa = x + i; ans.back().ya = y + j; } } a[x + i][y + j] ^= 1; } } int main() { scanf( %d , &T); while (T--) { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); for (int j = 1; j <= m; j++) a[i][j] = s[j] - 0 ; } ans.clear(); for (int i = 1; i <= n - 2; i++) for (int j = 1; j <= m; j++) if (a[i][j]) { if (j < m) operate(i, j, i, j + 1, 1); else operate(i, j - 1, i, j - 1, 1); } for (int i = 1; i <= m; i++) for (int j = 0; j <= 1; j++) for (int k = 0; k <= 1; k++) f[i][j][k] = 1e9; f[1][a[n - 1][1]][a[n][1]] = 0; for (int i = 1; i < m; i++) for (int j = 0; j <= 1; j++) for (int k = 0; k <= 1; k++) if (f[i][j][k] != 1e9) { int t1 = a[n - 1][i], t2 = a[n][i]; a[n - 1][i] = j; a[n][i] = k; for (int l = 0; l < 16; l++) { if (l & 1) operate(n - 1, i, n - 1, i); if (l >> 1 & 1) operate(n - 1, i, n, i); if (l >> 2 & 1) operate(n - 1, i, n - 1, i + 1); if (l >> 3 & 1) operate(n - 1, i, n, i + 1); if (!a[n - 1][i] && !a[n][i] && f[i + 1][a[n - 1][i + 1]][a[n][i + 1]] > f[i][j][k] + popcount(l)) { f[i + 1][a[n - 1][i + 1]][a[n][i + 1]] = f[i][j][k] + popcount(l); pre[i + 1][a[n - 1][i + 1]][a[n][i + 1]] = (PRE){j, k, l}; } if (l & 1) operate(n - 1, i, n - 1, i); if (l >> 1 & 1) operate(n - 1, i, n, i); if (l >> 2 & 1) operate(n - 1, i, n - 1, i + 1); if (l >> 3 & 1) operate(n - 1, i, n, i + 1); } a[n - 1][i] = t1; a[n][i] = t2; } int t1 = 0, t2 = 0; for (int i = m; i > 1; i--) { int l = pre[i][t1][t2].s; if (l & 1) operate(n - 1, i - 1, n - 1, i - 1, 1); if (l >> 1 & 1) operate(n - 1, i - 1, n, i - 1, 1); if (l >> 2 & 1) operate(n - 1, i - 1, n - 1, i, 1); if (l >> 3 & 1) operate(n - 1, i - 1, n, i, 1); int n1 = pre[i][t1][t2].p1, n2 = pre[i][t1][t2].p2; t1 = n1; t2 = n2; } printf( %d n , (int)ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d %d %d %d %d %d n , ans[i].xa, ans[i].ya, ans[i].xb, ans[i].yb, ans[i].xc, ans[i].yc); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2) { cout << black << endl; } else { cout << white << n1 2 n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int N, M; cin >> N >> M; int a[N][M]; for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { cin >> a[i][j]; } } long long l = 0, r = 1e9 + 1; int i1 = 1, i2 = 1; int vis[1 << M]; while (r - l > 1) { long long m = (l + r) >> 1; bool check = false; memset(vis, 0, sizeof(vis)); for (int i = 0; i < N; i++) { int bit = 0; for (int j = 0; j < M; j++) { if (a[i][j] >= m) { bit ^= (1 << j); } } vis[bit] = i + 1; } for (int i = 0; i < (1 << M); i++) { for (int j = 0; j < (1 << M); j++) { if (vis[i] && vis[j] && ((i | j) + 1) == (1 << M)) { i1 = vis[i], i2 = vis[j]; check = true; break; } } } if (check) l = m; else r = m; } cout << i1 << << i2; } |
#include <bits/stdc++.h> using namespace std; void solve() { string number; cin >> number; int n = number.length(); int answer; vector<vector<int> > remainders = { {}, {1}, {1, 2, 4, 3}, {1, 3, 4, 2}, {1, 4}}; int last_digit = number[n - 1] - 0 ; if (n == 1) { answer = (remainders[1][last_digit % 1] + remainders[2][last_digit % 4] + remainders[3][last_digit % 4] + remainders[4][last_digit % 2]) % 5; } else { int last_two_digits = (number[n - 1] - 0 ) + 10 * (number[n - 2] - 0 ); answer = (remainders[1][last_two_digits % 1] + remainders[2][last_two_digits % 4] + remainders[3][last_two_digits % 4] + remainders[4][last_two_digits % 2]) % 5; } cout << answer << endl; } int main() { { ios::sync_with_stdio(false); cout << fixed << setprecision(10); } solve(); return 0; } |
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