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#include <bits/stdc++.h> using namespace std; const int maxn = 5000 + 10; int main() { int n, k; int a[maxn]; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , &a[i]); int sum = 0; int maxs = 0; double maxa = 0; for (int i = k; i <= n; i++) { for (int j = 0; j < i; j++) sum += a[j]; maxs = sum; for (int j = 1; j < n - i + 1; j++) { sum = sum - a[j - 1] + a[j + i - 1]; maxs = max(maxs, sum); } double a = maxs * 1.0 / i; maxa = max(maxa, a); sum = 0; } printf( %lf n , maxa); return 0; } |
#include <bits/stdc++.h> using namespace std; int read(); const int N = 1.5e5 + 5; int n, p, k, m, a[N]; vector<pair<int, int> > seg[N << 2], res; int eq[N << 2]; void puteq(int k, int l, int r, int v) { eq[k] = v; seg[k].clear(); seg[k].push_back(make_pair(v, r - l + 1)); } bool cmp(const pair<int, int> &a, const pair<int, int> &b) { return a.second > b.second; } void pushup(vector<pair<int, int> > &a, vector<pair<int, int> > &b) { for (int i = (0); i < (b.size()); ++i) a.push_back(b[i]); sort(a.begin(), a.end()); for (int i = (0); i < (int(a.size()) - 1); ++i) if (a[i].first == a[i + 1].first) a[i + 1].second += a[i].second, a[i].second = 0; sort(a.begin(), a.end(), cmp); while (a.size() && a.back().second == 0) a.pop_back(); while (a.size() > k) { for (int i = (k + 1); i >= (1); --i) a[a.size() - i].second -= a.back().second; while (a.size() && a.back().second == 0) a.pop_back(); } } void pushdown(int k, int l, int r, int mid) { if (eq[k]) { puteq((k << 1), l, mid, eq[k]); puteq(((k << 1) | 1), mid + 1, r, eq[k]); eq[k] = 0; } } void change(int k, int l, int r, int x, int y, int v) { if (x <= l && r <= y) return puteq(k, l, r, v); int mid = l + r >> 1; pushdown(k, l, r, mid); if (x <= mid) change((k << 1), l, mid, x, y, v); if (y > mid) change(((k << 1) | 1), mid + 1, r, x, y, v); seg[k] = seg[(k << 1)]; pushup(seg[k], seg[((k << 1) | 1)]); } vector<pair<int, int> > ans; void query(int k, int l, int r, int x, int y) { if (x <= l && r <= y) return pushup(ans, seg[k]); int mid = l + r >> 1; pushdown(k, l, r, mid); if (x <= mid) query((k << 1), l, mid, x, y); if (y > mid) query(((k << 1) | 1), mid + 1, r, x, y); } void build(int k, int l, int r) { if (l == r) { seg[k].push_back(make_pair(a[l], 1)); return; } int mid = l + r >> 1; build((k << 1), l, mid), build(((k << 1) | 1), mid + 1, r); seg[k] = seg[(k << 1)], pushup(seg[k], seg[((k << 1) | 1)]); } int main() { scanf( %d%d%d , &n, &m, &p); k = 100 / p; for (int i = (1); i <= (n); ++i) scanf( %d , a + i); build(1, 1, n); while (m--) { static int op, l, r, v; scanf( %d%d%d , &op, &l, &r); if (op == 1) scanf( %d , &v), change(1, 1, n, l, r, v); else { ans.clear(); query(1, 1, n, l, r); printf( %d , int(ans.size())); for (int i = (0); i < (ans.size()); ++i) printf( %d , ans[i].first); puts( ); } } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:41:11 11/25/2009
// Design Name:
// Module Name: tetris_blocks
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//------------------------------------------------------------------------
// given a type and rotation outputs the block encoded in a 16 bit int
//------------------------------------------------------------------------
module JIZLOTS_sel(input[2:0] type, input[1:0] rot, output reg[0:15] block);
wire[0:15] block_t, block_z, block_s, block_j, block_l, block_o, block_i;
T_sel t(rot, block_t);
Z_sel z(rot, block_z);
S_sel s(rot, block_s);
J_sel j(rot, block_j);
L_sel l(rot, block_l);
O_sel o(rot, block_o);
I_sel i(rot, block_i);
always @*
begin
case(type)
0: block = block_t;
1: block = block_z;
2: block = block_s;
3: block = block_j;
4: block = block_l;
5: block = block_o;
6: block = block_i;
default: block = 0; //shouldn't happen
endcase
end
endmodule
module T_sel(input[1:0] rot, output reg[0:15] block);
wire[0:15] t0 = 16'b1110010000000000;
wire[0:15] t1 = 16'b0010011000100000;
wire[0:15] t2 = 16'b0000010011100000;
wire[0:15] t3 = 16'b1000110010000000;
always @*
begin
case(rot)
0: block = t0;
1: block = t1;
2: block = t2;
3: block = t3;
default: block = t0;
endcase
end
endmodule
module Z_sel(input[1:0] rot, output reg[0:15] block);
wire[0:15] z0 = 16'b1100011000000000;
wire[0:15] z1 = 16'b0010011001000000;
wire[0:15] z2 = 16'b0000110001100000;
wire[0:15] z3 = 16'b0100110010000000;
always @*
begin
case(rot)
0: block = z0;
1: block = z1;
2: block = z2;
3: block = z3;
default: block = z0;
endcase
end
endmodule
module S_sel(input[1:0] rot, output reg[0:15] block);
wire[0:15] s0 = 16'b0110110000000000;
wire[0:15] s1 = 16'b0100011000100000;
wire[0:15] s2 = 16'b0000011011000000;
wire[0:15] s3 = 16'b1000110001000000;
always @*
begin
case(rot)
0: block = s0;
1: block = s1;
2: block = s2;
3: block = s3;
default: block = s0;
endcase
end
endmodule
module J_sel(input[1:0] rot, output reg[0:15] block);
wire[0:15] j0 = 16'b0100010011000000;
wire[0:15] j1 = 16'b1000111000000000;
wire[0:15] j2 = 16'b0110010001000000;
wire[0:15] j3 = 16'b0000111000100000;
always @*
begin
case(rot)
0: block = j0;
1: block = j1;
2: block = j2;
3: block = j3;
default: block = j0;
endcase
end
endmodule
module L_sel(input[1:0] rot, output reg[0:15] block);
wire[0:15] l0 = 16'b0100010011000000;
wire[0:15] l1 = 16'b0000111010000000;
wire[0:15] l2 = 16'b1100010001000000;
wire[0:15] l3 = 16'b0010111000000000;
always @*
begin
case(rot)
0: block = l0;
1: block = l1;
2: block = l2;
3: block = l3;
default: block = l0;
endcase
end
endmodule
module O_sel(input[1:0] rot, output reg[0:15] block);
wire[0:15] o0 = 16'b1100110000000000;
always @*
begin
case(rot)
default: block = o0;
endcase
end
endmodule
module I_sel(input[1:0] rot, output reg[0:15] block);
wire[0:15] i0 = 16'b1000100010001000;
wire[0:15] i1 = 16'b0000000011110000;
always @*
begin
case(rot)
0: block = i0;
1: block = i1;
2: block = i0;
3: block = i1;
default: block = i0;
endcase
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Detects rising edge of input signal and outputs a single-shot
// signal upon detection
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rising_edge_detect(
input clk,
input rst,
input in,
output one_shot_out);
reg in_reg;
//register the input
always@(posedge clk)begin
if(rst)begin
in_reg <= 1'b0;
end else begin
in_reg <= in;
end
end
//detect the rising edge
assign one_shot_out = ~in_reg & in;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> istream &operator>>(istream &in, pair<T1, T2> &P) { in >> P.first >> P.second; return in; } template <class T1, class T2> ostream &operator<<(ostream &out, const pair<T1, T2> &P) { out << ( << P.first << , << P.second << ) ; return out; } template <class T> istream &operator>>(istream &in, vector<T> &arr) { for (auto &x : arr) in >> x; return in; } template <class T> ostream &operator<<(ostream &out, const vector<T> &arr) { for (auto &x : arr) out << x << ; cout << n ; return out; } template <class T> istream &operator>>(istream &in, deque<T> &arr) { for (auto &x : arr) in >> x; return in; } template <class T> ostream &operator<<(ostream &out, const deque<T> &arr) { for (auto &x : arr) out << x << ; cout << n ; return out; } long long n, m, q, k, v[1000050], l, pref[1000050]; pair<long long, long long> TT, w[1000050]; string second; long long dp[1000050]; long long prox[1000050]; long long resolve(long long cost) { memset(dp, 0, sizeof dp); for (long long i = n; i >= 1; i--) { long long A = dp[min(n + 1, i + l)] + (pref[min(n, i + l - 1)] - pref[i - 1]) - cost; long long B = dp[i + 1]; if (A > B) prox[i] = 0; else prox[i] = 1; dp[i] = max(A, B); } long long j = 1, usados = 0; while (j <= n) { if (!prox[j]) usados++, j = j + l; else j = j + 1; } return usados; } long long solve(long long a, long long b) { long long ini = 0, fim = 200000000000000000, mid, best = -1; while (fim >= ini) { mid = (ini + fim) / 2; long long us = resolve(mid); if (us <= k) best = mid, fim = mid - 1; else ini = mid + 1; } if (best == -1) return 0; long long us = resolve(best); return dp[1] + k * best; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k >> l; cin >> second; for (long long i = 1; i <= n; i++) { if ( a <= second[i - 1] and second[i - 1] <= z ) v[i] = 0; else v[i] = 1; } for (long long i = 1; i <= n; i++) pref[i] = pref[i - 1] + v[i]; long long A = pref[n] - solve(1, k); for (long long i = 1; i <= n; i++) { v[i] ^= 1; pref[i] = pref[i - 1] + v[i]; } long long B = pref[n] - solve(1, k); cout << min(A, B) << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6; vector<long long> v[105]; map<long long, long long> mp; int vis[105]; long long cnt, cnt2; void dfs(int s) { vis[s] = 1; cnt += v[s].size(); cnt2++; for (int i = 0; i < v[s].size(); i++) { if (!vis[v[s][i]]) dfs(v[s][i]); } } int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m, b, ans = 0, ans2, x, y, z, i, s; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } for (int i = 1; i <= n; i++) { if (!vis[i]) { cnt = 0; cnt2 = 0; dfs(i); if (cnt2 * 2 == cnt) { if (cnt2 % 2) ans++; } } } if ((n - ans) % 2 == 0) cout << ans; else cout << ans + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int a, b; node(int a = 0, int b = (int)1e9) : a(a), b(b) {} int get(int x) { return a * x + b; } }; struct Zwei { vector<node> st; vector<int> a; int n; void add(int pos) { a.push_back(pos); } void update() { sort(a.begin(), a.end()); a.resize(unique(a.begin(), a.end()) - a.begin()); n = (int)a.size(); st.resize(n << 2 | 1); } void modify(int id, int l, int r, node val) { int mid = l + r >> 1; if (st[id].get(a[mid]) > val.get(a[mid])) swap(st[id], val); if (l == r) return; if (st[id].get(a[l]) > val.get(a[l])) modify(id << 1, l, mid, val); if (st[id].get(a[r]) > val.get(a[r])) modify(id << 1 | 1, mid + 1, r, val); } int get(int id, int l, int r, int v) { int ans = st[id].get(v); if (l == r) assert(a[l] == v); if (l == r) return ans; int mid = l + r >> 1; if (v <= a[mid]) return min(ans, get(id << 1, l, mid, v)); return min(ans, get(id << 1 | 1, mid + 1, r, v)); } int get(int v) { if (!n) return (int)1e9; return get(1, 0, n - 1, v); } void modify(node val) { if (!n) return; modify(1, 0, n - 1, val); } }; struct Eins { vector<Zwei> st; int n; Eins(int n) : n(n) { st.resize(n << 2 | 1); } void build(int id, int l, int r) { st[id].update(); if (l == r) return; int mid = l + r >> 1; build(id << 1, l, mid); build(id << 1 | 1, mid + 1, r); } void add(int id, int l, int r, int L, int R, int v) { if (L <= l && r <= R) { st[id].add(v); return; } int mid = l + r >> 1; if (L <= mid) add(id << 1, l, mid, L, R, v); if (R > mid) add(id << 1 | 1, mid + 1, r, L, R, v); } void modify(int id, int l, int r, int pos, node val) { st[id].modify(val); if (l == r) return; int mid = l + r >> 1; if (pos <= mid) modify(id << 1, l, mid, pos, val); else modify(id << 1 | 1, mid + 1, r, pos, val); } int get(int id, int l, int r, int L, int R, int v) { if (L <= l && r <= R) return st[id].get(v); int mid = l + r >> 1; int ans = (int)1e9 + 1; if (L <= mid) ans = min(ans, get(id << 1, l, mid, L, R, v)); if (R > mid) ans = min(ans, get(id << 1 | 1, mid + 1, r, L, R, v)); return ans; } }; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a(n + 1); vector<int> t(n + 1); for (int i = 1; i <= n; i++) { cin >> a[i]; t[i] = t[i - 1] + a[i]; } int q; cin >> q; vector<pair<int, int>> Query; Eins Tree(n); while (q--) { int x, y; cin >> x >> y; Query.emplace_back(x, y); Tree.add(1, 1, n, y - x + 1, y, y - x); } Tree.build(1, 1, n); for (int i = 1; i <= n; i++) Tree.modify(1, 1, n, i, node(-a[i], a[i] * i - t[i])); for (auto& x : Query) { cout << Tree.get(1, 1, n, x.second - x.first + 1, x.second, x.second - x.first) + t[x.second] << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A41O_BEHAVIORAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, sz[maxn], ans[maxn]; long long sum; vector<int> adj[maxn], vec; void dfs(int u, int par) { sz[u] = 1; for (auto v : adj[u]) if (v != par) { dfs(v, u); sz[u] += sz[v]; } } void DFSend(int u, int par) { vec.push_back(u); for (auto v : adj[u]) if (v != par) DFSend(v, u); } int centroid(int u, int par) { for (auto v : adj[u]) if (v != par && sz[v] * 2 > n) return centroid(v, u); return u; } void read_input() { cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } } void solve() { dfs(1, 0); for (int i = 1; i <= n; i++) sum += min(sz[i], n - sz[i]); sum *= 2; DFSend(centroid(1, 0), -1); for (int i = 0; i < n; i++) ans[vec[i]] = vec[(i + n / 2) % n]; cout << sum << n ; for (int i = 1; i <= n; i++) cout << ans[i] << ; } int main() { read_input(), solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200010; int T, n, m, ans; char s[N], p[N]; int ne[N], len[N]; int main() { scanf( %s , s + 1); m = strlen(s + 1); cin >> T; while (T--) { scanf( %s , p + 1); n = strlen(p + 1); if (n == 1) continue; for (int i = 2, j = 0; i <= n; i++) { while (j && p[i] != p[j + 1]) j = ne[j]; if (p[i] == p[j + 1]) j++; ne[i] = j; } memset(len, 0, sizeof len); for (int i = 1, j = 0; i <= m; i++) { while (j && s[i] != p[j + 1]) j = ne[j]; if (s[i] == p[j + 1]) j++; len[i] = max(len[i - 1], j); if (j == n) j = ne[j]; } memset(ne, 0, sizeof ne); for (int i = 2, j = 0; i <= n; i++) { while (j && p[n - i + 1] != p[n - j]) j = ne[j]; if (p[n - i + 1] == p[n - j]) j++; ne[i] = j; } bool flag = false; for (int i = 1, j = 0; i <= m; i++) { while (j && s[m - i + 1] != p[n - j]) j = ne[j]; if (s[m - i + 1] == p[n - j]) j++; if (j && len[m - i] && (j + len[m - i] >= n)) { flag = true; break; } if (j == n) j = ne[j]; } if (flag) ans++; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, sx, sy, dx, dy, t; struct matrix { long long m[8][8]; matrix() { memset(m, 0, sizeof(m)); } }; matrix mul(matrix a, matrix b) { matrix tmp; for (int i = 1; i <= 6; i++) for (int k = 1; k <= 6; k++) if (a.m[i][k]) for (int j = 1; j <= 6; j++) tmp.m[i][j] = (tmp.m[i][j] + a.m[i][k] * b.m[k][j] + n) % n; return tmp; } matrix powmul(matrix a, long long t) { matrix tmp; for (int i = 1; i <= 6; i++) tmp.m[i][i] = 1; while (t) { if (t & 1) tmp = mul(tmp, a); a = mul(a, a); t >>= 1; } return tmp; } int main() { scanf( %lld%lld%lld%lld%lld%lld , &n, &sx, &sy, &dx, &dy, &t); matrix base; base.m[1][2] = base.m[1][3] = base.m[1][5] = 1; base.m[2][1] = base.m[2][4] = base.m[2][5] = 1; base.m[3][1] = base.m[3][2] = base.m[3][3] = base.m[3][5] = 1; base.m[4][1] = base.m[4][2] = base.m[4][4] = base.m[4][5] = 1; base.m[5][5] = base.m[5][6] = base.m[6][6] = 1; base.m[2][2] = base.m[1][1] = base.m[1][6] = base.m[2][6] = base.m[3][6] = base.m[4][6] = 2; base = powmul(base, t); matrix ans; ans.m[1][1] = sx - 1; ans.m[2][1] = sy - 1; ans.m[3][1] = (dx % n + n) % n; ans.m[4][1] = (dy % n + n) % n; ans.m[6][1] = 1; ans = mul(base, ans); printf( %lld %lld n , ans.m[1][1] + 1, ans.m[2][1] + 1); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_M_V
`define SKY130_FD_SC_LP__OR2B_M_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2b_m (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2b_m (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_M_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ans, t, s, a, i, b, k; int main() { cin >> k >> a >> b; s = (0 - a) / k + 1; while (a <= 0) { a = a + s * k; b = s * k + b; } ans = b / k - (a - 1) / k; cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000020; const int maxm = 1000020; const int MOd = 998244353; void solve() { string s; cin >> s; int c = 0, c1 = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == 0 ) { if (!c) printf( 1 1 n ); else printf( 3 1 n ); c ^= 1; } else { if (!c1) printf( 4 3 n ); else printf( 4 1 n ); c1 ^= 1; } } } int main() { int n = 1; while (n--) solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_2_V
`define SKY130_FD_SC_LP__OR3B_2_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_2_V
|
// Check that packed arrays of all sorts get elaborated without an error and
// that the resulting type has the right packed width.
module test;
typedef bit bit2;
typedef logic [1:0] vector;
bit2 [1:0] b;
vector [2:0] l;
typedef enum logic [7:0] {
A
} E;
typedef E [1:0] EP;
typedef EP [2:0] EPP;
E e;
EP ep1;
E [1:0] ep2;
EP [2:0] epp1;
EPP epp2;
EPP [3:0] eppp;
typedef struct packed {
longint x;
} S1;
typedef struct packed {
time t;
integer i;
logic [1:0] x;
bit [3:0] y;
int z;
shortint w;
E e;
EP ep;
S1 s;
} S2;
localparam S_SIZE = 64 + 32 + 2 + 4 + 32 + 16 + 8 + 8*2 + 64;
typedef S2 [3:0] SP;
typedef SP [9:0] SPP;
S2 s;
SP sp1;
S2 [3:0] sp2;
SP [9:0] spp1;
SPP spp2;
SPP [1:0] sppp;
bit failed = 1'b0;
initial begin
// Packed arrays of basic types
failed |= $bits(b) !== 2;
failed |= $bits(l) !== 2 * 3;
// Packed arrays of enums
failed |= $bits(e) !== 8;
failed |= $bits(ep1) !== $bits(e) * 2;
failed |= $bits(ep2) !== $bits(ep1);
failed |= $bits(epp1) !== $bits(ep1) * 3;
failed |= $bits(epp2) !== $bits(epp1);
failed |= $bits(eppp) !== $bits(epp1) * 4;
// Packed arrays of structs
failed |= $bits(s) !== S_SIZE;
failed |= $bits(sp1) != $bits(s) * 4;
failed |= $bits(sp2) != $bits(sp1);
failed |= $bits(spp1) != $bits(sp1) * 10;
failed |= $bits(spp1) != $bits(spp2);
failed |= $bits(sppp) != $bits(spp1) * 2;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`default_nettype none
module l1_data_cache_counter(
input wire iCLOCK,
input wire inRESET,
//Hit Infomation
input wire iCACHE_VALID,
input wire iCACHE_HIT,
//Infomation
output wire [6:0] oINFO_COUNT
);
reg [99:0] b_counter;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_counter <= 100'h0;
end
else begin
if(iCACHE_VALID)begin
b_counter <= {b_counter[98:0], iCACHE_HIT};
end
end
end
reg [3:0] b_buffer0[0:9]; //10*10
reg [5:0] b_buffer1[0:1]; //50*2
reg [6:0] b_buffer2; //100*1
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_buffer0[0] <= 4'h0;
b_buffer0[1] <= 4'h0;
b_buffer0[2] <= 4'h0;
b_buffer0[3] <= 4'h0;
b_buffer0[4] <= 4'h0;
b_buffer0[5] <= 4'h0;
b_buffer0[6] <= 4'h0;
b_buffer0[7] <= 4'h0;
b_buffer0[8] <= 4'h0;
b_buffer0[9] <= 4'h0;
b_buffer1[0] <= 6'h0;
b_buffer1[1] <= 6'h1;
b_buffer2 <= 7'h0;
end
else begin
//Buffer0
b_buffer0[0] <= 4'h0
+ b_counter[0] + b_counter[1] + b_counter[2] + b_counter[3] + b_counter[4]
+ b_counter[5] + b_counter[6] + b_counter[7] + b_counter[8] + b_counter[9];
b_buffer0[1] <= 4'h0
+ b_counter[10] + b_counter[11] + b_counter[12] + b_counter[13] + b_counter[14]
+ b_counter[15] + b_counter[16] + b_counter[17] + b_counter[18] + b_counter[19];
b_buffer0[2] <= 4'h0
+ b_counter[20] + b_counter[21] + b_counter[22] + b_counter[23] + b_counter[24]
+ b_counter[25] + b_counter[26] + b_counter[27] + b_counter[28] + b_counter[29];
b_buffer0[3] <= 4'h0
+ b_counter[30] + b_counter[31] + b_counter[32] + b_counter[33] + b_counter[34]
+ b_counter[35] + b_counter[36] + b_counter[37] + b_counter[38] + b_counter[39];
b_buffer0[4] <= 4'h0
+ b_counter[40] + b_counter[41] + b_counter[42] + b_counter[43] + b_counter[44]
+ b_counter[45] + b_counter[46] + b_counter[47] + b_counter[48] + b_counter[49];
b_buffer0[5] <= 4'h0
+ b_counter[50] + b_counter[51] + b_counter[52] + b_counter[53] + b_counter[54]
+ b_counter[55] + b_counter[56] + b_counter[57] + b_counter[58] + b_counter[59];
b_buffer0[6] <= 4'h0
+ b_counter[60] + b_counter[61] + b_counter[62] + b_counter[63] + b_counter[64]
+ b_counter[65] + b_counter[66] + b_counter[67] + b_counter[68] + b_counter[69];
b_buffer0[7] <= 4'h0
+ b_counter[70] + b_counter[71] + b_counter[72] + b_counter[73] + b_counter[74]
+ b_counter[75] + b_counter[76] + b_counter[77] + b_counter[78] + b_counter[79];
b_buffer0[8] <= 4'h0
+ b_counter[80] + b_counter[81] + b_counter[82] + b_counter[83] + b_counter[84]
+ b_counter[85] + b_counter[86] + b_counter[87] + b_counter[88] + b_counter[89];
b_buffer0[9] <= 4'h0
+ b_counter[90] + b_counter[91] + b_counter[92] + b_counter[93] + b_counter[94]
+ b_counter[95] + b_counter[96] + b_counter[97] + b_counter[98] + b_counter[99];
b_buffer1[0] <= 6'h0 + b_buffer0[0] + b_buffer0[1] + b_buffer0[2] + b_buffer0[3] + b_buffer0[4];
b_buffer1[1] <= 6'h0 + b_buffer0[5] + b_buffer0[6] + b_buffer0[7] + b_buffer0[8] + b_buffer0[9];
b_buffer2 <= b_buffer1[0] + b_buffer1[1];
end
end
assign oINFO_COUNT = b_buffer2;
endmodule
`default_nettype wire
|
/**************************************
* Module: simul_axi_fifo
* Date:2014-03-23
* Author: Andrey Filippov
*
* Description:
***************************************/
`timescale 1ns/1ps
module simul_axi_fifo
#(
parameter integer WIDTH= 64, // total number of output bits
parameter integer LATENCY=0, // minimal delay between inout and output ( 0 - next cycle)
parameter integer DEPTH=8, // maximal number of commands in FIFO
// parameter OUT_DELAY = 3.5,
parameter integer FIFO_DEPTH=LATENCY+DEPTH+1
// parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
)(
input clk,
input reset,
input [WIDTH-1:0] data_in,
input load,
output input_ready,
output [WIDTH-1:0] data_out,
output valid,
input ready);
reg [WIDTH-1:0] fifo [0:FIFO_DEPTH-1];
integer in_address;
integer out_address;
integer in_count;
integer out_count;
reg [LATENCY:0] latency_delay_r;
wire [LATENCY+1:0] latency_delay={latency_delay_r,load};
wire out_inc=latency_delay[LATENCY];
assign data_out= fifo[out_address];
assign valid= out_count!=0;
assign input_ready= in_count<DEPTH;
// assign out_inc={
always @ (posedge clk or posedge reset) begin
if (reset) latency_delay_r <= 0;
else latency_delay_r <= latency_delay[LATENCY:0];
if (reset) in_address <= 0;
else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
if (reset) out_address <= 0;
else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
if (reset) in_count <= 0;
else if (!(valid && ready) && load) in_count <= in_count+1;
else if (valid && ready && !load) in_count <= in_count-1;
if (reset) out_count <= 0;
else if (!(valid && ready) && out_inc) out_count <= out_count+1;
else if (valid && ready && !out_inc) out_count <= out_count-1;
end
always @ (posedge clk) begin
if (load) fifo[in_address] <= data_in;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { long long n, d, m; cin >> n >> d >> m; long long ans = 0; long long a[n]; vector<long long> big, small; for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) { if (a[i] > m) big.push_back(a[i]); else small.push_back(a[i]); } sort(big.rbegin(), big.rend()); sort(small.rbegin(), small.rend()); long long p = big.size(), q = small.size(); for (long long i = 1; i < p; i++) big[i] += big[i - 1]; for (long long i = 1; i < q; i++) small[i] += small[i - 1]; if (q > 0) ans = small[q - 1]; for (long long i = 0; i < p; i++) { if (i * (d + 1) + 1 <= n) { ans = max(ans, big[i]); long long rem = n - (i * (d + 1) + 1); long long ind = -1; if (q > 0 and rem > 0) { ind = max(0LL, min(rem - 1LL, q - 1)); ans = max(ans, big[i] + small[ind]); } } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; const long long INF = 1e18; const long long MOD = 1000000007; long double A[100005], B[100005]; int main() { int n, p; cin >> n >> p; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; A[i] = y / p; A[i] -= (x - 1) / p; B[i] = (y - x + 1); } long double res; long double ans = 0; for (int i = 1; i < n; i++) { res = (A[i] * A[i - 1]) + (A[i] * (B[i - 1] - A[i - 1])) + (A[i - 1] * (B[i] - A[i])); long double d = B[i] * B[i - 1]; res = res / d; res = res * 2000; ans += res; } res = (A[0] * A[n - 1]) + (A[0] * (B[n - 1] - A[n - 1])) + (A[n - 1] * (B[0] - A[0])); long double d = B[0] * B[n - 1]; res = res / d; res = res * 2000; ans += res; cout << setprecision(10) << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300010; int n, l[N], t[N]; long long r, dv, res, tcur; vector<long long> ans; void solve(int l, int t) { if (2 * l <= t) { tcur += 2 * l; return; } long long x = t - l; long long tmp = (1ll * l - x + r - 1) / r; res += tmp; dv = x + tmp * r - l; tcur += 2 * x; long long t1 = tcur; while (ans.size() < 1e5 + 10 && tmp) { ans.push_back(t1); tmp--; t1 += r; } tcur += l - x; } int main() { cin >> n >> r; for (int i = 1; i <= n; i++) cin >> l[i]; for (int i = 1; i <= n; i++) cin >> t[i]; res = 0; dv = 0; tcur = 0; for (int i = 1; i <= n; i++) { if (l[i] > t[i]) { res = -1; break; } if (l[i] <= dv) { dv -= l[i]; tcur += l[i]; continue; } l[i] -= dv; t[i] -= dv; tcur += dv; dv = 0; solve(l[i], t[i]); } cout << res << endl; if (res != -1 && ans.size() <= 1e5) { assert(res == ans.size()); for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, d; vector<int> e[100000 + 5], lst[100000 + 5]; int dfn[100000 + 5], low[100000 + 5], cnt, tot, sta[100000 + 5], ptr, scc[100000 + 5], cycle[100000 + 5]; char open[100000 + 5][55]; void tarjan(int now) { dfn[now] = low[now] = ++cnt; sta[++ptr] = now; for (auto v : e[now]) { if (!dfn[v]) { tarjan(v); low[now] = min(low[now], low[v]); } else if (!scc[v]) low[now] = min(low[now], dfn[v]); } if (low[now] == dfn[now]) { tot++; while (sta[ptr] != now) scc[sta[ptr--]] = tot; scc[sta[ptr--]] = tot; } return; } int gcd(int x, int y) { return x ? gcd(y % x, x) : y; } int _gcd[55]; bool can[100000 + 5][55]; int off[100000 + 5]; pair<int, int> q[100000 * 50 + 5]; void bfs(int s, int id) { int rear = 0; q[rear].first = s; q[rear].second = 0; can[s][0] = 1; for (int front = 0; front <= rear; front++) { int now = q[front].first; int day = q[front].second; int nd = (day + 1) % d; for (auto v : e[now]) if (scc[v] == id) { if (can[v][nd] == 0) { can[v][nd] = 1; rear++; q[rear].first = v; q[rear].second = nd; } } } cycle[id] = d; for (int i = 1; i <= d - 1; i++) if (can[s][i]) { cycle[id] = i; break; } assert(d % cycle[id] == 0); } int dp[100000 + 5][55], dpscc[100000 + 5][55]; void upd(int &x, int y) { if (y > x) x = y; } int main() { scanf( %d%d%d , &n, &m, &d); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); e[x].push_back(y); } for (int i = 1; i <= n; i++) scanf( %s , open[i]); for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(i); for (int i = 1; i <= n; i++) lst[scc[i]].push_back(i); for (int i = 1; i <= tot; i++) bfs(lst[i][0], i); for (int i = 1; i <= n; i++) { for (int j = 0; j <= d - 1; j++) if (can[i][j]) { off[i] = j; break; } } memset(dp, -1, sizeof dp); memset(dpscc, -1, sizeof dpscc); int ans = 0; dpscc[scc[1]][0] = 0; for (int id = tot; id >= 1; id--) { int c = cycle[id]; int cnt[55] = {}; for (auto now : lst[id]) { bool tmp[55] = {}; for (int i = 0; i <= d - 1; i++) if (open[now][i] == 1 ) tmp[(i - off[now] + c) % c] = 1; for (int i = 0; i <= d - 1; i++) cnt[i] += tmp[i]; } for (auto now : lst[id]) { for (int i = 0; i <= d - 1; i++) if (dpscc[id][(i - off[now] + c) % c] >= 0) dp[now][i] = dpscc[id][(i - off[now] + c) % c] + cnt[(i - off[now] + c) % c]; for (int i = 0; i <= d - 1; i++) ans = max(ans, dp[now][i]); } for (auto now : lst[id]) for (auto v : e[now]) if (scc[v] != id) { int nid = scc[v]; for (int i = 0; i <= d - 1; i++) upd(dpscc[nid][(i + 1 - off[v] + cycle[nid]) % cycle[nid]], dp[now][i]); } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; unordered_set<string> was; int n, i, j, pos, k = 13, t; string codes[1001]; int main() { ios_base::sync_with_stdio(false); cin >> n; for (; i < n; ++i) cin >> codes[i]; for (i = 0; i < n; ++i) for (j = i + 1; j < n; ++j) { t = 0; for (pos = 0; pos < 6; ++pos) t += codes[i][pos] != codes[j][pos]; k = min(k, t); } cout << (k - 1) / 2; return 0; } |
#include <bits/stdc++.h> using namespace std; char s[100000]; int main() { int m, n, j, k, l, t, ll; bool is = false; cin >> t; cin >> s; if (t < 5) { cout << no << endl; return 0; } l = t / 5; ll = t % 5; for (j = 0; j < t && !is; j++) for (k = 1; k < t && !is; k++) if (j + 4 * k < t && s[j] == * && s[j + 2 * k] == * && s[j + k] == * && s[j + 3 * k] == * && s[j + 4 * k] == * ) { is = true; } if (is) cout << yes << endl; else cout << no << endl; return 0; } |
#include <bits/stdc++.h> const int dx[] = {1, 0, -1, 0}; const int dy[] = {0, 1, 0, -1}; using namespace std; const int MAXN = 55; int n; int a[2][MAXN]; int asum[2][MAXN]; int b[MAXN]; int main() { cin.tie(0); ios::sync_with_stdio(false); cin >> n; for (int j = 0; j < 2; j++) for (int i = 0; i < n - 1; i++) cin >> a[j][i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 1; i < n; i++) asum[0][i] = asum[0][i - 1] + a[0][i - 1]; for (int i = n - 2; i >= 0; i--) asum[1][i] = asum[1][i + 1] + a[1][i]; vector<int> length; for (int i = 0; i < n; i++) length.push_back(asum[0][i] + asum[1][i] + b[i]); sort(length.begin(), length.end()); cout << length[0] + length[1] << endl; return 0; } |
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module padder1(in, byte_num, out);
input [63:0] in;
input [2:0] byte_num;
output reg [63:0] out;
always @ (*)
case (byte_num)
0: out = 64'h0100000000000000;
1: out = {in[63:56], 56'h01000000000000};
2: out = {in[63:48], 48'h010000000000};
3: out = {in[63:40], 40'h0100000000};
4: out = {in[63:32], 32'h01000000};
5: out = {in[63:24], 24'h010000};
6: out = {in[63:16], 16'h0100};
7: out = {in[63:8], 8'h01};
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int gi() { int x = 0, w = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) w = 0, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return w ? x : -x; } const int N = 3e5 + 5; int q, fa[N + N], top; pair<int, int> sz[N + N], sta[N]; map<pair<int, int>, int> M; vector<pair<int, int> > vec[N << 2]; long long ans; pair<int, int> operator+(pair<int, int> a, pair<int, int> b) { return make_pair(a.first + b.first, a.second + b.second); } pair<int, int> operator-(pair<int, int> a, pair<int, int> b) { return make_pair(a.first - b.first, a.second - b.second); } int find(int x) { return x == fa[x] ? x : find(fa[x]); } void modify(int x, int l, int r, int ql, int qr, pair<int, int> p) { if (l >= ql && r <= qr) { vec[x].push_back(p); return; } int mid = l + r >> 1; if (ql <= mid) modify(x << 1, l, mid, ql, qr, p); if (qr > mid) modify(x << 1 | 1, mid + 1, r, ql, qr, p); } void dfs(int x, int l, int r) { int tt = top; for (pair<int, int> p : vec[x]) if (find(p.first) != find(p.second)) { int u = find(p.first), v = find(p.second); if (sz[u].first + sz[u].second < sz[v].first + sz[v].second) swap(u, v); sta[++top] = make_pair(u, v); ans -= 1ll * sz[u].first * sz[u].second; ans -= 1ll * sz[v].first * sz[v].second; fa[v] = u; sz[u] = sz[u] + sz[v]; ans += 1ll * sz[u].first * sz[u].second; } if (l == r) printf( %lld , ans); else { int mid = l + r >> 1; dfs(x << 1, l, mid); dfs(x << 1 | 1, mid + 1, r); } while (top > tt) { int u = sta[top].first, v = sta[top].second; --top; ans -= 1ll * sz[u].first * sz[u].second; fa[v] = v; sz[u] = sz[u] - sz[v]; ans += 1ll * sz[u].first * sz[u].second; ans += 1ll * sz[v].first * sz[v].second; } } int main() { q = gi(); for (int i = 1; i <= q; ++i) { int x = gi(), y = gi() + N; if (M.find(make_pair(x, y)) == M.end()) M[make_pair(x, y)] = i; else modify(1, 1, q, M[make_pair(x, y)], i - 1, make_pair(x, y)), M.erase(make_pair(x, y)); } for (auto it = M.begin(); it != M.end(); ++it) modify(1, 1, q, (*it).second, q, (*it).first); for (int i = 1; i < N + N; ++i) fa[i] = i, sz[i] = make_pair(i < N, i >= N); dfs(1, 1, q); return 0; } |
//----------------------------------------------------------------------------
//-- Limitaciones en la sintesis de puertas triestado
//-- Error 2: Conexion de dos registro de 1 bit a un cable de 2 bits
//-- a traves de dos puertas triestado. Controlados con la misma
//-- señal de enable
//----------------------------------------------------------------------------
//-- (C) BQ. November 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
/*
El error obtenido al sintetizar es:
arachne-pnr -d 1k -p error2.pcf error2.blif -o error2.txt
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
supported packages: tq144, vq100
read_blif error2.blif...
prune...
read_pcf error2.pcf...
instantiate_io...
fatal error: $_TBUF_ gate must drive top-level output or inout port
Makefile:208: recipe for target 'error2.bin' failed
make: *** [error2.bin] Error 1
*/
`default_nettype none
module error2 (
input wire clk, //-- Entrada de reloj
output wire [1:0] leds); //-- Leds a controlar
//-- Senal de habilitacion para las puertas
wire ena = 1'b1;
//-- Registro de 1 bit
reg reg0;
always @(posedge clk)
reg0 <= 1'b1;
//-- Registro de 1 bit
reg reg1;
always @(posedge clk)
reg1 <= 1'b1;
//-- Conectar los registros al cable de 2 bits
//-- Se controlan con la misma señal de habilitacion
assign leds[0] = (ena) ? reg0 : 1'bz;
assign leds[1] = (ena) ? reg1 : 1'bz;
endmodule
|
#include <bits/stdc++.h> using namespace std; class mat { public: long long a, b, c, d; }; mat a; long long n, k, l, m, step, res; long long power(long long a, long long b); mat mult(mat a, mat b); mat power1(mat a, long long n); int main() { cin >> n >> k >> l >> m; step = power(2, n); a.a = a.b = a.c = 1; a.d = 0; a = power1(a, n + 1); res = 1; while (l > 0) { if (k % 2) res = (res * ((step + m - a.a) % m)) % m; else res = (res * a.a) % m; k /= 2; l--; } if (k > 0) cout << 0; else cout << res % m; return 0; } long long power(long long a, long long b) { long long res; if (b == 0) return 1; res = power(a, b / 2) % m; res = (res * res) % m; if (b % 2) res = (res * a) % m; return res; } mat mult(mat a, mat b) { mat res; res.a = (a.a * b.a + a.b * b.c) % m; res.b = (a.a * b.b + a.b * b.d) % m; res.c = (a.c * b.a + a.d * b.c) % m; res.d = (a.c * b.b + a.d * b.d) % m; return res; } mat power1(mat a, long long n) { mat res, a1; if (n == 0) { res.a = res.d = 1; res.b = res.c = 0; return res; } res = power1(a, n / 2); res = mult(res, res); if (n % 2) { a1.a = a1.b = a1.c = 1; a1.d = 0; res = mult(res, a1); } return res; } |
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module simpledpram (clock,
wraddress, wrdata, wren,
rdaddress, rddata);
parameter DATA_WIDTH = 36;
parameter ADDR_WIDTH = 7;
parameter INIT_FILE = "somefile"; // No .mif!
input clock;
input [ADDR_WIDTH-1:0] wraddress;
input [DATA_WIDTH-1:0] wrdata;
input wren;
input [ADDR_WIDTH-1:0] rdaddress;
output [DATA_WIDTH-1:0] rddata;
wire [DATA_WIDTH-1:0] sub_wire0;
wire [DATA_WIDTH-1:0] rddata = sub_wire0[DATA_WIDTH-1:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (wrdata),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.init_file = {INIT_FILE,".mif"},
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1 << ADDR_WIDTH,
altsyncram_component.numwords_b = 1 << ADDR_WIDTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
endmodule
|
`timescale 1ns / 1ps
module Coprocessor(
clk,
rst,
c0_rd_addr,
c0_wr_addr,
c0_w_data,
pc_i,
InTcause,
c0_reg_we,
WriteEPC,
WriteCause,
c0_r_data,
epc_o,
WriteInt,
Int_en_i,
Int_en_o
);
// ================ IO interface
input clk, rst;
input wire [31: 0] c0_w_data, pc_i;
input wire [ 4: 0] c0_rd_addr, c0_wr_addr;
input wire [ 4: 0] InTcause;
input wire c0_reg_we, WriteEPC, WriteCause,
WriteInt, Int_en_i;
output wire [31: 0] c0_r_data, epc_o, Int_en_o;
integer i = 0;
reg [31: 0] c0reg[11:14];
// 11 Enable, 12 Base, 13 Cause, 14 Epc
assign c0_r_data = c0reg[c0_rd_addr];
assign epc_o = c0reg[14];
assign Int_en_o = c0reg[11];
initial begin
for(i = 11; i <= 14; i = i + 1)
c0reg[i] <= 32'b0;
end
always @(posedge clk ) begin
if (rst) begin
// reset
for(i = 11; i <= 14; i = i + 1)
c0reg[i] <= 32'b0;
end
else begin
if (c0_reg_we == 1)
c0reg[c0_wr_addr] <= c0_w_data;
if (WriteInt == 1)
c0reg[11][0] <= Int_en_i;
if (WriteCause == 1)
c0reg[13] <= InTcause;
if (WriteEPC == 1)
c0reg[14] <= pc_i;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long bin_pow(long long a, long long b) { if (b == 0) return 1; if (b % 2 == 0) { long long t = bin_pow(a, b / 2); return t * t % 1000000007; } else return a * bin_pow(a, b - 1) % 1000000007; } vector<long long> graph[500000]; bool used[500000]; long long w[500000], comp; map<pair<long long, long long>, long long> mp1; void dfs(long long v) { used[v] = 1; comp++; for (auto u : graph[v]) { if (w[u] == 0 || used[u] || mp1[{u, v}] == 0) continue; dfs(u); } } int main() { ios::sync_with_stdio(false); cin.tie(0); long long t = 1, n, m, k = 0, sum = 0, l = 0, r = 0, x = 0, y = 0, z = 0, ans = 0, mn = LLONG_MAX, mx = LLONG_MIN; cin >> n >> m >> k; vector<long long> a(n), b; map<long long, vector<pair<long long, long long>>> mp; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) { cin >> x >> y; x--, y--; z = a[x] ^ a[y]; b.push_back(z); mp[z].push_back({x, y}); graph[x].push_back(y); graph[y].push_back(x); } sort(b.begin(), b.end()); b.erase(unique(b.begin(), b.end()), b.end()); for (int i = 0; i < b.size(); i++) { z = b[i]; long long k1 = 0; l = 0; for (auto u : mp[z]) { x = u.first, y = u.second; w[x] = w[y] = 1; mp1[{x, y}] = mp1[{y, x}] = 1; } for (auto u : mp[z]) { x = u.first, y = u.second; if (used[x]) continue; comp = 0; dfs(x); l += comp; k1++; } x = bin_pow(2, n - l) * bin_pow(2, k1) % 1000000007; ans += x; ans %= 1000000007; for (auto u : mp[z]) { x = u.first, y = u.second; w[x] = w[y] = used[x] = used[y] = 0; mp1[{x, y}] = mp1[{y, x}] = 0; } } t = ((bin_pow(2, k) - (long long)b.size()) % 1000000007 + 1000000007) % 1000000007; t *= bin_pow(2, n); t %= 1000000007; ans += t; ans %= 1000000007; cout << ans; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline ) using namespace std; const int N = 7005; const int M = 200000; const long long mod = 1e9 + 7; const long long inf = 0x3f3f3f3f; namespace FastIO { template <typename tp> inline void read(tp& x) { x = 0; register char c = getchar(); register bool f = 0; for (; c < 0 || c > 9 ; f |= (c == - ), c = getchar()) ; for (; c >= 0 && c <= 9 ; x = (x << 3) + (x << 1) + c - 0 , c = getchar()) ; if (f) x = -x; } template <typename tp> inline void write(tp x) { if (x == 0) return (void)(putchar( 0 )); if (x < 0) putchar( - ), x = -x; long long pr[20]; register long long cnt = 0; for (; x; x /= 10) pr[++cnt] = x % 10; while (cnt) putchar(pr[cnt--] + 0 ); } template <typename tp> inline void writeln(tp x) { write(x); putchar( n ); } } // namespace FastIO using namespace FastIO; struct line { int l, r, val; line() {} line(int l, int r, int val) { this->l = l; this->r = r; this->val = val; } }; int n, m, lx[M], ly[M]; vector<line> xx[N]; int solve(int d, int x, int y) { set<int> ans; for (int i = d; i <= n; i++) { for (int j = 0; j < xx[i].size(); j++) { line& c = xx[i][j]; if (c.l <= y && c.r >= x) ans.insert(c.val); } x = (lx[x] == -1 ? ly[x] : lx[x]); y = ly[y]; } return ans.size(); } void init() { int cnt = 1, p = 3; memset(lx, -1, sizeof(lx)); memset(ly, -1, sizeof(ly)); lx[1] = 1; ly[1] = 2; for (int i = 2; i < M; i++) { if ((1 << cnt) == i) cnt++, lx[i] = p++; ly[i] = p++; } } int flag, d, x, y, val; int main() { init(); read(n), read(m); for (int i = 0; i < m; i++) { read(flag); if (flag == 1) read(d), read(x), read(y), read(val), xx[d].push_back(line(x, y, val)); else read(d), read(x), writeln(solve(d, x, x)); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T& x) { bool fu = 0; char c; for (c = getchar(); c <= 32; c = getchar()) ; if (c == - ) fu = 1, c = getchar(); for (x = 0; c > 32; c = getchar()) x = x * 10 + c - 0 ; if (fu) x = -x; }; template <class T> inline void read(T& x, T& y) { read(x); read(y); } template <class T> inline void read(T& x, T& y, T& z) { read(x); read(y); read(z); } inline char getc() { char c; for (c = getchar(); c <= 32; c = getchar()) ; return c; } int n, m, st, i, j, k, l, K, P, x, y; int D0[610], D1[610], n0[610], n1[610]; int e[610][610]; long long a[610][610]; bool vis[610]; long long f[610]; long long dfs(int i) { if (i == st) return 1; if (vis[i]) return f[i]; vis[i] = 1; long long ans = 0; for (int j = 1; j <= n; j++) if (e[j][i]) ans = (ans + dfs(j) * e[j][i]) % P; return f[i] = ans; } int main() { read(n, m, P); for (i = 1; i <= m; i++) read(x, y), e[x][y]++, D0[x]++, D1[y]++; for (i = 1; i <= n; i++) if (D0[i] == 0) n0[i] = ++n0[0]; for (i = 1; i <= n; i++) if (D1[i] == 0) n1[i] = ++n1[0]; K = n0[0]; for (i = 1; i <= n; i++) if (n1[i]) { memset(vis, 0, sizeof(vis)); memset(f, 0, sizeof(f)); st = i; for (j = 1; j <= n; j++) if (n0[j]) a[n1[i]][n0[j]] = dfs(j); } long long ans = 1; for (i = 1; i <= K; i++) { for (j = i; j <= K; j++) if (a[j][i]) { if (j != i) ans = -ans; for (k = i; k <= K; k++) swap(a[j][k], a[i][k]); break; } if (a[i][i] == 0) continue; for (j = i + 1; j <= K; j++) while (a[j][i]) { long long res = a[j][i] / a[i][i]; for (k = i; k <= K; k++) a[j][k] = (a[j][k] - a[i][k] * res) % P; if (a[j][i]) { ans = -ans; for (k = i; k <= K; k++) swap(a[j][k], a[i][k]); } } } for (i = 1; i <= K; i++) ans = ans * a[i][i] % P; if (ans < 0) ans += P; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, s, k; vector<int> a; void Input() { cin >> n >> s >> k; a.clear(); a.resize(k); for (auto &z : a) cin >> z; } void Solve() { for (int i = 0; i <= k; i++) { if (s - i >= 1 && find(a.begin(), a.end(), s - i) == a.end()) { cout << i << n ; return; } if (s + i <= n && find(a.begin(), a.end(), s + i) == a.end()) { cout << i << n ; return; } } assert(false); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); int T; cin >> T; while (T--) { Input(); Solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline bool CHMAX(T& a, T b) { if (a < b) { a = b; return true; } return false; } template <class T> inline bool CHMIN(T& a, T b) { if (a > b) { a = b; return true; } return false; } constexpr long long INF = 1e18; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long N; cin >> N; vector<long long> a(N); for (long long i = 0; i < (long long)(N); i++) cin >> a[i]; map<long long, long long> mp; for (long long i = 0; i < (long long)(N); i++) { mp[a[i]]++; } vector<long long> cnt(N + 1); long long now = 0; for (auto e : mp) cnt[e.second]++; for (long long i = (long long)cnt.size() - 1 - 1; i >= 0; i--) { cnt[i] += cnt[i + 1]; } long long ma = -INF; long long h, w; for (long long i = 1; i < (long long)cnt.size(); i++) { now += cnt[i]; for (long long j = i; j * j <= now; j++) { long long nj = now / j; if (CHMAX(ma, j * nj)) { h = j, w = nj; } } } vector<long long> c; map<long long, long long> mpp; for (long long i = 0; i < (long long)(N); i++) if (++mpp[a[i]] <= h) { c.push_back(a[i]); if (c.size() == h * w) break; } sort(c.begin(), c.end()); vector<pair<long long, long long>> d; long long ren = 1; for (long long i = 0; i < (long long)(c.size()); i++) { if (i + 1 == c.size() || c[i] != c[i + 1]) { d.push_back({ren, c[i]}); ren = 1; } else { ren++; } } sort(d.begin(), d.end()); reverse(d.begin(), d.end()); vector<long long> e; for (long long i = 0; i < (long long)(d.size()); i++) { for (long long j = 0; j < (long long)(d[i].first); j++) { e.push_back(d[i].second); } } vector<vector<long long>> ans(h, vector<long long>(w)); long long cntcnt = 0; for (long long j = 0; j < (long long)(w); j++) for (long long i = 0; i < (long long)(h); i++) ans[i][j] = e[cntcnt++]; cout << h * w << n ; cout << h << << w << n ; for (long long i = 0; i < (long long)(h); i++) { for (long long j = 0; j < (long long)(w); j++) { if (j) cout << ; cout << ans[i][(j - i + w) % w]; } cout << n ; } } |
`include "../led_ctl.v"
module test;
reg read_n;
reg write_n;
reg reset_n;
reg ce_n;
wire [7:0] data;
wire [7:0] leds;
reg [7:0] write_data;
assign data = (~(write_n)) ? write_data : 8'bz;
led_ctl led1(read_n, write_n, reset_n, ce_n, data, leds);
initial begin
$dumpfile("led_ctl-test.vcd");
$dumpvars(0,test);
// start disabled
ce_n = 1'b1;
read_n = 1'b1;
write_n = 1'b1;
reset_n = 1'b1;
write_data = 8'hAA;
// should see:
// data == high z
// reset
#1 reset_n = 1'b0;
#1 reset_n = 1'b1;
// should see:
// led1.leds == ~(0x00)
// write cycle
#1 write_data = 8'hBB;
#1 ce_n = 1'b0;
#1 write_n = 1'b0;
// should see:
// test.data == 0xBB
// led1.leds == ~(0xBB) -> 0x44
// back to disabled
#1 ce_n = 1'b1;
read_n = 1'b1;
write_n = 1'b1;
// should see:
// data == high z
// read cycle
#1 ce_n = 1'b0;
#1 read_n = 1'b0;
// should see:
// test.data == ~(0x44) -> 0xBB
// back to disabled
#1 ce_n = 1'b1;
read_n = 1'b1;
write_n = 1'b1;
// should see:
// data == high z
#1;
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 Yutetsu TAKATSUKASA.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic o; // From test of Test.v
// End of automatics
wire [31:0] i = crc[31:0];
Test test(/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.clk (clk),
.i (i[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'b0, o};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$display("o %b", o);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc < 99) begin
end
else begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hcae926ece668f35d
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(/*AUTOARG*/
// Outputs
o,
// Inputs
clk, i
);
input clk;
input [31:0] i;
logic [31:0] d;
logic d0, d1, d2, d3, d4, d5, d6, d7;
logic bug3182_out;
logic bug3197_out;
output logic o;
logic [6:0] tmp;
assign o = ^tmp;
always_ff @(posedge clk) begin
d <= i;
d0 <= i[0];
d1 <= i[1];
d2 <= i[2];
d3 <= i[3];
d4 <= i[4];
d5 <= i[5];
d6 <= i[6];
d7 <= i[7];
end
always_ff @(posedge clk) begin
// Cover more lines in V3Const.cpp
tmp[0] <= (d0 || (!d0 && d1)) ^ ((!d2 && d3) || d2); // maatchOrAndNot()
tmp[1] <= ((32'd2 ** i) & 32'h10) == 32'b0; // replacePowShift
tmp[2] <= ((d0 & d1) | (d0 & d2))^ ((d3 & d4) | (d5 & d4)); // replaceAndOr()
tmp[3] <= d0 <-> d1; // replaceLogEq()
tmp[4] <= i[0] & (i[1] & (i[2] & (i[3] | d[4]))); // ConstBitOpTreeVisitor::m_frozenNodes
tmp[5] <= bug3182_out;
tmp[6] <= bug3197_out;
end
bug3182 i_bug3182(.in(d[4:0]), .out(bug3182_out));
bug3197 i_bug3197(.clk(clk), .in(d), .out(bug3197_out));
endmodule
module bug3182(in, out);
input wire [4:0] in;
output wire out;
// This function always returns 0, so safe to take bitwise OR with any value.
// Calling this function stops constant folding as Verialtor does not know
// what this function returns.
import "DPI-C" context function int fake_dependency();
logic [4:0] bit_source;
/* verilator lint_off WIDTH */
always @(in)
bit_source = fake_dependency() | in;
wire [5:0] tmp = bit_source; // V3Gate should inline this
wire out = ~(tmp >> 5) & (bit_source == 5'd10);
/* verilator lint_on WIDTH */
endmodule
module bug3197(input wire clk, input wire [31:0] in, output out);
logic [63:0] d;
always_ff @(posedge clk)
d <= {d[31:0], in[0] ? in : 32'b0};
wire tmp0 = (|d[38:0]);
assign out = (d[39] | tmp0);
endmodule
|
// zhiyang ong
// andrew mattheisen
// The next line is only used for module synthesis
//`include "~/ee577b/syn/src/control.h"
module control(instr,
aluop, ww,
memEn, memWrEn, maddr, wbyteen,
regop, rrdaddra, rrdaddrb, rwraddrd,
reginmuxop,
aluinmuxop,
immediate);
// INPUTS
input [0:31] instr;
// OUTPUTS
output [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
output [0:2] regop;
output [0:1] ww;
output [0:20] maddr;
output memEn, memWrEn;
output reginmuxop, aluinmuxop;
output [0:15] wbyteen;
output [0:127] immediate;
// REGISTERS
reg [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
reg [0:2] ppp, regop;
reg [0:1] ww, memop;
reg [0:20] maddr;
reg memEn, memWrEn;
reg reginmuxop, aluinmuxop;
reg [0:15] wbyteen;
reg [0:127] immediate;
// PARAMETERS
parameter zero = 1'b0;
parameter one = 1'b1;
always @ (ppp or ww or instr) // determine wbyteen
begin
if (instr[5]== 1'b1)
begin
wbyteen=16'b1111111111111111;
end
else if (ppp == `aa)
wbyteen=16'b1111111111111111;
else if (ppp == `uu)
wbyteen=16'b1111111100000000;
else if (ppp == `dd)
wbyteen=16'b0000000011111111;
else if (ppp == `ee)
begin
if (ww==`w8)
wbyteen=16'b1010101010101010;
else if (ww==`w16)
wbyteen=16'b1100110011001100;
else if (ww==`w32)
wbyteen=16'b1111000011110000;
else // default
wbyteen=16'b0;
end
else if (ppp == `oo)
begin
if (ww==`w8)
wbyteen=16'b0101010101010101;
else if (ww==`w16)
wbyteen=16'b0011001100110011;
else if (ww==`w32)
wbyteen=16'b0000111100001111;
else // default
wbyteen=16'b0;
end
else if (ppp == `mm)
begin
if (ww==`w8)
wbyteen=16'b1000000000000000;
else if (ww==`w16)
wbyteen=16'b1100000000000000;
else if (ww==`w32)
wbyteen=16'b1111000000000000;
else // default
wbyteen=16'b0;
end
else if (ppp == `ll)
begin
if (ww==`w8)
wbyteen=16'b0000000000000001;
else if (ww==`w16)
wbyteen=16'b0000000000000011;
else if (ww==`w32)
wbyteen=16'b0000000000001111;
else // default
wbyteen=16'b0;
end
else // default
wbyteen=16'b0;
end //always @ (ppp or ww)
always @ (instr)
begin
immediate={instr[16:20], {123{zero}}};
ppp=instr[21:23];
ww=instr[24:25];
maddr=instr[11:31];
rwraddrd=instr[6:10];
if (instr[2] == 1'b1) // => instr is wmv
begin
aluop=instr[26:31]; // alu control
regop=`rd1wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=one; // mux control
reginmuxop=zero;
end // if (instr[2] == 1'b1)
else if (instr[3] == 1'b1) // must examine bits 0-5
begin
if ({instr[26:28], instr[31]} == 4'b0101) // immediate shift
begin
aluop=instr[26:31]; // alu control
regop=`rd1wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=one; // mux control
reginmuxop=zero;
end
else if (instr[26:31]==6'b001000) // instr is wnot
begin
aluop=instr[26:31]; // alu control
regop=`rd1wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=one; // mux control
reginmuxop=zero;
end
else // all other commands
begin
aluop=instr[26:31]; // alu control
regop=`rd2wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=zero; // mux control
reginmuxop=zero;
end
end // else if (instr[3] == 1'b1)
else if (instr[4]==1'b1) // => instr is wst
begin
aluop=`alunop; // alu control
regop=`rd2wr0; // reg control
rrdaddra=instr[6:10]; // note this is special
rrdaddrb=instr[6:10]; // note this is special
//memop=`memwst; // mem control
memEn=one;
memWrEn=one;
aluinmuxop=zero; // mux control
reginmuxop=zero;
end // else if (instr[4]==1'b1)
else if (instr[5]==1'b1) // => instr is wld
begin
aluop=`alunop; // alu control
regop=`rd0wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memwld; // mem control
memEn=one;
memWrEn=zero;
aluinmuxop=zero; // mux control
reginmuxop=one;
end // else if (instr[5]==1'b1)
else // => instr is NOP
begin
aluop=`alunop;
regop=`regnop;
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop;
memEn=zero;
memWrEn=zero;
reginmuxop=zero;
aluinmuxop=zero;
end // else
end // always @ (instr)
endmodule
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// The suffix _AA is meaningless.
module buffer_AA
#(
parameter WIDTH = 32,
parameter MEM_SIZE = 64,
parameter LOG_MEM_SIZE = 6
)
(
input wire clk,
input wire rst_n,
// Write new data.
input wire write_strobe,
input wire [WIDTH-1: 0] write_data,
// Delete the current read data.
input wire read_delete,
// The current read data.
output reg read_full,
output reg [WIDTH-1: 0] read_data,
// Buffer overflow.
output reg write_error,
output reg read_error
);
reg [MEM_SIZE-1:0] full;
reg [WIDTH-1: 0] RAM[MEM_SIZE-1:0];
reg [LOG_MEM_SIZE-1: 0] write_addr;
reg [LOG_MEM_SIZE-1: 0] read_addr;
wire [LOG_MEM_SIZE-1: 0] next_read_addr;
assign next_read_addr = read_addr + 1;
always @(posedge clk)
if (!rst_n)
begin
write_error <= 1'b0;
read_error <= 1'b0;
full <= {MEM_SIZE{1'b0}};
write_addr <= {LOG_MEM_SIZE{1'b0}};
read_addr <= {LOG_MEM_SIZE{1'b0}};
end
else
begin
if (write_strobe)
begin
if (!full[write_addr])
begin
RAM[write_addr] <= write_data;
full[write_addr] <= 1'b1;
write_addr <= write_addr + 1;
end
else
write_error <= 1'b1;
end
if (read_delete)
begin
if (full[read_addr])
begin
full[read_addr] <= 1'b0;
read_addr <= next_read_addr;
read_full <= full[next_read_addr];
read_data <= RAM[next_read_addr];
end
else
begin
read_error <= 1'b1;
read_full <= full[read_addr];
read_data <= RAM[read_addr];
end
end
else
begin
read_full <= full[read_addr];
read_data <= RAM[read_addr];
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:31:14 10/18/2012
// Design Name:
// Module Name: dummy_ula
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dummy_ula(
input wire clk,
input wire mode,
output reg [2:0] r,
output reg [2:0] g,
output reg [2:0] b,
output wire csync
);
reg [2:0] ri = 3'b000;
reg [2:0] gi = 3'b000;
reg [2:0] bi = 3'b000;
wire [8:0] hc;
wire [8:0] vc;
wire blank;
sync_generator_pal_ntsc sincronismos (
.clk(clk), // 7 MHz
.in_mode(mode), // 0: PAL, 1: NTSC
.csync_n(csync),
.hc(hc),
.vc(vc),
.blank(blank)
);
parameter BLACK = 9'b000000000,
BLUE = 9'b000000111,
RED = 9'b000111000,
MAGENTA = 9'b000111111,
GREEN = 9'b111000000,
CYAN = 9'b111000111,
YELLOW = 9'b111111000,
WHITE = 9'b111111111;
always @* begin
if (blank == 1'b1) begin
{g,r,b} = BLACK;
end
else begin
{g,r,b} = BLACK;
if (hc >= (44*0) && hc <= (44*1-1)) begin
{g,r,b} = WHITE;
end
if (hc >= (44*1) && hc <= (44*2-1)) begin
{g,r,b} = YELLOW;
end
if (hc >= (44*2) && hc <= (44*3-1)) begin
{g,r,b} = CYAN;
end
if (hc >= (44*3) && hc <= (44*4-1)) begin
{g,r,b} = GREEN;
end
if (hc >= (44*4) && hc <= (44*5-1)) begin
{g,r,b} = MAGENTA;
end
if (hc >= (44*5) && hc <= (44*6-1)) begin
{g,r,b} = RED;
end
if (hc >= (44*6) && hc <= (44*7-1)) begin
{g,r,b} = BLUE;
end
if (hc >= (44*7) && hc <= (44*8-1)) begin
{g,r,b} = BLACK;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000000 + 7; const long long int N = 10000000 + 6; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int q; cin >> q; for (int i = 0; i < q; ++i) { long long n; cin >> n; vector<int> vals; int pos2 = -1; while (n > 0) { vals.push_back(n % 3); if (vals.back() == 2) pos2 = int(vals.size()) - 1; n /= 3; } vals.push_back(0); if (pos2 != -1) { int pos0 = find(vals.begin() + pos2, vals.end(), 0) - vals.begin(); vals[pos0] = 1; for (int i = pos0 - 1; i >= 0; --i) { vals[i] = 0; } } long long ans = 0; long long pw = 1; for (int i = 0; i < int(vals.size()); ++i) { ans += pw * vals[i]; pw *= 3; } if (vals.back() == 1) ans = pw / 3; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; void print(vector<pair<int, int> > &v) { for (int i = 0; i < v.size(); i++) cout << v[i].second << ; cout << endl; } int main() { int n; cin >> n; vector<pair<int, int> > input; for (int i = 0; i < n; i++) { int x; cin >> x; input.push_back(make_pair(x, i + 1)); } sort(input.begin(), input.end()); vector<pair<int, int> > swaps; for (int i = 1; i < n && swaps.size() < 2; i++) { if (input[i - 1].first == input[i].first) { swaps.push_back(make_pair(i - 1, i)); } } if (swaps.size() < 2) { cout << NO ; return 0; } cout << YES << endl; print(input); swap(input[swaps[0].first], input[swaps[0].second]); print(input); swap(input[swaps[1].first], input[swaps[1].second]); print(input); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; if (m >= n && k >= n) { cout << Yes << endl; } else cout << No << endl; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 300005; int res, cnt, head[Maxn], choose[Maxn], target[Maxn], las[Maxn], ct, n[Maxn], k, val[Maxn], a[20][Maxn], b[Maxn], bel[Maxn], state_cnt; bool vis1[Maxn], vis2[Maxn], ans[Maxn], done[20], flag; map<long long, int> Ma; long long sum[Maxn], tot; int tmp_state, Solution[Maxn][20], Solution_cnt; struct edg { int nxt, to; } edge[2 * Maxn]; void add(int x, int y) { if (bel[x] == bel[y]) return; if (done[bel[x]] || done[bel[y]]) return; edge[++cnt] = (edg){head[x], y}; head[x] = cnt; } void dfs(int u) { vis1[u] = true; vis2[u] = true; for (int i = head[u]; i; i = edge[i].nxt) { int to = edge[i].to; if (vis2[to]) { res = to; tmp_state = 0; state_cnt++; tmp_state |= (1 << (bel[to] - 1)); tmp_state |= (1 << (bel[u] - 1)); vis2[u] = false; Solution[state_cnt][1] = to, Solution[state_cnt][2] = u; Solution_cnt = 2; return; } dfs(to); if (flag) return; if (tmp_state & (1 << (bel[u] - 1))) { if (res == u) val[state_cnt] = tmp_state, reverse(Solution[state_cnt] + 1, Solution[state_cnt] + Solution_cnt + 1), Solution[state_cnt][Solution_cnt + 1] = Solution[state_cnt][1], tmp_state = 0; else state_cnt--, tmp_state = 0; flag = true; return; } else if (tmp_state) { tmp_state |= (1 << (bel[u] - 1)); Solution[state_cnt][++Solution_cnt] = u; vis2[u] = false; return; } } vis2[u] = false; } void get_ans(int id) { choose[bel[Solution[id][1]]] = b[Solution[id][1]]; for (int i = 2; Solution[id][i]; i++) { choose[bel[Solution[id][i]]] = b[Solution[id][i]]; target[bel[Solution[id][i - 1]]] = bel[Solution[id][i]]; } } int main() { scanf( %d , &k); for (int i = 1; i <= k; i++) { scanf( %d , &n[i]); for (int j = 1; j <= n[i]; j++) scanf( %d , &a[i][j]), b[++ct] = a[i][j], sum[i] += a[i][j], tot += a[i][j]; } if (tot % k) { printf( NO ); return 0; } tot /= k; for (int i = 1; i <= k; i++) if (tot == sum[i]) done[i] = true; sort(b + 1, b + 1 + ct); for (int i = 1; i <= k; i++) for (int j = 1; j <= n[i]; j++) Ma[a[i][j]] = lower_bound(b + 1, b + 1 + ct, a[i][j]) - b, bel[Ma[a[i][j]]] = i; for (int i = 1; i <= k; i++) for (int j = 1; j <= n[i]; j++) if (Ma[tot - sum[i] + a[i][j]]) add(Ma[tot - sum[i] + a[i][j]], Ma[a[i][j]]); for (int i = 1; i <= ct; i++) if (!vis1[i]) flag = false, dfs(i); for (int i = 1; i <= k; i++) if (sum[i] == tot) val[++state_cnt] = 1 << (i - 1); int maxi = (1 << k) - 1; ans[0] = true; for (int i = 0; i <= maxi; i++) if (ans[i]) for (int j = 1; j <= state_cnt; j++) if (!(val[j] & i)) ans[val[j] | i] = true, las[val[j] | i] = j; if (ans[maxi]) { printf( YES n ); int state_now = maxi; while (state_now) { get_ans(las[state_now]); state_now ^= val[las[state_now]]; } for (int i = 1; i <= k; i++) if (target[i]) printf( %d %d n , choose[i], target[i]); else printf( %d %d n , a[i][1], i); return 0; } printf( NO ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_SYMBOL_V
`define SKY130_FD_SC_HS__A311OI_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_SYMBOL_V
|
`timescale 1ps / 1ps
module image_to_ppfifo #(
parameter BUFFER_SIZE = 9
)(
input clk,
input rst,
input axis_clk,
input w_axis_rst,
input i_enable,
input i_video_hsync,
input i_sof_stb,
input [2:0] i_red,
input [2:0] i_green,
input [1:0] i_blue,
//Memory FIFO Interface
output o_rfifo_ready,
input i_rfifo_activate,
input i_rfifo_strobe,
output [24:0] o_rfifo_data,
output [23:0] o_rfifo_size
);
//Local Parameters
//Registers/Wires
wire w_write_ready;
reg r_write_activate;
wire [23:0] w_write_fifo_size;
reg r_write_stb;
reg [24:0] r_write_data;
//Submodules
block_fifo #(
.DATA_WIDTH (25 ),
.ADDRESS_WIDTH (BUFFER_SIZE )
) bf (
.reset (rst | w_axis_rst ),
//write side
.write_clock (clk ),
.write_ready (w_write_ready ),
.write_activate (w_write_activate ),
.write_fifo_size (w_write_fifo_size ),
.write_strobe (r_write_stb ),
.write_data (r_write_data ),
//read size
.read_clock (axis_clk ),
.read_strobe (i_rfifo_strobe ),
.read_ready (o_rfifo_ready ),
.read_activate (i_rfifo_activate ),
.read_count (o_rfifo_size ),
.read_data (o_rfifo_data )
);
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
r_write_stb <= 0;
if (rst) begin
r_write_activate <= 0;
r_write_stb <= 0;
r_write_data <= 0;
end
else begin
if (i_enable && !r_write_activate && w_write_ready) begin
r_write_activate <= 1;
end
if (r_write_activate) begin
if (i_video_hsync) begin
r_write_data <= {i_sof_stb, i_red, i_green, i_blue};
r_write_stb <= 1;
end
else begin
r_write_activate <= 0;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O32A_BEHAVIORAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_BEHAVIORAL_V |
/*
* Milkymist VJ SoC
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_sdrio(
input sys_clk,
input direction,
input direction_r,
input [ 1:0] mo,
input [15:0] dout,
output reg [15:0] di,
output [ 1:0] sdram_dqm,
inout [15:0] sdram_dq
);
wire [15:0] sdram_data_out;
assign sdram_dq = direction ? sdram_data_out : 16'hzzzz;
/*
* In this case, without DDR primitives and delays, this block
* is extremely simple
*/
assign sdram_dqm = mo;
assign sdram_data_out = dout;
// Behaviour
always @(posedge sys_clk) di <= sdram_dq;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 5; const int MOD = 1e9 + 7; int dr[4] = {0, 0, 1, -1}; int dc[4] = {1, -1, 0, 0}; int ddr[8] = {0, 0, 1, -1, 1, -1, 1, -1}; int ddc[8] = {1, -1, 0, 0, 1, -1, -1, 1}; bool isPrime(int n) { if (n <= 1) return false; for (int i = 2; i < n; i++) if (n % i == 0) return false; return true; } long long int power(long long int a, long long int b) { long long int ans = 1; while (b) { if (b & 1) ans = (ans * a) % MOD; a = (a * a) % MOD; b /= 2; } return ans; } long long int nCr(long long int n, long long int r) { long long int ans = 1, i; if (r > n - r) r = n - r; for (i = 0; i < r; i++) { ans = (ans * (n - i)) % MOD; ans = (ans * power(i + 1, MOD - 2)) % MOD; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; cin >> t; int tt = 0; while (t--) { int n, k; cin >> n >> k; string s; cin >> s; int a = k / 3; a++; string r; for (int i = 0; i < a; i++) { r = r + RGB ; } r = r + RGB ; int mn = 1e5; for (int i = 0; i < n - k + 1; i++) { int mm = 1e5; string p = s.substr(i, k); int c = 0, d = 0, e = 0; for (int j = 0; j < k; j++) { if (p[j] != r[j]) c++; if (p[j] != r[j + 1]) d++; if (p[j] != r[j + 2]) e++; } mm = min(c, min(d, e)); mn = min(mn, mm); } cout << mn << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLRBP_FUNCTIONAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ms__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n, k; const int maxn = 1e5 + 10; stack<int> max_seen; int ans[maxn]; vector<int> to[maxn]; void calc(int a) { int s = max(a - k, 0), t = min(n, a + k + 1); if (max_seen.empty()) ans[a] += t - s; else ans[a] += t - max(max_seen.top(), s); max_seen.push(t); for (int i = 0; i < to[a].size(); i++) { ans[to[a][i]] = ans[a]; calc(to[a][i]); } max_seen.pop(); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) { int x; cin >> x; if (x > 0) to[x - 1].push_back(i); } for (int i = 0; i < n; i++) if (ans[i] == 0) calc(i); for (int i = 0; i < n; i++) cout << ans[i] << ; } |
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_cc.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 20 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser out characterization and control. Logic to interface with
//Chipscope and control. Intended to support real time observation. Largely
//not generated for production implementations.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_cc #
(parameter TCQ = 100,
parameter CCENABLE = 0,
parameter PCT_SAMPS_SOLID = 95,
parameter SAMPCNTRWIDTH = 8,
parameter SAMPLES = 128,
parameter TAPCNTRWIDTH = 7)
(/*AUTOARG*/
// Outputs
samples, samps_solid_thresh, poc_error,
// Inputs
tap, samps_hi_held, psen, clk, rst, ktap_at_right_edge,
ktap_at_left_edge, mmcm_lbclk_edge_aligned, mmcm_edge_detect_done,
fall_lead_right, fall_trail_right, rise_lead_right,
rise_trail_right, fall_lead_left, fall_trail_left, rise_lead_left,
rise_trail_left, fall_lead_center, fall_trail_center,
rise_lead_center, rise_trail_center
);
// Remember SAMPLES is whole number counting. Zero corresponds to one sample.
localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01;
output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;
input [TAPCNTRWIDTH-1:0] tap;
input [SAMPCNTRWIDTH:0] samps_hi_held;
input psen;
input clk, rst;
input ktap_at_right_edge, ktap_at_left_edge;
input mmcm_lbclk_edge_aligned;
wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned;
input mmcm_edge_detect_done;
reg mmcm_edge_detect_done_r;
always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done;
wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r;
reg [6:0] aligned_cnt_r;
wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done};
always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns;
reg poc_error_r;
wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r);
always @(posedge clk) poc_error_r <= #TCQ poc_error_ns;
output poc_error;
assign poc_error = poc_error_r;
input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right;
input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left;
input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center;
generate if (CCENABLE == 0) begin : no_characterization
assign samples = SAMPLES[SAMPCNTRWIDTH:0];
assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0];
end else begin : characterization
end endgenerate
endmodule // mig_7series_v2_3_poc_cc
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long x, y; int main() { ios_base::sync_with_stdio(0); ; cin >> x >> y; if ((long long)sqrt(x * x + y * y + 0.5) == sqrt(x * x + y * y)) { cout << black << n ; return 0; } long long d = sqrt(x * x + y * y); if ((x > 0 && y > 0) || (x < 0 && y < 0)) { if (d % 2 == 0) cout << black << n ; else cout << white << n ; } else { if (d % 2 == 0) cout << white << n ; else cout << black << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int N, R, C, g[110][110]; vector<int> A, B; int main() { scanf( %d %d %d , &N, &R, &C); for (int i = 1; i <= (N); i++) { if (i & 1) A.push_back(i); else B.push_back(i); } for (int r = 1; r <= (R); r++) for (int c = 1; c <= (C); c++) { if ((r + c) % 2 == 0 && A.size()) g[r][c] = A.back(), A.pop_back(); if ((r + c) % 2 == 1 && B.size()) g[r][c] = B.back(), B.pop_back(); } if (A.size() || B.size()) puts( -1 ); else { for (int r = 1; r <= (R); r++) { for (int c = 1; c <= (C); c++) printf( %d , g[r][c]); puts( ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int sigma_size = 26; const int N = 100 + 50; const int MAXN = 100000 + 50; const int inf = 0x3fffffff; const double eps = 1e-8; const int mod = 1000000000 + 7; int n, k; int a[N]; double dp[N][N], res[N][N]; int main() { while (~scanf( %d%d , &n, &k)) { for (int i = 1; i <= n; i++) scanf( %d , &a[i]); memset(dp, 0, sizeof(dp)); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) dp[i][j] = 1; while (k--) { memcpy(res, dp, sizeof(dp)); memset(dp, 0, sizeof(dp)); for (int l = 1; l <= n; l++) for (int r = l; r <= n; r++) { for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { int x = i, y = j; if (l <= x && x <= r) x = l + r - x; if (l <= y && y <= r) y = l + r - y; if (x > y) swap(x, y); if (l <= x && y <= r) dp[x][y] += (1 - res[i][j]) * 2.0 / (n + 1) / n; else dp[x][y] += res[i][j] * 2.0 / (n + 1) / n; } } } double ans = 0; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (a[i] > a[j]) ans += dp[i][j]; else ans += 1.0 - dp[i][j]; printf( %.10f n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const int mod = 998244353; const int maxn = 2005; string s; long long ans = 0; int n; vector<pair<int, int> > edges[maxn]; int col[maxn], vis[maxn]; int isbi = 1; void flood(int x, int curcol) { if (vis[x]) { if (col[x] != curcol) { isbi = 0; } return; } vis[x] = 1; col[x] = curcol; for (int i = 0; i < edges[x].size(); i++) { int u = edges[x][i].first, v = edges[x][i].second; flood(u, curcol ^ v); } } int pw(int x, int y) { if (!y) return 1; if (y == 1) return x; int mid = pw(x, y >> 1); if (y & 1) return 1ll * mid * mid % mod * x % mod; return 1ll * mid * mid % mod; } int sear() { isbi = 1; int con = 0; for (int i = 0; i <= 2 * n + 1; i++) { if (!vis[i]) { flood(i, 0); ++con; } } if (!isbi) return 0; return pw(2, con - 1); } int solve(int m) { memset(vis, 0, sizeof vis); memset(col, -1, sizeof col); for (int i = 0; i <= maxn - 1; i++) edges[i].clear(); for (int i = 0; i < n; i++) { edges[i].push_back(make_pair(n - 1 - i, 0)); } for (int i = 0; i < m; i++) { edges[i + n].push_back(make_pair(n + (m - 1 - i), 0)); } for (int i = m; i < n; i++) { edges[i + n].push_back(make_pair(2 * n, 0)); edges[2 * n].push_back(make_pair(i + n, 0)); } for (int i = 0; i < n; i++) { if (s[n - 1 - i] == 0 ) { edges[i].push_back(make_pair(i + n, 0)); edges[i + n].push_back(make_pair(i, 0)); } else if (s[n - 1 - i] == 1 ) { edges[i].push_back(make_pair(i + n, 1)); edges[i + n].push_back(make_pair(i, 1)); } } edges[2 * n].push_back(make_pair(2 * n + 1, 1)); edges[2 * n + 1].push_back(make_pair(2 * n, 1)); edges[n].push_back(make_pair(2 * n + 1, 0)); edges[2 * n + 1].push_back(make_pair(n, 0)); edges[0].push_back(make_pair(2 * n + 1, 0)); edges[2 * n + 1].push_back(make_pair(0, 0)); return sear(); } int main() { ios::sync_with_stdio(false); cin >> s; n = s.size(); for (int i = 1; i < n; i++) { ans = (ans + solve(i)) % mod; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e15; const int maxn = 5000 + 5; long long cnt[maxn + 10]; long long p[maxn + 10][maxn + 10]; long long pd[maxn + 10]; int main() { memset(cnt, 0, sizeof(cnt)); int n; scanf( %d , &n); for (int i = (1); i <= (n); i++) { int u; scanf( %d , &u); cnt[u]++; } for (int i = (2); i <= (maxn); i++) { for (int j = (1); j <= (i); j++) p[i][j] += p[i - 1][j]; int mm = sqrt(i), tem = i; for (int j = (2); j <= (mm); j++) { while (tem % j == 0) { p[i][j]++; tem /= j; } } if (tem > 1) p[i][tem]++; } long long ans = 0, cur = 0; for (int i = (1); i <= (maxn); i++) { if (!cnt[i]) { pd[i] = 1; continue; } for (int j = (1); j <= (i); j++) { ans += p[i][j] * cnt[i]; cur += p[i][j] * cnt[i]; if (p[i][j]) pd[i] = j; } } while (*max_element(pd, pd + maxn + 10) > 1) { long long f[maxn + 10]; memset(f, 0, sizeof(f)); for (int i = (1); i <= (maxn); i++) f[pd[i]] += cnt[i]; long long besp = max_element(f, f + maxn + 10) - f; long long besg = f[besp]; if (besg * 2 <= n || besp == 1) break; cur += n - 2 * besg; ans = min(ans, cur); for (int i = (1); i <= (maxn); i++) { if (pd[i] != besp) pd[i] = 1; if (pd[i] == 1) continue; p[i][besp] -= 1; while (pd[i] > 1 && p[i][pd[i]] == 0) pd[i]--; } } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5010; int n, m, s; vector<int> e[N]; int low[N], dfn[N], idx; bool vis[N]; stack<int> st; bool in_stack[N]; int color[N], color_tot; int indeg[N]; int ans; void AddEdge(int u, int v) { e[u].push_back(v); } void Dfs(int u) { low[u] = dfn[u] = ++idx; in_stack[u] = true; st.push(u); for (int v : e[u]) { if (!dfn[v]) { Dfs(v); low[u] = min(low[u], low[v]); } else if (in_stack[v]) { low[u] = min(low[u], dfn[v]); } } if (low[u] == dfn[u]) { ++color_tot; int v; do { v = st.top(); st.pop(); in_stack[v] = false; color[v] = color_tot; } while (v != u); } } void Tarjan() { for (int i = 1; i <= n; ++i) if (!color[i]) Dfs(i); } int main() { scanf( %d%d%d , &n, &m, &s); for (int i = 1; i <= m; ++i) { int u, v; scanf( %d%d , &u, &v); AddEdge(u, v); } Tarjan(); for (int i = 1; i <= n; ++i) ; for (int i = 1; i <= n; ++i) for (int j : e[i]) if (color[i] != color[j]) ++indeg[color[j]]; for (int i = 1; i <= color_tot; ++i) ; for (int i = 1; i <= color_tot; ++i) if (indeg[i] == 0) ++ans; if (indeg[color[s]] == 0) --ans; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int *a; int *b; int n; long long int what(long long x) { long long int s = 0; for (int i = 0; i < n; i++) { s += (x * a[i]) / b[i]; } return s; } int main() { int i, j; int c; cin >> n >> c; a = new int[n]; b = new int[n]; for (i = 0; i < n; i++) { cin >> a[i] >> b[i]; } c = c - n; long long int l = 0; long long int r = ((c + 1) * b[0]) / a[0] + 3; long long int x; x = r; while (r - l > 1) { if (what(x) < c) l = x; else r = x; x = (l + r) / 2; } long long int rl = r; l = 0; r = ((c + 1) * b[0]) / a[0] + 3; x = r; while (r - l > 1) { if (what(x) <= c) l = x; else r = x; x = (l + r) / 2; } cout << (r - rl); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__TAPVGND2_PP_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd2 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
// BCHEncoderX for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH encoder (page encoder) array
// Module Name: BCHEncoderX
// File Name: BCHEncoderX.v
//
// Version: v1.0.0
//
// Description: BCH encoder (page encoder) array
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module BCHEncoderX
#
(
parameter Multi = 2
)
(
iClock ,
iReset ,
iEnable ,
iData ,
iDataValid ,
oDataReady ,
oDataLast ,
oParityData ,
oParityValid ,
oParityLast ,
iParityReady
);
input iClock ;
input iReset ;
input iEnable ;
input [8*Multi - 1:0] iData ;
input iDataValid ;
output oDataReady ;
output oDataLast ;
output [8*Multi - 1:0] oParityData ;
output oParityValid ;
output oParityLast ;
input iParityReady ;
wire [Multi - 1:0] wDataReady ;
wire [Multi - 1:0] wDataLast ;
wire [Multi - 1:0] wParityStrobe ;
wire [Multi - 1:0] wParityLast ;
genvar c;
generate
for (c = 0; c < Multi; c = c + 1)
begin
d_BCH_encoder_top
BCHPEncoder
(
.i_clk (iClock ),
.i_nRESET (!iReset ),
.i_exe_encoding (iEnable ),
.i_message_valid (iDataValid ),
.i_message (iData[(c + 1) * 8 - 1:c * 8] ),
.o_message_ready (wDataReady[c] ),
.i_parity_ready (iParityReady ),
.o_encoding_start ( ),
.o_last_m_block_rcvd (wDataLast[c] ),
.o_encoding_cmplt ( ),
.o_parity_valid (wParityStrobe[c] ),
.o_parity_out_start ( ),
.o_parity_out_cmplt (wParityLast[c] ),
.o_parity_out (oParityData[(c + 1) * 8 - 1:c * 8] )
);
end
endgenerate
assign oDataLast = wDataLast[0] ;
assign oParityValid = wParityStrobe[0] ;
assign oParityLast = wParityLast[0] ;
assign oDataReady = wDataReady[0] ;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int nextint() { int res = 0; char c = 0; while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) { res = res * 10 + c - 0 ; c = getchar(); } return res; } int n; long long a[200000], b[200000]; bool good[200000]; bool ans[200000]; long long diff[200000]; const int maxh = 17; const int maxn = (1 << maxh); long long tree[2 * maxn]; void build() { for (int i = maxn - 1; i; i--) tree[i] = min(tree[i + i], tree[i + i + 1]); } long long get(int i, int j) { long long result = (long long)1e18; for (i += maxn - 1, j += maxn; i + 1 != j; i >>= 1, j >>= 1) { if (!(i & 1)) result = min(result, tree[i + 1]); if (j & 1) result = min(result, tree[j - 1]); } return result; } long long get_min(int i, int j) { long long result = (long long)1e18; if (i <= j) result = get(i + 1, j + 2); return result; } void go() { memset(tree, 0, sizeof(tree)); for (int i = 0; i < (int)(n); ++i) tree[maxn + i + 1] = tree[maxn + i] + diff[i]; build(); for (int i = 0; i < (int)(n); ++i) { long long presum = tree[maxn + i]; long long postsum = tree[maxn + n] - presum; long long m_main = get_min(i, n - 1); long long m_oth = get_min(0, i - 1); bool ok = true; if (-presum + m_main < 0) ok = false; if (postsum + m_oth < 0) ok = false; good[i] = ok; } } int main() { cin >> n; for (int i = 0; i < (int)(n); ++i) { int _a; scanf( %d , &_a); a[i] = _a; } for (int i = 0; i < (int)(n); ++i) { int _b; scanf( %d , &_b); b[i] = _b; } for (int i = 0; i < (int)(n); ++i) diff[i] = a[i] - b[i]; go(); for (int i = 0; i < (int)(n); ++i) if (good[i]) ans[i] = true; memset(good, 0, sizeof(good)); reverse(a + 1, a + n); reverse(b, b + n); for (int i = 0; i < (int)(n); ++i) diff[i] = a[i] - b[i]; go(); for (int i = 0; i < (int)(n); ++i) if (good[i]) ans[(n - i) % n] = true; int ans_size = 0; for (int i = 0; i < (int)(n); ++i) if (ans[i]) ans_size++; cout << ans_size << endl; for (int i = 0; i < (int)(n); ++i) if (ans[i]) cout << (i + 1) << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, ans, now; int v[505][505]; int main() { scanf( %d%d , &n, &k); now = n * n; for (int i = n; i >= 1; i--) for (int h = n; h >= k; h--) v[i][h] = now--; now = 1; for (int i = 1; i <= n; i++) for (int h = 1; h < k; h++) v[i][h] = now++; for (int i = 1; i <= n; i++) ans += v[i][k]; printf( %d n , ans); for (int i = 1; i <= n; i++) { for (int h = 1; h <= n; h++) cout << v[i][h] << ; cout << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { double s = 0, n; cin >> n; while (n > 0) { s += (1 / n); n--; } cout << s << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, m; int a[maxn], b[maxn]; int main() { cin >> n >> m; m--; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } if (a[0] == 0) { cout << NO ; return 0; } if (b[m] == 0 && a[m] == 0) { cout << NO ; return 0; } if (a[m] != 0) { cout << YES ; return 0; } for (int i = m; i < n; i++) { if (b[i] == 1 && a[i] == 1) { cout << YES ; return 0; } } cout << NO ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:43:12 03/11/2015
// Design Name: delay
// Module Name: /home/vka/Programming/VHDL/workspace/test/tb_delay.v
// Project Name: test
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: delay
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_delay;
// Inputs
reg [7:0] in;
reg ce;
reg clk;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
delay #
(
.DELAY(1)
)
uut (
.d(in),
.ce(ce),
.clk(clk),
.q(out)
);
initial begin
// Initialize Inputs
in = 8'b00000001;
//out = 0;
ce = 1;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always
begin
#10
clk = !clk;
#10
clk = !clk;
in = in + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[11][11] = {0}, n; cin >> n; for (int i = 0; i < n; i++) { a[0][i] = 1; a[i][0] = 1; } for (int i = 1; i < n; i++) { for (int j = 1; j < n; j++) { a[i][j] = a[i - 1][j] + a[i][j - 1]; } } cout << a[n - 1][n - 1] << n ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.11.2016 16:55:54
// Design Name:
// Module Name: frequency_analyzer_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module frequency_analyzer_synch_testbench;
reg clock;
reg reset;
reg enable;
wire start_analyzer_0;
wire stop_analyzer_0;
wire start_analyzer_1;
wire stop_analyzer_1;
frequency_analyzer_synch #(.FREQUENCY(2000), .CLOCK(100000000)) f(
.clock(clock),
.enable(enable),
.reset(reset),
.start_analyzer_0(start_analyzer_0),
.stop_analyzer_0(stop_analyzer_0),
.start_analyzer_1(start_analyzer_1),
.stop_analyzer_1(stop_analyzer_1));
initial begin
clock <= 1'b0;
reset <= 1'b0;
enable <= 1'b0;
reset <= #10 1'b1;
enable <= #10 1'b1;
end
always #5 clock <= ~clock;
endmodule |
#include <bits/stdc++.h> using namespace std; vector<long long> adj[200005]; vector<long long> vis(200005); signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, j, k = 0, n, t = 1, m, l = 0; for (i = 0; i < 200005; i++) vis[i] = 0; while (t--) { cin >> n; for (i = 0; i < n; i++) { cin >> l >> m; adj[m].push_back(l); adj[l].push_back(m); } long long d[n + 1]; for (i = 0; i <= n; i++) d[i] = 100000000000; queue<long long> q; d[1] = 0; q.push(1); vis[1] = 1; long long farthest = -1; while (!q.empty()) { long long s = q.front(); q.pop(); for (auto u : adj[s]) { if (vis[u]) continue; vis[u] = 1; d[u] = d[s] + 1; farthest = u; q.push(u); } } long long par[n + 1]; for (i = 0; i <= n; i++) par[i] = -1; for (i = 0; i <= n; i++) { d[i] = 100000000000; vis[i] = 0; } d[farthest] = 0; q.push(farthest); vis[farthest] = 1; long long farthest1 = -1; while (!q.empty()) { long long s = q.front(); q.pop(); for (auto u : adj[s]) { if (vis[u]) continue; vis[u] = 1; d[u] = d[s] + 1; par[u] = s; farthest1 = u; q.push(u); } } for (i = 0; i <= n; i++) vis[i] = 0; long long node = farthest1; while (node != farthest) { vis[node] = 1; node = par[node]; } vis[node] = 1; long long ans = d[farthest1]; for (i = 1; i <= n; i++) { d[i] = 0; if (vis[i] == 1) { q.push(i); } } long long farthest2 = -1; while (!q.empty()) { long long s = q.front(); q.pop(); for (auto u : adj[s]) { if (vis[u]) continue; vis[u] = 1; d[u] = d[s] + 1; par[u] = s; farthest2 = u; q.push(u); } } if (farthest2 != -1) ans += d[farthest2]; else { for (i = 1; i <= n; i++) { if (i != farthest1 && i != farthest) { farthest2 = i; break; } } } cout << ans << n ; cout << farthest2 << << farthest1 << << farthest << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 20; vector<int> a[N]; vector<int> Q; int t, x, p, k; int solve(int n, int p) { int ret = 0; Q.clear(); Q.push_back(-1); vector<int>& f = a[p]; for (int i = 0; i < (int)f.size(); ++i) { int top = Q.size(); for (int j = 0; j < top; ++j) { Q.push_back(-1 * f[i] * Q[j]); } } for (int i = 1; i < (int)Q.size(); ++i) { ret += n / Q[i]; } return n - ret; } int main() { for (int i = 2; i <= 1000000; ++i) { if (a[i].size() > 0) continue; for (int j = i; j <= 1000000; j += i) { a[j].push_back(i); } } scanf( %d , &t); while (t--) { scanf( %d %d %d , &x, &p, &k); k += solve(x, p); int lb = 1, ub = 1e9, ans = x; while (lb <= ub) { int mid = (lb + ub) / 2; if (solve(mid, p) >= k) { ans = mid; ub = mid - 1; } else { lb = mid + 1; } } printf( %d n , ans); } } |
#include <bits/stdc++.h> using namespace std; bool prime(int x) { if (x == 1) return false; else if (x == 2) return true; for (int i = 2; i * i <= x; i++) { if (x % i == 0) return false; } return true; } void fun2(int t) { if (t == 1) { cout << * ; return; } cout << * ; return fun2(t - 1); } void fun(int s) { map<int, int> asd; map<int, int>::iterator ir; ir = asd.begin(); ir->first; if (s) { cout << s % 10 << endl; fun(s / 10); } } long long numb(long long i) { if (i == 2 || i == 1) return 1; else { long long n = i, z = 0; while (n > 1) { if (i % n == 0) { z++; } n--; } return z; } } int main() { std::ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int r1, r2, c1, c2, d1, d2; cin >> r1 >> r2 >> c1 >> c2 >> d1 >> d2; vector<vector<int>> v(2, vector<int>(2)); v[0][0] = (r1 - c2 + d1) / 2; v[0][1] = r1 - v[0][0]; v[1][0] = c1 - v[0][0]; v[1][1] = d1 - v[0][0]; bool b = true; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { for (int h = 0; h < 2; h++) { for (int g = 0; g < 2; g++) { if (i == h && j == g) continue; if (v[i][j] == v[h][g]) { b = false; } } } } } for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { if (v[i][j] == 0 || v[i][j] > 9) b = false; } } if (r1 != v[0][0] + v[0][1] || r2 != v[1][0] + v[1][1] || c1 != v[0][0] + v[1][0] || c2 != v[0][1] + v[1][1] || d1 != v[0][0] + v[1][1] || d2 != v[0][1] + v[1][0]) b = false; if (b) { for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { cout << v[i][j] << ; } cout << endl; } } else { cout << -1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int inf = 1e9 + 7; const ll longinf = 1LL << 60; const ll mod = 1e9 + 7; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; for (int i = 0; i < t; ++i) { int n; cin >> n; cout << n / 2 + 1 << n ; } } |
//==================================================================================================
// Filename : testbench_CORDICArch2.v
// Created On : 2016-10-03 23:33:09
// Last Modified : 2016-10-03 23:33:26
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
module testbench_CORDIC_Arch2 (); /* this is automatically generated */
parameter PERIOD = 10;
//ESTAS SON DEFINICIONES QUE SE REALIZAN EN LOS COMANDOS O CONFIGURACIONES
//DEL SIMULADOR O EL SINTETIZADOR
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk; // Reloj del sistema.
reg rst; // Señal de reset del sistema.
reg beg_fsm_cordic; // Señal de inicio de la maquina de estados del módulo CORDIC.
reg ack_cordic; // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
reg [1:0] r_mode;
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // Señal de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
CORDIC_Arch2 #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) uut
(
.clk (clk),
.rst (rst),
.beg_fsm_cordic (beg_fsm_cordic),
.ack_cordic (ack_cordic),
.operation (operation),
.data_in (data_in),
.shift_region_flag (shift_region_flag),
.r_mode (r_mode),
.ready_cordic (ready_cordic),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.data_output (data_output)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
//reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
clk = 0;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 32'h00000000;
shift_region_flag = 2'b00;
rst = 1;
//Depending upong the sumulator, this directive will
//understand that if the macro is defined (e.g. RMODE00)
//then the following code will be added to the compilation
//simulation or sinthesis.
//This is added in order to simulate the accuracy change of the system.
`ifdef RMODE00
r_mode = 2'b00;
`endif
`ifdef RMODE01
r_mode = 2'b01;
`endif
`ifdef RMODE10
r_mode = 2'b10;
`endif
`ifdef RMODE11
r_mode = 2'b11;
`endif
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
#100 rst = 0;
// #15
// data_in = 32'h3f25514d; //37 grados
// shift_region_flag = 2'b00;
// #5
// beg_fsm_cordic = 1;
// #10
// beg_fsm_cordic = 0;
end
initial begin
$readmemh("CORDIC32_input_angles_hex.txt", Array_IN);
//$readmemh("Hexadecimal_B.txt", Array_IN_2);
end
// clock
initial forever #5 clk = ~clk;
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_fsm_cordic = 0;
data_in = Array_IN[contador];
#40;
Cont_CLK = Cont_CLK + 1;
ack_cordic = 0;
#40;
end
else if(Cont_CLK ==2) begin
ack_cordic = 0;
beg_fsm_cordic = 1;
Cont_CLK = Cont_CLK +1 ;
#40;
end
else begin
ack_cordic = 0;
Cont_CLK = Cont_CLK + 1;
beg_fsm_cordic = 0;
#40;
end
if(ready_cordic==1) begin
ack_cordic = 1;
Cont_CLK = 0;
#15;
end
if(ready_cordic==1 && ack_cordic) begin
Cont_CLK = 0;
#15;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready_cordic) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",data_output);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 14:29:09 09/24/2015
// Design Name: KeyScanController
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/Lab2-Part2-Controller7SegmentDisplayKeypadScanner/KeyScanControlleTest.v
// Project Name: Lab2-Part2-Controller7SegmentDisplayKeypadScanner
////////////////////////////////////////////////////////////////////////////////
module KeyScanControllerTest;
reg Clock, Found, Reset, Start;
wire Load, Shift;
wire [2:0] CurrentState = uut.CurrentState;
wire StartTimer = uut.StartTimer;
wire TimerDone = uut.TimerDone;
defparam uut.Timer.Divider = 3;
KeyScanController uut(Clock, Found, Reset, Start, Load, Shift);
always #10 Clock = ~Clock;
initial begin
Clock = 0; Found = 0; Reset = 1; Start = 0; #25;
Start = 1; #20;
Reset = 0; #20;
Start = 0; #90;
Found = 1; #30;
Found = 0; #40;
Start = 1; #20;
Start = 0; #40;
Found = 1; #80;
Found = 0; #450;
$stop;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFINV_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__BUFINV_PP_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__bufinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFINV_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { while (b) { a %= b; swap(a, b); } return a; } int main() { int n; cin >> n; vector<int> q(n); for (int i = 0; i < n; ++i) cin >> q[i]; vector<int> cost(n, -1); int m; cin >> m; for (int i = 0; i < m; ++i) { int a, b, c; cin >> a >> b >> c; if (cost[b - 1] == -1 || cost[b - 1] > c) { cost[b - 1] = c; } } int ans = 0, head = 0; for (int i = 0; i < n; ++i) { if (cost[i] != -1) ans += cost[i]; else head++; } if (head > 1) cout << -1 << endl; else { if (!head) { int maxx = cost[0]; for (int i = 1; i < n; ++i) maxx = max(maxx, cost[i]); ans -= maxx; } cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_TB_V
`define SKY130_FD_SC_HS__DLRTN_TB_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hs__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_TB_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { int A, B; cin >> A >> B; string a, b; cin >> a >> b; int p = 0, m = a.size(); for (int i = 0; i + a.size() <= b.size(); i++) { int k = 0; for (int j = 0; j < a.size(); j++) { if (a[j] != b[i + j]) k++; } if (k < m) { m = k; p = i; } } vector<int> v; for (int i = 0; i < a.size(); i++) { if (a[i] != b[i + p]) v.push_back(i); } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { cout << v[i] + 1 << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; char ch = getchar(); bool f = 0; for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = 1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return f ? -x : x; } void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(long long x) { write(x); putchar( n ); } void writep(long long x) { write(x); putchar( ); } long long const N = 1e6 + 3; long long n, a[N]; signed main() { n = read(); long long ans = 0; for (long long i = 1; i <= n; i++) a[i] = read(), ans += a[i]; if (n == 1) { writeln(a[1]); return 0; } sort(a + 1, a + n + 1); if (a[1] <= 0) { for (long long i = 1; i < n && a[i] <= 0; i++) ans -= 2 * a[i]; } else { ans -= 2 * a[1]; } writeln(ans); } |
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Thanks Rudolf Usselmann yours was a better implementation than mine
Copyright (C) 2000-2002
Rudolf Usselmann
www.asics.ws
*/
`timescale 1 ns/1 ps
module wishbone_interconnect (
//control signals
input clk,
input rst,
//wishbone master signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int,
//Slave 1
output o_s1_we,
output o_s1_cyc,
output o_s1_stb,
output [3:0] o_s1_sel,
input i_s1_ack,
output [31:0] o_s1_dat,
input [31:0] i_s1_dat,
output [31:0] o_s1_adr,
input i_s1_int,
//Slave 2
output o_s2_we,
output o_s2_cyc,
output o_s2_stb,
output [3:0] o_s2_sel,
input i_s2_ack,
output [31:0] o_s2_dat,
input [31:0] i_s2_dat,
output [31:0] o_s2_adr,
input i_s2_int,
//Slave 3
output o_s3_we,
output o_s3_cyc,
output o_s3_stb,
output [3:0] o_s3_sel,
input i_s3_ack,
output [31:0] o_s3_dat,
input [31:0] i_s3_dat,
output [31:0] o_s3_adr,
input i_s3_int,
//Slave 4
output o_s4_we,
output o_s4_cyc,
output o_s4_stb,
output [3:0] o_s4_sel,
input i_s4_ack,
output [31:0] o_s4_dat,
input [31:0] i_s4_dat,
output [31:0] o_s4_adr,
input i_s4_int
);
parameter ADDR_0 = 0;
parameter ADDR_1 = 1;
parameter ADDR_2 = 2;
parameter ADDR_3 = 3;
parameter ADDR_4 = 4;
parameter ADDR_FF = 8'hFF;
//state
//wishbone slave signals
//this should be parameterized
wire [7:0]slave_select;
wire [31:0] interrupts;
assign slave_select = i_m_adr[31:24];
//data in from slave
always @ (slave_select or i_s0_dat or i_s1_dat or i_s2_dat or i_s3_dat or i_s4_dat or interrupts) begin
case (slave_select)
ADDR_0: begin
o_m_dat <= i_s0_dat;
end
ADDR_1: begin
o_m_dat <= i_s1_dat;
end
ADDR_2: begin
o_m_dat <= i_s2_dat;
end
ADDR_3: begin
o_m_dat <= i_s3_dat;
end
ADDR_4: begin
o_m_dat <= i_s4_dat;
end
default: begin
o_m_dat <= interrupts;
end
endcase
end
//ack in from slave
always @ (slave_select or i_s0_ack or i_s1_ack or i_s2_ack or i_s3_ack or i_s4_ack) begin
case (slave_select)
ADDR_0: begin
o_m_ack <= i_s0_ack;
end
ADDR_1: begin
o_m_ack <= i_s1_ack;
end
ADDR_2: begin
o_m_ack <= i_s2_ack;
end
ADDR_3: begin
o_m_ack <= i_s3_ack;
end
ADDR_4: begin
o_m_ack <= i_s4_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
assign interrupts[0] = i_s0_int;
assign interrupts[1] = i_s1_int;
assign interrupts[2] = i_s2_int;
assign interrupts[3] = i_s3_int;
assign interrupts[4] = i_s4_int;
assign interrupts[31:5] = 0;
assign o_m_int = (interrupts != 0);
assign o_s0_we = (slave_select == ADDR_0) ? i_m_we: 1'b0;
assign o_s0_stb = (slave_select == ADDR_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (slave_select == ADDR_0) ? i_m_sel: 4'h0;
assign o_s0_cyc = (slave_select == ADDR_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (slave_select == ADDR_0) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s0_dat = (slave_select == ADDR_0) ? i_m_dat: 32'h0;
assign o_s1_we = (slave_select == ADDR_1) ? i_m_we: 1'b0;
assign o_s1_stb = (slave_select == ADDR_1) ? i_m_stb: 1'b0;
assign o_s1_sel = (slave_select == ADDR_1) ? i_m_sel: 4'h0;
assign o_s1_cyc = (slave_select == ADDR_1) ? i_m_cyc: 1'b0;
assign o_s1_adr = (slave_select == ADDR_1) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s1_dat = (slave_select == ADDR_1) ? i_m_dat: 32'h0;
assign o_s2_we = (slave_select == ADDR_2) ? i_m_we: 1'b0;
assign o_s2_stb = (slave_select == ADDR_2) ? i_m_stb: 1'b0;
assign o_s2_sel = (slave_select == ADDR_2) ? i_m_sel: 4'h0;
assign o_s2_cyc = (slave_select == ADDR_2) ? i_m_cyc: 1'b0;
assign o_s2_adr = (slave_select == ADDR_2) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s2_dat = (slave_select == ADDR_2) ? i_m_dat: 32'h0;
assign o_s3_we = (slave_select == ADDR_3) ? i_m_we: 1'b0;
assign o_s3_stb = (slave_select == ADDR_3) ? i_m_stb: 1'b0;
assign o_s3_sel = (slave_select == ADDR_3) ? i_m_sel: 4'h0;
assign o_s3_cyc = (slave_select == ADDR_3) ? i_m_cyc: 1'b0;
assign o_s3_adr = (slave_select == ADDR_3) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s3_dat = (slave_select == ADDR_3) ? i_m_dat: 32'h0;
assign o_s4_we = (slave_select == ADDR_4) ? i_m_we: 1'b0;
assign o_s4_stb = (slave_select == ADDR_4) ? i_m_stb: 1'b0;
assign o_s4_sel = (slave_select == ADDR_4) ? i_m_sel: 4'h0;
assign o_s4_cyc = (slave_select == ADDR_4) ? i_m_cyc: 1'b0;
assign o_s4_adr = (slave_select == ADDR_4) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s4_dat = (slave_select == ADDR_4) ? i_m_dat: 32'h0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_4_V
`define SKY130_FD_SC_LP__AND4BB_4_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_BLACKBOX_V
`define SKY130_FD_SC_MS__A311O_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int N, M; long long Ans; struct rec { int w, h, s, k; rec() {} rec(int a, int b, int c, int i) { w = a; h = b; s = c; k = i; } } P[1010], Q[1010]; int vis[1010]; bool cmp_h(const rec &a, const rec &b) { return a.h > b.h; } bool cmp_s(const rec &a, const rec &b) { return a.s > b.s; } long long sumw(int maxh) { long long sum = 0; int cnt = 0; for (int i = 1; i <= N; ++i) { if (P[i].h <= maxh) break; int s = 1e10; if (P[i].w <= maxh && cnt < M) { ++cnt; vis[P[i].k] = maxh; s = P[i].h; } sum += s; } for (int i = 1; i <= N; ++i) if (vis[Q[i].k] != maxh) { int s = Q[i].w; if (Q[i].w <= maxh && cnt < M && s > Q[i].h) { ++cnt; vis[Q[i].k] = maxh; s = Q[i].h; } sum += s; } return sum; } int main() { scanf( %d , &N); M = N / 2; for (int i = 1; i <= N; ++i) { int w, h; scanf( %d%d , &w, &h); Q[i] = P[i] = rec(w, h, w - h, i); } sort(P + 1, P + N + 1, cmp_h); sort(Q + 1, Q + N + 1, cmp_s); Ans = 1e9; for (int hi = 1; hi <= 1000; ++hi) { Ans = min(Ans, (long long)hi * sumw(hi)); } printf( %lld n , Ans); } |
// part of NeoGS project (c) 2007-2008 NedoPC
//
// sound_mulacc is a serial multiplier-accumulator for volume and sound data value.
// Input data is: volume (6bit unsigned) and sound data (8bit signed with sign bit inverted,
// thus compatible with unsigned data centered at $7f-$80), and clr_sum bit.
// Input data is read and multiply-add starts after 1-clock positive pulse on load pin,
// when ready becomes 1, operation is finished, output is defined and another load pulse could be accepted.
// If clr_sum is read to be 1, sum is also cleared (and the output will be just result of multiply), otherwise
// output will be the sum of previous result with current multiplication result.
//
// clock number XX | 00 | 01 | 02 | || | 14 | 15 | 16 |
// clock __/``\__/``\__/``\__/``\__/``||_/``\__/``\__/``\__/``\__/``\__/``\__/``\__/``
// load _________/`````\___________________||______________________________________________
// inputs are read here --> * ||
// ready ```````````````\___________________||______________/```````````````````````````````
// data out old data |XXXXXXXXXXXXX||XXXXXXXXXXXXXX| new data ready
module sound_mulacc(
clock, // input clock (24 MHz)
vol_in, // input volume (6 bit unsigned)
dat_in, // input sound data (8 bit signed with sign bit inverted)
mode_inv7b, // whether to invert 7th bit of dat_in
load, // load pulse input
clr_sum, // clear sum input
ready, // ready output
sum_out // 16-bit sum output
);
input clock;
input [5:0] vol_in;
input [7:0] dat_in;
input mode_inv7b;
input load;
input clr_sum;
output reg ready;
output reg [15:0] sum_out;
wire [5:0] add_data;
wire [6:0] sum_unreg;
reg [6:0] sum_reg;
reg [7:0] shifter;
reg [5:0] adder;
wire mul_out;
reg [3:0] counter;
reg clr_sum_reg;
wire [1:0] temp_sum;
wire carry_in;
wire old_data_in;
reg old_carry;
// control section
//
always @(posedge clock)
begin
if( load )
ready <= 1'b0;
if( counter[3:0] == 4'd15 )
ready <= 1'b1;
if( load )
counter <= 4'd0;
else
counter <= counter + 4'd1;
end
// serial multiplier section
//
assign add_data = ( shifter[0] ) ? adder : 6'd0; // data to be added controlled by LSB of shifter
assign sum_unreg[6:0] = sum_reg[6:1] + add_data[5:0]; // sum of two values
assign mul_out = sum_unreg[0];
always @(posedge clock)
begin
if( !load ) // normal addition
begin
sum_reg[6:0] <= sum_unreg[6:0];
shifter[6:0] <= shifter[7:1];
end
else // load==1
begin
sum_reg[6:0] <= 7'd0;
shifter[7] <= ~(mode_inv7b^dat_in[7]); // convert to signed data (we need signed result), invert 7th bit if needed
shifter[6:0] <= dat_in[6:0];
adder <= vol_in;
end
end
// serial adder section
//
always @(posedge clock)
begin
if( load )
clr_sum_reg <= clr_sum;
end
assign carry_in = (counter==4'd0) ? 1'b0 : old_carry;
assign old_data_in = (clr_sum_reg) ? 1'b0 : sum_out[0];
assign temp_sum[1:0] = carry_in + mul_out + old_data_in;
always @(posedge clock)
begin
if( !ready )
begin
sum_out[15:0] <= { temp_sum[0], sum_out[15:1] };
old_carry <= temp_sum[1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long BigMod(long long B, long long P, long long M) { long long R = 1; while (P > 0) { if (P % 2 == 1) { R = (R * B) % M; } P /= 2; B = (B * B) % M; } return R; } template <class T1> void deb(T1 e1) { cout << e1 << endl; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << endl; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << endl; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << endl; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << endl; } const int MAX = 100060; map<int, int> mpp; int cnt[2][MAX]; int res[MAX]; int main() { memset(cnt, (0), sizeof(cnt)); ; vector<int> tmp, rval; int v; set<int> com; int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &v); rval.push_back((v)); tmp.push_back((v)); } sort(tmp.begin(), tmp.end()); for (int i = 0; i < n; i++) { mpp[tmp[i]] = i + 1; } v = mpp[rval[0]]; com.insert(v); for (int i = 1; i < n; i++) { v = mpp[rval[i]]; auto it = com.lower_bound(v); if (it != com.begin()) { auto it1 = it; it1--; int u = (*it1); if (cnt[0][u] != -1) { res[i] = tmp[u - 1]; com.insert(v); cnt[0][u]--; continue; } } if (it != com.end()) { auto it1 = it; int u = (*it1); if (cnt[1][u] != -2) { res[i] = tmp[u - 1]; com.insert(v); cnt[1][u]--; continue; } } } for (int i = 1; i < n; i++) { if (i != 1) printf( ); printf( %d , res[i]); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int s[100010]; int main() { long long n, x; cin >> n >> x; long long sum = 0, ans = 0; for (int i = 0; i < n; i++) { cin >> s[i]; } sort(s, s + n); int j = 0; while (j < n) { if (x < 1) x = 1; ans += s[j] * x; x--; j++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( no-stack-protector ) #pragma GCC target( sse,sse2,ssse3,sse3,sse4,popcnt,avx,mmx,abm,tune=native ) using namespace std; signed main() { cin.tie(nullptr)->sync_with_stdio(false); long long n, k; cin >> n >> k; string s, t; cin >> s >> t; long long ans = 0, hv = 1; for (long long i = 0; i < n; i++) { if (hv < k) { hv *= 2; if (s[i] == t[i]) { hv--; } else if (s[i] == b && t[i] == a ) { hv -= 2; } hv = min(hv, k); } ans += hv; } cout << ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INPUTISO0P_FUNCTIONAL_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_FUNCTIONAL_V |
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency simulation mode. In this
// case just pass everything through to the ARM, which can bit-bang this
// (because it is so slow).
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd191);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule
|
#include <bits/stdc++.h> template <class T> const T& min(const T& a, const T& b, const T& c) { return min(a, min(b, c)); } template <class T> const T& max(const T& a, const T& b, const T& c) { return max(a, max(b, c)); } using namespace std; int gcd(long long a, long long b) { while (true) { if (a < b) swap(a, b); if (b == 0) return a; a = a % b; } } int main() { int n, k; cin >> n >> k; if (k > n) { cout << -1 ; return 0; } if (k == 1) { if (n == 1) cout << a ; else cout << -1 ; return 0; } if (k == 2) { for (__typeof(n) i = 0; i < n; i++) { cout << (((i % 2) == 0) ? a : b ); } return 0; } int written = 0; for (__typeof(n - (k - 2)) i = 0; i < n - (k - 2); i++) { cout << (((i % 2) == 0) ? a : b ); } for (__typeof(k - 2) i = 0; i < k - 2; i++) { char c = c + i; cout << c; } } template <class T> string toStr(T t) { std::stringstream strstream; string resStr; strstream << t; strstream >> resStr; return resStr; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n <= 4) cout << No solution << endl; else { double alpha = 2 * M_PI / n; cout << fixed << setprecision(6); double x = 0, y = 0; for (int i = 1; i <= n - 2; i++) { cout << x << << y << endl; double l = 500; l += 0.01 * i; x += l * cos(alpha * i), y += l * sin(alpha * i); } cout << x << << y << endl; x -= y / sin(alpha * (n - 1)) * cos(alpha * (n - 1)), y = 0; cout << x << << y << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; mt19937 rng((int)chrono::steady_clock::now().time_since_epoch().count()); struct kuhn { int n, m; vector<vector<int>> g; vector<int> vis, ma, mb; kuhn(int n_, int m_) : n(n_), m(m_), g(n), vis(n + m), ma(n, -1), mb(m, -1) {} void add(int a, int b) { g[a].push_back(b); } bool dfs(int i) { vis[i] = 1; for (int j : g[i]) if (!vis[n + j]) { vis[n + j] = 1; if (mb[j] == -1 or dfs(mb[j])) { ma[i] = j, mb[j] = i; return true; } } return false; } int matching() { int ret = 0, aum = 1; for (auto& i : g) shuffle(i.begin(), i.end(), rng); while (aum) { for (int j = 0; j < m; j++) vis[n + j] = 0; aum = 0; for (int i = 0; i < n; i++) if (ma[i] == -1 and dfs(i)) ret++, aum = 1; } return ret; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<string> v(n); for (auto& i : v) cin >> i; vector<string> v2; kuhn k((n - 1) * m, (m - 1) * n); int vert = 0, qt = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (v[i][j] == # ) { qt++; if (i + 1 < n and v[i + 1][j] == # ) { vert++; if (j + 1 < m and v[i][j + 1] == # ) k.add(m * i + j, n * j + i); if (j + 1 < m and v[i + 1][j + 1] == # ) k.add(m * i + j, n * j + i + 1); if (j and v[i][j - 1] == # ) k.add(m * i + j, n * (j - 1) + i); if (j and v[i + 1][j - 1] == # ) k.add(m * i + j, n * (j - 1) + i + 1); } if (j + 1 < m and v[i][j + 1] == # ) vert++; } cout << qt - (vert - k.matching()) << n ; exit(0); } |
#include <bits/stdc++.h> int n, m, p, r[605], c[605], f[605], g[605][605], a[605][605], b[605][605]; void tuopu() { int h = 0, t = 0; for (int i = 1; i <= n; i++) if (!r[i]) f[++t] = i, g[i][t] = 1; m = t; while (h < t) { int x = f[++h]; for (int i = 1; i <= n; i++) if (b[x][i]) { r[i] -= b[x][i]; if (!r[i]) f[++t] = i; for (int j = 1; j <= m; j++) g[i][j] = (g[i][j] + (long long)g[x][j] * b[x][i]) % p; } } int now = 0; for (int j = 1; j <= n; j++) if (!c[j]) { ++now; for (int i = 1; i <= m; i++) a[i][now] = g[j][i]; } } void swap(int &x, int &y) { int tmp = x; x = y; y = tmp; } void work() { int flag = 1; for (int i = 1; i <= m; i++) { if (!a[i][i]) for (int j = i + 1; j <= m; j++) if (a[j][i]) { for (int k = i; k <= m; k++) swap(a[i][k], a[j][k]); flag = -flag; break; } for (int j = i + 1; j <= m; j++) while (a[j][i]) { long long z; if (a[i][i]) z = a[j][i] / a[i][i]; else z = 0; flag = -flag; for (int k = i; k <= m; k++) a[j][k] = (a[j][k] - z * a[i][k]) % p, swap(a[j][k], a[i][k]); } } long long ans = flag; for (int i = 1; i <= m; i++) ans = ans * a[i][i] % p; printf( %d n , (ans + p) % p); } int main() { scanf( %d%d%d , &n, &m, &p); int x, y; for (int i = 1; i <= m; i++) scanf( %d%d , &x, &y), b[x][y]++, c[x]++, r[y]++; tuopu(); work(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_SYMBOL_V
`define SKY130_FD_SC_HVL__NOR2_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_SYMBOL_V
|
//Copyright 2014 Zeno Futurista ()
//
//Licensed under the Apache License, Version 2.0 (the "License");
//you may not use this file except in compliance with the License.
//You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//Unless required by applicable law or agreed to in writing, software
//distributed under the License is distributed on an "AS IS" BASIS,
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//See the License for the specific language governing permissions and
//limitations under the License.
//I hope this writings will be usefull for someone, i am trying to follow nice variable namings
//so that it should be easy to understand even for people not skilled in verilog
//this module has following functions:
//deserializer/serializer for input output serial wire format
//sha job controller and result filter
//extern module queueram #(parameter elementWidth = 8, parameter elementCount = 8) (input clk, input [(elementWidth-1):0] data[0:(elementCount-1)], input [7:0] write_addr, input [7:0] read_addr, input we, output [(elementWidth-1):0] q[0:(elementCount-1)]);
extern module queueram #(parameter elementWidth = 32, parameter elementCount = 8, parameter depth = 256, parameter addrWidth = log2(depth)) (input clk, input [(elementWidth-1):0] data[0:(elementCount-1)], input [(addrWidth-1):0] write_addr, input [(addrWidth-1):0] read_addr, input we, output [(elementWidth-1):0] q[0:(elementCount-1)]);
module sha_core(
input clk,
//result from sha mix
input [7:0] hashResult[0:31],
//job which corresponds to result
input [31:0] jobIn,
//corresponding nonce
input [31:0] nonceIn,
//result available signal
input resultReady,
//input data available signal
input load,
//input data
input[7:0] in,
//transmitter ready signal
input read,
//output data for sha mix
output[7:0] dataToHash[0:79],
//job for mix
output [31:0] jobOut,
//output signal for mix to begin work
output reg startHashing,
//signal for transmitter - there is result available - start sending
output jobReady,
//output data for transmitter
output [7:0] out
);
//serializer/deserializer pointers
reg[10:0] write_ptr;
reg[10:0] read_ptr;
//output job nonce pair wires
wire [7:0] jobNonce[0:7];
wire [7:0] jobNonceMem[0:7];
//assemble job ID from deserialized data
assign jobOut = {header[84], header[85], header[86], header[87]};
//target used to compare result
wire [31:0] target = {header[80], header[81], header[82], header[83]};
//actual haeader working header (contains btc protocol header, target and jobID - header = 80B, target = 4B, job = 4B)
reg[7:0] header[0:87];
//data to be hashed (first 80B of receive header)
assign dataToHash = header[0:79];
//queue 8 zeros to be sent to client software when, (client should never use job ID 0)
assign jobNonce[0] = jobIn[31:24];
assign jobNonce[1] = jobIn[23:16];
assign jobNonce[2] = jobIn[15:8];
assign jobNonce[3] = jobIn[7:0];
assign jobNonce[4] = nonceIn[31:24];
assign jobNonce[5] = nonceIn[23:16];
assign jobNonce[6] = nonceIn[15:8];
assign jobNonce[7] = nonceIn[7:0];
//internal states
//we hit last nonce, signal that we need new work
reg requestWorkEnable;
//after all results have been sent, do actual request
wire requestNewWork = (requestWorkEnable & ~jobReady);
//we need to drop one result from result queue
reg resultSent;
wire [7:0] zeros[0:7] = '{0,0,0,0,0,0,0,0};
//queues result if difficulty is met
resultqueue rq(clk, difficultyMet | requestNewWork, resultSent, requestNewWork ? zeros : resultBuffer, jobNonceMem, jobReady);
//result buffer
reg [7:0] resultBuffer[0:7];
//difficulty met signal register
reg difficultyMet;
//some initials
initial begin
write_ptr = 0;
read_ptr = 0;
startHashing = 0;
end
//set actual output byte
assign out = jobNonceMem[read_ptr];
always @(posedge clk) begin
if(load) begin
//there is something to deserialize
header[write_ptr] <= in;
if(write_ptr == 87) begin
write_ptr <= 0;
//all work data ready, start mixing
startHashing <= 1;
end else begin
write_ptr <= write_ptr + 1;
end
end
//switch off startHashing signal after one cycle
if(startHashing) begin
startHashing <= 0;
end
//buffer input jobnonce
resultBuffer <= jobNonce;
if(resultReady) begin
//job filter, decides if we met requested difficulty
difficultyMet <= ({hashResult[31],hashResult[30],hashResult[29],hashResult[28]} == 0) & ({hashResult[27],hashResult[26],hashResult[25],hashResult[24]} <= target);
//result with last nonce occured, we need new work
if((nonceIn == 32'hffffffff) && (jobIn == jobOut)) begin
requestWorkEnable <= 1;
end
end else begin
//otherwise nothing happened
difficultyMet <= 0;
end
//queue request new work packet (8 zeros)
//client driver understands to this message and knows that it should schedule new work
//therefore job should not use zero ID
if(requestNewWork) begin
requestWorkEnable <= 0;
end
//wait one cycle after sending last byte
if(resultSent) begin
resultSent <= 0;
end
//this end part is responsible for setting data to be sent
//there must be some job waiting in queue, transmitter ready to read, and one cycle pause after previous result (queue drops, it is probably not neccessarry cause queue is passtrough)
if(jobReady & read & ~resultSent) begin
if(read_ptr == 7) begin
//end of packet
read_ptr <= 0;
resultSent <= 1;
end else begin
read_ptr <= read_ptr +1;
end
end
end
endmodule
//queue - same as in sha, but different data size
//inspiration taken from altera examples
//this queue now replaces last element if it is full, could be changed, but newer results are ussually better
//anyway it should be never filled, if so we need to change target
//specifically tailored for sha miner
module resultqueue(input clk, input write, input read, input [7:0] in[0:7], output [7:0] out[0:7], output available, output full);
reg[7:0] write_addr, read_addr;
reg[8:0] count;
ram #(.elementWidth(8), .elementCount(8), .depth(256)) ram(clk, in, write_addr, (read & available) ? (read_addr+1) : read_addr, write, out);
initial begin
read_addr = 0;
write_addr = 0;
count = 0;
end
//queue is full
assign full = (count == 256);
//some elements available
assign available = (count > 0);
always@(posedge clk) begin
//put, drop and available case
if(write & read & available) begin
write_addr <= write_addr + 1;
read_addr <= read_addr +1;
//write only case
end else if(write) begin
write_addr <= write_addr + 1;
//this causes rewrite of oldest value
if(~full) begin
count <= count +1;
end
//drop only case
end else if(read & available) begin
read_addr <= read_addr + 1;
count <= count - 1;
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file inst_mem.v when simulating
// the core, inst_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module inst_mem(
clka,
addra,
douta);
input clka;
input [6 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(7),
.C_ADDRB_WIDTH(7),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(128),
.C_READ_DEPTH_B(128),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("NONE"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(128),
.C_WRITE_DEPTH_B(128),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3e"))
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of inst_mem is "black_box"
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(3) using namespace std; inline long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline long long lcm(long long a, long long b) { return a * b / gcd(a, b); } inline int qpow(int a, int n) { int ans = 1; while (n) { if (n & 1) { ans *= a; } a *= a; n >>= 1; } return ans; } inline long long _qpow(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } inline long long ksm(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } const int maxnum = 1e6 + 5; const int MAXN = (1 << 13) - 1; set<int> st[maxnum]; int n; int x; int f[MAXN + 5]; void slove() { cin >> n; for (int i = 1; i <= n; i++) { cin >> x; st[x].insert(i); } for (int i = 0; i <= MAXN; i++) f[i] = 0x3f3f3f3f; f[0] = 0; for (int i = 0; i <= MAXN; i++) { for (int j = MAXN; j >= 0; j--) { auto it = st[i].upper_bound(f[j]); if (it != st[i].end()) { f[i ^ j] = min(f[i ^ j], *it); } } } vector<int> ans; for (int i = 0; i <= MAXN; i++) { if (f[i] != 0x3f3f3f3f) ans.push_back(i); } cout << ans.size() << n ; for (int x : ans) cout << x << ; cout << n ; } signed main() { std::ios::sync_with_stdio(false); std::cin.tie(0); ; slove(); return 0; } |
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