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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_cnt_lead0_lvl1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Lowest level of lead 0 counters. Lead 0 count for 4 bits.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_cnt_lead0_lvl1 (
din,
din_3_0_eq_0,
din_3_2_eq_0,
lead0_4b_0
);
input [3:0] din; // data for lead 0 count bits[3:0]
output din_3_0_eq_0; // data in[3:0] is zero
output din_3_2_eq_0; // data in[3:2] is zero
output lead0_4b_0; // bit[0] of lead 0 count
wire din_3_0_eq_0;
wire din_3_2_eq_0;
wire lead0_4b_0;
assign din_3_0_eq_0= (!(|din[3:0]));
assign din_3_2_eq_0= (!(|din[3:2]));
assign lead0_4b_0= ((!din_3_2_eq_0) && (!din[3]))
|| (din_3_2_eq_0 && (!din[1]));
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:35:24 11/16/2014
// Design Name: vCounter2BCD
// Module Name: /home/aneez/workspace/vLCDisplay/vCounter2BCD_tb.v
// Project Name: vLCDisplay
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: vCounter2BCD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module vCounter4DigitBCD_tb;
// Inputs
reg clk;
reg enable;
reg rst;
// Outputs
wire [15:0] count;
wire cout;
// Instantiate the Unit Under Test (UUT)
vCounter4DigitBCD uut (
.clk(clk),
.count(count),
.enable(enable),
.cout(cout),
.grst(rst)
);
initial begin
// Initialize Inputs
clk = 0;
enable = 0;
rst = 0;
#10 enable = 1;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
always #10 clk = ~clk;
initial
#10000 $finish;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, s = 19, i, sum, j, l; int main() { cin >> n; for (i = 1; i < n; i++) { s += 9; l = s; while (l) { sum += (l % 10); l /= 10; } if (sum != 10) i--; sum = 0; } cout << s; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Boston University
// Engineer: Zafar M. Takhirov
//
// Create Date: 12:59:40 04/12/2011
// Design Name: EC311 Support Files
// Module Name: vga_display
// Project Name: Lab5 / Lab6 / Project
// Target Devices: xc6slx16-3csg324
// Tool versions: XILINX ISE 13.3
// Description:
//
// Dependencies: vga_controller_640_60
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_display(St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar,
HS, VS, R, G, B, An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp,
Sw0, Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw7,
rst, ClkPort, btnU, btnD);
input rst; // global reset
input ClkPort, btnU, btnD;
input Sw0, Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw7;
// color outputs to show on display (current pixel)
output [2:0] R, G;
output [1:0] B;
output St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar;
output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
reg [2:0] R, G;
reg [1:0] B;
wire [2:0] sprite_R, sprite_G;
wire [1:0] sprite_B;
assign {St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_oe_bar, Mt_St_we_bar} = {5'b00000};//{5'b11111};
assign {An0, An1, An2, An3} = {4'b0000};
assign {Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp} = {8'hFF};
wire [7:0] switches;
assign switches = {Sw0, Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw7};
// Synchronization signals
output HS;
output VS;
// controls:
wire [10:0] hcount, vcount; // coordinates for the current pixel
wire blank; // signal to indicate the current coordinate is blank
wire figure; // the figure you want to display
// memory interface:
reg [7:0] dout;
wire [7:0] ben_dout;
wire [7:0] dec_dout;
reg [14:0] ben_read_addr;
wire [14:0] decr_read_addr;
wire [14:0] sprite_read_addr;
wire inside_image;
// wire [7:0] pezh_dout;
/////////////////////////////////////////////////////
// Begin clock division
parameter N = 2; // VGA clock divider
parameter dec_N = 12; //16; // decryptor clock divider
reg clk_25Mhz;
reg clk_decrypter;
reg [dec_N-1:0] count;
initial count = 0;
always @ (posedge ClkPort) begin
count <= count + 1'b1;
clk_25Mhz <= count[N-1];
clk_decrypter <= count[dec_N-1];
end
assign MEM_READ_CLOCK = clk_25Mhz;
assign MEM_WRITE_CLOCK = clk_25Mhz;
reg [30:0] icount;
initial icount = 0;
reg decrypter_active;
initial decrypter_active = 0;
reg [14:0] write_addr;
wire [14:0] write_addr_dec;
reg [14:0] reset_addr;
wire dec_done;
always @ (posedge MEM_WRITE_CLOCK) begin
icount <= icount + 1;
if (!dec_done) begin
write_addr <= write_addr_dec;
dec_mem_din <= dec_din;
reset_addr <= 0;
if (icount[26]) begin
dout <= dec_dout;
ben_read_addr <= decr_read_addr;
decrypter_active <= 1'b1;
end else begin
dout <= ben_dout;
ben_read_addr <= sprite_read_addr;
decrypter_active <= 1'b0;
end
R <= sprite_R;
G <= sprite_G;
B <= sprite_B;
end else begin
// why the f is this - 4 who knows :'(
write_addr <= reset_addr - 4;
ben_read_addr <= reset_addr;
dec_mem_din <= ben_dout;
reset_addr <= reset_addr + 1;
R <= 3'd0;
G <= 3'd0;
B <= 2'd0;
end
end
// End clock division
/////////////////////////////////////////////////////
// Call driver
vga_controller_640_60 vc(
.rst(rst),
.pixel_clk(clk_25Mhz),
.HS(HS),
.VS(VS),
.hcounter(hcount),
.vcounter(vcount),
.blank(blank)
);
vga_bsprite sprites_mem(
.hc(hcount),
.vc(vcount),
.mem_value(dout),
.rom_addr(sprite_read_addr),
.R(sprite_R),
.G(sprite_G),
.B(sprite_B),
.blank(blank),
.inside_image(inside_image)
);
pezhman_mem /*ben_mem*/ ben (
.clka(clk_25Mhz), // input clka
.addra(ben_read_addr), // input [14 : 0] read_addr
.douta(ben_dout) // output [7 : 0] douta
);
wire write_en;
wire [7:0] dec_din;
reg [7:0] dec_mem_din;
assign write_en = 1'b1; //(~blank) & inside_image;
// this will take some thought
// we want to read some part of the image (some address) and show that
// switch between ^ and reading some other part of the image that the decryptor is now decrypting and write correspondingly
reg [63:0] button_key;
always @(posedge ClkPort) begin: KEY_GEN
integer i;
for (i = 0; i < 8; i = i + 1) begin
if (switches[i])
button_key[8 * i +: 8] = 8'hFF;
else
button_key[8 * i +: 8] = 8'h00;
end
end
decrypter dec(
.clk(clk_decrypter),
.reset(rst),
.encrypted_data(ben_dout),
.read_addr(decr_read_addr),
.write_addr(write_addr_dec),
.decrypted_data(dec_din),
.decrypter_active(decrypter_active),
.done(dec_done),
.key(button_key)
);
decryption_mem dec_mem (
.clka(MEM_WRITE_CLOCK),
.addra(write_addr),
.dina(dec_mem_din),
.wea(write_en),
.clkb(MEM_READ_CLOCK),
.addrb(sprite_read_addr),
.doutb(dec_dout),
.rstb(1'b0)
);
endmodule
|
/*
Memory will halt the processor clock until the data has been obtained from the USB-EPP interface
*/
module memory(
input wire mclk,
input wire epp_astb,
input wire epp_dstb,
input wire epp_wr,
output wire epp_wait,
inout wire[7:0] epp_data,
output reg core_stall = 0,
input wire read,
input wire write,
input wire[31:0] address,
input wire[31:0] din,
output reg[31:0] dout = 0
);
parameter state_idle = 2'b00;
parameter state_read = 2'b01;
parameter state_write = 2'b10;
reg[1:0] state = state_idle;
reg[7:6] status = 0; // -> EPP
wire complete; // <- EPP
reg complete_clr = 0; // -> EPP
wire[31:0] dout_val; // <- EPP
memory_epp memory_epp_inst (
.mclk(mclk),
.epp_astb(epp_astb),
.epp_dstb(epp_dstb),
.epp_wr(epp_wr),
.epp_wait(epp_wait),
.epp_data(epp_data),
.status(status),
.address(address),
.dout(dout_val),
.din(din),
.complete(complete),
.complete_clr(complete_clr)
);
// Process
always @ (posedge mclk) begin
case(state)
state_read:
if(complete == 1) begin
dout <= dout_val;
core_stall <= 0;
complete_clr <= 1;
status <= 0;
state <= state_idle;
end
state_write:
if(complete == 1) begin
core_stall <= 0;
complete_clr <= 1;
status <= 0;
state <= state_idle;
end
default: begin
if(read == 1) begin
core_stall <= 1;
state <= state_read;
status <= 2'b10; // Status Flag = Read
end else if(write == 1) begin
core_stall <= 1;
state <= state_write;
status <= 2'b01; // Status Flag = Write
end
complete_clr <= 0;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:05:34 05/14/2015
// Design Name:
// Module Name: median5x5
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module median5x5 # (
parameter [9:0] H_SIZE = 83 // domylny rozmiar obrazu to szeroko = 64 piksele
)(
input clk,
input ce,
input rst,
input mask,
input in_de,
input in_vsync,
input in_hsync,
output median,
output out_de,
output out_vsync,
output out_hsync
);
wire [3:0] delay_line11;
reg [3:0] delay_line12 [4:0];
wire [3:0] delay_line21;
reg [3:0] delay_line22 [4:0];
wire [3:0] delay_line31;
reg [3:0] delay_line32 [4:0];
wire [3:0] delay_line41;
reg [3:0] delay_line42 [4:0];
wire [3:0] delay_line51;
reg [3:0] delay_line52 [4:0];
reg [4:0] sum_lines[4:0];
reg [4:0] sum_final;
assign delay_line11 = {mask, in_de, in_hsync, in_vsync};
//pojedyncze opoznienia dla piksela
genvar i;
generate
always @(posedge clk)
begin
delay_line12[0] <= delay_line11;
delay_line22[0] <= delay_line21;
delay_line32[0] <= delay_line31;
delay_line42[0] <= delay_line41;
delay_line52[0] <= delay_line51;
delay_line12[1] <= delay_line12[0];
delay_line22[1] <= delay_line22[0];
delay_line32[1] <= delay_line32[0];
delay_line42[1] <= delay_line42[0];
delay_line52[1] <= delay_line52[0];
delay_line12[2] <= delay_line12[1];
delay_line22[2] <= delay_line22[1];
delay_line32[2] <= delay_line32[1];
delay_line42[2] <= delay_line42[1];
delay_line52[2] <= delay_line52[1];
delay_line12[3] <= delay_line12[2];
delay_line22[3] <= delay_line22[2];
delay_line32[3] <= delay_line32[2];
delay_line42[3] <= delay_line42[2];
delay_line52[3] <= delay_line52[2];
delay_line12[4] <= delay_line12[3];
delay_line22[4] <= delay_line22[3];
delay_line32[4] <= delay_line32[3];
delay_line42[4] <= delay_line42[3];
delay_line52[4] <= delay_line52[3];
end
endgenerate;
delayLinieBRAM_WP long_delay
(
.clk(clk),
.rst(1'b0),
.ce(1'b1),
.din({delay_line12[4], delay_line22[4], delay_line32[4], delay_line42[4]}),
.dout({delay_line21, delay_line31, delay_line41, delay_line51}),
.h_size(H_SIZE - 5)
);
always @(posedge clk)
begin
//wyznaczanie sum
if(context_valid) begin
sum_lines[0] <= delay_line12[0][3] + delay_line12[1][3] + delay_line12[2][3] + delay_line12[3][3] + delay_line12[4][3];
sum_lines[1] <= delay_line22[0][3] + delay_line22[1][3] + delay_line22[2][3] + delay_line22[3][3] + delay_line22[4][3];
sum_lines[2] <= delay_line32[0][3] + delay_line32[1][3] + delay_line32[2][3] + delay_line32[3][3] + delay_line32[4][3];
sum_lines[3] <= delay_line42[0][3] + delay_line42[1][3] + delay_line42[2][3] + delay_line42[3][3] + delay_line42[4][3];
sum_lines[4] <= delay_line52[0][3] + delay_line52[1][3] + delay_line52[2][3] + delay_line52[3][3] + delay_line52[4][3];
sum_final <= sum_lines[0] + sum_lines[1] + sum_lines[2] + sum_lines[3] + sum_lines[4];
end
end
wire context_valid;
assign context_valid = delay_line12[0][1] & delay_line12[1][1] & delay_line12[2][1] & delay_line12[3][1] & delay_line12[4][1] &
delay_line22[0][1] & delay_line22[1][1] & delay_line22[2][1] & delay_line22[3][1] & delay_line22[4][1] &
delay_line32[0][1] & delay_line32[1][1] & delay_line32[2][1] & delay_line32[3][1] & delay_line32[4][1] &
delay_line42[0][1] & delay_line42[1][1] & delay_line42[2][1] & delay_line42[3][1] & delay_line42[4][1] &
delay_line52[0][1] & delay_line52[1][1] & delay_line52[2][1] & delay_line52[3][1] & delay_line52[4][1];
wire [2:0] d_dhv;
delay #
(
.N(3),
.DELAY(2)
)
dhv
(
.d(delay_line32[3][2:0]),
.ce(1'b1),
.clk(clk),
.q({d_dhv})
);
assign out_de = d_dhv[2];
assign out_hsync = d_dhv[1];
assign out_vsync = d_dhv[0];
reg median_latch = 0;
always @(posedge clk)
begin
if(context_valid) median_latch <= (sum_final > 5'd12) ? 1'b1 : 1'b0;
end;
assign median = median_latch;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Grig Barbulescu
//
// Create Date: 01/17/2016 04:48:20 PM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// This small sketch demonstrates the division operation on Zybo board.
// This was implemented to use only the PL, but no PS nor ARM.
// The usage is simple:
// - on swithes 3:0 select the upper four bits of dividend, then press&release button 3
// - on swithes 3:0 select the lower four bits of dividend, then press&release button 2
// - on swithes 3:0 select the four bits of divisor, then press&release button 1
// - on LEDs 3:0 will be visible the four bits of the quotient
// - if you push the button 0, on the LEDs will appear the four bits of the remainder
//////////////////////////////////////////////////////////////////////////////////
module top( input clk,
output reg [3:0] led,
input [3:0] btn,
input [3:0] sw );
reg [7:0] A;
reg [3:0] B;
wire [3:0] Q;
wire [3:0] R;
div inst( .clk(clk),
.A(A),
.B(B),
.Q(Q),
.R(R)
);
always @(posedge clk)
begin
if(btn[3]) A[7:4] <= sw[3:0];
if(btn[2]) A[3:0] <= sw[3:0];
if(btn[1]) B[3:0] <= sw[3:0];
if(btn[0]) led[3:0] <= R[3:0];
else led[3:0] <= Q[3:0];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void jizz() { cout << -1 << endl; exit(0); } int s[200005], l[200005], r[200005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> s[i] >> l[i]; r[i] = s[i] + l[i]; l[i] = s[i]; } int nl = -9, nr = 3000006; for (int i = 1; i <= n; ++i) { --nl, ++nr; nl = l[i] = max(l[i], nl); nr = r[i] = min(r[i], nr); if (l[i] > r[i]) jizz(); } nl = -9, nr = 3000006; for (int i = n; i >= 1; --i) { --nl, ++nr; nl = l[i] = max(l[i], nl); nr = r[i] = min(r[i], nr); if (l[i] > r[i]) jizz(); } long long tot = 0; for (int i = 1; i <= n; ++i) { tot += r[i] - s[i]; } cout << tot << endl; for (int i = 1; i <= n; ++i) cout << r[i] << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; int N, M; string s[2020]; long long dp[2020][2020][2], C[2020][2020][2], S[2020][2020][2]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> N >> M; for (int i = 1; i <= N; i++) { cin >> s[i]; s[i] = # + s[i]; } for (int i = N; i >= 1; i--) for (int j = M; j >= 1; j--) { C[i][j][0] = C[i][j + 1][0] + (s[i][j] == R ); C[i][j][1] = C[i + 1][j][1] + (s[i][j] == R ); if (i == N && j == M) { dp[i][j][0] = dp[i][j][1] = 1; } else { int r = M - C[i][j + 1][0]; int d = N - C[i + 1][j][1]; dp[i][j][0] = (S[i][j + 1][0] - S[i][r + 1][0]) % 1000000007; dp[i][j][1] = (S[i + 1][j][1] - S[d + 1][j][1]) % 1000000007; } S[i][j][0] = (S[i][j + 1][0] + dp[i][j][1]) % 1000000007; S[i][j][1] = (S[i + 1][j][1] + dp[i][j][0]) % 1000000007; } long long res = dp[1][1][0] + dp[1][1][1]; if (N == 1 && M == 1) res = 1; res %= 1000000007; res += 1000000007; res %= 1000000007; printf( %lld , res); return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_b.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
input wire port_b_1, // Will create p_mix_sig_1_go port
input wire port_b_3, // Interhierachy link, will create p_mix_sig_3_go
output wire port_b_4, // Interhierachy link, will create p_mix_sig_4_gi
input wire port_b_5_1, // Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
input wire port_b_5_2, // Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
input wire [3:0] port_b_6i, // Conflicting definition
output wire [3:0] port_b_6o, // Conflicting definition
input wire [5:0] sig_07, // Conflicting definition, IN false!
input wire [8:2] sig_08 // VHDL intermediate needed (port name)
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> const int maxn = 10010; const int mod = 1000000007; int n; char ch[4][maxn]; int f[maxn][8][2]; int obs[maxn]; int ot, vt; void part0() { memset(obs, 0, sizeof(obs)); for (int j = 1; j <= n; j++) for (int i = 3; i >= 1; i--) obs[j] = (obs[j] << 1) + ((ch[i][j] != . ) ? 1 : 0); for (int i = 1; i <= 3; i++) for (int j = 1; j <= n; j++) if (ch[i][j] == O ) { ot = j; vt = 1 << (i - 1); } } void init() { scanf( %d , &n); for (int i = 1; i <= 3; i++) scanf( %s , ch[i] + 1); } void solve() { part0(); memset(f, 0, sizeof(f)); f[0][7][0] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j < 8; j++) for (int k = 0; k < 2; k++) { if (!f[i - 1][j][k]) continue; int cnt = j ^ 7; if (cnt & obs[i]) continue; int oc = cnt | obs[i]; for (int c = 0; c <= 6; c += 3) { if (oc & c) continue; int oct = oc | c; if ((i == ot - 1) && (cnt & vt) || (i == ot) && (!(oc ^ vt)) && (vt != 2) || (i - 2 == ot) && (cnt & vt)) { f[i][oct][1] = (f[i][oct][1] + f[i - 1][j][k]) % mod; } else f[i][oct][k] = (f[i][oct][k] + f[i - 1][j][k]) % mod; } } } void print() { printf( %d n , f[n][7][1]); } int main() { init(); solve(); print(); return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always repeat (expression) statement ;
module main ;
reg [3:0] value1,value2,value3;
initial
begin
value1 = 0; // Time 0 assignemnt
value2 = 0;
#6 ;
if(value1 != 4'h1)
begin
$display("FAILED - 3.1.7B always forever (1) ");
value2 = 1;
end
#5 ;
if(value1 != 4'h2)
begin
$display("FAILED - 3.1.7B always forever (2) ");
value2 = 1;
end
#5 ;
if(value1 != 4'h3)
begin
$display("FAILED - 3.1.7B always forever (3) ");
value2 = 1;
end
if(value2 == 0)
$display("PASSED");
$finish;
end
always repeat(3) begin
#5 ;
value1 = value1 + 1;
end
endmodule
|
`timescale 1ns / 1ps
//---------------------------------------------------------------------//
// Name: compute_vex_tb.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Test structure for the compute_vex.v module.
//---------------------------------------------------------------------//
module amer_put_tb;
// Inputs
reg clk;
reg nrst;
reg start_s1;
reg start_s2;
reg [63:0] plus;
reg [63:0] minus;
reg [63:0] K_over_S;
reg [63:0] p_up;
reg [63:0] p_down;
// Outputs
wire [63:0] result;
// Instantiate the Unit Under Test (UUT)
amer_put uut (
.clk(clk),
.nrst(nrst),
.start_s1(start_s1),
.start_s2(start_s2),
.p_up(p_up),
.p_down(p_down),
.log_lambda_up(plus),
.log_lambda_down(minus),
.K_over_S(K_over_S),
.result(result)
);
initial begin
// Initialize Inputs
clk = 0;
nrst = 0;
start_s1 = 0;
start_s2 = 0;
K_over_S <= 64'h3ff0000000000000; // 1
plus <= 64'h3f8030dc4ea03a72;
minus <= 64'hbf8030dc4ea03a72;
p_up <= 64'h3fdfe9e61a77116f;
p_down <= 64'h3fe00af7fa15cd9b;
// plus <= 64'h3f40624dd2f1a9fc; // 5e-4
// minus <= 64'hbf40624dd2f1a9fc; // -5e-4
// p_up <= 64'h3fe0000000000000; // 0.5
// p_down <= 64'h3fe0000000000000; // 0.5
// Wait 100 ns for global reset to finish
#100;
nrst <= 1'b1;
repeat(5)@(posedge clk);
start_s1 <= 1'b1;
repeat(1)@(posedge clk);
start_s1 <= 1'b0;
repeat(8050)@(posedge clk);
//start_s2 <= 1'b1;
//repeat(1)@(posedge clk);
//start_s2 <= 1'b0;
repeat(500000)@(posedge clk);
// repeat(70)@(posedge clk);
end
// Clocking
initial begin
#20
forever clk = #20 ~clk;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_4_V
`define SKY130_FD_SC_HS__SDFRTP_4_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_4 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_4 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_4_V
|
module integration_tb();
reg clk, enable, reset, advance, direction, break, align;
integer i;
wire [3:0] state;
reg [15:0] compare, autoreload;
wire compare_out;
wire [15:0] value;
wire pos, neg, db, tim_commutation_out;
commutation motor1(
.clk(clk),
.enable_i(enable),
.reset_i(reset),
.advance_i(pos),
.direction_i(direction),
.break_i(break),
.align_i(align),
.state_o(state)
);
timer #(.C_WIDTH(16)) tim_commutation(
.clk(clk),
.enable_i(enable),
.reset_i(reset),
.compare_i(compare),
.autoreload_i(autoreload),
.compare_o(tim_commutation_out),
.value_o(value)
);
debouncer #(.DEBOUNCE_COUNT(2)) dut(
.clk_i(clk),
.reset_i(reset),
.pin_i(tim_commutation_out),
.posedge_o(pos),
.negedge_o(neg),
.debounced_o(db)
);
always #1 clk = !clk;
initial begin
$dumpfile("integration.vcd");
$dumpvars(0,integration_tb);
clk = 1'b0; enable = 1'b1; reset = 1'b1; compare = 16'h0008; autoreload = 16'h000F;
#5
enable = 1'b1; reset = 1'b0; advance = 1'b0; direction = 1'b1; break = 1'b0; align = 1'b0;
#1000
$finish;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:60777216 ) using namespace std; int d[10]; int c[107][107]; long long dp[107][17]; long long solve(int len, int pos) { if (pos == 9) { if (len >= d[9]) { return 1; } return 0; } if (dp[len][pos] != -1) { return dp[len][pos]; } dp[len][pos] = 0; if (pos == 0) { for (int j = d[pos]; j <= len; ++j) { dp[len][pos] += solve(len - j, pos + 1) * c[len - 1][j] % 1000000007; if (dp[len][pos] >= 1000000007) dp[len][pos] -= 1000000007; } } else { for (int j = d[pos]; j <= len; ++j) { dp[len][pos] += solve(len - j, pos + 1) * c[len][j] % 1000000007; if (dp[len][pos] >= 1000000007) dp[len][pos] -= 1000000007; } } return dp[len][pos]; } int main() { c[0][0] = 1; c[1][1] = 1; c[1][0] = 1; for (int i = 2; i <= 100; ++i) { c[i][i] = 1; c[i][0] = 1; for (int j = 1; j < i; ++j) { c[i][j] = c[i - 1][j] + c[i - 1][j - 1]; if (c[i][j] >= 1000000007) c[i][j] -= 1000000007; } } long long ans = 0; memset(dp, -1, sizeof(dp)); int len; scanf( %d , &len); for (int i = 0; i < 10; ++i) { scanf( %d , d + i); } for (int i = 1; i <= len; ++i) { ans += solve(i, 0); if (ans >= 1000000007) ans -= 1000000007; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int P = 998244353, N = 3e5; int n, L, C, r[N], A[N], B[N]; int g[N], g0[N], g1[N], g2[N]; int f0[N], f1[N], f2[N]; int q0[N], q1[N]; int t1[N], t2[N], t3[N], t4[N]; inline void Add(int &x, int y) { x += y; if (x >= P) x -= P; } inline int Mul(int x, int y) { return 1ll * x * y % P; } inline int fpow(int x, int k) { int s = 1; for (; k; k >>= 1, x = Mul(x, x)) if (k & 1) s = Mul(s, x); return s; } inline void NTT_prepare(int len) { for (L = 1, C = 0; L < len; L <<= 1, ++C) ; for (int i = 0; i < L; ++i) r[i] = (r[i >> 1] >> 1) | ((i & 1) << (C - 1)); } void NTT(int *A, int op) { for (int i = 0; i < L; ++i) if (i < r[i]) swap(A[i], A[r[i]]); for (int i = 1; i < L; i <<= 1) { int Wn = fpow(3, (P - 1) / (i << 1)); if (op == -1) Wn = fpow(Wn, P - 2); for (int j = 0; j < L; j += i << 1) { int w = 1; for (int k = 0; k < i; ++k, w = Mul(w, Wn)) { int p = A[j + k], q = Mul(w, A[j + i + k]); A[j + k] = (p + q) % P; A[j + i + k] = ((p - q) % P + P) % P; } } } if (op == -1) { int inv_L = fpow(L, P - 2); for (int i = 0; i < L; ++i) A[i] = Mul(A[i], inv_L); } } void Convolve(int *a, int *b, int *C) { for (int i = 0; i < L / 2; ++i) A[i] = a[i]; for (int i = 0; i < L / 2; ++i) B[i] = b[i]; for (int i = L / 2; i < L; ++i) A[i] = B[i] = 0; NTT(A, 1); NTT(B, 1); for (int i = 0; i < L; ++i) C[i] = Mul(A[i], B[i]); NTT(C, -1); } void Solve_1(int l, int r) { if (l == r) { Add(f0[l], g0[l]); Add(f1[l], g1[l]); return; } int mid = (l + r) / 2; Solve_1(l, mid); NTT_prepare(2 * (r - l + 1)); for (int i = 0; i < L; ++i) q0[i] = (i + l <= mid ? f0[i + l] : 0); for (int i = 0; i < L; ++i) q1[i] = (i + l <= mid ? f1[i + l] : 0); Convolve(g0, q0, t1); Convolve(g1, q0, t2); Convolve(g1, q1, t3); Convolve(g2, q1, t4); for (int i = 0; i < L / 2; ++i) { if (mid + 1 <= i + l + 1 && i + l + 1 <= r) { Add(f0[i + l + 1], t1[i]); Add(f1[i + l + 1], t2[i]); } if (mid + 1 <= i + l + 3 && i + l + 3 <= r) { Add(f0[i + l + 3], t3[i]); Add(f1[i + l + 3], t4[i]); } } Solve_1(mid + 1, r); } void Solve_2(int l, int r) { if (l == r) { Add(f2[l], g2[l]); Add(f2[l], l >= 1 ? t1[l - 1] : 0); return; } int mid = (l + r) / 2; Solve_2(l, mid); NTT_prepare(2 * (r - l + 1)); for (int i = 0; i < L; ++i) q0[i] = (i + l <= mid ? f2[i + l] : 0); Convolve(g2, q0, t2); for (int i = 0; i < L / 2; ++i) { if (mid + 1 - 3 <= i + l && i + l <= r - 3) { Add(f2[i + l + 3], t2[i]); } } Solve_2(mid + 1, r); } int main() { scanf( %d , &n); g[0] = 1; g[2] = 1; for (int i = 4; i <= n; i += 2) g[i] = (g[i - 2] + g[i - 4]) % P; for (int i = 0; i <= n; ++i) { g0[i] = Mul(g[i], Mul(i, i)); g1[i] = Mul(g[i], Mul(i + 1, i + 1)); g2[i] = Mul(g[i], Mul(i + 2, i + 2)); } Solve_1(0, n); NTT_prepare(2 * n); Convolve(g1, f1, t1); Solve_2(0, n); int ans = Mul(Mul((g[n - 1] + g[n - 3]) % P, Mul(n - 1, n - 1)), n); for (int i = 2; i <= n - 2; ++i) { Add(ans, Mul(Mul(Mul(g[i - 1], Mul(i - 1, i - 1)), f0[n - i - 1]), i)); Add(ans, Mul(Mul(Mul(g[i - 2], Mul(i - 1, i - 1)), f1[n - i - 2]), Mul(2, i))); if (3 <= i && i <= n - 3) Add(ans, Mul(Mul(Mul(g[i - 3], Mul(i - 1, i - 1)), f2[n - i - 3]), i)); } printf( %d n , ans); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:44:42 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_xlconcat_0/system_microblaze_0_xlconcat_0_stub.v
// Design : system_microblaze_0_xlconcat_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlconcat,Vivado 2016.4" *)
module system_microblaze_0_xlconcat_0(In0, In1, In2, In3, In4, In5, In6, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],In2[0:0],In3[0:0],In4[0:0],In5[0:0],In6[0:0],dout[6:0]" */;
input [0:0]In0;
input [0:0]In1;
input [0:0]In2;
input [0:0]In3;
input [0:0]In4;
input [0:0]In5;
input [0:0]In6;
output [6:0]dout;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altsource_probe_top
#(
parameter lpm_type = "altsource_probe", // required by the coding standard
parameter lpm_hint = "UNUSED", // required by the coding standard
parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned.
parameter sld_instance_index = 0, // unique identifier for the altsource_probe instance.
parameter sld_node_info_parameter = + sld_instance_index, // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl.
parameter sld_ir_width = 4,
parameter instance_id = "UNUSED", // optional name for the instance.
parameter probe_width = 1, // probe port width
parameter source_width= 1, // source port width
parameter source_initial_value = "0", // initial source port value
parameter enable_metastability = "NO" // yes to add two register
)
(
input [probe_width - 1 : 0] probe, // probe inputs
output [source_width - 1 : 0] source, // source outputs
input source_clk, // clock of the registers used to metastabilize the source output
input tri1 source_ena // enable of the registers used to metastabilize the source output
);
altsource_probe #(
.lpm_type(lpm_type),
.lpm_hint(lpm_hint),
.sld_auto_instance_index(sld_auto_instance_index),
.sld_instance_index(sld_instance_index),
.SLD_NODE_INFO(sld_node_info_parameter),
.sld_ir_width(sld_ir_width),
.instance_id(instance_id),
.probe_width(probe_width),
.source_width(source_width),
.source_initial_value(source_initial_value),
.enable_metastability(enable_metastability)
)issp_impl
(
.probe(probe),
.source(source),
.source_clk(source_clk),
.source_ena(source_ena)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_TB_V
/**
* udp_dff$PR_pp$sN: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pr_pp_sn.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 RESET = 1'b1;
#160 SLEEP_B = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 RESET = 1'b0;
#240 SLEEP_B = 1'b0;
#260 SLEEP_B = 1'b1;
#280 RESET = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 SLEEP_B = 1'bx;
#360 RESET = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PR_pp$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_TB_V
|
`timescale 1ns/1ps
`include "global.v"
module fpu_top(clk_in, reset_in, fpuOpCode_in, roundingMode_in, operandA_in, operandB_in, resultReady_out, result_out,
invalidOperation_out, divisionByZero_out, overflow_out, underflow_out, inexact_out);
// I/O PORTS
input clk_in, reset_in;
input [3:0] fpuOpCode_in;
input [1:0] roundingMode_in;
input [31:0] operandA_in, operandB_in;
output resultReady_out;
output [31:0] result_out;
//exception flags
output invalidOperation_out, divisionByZero_out, overflow_out, underflow_out, inexact_out;
// INTERNAL REGISTERS
reg [8:0] expAluResultRegister; //9 bit
reg [31:0] sigAluResultRegister; //31 bit
//WIRES
//input control
wire readFPInput; //mux between integer and floating-point input
wire [31:0] trueInputA;
//SVD output
//to control unit
wire signA, signB, isZeroA, isZeroB, isInfA, isInfB, isNanA, isNanB, isDenormA, isDenormB;
//data
wire [32:0] operandAExpanded, operandBExpanded;
//exp ALU register file
//control
wire erfWriteSelectR0, erfWriteSelectR1;
wire erfWriteEnableR0, erfWriteEnableR1;
wire [2:0] erfReadSelectA, erfReadSelectB;
//data
wire [8:0] erfWriteValueR0, erfWriteValueR1; // 9 bit
wire [8:0] erfReadValueA, erfReadValueB; // 9 bit
//exp ALU connections
//control
wire expAluRegOrSigResult;
wire [2:0] expAluOpCode;
wire errWriteEnable;
//data
wire expAluNegFlag, expAluZeroFlag;
wire [8:0] expAluOpA, expAluOpB;
wire [8:0] expAluResult;
//large ALU register file
//control
wire srfWriteSelectR0, srfWriteSelectR1;
wire srfWriteEnableR0, srfWriteEnableR1;
wire srfShiftEnableR0;
wire [3:0] srfReadSelectA, srfReadSelectB;
//data
wire [31:0] srfWriteValueR0, srfWriteValueR1; // 32 bit
wire [31:0] srfReadValueA, srfReadValueB; // 32 bit
//significand ALU connections
//control
wire sigAluRegOrMul, sigAluSrr, sigAluRegOrExpResult;
wire [3:0] sigAluOpCode;
wire srrWriteEnable, srrShiftEnable;
//data
wire [31:0] sigAluOpA, sigAluOpB, sigAluOpA_tmp;
wire sigAluNegFlag, sigAluZeroFlag;
wire [31:0] sigAluResult;
wire srrShiftIn;
// multiplier chain
//control
wire [1:0] maskAndShiftOp;
wire mulEnable;
wire [1:0] shiftAndExtendOp;
//data
wire [15:0] mulInputMaskedShiftedA, mulInputMaskedShiftedB;
wire [31:0] mulResult;
wire [31:0] mulResultShiftedExtended;
wire stickyBitData;
//output control
wire outputFPResult; //mux between outputting a FP-result or an integer result
wire resultSign;
// ASSIGNMENTS
assign result_out[31:0] = (outputFPResult) ? {resultSign, expAluResultRegister[7:0], sigAluResultRegister[29:7]} :
sigAluResultRegister[31:0];
//mux between input exponent and exp ALU result
assign erfWriteValueR0 = (erfWriteSelectR0 == 1'b0) ? expAluResult : operandAExpanded[31:24];
//mux between input exponent and exp ALU result
assign erfWriteValueR1 = (erfWriteSelectR1 == 1'b0) ? expAluResult : operandBExpanded[31:24];
//connect small register file with the small ALU
assign expAluOpA = erfReadValueA;
assign expAluOpB = (expAluRegOrSigResult == 1'b0) ? erfReadValueB : sigAluResultRegister[8:0];
//mux between integer input and floating-point input
assign trueInputA = (readFPInput) ? {2'b0, operandAExpanded[23:0], 6'b0} : operandA_in[31:0];
//mux between input A and large ALU result
assign srfWriteValueR0 = (srfWriteSelectR0 == 1'b0) ? sigAluResult : trueInputA;
//mux between input B and large ALU result
assign srfWriteValueR1 = (srfWriteSelectR1 == 1'b0) ? sigAluResult : {2'b0, operandBExpanded[23:0], 6'b0};
//connect large register file with the large ALU
assign sigAluOpA_tmp = (sigAluRegOrMul) ? mulResultShiftedExtended : srfReadValueA;
assign sigAluOpA = (sigAluSrr) ? sigAluResultRegister : sigAluOpA_tmp;
assign sigAluOpB = (sigAluRegOrExpResult)? expAluResultRegister : srfReadValueB;
//INSTANTIATIONS
SVDUnit svdUnitA(operandA_in, signA, isZeroA, isInfA, isNanA, isDenormA, operandAExpanded);
SVDUnit svdUnitB(operandB_in, signB, isZeroB, isInfB, isNanB, isDenormB, operandBExpanded);
FpuControlUnit controlUnit(.clk_in(clk_in), .reset_in(reset_in), .fpuOpCode_in(fpuOpCode_in),
.roundingMode_in(roundingMode_in),
.signA_in(signA), .signB_in(signB), .isZeroA_in(isZeroA), .isZeroB_in(isZeroB),
.isInfA_in(isInfA), .isInfB_in(isInfB), .isNanA_in(isNanA), .isNanB_in(isNanB),
.isDenormA_in(isDenormA), .isDenormB_in(isDenormB),
.readFPInput_out(readFPInput),
.expAluNegFlag_in(expAluNegFlag), .expAluZeroFlag_in(expAluZeroFlag),
.sigAluNegFlag_in(sigAluNegFlag), .sigAluZeroFlag_in(sigAluZeroFlag),
.guardBit_in(srfReadValueA[6]), .roundBit_in(srfReadValueA[5]), .stickyBitData_in(stickyBitData),
.erfWriteSelectR0_out(erfWriteSelectR0), .erfWriteSelectR1_out(erfWriteSelectR1),
.erfWriteEnableR0_out(erfWriteEnableR0), .erfWriteEnableR1_out(erfWriteEnableR1),
.erfReadSelectA_out(erfReadSelectA), .erfReadSelectB_out(erfReadSelectB),
.srfWriteSelectR0_out(srfWriteSelectR0), .srfWriteSelectR1_out(srfWriteSelectR1),
.srfWriteEnableR0_out(srfWriteEnableR0), .srfWriteEnableR1_out(srfWriteEnableR1),
.srfShiftEnableR0_out(srfShiftEnableR0), .srfReadSelectA_out(srfReadSelectA),
.srfReadSelectB_out(srfReadSelectB),
.expAluRegOrSigResult_out(expAluRegOrSigResult),
.expAluOp_out(expAluOpCode),
.errWriteEnable_out(errWriteEnable),
.sigAluRegOrMul_out(sigAluRegOrMul), .sigAluSrr_out(sigAluSrr), .sigAluRegOrExpResult_out(sigAluRegOrExpResult),
.sigAluOp_out(sigAluOpCode),
.srrWriteEnable_out(srrWriteEnable),
.srrShiftEnable_out(srrShiftEnable),
.srrShiftIn_out(srrShiftIn),
.maskAndShiftOp_out(maskAndShiftOp),
.mulEnable_out(mulEnable),
.shiftAndExtendOp_out(shiftAndExtendOp),
.outputFPResult_out(outputFPResult),
.resultSign_out(resultSign),
.resultReady_out(resultReady_out),
.invalidOperationDetected_out(invalidOperation_out), .divisionByZeroDetected_out(divisionByZero_out),
.overflowDetected_out(overflow_out), .underflowDetected_out(underflow_out), .inexactDetected_out(inexact_out)
);
ExpRegisterFile expRegisterFile(clk_in, reset_in, erfWriteEnableR0, erfWriteEnableR1, erfWriteValueR0, erfWriteValueR1,
erfReadSelectA, erfReadSelectB, erfReadValueA, erfReadValueB);
ExponentALU expALU(expAluOpCode, expAluOpA, expAluOpB, expAluNegFlag, expAluZeroFlag, expAluResult);
SigRegisterFile sigRegisterFile(clk_in, reset_in, srfWriteEnableR0, srfWriteEnableR1, srfWriteValueR0, srfWriteValueR1,
srfShiftEnableR0, srfReadSelectA, srfReadSelectB, srfReadValueA, srfReadValueB);
SignificandALU sigALU(sigAluOpCode, sigAluOpA, sigAluOpB, sigAluNegFlag, sigAluZeroFlag, sigAluResult);
//MULTIPLIER CHAIN
MaskAndShift maskAndShift(maskAndShiftOp, operandAExpanded[23:0], operandBExpanded[23:0],
mulInputMaskedShiftedA, mulInputMaskedShiftedB);
ExternalMul16x16 externalMul(clk_in, reset_in, mulEnable, mulInputMaskedShiftedA,
mulInputMaskedShiftedB, mulResult);
ShiftAndExtend shiftAndExtend(shiftAndExtendOp, mulResult, mulResultShiftedExtended, stickyBitData);
// SYNCHRONOUS BLOCK - <TODO: replace with register modules?>
always @(posedge clk_in) begin
if (reset_in) begin
expAluResultRegister = 0;
sigAluResultRegister = 0;
end else begin
//update exponent result register
if (errWriteEnable) expAluResultRegister = expAluResult;
//update significand result register
if (srrShiftEnable)
sigAluResultRegister = {sigAluResultRegister[30:0], srrShiftIn}; //shift a bit into SRR
else begin
if (srrWriteEnable) sigAluResultRegister = sigAluResult; //write ALU result into SRR
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:59:16 05/22/2016
// Design Name:
// Module Name: Deteccion_Tecla
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Deteccion_Tecla(
input clk,
input reset,
input ps2d,
input ps2c,
input reset_escritura,
input [7:0] Segundos_RTC,
input [7:0] Minutos_RTC,
input [7:0] Horas_RTC,
output [7:0] Senal,
output Senal_2_ren,
output [7:0] Parametro,
output [7:0] Salida_1,
output [7:0] Salida_2,
output [7:0] Salida_3,
output [7:0] VGA_1,
output [7:0] VGA_2,
output [7:0] VGA_3,
output Flag_VGA,
output [7:0] Flag_Pico,
output [7:0] Salida_G
);
wire rx_done_tick;
wire [7:0] dout;
wire [7:0] Salida;
wire [1:0] Cuenta_ID;
wire [5:0] Cuenta_Segundos;
wire [5:0] Cuenta_Minutos;
wire [4:0] Cuenta_Horas;
wire [4:0] Cuenta_Year;
wire [3:0] Cuenta_Mes;
wire [6:0] Cuenta_Dia;
wire [7:0] Segundos_R;
wire [7:0] Minutos_R;
wire [7:0] Horas_R;
wire [7:0] Salida_Guardar;
wire [7:0] Salida_Estado_Cronometro;
wire reset_crono;
wire Salida_Reset;
assign Parametro = Salida;
assign Salida_G = Salida_Guardar;
ps2_rx F1 (
.clk(clk),
.reset(reset),
.ps2d(ps2d),
.ps2c(ps2c),
.rx_en(1'b1),
.rx_done_tick(rx_done_tick),
.dout(dout)
);
kb_code F2 (
.clk(clk),
.reset(reset),
.scan_done_tick(rx_done_tick),
.scan_out(dout),
.got_code_tick(got_code_tick)
);
Contador_ID F3 (
.rst(reset),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_ID)
);
Contador_AD_Segundos F4 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Segundos)
);
Contador_AD_Minutos F5 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Minutos)
);
Contador_AD_Horas F6 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Horas)
);
Contador_AD_Year F7(
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Year)
);
Contador_AD_Mes F8(
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Mes)
);
Contador_AD_Dia F9 (
.estado (Salida),
.rst(reset),
.en(Cuenta_ID),
.Cambio(dout),
.got_data(got_code_tick),
.clk(clk),
.Cuenta(Cuenta_Dia)
);
Registro F10 (
.clk(clk),
.reset(reset),
.en(got_code_tick),
.codigo(dout),
.Salida(Salida)
);
MUX F11 (
.clk(clk),
.Estado(Salida),
.Cuenta_Segundos(Cuenta_Segundos),
.Cuenta_Minutos(Cuenta_Minutos),
.Cuenta_Horas(Cuenta_Horas),
.Cuenta_Year(Cuenta_Year),
.Cuenta_Mes(Cuenta_Mes),
.Cuenta_Dia(Cuenta_Dia),
.Salida_1(Salida_1),
.Salida_2(Salida_2),
.Salida_3(Salida_3)
);
Senal_Escritura F12 (
.Tecla(dout),
.got_data (got_code_tick),
.reset_escritura (reset_escritura),
.clk(clk),
.Senal(Senal)
);
Control_de_modo F13 (
.Tecla(dout),
.reset_escritura(Senal),
.clk(clk),
.got_data(got_code_tick),
.Senal(Senal_2_ren)
);
Decodificador_VGA F14 (
.clk(clk),
.Contador_1(Salida_1),
.Contador_2(Salida_2),
.Contador_3(Salida_3),
.VGA_1(VGA_1),
.VGA_2(VGA_2),
.VGA_3(VGA_3)
);
Registro_Contadores_Cronometro F15(
.clk(clk),
.Segundos(VGA_1),
.Minutos(VGA_2),
.Horas(VGA_3),
.Tecla(Salida_Estado_Cronometro),
.Segundos_R(Segundos_R),
.Minutos_R(Minutos_R),
.Horas_R(Horas_R)
);
Registro_Guardar F16 (
.Tecla(dout),
.clk(clk),
.reset(reset),
.Salida_Guardar(Salida_Guardar)
);
Registro_Estado_Cronometro F17 (
.Tecla(dout),
.clk(clk),
.reset(Salida_Reset),
.Salida_Estado_Cronometro(Salida_Estado_Cronometro)
);
Banderas_Alarma F18 (
.Segundos(Segundos_R),
.Minutos(Minutos_R),
.Horas(Horas_R),
.Segundos_RTC(Segundos_RTC),
.Minutos_RTC(Minutos_RTC),
.Horas_RTC(Horas_RTC),
.Estado(Salida_Estado_Cronometro),
.Guardar(Salida_Guardar),
.clk(clk),
.reset(reset),
.Flag_Pico(Flag_Pico)
);
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Amber 2 Core top-Level module //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Instantiates the core consisting of fetch, instruction //
// decode, execute, and co-processor. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_core
(
input i_clk,
input i_rst,
output [31:0] o_m_address, //data memory
output [31:0] o_m_write,
output o_m_write_en,
output [3:0] o_m_byte_enable,
input [31:0] i_m_read,
output terminate
);
wire [31:0] execute_address;
wire [31:0] execute_address_nxt; // un-registered version of execute_address to the cache rams
wire [31:0] write_data;
wire write_enable;
wire [31:0] read_data;
wire [3:0] byte_enable;
wire status_bits_flags_wen;
wire [31:0] imm32;
wire [4:0] imm_shift_amount;
wire [3:0] condition;
wire [31:0] read_data_s2;
wire [4:0] read_data_alignment;
wire [3:0] rm_sel;
wire [3:0] rds_sel;
wire [3:0] rn_sel;
wire [3:0] rm_sel_nxt;
wire [3:0] rds_sel_nxt;
wire [3:0] rn_sel_nxt;
wire [1:0] barrel_shift_amount_sel;
wire [1:0] barrel_shift_data_sel;
wire [1:0] barrel_shift_function;
wire use_carry_in;
wire [8:0] alu_function;
wire [1:0] multiply_function;
wire [3:0] address_sel;
wire [1:0] pc_sel;
wire [1:0] byte_enable_sel;
wire [2:0] status_bits_sel;
wire [2:0] reg_write_sel;
wire write_data_wen;
wire pc_wen;
wire [14:0] reg_bank_wen;
wire multiply_done;
assign terminate = ({execute_address[31:2], 2'd0} == 32'h00000018) && (execute_address_nxt == 32'h0000001c);
a23_fetch u_fetch (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_address ( {execute_address[31:2], 2'd0} ),
.i_address_nxt ( execute_address_nxt ),
.i_write_data ( write_data ),
.i_write_enable ( write_enable ),
.o_read_data ( read_data ),
.i_byte_enable ( byte_enable ),
.i_cache_enable ( 1'b0 ),
.i_cache_flush ( 1'b0 ),
.i_cacheable_area ( 32'b0 ),
.o_m_address ( o_m_address ),
.o_m_write ( o_m_write ),
.o_m_write_en ( o_m_write_en ),
.o_m_byte_enable ( o_m_byte_enable ),
.i_m_read ( i_m_read )
);
a23_decode u_decode (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
// Instruction fetch or data read signals
.i_read_data ( read_data ),
.i_execute_address ( execute_address ),
.o_read_data ( read_data_s2 ),
.o_read_data_alignment ( read_data_alignment ),
.i_multiply_done ( multiply_done ),
.o_imm32 ( imm32 ),
.o_imm_shift_amount ( imm_shift_amount ),
.o_condition ( condition ),
.o_rm_sel ( rm_sel ),
.o_rds_sel ( rds_sel ),
.o_rn_sel ( rn_sel ),
.o_rm_sel_nxt ( rm_sel_nxt ),
.o_rds_sel_nxt ( rds_sel_nxt ),
.o_rn_sel_nxt ( rn_sel_nxt ),
.o_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
.o_barrel_shift_data_sel ( barrel_shift_data_sel ),
.o_barrel_shift_function ( barrel_shift_function ),
.o_use_carry_in ( use_carry_in ),
.o_alu_function ( alu_function ),
.o_multiply_function ( multiply_function ),
.o_address_sel ( address_sel ),
.o_pc_sel ( pc_sel ),
.o_byte_enable_sel ( byte_enable_sel ),
.o_status_bits_sel ( status_bits_sel ),
.o_reg_write_sel ( reg_write_sel ),
.o_write_data_wen ( write_data_wen ),
.o_pc_wen ( pc_wen ),
.o_reg_bank_wen ( reg_bank_wen ),
.o_status_bits_flags_wen ( status_bits_flags_wen )
);
a23_execute u_execute (
.i_clk ( i_clk ),
.i_rst ( i_rst ),
.i_read_data ( read_data_s2 ),
.i_read_data_alignment ( read_data_alignment ),
.o_write_data ( write_data ),
.o_address ( execute_address ),
.o_address_nxt ( execute_address_nxt ),
.o_byte_enable ( byte_enable ),
.o_write_enable ( write_enable ),
.o_multiply_done ( multiply_done ),
.i_imm32 ( imm32 ),
.i_imm_shift_amount ( imm_shift_amount ),
.i_condition ( condition ),
.i_rm_sel ( rm_sel ),
.i_rds_sel ( rds_sel ),
.i_rn_sel ( rn_sel ),
.i_rm_sel_nxt ( rm_sel_nxt ),
.i_rds_sel_nxt ( rds_sel_nxt ),
.i_rn_sel_nxt ( rn_sel_nxt ),
.i_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
.i_barrel_shift_data_sel ( barrel_shift_data_sel ),
.i_barrel_shift_function ( barrel_shift_function ),
.i_use_carry_in ( use_carry_in ),
.i_alu_function ( alu_function ),
.i_multiply_function ( multiply_function ),
.i_address_sel ( address_sel ),
.i_pc_sel ( pc_sel ),
.i_byte_enable_sel ( byte_enable_sel ),
.i_status_bits_sel ( status_bits_sel ),
.i_reg_write_sel ( reg_write_sel ),
.i_write_data_wen ( write_data_wen ),
.i_pc_wen ( pc_wen ),
.i_reg_bank_wen ( reg_bank_wen ),
.i_status_bits_flags_wen ( status_bits_flags_wen )
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module amm_master_qsys_with_pcie_video_rgb_resampler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 23;
parameter ODW = 29;
parameter IEW = 1;
parameter OEW = 1;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = ALPHA;
assign converted_data[29:20] = r[ 9: 0];
assign converted_data[19:10] = g[ 9: 0];
assign converted_data[ 9: 0] = b[ 9: 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; map<int, int> cnt, b; vector<int> ans; int a[200010], x; int n, m, p; int main() { cin >> n >> m >> p; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) { cin >> x; b[x]++; } for (int i = 0; i < p; i++) { if (i + (long long)(m - 1) * p >= n) break; long long j; cnt = b; for (j = i; j <= i + (long long)(m - 1) * p; j += p) if (--cnt[a[j]] == 0) cnt.erase(a[j]); if (cnt.size() == 0) ans.push_back(i + 1); for (long long k = i; j < n; j += p, k += p) { if (--cnt[a[j]] == 0) cnt.erase(a[j]); if (++cnt[a[k]] == 0) cnt.erase(a[k]); if (cnt.size() == 0) ans.push_back(k + p + 1); } } sort(ans.begin(), ans.end()); cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9434_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 1:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int maxt[5210][5210]; int a[5210][5210]; char str[5210]; int getn(char ch) { if (ch >= 0 && ch <= 9 ) { return ch - 0 ; } else { return 10 + ch - A ; } } int main() { scanf( %d , &n); memset(maxt, 0, sizeof(maxt)); for (int i = 1; i <= n; i++) { scanf( %s , str + 1); int In = 0, len = strlen(str + 1); for (int j = len; j >= 1; j--) { int N = getn(str[j]); int Jn = 0; while (N) { a[i][n - In - Jn] = N % 2; N /= 2; Jn++; } for (; Jn < 4; Jn++) { if (n - In - Jn == 0) { break; } a[i][n - In - Jn] = 0; } In += Jn; } for (int j = n - In; j >= 1; j--) { a[i][j] = 0; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { maxt[i][j] = a[i][j] + maxt[i - 1][j] + maxt[i][j - 1] - maxt[i - 1][j - 1]; } } for (int I = n; I >= 1; I--) { if (n % I == 0) { int flag = 1; for (int i = 1; i <= (n / I); i++) { for (int j = 1; j <= (n / I); j++) { int cnt = maxt[i * I][j * I] - maxt[(i - 1) * I][j * I] - maxt[i * I][(j - 1) * I] + maxt[(i - 1) * I][(j - 1) * I]; if (cnt != I * I * a[i * I][j * I]) { flag = 0; break; } } if (!flag) { break; } } if (flag) { printf( %d n , I); break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b; long long p(1); cin >> a >> b; while (b--) p = (p << 1ll) % 1000000009ll; long long ans(1); while (a--) { p--; if (p < 0) p += 1000000009ll; ans *= p; ans %= 1000000009ll; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; map<pair<int, int>, int> M; set<pair<int, int> > tmp; char s[77777][11]; int main() { int n; scanf( %d , &n); for (int ii = 0; ii < n; ii++) { scanf( %s , s[ii]); for (int i = 0; i < 9; i++) { for (int j = i; j < 9; j++) { int ans = 0; for (int k = i; k <= j; k++) ans = ans * 10 + s[ii][k] - 0 ; tmp.insert(make_pair(j - i + 1, ans)); } } for (set<pair<int, int> >::iterator it = tmp.begin(); it != tmp.end(); it++) { M[*it]++; } tmp.clear(); } for (int ii = 0; ii < n; ii++) { int di, dj, res = 10; for (int i = 0; i < 9; i++) { for (int j = i; j < 9; j++) { int ans = 0; for (int k = i; k <= j; k++) ans = ans * 10 + s[ii][k] - 0 ; if (M[make_pair(j - i + 1, ans)] == 1 && res > j - i + 1) { res = j - i + 1; di = i, dj = j; } } } for (int k = di; k <= dj; k++) putchar(s[ii][k]); puts( ); } } |
`timescale 1ns / 1ps
module HighPassFilter(clk, new_sample, input_sample, output_sample);
input clk;
input new_sample;
reg enable_systolic;
wire clk_systolic;
input [15:0] input_sample;
output [15:0] output_sample;
reg [2:0] state;
localparam IDLE = 3'd0,
CLK_A = 3'd1,
CLK_B = 3'd2,
CLK_C = 3'd3,
CLK_D = 3'd4;
initial begin
state <= IDLE;
enable_systolic <= 1'b0;
end
always @ (posedge clk) begin
case(state)
IDLE: begin
if(new_sample)
state <= CLK_A;
else
state <= IDLE;
end
CLK_A: begin
enable_systolic <= 1'b1;
state <= CLK_B;
end
CLK_B: begin
enable_systolic <= 1'b1;
state <= CLK_C;
end
CLK_C: begin
enable_systolic <= 1'b0;
state <= IDLE;
end
endcase
end
localparam NUM_COEFFS = 99; // 57
localparam BITS_COEFF = 8;
localparam NUM_COEFFS_BITS = NUM_COEFFS * BITS_COEFF;
/*
// Simulator coefficients
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
8'sd1,
8'sd1,
8'sd1,
-8'sd1
};
*/
/*
// High pass coefficients
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd1,
8'sd0,
8'sd0,
-8'sd1,
-8'sd1,
-8'sd2,
-8'sd1,
8'sd0,
8'sd2,
8'sd4,
8'sd4,
8'sd3,
8'sd0,
-8'sd6,
-8'sd12,
-8'sd19,
-8'sd24,
8'sd102,
-8'sd24,
-8'sd19,
-8'sd12,
-8'sd6,
8'sd0,
8'sd3,
8'sd4,
8'sd4,
8'sd2,
8'sd0,
-8'sd1,
-8'sd2,
-8'sd1,
-8'sd1,
8'sd0,
8'sd0,
8'sd1,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0
};
*/
// High pass, 6000 Hz stop frequency, 60 dB attenuate, 48 khz sampling freq, multiplier: 113
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
-8'sd1,
8'sd0,
8'sd0,
8'sd1,
8'sd1,
8'sd1,
8'sd0,
-8'sd1,
-8'sd1,
-8'sd1,
8'sd0,
8'sd1,
8'sd2,
8'sd2,
8'sd0,
-8'sd2,
-8'sd3,
-8'sd3,
8'sd0,
8'sd3,
8'sd6,
8'sd5,
8'sd0,
-8'sd8,
-8'sd18,
-8'sd25,
8'sd85,
-8'sd25,
-8'sd18,
-8'sd8,
8'sd0,
8'sd5,
8'sd6,
8'sd3,
8'sd0,
-8'sd3,
-8'sd3,
-8'sd2,
8'sd0,
8'sd2,
8'sd2,
8'sd1,
8'sd0,
-8'sd1,
-8'sd1,
-8'sd1,
8'sd0,
8'sd1,
8'sd1,
8'sd1,
8'sd0,
8'sd0,
-8'sd1,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0,
8'sd0
};
wire [31:0] a_out [0:NUM_COEFFS];
wire [31:0] b_out [0:NUM_COEFFS];
genvar j;
generate
for(j = 0; j < NUM_COEFFS; j = j+1) begin: GEN
processingUnit #(COEFFS[NUM_COEFFS_BITS-1-(j*BITS_COEFF):NUM_COEFFS_BITS-(j*BITS_COEFF)-BITS_COEFF]) gen_proc(
.clk(clk),
.a_in(a_out[j]),
.a_out(a_out[j+1]),
.b_out(b_out[j]),
.b_in(b_out[j+1]),
.enable(enable_systolic)
);
end
endgenerate
assign a_out[0] = {{16{input_sample[15]}}, input_sample}; // sign extend to 32 bits
assign b_out[NUM_COEFFS] = 32'h0;
assign output_sample = b_out[0][23:7]; // divide by 128
endmodule
/*
processingUnit #(1) p00 (clk, systolic_input, a_out[0], systolic_output, b_out[17], enable_systolic);
processingUnit #(3) p01 (clk, a_out[0], a_out[1], b_out[17], b_out[16], enable_systolic);
processingUnit #(5) p02 (clk, a_out[1], a_out[2], b_out[16], b_out[15], enable_systolic);
processingUnit #(7) p03 (clk, a_out[2], a_out[3], b_out[15], b_out[14], enable_systolic);
processingUnit #(11)p04 (clk, a_out[3], a_out[4], b_out[14], b_out[13], enable_systolic);
processingUnit #(13)p05 (clk, a_out[4], a_out[5], b_out[13], b_out[12], enable_systolic);
processingUnit #(16)p06 (clk, a_out[5], a_out[6], b_out[12], b_out[11], enable_systolic);
processingUnit #(19)p07 (clk, a_out[6], a_out[7], b_out[11], b_out[10], enable_systolic);
processingUnit #(20)p08 (clk, a_out[7], a_out[8], b_out[10], b_out[9], enable_systolic);
processingUnit #(21)p09 (clk, a_out[8], a_out[9], b_out[9], b_out[8], enable_systolic);
processingUnit #(20)p10 (clk, a_out[9], a_out[10], b_out[8], b_out[7], enable_systolic);
processingUnit #(19)p11 (clk, a_out[10], a_out[11], b_out[7], b_out[6], enable_systolic);
processingUnit #(16)p12 (clk, a_out[11], a_out[12], b_out[6], b_out[5], enable_systolic);
processingUnit #(13)p13 (clk, a_out[12], a_out[13], b_out[5], b_out[4], enable_systolic);
processingUnit #(11)p14 (clk, a_out[13], a_out[14], b_out[4], b_out[3], enable_systolic);
processingUnit #(7) p15 (clk, a_out[14], a_out[15], b_out[3], b_out[2], enable_systolic);
processingUnit #(5) p16 (clk, a_out[15], a_out[16], b_out[2], b_out[1], enable_systolic);
processingUnit #(3) p17 (clk, a_out[16], a_out[17], b_out[1], b_out[0], enable_systolic);
processingUnit #(1) p18 (clk, a_out[17], , b_out[0], 32'h0, enable_systolic);*/
|
/*
This file is part of avgai.
avgai is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
avgai is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with avgai. If not, see <http://www.gnu.org/licenses/>.
Copyright Dakota Fisher 2014
*/
module debounce(input clk, but, output reg debounced);
reg [9:0] debTimer;
always @(posedge clk) begin
if (debounced == but)
debTimer <= 0;
else if (debTimer != -10'b1)
debTimer <= debTimer+1;
else if (debTimer == -10'b1)
debounced <= but;
end
endmodule
module clkDiv(input clk, output divClk);
parameter n = 25;
reg [n-1:0] count = 0;
assign divClk = count[n-1];
always @(posedge clk)
count <= count + 1;
endmodule
|
module TestStateEncoder();
//Inputs to encoder
reg clk, enable;
//reg [6:0] state;
reg [13:0] state;
//Encoder output.
wire out;
defparam e.STATE_LENGTH=4'b1110;
stateEncoder e(clk, state, enable, out);
initial begin
$dumpfile ("TestStateEncoderTestbench.vcd");
$dumpvars;
end
initial begin
$display("\tTime\tState\tEnable\tOutput");
$monitor("\t%d\t%b\t%b\t%b",$time, state,enable,out);
end
//Simulation block
initial begin
#0
//state=7'b1100110; //State
state=14'b11001100000; //State
clk=1'b1; //Start clock high so first inversion is a falling edge.
#10 //Wait 5 clock positive edges.
enable = 1'b1; //Trigger enable.
$display("Enable triggered.");
#6 enable = 1'b0;
#6 enable = 1'b1; //Output will not be done - check to make sure that this enable state going high does not change output.
$display("Enable triggered.");
#6 enable = 1'b0; //Reset enable.
#50 //Wait, change state, and then trigger enable.
//state=7'b0011001;
state=14'b00110010000;
#10
enable = 1'b1;
$display("Enable triggered.");
#10 enable=1'b0;
#50 $finish; //End simulation
end
//Make clock
always begin
#1
clk=~clk; //Invert clock
end
endmodule
|
`default_nettype none
// ============================================================================
module message_formatter #
(
parameter WIDTH = 24, // Word length in bits. MUST be a multiply of 4
parameter COUNT = 2, // Word count
parameter TX_INTERVAL = 4 // Character transmission interval
)
(
// Clock and reset
input wire CLK,
input wire RST,
// Data input
input wire I_STB,
input wire [(WIDTH*COUNT)-1:0] I_DAT,
// ASCII output
output wire O_STB,
output wire [7:0] O_DAT
);
// ============================================================================
// Total input data word width
localparam TOTAL_WIDTH = WIDTH * COUNT;
// ============================================================================
// FSM states
integer fsm;
localparam FSM_IDLE = 'h00;
localparam FSM_TX_HEX = 'h11;
localparam FSM_TX_CR = 'h21;
localparam FSM_TX_LF = 'h22;
localparam FSM_TX_SEP = 'h31;
// ============================================================================
// TX interval counter
reg [24:0] tx_dly_cnt;
reg tx_req;
wire tx_rdy;
always @(posedge CLK)
if (RST)
tx_dly_cnt <= -1;
else if (!tx_rdy)
tx_dly_cnt <= tx_dly_cnt - 1;
else if ( tx_rdy && tx_req)
tx_dly_cnt <= TX_INTERVAL - 2;
assign tx_rdy = tx_dly_cnt[24];
always @(posedge CLK)
if (RST)
tx_req <= 1'b0;
else case (fsm)
FSM_TX_HEX: tx_req <= 1'b1;
FSM_TX_SEP: tx_req <= 1'b1;
FSM_TX_CR: tx_req <= 1'b1;
FSM_TX_LF: tx_req <= 1'b1;
default: tx_req <= 1'b0;
endcase
// ============================================================================
// Word and char counter
reg [7:0] char_cnt;
reg [7:0] word_cnt;
always @(posedge CLK)
if (fsm == FSM_IDLE || fsm == FSM_TX_SEP)
char_cnt <= (WIDTH/4) - 1;
else if (tx_rdy && fsm == FSM_TX_HEX)
char_cnt <= char_cnt - 1;
always @(posedge CLK)
if (fsm == FSM_IDLE)
word_cnt <= COUNT - 1;
else if (tx_rdy && fsm == FSM_TX_SEP)
word_cnt <= word_cnt - 1;
// ============================================================================
// Data shift register
reg [TOTAL_WIDTH-1:0] sr_reg;
wire [3:0] sr_dat;
always @(posedge CLK)
if (fsm == FSM_IDLE && I_STB)
sr_reg <= I_DAT;
else if (fsm == FSM_TX_HEX && tx_rdy)
sr_reg <= sr_reg << 4;
assign sr_dat = sr_reg[TOTAL_WIDTH-1:TOTAL_WIDTH-4];
// ============================================================================
// Control FSM
always @(posedge CLK)
if (RST)
fsm <= FSM_IDLE;
else case (fsm)
FSM_IDLE: if (I_STB) fsm <= FSM_TX_HEX;
FSM_TX_HEX:
if (tx_rdy && (char_cnt == 0) && (word_cnt == 0))
fsm <= FSM_TX_CR;
else if (tx_rdy && (char_cnt == 0)) fsm <= FSM_TX_SEP;
else if (tx_rdy && (char_cnt != 0)) fsm <= FSM_TX_HEX;
FSM_TX_SEP: if (tx_rdy) fsm <= FSM_TX_HEX;
FSM_TX_CR: if (tx_rdy) fsm <= FSM_TX_LF;
FSM_TX_LF: if (tx_rdy) fsm <= FSM_IDLE;
endcase
// ============================================================================
// Data to ASCII converter
reg o_stb;
reg [7:0] o_dat;
always @(posedge CLK or posedge RST)
if (RST)
o_stb <= 1'd0;
else
o_stb <= tx_req & tx_rdy;
always @(posedge CLK)
if (fsm == FSM_TX_CR)
o_dat <= 8'h0D;
else if (fsm == FSM_TX_LF)
o_dat <= 8'h0A;
else if (fsm == FSM_TX_SEP)
o_dat <= "_";
else if (fsm == FSM_TX_HEX) case (sr_dat)
4'h0: o_dat <= "0";
4'h1: o_dat <= "1";
4'h2: o_dat <= "2";
4'h3: o_dat <= "3";
4'h4: o_dat <= "4";
4'h5: o_dat <= "5";
4'h6: o_dat <= "6";
4'h7: o_dat <= "7";
4'h8: o_dat <= "8";
4'h9: o_dat <= "9";
4'hA: o_dat <= "A";
4'hB: o_dat <= "B";
4'hC: o_dat <= "C";
4'hD: o_dat <= "D";
4'hE: o_dat <= "E";
4'hF: o_dat <= "F";
endcase
assign O_STB = o_stb;
assign O_DAT = o_dat;
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module test_sdspi (
input clk_50_,
input sw0_,
output reg [7:0] ledg_,
// SD card signals
output sd_sclk_,
input sd_miso_,
output sd_mosi_,
output sd_ss_
);
// Registers and nets
wire clk;
wire sys_clk;
reg [1:0] clk_div;
wire lock;
wire rst;
reg [8:0] dat_i;
wire [7:0] dat_o;
reg we;
reg [1:0] sel;
reg stb;
wire ack;
reg [7:0] st;
reg [7:0] cnt;
// Module instantiations
pll pll (
.inclk0 (clk_50_),
.c2 (sys_clk),
.locked (lock)
);
sdspi sdspi (
// Serial pad signal
.sclk (sd_sclk_),
.miso (sd_miso_),
.mosi (sd_mosi_),
.ss (sd_ss_),
// Wishbone slave interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (stb),
.wb_cyc_i (stb),
.wb_ack_o (ack)
);
// Continuous assignments
assign clk = clk_div[1];
assign rst = sw0_ | !lock;
// Behaviour
always @(posedge clk)
if (rst)
begin
dat_i <= 9'h0;
we <= 1'b0;
sel <= 2'b00;
stb <= 1'b0;
st <= 8'h0;
cnt <= 8'd90;
end
else
case (st)
8'h0:
begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h1;
end
8'h1:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= (cnt==8'd0) ? 8'h2 : 8'h1;
cnt <= cnt - 8'd1;
end
8'h2:
if (ack) begin
dat_i <= 9'h0ff;
we <= 1'b1;
sel <= 2'b11;
stb <= 1'b1;
st <= 8'h3;
end
8'h3:
if (ack) begin
dat_i <= 9'h40;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h4;
end
8'h4:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h5;
end
8'h5:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h6;
end
8'h6:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h7;
end
8'h7:
if (ack) begin
dat_i <= 9'h00;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h8;
end
8'h8:
if (ack) begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h49;
end
8'h49:
if (ack) begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= 8'h50;
cnt <= 8'd4;
end
8'h50:
begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= (cnt==8'd0) ? 8'h9 : 8'h50;
cnt <= cnt - 8'd1;
end
8'h9:
begin
dat_i <= 9'hff;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'h52;
end
8'h52:
if (ack) begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= 8'h53;
cnt <= 8'd7;
end
8'h53:
begin
dat_i <= 9'h95;
we <= 1'b1;
sel <= 2'b01;
stb <= 1'b0;
st <= (cnt==8'd0) ? 8'd10 : 8'h53;
cnt <= cnt - 8'd1;
end
8'd10:
begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd11;
end
8'd11:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd12;
end
8'd12:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd13;
end
8'd13:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd14;
end
8'd14:
if (ack) begin
dat_i <= 9'hff;
we <= 1'b0;
sel <= 2'b01;
stb <= 1'b1;
st <= 8'd15;
end
endcase
/*
always #5 clk <= !clk;
initial
begin
clk <= 1'b0;
rst <= 1'b1;
miso <= 1'b1;
#100 rst <= 1'b0;
#935 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b0;
#10 miso <= 1'b1;
end
*/
// clk_div
always @(posedge sys_clk) clk_div <= clk_div + 2'd1;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:22 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_stub.v
// Design : zynq_design_1_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module zynq_design_1_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_in2_gt_in1_2b.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Two bit comparison of two inputs that can have any value.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_in2_gt_in1_2b (
din1,
din2,
din2_neq_din1,
din2_gt_din1
);
input [1:0] din1; // input 1- 3 bits
input [1:0] din2; // input 2- 3 bits
output din2_neq_din1; // input 2 doesn't equal input 1
output din2_gt_din1; // input 2 is greater than input 1
wire [1:0] din2_eq_din1;
wire din2_neq_din1;
wire din2_gt_din1;
assign din2_eq_din1[1:0]= (~(din1 ^ din2));
assign din2_neq_din1= (!(&din2_eq_din1));
assign din2_gt_din1= ((!din1[1]) && din2[1])
|| (din2_eq_din1[1] && (!din1[0]) && din2[0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e6; long long n, K, d, a[200010]; map<long long, long long> mp; struct trnode { long long lc, rc, c, u; } tr[400010]; long long tot = 0; void pushdown(long long x) { long long lc = tr[x].lc, rc = tr[x].rc, c = tr[x].u; tr[x].u = 0; tr[lc].c += c; tr[rc].c += c; tr[lc].u += c; tr[rc].u += c; } void change(long long x, long long l, long long r, long long fl, long long fr, long long c, long long op) { if (l == fl && r == fr) { if (op) tr[x].c = c; else tr[x].c += c, tr[x].u += c; return; } long long mid = (l + r) / 2; if (tr[x].u) pushdown(x); if (fr <= mid) change(tr[x].lc, l, mid, fl, fr, c, op); else if (fl > mid) change(tr[x].rc, mid + 1, r, fl, fr, c, op); else change(tr[x].lc, l, mid, fl, mid, c, op), change(tr[x].rc, mid + 1, r, mid + 1, fr, c, op); tr[x].c = min(tr[tr[x].lc].c, tr[tr[x].rc].c); } long long bt(long long l, long long r) { long long x = ++tot; tr[x].c = inf; if (l != r) { long long mid = (l + r) / 2; tr[x].lc = bt(l, mid); tr[x].rc = bt(mid + 1, r); } return x; } long long findans(long long x, long long l, long long r) { if (l == r) return tr[x].c <= K ? l : inf; if (tr[x].u) pushdown(x); long long mid = (l + r) / 2; if (tr[tr[x].lc].c <= K) return findans(tr[x].lc, l, mid); return findans(tr[x].rc, mid + 1, r); } long long L = 1, R = 1, s1[200010], s2[200010], t1 = 0, t2 = 0, la = 1; int main() { scanf( %lld %lld %lld , &n, &K, &d); for (long long i = 1; i <= n; i++) scanf( %lld , &a[i]); if (d == 0) { L = 1; R = 1; long long l = 1, r = 1; for (int i = 2; i <= n; i++) { r = i; if (a[i] != a[i - 1]) l = i; if (r - l + 1 > R - L + 1) L = l, R = r; } printf( %lld %lld , L, R); return 0; } bt(1, n); change(1, 1, n, 1, 1, 0, 1); s1[++t1] = 1; s2[++t2] = 1; mp[a[1]] = 1; for (long long i = 2; i <= n; i++) { long long tmp = la; tmp = max(tmp, mp[a[i]] + 1); if ((a[i] - a[i - 1]) % d != 0) tmp = i; mp[a[i]] = i; if (la < tmp) change(1, 1, n, la, tmp - 1, inf, 0), la = tmp; while (t1 && a[s1[t1]] <= a[i]) change(1, 1, n, s1[t1 - 1] + 1, s1[t1], (a[i] - a[s1[t1]]) / d, 0), t1--; while (t2 && a[s2[t2]] >= a[i]) change(1, 1, n, s2[t2 - 1] + 1, s2[t2], (a[s2[t2]] - a[i]) / d, 0), t2--; change(1, 1, n, i, i, 1, 1); change(1, 1, n, la, i, -1, 0); s1[++t1] = i; s2[++t2] = i; long long l = findans(1, 1, n), r = i; if (r - l + 1 > R - L + 1) L = l, R = r; } printf( %lld %lld , L, R); } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_64_1.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_64_1 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [0:0] data;
input rdreq;
input wrreq;
output empty;
output [0:0] q;
wire sub_wire0;
wire [0:0] sub_wire1;
wire empty = sub_wire0;
wire [0:0] q = sub_wire1[0:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 1,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_1_wave*.jpg FALSE
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* ARP cache
*/
module arp_cache #(
parameter CACHE_ADDR_WIDTH = 9
)
(
input wire clk,
input wire rst,
/*
* Cache query
*/
input wire query_request_valid,
output wire query_request_ready,
input wire [31:0] query_request_ip,
output wire query_response_valid,
input wire query_response_ready,
output wire query_response_error,
output wire [47:0] query_response_mac,
/*
* Cache write
*/
input wire write_request_valid,
output wire write_request_ready,
input wire [31:0] write_request_ip,
input wire [47:0] write_request_mac,
/*
* Configuration
*/
input wire clear_cache
);
reg mem_write = 0;
reg store_query = 0;
reg store_write = 0;
reg query_ip_valid_reg = 0, query_ip_valid_next;
reg [31:0] query_ip_reg = 0;
reg write_ip_valid_reg = 0, write_ip_valid_next;
reg [31:0] write_ip_reg = 0;
reg [47:0] write_mac_reg = 0;
reg clear_cache_reg = 0, clear_cache_next;
reg [CACHE_ADDR_WIDTH-1:0] wr_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, wr_ptr_next;
reg [CACHE_ADDR_WIDTH-1:0] rd_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, rd_ptr_next;
reg valid_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [31:0] ip_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [47:0] mac_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg query_request_ready_reg = 0, query_request_ready_next;
reg query_response_valid_reg = 0, query_response_valid_next;
reg query_response_error_reg = 0, query_response_error_next;
reg [47:0] query_response_mac_reg = 0;
reg write_request_ready_reg = 0, write_request_ready_next;
wire [31:0] query_request_hash;
wire [31:0] write_request_hash;
assign query_request_ready = query_request_ready_reg;
assign query_response_valid = query_response_valid_reg;
assign query_response_error = query_response_error_reg;
assign query_response_mac = query_response_mac_reg;
assign write_request_ready = write_request_ready_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
rd_hash (
.data_in(query_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(query_request_hash)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
wr_hash (
.data_in(write_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(write_request_hash)
);
integer i;
initial begin
for (i = 0; i < 2**CACHE_ADDR_WIDTH; i = i + 1) begin
valid_mem[i] = 1'b0;
ip_addr_mem[i] = 32'd0;
mac_addr_mem[i] = 48'd0;
end
end
always @* begin
mem_write = 1'b0;
store_query = 1'b0;
store_write = 1'b0;
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
clear_cache_next = clear_cache_reg | clear_cache;
query_ip_valid_next = query_ip_valid_reg;
query_request_ready_next = (~query_ip_valid_reg || ~query_request_valid || query_response_ready) && !clear_cache_next;
query_response_valid_next = query_response_valid_reg & ~query_response_ready;
query_response_error_next = query_response_error_reg;
if (query_ip_valid_reg && (~query_request_valid || query_response_ready)) begin
query_response_valid_next = 1;
query_ip_valid_next = 0;
if (valid_mem[rd_ptr_reg] && ip_addr_mem[rd_ptr_reg] == query_ip_reg) begin
query_response_error_next = 0;
end else begin
query_response_error_next = 1;
end
end
if (query_request_valid && query_request_ready && (~query_ip_valid_reg || ~query_request_valid || query_response_ready)) begin
store_query = 1;
query_ip_valid_next = 1;
rd_ptr_next = query_request_hash[CACHE_ADDR_WIDTH-1:0];
end
write_ip_valid_next = write_ip_valid_reg;
write_request_ready_next = !clear_cache_next;
if (write_ip_valid_reg) begin
write_ip_valid_next = 0;
mem_write = 1;
end
if (write_request_valid && write_request_ready) begin
store_write = 1;
write_ip_valid_next = 1;
wr_ptr_next = write_request_hash[CACHE_ADDR_WIDTH-1:0];
end
if (clear_cache) begin
clear_cache_next = 1'b1;
wr_ptr_next = 0;
end else if (clear_cache_reg) begin
wr_ptr_next = wr_ptr_reg + 1;
clear_cache_next = wr_ptr_next != 0;
mem_write = 1;
end
end
always @(posedge clk) begin
if (rst) begin
query_ip_valid_reg <= 1'b0;
query_request_ready_reg <= 1'b0;
query_response_valid_reg <= 1'b0;
write_ip_valid_reg <= 1'b0;
write_request_ready_reg <= 1'b0;
clear_cache_reg <= 1'b1;
wr_ptr_reg <= 0;
end else begin
query_ip_valid_reg <= query_ip_valid_next;
query_request_ready_reg <= query_request_ready_next;
query_response_valid_reg <= query_response_valid_next;
write_ip_valid_reg <= write_ip_valid_next;
write_request_ready_reg <= write_request_ready_next;
clear_cache_reg <= clear_cache_next;
wr_ptr_reg <= wr_ptr_next;
end
query_response_error_reg <= query_response_error_next;
if (store_query) begin
query_ip_reg <= query_request_ip;
end
if (store_write) begin
write_ip_reg <= write_request_ip;
write_mac_reg <= write_request_mac;
end
rd_ptr_reg <= rd_ptr_next;
query_response_mac_reg <= mac_addr_mem[rd_ptr_reg];
if (mem_write) begin
valid_mem[wr_ptr_reg] <= !clear_cache_reg;
ip_addr_mem[wr_ptr_reg] <= write_ip_reg;
mac_addr_mem[wr_ptr_reg] <= write_mac_reg;
end
end
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long p = 1000000000; vector<int> a; a.resize(n); long long fib[100]; fib[0] = 1; fib[1] = 1; for (long long i = 2; i < 100; i++) fib[i] = (fib[i - 1] + fib[i - 2]) % p; for (int i = 0; i < n; i++) cin >> a[i]; long long t, x, y; for (int i = 0; i < m; i++) { cin >> t >> x >> y; if (t == 1) { x--; a[x] = y; } else { x--; y--; long long res = 0; for (long long j = 0; j + x <= y; j++) { res += a[x + j] * fib[j]; res = res % p; } cout << res << endl; } } return 0; } |
module konamicoder (
digit_0,
digit_1,
digit_2,
digit_3,
state
);
output [6:0] digit_0;
output [6:0] digit_1;
output [6:0] digit_2;
output [6:0] digit_3;
input [3:0] state;
wire [6:0] digit_0;
wire [6:0] digit_1;
wire [6:0] digit_2;
wire [6:0] digit_3;
// Least-significant bit is segment 'A', most significant is 'G'
parameter char_u = 7'b0111110;
parameter char_p = 7'b1110011;
parameter char_d = 7'b1011110;
parameter char_n = 7'b1010100;
parameter char_l = 7'b0111000;
parameter char_f = 7'b1110001;
parameter char_r = 7'b1010000;
parameter char_h = 7'b1110100;
parameter char_0 = 7'b0111111;
parameter char_1 = 7'b0000110;
parameter char_2 = 7'b1011011;
parameter char_9 = 7'b1101111;
parameter char_ = 7'b1000000;
assign digit_0 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_u :
(state == 4'd2) ? char_u :
(state == 4'd3) ? char_d :
(state == 4'd4) ? char_d :
(state == 4'd5) ? char_l :
(state == 4'd6) ? char_r :
(state == 4'd7) ? char_l :
(state == 4'd8) ? char_r :
(state == 4'd9) ? char_9 : char_0;
assign digit_1 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_p :
(state == 4'd2) ? char_p :
(state == 4'd3) ? char_n :
(state == 4'd4) ? char_n :
(state == 4'd5) ? char_f :
(state == 4'd6) ? char_h :
(state == 4'd7) ? char_f :
(state == 4'd8) ? char_h :
(state == 4'd9) ? char_9 : char_0;
assign digit_2 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_ :
(state == 4'd2) ? char_ :
(state == 4'd3) ? char_ :
(state == 4'd4) ? char_ :
(state == 4'd5) ? char_ :
(state == 4'd6) ? char_ :
(state == 4'd7) ? char_ :
(state == 4'd8) ? char_ :
(state == 4'd9) ? char_9 : char_0;
assign digit_3 =
(state == 4'd0) ? char_ :
(state == 4'd1) ? char_1 :
(state == 4'd2) ? char_2 :
(state == 4'd3) ? char_1 :
(state == 4'd4) ? char_2 :
(state == 4'd5) ? char_1 :
(state == 4'd6) ? char_1 :
(state == 4'd7) ? char_2 :
(state == 4'd8) ? char_2 :
(state == 4'd9) ? char_9 : char_0;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9122_if (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
// internal resets and clocks
dac_rst,
dac_clk,
dac_div_clk,
dac_status,
// data interface
dac_frame_i0,
dac_data_i0,
dac_frame_i1,
dac_data_i1,
dac_frame_i2,
dac_data_i2,
dac_frame_i3,
dac_data_i3,
dac_frame_q0,
dac_data_q0,
dac_frame_q1,
dac_data_q1,
dac_frame_q2,
dac_data_q2,
dac_frame_q3,
dac_data_q3,
// mmcm reset
mmcm_rst,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_IODELAY_GROUP = "dac_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
// internal resets and clocks
input dac_rst;
output dac_clk;
output dac_div_clk;
output dac_status;
// data interface
input dac_frame_i0;
input [15:0] dac_data_i0;
input dac_frame_i1;
input [15:0] dac_data_i1;
input dac_frame_i2;
input [15:0] dac_data_i2;
input dac_frame_i3;
input [15:0] dac_data_i3;
input dac_frame_q0;
input [15:0] dac_data_q0;
input dac_frame_q1;
input [15:0] dac_data_q1;
input dac_frame_q2;
input [15:0] dac_data_q2;
input dac_frame_q3;
input [15:0] dac_data_q3;
// mmcm reset
input mmcm_rst;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg dac_status_m1 = 'd0;
reg dac_status = 'd0;
// dac status
always @(posedge dac_div_clk) begin
if (dac_rst == 1'b1) begin
dac_status_m1 <= 1'd0;
dac_status <= 1'd0;
end else begin
dac_status_m1 <= up_drp_locked;
dac_status <= dac_status_m1;
end
end
// dac data output serdes(s) & buffers
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DATA_WIDTH(16))
i_serdes_out_data (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_data_i0),
.data_s1 (dac_data_q0),
.data_s2 (dac_data_i1),
.data_s3 (dac_data_q1),
.data_s4 (dac_data_i2),
.data_s5 (dac_data_q2),
.data_s6 (dac_data_i3),
.data_s7 (dac_data_q3),
.data_out_p (dac_data_out_p),
.data_out_n (dac_data_out_n));
// dac frame output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DATA_WIDTH(1))
i_serdes_out_frame (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_frame_i0),
.data_s1 (dac_frame_q0),
.data_s2 (dac_frame_i1),
.data_s3 (dac_frame_q1),
.data_s4 (dac_frame_i2),
.data_s5 (dac_frame_q2),
.data_s6 (dac_frame_i3),
.data_s7 (dac_frame_q3),
.data_out_p (dac_frame_out_p),
.data_out_n (dac_frame_out_n));
// dac clock output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DATA_WIDTH(1))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
.data_s3 (1'b0),
.data_s4 (1'b1),
.data_s5 (1'b0),
.data_s6 (1'b1),
.data_s7 (1'b0),
.data_out_p (dac_clk_out_p),
.data_out_n (dac_clk_out_n));
// dac clock input buffers
ad_serdes_clk #(
.SERDES (PCORE_SERDES_DDR_N),
.MMCM (PCORE_MMCM_BUFIO_N),
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (1.667),
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8))
i_serdes_clk (
.mmcm_rst (mmcm_rst),
.clk_in_p (dac_clk_in_p),
.clk_in_n (dac_clk_in_n),
.clk (dac_clk),
.div_clk (dac_div_clk),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; bool match(string s1, string s2) { long long cnt = 0; for (long long i = 0; s1[i]; ++i) { if (s1[i] != s2[i]) ++cnt; if (cnt > 1) return 0; } return 1; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n, m; cin >> n >> m; vector<string> v(n); for (long long i = 0; i < n; ++i) cin >> v[i]; bool ans = 0; string str; for (long long i = 0; i < m; ++i) { string s = v[0]; for (long long j = 1; j < n; ++j) { s[i] = v[j][i]; bool all_match = 1; for (long long k = 1; k < n; ++k) { if (!match(s, v[k])) { all_match = 0; break; } } if (all_match) { ans = 1; str = s; break; } } if (ans) break; } if (ans) cout << str << n ; else { bool all_match = 1; for (long long i = 1; i < n; ++i) { if (!match(v[0], v[i])) { all_match = 0; break; } } if (all_match) cout << v[0] << n ; else cout << -1 << n ; } } } |
#include <bits/stdc++.h> using namespace std; int xx[4] = {0, 0, 1, -1}; int yy[4] = {1, -1, 0, 0}; int n, m, q; int h[int(1e3 + 100)], dem, st[int(1e3 + 100)], vt[int(1e3 + 100)], top, mid; int a[int(1e3 + 100)][int(1e3 + 100)]; int hl[int(1e3 + 100)][int(1e3 + 100)], cl[int(1e3 + 100)][int(1e3 + 100)], cr[int(1e3 + 100)][int(1e3 + 100)], hr[int(1e3 + 100)][int(1e3 + 100)]; int solve() { int res = 0; h[dem + 1] = 0; for (int i = (1), _b = (dem + 1); i <= _b; i++) { int y = i; while (top != 0 && h[i] <= st[top]) { if (vt[top] <= mid && mid < i) res = max(res, (i - vt[top]) * st[top]); y = vt[top]; top--; } if (h[i] > st[top]) { top++; st[top] = h[i]; vt[top] = y; } } return res; } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = (1), _b = (n); i <= _b; i++) for (int j = (1), _b = (m); j <= _b; j++) scanf( %d , &a[i][j]); for (int i = (1), _b = (n); i <= _b; i++) for (int j = (1), _b = (m); j <= _b; j++) if (a[i][j] == 1) { hl[i][j] = hl[i][j - 1] + 1; cl[i][j] = cl[i - 1][j] + 1; } else { hl[i][j] = 0; cl[i][j] = 0; } for (int i = (n), _a = (1); i >= _a; i--) for (int j = (m), _a = (1); j >= _a; j--) if (a[i][j] == 1) { hr[i][j] = hr[i][j + 1] + 1; cr[i][j] = cr[i + 1][j] + 1; } else { hr[i][j] = 0; cr[i][j] = 0; } for (int i = (1), _b = (q); i <= _b; i++) { int s, x, y; scanf( %d%d%d , &s, &x, &y); if (s == 1) { a[x][y] = 1 - a[x][y]; for (int j = (y), _b = (m); j <= _b; j++) if (a[x][j]) { hl[x][j] = hl[x][j - 1] + 1; } else hl[x][j] = 0; for (int j = (y), _a = (1); j >= _a; j--) if (a[x][j]) { hr[x][j] = hr[x][j + 1] + 1; } else hr[x][j] = 0; for (int i = (x), _b = (n); i <= _b; i++) if (a[i][y]) { cl[i][y] = cl[i - 1][y] + 1; } else cl[i][y] = 0; for (int i = (x), _a = (1); i >= _a; i--) if (a[i][y]) { cr[i][y] = cr[i + 1][y] + 1; } else cr[i][y] = 0; } else { if (a[x][y] == 0) { printf( 0 n ); continue; } int res = 0; int l = x; int r = x; while (a[l - 1][y]) l--; while (a[r + 1][y]) r++; dem = 0; for (int i = (l), _b = (r); i <= _b; i++) { dem++; h[dem] = hr[i][y]; if (i == x) mid = dem; } res = max(res, solve()); dem = 0; for (int i = (l), _b = (r); i <= _b; i++) { dem++; h[dem] = hl[i][y]; if (i == x) mid = dem; } res = max(res, solve()); l = y; r = y; while (a[x][l - 1]) l--; while (a[x][r + 1]) r++; dem = 0; for (int i = (l), _b = (r); i <= _b; i++) { dem++; h[dem] = cr[x][i]; if (i == y) mid = dem; } res = max(res, solve()); dem = 0; for (int i = (l), _b = (r); i <= _b; i++) { dem++; h[dem] = cl[x][i]; if (i == y) mid = dem; } res = max(res, solve()); printf( %d n , res); } } } |
// -*- Mode: Verilog -*-
// Filename : test_00.v
// Description : Simple ADXL362 Test Case to bring environment to life
// Author : Philip Tracton
// Created On : Thu Jun 23 11:36:12 2016
// Last Modified By: Philip Tracton
// Last Modified On: Thu Jun 23 11:36:12 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "simulation_includes.vh"
module test_case ();
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "accelerometer_00";
parameter number_of_tests = 16;
defparam `ADXL362_ACCELEROMETER.XDATA_FILE = "accelerometer_00_xdata.txt";
defparam `ADXL362_ACCELEROMETER.YDATA_FILE = "accelerometer_00_ydata.txt";
defparam `ADXL362_ACCELEROMETER.ZDATA_FILE = "accelerometer_00_zdata.txt";
defparam `ADXL362_ACCELEROMETER.TEMPERATURE_FILE = "accelerometer_00_temperature_data.txt";
reg err;
reg [31:0] data_out = 0;
integer i;
initial begin
$display("Accelerometer 00 Case");
`TB.master_bfm.reset;
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
@(negedge `ADXL362_RESET);
`SIMPLE_SPI_INIT;
//
// Set FIFO Mode to Streaming
// Turn on Temperature FIFO
//
`ADXL362_WRITE_REGISTER(`ADXL362_FIFO_CONTROL, 8'h06);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
while (data_out[8] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(5) @(posedge `WB_CLK);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_XDATA_LOW, 16'h0001);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_YDATA_LOW, 16'h0011);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_ZDATA_LOW, 16'h00f1);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_TEMP_LOW, 16'h0047);
while (data_out[8] ==1) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
while (data_out[8] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(5) @(posedge `WB_CLK);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_XDATA_LOW, 16'h0002);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_YDATA_LOW, 16'h0012);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_ZDATA_LOW, 16'h00F2);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_TEMP_LOW, 16'h0048);
while (data_out[8] ==1) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
while (data_out[8] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(5) @(posedge `WB_CLK);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_XDATA_LOW, 16'h0003);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_YDATA_LOW, 16'h0013);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_ZDATA_LOW, 16'h00F3);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_TEMP_LOW, 16'h0049);
while (data_out[8] ==1) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
while (data_out[8] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(5) @(posedge `WB_CLK);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_XDATA_LOW, 16'h0004);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_YDATA_LOW, 16'h0014);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_ZDATA_LOW, 16'h00F4);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_TEMP_LOW, 16'h004A);
while (data_out[8] ==1) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(100) @(posedge `WB_CLK);
`TEST_COMPLETE;
end
endmodule // test_case
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111OI_1_V
`define SKY130_FD_SC_HD__A2111OI_1_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111oi_1 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111OI_1_V
|
// ------------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- ---------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// ------------------------------------------------------------------------------
// -- --
// -- This stage merely acts as a buffer in between the ALU stage and the reg.--
// -- file (i.e., writeback stage). 32-bit data received from the cache is --
// -- is rotated appropriately here in case of byte reads or halfword reads. --
// -- Otherwise, this stage is simply a buffer. --
// -- --
// ------------------------------------------------------------------------------
`default_nettype none
module zap_memory_main
#(
// Width of CPSR.
parameter FLAG_WDT = 32,
// Number of physical registers.
parameter PHY_REGS = 46
)
(
// Debug
input wire [64*8-1:0] i_decompile,
output reg [64*8-1:0] o_decompile,
// Clock and reset.
input wire i_clk,
input wire i_reset,
// Pipeline control signals.
input wire i_clear_from_writeback,
input wire i_data_stall,
// Memory stuff.
input wire i_mem_load_ff,
input wire [31:0] i_mem_address_ff, // Access Address.
// Data read from memory.
input wire [31:0] i_mem_rd_data,
// Memory fault transfer. i_mem_fault comes from the cache unit.
input wire [1:0] i_mem_fault, // Fault in.
output reg [1:0] o_mem_fault, // Fault out.
// Data valid and buffered PC.
input wire i_dav_ff,
input wire [31:0] i_pc_plus_8_ff,
// ALU value, flags,and where to write the value.
input wire [31:0] i_alu_result_ff,
input wire [FLAG_WDT-1:0] i_flags_ff,
input wire [$clog2(PHY_REGS)-1:0] i_destination_index_ff,
// Interrupts.
input wire i_irq_ff,
input wire i_fiq_ff,
input wire i_instr_abort_ff,
input wire i_swi_ff,
// Memory SRCDEST index. For loads, this tells the register file where
// to put the read data. Set to point to RAZ if invalid.
input wire [$clog2(PHY_REGS)-1:0] i_mem_srcdest_index_ff,
// SRCDEST value.
input wire [31:0] i_mem_srcdest_value_ff,
// Memory size and type.
input wire i_sbyte_ff,
i_ubyte_ff,
i_shalf_ff,
i_uhalf_ff,
// Undefined instr.
input wire i_und_ff,
output reg o_und_ff,
// ALU result and flags.
output reg [31:0] o_alu_result_ff,
output reg [FLAG_WDT-1:0] o_flags_ff,
// Where to write ALU and memory read target register.
output reg [$clog2(PHY_REGS)-1:0] o_destination_index_ff,
// Set to point to the RAZ register if invalid.
output reg [$clog2(PHY_REGS)-1:0] o_mem_srcdest_index_ff,
// Outputs valid and PC buffer.
output reg o_dav_ff,
output reg [31:0] o_pc_plus_8_ff,
// The whole interrupt signaling scheme.
output reg o_irq_ff,
output reg o_fiq_ff,
output reg o_swi_ff,
output reg o_instr_abort_ff,
// Memory load information is passed down.
output reg o_mem_load_ff,
output reg [31:0] o_mem_rd_data
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
reg i_mem_load_ff2 ;
reg [31:0] i_mem_srcdest_value_ff2 ;
reg [31:0] i_mem_address_ff2 ;
reg i_sbyte_ff2 ;
reg i_ubyte_ff2 ;
reg i_shalf_ff2 ;
reg i_uhalf_ff2 ;
reg [31:0] mem_rd_data ;
// Invalidates the outptus of this stage.
task clear;
begin
// Invalidate stage.
o_dav_ff <= 0;
// Clear interrupts.
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_swi_ff <= 0;
o_instr_abort_ff <= 0;
o_und_ff <= 0;
o_mem_fault <= 0;
end
endtask
// On reset or on a clear from WB, we will disable the vectors
// in this unit. Else, we will just flop everything out.
always @ (posedge i_clk)
if ( i_reset )
begin
clear;
end
else if ( i_clear_from_writeback )
begin
clear;
end
else if ( i_data_stall )
begin
// Stall unit. Outputs do not change.
o_dav_ff <= 1'd0;
end
else
begin
// Just flop everything out.
o_alu_result_ff <= i_alu_result_ff;
o_flags_ff <= i_flags_ff;
o_mem_srcdest_index_ff<= i_mem_srcdest_index_ff;
o_dav_ff <= i_dav_ff;
o_destination_index_ff<= i_destination_index_ff;
o_pc_plus_8_ff <= i_pc_plus_8_ff;
o_irq_ff <= i_irq_ff;
o_fiq_ff <= i_fiq_ff;
o_swi_ff <= i_swi_ff;
o_instr_abort_ff <= i_instr_abort_ff;
o_mem_load_ff <= i_mem_load_ff;
o_und_ff <= i_und_ff;
o_mem_fault <= i_mem_fault;
mem_rd_data <= i_mem_rd_data;
// Debug.
o_decompile <= i_decompile;
end
// Manual Pipeline Retiming.
always @ (posedge i_clk)
begin
if ( !i_data_stall )
begin
i_mem_load_ff2 <= i_mem_load_ff;
i_mem_srcdest_value_ff2 <= i_mem_srcdest_value_ff;
i_mem_address_ff2 <= i_mem_address_ff;
i_sbyte_ff2 <= i_sbyte_ff;
i_ubyte_ff2 <= i_ubyte_ff;
i_shalf_ff2 <= i_shalf_ff;
i_uhalf_ff2 <= i_uhalf_ff;
end
end
always @*
o_mem_rd_data = transform((i_mem_load_ff2 ? mem_rd_data :
i_mem_srcdest_value_ff2), i_mem_address_ff2[1:0],
i_sbyte_ff2, i_ubyte_ff2, i_shalf_ff2, i_uhalf_ff2,
i_mem_load_ff2);
// Memory always loads 32-bit to processor.
// We will rotate that here as we wish.
function [31:0] transform (
// Data and address.
input [31:0] data,
input [1:0] address,
// Memory access data type.
input sbyte,
input ubyte,
input shalf,
input uhalf,
// Memory load.
input mem_load_ff
);
begin: transform_function
reg [31:0] d; // Data shorthand.
transform = 32'd0;
d = data;
// Unsigned byte. Take only lower byte.
if ( ubyte == 1'd1 )
begin
case ( address[1:0] )
0: transform = (d >> 0) & 32'h000000ff;
1: transform = (d >> 8) & 32'h000000ff;
2: transform = (d >> 16) & 32'h000000ff;
3: transform = (d >> 24) & 32'h000000ff;
endcase
end
// Signed byte. Sign extend lower byte.
else if ( sbyte == 1'd1 )
begin
// Take lower byte.
case ( address[1:0] )
0: transform = (d >> 0) & 32'h000000ff;
1: transform = (d >> 8) & 32'h000000ff;
2: transform = (d >> 16) & 32'h000000ff;
3: transform = (d >> 24) & 32'h000000ff;
endcase
// Sign extend.
transform = $signed(transform[7:0]);
end
// Signed half word. Sign extend lower 16-bit.
else if ( shalf == 1'd1 )
begin
case ( address[1] )
0: transform = (d >> 0) & 32'h0000ffff;
1: transform = (d >> 16) & 32'h0000ffff;
endcase
transform = $signed(transform[15:0]);
end
// Unsigned half word. Take only lower 16-bit.
else if ( uhalf == 1'd1 )
begin
case ( address[1] )
0: transform = (d >> 0) & 32'h0000ffff;
1: transform = (d >> 16) & 32'h0000ffff;
endcase
end
else // Default. Typically, a word.
begin
transform = data;
end
// Override above computation if not a memory load.
if ( !mem_load_ff )
begin
transform = data; // No memory load means pass data on.
end
end
endfunction
endmodule
`default_nettype wire
|
module data_generator(
input wire CLK,
input wire CE,
output wire D1,
output wire D2
);
// Ring buffers
reg [254:0] ring1;
initial ring1 <= 255'b010100110101100010111100101101010010011100001110110010000001011011011111011000101110100111001101101100110111101100001111100110000001011011010000111011000010001010101000101111101110110111100110110000001100101111111011010111100001101100001101111111001110111;
reg [255:0] ring2;
initial ring2 <= 256'b1010101100101110000100100101010000100000101110111011110111011111000111101101010101110111010011011101100100011111111101101000111110110110100010011011001001000011100011001001110001110101000001010011011001100101000001011111011101010000110011101111110100110010;
reg [256:0] ring3;
initial ring3 <= 257'b10000001100111000110101001001111100011011001100011011111000100110100110001011101100111110101101111101011000101110100100110110010000111100011111101010000000100101000100100110101011111011000100100001001100110101011111101101011011100010101000111110010110011110;
// Rotate ring buffers
always @(posedge CLK)
if (CE) ring1 <= {ring1[0], ring1[254:1]};
always @(posedge CLK)
if (CE) ring2 <= {ring2[0], ring2[255:1]};
always @(posedge CLK)
if (CE) ring3 <= {ring3[0], ring3[256:1]};
// Output data
assign D1 = ring1[0] ^ ring2[0];
assign D2 = ring2[0] ^ ring3[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; map<int, vector<int> > mx; map<int, vector<int> > my; int pow(int x) { long long i = 2; long long r = 1; while (x) { if (x & 1) r = (r * i) % 1000000007; i = (i * i) % 1000000007; x = x >> 1; } return r; } int main() { ios::sync_with_stdio(false); int i, j, n, t; cin >> n; int x[n]; int y[n]; long long an = 1; for (i = 0; i < n; i++) { cin >> x[i] >> y[i]; mx[x[i]].push_back(i); my[y[i]].push_back(i); } bool visit[i]; memset(visit, 0, i); set<int> sx; set<int> sy; int c; queue<int> q; for (i = 0; i < n; i++) if (!visit[i]) { c = 0; sx.clear(); sy.clear(); for (j = 0; j < mx[x[i]].size(); j++) { c++; q.push(mx[x[i]][j]); visit[mx[x[i]][j]] = 1; } sx.insert(x[i]); for (j = 0; j < my[y[i]].size(); j++) { c++; q.push(my[y[i]][j]); visit[my[y[i]][j]] = 1; } sy.insert(y[i]); t = i; while (!q.empty()) { i = q.front(); q.pop(); if (sx.find(x[i]) == sx.end()) for (j = 0; j < mx[x[i]].size(); j++) { c++; q.push(mx[x[i]][j]); visit[mx[x[i]][j]] = 1; } sx.insert(x[i]); if (sy.find(y[i]) == sy.end()) for (j = 0; j < my[y[i]].size(); j++) { c++; q.push(my[y[i]][j]); visit[my[y[i]][j]] = 1; } sy.insert(y[i]); } i = t; if (c / 2 < sx.size() + sy.size()) an = (an * (pow(sx.size() + sy.size()) + 1000000007 - 1)) % 1000000007; else an = (an * pow(sx.size() + sy.size())) % 1000000007; } cout << an; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { set<string> S; long n; string a; cin >> n; for (long i = 0; i < n; i++) { cin >> a; string s = ; long j = 0; while (j < a.size()) { if (a[j] == k ) { long k = j; while (a[k] == k ) k++; if (a[k] == h ) { j = k; s = s + kh ; } else { s.push_back(a[j]); } } else if (a[j] == u ) { s = s + oo ; } else if (a[j] == h ) { s = s + kh ; } else { s.push_back(a[j]); } j++; } S.insert(s); } cout << S.size(); } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T abs(T t) { return t < 0 ? -t : t; } const unsigned long long modn = 1000000007; inline unsigned long long mod(unsigned long long x) { return x % modn; } const int MAX = 100009; int deg[MAX], ok[MAX]; vector<int> adj[MAX]; void dfs(int u, int p) { if (deg[u] > 3) return; ok[u]++; if (deg[u] == 3) return; for (int v : adj[u]) if (v != p) dfs(v, u); } int main() { int i, n, a, b; scanf( %d , &n); for (i = 0; i < n - 1; i++) { scanf( %d %d , &a, &b); adj[--a].push_back(--b); adj[b].push_back(a); deg[a]++; deg[b]++; } for (i = 0; i < n; i++) if (deg[i] == 1) dfs(i, -1); for (i = 0; i < n; i++) if (deg[i] == 3 && ok[i] <= 1) ok[i] = 0; for (i = 0; i < n; i++) { if (ok[i]) continue; int ct = 0; for (int v : adj[i]) if (!ok[v]) ct++; if (ct > 2) break; } if (i < n) puts( No ); else puts( Yes ); } |
#include <bits/stdc++.h> using namespace std; int n, m; char gird[64][64]; set<long long int> set_of_cols; int main(void) { int i, j; scanf( %d%d , &n, &m); for (i = 0; i < n; ++i) scanf( %s , gird[i]); for (i = 0; i < n; ++i) { long long int id = 0; for (j = 0; j < m; ++j) { id <<= 1; id |= ( # == gird[i][j]) ? 1 : 0; } for (auto have : set_of_cols) { if (have != id && ((have & id) != 0)) { puts( No ); return 0; } } set_of_cols.insert(id); } puts( Yes ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__MUX2_FUNCTIONAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cout.tie(0), cin.tie(0); int n; cin >> n; if (n <= 3) { cout << 0 << n ; return 0; } int Max = -1, k; for (int i = 2; i < n; ++i) { int tp = n / i * (i - 1); if (n % i >= 1) tp += n % i - 1; tp -= i - 1; if (tp > Max) Max = tp, k = i; } set<int> Se; vector<int> SS(n); int a = n / k, ps = 0; for (int i = 0; i < a; ++i) { for (int j = 0; j < k; ++j) { if (j == k - 1) ps++; else Se.insert(ps++); } } for (; ps < n - 1; ++ps) Se.insert(ps); for (int i : Se) SS[i] = 1; bool ok = 0; while (!ok) { vector<int> A; for (int i = 0; i < k; ++i) if (((int)(Se).size())) { A.push_back(*Se.begin()); Se.erase(Se.begin()); } if (((int)(Se).size()) == 0) ok = 1; cout << ((int)(A).size()) << ; for (int i : A) cout << i + 1 << ; cout << endl; cout.flush(); int l; cin >> l; --l; for (int i = 0; i < k; ++i) { if (SS[(i + l) % n]) Se.insert((i + l) % n); } if (ok) { cout << 0 << endl; cout.flush(); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[123456]; int avg[123456]; for (int i = 0; i < n; i++) cin >> a[i]; long long count = 0; for (int i = 0; i < n; i++) count += a[i]; int Max = count / n; int rem = count % n; long long c = 0; for (int i = 0; i < n; i++) avg[i] = Max; sort(a, a + n); for (int i = n - 1; i >= 0; i--) { if (!rem) continue; avg[i]++; rem--; } for (int i = 0; i < n; i++) if (a[i] > avg[i]) c += a[i] - avg[i]; cout << c << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, m; cin >> n >> m; bool aOk = true, bOk = true; vector<vector<int>> a(n, vector<int>(m)), b(n, vector<int>(m)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> b[i][j]; int t1 = a[i][j], t2 = b[i][j]; a[i][j] = min(t1, t2); b[i][j] = max(t1, t2); if ((i - 1) >= 0) { if (b[i][j] <= b[i - 1][j]) bOk = false; if (a[i][j] <= a[i - 1][j]) aOk = false; } if ((j - 1) >= 0) { if (b[i][j] <= b[i][j - 1]) bOk = false; if (a[i][j] <= a[i][j - 1]) aOk = false; } } } if (aOk and bOk) cout << Possible n ; else cout << Impossible n ; } |
#include <bits/stdc++.h> using namespace std; int ans[120000], fa[120000], i, j, k, l, n, m, n2; int get(int x) { return fa[x] == x ? x : (fa[x] = get(fa[x])); } int main() { scanf( %d , &n); if (n & 1) return puts( -1 ), 0; for (i = 0; i < n; ++i) fa[i] = i; n2 = n / 2; for (i = 0; i < n2; ++i) { ans[i] = i * 2; ans[i + n2] = i * 2 + 1; fa[get(i)] = get(i * 2); fa[get(i + n2)] = get(i * 2 + 1); } for (i = 0; i < n2; ++i) if (get(i) != get(i + n2)) { swap(ans[i], ans[i + n2]); fa[get(i)] = get(i + n2); } for (i = 0;;) { printf( %d , i); i = ans[i]; if (!i) break; } printf( 0 n ); } |
#include <bits/stdc++.h> using namespace std; struct child { long long v, p, d; }; child c[4123]; bool gone[4123]; int main() { int n; scanf( %d , &n); for (int i = 0; i < (int)(n); i++) { scanf( %lld%lld%lld , &c[i].v, &c[i].d, &c[i].p); } int ans = 0; vector<int> all; for (int i = 0; i < (int)(n); i++) { if (gone[i]) continue; ans++; all.push_back(i + 1); for (int j = i + 1; j < n && c[i].v; j++) { if (gone[j]) continue; c[j].p -= c[i].v; c[i].v--; } long long dec = 0; for (int j = i + 1; j < n; j++) { if (gone[j]) continue; c[j].p -= dec; if (c[j].p < 0) { gone[j] = 1; dec += c[j].d; } } } printf( %d n , ans); for (int i = 0; i < (int)(all.size()); i++) { printf( %d%c , all[i], (i == all.size() - 1 ? n : )); } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:12:55 03/06/2016
// Design Name: sumcomp
// Module Name: C:/XilinxP/Practica1/sumcomp_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sumcomp
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Test para Sumador completo de 1 bit, Practica 1
module sumcomp_test;
// Inputs
reg xi;
reg yi;
reg ci;
// Outputs
wire Si;
wire Co;
// Instantiate the Unit Under Test (UUT)
sumcomp uut (
.xi(xi),
.yi(yi),
.ci(ci),
.Si(Si),
.Co(Co)
);
initial begin
$display("...");
// Initialize Inputs
xi = 0;
yi = 0;
ci = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
xi = 0; yi = 0; ci = 0; //000
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 0; ci = 1; //001
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 1; ci = 0; //010
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 0; yi = 1; ci = 1; //011
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 0; ci = 0; //100
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 0; ci = 1; //101
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 1; ci = 0; //110
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
xi = 1; yi = 1; ci = 1; //111
#50;
$display("xi = %b, yi = %b, ci = %b, Si = %b, Co = %b", xi, yi, ci, Si, Co);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void ZZ(const char* name, Arg1&& arg1) { std::cerr << name << = << arg1 << endl; } template <typename Arg1, typename... Args> void ZZ(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); std::cerr.write(names, comma - names) << = << arg1; ZZ(comma, args...); } int n, u, v; int nxt[1000010], ans[1000010], cnt[1000010]; pair<int, int> a[1000000]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); ; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; cnt[a[i].second] = 1; nxt[a[i].first] = a[i].second; if (!a[i].first) u = a[i].second; } for (int i = 0; i < n; i++) { if (!cnt[a[i].first]) { v = a[i].first; break; } } for (int i = 0; i < n; i += 2) { ans[i] = v; v = nxt[v]; } for (int i = 1; i < n; i += 2) { ans[i] = u; u = nxt[u]; } for (int i = 0; i < n; i++) cout << ans[i] << ; return 0; } |
//======================================================================
//
// chacha_poly1305_p1305.v
// -----------------------
// Poly 1305 module for the ChaCha20-Poly1305 AEAD cipher core.
//
//
// Copyright (c) 2016, Secworks Sweden AB
// Joachim Strömbergson
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module chacha20_poly1305_p1305(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire done,
input wire [255 : 0] key,
output wire [127 : 0] tag
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam R_CLAMP = 128'h0ffffffc0ffffffc0ffffffc0fffffff;
localparam POLY1305 = 129'h3fffffffffffffffffffffffffffffffb;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [127 : 0] r_reg;
reg [127 : 0] r_new;
reg r_we;
reg [127 : 0] s_reg;
reg [127 : 0] s_new;
reg s_we;
reg [255 : 0] acc_reg;
reg [255 : 0] acc_new;
reg acc_we;
reg [2 : 0] p1305_ctrl_reg;
reg [2 : 0] p1305_ctrl_new;
reg p1305_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin
if (!reset_n)
begin
r_reg <= 128'h0;
s_reg <= 128'h0;
acc_reg <= 256'h0;
p1305_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (r_we)
r_reg <= r_new;
if (s_we)
s_reg <= s_new;
if (acc_we)
acc_reg <= acc_new;
if (p1305_ctrl_we)
p1305_ctrl_reg <= p1305_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// poly1305_dp
//
// The datapath for implementing poly1305. We need logic
// to init the accumulator and setting the r, s keys. We need
// logic to either update the accumulator from cleartext
// or calculated ciphertext.
//----------------------------------------------------------------
always @*
begin : poly1305_dp
reg [512 : 0] block;
acc_new = 256'h0;
acc_we = 0;
r_new = data_out[255 : 128] & R_CLAMP;
r_we = 0;
s_new = data_out[127 : 000];
s_we = 0;
if (poly1305_init)
begin
r_we = 1;
s_we = 1;
acc_we = 1;
end
if (poly1305_next)
begin
if (encdec)
block = {1'h1, data_out};
else
block = {1'h1, data_in};
acc_new = ((acc_reg + block) * r_reg) % POLY1305;
acc_we = 1;
end
end
//----------------------------------------------------------------
// p1305_ctrl
//
// Main control FSM.
//----------------------------------------------------------------
always @*
begin : p1305_ctrl
p1305_ctrl_new = CTRL_IDLE;
p1305_ctrl_we = 0;
case (p1305_ctrl_reg)
CTRL_IDLE:
begin
end
default:
begin
end
endcase // case (p1305_ctrl_reg)
end // p1305_ctrl
endmodule // chacha_poly1305_p1305
//======================================================================
// EOF chacha_poly1305_p1305.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int read() { bool f = 0; int x = 0; char c = getchar(); while (c < 0 || 9 < c) { if (c == - ) f = 1; c = getchar(); } while ( 0 <= c && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); return !f ? x : -x; } const int MAXN = 200000; const int INF = 0x3f3f3f3f; int fa[MAXN + 5], ch[MAXN + 5][2]; long long a[MAXN + 5], siz[MAXN + 5], sum[MAXN + 5], ans[MAXN + 5], all[MAXN + 5], ad[MAXN + 5], de[MAXN + 5]; bool pan(int u) { return ch[fa[u]][1] == u; } bool isroot(int u) { return (ch[fa[u]][0] != u && ch[fa[u]][1] != u); } void PushUp(int u) { sum[u] = sum[ch[u][0]] + sum[ch[u][1]] + siz[u]; all[u] = all[ch[u][0]] + all[ch[u][1]] + siz[u] * a[u]; ans[u] = ans[ch[u][0]] + ans[ch[u][1]] + ad[u] + a[u] * (siz[u] * siz[u] - de[u]) + 2 * a[u] * siz[u] * sum[ch[u][1]] + 2 * all[ch[u][0]] * (sum[u] - sum[ch[u][0]]); return; } void Rotate(int x) { int y = fa[x], z = fa[y], dx = pan(x), dy = pan(y), w = ch[x][dx ^ 1]; if (!isroot(y)) ch[z][dy] = x; ch[x][dx ^ 1] = y, ch[y][dx] = w; if (w) fa[w] = y; fa[y] = x, fa[x] = z; PushUp(y); return; } void Splay(int x) { for (int y = fa[x]; !isroot(x); Rotate(x), y = fa[x]) if (!isroot(y)) Rotate(pan(x) == pan(y) ? y : x); PushUp(x); return; } int Access(int x) { int y = 0; while (x) { Splay(x); siz[x] -= sum[y]; ad[x] -= ans[y]; de[x] -= sum[y] * sum[y]; siz[x] += sum[ch[x][1]]; ad[x] += ans[ch[x][1]]; de[x] += sum[ch[x][1]] * sum[ch[x][1]]; ch[x][1] = y, PushUp(x), y = x, x = fa[x]; } return y; } void Link(int x, int y) { Access(y); Splay(y); Access(x); Splay(x); fa[y] = x; siz[x] += sum[y]; ad[x] += ans[y]; de[x] += 1ll * sum[y] * sum[y]; PushUp(x); return; } void Cut(int x, int y) { Access(x); Splay(x); Splay(y); siz[x] -= sum[y]; ad[x] -= ans[y]; de[x] -= 1ll * sum[y] * sum[y]; fa[y] = 0; PushUp(x); return; } char Re[5]; int f[MAXN + 5]; bool check(int x, int y) { Access(y); Splay(y), Splay(x); return !isroot(y); } int main() { int n = read(); for (int i = 2; i <= n; i++) f[i] = read(); for (int i = 1; i <= n; i++) a[i] = read(), sum[i] = siz[i] = 1, ans[i] = all[i] = a[i]; for (int i = 2; i <= n; i++) Link(f[i], i); Access(1), Splay(1); printf( %.10f n , 1.0 * ans[1] / n / n); int m = read(); for (int i = 1; i <= m; i++) { scanf( %s , Re); if (Re[0] == P ) { int x = read(), y = read(); if (f[x] == y || f[y] == x) goto Break; if (check(x, y)) swap(x, y); Cut(f[x], x), f[x] = y; Link(f[x], x); } else { int x = read(), y = read(); Access(x), Splay(x); a[x] = y; PushUp(x); } Break: Access(1), Splay(1); printf( %.10f n , 1.0 * ans[1] / n / n); } return 0; } |
module qsys (
clk_clk,
reset_reset_n,
sdram_clock_areset_conduit_export,
sdram_clock_c0_clk,
sdram_read_control_fixed_location,
sdram_read_control_read_base,
sdram_read_control_read_length,
sdram_read_control_go,
sdram_read_control_done,
sdram_read_control_early_done,
sdram_read_user_read_buffer,
sdram_read_user_buffer_output_data,
sdram_read_user_data_available,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n,
sdram_write_control_fixed_location,
sdram_write_control_write_base,
sdram_write_control_write_length,
sdram_write_control_go,
sdram_write_control_done,
sdram_write_user_write_buffer,
sdram_write_user_buffer_input_data,
sdram_write_user_buffer_full);
input clk_clk;
input reset_reset_n;
input sdram_clock_areset_conduit_export;
output sdram_clock_c0_clk;
input sdram_read_control_fixed_location;
input [31:0] sdram_read_control_read_base;
input [31:0] sdram_read_control_read_length;
input sdram_read_control_go;
output sdram_read_control_done;
output sdram_read_control_early_done;
input sdram_read_user_read_buffer;
output [63:0] sdram_read_user_buffer_output_data;
output sdram_read_user_data_available;
output [12:0] sdram_wire_addr;
output [1:0] sdram_wire_ba;
output sdram_wire_cas_n;
output sdram_wire_cke;
output sdram_wire_cs_n;
inout [15:0] sdram_wire_dq;
output [1:0] sdram_wire_dqm;
output sdram_wire_ras_n;
output sdram_wire_we_n;
input sdram_write_control_fixed_location;
input [31:0] sdram_write_control_write_base;
input [31:0] sdram_write_control_write_length;
input sdram_write_control_go;
output sdram_write_control_done;
input sdram_write_user_write_buffer;
input [63:0] sdram_write_user_buffer_input_data;
output sdram_write_user_buffer_full;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_2clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ram_2clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLKA,
input CLKB,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
`include "functions.vh"
//Local parameters
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A221OI_FUNCTIONAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_FUNCTIONAL_PP_V |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cx4_pgmrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cx4_pgmrom (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [8:0] rdaddress;
input [9:0] wraddress;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({16{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_pgmrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_pgmrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_pgmrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_pgmrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_pgmrom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_pgmrom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFXTP_PP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ic_filter.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ic_filter(
// Outputs
torcvr,
// Inputs
topad,
vddo );
output torcvr;
input topad;
input vddo;
assign torcvr = topad ;
endmodule
|
#include <iostream> #include <vector> #include <algorithm> using namespace std; #define int long long void solve() { int n; vector<long long> vect; cin >> n; for (int i = 0; i < n; i++) { long long x; cin >> x; vect.push_back(x); } sort(vect.begin(), vect.end()); long long res = 0; long long now = 0; for (int i = n - 2; i >= 0; i--) { res -= now - (n - i - 2) * vect[i]; now += vect[i + 1]; } cout << res << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; for (int i = 0; i < t; i++) solve(); return 0; } |
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave
*******************************************************************************/
module spi_slave_cpha0(
clk,sck,mosi,miso,ssel,rst_n
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
/*******************************************************************************
*read from mosi we double sample the data
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
/* indicate a byte has been received */
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
assign miso = mosi_data; // send MSB first
endmodule |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Grab settings off the wishbone bus, send them out to settings bus
// 16 bits little endian, but all registers need to be written 32 bits at a time.
// This means that you write the low 16 bits first and then the high 16 bits.
// The setting regs are strobed when the high 16 bits are written
module settings_bus_16LE
#(parameter AWIDTH=16, RWIDTH=8)
(input wb_clk,
input wb_rst,
input [AWIDTH-1:0] wb_adr_i,
input [15:0] wb_dat_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output strobe,
output reg [7:0] addr,
output reg [31:0] data);
reg stb_int;
always @(posedge wb_clk)
if(wb_rst)
begin
stb_int <= 1'b0;
addr <= 8'd0;
data <= 32'd0;
end
else if(wb_we_i & wb_stb_i)
begin
addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits
if(wb_adr_i[1])
begin
stb_int <= 1'b1; // We now have both halves
data[31:16] <= wb_dat_i;
end
else
begin
stb_int <= 1'b0; // Don't strobe, we need other half
data[15:0] <= wb_dat_i;
end
end
else
stb_int <= 1'b0;
always @(posedge wb_clk)
if(wb_rst)
wb_ack_o <= 0;
else
wb_ack_o <= wb_stb_i & ~wb_ack_o;
assign strobe = stb_int & wb_ack_o;
endmodule // settings_bus_16LE
|
//`define ADD_SFD
module fifo9togmii (
// FIFO
input sys_rst,
input [8:0] dout,
input empty,
output rd_en,
output rd_clk,
// GMII
input gmii_tx_clk,
output gmii_tx_en,
output [7:0] gmii_txd
);
assign rd_clk = gmii_tx_clk;
//-----------------------------------
// CRC generator
//-----------------------------------
wire crc_init;
wire [31:0] crc_out;
reg crc_rd;
reg [7:0] txd;
assign crc_data_en = ~crc_rd;
crc_gen crc_inst (
.Reset(sys_rst),
.Clk(gmii_tx_clk),
.Init(crc_init),
.Frame_data(txd),
.Data_en(crc_data_en),
.CRC_rd(crc_rd),
.CRC_end(),
.CRC_out(crc_out)
);
`ifndef ADD_SFD
//-----------------------------------
// logic
//-----------------------------------
parameter STATE_IDLE = 2'h0;
parameter STATE_DATA = 2'h1;
parameter STATE_FCS = 2'h2;
reg [1:0] state;
reg [12:0] count;
reg [1:0] fcs_count;
reg [7:0] txd1, txd2;
reg tx_en;
assign crc_init = (count == 12'd7);
always @(posedge gmii_tx_clk) begin
if (sys_rst) begin
state <= STATE_IDLE;
txd <= 8'h0;
tx_en <= 1'b0;
count <= 12'h0;
crc_rd <= 1'b0;
fcs_count <= 2'h0;
end else begin
tx_en <= 1'b0;
crc_rd <= 1'b0;
case (state)
STATE_IDLE: begin
if (empty == 1'b0 && dout[8] == 1'b1) begin
txd <= dout[ 7: 0];
tx_en <= 1'b1;
state <= STATE_DATA;
count <= 12'h0;
end
end
STATE_DATA: begin
count <= count + 12'h1;
if (empty == 1'b0) begin
txd <= dout[ 7: 0];
tx_en <= dout[8];
if (dout[8] == 1'b0) begin
crc_rd <= 1'b1;
txd <= crc_out[31:24];
tx_en <= 1'b1;
fcs_count <= 2'h0;
state <= STATE_FCS;
end
end else
state <= STATE_IDLE;
end
STATE_FCS: begin
crc_rd <= 1'b1;
fcs_count <= fcs_count + 2'h1;
case (fcs_count)
2'h0: txd <= crc_out[23:16];
2'h1: txd <= crc_out[15: 8];
2'h2: begin
txd <= crc_out[ 7: 0];
state <= STATE_IDLE;
end
endcase
tx_en <= 1'b1;
end
endcase
end
end
assign rd_en = ~empty;
`else
//-----------------------------------
// logic
//-----------------------------------
parameter STATE_IDLE = 3'h0;
parameter STATE_PRE = 3'h1;
parameter STATE_SFD = 3'h2;
parameter STATE_DATA = 3'h3;
parameter STATE_FCS = 3'h4;
reg [2:0] state;
reg [2:0] count;
reg [1:0] fcs_count;
reg [7:0] txd1, txd2;
reg tx_en;
reg crc_init_req;
assign crc_init = crc_init_req;
always @(posedge gmii_tx_clk) begin
if (sys_rst) begin
state <= STATE_IDLE;
txd <= 8'h0;
tx_en <= 1'b0;
count <= 3'h0;
crc_init_req <= 1'b0;
crc_rd <= 1'b0;
fcs_count <= 2'h0;
end else begin
tx_en <= 1'b0;
crc_init_req <= 1'b0;
crc_rd <= 1'b0;
case (state)
STATE_IDLE: begin
if (empty == 1'b0 && dout[8] == 1'b1) begin
txd <= 8'h55;
tx_en <= 1'b1;
txd1 <= dout;
state <= STATE_PRE;
count <= 3'h0;
end
end
STATE_PRE: begin
tx_en <= 1'b1;
count <= count + 3'h1;
case (count)
3'h0: begin
txd <= 8'h55;
txd2 <= dout;
end
3'h6: begin
txd <= 8'hd5;
crc_init_req <= 1'b1;
end
3'h7: begin
txd <= txd1;
state <= STATE_SFD;
end
default: begin
txd <= 8'h55;
end
endcase
end
STATE_SFD: begin
txd <= txd2;
tx_en <= 1'b1;
state <= STATE_DATA;
end
STATE_DATA: begin
if (empty == 1'b0) begin
txd <= dout[ 7: 0];
tx_en <= dout[8];
if (dout[8] == 1'b0) begin
crc_rd <= 1'b1;
txd <= crc_out[31:24];
tx_en <= 1'b1;
fcs_count <= 2'h0;
state <= STATE_FCS;
end
end else
state <= STATE_IDLE;
end
STATE_FCS: begin
crc_rd <= 1'b1;
fcs_count <= fcs_count + 2'h1;
case (fcs_count)
2'h0: txd <= crc_out[23:16];
2'h1: txd <= crc_out[15: 8];
2'h2: begin
txd <= crc_out[ 7: 0];
state <= STATE_IDLE;
end
endcase
tx_en <= 1'b1;
end
endcase
end
end
assign rd_en = ~empty && (state != STATE_PRE);
`endif
assign gmii_tx_en = tx_en;
assign gmii_txd = txd;
endmodule
|
#include <bits/stdc++.h> inline void DoNothing() {} template <typename T> inline T Abs(const T a) { return a < 0 ? -a : a; } template <typename T> inline T Min(const T a, const T b) { return a < b ? a : b; } template <typename T> inline T Max(const T a, const T b) { return a > b ? a : b; } static const long double eps = 1.0e-07; template <typename T> inline T IsEqual(const T a, const T b) { return Abs(a - b) < eps; } template <typename T> inline T IsGreater(const T a, const T b) { return a > b + eps; } template <typename T> inline T IsLess(const T a, const T b) { return a + eps < b; } template <typename T> inline void Print(const T& val) { std::cout << val << ; } template <typename T> inline std::string ToStr(const T& val) { std::ostringstream ostr; ostr << val; return ostr.str(); } template <typename T> inline bool FromStr(const std::string& str, T& val) { std::istringstream istr(str); istr >> val; return !!istr; } struct Rand { unsigned long z_, w_; unsigned long get32() { z_ = 36969 * (z_ & 65535) + (z_ >> 16); w_ = 18000 * (w_ & 65535) + (w_ >> 16); return (z_ << 16) + (w_ & 65535); } void Reset() { z_ = 1; w_ = 1; } Rand() { Reset(); } }; template <typename T> inline std::vector<std::vector<T> > CreateVector2d(const size_t rowCnt, const size_t colCnt) { return std::vector<std::vector<T> >(rowCnt, std::vector<T>(colCnt)); } void Prepare(); class StopWatchEx { public: StopWatchEx(); ~StopWatchEx(); private: struct Data; Data* pData; }; inline double CalcRk(const double rb, const double rs, size_t k) { const double i_ds = 1 / (2 * rs); const double i_db = 1 / (2 * rb); const double i_d = i_ds - i_db; const double i_xc = i_db + i_d / 2; const double i_yc = i_d * (double)(k); const double i_c = sqrt(i_yc * i_yc + i_xc * i_xc); const double z1 = 1 / (i_c - i_d / 2); const double z2 = 1 / (i_c + i_d / 2); const double rk = (z1 - z2) / 2; return rk; } bool Solve(bool bCheckInputStream = false) { size_t n; std::cin >> n; if (bCheckInputStream && !std::cin) { return false; } StopWatchEx _sw; for (size_t i = 0; i < n; i++) { size_t rb, rs, k; std::cin >> rb >> rs >> k; const double rk = CalcRk((double)rb, (double)rs, k); std::cout << std::setprecision(8) << std::setw(12) << rk << std::endl; } return true; } int main() { Prepare(); Solve(); } struct StopWatchEx::Data {}; StopWatchEx::StopWatchEx() {} StopWatchEx::~StopWatchEx() {} void Prepare() {} |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, tt; cin >> n >> tt; vector<int> a(1 << n); long long sum = 0; for (int i = 0; i < (1 << n); i++) { cin >> a[i]; sum += (long long)a[i]; } cout << fixed << setprecision(17) << (double)sum / (1 << n) << n ; while (tt--) { int x, y; cin >> x >> y; sum += y - a[x]; a[x] = y; cout << fixed << setprecision(17) << (double)sum / (1 << n) << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; map<string, string> mp; for (int i = 0; i < m; i++) { string s1, s2; cin >> s1 >> s2; if (s2.size() < s1.size()) mp[s1] = s2; else mp[s1] = s1; } for (int i = 0; i < n; i++) { string s; cin >> s; for (auto it = mp.begin(); it != mp.end(); it++) { if (it->first == s) { cout << it->second << ; break; } } } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; static const int INF = 500000000; template <class T> void debug(T a, T b) { for (; a != b; ++a) cerr << *a << ; cerr << endl; } int n; pair<pair<int, int>, int> es[5005]; vector<pair<int, int> > g[5005]; int size[5005]; int cut[5005]; int prep(int v, int p) { size[v] = 1; for (int i = 0; i < g[v].size(); ++i) { int to = g[v][i].first; if (to == p || cut[to]) continue; size[v] += prep(to, v); } return size[v]; } int type; int cost[2], root[2], all[2]; void dfs(int v, int p) { int maxi = 0; for (int i = 0; i < g[v].size(); ++i) { int to = g[v][i].first; if (to == p || cut[to]) continue; maxi = max(maxi, size[to]); dfs(to, v); } if (max(maxi, all[type] - size[v]) < cost[type]) { cost[type] = max(maxi, all[type] - size[v]); root[type] = v; } } long long int tot; int dfs2(int v, int p) { size[v] = 1; for (int i = 0; i < g[v].size(); ++i) { int to = g[v][i].first; if (to == p || cut[to]) continue; size[v] += dfs2(to, v); tot += size[to] * (all[type] - size[to]) * (long long int)g[v][i].second; tot += size[to] * (long long int)all[type ^ 1] * g[v][i].second; } return size[v]; } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; ++i) { int a, b, c; scanf( %d%d%d , &a, &b, &c); --a; --b; g[a].push_back(make_pair(b, c)); g[b].push_back(make_pair(a, c)); es[i] = make_pair(make_pair(a, b), c); } long long int ans = 1e18; for (int i = 0; i < n - 1; ++i) { int a = es[i].first.first, b = es[i].first.second; tot = 0; cost[0] = cost[1] = INF; type = 0; cut[b] = 1; all[0] = prep(a, b); all[1] = n - all[0]; dfs(a, b); dfs2(root[0], -1); type = 1; cut[b] = 0; cut[a] = 1; all[1] = prep(b, a); dfs(b, a); dfs2(root[1], -1); cut[a] = 0; tot += all[0] * all[1] * (long long int)es[i].second; ans = min(ans, tot); } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S15_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYGATE4S15_FUNCTIONAL_V
/**
* dlygate4s15: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlygate4s15 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S15_FUNCTIONAL_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: A small shadow-RAM to qualify the data entries in the dual-port
// compram
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Modification by zjs, 2009-6-18, pending
// (1) move posted packet generator and non-posted packet generator out --- done
// (2) add dma write data fifo --------------- done
// (3) modify tx sm
// scheduling -------------------------- done
// disable write dma done -------------- done
// register/memory read ---------------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pending_comp_ram_32x1(
input clk,
input d_in,
input [4:0] addr,
input we,
output reg [31:0] d_out = 32'h00000000
);
wire [31:0] addr_decode;
//binary-to-onehot address decoder for ram
assign addr_decode[31:0] = 32'h00000001 << addr[4:0];
//generate a 32-entry ram with
//addressable inputs entries
//and outputs which are always present;
//essentially this is a 32x1 register file
genvar i;
generate
for(i=0;i<32;i=i+1)begin: bitram
always@(posedge clk)begin
if(addr_decode[i] && we)begin
d_out[i] <= d_in;
end
end
end
endgenerate
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon ST Packets to Bytes Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_packets_to_bytes
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0)
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST in with packets
output reg in_ready,
input in_valid,
input [7: 0] in_data,
input [CHANNEL_WIDTH-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
reg sent_esc, sent_sop, sent_eop;
reg sent_channel_char, channel_escaped, sent_channel;
reg [CHANNEL_WIDTH:0] stored_channel;
reg [4:0] channel_count;
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
reg channel_needs_esc;
wire need_sop, need_eop, need_esc, need_channel;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign need_esc = (in_data === 8'h7a |
in_data === 8'h7b |
in_data === 8'h7c |
in_data === 8'h7d );
assign need_eop = (in_endofpacket);
assign need_sop = (in_startofpacket);
generate
if( CHANNEL_WIDTH > 0) begin
wire channel_changed;
assign channel_changed = (in_channel != stored_channel);
assign need_channel = (need_sop | channel_changed);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
out_data <= 0;
out_valid <= 0;
channel_count <= 0;
channel_needs_esc <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin
sent_channel_char <= 1;
out_data <= 8'h7c;
channel_count <= CHN_COUNT[4:0];
stored_varchannel <= in_channel;
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
channel_needs_esc <= (in_channel == 8'h7a |
in_channel == 8'h7b |
in_channel == 8'h7c |
in_channel == 8'h7d );
end
end else if (channel_needs_esc & ~channel_escaped) begin
out_data <= 8'h7d;
channel_escaped <= 1;
end else if (~sent_channel) begin
if (ENCODING) begin
// Sending out MSB=1, while not last 7 bits of Channel
if (channel_count > 0) begin
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
stored_varchannel <= stored_varchannel<<7;
channel_count <= channel_count - 1'b1;
// check whether the last 7 bits need escape or not
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
channel_needs_esc <=
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
end
end else begin
// Sending out MSB=0, last 7 bits of Channel
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
sent_channel <= 1;
end
end else begin
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= in_channel ^ 8'h20;
end else out_data <= in_channel;
sent_channel <= 1;
end
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
end
end
end
end
//channel related signals
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
//extra bit in stored_channel to force reset
stored_channel <= {CHANNEL_WIDTH{1'b1}};
end else begin
//update stored_channel only when it is sent out
if (sent_channel) stored_channel <= in_channel;
end
end
always @* begin
// in_ready. Low when:
// back pressured, or when
// we are outputting a control character, which means that one of
// {escape_char, start of packet, end of packet, channel}
// needs to be, but has not yet, been handled.
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end else begin
assign need_channel = (need_sop);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
out_data <= 0;
out_valid <= 0;
sent_channel <= 0;
sent_channel_char <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
sent_channel_char <= 1;
out_data <= 8'h7c;
end else if (~sent_channel) begin
out_data <= 'h0;
sent_channel <= 1;
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
end
end
end
end
always @* begin
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end
endgenerate
endmodule
|
// This file is part of Verilog-65c816.
//
// Copyright 2017 by FPGApeeps
//
// Verilog-65c816 is free software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// Verilog-65c816 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with Verilog-65c816. If not, see <http://www.gnu.org/licenses/>.
`include "src/inc/misc_defines.v"
`include "src/inc/test_ram_defines.v"
// Block RAM test module
module _InternalTestRam(input wire clk,
// Write enable
input wire we,
// Address
input wire [`TR_ADDR_MSB_POS:0] addr,
// Data in
input wire [`TR_DATA_MSB_POS:0] data_in,
// Data out
output reg [`TR_DATA_MSB_POS:0] data_out);
`include "src/inc/cpu_debug_params.v"
reg [`TR_DATA_MSB_POS:0] __mem[0:`_ARR_SIZE_THING(`_TR_ADDR_WIDTH)];
initial $readmemh("readmemh_input.txt.ignore", __mem);
always @ (posedge clk)
begin
//$display("In _InternalTestRam: %h\t\t%h\t\t%h, %h",
// we,
// addr,
// data_in, data_out);
$display("In _InternalTestRam: %h\t\t%h, %h, %h\t\t%h",
we,
__mem[__debug_addr_0], __mem[__debug_addr_1],
__mem[__debug_addr_2],
data_out);
if (we)
begin
__mem[addr] <= data_in;
end
data_out <= __mem[addr];
end
endmodule
module TestRam(input wire clk,
input wire req_rdwr,
// Write enable
input wire we,
// Address
input wire [`TR_ADDR_MSB_POS:0] addr,
// Data in
input wire [`TR_DATA_MSB_POS:0] data_in,
// Data out
output wire [`TR_DATA_MSB_POS:0] data_out,
// data_ready goes high when data is ready
output reg data_ready);
`include "src/inc/generic_params.v"
reg __can_rdwr;
//reg [1:0] __can_rdwr;
// "pt" is short for "passthrough"
wire __pt_we;
wire [`TR_ADDR_MSB_POS:0] __pt_addr;
wire [`TR_DATA_MSB_POS:0] __pt_data_in, __pt_data_out;
// Inputs to internal_test_ram
assign __pt_we = we;
assign __pt_addr = addr;
assign __pt_data_in = data_in;
// Outputs from internal_test_ram
assign data_out = __pt_data_out;
_InternalTestRam internal_test_ram(.clk(clk), .we(__pt_we),
.addr(__pt_addr), .data_in(__pt_data_in),
.data_out(__pt_data_out));
initial data_ready = __false;
initial __can_rdwr = __false;
always @ (posedge clk)
begin
//__can_rdwr <= !__can_rdwr;
if (!req_rdwr)
begin
data_ready <= __false;
__can_rdwr <= __false;
end
else // if (req_rdwr)
begin
__can_rdwr <= !__can_rdwr;
data_ready <= __can_rdwr;
end
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The Reset Ctrl module to implement reset control
//
// ====================================================================
`include "e203_defines.v"
module e203_reset_ctrl #(
parameter MASTER = 1
)(
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The core's clk and rst
output rst_core,
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
// The Top always on clk and rst
output rst_aon
);
wire rst_sync_n;
`ifndef E203_HAS_LOCKSTEP//{
localparam RST_SYNC_LEVEL = `E203_ASYNC_FF_LEVELS;
`endif//}
reg [RST_SYNC_LEVEL-1:0] rst_sync_r;
generate
if(MASTER == 1) begin:master_gen
always @(posedge clk or negedge rst_n)
begin:rst_sync_PROC
if(rst_n == 1'b0)
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {RST_SYNC_LEVEL{1'b0}};
end
else
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {rst_sync_r[RST_SYNC_LEVEL-2:0],1'b1};
end
end
assign rst_sync_n = test_mode ? rst_n : rst_sync_r[`E203_ASYNC_FF_LEVELS-1];
end
else begin:slave_gen
// Just pass through for slave in lockstep mode
always @ *
begin:rst_sync_PROC
rst_sync_r = {RST_SYNC_LEVEL{1'b0}};
end
assign rst_sync_n = rst_n;
end
endgenerate
// The core's clk and rst
assign rst_core = rst_sync_n;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
assign rst_itcm = rst_sync_n;
`endif
`ifdef E203_HAS_DTCM
assign rst_dtcm = rst_sync_n;
`endif
// The Top always on clk and rst
assign rst_aon = rst_sync_n;
endmodule
|
#include <bits/stdc++.h> using namespace std; long double det(long double x, long double y, long double z, long double t) { return x * t - y * z; } long long int pow(long long int n, long long int m) { if (m == 0) return 1; if (m == 1) return n % (int)1e9 + 7; long long int t = pow(n, m / 2) % (int)1e9 + 7; if (m % 2 == 0) return (t % (int)1e9 + 7 * t % (int)1e9 + 7) % (int)1e9 + 7; else return ((t % (int)1e9 + 7 * t % (int)1e9 + 7) % (int)1e9 + 7 * (n % (int)1e9 + 7)) % (int)1e9 + 7; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int x, y, i, z = 1, q = 1; cin >> x >> y; if (x == 0) return cout << 0, 0; x %= (int)1e9 + 7; x *= 2; x %= (int)1e9 + 7; x -= 1; if (y % 2) { y -= 1; q *= 2; } while (y > 0) { z = 2; for (i = 1; i <= (long long int)log2(y); i++) { z *= z; z %= (int)1e9 + 7; } y -= pow(2, (long long int)log2(y)); q *= z; q %= (int)1e9 + 7; } long long int ans = q * x + 1; while (ans >= (int)1e9 + 7) ans -= (int)1e9 + 7; while (ans < 0) ans += (int)1e9 + 7; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; while (~scanf( %d , &t)) { while (t--) { int n; scanf( %d , &n); char a[n + 1]; scanf( %s , a); int ans = 0; for (int i = 0; i < n; i++) { if (a[i] == > || a[n - i - 1] == < ) { break; } else { ans++; } } printf( %d n , ans); } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b; cin >> n >> m; double mn = 101.00, x = 0.00; for (int i = 1; i <= n; i++) { cin >> a >> b; x = a / (b * 1.00); if (mn > x) mn = x; } cout << fixed << setprecision(8); cout << mn * m << endl; return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 8405 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w255,
w4,
w5,
w8160,
w8415,
w10,
w8405;
assign w1 = i_data0;
assign w10 = w5 << 1;
assign w255 = w256 - w1;
assign w256 = w1 << 8;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w8160 = w255 << 5;
assign w8405 = w8415 - w10;
assign w8415 = w255 + w8160;
assign o_data0 = w8405;
//multiplier_block area estimate = 7577.53919243235;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O221A_FUNCTIONAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int MOD = 1e9 + 7; long long int power(long long int a, long long int b) { long long int res = 1; a = a % MOD; while (b > 0) { if (b & 1) { res = (res * a) % MOD; b--; } a = (a * a) % MOD; b >>= 1; } return res; } long long int fermat_inv(long long int y) { return power(y, MOD - 2); } long long int gcd(long long int a, long long int b) { return (b == 0) ? a : gcd(b, a % b); } long long int min(long long int a, long long int b) { return (a > b) ? b : a; } long long int max(long long int a, long long int b) { return (a > b) ? a : b; } bool prime[1000001]; vector<int> primes; void SieveOfEratosthenes(int n) { memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } for (int p = 2; p < 1000001; p++) if (prime[p]) primes.push_back(p); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; cin >> t; while (t--) { long long int n, a, b; string s; cin >> n >> a >> b >> s; long long int cost = n * a + (n + 1) * b; vector<int> v; long long int j = 1; for (int i = 1; i < n; i++) { if (s[i] == s[i - 1]) j++; else { v.push_back(j); j = 1; } } if (v.empty()) { cout << cost << n ; continue; } v.erase(v.begin()); cost += 2 * a; for (int i = 0; i < v.size(); i++) { if (i % 2 == 0) cost += (long long int)(v[i] + 1) * b; else { if (2 * a <= (long long int)(v[i] - 1) * b) cost += 2 * a; else cost += (long long int)(v[i] - 1) * b; } } cout << cost << n ; } } |
#include <bits/stdc++.h> using namespace std; const long long N = 5e5 + 5; const long long mod = 1e9 + 7; void solve() { long long n; cin >> n; if (n == 1) { cout << -1 << endl; return; } cout << n << << n + 1 << << n * (n + 1) << endl; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int SIZE = 100005; int gap, tmp[SIZE * 2]; class SuffixArray { public: int sa[SIZE], rk[SIZE], ht[SIZE]; static bool cmp(int x, int y) { if (tmp[x] != tmp[y]) return tmp[x] < tmp[y]; return tmp[x + gap] < tmp[y + gap]; } void gao(const char* s, int n) { copy(s, s + n + 1, rk); for (gap = 1; gap <= n; gap <<= 1) { for (int i = 0; i <= n; i++) sa[i] = i; copy(rk, rk + n + 1, tmp); sort(sa, sa + n + 1, cmp); for (int i = rk[*sa] = 0; i < n; i++) rk[sa[i + 1]] = rk[sa[i]] + cmp(sa[i], sa[i + 1]); } for (int i = gap = ht[*sa] = 0; i < n; i++) { if (gap) --gap; while (s[i + gap] == s[sa[rk[i] - 1] + gap]) gap++; ht[rk[i]] = gap; } } }; char str[SIZE]; SuffixArray SA; int main() { int n = strlen(gets(str)); long long ans = n * (n + 1ll) / 2, cnt = 0; SA.gao(str, n); vector<int> u = {0}; for (int i = 1; i <= n; i++) { while (SA.ht[i] < SA.ht[u.back()]) { cnt -= SA.ht[u.back()] * (u.back() - u[u.size() - 2]); u.pop_back(); } u.push_back(i); cnt += SA.ht[u.back()] * (u.back() - u[u.size() - 2]); ans += cnt; } printf( %I64d n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { const string t = RGB ; int q; cin >> q; for (int i = 0; i < q; ++i) { int n, k; string s; cin >> n >> k >> s; int ans = 1e9; for (int j = 0; j < n - k + 1; ++j) { for (int offset = 0; offset < 3; ++offset) { int cur = 0; for (int pos = 0; pos < k; ++pos) { if (s[j + pos] != t[(pos + offset) % 3]) { ++cur; } } ans = min(ans, cur); } } cout << ans << endl; } return 0; } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4kx16_dc.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SREGSBP_PP_BLACKBOX_V
/**
* sregsbp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void _print(long long t) { cerr << t; } void _print(int t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(vector<vector<T>> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << , ; _print(p.second); cerr << } ; } template <class T> void _print(vector<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(vector<vector<T>> v) { cerr << ==> << endl; for (vector<T> vec : v) { for (T i : vec) { _print(i); cerr << ; } cerr << endl; } } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } mt19937_64 rang( chrono::high_resolution_clock::now().time_since_epoch().count()); int rng(int lim) { uniform_int_distribution<int> uid(0, lim - 1); return uid(rang); } const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; long long mod_exp(long long a, long long b) { a %= mod; if (a == 0) return 0LL; long long res = 1LL; while (b > 0) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } long long mod_inv(long long a) { return mod_exp(a, mod - 2); } long long GCD(long long a, long long b) { return (b == 0) ? a : GCD(b, a % b); } void solve() { long long a1, a2, a3, a4, a5, a6; cin >> a1 >> a2 >> a3 >> a4 >> a5 >> a6; cout << ((a1 + a2 + a3) * (a1 + a2 + a3)) - (a1 * a1) - (a3 * a3) - (a5 * a5); } int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); srand(chrono::high_resolution_clock::now().time_since_epoch().count()); int t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct tree { int l, r, c, p; }; int n, K, m, r; long long res, a[10000011], b[10000011]; bool cmp1(tree a, tree b) { return a.l < b.l; } bool cmp2(tree a, tree b) { return a.r < b.r; } void update(int x, int l, int r, int c, int p) { if (l == r) { a[x] += c, b[x] += 1ll * l * c; return; } int mid = (l + r) >> 1; if (p <= mid) update(x << 1, l, mid, c, p); else update(x << 1 | 1, mid + 1, r, c, p); a[x] = a[x << 1] + a[x << 1 | 1], b[x] = b[x << 1] + b[x << 1 | 1]; return; } long long query(int x, int l, int r, int p) { if (l == r) { if (p <= a[x]) return 1ll * l * p; return b[x]; } int mid = (l + r) >> 1; if (a[x << 1] >= p) return query(x << 1, l, mid, p); return query(x << 1 | 1, mid + 1, r, p - a[x << 1]) + b[x << 1]; } int main() { scanf( %d%d%d , &n, &K, &m); tree a[m + 1], b[m + 1]; for (int i = 1; i <= m; i++) scanf( %d%d%d%d , &a[i].l, &a[i].r, &a[i].c, &a[i].p), b[i] = a[i]; for (int i = 1; i <= m; i++) r = max(r, a[i].p); sort(a + 1, a + m + 1, cmp1); sort(b + 1, b + m + 1, cmp2); for (int i = 1, j = 1, k = 1; i <= n; i++) { while (j <= m && a[j].l == i) update(1, 1, r, a[j].c, a[j].p), j++; res += query(1, 1, r, K); while (k <= m && b[k].r == i) update(1, 1, r, -b[k].c, b[k].p), k++; } printf( %lld , res); return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2010/11/09 17:40:54 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2010/11/09 17:40:54 mishra Exp $
**$Date: 2010/11/09 17:40:54 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_1/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module iodelay_ctrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name when
// multiple IP cores used in design
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter RST_ACT_LOW = 1 // Reset input polarity
// (0 = active high, 1 = active low)
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output clk_ref,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input
//***************************************************************************
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
assign clk_ref = clk_ref_bufg;
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "decoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_decoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [10:0] qout;
// Declare "reg" signals: inputs to the DUT
reg [14:0] cin;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
ham_15_11_decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
cin,qout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
cin = 15'b110101100000011;
$display(cin[1]," << b1 b2 >>",cin[2]);
$display(cin[3]," << b1 b2 >>",cin[4]);
// @ t=0,
#1;
cin = 15'b111000111000011;
#1;
cin = 15'b110011101010011;
#1;
cin = 15'b111101110010011;
#1;
cin = 15'b111110000100011;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
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