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module top;
reg [15:0] out_16;
reg [31:0] in_32, in_32x, out_32, out_32x;
reg [63:0] out_64;
integer res, fd;
reg passed;
initial begin
passed = 1'b1;
// Check that a normal 32 bit %z works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #1 returned %d", res);
passed = 1'b0;
end else if (in_32 !== out_32) begin
$display("FAILED: #1 %b !== %b", in_32, out_32);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #1 EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that a normal 32/64 bit %z works as expected. Do the write as
// two 32 bit values to make sure the word order is correct.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
in_32x = 32'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%z", in_32x);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_64);
if (res !== 1) $display("FAILED: $fscanf() #2a returned %d", res);
else if ({in_32x,in_32} !== out_64) begin
$display("FAILED: #2a %b !== %b", {in_32x,in_32}, out_64);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #2a EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that a normal 64/64 bit %z works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
in_32x = 32'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%z", {in_32x,in_32});
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_64);
if (res !== 1) $display("FAILED: $fscanf() #2b returned %d", res);
else if ({in_32x,in_32} !== out_64) begin
$display("FAILED: #2b %b !== %b", {in_32x,in_32}, out_64);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #2b EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that a normal 64/32 bit %z works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
in_32x = 32'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%z", {in_32x,in_32});
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z%z", out_32,out_32x);
if (res !== 2) $display("FAILED: $fscanf() #2c returned %d", res);
else if ({in_32x,in_32} !== {out_32x, out_32}) begin
$display("FAILED: #2c %b !== %b", {in_32x,in_32}, {out_32x,out_32});
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #2c EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that a 16 bit %z works as expected.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%z", out_16);
if (res !== 1) begin
$display("FAILED: $fscanf() #3 returned %d", res);
passed = 1'b0;
end else if (in_32[15:0] !== out_16) begin
$display("FAILED: #3 %b !== %b", in_32[15:0], out_16);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #3 EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that a 16 bit %z works as expected even with a 32 bit variable.
// All 32 bits are read but we truncate and zero fill the result.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%16z", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #4 returned %d", res);
passed = 1'b0;
end else if (in_32[15:0] !== out_32) begin
$display("FAILED: #4 %b !== %b", in_32[15:0], out_32);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #4 EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that a 32 bit %z works with a 64 bit variable when sized.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%32z", out_64);
if (res !== 1) begin
$display("FAILED: $fscanf() #5 returned %d", res);
passed = 1'b0;
end else if (in_32 !== out_64) begin
$display("FAILED: #5 %b !== %b", in_32, out_64);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #5 EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that by default one element is suppressed.
fd = $fopen("work/test_fscanf.bin", "wb");
in_32x = 32'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%z", in_32x);
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%*z%z", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #6 returned %d", res);
passed = 1'b0;
end else if (in_32 !== out_32) begin
$display("FAILED: #6 %b !== %b", in_32, out_32);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #6 EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that multiple elements can be suppressed (exact count).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32x = 32'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%z%z", in_32x, in_32x);
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%*64z%z", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #7 returned %d", res);
passed = 1'b0;
end else if (in_32 !== out_32) begin
$display("FAILED: #7 %b !== %b", in_32, out_32);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #7 EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
// Check that multiple elements can be suppressed (minimum count).
fd = $fopen("work/test_fscanf.bin", "wb");
in_32x = 32'b0001000x_0010000x_0011000x_0100000x;
$fwrite(fd, "%z%z", in_32x, in_32x);
in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x;
$fwrite(fd, "%z", in_32);
$fclose(fd);
fd = $fopen("work/test_fscanf.bin", "rb");
res = $fscanf(fd, "%*33z%z", out_32);
if (res !== 1) begin
$display("FAILED: $fscanf() #8 returned %d", res);
passed = 1'b0;
end else if (in_32 !== out_32) begin
$display("FAILED: #8 %b !== %b", in_32, out_32);
passed = 1'b0;
end
res = $fscanf(fd, "%z", out_32);
if (res !== -1) begin
$display("FAILED: $fscanf() #8 EOF returned %d (%b)", res, out_32);
passed = 1'b0;
end
$fclose(fd);
if (passed) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CONB_PP_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, k, a[10010]; bool vs[3000][3000]; int main() { cin >> n >> k; for (int i = n + 1; i <= n + k; i++) { a[i] = i - n; } for (int i = 1; i <= n; i++) a[i] = i; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= i + k; j++) { if (!vs[a[i]][a[j]] && !vs[a[j]][a[i]]) { vs[a[i]][a[j]] = true; vs[a[j]][a[i]] = true; } else { cout << -1; exit(0); } } } if (n == 1) { cout << -1; exit(0); } cout << n * k << n ; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= i + k; j++) cout << a[i] << << a[j] << n ; } |
/// date :2016/3/3
/// engineer :ZhaiShaoMin
/// module name: data path of FSM_upload_flit
/// module function : combination of needed state elment,which are controled by FSM_upload_flit
module upload_datapath(// input
clk,
rst,
clr_max,
clr_inv_ids,
clr_sel_cnt_inv,
clr_sel_cnt,
inc_sel_cnt,
inc_sel_cnt_inv,
en_flit_max_in,
en_for_reg,
en_inv_ids,
inv_ids_in,
dest_sel,
flit_max_in,
head_flit,
addrhi,
addrlo,
/* datahi1,
datalo1,
datahi2,
datalo2,
datahi3,
datalo3,
datahi4,
datalo4, */
//output
flit_out,
cnt_eq_max,
cnt_invs_eq_3,
cnt_eq_0,
inv_ids_reg_out,
sel_cnt_invs_out
);
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
///////////////////Datapath Unit///////////////////////////////////////////////////
input clk;
input rst;
// input [3:0] inv_ids_in; // invreq vector used for generating every invreqs
// input en_for_reg; // enable for all kinds of flits regs
input [15:0] head_flit;
input [15:0] addrhi;
input [15:0] addrlo;
/* input [15:0] datahi1;
input [15:0] datalo1;
input [15:0] datahi2;
input [15:0] datalo2;
input [15:0] datahi3;
input [15:0] datalo3;
input [15:0] datahi4;
input [15:0] datalo4; */
input clr_max;
input clr_inv_ids;
input clr_sel_cnt_inv;
input clr_sel_cnt;
input inc_sel_cnt;
input inc_sel_cnt_inv;
input en_for_reg;
input en_inv_ids;
input [3:0] inv_ids_in;
input [3:0] flit_max_in;
input en_flit_max_in;
input dest_sel;
// output
output [15:0] flit_out;
output cnt_eq_max;
output cnt_invs_eq_3;
output cnt_eq_0;
output [3:0] inv_ids_reg_out;
output [1:0] sel_cnt_invs_out;
// register max_number of flits of a message
reg [3:0] flits_max;
always@(posedge clk)
begin
if(rst||clr_max)
flits_max<=4'b0000;
else if(en_flit_max_in)
flits_max<=flit_max_in;
end
// register current needed invreqs vector
reg [3:0] inv_ids_reg;
always@(posedge clk)
begin
if(rst||clr_inv_ids)
inv_ids_reg<=4'b0000;
else if(en_inv_ids)
inv_ids_reg<=inv_ids_in;
end
wire [3:0] inv_ids_reg_out;
assign inv_ids_reg_out=inv_ids_reg;
// selection counter for mux flit among 11 flit regs
reg [3:0] sel_cnt;
always@(posedge clk)
begin
if(rst||clr_sel_cnt)
sel_cnt<=4'b0000;
else if(inc_sel_cnt)
sel_cnt<=sel_cnt+4'b0001;
end
// selection counter for invreqs_vector generating different invreqs with different dest id
reg [1:0] sel_cnt_invs;
always@(posedge clk)
begin
if(rst||clr_sel_cnt_inv)
sel_cnt_invs<=2'b00;
else if(inc_sel_cnt_inv)
sel_cnt_invs<=sel_cnt_invs+2'b01;
end
wire [1:0] sel_cnt_invs_out;
assign sel_cnt_invs_out=sel_cnt_invs;
wire cnt_eq_0;
assign cnt_eq_0=(sel_cnt==4'b0000);
wire cnt_eq_max;
assign cnt_eq_max=(sel_cnt==flits_max);
wire cnt_invs_eq_3;
assign cnt_invs_eq_3=(sel_cnt_invs==2'b11);
reg [15:0] head_flit_reg;
reg [15:0] addrhi_reg;
reg [15:0] addrlo_reg;
/*reg [15:0] datahi1_reg;
reg [15:0] datalo1_reg;
reg [15:0] datahi2_reg;
reg [15:0] datalo2_reg;
reg [15:0] datahi3_reg;
reg [15:0] datalo3_reg;
reg [15:0] datahi4_reg;
reg [15:0] datalo4_reg; */
always@(posedge clk)
begin
if(rst)
begin
head_flit_reg<=16'h0000;
addrhi_reg<=16'h0000;
addrlo_reg<=16'h0000;
/* datahi1_reg<=16'h0000;
datalo1_reg<=16'h0000;
datahi2_reg<=16'h0000;
datalo2_reg<=16'h0000;
datahi3_reg<=16'h0000;
datalo3_reg<=16'h0000;
datahi4_reg<=16'h0000;
datalo4_reg<=16'h0000; */
end
else if(en_for_reg)
begin
head_flit_reg<=head_flit;
addrhi_reg<=addrhi;
addrlo_reg<=addrlo;
/* datahi1_reg<=datahi1;
datalo1_reg<=datahi1;
datahi2_reg<=datahi1;
datalo2_reg<=datalo2;
datahi3_reg<=datahi3;
datalo3_reg<=datalo3;
datahi4_reg<=datahi4;
datalo4_reg<=datalo4; */
end
end
// dest selection if 0 :scORinvreqs ;1 :wbORflushreqs
wire [1:0] dest_seled_id;
assign dest_seled_id=dest_sel?head_flit_reg[15:14]:sel_cnt_invs;
// select flit outputting to req fifo
reg [15:0] flit_seled_out;
always@(*)
begin
// if(en_sel)
// begin
case(sel_cnt)
4'b0000:flit_seled_out={dest_seled_id,head_flit_reg[13:0]};
4'b0001:flit_seled_out=addrhi_reg;
4'b0010:flit_seled_out=addrlo_reg;
/* 4'b0011:flit_seled_out=datahi1_reg;
4'b0100:flit_seled_out=datalo1_reg;
4'b0101:flit_seled_out=datahi2_reg;
4'b0110:flit_seled_out=datalo2_reg;
4'b0111:flit_seled_out=datahi3_reg;
4'b1000:flit_seled_out=datalo3_reg;
4'b1001:flit_seled_out=datahi4_reg;
4'b1010:flit_seled_out=datalo4_reg; */
default:flit_seled_out=head_flit_reg;
endcase
// end
end
assign flit_out=flit_seled_out;
endmodule |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000000 + 10; char b[maxn]; int a[maxn]; int ccc[20]; int main() { long long n; long long sum = 0; cin >> n; if (n % 2 == 0) sum = n / 2; else sum = (-n - 1) / 2; cout << sum << endl; return 0; } |
`timescale 1ns / 1ps
/*
* File : uart-min.v
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 24-May-2010 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* 115200 baud 8-N-1 serial port, using only Tx and Rx.
* (8 data bits, no parity, 1 stop bit, no flow control.)
* Configurable baud rate determined by clocking module, 16x oversampling
* for Rx data, Rx filtering, and configurable FIFO buffers for receiving
* and transmitting.
*
* Described as '_min' due to lack of overflow and other status signals
* as well as the use of only Tx and Rx signals.
*/
module uart_min(
input clock,
input reset,
input write,
input [7:0] data_in, // tx going into uart, out of serial port
input read,
output [7:0] data_out, // rx coming in from serial port, out of uart
output data_ready,
output [8:0] rx_count, // Number of available bytes
/*------------------------*/
input RxD, // Input RxD pin
output TxD // Output TxD pin
);
localparam DATA_WIDTH = 8; // Bit-width of FIFO data (should be 8)
localparam ADDR_WIDTH = 8; // 2^ADDR_WIDTH bytes of FIFO space
/* Clocking Signals */
wire uart_tick, uart_tick_16x;
/* Receive Signals */
wire [7:0] rx_data; // Raw bytes coming in from uart
wire rx_data_ready; // Synchronous pulse indicating this (^)
wire rx_fifo_empty;
/* Send Signals */
reg tx_fifo_deQ = 0;
reg tx_start = 0;
wire tx_free;
wire tx_fifo_empty;
wire [7:0] tx_fifo_data_out;
assign data_ready = ~rx_fifo_empty;
always @(posedge clock) begin
if (reset) begin
tx_fifo_deQ <= 0;
tx_start <= 0;
end
else begin
if (~tx_fifo_empty & tx_free & uart_tick) begin
tx_fifo_deQ <= 1;
tx_start <= 1;
end
else begin
tx_fifo_deQ <= 0;
tx_start <= 0;
end
end
end
uart_clock clocks (
.clock (clock),
.uart_tick (uart_tick),
.uart_tick_16x (uart_tick_16x)
);
uart_tx tx (
.clock (clock),
.reset (reset),
.uart_tick (uart_tick),
.TxD_data (tx_fifo_data_out),
.TxD_start (tx_start),
.ready (tx_free),
.TxD (TxD)
);
uart_rx rx (
.clock (clock),
.reset (reset),
.RxD (RxD),
.uart_tick_16x (uart_tick_16x),
.RxD_data (rx_data),
.data_ready (rx_data_ready)
);
FIFO_NoFull_Count #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
tx_buffer (
.clock (clock),
.reset (reset),
.enQ (write),
.deQ (tx_fifo_deQ),
.data_in (data_in),
.data_out (tx_fifo_data_out),
.empty (tx_fifo_empty),
.count ()
);
FIFO_NoFull_Count #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
rx_buffer (
.clock (clock),
.reset (reset),
.enQ (rx_data_ready),
.deQ (read),
.data_in (rx_data),
.data_out (data_out),
.empty (rx_fifo_empty),
.count (rx_count)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GROUND_LVC_WPAD_BLACKBOX_V
`define SKY130_FD_IO__TOP_GROUND_LVC_WPAD_BLACKBOX_V
/**
* top_ground_lvc_wpad: Base ground I/O pad with low voltage clamp.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_ground_lvc_wpad (
G_PAD ,
AMUXBUS_A,
AMUXBUS_B
);
inout G_PAD ;
inout AMUXBUS_A;
inout AMUXBUS_B;
// Voltage supply signals
supply0 SRC_BDY_LVC1;
supply0 SRC_BDY_LVC2;
supply1 OGC_LVC ;
supply1 DRN_LVC1 ;
supply1 BDY2_B2B ;
supply0 DRN_LVC2 ;
supply0 G_CORE ;
supply1 VDDIO ;
supply1 VDDIO_Q ;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH ;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q ;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GROUND_LVC_WPAD_BLACKBOX_V
|
#include <bits/stdc++.h> const long long inf = std::numeric_limits<long long>::max(); const int infint = std::numeric_limits<int>::max(); const long long mod = 1e9 + 7; using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); vector<int> g[500100]; long long a[500100]; long long par[500100][21]; void dfs(int v, int p) { for (auto i : g[v]) { if (i == p) continue; dfs(i, v); par[i][0] = v; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; long long mn = inf; for (int i = 0; i < n; i++) { cin >> a[i]; mn = min(a[i], mn); } for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; x--, y--; g[x].push_back(y); g[y].push_back(x); } for (int i = 0; i < n; i++) { if (a[i] == mn) { par[i][0] = i; dfs(i, -1); break; } } long long w = 0; for (int i = 1; i < 21; i++) for (int j = 0; j < n; j++) par[j][i] = par[par[j][i - 1]][i - 1]; for (int i = 0; i < n; i++) { if (a[i] == mn) continue; long long now = inf; for (int j = 0; j < 21; j++) { now = min(now, a[par[i][j]] * (j + 1) + a[i]); } w += now; } cout << w; return 0; } |
#include <bits/stdc++.h> using namespace std; int arr[500005], brr[500005]; pair<int, int> tree[500005 * 4]; vector<int> vv[500005]; vector<pair<int, int> > qr[500005]; int ans[500005]; void build(int node, int b, int e) { if (b == e) { tree[node] = make_pair(500000000, 500000000); return; } int left = 2 * node, right = left + 1, mid = (b + e) / 2; build(left, b, mid); build(right, mid + 1, e); tree[node] = tree[left]; } void update(int node, int b, int e, int i, int v) { if (e < i || b > i) return; if (b == e && b == i) { tree[node] = make_pair(v, arr[b]); return; } int left = 2 * node, right = left + 1, mid = (b + e) / 2; update(left, b, mid, i, v); update(right, mid + 1, e, i, v); if (tree[left].first <= tree[right].first) { tree[node] = tree[left]; } else tree[node] = tree[right]; } pair<int, int> query(int node, int b, int e, int l, int r) { if (b > r || e < l) return make_pair(500000000, 500000000); if (b >= l && e <= r) return tree[node]; int left = 2 * node, right = left + 1, mid = (b + e) / 2; pair<int, int> p = query(left, b, mid, l, r); pair<int, int> q = query(right, mid + 1, e, l, r); if (p.first <= q.first) return p; return q; } int main() { int n; scanf( %d , &n); int mx = 0; for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]); vv[arr[i]].push_back(i); mx = max(mx, arr[i]); } int q; scanf( %d , &q); for (int i = 1; i <= q; i++) { int l, r; scanf( %d %d , &l, &r); qr[r].push_back(make_pair(l, i)); } build(1, 1, n); for (int i = 1; i <= n; i++) { int id = lower_bound(vv[arr[i]].begin(), vv[arr[i]].end(), i) - vv[arr[i]].begin(); int v; if (id == 0) { v = 1; brr[arr[i]] = i; } else { v = vv[arr[i]][id - 1] + 1; update(1, 1, n, brr[arr[i]], 500000000); brr[arr[i]] = i; } update(1, 1, n, i, v); for (int j = 0; j < qr[i].size(); j++) { pair<int, int> ret = query(1, 1, n, qr[i][j].first, i); if (qr[i][j].first >= ret.first) ans[qr[i][j].second] = ret.second; } } for (int i = 1; i <= q; i++) printf( %d n , ans[i]); } |
// nios_system_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 189
`timescale 1 ps / 1 ps
module nios_system_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The programmiable regs for HCLKGEN
//
// ====================================================================
module sirv_hclkgen_regs(
input clk,
input rst_n,
output pllbypass ,
output pll_RESET ,
output pll_ASLEEP ,
output [1:0] pll_OD,
output [7:0] pll_M,
output [4:0] pll_N,
output plloutdivby1,
output [5:0] plloutdiv,
output hfxoscen,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [12-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata
);
// Directly connect the command channel with response channel
assign i_icb_rsp_valid = i_icb_cmd_valid;
assign i_icb_cmd_ready = i_icb_rsp_ready;
wire icb_wr_en = i_icb_cmd_valid & i_icb_cmd_ready & (~i_icb_cmd_read);
wire [32-1:0] icb_wdata = i_icb_cmd_wdata;
wire [32-1:0] hfxosccfg_r;
wire [32-1:0] pllcfg_r;
wire [32-1:0] plloutdiv_r;
// Addr selection
wire sel_hfxosccfg = (i_icb_cmd_addr == 12'h004);
wire sel_pllcfg = (i_icb_cmd_addr == 12'h008);
wire sel_plloutdiv = (i_icb_cmd_addr == 12'h00C);
wire icb_wr_en_hfxosccfg = icb_wr_en & sel_hfxosccfg ;
wire icb_wr_en_pllcfg = icb_wr_en & sel_pllcfg ;
wire icb_wr_en_plloutdiv = icb_wr_en & sel_plloutdiv ;
assign i_icb_rsp_rdata =
({32{sel_hfxosccfg}} & hfxosccfg_r)
| ({32{sel_pllcfg }} & pllcfg_r )
| ({32{sel_plloutdiv}} & plloutdiv_r);
/////////////////////////////////////////////////////////////////////////////////////////
// HFXOSCCFG
wire hfxoscen_ena = icb_wr_en_hfxosccfg;
// The reset value is 1
sirv_gnrl_dfflrs #(1) hfxoscen_dfflrs (hfxoscen_ena, icb_wdata[30], hfxoscen, clk, rst_n);
assign hfxosccfg_r = {1'b0, hfxoscen, 30'b0};
/////////////////////////////////////////////////////////////////////////////////////////
// PLLCFG
//
// N: The reset value is 2 = 5'h2 = 5'b0_0010
sirv_gnrl_dfflr #(3) pll_N_42_dfflr (icb_wr_en_pllcfg, icb_wdata[4:2], pll_N[4:2], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_N_1_dfflr (icb_wr_en_pllcfg, icb_wdata[1], pll_N[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_N_0_dfflr (icb_wr_en_pllcfg, icb_wdata[0], pll_N[0], clk, rst_n);
//
// M: The reset value is 50 = 8'h32 = 8'b0011_0010
sirv_gnrl_dfflr #(1) pll_M_7_dfflr (icb_wr_en_pllcfg, icb_wdata[12], pll_M[7], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_6_dfflr (icb_wr_en_pllcfg, icb_wdata[11], pll_M[6], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_5_dfflr (icb_wr_en_pllcfg, icb_wdata[10], pll_M[5], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_4_dfflr (icb_wr_en_pllcfg, icb_wdata[09], pll_M[4], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_3_dfflr (icb_wr_en_pllcfg, icb_wdata[08], pll_M[3], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_2_dfflr (icb_wr_en_pllcfg, icb_wdata[07], pll_M[2], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_1_dfflr (icb_wr_en_pllcfg, icb_wdata[06], pll_M[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_0_dfflr (icb_wr_en_pllcfg, icb_wdata[05], pll_M[0], clk, rst_n);
// OD: The reset value is 2 = 2'b10
sirv_gnrl_dfflrs #(1) pll_OD_1_dfflrs(icb_wr_en_pllcfg, icb_wdata[14], pll_OD[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_OD_0_dfflr (icb_wr_en_pllcfg, icb_wdata[13], pll_OD[0], clk, rst_n);
// Bypass: The reset value is 1
sirv_gnrl_dfflrs #(1) pllbypass_dfflrs (icb_wr_en_pllcfg, icb_wdata[18], pllbypass, clk, rst_n);
// RESET: The reset value is 0
sirv_gnrl_dfflr #(1) pll_RESET_dfflrs (icb_wr_en_pllcfg, icb_wdata[30], pll_RESET, clk, rst_n);
// ASLEEP: The asleep value is 0
sirv_gnrl_dfflr #(1) pll_ASLEEP_dfflrs (icb_wr_en_pllcfg, icb_wdata[29], pll_ASLEEP, clk, rst_n);
assign pllcfg_r[31] = 1'b0;
assign pllcfg_r[30] = pll_RESET;
assign pllcfg_r[29] = pll_ASLEEP;
assign pllcfg_r[28:19] = 10'b0;
assign pllcfg_r[18] = pllbypass;
assign pllcfg_r[17:15] = 3'b0;
assign pllcfg_r[14:13] = pll_OD;
assign pllcfg_r[12:5] = pll_M;
assign pllcfg_r[4:0] = pll_N;
/////////////////////////////////////////////////////////////////////////////////////////
// PLLOUTDIV
//
wire plloutdiv_ena = icb_wr_en_plloutdiv;
sirv_gnrl_dfflr #(6) plloutdiv_dfflr (plloutdiv_ena, icb_wdata[5:0], plloutdiv, clk, rst_n);
wire plloutdivby1_ena = icb_wr_en_plloutdiv;
// The reset value is 1
sirv_gnrl_dfflrs #(1) plloutdivby1_dfflrs (plloutdivby1_ena, icb_wdata[8], plloutdivby1, clk, rst_n);
assign plloutdiv_r[31:9] = 23'b0;
assign plloutdiv_r[8] = plloutdivby1;
assign plloutdiv_r[7:6] = 2'b0;
assign plloutdiv_r[5:0] = plloutdiv;
endmodule
|
#include<bits/stdc++.h> #define ll long long #define ld long double #define ff first #define ss second #define eb emplace_back #define pb push_back #define mp make_pair #define all(x) begin(x), end(x) #define endl n int dx[4] = {1, -1, 0, 0}; int dy[4] = {0, 0, -1, 1}; // ll dp[100005]; ll mod = 1e9 + 7; bool vis[100000]; using namespace std; bool isPrime(ll n) { ll j; for ( j = 2; j <= sqrt(n); j++) { if (n % j == 0) { break; } } if (j > sqrt(n)) { return 1; } else { return 0; } } ll modexpo(ll a, ll b) { ll ans = 1; a = a % mod; while (b > 0) { if ((b & 1) == 1) { ans = ((ans % mod) * (a % mod)) % mod; } b = b >> 1; a = ((a % mod) * (a % mod)) % mod; } return ans; } ll invmod(ll n) { return modexpo(n, mod - 2); } ll comb(ll n, ll r) { if (r == 0) { return 1; } ll fact[n + 1]; fact[0] = 1; for (ll i = 1; i <= n; i++) { fact[i] = (fact[i - 1] * i) % mod; } return (fact[n] * invmod(fact[r]) % mod * invmod(fact[n - r]) % mod) % mod; } ll gcd(ll a, ll b) { if (a == 0) { return b; } return gcd(b % a, a); } ll lcm(ll a, ll b) { return (a * b) / gcd(a, b); } void dfs(ll i, vector<ll>adj[], bool visited[]) { visited[i] = 1; for (auto j : adj[i]) { if (visited[j] == 0) { dfs(j, adj, visited); } } } bool sortbysecdesc(const pair<ll, ll> &a, const pair<ll, ll> &b) { return a.second > b.second; } void solve(ll k) { ll n; cin >> n; ll w[n + 1], ans = 0; w[0] = 0; vector<pair<ll, ll>>p; for (ll i = 0; i < n; i++) { cin >> w[i + 1]; p.pb(mp(i + 1, w[i + 1])); ans += w[i + 1]; } ll in[n + 1]; // memset(in, -1, sizeof(in)); for (ll i = 0; i <= n; i++) { in[i] = -1; } for (ll i = 0; i < n - 1; i++) { ll u, v; cin >> u >> v; in[u]++, in[v]++; } cout << ans << ; sort(p.begin(), p.end(), sortbysecdesc); for (ll i = 0; i < p.size(); i++) { while (in[p[i].first] > 0) { ans += p[i].second; cout << ans << ; in[p[i].first]--; } } cout << endl; } int main() { #ifndef ONLINE_JUDGE // for getting input from input.txt freopen( input.txt , r , stdin); // for writing output to output.txt freopen( output.txt , w , stdout); #endif ios_base::sync_with_stdio(false); cin.tie(NULL); ll t = 1; cin >> t; ll k = 1; while (k <= t) { solve(k); k++; } return 0; } // f3=f2-f1,f4=-f1,f5=-f2,f6=f1-f2,f7=f1,f8=f2,f9=f2-f1, |
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_meta.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Fri 24 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser output calibration edge store.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_edge_store #
(parameter TCQ = 100,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
fall_lead, fall_trail, rise_lead, rise_trail,
// Inputs
clk, run_polarity, run_end, select0, select1, tap, run
);
input clk;
input run_polarity;
input run_end;
input select0;
input select1;
input [TAPCNTRWIDTH-1:0] tap;
input [TAPCNTRWIDTH-1:0] run;
wire [TAPCNTRWIDTH:0] trailing_edge = run > tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run
: tap - run;
wire run_end_this = run_end && select0 && select1;
reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r;
output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail;
assign fall_lead = fall_lead_r;
assign fall_trail = fall_trail_r;
assign rise_lead = rise_lead_r;
assign rise_trail = rise_trail_r;
wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r;
wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]
: rise_trail_r;
wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r;
wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]
: fall_trail_r;
always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns;
always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns;
always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns;
always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns;
endmodule // mig_7series_v2_3_poc_edge_store
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL.
module range_test;
range_entity dut();
initial begin
int i;
#1; // wait for signal assignments
if(dut.left_asc !== 2)
begin
$display("FAILED: left_asc should be %2d but is %2d", 2, dut.left_asc);
$finish();
end
if(dut.right_asc !== 4)
begin
$display("FAILED: right_asc should be %2d but is %2d", 2, dut.right_asc);
$finish();
end
if(dut.left_dsc !== 9)
begin
$display("FAILED: left_dsc should be %2d but is %2d", 2, dut.left_dsc);
$finish();
end
if(dut.right_dsc !== 3)
begin
$display("FAILED: right_dsc should be %2d but is %2d", 2, dut.right_dsc);
$finish();
end
if(dut.pow_left !== 16)
begin
$display("FAILED: pow_left should be %2d but is %2d", 16, dut.pow_left);
$finish();
end
if(dut.rem_left !== 2)
begin
$display("FAILED: rem_left should be %2d but is %2d", 2, dut.rem_left);
$finish();
end
for(i = $left(dut.ascending); i <= $right(dut.ascending); i++)
begin
if(2*i !== dut.ascending[i])
begin
$display("FAILED: ascending[%2d] should be %2d but is %2d", i, 2*i, dut.ascending[i]);
$finish();
end
end
for(i = $right(dut.descending); i <= $left(dut.descending); i++)
begin
if(3*i !== dut.descending[i])
begin
$display("FAILED: descending[%2d] should be %2d but is %2d", i, 3*i, dut.descending[i]);
$finish();
end
end
for(i = $left(dut.ascending_rev); i <= $right(dut.ascending_rev); i++)
begin
if(4*i !== dut.ascending_rev[i])
begin
$display("FAILED: ascending_rev[%2d] should be %2d but is %2d", i, 4*i, dut.ascending_rev[i]);
$finish();
end
end
for(i = $right(dut.descending_rev); i <= $left(dut.descending_rev); i++)
begin
if(5*i !== dut.descending_rev[i])
begin
$display("FAILED: descending_rev[%2d] should be %2d but is %2d", i, 5*i, dut.descending_rev[i]);
$finish();
end
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_4_V
`define SKY130_FD_SC_LP__O31A_4_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_4_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage3.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module stage3 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/phd.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/phd.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/phd.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int read() { int q = 0; char ch = ; while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) q = q * 10 + ch - 0 , ch = getchar(); return q; } const int N = 100005; double P[N][110], ans; int n, m, a[N], b[N]; double C(int d, int u) { if (d < u || d < 0 || u < 0) return 0; double ans = 1; for (register int i = d - u + 1; i <= d; ++i) ans *= i; for (register int i = 1; i <= u; ++i) ans /= i; return ans; } int main() { n = read(); for (register int i = 1; i <= n; ++i) a[i] = b[i] = read(), P[i][a[i]] = 1, ans += (a[i] == 0); m = read(); while (m--) { int x = read(), y = read(), k = read(); ans -= P[x][0]; for (register int i = 0; i <= a[x]; ++i) { double tmp = 0, all = C(b[x], k); for (register int j = 0; j <= k; ++j) tmp += P[x][i + j] * C(b[x] - i - j, k - j) * C(i + j, j); P[x][i] = tmp / all; } ans += P[x][0], b[x] -= k, b[y] += k; printf( %.10lf n , ans); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_SYMBOL_V
`define SKY130_FD_SC_HD__O2BB2AI_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_SYMBOL_V
|
#include <bits/stdc++.h> int main() { int N, A, B, C; char Error = 0; scanf( %d , &N); while (N) { A = N % 10; B = N % 100; C = N % 1000; if (A == 1) { N /= 10; } else if (B == 14) { N /= 100; } else if (C == 144) { N /= 1000; } else { Error = 1; break; } } puts(Error ? NO : YES ); return 0; } |
//
// Copyright (c) 2000 Steve Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// for3.16A - Template 1 - for(val1=0; val1 <= expr ; val1 = val1 + 1) some_action
//
module test ;
reg [3:0] val1;
reg [3:0] val2;
initial
begin
val2 = 0;
for(val1 = 0; val1 <= 4'ha; val1 = val1+1)
begin
val2 = val2 + 1;
end
if(val2 === 4'hb)
$display("PASSED");
else
begin
$display("FAILED val2 s/b 4'ha, but is %h",val2);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const int N = 1000010; template <class T> class BIT { T bit[N + 1]; int n; public: BIT() { n = N; memset(bit, 0, sizeof(bit)); } T sum(int i) { T s = 0; ++i; while (i > 0) { s += bit[i]; s %= MOD; i -= i & -i; } return s; } void add(int i, T x) { ++i; while (i <= n) { bit[i] += x; bit[i] %= MOD; i += i & -i; } } }; BIT<long long> T; int n, m, k; vector<pair<int, int>> in[1000010]; vector<pair<int, int>> out[1000010]; set<int> alive; set<pair<int, int>> itv; int main() { scanf( %d %d %d , &n, &m, &k); alive.insert(1); itv.insert(make_pair(0, 0)); for (int i = 0; i < (k); i++) { int a, b, c, d; scanf( %d %d %d %d , &a, &b, &c, &d); in[b].push_back(make_pair(a, c)); out[d + 1].push_back(make_pair(a, c)); } T.add(1, 1); for (int i = 1; i <= m; ++i) if (in[i].size() > 0 || out[i].size() > 0) { sort((in[i]).begin(), (in[i]).end()); sort((out[i]).begin(), (out[i]).end()); vector<pair<int, long long>> vals; for (int j = 0; j < (in[i].size()); j++) { pair<int, int> p = in[i][j]; auto it = itv.upper_bound(make_pair(p.second + 1, n)); --it; if (it->second < p.second + 1) { long long num = T.sum(p.second) - T.sum(it->second); num %= MOD; if (num < 0) num += MOD; vals.emplace_back(p.second + 1, i > 1 ? num : 0LL); if (i > 1) alive.insert(p.second + 1); } } for (pair<int, int> p : out[i]) { itv.erase(p); } for (int j = 0; j < (vals.size()); j++) { T.add(vals[j].first, vals[j].second); } for (int j = 0; j < (in[i].size()); j++) { pair<int, int> p = in[i][j]; itv.insert(p); auto it = alive.lower_bound(p.first); while (it != alive.end() && *it <= p.second) { int pos = *it; long long k = T.sum(pos) - T.sum(pos - 1); k %= MOD; T.add(pos, MOD - k); alive.erase(it++); } } } long long ret = T.sum(n); auto it = itv.end(); --it; ret = (ret - T.sum(it->second)) % MOD; if (ret < 0) ret += MOD; printf( %d n , (int)ret); return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_0_1,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_0_1,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=16,DIN_FROM=15,DIN_TO=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_0_1 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [13 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(2)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; template <class T, class U> inline void add_self(T &a, U b) { a += b; if (a >= mod) a -= mod; if (a < 0) a += mod; } template <class T, class U> inline void min_self(T &x, U y) { if (y < x) x = y; } template <class T, class U> inline void max_self(T &x, U y) { if (y > x) x = y; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { cout << t; ; if (sizeof...(v)) cerr << , ; _print(v...); } template <class T, class U> void print_m(const map<T, U> &m, int w = 3) { if (m.empty()) { cout << Empty << endl; return; } for (auto x : m) cout << ( << x.first << : << x.second << ), << endl; cout << endl; } template <class T, class U> void debp(const pair<T, U> &pr, bool end_line = 1) { cout << { << pr.first << << pr.second << } ; cout << (end_line ? n : , ); } template <class T> void print_vp(const T &vp, int sep_line = 0) { if (vp.empty()) { cout << Empty << endl; return; } if (!sep_line) cout << { ; for (auto x : vp) debp(x, sep_line); if (!sep_line) cout << } n ; cout << endl; } template <typename T> void print(const T &v, bool show_index = false) { int w = 2; if (show_index) { for (int i = 0; i < int((v).size()); i++) cout << setw(w) << i << ; cout << endl; } for (auto &el : v) cout << setw(w) << el << ; cout << endl; } template <typename T> void print_vv(const T &vv) { if (int((vv).size()) == 0) { cout << Empty << endl; return; } int w = 3; cout << setw(w) << ; for (int j = 0; j < int((*vv.begin()).size()); j++) cout << setw(w) << j << ; cout << endl; int i = 0; for (auto &v : vv) { cout << i++ << { ; for (auto &el : v) cout << setw(w) << el << ; cout << }, n ; } cout << endl; } int n, t; const int nax = 200; vector<double> glass(nax); void dfs(int g, int l) { if (l > n) return; if (glass[g] > 1) { double half = (glass[g] - 1) / 2; glass[g] = 1; int c1 = (g + l); int c2 = (g + l + 1); glass[c1] += half; glass[c2] += half; if (glass[c1] > 1) dfs(c1, l + 1); if (glass[c2] > 1) dfs(c2, l + 1); } } void bfs() { set<int> q; if (glass[1] > 1) q.insert(1); int l = 1; while (!q.empty()) { if (l > 10) break; set<int> nq; for (auto top : q) { double half = (glass[top] - 1) / 2; glass[top] = 1; int c1 = (top + l); int c2 = (top + l + 1); glass[c1] += half; glass[c2] += half; if (glass[c1] > 1) nq.insert(c1); if (glass[c2] > 1) nq.insert(c2); } q = nq; ++l; } } int main() { while (cin >> n >> t) { glass.clear(); glass.resize(nax); for (int i = 0; i < int(t); i++) { glass[1] += 1; bfs(); } int ed = (n * (n + 1)) / 2; int cnt = 0; for (int i = int(1); i < int(ed + 1); i++) if (glass[i] >= 1) ++cnt; cout << cnt << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int mp[500][500]; int rSum[500][500], cSum[500][500]; int dSumF[500][500], dSumB[500][500]; int blacks(int r1, int c1, int r2, int c2) { int ans = 1; if (r1 == r2 && c1 == c2) { ans = 1; } else if (r1 == r2) { if (c2 > c1) { ans = rSum[r1][c2] - rSum[r1][c1 - 1]; } else { ans = rSum[r1][c1] - rSum[r1][c2 - 1]; } } else if (c1 == c2) { if (r2 > r1) { ans = cSum[r2][c1] - cSum[r1 - 1][c1]; } else { ans = cSum[r1][c1] - cSum[r2 - 1][c1]; } } else if (abs(r1 - r2) == abs(c1 - c2)) { if (r1 < r2) { if (c1 < c2) { ans = dSumB[r2][c2] - dSumB[r1 - 1][c1 - 1]; } else { ans = dSumF[r2][c2] - dSumF[r1 - 1][c1 + 1]; } } else { if (c2 < c1) { ans = dSumB[r1][c1] - dSumB[r2 - 1][c2 - 1]; } else { ans = dSumF[r1][c1] - dSumF[r2 - 1][c2 + 1]; } } } else ans = 1; return ans; } int valid(int r1, int c1, int r2, int c2, int r3, int c3) { return !(blacks(r1, c1, r2, c2) || blacks(r1, c1, r3, c3) || blacks(r2, c2, r3, c3)); } int main() { scanf( %d %d n , &n, &m); int i, j, k; char c; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { scanf( %c , &c); mp[i][j] = c - 0 ; } scanf( n ); } for (i = 0; i <= n + 1; i++) { for (j = 0; j <= m + 1; j++) { rSum[i][j] = 0; cSum[i][j] = 0; dSumB[i][j] = 0; dSumF[i][j] = 0; } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { rSum[i][j] = rSum[i][j - 1] + mp[i][j]; cSum[i][j] = cSum[i - 1][j] + mp[i][j]; dSumF[i][j] = dSumF[i - 1][j + 1] + mp[i][j]; dSumB[i][j] = dSumB[i - 1][j - 1] + mp[i][j]; } } int ans = 0; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { for (k = 1; j + k <= m && i - k > 0; k++) { ans += valid(i, j, i, j + k, i - k, j); } for (k = 1; j - k > 0 && i - k > 0; k++) { ans += valid(i, j, i, j - k, i - k, j); } for (k = 1; j + k <= m && i + k <= n; k++) { ans += valid(i, j, i, j + k, i + k, j); } for (k = 1; j - k > 0 && i + k <= n; k++) { ans += valid(i, j, i, j - k, i + k, j); } k = 1; while (i - k > 0 && j + k <= m && j - k > 0) { ans += valid(i, j, i - k, j + k, i - k, j - k); k++; } k = 1; while (i + k <= n && j + k <= m && j - k > 0) { ans += valid(i, j, i + k, j + k, i + k, j - k); k++; } k = 1; while (j - k > 0 && i + k <= n && i - k > 0) { ans += valid(i, j, i + k, j - k, i - k, j - k); k++; } k = 1; while (j + k <= m && i + k <= n && i - k > 0) { ans += valid(i, j, i + k, j + k, i - k, j + k); k++; } } } printf( %d n , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:11:30 08/20/2015
// Design Name:
// Module Name: Sixth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Comparators
//Module Parameter
//W_Exp = 9 ; Single Precision Format
//W_Exp = 11; Double Precision Format
# (parameter W_Exp = 9)
/* # (parameter W_Exp = 12)*/
(
input wire [W_Exp-1:0] exp, //exponent of the fifth phase
output wire overflow, //overflow flag
output wire underflow //underflow flag
);
wire [W_Exp-1:0] U_limit; //Max Normal value of the standar ieee 754
wire [W_Exp-1:0] L_limit; //Min Normal value of the standar ieee 754
//Compares the exponent with the Max Normal Value, if the exponent is
//larger than U_limit then exist overflow
Greater_Comparator #(.W(W_Exp)) GTComparator (
.Data_A(exp),
.Data_B(U_limit),
.gthan(overflow)
);
//Compares the exponent with the Min Normal Value, if the exponent is
//smaller than L_limit then exist underflow
Comparator_Less #(.W(W_Exp)) LTComparator (
.Data_A(exp),
.Data_B(L_limit),
.less(underflow)
);
//This generate sentence creates the limit values based on the
//precision format
generate
if(W_Exp == 9) begin
assign U_limit = 9'hfe;
assign L_limit = 9'h01;
end
else begin
assign U_limit = 12'b111111111110;
assign L_limit = 12'b000000000001;
end
endgenerate
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ff_80x32_fwft_async.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ff_80x32_fwft_async (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [79:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [79:0] q;
output rdempty;
output [4:0] rdusedw;
output wrfull;
output [4:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [79:0] sub_wire1;
wire sub_wire2;
wire [4:0] sub_wire3;
wire [4:0] sub_wire4;
wire wrfull = sub_wire0;
wire [79:0] q = sub_wire1[79:0];
wire rdempty = sub_wire2;
wire [4:0] wrusedw = sub_wire3[4:0];
wire [4:0] rdusedw = sub_wire4[4:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdusedw (sub_wire4),
.rdfull (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
dcfifo_component.lpm_numwords = 32,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 80,
dcfifo_component.lpm_widthu = 5,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "80"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "80"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "80"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 80 0 INPUT NODEFVAL "data[79..0]"
// Retrieval info: USED_PORT: q 0 0 80 0 OUTPUT NODEFVAL "q[79..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 5 0 OUTPUT NODEFVAL "rdusedw[4..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL "wrusedw[4..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 80 0 data 0 0 80 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 80 0 @q 0 0 80 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 5 0 @rdusedw 0 0 5 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_80x32_fwft_async.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_80x32_fwft_async.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_80x32_fwft_async.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_80x32_fwft_async.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_80x32_fwft_async_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_80x32_fwft_async_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long xorsum(long long n, long long k) { if (k == 1) return n; int msb = (int)log2((double)n); if ((1ll << msb) > n) msb--; return (2ll << msb) - 1; } int main() { long long n, k; cin >> n >> k; cout << xorsum(n, k) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; template <int mod> struct ModInt { int x; ModInt() : x(0) {} ModInt(int64_t y) : x(y >= 0 ? y % mod : (mod - (-y) % mod) % mod) {} ModInt &operator+=(const ModInt &p) { if ((x += p.x) >= mod) x -= mod; return *this; } ModInt &operator-=(const ModInt &p) { if ((x += mod - p.x) >= mod) x -= mod; return *this; } ModInt &operator*=(const ModInt &p) { x = (int)(1LL * x * p.x % mod); return *this; } ModInt &operator/=(const ModInt &p) { *this *= p.inverse(); return *this; } ModInt operator-() const { return ModInt(-x); } ModInt operator+(const ModInt &p) const { return ModInt(*this) += p; } ModInt operator-(const ModInt &p) const { return ModInt(*this) -= p; } ModInt operator*(const ModInt &p) const { return ModInt(*this) *= p; } ModInt operator/(const ModInt &p) const { return ModInt(*this) /= p; } bool operator==(const ModInt &p) const { return x == p.x; } bool operator!=(const ModInt &p) const { return x != p.x; } ModInt inverse() const { int a = x, b = mod, u = 1, v = 0, t; while (b > 0) { t = a / b; swap(a -= t * b, b); swap(u -= t * v, v); } return ModInt(u); } ModInt pow(int64_t n) const { ModInt ret(1), mul(x); while (n > 0) { if (n & 1) ret *= mul; mul *= mul; n >>= 1; } return ret; } friend ostream &operator<<(ostream &os, const ModInt &p) { return os << p.x; } friend istream &operator>>(istream &is, ModInt &a) { int64_t t; is >> t; a = ModInt<mod>(t); return (is); } static int get_mod() { return mod; } }; using mint = ModInt<MOD>; long long mod_pow(long long x, long long n) { if (n == 0) return 1; long long res = mod_pow(x * x % MOD, n / 2); if (n & 1) res = res * x % MOD; return res; } long long power(long long num, long long pw) { if (pw == 0) return 1; long long res = power(num * num, pw / 2); if (pw & 1) res *= pw; return res; } long long ln(long long num, long long base) { int steps = 0; while (num > 1) { num /= base; steps++; } return steps; } int S = 100001; vector<int> Seive(S); void seive() { fill(Seive.begin(), Seive.end(), 0); Seive[0] = 0; Seive[1] = 0; for (long long i = 2; i <= S; i++) { if (Seive[i]) continue; for (long long j = i * i; j <= S; j += i) Seive[j] = 1; } } long long gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(int a, int b) { return (a / gcd(a, b)) * b; } bool sortbysec(const pair<long long, long long> &a, const pair<long long, long long> &b) { if (a.second == b.second) return a.first < b.first; return (a.second < b.second); } bool compare(const pair<string, int> &a, const pair<string, int> &b) { for (int i = 0; i < a.first.length(); i++) { if (i % 2 == 0) { if (a.first[i] < b.first[i]) return true; if (a.first[i] > b.first[i]) return false; } else { if (a.first[i] > b.first[i]) return true; if (a.first[i] < b.first[i]) return false; } } } int binarySearch(vector<pair<int, int>> a) { int r = a.size(); int l = 1; int ans = r; while (l <= r) { int mid = (l + r) / 2; int rem = mid, curr = 0; for (int i = 0; i < a.size(); i++) { if (a[i].first >= rem - 1) { if (a[i].second >= curr) { curr++; rem--; } } } if (rem <= 0) { ans = mid; l = mid + 1; } else { r = mid - 1; } } return ans; } void toggle(bool &x) { x ^= 1; } void solve() { int q; cin >> q; map<int, list<int>> m; int i = 0; while (q--) { int num; cin >> num; if (num == 1) { int x; cin >> x; m[x].push_back(i); i++; } else { int x, y; cin >> x >> y; if (x == y) continue; if (m[x].size() > m[y].size()) m[x].swap(m[y]); for (auto &i : m[x]) { m[y].push_back(i); } m.erase(x); } } vector<pair<int, int>> v; for (auto x : m) { for (auto y : x.second) { v.push_back({x.first, y}); } } sort(v.begin(), v.end(), sortbysec); for (auto x : v) { cout << x.first << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; for (int T = 1; T <= t; T++) { solve(); } } |
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at
//-- the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the
//-- time is 0
//------------------------------------------------------------------------------
//-- (c) Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-----------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_tx when to transmit the next bit
//-- __ __
//-- __| |_____________________________________________| |________________
//-- -> <- 1 clock cycle
//--
//------------------------------------------------------------------------------
module baudgen_tx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
always @(posedge clk)
if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is 0, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == 0) ? clk_ena : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; void bfs(long long root, list<long long> adj[], vector<long long> &level) { level[root] = 0; queue<long long> qu; qu.push(root); while (!qu.empty()) { long long cur = qu.front(); qu.pop(); for (auto it : adj[cur]) { if (level[it] == -1) { level[it] = level[cur] + 1; qu.push(it); } } } } void solve() { long long V, E, a, b; cin >> V >> E; list<long long> adj[V + 1]; vector<long long> level(V + 1, -1); for (long long i = 0; i < E; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } bfs(1, adj, level); map<long long, vector<long long> > mp; for (int i = 1; i <= V; i++) { mp[level[i]].push_back(i); } a = mp.size(); vector<long long> ans1, ans2; for (int i = 0; i < a; i += 2) { vector<long long> hold = mp[i]; for (auto it : hold) ans1.push_back(it); } for (int i = 1; i < a; i += 2) { vector<long long> hold = mp[i]; for (auto it : hold) ans2.push_back(it); } if (ans1.size() < ans2.size()) { cout << ans1.size() << endl; for (auto it : ans1) cout << it << ; cout << endl; } else { cout << ans2.size() << endl; for (auto it : ans2) cout << it << ; cout << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long q = 1; cin >> q; while (q--) { solve(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_PP_V |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
lab9_soc_nios2_qsys_0_jtag_debug_module_tck the_lab9_soc_nios2_qsys_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
lab9_soc_nios2_qsys_0_jtag_debug_module_sysclk the_lab9_soc_nios2_qsys_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic lab9_soc_nios2_qsys_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_instance_index = 0,
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_ir_width = 2,
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_mfg_id = 70,
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_sim_action = "",
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_type_id = 34,
// lab9_soc_nios2_qsys_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; int n, m, fa[N], f[N], d[N], head[N], xx, yy, ww, fr[N]; int ans; bool in[N], c[N]; struct nd { int x, y, w, id; } a[N]; bool operator<(nd a, nd b) { return a.w < b.w || (a.w == b.w && a.id < b.id); } struct ndd { int ne, to, w; } e[N]; void ins(int x, int y, int w) { static int cnt; e[++cnt].to = y; e[cnt].ne = head[x]; head[x] = cnt; e[cnt].w = w; } int gf(int x) { return fa[x] == x ? x : fa[x] = gf(fa[x]); } void dfs(int x) { for (int i = head[x]; i; i = e[i].ne) if (e[i].to != f[x]) { int y = e[i].to; f[y] = x; d[y] = d[x] + 1; fr[y] = e[i].w; dfs(y); } } void col(int x, int b) { c[x] = 1; for (int i = head[x]; i; i = e[i].ne) if (e[i].to != b) { int y = e[i].to; col(y, x); } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) { scanf( %d%d%d , &a[i].x, &a[i].y, &a[i].w); a[i].id = i; } xx = a[1].x, yy = a[1].y, ww = a[1].w; sort(a + 1, a + m + 1); for (int i = 1; i <= n; ++i) fa[i] = i; for (int i = 1; i <= m; ++i) { int fx = gf(a[i].x), fy = gf(a[i].y); if (fx != fy) { fa[fx] = fy; in[a[i].id] = 1; ins(a[i].x, a[i].y, a[i].w); ins(a[i].y, a[i].x, a[i].w); } } d[1] = 1; dfs(1); if (!in[1]) { while (xx != yy) { if (d[xx] < d[yy]) swap(xx, yy); ans = max(ans, fr[xx]); xx = f[xx]; } } else { ans = 1e9; col(yy, xx); for (int i = 1; i <= m; ++i) if (!in[a[i].id]) { if (c[a[i].x] ^ c[a[i].y]) ans = min(ans, a[i].w); } } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /stack:200000000 ) int t, n, m, j, ans, k, a, b, c, d, e, f, sum, i, sz, row, col, l; string s, s2, s3, s4; deque<pair<int, int> > v; void brainfuck(); int main() { ios_base::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); brainfuck(); return 0; } void brainfuck() { cin >> n >> m >> k; for (i = 1; i <= n; i++) { for (j = 1; i & 1 && j <= m; j++) v.push_back({i, j}); for (j = m; i % 2 == 0 && j >= 1; j--) v.push_back({i, j}); } for (j = 1; j <= k; j++) { if (j != k) a = 2; else a = v.size(); cout << a; while (a--) { cout << << v.front().first << << v.front().second; v.pop_front(); } cout << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int a[100010]; int b[100010]; while (scanf( %d , &a[0]) != EOF) { getchar(); int n = 1; while (scanf( %d , &a[n]) != EOF) { n++; getchar(); } sort(a, a + n); a[n] = 9999999; int h = 0; for (int i = 0; i < n; i++) { if (i == 0) { b[h++] = a[i]; } else if (a[i] != a[i - 1]) { b[h++] = a[i]; } } b[h] = 99999; int p = b[0]; int q = b[0]; int flag = 0; int ff = 0; for (int i = 1; i <= h; i++) { if (b[i] == b[i - 1] + 1) { p = b[i]; } else if (b[i] != b[i - 1] + 1) { ff = 1; if (flag == 1) { printf( , ); } flag = 1; if (p == q) { printf( %d , p); } else { printf( %d-%d , q, p); } p = b[i]; q = b[i]; } } printf( n ); } return 0; } |
module Section5_Top(
input DigitalLDir,
input DigitalRDir,
input reset_n,
output [3:0] outputs
/*output Len,
output Ldir,
output Ren,
output Rdir */
);
wire clk; //used for the oscillator's 2.08 MHz clock
wire clk_2; //used for slowed down, 5 Hz clock
//This is an instance of a special, built in module that accesses our chip's oscillator
OSCH #("2.08") osc_int ( //"2.03" specifies the operating frequency, 2.03 MHz. Other clock frequencies can be found in the MachX02's documentation
.STDBY(1'b0), //Specifies active state
.OSC(clk), //Outputs clock signal to 'clk' net
.SEDSTDBY()); //Leaves SEDSTDBY pin unconnected
//This module is instantiated from another file, 'Clock_Counter.v'
//It will take an input clock, slow it down based on parameters set inside of the module, and output the new clock. Reset functionality is also built-in
clock_counter counter_1(
.clk_i(clk),
.reset_n(reset_n),
.clk_o(clk_2));
//This module is instantiated from another file, 'State_Machine.v'
//It contains a Moore state machine that will take a clock and reset, and output LED combinations
Sec5_SM FSM_1(
.DigitalLDir(DigitalLDir),
.DigitalRDir(DigitalRDir),
.clk_i(clk_2),
.reset_n(reset_n),
.outputs(outputs)
/*.Len(Len),
.Ldir(Ldir),
.Ren(Ren),
.Rdir(Rdir)*/
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_1_V
`define SKY130_FD_SC_LP__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_1 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_1 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__XNOR3_PP_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 5; const long long infll = 1e18 + 5ll; const long double eps = 1e-9; const int maxn = 1e5 + 100; const long long maxlog = 21; const int P = 97; const int mod = 1e9 + 9; int n, m, lvl[maxn], up[maxlog][maxn], sub[maxn], par[maxn], ans[maxn]; std::vector<int> g[maxn]; bool ban[maxn]; void dfs1(int v = 1, int pr = 0) { lvl[v] = lvl[pr] + 1; up[0][v] = pr; for (int i = 1; i < 20; ++i) up[i][v] = up[i - 1][up[i - 1][v]]; for (auto to : g[v]) if (pr != to) { dfs1(to, v); } } int nn; void dfs2(int v, int pr) { sub[v] = 1; ++nn; for (auto to : g[v]) { if (to != pr && !ban[to]) { dfs2(to, v); sub[v] += sub[to]; } } } int getCentroid(int v, int pr) { for (auto to : g[v]) { if (to != pr && !ban[to] && sub[to] * 2 > nn) { return getCentroid(to, v); } } return v; } void decompose(int v, int pr) { nn = 0; dfs2(v, pr); int centroid = getCentroid(v, pr); par[centroid] = pr; ban[centroid] = 1; for (auto to : g[centroid]) { if (to == pr || ban[to]) continue; decompose(to, centroid); } } int lca(int a, int b) { if (lvl[a] > lvl[b]) swap(a, b); int d = lvl[b] - lvl[a]; for (int i = 0; i < maxlog; ++i) if (d & (1 << i)) b = up[i][b]; if (a == b) return b; for (int i = maxlog - 1; i >= 0; --i) if (up[i][a] != up[i][b]) a = up[i][a], b = up[i][b]; return up[0][a]; } int dist(int u, int v) { return lvl[u] + lvl[v] - 2 * lvl[lca(u, v)]; } void upd(int v) { int x = v; while (x != 0) { ans[x] = min(ans[x], dist(x, v)); x = par[x]; } } int query(int v) { int x = v, res = inf; while (x != 0) { res = min(res, ans[x] + dist(x, v)); x = par[x]; } return res; } int main() { ios_base::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); if (fopen( sorting .in , r )) freopen( sorting .in , r , stdin), freopen( sorting .out , w , stdout); ; cin >> n >> m; for (int i = 1, u, v; i < n; ++i) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } dfs1(); decompose(1, 0); memset(ans, inf, sizeof ans); upd(1); for (int i = 1, t, v; i <= m; ++i) { cin >> t >> v; if (t == 1) { upd(v); } else { cout << query(v) << n ; } } return 0; } |
#include<bits/stdc++.h> #define int long long using namespace std; const int mod=1e9+7; const int N=3e5+100; int fa[N]; //并查集,表示i的祖父fa[i] int begi; //记录可以随意放的点的位置(只有一个) int n,m; int a[N],b[N],c[N],in[N],ans[N]; //a[i]和b[i]表示i必须在a[i]的左边，b[i]的右边 //c[i]表示在缩成一个点的一段中的开头(b[i]的限制中能无限制的放位置) //in[i]表示入度,ans[i]表示答案 vector<int>g[N],h[N]; //h[i]存储i必须在h[i][1..n]左边 //g[i]表示缩点之后i必须在g[i][1..n]左边 bool vis[N]; //判断序列是否合法 int find(int x)//并查集搜爸爸 { if(fa[x]==x)return x; return fa[x]=find(fa[x]); } signed main() { scanf( %lld%lld ,&n,&m); for(int i=1;i<=n;i++) fa[i]=i; for(int i=1;i<=n;i++) { int x,y; scanf( %lld ,&x); if(x==0)begi=i;//储存无限制放的点的位置 else h[x].push_back(i);//记录顺序 } while(m--)//判能否组成序列 { int x,y; scanf( %lld%lld ,&x,&y); // cout<<x<< <<y<<endl; a[x]=y; b[y]=x; x=find(x),y=find(y); // cout<<x<< <<y<<endl; if(x==y)//如果成环 { puts( 0 ); return 0; } fa[x]=y;//合并 //无义，相当于把两个集合合并，用来判环后就没用了 //如果一个集合内的元素互相指向，就矛盾了 } for(int i=1;i<=n;i++) { if(b[i]==0)c[find(i)]=i; //缩点，也就是把一段互相关联的区间缩成一个点去做 //c[find(i)]也就是这一段区间的开头 //也就是说这一个开头不受这一段区间内的点的限制 //反而这个点可以限制这个区间内的其他点 for(int j=0;j<h[i].size();j++) { int x=h[i][j]; if(find(i)!=find(x)) { g[find(i)].push_back(find(x)); //因为把一段缩成一个点 //所以需要把这一段区间内的点的限制关系都转移到这一个点上 in[find(x)]++; //这一个点的入度(做拓扑排序) } } } queue<int>q; //拓扑排序专属队列 q.push(find(begi)); //从无限制的点开始 int ct=0; while(!q.empty()) { int x=q.front(); q.pop(); int t=c[x]; //找到缩点 while(t)//把这缩点里面的一个区间记录到答案内 { ans[++ct]=t; t=a[t]; } for(int i=0;i<g[x].size();i++)//拓扑排序pd操作 { int y=g[x][i]; in[y]--; if(in[y]==0)q.push(y); } } if(ct!=n)//如果答案数不等于n,就相当于不合法 { puts( 0 ); return 0; } vis[begi]=1; //判断序列前后关系是否合法 //因为begi没有限制，所以第一个判 for(int i=1;i<=n;i++) //按答案顺序说 { if(vis[ans[i]]==0)//如果按照限制关系还没被判断(就相当于i要在j的左边，可j先比i出现了) return puts( 0 ),0; for(int j=0;j<h[ans[i]].size();j++)//类似拓扑，把能在接下来队列里的点判为1 vis[h[ans[i]][j]]=1; } for(int i=1;i<=n;i++)//输出 { printf( %lld ,ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const long long ooo = 9223372036854775807ll; const int _cnt = 1000 * 1000 + 7; const int _p = 1000 * 1000 * 1000 + 7; const int N = 1001005; const double PI = acos(-1.0); const double eps = 1e-9; int o(int x) { return x % _p; } int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a / gcd(a, b) * b; } void file_put() { freopen( filename.in , r , stdin); freopen( filename.out , w , stdout); } int p[N], prime[N], phi[N], top, T, X, P, K, pp[N]; long long l, r, mid, ans; void init_prime(int N) { top = 0, phi[1] = 1; for (int i = 2; i <= N; ++i) { if (!p[i]) prime[++top] = i, phi[i] = i - 1; for (int j = 1; j <= top; ++j) { if ((long long)i * prime[j] > N) break; p[i * prime[j]] = 1; if (i % prime[j] == 0) { phi[i * prime[j]] = phi[i] * prime[j]; break; } phi[i * prime[j]] = phi[i] * phi[prime[j]]; } } } void init(int x) { pp[0] = 0; for (int i = 1; i <= top && (long long)prime[i] * prime[i] <= x; i++) if (x % prime[i] == 0) { pp[++pp[0]] = prime[i]; while (x % prime[i] == 0) x /= prime[i]; if (x == 1) return; if (!p[x]) { pp[++pp[0]] = x; return; } } if (x > 1) pp[++pp[0]] = x; } void dfs(int k, int op, long long s, long long n, long long &ans) { if (k > pp[0]) { ans += n / s * op; return; } dfs(k + 1, op, s, n, ans); if (s * pp[k] <= n) dfs(k + 1, -op, s * pp[k], n, ans); } long long Count(long long x) { long long ans = 0; dfs(1, 1, 1, x % P, ans); return x / P * phi[P] + ans; } int main() { scanf( %d , &T); init_prime(N - 5); while (T--) { scanf( %d%d%d , &X, &P, &K), init(P); K += Count(X), l = 1, r = 1e8; while (l <= r) { mid = (l + r) >> 1; if (Count(mid) >= K) ans = mid, r = mid - 1; else l = mid + 1; } printf( %I64d n , ans); } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:31:57 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.6 2006/06/26 08:39:42 wig Exp $
// $Date: 2006/06/26 08:39:42 $
// $Log: inst_a_e.v,v $
// Revision 1.6 2006/06/26 08:39:42 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No `defines in this module
module inst_a_e
//
// Generated Module inst_a
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_1
inst_1_e #(
.FOO(16)
) inst_1 (
);
// End of Generated Instance Port Map for inst_1
// Generated Instance Port Map for inst_10
inst_10_e #(
.FOO(32)
) inst_10 (
);
// End of Generated Instance Port Map for inst_10
// Generated Instance Port Map for inst_2
inst_2_e #(
.FOO(16)
) inst_2 (
);
// End of Generated Instance Port Map for inst_2
// Generated Instance Port Map for inst_3
inst_3_e #(
.FOO(16)
) inst_3 (
);
// End of Generated Instance Port Map for inst_3
// Generated Instance Port Map for inst_4
inst_4_e #(
.FOO(16)
) inst_4 (
);
// End of Generated Instance Port Map for inst_4
// Generated Instance Port Map for inst_5
inst_5_e inst_5 (
);
// End of Generated Instance Port Map for inst_5
// Generated Instance Port Map for inst_6
inst_6_e inst_6 (
);
// End of Generated Instance Port Map for inst_6
// Generated Instance Port Map for inst_7
inst_7_e #(
.FOO(32)
) inst_7 (
);
// End of Generated Instance Port Map for inst_7
// Generated Instance Port Map for inst_8
inst_8_e #(
.FOO(32)
) inst_8 (
);
// End of Generated Instance Port Map for inst_8
// Generated Instance Port Map for inst_9
inst_9_e #(
.FOO(32)
) inst_9 (
);
// End of Generated Instance Port Map for inst_9
// Generated Instance Port Map for inst_aa
inst_aa_e #(
.NO_DEFAULT("nodefault"),
.NO_NAME("noname"),
.WIDTH(15)
) inst_aa (
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
inst_ab_e #(
.WIDTH(31)
) inst_ab (
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
inst_ac_e inst_ac (
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
inst_ad_e inst_ad (
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
inst_ae_e inst_ae (
);
// End of Generated Instance Port Map for inst_ae
// Generated Instance Port Map for inst_m1
inst_m_e #(
.FOO(15)
) inst_m1 (
);
// End of Generated Instance Port Map for inst_m1
// Generated Instance Port Map for inst_m10
inst_m_e #(
.FOO(30)
) inst_m10 (
);
// End of Generated Instance Port Map for inst_m10
// Generated Instance Port Map for inst_m2
inst_m_e #(
.FOO(15)
) inst_m2 (
);
// End of Generated Instance Port Map for inst_m2
// Generated Instance Port Map for inst_m3
inst_m_e #(
.FOO(15)
) inst_m3 (
);
// End of Generated Instance Port Map for inst_m3
// Generated Instance Port Map for inst_m4
inst_m_e #(
.FOO(15)
) inst_m4 (
);
// End of Generated Instance Port Map for inst_m4
// Generated Instance Port Map for inst_m5
inst_m_e #(
.FOO(15)
) inst_m5 (
);
// End of Generated Instance Port Map for inst_m5
// Generated Instance Port Map for inst_m6
inst_m_e #(
.FOO(30)
) inst_m6 (
);
// End of Generated Instance Port Map for inst_m6
// Generated Instance Port Map for inst_m7
inst_m_e #(
.FOO(30)
) inst_m7 (
);
// End of Generated Instance Port Map for inst_m7
// Generated Instance Port Map for inst_m8
inst_m_e #(
.FOO(30)
) inst_m8 (
);
// End of Generated Instance Port Map for inst_m8
// Generated Instance Port Map for inst_m9
inst_m_e #(
.FOO(30)
) inst_m9 (
);
// End of Generated Instance Port Map for inst_m9
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
module top (
input wire i_clk,
input wire i_rst,
input wire i_ce,
input wire i_d1,
input wire i_d2,
output wire [23:0] io,
);
// BUFGs
wire clk;
BUFG bufg_1 (.I(i_clk), .O(clk));
genvar sa, e, i, sr;
generate begin
// SRTYPE
for (sa=0; sa<2; sa=sa+1) begin
localparam SRTYPE = (sa != 0) ? "SYNC" : "ASYNC";
// DDR_CLK_EDGE
for (e=0; e<2; e=e+1) begin
localparam EDGE = (e == 0) ? "SAME_EDGE" :
/*(e == 1) ?*/ "OPPOSITE_EDGE";
// Set, Reset or neither
for (sr=0; sr<3; sr=sr+1) begin
wire r;
wire s;
assign r = ((sr & 1) != 0) ? i_rst : 1'b0;
assign s = ((sr & 2) != 0) ? i_rst : 1'b0;
// INIT_Q
for (i=0; i<2; i=i+1) begin
localparam idx = sa*12 + e*6 + sr*2 + i;
wire [0:0] t;
wire [0:0] i_sig;
ODDR # (
.SRTYPE (SRTYPE),
.INIT (i == 1),
.DDR_CLK_EDGE (EDGE)
) tddr (
.C(clk), .CE(i_ce), .D1(i_d1), .D2(i_d2),
.R(r), .S(s),
.Q(t)
);
ODDR # (
.SRTYPE (SRTYPE),
.INIT (i == 1),
.DDR_CLK_EDGE (EDGE)
) oddr (
.C(clk), .CE(i_ce), .D1(i_d1), .D2(i_d2),
.R(r), .S(s),
.Q(i_sig)
);
// Cannot instance OBUFT because Yosys infers IOBs and
// inserts an inferred OBUF after the OBUFT...
assign io[idx] = (t == 1'b0) ? i_sig : 1'bz;
end
end
end
end
end endgenerate
endmodule
|
#include <bits/stdc++.h> int cmpfunc(const void* a, const void* b) { return (*(int*)a - *(int*)b); } int main() { int t, x, i, j, c; scanf( %d , &t); while (t--) { char n[101]; int m[101]; scanf( %s , &n); x = strlen(n); j = 0; c = 0; for (i = 0; i < x; i++) { if (n[i] == 1 ) c++; else if (c > 0) { m[j++] = c; c = 0; } } if (c > 0) m[j++] = c; qsort(m, j, sizeof(int), cmpfunc); c = 0; for (i = j - 1; i >= 0; i = i - 2) c = c + m[i]; printf( %d n , c); } } |
#include <bits/stdc++.h> using namespace std; int main() { int i, test, n, m, value; cin >> test; while (test--) { int s = 0; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> value; s += value; } if (s == m) { printf( YES n ); } else { printf( NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; t = 1; for (int r = 0; r < t; r++) { long long n, m, i, x, y, z, sum = 0; cin >> n >> m; vector<string> v(51); char a = a , b = A ; for (i = 0; i <= 50; i++) { if (b > Z ) b = A ; v[i].push_back(b); if (i >= 26) { v[i].push_back(a); a++; } b++; } x = 0, y = 0; vector<string> ans; string temp; while (y < m - 1) { ans.push_back(v[y]); y++; } x = y; for (i = 0; i < (n - m + 1); i++, x++) { cin >> temp; if (temp == NO ) { ans.push_back(ans[x - (m - 1)]); } else { ans.push_back(v[y]); y++; } } for (i = 0; i < n; i++) cout << ans[i] << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[10][10]; int d[10], b[10]; long long kq; void dequy(int k) { int i; long long sum; if (k == 6) { sum = a[d[1]][d[2]] + a[d[2]][d[1]] + a[d[3]][d[4]] + a[d[4]][d[3]]; sum += a[d[2]][d[3]] + a[d[3]][d[2]] + a[d[4]][d[5]] + a[d[5]][d[4]]; sum += a[d[3]][d[4]] + a[d[4]][d[3]]; sum += a[d[4]][d[5]] + a[d[5]][d[4]]; kq = max(kq, sum); return; } for (i = 1; i <= 5; i++) if (b[i] == 0) { b[i] = 1; d[k] = i; dequy(k + 1); b[i] = 0; } } void solve() { int i, j; memset(b, 0, sizeof(b)); dequy(1); cout << kq << endl; } void input() { int i, j; for (i = 1; i <= 5; i++) for (j = 1; j <= 5; j++) cin >> a[i][j]; solve(); } int main() { input(); fclose(stdin); fclose(stdout); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; int m; cin >> n >> m; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); int ans = 0; for (int i = 0; i < m; i++) { if (a[i] >= 0) break; ans += a[i]; } cout << abs(ans) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char s[100003], ss[100003]; int main() { int ans = 0; scanf( %s , s + 1); int len = strlen(s + 1); int n = 0; for (int i = 1; i <= len; i++) { if (n > 0 && ss[n] == s[i]) { n--; ans++; } else ss[++n] = s[i]; } if (ans % 2) printf( Yes n ); else printf( No n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1000000007; const long double eps = 1e-9; const long double pi = 3.141592653589793; const long double e = 2.718281828459045; int dp[100005], h[100005]; int n, mmm; int main() { memset(dp, -1, sizeof(dp)); memset(h, 0, sizeof(h)); mmm = 0; scanf( %d , &n); dp[0] = 0; dp[n + 1] = 0; for (int i = 1; i <= n; i++) { scanf( %d , &h[i]); } for (int i = 1; i <= n; i++) { dp[i] = min(dp[i - 1] + 1, h[i]); } for (int i = n; i >= 1; i--) { dp[i] = min(dp[i], dp[i + 1] + 1); mmm = max(mmm, dp[i]); } cout << mmm << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5; int a[maxn], b[maxn], c[maxn]; int n, K, i, j, x, y, bl, la; int main() { scanf( %d%d , &n, &K); x = K; for (i = 2; i <= x; i++) if (x % i == 0) { a[++la] = i; while (x % i == 0) { b[la]++; x /= i; } } for (i = 1; i <= n; i++) { scanf( %d , &x); for (j = 1; j <= la; j++) { y = 0; while (x % a[j] == 0) { y++; x /= a[j]; } c[j] = max(c[j], y); } } bl = 1; for (i = 1; i <= la; i++) if (c[i] < b[i]) { bl = 0; break; } if (bl) printf( Yes ); else printf( No ); return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for udp_ip_rx
*/
module test_udp_ip_rx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_ip_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [3:0] s_ip_version = 0;
reg [3:0] s_ip_ihl = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [15:0] s_ip_identification = 0;
reg [2:0] s_ip_flags = 0;
reg [12:0] s_ip_fragment_offset = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [15:0] s_ip_header_checksum = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [7:0] s_ip_payload_axis_tdata = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg m_udp_hdr_ready = 0;
reg m_udp_payload_axis_tready = 0;
// Outputs
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire m_udp_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [15:0] m_udp_source_port;
wire [15:0] m_udp_dest_port;
wire [15:0] m_udp_length;
wire [15:0] m_udp_checksum;
wire [7:0] m_udp_payload_axis_tdata;
wire m_udp_payload_axis_tvalid;
wire m_udp_payload_axis_tlast;
wire m_udp_payload_axis_tuser;
wire busy;
wire error_header_early_termination;
wire error_payload_early_termination;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_ip_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_version,
s_ip_ihl,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_header_checksum,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
m_udp_hdr_ready,
m_udp_payload_axis_tready
);
$to_myhdl(
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_udp_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_udp_source_port,
m_udp_dest_port,
m_udp_length,
m_udp_checksum,
m_udp_payload_axis_tdata,
m_udp_payload_axis_tvalid,
m_udp_payload_axis_tlast,
m_udp_payload_axis_tuser,
busy,
error_header_early_termination,
error_payload_early_termination
);
// dump file
$dumpfile("test_udp_ip_rx.lxt");
$dumpvars(0, test_udp_ip_rx);
end
udp_ip_rx
UUT (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_version(s_ip_version),
.s_ip_ihl(s_ip_ihl),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_header_checksum(s_ip_header_checksum),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
// Status signals
.busy(busy),
.error_header_early_termination(error_header_early_termination),
.error_payload_early_termination(error_payload_early_termination)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[100010]; int sieve[100010]; int main() { int n, i, j, m, x, a, b, ans, q, flag = 0, cnt = 0; scanf( %d , &n); for (i = 2; i <= n; i++) { if (!sieve[i]) { for (j = i * i; j <= n; j += i) sieve[j] = 1; for (j = i; j <= n; j = j * i) { arr[cnt++] = j; } } } printf( %d n , cnt); for (i = 0; i < cnt; i++) printf( %d , arr[i]); if (cnt) printf( n ); return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.92
// \ \ Application: MIG
// / / Filename: rd_bitslip.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:04 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Shifts and delays data from ISERDES, in both memory clock and internal
// clock cycles. Used to uniquely shift/delay each byte to align all bytes
// in data word
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: rd_bitslip.v,v 1.1 2011/06/02 07:18:04 mishra Exp $
**$Date: 2011/06/02 07:18:04 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/rd_bitslip.v,v $
******************************************************************************/
`timescale 1ps/1ps
module rd_bitslip #
(
parameter TCQ = 100
)
(
input clk,
input [1:0] bitslip_cnt,
input [1:0] clkdly_cnt,
input [5:0] din,
output reg [3:0] qout
);
reg din2_r;
reg [3:0] slip_out;
reg [3:0] slip_out_r;
reg [3:0] slip_out_r2;
reg [3:0] slip_out_r3;
//***************************************************************************
always @(posedge clk)
din2_r <= #TCQ din[2];
// Can shift data from ISERDES from 0-3 fast clock cycles
// NOTE: This is coded combinationally, in order to allow register to
// occur after MUXing of delayed outputs. Timing may be difficult to
// meet on this logic, if necessary, the register may need to be moved
// here instead, or another register added.
always @(bitslip_cnt or din or din2_r)
case (bitslip_cnt)
2'b00: // No slip
slip_out = {din[3], din[2], din[1], din[0]};
2'b01: // Slip = 0.5 cycle
slip_out = {din[4], din[3], din[2], din[1]};
2'b10: // Slip = 1 cycle
slip_out = {din[5], din[4], din[3], din[2]};
2'b11: // Slip = 1.5 cycle
slip_out = {din2_r, din[5], din[4], din[3]};
endcase
// Can delay up to 3 additional internal clock cycles - this accounts
// not only for delays due to DRAM, PCB routing between different bytes,
// but also differences within the FPGA - e.g. clock skew between different
// I/O columns, and differences in latency between different circular
// buffers or whatever synchronization method (FIFO) is used to get the
// data into the global clock domain
always @(posedge clk) begin
slip_out_r <= #TCQ slip_out;
slip_out_r2 <= #TCQ slip_out_r;
slip_out_r3 <= #TCQ slip_out_r2;
end
always @(posedge clk)
case (clkdly_cnt)
2'b00: qout <= #TCQ slip_out;
2'b01: qout <= #TCQ slip_out_r;
2'b10: qout <= #TCQ slip_out_r2;
2'b11: qout <= #TCQ slip_out_r3;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 30; unsigned long long n, k, x; unsigned long long a[300000]; unsigned long long dpL[300000]; unsigned long long dpR[300000]; int main() { int i, j; cin >> n >> k >> x; unsigned long long s = 0, MAX = 0; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n - 1; i++) { dpL[i + 1] = dpL[i] | a[i]; } for (i = n - 1; i > 0; i--) { dpR[i - 1] = dpR[i] | a[i]; } unsigned long long ans1 = a[0], ans2 = a[n - 1]; for (i = 0; i < k; i++) { ans1 = ans1 * x; ans2 = ans2 * x; } unsigned long long ans = max(ans1 | dpR[0], ans2 | dpL[n - 1]); for (i = 1; i < n - 1; i++) { unsigned long long ANS = a[i]; for (j = 0; j < k; j++) { ANS *= x; } ans = max(ans, ANS | dpL[i] | dpR[i]); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int N, K; int tosum; int begin1 = 1000000001, end1; map<int, pair<int, int> > m; vector<pair<int, int> > v; int main() { if (fopen( cf612d.in , r )) { freopen( cf612d.in , r , stdin); freopen( cf612d.out , w , stdout); } scanf( %d %d , &N, &K); for (int i = 0; i < N; i++) { int a, b; scanf( %d %d , &a, &b); m[a].first++; m[b].second++; } for (map<int, pair<int, int> >::iterator it = m.begin(); it != m.end(); it++) { tosum += it->second.first; if (tosum >= K && begin1 == 1000000001) { begin1 = it->first; } tosum -= it->second.second; if (tosum < K && begin1 != 1000000001) { end1 = it->first; v.push_back(make_pair(begin1, end1)); begin1 = 1000000001; } } printf( %u n , v.size()); for (int i = 0; i < v.size(); i++) { printf( %d %d n , v[i].first, v[i].second); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int dx[4] = {0, 1, -1, 0}, dy[4] = {-1, 0, 0, 1}; int n, m; char g[60][60]; bool col[60][60][2][4]; bool tmp[60][60][2][4]; bool inrange(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } void solve(int x, int y, int turn, int dir) { int nx = x + dx[dir], ny = y + dy[dir]; if (inrange(nx, ny) && g[nx][ny] == B && tmp[nx][ny][turn][dir] == false) { tmp[nx][ny][turn][dir] = tmp[nx][ny][1][dir] = true; solve(nx, ny, turn, dir); } if (turn == 1) return; for (int i = 0; i < 4; i++) { if (i == dir) continue; nx = x + dx[i], ny = y + dy[i]; if (inrange(nx, ny) && g[nx][ny] == B && tmp[nx][ny][1][i] == false) { tmp[nx][ny][1][i] = true; solve(nx, ny, 1, i); } } return; } bool check() { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (g[i][j] == B ) { bool ok = false; for (int x = 0; x < 2 && !ok; x++) for (int y = 0; y < 4 && !ok; y++) if (tmp[i][j][x][y]) ok = true; if (!ok) return false; } return true; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> g[i][j]; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (g[i][j] == B ) { memset(tmp, false, sizeof(tmp)); for (int k = 0; k < 4; k++) tmp[i][j][0][k] = tmp[i][j][1][k] = true, solve(i, j, 0, k); if (!check()) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Edge { int v, next; } edge[2050]; int e, ft[2050]; int a, n, m; bool rain[2050]; int x[2050], p[2050]; long long dp[2050][2050]; long long opt[2050]; int main() { int l, r; while (cin >> a >> n >> m) { e = 0; for (int i = 0; i <= a; i++) { rain[i] = false; for (int j = 0; j <= m; j++) dp[i][j] = (1ll << 60); ft[i] = -1; } for (int i = 0; i < n; i++) { scanf( %d%d , &l, &r); while (l < r) { rain[l++] = true; } } for (int i = 0; i < m; i++) { scanf( %d%d , x + i, p + i); edge[e].v = i; edge[e].next = ft[x[i]]; ft[x[i]] = e++; if (x[i] == 0) dp[0][i] = 0; } dp[0][m] = 0; p[m] = 0; opt[0] = 0; for (int i = 0; i < a; i++) { for (int j = 0; j <= m; j++) { if (dp[i][j] >= (1ll << 60)) continue; if (j < m || !rain[i]) dp[i + 1][j] = min(dp[i + 1][j], dp[i][j] + p[j]); } opt[i + 1] = (1ll << 60); for (int j = 0; j <= m; j++) opt[i + 1] = min(opt[i + 1], dp[i + 1][j]); for (int j = ft[i + 1]; j != -1; j = edge[j].next) { int idx = edge[j].v; dp[i + 1][idx] = min(dp[i + 1][idx], opt[i + 1]); } dp[i + 1][m] = min(dp[i + 1][m], opt[i + 1]); } long long ans = -1; if (opt[a] < (1ll << 60)) ans = opt[a]; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007LL; long long base = 10000007; long long large = 1000000000000000000LL; class UnionFind { private: vector<int> p, rank; public: UnionFind(int n) { rank.assign(n, 0); p.assign(n, 0); for (int i = 0; i < n; i++) { p[i] = i; } } int findSet(int i) { return (p[i] == i) ? i : (p[i] = findSet(p[i])); } bool isSameSet(int i, int j) { return findSet(i) == findSet(j); } void unionSet(int i, int j) { if (!isSameSet(i, j)) { int x = findSet(i), y = findSet(j); if (rank[x] > rank[y]) { p[y] = x; } else { p[x] = y; if (rank[x] == rank[y]) { rank[y]++; } } } } }; vector<vector<pair<int, int> > > adj; int n, m; vector<pair<pair<int, int>, int> > e; vector<int> dp; void dfs(int u, int pa, int val) { dp[u] = val; for (int j = 0; j < (int)adj[u].size(); j++) { int v = adj[u][j].first; int d = adj[u][j].second; if (v != pa) { dfs(v, u, val ^ d); } } } int main() { cin >> n >> m; UnionFind uf(n); adj.assign(n, vector<pair<int, int> >()); for (int i = 0; i < m; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); x--; y--; if (uf.isSameSet(x, y)) { e.push_back(pair<pair<int, int>, int>(pair<int, int>(x, y), z)); } else { uf.unionSet(x, y); adj[x].push_back(pair<int, int>(y, z)); adj[y].push_back(pair<int, int>(x, z)); } } dp.assign(n, 0); dfs(0, -1, 0); vector<int> mask; for (int i = 0; i < (int)e.size(); i++) { int x = e[i].first.first; int y = e[i].first.second; int z = e[i].second; int lo = dp[x] ^ dp[y] ^ z; mask.push_back(lo); } int cur = 0; for (int l = 30; l >= 0; l--) { int c = -1; for (int i = cur; i < (int)mask.size(); i++) { if (mask[i] & (1 << l)) { c = i; break; } } if (c == -1) continue; swap(mask[cur], mask[c]); for (int i = cur + 1; i < (int)mask.size(); i++) { if (mask[i] & (1 << l)) mask[i] ^= mask[cur]; } cur++; } vector<int> basis; for (int i = 0; i < cur; i++) { basis.push_back(mask[i]); } int l = 30; int dis = dp[n - 1]; for (int i = 0; i < (int)basis.size(); i++) { while (((1 << l) & basis[i]) == 0) l--; if ((1 << l) & dis) dis ^= basis[i]; } cout << dis << endl; return 0; } |
`default_nettype none
module execute_jump(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Event CTRL
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_IRQ_FRONT2BACK,
input wire iEVENT_IRQ_BACK2FRONT,
input wire iEVENT_END,
//State
input wire iSTATE_NORMAL,
//Previous - PREDICT
input wire iPREV_VALID,
input wire iPREV_EX_BRANCH,
input wire iPREV_EX_SYS_REG,
input wire [31:0] iPREV_PC,
input wire iPREV_BRANCH_PREDICT_ENA,
input wire iPREV_BRANCH_PREDICT_HIT,
//Ignore Predict
input wire iPREV_BRANCH_NORMAL_JUMP_INST,
//BRANCH
input wire iPREV_BRANCH_PREDICT_MISS_VALID, //not need jump, but predict jump
input wire iPREV_BRANCH_PREDICT_ADDR_MISS_VALID, //need jump, but predict addr is diffelent
input wire iPREV_BRANCH_IB_VALID,
input wire [31:0] iPREV_BRANCH_ADDR,
//SYSREG JUMP
input wire iPREV_SYSREG_IDT_VALID,
input wire iPREV_SYSREG_PDT_VALID,
input wire iPREV_SYSREG_PSR_VALID,
input wire [31:0] iPREV_SYSREG_ADDR,
/*************************************
Next
*************************************/
//Next
input wire iNEXT_BUSY,
output wire oNEXT_PREDICT_ENA,
output wire oNEXT_PREDICT_HIT,
output wire oNEXT_JUMP_VALID,
output wire [31:0] oNEXT_JUMP_ADDR,
//Ignore Predict
output wire oNEXT_NORMAL_JUMP_INST,
//Kaind of Jump
output wire oNEXT_TYPE_BRANCH_VALID,
output wire oNEXT_TYPE_BRANCH_IB_VALID,
output wire oNEXT_TYPE_SYSREG_IDT_VALID,
output wire oNEXT_TYPE_SYSREG_PDT_VALID,
output wire oNEXT_TYPE_SYSREG_PSR_VALID
);
wire jump_condition = iPREV_BRANCH_PREDICT_MISS_VALID || iPREV_BRANCH_PREDICT_ADDR_MISS_VALID;// || iPREV_BRANCH_IB_VALID || iPREV_SYSREG_IDT_VALID || iPREV_SYSREG_PDT_VALID || iPREV_SYSREG_PSR_VALID;
reg b_predict_ena;
reg b_predict_hit;
reg b_jump_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_BRANCH)begin// && (b_state == PL_STT_IDLE))begin
b_predict_ena <= iPREV_BRANCH_PREDICT_ENA;
b_predict_hit <= iPREV_BRANCH_PREDICT_HIT;
b_jump_valid <= jump_condition;
end
else begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
end
end
else begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
end
end
reg [31:0] b_jump_addr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_jump_addr <= 32'h0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_jump_addr <= 32'h0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID)begin
if(iPREV_EX_BRANCH)begin
if(iPREV_BRANCH_PREDICT_ADDR_MISS_VALID || iPREV_BRANCH_IB_VALID)begin
b_jump_addr <= iPREV_BRANCH_ADDR;
end
else if(iPREV_BRANCH_PREDICT_MISS_VALID)begin
b_jump_addr <= iPREV_PC;
end
end
else if(iPREV_EX_SYS_REG) begin
b_jump_addr <= iPREV_SYSREG_ADDR;
end
end
else begin
b_jump_addr <= 32'h0;
end
end
end
else begin
b_jump_addr <= 32'h0;
end
end
end
reg b_branch_normal_valid;
reg b_branch_ib_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_BRANCH)begin// && (b_state == PL_STT_IDLE))begin
b_branch_normal_valid <= iPREV_BRANCH_PREDICT_MISS_VALID || iPREV_BRANCH_PREDICT_ADDR_MISS_VALID;
b_branch_ib_valid <= iPREV_BRANCH_IB_VALID;
end
else begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
end
end
else begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
end
end
reg b_branch_normal_jump_inst;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_branch_normal_jump_inst <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_branch_normal_jump_inst <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_BRANCH)begin// && (b_state == PL_STT_IDLE))begin
b_branch_normal_jump_inst <= iPREV_BRANCH_NORMAL_JUMP_INST;
end
else begin
b_branch_normal_jump_inst <= 1'b0;
end
end
end
else begin
b_branch_normal_jump_inst <= 1'b0;
end
end
end
reg b_sysreg_idt_valid;
reg b_sysreg_pdt_valid;
reg b_sysreg_psr_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_SYS_REG)begin// && (b_state == PL_STT_IDLE))begin
b_sysreg_idt_valid <= iPREV_SYSREG_IDT_VALID;
b_sysreg_pdt_valid <= iPREV_SYSREG_PDT_VALID;
b_sysreg_psr_valid <= iPREV_SYSREG_PSR_VALID;
end
else begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
end
end
else begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
end
end
assign oNEXT_PREDICT_ENA = b_predict_ena;
assign oNEXT_PREDICT_HIT = b_predict_hit;
assign oNEXT_JUMP_VALID = b_jump_valid;
assign oNEXT_JUMP_ADDR = b_jump_addr;
assign oNEXT_NORMAL_JUMP_INST = b_branch_normal_jump_inst;
//Kaind of Jump
assign oNEXT_TYPE_BRANCH_VALID = b_branch_normal_valid;
assign oNEXT_TYPE_BRANCH_IB_VALID = b_branch_ib_valid;
assign oNEXT_TYPE_SYSREG_IDT_VALID = b_sysreg_idt_valid;
assign oNEXT_TYPE_SYSREG_PDT_VALID = b_sysreg_pdt_valid;
assign oNEXT_TYPE_SYSREG_PSR_VALID = b_sysreg_psr_valid;
endmodule // execute_jump
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_PP_BLACKBOX_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_PP_BLACKBOX_V
|
#include <bits/stdc++.h> namespace std { template <typename...> using void_t = void; } template <typename T, typename _ = void> struct is_container : std::false_type {}; template <typename... Ts> struct is_container_helper {}; template <typename T> struct is_container< T, typename std::conditional< false, is_container_helper<decltype(std::declval<T>().size()), decltype(std::declval<T>().begin()), decltype(std::declval<T>().end()), decltype(std::declval<T>().cbegin()), decltype(std::declval<T>().cend())>, void>::type> : public std::true_type {}; class IO { static const int bufSize = 1 << 20; char inBuf[bufSize], outBuf[bufSize]; char *ip1 = inBuf, *ip2 = inBuf; int goodReadBit = 1, op1 = -1, op2 = bufSize - 1; __inline__ __attribute__((always_inline)) int gc() { return ip1 == ip2 && (ip2 = (ip1 = inBuf) + fread(inBuf, 1, bufSize, stdin), ip1 == ip2) ? (goodReadBit = 0, EOF) : *ip1++; } template <typename T> __inline__ __attribute__((always_inline)) void __RI(T &x) { int ch = gc(), neg = 1; x = 0; for (; !(isdigit(ch) || ch == - || ch == EOF); ch = gc()) { } if (ch == EOF) return; if (ch == - ) neg = -1, ch = gc(); for (; isdigit(ch); ch = gc()) x = x * 10 + (ch - 48) * neg; } template <typename T> __inline__ __attribute__((always_inline)) void __RC(T &x) { int ch; while (isspace(ch = gc())) { } if (ch == EOF) return; x = ch; } __inline__ __attribute__((always_inline)) void __RS(std::string &x) { char ch; x.clear(); for (ch = gc(); isspace(ch); ch = gc()) { } if (ch == EOF) return; for (; !isspace(ch) && ch != EOF; ch = gc()) x.push_back(ch); } public: __inline__ __attribute__((always_inline)) IO &R(char &x) { return __RC(x), (*this); } __inline__ __attribute__((always_inline)) IO &R(unsigned char &x) { return __RC(x), (*this); } __inline__ __attribute__((always_inline)) IO &R(std::string &x) { return __RS(x), (*this); } template <typename T1, typename T2> __inline__ __attribute__((always_inline)) IO &R(std::pair<T1, T2> &x) { return R(x.first), R(x.second), (*this); } template <typename T, typename... Args> __inline__ __attribute__((always_inline)) IO &RA(T *a, int n) { for (int i = 0; i < n; ++i) R(a[i]); return (*this); } template <typename T, typename... Args> __inline__ __attribute__((always_inline)) IO &R(T &x, Args &...args) { return R(x), R(args...), (*this); } template <typename T, typename... Args> __inline__ __attribute__((always_inline)) IO &RA(T *a, int n, Args... args) { for (int i = 0; i < n; ++i) RA(a[i], args...); return (*this); } template <typename T> __inline__ __attribute__((always_inline)) typename std::enable_if<std::is_integral<T>::value, IO>::type & R(T &x) { return __RI(x), (*this); } template <typename T> __inline__ __attribute__((always_inline)) typename std::enable_if<is_container<T>::value, IO>::type & R(T &x) { for (auto &i : x) R(i); return (*this); } template <typename T> __inline__ __attribute__((always_inline)) typename std::enable_if< std::is_void<std::void_t<decltype(std::declval<T>().read())>>::value, IO>::type & R(T &x) { return x.read(), (*this); } private: char space = ; __inline__ __attribute__((always_inline)) void pc(const char &x) { if (op1 == op2) flush(); outBuf[++op1] = x; } template <typename T> __inline__ __attribute__((always_inline)) void __WI(T x) { static char buf[sizeof(T) * 16 / 5]; static int len = -1; if (x >= 0) { do { buf[++len] = x % 10 + 48, x /= 10; } while (x); } else { pc( - ); do { buf[++len] = -(x % 10) + 48, x /= 10; } while (x); } while (len >= 0) { pc(buf[len]), --len; } } public: __inline__ __attribute__((always_inline)) void flush() { fwrite(outBuf, 1, op1 + 1, stdout), op1 = -1; } __inline__ __attribute__((always_inline)) IO &W(const char &x) { return pc(x), (*this); } __inline__ __attribute__((always_inline)) IO &W(const char *x) { while (*x != 0 ) pc(*(x++)); return (*this); } __inline__ __attribute__((always_inline)) IO &W(const std::string &x) { return W(x.c_str()), (*this); } template <typename T1, typename T2> __inline__ __attribute__((always_inline)) IO &W(const std::pair<T1, T2> &x) { WS(x.first); W(x.second); return (*this); } __inline__ __attribute__((always_inline)) IO &WL() { return W( n ), (*this); } template <typename T> __inline__ __attribute__((always_inline)) IO &WL(const T &x) { return W(x), W( n ), (*this); } __inline__ __attribute__((always_inline)) IO &WS() { return W(space), (*this); } template <typename T> __inline__ __attribute__((always_inline)) IO &WS(const T &x) { return W(x), W(space), (*this); } template <typename T> __inline__ __attribute__((always_inline)) IO &WA(T *a, int n) { for (int i = 0; i < n; i++) WS(a[i]); WL(); return (*this); } template <typename T, typename... Args> __inline__ __attribute__((always_inline)) IO &W(const T &x, const Args &...args) { W(x), W(space), W(args...); return (*this); } template <typename T, typename... Args> __inline__ __attribute__((always_inline)) IO &WS(const T &x, const Args &...args) { return W(x), W(space), W(args...), W(space), (*this); } template <typename... Args> __inline__ __attribute__((always_inline)) IO &WL(const Args &...args) { return W(args...), W( n ), (*this); } template <typename T, typename... Args> __inline__ __attribute__((always_inline)) IO &WA(T *a, int n, Args... args) { for (int i = 0; i < n; i++) WA(a[i], args...); return (*this); } template <typename T> __inline__ __attribute__((always_inline)) typename std::enable_if<std::is_integral<T>::value, IO>::type & W(const T &x) { return __WI(x), (*this); } template <typename T> __inline__ __attribute__((always_inline)) typename std::enable_if<is_container<T>::value, IO>::type & W(const T &x) { for (auto &i : x) WS(i); WL(); return (*this); } template <typename T> __inline__ __attribute__((always_inline)) typename std::enable_if< std::is_void<std::void_t<decltype(std::declval<T>().write())>>::value, IO>::type & W(const T &x) { return x.write(), (*this); } template <typename T> __inline__ __attribute__((always_inline)) IO &operator>>(T &x) { R(x); return (*this); } template <typename T> __inline__ __attribute__((always_inline)) IO &operator<<(const T &x) { W(x); return (*this); } int good() { return goodReadBit; } IO() {} ~IO() { flush(); } } io; const std::int32_t INF = 0x3f3f3f3f; const std::int64_t INFL = 0x3f3f3f3f3f3f3f3f; using namespace std; namespace Math { template <typename T, typename T2> T qpow(T a, T2 b, const int &MOD) { T ans = 1; for (; b; b >>= 1) { if (b & 1) ans = (a * ans) % MOD; a = (a * a) % MOD; } return ans; } template <typename T> T exgcd(T l, T r, T &x, T &y) { if (!r) { x = 1, y = 0; return l; } else { int d = exgcd(r, l % r, y, x); y -= l / r * x; return d; } } template <typename T> T inv(T a, const int &MOD) { return qpow(a, MOD - 2, MOD); } template <typename T> T exinv(T a, const int &MOD) { T x, y; exgcd(a, MOD, x, y); x %= MOD; return x + ((x >> (sizeof(T) * 8 - 1)) & MOD); } template <typename T, T MOD> struct ModInt { T x; ModInt(T x = 0) : x(x) { while (x < 0) x += MOD; } ModInt<T, MOD> operator+=(const ModInt<T, MOD> &y) { x += y.x - MOD; x += (x >> (sizeof(T) * 8 - 1)) & MOD; return (*this); } ModInt<T, MOD> operator-=(const ModInt<T, MOD> &y) { x = x - y.x; x += (x >> (sizeof(T) * 8 - 1)) & MOD; return (*this); } ModInt<T, MOD> operator*=(const ModInt<T, MOD> &y) { x = x * y.x % MOD; return (*this); } ModInt<T, MOD> operator/=(const ModInt<T, MOD> &y) { x = x * inv(y.x, MOD) % MOD; return (*this); } ModInt<T, MOD> pow(int64_t p) { return x = qpow(x, p, MOD), *this; } void write() const { io.W(x); } void read() { io.R(x); x %= MOD; if (x < 0) x += MOD; } }; template <typename T, T MOD> ModInt<T, MOD> operator+(ModInt<T, MOD> a, const ModInt<T, MOD> &b) { a += b; return a; } template <typename T, T MOD> ModInt<T, MOD> operator-(ModInt<T, MOD> a, const ModInt<T, MOD> &b) { a -= b; return a; } template <typename T, T MOD> ModInt<T, MOD> operator*(ModInt<T, MOD> a, const ModInt<T, MOD> &b) { a *= b; return a; } template <typename T, T MOD> ModInt<T, MOD> operator/(ModInt<T, MOD> a, const ModInt<T, MOD> &b) { a /= b; return a; } template <typename T, T MOD> bool operator==(const ModInt<T, MOD> &a, const ModInt<T, MOD> &b) { return a.x == b.x; } } // namespace Math using mint = Math::ModInt<int64_t, int(1e9 + 7)>; int main() { int n, q; io.R(n, q); vector<mint> a(n); io.R(a); a.insert(a.begin(), mint(0)); vector<mint> preSum(n + 1), preSquareSum(n + 1); partial_sum(a.begin(), a.end(), preSum.begin()); partial_sum(a.begin(), a.end(), preSquareSum.begin(), [](mint a, mint b) { return a + b * b; }); mint inv2 = mint(1) / mint(2); mint inv6 = mint(1) / mint(6); while (q--) { int l, r, d; io.R(l, r, d); mint len = r - l + 1; mint x = ((preSum[r] - preSum[l - 1]) * mint(2) / len - (len - mint(1)) * mint(d)) * inv2; mint y = x * x * len + x * (len - mint(1)) * len * mint(d) + len * (mint(2) * len * len - mint(3) * len + mint(1)) * mint(d) * mint(d) * inv6; mint z = (preSquareSum[r] - preSquareSum[l - 1]); io.WL(y == z ? Yes : No ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// A test that a package import declaration can preceed a parameter port list
// in an interface declaration. See 25.3 of the 1800-2017 LRM.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
package bus_pkg;
parameter WIDTH = 8;
endpackage
interface simple_bus
import bus_pkg::*; // Import preceding parameters.
#(p_width = WIDTH)
(input logic clk);
logic req, gnt;
logic [p_width-1:0] addr;
logic [p_width-1:0] data;
modport slave(input req, addr, clk,
output gnt,
input data);
modport master(input gnt, clk,
output req, addr,
output data);
endinterface
module mem(simple_bus a);
logic avail;
always @(posedge a.clk)
a.gnt <= a.req & avail;
initial begin
if ($bits(a.data) != 8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module t (input clk);
simple_bus sb(clk);
mem mem(sb.slave);
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr int MAXN = 200000; int x[MAXN + 2]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> x[i]; sort(x, x + n); int ans = INT_MAX; for (int i = 0; i < n / 2; i++) ans = min(ans, x[i + n / 2] - x[i]); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC diagnostic warning -Wall int main() { int n; scanf( %d , &n); vector<vector<int> > sec(n); for (typeof(n) i = (0); i < (n); i++) { int k; scanf( %d , &k); sec[i].resize(k); for (typeof(k) j = (0); j < (k); j++) scanf( %d , &sec[i][j]); sort((sec[i]).begin(), (sec[i]).end()); } int count = 0; for (typeof(n) i = (0); i < (n); i++) { int k = int(sec[i].size()); if (not k) continue; int lasth = sec[i][0]; ; int l = (i - 1 + n) % n; int r = (i + 1) % n; for (typeof(k) j = (1); j < (k); j++) { int nl = lower_bound((sec[l]).begin(), (sec[l]).end(), sec[i][j]) - lower_bound((sec[l]).begin(), (sec[l]).end(), lasth); int nr = lower_bound((sec[r]).begin(), (sec[r]).end(), sec[i][j]) - lower_bound((sec[r]).begin(), (sec[r]).end(), lasth); if (nl != nr) count++; lasth = sec[i][j]; } } printf( %d n , count); } |
#include <bits/stdc++.h> using namespace std; long long n, x, k, lb, ub, ans = -1; int main() { long long l, r; scanf( %lld%lld%lld%lld , &n, &l, &r, &k); x = (r >= l ? r - l + 1 : r + n - l + 1) % n; for (long long i = k, j, r; i; i = j) { j = k / (k / i + 1); r = k / i; ub = min(2 * n, i); lb = max(n, j + 1); ub = min(ub, min((2 * n + k - 2 * x + 1) / (r + 1), (k - x) / r)); lb = max(lb, (k - 2 * x + r - 1) / r); if (ub >= lb) ans = max(ans, ub); } if (x <= k && k <= x * 2) ans = max(ans, n + min(k - x, x - 1) + n - x + 1); if (!x && k == n) ans = max(ans, n + 1); printf( %lld n , ~ans ? ans - n : ans); } |
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ff
// ============================================================
// File Name: gl_dff5er.v
// Megafunction Name(s):
// lpm_ff
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 151 09/26/2007 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gl_dff5er (
clock,
data,
enable,
sclr,
q);
input clock;
input [4:0] data;
input enable;
input sclr;
output [4:0] q;
wire [4:0] sub_wire0;
wire [4:0] q = sub_wire0[4:0];
lpm_ff lpm_ff_component (
.enable (enable),
.sclr (sclr),
.clock (clock),
.data (data),
.q (sub_wire0)
// synopsys translate_off
,
.aclr (),
.aload (),
.aset (),
.sload (),
.sset ()
// synopsys translate_on
);
defparam
lpm_ff_component.lpm_fftype = "DFF",
lpm_ff_component.lpm_type = "LPM_FF",
lpm_ff_component.lpm_width = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: SCLR NUMERIC "1"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "5"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
// Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
// Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
// Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5er.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5er.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5er.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5er.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5er_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5er_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } string s; int main() { int t, cas = 1; cin >> s; int n = ((int)(s).size()); for (int i = 1; i <= n / 2; i++) { int cnt = 0; for (int j = 0; j < n - i; j++) { if (s[j] == s[j + i]) cnt++; else cnt = 0; if (cnt == i) { s = s.substr(0, j - i + 1) + s.substr(j + 1, n - j - 1); n -= i; i = 0; break; } } } cout << s << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_TB_V
`define SKY130_FD_SC_MS__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_TB_V
|
#include <bits/stdc++.h> using namespace std; int n, a, b, i, p = 2e9; int main() { for (cin >> n; i < n; i++) { cin >> a >> b; if (max(a, b) <= p) p = max(a, b); else if (a <= p) p = a; else if (b <= p) p = b; else return cout << NO , 0; } cout << YES ; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
inout [ 3: 0] bidir_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 3: 0] bidir_port;
wire clk_en;
reg [ 3: 0] data_dir;
wire [ 3: 0] data_in;
reg [ 3: 0] data_out;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[3 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[3 : 0];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> months = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; const int MAX = 1e5 + 55; const int inf = 1e9 + 77; const int MOD = 1e9 + 7; const double PI = acos(-1.0); const double eps = 1e-7; int main() { int n, k; scanf( %d , &n); scanf( %d , &k); if (n > (long long)k * (long long)(k - 1)) { printf( NO ); return 0; } printf( YES n ); int need = n; for (int i = 1; i <= k && need; ++i) { for (int j = i + 1; j <= k && need; ++j) { printf( %d %d n , i, j); --need; if (need) { printf( %d %d n , j, i); --need; } } } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_IBUFDISABLE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 04/04/11 - CR 604808 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/10/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_IBUFDISABLE (O, I, IB, IBUFDISABLE);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IBUFDS_IBUFDISABLE";
output O;
input I;
input IB;
input IBUFDISABLE;
wire i_in, ib_in, ibufdisable_in;
reg o_out;
wire out_val;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((ibufdisable_in === 1'b1) ? out_val : ((ibufdisable_in === 1'b0) ? o_out : 1'bx));
assign i_in = I;
assign ib_in = IB;
assign ibufdisable_in = IBUFDISABLE;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
#1 $finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
default : begin
assign out_val = 1'b0;
end
endcase
endgenerate
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int n, k; int p[55]; string t; void getp() { int j = 0; p[0] = p[1] = 0; for (int i = 1; i < t.length(); ++i) { while (j && t[j] != t[i]) j = p[j]; if (t[j] == t[i]) j++; p[i + 1] = j; } } void build() { getp(); string ans = t; int cnt = 1; while (cnt < k) { for (int i = p[t.length()]; i < t.length(); ++i) ans.append(1, t[i]); cnt++; } cout << ans; } int main() { cin >> n >> k >> t; build(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<long long> bs(n); for (auto &x : bs) cin >> x; if (count(bs.begin(), bs.end(), 0) == n) { cout << YES << endl; for (int _ = 0; _ < (n); ++_) cout << 1 << ; cout << endl; return 0; } auto prv = [&](int i) { return (i + n - 1) % n; }; bs.push_back(bs[0]); for (int i = 0; i < (n); ++i) if (bs[i] > bs[prv(i)]) { vector<long long> a(n); a[i] = bs[i]; for (int k = prv(i); k != i; k = prv(k)) { int j = prv(k), l = (k + 1) % n; long long x; long long dif = bs[j] - bs[k]; if (dif < 0) x = 0; else { x = 1 + dif / a[l]; } a[k] = bs[k] + x * a[l]; } cout << YES << endl; for (auto &x : a) cout << x << ; cout << endl; return 0; } cout << NO << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 2410; int n, l, r, a[N]; vector<int> p; tuple<int, int, int> tmp[2]; vector<tuple<int, int, int>> ans; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = 1, x; i <= 3 * n; i++) cin >> x, a[x] = 1; for (int i = 1; i <= 6 * n; i++) p.push_back(i); for (int i = 1; i <= 2 * n; i++) { l = 0, r = p.size() - 1; while (l < r && a[p[l]] == a[p[l + 1]] && a[p[l]] == a[p[l + 2]]) tmp[a[p[l]]] = {p[l], p[l + 1], p[l + 2]}, l += 3; while (l < r && a[p[r]] == a[p[r - 1]] && a[p[r]] == a[p[r - 2]]) tmp[a[p[r]]] = {p[r - 2], p[r - 1], p[r]}, r -= 3; if (l < r) { for (int j = l; j + 2 <= r; j++) if ((i & 1) == a[p[j]] && (i & 1) == a[p[j + 1]] && (i & 1) == a[p[j + 2]]) { ans.push_back({p[j], p[j + 1], p[j + 2]}); goto next; } } ans.push_back(tmp[i & 1]); next: p.erase(find(p.begin(), p.end(), get<0>(ans.back()))); p.erase(find(p.begin(), p.end(), get<1>(ans.back()))); p.erase(find(p.begin(), p.end(), get<2>(ans.back()))); } for (const auto &it : ans) cout << get<0>(it) << << get<1>(it) << << get<2>(it) << endl; } |
#include <bits/stdc++.h> using namespace std; int n, m; pair<int, int> answer[404]; set<pair<int, int> > S; set<pair<int, int> >::iterator it, ii; bool check(pair<int, int> c) { ii = S.lower_bound(make_pair(c.first, 0)); if (ii != S.end()) { if (c.first + c.second > (*ii).first) return false; } if (ii != S.begin()) { ii--; if (c.first < (*ii).first + (*ii).second) return false; } return true; } int main() { scanf( %d , &n); S.insert(make_pair(0, 1)); for (int i = 0; i < n; ++i) { int x, y; scanf( %d %d , &x, &y); pair<int, int> c = make_pair(x, y); if (check(c)) { answer[i] = c; S.insert(c); continue; } for (it = S.begin(); it != S.end(); it++) { c = make_pair((*it).first + (*it).second, y); if (check(c)) { S.insert(c); answer[i] = c; break; } } } for (int i = 0; i < n; ++i) printf( %d %d n , answer[i].first, answer[i].second + answer[i].first - 1); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int ex[n], e[n]; int temp = n; int i = 0; while (temp--) { cin >> ex[i] >> e[i]; i++; } int sum = e[0], m = e[0]; for (int j = 1; j < n; j++) { sum = sum - ex[j] + e[j]; if (sum > m) { m = sum; } } cout << m << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; int main() { long long v, w1, w2, v1, v2; cin >> v >> w1 >> w2 >> v1 >> v2; long long x = max(v1, v2); if (x * x >= v) { if (v1 < v2) swap(v1, v2), swap(w1, w2); long long ans = 0; for (int i = 0; i <= v / v1; i++) { ans = max(ans, i * w1 + (v - i * v1) / v2 * w2); } cout << ans << endl; } else { if (1.0 * w1 / v1 > 1.0 * w2 / v2) { swap(v1, v2), swap(w1, w2); } long long ans = 0; for (int i = 0; i < v2; i++) { ans = max(ans, i * w1 + (v - i * v1) / v2 * w2); } cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_M_V
`define SKY130_FD_SC_LP__A2BB2O_M_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_m (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_m (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_BLACKBOX_V
/**
* udp_isolatch_pp$PKG$s: Power isolating latch. Includes VPWR, KAPWR,
* and VGND power pins with active low sleep
* pin (SLEEP_B).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_isolatch_pp$PKG$s (
Q ,
D ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_V |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate left hand variable index
module main ;
reg [3:0] a,b;
reg c;
reg error;
always @(c or b)
a[b] = c;
initial
begin
#1 ;
a = 4'b1111;
error = 0;
b = 1'b0;
c = 1'b0;
#1 ;
if(a != 4'b1110)
begin
$display("FAILED - var index - a = %b, [b] = %d, c=%b",a,b,c);
error = 1;
end
#1 ;
b = 1;
#1 ;
if(a != 4'b1100)
begin
$display("FAILED - var index - a = %b, [b] = %d, c=%b",a,b,c);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200009; const long long MOD = 119 << 23 | 1; class { public: bool g[1 << 22]; int a[1 << 22]; int N, M, n, m; void solve() { int _; cin >> _; while (_--) { cin >> n >> m; N = (1 << n) - 1; M = (1 << m) - 1; for (int i = 1; i <= N; ++i) cin >> a[i]; for (int i = M + 1; i <= N; ++i) g[i] = 1; for (int i = M; i; --i) { if (a[i << 1] < a[i << 1 | 1]) { g[i] = g[i << 1 | 1]; } else { g[i] = g[i << 1]; } } vector<int> ans; int rt = 1; for (int i = 0; i < N - M; ++i) { while (!g[rt]) rt++; ans.push_back(rt); down(rt); } long long sum = 0; for (int i = 1; i <= M; ++i) sum += a[i]; cout << sum << n ; for (int i : ans) cout << i << ; cout << n ; for (int i = 1; i <= N; ++i) g[i] = a[i] = 0; } } void down(int rt) { int lson = rt << 1, rson = rt << 1 | 1; if (a[lson] == 0 && a[rson] == 0) { a[rt] = 0; g[rt] = 0; return; } if (a[lson] > a[rson]) { a[rt] = a[lson]; down(lson); } else { a[rt] = a[rson]; down(rson); } if (rt <= M) { if (a[lson] > a[rson]) g[rt] = g[lson]; else g[rt] = g[rson]; } } } NSPACE; int main() { ; ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); NSPACE.solve(); } |
#include <bits/stdc++.h> using namespace std; double revs, a, b, c, d, C, totdist; const double pi = atan(1) * 4; int n, r, v, s, f; double distcovered(double t) { return max(r * (t + sin(t)), r * (t - sin(t))); } int main() { cout << fixed << setprecision(8); cin >> n >> r >> v; for (int c = 0; c < n; c++) { scanf( %d%d , &s, &f); a = f - s; a = a / 2; double up, low; low = 0; up = a / r + 2 * pi; for (int c = 0; c < 100; c++) { double mid = (low + up) / 2; b = distcovered(mid); if (b == a) break; else if (b > a) up = mid; else low = mid; } double mid = (low + up) / 2; double speed = (double)v / r; double time = mid / speed * 2; printf( %.8f n , time); } return 0; } |
/*
* File: top_pss.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* top module for pippo sub-system, includes
* pippo core, imc, dmc, icbu, dcbu
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module top_pss(
clk, rst,
txd, rxd,
dsu_rst,
dsu_burn_enable,
dsu_sram_we,
iimx_adr_o,
iimx_rqt_o,
iimx_rty_i,
iimx_ack_i,
iimx_err_i,
iimx_dat_i,
iimx_adr_i,
dimx_adr_o,
dimx_rqt_o,
dimx_we_o,
dimx_sel_o,
dimx_dat_o,
dimx_dat_i,
dimx_ack_i,
dimx_err_i
);
//
// I/O
//
input clk;
input rst;
input dsu_rst;
input dsu_burn_enable;
output dsu_sram_we;
output txd;
input rxd;
output [31:0] iimx_adr_o;
output iimx_rqt_o;
output [31:0] iimx_dat_i;
output iimx_ack_i;
output iimx_rty_i;
output iimx_err_i;
output [31:0] iimx_adr_i;
output [31:0] dimx_adr_o;
output dimx_rqt_o;
output dimx_we_o;
output [3:0] dimx_sel_o;
output [31:0] dimx_dat_o;
output [31:0] dimx_dat_i;
output dimx_ack_i;
output dimx_err_i;
//
// interconnections
//
wire [31:0] iimx_adr_o;
wire iimx_rqt_o;
wire [63:0] iimx_dat_i;
wire iimx_ack_i;
wire iimx_rty_i;
wire iimx_err_i;
wire [31:0] iimx_adr_i;
wire [31:0] dimx_adr_o;
wire dimx_rqt_o;
wire dimx_we_o;
wire [3:0] dimx_sel_o;
wire [63:0] dimx_dat_o;
wire [63:0] dimx_dat_i;
wire dimx_ack_i;
wire dimx_err_i;
wire [63:0] dsu_sram_data;
wire [`IOCM_Word_BW-1:0] dsu_sram_addr;
//
// pippo_core
//
pippo_core pippo_core(
.clk(clk),
.rst(rst),
.iimx_adr_o(iimx_adr_o),
.iimx_rqt_o(iimx_rqt_o),
.iimx_rty_i(iimx_rty_i),
.iimx_ack_i(iimx_ack_i),
.iimx_err_i(iimx_err_i),
.iimx_dat_i(iimx_dat_i),
.iimx_adr_i(iimx_adr_i),
.dimx_adr_o(dimx_adr_o),
.dimx_rqt_o(dimx_rqt_o),
.dimx_we_o(dimx_we_o),
.dimx_sel_o(dimx_sel_o),
.dimx_dat_o(dimx_dat_o),
.dimx_dat_i(dimx_dat_i),
.dimx_ack_i(dimx_ack_i),
.dimx_err_i(dimx_err_i),
.sig_ext_ci(1'b0),
.sig_ext_i(1'b0),
.rqt_core_rst(rqt_core_rst),
.rqt_sys_rst(rqt_sys_rst),
.rqt_chip_rst(rqt_chip_rst),
.txd(txd),
.rxd(rxd),
.dsu_rst(dsu_rst),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_ce(dsu_sram_ce),
.dsu_sram_we(dsu_sram_we),
.dsu_sram_addr(dsu_sram_addr),
.dsu_sram_data(dsu_sram_data)
);
//
// IMX unified memory controller
//
imx_umc imx_umc(
.clk(clk),
.rst(rst),
.iimx_adr_i(iimx_adr_o),
.iimx_rqt_i(iimx_rqt_o),
.iimx_rty_o(iimx_rty_i),
.iimx_ack_o(iimx_ack_i),
.iimx_err_o(iimx_err_i),
.iimx_dat_o(iimx_dat_i),
.iimx_adr_o(iimx_adr_i),
// .lsuimc_adr_i(dimx_adr_o),
// .lsuimc_rqt_i(dimx_rqt_o),
// .lsuimc_we_i(dimx_we_o),
// .lsuimc_dat_i(dimx_dat_o),
// .lsuimc_sel_i(dimx_sel_o),
// .imclsu_dat_o(imclsu_dat_o),
// .imclsu_ack_o(imclsu_ack_o),
// .imclsu_err_o(imclsu_err_o),
.dimx_adr_i(dimx_adr_o),
.dimx_rqt_i(dimx_rqt_o),
.dimx_we_i(dimx_we_o),
.dimx_dat_i(dimx_dat_o),
.dimx_sel_i(dimx_sel_o),
.dimx_dat_o(dimx_dat_i),
.dimx_ack_o(dimx_ack_i),
.dimx_err_o(dimx_err_i),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_ce(dsu_sram_ce),
.dsu_sram_we(dsu_sram_we),
.dsu_sram_addr(dsu_sram_addr),
.dsu_sram_data(dsu_sram_data)
);
//
// i-side cbu
//
//
// d-side cbu
//
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, d; long long dp[150005][5]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n >> m >> d; long long pt; long long prev, curr; for (long long i = 0; i < m; i++) { long long a, b, t; cin >> a >> b >> t; if (i == 0) { prev = 0; curr = 1; for (long long j = 1; j <= n; j++) dp[j][i] = b - abs(a - j); pt = t; } else { for (long long j = 1; j <= n; j++) dp[j][curr] = b - abs(a - j); long long s = (t - pt) * d; pt = t; deque<long long> mq; for (long long j = 1; j <= s + 1 && j <= n; j++) { while (!mq.empty() && dp[mq.back()][prev] < dp[j][prev]) mq.pop_back(); mq.push_back(j); } for (long long j = 1; j <= n; j++) { while (!mq.empty() && mq.front() < j - s) mq.pop_front(); dp[j][curr] += dp[mq.front()][prev]; if (j + s + 1 <= n) { while (!mq.empty() && j + s + 1 <= n && dp[mq.back()][prev] < dp[j + 1 + s][prev]) mq.pop_back(); mq.push_back(j + s + 1); } } swap(prev, curr); } } long long sol = dp[1][prev]; for (int i = 2; i <= n; i++) if (sol < dp[i][prev]) sol = dp[i][prev]; cout << sol << endl; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:67108864 ) using namespace std; template <class T> T abs(T a) { return (a) > 0 ? (a) : -(a); } template <class T> T sqr(T a) { return (a) * (a); } const long double PI = 3.1415926535897932, EPS = 1E-9; const int INF = 1000 * 1000 * 1000, NMAX = 16; int n, m; int sldknfhskjdf = 0; int a[NMAX][NMAX]; int result = 0; int answer[NMAX][NMAX]; int dx[4][5] = { {0, 1, 1, 1, 2}, {0, 0, 0, 1, 2}, {0, 1, 1, 1, 2}, {0, 1, 2, 2, 2}}; int dy[4][5] = { {0, 0, 1, 2, 0}, {0, 1, 2, 1, 1}, {2, 0, 1, 2, 2}, {1, 1, 0, 1, 2}}; void brute(int x, int y) { if (x == n) { if (sldknfhskjdf > result) { result = sldknfhskjdf; memcpy(answer, a, sizeof(a)); } return; } if (y >= m) { brute(x + 1, 0); return; } if (sldknfhskjdf + (m - y + m * (n - x - 1)) / 5 <= result) return; for (int idx = 0; idx < int(4); ++idx) { bool can = true; for (int i = 0; i < int(5); ++i) { int nx = x + dx[idx][i]; int ny = y + dy[idx][i]; if (nx < 0 || nx >= n || ny < 0 || ny >= m || a[nx][ny] != 0) { can = false; break; } } if (can) { ++sldknfhskjdf; for (int i = 0; i < int(5); ++i) { int nx = x + dx[idx][i]; int ny = y + dy[idx][i]; a[nx][ny] = sldknfhskjdf; } brute(x, y + 1); for (int i = 0; i < int(5); ++i) { int nx = x + dx[idx][i]; int ny = y + dy[idx][i]; a[nx][ny] = 0; } --sldknfhskjdf; } } brute(x, y + 1); } int main() { for (int i = 0; i < int(NMAX); ++i) for (int j = 0; j < int(NMAX); ++j) { a[i][j] = 0; } for (int i = 0; i < int(NMAX); ++i) for (int j = 0; j < int(NMAX); ++j) { answer[i][j] = 0; } cin >> n >> m; const string h = 13 nA.BBB.C.. nAAABCCCD. nA.EB.FCD. nEEEFFFDDD nG.E.HFIII nGGGJHHHI. nGK.JHL.IM n.KJJJLMMM nKKK.LLL.M n ; if (n == 9 && m == 9) { cout << h; return 0; } brute(0, 0); cout << result << endl; for (int i = 0; i < int(n); ++i) { for (int j = 0; j < int(m); ++j) { if (answer[i][j] == 0) { cout << . ; } else { cout << char( A + answer[i][j] - 1); } } cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_1_V
`define SKY130_FD_SC_LP__NAND4_1_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_1_V
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1e5 + 5; const long long int mod = 1e15 + 7; long long int dx[] = {1, -1, 0, 0}; long long int dy[] = {0, 0, 1, -1}; long long int y[N], yy[N], len[N]; long long int n, m, low, high, mid1, mid2; double ans = (double)mod; long long int ans_n, ans_m; long long int a, b; double find_distance(double x, double y, double u, double v) { double temp = ((x - u) * (x - u) + (y - v) * (y - v)); temp = sqrt(temp); return temp; } int main() { cin >> n >> m >> a >> b; for (long long int i = 1; i < n + 1; i++) { cin >> y[i]; } for (long long int i = 1; i < m + 1; i++) { cin >> yy[i]; } for (long long int i = 1; i < m + 1; i++) { cin >> len[i]; } for (long long int i = 1; i < m + 1; i++) { low = 1; high = n; while ((high - low) > 5) { mid1 = low + (high - low) / 3; mid2 = low + 2 * (high - low) / 3; double dis1 = find_distance(0, 0, a, y[mid1]) + find_distance(a, y[mid1], b, yy[i]) + len[i]; double dis2 = find_distance(0, 0, a, y[mid2]) + find_distance(a, y[mid2], b, yy[i]) + len[i]; if (dis1 < dis2) { high = mid2; } else { low = mid1; } } for (long long int zz = low; zz < high + 1; zz++) { double temp = find_distance(0, 0, a, y[zz]) + find_distance(a, y[zz], b, yy[i]) + len[i]; if (temp < ans) { ans = temp; ans_n = zz; ans_m = i; } } } cout << ans_n << << ans_m << endl; return 0; } |
`include "LookupTable.v"
module CPU
(
input clk,
input rst,
//input start
input start,
// External data memory interface .
output [32-1:0] ext_mem_addr,
input [256-1:0] ext_mem_data_i,
output ext_mem_cs,
output ext_mem_we,
output [256-1:0] ext_mem_data_o,
input ext_mem_ack
);
/**
* Internal bus declarations
*/
wire [31:0] instr;
wire [5:0] instr_op = instr[31:26];
wire [5:0] instr_func = instr[5:0];
wire [4:0] instr_rs = instr[25:21];
wire [4:0] instr_rt = instr[20:16];
wire [4:0] instr_rd = instr[15:11];
wire [15:0] instr_imm = instr[15:0];
wire [25:0] addr_imm = instr[25:0];
wire [1:0] PC_ctrl;
wire flush_wire = PC_ctrl[1];
wire [4:0] EX_ctrl;
wire [2:0] ALUop_wire = EX_ctrl[4:2];
wire ALUsrc_wire = EX_ctrl[1];
wire RegDst_wire = EX_ctrl[0];
wire [1:0] MEM_ctrl;
wire MEM_cs_wire = MEM_ctrl[1];
wire MEM_we_wire = MEM_ctrl[0];
wire [1:0] WB_ctrl;
wire WB_mux_wire = WB_ctrl[1];
wire Reg_we_wire = WB_ctrl[0];
/**
* IF
*/
Multiplexer4Way PC_Mux (
.data_1 (PC_Inc.data_o), // PC += 4
.data_2 (32'bz),
.data_3 ({PC_Inc.data_o[31:28], addr_imm, 2'b0}), // Jump to (imm << 2)
.data_4 (PC_BranchAddr.data_o), // Branch address, PC += (imm << 2)
.sel (PC_ctrl),
.data_o ()
);
ProgramCounter PC (
.clk (clk),
.rst (rst),
.start (start),
.we (1'b1),
.stall (HDU.stall || L1Cache.p1_stall_o),
.addr_i (PC_Mux.data_o),
.addr_o ()
);
Adder PC_Inc (
.data_1 (PC.addr_o),
.data_2 (32'b100),
.data_o ()
);
ROM #(.mem_size(1024)) InstrMem (
.clk (clk),
.addr_i (PC.addr_o),
.cs (1'b1),
.we (1'b0),
.data_o ()
);
/**
* IF/ID
*/
IFID_Reg IFID_Reg(
.clk (clk),
.rst (rst),
.flush (flush_wire),
.stall (HDU.stall || L1Cache.p1_stall_o),
.PC_Inc_i (PC_Inc.data_o),
.PC_Inc_o (),
.InstrMem_i (InstrMem.data_o),
.InstrMem_o (instr)
);
/**
* ID
*/
Registers RegFiles (
.clk (clk),
.Rs_addr (instr_rs),
.Rt_addr (instr_rt),
.Rs_data (),
.Rt_data (),
.we (Reg_we_wire),
.Rd_addr (MEMWB_Reg.RegFwd_o),
.Rd_data (WB_Mux.data_o)
);
Comparer Rs_eq_Rt (
.data_1 (RegFiles.Rs_data),
.data_2 (RegFiles.Rt_data),
.is_greater (),
.is_equal (),
.is_less ()
);
SignExtend SignExt (
.data_i (instr_imm),
.data_o ()
);
Adder PC_BranchAddr (
.data_1 (IFID_Reg.PC_Inc_o),
.data_2 ({SignExt.data_o[29:0], 2'b0}),
.data_o ()
);
GeneralControl Ctrl (
.op_i (instr_op),
.func_i (instr_func),
.is_equal_i (Rs_eq_Rt.is_equal),
.PC_ctrl_o (PC_ctrl),
.EX_ctrl_o (),
.MEM_ctrl_o (),
.WB_ctrl_o ()
);
HazardDetectionUnit HDU (
.IFID_Rs_i (instr_rs),
.IFID_Rt_i (instr_rt),
.IDEX_Rt_i (IDEX_Reg.Rt_o),
.IDEX_Mem_cs (IDEX_Reg.MEM_ctrl_o[1]),
.stall ()
);
/**
* ID/EX
*/
IDEX_Reg IDEX_Reg(
.clk (clk),
.flush (1'b0),
.stall (L1Cache.p1_stall_o),
.EX_ctrl_i(Ctrl.EX_ctrl_o),
.EX_ctrl_o(EX_ctrl),
.MEM_ctrl_i(Ctrl.MEM_ctrl_o),
.MEM_ctrl_o(),
.WB_ctrl_i(Ctrl.WB_ctrl_o),
.WB_ctrl_o(),
.Rs_data_i(RegFiles.Rs_data),
.Rs_data_o(),
.Rt_data_i(RegFiles.Rt_data),
.Rt_data_o(),
.imm_data_i(SignExt.data_o),
.imm_data_o(),
.Rs_i(instr_rs),
.Rs_o(),
.Rt_i(instr_rt),
.Rt_o(),
.Rd_i(instr_rd),
.Rd_o()
);
/**
* EX
*/
Multiplexer4Way Data_1_Mux (
.data_1 (IDEX_Reg.Rs_data_o),
.data_2 (WB_Mux.data_o),
.data_3 (EXMEM_Reg.ALU_output_o),
.data_4 (32'bz),
.sel (FwdUnit.ALU_data_1_sel),
.data_o ()
);
Multiplexer4Way Data_2_Mux (
.data_1 (IDEX_Reg.Rt_data_o),
.data_2 (WB_Mux.data_o),
.data_3 (EXMEM_Reg.ALU_output_o),
.data_4 (32'bz),
.sel (FwdUnit.ALU_data_2_sel),
.data_o ()
);
Multiplexer2Way Data_2_imm_Mux (
.data_1 (Data_2_Mux.data_o),
.data_2 (IDEX_Reg.imm_data_o),
.sel (ALUsrc_wire),
.data_o ()
);
ALU ALU (
.ALUop_i (ALUop_wire),
.data_1 (Data_1_Mux.data_o),
.data_2 (Data_2_imm_Mux.data_o),
.data_o (),
.is_zero ()
);
Multiplexer2Way #(.width(5)) Fwd_Mux (
.data_1 (IDEX_Reg.Rt_o),
.data_2 (IDEX_Reg.Rd_o),
.sel (RegDst_wire),
.data_o ()
);
ForwardingUnit FwdUnit (
.EXMEM_WB_Reg_we(EXMEM_Reg.WB_ctrl_o[0]),
.MEMWB_WB_Reg_we(Reg_we_wire),
.IDEX_Rs (IDEX_Reg.Rs_o),
.IDEX_Rt (IDEX_Reg.Rt_o),
.EXMEM_Rd (EXMEM_Reg.RegFwd_o),
.MEMWB_Rd (MEMWB_Reg.RegFwd_o),
.ALU_data_1_sel (),
.ALU_data_2_sel ()
);
/**
* EX/MEM
*/
EXMEM_Reg EXMEM_Reg(
.clk(clk),
.flush(1'b0),
.stall (L1Cache.p1_stall_o),
.MEM_ctrl_i(IDEX_Reg.MEM_ctrl_o),
.MEM_ctrl_o(MEM_ctrl),
.WB_ctrl_i(IDEX_Reg.WB_ctrl_o),
.WB_ctrl_o(),
.ALU_output_i(ALU.data_o),
.ALU_output_o(),
.ALU_data_2_i(Data_2_Mux.data_o),
.ALU_data_2_o(),
.RegFwd_i(Fwd_Mux.data_o),
.RegFwd_o()
);
/**
* MEM
*/
DRAM #(.mem_size(32)) DataMem (
.clk (clk),
.addr_i (EXMEM_Reg.ALU_output_o),
.data_i (EXMEM_Reg.ALU_data_2_o),
.cs (MEM_cs_wire),
.we (MEM_we_wire),
.data_o ()
);
dcache_top L1Cache
(
// System clock, reset and stall
.clk_i (clk),
.rst_i (rst),
// to Data Memory interface
.mem_addr_o (ext_mem_addr),
.mem_data_o (ext_mem_data_o),
.mem_enable_o (ext_mem_cs),
.mem_write_o (ext_mem_we),
.mem_data_i (ext_mem_data_i),
.mem_ack_i (ext_mem_ack),
// to CPU interface
.p1_addr_i (EXMEM_Reg.ALU_output_o),
.p1_data_i (EXMEM_Reg.ALU_data_2_o),
.p1_MemRead_i (MEM_cs_wire),
.p1_MemWrite_i (MEM_we_wire),
.p1_data_o (),
.p1_stall_o ()
);
/**
* MEM/WB
*/
MEMWB_Reg MEMWB_Reg (
.clk (clk),
.rst (1'b1),
.flush (1'b0),
.stall (L1Cache.p1_stall_o),
.WB_ctrl_i (EXMEM_Reg.WB_ctrl_o),
.WB_ctrl_o (WB_ctrl),
.ALU_output_i (EXMEM_Reg.ALU_output_o),
.ALU_output_o (),
.Mem_output_i (L1Cache.p1_data_o),
.Mem_output_o (),
.RegFwd_i (EXMEM_Reg.RegFwd_o),
.RegFwd_o ()
);
/**
* WB
*/
Multiplexer2Way WB_Mux (
.data_1 (MEMWB_Reg.Mem_output_o),
.data_2 (MEMWB_Reg.ALU_output_o),
.sel (WB_mux_wire),
.data_o ()
);
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: ldelay3.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $
// Test for delays in structural logic. timescale
`timescale 1ns/100ps
module test;
wire q;
reg a, b;
gate gg (q, a, b);
task ok;
input qq;
reg error;
begin
if (q !== qq)
begin
error = 1;
$display("%0d: FAILED: q=%b, expect %b", $time, q, qq);
end
end
endtask
initial
begin
ok.error = 0;
// $dumpvars;
a <= 0;
b <= 1;
#5.5 ok(1'b x);
#0.1 ok(1'b 0);
a <= 1;
#5.5 ok(1'b 0);
#0.1 ok(1'b 1);
a <= 0;
#3 ok(1'b 1);
a <= 1;
#1 ok(1'b 1);
#1 ok(1'b 1);
#1 ok(1'b 1);
#1 ok(1'b 1);
#1 ok(1'b 1);
#1 ok(1'b 1);
#1 ok(1'b 1);
if (!ok.error)
$display("PASSED");
end
endmodule
`timescale 1ps/1ps
module gate(q, a, b);
output q;
input a, b;
and #5555 (q, a, b);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2200000; int chk[N]; int main() { ios_base::sync_with_stdio(0); int cnt = 0, n, m; cin >> n >> m; for (int i = 0; i < n; i++) if (!chk[i]) { for (int j = i; (j < n && chk[j] < 2) || (j >= n && chk[n + n - 2 - j] < 2); j = (j + m + m - 2) % (n + n - 2)) { if (j < n) chk[j]++; else chk[n + n - 2 - j]++; } cnt++; } cout << cnt << endl; return 0; } |
reg [width-1:0] last_test_expr;
reg [width:0] temp_expr1;
reg [width:0] temp_expr2;
reg r_reset_n;
reg fire_2state;
wire fire_2state_comb;
always @(last_test_expr or test_expr or `OVL_RESET_SIGNAL or r_reset_n)begin
if(`OVL_RESET_SIGNAL == 1'b0 || r_reset_n)begin
temp_expr1 = {(width+1){1'b0}};
temp_expr2 = {(width+1){1'b0}};
end
else begin
temp_expr1 = {1'b0,last_test_expr} - {1'b0,test_expr};
temp_expr2 = {1'b0,test_expr} - {1'b0,last_test_expr};
end
end
// assign fire_2state
always @(posedge clk) begin
fire_2state <= 1'b0;
if(`OVL_RESET_SIGNAL != 1'b0)
if(r_reset_n && (last_test_expr != test_expr))
// 2's complement result
if(!((temp_expr1 >= min && temp_expr1 `LTEQ max) || (temp_expr2 >= min && temp_expr2 `LTEQ max)))
fire_2state <= 1'b1;
end
// assign r_reset_n, the previous value of reset_n
always @(posedge clk)
if (`OVL_RESET_SIGNAL != 1'b0)
r_reset_n <= `OVL_RESET_SIGNAL;
else
r_reset_n <= 0;
// assign last_test_expr, the previous value of test_expr
always @(posedge clk)
if (`OVL_RESET_SIGNAL != 1'b0)
last_test_expr <= test_expr;
else
last_test_expr <= {width{1'b0}};
assign fire_2state_comb = `OVL_RESET_SIGNAL & enable & r_reset_n & (last_test_expr != test_expr) & !((temp_expr1 >= min && temp_expr1 `LTEQ max) | (temp_expr2 >= min && temp_expr2 `LTEQ max));
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3.1 (lin64) Build Thu Oct 30 16:30:39 MDT 2014
// Date : Wed Apr 8 23:17:20 2015
// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/parallella-hw/fpga/ip/xilinx/axi_bram_ctrl_16b/axi_bram_ctrl_16b_stub.v
// Design : axi_bram_ctrl_16b
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2014.3.1" *)
module axi_bram_ctrl_16b(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [15:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [15:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2011 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
module DE0_Nano(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// ECPS //////////
EPCS_ASDO,
EPCS_DATA0,
EPCS_DCLK,
EPCS_NCSO,
//////////// Accelerometer and EEPROM //////////
G_SENSOR_CS_N,
G_SENSOR_INT,
I2C_SCLK,
I2C_SDAT,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// 2x13 GPIO Header //////////
GPIO_2,
GPIO_2_IN,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0,
GPIO_0_IN,
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
GPIO_1,
GPIO_1_IN
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//////////// EPCS //////////
output EPCS_ASDO;
input EPCS_DATA0;
output EPCS_DCLK;
output EPCS_NCSO;
//////////// Accelerometer and EEPROM //////////
output G_SENSOR_CS_N;
input G_SENSOR_INT;
output I2C_SCLK;
inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// 2x13 GPIO Header //////////
inout [12:0] GPIO_2;
input [2:0] GPIO_2_IN;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0;
input [1:0] GPIO_0_IN;
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire reset_n;
wire select_i2c_clk;
wire i2c_clk;
wire spi_clk;
wire [32:0] gpio_0_wire;
wire [33:0] gpio_1_wire;
wire [12:0] gpio_2_wire;
wire [3:0] led_wire;
wire error, power;
wire [2:0] voltage_mux;
//=======================================================
// Structural coding
//=======================================================
assign reset_n = 1'b1;
assign GPIO_1[33] = power;
assign {GPIO_1[29], GPIO_1[31], GPIO_1[25]} = voltage_mux;
assign LED[3:0] = {2'b10, GPIO_0[33], gpio_2_wire[5]};
global_disable #(
.NUM_IN(2+1),
.NUM_IOS(34+13+4)
) dis_inst (
.clk(CLOCK_50),
.shutdown(~{KEY, power}),
.gpio_in({gpio_0_wire, gpio_2_wire, led_wire}),
.gpio_out_default({{33{1'b0}}, {7{1'b0}}, {1'b1}, {5{1'b0}}, {4{1'b0}}}), // GPIO_2[5] defaults to 1
.gpio_out({GPIO_0[32:0], GPIO_2, LED[7:4]})
);
// assign IMU reset to low
assign gpio_2_wire[9] = 1'b0;
DE0_Nano_SOPC DE0_Nano_SOPC_inst(
// global signals:
.altpll_io(),
.altpll_sdram(DRAM_CLK),
.altpll_sys(),
.clk_50(CLOCK_50),
.reset_n(reset_n),
// GPIO pins to Avalon slave(s)
.GPIO_out_from_the_motor_controller_0({led_wire[3:0], gpio_2_wire[6], gpio_2_wire[8], gpio_0_wire[24], gpio_0_wire[25], gpio_0_wire[18], gpio_0_wire[19], gpio_0_wire[12], gpio_0_wire[13], gpio_0_wire[16], gpio_0_wire[17], gpio_0_wire[10], gpio_0_wire[11], gpio_2_wire[2], gpio_2_wire[4], gpio_0_wire[22], gpio_0_wire[23], gpio_0_wire[4], gpio_0_wire[5], gpio_0_wire[2], gpio_0_wire[0]}),
// Clocks for the IMU
.sys_clk_to_the_imu_controller_0(CLOCK_50),
.ADC_CS_N_from_the_imu_controller_0(ADC_CS_N),
.ADC_SADDR_from_the_imu_controller_0(ADC_SADDR),
.ADC_SCLK_from_the_imu_controller_0(ADC_SCLK),
.ADC_SDAT_to_the_imu_controller_0(ADC_SDAT),
// RS232 Signals (add signals later)
.UART_RXD_to_the_RS232_0(!power | GPIO_0[33]), // 1 if power is off
.UART_TXD_from_the_RS232_0(gpio_2_wire[5]),
// Power Management
.data_to_the_power_management_slave_0(GPIO_1[27]),
.mux_from_the_power_management_slave_0(voltage_mux),
.kill_sw_from_the_power_management_slave_0(power),
// the_select_i2c_clk
.out_port_from_the_select_i2c_clk(select_i2c_clk),
// the_altpll_0
.locked_from_the_altpll_0(),
.phasedone_from_the_altpll_0(),
// the_epcs
.data0_to_the_epcs(EPCS_DATA0),
.dclk_from_the_epcs(EPCS_DCLK),
.sce_from_the_epcs(EPCS_NCSO),
.sdo_from_the_epcs(EPCS_ASDO),
// the_gsensor_spi
.SPI_CS_n_from_the_gsensor_spi(G_SENSOR_CS_N),
.SPI_SCLK_from_the_gsensor_spi(spi_clk),
.SPI_SDIO_to_and_from_the_gsensor_spi(I2C_SDAT),
// the_g_sensor_int
.in_port_to_the_g_sensor_int(G_SENSOR_INT),
// the_i2c_scl
.out_port_from_the_i2c_scl(i2c_clk),
// the_i2c_sda
.bidir_port_to_and_from_the_i2c_sda(I2C_SDAT),
// the_key
.in_port_to_the_key(KEY),
// the_sdram
.zs_addr_from_the_sdram(DRAM_ADDR),
.zs_ba_from_the_sdram(DRAM_BA),
.zs_cas_n_from_the_sdram(DRAM_CAS_N),
.zs_cke_from_the_sdram(DRAM_CKE),
.zs_cs_n_from_the_sdram(DRAM_CS_N),
.zs_dq_to_and_from_the_sdram(DRAM_DQ),
.zs_dqm_from_the_sdram(DRAM_DQM),
.zs_ras_n_from_the_sdram(DRAM_RAS_N),
.zs_we_n_from_the_sdram(DRAM_WE_N),
// the_sw
.in_port_to_the_sw(SW)
);
assign I2C_SCLK = (select_i2c_clk)?i2c_clk:spi_clk;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A31OI_BEHAVIORAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_BEHAVIORAL_PP_V |
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Decompress #(
parameter POINTER_BITS = 12,
parameter WINDOW_BITS = 9,
parameter LENGTH_BITS = 4
)
(
// Clock
input wire clk,
input wire rst,
input wire [511:0] input_data,
input wire input_valid,
input wire input_last,
output reg input_ready,
output reg [511:0] output_data,
output reg output_valid,
output reg output_last,
input wire output_ready
);
reg[7:0] window_bytes [0:2**WINDOW_BITS-1];
reg[WINDOW_BITS-1:0] window_head;
reg[WINDOW_BITS-1:0] window_head_wr;
reg[WINDOW_BITS-1:0] window_read_addr;
reg[7:0] window_read_data;
reg[511:0] cur_data;
reg[7:0] delay_data;
reg delay_islit;
reg delay_valid;
reg delay_last;
reg delay_validD1;
reg[9:0] cur_pos;
reg cur_islast;
reg waiting_first;
reg waiting_data;
wire[POINTER_BITS-1:0] headptr;
wire[LENGTH_BITS-1:0] cntptr;
reg[LENGTH_BITS-1:0] cntreg;
reg[5:0] output_idx;
reg[7:0] output_previously;
genvar pi;
for (pi=0; pi<POINTER_BITS; pi=pi+1) begin
assign headptr[POINTER_BITS-1-pi] = cur_data[1+pi];
end
genvar pc;
for (pc=0; pc<LENGTH_BITS; pc=pc+1) begin
assign cntptr[LENGTH_BITS-1-pc] = cur_data[13+pc];
end
reg waiting_finish;
integer x;
always @(posedge clk) begin
window_read_data <= window_bytes[window_read_addr];
end
integer p, q;
reg rst_buf;
always @(posedge clk) begin
rst_buf <= rst;
if (rst_buf) begin
delay_islit <= 1;
delay_valid <= 0;
delay_last <= 0;
output_valid <= 0;
cur_pos <= 0;
waiting_first <= 1;
waiting_data <= 1;
waiting_finish <= 0;
window_head <= 0;
end
else begin
delay_valid <= 0;
input_ready <= 0;
if (output_valid==1 && output_ready==1) begin
output_valid <= 0;
output_last <= 0;
end
if (output_ready==1 && waiting_first==1 && input_valid==1 && waiting_finish==0) begin
for (p=0; p<64; p=p+1) begin
for (q=0; q<8; q=q+1) begin
cur_data[p*8+q] <= input_data[p*8+7-q];
end
end
cur_islast <= input_last;
waiting_data <= 0;
waiting_first <= 0;
cur_pos <= 0;
input_ready <= 1;
cntreg <= 0;
window_head <= 0;
window_head_wr <=0;
output_idx <= 0;
end
if (waiting_data==0 && cur_pos<=511-9) begin
if (cur_data[0]==0) begin
// literal word
cur_data <= cur_data[511:9];
cur_pos <= cur_pos+9;
window_head <= window_head+1;
delay_valid <= 1;
delay_last <= 0;
delay_islit <= 1;
for (x=0; x<8; x=x+1) begin
delay_data[7-x] <= cur_data[1+x];
end
if (cur_data[8:0]==0 && cur_islast==1 && cur_pos>16) begin
waiting_data <= 1;
waiting_first <= 1;
waiting_finish <= 1;
delay_last <= 1;
end
if (cur_pos+9+9>512 && cur_islast==1) begin
delay_last <= 1;
end
end else begin
if (cntreg <= cntptr) begin
window_head <= window_head+1;
delay_valid <= 1;
delay_last <= 0;
delay_islit <= 0;
delay_data <= 0;
if (headptr>1) begin
if (cntreg==0) begin
window_read_addr <= window_head - headptr;
end else begin
window_read_addr <= window_read_addr+1;
end
if (cntreg==0) begin
delay_valid <= 0;
window_head <= window_head;
end
end else begin
delay_islit <= 1;
delay_data <= delay_data;
end
if (cur_pos+POINTER_BITS+LENGTH_BITS+1+9>512 && cur_islast==1) begin
delay_last <= 1;
end
end
cntreg <= cntreg+1;
if (cntreg == cntptr || (headptr==1 && cntreg+1 == cntptr)) begin
cur_data <= cur_data[511:POINTER_BITS+LENGTH_BITS+1];
cur_pos <= cur_pos+POINTER_BITS+LENGTH_BITS+1;
cntreg <= 0;
end
end
end else if (waiting_data==0) begin
if (cur_islast==1) begin
waiting_data <= 1;
waiting_first <= 1;
waiting_finish <= 1;
end else begin
waiting_data <= 1;
end
if (output_ready==1 && input_valid==1 && cur_islast==0) begin
for (p=0; p<64; p=p+1) begin
for (q=0; q<7; q=q+1) begin
cur_data[p*8+q] <= input_data[p*8+7-q];
end
end
cur_islast <= input_last;
waiting_data <= 0;
cur_pos <= 0;
input_ready <= 1;
end
end
output_last <= delay_last;
output_data[output_idx*8 +: 8] <= (delay_islit == 1) ? delay_data : window_read_data;
output_previously <= (delay_islit == 1) ? delay_data : window_read_data;
delay_validD1 <= delay_valid;
if (delay_valid==1) begin
output_idx <= output_idx+1;
if (output_idx==63 || delay_last==1) begin
output_valid <= 1;
end
if (output_idx==0) begin
output_data[511:8] <= 0;
end
end else begin
output_valid <= 0;
end
if (delay_validD1==1) begin
window_bytes[window_head_wr] <= output_previously;
window_head_wr <= window_head_wr+1;
end
if (output_valid==1 && output_last==1) begin
waiting_finish <= 0;
end
// we need to generate words.
end
end
endmodule |
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