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#include <bits/stdc++.h> using namespace std; int main() { int n, k, sumk; cin >> n >> k; k--; int out[500][500]; sumk = 0; int current = n * n; for (int i = 0; i < n; ++i) { for (int j = n - 1; j >= k; --j) { out[i][j] = current; if (j == k) { sumk += current; } current--; } } for (int i = 0; i < n; ++i) { for (int j = k - 1; j >= 0; --j) { out[i][j] = current; current--; } } cout << sumk << endl; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cout << out[i][j] << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int a, b; cin >> a >> b; if (a % b == 0) { cout << 0 << n ; } else { long long int g = a / b; long long int ans = (b * (g + 1) - a); cout << ans << n ; } } return 0; } |
/*
* Copyright (c) 2000 Steve Wilson ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Verify signed constant assignment to an reg.
*/
module test;
integer I0,I1;
reg [15:0] R0,R1;
reg [3:0] error;
initial
begin
R0 = -4'd12;
R1 = -16'd12;
error = 0;
if(R0 !== 16'hfff4)
begin
$display("FAILED - negative decimal assignment failed. R0 s/b fff4, is %h",
R0);
error = 1;
end
if(R1 !== 16'hfff4)
begin
$display("FAILED - negative decimal assignment failed. R1 s/b fff4, is %h",
R1);
error = 1;
end
if(error === 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int num[27]; int num2[27]; inline int idx(char a) { return a - a ; } char sa[5555], sb[5555], sans1[5555], sans2[5555], sans[5555]; inline char rev(int id) { return a + id; } int lena, lenb; bool ans1, ans2; int main() { scanf( %s , sa); scanf( %s , sb); ans1 = false; ans2 = false; memset(num, 0, sizeof(num)); memset(num2, 0, sizeof(num2)); lena = strlen(sa); lenb = strlen(sb); for (int i = 0; i < lena; i++) { num[idx(sa[i])]++; num2[idx(sa[i])]++; } if (lena > lenb) { int flag = 1; for (int i = 0; i < lenb; i++) { sans1[i] = sb[i]; if (!num[idx(sb[i])]) { flag = 0; break; } else { num[idx(sb[i])]--; } } if (flag) { ans1 = true; int tl = lenb; for (int i = 0; i < 26; i++) { while (num[i]) { num[i]--; sans1[tl++] = rev(i); } } sans1[tl] = 0 ; } } for (int i = 0; i < 26; i++) num[i] = num2[i]; int lastmch = -1; for (int i = 0; i < lenb; i++) { if (num[idx(sb[i])]) { num[idx(sb[i])]--; sans2[i] = sb[i]; lastmch = i; } else { int tl = i; int fg = 0; for (int j = idx(sb[i]) + 1; j < 26; j++) { if (num[j]) { fg = 1; num[j]--; sans2[tl++] = rev(j); break; } } if (!fg) { for (int k = i - 1; k >= 0; k--) { tl = k; if (tl >= 0) { num[idx(sb[k])]++; for (int j = idx(sb[k]) + 1; j < 26; j++) { if (num[j]) { lastmch = k - 1; fg = 1; num[j]--; sans2[tl++] = rev(j); break; } } } if (fg) break; } } if (fg) { ans2 = true; for (int j = 0; j < 26; j++) { while (num[j]) { num[j]--; sans2[tl++] = rev(j); } } } sans2[tl] = 0 ; break; } } if (lastmch == lenb - 1 && ans2 == 0) { int i = lenb; int fg = 0; int tl; for (int k = i - 1; k >= 0; k--) { tl = k; if (tl >= 0) { num[idx(sb[k])]++; for (int j = idx(sb[k]) + 1; j < 26; j++) { if (num[j]) { lastmch = k - 1; fg = 1; num[j]--; sans2[tl++] = rev(j); break; } } } if (fg) break; } if (fg) { ans2 = true; for (int j = 0; j < 26; j++) { while (num[j]) { num[j]--; sans2[tl++] = rev(j); } } } sans2[tl] = 0 ; } int fg = 0; if (ans1 == false && ans2 == false) { cout << -1 << endl; return 0; } if (ans1) { fg = 1; strcpy(sans, sans1); } if (fg && ans2) { if (strcmp(sans1, sans2) > 0) { strcpy(sans, sans2); } else { strcpy(sans, sans1); } } else if (ans2) { strcpy(sans, sans2); } puts(sans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; long long int i, a[n]; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (a[0] == a[n - 1] && a[0] == 0) { while (k--) cout << 0 << endl; } long long int b[n], ct = 0; for (i = 0; i < n; i++) { while (i < n && a[i] == a[i + 1]) i++; b[ct++] = a[i]; } i = 0; long long int cnt = 0; while (k--) { while (b[i] == 0) i++; if (i >= ct) cout << 0 << endl; else cout << b[i] - cnt << endl; cnt = b[i]; i++; } } |
#include <bits/stdc++.h> const double EPS = 1e-24; const long long int MOD = 1000000007ll; const long long int MOD1 = 1000000009ll; const long long int MOD2 = 1100000009ll; const double PI = 3.14159265359; int INF = 2147483645; long long int INFINF = 9223372036854775807; template <class T> T Max2(T a, T b) { return a < b ? b : a; } template <class T> T Min2(T a, T b) { return a < b ? a : b; } template <class T> T Max3(T a, T b, T c) { return Max2(Max2(a, b), c); } template <class T> T Min3(T a, T b, T c) { return Min2(Min2(a, b), c); } template <class T> T Max4(T a, T b, T c, T d) { return Max2(Max2(a, b), Max2(c, d)); } template <class T> T Min4(T a, T b, T c, T d) { return Min2(Min2(a, b), Min2(c, d)); } using namespace std; int bit_count(long long int _x) { int _ret = 0; while (_x) { if (_x % 2 == 1) _ret++; _x /= 2; } return _ret; } int bit(long long int _mask, long long int _i) { return (_mask & (1 << _i)) == 0 ? 0 : 1; } long long int powermod(long long int _a, long long int _b, long long int _m) { long long int _r = 1; while (_b) { if (_b % 2 == 1) _r = (_r * _a) % _m; _b /= 2; _a = (_a * _a) % _m; } return _r; } int x[5], y[5]; bool issquare[30010]; int sz, sz2; char s[110][110]; char c[5]; void type2(int a1, int a2, int b1, int b2, int c1, int c2, int i1, int i2, int i3) { for (int i = 1; i <= a1; i++) for (int j = 1; j <= a2; j++) s[i][j] = c[i1]; for (int i = a1 + 1; i <= a1 + b1; i++) for (int j = 1; j <= b2; j++) s[i][j] = c[i2]; for (int i = 1; i <= c1; i++) for (int j = a2 + 1; j <= a2 + c2; j++) s[i][j] = c[i3]; } void print() { cout << sz << n ; for (int i = 1; i <= sz; i++) { for (int j = 1; j <= sz; j++) cout << s[i][j]; cout << n ; } } int main() { std::ios::sync_with_stdio(false); srand(time(NULL)); for (int i = 1; i <= 3; i++) cin >> x[i] >> y[i]; c[1] = A ; c[2] = B ; c[3] = C ; for (int i = 2; i * i <= 30010; i++) issquare[i * i] = true; sz2 = 0; for (int i = 1; i <= 3; i++) sz2 += x[i] * y[i]; if (!issquare[sz2]) { cout << -1 ; return 0; } for (int i = 2; i * i <= 30010; i++) { if (i * i == sz2) { sz = i; break; } } for (int i = 1; i <= 3; i++) if (x[i] > y[i]) swap(x[i], y[i]); if (y[1] == sz && y[2] == sz && y[3] == sz && x[1] + x[2] + x[3] == sz) { cout << sz << n ; for (int i = 1; i <= x[1]; i++) { for (int j = 1; j <= y[1]; j++) cout << A ; cout << n ; } for (int i = 1; i <= x[2]; i++) { for (int j = 1; j <= y[2]; j++) cout << B ; cout << n ; } for (int i = 1; i <= x[3]; i++) { for (int j = 1; j <= y[3]; j++) cout << C ; cout << n ; } return 0; } for (int i = 1; i <= 3; i++) for (int j = 1; j <= 3; j++) for (int k = 1; k <= 3; k++) { if (i == j || j == k || i == k) continue; if (x[j] + x[k] == sz && y[j] == y[k]) { if (x[i] == sz && y[i] == sz - y[j]) { type2(x[j], y[j], x[k], y[k], x[i], y[i], j, k, i); print(); return 0; } if (y[i] == sz && x[i] == sz - y[j]) { type2(x[j], y[j], x[k], y[k], y[i], x[i], j, k, i); print(); return 0; } } else if (x[j] + y[k] == sz && y[j] == x[k]) { if (x[i] == sz && y[i] == sz - y[j]) { type2(x[j], y[j], y[k], x[k], x[i], y[i], j, k, i); print(); return 0; } if (y[i] == sz && x[i] == sz - y[j]) { type2(x[j], y[j], y[k], x[k], y[i], x[i], j, k, i); print(); return 0; } } else if (y[j] + x[k] == sz && x[j] == y[k]) { if (x[i] == sz && y[i] == sz - x[j]) { type2(y[j], x[j], x[k], y[k], x[i], y[i], j, k, i); print(); return 0; } if (y[i] == sz && x[i] == sz - x[j]) { type2(y[j], x[j], x[k], y[k], y[i], x[i], j, k, i); print(); return 0; } } else if (y[j] + y[k] == sz && x[j] == x[k]) { if (x[i] == sz && y[i] == sz - x[j]) { type2(y[j], x[j], y[k], x[k], x[i], y[i], j, k, i); print(); return 0; } if (y[i] == sz && x[i] == sz - x[j]) { type2(y[j], x[j], y[k], x[k], y[i], x[i], j, k, i); print(); return 0; } } } cout << -1 ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); int n, q, i; cin >> n; int arr[106] = {}; for (i = 1; i <= n; i++) { cin >> arr[i]; } cin >> q; int x, y; while (q--) { cin >> x >> y; arr[x - 1] += (y - 1); arr[x + 1] += (arr[x] - y); arr[x] = 0; } for (i = 1; i <= n; i++) { cout << arr[i] << n ; } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_mux_4to1_sel2_32_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
)(
input [31 : 0] din1,
input [31 : 0] din2,
input [31 : 0] din3,
input [31 : 0] din4,
input [1 : 0] din5,
output [31 : 0] dout);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [31 : 0] mux_1_0;
wire [31 : 0] mux_1_1;
// level 2 signals
wire [31 : 0] mux_2_0;
assign sel = din5;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
|
module top (input CLK,
inout SCL,
inout SDA,
//-- Debug. Logic analizer
output D0,
output D1,
output D13,
//-- Debug: buttons and leds
input SW1,
input SW2,
output LED0
);
localparam ADDR = 7'b000_0000;
i2c_master i2c (.clk(CLK),
.rst(SW1),
.scl(SCL),
.sda(SDA),
.enable(SW2),
.addr(ADDR),
.rw(1'b1),
.data_wr(8'h00),
.data_rd(data),
.fast_mode(1'b0),
.busy(busy),
.ack_error(ack_error)
);
wire en = 1'b1;
wire busy;
wire ack_error;
wire [7:0] data;
//-- Debug connections
assign D0 = SW2;
//assign D1 = CLK;
assign LED0 = SW1;
//assign D13 = CLK;
endmodule
module i2c_master (input clk,
input rst,
inout scl,
inout sda,
input enable,
input [6:0] addr,
input rw,
output busy,
output ack_error,
output [7:0] data_rd,
input [7:0] data_wr,
input fast_mode);
parameter BUS_CLK_400 = 400_000;
parameter BUS_CLK_100 = 100_000;
parameter CLK_FREQ = 12_000_000; //-- 100_000_000 Initial value
localparam DIVIDER_400 = (CLK_FREQ/BUS_CLK_400/4);
localparam DIVIDER_100 = (CLK_FREQ/BUS_CLK_100/4);
localparam IDLE = 4'b0000;
localparam START = 4'b0001;
localparam COMMAND = 4'b0010;
localparam SLV_ACK1 = 4'b0011;
localparam WR = 4'b0100;
localparam RD = 4'b0101;
localparam SLV_ACK2 = 4'b0110;
localparam MSTR_ACK = 4'b0111;
localparam STOP = 4'b1000;
reg [3:0] state = IDLE;
reg stretch;
reg [9:0] count;
reg [9:0] pre_div;
reg ack_error;
reg data_clk;
reg data_clk_prev;
wire scl_in;
reg scl_clk;
reg scl_enable = 0;
wire sda_in;
reg sda_enable;
reg sda_int = 1'b1;
reg [7:0] data_rx;
reg [3:0] bit_cnt = 4'h7;
reg [7:0] data_tx;
reg [7:0] addr_rw;
always @ (posedge clk or posedge rst)
begin
if (rst) begin
stretch <= 0;
count <= 0;
end else begin
data_clk_prev <= data_clk;
if (fast_mode)
pre_div <= DIVIDER_400;
else
pre_div <= DIVIDER_100;
if (count == pre_div*4-1) begin
count <= 0;
end else if (stretch == 1'b0) begin
count <= count + 1;
end
if (count > 0 && count <= pre_div-1) begin
scl_clk <= 1'b0;
data_clk <= 1'b0;
end else if (count >= pre_div && count <= pre_div*2-1) begin
scl_clk <= 1'b0;
data_clk <= 1'b1;
end else if (count >= pre_div*2 && count <= pre_div*3-1) begin
scl_clk <= 1'b1;
if (scl_in == 1'b0)
stretch <= 1'b1;
else
stretch <= 1'b0;
data_clk <= 1'b1;
end else begin
scl_clk <= 1'b1;
data_clk <= 1'b0;
end
end
end
always @ (posedge clk or posedge rst)
begin
if (rst) begin
busy <= 1'b0;
scl_enable <= 1'b0;
sda_int <= 1'b1;
ack_error <= 1'b0;
bit_cnt <= 4'h7;
state <= IDLE;
data_rd <= 8'b00000000;
end else begin
if (data_clk == 1'b1 && data_clk_prev == 1'b0) begin
case (state)
IDLE: begin
if (enable == 1'b1) begin
busy <= 1'b1;
addr_rw <= {addr, rw};
state <= START;
end else begin
busy <= 1'b0;
state <= IDLE;
end
end
START: begin
busy <= 1'b1;
sda_int <= addr_rw[bit_cnt];
state <= COMMAND;
end
COMMAND: begin
if (bit_cnt == 4'b0000) begin
sda_int <= 1'b1;
bit_cnt <= 4'h7;
state<= SLV_ACK1;
end else begin
bit_cnt <= bit_cnt - 1;
sda_int <= addr_rw[bit_cnt-1];
state <= COMMAND;
end
end
SLV_ACK1: begin
if (addr_rw[0] == 1'b0) begin
sda_int <= data_tx[bit_cnt];
state <= WR;
data_tx <= data_wr;
end else begin
sda_int <= 1'b1;
state <= RD;
end
end
WR: begin
if (bit_cnt == 4'b0000) begin
sda_int <= 1'b1;
bit_cnt <= 4'h7;
state <= SLV_ACK2;
busy <= 1'b0;
end else begin
bit_cnt <= bit_cnt - 1;
sda_int <= data_tx[bit_cnt-1];
state <= WR;
busy <= 1'b1;
end
end
RD: begin
if (bit_cnt == 4'b0000) begin
if (enable == 1'b1 && addr_rw == {addr, rw})
sda_int <= 1'b0;
else
sda_int <= 1'b1;
bit_cnt <= 4'h7;
data_rd <= data_rx;
state <= MSTR_ACK;
busy <= 1'b0;
end else begin
bit_cnt <= bit_cnt - 1;
state <= RD;
busy <= 1'b1;
end
end
SLV_ACK2: begin
if (enable == 1'b1) begin
addr_rw <= {addr, rw};
data_tx <= data_wr;
if (addr_rw == {addr, rw}) begin
sda_int <= data_wr[bit_cnt];
state <= WR;
end else begin
state <= START;
end
end else begin
state <= STOP;
end
end
MSTR_ACK: begin
if (enable == 1'b1) begin
addr_rw <= {addr, rw};
data_tx <= data_wr;
if (addr_rw == {addr, rw}) begin
sda_int <= 1'b1;
state <= RD;
end else begin
state <= START;
end
end else begin
state <= STOP;
end
end
STOP: begin
busy <= 1'b0;
state <= IDLE;
end
endcase
end else if (data_clk == 1'b0 && data_clk_prev == 1'b1) begin
case (state)
START: begin
if (scl_enable == 1'b0) begin
scl_enable <= 1'b1;
ack_error <= 1'b0;
end
end
SLV_ACK1: begin
if (sda_in != 1'b0 || ack_error == 1'b1)
ack_error <= 1'b1;
end
RD: begin
data_rx[bit_cnt] <= sda_in;
end
SLV_ACK2: begin
if (sda_in != 1'b0 || ack_error == 1'b1)
ack_error <= 1'b1;
end
STOP: begin
scl_enable <= 1'b0;
end
endcase
end
end
end
assign sda_enable = (state == START) ? data_clk_prev :
(state == STOP) ? !data_clk_prev : sda_int;
//Tri-State buffer controll
SB_IO # (
.PIN_TYPE(6'b1010_01),
.PULLUP(1'b0)
) scl_io (
.PACKAGE_PIN(scl),
.OUTPUT_ENABLE(scl_enable == 1'b1 && scl_clk == 1'b0),
.D_OUT_0(1'b0),
.D_IN_0(scl_in),
);
//Tri-State buffer controll
SB_IO # (
.PIN_TYPE(6'b1010_01),
.PULLUP(1'b0)
) sda_io (
.PACKAGE_PIN(sda),
.OUTPUT_ENABLE(sda_enable == 1'b0),
.D_OUT_0(1'b0),
.D_IN_0(sda_in),
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long n) { if (a == 0) return 0; if (a == 1 || n == 0) return 1; if (n == 1) return a % 1000000007; long long t = power(a, n / 2); t = t * t % 1000000007; if (n & 1) return t * a % 1000000007; return t; } int popcount(long long a) { int c = 0; while (a) { c++; a -= a & -a; } return c; } void factorize(int a) {} void update(int tree[], int idx, int val, int maxval) { for (; idx <= maxval; idx += idx & -idx) { tree[idx] += val; } } int read(int tree[], int idx) { long long sum = 0; for (; idx > 0; idx -= idx & -idx) { sum += tree[idx]; } return sum; } struct node2 { int id, val; node2() { static int ctx = 1; id = ctx++; }; node2(int a, int b = 0, int c = 0, int d = 0, int e = 0, int f = 0) { val = a; } }; struct comp2 { bool operator()(int a, int b) { return b < a; } }; bool cmp2(int a, int b) { return b < a; } struct node { long long x, y; }; struct comp { bool operator()(int a, int b) { return b < a; } }; bool cmp(int a, int b) { return b < a; } int n, m, a, b, c, d, k, h, w, x, y, p, q, t, res, ma, mi, T, act = 0, pas = 1, cur, flag, now; int deg[100009]; char s[1]; double e, f, z; vector<int> v[100009], vec; node ans[100009]; set<int> sett; map<int, int> mapp; void print() {} void print2() {} void input() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 1; i < n; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); deg[x]++; deg[y]++; } } int Y[] = {0, 1, 0, -1, 0}; int X[] = {0, 0, 1, 0, -1}; int bgfjsvf[] = {0, 3, 4, 1, 2}; void calc(int id, int par, long long y, long long x, long long dist, int dir) { ans[id].x = x; ans[id].y = y; int block = 1; for (auto u : v[id]) { if (u == par) continue; if (block == dir) block++; calc(u, id, y + Y[block] * dist, x + X[block] * dist, dist / 2, bgfjsvf[block]); block++; } } void solve() { for (int i = 1; i < n + 1; i++) if (deg[i] > 4) { flag = 1; return; } calc(1, 0, 0, 0, 1e9, 0); } void output() { if (flag == 1) cout << NO ; else { cout << YES << endl; for (int i = 1; i < n + 1; i++) cout << ans[i].x << << ans[i].y << endl; } } int main() { input(); solve(); output(); return 0; } |
`timescale 1 ns / 1 ps
module seven_segment_display
(
input clk,
input [15:0]num_in,
output reg [6:0]dig,
output reg dp,
output reg neg,
output reg clr,
output reg [3:0]dig_sel
);
//dig format
//dig[0] : A, top
//dig[1] : B, top/right
//dig[2] : C, bottom/right
//dig[3] : D, bottom
//dig[4] : E, bottom/left
//dig[5] : F, top/left
//dig[6] : G, middle
reg [6:0]dig1;
reg [6:0]dig2;
reg [6:0]dig3;
reg [6:0]dig4;
reg [19:0] clk_div;
always @(posedge clk) begin
clk_div = clk_div + 1;
end
always @(posedge clk) begin
/* dig_sel <= 4'b0001; */
/* dig <= dig1; */
if (clk_div == 0)
begin
if(dig_sel == 0)
dig_sel <= 1;
else
dig_sel <= {dig_sel[0],dig_sel[3:1]};
case(dig_sel)
4'b0010: dig <= dig4;
4'b0100: dig <= dig3;
4'b1000: dig <= dig2;
4'b0001: dig <= dig1;
endcase
end
end
always @(posedge clk) begin
case(num_in[3:0])
4'b0000: dig1 = 7'b1000000; //0
4'b0001: dig1 = 7'b1111001; //1
4'b0010: dig1 = 7'b0100100; //2
4'b0011: dig1 = 7'b0110000; //3
4'b0100: dig1 = 7'b0011001; //4
4'b0101: dig1 = 7'b0010010; //5
4'b0110: dig1 = 7'b0000010; //6
4'b0111: dig1 = 7'b1111000; //7
4'b1000: dig1 = 7'b0000000; //8
4'b1001: dig1 = 7'b0010000; //9
4'b1010: dig1 = 7'b0001000; //A
4'b1011: dig1 = 7'b0000011; //b
4'b1100: dig1 = 7'b1000110; //C
4'b1101: dig1 = 7'b0100001; //d
4'b1110: dig1 = 7'b0000110; //E
4'b1111: dig1 = 7'b0001110; //F
endcase
case(num_in[7:4])
4'b0000: dig2 = 7'b1000000; //0
4'b0001: dig2 = 7'b1111001; //1
4'b0010: dig2 = 7'b0100100; //2
4'b0011: dig2 = 7'b0110000; //3
4'b0100: dig2 = 7'b0011001; //4
4'b0101: dig2 = 7'b0010010; //5
4'b0110: dig2 = 7'b0000010; //6
4'b0111: dig2 = 7'b1111000; //7
4'b1000: dig2 = 7'b0000000; //8
4'b1001: dig2 = 7'b0010000; //9
4'b1010: dig2 = 7'b0001000; //A
4'b1011: dig2 = 7'b0000011; //b
4'b1100: dig2 = 7'b1000110; //C
4'b1101: dig2 = 7'b0100001; //d
4'b1110: dig2 = 7'b0000110; //E
4'b1111: dig2 = 7'b0001110; //F
endcase
case(num_in[11:8])
4'b0000: dig3 = 7'b1000000; //0
4'b0001: dig3 = 7'b1111001; //1
4'b0010: dig3 = 7'b0100100; //2
4'b0011: dig3 = 7'b0110000; //3
4'b0100: dig3 = 7'b0011001; //4
4'b0101: dig3 = 7'b0010010; //5
4'b0110: dig3 = 7'b0000010; //6
4'b0111: dig3 = 7'b1111000; //7
4'b1000: dig3 = 7'b0000000; //8
4'b1001: dig3 = 7'b0010000; //9
4'b1010: dig3 = 7'b0001000; //A
4'b1011: dig3 = 7'b0000011; //b
4'b1100: dig3 = 7'b1000110; //C
4'b1101: dig3 = 7'b0100001; //d
4'b1110: dig3 = 7'b0000110; //E
4'b1111: dig3 = 7'b0001110; //F
endcase
case(num_in[15:12])
4'b0000: dig4 = 7'b1000000; //0
4'b0001: dig4 = 7'b1111001; //1
4'b0010: dig4 = 7'b0100100; //2
4'b0011: dig4 = 7'b0110000; //3
4'b0100: dig4 = 7'b0011001; //4
4'b0101: dig4 = 7'b0010010; //5
4'b0110: dig4 = 7'b0000010; //6
4'b0111: dig4 = 7'b1111000; //7
4'b1000: dig4 = 7'b0000000; //8
4'b1001: dig4 = 7'b0010000; //9
4'b1010: dig4 = 7'b0001000; //A
4'b1011: dig4 = 7'b0000011; //b
4'b1100: dig4 = 7'b1000110; //C
4'b1101: dig4 = 7'b0100001; //d
4'b1110: dig4 = 7'b0000110; //E
4'b1111: dig4 = 7'b0001110; //F
endcase
end
always @(posedge clk) begin
dp <= 1;
neg <= 1;
clr <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int const N = 200001; int main() { int t; scanf( %d , &t); while (t--) { int n; string s, t; scanf( %d , &n); cin >> s >> t; set<int> msA[200], msB[200]; map<char, int> f; for (int i = 0; i < n; ++i) { msA[s[i]].insert(i); msB[t[i]].insert(i); ++f[s[i]], ++f[t[i]]; } bool ok = true; for (char i = a ; i <= z ; ++i) if (f[i] & 1) { ok = false; break; } vector<pair<int, int> > an; if (!ok) { puts( NO ); continue; } for (int i = 0; i < n; ++i) { if (s[i] == t[i]) continue; int sp = -1; for (int j = i + 1; j < n; ++j) { if (s[j] == s[i]) sp = j; if (s[j] != t[j] && s[j] == s[i]) { sp = j; break; } } if (~sp) { an.push_back({sp, i}); swap(s[sp], t[i]); continue; } for (int j = i + 1; j < n; ++j) { if (t[j] == s[i]) sp = j; if (s[j] != t[j] && t[j] == s[i]) { sp = j; break; } } if (~sp) { an.push_back({sp, sp}); swap(s[sp], t[sp]); an.push_back({sp, i}); swap(s[sp], t[i]); continue; } break; } if (s != t || an.size() > 2 * n) puts( NO ); else { printf( YES n%d n , an.size()); for (auto i : an) printf( %d %d n , i.first + 1, i.second + 1); } } } |
#include <bits/stdc++.h> using namespace std; int th[100080], bl[100080]; int main() { int i, j, n, k, mx = 0, sum, fl, fval; scanf( %d %d , &n, &k); for (i = 0; i < n; i++) { scanf( %d , &th[i]); } for (i = 0; i < n; i++) { scanf( %d , &bl[i]); } j = 0; i = 0; sum = 0; fl = 0; fval = th[0]; while (j < n) { while (i < k && j < n) { if (bl[j] == 0) sum += th[j]; i++; j++; } if (i == k && j <= n) { if (sum > mx) mx = sum; fl++; if (bl[fl - 1] == 0) sum -= fval; fval = th[fl]; i--; } } for (i = 0; i < n; i++) { if (bl[i] == 1) mx += th[i]; } printf( %d , mx); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, q, p[200005], a[200005], pi[200005], mra[200005], t; int mar[200005], su[200005], pr[200005], mm[200005], l, lr, r, Ilmm[200005]; vector<int> v[200005]; bool pa; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m >> q; for (int i = 1; i <= n; ++i) { cin >> p[i]; pi[p[i]] = i; } for (int i = 1; i <= m; ++i) { cin >> a[i]; } for (int i = 1; i <= m; ++i) { mar[a[i]] = i; if (pi[a[i]] == 1) { pr[i] = i; } else if (mar[p[pi[a[i]] - 1]]) { pr[i] = pr[mar[p[pi[a[i]] - 1]]]; } } for (int i = 1; i <= n; ++i) mar[i] = 0; for (int i = m; i > 0; --i) { v[a[i]].push_back(i); mar[a[i]] = i; if (pi[a[i]] == n) { su[i] = i; } else if (mar[p[pi[a[i]] + 1]]) { su[i] = su[mar[p[pi[a[i]] + 1]]]; } if (!su[i]) continue; if (pi[a[i]] > 1) { t = p[pi[a[i]] - 1]; l = 0; r = v[t].size(); --r; int tp = 0; while (l <= r) { lr = (l + r) / 2; if (pr[v[t][lr]] > su[i]) { tp = v[t][lr]; l = lr + 1; } else { r = lr - 1; } } mm[i] = tp; } else { mm[i] = su[i]; } } for (int i = m; i > 0; --i) { Ilmm[i] = Ilmm[i + 1]; if ((mm[i] && mm[i] < Ilmm[i]) || !Ilmm[i]) { Ilmm[i] = mm[i]; } } for (int i = 1; i <= q; ++i) { cin >> l >> r; pa = 0; if (Ilmm[l] && Ilmm[l] <= r) { pa = 1; } cout << pa; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_1_V
`define SKY130_FD_SC_HDLL__OR4B_1_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_1 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_1 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_BLACKBOX_V
`define SKY130_FD_SC_MS__A211O_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a211o (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long a[200001], b[200001], c[200001], d[200001], s, n, cnt[200001]; int bit(int a, int j) { return (a & (1 << j)) >> j; } int checkb() { int mb = 0; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= 29; ++j) { int x = bit(a[i], j), y = bit(b[i], j); if (x != 0) mb += cnt[j]; if (y != mb % 2) return 0; mb /= 2; } } return 1; } int checkc() { int mc = 0; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= 29; ++j) { int x = bit(a[i], j), y = bit(c[i], j); if (x != 1) mc += cnt[j]; else mc += n; if (y != mc % 2) return 0; mc /= 2; } } return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); scanf( %I64d , &n); for (int i = 1; i <= n; ++i) scanf( %I64d , &b[i]); for (int i = 1; i <= n; ++i) scanf( %I64d , &c[i]); for (int i = 1; i <= n; ++i) d[i] = b[i] + c[i], s += d[i]; s = s / (2 * n); for (int i = 1; i <= n; ++i) a[i] = (d[i] - s) / n; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= 29; ++j) { int x = bit(a[i], j); if (x) cnt[j]++; } } if (checkb() && checkc()) for (int i = 1; i <= n; ++i) printf( %I64d , a[i]); else printf( -1 ); return 0; } |
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); char *str = new char[n + 1]; scanf( %s , str); int size = strlen(str); int sum1 = 0, sum2 = 0; bool f = true; for (int i = 0; i < size / 2; ++i) { if ((str[i] == 4 || str[i] == 7 ) && (str[size - i - 1] == 4 || str[size - i - 1] == 7 )) { sum1 += str[i] - 0 ; sum2 += str[size - i - 1] - 0 ; } else { f = false; break; } } if (sum1 == sum2 && f) printf( YES n ); else printf( NO n ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int power(long long int a, long long int b) { if (b == 0) return 1; if (b == 1) return a; long long int r = power(a, b / 2) % 1000000007; if (b % 2 == 0) return (r * r) % 1000000007; else return (((r * r) % 1000000007) * a) % 1000000007; } int prime[1000009]; void sieve(int n) { prime[0] = prime[1] = 1; for (int i = 2; i <= sqrt(n); i++) { if (!prime[i]) { for (int j = 2 * i; j <= n; j++) { prime[j]++; } } } } bool comp(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { return (a.second < b.second); } const int N = 5 * 1e5 + 9; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; long long int a[n]; vector<pair<long long int, int> > v; for (int i = 0; i < n; i++) { cin >> a[i]; v.push_back({a[i], i + 1}); } sort(v.begin(), v.end()); if (n == 2 || n == 3) { cout << 1 n ; return 0; } map<long long int, long long int> mp; for (int i = 0; i < n - 1; i++) { mp[v[i + 1].first - v[i].first]++; } if (mp.size() > 3) { cout << -1 n ; return 0; } if (mp.size() == 1) { cout << v[0].second << n ; return 0; } if (n == 4) { if (v[1].first + v[3].first == 2 * v[2].first) { cout << v[0].second << n ; return 0; } if (v[0].first + v[3].first == 2 * v[2].first) { cout << v[1].second << n ; return 0; } if (v[0].first + v[3].first == 2 * v[1].first) { cout << v[2].second << n ; return 0; } if (v[0].first + v[2].first == 2 * v[1].first) { cout << v[3].second << n ; return 0; } cout << -1 n ; return 0; } for (int i = 0; i < n; i++) { if (i == 0) { mp[v[i + 1].first - v[i].first]--; if (mp[v[i + 1].first - v[i].first] == 0) { mp.erase(v[i + 1].first - v[i].first); } if (mp.size() == 1) { cout << v[0].second << n ; return 0; } mp[v[i + 1].first - v[i].first]++; } else if (i == n - 1) { mp[v[i].first - v[i - 1].first]--; if (mp[v[i].first - v[i - 1].first] == 0) { mp.erase(v[i].first - v[i - 1].first); } if (mp.size() == 1) { cout << v[n - 1].second << n ; return 0; } mp[v[i].first - v[i - 1].first]++; } else { mp[v[i + 1].first - v[i].first]--; mp[v[i].first - v[i - 1].first]--; if (mp[v[i + 1].first - v[i].first] == 0) { mp.erase(v[i + 1].first - v[i].first); } if (mp[v[i].first - v[i - 1].first] == 0) { mp.erase(v[i].first - v[i - 1].first); } mp[v[i + 1].first - v[i - 1].first]++; if (mp.size() == 1) { cout << v[i].second << n ; return 0; } mp[v[i + 1].first - v[i - 1].first]--; if (mp[v[i + 1].first - v[i - 1].first] == 0) { mp.erase(v[i + 1].first - v[i - 1].first); } mp[v[i + 1].first - v[i].first]++; mp[v[i].first - v[i - 1].first]++; } } cout << -1 n ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:03:27 10/03/2014
// Design Name:
// Module Name: topmodule
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module divider(
reset,
out,
clk
);
output out;
input clk;
input reset;
parameter divisor1 = 5;
parameter divisor2 = 2;
reg[31:0] cnt1;
reg result;
wire EN;
wire compare1,compare2;
// counter
always@(posedge clk or negedge reset)
begin
if(reset == 0)
cnt1 <= 0;
else if(cnt1 == divisor1)
cnt1 <= 1;
else
cnt1 <= cnt1 + 1;
end
//comparatorA for posedge
assign compare1 = (cnt1 == 5) ? 1 : 0;
//comparatorB for nevedge
assign compare2 = (cnt1 == divisor2) ? 1 : 0;
assign EN = compare1 | compare2;
// D-type flip-flop output
// posedge clk && (compareA || compareB) ???
always@(posedge clk or negedge reset)
begin
if(reset == 0)
result <= 0;
else if(EN)
result <= !result;
// do nothing
end
assign out = result;
endmodule
|
//======================================================================
//
// coretest_hashes.v
// -----------------
// Top level wrapper that creates the Cryptech coretest system.
// The wrapper contains instances of external interface, coretest
// and the core to be tested. And if more than one core is
// present the wrapper also includes address and data muxes.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module coretest_hashes(
input wire clk,
input wire reset_n,
// External interface.
input wire rxd,
output wire txd,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter UART_ADDR_PREFIX = 8'h00;
parameter SHA1_ADDR_PREFIX = 8'h10;
parameter SHA256_ADDR_PREFIX = 8'h20;
parameter SHA512_ADDR_PREFIX = 8'h30;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
// Coretest connections.
wire coretest_reset_n;
wire coretest_cs;
wire coretest_we;
wire [15 : 0] coretest_address;
wire [31 : 0] coretest_write_data;
reg [31 : 0] coretest_read_data;
reg coretest_error;
// uart connections
wire uart_rxd_syn;
wire [7 : 0] uart_rxd_data;
wire uart_rxd_ack;
wire uart_txd_syn;
wire [7 : 0] uart_txd_data;
wire uart_txd_ack;
reg uart_cs;
reg uart_we;
reg [7 : 0] uart_address;
reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data;
wire uart_error;
wire [7 : 0] uart_debug;
// sha1 connections.
reg sha1_cs;
reg sha1_we;
reg [7 : 0] sha1_address;
reg [31 : 0] sha1_write_data;
wire [31 : 0] sha1_read_data;
wire sha1_error;
wire [7 : 0] sha1_debug;
// sha256 connections.
reg sha256_cs;
reg sha256_we;
reg [7 : 0] sha256_address;
reg [31 : 0] sha256_write_data;
wire [31 : 0] sha256_read_data;
wire sha256_error;
wire [7 : 0] sha256_debug;
// sha512 connections.
reg sha512_cs;
reg sha512_we;
reg [7 : 0] sha512_address;
reg [31 : 0] sha512_write_data;
wire [31 : 0] sha512_read_data;
wire sha512_error;
wire [7 : 0] sha512_debug;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign debug = uart_debug;
//----------------------------------------------------------------
// Core instantiations.
//----------------------------------------------------------------
coretest coretest(
.clk(clk),
.reset_n(reset_n),
.rx_syn(uart_rxd_syn),
.rx_data(uart_rxd_data),
.rx_ack(uart_rxd_ack),
.tx_syn(uart_txd_syn),
.tx_data(uart_txd_data),
.tx_ack(uart_txd_ack),
// Interface to the core being tested.
.core_reset_n(coretest_reset_n),
.core_cs(coretest_cs),
.core_we(coretest_we),
.core_address(coretest_address),
.core_write_data(coretest_write_data),
.core_read_data(coretest_read_data),
.core_error(coretest_error)
);
uart uart(
.clk(clk),
.reset_n(reset_n),
.rxd(rxd),
.txd(txd),
.rxd_syn(uart_rxd_syn),
.rxd_data(uart_rxd_data),
.rxd_ack(uart_rxd_ack),
.txd_syn(uart_txd_syn),
.txd_data(uart_txd_data),
.txd_ack(uart_txd_ack),
.cs(uart_cs),
.we(uart_we),
.address(uart_address),
.write_data(uart_write_data),
.read_data(uart_read_data),
.error(uart_error),
.debug(uart_debug)
);
sha1 sha1(
// Clock and reset.
.clk(clk),
.reset_n(reset_n),
// Control.
.cs(sha1_cs),
.we(sha1_we),
// Data ports.
.address(sha1_address),
.write_data(sha1_write_data),
.read_data(sha1_read_data),
.error(sha1_error)
);
sha256 sha256(
// Clock and reset.
.clk(clk),
.reset_n(reset_n),
// Control.
.cs(sha256_cs),
.we(sha256_we),
// Data ports.
.address(sha256_address),
.write_data(sha256_write_data),
.read_data(sha256_read_data),
.error(sha256_error)
);
sha512 sha512(
// Clock and reset.
.clk(clk),
.reset_n(reset_n),
// Control.
.cs(sha512_cs),
.we(sha512_we),
// Data ports.
.address(sha512_address),
.write_data(sha512_write_data),
.read_data(sha512_read_data),
.error(sha512_error)
);
//----------------------------------------------------------------
// address_mux
//
// Combinational data mux that handles addressing between
// cores using the 32-bit memory like interface.
//----------------------------------------------------------------
always @*
begin : address_mux
// Default assignments.
coretest_read_data = 32'h00000000;
coretest_error = 0;
uart_cs = 0;
uart_we = 0;
uart_address = 8'h00;
uart_write_data = 32'h00000000;
sha1_cs = 0;
sha1_we = 0;
sha1_address = 8'h00;
sha1_write_data = 32'h00000000;
sha256_cs = 0;
sha256_we = 0;
sha256_address = 8'h00;
sha256_write_data = 32'h00000000;
sha512_cs = 0;
sha512_we = 0;
sha512_address = 8'h00;
sha512_write_data = 32'h00000000;
case (coretest_address[15 : 8])
UART_ADDR_PREFIX:
begin
uart_cs = coretest_cs;
uart_we = coretest_we;
uart_address = coretest_address[7 : 0];
uart_write_data = coretest_write_data;
coretest_read_data = uart_read_data;
coretest_error = uart_error;
end
SHA1_ADDR_PREFIX:
begin
sha1_cs = coretest_cs;
sha1_we = coretest_we;
sha1_address = coretest_address[7 : 0];
sha1_write_data = coretest_write_data;
coretest_read_data = sha1_read_data;
coretest_error = sha1_error;
end
SHA256_ADDR_PREFIX:
begin
sha256_cs = coretest_cs;
sha256_we = coretest_we;
sha256_address = coretest_address[7 : 0];
sha256_write_data = coretest_write_data;
coretest_read_data = sha256_read_data;
coretest_error = sha256_error;
end
SHA512_ADDR_PREFIX:
begin
sha512_cs = coretest_cs;
sha512_we = coretest_we;
sha512_address = coretest_address[7 : 0];
sha512_write_data = coretest_write_data;
coretest_read_data = sha512_read_data;
coretest_error = sha512_error;
end
default:
begin
end
endcase // case (coretest_address[15 : 8])
end // address_mux
endmodule // coretest_hashes
//======================================================================
// EOF coretest_hashes.v
//======================================================================
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// mem512b is 512 bytes synchronous memory, which maps directly to the EAB memory block of ACEX1K.
// rdaddr is read address, dataout is the data read. Data is read with 1-clock latency, i.e. it
// appears after the positive clock edge, which locked rdaddr.
// wraddr is write address, datain is data to be written. we enables write to memory: when it
// locks as being 1 at positive clock edge, data contained at datain is written to wraddr location.
//
// clk __/``\__/``\__/``\__/``\__/``
// rdaddr |addr1|addr2|
// dataout |data1|data2|
// wraddr |addr3|addr4|
// datain |data3|data4|
// we _________/```````````\_______
//
// data1 is the data read from addr1, data2 is read from addr2
// data3 is written to addr3, data4 is written to addr4
//
// simultaneous write and read to the same memory address lead to undefined read data.
module mem512b
(
input wire clk,
input wire re,
input wire [8:0] rdaddr,
output reg [7:0] dataout,
input wire we,
input wire [8:0] wraddr,
input wire [7:0] datain
);
reg [7:0] mem[0:511]; // memory block
always @(posedge clk)
if( re )
dataout <= mem[rdaddr];
always @(posedge clk)
if( we )
mem[wraddr] <= datain;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// C backend 'push' primitive
//
// Upstream are signals that go to the feedback (snk node is a acl_pop),
// downstream are signals that continue into our "normal" pipeline.
//
// dir indicates if you want to push it to the feedback
// 1 - push to feedback
// 0 - bypass, just push out to downstream
//===----------------------------------------------------------------------===//
module acl_push (
clock,
resetn,
// interface from kernel pipeline, input stream
dir,
data_in,
valid_in,
stall_out,
predicate,
// interface to kernel pipeline, downstream
valid_out,
stall_in,
data_out,
// interface to pipeline feedback, upstream
feedback_out,
feedback_valid_out,
feedback_stall_in
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 1;
parameter MIN_FIFO_LATENCY = 0;
// style can be "REGULAR", for a regular push
// or "TOKEN" for a special fifo that hands out tokens
parameter string STYLE = "REGULAR"; // "REGULAR"/"TOKEN"
parameter STALLFREE = 0;
input clock, resetn, stall_in, valid_in, feedback_stall_in;
output stall_out, valid_out, feedback_valid_out;
input [DATA_WIDTH-1:0] data_in;
input dir;
input predicate;
output [DATA_WIDTH-1:0] data_out, feedback_out;
wire [DATA_WIDTH-1:0] feedback;
wire data_downstream, data_upstream;
wire push_upstream;
assign push_upstream = dir & ~predicate;
assign data_upstream = valid_in & push_upstream;
assign data_downstream = valid_in;
wire feedback_stall, feedback_valid;
reg consumed_downstream, consumed_upstream;
assign valid_out = data_downstream & !consumed_downstream;
assign feedback_valid = data_upstream & !consumed_upstream;
assign data_out = data_in;
assign feedback = data_in;
//assign stall_out = valid_in & ( ~(data_downstream & ~stall_in) & ~(data_upstream & ~feedback_stall));
// assign stall_out = valid_in & ( ~(data_downstream & ~stall_in) | ~(data_upstream & ~feedback_stall));
assign stall_out = stall_in | (feedback_stall & push_upstream );
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
consumed_downstream <= 1'b0;
consumed_upstream <= 1'b0;
end else begin
if (consumed_downstream)
consumed_downstream <= stall_out;
else
consumed_downstream <= stall_out & (data_downstream & ~stall_in);
if (consumed_upstream)
consumed_upstream <= stall_out;
else
consumed_upstream <= stall_out & (data_upstream & ~feedback_stall);
end
end
localparam TYPE = MIN_FIFO_LATENCY < 1 ? (FIFO_DEPTH < 8 ? "zl_reg" : "zl_ram") : (MIN_FIFO_LATENCY < 3 ? (FIFO_DEPTH < 8 ? "ll_reg" : "ll_ram") : (FIFO_DEPTH < 8 ? "ll_reg" : "ram"));
generate
if ( STYLE == "TOKEN" )
begin
acl_token_fifo_counter
#(
.DEPTH(FIFO_DEPTH)
)
fifo (
.clock(clock),
.resetn(resetn),
.data_out(feedback_out),
.valid_in(feedback_valid),
.valid_out(feedback_valid_out),
.stall_in(feedback_stall_in),
.stall_out(feedback_stall)
);
end
else if (FIFO_DEPTH == 0) begin
// if no FIFO depth is requested, just connect
// feedback directly to output
assign feedback_out = feedback;
assign feedback_valid_out = feedback_valid;
assign feedback_stall = feedback_stall_in;
end
else if (FIFO_DEPTH == 1 && MIN_FIFO_LATENCY == 0) begin
// simply add a staging register if the requested depth is 1
// and the latency must be 0
acl_staging_reg #(
.WIDTH(DATA_WIDTH)
) staging_reg (
.clk(clock),
.reset(~resetn),
.i_data(feedback),
.i_valid(feedback_valid),
.o_stall(feedback_stall),
.o_data(feedback_out),
.o_valid(feedback_valid_out),
.i_stall(feedback_stall_in)
);
end
else
begin
// only allow full write in stall free clusters if you're an ll_reg
// otherwise, comb cycles can form, since stall_out depends on
// stall_in the acl_data_fifo. To make up for the last space, we
// add a capacity of 1 to the FIFO
localparam OFFSET = ( (TYPE == "ll_reg") && !STALLFREE ) ? 1 : 0;
localparam ALLOW_FULL_WRITE = ( (TYPE == "ll_reg") && !STALLFREE ) ? 0 : 1;
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(((TYPE == "ram") || (TYPE == "ll_ram") || (TYPE == "zl_ram")) ? FIFO_DEPTH + 1 : FIFO_DEPTH + OFFSET),
.IMPL(TYPE),
.ALLOW_FULL_WRITE(ALLOW_FULL_WRITE)
)
fifo (
.clock(clock),
.resetn(resetn),
.data_in(feedback),
.data_out(feedback_out),
.valid_in(feedback_valid),
.valid_out(feedback_valid_out),
.stall_in(feedback_stall_in),
.stall_out(feedback_stall)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod1 = 1000000007; const long long mod2 = 998244353; mt19937 rng( (unsigned int)chrono::steady_clock::now().time_since_epoch().count()); long long power(long long a, long long b) { long long result = 1; while (b > 0) { if (b % 2 == 1) { result *= a; } a *= a; b /= 2; } return result; } long long gcd(long long x, long long y) { long long r; while (y != 0 && (r = x % y) != 0) { x = y; y = r; } return y == 0 ? x : y; } long long countSetBits(long long x) { long long Count = 0; while (x > 0) { if (x & 1) Count++; x = x >> 1; } return Count; } long long mod(long long x, long long M) { return ((x % M + M) % M); } long long add(long long a, long long b, long long M) { return mod(mod(a, M) + mod(b, M), M); } long long mul(long long a, long long b, long long M) { return mod(mod(a, M) * mod(b, M), M); } long long powerM(long long a, long long b, long long M) { long long res = 1ll; while (b) { if (b % 2ll == 1ll) { res = mul(a, res, M); } a = mul(a, a, M); b /= 2ll; } return res; } void solve() { long long h, w; cin >> w >> h; long long x; cin >> x; vector<long long> v(x); for (long long i = 0; i < x; i++) { cin >> v[i]; } long long y; cin >> y; vector<long long> v1(y); for (long long i = 0; i < y; i++) { cin >> v1[i]; } long long z; cin >> z; vector<long long> v2(z); for (long long i = 0; i < z; i++) { cin >> v2[i]; } long long a; cin >> a; vector<long long> v3(a); for (long long i = 0; i < a; i++) { cin >> v3[i]; } sort(v.begin(), v.end()); sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); sort(v3.begin(), v3.end()); long long t = max(v[x - 1] - v[0], v1[y - 1] - v1[0]); long long ans1 = t * h; long long t1 = max(v2[z - 1] - v2[0], v3[a - 1] - v3[0]); long long ans2 = t1 * w; cout << max(ans2, ans1) << n ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cout << fixed << setprecision(20); long long t = 1; cin >> t; for (long long i = 1; i <= t; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e9 + 3; long long n, sum; vector<int> vec; int32_t main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = n - 100; i <= n; i++) { long long x = i; while (x) { sum += x % 10; x /= 10; } sum += i; if (sum == n) vec.push_back(i); sum = 0; } cout << vec.size() << endl; for (int i = 0; i < vec.size(); i++) cout << vec[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct data { int le, ri, cnt; data(int le_ = 0, int ri_ = 0, int cnt_ = 0) { le = le_; ri = ri_; cnt = cnt_; } }; const int N = 1e6 + 10; int seg[4 * N + 10]; int brk[5][4 * N + 10]; int n; void add(int idx, bool b, int L = 0, int R = n, int id = 1) { if (L == R - 1) { brk[b][id]++; return; } int mid = (L + R) / 2; if (idx < mid) add(idx, b, L, mid, 2 * id + 0); else add(idx, b, mid, R, 2 * id + 1); seg[id] = seg[2 * id + 0] + seg[2 * id + 1] + min(brk[0][2 * id + 0], brk[1][2 * id + 1]); brk[0][id] = brk[0][2 * id + 1] + max(0, brk[0][2 * id + 0] - brk[1][2 * id + 1]); brk[1][id] = brk[1][2 * id + 0] + max(0, brk[1][2 * id + 1] - brk[0][2 * id + 0]); return; } data get(int l, int r, int L = 0, int R = n, int id = 1) { if (L == l && R == r) return data(brk[0][id], brk[1][id], seg[id]); int mid = (L + R) / 2; data le, ri; if (l < mid) le = get(l, min(r, mid), L, mid, 2 * id + 0); if (r > mid) ri = get(max(l, mid), r, mid, R, 2 * id + 1); data ret; ret.cnt = le.cnt + ri.cnt + min(le.le, ri.ri); ret.le = ri.le + max(0, le.le - ri.ri); ret.ri = le.ri + max(0, ri.ri - le.le); return ret; } int main() { ios_base::sync_with_stdio(false); string s; cin >> s, n = s.size(); for (int i = 0; i < s.size(); i++) if (s[i] == ( ) add(i, 0); else add(i, 1); int q; cin >> q; while (q--) { int l, r; cin >> l >> r, l--; cout << 2 * get(l, r).cnt << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return x * f; } int n, k, a[201010]; long long f[201010][2]; long long power(long long x, long long p) { long long res = 1; while (p) { if (p & 1) res = res * x % 998244353; x = x * x % 998244353; p >>= 1; } return res; } long long dp(int l, int r, int len) { if (len == 0) { if (l == r && l != 0 && r != 0) return 0; return 1; } if (r == 0) { return (l == 0 ? k : (k - 1)) * power(k - 1, len - 1) % 998244353; } for (int i = 0; i <= len; i++) f[i][0] = f[i][1] = 0; if (l == 0) f[0][0] = k - 1, f[0][1] = 1, len--; else if (l == r) f[0][1] = 1; else f[0][0] = 1; for (int i = 1; i <= len; i++) { f[i][0] = (f[i][0] + f[i - 1][0] * (k - 2) + f[i - 1][1] * (k - 1)) % 998244353; f[i][1] = f[i - 1][0]; } return f[len][0]; } int main() { n = read(), k = read(); long long ans = 1; for (int i = 1; i <= n; i++) a[i] = read(); int lst = -1; for (int i = 1; i <= n + 2; i += 2) if (a[i] != -1) ans = ans * dp(a[lst], a[i], (i - lst) / 2 - 1) % 998244353, lst = i; lst = 0; for (int i = 2; i <= n + 2; i += 2) if (a[i] != -1) ans = ans * dp(a[lst], a[i], (i - lst) / 2 - 1) % 998244353, lst = i; cout << ans; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__MUX2_FUNCTIONAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ms__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int maxint = -1u >> 2; const double eps = 1e-6; const int MAX = 100001; int CA[MAX]; int CB[MAX]; int main() { int N; cin >> N; int ans = N + 1; if (N == 1 || N == 2) { cout << 0 << endl; return 0; } vector<int> A(N); vector<int> B(N); map<int, int> MA; map<int, int> MB; int half = N / 2; if (N % 2) half += 1; for (int i = 0; i < N; ++i) { int a, b; cin >> a >> b; if (a != b) { MB[b] = MB[b] + 1; } MA[a] = MA[a] + 1; if (MA[a] >= half) { cout << 0 << endl; return 0; } if (MB[b] >= half) { ans = min(ans, MB[b]); } } for (map<int, int>::iterator itr = MA.begin(); itr != MA.end(); ++itr) { if (itr->second + MB[itr->first] >= half) { ans = min(ans, half - itr->second); } } if (ans == N + 1) { cout << -1 << endl; } else cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { set<int> co[2]; set<pair<int, int> > delta[2]; int w, h, n; scanf( %d%d%d , &w, &h, &n); co[0].insert(0); co[0].insert(w); delta[0].insert(make_pair(w, 0)); co[1].insert(0); co[1].insert(h); delta[1].insert(make_pair(h, 0)); for (int i = (0), _end_ = (n); i < _end_; ++i) { static char s[2]; static int first; scanf( %s%d , s, &first); int ty = s[0] == H ; co[ty].insert(first); auto it = co[ty].lower_bound(first); auto tmp = it; --tmp; ++it; delta[ty].erase(make_pair(*it - *tmp, *tmp)); delta[ty].insert(make_pair(first - *tmp, *tmp)); delta[ty].insert(make_pair(*it - first, first)); printf( %I64d n , (long long)delta[0].rbegin()->first * delta[1].rbegin()->first); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); if (n < 6) printf( -1 n ); else { printf( 1 2 n2 3 n2 4 n3 5 n3 6 n ); for (int i = 7; i <= n; i++) printf( 3 %d n , i); } for (int i = 2; i <= n; i++) printf( %d %d n , i - 1, i); return 0; } |
#include <bits/stdc++.h> using namespace std; long long po(long long a, long long b) { long long x = 1, y = a; while (b > 0) { if (b % 2) { x = x * y; x %= 1000000007; } y = y * y; y %= 1000000007; b /= 2; } return x; } int main() { if (0) { freopen( C:/Users/gold/Desktop/sublime IO/input.txt , r , stdin); freopen( C:/Users/gold/Desktop/sublime IO/output.txt , w , stdout); } int T = 1; while (T--) { string s, s1; cin >> s >> s1; int n = s.length(); static int cnt[256]; for (int i = 0; i < n; i++) { cnt[s[i]]++; } int m = s1.length(); int ans = 0, ans1 = 0; for (int i = 0; i < m; i++) { if (cnt[s1[i]] > 0) { cnt[s1[i]]--; ans++; s1[i] = 1 ; } } for (int i = 0; i < m; i++) { if (s1[i] == 1 ) { continue; } if (s1[i] >= a && cnt[s1[i] - a + A ] > 0) { ans1++; cnt[s1[i] - a + A ]--; } else if (cnt[s1[i] - A + a ] > 0) { ans1++; cnt[s1[i] - A + a ]--; } } printf( %d %d n , ans, ans1); } return 0; } |
#include <bits/stdc++.h> const int maxn = 1e5 + 5, lim = 62, maxm = 65; const long long inf = 1e18; template <typename T> inline T min(T a, T b) { return a < b ? a : b; } int n; long long a[maxn], mod, dp[maxm][maxn]; inline bool Comp(long long a, long long b) { return a > b; } void radix_sort() { std::vector<long long> bit[2]; for (int i = 1; i <= n; i++) { bit[(a[i] & (1ll << (mod - 1))) > 0ll].push_back(a[i]); } int cnt = 0; for (int i = 0; i < bit[1].size(); i++) a[++cnt] = bit[1][i]; for (int i = 0; i < bit[0].size(); i++) a[++cnt] = bit[0][i]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); std::sort(a + 1, a + n + 1, Comp); for (int i = n; i >= 1; i--) a[i] = a[1] - a[i]; for (int i = 0; i <= lim; i++) for (int j = 0; j <= n; j++) dp[i][j] = inf; dp[0][0] = 0; for (int i = 0; i < lim; i++) { mod = i; if (i) radix_sort(); long long cnt = 0, tot = 0; mod = 1ll << i; for (int j = 1; j <= n; j++) cnt += a[j] & mod ? 1 : 0; for (int j = 0; j <= n; j++) { tot += a[j] & mod ? 1 : 0; dp[i + 1][cnt - tot + j] = min(dp[i + 1][cnt - tot + j], dp[i][j] + tot + (n - j) - (cnt - tot)); dp[i + 1][tot] = min(dp[i + 1][tot], dp[i][j] + j - tot + cnt - tot); } } printf( %lld n , dp[lim][0]); return 0; } |
module myAddSub(A,B,CI,ADD,BOP,Y,CO,OVF);
input [7:0] A;
input [7:0] B;
input CI;
input ADD;
input BOP;
output [7:0] Y;
output CO;
output OVF;
//------------------------------------------------------------
// This is an ADDER/SUBTRACTOR based on the adder subtractor
// that is in the schematic capture library. I added another
// control input that zeros out the B input so that this thing
// can also be used as an incrementer/decrementer depeding on
// the carry input.
//
// parameter:
// A............8 bit bus, input A of Adder/Subtractor
// B............8 bit bus, input B of Adder/Subtractor
// CI...........Carry/nBorrow input
// ADD..........if true, perform addition, 0 perform subtraction
// BOP..........if 1, pass B input, if 0, B = 0
// Y............8 bit bus, 8 bit sum output
// CO...........Carry/nBorrow output
// OVF..........overflow status output
//
//-------------------------------------------------------------
reg[7:0] I;
wire [7:0] Y;
wire C0,C1,C2,C3,C4,C5,C6;
wire C6O;
always @(A or B or CI or ADD or BOP)
begin
I[0] = A[0] ^ (B[0] & BOP) ^ ~ADD;
I[1] = A[1] ^ (B[1] & BOP) ^ ~ADD;
I[2] = A[2] ^ (B[2] & BOP) ^ ~ADD;
I[3] = A[3] ^ (B[3] & BOP) ^ ~ADD;
I[4] = A[4] ^ (B[4] & BOP) ^ ~ADD;
I[5] = A[5] ^ (B[5] & BOP) ^ ~ADD;
I[6] = A[6] ^ (B[6] & BOP) ^ ~ADD;
I[7] = A[7] ^ (B[7] & BOP) ^ ~ADD;
end
MUXCY_L MUXCY_L0 (.LO(C0),.CI(CI),.DI(A[0]),.S(I[0]) );
MUXCY_L MUXCY_L1 (.LO(C1),.CI(C0),.DI(A[1]),.S(I[1]) );
MUXCY_L MUXCY_L2 (.LO(C2),.CI(C1),.DI(A[2]),.S(I[2]) );
MUXCY_L MUXCY_L3 (.LO(C3),.CI(C2),.DI(A[3]),.S(I[3]) );
MUXCY_L MUXCY_L4 (.LO(C4),.CI(C3),.DI(A[4]),.S(I[4]) );
MUXCY_L MUXCY_L5 (.LO(C5),.CI(C4),.DI(A[5]),.S(I[5]) );
MUXCY_D MUXCY_D6 (.LO(C6),.O(C6O),.CI(C5),.DI(A[6]),.S(I[6]) );
MUXCY MUXCY_7 (.O(CO),.CI(C6),.DI(A[7]),.S(I[7]) );
XORCY XORCY0 (.O(Y[0]),.CI(CI), .LI(I[0]));
XORCY XORCY1 (.O(Y[1]),.CI(C0),.LI(I[1]));
XORCY XORCY2 (.O(Y[2]),.CI(C1),.LI(I[2]));
XORCY XORCY3 (.O(Y[3]),.CI(C2),.LI(I[3]));
XORCY XORCY4 (.O(Y[4]),.CI(C3),.LI(I[4]));
XORCY XORCY5 (.O(Y[5]),.CI(C4),.LI(I[5]));
XORCY XORCY6 (.O(Y[6]),.CI(C5),.LI(I[6]));
XORCY XORCY7 (.O(Y[7]),.CI(C6),.LI(I[7]));
XOR2 X1(.O(OVF),.I0(C6O),.I1(CO));
endmodule
|
#include<bits/stdc++.h> using namespace std; long long q,n,c[400005],z,ans,mn=1e14,d,x; map<long long,long long>las,ll; vector<long long>v; struct am{ long long va,ind; }; am a[400005]; bool cmp(am zz,am y){ return zz.ind<y.ind; } set<long long>st; int main(){ ios::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); cin>>q; while (q--){ cin>>n; st.clear(); v.clear(); las.clear(); ll.clear(); mn=1e14; for (long long i=1;i<=n;i++){ cin>>x; las[x]++; } z=1; for (auto it=las.begin();it!=las.end();it++){ a[z].va=it->first; a[z].ind=it->second; z++; } sort (a+1,a+z,cmp); for (long long i=z-1;i>=1;i--){ x=st.size(); mn=min(mn,n-(a[i].ind + a[i].ind*x)); st.insert(a[i].va); } cout<<mn<< n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_SYMBOL_V
`define SKY130_FD_SC_LP__ISO0P_SYMBOL_V
/**
* iso0p: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 1.01e9; const double eps = 1e-9; const int N = 1010; char s[N][N]; char res[N * N]; int resc = 0; char ch[4] = { D , L , R , U }; int dx[4] = {1, 0, 0, -1}; int dy[4] = {0, -1, 1, 0}; pair<int, int> q[N * N]; int st = 0, en = 0; int d[N][N]; int n, m; void bfs(int x, int y) { for (int i = 0; (i) < (n); ++i) for (int j = 0; (j) < (m); ++j) d[i][j] = inf; d[x][y] = 0; q[en++] = {x, y}; while (st < en) { x = q[st].first; y = q[st].second; st++; for (int i = 0; (i) < (4); ++i) { int xx = x + dx[i]; int yy = y + dy[i]; if (0 <= xx && xx < n && 0 <= yy && yy < m && s[xx][yy] == . && d[xx][yy] == inf) { d[xx][yy] = d[x][y] + 1; q[en++] = {xx, yy}; } } } } int main() { int k; scanf( %d%d%d , &n, &m, &k); if (k & 1) { printf( IMPOSSIBLE n ); return 0; } for (int i = 0; (i) < (n); ++i) scanf( %s , s[i]); int px = -1, py = -1; for (int i = 0; (i) < (n); ++i) for (int j = 0; (j) < (m); ++j) if (s[i][j] == X ) { px = i; py = j; s[i][j] = . ; } bfs(px, py); int x = px, y = py; for (int it = 0; (it) < (k); ++it) { int ok = 0; for (int i = 0; (i) < (4); ++i) { int xx = x + dx[i]; int yy = y + dy[i]; if (0 <= xx && xx < n && 0 <= yy && yy < m && d[xx][yy] <= k - it - 1) { res[resc++] = ch[i]; x = xx; y = yy; ok = 1; break; } } if (!ok) { printf( IMPOSSIBLE n ); return 0; } } printf( %s n , res); return 0; } |
/*
* This test runs the random number generator to make sure
* it follows the standard algorithm. It is based on the bug
* report from PR#995.
*/
module pr995 ();
integer seed;
integer i;
integer result;
initial begin
seed = 1;
$display ("Start sequence: seed=%h", seed);
result=$random(seed);
$display ("seed=%h result=%h", seed, result);
for (i=0; i<30; i=i+1) begin
result=$random(seed);
$display ("seed=%h result=%h", seed, result);
end
seed = 2;
$display ("Start sequence: seed=%h", seed);
result=$random(seed);
$display ("seed=%h result=%h", seed, result);
for (i=0; i<30; i=i+1) begin
result=$random(seed);
$display ("seed=%h result=%h", seed, result);
end
seed = 1;
$display ("Start sequence: seed=%h", seed);
result=$random(seed);
$display ("seed=%h result=%h", seed, result);
for (i=0; i<30; i=i+1) begin
result=$random(seed);
$display ("seed=%h result=%h", seed, result);
end
end
endmodule // rand
|
#include <bits/stdc++.h> using namespace std; int t; int n; int a[5001]; bool coutNO; vector<int> check[5001]; int main() { cin.tie(0); cout.tie(0); cin >> t; for (int ct = 1; ct <= t; ct++) { cin >> n; coutNO = true; for (int i = 1; i <= n; i++) check[i].clear(); for (int i = 1; i <= n; i++) { cin >> a[i]; check[a[i]].push_back(i); if (check[a[i]].size() >= 3) coutNO = false; } if (!coutNO) { cout << YES << n ; continue; } for (int i = 1; i <= n; i++) if (check[i].size() == 2) { if (check[i][0] + 1 != check[i][1]) { coutNO = false; break; } } if (coutNO) cout << NO << n ; else cout << YES << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_1_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_1_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog wrapper for tapvpwrvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvpwrvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__tapvpwrvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_1_V
|
#include <bits/stdc++.h> using namespace std; long long a[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, i; cin >> n; long long mx = -1, mn = 1e18; for (i = 0; i < n; i++) { cin >> a[i]; mn = min(mn, a[i]); mx = max(mx, a[i]); } long long cnt = 0; if (n < 3) cout << 0 << endl; else { for (i = 0; i < n; i++) { if (a[i] > mn && a[i] < mx) cnt++; } cout << cnt << endl; } } |
////////////////////////////////////////////////////////////////////////////////
// infrared_control: sub-modulo de genius_top que recebe e interpreta sinal IR.
//
// O sinal de IR recebido (ativacao baixa, mas invertido nos inputs) segue um
// padrao de ondas que se repete durante seu pressionamento, em uma estrutura de
// aproximadamente 34 bits.
// Neste projeto analisamos o comportamento do sinais dos botoes direcionais de
// um controle de DVD Sony atraves do SignalTap II da Altera a um clock de 38
// KHz.
// Constatamos que a diferenca entre um botao e outro ocorre proximo do nono bit
// do sinal, com cada bit durando em media 20 pulsos de clock. Contamos entao os
// pulsos de clock e conferimos o estado do bit nessa marca, com um avanco de 10
// bits para englobar quaisquer variacoes. Imagens desses sinais estao salvas na
// pasta ir_sinais;
// Detectado um padrao de botao, seguramos esse valor por 0.25 segundo
// e ignoramos inputs seguintes por 1.5 segundos.
//
// Os comentarios dos inputs fornecem suas descricoes e de onde vem.
// Os dos outputs fornecem suas descricoes e para onde vao.
////////////////////////////////////////////////////////////////////////////////
module infrared_control(
input infrared, // sinal de ir, input de genius_top
input clk, // clock 38 KHz, output de pll
input reset, // sinal de reset, input de genius_top
output reg led, // sinal para led vermelho 0, output de genius_top
output reg botao_1, // sinal para botao 1, input de fsm_top
output reg botao_2, // sinal para botao 2, input de fsm_top
output reg botao_3, // sinal para botao 3, input de fsm_top
output reg botao_4 // sinal para botao 4, input de fsm_top
);
// Inteiros auxiliares
integer count; // contagem de clocks entre pulsos
// Registradores de estado
reg estado_atual;
reg estado_prox;
// Parametros de estado
parameter IDLE = 0; // arguarda input (inicial)
parameter PRESS = 1; // detecta pressionamento
parameter BOT14 = 2; // botao 1 ou 4 pressionado
parameter BOT23 = 3; // botao 2 ou 3 pressionado
parameter KEEP1 = 4; // mantem botao 1 pressionado
parameter KEEP2 = 5; // mantem botao 2 pressionado
parameter KEEP3 = 6; // mantem botao 3 pressionado
parameter KEEP4 = 7; // mantem botao 4 pressionado
// Parametros de medida de tempo para clk 3.8 KHz
parameter T_IGNOR = 57000; // tempo de ignorancia de inputs (1.5s)
parameter T_PRESS = 950; // tempo de pressionamento do botao (0.25s)
// Pisca led a cada pulso recebido
always@(posedge clk) begin
if(infrared == 1) begin
led = 1;
end
else begin
led = 0;
end
end
// Incrementa contador de pulsos
always@(posedge clk)begin
case(estado_atual)
PRESS: count = count + 1;
BOT14: count = count + 1;
BOT23: count = count + 1;
KEEP1: count = count + 1;
KEEP2: count = count + 1;
KEEP3: count = count + 1;
KEEP4: count = count + 1;
default: count = 0;
endcase
end
// Decodificador de estados
always@(*) begin
case(estado_atual)
// Quando detectada alguma atividade comeca reconhecimento
IDLE: begin
if(infrared == 1) begin
estado_prox = PRESS;
end
else begin
estado_prox = IDLE;
end
end
// Procura diferenca de padroes entre botoes
PRESS: begin
if(count >= 130) begin
if(infrared == 1) begin
estado_prox = BOT14;
end
else begin
estado_prox = BOT23;
end
end
else begin
estado_prox = PRESS;
end
end
// Detecta diferenca entre botoes 1 e 4
BOT14: begin
if(count >= 190) begin
if(infrared == 1) begin
estado_prox = KEEP4;
end
else begin
estado_prox = KEEP1;
end
end
else begin
estado_prox = BOT14;
end
end
// Detecta diferenca entre botoes 2 e 3
BOT23: begin
if(count >= 170) begin
if(infrared == 1) begin
estado_prox = KEEP3;
end
else begin
estado_prox = KEEP2;
end
end
else begin
estado_prox = BOT23;
end
end
// Ignora input durante um tempo nos proximos 4 estados
KEEP1: begin
if(count >= T_IGNOR) begin
estado_prox = IDLE;
end
else begin
estado_prox = KEEP1;
end
end
KEEP2: begin
if(count >= T_IGNOR) begin
estado_prox = IDLE;
end
else begin
estado_prox = KEEP2;
end
end
KEEP3: begin
if(count >= T_IGNOR) begin
estado_prox = IDLE;
end
else begin
estado_prox = KEEP3;
end
end
KEEP4: begin
if(count >= T_IGNOR) begin
estado_prox = IDLE;
end
else begin
estado_prox = KEEP4;
end
end
// Caso estado nao identificado, retorna ao inicial
default: begin
estado_prox = IDLE;
end
endcase
end
// Atualiza registradores
always@(posedge clk) begin
if(reset) begin
estado_atual <= IDLE;
end
else begin
estado_atual <= estado_prox;
end
end
// Decodificador de saidas
always@(*) begin
case(estado_atual)
// Nos 2 estados seguintes se detecta a difereca no padrao de input e
// ativa o botao equivalente.
BOT14: begin
if(count >= 190) begin
if(infrared == 1) begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 1;
end
else begin
botao_1 = 1;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
end
else begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
end
BOT23: begin
if(count >= 170) begin
if(infrared == 1) begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 1;
botao_4 = 0;
end
else begin
botao_1 = 0;
botao_2 = 1;
botao_3 = 0;
botao_4 = 0;
end
end
else begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
end
// Nos 4 estados seguintes se mantem o botao pressionado por aprox 0.5
// segundos, ignorando inputs durante esse tempo.
KEEP1: begin
if(count >= T_PRESS) begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
else begin
botao_1 = 1;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
end
KEEP2: begin
if(count >= T_PRESS) begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
else begin
botao_1 = 0;
botao_2 = 1;
botao_3 = 0;
botao_4 = 0;
end
end
KEEP3: begin
if(count >= T_PRESS) begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
else begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 1;
botao_4 = 0;
end
end
KEEP4: begin
if(count >= T_PRESS) begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
else begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 1;
end
end
// Caso qualquer outro estado, botoes nao sao ativados
default: begin
botao_1 = 0;
botao_2 = 0;
botao_3 = 0;
botao_4 = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void Oli() { int a; cin >> a; vector<pair<int, int>> pr(a); for (int i = 0; i < a; i++) { cin >> pr[i].first >> pr[i].second; } int s = 0; int k = 1; for (int i = 0; i < pr.size(); i++) { if (pr[i].second >= 1) { k--; k += pr[i].second; s += pr[i].first; pr.erase(pr.begin() + i); i--; } } sort(pr.rbegin(), pr.rend()); int i = 0; while (k > 0 && i < pr.size()) { s += pr[i].first; i++; k--; } cout << s << endl; } int main() { int t = 1; while (t--) { Oli(); } return 0; } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* MII PHY interface
*/
module mii_phy_if #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2"
)
(
input wire rst,
/*
* MII interface to MAC
*/
output wire mac_mii_rx_clk,
output wire mac_mii_rx_rst,
output wire [3:0] mac_mii_rxd,
output wire mac_mii_rx_dv,
output wire mac_mii_rx_er,
output wire mac_mii_tx_clk,
output wire mac_mii_tx_rst,
input wire [3:0] mac_mii_txd,
input wire mac_mii_tx_en,
input wire mac_mii_tx_er,
/*
* MII interface to PHY
*/
input wire phy_mii_rx_clk,
input wire [3:0] phy_mii_rxd,
input wire phy_mii_rx_dv,
input wire phy_mii_rx_er,
input wire phy_mii_tx_clk,
output wire [3:0] phy_mii_txd,
output wire phy_mii_tx_en,
output wire phy_mii_tx_er
);
ssio_sdr_in #
(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(6)
)
rx_ssio_sdr_inst (
.input_clk(phy_mii_rx_clk),
.input_d({phy_mii_rxd, phy_mii_rx_dv, phy_mii_rx_er}),
.output_clk(mac_mii_rx_clk),
.output_q({mac_mii_rxd, mac_mii_rx_dv, mac_mii_rx_er})
);
(* IOB = "TRUE" *)
reg [3:0] phy_mii_txd_reg = 4'd0;
(* IOB = "TRUE" *)
reg phy_mii_tx_en_reg = 1'b0, phy_mii_tx_er_reg = 1'b0;
assign phy_mii_txd = phy_mii_txd_reg;
assign phy_mii_tx_en = phy_mii_tx_en_reg;
assign phy_mii_tx_er = phy_mii_tx_er_reg;
always @(posedge mac_mii_tx_clk) begin
phy_mii_txd_reg <= mac_mii_txd;
phy_mii_tx_en_reg <= mac_mii_tx_en;
phy_mii_tx_er_reg <= mac_mii_tx_er;
end
generate
if (TARGET == "XILINX") begin
BUFG
mii_bufg_inst (
.I(phy_mii_tx_clk),
.O(mac_mii_tx_clk)
);
end else begin
assign mac_mii_tx_clk = phy_mii_tx_clk;
end
endgenerate
// reset sync
reg [3:0] tx_rst_reg = 4'hf;
assign mac_mii_tx_rst = tx_rst_reg[0];
always @(posedge mac_mii_tx_clk or posedge rst) begin
if (rst) begin
tx_rst_reg <= 4'hf;
end else begin
tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
end
end
reg [3:0] rx_rst_reg = 4'hf;
assign mac_mii_rx_rst = rx_rst_reg[0];
always @(posedge mac_mii_rx_clk or posedge rst) begin
if (rst) begin
rx_rst_reg <= 4'hf;
end else begin
rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, const U &b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, const U &b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T1, class T2> inline void gn(T1 &x1, T2 &x2) { gn(x1), gn(x2); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } vector<int> adj[500500]; int can0[500500], can1[500500], dp0[500500], dp1[500500]; int dp[4]; int n, sz[500500]; void dfs(int u, int f = 0) { sz[u] = 1; for (int v : adj[u]) if (v != f) dfs(v, u), sz[u] += sz[v]; can0[u] = 1; dp[0] = 1, dp[1] = 0; for (int v : adj[u]) { if (v == f) continue; can0[u] &= can1[v]; int t[2] = {dp[0], dp[1]}; dp[0] = t[0] * can1[v]; dp[1] = t[0] * can0[v] + t[1] * can1[v]; } can1[u] = dp[1]; dp[0] = 1, dp[1] = 0; for (int v : adj[u]) { if (v == f) continue; int t[2] = {dp[0], dp[1]}; dp[0] = t[0] * can1[v]; dp[1] = t[1] * can1[v] + t[0] * dp1[v]; } dp0[u] = dp[1]; dp1[u] = can0[u]; dp[0] = 1, dp[1] = 0; for (int v : adj[u]) { if (v == f) continue; int t[2] = {dp[0], dp[1]}; dp[0] = t[0] * can1[v]; dp[1] = t[1] * can1[v] + t[0] * dp0[v]; } dp1[u] += dp[1]; dp[0] = 1, dp[1] = dp[2] = dp[3] = 0; for (int v : adj[u]) { if (v == f) continue; int t[4] = {dp[0], dp[1], dp[2], dp[3]}; dp[0] = t[0] * can1[v]; dp[1] = t[0] * can0[v] + t[1] * can1[v]; dp[2] = t[0] * dp1[v] + t[2] * can1[v]; dp[3] = t[1] * dp1[v] + t[2] * can0[v] + t[3] * can1[v]; } dp1[u] += dp[3]; } long long ans; int c0[500500], c1[500500], d0[500500], d1[500500]; int R[500500], Rdp[500500][4]; void redfs(int u, int f = 0) { if (f) { if (can1[u] && c1[u]) ans += (long long)sz[u] * (n - sz[u]); else ans += (long long)dp1[u] * d1[u]; } R[adj[u].size()] = 1; Rdp[adj[u].size()][0] = 1; Rdp[adj[u].size()][1] = 0; for (int i = adj[u].size(); i--;) { int v = adj[u][i]; R[i] = R[i + 1] & (v == f ? c1[u] : can1[v]); Rdp[i][0] = Rdp[i + 1][0] * (v == f ? c1[u] : can1[v]); Rdp[i][1] = Rdp[i + 1][0] * (v == f ? c0[u] : can0[v]) + Rdp[i + 1][1] * (v == f ? c1[u] : can1[v]); } int cur = 1; dp[0] = 1, dp[1] = 0; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v != f) { c0[v] = cur & R[i + 1]; c1[v] = dp[0] & Rdp[i + 1][1] | dp[1] & Rdp[i + 1][0]; } int t[2] = {dp[0], dp[1]}; cur &= (v == f ? c1[u] : can1[v]); dp[0] = t[0] * (v == f ? c1[u] : can1[v]); dp[1] = t[0] * (v == f ? c0[u] : can0[v]) + t[1] * (v == f ? c1[u] : can1[v]); } Rdp[adj[u].size()][0] = 1; Rdp[adj[u].size()][1] = 0; for (int i = adj[u].size(); i--;) { int v = adj[u][i]; Rdp[i][0] = Rdp[i + 1][0] * (v == f ? c1[u] : can1[v]); Rdp[i][1] = Rdp[i + 1][0] * (v == f ? d1[u] : dp1[v]) + Rdp[i + 1][1] * (v == f ? c1[u] : can1[v]); } dp[0] = 1, dp[1] = 0; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v != f) d0[v] = dp[0] * Rdp[i + 1][1] + dp[1] * Rdp[i + 1][0]; int t[2] = {dp[0], dp[1]}; dp[0] = t[0] * (v == f ? c1[u] : can1[v]); dp[1] = t[1] * (v == f ? c1[u] : can1[v]) + t[0] * (v == f ? d1[u] : dp1[v]); } for (int v : adj[u]) if (v != f) d1[v] = c0[v]; Rdp[adj[u].size()][0] = 1; Rdp[adj[u].size()][1] = 0; for (int i = adj[u].size(); i--;) { int v = adj[u][i]; Rdp[i][0] = Rdp[i + 1][0] * (v == f ? c1[u] : can1[v]); Rdp[i][1] = Rdp[i + 1][0] * (v == f ? d0[u] : dp0[v]) + Rdp[i + 1][1] * (v == f ? c1[u] : can1[v]); } dp[0] = 1, dp[1] = 0; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v != f) d1[v] += dp[0] * Rdp[i + 1][1] + dp[1] * Rdp[i + 1][0]; int t[2] = {dp[0], dp[1]}; dp[0] = t[0] * (v == f ? c1[u] : can1[v]); dp[1] = t[1] * (v == f ? c1[u] : can1[v]) + t[0] * (v == f ? d0[u] : dp0[v]); } Rdp[adj[u].size()][0] = 1; Rdp[adj[u].size()][1] = 0; Rdp[adj[u].size()][2] = 0; Rdp[adj[u].size()][3] = 0; for (int i = adj[u].size(); i--;) { int v = adj[u][i]; Rdp[i][0] = Rdp[i + 1][0] * (v == f ? c1[u] : can1[v]); Rdp[i][1] = Rdp[i + 1][0] * (v == f ? c0[u] : can0[v]) + Rdp[i + 1][1] * (v == f ? c1[u] : can1[v]); Rdp[i][2] = Rdp[i + 1][0] * (v == f ? d1[u] : dp1[v]) + Rdp[i + 1][2] * (v == f ? c1[u] : can1[v]); Rdp[i][3] = Rdp[i + 1][1] * (v == f ? d1[u] : dp1[v]) + Rdp[i + 1][2] * (v == f ? c0[u] : can0[v]) + Rdp[i + 1][3] * (v == f ? c1[u] : can1[v]); } dp[0] = 1, dp[1] = dp[2] = dp[3] = 0; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v != f) d1[v] += dp[0] * Rdp[i + 1][3] + dp[1] * Rdp[i + 1][2] + dp[2] * Rdp[i + 1][1] + dp[3] * Rdp[i + 1][0]; int t[4] = {dp[0], dp[1], dp[2], dp[3]}; dp[0] = t[0] * (v == f ? c1[u] : can1[v]); dp[1] = t[0] * (v == f ? c0[u] : can0[v]) + t[1] * (v == f ? c1[u] : can1[v]); dp[2] = t[0] * (v == f ? d1[u] : dp1[v]) + t[2] * (v == f ? c1[u] : can1[v]); dp[3] = t[1] * (v == f ? d1[u] : dp1[v]) + t[2] * (v == f ? c0[u] : can0[v]) + t[3] * (v == f ? c1[u] : can1[v]); } for (int v : adj[u]) if (v != f) redfs(v, u); } int main() { cin >> n; for (int i = 1; i < n; i++) { int u, v; gn(u, v); adj[u].push_back(v); adj[v].push_back(u); } dfs(1); redfs(1); cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O21BA_FUNCTIONAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ba (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_FUNCTIONAL_PP_V |
// file: Clock_gen.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___400.000______0.000______50.0______132.266____235.738
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock_gen,clk_wiz_v3_6,{component_name=Clock_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module Clock_gen
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (4),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (10.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { while (b > 0) { a %= b; swap(a, b); } return a; } template <class _T> inline _T sqr(const _T& first) { return first * first; } template <class _T> inline string tostr(const _T& a) { ostringstream os( ); os << a; return os.str(); } const long double PI = 3.1415926535897932384626433832795L; const double EPS = 1e-9; char TEMPORARY_CHAR; const int INF = 1e9; inline void input(int& a) { a = 0; while (((TEMPORARY_CHAR = getchar()) > 9 || TEMPORARY_CHAR < 0 ) && (TEMPORARY_CHAR != - )) { } char neg = 0; if (TEMPORARY_CHAR == - ) { neg = 1; TEMPORARY_CHAR = getchar(); } while (TEMPORARY_CHAR <= 9 && TEMPORARY_CHAR >= 0 ) { a = 10 * a + TEMPORARY_CHAR - 0 ; TEMPORARY_CHAR = getchar(); } if (neg) a = -a; } inline void out(long long a) { if (!a) putchar( 0 ); if (a < 0) { putchar( - ); a = -a; } char s[20]; int i; for (i = 0; a; ++i) { s[i] = 0 + a % 10; a /= 10; } for (int j = (i)-1; j >= 0; j--) putchar(s[j]); } inline int nxt() { int(ret); input((ret)); ; return ret; } const int MAXN = 300000; long long powers[MAXN + 1]; struct data { int len; long long data1; long long data2; }; data merge(const data& l, const data& r) { data res; res.len = l.len + r.len; res.data1 = r.data1 + l.data1 * powers[r.len]; res.data2 = l.data2 + r.data2 * powers[l.len]; return res; } int main() { int(n); input((n)); ; int first[n]; powers[0] = 1; for (int i = 1; i <= n; ++i) { powers[i] = powers[i - 1] * 3; } for (int i = 0; i < n; ++i) { first[i] = nxt() - 1; } data t[n + n]; for (int i = 0; i < n; ++i) { t[i + n].len = 1; t[i + n].data1 = t[i + n].data2 = 0; } for (int i = n - 1; i > 0; --i) { t[i] = merge(t[i + i], t[i + i + 1]); } for (int i = 0; i < n; ++i) { t[first[i] + n].data1 = t[first[i] + n].data2 = 1; int pos = first[i] + n; for (pos >>= 1; pos; pos >>= 1) { t[pos] = merge(t[pos + pos], t[pos + pos + 1]); } int r = min(first[i], n - first[i] - 1); data L{0, 0, 0}; data R{0, 0, 0}; int a = first[i] - r, b = first[i] + r; for (a += n, b += n; a <= b; a = (a + 1) >> 1, b = (b - 1) >> 1) { if (a & 1) { L = merge(L, t[a]); } if (!(b & 1)) { R = merge(t[b], R); } } data res = merge(L, R); if (res.data1 != res.data2) { puts( YES ); return 0; } } puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; pair<long long, long long> A[300005]; long long B[300005]; int main() { long long n; scanf( %lld , &n); for (long long i = 1; i <= n; ++i) { scanf( %lld , &A[i].first); A[i].second = i; } sort(A + 1, A + n + 1); long long val = 1; for (long long i = 1; i <= n; ++i) { val = max(val, A[i].first); B[A[i].second] = val; val++; } for (long long i = 1; i <= n; ++i) { printf( %lld , B[i]); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; for (int i = 0; i < t; i++) { int x; cin >> x; int ans = (x % 10 - 1) * 10; ans += 1; if (x / 10 > 0) ans += 2; if (x / 100 > 0) ans += 3; if (x / 1000 > 0) ans += 4; cout << ans << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_PP_V |
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Proper 8+2-bit DitherPWM, derived from PWM component v3.30
// Werner Johansson,
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 01/29/2016 at 19:06
// Component: DitherPWM
module DitherPWM (
output pwm,
input clock,
input reset
);
//`#start body` -- edit after this line, do not edit this line
/**************************************************************************/
/* Parameters */
/**************************************************************************/
/* localparams */
localparam PWM_DITHER_OFFSET0 = 2'd0;
localparam PWM_DITHER_OFFSET25 = 2'd1;
localparam PWM_DITHER_OFFSET50 = 2'd2;
localparam PWM_DITHER_OFFSET75 = 2'd3;
/* Control Register Bits*/
localparam PWM_CTRL_ENABLE = 8'h7; /* Enable the PWM */
localparam PWM_CTRL_DITHER_1 = 8'h1; /* Dither bit 1 */
localparam PWM_CTRL_DITHER_0 = 8'h0; /* Dither bit 0 */
/* Datapath Implementation */
localparam RESET_PERIOD_SHIFT_OP = `CS_ALU_OP_PASS;
localparam RESET_PERIOD_SRC_B = `CS_SRCB_D0;
localparam RESET_PERIOD_A0_SRC = `CS_A0_SRC___F0;
parameter dpconfig0 = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: Idle */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: Reset Period */
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Dec A0 (A0 = A0 - 1) */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Reset Period */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: Reset Period*/
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: Reset Period */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Reset Period */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: Reset Period */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A0_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1__A0, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_FX,
`SC_FIFO__EDGE,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* Internal signals */
wire cmp1_eq; /* A0 is equal to compare value 1 */
wire cmp1_less; /* A0 is less than to compare value 1 */
/* Clock Enable block signal */
wire ClockOutFromEnBlock;
/* wires for output registering logic */
wire tc_i;
reg tc_i_reg;
wire pwm_i;
reg pwm_i_reg;
/* Control Register Output */
wire [7:0] control;
/* Control Signals */
wire ctrl_enable;
wire [1:0] dithOff;
/* Triggers */
wire final_enable;
/* Dither Impl */
wire dith_sel;
reg [1:0] dith_count;
/* PWM output(s) */
wire pwm_temp;
/* Run Mode */
reg runmode_enable;
/* Datapath Implementation */
wire [2:0] cs_addr;
/* Clock Enable Block Component instance */
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
clock_enable_block (
/* output */.clock_out(ClockOutFromEnBlock),
/* input */ .clock_in(clock),
/* input */ .enable(1'b1)
);
/**************************************************************************/
/* Control Register Implementation */
/**************************************************************************/
generate
cy_psoc3_control #(.cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ctrlreg(
/* input */ .clock(ClockOutFromEnBlock),
/* output [07:00] */ .control(control)
);
assign ctrl_enable = control[PWM_CTRL_ENABLE];
assign dithOff = {control[PWM_CTRL_DITHER_1], control[PWM_CTRL_DITHER_0]};
endgenerate
/**************************************************************************/
/* Run Mode Block Implementations */
/**************************************************************************/
generate
always @(posedge ClockOutFromEnBlock or posedge reset)
begin
if(reset)
runmode_enable <= 1'b0;
else
runmode_enable <= ctrl_enable;
end
assign final_enable = runmode_enable;
endgenerate
/**************************************************************************/
/* Dither implementation */
/**************************************************************************/
always @(posedge ClockOutFromEnBlock or posedge reset)
begin
if(reset)
begin
dith_count <= 0;
end
else
begin
if(tc_i)
begin
dith_count <= dith_count + 1;
end
end
end
/* SUJA modified */
assign dith_sel = (dithOff[1:0] == PWM_DITHER_OFFSET0) ? 1'b0 :
(dithOff[1:0] == PWM_DITHER_OFFSET25) ? ((dith_count == 0) ? 1'b1 : 1'b0) :
(dithOff[1:0] == PWM_DITHER_OFFSET50) ? ((dith_count == 0 || dith_count == 2) ? 1'b1 : 1'b0) :
/*(DitherOffset == PWM_DITHER_OFFSET75) ? */((dith_count == 3) ? 1'b0 : 1'b1) ;
/**************************************************************************/
/* Datapath Implementation */
/**************************************************************************/
generate
assign cs_addr = {tc_i,final_enable,reset};
endgenerate
generate
cy_psoc3_dp8 #(.cy_dpconfig_a(dpconfig0)) pwmdp(
/* input */ .clk(ClockOutFromEnBlock),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(cmp1_eq), /* Compare1 ( A0 == D0 )*/
/* output */ .cl0(cmp1_less), /* Compare1 ( A0 < D0 ) */
/* output */ .z0(tc_i), /* tc ( A0 == 0 ) */
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* TODO: Can't use this because we exceed the number of outputs allowed from one Datapath. */
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
endgenerate
/**************************************************************************/
/* Pulse Width output(s) implementation */
/**************************************************************************/
/* Register the pwm output to avoid glitches on the output terminal*/
always @(posedge ClockOutFromEnBlock)
begin
pwm_i_reg <= pwm_i ;
/* Register the tc to avoid glitches on the output terminal */
tc_i_reg <= tc_i & final_enable;
end
assign pwm = pwm_i_reg;
assign pwm_i = pwm_temp & final_enable;
assign pwm_temp = (!dith_sel) ? cmp1_less : (cmp1_less | cmp1_eq);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_0_V
`define SKY130_FD_SC_LP__INVLP_0_V
/**
* invlp: Low Power Inverter.
*
* Verilog wrapper for invlp with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_0 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_0 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_0_V
|
#include <bits/stdc++.h> using namespace std; long long INF; int n; long long v[100005]; int c[100005]; long long mx[100005]; pair<long long, int> st[2]; int q; long long a, b; void solve(long long a, long long b) { long long ans = 0; st[0].first = 0; st[0].second = -2; st[1].first = 0; st[1].second = -1; fill(mx, mx + n, -INF); for (int i = 0; i < n; i++) { int clr = c[i]; long long val = v[i]; long long w1, w2, w; int td = 1; if (st[td].second == clr) td--; w1 = st[td].first + v[i] * b; w2 = mx[clr] + v[i] * a; w = max(w1, w2); if (w > mx[clr]) { if (st[1].second == clr) { st[1].first = w; } else if (st[0].second == clr) { st[0].first = w; } else { if (w >= st[1].first) { st[0] = st[1]; st[1] = make_pair(w, clr); } else if (w > st[0].first) { st[0] = make_pair(w, clr); } } mx[clr] = w; if (st[0] > st[1]) swap(st[0], st[1]); } } for (int i = 0; i < n; i++) { ans = max(ans, mx[i]); } cout << ans << endl; } int main() { INF = 1.0e18; cin >> n >> q; for (int i = 0; i < n; i++) cin >> v[i]; for (int i = 0; i < n; i++) cin >> c[i], c[i]--; for (int i = 0; i < q; i++) cin >> a >> b, solve(a, b); return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 333333; const int INF = 2000000000; int n, m, k, a[M]; inline int read() { char c = getchar(); int ans = 0; while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) ans = (ans << 1) + (ans << 3) + (c ^ 48), c = getchar(); return ans; } int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= m; i++) a[i] = INF; for (int i = 1, x, c; i <= n; i++) { x = read(), c = read(); a[x] = min(a[x], c); } int ans = 0; for (int i = 1; i <= m; i++) ans += a[i]; printf( %d , min(ans, k)); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T sqr(T x) { return x * x; } template <typename T> T abs(T x) { return x < 0 ? -x : x; } template <typename T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <typename T> bool chmin(T& x, const T& y) { if (x > y) { x = y; return true; } return false; } template <typename T> bool chmax(T& x, const T& y) { if (x < y) { x = y; return true; } return false; } string to_bin(int x) { string ret; while (x) { ret = ret + (char)((x % 2) + 0 ); x /= 2; } return ret; } int main(int, char**) { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { long long n; cin >> n; long long m = (n - 1) / 3; int k = 0; long long p = 1; while (m >= p) { m -= p; k += 1; p *= 4; } vector<long long> a; for (int i = 0; i < k; ++i) { a.push_back(m % 4); m /= 4; } long long A, B; A = 1LL << (2 * k); B = 1LL << (2 * k + 1); vector<long long> b = {0, 2, 3, 1}; for (int i = 0; i < k; ++i) { A ^= a[i] << (2 * i); B ^= b[a[i]] << (2 * i); } long long C = A ^ B; long long ans; if (n % 3 == 1) { ans = A; } else if (n % 3 == 2) { ans = B; } else { ans = C; } cout << ans << n ; } cerr << Time execute: << clock() / (double)CLOCKS_PER_SEC << sec << endl; return 0; } |
`define bsg_mux_one_hot_gen_macro(words,bits) \
if (harden_p && els_p == words && width_p == bits) \
begin: macro \
bsg_rp_tsmc_40_mux_w``words``_b``bits w``words``_b``bits \
(.* \
); \
end
module bsg_mux_one_hot #(parameter `BSG_INV_PARAM(width_p)
, els_p=1
, harden_p=1
)
(
input [els_p-1:0][width_p-1:0] data_i
,input [els_p-1:0] sel_one_hot_i
,output [width_p-1:0] data_o
);
wire [els_p-1:0][width_p-1:0] data_masked;
genvar i,j;
`bsg_mux_one_hot_gen_macro(3,14)
else
`bsg_mux_one_hot_gen_macro(3,4)
else
begin : notmacro
for (i = 0; i < els_p; i++)
begin : mask
assign data_masked[i] = data_i[i] & { width_p { sel_one_hot_i[i] } };
end
for (i = 0; i < width_p; i++)
begin: reduce
wire [els_p-1:0] gather;
for (j = 0; j < els_p; j++)
assign gather[j] = data_masked[j][i];
assign data_o[i] = | gather;
end
end
endmodule // bsg_mux_one_hot
`BSG_ABSTRACT_MODULE(bsg_mux_one_hot)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// Author: Yu-Sheng Lin
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc;
reg rstn;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
real fst_real = 1.23;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
longint fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
tri0 fst_tri0;
tri1 fst_tri1;
tri fst_tri;
wire fst_wire;
logic [4:0] state;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),
// Inputs
.clk (clk),
.rstn (rstn));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
rstn <= ~'1;
end
else if (cyc<10) begin
rstn <= ~'1;
end
else if (cyc<90) begin
rstn <= ~'0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input rstn,
output logic [4:0] state
);
logic [4:0] state_w;
logic [4:0] state_array [3];
assign state = state_array[0];
always_comb begin
state_w[4] = state_array[2][0];
state_w[3] = state_array[2][4];
state_w[2] = state_array[2][3] ^ state_array[2][0];
state_w[1] = state_array[2][2];
state_w[0] = state_array[2][1];
end
always_ff @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 3; i++)
state_array[i] <= 'b1;
end
else begin
for (int i = 0; i < 2; i++)
state_array[i] <= state_array[i+1];
state_array[2] <= state_w;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int bit(int mask, int n) { return mask & (1 << n) ? 1 : 0; } int rev(int a) { int res = 0; for (int i = 0; i < 8; ++i) res = res | ((1 << (7 - i)) * bit(a, i)); return res; } int main() { string s; int prev = 0; getline(cin, s); for (int i = 0; i < s.length(); ++i) { int cur = (256 + prev - rev(s[i])) % 256; cout << cur << endl; prev = rev(s[i]); } cin >> s; return 0; } |
#include <bits/stdc++.h> using namespace std; string run(vector<string> &vec) { vector<bool> used(vec.size(), false); vector<char> ans(100, 1 ); for (int i = 0; i < vec[0].size(); ++i) { ans[50 + i] = vec[0][i]; } used[0] = true; while (true) { int count = 0; for (int i = 1; i < vec.size(); ++i) { if (not used[i]) { bool thr = false; for (int p = 0; p < vec[i].size() && !thr; ++p) { for (int k = 0; k < ans.size() && !thr; ++k) { if (ans[k] == vec[i][p]) { int in = k - p; for (int np = 0; np < vec[i].size(); ++np) { ans[in + np] = vec[i][np]; } used[i] = true; count += 1; thr = true; } } } } } if (count == 0) break; } int sz = 0; for (int i = 0; i < vec.size(); ++i) { if (not used[i]) { vec[sz] = vec[i]; ++sz; } } vec.resize(sz); string ret; for (int i = 0; i < ans.size(); ++i) { if (ans[i] != 1 ) { ret += ans[i]; } } return ret; } int main() { int n; cin >> n; vector<string> vs(n); for (int i = 0; i < n; ++i) { cin >> vs[i]; } string ans; while (not vs.empty()) { string c1 = run(vs); ans += c1; } cout << ans; return 0; } |
#include <bits/stdc++.h> int main() { double k, b, n, t; double bacteria = 1; double time = 0; scanf( %lf %lf %lf %lf , &k, &b, &n, &t); while (bacteria <= t) { bacteria = (k * bacteria + b); if (bacteria > t) { break; } else if (bacteria == t) { time++; break; } time++; } if (time > n) { n = 0; } else { n -= time; } printf( %0.0lf n , n); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/16/2017 03:08:23 PM
// Design Name:
// Module Name: seg7x16
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg7x16(
input clk,
input reset,
input cs,
input [31:0] i_data,
output [7:0] o_seg,
output [7:0] o_sel
);
reg [14:0] cnt;
always @ (posedge clk, posedge reset)
if (reset)
cnt <= 0;
else
cnt <= cnt + 1'b1;
wire seg7_clk = cnt[14];
reg [2:0] seg7_addr;
always @ (posedge seg7_clk, posedge reset)
if(reset)
seg7_addr <= 0;
else
seg7_addr <= seg7_addr + 1'b1;
reg [7:0] o_sel_r;
always @ (*)
case(seg7_addr)
7 : o_sel_r = 8'b01111111;
6 : o_sel_r = 8'b10111111;
5 : o_sel_r = 8'b11011111;
4 : o_sel_r = 8'b11101111;
3 : o_sel_r = 8'b11110111;
2 : o_sel_r = 8'b11111011;
1 : o_sel_r = 8'b11111101;
0 : o_sel_r = 8'b11111110;
endcase
reg [31:0] i_data_store;
always @ (posedge clk, posedge reset)
if(reset)
i_data_store <= 0;
else if(cs)
i_data_store <= i_data;
reg [7:0] seg_data_r;
always @ (*)
case(seg7_addr)
0 : seg_data_r = i_data_store[3:0];
1 : seg_data_r = i_data_store[7:4];
2 : seg_data_r = i_data_store[11:8];
3 : seg_data_r = i_data_store[15:12];
4 : seg_data_r = i_data_store[19:16];
5 : seg_data_r = i_data_store[23:20];
6 : seg_data_r = i_data_store[27:24];
7 : seg_data_r = i_data_store[31:28];
endcase
reg [7:0] o_seg_r;
always @ (posedge clk, posedge reset)
if(reset)
o_seg_r <= 8'hff;
else
case(seg_data_r)
4'h0 : o_seg_r <= 8'hC0;
4'h1 : o_seg_r <= 8'hF9;
4'h2 : o_seg_r <= 8'hA4;
4'h3 : o_seg_r <= 8'hB0;
4'h4 : o_seg_r <= 8'h99;
4'h5 : o_seg_r <= 8'h92;
4'h6 : o_seg_r <= 8'h82;
4'h7 : o_seg_r <= 8'hF8;
4'h8 : o_seg_r <= 8'h80;
4'h9 : o_seg_r <= 8'h90;
4'hA : o_seg_r <= 8'h88;
4'hB : o_seg_r <= 8'h83;
4'hC : o_seg_r <= 8'hC6;
4'hD : o_seg_r <= 8'hA1;
4'hE : o_seg_r <= 8'h86;
4'hF : o_seg_r <= 8'h8E;
endcase
assign o_sel = o_sel_r;
assign o_seg = o_seg_r;
endmodule
|
module test;
reg clk = 0;
reg reset = 1;
initial begin
reset = 1;
#250 reset = 0;
end
always #100 clk = ~clk;
reg io_in_bits_centeroidsFinished ;
reg io_in_bits_pointsFinished ;
wire [15:0] io_in_bits_centeroidIndex;
wire [63:0] io_in_bits_point_x;
wire [63:0] io_in_bits_point_y;
wire [63:0] io_in_bits_point_z;
wire [15:0] io_out_bits_centeroidIndex;
wire [63:0] io_out_bits_point_x;
wire [63:0] io_out_bits_point_y;
wire [63:0] io_out_bits_point_z;
wire io_out_ready;
wire [3:0] io_in_tag;
assign io_pcIn_valid = 1'b0;
assign io_in_valid = 1'b1;
assign io_out_ready = 1'b1;
assign io_in_tag = 4'b1;
Top
Top(
clk,
reset,
io_in_ready,
io_in_valid,
io_in_bits_centeroidsFinished,
io_in_bits_pointsFinished,
io_in_bits_centeroidIndex,
io_in_bits_point_x,
io_in_bits_point_y,
io_in_bits_point_z,
io_in_tag,
io_out_ready,
io_out_valid,
io_out_bits_centeroidsFinished,
io_out_bits_pointsFinished,
io_out_bits_centeroidIndex,
io_out_bits_point_x,
io_out_bits_point_y,
io_out_bits_point_z,
io_out_tag,
io_pcIn_valid,
io_pcIn_bits_request,
io_pcIn_bits_moduleId,
io_pcIn_bits_portId,
io_pcIn_bits_pcValue,
io_pcIn_bits_pcType,
io_pcOut_valid,
io_pcOut_bits_request,
io_pcOut_bits_moduleId,
io_pcOut_bits_portId,
io_pcOut_bits_pcValue,
io_pcOut_bits_pcType);
integer count = 0;
always @(negedge clk) begin
#50;
io_in_bits_centeroidsFinished = 1'b0;
io_in_bits_pointsFinished = 1'b0;
if (count == 10) begin
io_in_bits_centeroidsFinished = 1'b1;
end
if (count == 310) begin
io_in_bits_pointsFinished = 1'b1;
end
if (io_in_ready) begin
count = count + 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_FUNCTIONAL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s50 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, M = 1e6 + 5; long long T, l[N], dp[N], fen[M][2]; vector<int> adj[N]; int n, x[N], t[N]; void add(int p, int x) { for (long long y = 1LL * x * p; p < M; p += p & -p) fen[p][0] += x, fen[p][1] += y; } long long get(int p, int id) { long long ans = 0; for (; p; p -= p & -p) ans += fen[p][id]; return ans; } void dfs(int u) { add(t[u], x[u]); int L = 0, R = M; while (L + 1 < R) { int mid = L + R >> 1; (T < 2 * l[u] + get(mid, 1) ? R : L) = mid; } long long mx[2] = {}; for (int v : adj[u]) { l[v] += l[u], dfs(v); dp[v] > mx[1] ? mx[0] = mx[1], mx[1] = dp[v] : mx[0] = max(mx[0], dp[v]); } dp[u] = max(get(L, 0) + (R < M && T > 2 * l[u]) * (T - 2 * l[u] - get(L, 1)) / R, mx[!u]); add(t[u], -x[u]); } int main() { cin >> n >> T; for (int u = 0; u < n; u++) cin >> x[u]; for (int u = 0; u < n; u++) cin >> t[u]; for (int u = 1, v; u < n; u++) { cin >> v >> l[u]; adj[--v].push_back(u); } dfs(0), cout << dp[0]; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_LP_V
`define SKY130_FD_SC_LP__AND4BB_LP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_lp (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_lp (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_LP_V
|
module erx_remap (/*AUTOARG*/
// Outputs
emesh_access_out, emesh_packet_out,
// Inputs
clk, reset, emesh_access_in, emesh_packet_in, remap_mode,
remap_sel, remap_pattern, remap_base
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h808;
//Clock/reset
input clk;
input reset;
//Input from arbiter
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
//Configuration
input [1:0] remap_mode; //00=none,01=static,02=continuity
input [11:0] remap_sel; //number of bits to remap
input [11:0] remap_pattern; //static pattern to map to
input [31:0] remap_base; //remap offset
//Output to TX IO
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
wire [31:0] static_remap;
wire [31:0] dynamic_remap;
wire [31:0] remap_mux;
wire write_in;
wire read_in;
wire [31:0] addr_in;
wire [31:0] addr_out;
wire remap_en;
reg emesh_access_out;
reg [PW-1:0] emesh_packet_out;
//TODO:FIX!??
parameter[5:0] colid = ID[5:0];
//parsing packet
assign addr_in[31:0] = emesh_packet_in[39:8];
assign write_in = emesh_packet_in[1];
assign read_in = ~emesh_packet_in[1];
//simple static remap
assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
(~remap_sel[11:0] & addr_in[31:20]);
assign static_remap[19:0] = addr_in[19:0];
//more complex compresssed map
assign dynamic_remap[31:0] = addr_in[31:0] //input
- (colid << 20) //subtracing elink (start at 0)
+ remap_base[31:0] //adding back base
- (addr_in[31:26]<<$clog2(colid));
//Static, dynamic, or no remap
assign remap_mux[31:0] = (remap_mode[1:0]==2'b00) ? addr_in[31:0] :
(remap_mode[1:0]==2'b01) ? static_remap[31:0] :
dynamic_remap[31:0];
//Access
always @ (posedge clk)
if (reset)
emesh_access_out <= 1'b0;
else
emesh_access_out <= emesh_access_in;
//Packet
always @ (posedge clk)
emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
remap_mux[31:0],
emesh_packet_in[7:0]
};
endmodule // etx_mux
|
#include <bits/stdc++.h> using namespace std; bool dp[10005][3]; int main() { int n, i; string s; set<string> ans; cin >> s; n = s.length(); for (i = n - 1; i >= 5; i--) { if (i + 2 <= n) { if (i + 2 == n || dp[i + 2][1] || (dp[i + 2][0] && s.substr(i + 2, 2) != s.substr(i, 2))) { dp[i][0] = true; ans.insert(s.substr(i, 2)); } } if (i + 3 <= n) { if (i + 3 == n || dp[i + 3][0] || (dp[i + 3][1] && s.substr(i + 3, 3) != s.substr(i, 3))) { dp[i][1] = true; ans.insert(s.substr(i, 3)); } } } cout << ans.size() << endl; while (!ans.empty()) { cout << *ans.begin() << endl; ans.erase(ans.begin()); } } |
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, i, ans, p, MD = 1000000007; cin >> a >> b; p = ((a * (a + 1)) / 2) % MD; p = p * b % MD; p = (a + p) % MD; ans = ((b * (b - 1) / 2)) % MD; ans = (ans * p) % MD; cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_PP_SYMBOL_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s18kapwr (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void Solve() { string s; cin >> s; int n = s.size(); int cnt1 = 0, cnt2 = 0; for (int i = 0; i < n - 1; i++) { string t = s.substr(i, 2); if (t == ab ) { cnt1++; } else if (t == ba ) { cnt2++; } } if (cnt1 == cnt2) { cout << s << n ; return; } if (cnt1 > cnt2) { for (int i = n - 1; i >= 0; i--) { if (s[i] == b ) { s[i] = a ; break; } } } else { for (int i = n - 1; i >= 0; i--) { if (s[i] == a ) { s[i] = b ; break; } } } cout << s << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int TC = 1; cin >> TC; while (TC--) Solve(); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:02 05/08/2014
// Design Name:
// Module Name: data_path
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_path(
clk,
reset,
MIO_ready,
IorD,
IRWrite,
RegDst,
RegWrite,
MemtoReg,
data2Mem,
data2CPU,
ALUSrcA,
ALUSrcB,
PCSource,
PCWrite,
PCWriteCond,
Beq,
Signext,
ALU_operation,
PC_Current,
Inst_R,
data_out,
M_addr,
zero,
overflow,
WriteEPC,
WriteCause,
WriteCp0,
InTcause,
WriteIen,
Int_en,
intrrupt_en_o
);
input wire clk, reset;
input wire MIO_ready, IorD, RegWrite, IRWrite, PCWrite,
PCWriteCond, Beq, data2Mem, Signext, WriteEPC,
WriteCause, WriteCp0, WriteIen, Int_en;
input wire [ 1: 0] RegDst, ALUSrcA, ALUSrcB;
input wire [ 2: 0] PCSource, MemtoReg;
input wire [ 3: 0] ALU_operation;
input wire [ 4: 0] InTcause;
input wire [31: 0] data2CPU;
output wire [31: 0] intrrupt_en_o;
output reg [31: 0] PC_Current;
output reg [31: 0] Inst_R = 0;
output wire [31: 0] data_out;
output wire [31: 0] M_addr;
output wire zero, overflow;
reg [31: 0] ALU_Out = 32'h0, MDR = 32'h0, ALU_Out2 = 32'h0;
wire [31: 0] reg_outA, reg_outB, r6out; //regs
wire [31: 0] epc_out, c0_r_data;
wire modificative;
//ALU
wire [31: 0] Alu_B, res;
reg [31: 0] Alu_A;
wire [31: 0] rdata_A, rdata_B;
reg [31: 0] w_reg_data;
wire [15: 0] imm;
wire [31: 0] imm_ext;
wire [ 4: 0] shamt;
wire [ 4: 0] reg_Rs_addr_A,reg_Rt_addr_B,reg_rd_addr,reg_Wt_addr;
reg [31: 0] dataToCpu;
always @(posedge clk) dataToCpu <= data2CPU;
assign rst=reset;
// locked inst form memory
always @(posedge clk or posedge rst)begin
if(rst) begin
Inst_R <= 0;
end
else begin
if (IRWrite && MIO_ready)
Inst_R <= data2CPU;
else
Inst_R <= Inst_R;
if (MIO_ready)
MDR <= data2CPU;
ALU_Out <= res;
ALU_Out2 <= ALU_Out;
end
end
//+++++++++++++++++++++++++++++++++++++++++++ signed or unsigned extends
single_signext signext(Signext, imm, imm_ext);
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
alu D1(
.A (Alu_A),
.B (Alu_B),
.ALU_operation (ALU_operation),
.shamt (shamt),
.res (res),
.zero (zero),
.overflow(overflow)
);
Regs reg_files(
.clk (clk),
.rst (rst),
.reg_R_addr_A (reg_Rs_addr_A),
.reg_R_addr_B (reg_Rt_addr_B),
.reg_W_addr (reg_Wt_addr),
.wdata (w_reg_data),
.reg_we (RegWrite),
.rdata_A (rdata_A),
.rdata_B (rdata_B)
);
// Instructions as mfc0 $t1, $11
Coprocessor cp0(
.clk (clk),
.rst (reset),
.c0_rd_addr (reg_rd_addr), // mfc0 $rt, $rd, which is $rt
.c0_wr_addr (reg_rd_addr),
.c0_w_data (rdata_B), // mtc0 $rd, $rt, which is rdata_B
.pc_i (res),
.InTcause (InTcause), //
.c0_reg_we (WriteCp0),
.WriteEPC (WriteEPC),
.WriteCause (WriteCause),
.WriteInt (WriteIen),
.Int_en_i (Int_en),
.Int_en_o (intrrupt_en_o),
.c0_r_data (c0_r_data), // used for instructions mfc0
.epc_o (epc_out) // eret return epc
);
initial begin
PC_Current = 32'h0000_0000;
end
//path with MUX++++++++++++++++++++++++++++++++++++++++++++++++++++++
// reg path
assign reg_Rs_addr_A = Inst_R[25:21]; //REG Source 1 rs
assign reg_Rt_addr_B = Inst_R[20:16]; //REG Source 2 or Destination rt
assign reg_rd_addr = Inst_R[15:11]; //REG Destination rd
assign imm = Inst_R[15: 0]; //Immediate
assign shamt = Inst_R[10: 6];
// reg write data
always @(*) begin
case(MemtoReg)
3'b000: w_reg_data <= ALU_Out; // ALU OP
3'b001: w_reg_data <= MDR; // LW
3'b010: w_reg_data <= {imm,16'h0000}; // lui
3'b011: w_reg_data <= PC_Current; // jr
3'b100: w_reg_data <= c0_r_data; // mfc0
endcase
end
/*
mux4to1_32 mux_w_reg_data(
.a (ALU_Out), //ALU OP
.b (MDR), //LW
.c ({imm,16'h0000}), //lui
.d (PC_Current), // jr
.sel (MemtoReg),
.o (w_reg_data)
);
*/
// reg write port addr
mux4to1_5 mux_w_reg_addr(
.a (reg_Rt_addr_B), //reg addr=IR[21:16]
.b (reg_rd_addr), //reg addr=IR[15:11], LW or lui
.c (5'b11111), //reg addr=$Ra(31) jr
.d (5'b00000), // not use
.sel (RegDst),
.o (reg_Wt_addr)
);
//---------------ALU path
// Alu source A
always @(*) begin
case( ALUSrcA )
2'b00: Alu_A <= PC_Current; // PC
2'b01: Alu_A <= rdata_A; // reg out A
2'b10: Alu_A <= dataToCpu; // Sh
2'b11: Alu_A <= PC_Current - 4; // pc - 4 for syscall
endcase
end
/*
mux3to1_32 mux_Alu_A(
.a (rdata_A), // reg out A
.b (PC_Current), // PC
.c (dataToCpu), // Sh
.d (PC_Current - 4), // pc - 4 for syscall
.sel (ALUSrcA),
.o (Alu_A)
);
*/
mux4to1_32 mux_Alu_B(
.a (rdata_B), //reg out B
.b (32'h00000004), //4 for PC+4
.c (imm_ext), //imm
.d ({{14{imm[15]}},imm,2'b00}), // offset
.sel (ALUSrcB),
.o (Alu_B)
);
//pc Generator
//+++++++++++++++++++++++++++++++++++++++++++++++++
assign modificative = PCWrite || (PCWriteCond && (~(zero || Beq) | (zero && Beq)));
//(PCWriteCond&&zero)
always @(posedge clk or posedge reset) begin
if (reset == 1) // reset
PC_Current <= 32'h00000000;
else if (modificative == 1)begin
case ( PCSource )
3'b000: if (MIO_ready)
PC_Current <= res; // PC+4
3'b001: PC_Current <= ALU_Out; // branch
3'b010: PC_Current <= {PC_Current[31:28],Inst_R[25:0],2'b00}; // jump
3'b011: PC_Current <= res; // jr and jalr
3'b100: PC_Current <= 32'h0000_0004;
3'b101: PC_Current <= epc_out;
endcase
end
end
//---------------memory path
assign data_out = data2Mem? ALU_Out2: rdata_B; //data to store memory or IO
mux2to1_32 mux_M_addr (
.a (ALU_Out), //access memory
.b (PC_Current), //IF
.sel (IorD),
.o (M_addr)
);
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 710, size = 1 << 20, mod = (int)1e9 + 7, inf = 2e9; const long long INF = 1e15; template <class o> void qr(o& x) { char c = getchar(); x = 0; int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); x *= f; } template <class o, class... O> void qr(o& x, O&... y) { qr(x); qr(y...); } template <class o> void qw(o x) { if (x / 10) qw(x / 10); putchar(x % 10 + 0 ); } template <class o> void pr1(o x) { if (x < 0) x = -x, putchar( - ); qw(x); putchar( ); } template <class o, class... O> void pr1(o x, O... y) { pr1(x); pr1(y...); } template <class o> void pr2(o x) { if (x < 0) x = -x, putchar( - ); qw(x); putchar( n ); } template <class o, class... O> void pr2(o x, O... y) { pr2(x); pr2(y...); } long long gcd(long long a, long long b) { return !a ? b : gcd(b % a, a); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long power(long long a, long long b = mod - 2, long long p = mod) { long long c = 1; while (b) { if (b & 1) c = c * a % p; b /= 2; a = a * a % p; } return c; } long long exgcd(long long a, long long b, long long& x, long long& y) { if (!a) { x = 0; y = 1; return b; } long long d = exgcd(b % a, a, y, x); x -= b / a * y; return d; } long long INV(long long n, long long p = mod) { long long x, y; exgcd(n, p, x, y); return (x % p + p) % p; } template <class o> void cmax(o& x, o y) { if (x < y) x = y; } template <class o> void cmin(o& x, o y) { if (x > y) x = y; } template <typename t1, typename t2> void ad(t1& x, t2 y) { x += y; if (x >= mod) x -= mod; } template <typename t1, typename t2> void dl(t1& x, t2 y) { x -= y; if (x < 0) x += mod; } char str[N]; int n, a[N], cnt[10], f[N][N][10][2]; void solve() { scanf( %s , str + 1); int n = strlen(str + 1); for (int i = 1; i <= n; i++) a[i] = str[i] - 0 ; for (int i = 1; i <= 9; i++) f[0][0][i][0] = 1; for (int i = 0; i <= n - 1; i++) for (int j = 0; j <= i; j++) for (int k = 1; k <= 9; k++) for (int l = 0; l <= 1; l++) if (f[i][j][k][l]) for (int v = !l ? a[i + 1] : 9; v >= 0; v--) ad(f[i + 1][j + (v >= k)][k][l | (v < a[i + 1])], f[i][j][k][l]); long long p = 1, ans = 0; for (int i = 1; i <= n; i++) { long long sum = 0; for (int j = 1; j <= 9; j++) sum += f[n][i][j][0] + f[n][i][j][1]; sum %= mod; ans = (ans + sum * p) % mod; p = (p * 10 + 1) % mod; } pr2(ans); } int main() { int T = 1; while (T--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int q; long long N, M, K; cin >> N >> K >> M; vector<long long> A(N); long long s = 0; for (int i = 0; i < N; i++) { cin >> A[i]; s += A[i]; } sort(A.begin(), A.end()); long double res = (long double)(s + min(M, N * K)) / (long double)N; for (int i = 0; i < min(N - 1, M); i++) { s -= A[i]; long long tp = s + min((N - i - 1) * K, M - i - 1); long double avg = (long double)tp / (long double)(N - i - 1); res = max(res, avg); } cout << fixed << setprecision(20) << res << endl; } |
`default_nettype none
// ============================================================================
module receiver #
(
parameter WIDTH = 8,
parameter MODE = "SDR"
)
(
input wire CLK,
input wire RST,
input wire I_CLK,
input wire I_DAT,
output wire O_STB,
output wire [WIDTH-1:0] O_DAT,
input wire O_BITSLIP
);
// ============================================================================
// CLKDIV generation using a BUFR
wire i_clkdiv;
wire i_rstdiv;
// Divider for BUFR
localparam DIVIDE = (MODE == "SDR" && WIDTH == 2) ? "2" :
(MODE == "SDR" && WIDTH == 3) ? "3" :
(MODE == "SDR" && WIDTH == 4) ? "4" :
(MODE == "SDR" && WIDTH == 5) ? "5" :
(MODE == "SDR" && WIDTH == 6) ? "6" :
(MODE == "SDR" && WIDTH == 7) ? "7" :
(MODE == "SDR" && WIDTH == 8) ? "8" :
(MODE == "DDR" && WIDTH == 4) ? "2" :
(MODE == "DDR" && WIDTH == 6) ? "3" :
(MODE == "DDR" && WIDTH == 8) ? "4" : "BYPASS";
// BUFR
BUFR #
(
.BUFR_DIVIDE (DIVIDE)
)
bufr_div
(
.I (I_CLK),
.O (i_clkdiv),
.CLR (1'b0),
.CE (1'b1)
);
// ISERDES reset generator
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge i_clkdiv)
if (RST) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign i_rstdiv = rst_sr[0];
// ============================================================================
// ISERDES
wire [7:0] d_dat;
(* KEEP, DONT_TOUCH *)
ISERDESE2 #
(
.DATA_RATE (MODE),
.DATA_WIDTH (WIDTH),
.INTERFACE_TYPE ("NETWORKING"),
.IS_CLKB_INVERTED (1'b1) // Do we have bits for that ??
)
iserdes
(
.CLK (I_CLK),
.CLKB (I_CLK),
.CLKDIV (i_clkdiv),
.CE1 (1'b1),
.CE2 (1'b1),
.RST (i_rstdiv),
.BITSLIP (bitslip),
.D (I_DAT),
.Q1 (d_dat[0]),
.Q2 (d_dat[1]),
.Q3 (d_dat[2]),
.Q4 (d_dat[3]),
.Q5 (d_dat[4]),
.Q6 (d_dat[5]),
.Q7 (d_dat[6]),
.Q8 (d_dat[7])
);
// ============================================================================
// Generate strobe synchronous to CLK
reg clk_p;
reg tick;
always @(posedge CLK)
clk_p <= i_clkdiv;
always @(posedge CLK)
if (RST)
tick <= 1'b0;
else
tick <= !clk_p && i_clkdiv;
// ============================================================================
// Bitslip. The bitslip signal should be synchronous to the CLKDIV. Here it is
// asserted for as long as the CLKDIV period but it is not synchronous to it.
reg bitslip_req;
reg bitslip;
always @(posedge CLK)
if (RST)
bitslip_req <= 1'b0;
else if (!bitslip_req && O_BITSLIP)
bitslip_req <= 1'b1;
else if (tick)
bitslip_req <= 1'b0;
always @(posedge CLK)
if (RST)
bitslip <= 1'd0;
else if (tick)
bitslip <= bitslip_req;
// ============================================================================
// Output sync to CLK
reg x_stb;
reg o_stb;
reg [WIDTH-1:0] o_dat;
always @(posedge CLK)
if (RST)
x_stb <= 1'b0;
else if(!x_stb && tick)
x_stb <= 1'b1;
else if( x_stb)
x_stb <= 1'b0;
always @(posedge CLK)
if (RST)
o_stb <= 1'd0;
else
o_stb <= x_stb;
always @(posedge CLK)
if (x_stb)
o_dat <= d_dat;
assign O_STB = o_stb;
assign O_DAT = o_dat[WIDTH-1:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string n; cin >> n; string m; cin >> m; sort(m.begin(), m.end()); int cn = 0; int cm = 0; int res = 0; for (int i = 0; i < m.length(); i += cm) { cm = count(m.begin(), m.end(), m[i]); cn = count(n.begin(), n.end(), m[i]); if (cn == 0) { cout << -1; return 0; } else if (cn >= cm) res += cm; else res += cn; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, b; cin >> n; for (int i = 0; i < n; i++) { cin >> b; int a[b + 1]; for (int j = 0; j < b; j++) cin >> a[j]; sort(a, a + b); int mn = 999999; for (int j = 1; j < b; j++) { mn = min(a[j] - a[j - 1], mn); } cout << mn << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, s, c[10000]; cin >> n >> a >> b; for (int i = 1; i <= n; i++) { cin >> c[i]; } s = 0; for (int i = 1; i <= n / 2; i++) { if (c[i] != 2 && c[n - i + 1] != 2 && c[i] != c[n - i + 1]) { cout << -1 << endl; return 0; } else if (c[i] == c[n - i + 1] && c[i] == 2) { s += 2 * min(a, b); } else if (c[i] == 2 && c[n - i + 1] != 2) { if (c[n - i + 1] == 0) s += a; else s += b; } else if (c[i] != 2 && c[n - i + 1] == 2) { if (c[i] == 0) s += a; else s += b; } } if (n % 2 == 1 && c[n / 2 + 1] == 2) s += min(a, b); cout << s << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxN = (int)1e5 + 100; const int MAX = (int)1e5 + 1; int l[maxN], d[maxN], cnt[maxN], q[maxN]; vector<int> pool[maxN]; multiset<int> p; void solveTask() { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> l[i]; for (int i = 1; i <= n; ++i) cin >> d[i]; for (int i = 1; i <= n; ++i) q[l[i]] += d[i], cnt[l[i]] += 1, pool[l[i]].push_back(d[i]); int answer = 0; int all_sum = 0; for (int i = 1; i <= MAX; ++i) { if (cnt[i] == 0) continue; int possibleCnt = cnt[i] - 1; int cur_sum = 0; for (set<int>::iterator it = p.begin(); it != p.end(); ++it) { if (possibleCnt == 0) break; cur_sum -= *it; --possibleCnt; } answer = max(answer, cur_sum + q[i]); all_sum += q[i]; for (int j = 0; j < pool[i].size(); ++j) { p.insert(-pool[i][j]); } } cout << all_sum - answer << endl; } int main() { solveTask(); ios_base::sync_with_stdio(false); return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
// the core, dac_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dac_buf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
module circl_b(
input wire [6:0] in_addr,
output reg [6:0] out_word
);
always @*
case( in_addr )
7'h01: out_word = 7'h0A;
7'h02: out_word = 7'h12;
7'h03: out_word = 7'h18;
7'h04: out_word = 7'h1C;
7'h05: out_word = 7'h20;
7'h06: out_word = 7'h23;
7'h07: out_word = 7'h26;
7'h08: out_word = 7'h29;
7'h09: out_word = 7'h2C;
7'h0A: out_word = 7'h2E;
7'h0B: out_word = 7'h30;
7'h0C: out_word = 7'h33;
7'h0D: out_word = 7'h35;
7'h0E: out_word = 7'h37;
7'h0F: out_word = 7'h38;
7'h10: out_word = 7'h3A;
7'h11: out_word = 7'h3C;
7'h12: out_word = 7'h3E;
7'h13: out_word = 7'h3F;
7'h14: out_word = 7'h41;
7'h15: out_word = 7'h42;
7'h16: out_word = 7'h44;
7'h17: out_word = 7'h45;
7'h18: out_word = 7'h46;
7'h19: out_word = 7'h48;
7'h1A: out_word = 7'h49;
7'h1B: out_word = 7'h4A;
7'h1C: out_word = 7'h4C;
7'h1D: out_word = 7'h4D;
7'h1E: out_word = 7'h4E;
7'h1F: out_word = 7'h4F;
7'h20: out_word = 7'h50;
7'h21: out_word = 7'h51;
7'h22: out_word = 7'h52;
7'h23: out_word = 7'h53;
7'h24: out_word = 7'h54;
7'h25: out_word = 7'h55;
7'h26: out_word = 7'h56;
7'h27: out_word = 7'h57;
7'h28: out_word = 7'h58;
7'h29: out_word = 7'h59;
7'h2A: out_word = 7'h5A;
7'h2B: out_word = 7'h5B;
7'h2C: out_word = 7'h5C;
7'h2D: out_word = 7'h5C;
// 7'h2E: out_word = 7'h5D;
// 7'h2F: out_word = 7'h5E;
// 7'h30: out_word = 7'h5F;
// 7'h31: out_word = 7'h5F;
// 7'h32: out_word = 7'h60;
// 7'h33: out_word = 7'h61;
// 7'h34: out_word = 7'h62;
// 7'h35: out_word = 7'h62;
// 7'h36: out_word = 7'h63;
// 7'h37: out_word = 7'h64;
// 7'h38: out_word = 7'h64;
// 7'h39: out_word = 7'h65;
// 7'h3A: out_word = 7'h66;
// 7'h3B: out_word = 7'h66;
// 7'h3C: out_word = 7'h67;
// 7'h3D: out_word = 7'h67;
// 7'h3E: out_word = 7'h68;
// 7'h3F: out_word = 7'h68;
// 7'h40: out_word = 7'h69;
// 7'h41: out_word = 7'h6A;
// 7'h42: out_word = 7'h6A;
// 7'h43: out_word = 7'h6B;
// 7'h44: out_word = 7'h6B;
// 7'h45: out_word = 7'h6C;
// 7'h46: out_word = 7'h6C;
// 7'h47: out_word = 7'h6C;
// 7'h48: out_word = 7'h6D;
// 7'h49: out_word = 7'h6D;
// 7'h4A: out_word = 7'h6E;
7'h4B: out_word = 7'h6E;
7'h4C: out_word = 7'h6F;
7'h4D: out_word = 7'h6F;
7'h4E: out_word = 7'h6F;
7'h4F: out_word = 7'h70;
7'h50: out_word = 7'h70;
7'h51: out_word = 7'h70;
7'h52: out_word = 7'h71;
7'h53: out_word = 7'h71;
7'h54: out_word = 7'h71;
7'h55: out_word = 7'h72;
7'h56: out_word = 7'h72;
7'h57: out_word = 7'h72;
7'h58: out_word = 7'h73;
7'h59: out_word = 7'h73;
7'h5A: out_word = 7'h73;
7'h5B: out_word = 7'h73;
7'h5C: out_word = 7'h74;
7'h5D: out_word = 7'h74;
7'h5E: out_word = 7'h74;
7'h5F: out_word = 7'h74;
7'h60: out_word = 7'h75;
7'h61: out_word = 7'h75;
7'h62: out_word = 7'h75;
7'h63: out_word = 7'h75;
7'h64: out_word = 7'h75;
7'h65: out_word = 7'h75;
7'h66: out_word = 7'h76;
7'h67: out_word = 7'h76;
7'h68: out_word = 7'h76;
7'h69: out_word = 7'h76;
7'h6A: out_word = 7'h76;
7'h6B: out_word = 7'h76;
7'h6C: out_word = 7'h76;
7'h6D: out_word = 7'h76;
7'h6E: out_word = 7'h77;
7'h6F: out_word = 7'h77;
7'h70: out_word = 7'h77;
7'h71: out_word = 7'h77;
7'h72: out_word = 7'h77;
7'h73: out_word = 7'h77;
7'h74: out_word = 7'h77;
7'h75: out_word = 7'h77;
7'h76: out_word = 7'h77;
7'h77: out_word = 7'h77;
7'h78: out_word = 7'h77;
default out_word = 7'h00;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; signed main() { long long ans; cin >> n; n++; if (n == 1) ans = 0; else if (n % 2 == 0) ans = n / 2; else ans = n; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f2f1f0f; const long long LINF = 1ll * INF * INF; const int MAX_N = 2e5 + 100; int N; long long C; int Nr[MAX_N * 2]; long long SumNr[MAX_N * 2]; long long Ans[MAX_N]; long long SumAns[MAX_N]; long long getSum(long long val[], int a, int b) { return val[b] - val[a - 1]; } long long getVal(int a, int b) { return getSum(SumNr, a * 2 - 1, b * 2 - 1) - getSum(SumAns, a, b - 1); } int main() { cin >> N >> C; for (int i = 1; i <= N * 2 - 1; i++) scanf( %d , &Nr[i]), SumNr[i] = SumNr[i - 1] + Nr[i]; deque<int> dQ; int cl = 0; for (int r = 1; r <= N; r++) { while (!dQ.empty() && getVal(dQ.back(), r) < Nr[r * 2 - 1]) dQ.pop_back(); dQ.push_back(r); while (!dQ.empty() && getSum(SumNr, dQ.front() * 2 - 1, r * 2 - 1) >= C) dQ.pop_front(); while (cl + 1 <= N && getSum(SumNr, (cl + 1) * 2 - 1, r * 2 - 1) >= C) cl++; if (cl != 0) Ans[r] = max(Ans[r], C - getSum(SumAns, cl, r - 1)); if (!dQ.empty()) Ans[r] = max(Ans[r], getVal(dQ.front(), r)); SumAns[r] = SumAns[r - 1] + Ans[r]; } printf( %lld n , SumAns[N]); return 0; } |
#include <bits/stdc++.h> using namespace std; char tr[100005]; map<char, int> p; char num[12] = { AHIMOTUVWXY }; char num1[27] = { ABCDEFGHIJKLMNOPQRSTUVWXYZ }; void init() { int i; for (i = 0; i < 26; i++) { p[num1[i]] = 0; } for (i = 0; i < 11; i++) { p[num[i]] = 1; } } int main() { init(); int n, i, j; while (scanf( %s , tr) != EOF) { n = strlen(tr); for (i = 0, j = n - 1; i < n / 2; i++, j--) { if (tr[i] != tr[j]) break; } if (i < n / 2) { printf( NO n ); continue; } for (i = 0; i < n; i++) { if (!p[tr[i]]) break; } if (i < n) printf( NO n ); else printf( YES n ); } return 0; } |
/* Verilog for cell 'PPGen_wordslice{sch}' from library 'wordlib8' */
/* Created on Mon Nov 04, 2013 20:40:31 */
/* Last revised on Wed Nov 06, 2013 18:23:07 */
/* Written on Wed Nov 06, 2013 18:23:30 by Electric VLSI Design System, version 8.06 */
module muddlib07__and2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_1, net_2;
tranif1 nmos_0(net_1, net_2, b);
tranif1 nmos_1(gnd, net_1, a);
tranif1 nmos_2(gnd, y, net_2);
tranif0 pmos_0(net_2, vdd, b);
tranif0 pmos_1(net_2, vdd, a);
tranif0 pmos_2(y, vdd, net_2);
endmodule /* muddlib07__and2_1x */
module muddlib07__xor2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire ab, bb, net_3, net_4, net_7, net_8;
tranif1 nmos_0(gnd, net_3, a);
tranif1 nmos_1(gnd, net_4, ab);
tranif1 nmos_2(net_3, y, b);
tranif1 nmos_3(net_4, y, bb);
tranif1 nmos_4(gnd, bb, b);
tranif1 nmos_5(gnd, ab, a);
tranif0 pmos_0(y, net_7, b);
tranif0 pmos_1(net_7, vdd, ab);
tranif0 pmos_2(y, net_8, bb);
tranif0 pmos_3(net_8, vdd, a);
tranif0 pmos_4(bb, vdd, b);
tranif0 pmos_5(ab, vdd, a);
endmodule /* muddlib07__xor2_1x */
module wordlib8__HalfAdder(A, Cin, Cout, Sum);
input A;
input Cin;
output Cout;
output Sum;
supply1 vdd;
supply0 gnd;
muddlib07__and2_1x and2_1x_0(.a(A), .b(Cin), .y(Cout));
muddlib07__xor2_1x xor2_1x_0(.a(A), .b(Cin), .y(Sum));
endmodule /* wordlib8__HalfAdder */
module muddlib07__inv_1x(a, y);
input a;
output y;
supply1 vdd;
supply0 gnd;
tranif1 nmos_0(gnd, y, a);
tranif0 pmos_0(y, vdd, a);
endmodule /* muddlib07__inv_1x */
module muddlib07__nand2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_5;
tranif1 nmos_0(net_5, y, b);
tranif1 nmos_1(gnd, net_5, a);
tranif0 pmos_0(y, vdd, b);
tranif0 pmos_1(y, vdd, a);
endmodule /* muddlib07__nand2_1x */
module muddlib07__nor2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_9;
tranif1 nmos_0(gnd, y, a);
tranif1 nmos_1(gnd, y, b);
tranif0 pmos_0(y, net_9, b);
tranif0 pmos_1(net_9, vdd, a);
endmodule /* muddlib07__nor2_1x */
module wordlib8__NAND8_reducer(inY, reduced_AND);
output [7:0] inY;
output reduced_AND;
supply1 vdd;
supply0 gnd;
wire net_0, net_10, net_14, net_2, net_4, net_6, net_8;
muddlib07__inv_1x inv_1x_0(.a(inY[7]), .y(net_14));
muddlib07__nand2_1x nand2_1x_0(.a(net_0), .b(net_2), .y(net_8));
muddlib07__nand2_1x nand2_1x_1(.a(net_4), .b(net_6), .y(net_10));
muddlib07__nor2_1x nor2_1x_0(.a(net_14), .b(inY[6]), .y(net_0));
muddlib07__nor2_1x nor2_1x_1(.a(inY[5]), .b(inY[4]), .y(net_2));
muddlib07__nor2_1x nor2_1x_2(.a(inY[3]), .b(inY[2]), .y(net_4));
muddlib07__nor2_1x nor2_1x_3(.a(inY[1]), .b(inY[0]), .y(net_6));
muddlib07__nor2_1x nor2_1x_8(.a(net_8), .b(net_10), .y(reduced_AND));
endmodule /* wordlib8__NAND8_reducer */
module wordlib8__PPGen_1bit(Double, Negate, Single, Yi, Yi_m1, PPi);
input Double;
input Negate;
input Single;
input Yi;
input Yi_m1;
output PPi;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_4;
muddlib07__nand2_1x nand2_1x_0(.a(Single), .b(Yi), .y(net_0));
muddlib07__nand2_1x nand2_1x_1(.a(net_0), .b(net_2), .y(net_4));
muddlib07__nand2_1x nand2_1x_2(.a(Double), .b(Yi_m1), .y(net_2));
muddlib07__xor2_1x xor2_1x_0(.a(net_4), .b(Negate), .y(PPi));
endmodule /* wordlib8__PPGen_1bit */
module muddlib07__nand3_1x(a, b, c, y);
input a;
input b;
input c;
output y;
supply1 vdd;
supply0 gnd;
wire net_15, net_4;
tranif1 nmos_0(net_15, net_4, b);
tranif1 nmos_1(net_4, y, c);
tranif1 nmos_2(gnd, net_15, a);
tranif0 pmos_0(y, vdd, c);
tranif0 pmos_1(y, vdd, b);
tranif0 pmos_2(y, vdd, a);
endmodule /* muddlib07__nand3_1x */
module wordlib8__PPGen_9bits(Double, Negate, Single, Y, PP, Sign);
input Double;
input Negate;
input Single;
input [7:0] Y;
output [8:0] PP;
output Sign;
supply1 vdd;
supply0 gnd;
wire HalfAdde_8_Cout, net_111, net_113, net_168, net_177, net_51, net_52;
wire net_53, net_54, net_55, net_56, net_57, net_58, net_59, net_64, net_69;
wire net_74, net_79, net_84, net_92;
wordlib8__HalfAdder HalfAdde_0(.A(net_58), .Cin(net_59), .Cout(net_113),
.Sum(PP[7]));
wordlib8__HalfAdder HalfAdde_1(.A(net_57), .Cin(net_64), .Cout(net_59),
.Sum(PP[6]));
wordlib8__HalfAdder HalfAdde_2(.A(net_56), .Cin(net_69), .Cout(net_64),
.Sum(PP[5]));
wordlib8__HalfAdder HalfAdde_3(.A(net_55), .Cin(net_74), .Cout(net_69),
.Sum(PP[4]));
wordlib8__HalfAdder HalfAdde_4(.A(net_54), .Cin(net_79), .Cout(net_74),
.Sum(PP[3]));
wordlib8__HalfAdder HalfAdde_5(.A(net_53), .Cin(net_84), .Cout(net_79),
.Sum(PP[2]));
wordlib8__HalfAdder HalfAdde_6(.A(net_52), .Cin(net_92), .Cout(net_84),
.Sum(PP[1]));
wordlib8__HalfAdder HalfAdde_7(.A(net_51), .Cin(Negate), .Cout(net_92),
.Sum(PP[0]));
wordlib8__HalfAdder HalfAdde_8(.A(net_111), .Cin(net_113),
.Cout(HalfAdde_8_Cout), .Sum(PP[8]));
wordlib8__NAND8_reducer NAND8_re_0(.inY(Y[7:0]), .reduced_AND(net_177));
wordlib8__PPGen_1bit PPGen_1b_0(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[7]), .Yi_m1(Y[6]), .PPi(net_58));
wordlib8__PPGen_1bit PPGen_1b_1(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[6]), .Yi_m1(Y[5]), .PPi(net_57));
wordlib8__PPGen_1bit PPGen_1b_2(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[5]), .Yi_m1(Y[4]), .PPi(net_56));
wordlib8__PPGen_1bit PPGen_1b_3(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[4]), .Yi_m1(Y[3]), .PPi(net_55));
wordlib8__PPGen_1bit PPGen_1b_4(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[3]), .Yi_m1(Y[2]), .PPi(net_54));
wordlib8__PPGen_1bit PPGen_1b_5(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[2]), .Yi_m1(Y[1]), .PPi(net_53));
wordlib8__PPGen_1bit PPGen_1b_6(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[1]), .Yi_m1(Y[0]), .PPi(net_52));
wordlib8__PPGen_1bit PPGen_1b_7(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[0]), .Yi_m1(gnd), .PPi(net_51));
wordlib8__PPGen_1bit PPGen_1b_8(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[7]), .Yi_m1(Y[7]), .PPi(net_111));
muddlib07__and2_1x and2_1x_0(.a(net_168), .b(PP[8]), .y(Sign));
muddlib07__nand3_1x nand3_1x_0(.a(net_177), .b(Negate), .c(Double),
.y(net_168));
endmodule /* wordlib8__PPGen_9bits */
module PPGen_wordslice(Double, Negate, Single, Y, PP0, PP1, PP2, PP3, Sign0,
Sign1, Sign2, Sign3);
input [3:0] Double;
input [3:0] Negate;
input [3:0] Single;
input [7:0] Y;
output [8:0] PP0;
output [8:0] PP1;
output [8:0] PP2;
output [8:0] PP3;
output Sign0;
output Sign1;
output Sign2;
output Sign3;
supply1 vdd;
supply0 gnd;
wordlib8__PPGen_9bits PPGen_9b_0(.Double(Double[3]), .Negate(Negate[3]),
.Single(Single[3]), .Y(Y[7:0]), .PP(PP3[8:0]), .Sign(Sign3));
wordlib8__PPGen_9bits PPGen_9b_1(.Double(Double[2]), .Negate(Negate[2]),
.Single(Single[2]), .Y(Y[7:0]), .PP(PP2[8:0]), .Sign(Sign2));
wordlib8__PPGen_9bits PPGen_9b_2(.Double(Double[1]), .Negate(Negate[1]),
.Single(Single[1]), .Y(Y[7:0]), .PP(PP1[8:0]), .Sign(Sign1));
wordlib8__PPGen_9bits PPGen_9b_3(.Double(Double[0]), .Negate(Negate[0]),
.Single(Single[0]), .Y(Y[7:0]), .PP(PP0[8:0]), .Sign(Sign0));
endmodule /* PPGen_wordslice */
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10; const int maxe = maxn * 2; int fir[maxn]; struct Edge { int v, c, nxt; Edge(int v = 0, int c = 0, int nxt = 0) : v(v), c(c), nxt(nxt) {} } edge[maxe]; int cnt; bool cir[maxn]; void init() { memset(fir, -1, sizeof(fir)); cnt = 0; } void add_edge(int u, int v, int c) { edge[cnt] = Edge(v, c, fir[u]); fir[u] = cnt++; } bool dfs(int from, int to, int c) { cir[from] = true; if (from == to) return true; for (int e = fir[from]; e != -1; e = edge[e].nxt) if (!cir[edge[e].v]) { if (edge[e].c != c) continue; if (dfs(edge[e].v, to, c)) { return true; } } return false; } int solve(int from, int to) { int ans = 0; bool vis[maxn]; memset(vis, false, sizeof(vis)); for (int e = fir[from]; e != -1; e = edge[e].nxt) if (!vis[edge[e].c]) { memset(cir, false, sizeof(cir)); if (dfs(from, to, edge[e].c)) { ans++; } vis[edge[e].c] = true; } return ans; } int main() { int n, m; scanf( %d%d , &n, &m); init(); for (int i = 0; i < m; i++) { int u, v, c; scanf( %d%d%d , &u, &v, &c); add_edge(u, v, c); add_edge(v, u, c); } int q; scanf( %d , &q); while (q--) { int u, v; scanf( %d%d , &u, &v); printf( %d n , solve(u, v)); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/24/2016 02:54:35 PM
// Design Name:
// Module Name: Problem1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem1(
input [3:0] Binary_Number,
output reg [6:0] Cathodes,
output reg Anode
);
// Cathode 0 is A
always @ ( Binary_Number)
begin
Anode = 0;
case(Binary_Number)
4'b0000: begin // number 0
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 0;
Cathodes[6] = 1;
end
4'b0001: begin // number 1
Cathodes[0] = 1;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 1;
Cathodes[5] = 1;
Cathodes[6] = 1;
end
4'b0010: begin //number 2
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 1;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
4'b0011: begin // number 3
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 1;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
4'b0100: begin // number 4
Cathodes[0] = 1;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 1;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b0101: begin // number 5
Cathodes[0] = 0;
Cathodes[1] = 1;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 1;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b0110: begin // number 6
Cathodes[0] = 0;
Cathodes[1] = 1;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b0111: begin // number 7
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 1;
Cathodes[5] = 1;
Cathodes[6] = 1;
end
4'b1000: begin // number 8
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b1001: begin // number 9
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 1;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b1010: begin // capital A
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 0;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b1011: begin // lowercase b
Cathodes[0] = 1;
Cathodes[1] = 1;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b1100: begin // lowercase c
Cathodes[0] = 1;
Cathodes[1] = 1;
Cathodes[2] = 1;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
4'b1101: begin // lowercase d
Cathodes[0] = 1;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
4'b1110: begin // capital E
Cathodes[0] = 0;
Cathodes[1] = 1;
Cathodes[2] = 1;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
4'b1111: begin // capital F
Cathodes[0] = 0;
Cathodes[1] = 1;
Cathodes[2] = 1;
Cathodes[3] = 1;
Cathodes[4] = 0;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
endcase
end
endmodule
|
module pr_region_default_mm_bridge_1 #(
parameter DATA_WIDTH = 512,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 32,
parameter BURSTCOUNT_WIDTH = 5,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [63:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [63:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long pred[300005]; long long suffc[300005]; long long ans[300005]; int main() { int n, m; scanf( %d %d , &n, &m); pair<int, int> ara[n]; vector<pair<int, int> > vt(n); for (int i = 0; i < n; i++) { scanf( %d %d , &ara[i].first, &ara[i].second); vt[i] = {ara[i].second - ara[i].first, i}; } sort(vt.begin(), vt.end()); pred[0] = ara[vt[0].second].second; for (int i = 1; i < n; i++) { pred[i] = pred[i - 1] + ara[vt[i].second].second; } suffc[n - 1] = ara[vt[n - 1].second].first; for (int i = n - 2; i >= 0; i--) { suffc[i] = suffc[i + 1] + ara[vt[i].second].first; } for (int i = 0; i < n; i++) { int pos = upper_bound(vt.begin(), vt.end(), make_pair(ara[i].second - ara[i].first, n + 1)) - vt.begin(); ans[i] += 1ll * suffc[pos] + 1ll * (n - pos) * ara[i].second; pos--; if (pos >= 0) ans[i] += 1ll * pred[pos] + 1ll * (pos + 1) * ara[i].first, ans[i] -= ara[i].first + ara[i].second; if (i == 0) { } } for (int i = 0; i < m; i++) { int u, v; scanf( %d %d , &u, &v); u--, v--; ans[u] -= min(ara[u].first + ara[v].second, ara[u].second + ara[v].first); ans[v] -= min(ara[u].first + ara[v].second, ara[u].second + ara[v].first); } for (int i = 0; i < n; i++) printf( %lld , ans[i]); return 0; } |
// ICEDEV=hx8k-ct256 bash ../icecube.sh sb_ram40.v
// ../../icebox/icebox_vlog.py -P sb_ram40.psb sb_ram40.txt
// ../../icebox/icebox_explain.py -t '7 21' sb_ram40.txt
module top (
input [10:0] WADDR,
input [10:0] RADDR,
input [15:0] MASK,
input [15:0] WDATA,
output [15:0] RDATA_0,
output [ 7:0] RDATA_1,
output [ 1:0] RDATA_3,
input WE, WCLKE, WCLK,
input RE, RCLKE, RCLK,
output X
);
// Write Mode 0: 8 Bit ADDR, 16 Bit DATA, MASK
// Write Mode 1: 9 Bit ADDR, 8 Bit DATA, NO MASK
// Write Mode 2: 10 Bit ADDR, 4 Bit DATA, NO MASK
// Write Mode 3: 11 Bit ADDR, 2 Bit DATA, NO MASK
SB_RAM40_4K #(
.READ_MODE(0),
.WRITE_MODE(0)
) ram40_00 (
.WADDR(WADDR[7:0]),
.RADDR(RADDR[7:0]),
.MASK(MASK),
.WDATA(WDATA),
.RDATA(RDATA_0),
.WE(WE),
.WCLKE(WCLKE),
.WCLK(WCLK),
.RE(RE),
.RCLKE(RCLKE),
.RCLK(RCLK)
);
SB_RAM40_4K #(
.READ_MODE(1),
.WRITE_MODE(2)
) ram40_12 (
.WADDR(WADDR[9:0]),
.RADDR(RADDR[8:0]),
.WDATA(WDATA[3:0]),
.RDATA(RDATA_1),
.WE(WE),
.WCLKE(WCLKE),
.WCLK(WCLK),
.RE(RE),
.RCLKE(RCLKE),
.RCLK(RCLK)
);
SB_RAM40_4K #(
.READ_MODE(3),
.WRITE_MODE(3)
) ram40_33 (
.WADDR(WADDR),
.RADDR(RADDR),
.WDATA(WDATA[1:0]),
.RDATA(RDATA_3),
.WE(WE),
.WCLKE(WCLKE),
.WCLK(WCLK),
.RE(RE),
.RCLKE(RCLKE),
.RCLK(RCLK)
);
SB_LUT4 #(
.LUT_INIT(16'b 1000_0000_0000_0000)
) lut (
.O(X),
.I0(RDATA_0[0]),
.I1(RDATA_0[6]),
.I2(RDATA_0[8]),
.I3(RDATA_0[14])
);
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_DATA_WIDTH/8-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr ;
assign itf_cmd_burstlen = avl_size ;
assign itf_cmd_autopercharge = local_autopch_req ;
assign itf_cmd_priority = local_priority ;
assign itf_cmd_multicast = local_multicast ;
assign itf_cmd = avl_write_req;
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req : itf_cmd_ready & avl_write_req;
assign itf_wr_data = avl_wdata ;
assign itf_wr_data_byte_en = avl_be ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid;
assign avl_rdata = itf_rd_data;
assign local_rdata_error = itf_rd_data_error;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
burst_counter <= avl_size - 1;
else if (avl_write_req && itf_wr_data_ready)
burst_counter <= burst_counter - 1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
data_pass <= 1;
else if (burst_counter == 1 && avl_write_req && itf_wr_data_ready)
data_pass <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_brams_v6.v
// Version : 1.7
//--
//-- Description: BlockRAM module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_brams_v6
#(
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
parameter TCQ = 1;
//synthesis translate_off
initial begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_dly;
reg [12:0] waddr_dly;
reg [71:0] wdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
wen_dly <= #TCQ 1'b0;
waddr_dly <= #TCQ 13'b0;
wdata_dly <= #TCQ 72'b0;
end else begin
wen_dly <= #TCQ wen;
waddr_dly <= #TCQ waddr;
wdata_dly <= #TCQ wdata;
end
end
assign wen_int = wen_dly;
assign waddr_int = waddr_dly;
assign wdata_int = wdata_dly;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_dly;
reg [12:0] raddr_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
ren_dly <= #TCQ 1'b0;
raddr_dly <= #TCQ 13'b0;
end else begin
ren_dly <= #TCQ ren;
raddr_dly <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_dly;
assign raddr_int = raddr_dly;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
rdata_dly <= #TCQ 72'b0;
end else begin
rdata_dly <= #TCQ rdata_int;
end // else: !if(reset_i)
end
assign rdata = rdata_dly;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign #TCQ rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar i;
for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams
pcie_bram_v6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))
ram (.user_clk_i(user_clk_i), .reset_i(reset_i),
.wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]),
.ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));
end
endgenerate
endmodule // pcie_brams_v6
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double eps = 1e-9; int n, m, l, r; int main() { int T, cas = 1, x = INF; scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) { scanf( %d%d , &l, &r); x = min(x, r - l + 1); } printf( %d n , x); for (int i = 1; i <= n; ++i) printf( %d%c , i % x, i == n ? n : ); return 0; } |
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module pulse2pulse(/*AUTOARG*/
// Outputs
out,
// Inputs
inclk, outclk, in, reset
);
//clocks
input inclk;
input outclk;
input in;
output out;
//reset
input reset;
wire intoggle;
wire insync;
//pulse to toggle
pulse2toggle pulse2toggle(
// Outputs
.out (intoggle),
// Inputs
.clk (inclk),
.in (in),
.reset (reset));
//metastability synchronizer
synchronizer #(1) synchronizer(
// Outputs
.out (insync),
// Inputs
.in (intoggle),
.clk (outclk),
.reset (reset));
//toogle to pulse
toggle2pulse toggle2pulse(
// Outputs
.out (out),
// Inputs
.clk (outclk),
.in (insync),
.reset (reset));
endmodule // pulse2pulse
|
#include <bits/stdc++.h> using namespace std; int s[200005]; struct pp { int lev; int loc; } s1[200005], s2[200005]; bool cmp(pp &a, pp &b) { return a.lev < b.lev; } int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int s1h = 0, s2h = 0; string test; int n; cin >> n; for (int j = 0; j < n; j++) { cin >> s[j]; } cin >> test; for (int p = 0; p < test.length(); p++) { if (test[p] == 0 ) s1[s1h].lev = s[p], s1[s1h++].loc = p; else s2[s2h].lev = s[p], s2[s2h++].loc = p; } sort(s1, s1 + s1h, cmp); sort(s2, s2 + s2h, cmp); for (int j = 0; j < s1h; j++) { s[s1[j].loc] = j + 1; } for (int j = 0; j < s2h; j++) { s[s2[j].loc] = j + s1h + 1; } for (int j = 0; j < n; j++) cout << s[j] << ; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <typename T> inline T range(T l, T r) { return uniform_int_distribution<T>(l, r)(rng); } inline void setin(string s) { freopen(s.c_str(), r , stdin); } inline void setout(string s) { freopen(s.c_str(), w , stdout); } template <typename T> void Min(T &a, T b) { a = min(a, b); } template <typename T> void Max(T &a, T b) { a = max(a, b); } const int mod = 998244353; const int inf = 0x3f3f3f3f; const int N = 1e6 + 15; int n; vector<int> g[N]; int cnt[N], cl[N]; void dfs(int v, int p = -1) { cnt[cl[v]]++; for (int to : g[v]) { if (to != p) { cl[to] = cl[v] ^ 1; dfs(to, v); } } } int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); cin >> n; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } dfs(1); cout << min(cnt[0], cnt[1]) - 1 << n ; return 0; } |
module k_nns_seq
#
(
parameter W = 15,
parameter K = 4
)
(
clk,
rst,
g_input,
e_input,
o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value;
for (log2=0; temp>0; log2=log2+1)
temp = temp>>1;
end
endfunction
localparam LOGW = log2(W);
input clk;
input rst;
input [W-1:0] g_input;
input [W-1:0] e_input;
output [W*K-1:0] o;
wire [LOGW-1:0] dist;
wire [W-1:0] min_val [K-1:0];
wire [LOGW-1:0] min_dist [K-1:0];
reg [W-1:0] min_val_reg [K-1:0];
reg [LOGW-1:0] min_dist_reg [K-1:0];
wire gt_dist_1 [K-1:0];
wire gt_dist_2 [K-1:0];
wire [W-1:0] local_min_val [K:0];
wire [LOGW-1:0] local_min_dist [K:0];
genvar i;
generate
for (i=0;i<K;i=i+1)
begin:D_ASN
assign o[W*(i+1)-1:W*i] = min_val[i];
end
endgenerate
COUNT
#(
.N(W)
)
COUNT_
(
.A(g_input ^ e_input),
.S(dist)
);
generate
for (i=0;i<K;i=i+1)
begin:COMP_ASN
COMP
#(
.N(LOGW)
)
COMP_1
(
.A(min_dist_reg[i]),
.B(local_min_dist[i+1]),
.O(gt_dist_1[i])
);
if(i>0)
begin
COMP
#(
.N(LOGW)
)
COMP_2
(
.A(min_dist_reg[i-1]),
.B(local_min_dist[i]),
.O(gt_dist_2[i])
);
end
else
begin
assign gt_dist_2[i] = 0;
end
end
endgenerate
generate
for (i=0;i<K;i=i+1)
begin:MUX_ASN
MUX
#(
.N(LOGW)
)
MUX_1
(
.A(min_dist_reg[i]),
.B(local_min_dist[i+1]),
.S(gt_dist_1[i]),
.O(local_min_dist[i])
);
if(i>0)
begin
MUX
#(
.N(LOGW)
)
MUX_2
(
.A(local_min_dist[i]),
.B(min_dist_reg[i-1]),
.S(gt_dist_2[i]),
.O(min_dist[i])
);
end
else
begin
assign min_dist[i] = local_min_dist[i];
end
MUX
#(
.N(W)
)
MUX_3
(
.A(min_val_reg[i]),
.B(local_min_val[i+1]),
.S(gt_dist_1[i]),
.O(local_min_val[i])
);
if(i>0)
begin
MUX
#(
.N(W)
)
MUX_4
(
.A(local_min_val[i]),
.B(min_val_reg[i-1]),
.S(gt_dist_2[i]),
.O(min_val[i])
);
end
else
begin
assign min_val[i] = local_min_val[i];
end
end
endgenerate
assign local_min_dist[K] = dist;
assign local_min_val[K] = e_input;
integer j;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
for(j=0;j<K;j=j+1)
begin
min_val_reg[j] <= 0;
min_dist_reg[j] <= {LOGW{1'b1}};
end
end
else
begin
for(j=0;j<K;j=j+1)
begin
min_val_reg[j] <= min_val[j];
min_dist_reg[j] <= min_dist[j];
end
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 9: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] d1_data_in;
reg [ 9: 0] d2_data_in;
wire [ 9: 0] data_in;
reg [ 9: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 9: 0] edge_detect;
wire irq;
reg [ 9: 0] irq_mask;
wire [ 9: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({10 {(address == 0)}} & data_in) |
({10 {(address == 2)}} & irq_mask) |
({10 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[9 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[4])
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[5])
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[6])
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[7])
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[8] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[8])
edge_capture[8] <= 0;
else if (edge_detect[8])
edge_capture[8] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[9] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[9])
edge_capture[9] <= 0;
else if (edge_detect[9])
edge_capture[9] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, cnt_t = 0; vector<pair<int, int>> ls_[2]; vector<int> upb, downb; bool cmp(pair<int, int> a, pair<int, int> b) { if (a.first != b.first) { return a.first < b.first; } return a.second < b.second; } long long proc(vector<pair<int, int>> &ls) { long long sum = 0; int sz = ls.size(); if (sz == 0) return 0; sort(ls.begin(), ls.end(), cmp); int ex_up = 0, ex_down = 0; int bup = -200001; int bdown = -bup; int i, rup, rdown; for (i = 0; i < sz; i++) { if (ls[i].second > bup || ls[i].second == bup && ls[i].first > rup) { bup = ls[i].second, rup = ls[i].first; } if (ls[i].second < bdown || ls[i].second == bdown && ls[i].first > rdown) { bdown = ls[i].second, rdown = ls[i].first; } } int j, k; int bd; bd = ls[0].second; int bsz = (ls.back().first - ls[0].first) / 2; upb.clear(); upb.resize(bsz); downb.clear(); downb.resize(bsz); for (i = 0, k = ls[0].first; k < rup; k += 2) { for (j = i; ls[j].first == k; j++) ; if (j > i) { if (ls[j - 1].second > bd) bd = ls[j - 1].second; i = j; } upb[(k - ls[0].first) / 2] = bd; } bd = ls[0].second; for (i = 0, k = ls[0].first; k < rdown; k += 2) { for (j = i; ls[j].first == k; j++) ; if (j > i) { if (ls[i].second < bd) bd = ls[i].second; i = j; } downb[(k - ls[0].first) / 2] = bd; } bd = ls.back().second; for (i = sz - 1, k = ls.back().first; k > rup; k -= 2) { for (j = i; ls[j].first == k; j--) ; if (j < i) { if (ls[i].second > bd) bd = ls[i].second; i = j; } upb[bsz - 1 - (ls.back().first - k) / 2] = bd; } bd = ls.back().second; for (i = sz - 1, k = ls.back().first; k > rdown; k -= 2) { for (j = i; ls[j].first == k; j--) ; if (j < i) { if (ls[j + 1].second < bd) bd = ls[j + 1].second; i = j; } downb[bsz - 1 - (ls.back().first - k) / 2] = bd; } for (i = 0; i < bsz; i++) { if (upb[i] >= downb[i]) { sum += (upb[i] - downb[i]) / 2; } } return sum; } int main() { int n, i, u, v; scanf( %d , &n); ls_[0].clear(); ls_[1].clear(); for (i = 0; i < n; i++) { scanf( %d%d , &u, &v); ls_[((u + v) % 2 + 2) % 2].push_back(make_pair(u - v, u + v)); } long long ans = proc(ls_[0]) + proc(ls_[1]); printf( %lld n , ans); return 0; } |
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