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#include <bits/stdc++.h> using namespace std; template <typename _T> inline void read(_T &f) { f = 0; _T fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fu = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + (c & 15); c = getchar(); } f *= fu; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 48); else print(x / 10), putchar(x % 10 + 48); } template <typename T> void print(T x, char t) { print(x); putchar(t); } template <typename T> struct hash_map_t { vector<T> v, val, nxt; vector<int> head; int mod, tot, lastv; T lastans; bool have_ans; hash_map_t(int md = 0) { head.clear(); v.clear(); val.clear(); nxt.clear(); tot = 0; mod = md; nxt.resize(1); v.resize(1); val.resize(1); head.resize(mod); have_ans = 0; } bool count(int x) { int u = x % mod; for (register int i = head[u]; i; i = nxt[i]) { if (v[i] == x) { have_ans = 1; lastv = x; lastans = val[i]; return 1; } } return 0; } void ins(int x, int y) { int u = x % mod; nxt.push_back(head[u]); head[u] = ++tot; v.push_back(x); val.push_back(y); } int qry(int x) { if (have_ans && lastv == x) return lastans; count(x); return lastans; } }; const int N = 4e5 + 5; struct edge_t { int u, v, next; } G[N << 1]; int maxn[N << 2], head[N], siz[N], ans[N], tops[N]; int n, tot, dfn; inline void addedge(int u, int v) { G[++tot] = (edge_t){u, v, head[u]}, head[u] = tot; G[++tot] = (edge_t){v, u, head[v]}, head[v] = tot; } void update(int u) { maxn[u] = max(maxn[u << 1], maxn[u << 1 | 1]); } void change(int u, int l, int r, int x, int y) { if (l == r) { maxn[u] = y; return; } int mid = (l + r) >> 1; if (mid >= x) change(u << 1, l, mid, x, y); else change(u << 1 | 1, mid + 1, r, x, y); update(u); } int query(int u, int l, int r, int L, int R) { if (l > r) return 0; if (l <= L && R <= r) return maxn[u]; int mid = (L + R) >> 1, ans = 0; if (mid >= l) ans = max(ans, query(u << 1, l, r, L, mid)); if (mid + 1 <= r) ans = max(ans, query(u << 1 | 1, l, r, mid + 1, R)); return ans; } void dfs1(int u, int fa) { tops[u] = ++dfn; siz[u] = 1; for (register int i = head[u]; i; i = G[i].next) { int v = G[i].v; if (v == fa) continue; dfs1(v, u); siz[u] += siz[v]; } if (siz[u] <= (n >> 1)) change(1, 1, n, tops[u], siz[u]); } void dfs2(int u, int fa, int mx) { bool qaq = 1; if (n - siz[u] > (n >> 1) && max(max(query(1, 1, tops[u] - 1, 1, n), query(1, tops[u] + siz[u], n, 1, n)), mx) >= n - siz[u] - (n >> 1)) ans[u] = 1; if (n - siz[u] <= (n >> 1)) mx = max(mx, n - siz[u]); else qaq = 0; if (siz[u] <= (n >> 1)) change(1, 1, n, tops[u], 0); for (register int i = head[u]; i; i = G[i].next) { int v = G[i].v; if (v == fa) continue; dfs2(v, u, mx); if (siz[v] > (n >> 1)) { qaq = 0; if (query(1, tops[u], tops[u] + siz[u] - 1, 1, n) >= siz[v] - (n >> 1)) ans[u] = 1; } } if (qaq) ans[u] = 1; if (siz[u] <= (n >> 1)) change(1, 1, n, tops[u], siz[u]); } int main() { read(n); for (register int i = 1; i < n; i++) { int u, v; read(u); read(v); addedge(u, v); } dfs1(1, 0); dfs2(1, 0, 0); for (register int i = 1; i <= n; i++) print(ans[i], i == n ? n : ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A32O_FUNCTIONAL_PP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 and0_out ;
wire B1 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> int main() { int n; while (scanf( %d , &n) != EOF) { int ans = 0; int sum = 0; while (n--) { int x; scanf( %d , &x); if (x == -1) { if (!sum) ans++; else sum--; } else sum += x; } printf( %d n , ans); } return 0; } |
module sopc(
input clock,
input reset
);
wire rom_chip_enable ;
wire [31:0] rom_read_address;
wire [31:0] rom_read_data ;
wire ram_chip_enable ;
wire ram_read_enable ;
wire [31:0] ram_read_address ;
wire [31:0] ram_read_data ;
wire ram_write_enable ;
wire [31:0] ram_write_address;
wire [ 3:0] ram_write_select ;
wire [31:0] ram_write_data ;
cpu cpu(
.clock (clock ),
.reset (reset ),
.rom_read_address (rom_read_address ),
.rom_read_data (rom_read_data ),
.ram_read_enable (ram_read_enable ),
.ram_read_address (ram_read_address ),
.ram_read_data (ram_read_data ),
.ram_write_enable (ram_write_enable ),
.ram_write_address (ram_write_address),
.ram_write_select (ram_write_select ),
.ram_write_data (ram_write_data )
);
assign rom_chip_enable = (reset == `RESET_ENABLE) ? `CHIP_DISABLE : `CHIP_ENABLE;
assign ram_chip_enable = (reset == `RESET_ENABLE) ? `CHIP_DISABLE : `CHIP_ENABLE;
rom rom(
.chip_enable (rom_chip_enable ),
.read_address (rom_read_address),
.read_data (rom_read_data )
);
ram ram(
.clock (clock ),
.chip_enable (ram_chip_enable ),
.read_enable (ram_read_enable ),
.read_address (ram_read_address ),
.read_data (ram_read_data ),
.write_enable (ram_write_enable ),
.write_address (ram_write_address),
.write_select (ram_write_select ),
.write_data (ram_write_data )
);
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { long long n, l, r; cin >> n; pair<pair<long long, long long>, long long> lr[n + 1]; for (long long i = 1; i <= n; i++) { cin >> lr[i].first.first >> lr[i].first.second; lr[i].second = i; } sort(lr + 1, lr + n + 1); for (long long i = 2; i <= n; i++) { if (lr[i].first.second <= lr[i - 1].first.second) { return cout << lr[i].second << << lr[i - 1].second, 0; } if (lr[i].first.first == lr[i - 1].first.first) { return cout << lr[i - 1].second << << lr[i].second, 0; } } cout << -1 -1 ; } |
#include <bits/stdc++.h> using namespace std; int n, i, j, k, s, a[50], b[50], c[50]; long long x; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %I64d , &x); for (j = 0; (1ll << j) < x; j++) ; if ((1ll << j) == x) a[j]++; else b[j - 1]++; } for (i = a[0]; i > 0; i--) { k = i; s = 0; for (j = 0; j <= 40; j++) { k = min(k, a[j]); c[j] = k; } for (j = 40; j >= 0; j--) { s += b[j] + a[j] - c[j]; if (s > c[j]) break; } if (j >= 0) break; } if (i == a[0]) cout << -1 ; else for (i++; i <= a[0]; i++) cout << i << ; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, h; cin >> n >> h; for (int i = 1; i < n; i++) printf( %.10f , h * sqrt(1. * i / n)); puts( ); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; t = 1; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_0_V
`define SKY130_FD_SC_LP__INV_0_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_0 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_0 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_0_V
|
//-----------------------------------------------------------------
//
// Filename : xlclockdriver.v
//
// Date : 6/29/2004
//
// Description : Verilog description of a clock enable generator block.
// This code is synthesizable.
//
// Assumptions : period >= 1
//
// Mod. History : Translated VHDL clockdriver to Verilog
// : Added pipeline registers
//
// Mod. Dates : 6/29/2004
// : 12/14/2004
//
//-------------------------------------------------------------------
`timescale 1 ns / 10 ps
module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic);
parameter signed [31:0] log_2_period = 1;
parameter signed [31:0] period = 2;
parameter signed [31:0] use_bufg = 1'b0;
parameter signed [31:0] pipeline_regs = 5;
input sysclk;
input sysclr;
input sysce;
output clk;
output clr;
output ce;
output ce_logic;
//A maximum value of 8 would allow register balancing to the tune of 10^8
//It is set to 8 since we do not have more than 10^8 nets in an FPGA
parameter signed [31:0] max_pipeline_regs = 8;
//Check if requested pipeline regs are greater than the max amount
parameter signed [31:0] num_pipeline_regs = (max_pipeline_regs > pipeline_regs)? pipeline_regs : max_pipeline_regs;
parameter signed [31:0] factor = num_pipeline_regs/period;
parameter signed [31:0] rem_pipeline_regs = num_pipeline_regs - (period * factor) + 1;
//Old constant values
parameter [log_2_period-1:0] trunc_period = ~period + 1;
parameter signed [31:0] period_floor = (period>2)? period : 2;
parameter signed [31:0] power_of_2_counter = (trunc_period == period) ? 1 : 0;
parameter signed [31:0] cnt_width = (power_of_2_counter & (log_2_period>1)) ? (log_2_period - 1) : log_2_period;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus1 = period_floor-2;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus2 = (period-3>0)? period-3 : 0;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus_regs = ((period-rem_pipeline_regs)>0)? (period-rem_pipeline_regs) : 0;
reg [cnt_width-1:0] clk_num;
reg temp_ce_vec;
wire [num_pipeline_regs:0] ce_vec;
wire [num_pipeline_regs:0] ce_vec_logic;
wire internal_ce;
wire internal_ce_logic;
reg cnt_clr;
wire cnt_clr_dly;
genvar index;
initial
begin
clk_num = 'b0;
end
assign clk = sysclk ;
assign clr = sysclr ;
// Clock Number Counter
always @(posedge sysclk)
begin : cntr_gen
if (sysce == 1'b1)
begin:hc
if ((cnt_clr_dly == 1'b1) || (sysclr == 1'b1))
begin:u1
clk_num = {cnt_width{1'b0}};
end
else
begin:u2
clk_num = clk_num + 1 ;
end
end
end
// Clear logic for counter
generate
if (power_of_2_counter == 1)
begin:clr_gen_p2
always @(sysclr)
begin:u1
cnt_clr = sysclr;
end
end
endgenerate
generate
if (power_of_2_counter == 0)
begin:clr_gen
always @(clk_num or sysclr)
begin:u1
if ( (clk_num == clk_for_ce_pulse_minus1) | (sysclr == 1'b1) )
begin:u2
cnt_clr = 1'b1 ;
end
else
begin:u3
cnt_clr = 1'b0 ;
end
end
end // block: clr_gen
endgenerate
synth_reg_w_init #(1, 0, 'b0000, 1)
clr_reg(.i(cnt_clr),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(cnt_clr_dly));
//Clock Enable Generation
generate
if (period > 1)
begin:pipelined_ce
always @(clk_num)
begin:np_ce_gen
if (clk_num == clk_for_ce_pulse_minus_regs)
begin
temp_ce_vec = 1'b1 ;
end
else
begin
temp_ce_vec = 1'b0 ;
end
end
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg(.i(ce_vec[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec[index]));
end //block ce_pipeline
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline_logic
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg_logic(.i(ce_vec_logic[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec_logic[index]));
end //block ce_pipeline
assign ce_vec_logic[num_pipeline_regs] = temp_ce_vec;
assign ce_vec[num_pipeline_regs] = temp_ce_vec;
assign internal_ce = ce_vec[0];
assign internal_ce_logic = ce_vec_logic[0];
end // block: pipelined_ce
endgenerate
generate
if (period > 1)
begin:period_greater_than_1
if (use_bufg == 1'b1)
begin:use_bufg
BUFG ce_bufg_inst(.I(internal_ce), .O(ce));
BUFG ce_logic_bufg_inst(.I(internal_ce_logic), .O(ce_logic));
end
else
begin:no_bufg
assign ce = internal_ce & sysce;
assign ce_logic = internal_ce_logic & sysce;
end
end
endgenerate
generate
if (period == 1)
begin:period_1
assign ce = sysce;
assign ce_logic = sysce;
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long int pow_mod(long long int a, long long int b) { long long int res = 1; while (b != 0) { if (b & 1) { res = (res * a) % 1000000007; } a = (a * a) % 1000000007; b /= 2; } return res; } void solve() { long long int x1, y1, z1; cin >> x1 >> y1 >> z1; long long int x2, y2, z2; cin >> x2 >> y2 >> z2; long long int ans = 0; ans = min(z1, y2); ans *= 2; z1 -= min(z1, y2); z2 -= min(z2, z1); z2 -= min(z2, x1); ans -= z2 * 2; cout << ans << endl; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; t = 1; cin >> t; while (t--) solve(); return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file sounds_mem.v when simulating
// the core, sounds_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module sounds_mem(
clka,
addra,
douta
);
input clka;
input [3 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(4),
.C_ADDRB_WIDTH(4),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("sounds_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16),
.C_READ_DEPTH_B(16),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16),
.C_WRITE_DEPTH_B(16),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; vector<pair<int, int>> g[N], ans[N]; long long dist[N]; priority_queue<pair<int, int>> pq; bool vis[N]; void dijkstra(int s) { fill(dist, dist + N, 1LL << 61); memset(vis, false, sizeof(vis)); dist[s] = 0; pq.push({0, s}); while (!pq.empty()) { int u = pq.top().second; pq.pop(); if (vis[u]) continue; vis[u] = true; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i].first, w = g[u][i].second; if (dist[v] > dist[u] + w) { dist[v] = dist[u] + w; pq.push({-dist[v], v}); } } } } int main() { int n, m; cin >> n >> m; int x, y; cin >> x >> y; for (int i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; g[u].push_back({v, w}); g[v].push_back({u, w}); } for (int i = 1; i <= n; i++) { long long ti, ci; cin >> ti >> ci; dijkstra(i); for (int j = 1; j <= n; j++) { if (dist[j] <= ti) { ans[i].push_back({j, ci}); } } } for (int i = 1; i <= n; i++) { g[i] = ans[i]; } dijkstra(x); if (dist[y] == 1LL << 61) cout << -1; else cout << dist[y]; return 0; } |
#include <bits/stdc++.h> int main(void) { unsigned int const max_skill_level = 100; unsigned int number_of_boys; unsigned int number_of_girls; unsigned int number_of_pairs = 0; std::vector<unsigned int> number_of_boys_with_each_skill_level( max_skill_level + 1, 0); std::vector<unsigned int> number_of_girls_with_each_skill_level( max_skill_level + 1, 0); std::ios_base::sync_with_stdio(false); std::cin >> number_of_boys; for (unsigned int i = 0; i < number_of_boys; ++i) { std::size_t skill_level; std::cin >> skill_level; ++number_of_boys_with_each_skill_level[skill_level]; } std::cin >> number_of_girls; for (unsigned int i = 0; i < number_of_girls; ++i) { std::size_t skill_level; std::cin >> skill_level; ++number_of_girls_with_each_skill_level[skill_level]; } for (std::size_t i = 0; i < max_skill_level; ++i) { unsigned int number_of_new_pairs; number_of_new_pairs = std::min(number_of_boys_with_each_skill_level[i], number_of_girls_with_each_skill_level[i]); number_of_boys_with_each_skill_level[i] -= number_of_new_pairs; number_of_girls_with_each_skill_level[i] -= number_of_new_pairs; number_of_pairs += number_of_new_pairs; number_of_new_pairs = std::min(number_of_boys_with_each_skill_level[i], number_of_girls_with_each_skill_level[i + 1]); number_of_boys_with_each_skill_level[i] -= number_of_new_pairs; number_of_girls_with_each_skill_level[i + 1] -= number_of_new_pairs; number_of_pairs += number_of_new_pairs; number_of_new_pairs = std::min(number_of_boys_with_each_skill_level[i + 1], number_of_girls_with_each_skill_level[i]); number_of_boys_with_each_skill_level[i + 1] -= number_of_new_pairs; number_of_girls_with_each_skill_level[i] -= number_of_new_pairs; number_of_pairs += number_of_new_pairs; } number_of_pairs += std::min(number_of_boys_with_each_skill_level.back(), number_of_girls_with_each_skill_level.back()); std::cout << number_of_pairs << n ; return 0; } |
//======================================================================
//
// Module Name: WHIRLPOOL_WCIPHER_MU
// Description: Mu function of Whirlpool W-Cipher
//
// Language: Verilog-2001
//
// Module Dependencies: none
//
// Developer: Saied H. Khayat
// URL: https://github.com/saiedhk
// Date: May 2014
//
// Copyright Notice: Free use of this library is permitted under the
// guidelines and in accordance with the MIT License (MIT).
// http://opensource.org/licenses/MIT
//
//======================================================================
`timescale 1ns/1ps
//`define DEBUG
`define PRINT_TEST_VECTORS
module WHIRLPOOL_WCIPHER_MU (
output [7:0] B00, B01, B02, B03, B04, B05, B06, B07,
B10, B11, B12, B13, B14, B15, B16, B17,
B20, B21, B22, B23, B24, B25, B26, B27,
B30, B31, B32, B33, B34, B35, B36, B37,
B40, B41, B42, B43, B44, B45, B46, B47,
B50, B51, B52, B53, B54, B55, B56, B57,
B60, B61, B62, B63, B64, B65, B66, B67,
B70, B71, B72, B73, B74, B75, B76, B77,
input [0:511] A // input bit string (bit order left to right)
);
//---------combinational processes----------
assign B00 = A[0 : 7 ];
assign B01 = A[8 : 15 ];
assign B02 = A[16 : 23 ];
assign B03 = A[24 : 31 ];
assign B04 = A[32 : 39 ];
assign B05 = A[40 : 47 ];
assign B06 = A[48 : 55 ];
assign B07 = A[56 : 63 ];
assign B10 = A[64 : 71 ];
assign B11 = A[72 : 79 ];
assign B12 = A[80 : 87 ];
assign B13 = A[88 : 95 ];
assign B14 = A[96 : 103];
assign B15 = A[104 : 111];
assign B16 = A[112 : 119];
assign B17 = A[120 : 127];
assign B20 = A[128 : 135];
assign B21 = A[136 : 143];
assign B22 = A[144 : 151];
assign B23 = A[152 : 159];
assign B24 = A[160 : 167];
assign B25 = A[168 : 175];
assign B26 = A[176 : 183];
assign B27 = A[184 : 191];
assign B30 = A[192 : 199];
assign B31 = A[200 : 207];
assign B32 = A[208 : 215];
assign B33 = A[216 : 223];
assign B34 = A[224 : 231];
assign B35 = A[232 : 239];
assign B36 = A[240 : 247];
assign B37 = A[248 : 255];
assign B40 = A[256 : 263];
assign B41 = A[264 : 271];
assign B42 = A[272 : 279];
assign B43 = A[280 : 287];
assign B44 = A[288 : 295];
assign B45 = A[296 : 303];
assign B46 = A[304 : 311];
assign B47 = A[312 : 319];
assign B50 = A[320 : 327];
assign B51 = A[328 : 335];
assign B52 = A[336 : 343];
assign B53 = A[344 : 351];
assign B54 = A[352 : 359];
assign B55 = A[360 : 367];
assign B56 = A[368 : 375];
assign B57 = A[376 : 383];
assign B60 = A[384 : 391];
assign B61 = A[392 : 399];
assign B62 = A[400 : 407];
assign B63 = A[408 : 415];
assign B64 = A[416 : 423];
assign B65 = A[424 : 431];
assign B66 = A[432 : 439];
assign B67 = A[440 : 447];
assign B70 = A[448 : 455];
assign B71 = A[456 : 463];
assign B72 = A[464 : 471];
assign B73 = A[472 : 479];
assign B74 = A[480 : 487];
assign B75 = A[488 : 495];
assign B76 = A[496 : 503];
assign B77 = A[504 : 511];
endmodule |
// File: clock.v
// Generated by MyHDL 0.8.1
// Date: Sun May 15 22:24:35 2016
`timescale 500ms/1ms
module clock (
clk,
fast_clk,
rst,
en,
sec,
pm,
io_seg,
io_sel
);
input clk;
input fast_clk;
input rst;
input en;
output [7:0] sec;
reg [7:0] sec;
output [17:0] pm;
reg [17:0] pm;
output [7:0] io_seg;
wire [7:0] io_seg;
output [3:0] io_sel; // Digit select on IO Shield
wire [3:0] io_sel;
reg [3:0] count [0:6-1];
reg [1:0] i, j;
// CLOCK_DECODER 74LS247
assign io_seg[0] = (((count[i+2][0] && (!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3])) || ((!count[i+2][0]) && (!count[i+2][1]) && count[i+2][2]) || (count[i+2][1] && count[i+2][3])) != 0);
assign io_seg[1] = (((count[i+2][0] && (!count[i+2][1]) && count[i+2][2]) || ((!count[i+2][0]) && count[i+2][1] && count[i+2][2]) || (count[i+2][1] && count[i+2][3])) != 0);
assign io_seg[2] = ((((!count[i+2][0]) && count[i+2][1] && (!count[i+2][2])) || (count[i+2][2] && count[i+2][3])) != 0);
assign io_seg[3] = (((count[i+2][0] && (!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3])) || (count[i+2][0] && count[i+2][1] && count[i+2][2]) || ((!count[i+2][0]) && (!count[i+2][1]) && count[i+2][2])) != 0);
assign io_seg[4] = ((count[i+2][0] || ((!count[i+2][1]) && count[i+2][2])) != 0);
assign io_seg[5] = (((count[i+2][0] && (!count[i+2][2]) && (!count[i+2][3])) || (count[i+2][0] && count[i+2][1]) || (count[i+2][1] && (!count[i+2][2]))) != 0);
assign io_seg[6] = (((count[i+2][0] && count[i+2][1] && count[i+2][2]) || ((!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3]))) != 0);
assign io_seg[7] = 1'b1 && ~(~i[0] && i[1]);
// Select 7-segment display to show digit
assign io_sel[0] = ~(~i[0] && ~i[1]);
assign io_sel[1] = ~(i[0] && ~i[1]);
assign io_sel[2] = ~(~i[0] && i[1]);
assign io_sel[3] = ~(i[0] && i[1]) || (count[5] == 0);
always @(i) begin
j = i + 1'b1;
end
always @(posedge fast_clk, negedge fast_clk) begin
if (rst) begin
i <= 1'b0;
end else begin
i <= j;
end
end
always @(posedge clk, posedge rst) begin: CLOCK_COUNTER
if (rst) begin
count[0] <= 0;
count[1] <= 0;
count[2] <= 0;
count[3] <= 0;
count[4] <= 0;
end else if (en) begin
count[0] <= ((count[0] + 1) % 10);
count[1] <= ((count[1] + (count[0] == 9)) % 6);
count[2] <= ((count[2] + ((count[0] == 9) && (count[1] == 5))) % 10);
count[3] <= ((count[3] + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9))) % 6);
count[4] <= (((count[4] + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5))) % (10 - (7 * count[5]))) + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 2) && (count[5] != 0)));
end
end
always @(posedge clk, posedge rst) begin: CLOCK_TFF
if (rst) begin
count[5] <= 0;
pm <= 18'b0;
sec <= 8'b0;
end else if (en) begin
count[5] <= ((count[5] != 0) ^ (((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 9)) || ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 2) && (count[5] != 0))));
pm <= {18{(pm[0] ^ ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 1) && (count[5] != 0)))}};
sec <= (count[0]+10*count[1]+1) % 60;
end
end
endmodule |
#include <bits/stdc++.h> const long long MAX_N = 2e5 + 100; const long long MOD = 1e9 + 7; using namespace std; long long rm[MAX_N][20]; long long a[MAX_N]; map<int, int> last; long long ans; const long long c = (1ll << 50) - 1; long long ask(long long l, long long r) { long long len = r - l + 1; int lg = (int)log2(len); long long s = r - (1 << lg) + 1; return (rm[l][lg] | rm[s][lg]); } bool check(long long i, long long j) { j ^= c; if (j & i) return true; return false; } int main() { long long n; cin >> n; ans = n * (n + 1) / 2; for (int i = 1; i <= n; ++i) cin >> a[i], last[a[i]] = 0; for (int i = 1; i <= n; ++i) rm[i][0] = a[i]; for (int i = 1; i < 20; ++i) { for (int j = 1; j <= n - (1 << i) + 1; ++j) { rm[j][i] = rm[j][i - 1] | rm[j + (1 << (i - 1))][i - 1]; } } for (int i = 1; i <= n; ++i) { long long l1 = i; long long r1 = last[a[i]] + 1; long long l2 = i; long long r2 = n; if (!check(ask(r1, i), a[i])) l1 = r1; else { while (l1 - r1 > 1) { long long mid = (l1 + r1) / 2; if (!check(ask(mid, i), a[i])) l1 = mid; else r1 = mid; } } if (!check(ask(i, n), a[i])) l2 = n; else { while (r2 - l2 > 1) { long long mid = (l2 + r2) / 2; if (!check(ask(i, mid), a[i])) l2 = mid; else r2 = mid; } } ans -= (i - l1 + 1) * (l2 - i + 1); last[a[i]] = i; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long cnt = 0; int H; scanf( %d , &H); ; long long N; cin >> N; N--; long long n = 0; int d = 0; for (int h = (0); h < (H); h++) { long long msk = ((1LL) << (long long)(H - h - 1)); if (N & msk) { if (d & 1) cnt++; else { cnt += msk * 2LL; d++; } } else { if (d & 1) { cnt += msk * 2LL; d++; } else cnt++; } d++; } cout << cnt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100100], id[100100], t, Ans, ans[100100], n, i, vis[100100], j, k; int flag; vector<int> vec[100100]; bool cmp(int u, int v) { return a[u] < a[v]; } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); id[i] = i; } sort(id + 1, id + 1 + n, cmp); vec[1].push_back(1); if (n > 1) vec[1].push_back(n); vis[1] = vis[n] = vis[0] = vis[n + 1] = 1; ; j = 1; while (a[id[j]] == 1) { if (vis[id[j]] == 0) { vec[1].push_back(id[j]); vis[id[j]] = 1; } j++; } for (i = 2; i <= n; i++) { flag = 0; while (a[id[j]] == i) { if (vis[id[j]] == 0) { vec[i].push_back(id[j]); vis[id[j]] = 1; flag = 1; } j++; } for (k = 0; k < vec[i - 1].size(); k++) { t = vec[i - 1][k]; if (vis[t - 1] == 0) { vis[t - 1] = 1; vec[i].push_back(t - 1); flag = 1; } if (vis[t + 1] == 0) { vis[t + 1] = 1; vec[i].push_back(t + 1); flag = 1; } } if (!flag) break; } printf( %d n , i - 1); } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const int SINF = 0x7fffffff; const long long LINF = 0x3fffffffffffffff; const long long SLINF = 0x7fffffffffffffff; const long double DINF = pow(2, 100); const int MAXN = 100007; const long double EPS = 1e-17; const long double AEPS = 1e-7; const int TMS = 80; const long double MAX = 4e9; const long double PI = acos(-1.0); class ftT { public: void clear() { memset(data, 0, sizeof(data)); } void upd(int p, int x) { for (; p < MAXN; p += p & -p) data[p] += x; } int sum(int p) { int ans = 0; for (; p; p ^= p & -p) ans += data[p]; return ans; } int query(int l, int r) { return sum(r) - sum(l - 1); } private: int data[MAXN]; } ft; struct eT { void setd(long double _t, long double _r, int _tp, int _id) { t = _t, r = _r, tp = _tp, id = _id; } bool operator<(const eT &a) const { return ((((t - a.t) >= 0) ? (t - a.t) : (-(t - a.t))) > EPS) ? t < a.t : (tp ^ a.tp) ? (tp > a.tp) : (r < a.r); } long double t, r; int tp, id; } ev[MAXN]; int n, m; int ke; long double sx, sy; long double la[MAXN], lb[MAXN]; long double al[MAXN], ar[MAXN]; int pl[MAXN], pr[MAXN]; void init(); void input(); void work(); void precheck(long double tst); long long check(long double tst); long double getsum(long double cr); long double adj(long double ang); long double getdist(int i, int j); int main() { init(); input(); work(); } void init() { ios::sync_with_stdio(false); } void input() { scanf( %d , &n); int tx, ty; scanf( %d%d%d , &tx, &ty, &m), sx = static_cast<long double>(tx) / 1000, sy = static_cast<long double>(ty) / 1000; for (int i = 1; i <= n; ++i) scanf( %d%d , &tx, &ty), la[i] = static_cast<long double>(tx) / 1000, lb[i] = static_cast<long double>(ty) / 1000; } void work() { long double l = 0, r = MAX, mid; for (int _t = 0; _t < TMS; ++_t) { mid = l + (r - l) / 2; if (check(mid) >= m) r = mid; else l = mid; } long double maxd = l; while (check(l) >= m) l -= (((1) > (l)) ? (1) : (l)) * AEPS; int nc = check(l); cout << setprecision(13) << fixed << (getsum(l) + maxd * (m - nc)) << endl; } void precheck(long double tst) { long double sd, oa, da, a1, a2; for (int i = 1; i <= n; ++i) { sd = abs(la[i] * sx - sy + lb[i]) / sqrt(la[i] * la[i] + 1); if (sd > tst - EPS) al[i] = ar[i] = -DINF; else { if ((((la[i]) >= 0) ? (la[i]) : (-(la[i]))) < EPS) oa = PI / 2; else oa = atan(-1 / la[i]); if (oa < -EPS) oa += PI; if (la[i] * sx + lb[i] - sy < -EPS) oa += PI; da = acos(sd / tst); a1 = adj(oa + da), a2 = adj(oa - da); if (a1 > a2) swap(a1, a2); al[i] = a1, ar[i] = a2; } } ke = 0; for (int i = 1; i <= n; ++i) if (al[i] != -DINF) ev[++ke].setd(al[i], ar[i], 1, i), ev[++ke].setd(ar[i], ar[i], 0, i); sort(ev + 1, ev + 1 + ke); for (int i = 1; i <= ke; ++i) { if (ev[i].tp) pl[ev[i].id] = i; else pr[ev[i].id] = i; } } long long check(long double tst) { precheck(tst); long long ans = 0; int ni; ft.clear(); for (int i = 1; i <= ke; ++i) { if (ev[i].tp) { ni = ev[i].id; ans += ft.query(pl[ni], pr[ni]); ft.upd(pr[ni], 1); } } return ans; } long double getsum(long double cr) { precheck(cr); long double ans = 0; vector<pair<int, int> > ar; int ni, li; for (int i = 1; i <= ke; ++i) { if (ev[i].tp) { ni = ev[i].id; li = lower_bound(ar.begin(), ar.end(), make_pair(i, 0)) - ar.begin(); for (int j = li; j < ar.size() && ar[j].first <= pr[ni]; ++j) ans += getdist(ar[j].second, ni); ar.insert(upper_bound(ar.begin(), ar.end(), make_pair(pr[ni], INF)), make_pair(pr[ni], ni)); } } return ans; } long double adj(long double ang) { while (ang < -EPS) ang += 2 * PI; while (ang > 2 * PI - EPS) ang -= 2 * PI; return ang; } long double getdist(int i, int j) { long double x = (lb[i] - lb[j]) / (la[j] - la[i]); long double y = (la[j] * lb[i] - la[i] * lb[j]) / (la[j] - la[i]); return sqrt((x - sx) * (x - sx) + (y - sy) * (y - sy)); } |
// nios_tester_audio_in_dma.v
// This file was auto-generated from altera_msgdma_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module nios_tester_audio_in_dma (
output wire [25:0] mm_write_address, // mm_write.address
output wire mm_write_write, // .write
output wire [3:0] mm_write_byteenable, // .byteenable
output wire [31:0] mm_write_writedata, // .writedata
input wire mm_write_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_n_reset_n, // reset_n.reset_n
input wire [31:0] csr_writedata, // csr.writedata
input wire csr_write, // .write
input wire [3:0] csr_byteenable, // .byteenable
output wire [31:0] csr_readdata, // .readdata
input wire csr_read, // .read
input wire [2:0] csr_address, // .address
input wire descriptor_slave_write, // descriptor_slave.write
output wire descriptor_slave_waitrequest, // .waitrequest
input wire [127:0] descriptor_slave_writedata, // .writedata
input wire [15:0] descriptor_slave_byteenable, // .byteenable
output wire csr_irq_irq, // csr_irq.irq
input wire [31:0] st_sink_data, // st_sink.data
input wire st_sink_valid, // .valid
output wire st_sink_ready // .ready
);
wire dispatcher_internal_write_command_source_valid; // dispatcher_internal:src_write_master_valid -> write_mstr_internal:snk_command_valid
wire [255:0] dispatcher_internal_write_command_source_data; // dispatcher_internal:src_write_master_data -> write_mstr_internal:snk_command_data
wire dispatcher_internal_write_command_source_ready; // write_mstr_internal:snk_command_ready -> dispatcher_internal:src_write_master_ready
wire write_mstr_internal_response_source_valid; // write_mstr_internal:src_response_valid -> dispatcher_internal:snk_write_master_valid
wire [255:0] write_mstr_internal_response_source_data; // write_mstr_internal:src_response_data -> dispatcher_internal:snk_write_master_data
wire write_mstr_internal_response_source_ready; // dispatcher_internal:snk_write_master_ready -> write_mstr_internal:src_response_ready
dispatcher #(
.MODE (2),
.RESPONSE_PORT (2),
.DESCRIPTOR_INTERFACE (0),
.DESCRIPTOR_FIFO_DEPTH (8),
.ENHANCED_FEATURES (0),
.DESCRIPTOR_WIDTH (128),
.DESCRIPTOR_BYTEENABLE_WIDTH (16)
) dispatcher_internal (
.clk (clock_clk), // clock.clk
.reset (~reset_n_reset_n), // clock_reset.reset
.csr_writedata (csr_writedata), // CSR.writedata
.csr_write (csr_write), // .write
.csr_byteenable (csr_byteenable), // .byteenable
.csr_readdata (csr_readdata), // .readdata
.csr_read (csr_read), // .read
.csr_address (csr_address), // .address
.descriptor_write (descriptor_slave_write), // Descriptor_Slave.write
.descriptor_waitrequest (descriptor_slave_waitrequest), // .waitrequest
.descriptor_writedata (descriptor_slave_writedata), // .writedata
.descriptor_byteenable (descriptor_slave_byteenable), // .byteenable
.src_write_master_data (dispatcher_internal_write_command_source_data), // Write_Command_Source.data
.src_write_master_valid (dispatcher_internal_write_command_source_valid), // .valid
.src_write_master_ready (dispatcher_internal_write_command_source_ready), // .ready
.snk_write_master_data (write_mstr_internal_response_source_data), // Write_Response_Sink.data
.snk_write_master_valid (write_mstr_internal_response_source_valid), // .valid
.snk_write_master_ready (write_mstr_internal_response_source_ready), // .ready
.csr_irq (csr_irq_irq), // csr_irq.irq
.src_response_data (), // (terminated)
.src_response_valid (), // (terminated)
.src_response_ready (1'b0), // (terminated)
.snk_descriptor_data (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_descriptor_valid (1'b0), // (terminated)
.snk_descriptor_ready (), // (terminated)
.mm_response_waitrequest (), // (terminated)
.mm_response_byteenable (4'b0000), // (terminated)
.mm_response_address (1'b0), // (terminated)
.mm_response_readdata (), // (terminated)
.mm_response_read (1'b0), // (terminated)
.src_read_master_data (), // (terminated)
.src_read_master_valid (), // (terminated)
.src_read_master_ready (1'b0), // (terminated)
.snk_read_master_data (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_read_master_valid (1'b0), // (terminated)
.snk_read_master_ready () // (terminated)
);
write_master #(
.DATA_WIDTH (32),
.LENGTH_WIDTH (21),
.FIFO_DEPTH (256),
.STRIDE_ENABLE (0),
.BURST_ENABLE (0),
.PACKET_ENABLE (0),
.ERROR_ENABLE (0),
.ERROR_WIDTH (8),
.BYTE_ENABLE_WIDTH (4),
.BYTE_ENABLE_WIDTH_LOG2 (2),
.ADDRESS_WIDTH (26),
.FIFO_DEPTH_LOG2 (8),
.SYMBOL_WIDTH (8),
.NUMBER_OF_SYMBOLS (4),
.NUMBER_OF_SYMBOLS_LOG2 (2),
.MAX_BURST_COUNT_WIDTH (1),
.UNALIGNED_ACCESSES_ENABLE (0),
.ONLY_FULL_ACCESS_ENABLE (1),
.BURST_WRAPPING_SUPPORT (0),
.PROGRAMMABLE_BURST_ENABLE (0),
.MAX_BURST_COUNT (1),
.FIFO_SPEED_OPTIMIZATION (1),
.STRIDE_WIDTH (1),
.ACTUAL_BYTES_TRANSFERRED_WIDTH (32)
) write_mstr_internal (
.clk (clock_clk), // Clock.clk
.reset (~reset_n_reset_n), // Clock_reset.reset
.master_address (mm_write_address), // Data_Write_Master.address
.master_write (mm_write_write), // .write
.master_byteenable (mm_write_byteenable), // .byteenable
.master_writedata (mm_write_writedata), // .writedata
.master_waitrequest (mm_write_waitrequest), // .waitrequest
.snk_data (st_sink_data), // Data_Sink.data
.snk_valid (st_sink_valid), // .valid
.snk_ready (st_sink_ready), // .ready
.snk_command_data (dispatcher_internal_write_command_source_data), // Command_Sink.data
.snk_command_valid (dispatcher_internal_write_command_source_valid), // .valid
.snk_command_ready (dispatcher_internal_write_command_source_ready), // .ready
.src_response_data (write_mstr_internal_response_source_data), // Response_Source.data
.src_response_valid (write_mstr_internal_response_source_valid), // .valid
.src_response_ready (write_mstr_internal_response_source_ready), // .ready
.master_burstcount (), // (terminated)
.snk_sop (1'b0), // (terminated)
.snk_eop (1'b0), // (terminated)
.snk_empty (2'b00), // (terminated)
.snk_error (8'b00000000) // (terminated)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; string sol; const int kBufferSize = 10000; int BufferInd = kBufferSize; char Buffer[kBufferSize]; void cit(int &n) { ((++BufferInd >= kBufferSize) ? (cin.read(Buffer, kBufferSize), BufferInd = 0) : (0)); for (; not((((Buffer[BufferInd]) >= 0 and (Buffer[BufferInd]) <= 9 ) or (Buffer[BufferInd]) == - ) ? (1) : (0)); ((++BufferInd >= kBufferSize) ? (cin.read(Buffer, kBufferSize), BufferInd = 0) : (0))) ; bool sign = false; if ((Buffer[BufferInd]) == - ) { ((++BufferInd >= kBufferSize) ? (cin.read(Buffer, kBufferSize), BufferInd = 0) : (0)); sign = true; } n = 0; for (; ((((Buffer[BufferInd]) >= 0 and (Buffer[BufferInd]) <= 9 ) or (Buffer[BufferInd]) == - ) ? (1) : (0)); ((++BufferInd >= kBufferSize) ? (cin.read(Buffer, kBufferSize), BufferInd = 0) : (0))) { n *= 10; n += (Buffer[BufferInd]) - 0 ; } if (sign) n *= -1; } int main() { std::ios_base::sync_with_stdio(false); int n, sum = 0; cin >> n; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) { int x; cin >> x; if (i == j) sum ^= x; } int q; cin >> q; while (q--) { int t; cin >> t; if (t == 1 or t == 2) { int x; cin >> x; sum ^= 1; } else { sol += 0 + sum; } } cout << sol << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
/**
* A Galois Linear Feedback Shift Register, uses the time to
* finish calibration as the seed and then generates 16-bit
* pseudo-random numbers. Re-seeds on user input for additional
* randomness.
*
* More info: https://en.wikipedia.org/wiki/LFSR#Galois_LFSRs
*
* @author Robert Fotino, 2016
*/
`include "definitions.vh"
module galois_lfsr
(
input clk,
input calib_done,
input [`NUM_USER_INPUTS-1:0] buf_inputs,
output reg [`WORD_BITS-1:0] rnd
);
initial begin
// Input to LFSR can't be 0
rnd = 1;
end
reg [`WORD_BITS-1:0] counter = 0;
reg [`NUM_USER_INPUTS-1:0] prev_inputs = 0;
reg prev_calib_done = 0;
always @ (posedge clk) begin
counter <= counter + 1;
prev_calib_done <= calib_done;
prev_inputs <= buf_inputs;
if ((calib_done && !prev_calib_done)
|| buf_inputs != prev_inputs) begin
// Seed output by XORing with counter
rnd <= rnd ^ counter;
counter <= 0;
end else begin
// Increment LFSR
rnd[`WORD_BITS-1] <= rnd[0];
rnd[`WORD_BITS-2] <= rnd[`WORD_BITS-1];
rnd[`WORD_BITS-3] <= rnd[`WORD_BITS-2] ^ rnd[0];
rnd[`WORD_BITS-4] <= rnd[`WORD_BITS-3] ^ rnd[0];
rnd[`WORD_BITS-5] <= rnd[`WORD_BITS-4];
rnd[`WORD_BITS-6] <= rnd[`WORD_BITS-5] ^ rnd[0];
rnd[`WORD_BITS-7:0] <= rnd[`WORD_BITS-6:1];
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N; string S; long long sol; long long dim; long long e; long long last() { long long d = 1ll; long long n = 0ll; long long sz = (long long)(S.size()); int zero = 0; for (long long i = sz - 1; i >= sz - dim && i >= 0 && n < N; i--) { if (d * (long long)(S[i] - 0 ) + n < N) { if (S[i] == 0 ) zero++; else zero = 0; n += d * (long long)(S[i] - 0 ), d *= 10ll, S.pop_back(); } } if (n == 0) zero--; while (zero > 0) S.push_back( 0 ), zero--; return n; } int main() { cin >> N >> S; long long c = N; while (c) c /= 10, dim++; e = 1ll; while (!S.empty()) { sol += e * last(); e *= N; } cout << sol; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_PP_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); int a1 = abs(a - c) * 2; int b1 = abs(b - d) * 2; int ans = a1 + b1 + 4; if (a != c && b != d) printf( %d n , ans); else printf( %d n , ans + 2); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_dmul_64ns_64ns_64_6_max_dsp
#(parameter
ID = 13,
NUM_STAGE = 6,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
HLS_accel_ap_dmul_4_max_dsp_64 HLS_accel_ap_dmul_4_max_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_dmask_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_dmask_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_dmask_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_dmask_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_connecting (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const static int INF = 1000000000; int t; string input; map<string, string> apa; int main() { scanf( %d , &t); string a, b; string v = void ; apa[v] = void ; while (t--) { cin >> input; if (input == typedef ) { cin >> a >> b; string tipe = ; int bintang = 0, dan = 0; for (int i = 0; a[i] != 0 ; i++) { if (a[i] == * ) bintang++; else if (a[i] == & ) dan++; else tipe += a[i]; } string bener = apa[tipe]; if (bener == errtype || tipe == errtype ) { apa[b] = errtype ; continue; } if (bintang >= dan) { for (int i = 0; i < bintang - dan; i++) { bener += * ; } apa[b] = bener; } else if (dan > bintang) { string ganti = ; dan = dan - bintang; for (int i = 0; bener[i] != 0 ; i++) { if (bener[i] == * ) { if (dan > 0) dan--; else { ganti += * ; } } else ganti += bener[i]; } if (dan == 0) apa[b] = ganti; else apa[b] = errtype ; } } else { cin >> a; string tipe = ; int bintang = 0, dan = 0; for (int i = 0; a[i] != 0 ; i++) { if (a[i] == * ) bintang++; else if (a[i] == & ) dan++; else tipe += a[i]; } string bener = apa[tipe]; if (bener == errtype || bener == ) { printf( errtype n ); continue; } if (bintang >= dan) { for (int i = 0; i < bintang - dan; i++) { bener += * ; } printf( %s n , bener.c_str()); } else if (dan > bintang) { string ganti = ; dan = dan - bintang; for (int i = 0; bener[i] != 0 ; i++) { if (bener[i] == * ) { if (dan > 0) dan--; else { ganti += * ; } } else ganti += bener[i]; } if (dan == 0) printf( %s n , ganti.c_str()); else printf( errtype n ); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long double PI = 3.1415926535898; const long long LLMAX = LLONG_MAX; int a[(int)2e5 + 5], b[(int)2e5 + 5], c[(int)2e5 + 5]; int n; vector<vector<int> > v((int)2e5 + 5); int type10 = 0; int type01 = 0; long long ans = 0; int one[(int)2e5 + 5] = {0}; int zero[(int)2e5 + 5] = {0}; void solve(int parent, int node) { if (b[node] != c[node]) { if (b[node]) one[node]++; else zero[node]++; } if (parent) a[node] = min(a[node], a[parent]); for (int i = 0; i < v[node].size(); i++) { if (v[node][i] == parent) continue; else { solve(node, v[node][i]); one[node] += one[v[node][i]]; zero[node] += zero[v[node][i]]; } } int dec = min(one[node], zero[node]); one[node] -= dec; zero[node] -= dec; ans += (long long)a[node] * 2 * dec; } int main() { int x, y; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i] >> b[i] >> c[i]; if (b[i] == 0 && c[i] == 1) type01++; else if (b[i] == 1 && c[i] == 0) type10++; } for (int i = 1; i < n; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } solve(0, 1); if (type01 != type10) { cout << -1 << n ; } else { cout << ans << n ; } } |
`timescale 1ns/1ns
`define SR 5'd12
`define CAUSE 5'd13
`define EPC 5'd14
`define PRID 5'd15
//ExcCode Values
`define EC_INT 5'b00000
module cp0 (input clk,
input rst,
input [4:0] a1,
input [4:0] a2,
input [31:0] din,
input [31:0] pc,
input [6:2] ExcCode,
input [5:0] HWInt,
input we,
input EXLSet,
input EXLClr,
output IntReq,
output [31:0] EPC,
output [31:0] dout
);
reg [15:10] im;
reg exl,ie;
reg [15:10] hwint_pend;
reg [31:0] _epc;
reg [31:0] PrId;
reg [6:2] _exccode;
always @(posedge clk or posedge rst) begin
if (rst) begin
ie<=1;
im<=6'b110000;
exl<=0;
hwint_pend<=0;
PrId<=32'h12345678;
end // if(rst)
else begin
hwint_pend<=HWInt;
if (IntReq) begin
_exccode<=ExcCode;
_epc<=pc-4;
exl<=1'b1;
end // if(Int)
else if (we) begin
//SR
if (a2==`SR) begin
{im,exl,ie}<={din[15:10],EXLClr?1'b1:din[1],din[0]};
end
else if (a2==`EPC) begin
_epc<=pc;
end
else if (EXLSet) begin
exl<=1'b1;
end // if(EXLSet)
else if (EXLClr) begin
exl<=1'b0;
end
end // if(we)
else if (EXLSet) begin
exl<=1'b1;
end // if(EXLSet)
else if (EXLClr) begin
exl<=1'b0;
end // if(EXLClr)
end
end
assign dout=(a1==`SR)?{16'b0,im,8'b0,exl,ie}:
(a1==`CAUSE)?{16'b0,hwint_pend,3'b0,_exccode,2'b00}:
(a1==`EPC)?_epc:
(a1==`PRID)?PrId:
32'h0000_0000;
assign EPC=_epc;
assign IntReq=ie&&(!exl)&&(hwint_pend[15:10]&im[15:10]);
endmodule // cp0
|
#include <bits/stdc++.h> using namespace std; long long fact[200010], cnt, cnt1[200010], cnt2[200010]; void precalc() { fact[0] = 1; for (int i = 1; i < 200010; i++) { fact[i] = (i * fact[i - 1]) % 1000000007; } } long long power(long long a, long long b, long long p) { if (b == 0) return 1; long long ret = power(a, b / 2, p); ret = (ret * ret) % p; if ((b % 2) == 1) ret = (ret * a) % p; return ret % p; } long long ncr(long long n, long long r) { if (n < r) { return 0; } long long ans = fact[n]; long long den = (fact[n - r] * fact[r]) % 1000000007; ans = (ans * power(den, 1000000007 - 2, 1000000007)) % 1000000007; return ans; } int main() { precalc(); string str; cin >> str; long long n = str.length(); cnt = 0; long long ans = 0; for (int i = 0; i < n; i++) { if (str[i] == ( ) { cnt++; } cnt1[i] = cnt; } cnt = 0; for (int i = n - 1; i >= 0; i--) { if (str[i] == ) ) { cnt++; } cnt2[i] = cnt; } for (int i = 0; i < n; i++) { if (str[i] == ( ) { long long x = cnt1[i]; long long y = cnt2[i]; ans = (ans + ncr(x + y - 1, x)) % 1000000007; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 25, INF = 1e9 + 5; inline int read() { char c = getchar(); int x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } int n, m, a[N][N]; bool check() { for (int i = 1; i <= n; i++) { int cnt = 0; for (int j = 1; j <= m; j++) if (a[i][j] != j) cnt++; if (cnt > 2) return false; } return true; } int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) a[i][j] = read(); if (check()) { puts( YES ); return 0; } for (int i = 1; i <= m; i++) for (int j = i + 1; j <= m; j++) { for (int z = 1; z <= n; z++) swap(a[z][i], a[z][j]); if (check()) { puts( YES ); return 0; } for (int z = 1; z <= n; z++) swap(a[z][i], a[z][j]); } puts( NO ); } |
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// m_near_mem_io_addr_base O 64 const
// m_near_mem_io_addr_size O 64 const
// m_near_mem_io_addr_lim O 64 const
// m_plic_addr_base O 64 const
// m_plic_addr_size O 64 const
// m_plic_addr_lim O 64 const
// m_uart0_addr_base O 64 const
// m_uart0_addr_size O 64 const
// m_uart0_addr_lim O 64 const
// m_boot_rom_addr_base O 64 const
// m_boot_rom_addr_size O 64 const
// m_boot_rom_addr_lim O 64 const
// m_mem0_controller_addr_base O 64 const
// m_mem0_controller_addr_size O 64 const
// m_mem0_controller_addr_lim O 64 const
// m_tcm_addr_base O 64 const
// m_tcm_addr_size O 64 const
// m_tcm_addr_lim O 64 const
// m_is_mem_addr O 1
// m_is_IO_addr O 1
// m_is_near_mem_IO_addr O 1
// m_pc_reset_value O 64 const
// m_mtvec_reset_value O 64 const
// m_nmivec_reset_value O 64 const
// CLK I 1 unused
// RST_N I 1 unused
// m_is_mem_addr_addr I 64
// m_is_IO_addr_addr I 64
// m_is_near_mem_IO_addr_addr I 64
//
// Combinational paths from inputs to outputs:
// m_is_mem_addr_addr -> m_is_mem_addr
// m_is_IO_addr_addr -> m_is_IO_addr
// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSoC_Map(CLK,
RST_N,
m_near_mem_io_addr_base,
m_near_mem_io_addr_size,
m_near_mem_io_addr_lim,
m_plic_addr_base,
m_plic_addr_size,
m_plic_addr_lim,
m_uart0_addr_base,
m_uart0_addr_size,
m_uart0_addr_lim,
m_boot_rom_addr_base,
m_boot_rom_addr_size,
m_boot_rom_addr_lim,
m_mem0_controller_addr_base,
m_mem0_controller_addr_size,
m_mem0_controller_addr_lim,
m_tcm_addr_base,
m_tcm_addr_size,
m_tcm_addr_lim,
m_is_mem_addr_addr,
m_is_mem_addr,
m_is_IO_addr_addr,
m_is_IO_addr,
m_is_near_mem_IO_addr_addr,
m_is_near_mem_IO_addr,
m_pc_reset_value,
m_mtvec_reset_value,
m_nmivec_reset_value);
input CLK;
input RST_N;
// value method m_near_mem_io_addr_base
output [63 : 0] m_near_mem_io_addr_base;
// value method m_near_mem_io_addr_size
output [63 : 0] m_near_mem_io_addr_size;
// value method m_near_mem_io_addr_lim
output [63 : 0] m_near_mem_io_addr_lim;
// value method m_plic_addr_base
output [63 : 0] m_plic_addr_base;
// value method m_plic_addr_size
output [63 : 0] m_plic_addr_size;
// value method m_plic_addr_lim
output [63 : 0] m_plic_addr_lim;
// value method m_uart0_addr_base
output [63 : 0] m_uart0_addr_base;
// value method m_uart0_addr_size
output [63 : 0] m_uart0_addr_size;
// value method m_uart0_addr_lim
output [63 : 0] m_uart0_addr_lim;
// value method m_boot_rom_addr_base
output [63 : 0] m_boot_rom_addr_base;
// value method m_boot_rom_addr_size
output [63 : 0] m_boot_rom_addr_size;
// value method m_boot_rom_addr_lim
output [63 : 0] m_boot_rom_addr_lim;
// value method m_mem0_controller_addr_base
output [63 : 0] m_mem0_controller_addr_base;
// value method m_mem0_controller_addr_size
output [63 : 0] m_mem0_controller_addr_size;
// value method m_mem0_controller_addr_lim
output [63 : 0] m_mem0_controller_addr_lim;
// value method m_tcm_addr_base
output [63 : 0] m_tcm_addr_base;
// value method m_tcm_addr_size
output [63 : 0] m_tcm_addr_size;
// value method m_tcm_addr_lim
output [63 : 0] m_tcm_addr_lim;
// value method m_is_mem_addr
input [63 : 0] m_is_mem_addr_addr;
output m_is_mem_addr;
// value method m_is_IO_addr
input [63 : 0] m_is_IO_addr_addr;
output m_is_IO_addr;
// value method m_is_near_mem_IO_addr
input [63 : 0] m_is_near_mem_IO_addr_addr;
output m_is_near_mem_IO_addr;
// value method m_pc_reset_value
output [63 : 0] m_pc_reset_value;
// value method m_mtvec_reset_value
output [63 : 0] m_mtvec_reset_value;
// value method m_nmivec_reset_value
output [63 : 0] m_nmivec_reset_value;
// signals for module outputs
wire [63 : 0] m_boot_rom_addr_base,
m_boot_rom_addr_lim,
m_boot_rom_addr_size,
m_mem0_controller_addr_base,
m_mem0_controller_addr_lim,
m_mem0_controller_addr_size,
m_mtvec_reset_value,
m_near_mem_io_addr_base,
m_near_mem_io_addr_lim,
m_near_mem_io_addr_size,
m_nmivec_reset_value,
m_pc_reset_value,
m_plic_addr_base,
m_plic_addr_lim,
m_plic_addr_size,
m_tcm_addr_base,
m_tcm_addr_lim,
m_tcm_addr_size,
m_uart0_addr_base,
m_uart0_addr_lim,
m_uart0_addr_size;
wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr;
// value method m_near_mem_io_addr_base
assign m_near_mem_io_addr_base = 64'h0000000002000000 ;
// value method m_near_mem_io_addr_size
assign m_near_mem_io_addr_size = 64'h000000000000C000 ;
// value method m_near_mem_io_addr_lim
assign m_near_mem_io_addr_lim = 64'd33603584 ;
// value method m_plic_addr_base
assign m_plic_addr_base = 64'h000000000C000000 ;
// value method m_plic_addr_size
assign m_plic_addr_size = 64'h0000000000400000 ;
// value method m_plic_addr_lim
assign m_plic_addr_lim = 64'd205520896 ;
// value method m_uart0_addr_base
assign m_uart0_addr_base = 64'h00000000C0000000 ;
// value method m_uart0_addr_size
assign m_uart0_addr_size = 64'h0000000000000080 ;
// value method m_uart0_addr_lim
assign m_uart0_addr_lim = 64'h00000000C0000080 ;
// value method m_boot_rom_addr_base
assign m_boot_rom_addr_base = 64'h0000000000001000 ;
// value method m_boot_rom_addr_size
assign m_boot_rom_addr_size = 64'h0000000000001000 ;
// value method m_boot_rom_addr_lim
assign m_boot_rom_addr_lim = 64'd8192 ;
// value method m_mem0_controller_addr_base
assign m_mem0_controller_addr_base = 64'h0000000080000000 ;
// value method m_mem0_controller_addr_size
assign m_mem0_controller_addr_size = 64'h0000000010000000 ;
// value method m_mem0_controller_addr_lim
assign m_mem0_controller_addr_lim = 64'h0000000090000000 ;
// value method m_tcm_addr_base
assign m_tcm_addr_base = 64'h0 ;
// value method m_tcm_addr_size
assign m_tcm_addr_size = 64'd0 ;
// value method m_tcm_addr_lim
assign m_tcm_addr_lim = 64'd0 ;
// value method m_is_mem_addr
assign m_is_mem_addr =
m_is_mem_addr_addr >= 64'h0000000000001000 &&
m_is_mem_addr_addr < 64'd8192 ||
m_is_mem_addr_addr >= 64'h0000000080000000 &&
m_is_mem_addr_addr < 64'h0000000090000000 ;
// value method m_is_IO_addr
assign m_is_IO_addr =
m_is_IO_addr_addr >= 64'h0000000002000000 &&
m_is_IO_addr_addr < 64'd33603584 ||
m_is_IO_addr_addr >= 64'h000000000C000000 &&
m_is_IO_addr_addr < 64'd205520896 ||
m_is_IO_addr_addr >= 64'h00000000C0000000 &&
m_is_IO_addr_addr < 64'h00000000C0000080 ;
// value method m_is_near_mem_IO_addr
assign m_is_near_mem_IO_addr =
m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 &&
m_is_near_mem_IO_addr_addr < 64'd33603584 ;
// value method m_pc_reset_value
assign m_pc_reset_value = 64'h0000000000001000 ;
// value method m_mtvec_reset_value
assign m_mtvec_reset_value = 64'h0000000000001000 ;
// value method m_nmivec_reset_value
assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ;
endmodule // mkSoC_Map
|
#include <bits/stdc++.h> using namespace std; pair<int, int> Castle[100010]; int Index[100010]; int main() { int N; scanf( %d , &N); int Temp; for (int i = 1; i <= N; i++) { scanf( %d , &Temp); Castle[i] = make_pair(Temp, i); } sort(Castle + 1, Castle + N + 1); int Max = 1; int Ans = 0; for (int i = 1; i <= N; i++) Index[Castle[i].second] = i; for (int i = 1; i <= N; i++) { Max = max(Max, Index[i]); if (Max == i) Ans++; } printf( %d n , Ans); return 0; } |
///////////////////////////////////////////////////////////////
// sha1_round.v version 0.1
//
// Primitive SHA1 Round
//
// Described in Stalling, page 284
//
// Paul Hartke, , Copyright (c)2002
//
// The information and description contained herein is the
// property of Paul Hartke.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// This code is made available "as is". There is no warranty,
// so use it at your own risk.
// Documentation? "Use the source, Luke!"
///////////////////////////////////////////////////////////////
module sha1_round (cv_in, w, round, cv_out);
input [159:0] cv_in;
input [31:0] w;
input [6:0] round;
output [159:0] cv_out;
reg [31:0] k;
reg [31:0] f;
wire [31:0] a_shift;
wire [31:0] b_shift;
wire [31:0] add_result;
wire [31:0] a = cv_in[159:128];
wire [31:0] b = cv_in[127:96];
wire [31:0] c = cv_in[95:64];
wire [31:0] d = cv_in[63:32];
wire [31:0] e = cv_in[31:0];
// Perhaps this should be a case statement?
// I want it to create 4 parallel comparators...
always @(round)
begin
k = 32'd0;
if ((round >= 7'd0) && (round <= 7'd19))
k = 32'h5A827999;
if ((round >= 7'd20) && (round <= 7'd39))
k = 32'h6ED9EBA1;
if ((round >= 7'd40) && (round <= 7'd59))
k = 32'h8F1BBCDC;
if ((round >= 7'd60) && (round <= 7'd79))
k = 32'hCA62C1D6;
end // always @ (round)
// Perhaps this should be a case statement?
// I want it to create 4 parallel comparators...
always @(round or b or c or d)
begin
f = 32'd0;
if ((round >= 7'd0) && (round <= 7'd19))
f = ((b & c) | (~b & d));
if ((round >= 7'd20) && (round <= 7'd39))
f = (b ^ c ^ d);
if ((round >= 7'd40) && (round <= 7'd59))
f = ((b & c) | (b & d) | (c & d));
if ((round >= 7'd60) && (round <= 7'd79))
f = (b ^ c ^ d);
end // always @ (round or b or c or d)
assign a_shift = {a[26:0], a[31:27]};
assign b_shift = {b[1:0], b[31:2]};
// Attempt to group early signals early...
// e and w come from register outputs
// k is 6 bit comparator & mux delay
// f is 6 bit comparator & mux delay & computation
// a is shift 5 from previous round
assign add_result = (a_shift + ((f + k) + (e + w)));
assign cv_out = {add_result, a, b_shift, c, d};
endmodule // sha1_round
|
#include <bits/stdc++.h> using namespace std; const int INF = (1 << 30); const double eps = 1e-9; const int mod = 1000000007; const int MAXN = int(1e5) + 100; const int dx[] = {-1, +1, 0, 0}; const int dy[] = {0, 0, -1, +1}; int main() { ios::sync_with_stdio(false); int n; cin >> n; vector<int> arr(n); for (int i = (0); i < int(n); ++i) { cin >> arr[i]; } sort((arr).begin(), (arr).end()); for (int i = (1); i < int(n); ++i) { int x = arr[i - 1]; int y = arr[i]; if (x == y) continue; if (y < x * 2) { cout << YES << endl; return 0; } } cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int pos[11][1111]; int gra[1111][1111]; int main() { int n, m; cin >> n >> m; int x; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cin >> x; pos[i][x - 1] = j; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { int flag = 1; for (int k = 0; k < m; k++) { flag &= (pos[k][i] < pos[k][j]); } if (flag == true) gra[i][j] = 1; else gra[i][j] = -INF; } } for (int k = 0; k < n; k++) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { gra[i][j] = max(gra[i][j], gra[i][k] + gra[k][j]); } } } int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { ans = max(ans, gra[i][j]); } } cout << ans + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { { ios_base::sync_with_stdio(false); cin.tie(0); }; int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<int> matching; vector<int> vis(3 * n + 1, 0); for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; if (!vis[u] and !vis[v]) { matching.push_back(i); vis[u] = vis[v] = 1; } } if (matching.size() >= n) { cout << Matching << endl; for (int i = 0; i < n; i++) cout << matching[i] << ; cout << endl; } else { cout << IndSet << endl; int seen = 0; for (int i = 1; i <= 3 * n and seen < n; i++) { if (!vis[i]) { cout << i << ; seen++; } } cout << endl; } } } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; string s; cin >> s; for (long long i = 1; i <= n; i++) if (!(n % i)) reverse(s.begin(), (s.begin() + i)); cout << s << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char my_array[50][50]; bool visited[50][50]; bool dfs(int i, int j, int c_i, int c_j) { if (visited[i][j]) { return true; } visited[i][j] = true; char col = my_array[i][j]; bool res = false; if (i > 0 && col == my_array[i - 1][j] && c_i != i - 1) { res |= dfs(i - 1, j, i, j); } if (j > 0 && col == my_array[i][j - 1] && c_j != j - 1) { res |= dfs(i, j - 1, i, j); } if (i < n - 1 && col == my_array[i + 1][j] && c_i != i + 1) { res |= dfs(i + 1, j, i, j); } if (j < m - 1 && col == my_array[i][j + 1] && c_j != j + 1) { res |= dfs(i, j + 1, i, j); } return res; } int main(int argc, const char* argv[]) { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> my_array[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (!visited[i][j] && dfs(i, j, -1, -1)) { cout << Yes ; return 0; } } } cout << No ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 3e5; int a[MAX] = {}; int main() { int t; cin >> t; while (t--) { char c; long long s; cin >> c >> s; long long a1 = 0; for (int i = 0; i < 18; i++) { a1 = a1 * 2 + s % 2; s /= 10; } if (c == + ) { a[a1]++; } else if (c == - ) { a[a1]--; } else { cout << a[a1] << n ; } } return 0; } |
`timescale 1ns/1ns
module spi_master
#(parameter SCLK_DIV = 8'd8,
parameter W = 8)
(input c, output busy, output done,
input [W-1:0] txd, input txdv,
output [W-1:0] rxd, output rxdv,
output sclk, output mosi, input miso, output cs);
assign rxd = 8'h0;
assign rxdv = 1'b0;
wire [W-1:0] txd_d1;
d1 #(8) txd_d1_r(.c(c), .d(txd), .q(txd_d1));
wire txdv_d1;
d1 txdv_d1_r(.c(c), .d(txdv), .q(txdv_d1));
wire txe = txdv_d1 & ~txdv;
wire [7:0] sclk_cnt;
wire sclk_match = sclk_cnt == SCLK_DIV-1;
r #(8) sclk_cnt_r
(.c(c), .en(1'b1), .rst(sclk_match), .d(sclk_cnt+1'b1), .q(sclk_cnt));
wire sclk_int;
r sclk_int_r(.c(c), .en(sclk_match), .rst(1'b0),
.d(~sclk_int), .q(sclk_int));
wire sclk_rising = ~sclk_int & sclk_match;
wire sclk_falling = sclk_int & sclk_match;
localparam SW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_ASSERT_CS = 3'd1;
localparam ST_WAIT_BEFORE_DATA = 3'd2;
localparam ST_READ_DATA = 3'd3;
localparam ST_TX_WORD = 3'd4;
localparam ST_POST_DATA = 3'd5;
localparam ST_DONE = 3'd6;
localparam CW = 4;
reg [SW+CW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_reg
(.c(c), .d(next_state), .rst(1'b0), .en(1'b1), .q(state));
wire dfifo_rdreq, dfifo_empty;
wire [8:0] dfifo_q;
wire [7:0] dfifo_usedw;
scfifo #(.lpm_width(9),
.lpm_numwords(256),
.lpm_widthu(8),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) dfifo // data fifo
(.clock(c),
.wrreq(txdv_d1), .data({txe, txd_d1}),
.rdreq(dfifo_rdreq), .q(dfifo_q),
.empty(dfifo_empty), .usedw(dfifo_usedw), .aclr(1'b0), .sclr(1'b0));
assign cs = ~ctrl[0];
localparam BIT_CNT_W = 8;
wire [BIT_CNT_W-1:0] bit_cnt;
wire bit_cnt_rst, bit_cnt_en;
r #(BIT_CNT_W) bit_cnt_r
(.c(c), .rst(bit_cnt_rst), .en(bit_cnt_en), .d(bit_cnt + 1'b1), .q(bit_cnt));
assign bit_cnt_rst = state == ST_READ_DATA | state == ST_ASSERT_CS;
assign bit_cnt_en = (state == ST_TX_WORD & sclk_rising) |
(state == ST_WAIT_BEFORE_DATA & sclk_rising);
wire last_byte;
r last_byte_r
(.c(c), .rst(state == ST_IDLE), .en(state == ST_READ_DATA),
.d(dfifo_q[8]), .q(last_byte));
assign dfifo_rdreq = state == ST_READ_DATA;
always @* begin
case (state)
ST_IDLE:
if (~dfifo_empty & sclk_rising) ctrl = { ST_ASSERT_CS , 4'b0001 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_ASSERT_CS:
if (sclk_falling) ctrl = { ST_WAIT_BEFORE_DATA, 4'b0001 };
else ctrl = { ST_ASSERT_CS , 4'b0001 };
ST_WAIT_BEFORE_DATA:
if (sclk_falling & bit_cnt == 8'h7)
ctrl = { ST_READ_DATA , 4'b0001 };
else ctrl = { ST_WAIT_BEFORE_DATA, 4'b0001};
ST_READ_DATA: ctrl = { ST_TX_WORD , 4'b0011 };
ST_TX_WORD:
if (sclk_falling & bit_cnt == 8'h8)
if (last_byte | dfifo_empty) ctrl = { ST_DONE , 4'b0011 };
else ctrl = { ST_READ_DATA , 4'b0011 };
else ctrl = { ST_TX_WORD , 4'b0011 };
ST_POST_DATA:
if (sclk_falling) ctrl = { ST_DONE , 4'b0001 };
else ctrl = { ST_POST_DATA , 4'b0001 };
ST_DONE: ctrl = { ST_IDLE , 4'b0001 };
default: ctrl = { ST_IDLE, 4'b0000 };
endcase
end
assign sclk = ctrl[1] ? sclk_int : 1'b1;
assign done = state == ST_DONE;
assign busy = (state != ST_IDLE) & (state != ST_DONE);
wire mosi_load = state == ST_READ_DATA;
wire mosi_shift_en = state == ST_TX_WORD & sclk_falling;
wire [W-1:0] mosi_shift;
r #(W) mosi_shift_r
(.c(c), .rst(1'b0), .en(mosi_shift_en | mosi_load),
.d(state == ST_READ_DATA ? dfifo_q[W-1:0] : {mosi_shift[W-2:0],1'b0}),
.q(mosi_shift));
assign mosi = ~cs & mosi_shift[W-1];
endmodule
/*
wire [WIDTH-1:0] miso_shift;
wire miso_shift_en;
wire miso_shift_reset = state == ST_ASSERT_CS;
r #(WIDTH) miso_shift_r(.c(clk), .rst(miso_shift_reset), .en(miso_shift_en),
.d({miso_shift[WIDTH-2:0], miso_sync}),
.q(miso_shift));
// delay registering MISO until it works its way out of synchronization
// todo: this is probably not enough. probably needs to take CPOL into account
wire miso_sclk_capture_edge;
generate
if (CPHA == 1) begin
assign miso_sclk_capture_edge = sclk_rising;
end else begin
assign miso_sclk_capture_edge = sclk_falling;
end
endgenerate
wire hack_cpol_extra_sample; // abomination
wire [DEBOUNCE-1:0] miso_shift_en_delay;
r #(DEBOUNCE) miso_shift_en_delay_r
(.c(clk), .en(1'b1), .rst(1'b0),
.d({((state == ST_DATA) & miso_sclk_capture_edge) | hack_cpol_extra_sample,
miso_shift_en_delay[DEBOUNCE-1:1]}),
.q(miso_shift_en_delay));
assign miso_shift_en = miso_shift_en_delay[0];
wire sclk_gated = (state == ST_DATA ? sclk_int : 1'b1 );
wire sclk_pos_pol = SCLK_FREE_RUNNING ? sclk_int : sclk_gated;
assign sclk = CPOL ? sclk_pos_pol : ~sclk_pos_pol;
assign ss = ~ctrl[0];
assign done = (state == ST_DONE) & sclk_falling;
assign miso_data = miso_shift;
generate
if (CPOL == 0) begin
assign hack_cpol_extra_sample = ctrl[3];
end else begin
assign hack_cpol_extra_sample = 0;
end
endgenerate
*/
/////////////////////////////////////////////////////////////////////////
`ifdef test_spi_master
module spi_master_tb();
wire c;
sim_clk #(100) clk_inst(c);
localparam W = 8;
reg [W-1:0] txd;
wire [W-1:0] rxd;
reg txdv;
wire rxdv;
wire done, busy;
wire sclk, mosi, miso, cs;
spi_master #(.SCLK_DIV(50), .W(8)) spi_master_inst
(.c(c), .busy(busy), .done(done),
.txd(txd), .txdv(txdv),
.rxd(rxd), .rxdv(rxdv),
.sclk(sclk), .mosi(mosi), .miso(miso), .cs(cs));
wire [W-1:0] slave_rxd;
wire slave_rxdv, slave_rxe;
spi_slave_rx spi_slave_rx_inst
(.clk(c),
.rxd(slave_rxd), .rxdv(slave_rxdv), .rxe(slave_rxe),
.cs(cs), .mosi(mosi), .miso(miso), .sclk(sclk));
initial begin
$dumpfile("spi_master_test.lxt");
$dumpvars();
txd = 8'ha5;
txdv = 0;
#100
@(posedge c);
#1 txdv = 1;
@(posedge c);
#1 txd = 8'h7;
@(posedge c);
#1 txd = 8'h51;
@(posedge c);
#1 txdv = 0;
#10000
@(posedge c);
#1 txdv = 1;
@(posedge c);
#1 txdv = 0;
#20000
$finish;
end
endmodule
`endif
|
module clock_counter(
input clk_i, //often, "tags" are added to variables to denote what they do for the user
input reset_n, //here, 'i' is used for input and 'o' for the output, while 'n' specifies an active low signal ("not")
output reg clk_o
);
reg [14:0] count; //register stores the counter value so that it can be modified on a clock edge. register size needs to store as large of a number as the counter reaches
//for this implementation, count must reach 415999, so 2^n >= 415999, n = 19
always @ (posedge clk_i, negedge reset_n)
begin
count <= count + 1; //at every positive edge, the counter is increased by 1
if(!reset_n)
begin
clk_o <= 0;
count <= 0; //if reset (active low) is pushed, the counter is reset
end
else
if(count >= 1800) //count value of greater than or equal to this value causes the output clock to be inverted. the resulting frequency will be input_frequency/(1+count_value)
begin //for this implementation, a frequency of 5 Hz was desired, so 2.08e6/5 - 1 = 34666
clk_o <= ~clk_o;
count <= 0; //resets the counter after the output clock has been inverted
end
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* MBus master layer wrapper for NON-power gating
*
* Update history:
*
* date: 11/08 '13
* modified content: Newly added
* modified by: Ye-sheng Kuo <>
* --------------------------------------------------------------------------
* IMPORTANT:
* --------------------------------------------------------------------------
* */
`include "include/mbus_def.v"
module mbus_ctrl_layer_wrapper
(
input CLK_EXT,
input CLKIN,
input RESETn,
input DIN,
output CLKOUT,
output DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
input TX_PRIORITY,
output TX_ACK,
output [`ADDR_WIDTH-1:0] RX_ADDR,
output [`DATA_WIDTH-1:0] RX_DATA,
output RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output RX_FAIL,
output RX_PEND,
output TX_FAIL,
output TX_SUCC,
input TX_RESP_ACK
);
parameter ADDRESS = 20'haaaaa;
wire w_n0lc0_clk_out;
wire w_n0lc0;
mbus_ctrl_wrapper#(.ADDRESS(ADDRESS)) n0
(
.CLK_EXT (CLK_EXT),
.CLKIN (CLKIN),
.CLKOUT (w_n0lc0_clk_out),
.RESETn (RESETn),
.DIN (DIN),
.DOUT (w_n0lc0),
.TX_ADDR (TX_ADDR),
.TX_DATA (TX_DATA),
.TX_REQ (TX_REQ),
.TX_ACK (TX_ACK),
.TX_PEND (TX_PEND),
.TX_PRIORITY (TX_PRIORITY),
.RX_ADDR (RX_ADDR),
.RX_DATA (RX_DATA),
.RX_REQ (RX_REQ),
.RX_ACK (RX_ACK),
.RX_BROADCAST (RX_BROADCAST),
.RX_FAIL (RX_FAIL),
.RX_PEND (RX_PEND),
.TX_SUCC (TX_SUCC),
.TX_FAIL (TX_FAIL),
.TX_RESP_ACK (TX_RESP_ACK),
.THRESHOLD (20'h05fff)
);
mbus_wire_ctrl lc0
(
.RESETn(RESETn),
.DOUT_FROM_BUS(w_n0lc0),
.CLKOUT_FROM_BUS(w_n0lc0_clk_out),
.DOUT(DOUT),
.CLKOUT(CLKOUT)
);
endmodule // mbus_layer_wrapper
|
#include <bits/stdc++.h> using namespace std; int f(string s1, string s2) { int k = 0; while (s2 != s1) { s2 += s2[0]; s2 = s2.substr(1); k++; if (k > s2.length()) return 1000000; } return k; } int main() { int n; cin >> n; vector<string> V(n); for (int i = 0; i < n; i++) cin >> V[i]; int MIN = 1000000, ans; for (int i = 0; i < n; i++) { ans = 0; for (int j = 0; j < n; j++) if (j != i) ans += f(V[i], V[j]); if (ans < MIN) MIN = ans; } if (MIN == 1000000) cout << -1 << endl; else cout << MIN << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int cnt[100500]; int bestAns, start, len; int longest[100500]; inline void updAns(int L, int R) { int val = cnt[R + 1] - cnt[L]; if (val > bestAns) { bestAns = val; start = L; len = R - L + 1; } } int main() { stack<pair<char, int> > seq; string s; cin >> s; int n = s.size(); for (int i = 1; i <= n; i++) { cnt[i] = s[i - 1] == [ ; cnt[i] += cnt[i - 1]; longest[i - 1] = n + 234; } for (int i = 0; i < n; i++) { pair<char, int> cur(s[i], i); if (seq.empty()) seq.push(cur); else { char pr = seq.top().first; if (s[i] == ] and pr == [ or s[i] == ) and pr == ( ) { pair<char, int> ws = seq.top(); seq.pop(); int low = ws.second, high = i; longest[i] = min(longest[i], low); if (low > 0 and longest[low - 1] < low - 1) { longest[i] = min(longest[i], longest[low - 1]); } updAns(longest[i], i); } else seq.push(cur); } } cout << bestAns << endl; cout << s.substr(start, len) << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/28/2016 11:50:35 AM
// Design Name:
// Module Name: box
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define TOP 0
`define RIGHT 1
`define BOTTOM 2
`define LEFT 3
`define WIDTH 640
`define HEIGHT 480
`define BOX_WIDTH WIDTH/4
`define BOX_HEIGHT HEIGHT/4
`define START_X WIDTH/2
`define START_Y HEIGHT/2
module box(
input logic move_up, move_down, move_left, move_right, mode, rst_n,
input logic [9:0] x, y,
output logic draw_box
);
logic [9:0] width, height, c_x, c_y;
logic [9:0] left, right, top, bottom;
assign draw_box = (x == left || x == right ||
y == top || y == bottom)
assign top = c_y - height;
assign bottom = c_y + height;
assign left = c_x - width;
assign right = c_x + width;
assign x_y_mode = mode;
assign width_height_mode = !mode;
up_down_counter #(BOX_WIDTH) width_counter(clk, rst_n,
width_height_mode, move_right, move_left, width);
up_down_counter #(BOX_HEIGHT) height_counter(clk, rst_n,
width_height_mode, move_up, move_down, height);
up_down_counter #(START_X) c_x_counter(clk, rst_n,
x_y_mode, move_right, move_left, c_x);
up_down_counter #(START_Y) c_y_counter(clk, rst_n,
x_y_mode, move_up, move_down, c_y);
endmodule
module up_down_counter
#(parameter DEFAULT=8'd100) (
input logic clk, rst_n, clr, en,
input logic count_up, count_down,
output logic [9:0] count
);
always_ff @(posedge clk) begin
if (~rst_n)
count <= DEFAULT;
else if (clr)
count <= DEFAULT;
else if (en) begin
if (count_up) count <= count + 1'b1;
else if (count_down) count <= count - 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int N = 100010; int a[N]; bool cont[110][N]; long long f[N][110], sumf[N]; int main() { ios::sync_with_stdio(false); int n, k, len; cin >> n >> k >> len; for (int i = 1; i <= n; i++) cin >> a[i]; for (int j = 1; j <= k; j++) { int cnt = 0; for (int i = 1; i <= n; i++) { if (a[i] == -1 || a[i] == j) cnt++; else cnt = 0; if (cnt >= len) cont[j][i] = true; } } f[0][0] = 1; sumf[0] = 1; for (int i = 1; i <= n; i++) { if (a[i] == -1) for (int j = 1; j <= k; j++) { f[i][j] = sumf[i - 1]; if (cont[j][i]) f[i][j] -= sumf[i - len] - f[i - len][j]; sumf[i] = (sumf[i] + f[i][j]) % MOD; } else { f[i][a[i]] = sumf[i - 1]; if (cont[a[i]][i]) f[i][a[i]] -= sumf[i - len] - f[i - len][a[i]]; sumf[i] = (sumf[i] + f[i][a[i]]) % MOD; } } cout << (sumf[n] + MOD) % MOD << n ; } |
#include <bits/stdc++.h> using namespace std; void task(); int main() { task(); return 0; } const int N = 2e5 + 10; const long long int MOD = (long long int)1e9 + 7; const int INF = 0x3f3f3f3f; const long long int LINF = (long long int)4e18 + 100; const int BUF_SIZE = (int)1e6 + 10; const double PI = acos(-1); pair<int, int> a[N]; double u[N], ad[N], bd[N]; long long int sq_dist(long long int x1, long long int y1, long long int x2, long long int y2) { return (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); } double dist(long long int x1, long long int y1, long long int x2, long long int y2) { return sqrt(sq_dist(x1, y1, x2, y2)); } double dp[N][2][2]; void task() { int ai, aj, bi, bj, ui, uj; cin >> ai >> aj >> bi >> bj >> ui >> uj; int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i].first >> a[i].second; } for (int i = 0; i < n; ++i) { u[i] = dist(ui, uj, a[i].first, a[i].second); (void(1)); ; } for (int i = 0; i < n; ++i) { ad[i] = dist(ai, aj, a[i].first, a[i].second) + u[i]; (void(1)); ; } for (int i = 0; i < n; ++i) { bd[i] = dist(bi, bj, a[i].first, a[i].second) + u[i]; (void(1)); ; } fill(dp[0][0], dp[0][0] + N * 2 * 2, LINF); dp[0][1][1] = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < 2; ++j) { for (int k = 0; k < 2; ++k) { (void(1)); ; if (j == 1) { dp[i + 1][j - 1][k] = min(dp[i][j][k] + ad[i], dp[i + 1][j - 1][k]); } if (k == 1) { dp[i + 1][j][k - 1] = min(dp[i][j][k] + bd[i], dp[i + 1][j][k - 1]); } dp[i + 1][j][k] = min(dp[i + 1][j][k], dp[i][j][k] + 2 * u[i]); } } } double ans = LINF; for (int i = 0; i < 2; ++i) { for (int j = 0; j < 2; ++j) if (!(i == 1 && j == 1)) { (void(1)); ; ans = min(ans, dp[n][i][j]); } } cout << fixed << setprecision(12) << ans; } |
#include <bits/stdc++.h> using namespace std; inline int add(int _a, int _b) { if (_a < 0) { _a += 1000000007; } if (_b < 0) { _b += 1000000007; } if (_a + _b >= 1000000007) { return _a + _b - 1000000007; } return _a + _b; } inline int mul(int _a, int _b) { if (_a < 0) { _a += 1000000007; } if (_b < 0) { _b += 1000000007; } return ((long long int)((long long int)_a * (long long int)_b)) % 1000000007; } const int N = 1000000; long long int tree[4 * N + 10], lz[4 * N + 10], cost[N + 10], dp[N + 10]; int n, parent[N + 10], m, sbtr[N + 10]; char w[N + 10]; vector<int> adj[N + 10], vec; bool mark[N + 10]; void input() { int i, j; scanf( %d , &n); ++n; for (i = 0; i < n - 1; ++i) { scanf( %d %c , &parent[i + 1], &w[i + 1]); adj[parent[i + 1]].push_back(i + 1); } scanf( %d , &m); for (i = 0; i < m; ++i) { int x; scanf( %d , &x); mark[x] = true; vec.push_back(x); } } bool cmp(int lhs, int rhs) { return w[lhs] < w[rhs]; } void dfs(int src) { int i, j; sbtr[src] += mark[src]; long long int sum = 0; for (i = 0; i < adj[src].size(); ++i) { int u = adj[src][i]; dfs(u); cost[u] = sum; sbtr[src] += sbtr[u]; sum += sbtr[u]; } } void make_tree(int lo, int hi, int iter) { int mid = (lo + hi) >> 1; if (lo == hi) { tree[iter] = 100000000000, lz[iter] = 0; return; } else if (lo < hi) { tree[iter] = 100000000000, lz[iter] = 0; make_tree(lo, mid, 2 * iter + 1); make_tree(mid + 1, hi, 2 * iter + 2); } } void mrg(int iter) { tree[iter] = min(tree[2 * iter + 1], tree[2 * iter + 2]); } void lazy_up(int iter, long long int v) { tree[iter] += v; lz[iter] += v; } void push_down(int iter) { lazy_up(2 * iter + 1, lz[iter]); lazy_up(2 * iter + 2, lz[iter]); lz[iter] = 0; } void point_update(int lo, int hi, int iter, int idx, long long int v) { int mid = (lo + hi) >> 1; if (lo == hi) { tree[iter] = v; return; } push_down(iter); if (idx >= lo && idx <= mid) { point_update(lo, mid, 2 * iter + 1, idx, v); } else { point_update(mid + 1, hi, 2 * iter + 2, idx, v); } mrg(iter); } void range_update(int lo, int hi, int iter, int l, int r, long long int v) { int mid = (lo + hi) >> 1; if (l > r) { return; } if (l <= lo && r >= hi) { lazy_up(iter, v); return; } push_down(iter); if (l >= lo && r <= mid) { range_update(lo, mid, 2 * iter + 1, l, r, v); } else if (l >= mid + 1 && r <= hi) { range_update(mid + 1, hi, 2 * iter + 2, l, r, v); } else { range_update(lo, mid, 2 * iter + 2, l, mid, v); range_update(mid + 1, hi, 2 * iter + 2, mid + 1, r, v); } mrg(iter); } void F(int src) { int i, j; if (src) { point_update(0, n - 1, 0, src, dp[parent[src]]); range_update(0, n - 1, 0, 0, n, cost[src] + mark[parent[src]]); if (mark[src]) { dp[src] = min(tree[0] + 1, dp[parent[src]] + 1); } else { dp[src] = dp[parent[src]] + 1; } } for (i = 0; i < adj[src].size(); ++i) { int u = adj[src][i]; F(u); } if (src) { point_update(0, n - 1, 0, src, 100000000000); range_update(0, n - 1, 0, 0, n, -(cost[src] + mark[parent[src]])); } } void solve() { int i, j; for (i = 0; i < n; ++i) { sort(adj[i].begin(), adj[i].end(), cmp); } dfs(0); make_tree(0, n - 1, 0); dp[0] = 0, F(0); for (i = 0; i < vec.size(); ++i) { if (i) { printf( ); } printf( %lld , dp[vec[i]]); } puts( ); } int main() { input(); solve(); } |
`define WIDTH_P 3
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
WIDTH_P is the width of the number of wait cycles needed. So each test
monitors the output for 2**WIDTH_P cycles.
2. PARAMETERIZATION
The parameter WIDTH_P has little influence on the way DUT synthesizes. So
a minimum set of tests might be WIDTH_P = 1,2,3,4. Tests with large
WIDTH_P may take long to finish because the number of cycles the test runs
grows exponentially with it.
***************************************************************************/
module test_bsg
#(parameter lg_wait_cycles_p = `WIDTH_P, // width of the timer
parameter cycle_time_p = 20,
parameter reset_cycles_lo_p = 1,
parameter reset_cycles_hi_p = 5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d\n", `WIDTH_P);
end
logic test_output, test_output_r, ref_test_output;
time reset_time, ready_time;
assign ref_test_output = ((ready_time-reset_time)/cycle_time_p)
== (2**`WIDTH_P); // checks correctness
// of ready timing
always_ff @(negedge reset)
begin
reset_time <= $time - (cycle_time_p / 2); // the test reset becomes 0
// on negedge
ready_time <= 0;
end
always_ff @(posedge test_output)
ready_time <= $time;
always_ff @(posedge clk)
begin
test_output_r <= test_output;
/*$display("\ntest_output: %b @ time: %d", test_output, $time);*/
if(!reset)
assert (test_output == ref_test_output)
else $error("mismatch at time = %d", $time);
if(test_output_r)
begin
$display("=============================================================\n");
$finish;
end
end
bsg_wait_after_reset #( .lg_wait_cycles_p(lg_wait_cycles_p)
) DUT
( .clk_i (clk)
, .reset_i (reset)
, .ready_r_o(test_output)
);
/*//log test results
logic [(3*lg_wait_cycles_p)-1:0] log;
assign log = { `BSG_SAFE_CLOG2(lg_wait_cycles_p+1)'(test_output)
, `BSG_SAFE_CLOG2(lg_wait_cycles_p+1)'(ref_test_output)
, `BSG_SAFE_CLOG2(lg_wait_cycles_p+1)'(lg_wait_cycles_p)};
bsg_nonsynth_ascii_writer #( .width_p (`BSG_SAFE_CLOG2(
lg_wait_cycles_p+1))
, .values_p (3)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%x")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i (log)
);*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s; cin >> n >> s; queue<int> q; int cntD = 0, cntR = 0; for (int i = 0; i < n; i++) { if (s[i] == R ) cntR++; else cntD++; q.push(i); } int removeD = 0, removeR = 0; while (!q.empty()) { if (cntD - removeD <= 0) { cout << R ; return 0; } if (cntR - removeR <= 0) { cout << D ; return 0; } int top = q.front(); q.pop(); if (s[top] == R ) { if (removeR) { removeR--; cntR--; } else { removeD++; q.push(top); } } else { if (removeD) { removeD--; cntD--; } else { removeR++; q.push(top); } } } return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_RAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "NIOS_SYSTEMV3_RAM.hex";
output [ 31: 0] readdata;
input [ 10: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2048,
the_altsyncram.numwords_a = 2048,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 11;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int K, N, M, Q; map<string, int> Basic, F[111]; string st, Comp_St[60]; vector<pair<string, int> > Comp[60]; int main() { cin >> K >> N >> M >> Q; for (int i = 1; i <= N; i++) { cin >> st; Basic[st] = i; } for (int i = 0, k; i < M; i++) { cin >> st; st = st.substr(0, st.size() - 1); Comp_St[i] = st; for (string stt; cin >> stt;) { cin >> k; Comp[i].push_back(make_pair(stt, k)); char ch; scanf( %c , &ch); if (ch != , ) break; } } for (int i = 0, p; i < Q; i++) { cin >> p >> st; F[p][st]++; for (int j = 0; j < M; j++) { st = Comp_St[j]; bool flag = true; for (int k = 0; k < Comp[j].size(); k++) if (F[p][Comp[j][k].first] < Comp[j][k].second) flag = false; if (flag) { F[p][st]++; for (int k = 0; k < Comp[j].size(); k++) F[p][Comp[j][k].first] -= Comp[j][k].second; } } } for (int i = 1; i <= K; i++) { int TOT = 0; for (map<string, int>::iterator it = F[i].begin(); it != F[i].end(); it++) if (it->second > 0) TOT++; printf( %d n , TOT); for (map<string, int>::iterator it = F[i].begin(); it != F[i].end(); it++) if (it->second > 0) cout << it->first << << it->second << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; long long b, q, l, m, a[N]; map<long long, int> vis; int main() { scanf( %lld%lld%lld%lld , &b, &q, &l, &m); while (m--) { long long x; scanf( %lld , &x); vis[x] = 1; } if (max(-b, b) > l) { printf( 0 n ); } else if (b == 0) { if (vis.count(b) == 0) printf( inf n ); else printf( 0 n ); } else { if (q == 0) { if (vis.count(0) == 0) { printf( inf n ); } else { printf( %d n , !vis.count(b)); } } else if (q == 1) { if (vis.count(b) == 0) printf( inf n ); else printf( 0 n ); } else if (q == -1) { if (vis.count(b) == 0 || vis.count(-b) == 0) printf( inf n ); else printf( 0 n ); } else { int ans = 0; while (max(-b, b) <= l) { if (vis.count(b) == 0) ans++; b *= q; } printf( %d n , ans); } } return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_button_shift_up (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 1489 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w3,
w1536,
w1537,
w48,
w1489;
assign w1 = i_data0;
assign w1489 = w1537 - w48;
assign w1536 = w3 << 9;
assign w1537 = w1 + w1536;
assign w3 = w4 - w1;
assign w4 = w1 << 2;
assign w48 = w3 << 4;
assign o_data0 = w1489;
//multiplier_block area estimate = 5235.75353578088;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_TB_V
`define SKY130_FD_SC_LP__O22AI_TB_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__o22ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int m = 1; while (m * (m - 1) <= 2 * n) m++; m = m - 1; cout << m << n ; int arr[m + 4][m + 3]; long long k = 1; for (int i = 0; i < m; i++) { long long count = 0; for (int j = i; j < m - 1; j++) { arr[i][j] = k + count++; } count = 0; for (long long j = i + 1; j < m; j++) { arr[j][i] = k + count++; } k = k + m - i - 1; } for (long long i = 0; i < m; i++) { for (long long j = 0; j < m - 1; j++) { cout << arr[i][j] << ; } cout << n ; } } |
#include <bits/stdc++.h> int inp() { char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); int sum = 0; while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum; } char s[1000010], l[1000010], r[1000010]; long long f[1000010], sum[1000010]; int n, sl, sr, pl[1000010], pr[1000010], hshs[1000010], hshl[1000010], hshr[1000010], fpow[1000010]; bool ok1(int x) { if (x + sl - 1 > n) return false; if (sl == pl[x]) return true; return l[pl[x] + 1] < s[x + pl[x]]; } bool ok2(int x) { if (x + sr - 1 > n) return false; if (pr[x] == sr) return true; return r[pr[x] + 1] > s[x + pr[x]]; } int get_hsh(int *hsh, int l, int r) { return (hsh[r] - ((long long)(hsh[l - 1]) * (long long)(fpow[r - l + 1]) % 998244353) + 998244353) % 998244353; } void solve(int *s, int *hsh, int len) { for (int i = 1; i <= n - len + 1; i++) { int l = 0; int r = len; while (l < r) { int mid = (l + r + 1) >> 1; if (get_hsh(hshs, i, i + mid - 1) == get_hsh(hsh, 1, mid)) l = mid; else r = mid - 1; } s[i] = l; } } void gethash(char *str, int *hsh, int len) { for (int i = 1; i <= len; i++) hsh[i] = ((long long)(hsh[i - 1]) * (long long)(11) + str[i] - 0 + 1) % 998244353; } int main() { fpow[0] = 1; for (int i = 1; i <= 1000000; i++) fpow[i] = ((long long)(fpow[i - 1]) * (long long)(11) % 998244353); scanf( %s , s + 1); scanf( %s , l + 1); scanf( %s , r + 1); n = strlen(s + 1); sl = strlen(l + 1); sr = strlen(r + 1); gethash(l, hshl, sl); gethash(r, hshr, sr); gethash(s, hshs, n); f[0] = 1; solve(pl, hshl, sl); solve(pr, hshr, sr); for (int i = 0; i <= n; i++) { if (i) { sum[i] += sum[i - 1]; f[i] += sum[i]; f[i] %= 998244353; } if (s[i + 1] == 0 ) { if (sl == 1 && l[1] == 0 ) { f[i + 1] += f[i]; f[i + 1] %= 998244353; } continue; } if (sl < sr) { sum[sl + i + 1] += f[i]; sum[sl + i + 1] %= 998244353; sum[sr + i] += 998244353 - f[i]; sum[sr + i] %= 998244353; } if (sl == sr) { if (ok1(i + 1) && ok2(i + 1)) { f[i + sl] += f[i]; f[i + sl] %= 998244353; } } else { if (ok1(i + 1)) { f[i + sl] += f[i]; f[i + sl] %= 998244353; } if (ok2(i + 1)) { f[i + sr] += f[i]; f[i + sr] %= 998244353; } } } std::cout << f[n] << std::endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_V |
module top(
input clk,
input rst,
input [7:0] a,
input [7:0] b,
output [15:0] y);
wire co;
wire [31:0] out;
SB_MAC16 i_sbmac16
(
.A(a),
.B(b),
.C(8'd0),
.D(8'd0),
.O(out),
.CLK(clk),
.IRSTTOP(rst),
.IRSTBOT(rst),
.ORSTTOP(rst),
.ORSTBOT(rst),
.AHOLD(1'b0),
.BHOLD(1'b0),
.CHOLD(1'b0),
.DHOLD(1'b0),
.OHOLDTOP(1'b0),
.OHOLDBOT(1'b0),
.OLOADTOP(1'b0),
.OLOADBOT(1'b0),
.ADDSUBTOP(1'b0),
.ADDSUBBOT(1'b0),
.CO(co),
.CI(1'b0),
.ACCUMCI(),
.ACCUMCO(),
.SIGNEXTIN(),
.SIGNEXTOUT()
);
//Config: mult_8x8_pipeline_unsigned
defparam i_sbmac16. B_SIGNED = 1'b0;
defparam i_sbmac16. A_SIGNED = 1'b0;
defparam i_sbmac16. MODE_8x8 = 1'b1;
defparam i_sbmac16. BOTADDSUB_CARRYSELECT = 2'b00;
defparam i_sbmac16. BOTADDSUB_UPPERINPUT = 1'b0;
defparam i_sbmac16. BOTADDSUB_LOWERINPUT = 2'b00;
defparam i_sbmac16. BOTOUTPUT_SELECT = 2'b10;
defparam i_sbmac16. TOPADDSUB_CARRYSELECT = 2'b00;
defparam i_sbmac16. TOPADDSUB_UPPERINPUT = 1'b0;
defparam i_sbmac16. TOPADDSUB_LOWERINPUT = 2'b00;
defparam i_sbmac16. TOPOUTPUT_SELECT = 2'b10;
defparam i_sbmac16. PIPELINE_16x16_MULT_REG2 = 1'b0;
defparam i_sbmac16. PIPELINE_16x16_MULT_REG1 = 1'b1;
defparam i_sbmac16. BOT_8x8_MULT_REG = 1'b1;
defparam i_sbmac16. TOP_8x8_MULT_REG = 1'b1;
defparam i_sbmac16. D_REG = 1'b0;
defparam i_sbmac16. B_REG = 1'b1;
defparam i_sbmac16. A_REG = 1'b1;
defparam i_sbmac16. C_REG = 1'b0;
assign y = out[15:0];
endmodule |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email:
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module asram16
(
clk_i,
data_o,
data_i,
address_i,
be_i,
wren_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] SIZE = 18;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i;
output [15:0] data_o;
input [15:0] data_i;
input [(SIZE - 1):0] address_i;
input [1:0] be_i;
input wren_i;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [7:0] ram_ub [((2<< (SIZE-1)) - 1):0];
reg [7:0] ram_lb [((2<< (SIZE-1)) - 1):0];
wire [15:0] data_o;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @ (posedge clk_i )
begin
if ((be_i[1] == 1'b0) && (wren_i == 1'b0))
begin
ram_ub[address_i] <= data_i[15:8];
end
if ((be_i[0] == 1'b0) && (wren_i == 1'b0))
begin
ram_lb[address_i] <= data_i[7:0];
end
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign data_o = { ram_ub[address_i], ram_lb[address_i] };
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:36777216 ) const int Nmax = 100100; const int Drection[4][2] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}}; int h, q; long long minV[55], maxV[55]; long long leftDown(long long L, int hg) { if (hg == h) return L; return leftDown(L << 1ll, hg + 1); } long long rightDown(long long R, int hg) { if (hg == h) return R; return rightDown((R << 1ll) + 1, hg + 1); } inline void end(long long x) { if (x == 0) cout << Data not sufficient! << endl; else if (x == -1) cout << Game cheated! << endl; else cout << x << endl; exit(0); } inline void add(long long x) { static long long extra = -1; if (x <= 0) end(extra); if (extra != -1) end(0); extra = x; } int main() { ios_base::sync_with_stdio(0); cin >> h >> q; minV[1] = maxV[1] = 1; for (int i = 2; i <= h; i++) { minV[i] = minV[i - 1] * 2ll; maxV[i] = maxV[i - 1] * 2ll + 1; } vector<pair<long long, long long> > list; for (int i = 1; i <= q; i++) { long long lv, L, R, ans; cin >> lv >> L >> R >> ans; if (ans == 1) { if (minV[lv] <= L - 1) list.push_back(make_pair(leftDown(minV[lv], lv), rightDown(L - 1, lv))); if (R + 1 <= maxV[lv]) list.push_back(make_pair(leftDown(R + 1, lv), rightDown(maxV[lv], lv))); } else list.push_back(make_pair(leftDown(L, lv), rightDown(R, lv))); } sort(list.begin(), list.end()); long long L = leftDown(1, 1); long long R = rightDown(1, 1); for (int i = 0; i < list.size(); i++) { if (list[i].first > L) { add(L++); i--; continue; } L = max(L, list[i].second + 1); } while (L <= R) add(L++); add(-10); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; long long sum = 0; for (int i = 0; i < n; i++) cin >> arr[i]; vector<int> odd, even; for (int i = 0; i < n; i++) { if (arr[i] & 1) odd.push_back(arr[i]); else even.push_back(arr[i]); } sort(odd.begin(), odd.end()); sort(even.begin(), even.end()); if (odd.size() > even.size()) { for (int i = 0; i < odd.size() - even.size() - 1; i++) sum += odd[i]; } else if (odd.size() == even.size()) sum = 0; else { for (int i = 0; i < even.size() - odd.size() - 1; i++) sum += even[i]; } cout << sum; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; if (a == b) cout << YES ; else if (b - a > 0 && c > 0) { if ((b - a) % c == 0) cout << YES ; else cout << NO ; } else if (b - a > 0 && c < 0) { cout << NO ; } else if (b - a < 0 && c > 0) { cout << NO ; } else if (b - a < 0 && c < 0) { if ((a - b) % c == 0) cout << YES ; else cout << NO ; } else if (c == 0) cout << NO ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FILL_FUNCTIONAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_FUNCTIONAL_PP_V |
`timescale 1 ns / 1 ps
`include "hapara_bram_dma_switch_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module hapara_bram_dma_switch_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_BLACKBOX_V
`define SKY130_FD_SC_MS__O31A_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o31a (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_1_V
`define SKY130_FD_SC_LP__SRSDFRTP_1_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Verilog wrapper for srsdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srsdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__srsdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.SLEEP_B(SLEEP_B),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__srsdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_1_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: five_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module five_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/five_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/five_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL five_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; namespace IO { const int maxn(1 << 21 | 1); char *iS, *iT, ibuf[maxn], obuf[maxn], *oS = obuf, *oT = obuf + maxn - 1, c, st[20]; int f, tp, len; inline char getc() { return iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, maxn, stdin), iS == iT ? EOF : *iS++) : *iS++; } template <class T> inline void read(T &x) { for (c = getc(), f = 1; c < 0 || c > 9 ; c = getc()) f = c == - ? -1 : 1; for (x = 0; c >= 0 && c <= 9 ; c = getc()) x = x * 10 + (c ^ 48); x *= f; } template <class T, class... Other> inline void read(T &x, Other &...y) { read(x), read(y...); } inline void flush() { fwrite(obuf, 1, oS - obuf, stdout), oS = obuf; } inline void putc(char ch) { *oS++ = ch; if (oS == oT) flush(); } template <class T> inline void print(T x, char ch = n ) { if (!x) putc( 0 ); if (x < 0) putc( - ), x = -x; while (x) st[++tp] = x % 10 + 0 , x /= 10; while (tp) putc(st[tp--]); putc(ch); } template <class T, class... Other> inline void print(T x, Other... y) { print(x), print(y...); } inline void print_str(char *s) { for (len = strlen(s), f = 0; f < len; ++f) putc(s[f]); } inline void read_str(char *s, int &l) { for (l = 0, c = getc(); (c < a || c > z ) && (c < A || c > Z ); c = getc()) ; for (; (c >= a && c <= z ) || (c >= A && c <= Z ); c = getc()) s[l++] = c; s[l] = 0 ; } } // namespace IO using IO ::flush; using IO ::print; using IO ::print_str; using IO ::read; using IO ::read_str; template <class T> inline void cmax(T &x, T y) { x = x >= y ? x : y; } template <class T, class... Other> inline void cmax(T &x, T y, Other... z) { Cmax(x, y), Cmax(x, z...); } template <class T> inline void cmin(T &x, T y) { x = x <= y ? x : y; } template <class T, class... Other> inline void cmin(T &x, T y, Other... z) { Cmin(x, y), Cmin(x, z...); } inline int gcd(int x, int y) { return y ? gcd(y, x % y) : x; } const int mod(998244353); inline void inc(int &x, const int y) { x = x + y >= mod ? x + y - mod : x + y; } inline void dec(int &x, const int y) { x = x - y < 0 ? x - y + mod : x - y; } inline int add(const int x, const int y) { return x + y >= mod ? x + y - mod : x + y; } inline int sub(const int x, const int y) { return x - y < 0 ? x - y + mod : x - y; } inline int fpow(long long x, int y) { long long ret = 1; for (; y; y >>= 1, x = x * x % mod) if (y & 1) ret = ret * x % mod; return ret; } const int maxn(1e5 + 5); int n, seq[maxn], st[18][maxn], lg[maxn], mx; long long cnt[maxn], sum[maxn], sumv[maxn]; inline int query_gcd(int l, int r) { int len = lg[r - l + 1]; return gcd(st[len][l], st[len][r - (1 << len) + 1]); } inline long long calc(long long m, long long a, long long b, long long c) { if (c < 0) c = -c, a = -a, b = -b; if (m <= 0) return 0; if (m == 1) return (a + b) / c; if (!a) return b / c * m; long long ma, mb, ra, rb, nm; if (b < 0 || b >= c || a < 0 || a >= c) { ma = (a % c + c) % c, mb = (b % c + c) % c; ra = (a - ma) / c, rb = (b - mb) / c; return calc(m, ma, mb, c) + (ra * m * (m + 1) >> 1) + rb * m; } nm = (a * m + b) / c; return nm * m - calc(nm, c, -b - 1, a); } inline long long solve(long long x, long long cx, long long y, long long cy, long long s) { if (!cx || !cy) return 0; if (cx * x + cy * y <= s) return cx * cy; long long s1 = s - cy * y, s2 = s - cx * x, ss = s - cx * x - cy * y; return calc(s / x, -x, s, y) - calc(s1 / x, -x, s1, y) - calc(s2 / y, -y, s2, x) + calc(ss / x, -x, ss, y); } inline long long check(long long mid) { int i, j, p; long long ret = 0, s, k; for (i = j = 1; i <= mx; ++i) { if (!cnt[i]) continue; k = min(mid / i, cnt[i]); if (k) ret += cnt[i] * k - (k * (k - 1) >> 1); while (j < mx && sumv[j + 1] - sumv[i - 1] <= mid) ++j; if (j >= i) ret += cnt[i] * (sum[j] - sum[i]); if (j == mx) continue; for (p = max(i, j); p < mx; ++p) { s = mid - sumv[p] + sumv[i]; if (s < 0) break; ret += solve(i, cnt[i], p + 1, cnt[p + 1], s); } } return ret; } int main() { int i, j, k, p, g; long long ql = 1, qr = 0, mid, ans, lim; read(n); for (i = 1; i <= n; ++i) read(seq[i]), st[0][i] = seq[i], cmax(mx, seq[i]); for (i = 2; i <= n; ++i) lg[i] = lg[i >> 1] + 1; for (j = 1; j <= lg[n]; ++j) for (i = 1; i + (1 << j) - 1 <= n; ++i) st[j][i] = gcd(st[j - 1][i], st[j - 1][i + (1 << (j - 1))]); for (i = 1; i <= n; ++i) for (j = i; j <= n; ++j) { g = query_gcd(i, j), p = j; for (k = lg[n - j]; ~k; --k) if (p + (1 << k) - 1 <= n && st[k][p] % g == 0) p += (1 << k) - 1; cnt[g] += p - j + 1, j = p; } for (i = 1; i <= mx; ++i) qr += cnt[i] * i, sum[i] = sum[i - 1] + cnt[i], sumv[i] = sumv[i - 1] + cnt[i] * i; lim = (long long)n * (n + 1) >> 1, lim = lim * (lim + 1) >> 1, lim = (lim + 1) >> 1; while (ql <= qr) { mid = (ql + qr) >> 1; if (check(mid) >= lim) qr = mid - 1, ans = mid; else ql = mid + 1; } print(ans); return flush(), 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:39 03/09/2016
// Design Name:
// Module Name: Control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Control(
input wire clk,rst,
input [7:0] in3,in2,in1,in0,
output reg [3:0] anodo,
output reg [7:0] catodo
);
localparam N = 18;
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
always @(posedge clk, posedge rst)
if (rst)
q_reg <= 0;
else
q_reg <= q_next;
assign q_next = q_reg + 1;
always @(*)
case (q_reg[N-1:N-2])
2'b00:
begin
anodo <= 4'b1110;
catodo <= in0;
end
2'b01:
begin
anodo <= 4'b1101;
catodo <= in1;
end
2'b10:
begin
anodo <= 4'b1011;
catodo <= in2;
end
default:
begin
anodo <= 4'b0111;
catodo <= in3;
end
endcase
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1,
parameter EXPORT_JTAG = 0,
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000 // PLI Simulation Port
) (
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
input wire jtag_ena,
input wire jtag_usr1,
input wire jtag_clr,
input wire jtag_clrn,
input wire jtag_state_tlr,
input wire jtag_state_rti,
input wire jtag_state_sdrs,
input wire jtag_state_cdr,
input wire jtag_state_sdr,
input wire jtag_state_e1dr,
input wire jtag_state_pdr,
input wire jtag_state_e2dr,
input wire jtag_state_udr,
input wire jtag_state_sirs,
input wire jtag_state_cir,
input wire jtag_state_sir,
input wire jtag_state_e1ir,
input wire jtag_state_pir,
input wire jtag_state_e2ir,
input wire jtag_state_uir,
input wire [2:0] jtag_ir_in,
output wire jtag_irq,
output wire [2:0] jtag_ir_out,
input wire clk,
input wire reset_n,
input wire source_ready,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// Signals in the JTAG clock domain
wire tck;
wire tdi;
wire tdo;
wire [2:0] ir_in;
wire virtual_state_cdr;
wire virtual_state_sdr;
wire virtual_state_udr;
assign jtag_irq = 1'b0;
assign jtag_ir_out = 3'b000;
generate
if (EXPORT_JTAG == 0) begin
// SLD node instantiation
altera_jtag_sld_node node (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_out (1'b0),
.ir_in (ir_in),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_uir ()
);
assign jtag_tdo = 1'b0;
end else begin
assign tck = jtag_tck;
assign tdi = jtag_tdi;
assign jtag_tdo = tdo;
assign ir_in = jtag_ir_in;
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
end
endgenerate
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data
);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)//,
//.debug_reset(debug_reset),
//.mgmt_valid(mgmt_valid),
//.mgmt_channel(mgmt_channel),
//.mgmt_data(mgmt_data)
);
// synthesis read_comments_as_HDL on
// assign source_valid = jtag_source_valid;
// assign source_data = jtag_source_data;
// assign sink_ready = jtag_sink_ready;
// assign resetrequest = jtag_resetrequest;
// synthesis read_comments_as_HDL off
//synthesis translate_off
assign source_valid = pli_out_valid;
assign source_data = pli_out_data;
assign sink_ready = pli_in_ready;
assign resetrequest = 1'b0;
//synthesis translate_on
assign jtag_tdo = 1'b0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, a[100][100], f[2000000], p; char s[30][30]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , s[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); memset(f, 0x3f, sizeof(f)); f[0] = 0; for (int i = 0; i <= (1 << n) - 2; i++) { for (int j = 0; j < n; j++) if (!(i & (1 << j))) { p = j; break; } for (int j = 0; j < m; j++) { int sum = 0, l = 0, mx = 0; f[i | (1 << p)] = min(f[i | (1 << p)], f[i] + a[p][j]); for (int k = 0; k < n; k++) if (s[k][j] == s[p][j]) { sum = sum + a[k][j]; mx = max(mx, a[k][j]); l = l | (1 << k); } f[i | l] = min(f[i | l], f[i] + sum - mx); } } return printf( %d , f[(1 << n) - 1]), 0; } |
#include <bits/stdc++.h> const int mod = 998244353, g = 3, _g = 332748118, maxn = 2e5 + 9; inline int Pow(int base, int b) { int ret(1); while (b) { if (b & 1) ret = 1ll * ret * base % mod; base = 1ll * base * base % mod; b >>= 1; } return ret; } int r[maxn], W[maxn]; inline int Fir(int n) { int limit(1), len(0), up(n << 1); while (limit < up) { limit <<= 1; ++len; } for (int i = 0; i < limit; ++i) r[i] = (r[i >> 1] >> 1) | ((i & 1) << len - 1); return limit; } inline void NTT(int *a, int n, int type) { for (int i = 0; i < n; ++i) if (i < r[i]) std::swap(a[i], a[r[i]]); for (int mid = 1; mid < n; mid <<= 1) { int wn(Pow(type ? g : _g, (mod - 1) / (mid << 1))); W[0] = 1; for (int i = 1; i < mid; ++i) W[i] = 1ll * W[i - 1] * wn % mod; for (int R = mid << 1, j = 0; j < n; j += R) for (int k = 0; k < mid; ++k) { int x(a[j + k]), y(1ll * W[k] * a[j + mid + k] % mod); a[j + k] = 1ll * (x + y) % mod; a[j + mid + k] = 1ll * (x - y + mod) % mod; } } } int T[maxn], F[maxn], H[maxn], G[maxn], fac[maxn], fav[maxn], tmp[maxn], sum[maxn], B[maxn]; inline int Mul(int n, int *a, int *b, int *ans) { int limit(Fir(n)); NTT(a, limit, 1); NTT(b, limit, 1); for (int i = 0; i < limit; ++i) ans[i] = 1ll * a[i] * b[i] % mod; NTT(ans, limit, 0); for (int i = ((n - 1) << 1) + 1; i < limit; ++i) a[i] = b[i] = 0; return Pow(limit, mod - 2); } inline void Solve(int n, int *a) { if (!n) { a[0] = 1; return; } if (n == 1) { a[1] = 1; return; } int len(n / 2); Solve(len, a); for (int i = 0; i <= len; ++i) { F[i] = 1ll * Pow(len, i) * fav[i] % mod; H[i] = 1ll * fac[i] * a[i] % mod; } for (int i = 0; i <= (len >> 1); ++i) std::swap(H[i], H[len - i]); int limit(Fir(len + 1)); for (int i = len + 1; i < limit; ++i) F[i] = H[i] = 0; NTT(F, limit, 1); NTT(H, limit, 1); for (int i = 0; i < limit; ++i) G[i] = 1ll * F[i] * H[i] % mod; NTT(G, limit, 0); int ty(Pow(limit, mod - 2)); for (int i = 0; i <= len; ++i) tmp[i] = 1ll * G[len - i] * ty % mod * Pow(fac[i], mod - 2) % mod; int val(Mul(len + 1, a, tmp, B)); for (int i = 0; i <= (len << 1); ++i) a[i] = 1ll * B[i] * val % mod; if (n & 1) { for (int i = 0; i < n; ++i) T[i] = a[i]; for (int i = 1; i <= n; ++i) a[i] = 1ll * (T[i - 1] + 1ll * (n - 1) * T[i] % mod) % mod; } } inline int Get_c(int n, int m) { return 1ll * fac[n] * fav[m] % mod * fav[n - m] % mod; } int n, a, b; int ans[maxn]; int main() { scanf( %d%d%d , &n, &a, &b); fac[0] = fac[1] = 1; for (int i = 2; i <= n; ++i) fac[i] = 1ll * fac[i - 1] * i % mod; fav[n] = Pow(fac[n], mod - 2); for (int i = n; i >= 1; --i) fav[i - 1] = 1ll * fav[i] * i % mod; Solve(n - 1, ans); printf( %d n , 1ll * ans[a + b - 2] * Get_c(a + b - 2, a - 1) % mod); } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Programmable Interrupt Controller ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PIC according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// None ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_pic(
// RISC Internal Interface
clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
pic_wakeup, intr,
// PIC Interface
pic_int
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input spr_cs; // SPR CS
input spr_write; // SPR Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output pic_wakeup; // Wakeup to the PM
output intr; // interrupt
// exception request
//
// PIC Interface
//
input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs
`ifdef OR1200_PIC_IMPLEMENTED
//
// PIC Mask Register bits (or no register)
//
`ifdef OR1200_PIC_PICMR
reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
`else
wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
`endif
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
`else
wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
`endif
//
// Internal wires & regs
//
wire picmr_sel; // PICMR select
wire picsr_sel; // PICSR select
wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg [31:0] spr_dat_o; // SPR data out
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
//
// Write to PICMR
//
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
if (rst)
picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
else if (picmr_sel && spr_write) begin
picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
end
`else
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
if (rst)
picsr <= {`OR1200_PIC_INTS{1'b0}};
else if (picsr_sel && spr_write) begin
picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
end else
picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
//
// Read PIC registers
//
always @(spr_addr or picmr or picsr)
case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_PIC_READREGS
`OR1200_PIC_OFS_PICMR: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
`endif
default: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
endcase
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
//
// Generate intr
//
assign intr = |um_ints;
//
// Assert pic_wakeup when intr is asserted
//
assign pic_wakeup = intr;
`else
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign intr = pic_int[1] | pic_int[0];
assign pic_wakeup= intr;
//
// Read PIC registers
//
`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif
`endif
`endif
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_rgmii_module.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
//
// $Revision: #1 $
// $Date: 2015/02/08 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top level RGMII interface (receive and transmit) module.
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ ( // new ports to cater for mii with RGMII interface are added
// inputs
rgmii_in,
speed,
//data
gm_tx_d,
m_tx_d,
//control
gm_tx_en,
m_tx_en,
gm_tx_err,
m_tx_err,
reset_rx_clk,
reset_tx_clk,
rx_clk,
rx_control,
tx_clk,
// outputs:
rgmii_out,
gm_rx_d,
m_rx_d,
gm_rx_dv,
m_rx_en,
gm_rx_err,
m_rx_err,
m_rx_col,
m_rx_crs,
tx_control
);
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [ 3: 0] rgmii_out;
output [ 7: 0] gm_rx_d;
output [ 3: 0] m_rx_d;
output gm_rx_dv;
output m_rx_en;
output gm_rx_err;
output m_rx_err;
output m_rx_col;
output m_rx_crs;
output tx_control;
input [ 3: 0] rgmii_in;
input speed;
input [ 7: 0] gm_tx_d;
input [ 3: 0] m_tx_d;
input gm_tx_en;
input m_tx_en;
input gm_tx_err;
input m_tx_err;
input reset_rx_clk;
input reset_tx_clk;
input rx_clk;
input rx_control;
input tx_clk;
wire [ 3: 0] rgmii_out;
wire [ 7: 0] gm_rx_d;
wire gm_rx_dv;
wire m_rx_en;
wire gm_rx_err;
wire m_rx_err;
wire m_rx_col;
reg m_rx_col_reg;
reg m_rx_crs;
reg rx_dv;
reg rx_err;
wire tx_control;
//wire tx_err;
reg [ 7: 0] rgmii_out_4_wire;
reg rgmii_out_1_wire_inp1;
reg rgmii_out_1_wire_inp2;
wire [ 7:0 ] rgmii_in_4_wire;
reg [ 7:0 ] rgmii_in_4_reg;
reg [ 7:0 ] rgmii_in_4_temp_reg;
wire [ 1:0 ] rgmii_in_1_wire;
reg [ 1:0 ] rgmii_in_1_temp_reg;
wire speed_reg;
reg m_tx_en_reg1;
reg m_tx_en_reg2;
reg m_tx_en_reg3;
reg m_tx_en_reg4;
assign gm_rx_d = rgmii_in_4_reg;
assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
altera_tse_rgmii_in4 the_rgmii_in4
(
.aclr (), //INPUT
.datain (rgmii_in), //INPUT
.dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
.dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
.inclock (rx_clk) //OUTPUT
);
altera_tse_rgmii_in1 the_rgmii_in1
(
.aclr (), //INPUT
.datain (rx_control), //INPUT
.dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
.dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
.inclock (rx_clk) //OUTPUT
);
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_temp_reg <= {8{1'b0}};
rgmii_in_1_temp_reg <= {2{1'b0}};
end
else begin
rgmii_in_4_temp_reg <= rgmii_in_4_wire;
rgmii_in_1_temp_reg <= rgmii_in_1_wire;
end
end
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_reg <= {8{1'b0}};
rx_err <= 1'b0;
rx_dv <= 1'b0;
end
else begin
rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
rx_err <= rgmii_in_1_wire[0];
rx_dv <= rgmii_in_1_temp_reg[1];
end
end
always @(rx_dv or rx_err or rgmii_in_4_reg)
begin
m_rx_crs = 1'b0;
if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
begin
m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
end
end
always @(posedge tx_clk or posedge reset_tx_clk)
begin
if(reset_tx_clk == 1'b1)
begin
m_tx_en_reg1 <= 1'b0;
m_tx_en_reg2 <= 1'b0;
m_tx_en_reg3 <= 1'b0;
m_tx_en_reg4 <= 1'b0;
end
else
begin
m_tx_en_reg1 <= m_tx_en;
m_tx_en_reg2 <= m_tx_en_reg1;
m_tx_en_reg3 <= m_tx_en_reg2;
m_tx_en_reg4 <= m_tx_en_reg3;
end
end
always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
begin
m_rx_col_reg = 1'b0;
if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
begin
m_rx_col_reg = 1'b1;
end
end
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(m_rx_col_reg), //INPUT
.dout(m_rx_col));// OUTPUT
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_2(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(speed), //INPUT
.dout(speed_reg));// OUTPUT
assign gm_rx_err = rx_err ^ rx_dv;
assign gm_rx_dv = rx_dv;
assign m_rx_err = rx_err ^ rx_dv;
assign m_rx_en = rx_dv;
// mux for Out 4
always @(*)
begin
case (speed_reg)
1'b1: rgmii_out_4_wire = gm_tx_d;
1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
endcase
end
// mux for Out 1
always @(*)
begin
case (speed_reg)
1'b1:
begin
rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
end
1'b0:
begin
rgmii_out_1_wire_inp1 = m_tx_en;
rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
end
endcase
end
altera_tse_rgmii_out4 the_rgmii_out4
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
.datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
.dataout (rgmii_out), //INPUT
.outclock (tx_clk) //OUTPUT
);
//assign tx_err = gm_tx_en ^ gm_tx_err;
altera_tse_rgmii_out1 the_rgmii_out1
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_1_wire_inp1), //INPUT
.datain_l (rgmii_out_1_wire_inp2), //INPUT
.dataout (tx_control), //INPUT
.outclock (tx_clk) //OUTPUT
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<int> v(n), rank(n + 1), v1(m); for (int i = 0; i < n; i++) { cin >> v[i]; rank[v[i]] = i + 1; } for (int i = 0; i < m; i++) cin >> v1[i]; long long cnt = 0; long long pre = 0; for (int i = 0; i < m; i++) { if (rank[v1[i]] < pre) { cnt += 1; } else { int k = rank[v1[i]] - 1; k -= i; cnt += (2 * k + 1); pre = rank[v1[i]]; } } cout << cnt << endl; } } |
#include <bits/stdc++.h> using namespace std; multiset<long long> dd; long long su; long long revsum[100001]; struct tab { long long l; long long d; } arr[100001]; long long findsumoftop(long long k) { long long ans = 0; multiset<long long>::iterator it = dd.begin(); while (k--) { if (it == dd.end()) { break; } else { ans += *it; it++; } } return -ans; } bool compare(const tab& t1, const tab& t2) { return t1.l < t2.l; } int main() { long long n; cin >> n; for (long long i = 0; i < n; ++i) cin >> arr[i].l; for (long long i = 0; i < n; ++i) cin >> arr[i].d; sort(arr, arr + n, compare); for (long long i = n - 1; i >= 0; --i) revsum[i] = arr[i].d + revsum[i + 1]; long long st = 0; long long en = 1; long long ma = 300000000; while (st < n) { if (arr[st].l == arr[en].l) en++; else { long long matmp = (su - findsumoftop(en - st - 1) + revsum[en]); for (long long i = st; i < en; ++i) dd.insert(-arr[i].d), su += arr[i].d; ma = min(ma, matmp); st = en; en++; } } cout << ma << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAM32X1S.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM32X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output O,
input A0,
input A1,
input A2,
input A3,
input A4,
input D,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM32X1S";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire D_in;
wire WCLK_in;
wire WE_in;
wire [4:0] A_in;
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
`ifdef XIL_TIMING
wire D_dly;
wire WCLK_dly;
wire WE_dly;
wire [4:0] A_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign A_in = A_dly;
assign D_in = D_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign A_in = {A4, A3, A2, A1, A0};
assign D_in = D;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
reg [31:0] mem;
initial
mem = INIT;
assign O = mem[A_in];
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier) mem[A_in] <= 1'bx;
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A0 => O) = (0:0:0, 0:0:0);
(A1 => O) = (0:0:0, 0:0:0);
(A2 => O) = (0:0:0, 0:0:0);
(A3 => O) = (0:0:0, 0:0:0);
(A4 => O) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge A0, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output [5:0] data_out
);
wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
FDCE FDCE_0 (
.D (data_in),
.C (clk),
.CE (1'b1),
.CLR(1'b0),
.Q (fdce_0_out)
);
FDCE FDCE_1 (
.D (fdce_0_out),
.C (clk),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[0])
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4'd12),
.CLKFBOUT_PHASE(90.0),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4'd12),
.CLKOUT0_PHASE(90.0),
.CLKOUT1_DIVIDE(3'd6),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(2'd3),
.CLKOUT2_PHASE(90.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout_x1),
.CLKOUT1(main_clkout_x2),
.CLKOUT2(main_clkout_x4),
.LOCKED(main_locked)
);
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
.C (main_clkout_x1),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[1])
);
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
.C (main_clkout_x2),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[2])
);
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
.C (main_clkout_x2),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[3])
);
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
.C (main_clkout_x2),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[4])
);
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
.C (main_clkout_x4),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[5])
);
endmodule
|
`timescale 1ns / 1ps
//*************************************************************************
// > ÎļþÃû: single_cycle_cpu_display.v
// > ÃèÊö £ºµ¥ÖÜÆÚCPUÏÔʾģ¿é£¬µ÷ÓÃFPGA°åÉϵÄIO½Ó¿ÚºÍ´¥ÃþÆÁ
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module single_cycle_cpu_display(
//ʱÖÓÓ븴λÐźÅ
input clk,
input resetn, //ºó׺"n"´ú±íµÍµçƽÓÐЧ
//Âö³å¿ª¹Ø£¬ÓÃÓÚ²úÉúÂö³åclk£¬ÊµÏÖµ¥²½Ö´ÐÐ
input btn_clk,
//´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);
//-----{ʱÖӺ͸´Î»ÐźÅ}begin
//²»ÐèÒª¸ü¸Ä£¬ÓÃÓÚµ¥²½µ÷ÊÔ
wire cpu_clk; //µ¥ÖÜÆÚCPUÀïʹÓÃÂö³å¿ª¹Ø×÷ΪʱÖÓ£¬ÒÔʵÏÖµ¥²½Ö´ÐÐ
reg btn_clk_r1;
reg btn_clk_r2;
always @(posedge clk)
begin
if (!resetn)
begin
btn_clk_r1<= 1'b0;
end
else
begin
btn_clk_r1 <= ~btn_clk;
end
btn_clk_r2 <= btn_clk_r1;
end
wire clk_en;
assign clk_en = !resetn || (!btn_clk_r1 && btn_clk_r2);
BUFGCE cpu_clk_cg(.I(clk),.CE(clk_en),.O(cpu_clk));
//-----{ʱÖӺ͸´Î»ÐźÅ}end
//-----{µ÷Óõ¥ÖÜÆÚCPUÄ£¿é}begin
//ÓÃÓÚÔÚFPGA°åÉÏÏÔʾ½á¹û
wire [31:0] cpu_pc; //CPUµÄPC
wire [31:0] cpu_inst; //¸ÃPCÈ¡³öµÄÖ¸Áî
wire [ 4:0] rf_addr; //ɨÃè¼Ä´æÆ÷¶ÑµÄµØÖ·
wire [31:0] rf_data; //¼Ä´æÆ÷¶Ñ´Óµ÷ÊԶ˿ڶÁ³öµÄÊý¾Ý
reg [31:0] mem_addr; //Òª¹Û²ìµÄÄÚ´æµØÖ·
wire [31:0] mem_data; //ÄÚ´æµØÖ·¶ÔÓ¦µÄÊý¾Ý
single_cycle_cpu cpu(
.clk (cpu_clk ),
.resetn (resetn ),
.rf_addr (rf_addr ),
.mem_addr(mem_addr),
.rf_data (rf_data ),
.mem_data(mem_data),
.cpu_pc (cpu_pc ),
.cpu_inst(cpu_inst)
);
//-----{µ÷Óõ¥ÖÜÆÚCPUÄ£¿é}end
//---------------------{µ÷Óô¥ÃþÆÁÄ£¿é}begin--------------------//
//-----{ʵÀý»¯´¥ÃþÆÁ}begin
//´ËС½Ú²»ÐèÒª¸ü¸Ä
reg display_valid;
reg [39:0] display_name;
reg [31:0] display_value;
wire [5 :0] display_number;
wire input_valid;
wire [31:0] input_value;
lcd_module lcd_module(
.clk (clk ), //10Mhz
.resetn (resetn ),
//µ÷Óô¥ÃþÆÁµÄ½Ó¿Ú
.display_valid (display_valid ),
.display_name (display_name ),
.display_value (display_value ),
.display_number (display_number),
.input_valid (input_valid ),
.input_value (input_value ),
//lcd´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
.lcd_rst (lcd_rst ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_data_io (lcd_data_io ),
.lcd_bl_ctr (lcd_bl_ctr ),
.ct_int (ct_int ),
.ct_sda (ct_sda ),
.ct_scl (ct_scl ),
.ct_rstn (ct_rstn )
);
//-----{ʵÀý»¯´¥ÃþÆÁ}end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}begin
//¸ù¾Ýʵ¼ÊÐèÒªÊäÈëµÄÊýÐ޸ĴËС½Ú£¬
//½¨Òé¶Ôÿһ¸öÊýµÄÊäÈ룬±àдµ¥¶ÀÒ»¸öalways¿é
always @(posedge clk)
begin
if (!resetn)
begin
mem_addr <= 32'd0;
end
else if (input_valid)
begin
mem_addr <= input_value;
end
end
assign rf_addr = display_number-6'd5;
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}begin
//¸ù¾ÝÐèÒªÏÔʾµÄÊýÐ޸ĴËС½Ú£¬
//´¥ÃþÆÁÉϹ²ÓÐ44¿éÏÔʾÇøÓò£¬¿ÉÏÔʾ44×é32λÊý¾Ý
//44¿éÏÔʾÇøÓò´Ó1¿ªÊ¼±àºÅ£¬±àºÅΪ1~44£¬
always @(posedge clk)
begin
if (display_number >6'd4 && display_number <6'd37 )
begin //¿éºÅ5~36ÏÔʾ32¸öͨÓüĴæÆ÷µÄÖµ
display_valid <= 1'b1;
display_name[39:16] <= "REG";
display_name[15: 8] <= {4'b0011,3'b000,rf_addr[4]};
display_name[7 : 0] <= {4'b0011,rf_addr[3:0]};
display_value <= rf_data;
end
else
begin
case(display_number)
6'd1 : //ÏÔʾPCÖµ
begin
display_valid <= 1'b1;
display_name <= " PC";
display_value <= cpu_pc;
end
6'd2 : //ÏÔʾPCÈ¡³öµÄÖ¸Áî
begin
display_valid <= 1'b1;
display_name <= " INST";
display_value <= cpu_inst;
end
6'd3 : //ÏÔʾҪ¹Û²ìµÄÄÚ´æµØÖ·
begin
display_valid <= 1'b1;
display_name <= "MADDR";
display_value <= mem_addr;
end
6'd4 : //ÏÔʾ¸ÃÄÚ´æµØÖ·¶ÔÓ¦µÄÊý¾Ý
begin
display_valid <= 1'b1;
display_name <= "MDATA";
display_value <= mem_data;
end
default :
begin
display_valid <= 1'b0;
end
endcase
end
end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}end
//----------------------{µ÷Óô¥ÃþÆÁÄ£¿é}end---------------------//
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:29:48 01/26/2016
// Design Name: rippleCarryAdder
// Module Name: F:/VLSI Lab/Adder/rippleCarryAdderTest.v
// Project Name: Adder
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: rippleCarryAdder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module rippleCarryAdderTest;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg carryin;
// Outputs
wire [3:0] sum;
wire carryout;
reg [10:0] i;
// Instantiate the Unit Under Test (UUT)
rippleCarryAdder uut (
.a(a),
.b(b),
.carryin(carryin),
.sum(sum),
.carryout(carryout)
);
initial begin
a = 4'b0000;
b = 4'b0000;
carryin=1'b0;
end
always @(a,b)
begin
for(i=0;i<16*16*2;i=i+1)
begin
{carryin,a,b}=i;
#10;
end
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int NMax = 100005; vector<int> G[NMax]; long double Array[NMax]; int DP[NMax], N; void Read() { cin >> N; for (int i = 1; i < N; i++) { int x; cin >> x; G[x].push_back(i + 1); } } void buildDP(int node) { DP[node] = 1; for (int i = 0; i < G[node].size(); i++) { int neighb = G[node][i]; buildDP(neighb); DP[node] += DP[neighb]; } } void DFS(int node) { int sz = G[node].size(); for (int i = 0; i < G[node].size(); i++) { int neighb = G[node][i]; Array[neighb] = Array[node] + 0.5 * ((long double)DP[node] - 1.0 - DP[neighb]) + 1.0; DFS(neighb); } } void Print() { for (int i = 1; i <= N; i++) cout << fixed << setprecision(2) << Array[i] << ; cout << n ; } int main() { Read(); buildDP(1); Array[1] = 1.0; DFS(1); Print(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long ar[1005][1005], br[1005][1005], fr[555]; string s[555]; string s1, s2; int main() { long long i, j, k, m, n, r, c; while (cin >> r >> c) { getchar(); s[0] = ; for (i = 1; i <= r; i++) { getline(cin, s[i]); } n = r; if (n & 1) { cout << n << endl; continue; } while (n > 0) { i = 1; j = n; while (s[i] == s[j]) { i++, j--; if (i > j) break; } if (i > j) n /= 2; else { cout << n << endl; return 0; } if (n & 1) { cout << n << endl; return 0; } } cout << 1 << endl; } return 0; } |
`include "uart.vh"
module top(
input ice_clk_i,
input rstn_i,
input rs232_rx_i,
output [7:0] led_o,
output rs232_tx_o
);
reg tx_i_v = 0, fifo_re = 0, fifo_re_d = 0, fifo_we = 0;
reg [`UART_DATA_LENGTH - 1 : 0] fifo_d = 0, tx_i = 0;
wire clk_uart_rx, clk_uart_tx;
wire fifo_empty, rx_o_v, tx_o_v;
wire [`UART_DATA_LENGTH - 1 : 0] fifo_q, rx_o;
infra infra (
.clk_i (ice_clk_i),
.clk_o_uart_rx(clk_uart_rx),
.clk_o_uart_tx(clk_uart_tx),
.rst_i(rstn_i),
.led_o (led_o),
.rx_i(rs232_rx_i),
.rx_o(rx_o),
.rx_o_v(rx_o_v),
.tx_i(tx_i),
.tx_i_v(tx_i_v),
.tx_o(rs232_tx_o),
.tx_o_v(tx_o_v)
);
fifo#(
.DATA_WIDTH(`UART_DATA_LENGTH),
.ASYNC(1)
) fifo(
.w_clk(clk_uart_rx),
.r_clk(clk_uart_tx),
.we(fifo_we),
.d(fifo_d),
.re(fifo_re),
.q(fifo_q),
.empty(fifo_empty),
.mask(16'b0)
);
always @ (posedge clk_uart_rx)
begin
fifo_we <= rx_o_v;
fifo_d <= rx_o;
end
always @ (posedge clk_uart_tx)
begin
fifo_re <= ~fifo_empty & ~tx_o_v & ~tx_i_v & ~fifo_re & ~fifo_re_d;
fifo_re_d <= fifo_re;
tx_i <= fifo_q;
tx_i_v <= fifo_re_d;
end
endmodule // top
|
`include "defines.v"
module if_id(
input wire clk,
input wire rst,
//input
//Instruction
input wire[31:0] insAddr_i,
input wire[31:0] ins_i, //000000 00001 00010 00011 000001 00001
//Control
input wire bubble_i,
input wire pauseControl_i,
input wire flush_i,
//Exception
input wire[3:0] exception_i,
input wire[31:0] badVAddr_i,
//output
//Instruction
output reg[31:0] insAddr_o,
output reg[31:0] ins_o,
//Exception
output reg[3:0] exception_o,
output reg[31:0] badVAddr_o,
output reg insValid_o
);
wire[31:0] insAddr = insAddr_o;
wire[31:0] ins = ins_o;
wire[3:0] exception = exception_o;
wire[31:0] badVAddr = badVAddr_o;
wire insValid = insValid_o;
always @(posedge clk) begin
if (rst == `Enable) begin
insAddr_o <= `ZeroWord;
ins_o <= `ZeroWord;
exception_o <= `EXC_NONE;
badVAddr_o <= `ZeroWord;
insValid_o <= `Disable;
end else if (pauseControl_i == `PAUSE_CONTROLED) begin
insAddr_o <= insAddr;
ins_o <= ins;
exception_o <= exception;
badVAddr_o <= badVAddr;
insValid_o <= insValid;
end else if (flush_i == `Enable) begin
insAddr_o <= `ZeroWord;
ins_o <= `ZeroWord;
exception_o <= `EXC_NONE;
badVAddr_o <= `ZeroWord;
insValid_o <= `Disable;
end else if (bubble_i == `Enable) begin
insAddr_o <= insAddr;
ins_o <= ins;
exception_o <= exception;
badVAddr_o <= badVAddr;
insValid_o <= insValid;
end else begin
insAddr_o <= insAddr_i;
ins_o <= ins_i;
//ins_o <= 32'b00000000001000100001100000100001;
exception_o <= exception_i;
badVAddr_o <= badVAddr_i;
insValid_o <= `Enable;
end
end
endmodule
|
// ethernet_port_interface_0.v
// Generated using ACDS version 12.0 178 at 2012.08.08.17:01:19
`timescale 1 ps / 1 ps
module ethernet_port_interface_0 (
input wire clk, // clock.clk
input wire reset, // reset.reset
input wire [26:0] control_port_address, // control_port.address
input wire control_port_read, // .read
output wire [31:0] control_port_readdata, // .readdata
input wire control_port_write, // .write
input wire [31:0] control_port_writedata, // .writedata
output wire control_port_waitrequest, // .waitrequest
input wire [7:0] sink_data0, // avalon_streaming_sink.data
output wire sink_ready0, // .ready
input wire sink_valid0, // .valid
input wire [5:0] sink_error0, // .error
input wire sink_startofpacket0, // .startofpacket
input wire sink_endofpacket0, // .endofpacket
output wire [7:0] source_data0, // avalon_streaming_source.data
input wire source_ready0, // .ready
output wire source_valid0, // .valid
output wire source_error0, // .error
output wire source_startofpacket0, // .startofpacket
output wire source_endofpacket0 // .endofpacket
);
ethernet_port_interface ethernet_port_interface_0_inst (
.clk (clk), // clock.clk
.reset (reset), // reset.reset
.control_port_address (control_port_address), // control_port.address
.control_port_read (control_port_read), // .read
.control_port_readdata (control_port_readdata), // .readdata
.control_port_write (control_port_write), // .write
.control_port_writedata (control_port_writedata), // .writedata
.control_port_waitrequest (control_port_waitrequest), // .waitrequest
.sink_data0 (sink_data0), // avalon_streaming_sink.data
.sink_ready0 (sink_ready0), // .ready
.sink_valid0 (sink_valid0), // .valid
.sink_error0 (sink_error0), // .error
.sink_startofpacket0 (sink_startofpacket0), // .startofpacket
.sink_endofpacket0 (sink_endofpacket0), // .endofpacket
.source_data0 (source_data0), // avalon_streaming_source.data
.source_ready0 (source_ready0), // .ready
.source_valid0 (source_valid0), // .valid
.source_error0 (source_error0), // .error
.source_startofpacket0 (source_startofpacket0), // .startofpacket
.source_endofpacket0 (source_endofpacket0) // .endofpacket
);
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
/*
* This example shows how to use Icarus Verilog to generate PLD output.
* The design is intended to fit into a 22v10 in a PLCC package, with
* pin assignments locked down by design. The command to compile this
* into a jedec file is;
*
* iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v
*
* The output file name (passed through the -o<file> switch) can be
* any file you desire. If the compilation and fitting all succeed, the
* output file will be a JEDEC file that you can take to your favorite
* PROM programmer to program the part.
*
* This source demonstrates some important principles of synthesizing
* a design for a PLD, including how to specify synchronous logic, and
* how to assign signals to pins. The pin assignment in particular is
* part specific, and must be right for the fitting to succeed.
*/
/*
* The register module is an 8 bit register that copies the input to
* the output registers on the rising edge of the clk input. The
* always statement creates a simple d-type flip-flop that is loaded
* on the rising edge of the clock.
*
* The output drivers are controlled by a single active low output
* enable. I used bufif0 devices in this example, but the exact same
* thing can be achieved with a continuous assignment like so:
*
* assign out = oe? 8'hzz : Q;
*
* Many people prefer the expression form. It is true that it does
* seem to express the intent a bit more clearly.
*/
module register (out, val, clk, oe);
output [7:0] out;
input [7:0] val;
input clk, oe;
reg [7:0] Q;
wire [7:0] out;
bufif0 drv[7:0](out, Q, oe);
always @(posedge clk) Q = val;
endmodule
/*
* The module pal is used to attach pin information to all the pins of
* the device. We use this to lock down the pin assignments of the
* synthesized result. The pin number assignments are for a 22v10 in
* a PLCC package.
*
* Note that this module has no logic in it. It is a convention I use
* that I put all the functionality in a separate module (seen above)
* and isolate the Icarus Verilog specific $attribute madness into a
* top-level module. The advantage of this style is that the entire
* module can be `ifdef'ed out when doing simulation and you don't
* need to worry that functionality will be affected.
*/
module pal;
wire out7, out6, out5, out4, out3, out2, out1, out0;
wire inp7, inp6, inp5, inp4, inp3, inp2, inp1, inp0;
wire clk, oe;
// The PAD attributes attach the wires to pins of the
// device. Output pins are prefixed by a 'o', and input pins by an
// 'i'. If not all the available output pins are used, then the
// remaining are available for the synthesizer to drop internal
// registers or extra logic layers.
$attribute(out7, "PAD", "o27");
$attribute(out6, "PAD", "o26");
$attribute(out5, "PAD", "o25");
$attribute(out4, "PAD", "o24");
$attribute(out3, "PAD", "o23");
$attribute(out2, "PAD", "o21");
$attribute(out1, "PAD", "o20");
$attribute(out0, "PAD", "o19");
$attribute(inp7, "PAD", "i10");
$attribute(inp6, "PAD", "i9");
$attribute(inp5, "PAD", "i7");
$attribute(inp4, "PAD", "i6");
$attribute(inp3, "PAD", "i5");
$attribute(inp2, "PAD", "i4");
$attribute(inp1, "PAD", "i3");
$attribute(inp0, "PAD", "i2");
//$attribute(clk, "PAD", "CLK");
$attribute(oe, "PAD", "i13");
register dev({out7, out6, out5, out4, out3, out2, out1, out0},
{inp7, inp6, inp5, inp4, inp3, inp2, inp1, inp0},
clk, oe);
endmodule // pal
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: MULT_FIRSQ.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MULT_FIRSQ (
dataa,
result);
input [29:0] dataa;
output [59:0] result;
wire [59:0] sub_wire0;
wire [59:0] result = sub_wire0[59:0];
altsquare altsquare_component (
.data (dataa),
.result (sub_wire0),
.aclr (1'b0),
.clock (1'b1),
.ena (1'b1));
defparam
altsquare_component.data_width = 30,
altsquare_component.lpm_type = "ALTSQUARE",
altsquare_component.pipeline = 0,
altsquare_component.representation = "SIGNED",
altsquare_component.result_width = 60;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "30"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "60"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "30"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "60"
// Retrieval info: USED_PORT: dataa 0 0 30 0 INPUT NODEFVAL "dataa[29..0]"
// Retrieval info: USED_PORT: result 0 0 60 0 OUTPUT NODEFVAL "result[59..0]"
// Retrieval info: CONNECT: @data 0 0 30 0 dataa 0 0 30 0
// Retrieval info: CONNECT: result 0 0 60 0 @result 0 0 60 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
*@file clk_synchronizer.v
*@brief Synchronize a generated clock edge to pps
*@author LUAN Yuezhen
*@date Last edited 2016.11.15
*@tab Tab size = 4 spaces
*/
module clk_synchronizer#(
parameter SYSCLK_FREQ_HZ = 64'd100_000_000,
parameter PPS_HIGH_LEVEL_US = 64'd10_000,
parameter GENCLK_FREQ_HZ = 1,
parameter FORWARD_OFFSET_CLK = 0
)(
input clk,
input rst_n,
input pps_in,
output sync_clk_out,
output clk_sync_ok_out
);
function integer log2ceil;
input reg [63 : 0] val;
reg [63 : 0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
localparam DUTY_CNT_N = SYSCLK_FREQ_HZ * PPS_HIGH_LEVEL_US / 64'd1_000_000;
localparam DIVIDER_NUM = SYSCLK_FREQ_HZ / GENCLK_FREQ_HZ;
localparam DIVIDER_BIT = log2ceil(DIVIDER_NUM);
reg clk_sync_flag;
reg rst_release;
wire rst_pps_rst;
reg rst_pps;
reg [DIVIDER_BIT - 1 : 0] clk_divider;
wire clk_gen_forward;
reg clk_generated;
always @ (posedge pps_in or posedge rst_pps_rst)
begin
if (rst_pps_rst) begin
rst_pps <= 0;
end
else begin
rst_pps <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
rst_release <= 0;
end
else if ((rst_pps == 1) || (clk_sync_flag == 1)) begin
rst_release <= 1;
end
else begin
rst_release <= 0;
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
clk_sync_flag <= 0;
end
else if (rst_release == 1) begin
clk_sync_flag <= 1;
end
else begin
clk_sync_flag <= clk_sync_flag;
end
end
always @ (posedge clk or posedge rst_pps)
begin
if (rst_pps) begin
clk_divider <= FORWARD_OFFSET_CLK + 2;
end
else if (clk_divider < DIVIDER_NUM - 1) begin
clk_divider <= clk_divider + 1'b1;
end
else begin
clk_divider <= 0;
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
clk_generated <= 0;
end
else if (clk_sync_flag) begin
clk_generated <= clk_gen_forward;
end
else begin
clk_generated <= 0;
end
end
assign rst_pps_rst = rst_release | (~rst_n);
assign clk_gen_forward = (clk_divider < DUTY_CNT_N) ? 1'b1: 1'b0;
assign clk_sync_ok_out = clk_sync_flag;
assign sync_clk_out = clk_generated;
endmodule
|
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Tue Mar 10 2009
*
* Brief Description:
*
* Functionality:
*
* Issues:
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_switch_8port
(
clk,
rst,
fric_in0,
fric_out0,
fric_in1,
fric_out1,
fric_in2,
fric_out2,
fric_in3,
fric_out3,
fric_in4,
fric_out4,
fric_in5,
fric_out5,
fric_in6,
fric_out6,
fric_in7,
fric_out7
);
// In/Out declarations
input clk;
input rst;
input [7:0] fric_in0;
output [7:0] fric_out0;
input [7:0] fric_in1;
output [7:0] fric_out1;
input [7:0] fric_in2;
output [7:0] fric_out2;
input [7:0] fric_in3;
output [7:0] fric_out3;
input [7:0] fric_in4;
output [7:0] fric_out4;
input [7:0] fric_in5;
output [7:0] fric_out5;
input [7:0] fric_in6;
output [7:0] fric_out6;
input [7:0] fric_in7;
output [7:0] fric_out7;
// Parameters
// Regs and Wires
// RTL or Instances
/****************************************************************************
* Subblock
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
endmodule // fric_switch_8port
|
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