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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Some inputs we'll set to random values
reg [6:0] addr;
reg [6:0] e0;
reg [5:0] e1;
reg [5:0] e2;
wire [7:0] data;
reg [2:0] wrapcheck_a;
reg [2:0] wrapcheck_b;
test test (/*AUTOINST*/
// Outputs
.data (data[7:0]),
// Inputs
.addr (addr[6:0]),
.e0 (e0[6:0]),
.e1 (e1[5:0]),
.e2 (e2[5:0]));
always @(/*AS*/addr) begin
case(addr[2:0])
3'd0+3'd0: wrapcheck_a = 3'h0;
3'd0+3'd1: wrapcheck_a = 3'h1;
3'd0+3'd2: wrapcheck_a = 3'h2;
3'd0+3'd3: wrapcheck_a = 3'h3;
default: wrapcheck_a = 3'h4;
endcase
case(addr[2:0])
3'd0+0: wrapcheck_b = 3'h0;
3'd1+1: wrapcheck_b = 3'h1;
3'd2+2: wrapcheck_b = 3'h2;
3'd3+3: wrapcheck_b = 3'h3;
default: wrapcheck_b = 3'h4;
endcase
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
addr <= 7'h28;
e0 <= 7'h11;
e1 <= 6'h02;
e2 <= 6'h03;
end
if (cyc==2) begin
addr <= 7'h2b;
if (data != 8'h11) $stop;
end
if (cyc==3) begin
addr <= 7'h2c;
if (data != 8'h03) $stop;
if (wrapcheck_a != 3'h3) $stop;
if (wrapcheck_b != 3'h4) $stop;
end
if (cyc==4) begin
addr <= 7'h0;
if (data != 8'h00) $stop;
if (wrapcheck_a != 3'h4) $stop;
if (wrapcheck_b != 3'h2) $stop;
end
if (cyc==5) begin
if (data != 8'h00) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
/* verilator lint_off WIDTH */
`define AI 7'h28
module test (/*AUTOARG*/
// Outputs
data,
// Inputs
addr, e0, e1, e2
);
output [7:0] data;
input [6:0] addr;
input [6:0] e0;
input [5:0] e1, e2;
reg [7:0] data;
always @(/*AS*/addr or e0 or e1 or e2)
begin
case (addr)
`AI: data = {e0[6], 1'b0, e0[5:0]};
`AI+1: data = e1;
`AI+2,
`AI+3: data = e2;
default: data = 0;
endcase
end
endmodule
// Local Variables:
// eval:(verilog-read-defines)
// verilog-auto-sense-defines-constant: t
// End:
|
/**
* @module ID_EX
* @author sabertazimi
* @email
* @brief ID_EX pipeline register
* @input clk clock signal
* @input rst reset signal
* @input en load enable signal
* @input ID_PC PC value in ID stage
* @input ID_IR instruction value in ID stage
* @input ID_writetolo writetolo signal in ID stage
* @input ID_regwe regwe signal in ID stage
* @input ID_ramtoreg ramtoreg signal in ID stage
* @input ID_lotoreg lotoreg signal in ID stage
* @input ID_syscall syscall signal in ID stage
* @input ID_ramwe ramwe signal in ID stage
* @input ID_rambyte rambyte signal in ID stage
* @input ID_regdst regdst signal in ID stage
* @input ID_aluop aluop signal in ID stage
* @input ID_alusrc alusrcc signal in ID stage
* @input ID_extop extop signal in ID stage
* @input ID_alusham alusham signal in ID stage
* @input ID_jal jal signal in ID stage
* @input ID_rs rs value in ID stage
* @input ID_rt rt value in ID stage
* @input ID_rd rd value in ID stage
* @input ID_sham sham value in ID stage
* @input ID_imm16 imm16 value in ID stage
* @input ID_r1 r1 value in ID stage
* @input ID_r2 r2 value in ID stage
* @output EX_PC PC value in EX stage
* @output EX_IR instruction value in EX stage
* @output EX_writetolo writetolo signal in EX stage
* @output EX_regwe regwe signal in EX stage
* @output EX_ramtoreg ramtoreg signal in EX stage
* @output EX_lotoreg lotoreg signal in EX stage
* @output EX_syscall syscall signal in EX stage
* @output EX_ramwe ramwe signal in EX stage
* @output EX_rambyte rambyte signal in EX stage
* @output EX_regdst regdst signal in EX stage
* @output EX_aluop aluop signal in EX stage
* @output EX_alusrc alusrcc signal in EX stage
* @output EX_extop extop signal in EX stage
* @output EX_alusham alusham signal in EX stage
* @output EX_jal jal signal in EX stage
* @output EX_rs rs value in EX stage
* @output EX_rt rt value in EX stage
* @output EX_rd rd value in EX stage
* @output EX_sham sham value in EX stage
* @output EX_imm16 imm16 value in EX stage
* @output EX_r1 r1 value in EX stage
* @output EX_r2 r2 value in EX stage
*/
module ID_EX
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input [DATA_WIDTH-1:0] ID_PC,
input [DATA_WIDTH-1:0] ID_IR,
input ID_writetolo,
input ID_regwe,
input ID_ramtoreg,
input ID_lotoreg,
input ID_syscall,
input ID_ramwe,
input ID_rambyte,
input ID_regdst,
input [3:0] ID_aluop,
input ID_alusrc,
input ID_extop,
input ID_alusham,
input ID_jal,
input [4:0] ID_rs,
input [4:0] ID_rt,
input [4:0] ID_rd,
input [4:0] ID_sham,
input [15:0] ID_imm16,
input [DATA_WIDTH-1:0] ID_r1,
input [DATA_WIDTH-1:0] ID_r2,
output [DATA_WIDTH-1:0] EX_PC,
output [DATA_WIDTH-1:0] EX_IR,
output EX_writetolo,
output EX_regwe,
output EX_ramtoreg,
output EX_lotoreg,
output EX_syscall,
output EX_ramwe,
output EX_rambyte,
output EX_regdst,
output [3:0] EX_aluop,
output EX_alusrc,
output EX_extop,
output EX_alusham,
output EX_jal,
output [4:0] EX_rs,
output [4:0] EX_rt,
output [4:0] EX_rd,
output [4:0] EX_sham,
output [15:0] EX_imm16,
output [DATA_WIDTH-1:0] EX_r1,
output [DATA_WIDTH-1:0] EX_r2
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) PC (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_PC),
.dout(EX_PC)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) IR (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_IR),
.dout(EX_IR)
);
register #(
.DATA_WIDTH(1)
) writetolo (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_writetolo),
.dout(EX_writetolo)
);
register #(
.DATA_WIDTH(1)
) regwe (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_regwe),
.dout(EX_regwe)
);
register #(
.DATA_WIDTH(1)
) ramtoreg (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_ramtoreg),
.dout(EX_ramtoreg)
);
register #(
.DATA_WIDTH(1)
) lotoreg (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_lotoreg),
.dout(EX_lotoreg)
);
register #(
.DATA_WIDTH(1)
) syscall (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_syscall),
.dout(EX_syscall)
);
register #(
.DATA_WIDTH(1)
) ramwe (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_ramwe),
.dout(EX_ramwe)
);
register #(
.DATA_WIDTH(1)
) rambyte (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_rambyte),
.dout(EX_rambyte)
);
register #(
.DATA_WIDTH(1)
) regdst (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_regdst),
.dout(EX_regdst)
);
register #(
.DATA_WIDTH(4)
) aluop (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_aluop),
.dout(EX_aluop)
);
register #(
.DATA_WIDTH(1)
) alusrc (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_alusrc),
.dout(EX_alusrc)
);
register #(
.DATA_WIDTH(1)
) extop (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_extop),
.dout(EX_extop)
);
register #(
.DATA_WIDTH(1)
) alusham (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_alusham),
.dout(EX_alusham)
);
register #(
.DATA_WIDTH(1)
) jal (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_jal),
.dout(EX_jal)
);
register #(
.DATA_WIDTH(5)
) rs (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_rs),
.dout(EX_rs)
);
register #(
.DATA_WIDTH(5)
) rt (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_rt),
.dout(EX_rt)
);
register #(
.DATA_WIDTH(5)
) rd (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_rd),
.dout(EX_rd)
);
register #(
.DATA_WIDTH(5)
) sham (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_sham),
.dout(EX_sham)
);
register #(
.DATA_WIDTH(16)
) imm16 (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_imm16),
.dout(EX_imm16)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) r1 (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_r1),
.dout(EX_r1)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) r2 (
.clk(clk),
.rst(rst),
.en(en),
.din(ID_r2),
.dout(EX_r2)
);
endmodule // ID_EX
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// Slow VRAM is 120ns (3mclk or more, probably 3.5mclk)
module slow_cycle(
input CLK_24M,
input CLK_24MB,
input LSPC_12M,
input LSPC_6M,
input LSPC_3M,
input LSPC_1_5M,
input RESETP,
input [14:0] VRAM_ADDR,
input [15:0] VRAM_WRITE,
input REG_VRAMADDR_MSB,
input PIXEL_H8,
input PIXEL_H256,
input [7:3] RASTERC,
input [3:0] PIXEL_HPLUS,
input [7:0] ACTIVE_RD,
input nVRAM_WRITE_REQ,
input [3:0] SPR_TILEMAP,
output SPR_TILE_VFLIP,
output SPR_TILE_HFLIP,
output SPR_AA_3, SPR_AA_2,
output [11:0] FIX_TILE,
output [3:0] FIX_PAL,
output [19:0] SPR_TILE,
output [7:0] SPR_PAL,
output [15:0] VRAM_LOW_READ,
output nCPU_WR_LOW,
input R91_nQ,
output CLK_CPU_READ_LOW,
output T160A_OUT,
output T160B_OUT,
input CLK_ACTIVE_RD,
input ACTIVE_RD_PRE8,
output Q174B_OUT,
input D208B_OUT,
input SPRITEMAP_ADDR_MSB,
input CLK_SPR_TILE,
input P222A_OUT,
input P210A_OUT
);
wire [14:0] B;
wire [15:0] E;
wire [15:0] FIX_MAP_READ;
wire [14:0] FIXMAP_ADDR;
wire [14:0] SPRMAP_ADDR;
wire [3:0] D233_Q;
wire [3:0] D283_Q;
wire [3:0] Q162_Q;
// CPU read
// H251 F269 F250 D214
FDS16bit H251(~CLK_CPU_READ_LOW, E, VRAM_LOW_READ);
// Fix map read
// E233 C269 B233 B200
FDS16bit E233(Q174B_OUT, E, FIX_MAP_READ);
assign FIX_TILE = FIX_MAP_READ[11:0];
FDSCell E251(~CLK_SPR_TILE, FIX_MAP_READ[15:12], FIX_PAL);
// Sprite map read even
// H233 C279 B250 C191
FDS16bit H233(~CLK_SPR_TILE, E, SPR_TILE[15:0]);
// Sprite map read even
// D233 D283 A249 C201
FDS16bit D233(D208B_OUT, E, {D233_Q, D283_Q, SPR_TILE[19:16], SPR_AA_3, SPR_AA_2, SPR_TILE_VFLIP, SPR_TILE_HFLIP});
FDSCell C233(Q174B_OUT, D233_Q, SPR_PAL[7:4]);
FDSCell D269(Q174B_OUT, D283_Q, SPR_PAL[3:0]);
assign E = VRAM_LOW_WRITE ? VRAM_WRITE : 16'bzzzzzzzzzzzzzzzz;
// BOE and BWE outputs
FD2 Q220(CLK_24MB, nCPU_WR_LOW, Q220_Q, BOE);
FD2 R289(LSPC_12M, R287A_OUT, BWE, R289_nQ);
assign R287A_OUT = Q220_Q | R289_nQ;
assign VRAM_LOW_WRITE = ~BWE;
// Address mux
// E54A F34 F30A
// F39A J31A H39A H75A
// F206A I75A E146A N177
// N179A N182 N172A K169A
assign B = ~N165_nQ ?
~N160_Q ? SPRMAP_ADDR : 15'd0
:
~N160_Q ? FIXMAP_ADDR : VRAM_ADDR;
assign FIXMAP_ADDR = {4'b1110, O62_nQ, PIXEL_HPLUS, ~PIXEL_H8, RASTERC[7:3]};
assign SPRMAP_ADDR = {H57_Q, ACTIVE_RD, O185_Q, SPR_TILEMAP, K166_Q};
FDM O185(P222A_OUT, SPRITEMAP_ADDR_MSB, O185_Q, );
FDM H57(CLK_ACTIVE_RD, ACTIVE_RD_PRE8, H57_Q, );
FDM K166(CLK_24M, P210A_OUT, K166_Q, );
FDM N165(CLK_24M, Q174B_OUT, , N165_nQ);
FDM N160(CLK_24M, N169A_OUT, N160_Q, );
FS1 Q162(LSPC_12M, R91_nQ, Q162_Q);
assign Q174B_OUT = ~Q162_Q[3];
assign N169A_OUT = ~|{Q174B_OUT, ~CLK_CPU_READ_LOW};
FDM T75(CLK_24M, T64A_OUT, T75_Q, );
assign CLK_CPU_READ_LOW = Q162_Q[1];
assign T160B_OUT = ~|{T75_Q, ~Q162_Q[0]};
assign T160A_OUT = ~|{Q162_Q[0], T75_Q};
assign T64A_OUT = ~&{LSPC_12M, LSPC_6M, LSPC_3M};
FDPCell O62(PIXEL_H8, PIXEL_H256, 1'b1, RESETP, O62_Q, O62_nQ);
assign F58B_OUT = REG_VRAMADDR_MSB | nVRAM_WRITE_REQ;
FDPCell Q106(~LSPC_1_5M, F58B_OUT, CLK_CPU_READ_LOW, 1'b1, nCPU_WR_LOW, );
vram_slow_u VRAMLU(B, E[15:8], 1'b0, BOE, BWE);
vram_slow_l VRAMLL(B, E[7:0], 1'b0, BOE, BWE);
endmodule
|
#include <bits/stdc++.h> using namespace std; int uf[310100]; int get_fa(int x) { return uf[x] == x ? x : uf[x] = get_fa(uf[x]); } struct Edge { Edge *next; int np; int id; } E[310100 * 2], *V[310100]; int tope = -1; void add_edge(int x, int y, int id) { E[++tope].np = y; E[tope].id = id; E[tope].next = V[x]; V[x] = &E[tope]; } int qq[310100]; int pnt[310100]; int pid[310100]; void dfs(int now) { for (Edge *ne = V[now]; ne; ne = ne->next) { if (ne->np == pnt[now]) continue; pnt[ne->np] = now; pid[ne->np] = ne->id; dfs(ne->np); } } int times[310100]; void dfs2(int now) { for (Edge *ne = V[now]; ne; ne = ne->next) { if (ne->np == pnt[now]) continue; dfs2(ne->np); times[now] = (times[now] + times[ne->np]) % 2; } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , qq + i); for (int i = 0; i < n; i++) uf[i] = i; for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); x--, y--; if (get_fa(x) != get_fa(y)) { uf[get_fa(x)] = get_fa(y); add_edge(x, y, i + 1); add_edge(y, x, i + 1); } } dfs(0); vector<int> A, B; for (int i = 0; i < n; i++) { int x; x = qq[i]; if (x == 1) A.push_back(i); if (x == -1) B.push_back(i); } if (A.size() % 2 == 1) { if (B.size() == 0) { printf( -1 n ); return 0; } else { A.push_back(B.back()); B.pop_back(); } } for (int i = 0; i < A.size(); i++) times[A[i]]++; dfs2(0); int ans = 0; for (int i = 1; i < n; i++) if (times[i] == 1) ans++; printf( %d n , ans); for (int i = 1; i < n; i++) if (times[i]) printf( %d n , pid[i]); } |
`include "LookupTable.v"
module GeneralControl (
input [5:0] op_i,
input [5:0] func_i,
input is_equal_i,
output reg [1:0] PC_ctrl_o,
output reg [4:0] EX_ctrl_o,
output reg [1:0] MEM_ctrl_o,
output reg [1:0] WB_ctrl_o
);
/**
* PC_ctrl_o <= { PC_mux(2) }
* PC_mux[0] -> jump/branch, PC_mux[1] -> normal/jump,branch
*/
/**
* EX_ctrl_o <= { ALUop(3), ALUsrc(1), RegDst(1) }
* ALUsrc -> 0:register, 1:immediate
* RegDst -> 0:rt, 1:rd
*/
/**
* MEM_ctrl_o <= { MEM_cs(1), MEM_we(1) }
*/
/**
* WB_ctrl_o <= { WB_mux(1), Reg_we(1) }
* WB_mux -> 0: memory, 1:ALU
*/
always @ (*)
begin
case (op_i)
// R-type instructions needs special care.
`ADD_op, `SUB_op, `MUL_op, `AND_op, `OR_op :
begin
case (func_i)
`ADD_func:
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `ADD_alu, 1'b0, 1'b1 };
MEM_ctrl_o <= { 1'b0, 1'b0 };
WB_ctrl_o <= { 1'b1, 1'b1 };
end
`SUB_func :
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `SUB_alu, 1'b0, 1'b1 };
MEM_ctrl_o <= { 1'b0, 1'b0 };
WB_ctrl_o <= { 1'b1, 1'b1 };
end
`MUL_func :
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `MUL_alu, 1'b0, 1'b1 };
MEM_ctrl_o <= { 1'b0, 1'b0 };
WB_ctrl_o <= { 1'b1, 1'b1 };
end
`AND_func :
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `AND_alu, 1'b0, 1'b1 };
MEM_ctrl_o <= { 1'b0, 1'b0 };
WB_ctrl_o <= { 1'b1, 1'b1 };
end
`OR_func :
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `OR_alu, 1'b0, 1'b1 };
MEM_ctrl_o <= { 1'b0, 1'b0 };
WB_ctrl_o <= { 1'b1, 1'b1 };
end
default :
begin
PC_ctrl_o <= 2'b0;
EX_ctrl_o <= 5'b0;
MEM_ctrl_o <= 2'b0;
WB_ctrl_o <= 2'b0;
end
endcase
end
`ADDI_op :
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `ADD_alu, 1'b1, 1'b0 };
MEM_ctrl_o <= { 1'b0, 1'b0 };
WB_ctrl_o <= { 1'b1, 1'b1 };
end
`LW_op :
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `ADD_alu, 1'b1, 1'b0 };
MEM_ctrl_o <= { 1'b1, 1'b0 };
WB_ctrl_o <= { 1'b0, 1'b1 };
end
`SW_op :
begin
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= { `ADD_alu, 1'b1, 1'b0 };
MEM_ctrl_o <= { 1'b1, 1'b1 };
WB_ctrl_o <= { 1'b1, 1'b0 };
end
`J_op :
begin
PC_ctrl_o <= { 1'b1, 1'b0 };
EX_ctrl_o <= 5'b0;
MEM_ctrl_o <= 2'b0;
WB_ctrl_o <= 2'b0;
end
`BEQ_op :
begin
// Identify the condition.
if(is_equal_i)
PC_ctrl_o <= { 1'b1, 1'b1 };
else
PC_ctrl_o <= { 1'b0, 1'b0 };
EX_ctrl_o <= 5'b0;
MEM_ctrl_o <= 2'b0;
WB_ctrl_o <= 2'b0;
end
default:
begin
PC_ctrl_o <= 2'b0;
EX_ctrl_o <= 5'b0;
MEM_ctrl_o <= 2'b0;
WB_ctrl_o <= 2'b0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_SYMBOL_V
`define SKY130_FD_SC_LP__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 5; vector<long long> f; vector<long long> s; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long a, b; cin >> a >> b; while (a > 0) { long long rem = a % 10; a /= 10; f.push_back(rem); } while (b > 0) { long long rem = b % 10; b /= 10; s.push_back(rem); } reverse(f.begin(), f.end()); reverse(s.begin(), s.end()); long long dp[10]; memset(dp, 0, sizeof(dp)); for (auto x : f) { dp[x]++; } if (f.size() < s.size()) { sort(f.begin(), f.end(), greater<long long>()); for (auto x : f) { cout << x; } cout << endl; return 0; } bool done = 0; for (long long i = 0; i < s.size(); ++i) { long long x = s[i]; for (long long num = x; num >= 0; --num) { if (dp[num] > 0) { if (num == x) { dp[num]--; vector<long long> rem; for (long long j = 0; j < 10; ++j) { long long tmp = dp[j]; while (tmp--) { rem.push_back(j); } } sort(rem.begin(), rem.end()); bool val = 1; for (long long j = i + 1; j < s.size(); ++j) { if (rem[j - (i + 1)] > s[j]) val = 0; if (rem[j - (i + 1)] < s[j]) break; } if (!val) { dp[num]++; continue; } dp[num]++; } cout << num; if (num < x) done = 1; dp[num]--; break; } } if (done) break; } vector<long long> rem; for (long long i = 0; i < 10; ++i) { while (dp[i] > 0) { rem.push_back(i); dp[i]--; } } sort(rem.begin(), rem.end(), greater<long long>()); for (auto x : rem) { cout << x; } cout << endl; } |
`timescale 1ns / 1ps
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog Module to implement a 64-bit ripple adder
*/
module ripple_adder_64
(
input [63:0] A,
input [63:0] B,
output [63:0] SUM,
output CARRY
);
// Create wires to connect each full_adder module to another to create a ripple
wire CARRY0, CARRY1, CARRY2, CARRY3, CARRY4, CARRY5, CARRY6, CARRY7, CARRY8, CARRY9, CARRY10;
wire CARRY11, CARRY12, CARRY13, CARRY14, CARRY15, CARRY16, CARRY17, CARRY18, CARRY19, CARRY20;
wire CARRY21, CARRY22, CARRY23, CARRY24, CARRY25, CARRY26, CARRY27, CARRY28, CARRY29, CARRY30;
wire CARRY31, CARRY32, CARRY33, CARRY34, CARRY35, CARRY36, CARRY37, CARRY38, CARRY39, CARRY40;
wire CARRY41, CARRY42, CARRY43, CARRY44, CARRY45, CARRY46, CARRY47, CARRY48, CARRY49, CARRY50;
wire CARRY51, CARRY52, CARRY53, CARRY54, CARRY55, CARRY56, CARRY57, CARRY58, CARRY59, CARRY60;
wire CARRY61, CARRY62, CARRY63;
// The first carry is zero
assign CARRY0 = 1'b0;
// Sixty-Four separate full adders are combined together to perform as one 64-bit adder
full_adder op1 (A[0], B[0], CARRY0, SUM[0], CARRY1);
full_adder op2 (A[1], B[1], CARRY1, SUM[1], CARRY2);
full_adder op3 (A[2], B[2], CARRY2, SUM[2], CARRY3);
full_adder op4 (A[3], B[3], CARRY3, SUM[3], CARRY4);
full_adder op5 (A[4], B[4], CARRY4, SUM[4], CARRY5);
full_adder op6 (A[5], B[5], CARRY5, SUM[5], CARRY6);
full_adder op7 (A[6], B[6], CARRY6, SUM[6], CARRY7);
full_adder op8 (A[7], B[7], CARRY7, SUM[7], CARRY8);
full_adder op9 (A[8], B[8], CARRY8, SUM[8], CARRY9);
full_adder op10 (A[9], B[9], CARRY9, SUM[9], CARRY10);
full_adder op11 (A[10], B[10], CARRY10, SUM[10], CARRY11);
full_adder op12 (A[11], B[11], CARRY11, SUM[11], CARRY12);
full_adder op13 (A[12], B[12], CARRY12, SUM[12], CARRY13);
full_adder op14 (A[13], B[13], CARRY13, SUM[13], CARRY14);
full_adder op15 (A[14], B[14], CARRY14, SUM[14], CARRY15);
full_adder op16 (A[15], B[15], CARRY15, SUM[15], CARRY16);
full_adder op17 (A[16], B[16], CARRY16, SUM[16], CARRY17);
full_adder op18 (A[17], B[17], CARRY17, SUM[17], CARRY18);
full_adder op19 (A[18], B[18], CARRY18, SUM[18], CARRY19);
full_adder op20 (A[19], B[19], CARRY19, SUM[19], CARRY20);
full_adder op21 (A[20], B[20], CARRY20, SUM[20], CARRY21);
full_adder op22 (A[21], B[21], CARRY21, SUM[21], CARRY22);
full_adder op23 (A[22], B[22], CARRY22, SUM[22], CARRY23);
full_adder op24 (A[23], B[23], CARRY23, SUM[23], CARRY24);
full_adder op25 (A[24], B[24], CARRY24, SUM[24], CARRY25);
full_adder op26 (A[25], B[25], CARRY25, SUM[25], CARRY26);
full_adder op27 (A[26], B[26], CARRY26, SUM[26], CARRY27);
full_adder op28 (A[27], B[27], CARRY27, SUM[27], CARRY28);
full_adder op29 (A[28], B[28], CARRY28, SUM[28], CARRY29);
full_adder op30 (A[29], B[29], CARRY29, SUM[29], CARRY30);
full_adder op31 (A[30], B[30], CARRY30, SUM[30], CARRY31);
full_adder op32 (A[31], B[31], CARRY31, SUM[31], CARRY32);
full_adder op33 (A[32], B[32], CARRY32, SUM[32], CARRY33);
full_adder op34 (A[33], B[33], CARRY33, SUM[33], CARRY34);
full_adder op35 (A[34], B[34], CARRY34, SUM[34], CARRY35);
full_adder op36 (A[35], B[35], CARRY35, SUM[35], CARRY36);
full_adder op37 (A[36], B[36], CARRY36, SUM[36], CARRY37);
full_adder op38 (A[37], B[37], CARRY37, SUM[37], CARRY38);
full_adder op39 (A[38], B[38], CARRY38, SUM[38], CARRY39);
full_adder op40 (A[39], B[39], CARRY39, SUM[39], CARRY40);
full_adder op41 (A[40], B[40], CARRY40, SUM[40], CARRY41);
full_adder op42 (A[41], B[41], CARRY41, SUM[41], CARRY42);
full_adder op43 (A[42], B[42], CARRY42, SUM[42], CARRY43);
full_adder op44 (A[43], B[43], CARRY43, SUM[43], CARRY44);
full_adder op45 (A[44], B[44], CARRY44, SUM[44], CARRY45);
full_adder op46 (A[45], B[45], CARRY45, SUM[45], CARRY46);
full_adder op47 (A[46], B[46], CARRY46, SUM[46], CARRY47);
full_adder op48 (A[47], B[47], CARRY47, SUM[47], CARRY48);
full_adder op49 (A[48], B[48], CARRY48, SUM[48], CARRY49);
full_adder op50 (A[49], B[49], CARRY49, SUM[49], CARRY50);
full_adder op51 (A[50], B[50], CARRY50, SUM[50], CARRY51);
full_adder op52 (A[51], B[51], CARRY51, SUM[51], CARRY52);
full_adder op53 (A[52], B[52], CARRY52, SUM[52], CARRY53);
full_adder op54 (A[53], B[53], CARRY53, SUM[53], CARRY54);
full_adder op55 (A[54], B[54], CARRY54, SUM[54], CARRY55);
full_adder op56 (A[55], B[55], CARRY55, SUM[55], CARRY56);
full_adder op57 (A[56], B[56], CARRY56, SUM[56], CARRY57);
full_adder op58 (A[57], B[57], CARRY57, SUM[57], CARRY58);
full_adder op59 (A[58], B[58], CARRY58, SUM[58], CARRY59);
full_adder op60 (A[59], B[59], CARRY59, SUM[59], CARRY60);
full_adder op61 (A[60], B[60], CARRY60, SUM[60], CARRY61);
full_adder op62 (A[61], B[61], CARRY61, SUM[61], CARRY62);
full_adder op63 (A[62], B[62], CARRY62, SUM[62], CARRY63);
full_adder op64 (A[63], B[63], CARRY63, SUM[63], CARRY);
endmodule
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog Module for the full adder module that will be used in the 64-bit ripple adder
*/
module full_adder
(
input A,
input B,
input CARRY_IN,
output SUM,
output CARRY_OUT
);
// Declaring wires for gate connections
wire tmpSum;
wire tmp1;
wire tmp1n;
wire tmp2;
wire tmp2n;
wire tmp3;
wire tmp4;
wire tmp5;
wire tmp6;
// Using two XOR gates with 2 inputs per gate to compute the SUM bit output
xor A1 (tmpSum, A, B);
xor A2 (SUM, CARRY_IN, tmpSum);
// Using various AND, NOT and OR gates with 2 inputs per gate to compute the CARRY_OUT bit
not B1N (tmp1n, B);
and B1 (tmp1, A, tmp1n);
not B2N (tmp2n, A);
and B2 (tmp2, tmp2n, B);
and B3 (tmp3, A, B);
and B4 (tmp4, tmp1, CARRY_IN);
and B5 (tmp5, tmp2, CARRY_IN);
or B6 (tmp6, tmp4, tmp5);
or B7 (CARRY_OUT, tmp6, tmp3);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int M = 2e3 + 5; const int INF = 0x7fffffff; const int mod = 998244353; const double eps = 1e-8; const double pi = acos(-1); int n, m; char str[N]; int f[N][26]; template <class T> inline void read(T &x) { char c; x = 1; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) x = -1; T res = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) res = res * 10 + c - 0 ; x *= res; } int main() { scanf( %s , str + 1); read(n); int len = strlen(str + 1); for (int i = 1; i <= len; i++) { for (int j = 0; j <= 25; j++) { if (str[i] - a == j) f[i][j] = f[i - 1][j] + 1; else f[i][j] = f[i - 1][j]; } } while (n--) { int l, r; read(l); read(r); int cnt = 0; for (int i = 0; i <= 25; i++) { if (f[r][i] - f[l - 1][i] > 0) cnt++; } if ((cnt >= 3) || (l == r) || (str[l] != str[r])) cout << Yes n ; else cout << No n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; cout << (n % 4 == 0 ? YES : NO ) << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file oam.v when simulating
// the core, oam. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module oam(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [7 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [7 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; struct E { int to, col, time, ind; E(int to, int col, int time, int ind) : to(to), col(col), time(time), ind(ind) {} }; int n, m, cnt; vector<E> g[50000]; int a[50000], b[50000], c[50000], d[50000], t[50000]; map<int, pair<int, int> > colInd; const int INF = 1e9 + 99; vector<int> sat[311111], rev[311111], tmp[311111], ord; bool used[311111]; int cmp[311111], curCmp; void dfs1(int v) { used[v] = true; for (int to : sat[v]) if (!used[to]) { dfs1(to); } ord.push_back(v); } void dfs2(int v) { cmp[v] = curCmp; for (int to : rev[v]) if (cmp[to] == -1) { dfs2(to); } } bool solve(int bound) { for (int i = 0; i < (int)(cnt << 1); ++i) sat[i] = tmp[i]; for (int i = 0; i < (int)(m); ++i) if (t[i] > bound) { sat[i << 1].push_back((i << 1) | 1); } for (int i = 0; i < (int)(cnt << 1); ++i) rev[i].clear(); for (int i = 0; i < (int)(cnt << 1); ++i) for (int to : sat[i]) { rev[to].push_back(i); } for (int i = 0; i < (int)(cnt << 1); ++i) used[i] = false; ord.clear(); for (int i = 0; i < (int)(cnt << 1); ++i) if (!used[i]) { dfs1(i); } reverse(ord.begin(), ord.end()); for (int i = 0; i < (int)(cnt << 1); ++i) cmp[i] = -1; curCmp = 0; for (int i : ord) if (cmp[i] == -1) { dfs2(i); ++curCmp; } for (int i = 0; i < (int)(cnt); ++i) if (cmp[i << 1] == cmp[(i << 1) | 1]) { return false; } return true; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < (int)(m); ++i) { int from, to, c, tt; scanf( %d%d%d%d , &from, &to, &c, &tt), --from, --to; g[from].push_back(E(to, c, tt, i)); g[to].push_back(E(from, c, tt, i)); t[i] = tt; } for (int i = 0; i < (int)(n); ++i) { a[i] = -1; for (E e : g[i]) { auto it = colInd.find(e.col); if (it != colInd.end()) { if (a[i] != -1) { printf( No n ); return 0; } a[i] = it->second.first; b[i] = e.ind; c[i] = it->second.second; d[i] = e.time; } else { colInd[e.col] = make_pair(e.ind, e.time); } } colInd.clear(); } int lo = 0, hi = 0, mid; for (int i = 0; i < (int)(n); ++i) if (a[i] != -1) { lo = max(lo, min(c[i], d[i])); hi = max(hi, max(c[i], d[i])); } if (hi == 0) { printf( Yes n0 0 n ); return 0; } cnt = m; for (int i = 0; i < (int)(n); ++i) if ((int)g[i].size() > 1) { for (int j = 0; j < (int)((int)g[i].size() - 1); ++j) { tmp[g[i][j].ind << 1].push_back((cnt + j) << 1); tmp[((cnt + j) << 1) | 1].push_back((g[i][j].ind << 1) | 1); } for (int j = 0; j < (int)((int)g[i].size() - 2); ++j) { tmp[(cnt + j) << 1].push_back((cnt + j + 1) << 1); tmp[((cnt + j + 1) << 1) | 1].push_back(((cnt + j) << 1) | 1); } for (int j = 1; j < (int)g[i].size(); ++j) { tmp[g[i][j].ind << 1].push_back(((cnt + j - 1) << 1) | 1); tmp[(cnt + j - 1) << 1].push_back((g[i][j].ind << 1) | 1); } cnt += (int)g[i].size() - 1; } for (int i = 0; i < (int)(n); ++i) if (a[i] != -1) { tmp[(a[i] << 1) | 1].push_back(b[i] << 1); tmp[(b[i] << 1) | 1].push_back(a[i] << 1); } while (lo < hi) { mid = (lo + hi) >> 1; if (solve(mid)) { hi = mid; } else { lo = mid + 1; } } if (solve(lo)) { printf( Yes n ); vector<int> ans; for (int i = 0; i < (int)(m); ++i) if (cmp[(i << 1) | 1] < cmp[i << 1]) { ans.push_back(i); } printf( %d %d n , lo, (int)ans.size()); for (int x : ans) printf( %d , x + 1); printf( n ); } else { printf( No n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, p, a; cin >> n >> k >> p; if (n % 2 && k) { n--; k--; } if (2 * k > n) { long long t = 2 * k - n; n -= t; k -= t; } while (p--) { cin >> a; if ((a > n) || ((a % 2 == 0) && ((n - a) / 2 < k))) putchar( X ); else putchar( . ); } } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double EPS = 1e-9; const int N = (1 << 15); const int OO = 200000; struct edge { int from, to, w; edge(int from, int to, int w) : from(from), to(to), w(w) {} bool operator<(const edge& e) const { return w < e.w; } }; struct UnionFind { vector<int> rank, parent; int forests; UnionFind(int n) { rank = vector<int>(n); parent = vector<int>(n); int forests = n; for (int i = 0; i < n; i++) parent[i] = i, rank[i] = 1; } int find_set(int x) { if (x == parent[x]) return x; return parent[x] = find_set(parent[x]); } void link(int x, int y) { if (rank[x] > rank[y]) swap(x, y); parent[x] = y; rank[y] += rank[x]; } bool union_sets(int x, int y) { x = find_set(x), y = find_set(y); if (x != y) { link(x, y); forests--; } return x != y; } long long same_set(int x, int y) { x = find_set(x), y = find_set(y); if (x == y) return 0; long long t = (long long)rank[x] * rank[y]; link(x, y); forests--; return t; } vector<vector<int>> connected_components() { vector<vector<int>> list(((int)(parent).size())); for (int i = 0; i < ((int)(parent).size()); i++) { list[find_set(i)].push_back(i); } return list; } }; vector<edge> edgeList; long long a[100005]; int main() { long long n, m, b, c; cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) { cin >> b >> c; edgeList.push_back(edge(b - 1, c - 1, min(a[b - 1], a[c - 1]))); } UnionFind uf(n); double mstCost = 0; priority_queue<edge> q; for (int i = 0; i < edgeList.size(); i++) q.push(edgeList[i]); while (!q.empty()) { edge e = q.top(); q.pop(); mstCost += uf.same_set(e.from, e.to) * e.w; } cout << fixed << setprecision(6) << 2 * mstCost / (n * (n - 1)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_1_V
`define SKY130_FD_SC_LP__DLYGATE4S50_1_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog wrapper for dlygate4s50 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlygate4s50.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlygate4s50_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlygate4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlygate4s50_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlygate4s50 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100000 + 10; map<long long, long long> mp; int main() { long long n, k, p, x, ans = 0; scanf( %lld%lld%lld , &n, &p, &k); for (long long i = 0; i < n; ++i) { scanf( %lld , &x); mp[((x * x % p * x % p * x % p - x * k % p) % p + p) % p]++; } for (auto e : mp) { x = e.second; ans += x * (x - 1) / 2; } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLRBP_PP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int mod = 1000000007; long long int gcd(long long int a, long long int b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a * b / gcd(a, b); } long long int bpow(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } long long int fact(long long int n) { if ((n == 0) || (n == 1)) return 1; else return n * fact(n - 1); } void go() {} int main() { go(); ios::sync_with_stdio(0); cin.tie(NULL); std::cout.tie(NULL); long long int n, m; cin >> n >> m; long long int minm = 0, maxm = 0; long long int modulo = n % m; long long int bukets = n / m; minm += (modulo * (bukets * (bukets + 1) / 2)); minm += ((m - modulo) * (bukets * (bukets - 1) / 2)); n -= (m - 1); maxm += (n * (n - 1) / 2); cout << minm << << maxm << n ; } |
#include <bits/stdc++.h> using namespace std; bool cmp(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { return a.second < b.second; } int main() { long long int n, k, ai, bi, total = 0, ans = 0; vector<long long int> a; vector<pair<long long int, long long int> > ab; map<long long int, long long int> jobs; scanf( %lld %lld , &n, &k); for (int i = 0; i < n; i++) { scanf( %lld , &ai), a.push_back(ai), jobs[ai]++; if (jobs[ai] == 1) total++; } for (int i = 0; i < n; i++) scanf( %lld , &bi), ab.push_back(make_pair(a[i], bi)); sort(ab.begin(), ab.end(), cmp); total = k - total; for (int i = 0; i < n; i++) { if (jobs[ab[i].first] > 1 && total > 0) { ans += ab[i].second; total--; jobs[ab[i].first]--; } } printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int maxn = 2e5 + 1; void solve() { string s, even, odd; cin >> s; for (long long int i = 0; i < s.length(); i++) { long long int val = s[i] - 0 ; if (val % 2 == 0) even += s[i]; else odd += s[i]; } if (odd.length() == 0) { cout << even << n ; } else if (even.length() == 0) { cout << odd << n ; } else { long long int n1 = odd.length(), n2 = even.length(); long long int i = 0, j = 0; while (i < n1 && j < n2) { if (odd[i] < even[j]) { cout << odd[i]; i++; } else if (odd[i] > even[j]) { cout << even[j]; j++; } else { cout << odd[i] << even[j]; i++; j++; } } while (i < n1) { cout << odd[i]; i++; } while (j < n2) { cout << even[j]; j++; } cout << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int T = 1, p = 0; cin >> T; do { solve(); p++; } while (p < T); return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int va, num; bool operator<(const node &o) const { return va < o.va; } } a[100005]; int n, m, nub, lastnode, nextnode, now; int mark[400005], mm; int ans[400005], co; vector<int> save[400005]; void dfs(int h) { mark[h] = 1; for (int i = 0; i < save[h].size(); i++) { if (mark[save[h][i]] == 1) { mm = 1; return; } if (mark[save[h][i]] == 0) { dfs(save[h][i]); } } ans[co] = h; co++; mark[h] = 2; } int main() { scanf( %d %d , &n, &m); nub = m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %d , &a[j].va); a[j].num = j; } sort(&a[0], &a[m]); lastnode = -1; for (int j = 0; j < m; j++) { if (a[j].va == -1) continue; nub++; nextnode = nub; now = a[j].va; while (j < m && a[j].va == now) { if (lastnode != -1) { save[lastnode].push_back(a[j].num); } save[a[j].num].push_back(nextnode); j++; } j--; lastnode = nextnode; } } for (int i = 0; i <= nub; i++) { if (!mark[i]) { dfs(i); } } if (mm) { printf( -1 n ); } else { for (int i = co - 1; i >= 0; i--) { if (ans[i] < m) { printf( %d , ans[i] + 1); } } printf( n ); } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; if (n / k % 2 == 0) { cout << NO ; } else { cout << YES ; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { long long w, id; bool friend operator<(node a, node b) { if (a.w == b.w) return a.id < b.id; else return a.w < b.w; } } a[1000004]; long long b[1000004][4]; long long l[1000004]; long long r[1000004]; int main() { long long n, x; cin >> n >> x; for (int i = 1; i <= n; ++i) { scanf( %lld , &a[i].w); a[i].id = i; } sort(a + 1, a + 1 + n); long long cnt = 1; b[cnt][0] = b[cnt][1] = a[1].id; b[cnt][3] = a[1].w; for (int i = 2; i <= n; ++i) { if (a[i].w == a[i - 1].w) b[cnt][1] = a[i].id; else { cnt++; b[cnt][0] = b[cnt][1] = a[i].id; b[cnt][3] = a[i].w; } } long long ans = 0; long long base = 0; long long lmax = 1; long long rmin = cnt; for (int i = 1; i <= cnt; ++i) { if (b[i][0] > base) { base = b[i][1]; l[i] = base; lmax = i; } else break; } base = 1e9; for (int i = cnt; i >= 1; --i) { if (b[i][1] < base) { base = b[i][0]; r[i] = base; rmin = i; } else break; } if (lmax < rmin) { for (int i = 1; i <= lmax; ++i) { int pos = upper_bound(r + (int)rmin, r + (int)cnt + 1, l[i]) - r; if (pos < cnt + 1) ans += (b[cnt][3] - b[pos - 1][3]) * (b[i + 1][3] - b[i][3]); } cout << ans + (x - b[cnt][3] + 1) * b[lmax + 1][3] + (b[cnt][3] - b[rmin - 1][3]) * b[1][3]; } else { cout << x * (x + 1) / 2 << endl; } } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const int maxn = 1e5 + 5; long long a[15], b[15]; int main() { for (int i = 0; i < 14; ++i) { cin >> a[i]; } long long ans = 0; for (int i = 0; i < 14; ++i) { if (a[i] == 0) continue; for (int j = 0; j < 14; ++j) b[j] = a[j]; b[i] = 0; for (int j = 0; j < 14; ++j) b[j] += a[i] / 14; long long tmp = a[i] % 14; int now = (i + 1) % 14; while (tmp--) { ++b[now]; now = (now + 1) % 14; } long long ans1 = 0; for (int j = 0; j < 14; ++j) { if (b[j] & 1) continue; ans1 += b[j]; } ans = max(ans, ans1); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n, m, len[maxn << 2]; bool first[maxn << 2]; long long mm[maxn], rr[maxn], ss[maxn], last[maxn << 2]; vector<long long> summ[maxn << 2], sumr[maxn << 2]; vector<int> tree[maxn << 2]; bool cmp(int a, int b) { return mm[a] * rr[b] < mm[b] * rr[a]; } void build(int cur, int l, int r) { len[cur] = 0; first[cur] = true, last[cur] = -1; tree[cur].clear(); tree[cur].push_back(0); for (int i = l; i <= r; i++) if (mm[i] != 0 && rr[i] != 0) tree[cur].push_back(i), len[cur]++; sort(tree[cur].begin() + 1, tree[cur].end(), cmp); summ[cur].clear(); sumr[cur].clear(); summ[cur].push_back(0); sumr[cur].push_back(0); long long sr = 0, sm = 0; for (int i = 1; i <= len[cur]; i++) { sr += rr[tree[cur][i]]; sm += mm[tree[cur][i]]; sumr[cur].push_back(sr); summ[cur].push_back(sm); } if (l != r) { build((cur << 1), l, ((l + r) >> 1)); build((cur << 1 | 1), ((l + r) >> 1) + 1, r); } } int find(int cur, long long t) { int l = 1, r = len[cur]; while (l <= r) { if (t * rr[tree[cur][((l + r) >> 1)]] >= mm[tree[cur][((l + r) >> 1)]]) l = ((l + r) >> 1) + 1; else r = ((l + r) >> 1) - 1; } return l - 1; } long long ask(int cur, int l, int r, long long t) { if (l == r && first[cur]) { long long ret = min(mm[l], t * rr[l] + ss[l]); ss[l] = 0, first[cur] = false; return ret; } if (last[cur] != -1) { long long delta = t - last[cur]; int mid = find(cur, delta); long long ret = 0; ret += summ[cur][mid]; ret += (sumr[cur][len[cur]] - sumr[cur][mid]) * delta; return ret; } long long ret = 0; ret += ask((cur << 1), l, ((l + r) >> 1), t); ret += ask((cur << 1 | 1), ((l + r) >> 1) + 1, r, t); return ret; } void down(int cur) { if (last[cur] != -1) { first[(cur << 1)] = first[(cur << 1 | 1)] = false; last[(cur << 1)] = last[(cur << 1 | 1)] = last[cur]; last[cur] = -1; } } long long query(int cur, int l, int r, int ql, int qr, long long t) { if (ql <= l && r <= qr) { long long ret = ask(cur, l, r, t); first[cur] = false, last[cur] = t; return ret; } down(cur); long long ret = 0; if (ql <= ((l + r) >> 1)) ret += query((cur << 1), l, ((l + r) >> 1), ql, qr, t); if (qr > ((l + r) >> 1)) ret += query((cur << 1 | 1), ((l + r) >> 1) + 1, r, ql, qr, t); return ret; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d%I64d%I64d , &ss[i], &mm[i], &rr[i]); build(1, 1, n); scanf( %d , &m); int qq = 0; while (m--) { ++qq; int t, l, r; scanf( %d%d%d , &t, &l, &r); printf( %I64d n , query(1, 1, n, l, r, t)); } return 0; } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program is designed to test non-constant bit selects in the
* concatenated l-value of procedural assignment.
*/
module main;
reg [3:0] vec;
reg a;
integer i;
initial begin
vec = 4'b0000;
a = 0;
if (vec !== 4'b0000) begin
$display("FAILED -- initialized vec to %b", vec);
$finish;
end
for (i = 0 ; i < 4 ; i = i + 1) begin
#1 { a, vec[i] } <= i;
end
#1 if (vec !== 4'b1010) begin
$display("FAILED == vec (%b) is not 1010", vec);
$finish;
end
if (a !== 1'b1) begin
$display("FAILED -- a (%b) is not 1", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > adj(2001); int match[2001 + 1], dis[2001 + 1]; bool visited[2001 + 1], minimumVertexCover[2001], maximumIndependentSet[2001]; const int inf = 1E9; void ResetVisited() { for (int i = 0; i <= 2001; ++i) { visited[i] = 0; } } bool BFS(vector<int> &U) { queue<int> Q; for (auto u : U) { if (match[u] == 2001) { dis[u] = 0; Q.push(u); } else { dis[u] = inf; } } dis[2001] = inf; while (!Q.empty()) { int u = Q.front(); Q.pop(); visited[u] = 1; if (dis[u] < dis[2001]) { for (auto v : adj[u]) { if (dis[match[v]] == inf) { visited[v] = 1; dis[match[v]] = 1 + dis[u]; Q.push(match[v]); } } } } return (dis[2001] != inf); } bool DFS(int u) { if (u == 2001) { return true; } for (auto v : adj[u]) { if (dis[match[v]] == 1 + dis[u]) { if (DFS(match[v])) { match[v] = u; match[u] = v; return true; } } } dis[u] = inf; return false; } int HopcroftKarpMaximumMatching(vector<int> &U, vector<int> &V) { for (auto u : U) { match[u] = 2001; } for (auto v : V) { match[v] = 2001; } int matching = 0; for (ResetVisited(); BFS(U); ResetVisited()) { for (auto u : U) { if (match[u] == 2001) { matching += DFS(u); } } } return matching; } void FillMinimumVertexCover(vector<int> &U, vector<int> &V) { for (auto u : U) { minimumVertexCover[u] = (match[u] != 2001 && visited[u] == 0); } for (auto v : V) { minimumVertexCover[v] = (match[v] != 2001 && visited[v] == 1); } } void FillMaximumIndependentSet(vector<int> &U, vector<int> &V) { for (auto u : U) { maximumIndependentSet[u] = (match[u] == 2001 || visited[u] == 1); } for (auto v : V) { maximumIndependentSet[v] = (match[v] == 2001 || visited[v] == 0); } } vector<tuple<int, int, int> > segments; vector<int> AddSegments(vector<pair<int, int> > v) { vector<int> V; sort(v.begin(), v.end()); for (int i = 0; i < v.size() - 1; ++i) { if (v[i + 1].first == v[i].first) { V.push_back(segments.size()); segments.push_back(make_tuple(v[i].first, v[i].second, v[i + 1].second)); } } return V; } bool DoSegmentsIntersect(int i, int j) { int x, y1, y2, y, x1, x2; tie(x, y1, y2) = segments[i]; tie(y, x1, x2) = segments[j]; return (x1 < x && x < x2 && y1 < y && y < y2); } vector<tuple<int, int, int, int> > MakeAnswerSegments( vector<int> &V, vector<pair<int, int> > &P, bool isHorizontal) { vector<tuple<int, int, int> > v; for (auto i : V) { if (maximumIndependentSet[i]) { v.push_back(segments[i]); } } for (auto p : P) { v.push_back(make_tuple(p.first, p.second, p.second)); } sort(v.begin(), v.end()); vector<tuple<int, int, int, int> > ans; for (int i = 0, j; i < v.size(); i = j) { int x, y1, y2; tie(x, y1, y2) = v[i]; for (j = i + 1; j < v.size(); ++j) { int nx, ny1, ny2; tie(nx, ny1, ny2) = v[j]; if (nx == x && ny1 == y2) { y2 = ny2; } else { break; } } if (isHorizontal) { ans.push_back(make_tuple(y1, x, y2, x)); } else { ans.push_back(make_tuple(x, y1, x, y2)); } } return ans; } void PrintAnswerSegments(vector<tuple<int, int, int, int> > &ans) { printf( %lu n , ans.size()); for (auto t : ans) { int x1, y1, x2, y2; tie(x1, y1, x2, y2) = t; printf( %d %d %d %d n , x1, y1, x2, y2); } } int main() { int n; vector<pair<int, int> > xyPoints, yxPoints; cin >> n; while (n--) { int x, y; cin >> x >> y; xyPoints.push_back(make_pair(x, y)); yxPoints.push_back(make_pair(y, x)); } vector<int> U = AddSegments(xyPoints); vector<int> V = AddSegments(yxPoints); for (auto u : U) { for (auto v : V) { if (DoSegmentsIntersect(u, v)) { adj[u].push_back(v); } } } HopcroftKarpMaximumMatching(U, V); FillMaximumIndependentSet(U, V); vector<tuple<int, int, int, int> > horizontalSegments = MakeAnswerSegments(V, yxPoints, 1); vector<tuple<int, int, int, int> > verticalSegments = MakeAnswerSegments(U, xyPoints, 0); PrintAnswerSegments(horizontalSegments); PrintAnswerSegments(verticalSegments); return 0; } |
module timer(ssd_out,clk,reset);
input clk,reset;
output [6:0] ssd_out;
reg [25:0] ticker;
reg [3:0] counter;
wire [3:0] ssd_in;
assign ssd_in = counter;
seven_seg_decoder ssd(ssd_out,ssd_in);
initial
begin
ticker = 49999999;
counter = 15;
end
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
ticker <= 49999999;
counter <= 15;
end
else
begin
ticker <= ticker - 1;
if (ticker == 0)
begin
ticker <= 49999999;
counter <= counter-1;
end
end
end
endmodule
module seven_seg_decoder(led_out,bin_in);
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
/* A => bin_in[3]
* B => bin_in[2]
* C => bin_in[1]
* D => bin_in[0]
*/
// note: tmp variables use implicit nets
//led_out[6] = A’B’C’ + A’BCD + ABC’D’
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
//led_out[5] = A’B’D + A’B’C + A’CD +ABC’D
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[4] = A’D + B’C’D + A’BC’
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
//led_out[3] = B’C’D + BCD + A’BC’D’ + AB’CD’
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[2] = ABD’ + ABC + A’B’CD’
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[1] = BCD’ + ACD + ABD’ + A’BC’D
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[0] = A’B’C’D + A’BC’D’ + AB’CD + ABC’D
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Intel FPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board.
// Input buffer map
module \$__inpad (input I, output O);
cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(1'b1),
.datad(1'b1));
end else
if(WIDTH == 3) begin
cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(1'b1));
end else
if(WIDTH == 4) begin
cyclone10lp_lcell_comb #(.lut_mask(LUT),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: MossbauerLab
// Engineer: EvilLord666 (Ushakov MV)
//
// Create Date: 01:41:52 01/09/2019
// Design Name:
// Module Name: messbauer_saw_tooth_generator
// Project Name: messbauer_test_environment
// Target Devices:
// Tool versions: ISE 14.7
// Description: ALINX AX309 Board Messbauer Generator
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`ifndef MAX_CHANNEL_NUMBER
`define MAX_CHANNEL_NUMBER 4096
`endif
module messbauer_saw_tooth_generator #
(
parameter GCLK_PERIOD = 20,
parameter DIRECT_SLOPE_DURATION = 512, // number of messbauer channels 4 code generation during direct motion
parameter CHANNEL_DURATION = (16 * (`MAX_CHANNEL_NUMBER / DIRECT_SLOPE_DURATION)) * 1000 / (2 * GCLK_PERIOD),
parameter REVERSE_SLOPE_DURATION = (15464000 / (2 * GCLK_PERIOD)) / CHANNEL_DURATION , // number of messbauer pseudo channels during reverse motion (channel does not actually generates) 15,464 ms
parameter DATA_WIDTH = 12
)
(
input wire clk,
input wire areset_n,
output reg [DATA_WIDTH-1:0] out_value
);
localparam RATIO_SLOPE_DURATOIN = DIRECT_SLOPE_DURATION / REVERSE_SLOPE_DURATION;
reg dir;
reg [15:0] counter;
always @ (posedge clk)
begin
if (!areset_n)
begin
out_value <= 0;
counter <=0;
dir <= 0;
end
else
begin
counter <= counter + 1;
if(dir == 0)
begin
if (counter == CHANNEL_DURATION)
begin
out_value <= out_value + 1;
counter <= 0;
end
if(out_value == DIRECT_SLOPE_DURATION)
dir <= 1;
end
else
begin
if (counter == CHANNEL_DURATION)
begin
out_value <= out_value > RATIO_SLOPE_DURATOIN ? out_value - RATIO_SLOPE_DURATOIN : 0;
counter <= 0;
end
if(out_value == 0)
dir <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class t> inline void read(t& res) { char ch; while (ch = getchar(), !isdigit(ch)) ; res = ch ^ 48; while (ch = getchar(), isdigit(ch)) res = res * 10 + (ch ^ 48); } template <class t> inline void print(t x) { if (x > 9) print(x / 10); putchar(x % 10 + 48); } const int e = 3e5 + 5, z1 = 29, z2 = 31, h1 = 1e9 + 7, h2 = 1e9 + 9; struct node { int s1, s2, len; node() {} node(int _s1, int _s2, int _len) : s1(_s1), s2(_s2), len(_len) {} } up[e], down[e]; vector<int> a[e], b[e], g[e]; int n, top[e], son[e], m, f[20][e], dep[e], mx[e]; int p1[e], p2[e], fa[e], dfn[e], id[e << 1], tim, logn[e << 1], c[21][e << 1]; int q1[e], q2[e], inv1, inv2; char s[e]; inline bool operator==(node a, node b) { return a.s1 == b.s1 && a.s2 == b.s2; } inline node operator+(node a, node b) { return node(((long long)a.s1 * p1[b.len] + b.s1) % h1, ((long long)a.s2 * p2[b.len] + b.s2) % h2, a.len + b.len); } inline int ksm(int x, int y, int mod) { int res = 1; while (y) { if (y & 1) res = (long long)res * x % mod; y >>= 1; x = (long long)x * x % mod; } return res; } inline void dfs1(int u, int pa) { int i; fa[u] = pa; dep[u] = dep[pa] + 1; mx[u] = dep[u]; s[u] -= a - 1; dfn[u] = ++tim; id[tim] = u; for (i = 0; i < 18; i++) f[i + 1][u] = f[i][f[i][u]]; node a = down[pa], b = up[pa]; down[u] = node(((long long)z1 * a.s1 + s[u]) % h1, ((long long)z2 * a.s2 + s[u]) % h2, a.len + 1); up[u] = node((b.s1 + (long long)p1[b.len] * s[u]) % h1, (b.s2 + (long long)p2[b.len] * s[u]) % h2, b.len + 1); for (auto v : g[u]) if (v != pa) { f[0][v] = u; dfs1(v, u); if (mx[v] > mx[u]) mx[u] = mx[v], son[u] = v; id[++tim] = u; } } inline void dfs2(int u, int pa, int fi) { top[u] = fi; if (son[u]) dfs2(son[u], u, fi); for (auto v : g[u]) if (v != pa && v != son[u]) dfs2(v, u, v); } inline int cmp(int x, int y) { return dep[x] < dep[y] ? x : y; } inline void init() { int i, j; logn[0] = -1; for (i = 1; i <= tim; i++) logn[i] = logn[i >> 1] + 1, c[0][i] = id[i]; for (j = 1; (1 << j) <= tim; j++) for (i = 1; i + (1 << j) - 1 <= tim; i++) c[j][i] = cmp(c[j - 1][i], c[j - 1][i + (1 << j - 1)]); } inline int lca(int l, int r) { l = dfn[l]; r = dfn[r]; if (l > r) swap(l, r); int k = logn[r - l + 1]; return cmp(c[k][l], c[k][r - (1 << k) + 1]); } inline int anc(int x, int k) { if (!k) return x; int y = logn[k], to; x = f[y][x]; k -= (1 << y); to = top[x]; if (dep[to] <= dep[x] - k) return b[to][dep[x] - k - dep[to]]; else return a[to][dep[to] - dep[x] + k]; } inline int sub1(int x, int y) { (x -= y) < 0 && (x += h1); return x; } inline int sub2(int x, int y) { (x -= y) < 0 && (x += h2); return x; } inline node query_up(int x, int y) { node a = up[x], b = up[y]; return node((long long)sub1(a.s1, b.s1) * q1[b.len] % h1, (long long)sub2(a.s2, b.s2) * q2[b.len] % h2, a.len - b.len); } inline node query_down(int x, int y) { node a = down[y], b = down[x]; return node(sub1(a.s1, (long long)b.s1 * p1[a.len - b.len] % h1), sub2(a.s2, (long long)b.s2 * p2[a.len - b.len] % h2), a.len - b.len); } inline node calc(int x, int y, int z, int len) { int d1 = dep[x] - dep[z] + 1, d2 = dep[x] + dep[y] - 2 * dep[z] + 1; if (len <= d1) { int u = anc(x, len - 1); return query_up(x, fa[u]); } else { int u = anc(y, d2 - len); return query_up(x, fa[z]) + query_down(z, u); } } inline int query(int x, int y, int u, int v) { int z = lca(x, y), w = lca(u, v), res = 0, l = 1, r = min(dep[x] + dep[y] - 2 * dep[z], dep[u] + dep[v] - 2 * dep[w]) + 1; while (l <= r) { int mid = l + r >> 1; if (calc(x, y, z, mid) == calc(u, v, w, mid)) res = mid, l = mid + 1; else r = mid - 1; } return res; } int main() { read(n); int i, x, y, u, v, j; scanf( %s , s + 1); for (i = 1; i < n; i++) { read(x); read(y); g[x].emplace_back(y); g[y].emplace_back(x); } inv1 = ksm(z1, h1 - 2, h1); inv2 = ksm(z2, h2 - 2, h2); p1[0] = p2[0] = q1[0] = q2[0] = 1; for (i = 1; i <= n; i++) { p1[i] = (long long)p1[i - 1] * z1 % h1; p2[i] = (long long)p2[i - 1] * z2 % h2; q1[i] = (long long)q1[i - 1] * inv1 % h1; q2[i] = (long long)q2[i - 1] * inv2 % h2; } dfs1(1, 0); dfs2(1, 0, 1); init(); for (i = 1; i <= n; i++) if (top[i] == i) { int x = i; for (j = 0; j <= mx[i] - dep[i]; j++) a[i].emplace_back(x), x = fa[x]; x = i; while (x) b[i].emplace_back(x), x = son[x]; } read(m); while (m--) { read(x); read(y); read(u); read(v); print(query(x, y, u, v)); putchar( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, int> mp; int n, m, cc; char s[1010]; int a[1010], cnt[1010]; void getcc(string s) { if (mp.find(s) == mp.end()) mp[s] = cc++; cnt[mp[s]]++; } int main() { int i, j, k; while (scanf( %d%d , &n, &m) > 0) { for (i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); mp.clear(); cc = 0; memset(cnt, 0, sizeof(cnt)); for (i = 0; i < m; i++) { scanf( %s , s); getcc(s); } sort(cnt, cnt + cc); int ma = 0, mi = 0; for (i = 0; i < cc; i++) { mi += a[i] * cnt[cc - 1 - i]; ma += a[n - 1 - i] * cnt[cc - 1 - i]; } printf( %d %d n , mi, ma); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> com; vector<long long> all; long long c, a, n, k, mm; void solve() { long long s = 0, e = (long long)1e9 * 2 + 5; long long mid = 0; long long sum = 0; while (s <= e) { mid = (s + e) / 2; for (int i = 0; i < n; i++) { sum += max((long long)0, (com[i] * mid - all[i])); if (sum > (long long)1e18) { sum = k + 1; break; } } if (sum <= k) { mm = mid; s = mid + 1; } else e = mid - 1; sum = 0; } cout << mm; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> c; com.push_back(c); } for (int i = 0; i < n; i++) { cin >> a; all.push_back(a); } solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n, m; cin >> n >> m; vector<string> v, vec; for (long long i = 1; i <= n; i++) { string s; cin >> s; v.push_back(s); } for (long long i = 1; i <= m; i++) { string s; cin >> s; vec.push_back(s); } long long q; cin >> q; while (q--) { long long a; cin >> a; long long u = a % v.size(); cout << v[(u - 1 + v.size()) % v.size()]; u = a % vec.size(); cout << vec[(u - 1 + vec.size()) % vec.size()]; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; const int ma = 35; int n, m, mat[ma][ma]; int main() { int t; scanf( %d , &t); int ans, one, zero; int sum, temp; int l, r; while (t--) { scanf( %d%d , &n, &m); one = zero = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { scanf( %d , &mat[i][j]); if (mat[i][j]) one++; else zero++; } ans = min(zero, one); zero = one = sum = 0; if (m > n) { l = 1, r = m; while (1) { temp = one = zero = 0; while ((1 + temp <= n) && (l - temp >= 1)) { if (mat[1 + temp][l - temp]) one++; else zero++; temp++; } temp--; if ((1 + temp == n) && (l - temp == r)) break; temp = 0; while ((n - temp >= 1) && (r + temp <= m)) { if (mat[n - temp][r + temp]) one++; else zero++; temp++; } sum += min(zero, one); if ((l + 1) == r + temp - 1) break; l++, r--; } } else { l = 1, r = n; while (1) { temp = one = zero = 0; while (l - temp >= 1 && 1 + temp <= m) { if (mat[l - temp][1 + temp]) one++; else zero++; temp++; } temp--; if (l - temp == r && 1 + temp == m) break; temp = 0; while (r + temp <= n && m - temp >= 1) { if (mat[r + temp][m - temp]) one++; else zero++; temp++; } sum += min(zero, one); if (l + 1 == r + temp - 1) break; l++, r--; } } printf( %d n , min(ans, sum)); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; long long powmod(long long a, long long b) { long long res = 1; for (; b; b >>= 1) { if (b & 1) (res *= a) %= mod; (a *= a) %= mod; } return res; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; long long ans = 0, now = 1, x = powmod(100, mod - 2); for (int i = 0; i < n; ++i) { (ans += now) %= mod; (now *= a[i]) %= mod; (now *= x) %= mod; } (ans *= powmod(now, mod - 2)) %= mod; cout << ans << n ; return 0; } |
#include <bits/stdc++.h> const int N = 3005; int n, D, h[N], nxt[N], adj[N], fa[N], t, f[N][N], inv[N], ifac[N], C[N][N], g[N], s[N][N]; inline void dfs(const int x) { for (register int i = 1; i <= n; ++i) f[x][i] = 1; for (register int i = h[x], j, v; i; i = nxt[i]) for (dfs(v = adj[i]), j = 1; j <= n; ++j) f[x][j] = (0ll + f[x][j]) * s[v][j] % 1000000007; for (register int i = 1; i <= n; ++i) s[x][i] = s[x][i - 1] + f[x][i], s[x][i] >= 1000000007 ? s[x][i] -= 1000000007 : 0; } int main() { scanf( %d%d , &n, &D); register int i, j; auto add = [&](const int u, const int v) { nxt[++t] = h[u], h[u] = t, adj[t] = v; }; for (i = 2; i <= n; ++i) scanf( %d , &fa[i]), add(fa[i], i); for (i = 2, inv[0] = inv[1] = ifac[0] = ifac[1] = 1; i <= n; ++i) inv[i] = (0ll + inv[1000000007 % i]) * (1000000007 - 1000000007 / i) % 1000000007, ifac[i] = (0ll + ifac[i - 1]) * inv[i] % 1000000007; for (i = C[0][0] = 1; i <= n; ++i) for (j = C[i][0] = C[i][i] = 1; j < i; ++j) C[i][j] = C[i - 1][j] + C[i - 1][j - 1], C[i][j] >= 1000000007 ? C[i][j] -= 1000000007 : 0; dfs(1); register int ans = 0, o; for (i = 1; i <= n; ++i) for (j = 1, g[i] = f[1][i]; j < i; ++j) g[i] = (g[i] - (0ll + C[i - 1][j - 1]) * g[j]) % 1000000007, g[i] < 0 ? g[i] += 1000000007 : 0; for (i = 1; i <= n; ans = (ans + (0ll + o) * g[i]) % 1000000007, ++i) for (j = D - i + 1, o = ifac[i]; j <= D; ++j) o = (0ll + o) * j % 1000000007; printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct ip { long long a, b, c, d, m; }; ip getip(long long num, int mm) { return {(num & (255 << 24)) >> 24, (num & (255 << 16)) >> 16, (num & (255 << 8)) >> 8, num & 255, mm}; } vector<ip> numtoip(pair<long long, long long> p) { long long s = p.first, e = p.second; vector<ip> ans; while (s < e) { int k = (!s) ? 32 : __builtin_ctzll(s); while (s + (1ll << k) - 1 >= e) k--; ans.push_back(getip(s, 32 - k)); s += 1ll << k; } return ans; } pair<long long, long long> iptonum(ip x) { long long n = x.a * (1 << 24) + x.b * (1 << 16) + x.c * (1 << 8) + x.d * (1 << 0); bitset<32> low(n), high(n); for (int i = 0, ThxDem = 32 - x.m; i < ThxDem; ++i) low[i] = 0, high[i] = 1; return {low.to_ullong(), high.to_ullong() + 1}; } struct disjoint_intervals { set<pair<long long, long long> > s; void insert(pair<long long, long long> v) { if (v.first >= v.second) return; auto at = s.lower_bound(v); auto it = at; if (at != s.begin() && (--at)->second >= v.first) v.first = at->first, --it; for (; it != s.end() && it->first <= v.second; s.erase(it++)) v.second = max(v.second, it->second); s.insert(v); } bool intersect(pair<long long, long long> v) { auto it = s.upper_bound({v.first, -2}); return (it != s.end() && it->first < v.second) || (it != s.begin() && prev(it)->second > v.first); } }; disjoint_intervals w, b; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0, ThxDem = n; i < ThxDem; ++i) { string s; cin >> s; s += . ; int now = 0, white = s[0] == + ; vector<int> v; for (int i = 1, ThxDem = ((int)(s).size()); i < ThxDem; ++i) { if (s[i] >= 0 && s[i] <= 9 ) now = 10 * now + s[i] - 0 ; else v.push_back(now), now = 0; } if (v.size() < 5) v.push_back(32); auto ran = iptonum({v[0], v[1], v[2], v[3], v[4]}); if (white) w.insert(ran); else b.insert(ran); } for (auto x : w.s) { if (b.intersect(x)) { cout << -1 << endl; return 0; } } vector<pair<long long, long long> > good = {{-1, 0}}, ans; for (auto x : w.s) good.push_back(x); good.push_back({1ll << 32, (1ll << 32) + 1ll}); for (int i = 1, ThxDem = ((int)(good).size()); i < ThxDem; ++i) ans.push_back({good[i - 1].second, good[i].first}); vector<ip> res; for (auto xx : ans) { vector<ip> x = numtoip(xx); for (auto aux : x) { auto rr = iptonum(aux); if (b.intersect(rr)) res.push_back(aux); } } cout << res.size() << endl; for (auto x : res) cout << x.a << . << x.b << . << x.c << . << x.d << / << x.m << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200100; int N, M; vector<int> edge[MAXN]; int dep[MAXN]; int croute[MAXN]; int par[MAXN]; pair<int, int> cover[MAXN]; bool seen[MAXN]; void run(int cloc, int last, int cdep) { seen[cloc] = true; croute[cdep] = cloc; dep[cloc] = cdep; par[cloc] = last; for (int i = 0; i < edge[cloc].size(); i++) { int neigh = edge[cloc][i]; if (neigh == last) continue; if (!seen[neigh]) run(neigh, cloc, cdep + 1); else { int s = dep[neigh]; for (int j = s + 1; j <= cdep; j++) { int k = croute[j]; if (cover[k].first != -1) { int a = cover[k].first, b = cover[k].second; int c = neigh, d = cloc; if (dep[a] > dep[c]) { swap(a, c); swap(b, d); } vector<int> x, y, z; int goalx = b, goaly = d; while (dep[goalx] > dep[goaly]) goalx = par[goalx]; while (dep[goaly] > dep[goalx]) goaly = par[goaly]; while (goalx != goaly) { goalx = par[goalx]; goaly = par[goaly]; } int goal = goalx; int n = c; x.push_back(n); while (n != a) { n = par[n]; x.push_back(n); } x.push_back(b); n = b; while (n != goal) { n = par[n]; x.push_back(n); } y.push_back(c); y.push_back(d); n = d; while (n != goal) { n = par[n]; y.push_back(n); } n = goal; z.push_back(n); while (n != c) { n = par[n]; z.push_back(n); } cout << YES n ; cout << x.size(); for (int m = 0; m < x.size(); m++) cout << << x[m] + 1; cout << n ; cout << y.size(); for (int m = 0; m < y.size(); m++) cout << << y[m] + 1; cout << n ; cout << z.size(); for (int m = z.size() - 1; m >= 0; m--) cout << << z[m] + 1; cout << n ; exit(0); } else cover[k] = make_pair(neigh, cloc); } } } } int main() { for (int i = 0; i < MAXN; i++) { cover[i] = make_pair(-1, -1); seen[i] = false; } cin >> N >> M; for (int i = 0; i < M; i++) { int a, b; cin >> a >> b; a--, b--; edge[a].push_back(b); edge[b].push_back(a); } for (int i = 0; i < N; i++) { if (!seen[i]) { run(i, -1, 0); } } cout << NO n ; return 0; } |
// implementation of a toggle element
// See Micropipelines, I. E. Sutherland Sutherland, Sproull, and Associates, Palo Alto, CA
// Published in:
// Communications of the ACM
// Volume 32 Issue 6, June 1989
// Pages 720-738
// ACM New York, NY, USA
// For the implementation, see :
// The Design and Implementation of an Asynchronous Microprocessor
// PhD thesis by Nigel Charles Paver
// trivial implementation - not robust
module toggle_simple (/*AUTOARG*/
// Outputs
dot, blank,
// Inputs
in, rstn
);
input in;
output dot;
output blank;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire dot;
wire blank, blank_n;
latch U_LATCH_1 (.i(blank_n),
.q(dot),
.en(in),
.rstn(rstn));
latch U_LATCH_2 (.i(dot),
.q(blank),
.en(!in),
.rstn(rstn));
inv U_INV(.i(blank), .zn(blank_n));
endmodule // toggle_simple
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
#include <bits/stdc++.h> int n, k, ans; long long s[200005], a[200005], b[200005]; void neg() { for (int i = 0; i <= n; i++) { a[i] = -a[i]; b[i] = -b[i]; } } void trans() { b[n]--; b[0] += 2; for (int i = 1; i < n; i++) b[i]++; for (int i = 0; i < n; i++) { b[i + 1] += b[i] / 2; b[i] %= 2; } } void print(long long x[]) { for (int i = 0; i <= n; i++) printf( %I64d , x[i]); printf( n ); } int main() { scanf( %d %d , &n, &k); for (int i = 0; i <= n; i++) scanf( %I64d , &a[i]); for (int i = 0; i < n; i++) { b[i] += a[i]; b[i + 1] += b[i] / 2; b[i] %= 2; if (b[i] < 0) { b[i + 1]--; b[i] += 2; } } b[n] += a[n]; if (b[n] < 0) neg(); trans(); for (int i = n; i >= 0; i--) { if (s[i + 1] == 10ll * k + 1) s[i] = 10ll * k + 1; else s[i] = s[i + 1] * 2 + b[i]; if (s[i] > 10ll * k) s[i] = 10ll * k + 1; } for (int i = 0; i <= n; i++) { if (i == n && llabs(s[i] - a[i]) <= k && s[i] != a[i]) ans++; if (i != n && llabs(s[i] - a[i]) <= k) ans++; if (b[i]) break; } printf( %d n , ans); scanf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; #define mod1 1000000007 #define mod2 998244353 #define ff first #define ss second #define int long long #define ll unsigned long long #define pb push_back #define mp make_pair #define pii pair<int,int> #define inf 9e18 #define N 15000005 #define pi 2*asin(1.0) #define endl n void fast() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif } int32_t main() { fast(); int t; cin>>t; while(t--){ int n,m; cin>>n>>m; int arr[n]; for(int i=0;i<n;i++){ cin>>arr[i]; } int cnt=n; int len=0; for(int i=n-1;i>=0;i--){ if(arr[i]==cnt){ cnt--; } else{ len=i+1; break; } } double ans=1.0; for(int i=0;i<m;i++){ int r; double p; cin>>r>>p; if(r>=len){ ans=(ans*(1.0-p)); } } ans=1.0-ans; if(len==0) ans=1.0; cout<<fixed<<setprecision(6)<<ans<<endl; } return 0; } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module win (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("win.mif"),
.C_INIT_FILE("win.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(15120),
.C_READ_DEPTH_A(15120),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(15120),
.C_READ_DEPTH_B(15120),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("5"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.227751 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const int N = 500005; const int MOD = 1e9 + 7; int i, n, m, k, rs, x, y; long long val[N]; map<int, int> p; map<long long, vector<pair<int, int>>> M; int Pow(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = ((long long)ans * a) % MOD, --b; a = ((long long)a * a) % MOD; b /= 2; } return ans; } int pfind(int x) { if (!p.count(x)) return p[x] = x; if (p[x] == x) return p[x] = x; return p[x] = pfind(p[x]); } void punite(int x, int y) { if (rand() & 1) p[pfind(x)] = pfind(y); else p[pfind(y)] = pfind(x); } int main() { scanf( %d %d %d , &n, &m, &k); rs = Pow(2, n + k); for (i = 1; i <= n; ++i) scanf( %lld , val + i); while (m--) { scanf( %d %d , &x, &y); M[val[x] ^ val[y]].push_back(make_pair(x, y)); } for (auto it : M) { vector<pair<int, int>> v = it.second; x = n; p.clear(); for (auto it : v) if (pfind(it.first) != pfind(it.second)) { punite(it.first, it.second); --x; } rs -= Pow(2, n); rs += Pow(2, x); if (rs < 0) rs += MOD; else rs %= MOD; } printf( %d n , rs); return 0; } |
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: dac_spi_if.v
//
// *Module Description:
// SPI interface for National's DAC121S101 12 bit DAC
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 66 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-03-07 09:09:38 +0100 (Sun, 07 Mar 2010) $
//----------------------------------------------------------------------------
module dac_spi_if (
// OUTPUTs
cntrl1, // Control value 1
cntrl2, // Control value 2
din, // SPI Serial Data
per_dout, // Peripheral data output
sclk, // SPI Serial Clock
sync_n, // SPI Frame synchronization signal (low active)
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// PARAMETERs
//============
parameter SCLK_DIV = 0; // Serial clock divider (Tsclk=Tmclk*(SCLK_DIV+1)*2)
parameter BASE_ADDR = 9'h190; // Registers base address
// OUTPUTs
//=========
output [3:0] cntrl1; // Control value 1
output [3:0] cntrl2; // Control value 2
output din; // SPI Serial Data
output [15:0] per_dout; // Peripheral data output
output sclk; // SPI Serial Clock
output sync_n; // SPI Frame synchronization signal (low active)
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 3;
// Register addresses offset
parameter [DEC_WD-1:0] DAC_VAL = 'h0,
DAC_STAT = 'h2,
CNTRL1 = 'h4,
CNTRL2 = 'h6;
// Register one-hot decoder utilities
parameter DEC_SZ = 2**DEC_WD;
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] DAC_VAL_D = (BASE_REG << DAC_VAL),
DAC_STAT_D = (BASE_REG << DAC_STAT),
CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (DAC_VAL_D & {DEC_SZ{(reg_addr == DAC_VAL )}}) |
(DAC_STAT_D & {DEC_SZ{(reg_addr == DAC_STAT)}}) |
(CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// DAC_VAL Register
//------------------
reg [11:0] dac_val;
reg dac_pd0;
reg dac_pd1;
wire dac_val_wr = reg_wr[DAC_VAL];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
dac_val <= 12'h000;
dac_pd0 <= 1'b0;
dac_pd1 <= 1'b0;
end
else if (dac_val_wr)
begin
dac_val <= per_din[11:0];
dac_pd0 <= per_din[12];
dac_pd1 <= per_din[13];
end
// CNTRL1 Register
//------------------
reg [3:0] cntrl1;
wire cntrl1_wr = reg_wr[CNTRL1];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl1 <= 4'h0;
else if (cntrl1_wr) cntrl1 <= per_din;
// CNTRL2 Register
//------------------
reg [3:0] cntrl2;
wire cntrl2_wr = reg_wr[CNTRL2];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl2 <= 4'h0;
else if (cntrl2_wr) cntrl2 <= per_din;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] dac_val_rd = { 2'b00, dac_pd1, dac_pd0, dac_val} & {16{reg_rd[DAC_VAL]}};
wire [15:0] dac_stat_rd = {15'h0000, ~sync_n} & {16{reg_rd[DAC_STAT]}};
wire [15:0] cntrl1_rd = {12'h000, cntrl1} & {16{reg_rd[CNTRL1]}};
wire [15:0] cntrl2_rd = {12'h000, cntrl2} & {16{reg_rd[CNTRL2]}};
wire [15:0] per_dout = dac_val_rd |
dac_stat_rd |
cntrl1_rd |
cntrl2_rd;
//============================================================================
// 5) SPI INTERFACE
//============================================================================
// SPI Clock divider
reg [3:0] spi_clk_div;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) spi_clk_div <= SCLK_DIV;
else if (spi_clk_div==0) spi_clk_div <= SCLK_DIV;
else spi_clk_div <= spi_clk_div-1;
// SPI Clock generation
reg sclk;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sclk <= 1'b0;
else if (spi_clk_div==0) sclk <= ~sclk;
wire sclk_re = (spi_clk_div==0) & ~sclk;
// SPI Transfer trigger
reg spi_tfx_trig;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) spi_tfx_trig <= 1'b0;
else if (dac_val_wr) spi_tfx_trig <= 1'b1;
else if (sclk_re & sync_n) spi_tfx_trig <= 1'b0;
wire spi_tfx_init = spi_tfx_trig & sync_n;
// Data counter
reg [3:0] spi_cnt;
wire spi_cnt_done = (spi_cnt==4'hf);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) spi_cnt <= 4'hf;
else if (sclk_re)
if (spi_tfx_init) spi_cnt <= 4'he;
else if (~spi_cnt_done) spi_cnt <= spi_cnt-1;
// Frame synchronization signal (low active)
reg sync_n;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sync_n <= 1'b1;
else if (sclk_re)
if (spi_tfx_init) sync_n <= 1'b0;
else if (spi_cnt_done) sync_n <= 1'b1;
// Value to be shifted_out
reg [15:0] dac_shifter;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) dac_shifter <= 16'h000;
else if (sclk_re)
if (spi_tfx_init) dac_shifter <= {2'b00, dac_pd1, dac_pd0, dac_val[11:0]};
else dac_shifter <= {dac_shifter[14:0], 1'b0};
assign din = dac_shifter[15];
endmodule // dac_spi_if
|
#include <bits/stdc++.h> using namespace std; const int64_t INF = (1 << 30) - 1; const long long oo = (1ll << 62) - 1; const long double PI = 3.1415926535898; const int64_t N = 100000 + 5; int64_t n; vector<int64_t> a[N]; int64_t d[5][N]; int64_t mau[N]; int64_t c[5][5]; int64_t dfs(int64_t u, int64_t p, int64_t col, int64_t vt) { col %= 3; col += 1; int64_t ans = d[c[vt][col]][u]; for (int64_t v : a[u]) { if (v == p) continue; ans += dfs(v, u, col, vt); } return ans; } void dfs2(int64_t u, int64_t p, int64_t col, int64_t vt) { col %= 3; col += 1; mau[u] = c[vt][col]; for (int64_t v : a[u]) { if (v == p) continue; dfs2(v, u, col, vt); } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (int64_t i = 1; i <= n; i++) cin >> d[1][i]; for (int64_t i = 1; i <= n; i++) cin >> d[2][i]; for (int64_t i = 1; i <= n; i++) cin >> d[3][i]; for (int64_t i = 1; i < n; i++) { int64_t u, v; cin >> u >> v; a[u].push_back(v); a[v].push_back(u); } for (int64_t i = 1; i <= n; i++) { if (a[i].size() >= 3) { cout << -1; return 0; } } c[1][1] = 1; c[1][2] = 2; c[1][3] = 3; c[2][1] = 1; c[2][2] = 3; c[2][3] = 2; int64_t s = 1; while (a[s].size() == 2) s++; int64_t res = oo, col, vt; for (int64_t i = 1; i <= 2; i++) { for (int64_t j = 1; j <= 3; j++) { int64_t ans = dfs(s, s, j - 1, i); if (ans < res) { res = ans; col = j; vt = i; } } } dfs2(s, s, col - 1, vt); cout << res << n ; for (int64_t i = 1; i <= n; i++) cout << mau[i] << ; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 16-Bit Shift Register Look-Up-Table with Clock Enable
// /___/ /\ Filename : SRL16E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:04 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module SRL16E #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] INIT = 16'h0000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);
reg [15:0] data;
wire [3:0] addr;
wire CLK_dly, D_dly, CE_dly;
wire CLK_in, D_in, CE_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
assign addr = {A3, A2, A1, A0};
always @(posedge CLK_in)
if (CE_in == 1'b1)
{data[15:0]} <= #100 {data[14:0], D_in};
assign Q = data[addr];
always @(notifier)
data[0] <= 1'bx;
`ifndef XIL_TIMING
assign D_dly = D;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign D_in = D_dly;
assign CE_in = CE_dly;
specify
(A0 => Q) = (0:0:0, 0:0:0);
(A1 => Q) = (0:0:0, 0:0:0);
(A2 => Q) = (0:0:0, 0:0:0);
(A3 => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Mon Mar 31 20:12:08 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_4/part_1/ip/clk_108MHz/clk_108MHz_funcsim.v
// Design : clk_108MHz
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_108MHz,clk_wiz_v5_1,{component_name=clk_108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_108MHz
(clk_100MHz,
clk_108MHz,
locked);
input clk_100MHz;
output clk_108MHz;
output locked;
wire clk_100MHz;
wire clk_108MHz;
wire locked;
clk_108MHzclk_108MHz_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_108MHz(clk_108MHz),
.locked(locked));
endmodule
module clk_108MHzclk_108MHz_clk_wiz
(clk_100MHz,
clk_108MHz,
locked);
input clk_100MHz;
output clk_108MHz;
output locked;
wire \<const0> ;
wire \<const1> ;
wire clk_100MHz;
wire clk_100MHz_clk_108MHz;
wire clk_108MHz;
wire clk_108MHz_clk_108MHz;
wire clkfbout_buf_clk_108MHz;
wire clkfbout_clk_108MHz;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_108MHz),
.O(clkfbout_buf_clk_108MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkin1_bufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_108MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_108MHz_clk_108MHz),
.O(clk_108MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.125000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(9.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_108MHz),
.CLKFBOUT(clkfbout_clk_108MHz),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_108MHz),
.CLKIN2(\<const0> ),
.CLKINSEL(\<const1> ),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_108MHz_clk_108MHz),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DCLK(\<const0> ),
.DEN(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(\<const0> ),
.LOCKED(locked),
.PSCLK(\<const0> ),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(\<const0> ),
.PSINCDEC(\<const0> ),
.PWRDWN(\<const0> ),
.RST(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
-------------------------------------------------------------------------------
This file is part of the hardware description for the Propeller 1 Design
for Pipistrello LX45.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
//
// Copyright 2014 Saanlima Electronics
//
// Magnus Karlsson 20140820 Moved reg and wire declarations to top of file
// Added PLL or DCM selection option
// Added dtr or inp_resn selection option
//
// Magnus Karlsson 20140818 Wrote top level verilog module from scratch based
// on top.tdf and tim.tdf in the Parallax release.
//`define use_pll 1 // comment out for DCM mode
`define use_dtr 1 // comment out for inp_resn instead of dtr
module top
(
input clock_50, // clock input
`ifdef use_dtr
input dtr, // serial port DTR input
`else
input inp_resn, // reset input (active low)
`endif
inout [31:0] pin, // i/o pins
output [7:0] ledg, // cog leds
output tx_led, // tx monitor LED
output rx_led, // rx monitor LED
output p16_led, // monitor LED for pin 16
output p17_led // monitor LED for pin 17
);
//
// reg and wire declarations
//
reg nres;
wire [7:0] cfg;
wire [31:0] pin_in, pin_out, pin_dir;
wire clkfb, clock_160, clk;
reg [23:0] reset_cnt;
reg reset_to;
wire res;
reg [7:0] cfgx;
reg [12:0] divide;
wire clk_pll;
wire clk_cog;
//
// Clock generation
//
`ifdef use_pll
//
// PLL (50 MHz -> 160 MHz)
//
PLL_BASE # (
.CLKIN_PERIOD(20),
.CLKFBOUT_MULT(16),
.CLKOUT0_DIVIDE(5),
.COMPENSATION("INTERNAL")
) PLL (
.CLKFBOUT(clkfb),
.CLKOUT0(clock_160),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(),
.CLKFBIN(clkfb),
.CLKIN(clock_50),
.RST(1'b0)
);
`else
//
// DCM (50 MHz -> 160 MHz)
//
DCM_SP DCM_SP_(
.CLKIN(clock_50),
.CLKFB(clkfb),
.RST(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSCLK(1'b0),
.DSSEN(1'b0),
.CLK0(clkfb),
.CLK90(),
.CLK180(),
.CLK270(),
.CLKDV(),
.CLK2X(),
.CLK2X180(),
.CLKFX(clock_160),
.CLKFX180(),
.STATUS(),
.LOCKED(),
.PSDONE());
defparam DCM_SP_.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_SP_.CLKIN_PERIOD = 20;
defparam DCM_SP_.CLK_FEEDBACK = "1X";
defparam DCM_SP_.CLKFX_DIVIDE = 5;
defparam DCM_SP_.CLKFX_MULTIPLY = 16;
`endif
BUFG BUFG_clk(.I(clock_160), .O(clk));
assign clk_pll = ((cfgx[6:5] == 2'b11) && (cfgx[2:0] == 3'b111)) ? clock_160 : divide[11];
assign clk_cog = divide[12];
`ifdef use_dtr
//
// Emulate RC filter on Prop Plug by generating a long reset pulse
// everytime DTR goes high
//
always @ (posedge clk or negedge dtr)
if (!dtr) begin
reset_cnt <= 24'd0;
reset_to <= 1'b0;
end else begin
reset_cnt <= reset_to ? reset_cnt : reset_cnt + 1;
reset_to <= (reset_cnt == 24'hfffff) ? 1'b1 : reset_to;
end
wire inp_resn = ~(dtr & ~reset_to);
`endif
//
// Clock control (from tim.tdf)
//
assign res = ~inp_resn;
always @ (posedge clk)
cfgx <= cfg;
always @ (posedge clk)
divide <= divide +
{ (cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b111) || res,
cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b110 && !res,
cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b101 && !res,
((cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b100) || cfgx[2:0] == 3'b000) && !res,
((cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b011) || (cfgx[5] == 1'b1 && cfgx[2:0] == 3'b010)) && !res,
7'b0,
cfgx[2:0] == 3'b001 && !res
};
//
// Propeller 1 core module
//
always @ (posedge clk_cog)
nres <= inp_resn & !cfgx[7];
dig core ( .nres (nres),
.cfg (cfg),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.pin_in (pin_in),
.pin_out (pin_out),
.pin_dir (pin_dir),
.cog_led (ledg) );
//
// Bidir I/O buffers
//
genvar i;
generate
for (i=0; i<32; i=i+1)
begin : iogen
IOBUF io_ (.IO(pin[i]), .O(pin_in[i]), .I(pin_out[i]), .T(~pin_dir[i]));
end
endgenerate
//
// Monitor LEDs
//
assign tx_led = pin_in[30];
assign rx_led = pin_in[31];
assign p16_led = pin_in[16];
assign p17_led = pin_in[17];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const long long INFLL = 1e18 + 1; const int MAX = 200001; const long long MOD = 1000000007; long long inq(long long k, long long q) { if (q == 0) return 1; long long l = inq(k, q / 2); if (q % 2 == 0) return l * l % MOD; else return (l * l) % MOD * k % MOD; } long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } long long cubr(long long a) { long long l = -1, r = 1e6 + 2; while (l < r - 1) { long long mid = (l + r) / 2; if (mid * mid * mid > a) r = mid; else l = mid; } return l; } long long max(long long a, long long b) { if (a > b) return a; return b; } long long min(long long a, long long b) { return -1 * max(-a, -b); } long long possible(long long q) { if (q == INF) return -1; return q; } bool correct(int x, int xx) { if (x < 0) return 0; if (x >= xx) return 0; return 1; } long long dsumm(long long x, long long k) { long long y = 1; long long z = 0; for (int i = 0; y < 1e18; i++) { z += x / y % k; y *= k; } return z; } long long dcount(long long x) { long long y = 1; long long z = 0; int c[100]; for (int i = 0; i < 10; i++) c[i] = 0; for (int i = 0; x > 0; i++) { if (c[x / y % 10] == 0) z++; c[x / y % 10] = 1; x /= 10; } return z; } long long lg10(long long x) { if (x == 0) return 0; return lg10(x / 10) + 1; } long long n, m; vector<int> graph[4000], graph2[4000]; long long ans; long long d[5000]; long long f[4000]; long long ff[4000]; int main() { cin >> n >> m; for (int(i) = 0; (i) != (m); i++) { int x, y; cin >> x >> y; x--; y--; graph[x].push_back(y); graph2[y].push_back(x); } long long it = 2; for (int b = 0; b < n; b++) { for (int c = b + 1; c < n; c++) { long long x = 0; long long y = 0; long long z = 0; for (int i = 0; i < graph[b].size(); i++) { d[graph[b][i]] = it; } for (int i = 0; i < graph[c].size(); i++) { if (d[graph[c][i]] == it) { x++; } } it++; for (int i = 0; i < graph2[b].size(); i++) { d[graph2[b][i]] = it; } for (int i = 0; i < graph2[c].size(); i++) { if (d[graph2[c][i]] == it) { y++; } } it++; for (int i = 0; i < graph[b].size(); i++) { ff[graph[b][i]] = it * 7; } for (int i = 0; i < graph[c].size(); i++) { if (ff[graph[c][i]] == it * 7) ff[graph[c][i]]++; else ff[graph[c][i]] = 0; } for (int i = 0; i < graph2[b].size(); i++) { if (ff[graph2[b][i]] == it * 7 + 1) ff[graph2[b][i]]++; else ff[graph2[b][i]] = 0; } for (int i = 0; i < graph2[c].size(); i++) { if (ff[graph2[c][i]] == it * 7 + 2) { z++; ff[graph2[c][i]] = 0; } } ans += (x - z) * (y - z) + z * (z - 1) + z * (x - z) + z * (y - z); } } cout << ans; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A31OI_FUNCTIONAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int a[2000]; int n; inline bool check() { int c = 0; for (int i = 0; i < n; ++i) if (a[i] + 1 == a[i + 1]) ++c; if (c == n) return true; else return false; } inline void push() { for (int i = 0; i <= n; ++i) { if (i % 2 == 0) { if (a[i] == n) a[i] = 0; else a[i] = a[i] + 1; } else { if (a[i] == 0) a[i] = n; else a[i] = a[i] - 1; } } } int main() { scanf( %d , &n); --n; for (int i = 0; i <= n; ++i) { scanf( %d , &a[i]); if (i % 2 == 0) { if (a[i] == n) a[i] = 0; else a[i] = a[i] + 1; } else { if (a[i] == 0) a[i] = n; else a[i] = a[i] - 1; } } if (check()) { puts( Yes ); return 0; } else { for (int i = 0; i < n; ++i) { push(); if (check()) { puts( Yes ); return 0; } } } puts( No ); return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const double eps = 1e-6; const long long INF = 0x3f3f3f3f3f3f3f3fll; const int inf = 0x3f3f3f3f; const int mod = 998244353; const int maxn = 1e6 + 100; long long qpow(long long a, long long b) { long long ret = 1; a %= mod; while (b) { if (b & 1) ret = ret * a % mod; b /= 2; a = a * a % mod; } return ret; } void solve() { long long w, h; scanf( %lld%lld , &w, &h); cout << qpow(2LL, w + h) << endl; } int main() { solve(); ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; return 0; } |
module LUT1(output F, input I0);
parameter [1:0] INIT = 0;
assign F = I0 ? INIT[1] : INIT[0];
endmodule
module LUT2(output F, input I0, I1);
parameter [3:0] INIT = 0;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT3(output F, input I0, I1, I2);
parameter [7:0] INIT = 0;
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT4(output F, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK)
Q <= D;
endmodule
module DFFN (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge CLK)
Q <= D;
endmodule
module VCC(output V);
assign V = 1;
endmodule
module GND(output G);
assign G = 0;
endmodule
module IBUF(output O, input I);
assign O = I;
endmodule
module OBUF(output O, input I);
assign O = I;
endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule
|
#include <bits/stdc++.h> using namespace std; using LL = long long; constexpr int N = 1e5 + 5; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, k, m; cin >> n >> k >> m; vector<int> in(k); for (int &e : in) cin >> e; sort(begin(in), end(in)); const int A = accumulate(begin(in), end(in), 0); int ans = 0; for (int i = 0; i <= n; i++) { if (i * A > m) break; int points = i * (k + 1); int have = m - i * A; int g = n - i; for (int x : in) { int t = min(g, have / x); points += t; have -= t * x; } ans = max(ans, points); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const long long N = 200005; const long long M = 1000000007; long long n, d; string s, t1, t2, t; long long rt = 1, tot = 1, ch[15][N], ed[N], fail[N]; void insert(string x) { long long len = x.length(), now = rt; for (long long i = 0; i < len; i++) { if (!ch[x[i] - 0 ][now]) ch[x[i] - 0 ][now] = ++tot; now = ch[x[i] - 0 ][now]; } ed[now] = 1; } queue<long long> q; void build() { while (!q.empty()) q.pop(); for (long long i = 0; i < 10; i++) { if (ch[i][rt]) { fail[ch[i][rt]] = rt; q.push(ch[i][rt]); } else ch[i][rt] = rt; } while (!q.empty()) { long long u = q.front(); q.pop(); for (long long i = 0; i < 10; i++) { if (ch[i][u]) { fail[ch[i][u]] = ch[i][fail[u]]; q.push(ch[i][u]); } else ch[i][u] = ch[i][fail[u]]; } } } void prep() { for (long long i = 1; i <= n; i++) { if (i + d / 2 - 1 > n) break; t = ; for (long long j = 1; j <= d / 2; j++) t += s[i + j - 1]; insert(t); } build(); } string minusone(string x) { x[d - 1]--; for (long long i = d - 1; i >= 0; i--) { if (x[i] < 0 ) { x[i] = 9 ; x[i - 1]--; } } return x; } long long g[2][55], dp[2][55][N]; long long calc(string x) { memset(g, 0, sizeof(g)); memset(dp, 0, sizeof(dp)); dp[1][0][1] = 1; g[0][d] = 1; g[1][d] = 1; for (long long i = d - 1; i >= 1; i--) { g[0][i] = (g[0][i + 1] * 10) % M; g[1][i] = (g[1][i + 1] + (x[i + 1] - 0 ) * g[0][i + 1]) % M; } for (long long i = 0; i < d; i++) { for (long long j = 1; j <= tot; j++) { if (ed[j]) continue; for (long long k = 0; k < 10; k++) { long long to = ch[k][j]; dp[0][i + 1][to] = (dp[0][i + 1][to] + dp[0][i][j]) % M; if (k < x[i + 1] - 0 ) dp[0][i + 1][to] = (dp[0][i + 1][to] + dp[1][i][j]) % M; if (k == x[i + 1] - 0 ) dp[1][i + 1][to] = (dp[1][i + 1][to] + dp[1][i][j]) % M; } } } long long ret = 0; for (long long i = 1; i <= d; i++) { for (long long j = 1; j <= tot; j++) { if (ed[j]) ret = (ret + dp[0][i][j] * g[0][i] + dp[1][i][j] * g[1][i]) % M; } } return ret; } int main() { ios::sync_with_stdio(false); cin >> s; n = s.length(); s = + s; cin >> t1 >> t2; d = t1.length(); t1 = minusone(t1); t1 = + t1; t2 = + t2; prep(); cout << (calc(t2) - calc(t1) + M) % M << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 dadi(chrono::high_resolution_clock::now().time_since_epoch().count()); const int N = 100 + 5, K = 1e3 + 5; int n, m, k, w[N], p[K], cnt[N][K]; struct game { int u, v, t; } a[K]; inline int add(int u, int v) { shuffle(p, p + k, dadi); int mx1 = *max_element(cnt[u], cnt[u] + k); int mx2 = *max_element(cnt[v], cnt[v] + k); for (int i = 0; i < k; i++) if (cnt[u][p[i]] < mx1 && cnt[v][p[i]] < mx2) return p[i]; for (int i = 0; i < k; i++) if (cnt[u][p[i]] < mx1 || cnt[v][p[i]] < mx2) return p[i]; return p[0]; } inline void read_input() { cin >> n >> m >> k; for (int i = 0; i < n; i++) cin >> w[i]; for (int i = 0; i < m; i++) { cin >> a[i].u >> a[i].v; a[i].u--, a[i].v--; } } inline void solve() { for (iota(p, p + k, 0); true; memset(cnt, 0, sizeof cnt)) { bool flag = true; for (int i = 0; i < m; i++) { cnt[a[i].u][a[i].t = add(a[i].u, a[i].v)]++; cnt[a[i].v][a[i].t++]++; } for (int i = 0; i < n; i++) flag &= *max_element(cnt[i], cnt[i] + k) - *min_element(cnt[i], cnt[i] + k) < 3; if (flag) break; } } inline void write_output() { for (int i = 0; i < m; i++) cout << a[i].t << endl; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); read_input(), solve(), write_output(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100020, mo = 1e9 + 7; int n, second[N], x, y, cnt, dfn[N], vis[N]; int dot[N], size; int l[N], r[N]; long long ans = 1; set<pair<int, int> > L[N], R[N]; struct Dot { int x, y; } s[N]; inline void read(int &x) { x = 0; char c = getchar(); int f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = 10 * x + c - 0 ; c = getchar(); } x *= f; } inline int LS() { sort(second + 1, second + n + 1); int l = 0; for (int i = 1; i <= n; i++) if (i == 1 || second[i] != second[i - 1]) second[++l] = second[i]; return l; } inline void dfs(int u) { if (u > n || u < 1) return; vis[u] = cnt; dot[++size] = u; set<pair<int, int> >::iterator it = L[s[u].x].find(pair<int, int>(s[u].y, u)); it++; if (!vis[(*it).second]) dfs((*it).second); it--; it--; if (!vis[(*it).second]) dfs((*it).second); it = R[s[u].y].find(pair<int, int>(s[u].x, u)); it++; if (!vis[(*it).second]) dfs((*it).second); it--; it--; if (!vis[(*it).second]) dfs((*it).second); } inline int power(long long a, int n) { long long ans = 1; while (n) { if (n & 1) ans = (ans * a % mo); a = (a * a % mo); n >>= 1; } return ans; } int main() { read(n); for (int i = 1; i <= n; i++) read(s[i].x), read(s[i].y); for (int i = 1; i <= n; i++) second[i] = s[i].x; int X = LS(); for (int i = 1; i <= n; i++) s[i].x = lower_bound(second + 1, second + X + 1, s[i].x) - second; for (int i = 1; i <= n; i++) second[i] = s[i].y; int Y = LS(); for (int i = 1; i <= n; i++) s[i].y = lower_bound(second + 1, second + Y + 1, s[i].y) - second; vis[n + 1] = 1e9; for (int i = 1; i <= n; i++) L[i].insert(pair<int, int>(0, n + 1)), L[i].insert(pair<int, int>(n + 1, n + 1)); for (int i = 1; i <= n; i++) R[i].insert(pair<int, int>(0, n + 1)), R[i].insert(pair<int, int>(n + 1, n + 1)); for (int i = 1; i <= n; i++) { L[s[i].x].insert(pair<int, int>(s[i].y, i)); R[s[i].y].insert(pair<int, int>(s[i].x, i)); } for (int i = 1; i <= n; i++) if (!vis[i]) { size = 0; cnt++; dfs(i); int num = 0; bool flag = 0; for (int j = 1; j <= size; j++) { if (l[s[dot[j]].x] || r[s[dot[j]].y]) flag = 1; num += (!l[s[dot[j]].x]) + (!r[s[dot[j]].y]); l[s[dot[j]].x] = 1; r[s[dot[j]].y] = 1; } int x = power(2, num); if (size < num) x--; if (x < 0) x += mo; ans = ans * x % mo; } printf( %lld , ans); return 0; } |
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module rx_data_buffer_data_w (
input negedge_clk,
input rx_resetn,
input [1:0] state_data_process,
input [2:0] control,
input last_is_timec,
input last_is_data,
input last_is_control,
output reg rx_buffer_write,
output reg rx_tick_out
);
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_buffer_write <= 1'b0;
rx_tick_out <= 1'b0;
end
else
begin
if(state_data_process == 2'd1 || state_data_process == 2'd2)
begin
if(last_is_timec == 1'b1)
begin
rx_tick_out <= 1'b1;
rx_buffer_write <= 1'b0;
end
else if(last_is_data == 1'b1)
begin
rx_buffer_write <= 1'b1;
rx_tick_out <= 1'b0;
end
else if(last_is_control == 1'b1)
begin
if(control[2:0] == 3'd6)
begin
rx_buffer_write <= 1'b1;
rx_tick_out <= 1'b0;
end
else if(control[2:0] == 3'd5)
begin
rx_buffer_write <= 1'b1;
rx_tick_out <= 1'b0;
end
else
begin
rx_buffer_write <= 1'b0;
rx_tick_out <= 1'b0;
end
end
else
begin
rx_buffer_write <= 1'b0;
rx_tick_out <= 1'b0;
end
end
else
begin
rx_buffer_write <= 1'b0;
rx_tick_out <= 1'b0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_4_V
`define SKY130_FD_SC_LS__SDFXTP_4_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_4 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_4_V
|
#include <bits/stdc++.h> using namespace std; char s[500001], t[500001]; long long nt[10000001], n, k, m; long long c[2]; void kmp(long long x, char a[]) { int i, j; for (nt[0] = j = -1, i = 1; i < x; nt[i++] = j) { while (~j && a[j + 1] != a[i]) j = nt[j]; if (a[j + 1] == a[i]) j++; } } int main() { scanf( %s , s); scanf( %s , t); n = strlen(t); kmp(n, t); k = nt[n - 1]; m = strlen(s); for (int i = 0; i < m; i++) c[s[i] - 0 ]++; for (int i = 0, j = 0; i < m; i++) { if (c[0] == 0) printf( 1 ); else if (c[1] == 0) printf( 0 ); else { printf( %c , t[j]); c[t[j] - 0 ]--; if (j == n - 1) j = nt[j]; j++; } } } |
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y) { if (y == 0) return 1; if (y & 1) return (x * power(x, y - 1)) % 1000000007; long long int t = power(x, y / 2); return (t * t) % 1000000007; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; set<int> arr[26]; int n = (int)s.size(); for (int i = 0; i < n; i++) arr[s[i] - a ].insert(i); string mk = Mike n ; string ann = Ann n ; bool found = false; for (int i = 0; i < n; i++) { found = false; for (int j = 0; j < s[i] - a ; j++) { auto itr = arr[j].lower_bound(0); if (itr != arr[j].end() && *itr < i) { found = true; break; } } if (true == found) cout << ann; else cout << mk; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND4_PP_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long ax, ay, bx, by, cx, cy; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> ax >> ay >> bx >> by >> cx >> cy; if ((by - ay) * (cx - bx) == (cy - by) * (bx - ax)) cout << NO n ; else if ((by - ay) * (by - ay) + (bx - ax) * (bx - ax) == (by - cy) * (by - cy) + (bx - cx) * (bx - cx)) cout << YES n ; else cout << NO n ; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; if (x1 == x2 && y1 == y2) { cout << 10 ; return; } if (x1 == x2) { cout << 2 * (abs(y2 - y1) + 1) + 4; return; } if (y1 == y2) { cout << 2 * (abs(x2 - x1) + 1) + 4; return; } cout << 2 * (abs(x2 - x1) + abs(y2 - y1) + 2); } int main() { solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, m, dx[] = {0, 0, -1, 1}, dy[] = {1, -1, 0, 0}, mp[100005], b; int cheak(int x, int y) { if (abs(x - y) == m || abs(x - y) == 1) return 1; else return 0; } void dfs(int x) { if (x == n * m) { b = 1; cout << YES << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) printf( %d , mp[i * m + j] + 1); printf( n ); } return; } for (int i = x; i < n * m; i++) { swap(mp[i], mp[x]); if ((x / m == 0 || cheak(mp[x], mp[(x / m - 1) * m + x % m]) == 0) && (x % m == 0 || cheak(mp[x], mp[x / m * m + x % m - 1]) == 0)) { dfs(x + 1); if (b == 1) return; swap(mp[i], mp[x]); } } } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n * m; i++) mp[i] = i; dfs(0); if (b == 0) printf( NO ); return 0; } |
#include <bits/stdc++.h> const double eps = 1e-9; const double pi = acos(-1); using namespace std; struct sx {}; bool cmp(int a, int b) { return a > b; } long long t1, t2, t3; int main() { int n, m; cin >> n >> m; int x = (n + m) / 3; while (t1 < x && ((n >= 1 && m >= 2) || (n >= 2 && m >= 1))) { if (n > m) { n -= 2; m -= 1; } else { m -= 2; n -= 1; } t1++; } cout << t1; } |
#include <bits/stdc++.h> using namespace std; int mx = INT_MIN, n, a[10]; char x; int main() { cin >> n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= 7; j++) { cin >> x; a[j] += x - 48; } } for (int i = 1; i <= 7; i++) if (mx < a[i]) mx = a[i]; cout << mx; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM_B.v when simulating
// the core, RAM_B. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM_B(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("kintex7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("RAM_B.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("kintex7")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return a == 0 ? b : gcd(b % a, a); } void solve(int test) { int n, k; cin >> n >> k; vector<pair<pair<int, int>, int>> v(n); int i, j, l; for (i = (0); i < (n); ++i) cin >> v[i].first.first >> v[i].first.second; for (i = (0); i < (n); ++i) if (v[i].first.first == 0 && v[i].first.second == 0) break; if (i == n) throw 0; if (i != 0) swap(v[0], v[i]); for (i = (1); i < (n); ++i) { v[i].second = gcd(abs(v[i].first.first), abs(v[i].first.second)); v[i].first.first /= v[i].second; v[i].first.second /= v[i].second; } sort(v.begin() + 1, v.end()); int prev = 1; vector<double> all(1, 0.0), neg; for (i = (2); i < (n + 1); ++i) if (i == n || v[prev].first != v[i].first) { long long x = v[prev].first.first; long long y = v[prev].first.second; double len = sqrt(x * x + y * y + 0.0); vector<double> w; for (j = (prev); j < (i); ++j) w.push_back(len * v[j].second); reverse((w).begin(), (w).end()); int mid = min((k + 1) / 2, int((w).size())); for (j = (0); j < (mid); ++j) all.push_back(w[j] * (k - 1 - 2 * j)); for (j = (mid); j < (int((w).size())); ++j) neg.push_back(w[j]); prev = i; } sort((all).begin(), (all).end()); sort((neg).begin(), (neg).end()); if (int((all).size()) < k) { int cnt = k - int((all).size()); int mid = (k + 1) / 2; for (i = (0); i < (cnt); ++i) all.push_back(neg[i] * (k - 1 - 2 * (mid + cnt - 1 - i))); sort((all).begin(), (all).end()); } reverse((all).begin(), (all).end()); double res = 0; for (i = (0); i < (k); ++i) res += all[i]; cout.precision(11); cout << res << endl; } int main() { int T = 1, t; for (t = (0); t < (T); ++t) solve(t); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int M = 205; long long n, m, k, cnt, ans; long long g[N], h[N], dp[N][M]; struct redpocket { long long s, t, d, w; bool operator<(const redpocket &x) const { if (w == x.w) return d < x.d; return w < x.w; } } a[N]; priority_queue<redpocket> q; bool cmp(redpocket x, redpocket y) { return x.s < y.s; } signed main() { scanf( %lld %lld %lld , &n, &m, &k); for (long long i = 1; i <= k; i++) scanf( %lld %lld %lld %lld , &a[i].s, &a[i].t, &a[i].d, &a[i].w); sort(a + 1, a + k + 1, cmp); g[0] = 1; cnt = 1; for (long long i = 1; i <= n; i++) { while (i >= a[cnt].s && cnt <= k) q.push(a[cnt++]); if (q.empty()) g[i] = i + 1; else { if (q.top().t < i) { i--; q.pop(); continue; } g[i] = q.top().d + 1; h[i] = q.top().w; } } memset(dp, 0x3f, sizeof(dp)); dp[0][0] = 0; for (long long i = 0; i <= n; i++) { for (long long j = 0; j <= m; j++) { dp[i + 1][j + 1] = min(dp[i + 1][j + 1], dp[i][j]); dp[g[i]][j] = min(dp[g[i]][j], dp[i][j] + h[i]); } } ans = 0x3f3f3f3f3f3f3f3f; for (long long i = 0; i <= m; i++) ans = min(ans, dp[n + 1][i]); cout << ans; return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Internal BIOS for the VGA
// File : bios_interal.v
// Author : Frank Bruno
// Created : 04-July-2014
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// To make the VGA operate within an FPGA without a BIOS, this puts it in
// Block RAMs
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module bios_internal
(
input hb_clk,
input hresetn,
input bios_clk,
input bios_wdat,
input bios_csn,
output reg bios_rdat
);
reg [31:0] instruction_address_reg;
reg [23:0] read_address;
wire [15:0] rdata16;
reg [4:0] counter;
reg [1:0] prom_cs;
parameter read_cmd = 8'b00000011;
parameter IDLE = 0, DATA_OUT = 1, WAIT = 2, DATA_OUT1 = 3;
always @(posedge hb_clk, negedge hresetn) begin
if (!hresetn) begin
instruction_address_reg <= 'h0;
counter <= 0;
prom_cs <= IDLE;
end else begin
case (prom_cs)
IDLE: begin
if (!bios_csn && bios_clk) begin
counter <= counter + 1;
instruction_address_reg[~counter] <= bios_wdat;
if (counter == 'h1e) begin
prom_cs <= WAIT;
counter <= 0;
end
end else if (bios_csn)
counter <= 0;
end // case: IDLE
WAIT: prom_cs <= DATA_OUT;
DATA_OUT: begin
if (!bios_csn && !bios_clk) begin
counter <= counter + 1;
prom_cs <= DATA_OUT1;
end else if (bios_csn)
prom_cs <= IDLE;
end
DATA_OUT1: begin
if (!bios_csn && !bios_clk) begin
counter <= counter + 1;
if (counter == 'hf)
instruction_address_reg <= instruction_address_reg + 2;
if (~|counter) prom_cs <= IDLE;
end else if (bios_csn)
prom_cs <= IDLE;
end
endcase // case (prom_cs)
end // else: !if(!hresetn)
end // always @ (posedge bios_clk)
wire [2:0] inv_counter;
assign inv_counter = ~counter[2:0];
always @*
bios_rdat = rdata16[{~counter[3], inv_counter}];
bios_rom u_bios_rom
(
.clock (bios_clk),
.address (instruction_address_reg[15:1]), // [13:0]
.q (rdata16) // [15:0]
);
// Serial Read data back.
//always @(negedge bios_clk) bios_rdat <= rdata16[read_address[3:0]];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; int n, k, dep[N], fa[N]; bitset<N> s[2], t[4], a, b; vector<bitset<N> > S; inline bitset<N> qry(bitset<N> x, int y) { y = min(y, n - 1); char c[N]; putchar( ? ); for (int i = 1; i <= n; i++) printf( %d , x[i] ? y : 0); puts( ); fflush(stdout); scanf( %s , c + 1); for (int i = 1; i <= n; i++) if (c[i] == 1 ) x[i] = 1; return x; } int main() { scanf( %d , &n); while ((1 << k) <= n) k++; s[0][1] = 1; for (int i = 1; i <= n; i++) a[i] = 1; S.push_back(a); for (int i = k - 1; ~i; i--) { int len = 1 << i; for (int j = 0; j < 4; j++) t[j] = qry(s[j & 1], len - (j >> 1)); s[0] |= s[1]; s[1].reset(); vector<bitset<N> > nS; for (int j = 0; j < S.size(); j++) { a = t[j & 1] & S[j]; b = t[(j & 1) + 2] & S[j]; s[1] |= a ^ b; nS.push_back(b); nS.push_back(S[j] ^ b); } S = nS; } for (int i = 0; i < S.size(); i++) for (int j = 1; j <= n; j++) if (S[i][j]) dep[j] = i; for (int i = 0; i < 3; i++) for (int j = 0; j < k; j++) { a.reset(); for (int x = 1; x <= n; x++) a[x] = (dep[x] % 3 == i && (x >> j & 1)); a = qry(a, 1); for (int x = 1; x <= n; x++) fa[x] |= ((dep[x] + 2) % 3 == i && a[x]) << j; } puts( ! ); for (int i = 2; i <= n; i++) printf( %d %d n , fa[i], i); return 0; } |
#include <bits/stdc++.h> using namespace std; string s1, s2, virus; pair<int, int> dp[105][105][105]; int l1, l2, lvirus; string ans = ; int pi[105]; void pf(string s) { memset(pi, 0, sizeof(pi)); int n = (int)s.length(); for (int i = 1; i < n; ++i) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) j = pi[j - 1]; if (s[i] == s[j]) ++j; pi[i] = j; } } int main() { cin >> s1 >> s2 >> virus; l1 = s1.length(); l2 = s2.length(); lvirus = virus.length(); int i, j, k; for (i = 1; i <= l1; i++) { for (j = 1; j <= l2; j++) { for (k = 0; k < lvirus; k++) { if (dp[i][j][k].first <= dp[i - 1][j][k].first) { dp[i][j][k].first = dp[i - 1][j][k].first; dp[i][j][k].second = 1; } if (dp[i][j][k].first <= dp[i][j - 1][k].first) { dp[i][j][k].first = dp[i][j - 1][k].first; dp[i][j][k].second = 2; } if (s1[i - 1] == s2[j - 1]) { if (k != 0 && s1[i - 1] == virus[k - 1]) { if (dp[i][j][k].first < dp[i - 1][j - 1][k - 1].first + 1) { dp[i][j][k].first = dp[i - 1][j - 1][k - 1].first + 1; dp[i][j][k].second = 3; } } int z = k; if (s1[i - 1] != virus[z]) { char c = virus[z]; virus[z] = s1[i - 1]; pf(virus); int v = pi[z]; if (dp[i][j][v].first < dp[i - 1][j - 1][z].first + 1) { dp[i][j][v].first = dp[i - 1][j - 1][z].first + 1; dp[i][j][v].second = 10 + z; } virus[z] = c; } } } } } int mx = 0, cur = -1; for (i = 0; i < lvirus; i++) { if (mx <= dp[l1][l2][i].first) { cur = i; mx = dp[l1][l2][i].first; } } if (mx == 0) { cout << 0; return 0; } i = l1; j = l2; while (i != 0 && j != 0) { if (dp[i][j][cur].second == 1) { i--; continue; } if (dp[i][j][cur].second == 2) { j--; continue; } if (dp[i][j][cur].second == 3) { ans = s1[i - 1] + ans; i--; j--; cur--; continue; } ans = s1[i - 1] + ans; cur = dp[i][j][cur].second - 10; i--; j--; } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__MUX2_BEHAVIORAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; while (scanf( %d , &n) != EOF) { if (n & 1) { int d = (n - 1) / 2; printf( %d n , d * 2 + d * d - d); for (int i = 2; i < n; i += 2) { for (int j = 2; j < i; j += 2) { printf( 4 %d %d %d %d n , j, i, j + 1, i + 1); printf( 4 %d %d %d %d n , j, i, j + 1, i + 1); } printf( 3 1 %d %d n , i, i + 1); printf( 3 1 %d %d n , i, i + 1); } } else { int d = (n - 2) / 2; printf( %d n , 4 + (d - 1) * 3 + d * d - d); printf( 3 1 2 3 n ); printf( 3 1 2 4 n ); printf( 3 3 4 1 n ); printf( 3 3 4 2 n ); for (int i = 5; i < n; i += 2) { for (int j = 1; j < i - 2; j += 2) { printf( 4 %d %d %d %d n , j, i, j + 1, i + 1); printf( 4 %d %d %d %d n , j, i, j + 1, i + 1); } printf( 4 %d %d %d %d n , i - 2, i, i - 1, i + 1); printf( 3 %d %d %d n , i - 2, i, i + 1); printf( 3 %d %d %d n , i - 1, i, i + 1); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct no { long long i, h, m; }; long long dp[40][40][40]; char str[40]; no pre[40][40][40]; long long pw[19]; vector<char> ans; int main() { long long n; scanf( %lld , &n); scanf( %s , str + 1); pw[0] = 1; for (long long i = 1; i < 19; i++) pw[i] = pw[i - 1] * 10LL; for (long long i = 0; i < 40; i++) for (long long j = 0; j < 40; j++) for (long long k = 0; k < 40; k++) dp[i][j][k] = -9999999999999LL; dp[0][0][0] = 0; pre[0][0][0] = {-1, -1, -1}; for (long long i = 1; i <= 2 * n; i++) { for (long long h = 0; h <= n; h++) { for (long long m = 0; m <= n; m++) { if (h) { if (dp[i - 1][h - 1][m] + pw[n - h] * (str[i] - 0 ) > dp[i][h][m]) { dp[i][h][m] = dp[i - 1][h - 1][m] + pw[n - h] * (str[i] - 0 ); pre[i][h][m] = {i - 1, h - 1, m}; } } if (m) { if (dp[i - 1][h][m - 1] + pw[n - m] * (str[i] - 0 ) > dp[i][h][m]) { dp[i][h][m] = dp[i - 1][h][m - 1] + pw[n - m] * (str[i] - 0 ); pre[i][h][m] = {i - 1, h, m - 1}; } } } } } no check = {-1, -1, -1}; no tren = {2 * n, n, n}; no pred = pre[tren.i][tren.h][tren.m]; while (pred.i != -1) { if (tren.h == pred.h) ans.push_back( M ); else ans.push_back( H ); tren = pred; pred = pre[tren.i][tren.h][tren.m]; } reverse(ans.begin(), ans.end()); for (long long i = 0; i < ans.size(); i++) printf( %c , ans[i]); return 0; } |
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (WRITE FIRST)
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
wire RENA = ENA & !WEA;
wire WENA = ENA & WEA;
wire RENB = ENB & !WEB;
wire WENB = ENB & WEB;
altsyncram
#(
.width_a (DATA_WIDTH),
.widthad_a (ADDR_WIDTH),
.numwords_a (MEMSIZE),
.outdata_reg_a ((PIPELINED) ? "CLOCK0" : "UNREGISTERED"),
.address_aclr_a ("NONE"),
.outdata_aclr_a ("NONE"),
.indata_aclr_a ("NONE"),
.wrcontrol_aclr_a ("NONE"),
.byteena_aclr_a ("NONE"),
.width_byteena_a (1),
.width_b (DATA_WIDTH),
.widthad_b (ADDR_WIDTH),
.numwords_b (MEMSIZE),
.rdcontrol_reg_b ("CLOCK1"),//
.address_reg_b ("CLOCK1"),//
.outdata_reg_b ((PIPELINED) ? "CLOCK1" : "UNREGISTERED"),
.outdata_aclr_b ("NONE"),//
.rdcontrol_aclr_b ("NONE"),//
.indata_reg_b ("CLOCK1"),//
.wrcontrol_wraddress_reg_b ("CLOCK1"),//
.byteena_reg_b ("CLOCK1"),//
.indata_aclr_b ("NONE"),//
.wrcontrol_aclr_b ("NONE"),//
.address_aclr_b ("NONE"),//
.byteena_aclr_b ("NONE"),//
.width_byteena_b (1),
.clock_enable_input_a ("BYPASS"),
.clock_enable_output_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.clock_enable_core_a ("USE_INPUT_CLKEN"),//
.clock_enable_core_b ("USE_INPUT_CLKEN"),//
.read_during_write_mode_port_a ("new_data_no_nbe_read"),
.read_during_write_mode_port_b ("new_data_no_nbe_read"),
.enable_ecc ("FALSE"),//
.width_eccstatus (3),//
.ecc_pipeline_stage_enabled ("FALSE"),//
.operation_mode ("BIDIR_DUAL_PORT"),
.byte_size (8),//
.read_during_write_mode_mixed_ports ("old_data"),//
.ram_block_type ("AUTO"),//
.init_file ("UNUSED"),//
.init_file_layout ("UNUSED"),//
.maximum_depth (MEMSIZE), // number of elements in memory
.intended_device_family ("Stratix"),//
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"),
.lpm_type ("altsyncram"),//
.implement_in_les ("OFF"), //
.power_up_uninitialized ("FALSE")
)
RAM
(
.wren_a (WENA),
.rden_a (RENB),
.data_a (DIA),
.address_a (ADDRA),
.clock0 (CLKA),
.clocken0 (1'b1),
.clocken1 (1'b1),
.aclr0 (1'b0),
.byteena_a (1'b1),
.addressstall_a (1'b0),
.q_a (DOA),
.wren_b (WENB),
.rden_b (RENB),
.data_b (DIB),
.address_b (ADDRB),
.clock1 (CLKB),
.clocken2 (1'b1),
.clocken3 (1'b1),
.aclr1 (1'b0),
.byteena_b (1'b1),
.addressstall_b (1'b0),
.q_b (DOB),
.eccstatus ()
);
endmodule // BRAM2
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const double EPS = 1e-9; const long long INF = 1e18 + 2007; const double PI = 3.1415926535897932384626433832795; const long long N = 200005; long long gcd(long long a, long long b) { return a ? gcd(b % a, a) : b; } signed main() { ios_base::sync_with_stdio(0); long long n, k; cin >> n >> k; long long g = 0; for (long long i = 0; i < n; i++) { long long a; cin >> a; g = gcd(g, a); } set<long long> ans; for (long long i = 0; i < k; i++) { ans.insert((g * i) % k); } cout << ans.size() << endl; for (auto x : ans) { cout << x << ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__INV_PP_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_PP_BLACKBOX_V
|
module spiral_16(
i_data,
o_data_4,
o_data_13,
o_data_22,
o_data_31,
o_data_38,
o_data_46,
o_data_54,
o_data_61,
o_data_67,
o_data_73,
o_data_78,
o_data_82,
o_data_85,
o_data_88,
o_data_90
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [16:0] i_data;
output signed [16+7:0] o_data_4;
output signed [16+7:0] o_data_13;
output signed [16+7:0] o_data_22;
output signed [16+7:0] o_data_31;
output signed [16+7:0] o_data_38;
output signed [16+7:0] o_data_46;
output signed [16+7:0] o_data_54;
output signed [16+7:0] o_data_61;
output signed [16+7:0] o_data_67;
output signed [16+7:0] o_data_73;
output signed [16+7:0] o_data_78;
output signed [16+7:0] o_data_82;
output signed [16+7:0] o_data_85;
output signed [16+7:0] o_data_88;
output signed [16+7:0] o_data_90;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [23:0] w1,
w32,
w31,
w8,
w23,
w4,
w27,
w39,
w62,
w61,
w9,
w2,
w11,
w13,
w18,
w19,
w41,
w36,
w45,
w67,
w64,
w73,
w16,
w17,
w68,
w85,
w22,
w38,
w46,
w54,
w78,
w82,
w88,
w90;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign w1 = i_data;
assign w32 = w1 << 5;
assign w31 = w32 - w1;
assign w8 = w1 << 3;
assign w23 = w31 - w8;
assign w4 = w1 << 2;
assign w27 = w31 - w4;
assign w39 = w31 + w8;
assign w62 = w31 << 1;
assign w61 = w62 - w1;
assign w9 = w1 + w8;
assign w2 = w1 << 1;
assign w11 = w9 + w2;
assign w13 = w9 + w4;
assign w18 = w9 << 1;
assign w19 = w1 + w18;
assign w41 = w9 + w32;
assign w36 = w9 << 2;
assign w45 = w9 + w36;
assign w67 = w31 + w36;
assign w64 = w1 << 6;
assign w73 = w9 + w64;
assign w16 = w1 << 4;
assign w17 = w1 + w16;
assign w68 = w17 << 2;
assign w85 = w17 + w68;
assign w22 = w11 << 1;
assign w38 = w19 << 1;
assign w46 = w23 << 1;
assign w54 = w27 << 1;
assign w78 = w39 << 1;
assign w82 = w41 << 1;
assign w88 = w11 << 3;
assign w90 = w45 << 1;
assign o_data_4= w4;
assign o_data_13=w13;
assign o_data_22=w22;
assign o_data_31=w31;
assign o_data_38=w38;
assign o_data_46=w46;
assign o_data_54=w54;
assign o_data_61=w61;
assign o_data_67=w67;
assign o_data_73=w73;
assign o_data_78=w78;
assign o_data_82=w82;
assign o_data_85=w85;
assign o_data_88=w88;
assign o_data_90=w90;
endmodule
|
#include <bits/stdc++.h> const int N = 1000001; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, k; string s; cin >> n >> k >> s; m = s.size(); int last[200]; memset(last, -1, sizeof last); for (int i = 0; i < m; i++) { last[s[i]] = i; } pair<int, char> a[k]; for (int i = 0; i < k; i++) { a[i] = make_pair(last[ a + i], a + i); } sort(a, a + k); int ind = 0; for (int i = 0; i < n; i++) { s += a[ind].second; ind = (ind + 1) % k; } long long int dp[200]; memset(dp, 0, sizeof dp); long long int t = 0; for (char c : s) { long long int h = dp[c]; dp[c] = (t + 1 + 1000000007) % 1000000007; t = (t - h + dp[c] + 1000000007) % 1000000007; } cout << (t + 1) % 1000000007; } |
#include <bits/stdc++.h> using namespace std; int n, ret, f[26]; vector<pair<pair<int, int>, int> > ss; int call(char c) { return int(c) - int( a ); } int main() { cin >> n; string s; for (int i = 1; i <= n; i++) { cin >> s; ss.push_back(make_pair(make_pair(call(s[0]), call(s[long(s.length()) - 1])), long(s.length()))); } ret = 0; for (int c = 0; c < 26; c++) { fill(f + 0, f + 26, 0); for (int i = 0; i < n; i++) { if ((ss[i].first.first == c) || (f[ss[i].first.first] > 0)) { f[ss[i].first.second] = max(f[ss[i].first.second], f[ss[i].first.first] + ss[i].second); } } ret = max(ret, f[c]); } printf( %d , ret); return 0; } |
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/19/2017 11:15:00 AM
// Design Name: CRC Generator - Slave
// Module Name: crcGenerator
// Project Name: SD2017
// Target Devices: Basys3
// Revision: 1.02
// Revision 1.02 - CRC General generator and length
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// CRC Slave : should be used through CRC Master
// Priority Clear > Enable
module crcGenerator
#(parameter LEN = 7)(
input inputBit,
input clk,
input clear,
input enable, // will not activate on clk input
input [LEN:0] generator,
output reg [LEN - 1:0] crc
);
wire invert;
assign invert = inputBit ^ crc[LEN - 1];
integer _i = 0;
always @ (posedge clk) begin
if (clear) begin
crc = 0;
end
else if (enable) begin
for (_i = LEN - 1; _i > 0; _i = _i - 1) begin
crc[_i] = crc[_i - 1] ^ (invert & generator[_i]);
end
crc[0] = invert;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string x, y, z; int a = 0, c = 0; cin >> x; cin >> y; cin >> z; for (int i = 0; i < x.length(); i++) { for (int j = 0; j < z.length(); j++) { if (x[i] == z[j]) { c += 1; z[j] = 1 ; break; } } } for (int i = 0; i < y.length(); i++) { for (int j = 0; j < z.length(); j++) { if (y[i] == z[j]) { a += 1; z[j] = 1 ; break; } } } if (c + a == z.length() && a == y.length() && c == x.length()) cout << YES ; else cout << NO ; } |
module top;
parameter neg_pose = -2**2;
parameter neg_poso = -2**3;
parameter m1_pose = -1**2;
parameter m1_poso = -1**3;
parameter zero_pos = 0**2;
parameter one_pos = 1**2;
parameter pos_pos = 2**2;
parameter neg_zero = -2**0;
parameter m1_zero = -1**0;
parameter zero_zero = 0**0;
parameter one_zero = 1**0;
parameter pos_zero = 2**0;
parameter neg_neg = -2**-1;
parameter m1_nege = -1**-2;
parameter m1_nego = -1**-1;
parameter zero_neg = 0**-1;
parameter one_neg = 1**-1;
parameter pos_neg = 2**-1;
reg pass;
initial begin
pass = 1'b1;
/* Positive exponent. */
if (neg_pose !== 4) begin
$display("Failed neg**pos even, got %d", neg_pose);
pass = 1'b0;
end
if (neg_poso !== -8) begin
$display("Failed neg**pos odd, got %d", neg_poso);
pass = 1'b0;
end
if (m1_pose !== 1) begin
$display("Failed -1**pos even, got %d", m1_pose);
pass = 1'b0;
end
if (m1_poso !== -1) begin
$display("Failed -1**pos odd, got %d", m1_poso);
pass = 1'b0;
end
if (zero_pos !== 0) begin
$display("Failed 0**pos, got %d", zero_pos);
pass = 1'b0;
end
if (one_pos !== 1) begin
$display("Failed 1**pos, got %d", one_pos);
pass = 1'b0;
end
if (pos_pos !== 4) begin
$display("Failed 1**pos, got %d", pos_pos);
pass = 1'b0;
end
/* Zero exponent. */
if (neg_zero !== 1) begin
$display("Failed neg**0, got %d", neg_zero);
pass = 1'b0;
end
if (m1_zero !== 1) begin
$display("Failed -1**0, got %d", m1_zero);
pass = 1'b0;
end
if (zero_zero !== 1) begin
$display("Failed 0**0, got %d", zero_zero);
pass = 1'b0;
end
if (one_zero !== 1) begin
$display("Failed 1**0, got %d", one_zero);
pass = 1'b0;
end
if (pos_zero !== 1) begin
$display("Failed pos**0, got %d", pos_zero);
pass = 1'b0;
end
/* Negative exponent. */
if (neg_neg !== 0) begin
$display("Failed neg**neg got %d", neg_neg);
pass = 1'b0;
end
if (m1_nege !== 1) begin
$display("Failed -1**neg (even) got %d", m1_nege);
pass = 1'b0;
end
if (m1_nego !== -1) begin
$display("Failed -1**neg (odd) got %d", m1_nego);
pass = 1'b0;
end
if (zero_neg !== 'sbx) begin
$display("Failed 0**neg (odd) got %d", zero_neg);
pass = 1'b0;
end
if (one_neg !== 1) begin
$display("Failed 1**neg got %d", one_neg);
pass = 1'b0;
end
if (pos_neg !== 0) begin
$display("Failed pos**neg got %d", pos_neg);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2015 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Application : Vivado HLS
// / / Filename: tb_multiSRC_onboard.v
// /___/ /\ Timestamp: Tue May 12 5:00:00 PST 2015
// \ \ / \
// \___\/\___\
//
//Command: N/A
//Device: 7K325T-2
//Design Name: multiSRC
//Purpose:
// This file is the functional verification testbench for the multiSRC
// onboard test.
//Reference:
// XAPP1236
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module tb_multiSRC_onboard;
parameter CLKCYCLE = 4;
reg test_start;
wire test_done;
wire test_pass;
reg clk;
reg rst;
integer i;
wire ap_start;
wire ap_ready;
wire ap_idle;
wire ap_done;
wire dut_rst;
wire vld_x;
wire vld_y;
wire [15:0] x;
wire [2:0] rat;
wire [47:0] y;
//-----------------------------------
// generate clock and reset
//-----------------------------------
initial begin
clk=1'b0;
rst=1'b1;
#14;
@(posedge clk);
@(posedge clk);
@(posedge clk);
rst=1'b0;
end
//---- clock gen -------------------
always
#(CLKCYCLE/2) clk = ~clk;
//----------------------------------
initial begin
test_start=1'b0;
#30;
test_start=1'b1;
#100;
test_start=1'b0;
for(i=0;i< (2048+8192);i=i+1) begin
@(posedge clk);
end
test_start=1'b1;
#100;
test_start=1'b0;
end
test_bench_onboard TB
(
.clk(clk),
.rst(rst),
.test_start(test_start),
.test_done(test_done),
.test_pass(test_pass),
.ap_ready(ap_ready),
.ap_idle(ap_idle),
.ap_done(ap_done),
.dut_vld_y(vld_y),
.dut_y(y),
.dut_rst(dut_rst),
.dut_start(ap_start),
.dut_vld_x(vld_x),
.dut_x(x),
.dut_rat(rat)
);
multiSRC DUT(
.ap_clk(clk),
.ap_rst(dut_rst),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.vld_i(vld_x),
.x_i_V(x),
.rat_i_V(rat),
.vld_o(vld_y),
.y_o_V(y)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); string s; cin >> s; size_t pos1 = s.find( AB ), pos2 = s.find( BA ); string tmp = s; s.erase(0, pos1 + 2); tmp.erase(0, pos2 + 2); bool check = false; if (pos1 == string::npos || pos2 == string::npos) { cout << NO ; } else { if (s.find( BA ) != string::npos || tmp.find( AB ) != string::npos) check = true; if (check) cout << YES ; else cout << NO ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x * f; } long long qpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = 1ll * ans * a % 1000000007; a = 1ll * a * a % 1000000007; b >>= 1; } return ans % 1000000007; } signed main() { cin >> n >> m; long long c = n - m + 1; c *= 2; n++; n *= 2; m--; long long tot = qpow(n, m); long long amo = (c * tot) % 1000000007; amo %= 1000000007; cout << amo; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_TB_V
`define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_TB_V
/**
* dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage
* gates on keep-alive power rail.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s50kapwr.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg KAPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__dlybuf4s50kapwr dut (.A(A), .VPWR(VPWR), .VGND(VGND), .KAPWR(KAPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_TB_V
|
//#############################################################################
//# Function: Falling Edge Sampled Register #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module ohr_reg0 #(parameter DW = 1 // data width
)
( input nreset, //async active low reset
input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0
asic_reg0 ireg [DW-1:0] (.nreset(nreset),
.clk(clk),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
end
else
begin
reg [DW-1:0] out_reg;
always @ (negedge clk or negedge nreset)
if(~nreset)
out_reg[DW-1:0] <= 'b0;
else
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
end // else: !if(ASIC)
endgenerate
endmodule // ohr_reg0
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, i; cin >> n >> m >> k; vector<long long int> a(n), s1(m, 0), e1(m, 0), tot1(m, 0), s2(n, 0), e2(n, 0), tot2(n, 0); long long int b[m][3]; long long int c[k][2]; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < m; i++) { cin >> b[i][0] >> b[i][1] >> b[i][2]; b[i][0]--; b[i][1]--; } for (i = 0; i < k; i++) { cin >> c[i][0] >> c[i][1]; c[i][0]--; c[i][1]--; s1[c[i][0]]++; e1[c[i][1]]++; } long long int sum = 0; for (i = 0; i < m; i++) { tot1[i] = sum + s1[i]; sum += s1[i] - e1[i]; } for (i = 0; i < m; i++) { s2[b[i][0]] += tot1[i] * b[i][2]; e2[b[i][1]] += tot1[i] * b[i][2]; } sum = 0; for (i = 0; i < n; i++) { tot2[i] = sum + s2[i] + a[i]; sum += s2[i] - e2[i]; cout << tot2[i] << ; } } |
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(nullptr); cout.tie(NULL); ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) { string s; cin >> s; int ans = 0; int one; bool turn = true; while (s.size() != 0) { one = 0; vector<pair<int, int>> len; bool go = false; int start; for (int i = 0; i < s.size(); i++) { if (s[i] == 1 ) { if (!go) { start = i; go = true; } if (i == s.size() - 1) { len.push_back({start, i}); } one++; } else { if (go) { len.push_back({start, i - 1}); go = false; } } } if (!one) { cout << 0 n ; break; } int length = len[0].second - len[0].first; pair<int, int> se = {len[0].first, len[0].second}; for (int i = 1; i < len.size(); i++) { if (length < len[i].second - len[i].first) { length = len[i].second - len[i].first; se = {len[i].first, len[i].second}; } } if (turn) ans += length + 1; s.erase(se.first, length + 1); if (one - (length + 1) == 0) { cout << ans << n ; break; } if (turn) turn = false; else turn = true; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { int n; cin >> n; vector<int> v(n); set<int> st; for (int i = 0; i < n; i++) { cin >> v[i]; st.insert(v[i]); } sort(v.begin(), v.end()); int mx = v.back(); int ans = mx; if (mx % 2 == 0 && mx % 3 == 0 && mx % 5 == 0) { if (st.find(mx / 2) != st.end() && st.find(mx / 3) != st.end() && st.find(mx / 5) != st.end()) { ans = max(ans, mx / 2 + mx / 3 + mx / 5); } } vector<int> tmp; while (!st.empty() && tmp.size() < 3) { int x = *st.rbegin(); st.erase(prev(st.end())); bool f = 1; for (auto it : tmp) { if (it % x == 0 || x % it == 0) f = 0; } if (f) tmp.push_back(x); } int sum = 0; for (auto it : tmp) sum += it; ans = max(ans, sum); cout << ans << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_2_V
`define SKY130_FD_SC_MS__NAND4B_2_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_2_V
|
#include <bits/stdc++.h> using namespace std; static long long mi[400005][20]; static bool mark[400005][20]; static long long psum[400005]; long long f(int x, int k) { if (k == 0) return psum[x]; if (mark[x][k]) return mi[x][k]; mark[x][k] = 1; return mi[x][k] = min(f(x, k - 1), f(x + (1 << (k - 1)), k - 1)); } long long qry(int l, int r) { int t = r - l + 1; int lg = 31 - __builtin_clz(t); return min(f(l, lg), f(r - (1 << lg) + 1, lg)); } int main() { long long n, a, b, c, d, start, len; scanf( %lld %lld %lld %lld %lld %lld %lld , &n, &a, &b, &c, &d, &start, &len); vector<pair<long long, long long> > v; for (long long i = 0; i < n; i++) { long long x, y; scanf( %lld %lld , &x, &y); v.push_back(make_pair(y, x)); } if (v[0].first == 0) psum[0] = -d; else psum[0] = c; for (int i = 1; i < n; i++) { if (v[i].first) psum[i] = psum[i - 1] + c; else psum[i] = psum[i - 1] - d; } psum[n] = 1000000000000000000; vector<long long> t; t.push_back(0); for (int i = 0; i < n; i++) { t.push_back(v[i].second + 1); if (v[i].second - len + 1 >= 0) t.push_back(v[i].second - len + 1); } sort(t.begin(), t.end()); int l = 0, r = 0; long long at = start; for (int i = 0; i < t.size(); i++) { while (l < v.size() && v[l].second < t[i]) { if (v[l].first) at += a; else at -= b; if (at < 0) { printf( -1 n ); return 0; } l++; } while (r < v.size() && v[r].second < t[i] + len) r++; long long low = qry(l, r - 1) - (l > 0 ? psum[l - 1] : 0) + at; if (low >= 0) { printf( %lld n , t[i]); return 0; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probec_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long int MOD = 1e9 + 7; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; long long int a[n]; for (long long int i = 0; i < n; i++) { cin >> a[i]; } if (n == 1) { cout << 1 << n ; return 0; } long long int pre[n + 5]; long long int suf[n + 5]; long long int ans = 1; pre[0] = 1; suf[n - 1] = 1; for (long long int i = 1; i < n; i++) { if (a[i] > a[i - 1]) { pre[i] = pre[i - 1]; pre[i]++; } else { pre[i] = 1; } ans = max(pre[i], ans); } for (long long int i = n - 2; i >= 0; i--) { if (a[i] < a[i + 1]) { suf[i] = suf[i + 1]; suf[i]++; } else { suf[i] = 1; } ans = max(pre[i], ans); } for (long long int i = 1; i + 1 < n; i++) { if (a[i + 1] - a[i - 1] >= 2) { ans = max(ans, 1 + pre[i - 1] + suf[i + 1]); } ans = max(ans, 1 + pre[i - 1]); ans = max(ans, 1 + suf[i + 1]); } ans = max(ans, 1 + suf[1]); ans = max(ans, 1 + pre[n - 2]); cout << ans << n ; return 0; } |
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