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#include <bits/stdc++.h> int S(int x) { return x & 1 ? -(x + 1) / 2 : x / 2; } int main() { int q; scanf( %d , &q); while (q--) { int l, r; scanf( %d%d , &l, &r); printf( %d n , S(r) - S(l - 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; const long long xx = 2e7; const long long MOD = 1e9 + 7; const long long inf = 1e18; long long isprime(long long n) { if (n == 2) return 1; if (n % 2 == 0) return 0; for (long long i = 3; i * i <= n; i += 2) { if (n % i == 0) return 0; } return 1; } signed main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; if (isprime(n)) { cout << 1 << n ; } else if (n % 2 == 0 || isprime(n - 2)) { cout << 2 << n ; } else cout << 3 << n ; } |
#include <bits/stdc++.h> using namespace std; bool vis[100005]; int main() { int n; while (cin >> n) { int i, tag = 0, num = 0; for (i = 5;; i += 5) { int x = i; while (x % 5 == 0 && x) { num++; x /= 5; } if (num == n) { tag = 1; break; } else if (num > n) break; } if (tag) { cout << 5 << endl; for (int p = 0; p < 5; p++) cout << i + p << ; cout << endl; } else cout << 0 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; string s; int n, i, j, k, mx = 0, sum = 0, vis[5005], letter[26], check[26][5005][26], ok; double ans = 0; int main() { cin >> s; n = s.length(); s = s + s; for (i = 0; i < n; i++) { letter[s[i] - a ]++; for (j = i; j < i + n; j++) { check[s[i] - a ][j - i + 1][s[j] - a ]++; } } for (i = 0; i < 26; i++) { if (!letter[i]) continue; mx = -1; for (j = 2; j <= n; j++) { sum = 0; for (k = 0; k < 26; k++) if (check[i][j][k] == 1) sum += 1; mx = max(mx, sum); } ans += 1.0 * mx / n; } printf( %lf , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, string> mp; string get_type(string s) { if (mp.count(s)) return mp[s]; int n = s.size(); if (s[0] == & && s[n - 1] == * ) return get_type(s.substr(1, n - 2)); if (s[0] == & ) { string ret = get_type(s.substr(1, n - 1)); int sz = ret.size(); if (ret == void or ret == errtype ) return errtype ; else { if (ret[sz - 1] == * ) return ret.substr(0, sz - 1); return s[0] + ret; } } if (s[n - 1] == * ) { string ret = get_type(s.substr(0, n - 1)); if (ret[0] == & ) return ret.substr(1, n - 1); if (ret == errtype ) return errtype ; return get_type(s.substr(0, n - 1)) + s[n - 1]; } return errtype ; } void add_type(string u, string v) { mp[v] = get_type(u); } int main() { mp[ void ] = void ; mp[ &void ] = errtype ; mp[ errtype ] = errtype ; ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int q; cin >> q; while (q--) { string fun, u, v; cin >> fun; if (fun == typedef ) { cin >> u >> v; add_type(u, v); } else { cin >> u; cout << get_type(u) << n ; } } } |
#include <bits/stdc++.h> using namespace std; void read(long long &x) { x = 0; char c = getchar(); int f = 1; while (!(c >= 0 && c <= 9 )) { if (c == - ) f = -1; c = getchar(); } while ((c >= 0 && c <= 9 )) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } x *= f; } void output(long long x) { if (x < 0) { x = -x; putchar( - ); } if (x > 9) output(x / 10); putchar(x % 10 + 0 ); } struct node { long long l, r; mutable long long val; node(long long L) : l(L) {} node(long long L, long long R, long long VAL) : l(L), r(R), val(VAL) {} }; bool operator<(node x, node y) { return x.l < y.l; } set<node> s; set<node>::iterator split(long long pos) { set<node>::iterator it = s.lower_bound(node(pos)); if (it != s.end() && it->l == pos) return it; it--; long long l = it->l, r = it->r, val = it->val; s.erase(it); s.insert(node(l, pos - 1, val)); return s.insert(node(pos, r, val)).first; } void add(long long l, long long r, long long x) { set<node>::iterator it2 = split(r + 1), it1 = split(l); for (set<node>::iterator it = it1; it != it2; ++it) { it->val += x; } } long long kth(long long l, long long r, long long x) { set<node>::iterator it2 = split(r + 1), it1 = split(l); vector<pair<long long, long long> > v; v.clear(); for (set<node>::iterator it = it1; it != it2; ++it) { v.push_back(pair<long long, long long>(it->val, it->r - it->l + 1)); } sort(v.begin(), v.end()); for (long long i = 0; i < v.size(); ++i) { x -= v[i].second; if (x <= 0) return v[i].first; } } long long ksm(long long a, long long b, long long c) { a %= c; long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % c; a = (a * a) % c; b >>= 1; } return ans; } long long query(long long l, long long r, long long x, long long y) { long long ans = 0; set<node>::iterator it2 = split(r + 1), it1 = split(l); for (set<node>::iterator it = it1; it != it2; ++it) { ans = (ans + (it->r - it->l + 1) * ksm(it->val, x, y) % y) % y; } return ans; } void assign(long long l, long long r, long long k) { set<node>::iterator it2 = split(r + 1), it1 = split(l); s.erase(it1, it2); s.insert(node(l, r, k)); } long long n, m, seed, vmax; long long op, l, r, x, y; long long rnd() { long long ret = seed; seed = (seed * 7 + 13) % 1000000007; return ret; } void SWAP(long long &x, long long &y) { x ^= y; y ^= x; x ^= y; } int main() { read(n), read(m), read(seed), read(vmax); for (long long i = 1; i <= n; ++i) { x = (rnd() % vmax) + 1; s.insert(node(i, i, x)); } for (long long i = 1; i <= m; ++i) { op = (rnd() % 4) + 1; l = (rnd() % n) + 1; r = (rnd() % n) + 1; if (l > r) SWAP(l, r); if (op == 1) { x = (rnd() % vmax) + 1; add(l, r, x); } else if (op == 2) { x = (rnd() % vmax) + 1; assign(l, r, x); } else if (op == 3) { x = (rnd() % (r - l + 1)) + 1; output(kth(l, r, x)); putchar( n ); } else { x = (rnd() % vmax) + 1; y = (rnd() % vmax) + 1; output(query(l, r, x, y)); putchar( n ); } } return 0; } |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module altera_up_audio_bit_counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [ 4: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
module LCD_TEST ( // Host Side
iCLK,iRST_N,
// LCD Side
LCD_DATA,LCD_RW,LCD_EN,LCD_RS );
// Host Side
input iCLK,iRST_N;
// LCD Side
output [7:0] LCD_DATA;
output LCD_RW,LCD_EN,LCD_RS;
// Internal Wires/Registers
reg [5:0] LUT_INDEX;
reg [8:0] LUT_DATA;
reg [5:0] mLCD_ST;
reg [17:0] mDLY;
reg mLCD_Start;
reg [7:0] mLCD_DATA;
reg mLCD_RS;
wire mLCD_Done;
parameter LCD_INTIAL = 0;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+16;
parameter LCD_LINE2 = LCD_LINE1+16+1;
parameter LUT_SIZE = LCD_LINE1+32+1;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mLCD_ST <= 0;
mDLY <= 0;
mLCD_Start <= 0;
mLCD_DATA <= 0;
mLCD_RS <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mLCD_ST)
0: begin
mLCD_DATA <= LUT_DATA[7:0];
mLCD_RS <= LUT_DATA[8];
mLCD_Start <= 1;
mLCD_ST <= 1;
end
1: begin
if(mLCD_Done)
begin
mLCD_Start <= 0;
mLCD_ST <= 2;
end
end
2: begin
if(mDLY<18'h3FFFE)
mDLY <= mDLY+1;
else
begin
mDLY <= 0;
mLCD_ST <= 3;
end
end
3: begin
LUT_INDEX <= LUT_INDEX+1;
mLCD_ST <= 0;
end
endcase
end
end
end
always
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h120; // Welcome to the
LCD_LINE1+1: LUT_DATA <= 9'h157;
LCD_LINE1+2: LUT_DATA <= 9'h165;
LCD_LINE1+3: LUT_DATA <= 9'h16C;
LCD_LINE1+4: LUT_DATA <= 9'h163;
LCD_LINE1+5: LUT_DATA <= 9'h16F;
LCD_LINE1+6: LUT_DATA <= 9'h16D;
LCD_LINE1+7: LUT_DATA <= 9'h165;
LCD_LINE1+8: LUT_DATA <= 9'h120;
LCD_LINE1+9: LUT_DATA <= 9'h174;
LCD_LINE1+10: LUT_DATA <= 9'h16F;
LCD_LINE1+11: LUT_DATA <= 9'h120;
LCD_LINE1+12: LUT_DATA <= 9'h174;
LCD_LINE1+13: LUT_DATA <= 9'h168;
LCD_LINE1+14: LUT_DATA <= 9'h165;
LCD_LINE1+15: LUT_DATA <= 9'h120;
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
LCD_LINE2+0: LUT_DATA <= 9'h120; // Altera DE2-70
LCD_LINE2+1: LUT_DATA <= 9'h141;
LCD_LINE2+2: LUT_DATA <= 9'h16C;
LCD_LINE2+3: LUT_DATA <= 9'h174;
LCD_LINE2+4: LUT_DATA <= 9'h165;
LCD_LINE2+5: LUT_DATA <= 9'h172;
LCD_LINE2+6: LUT_DATA <= 9'h161;
LCD_LINE2+7: LUT_DATA <= 9'h120;
LCD_LINE2+8: LUT_DATA <= 9'h144;
LCD_LINE2+9: LUT_DATA <= 9'h145;
LCD_LINE2+10: LUT_DATA <= 9'h132;
LCD_LINE2+11: LUT_DATA <= 9'h1B0;
LCD_LINE2+12: LUT_DATA <= 9'h137;
LCD_LINE2+13: LUT_DATA <= 9'h130;
LCD_LINE2+14: LUT_DATA <= 9'h120;
LCD_LINE2+15: LUT_DATA <= 9'h120;
default: LUT_DATA <= 9'h120;
endcase
end
LCD_Controller u0 ( // Host Side
.iDATA(mLCD_DATA),
.iRS(mLCD_RS),
.iStart(mLCD_Start),
.oDone(mLCD_Done),
.iCLK(iCLK),
.iRST_N(iRST_N),
// LCD Interface
.LCD_DATA(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS) );
endmodule |
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module \$__QLF_FACTOR_BRAM36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [14:0] A1ADDR_15;
wire [14:0] B1ADDR_15;
//wire [7:0] B1EN_8 = //B1EN;
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
wire [31:0] DOBDO;
wire [3:0] DOPBDOP;
//wire [2:0] WRITEDATAWIDTHB;
//wire [2:0] READDATAWIDTHA;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
assign A1ADDR_15[14:CFG_ABITS] = 0;
assign A1ADDR_15[CFG_ABITS-1:0] = A1ADDR;
assign B1ADDR_15[14:CFG_ABITS] = 0;
assign B1ADDR_15[CFG_ABITS-1:0] = B1ADDR;
/*if (CFG_DBITS == 1) begin
assign WRITEDATAWIDTHB = 3'b000;
assign READDATAWIDTHA = 3'b000;
end else if (CFG_DBITS == 2) begin
assign WRITEDATAWIDTHB = 3'b001;
assign READDATAWIDTHA = 3'b001;
end else if (CFG_DBITS > 2 && CFG_DBITS <= 4) begin
assign WRITEDATAWIDTHB = 3'b010;
assign READDATAWIDTHA = 3'b010;
end else if (CFG_DBITS > 4 && CFG_DBITS <= 9) begin
assign WRITEDATAWIDTHB = 3'b011;
assign READDATAWIDTHA = 3'b011;
end else if (CFG_DBITS > 9 && CFG_DBITS <= 18) begin
assign WRITEDATAWIDTHB = 3'b100;
assign READDATAWIDTHA = 3'b100;
end else if (CFG_DBITS > 18 && CFG_DBITS <= 36) begin
assign WRITEDATAWIDTHB = 3'b101;
assign READDATAWIDTHA = 3'b101;
end*/
generate if (CFG_DBITS > 8) begin
TDP_BRAM36 #(
//`include "brams_init_36.vh"
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
) _TECHMAP_REPLACE_ (
.WRITEDATAA(32'hFFFFFFFF),
.WRITEDATAAP(4'hF),
.READDATAA(DO[31:0]),
.READDATAAP(DOP[3:0]),
.ADDRA(A1ADDR_15),
.CLOCKA(CLK2),
.READENABLEA(A1EN),
.WRITEENABLEA(1'b0),
.BYTEENABLEA(4'b0),
//.WRITEDATAWIDTHA(3'b0),
//.READDATAWIDTHA(READDATAWIDTHA),
.WRITEDATAB(DI),
.WRITEDATABP(DIP),
.READDATAB(DOBDO),
.READDATABP(DOPBDOP),
.ADDRB(B1ADDR_15),
.CLOCKB(CLK3),
.READENABLEA(1'b0),
.WRITEENABLEB(1'b1),
.BYTEENABLEB(B1EN)
//.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
//.READDATAWIDTHB(3'b0)
);
end else begin
TDP_BRAM36 #(
//`include "brams_init_32.vh"
) _TECHMAP_REPLACE_ (
.WRITEDATAA(32'hFFFFFFFF),
.WRITEDATAAP(4'hF),
.READDATAA(DO[31:0]),
.READDATAAP(DOP[3:0]),
.ADDRA(A1ADDR_15),
.CLOCKA(CLK2),
.READENABLEA(A1EN),
.WRITEENABLEA(1'b0),
.BYTEENABLEA(4'b0),
//.WRITEDATAWIDTHA(3'b0),
//.READDATAWIDTHA(READDATAWIDTHA),
.WRITEDATAB(DI),
.WRITEDATABP(DIP),
.READDATAB(DOBDO),
.READDATABP(DOPBDOP),
.ADDRB(B1ADDR_15),
.CLOCKB(CLK3),
.READENABLEB(1'b0),
.WRITEENABLEB(1'b1),
.BYTEENABLEB(B1EN)
//.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
//.READDATAWIDTHB(3'b0)
);
end endgenerate
endmodule
// ------------------------------------------------------------------------
module \$__QLF_FACTOR_BRAM18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [13:0] A1ADDR_14;
wire [13:0] B1ADDR_14;
//wire [3:0] B1EN_4 = B1EN;
wire [1:0] DIP, DOP;
wire [15:0] DI, DO;
wire [15:0] DOBDO;
wire [1:0] DOPBDOP;
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
assign A1ADDR_14[13:CFG_ABITS] = 0;
assign A1ADDR_14[CFG_ABITS-1:0] = A1ADDR;
assign B1ADDR_14[13:CFG_ABITS] = 0;
assign B1ADDR_14[CFG_ABITS-1:0] = B1ADDR;
/*if (CFG_DBITS == 1) begin
assign WRITEDATAWIDTHB = 3'b000;
assign READDATAWIDTHA = 3'b000;
end else if (CFG_DBITS == 2) begin
assign WRITEDATAWIDTHB = 3'b001;
assign READDATAWIDTHA = 3'b001;
end else if (CFG_DBITS > 2 && CFG_DBITS <= 4) begin
assign WRITEDATAWIDTHB = 3'b010;
assign READDATAWIDTHA = 3'b010;
end else if (CFG_DBITS > 4 && CFG_DBITS <= 9) begin
assign WRITEDATAWIDTHB = 3'b011;
assign READDATAWIDTHA = 3'b011;
end else if (CFG_DBITS > 9 && CFG_DBITS <= 18) begin
//assign WRITEDATAWIDTHB = 3'b100;
assign READDATAWIDTHA = 3'b100;
end*/
generate if (CFG_DBITS > 8) begin
TDP_BRAM18 #(
//`include "brams_init_18.vh"
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
) _TECHMAP_REPLACE_ (
.WRITEDATAA(16'hFFFF),
.WRITEDATAAP(2'b11),
.READDATAA(DO[15:0]),
.READDATAAP(DOP[2:0]),
.ADDRA(A1ADDR_14),
.CLOCKA(CLK2),
.READENABLEA(A1EN),
.WRITEENABLEA(1'b0),
.BYTEENABLEA(2'b0),
//.WRITEDATAWIDTHA(3'b0),
//.READDATAWIDTHA(READDATAWIDTHA),
.WRITEDATAB(DI),
.WRITEDATABP(DIP),
.READDATAB(DOBDO),
.READDATABP(DOPBDOP),
.ADDRB(B1ADDR_14),
.CLOCKB(CLK3),
.READENABLEB(1'b0),
.WRITEENABLEB(1'b1),
.BYTEENABLEB(B1EN)
//.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
//.READDATAWIDTHB(3'b0)
);
end else begin
TDP_BRAM18 #(
//`include "brams_init_16.vh"
) _TECHMAP_REPLACE_ (
.WRITEDATAA(16'hFFFF),
.WRITEDATAAP(2'b11),
.READDATAA(DO[15:0]),
.READDATAAP(DOP[2:0]),
.ADDRA(A1ADDR_14),
.CLOCKA(CLK2),
.READENABLEA(A1EN),
.WRITEENABLEA(1'b0),
.BYTEENABLEA(2'b0),
//.WRITEDATAWIDTHA(3'b0),
// .READDATAWIDTHA(READDATAWIDTHA),
.WRITEDATAB(DI),
.WRITEDATABP(DIP),
.READDATAB(DOBDO),
.READDATABP(DOPBDOP),
.ADDRB(B1ADDR_14),
.CLOCKB(CLK3),
.READENABLEB(1'b0),
.WRITEENABLEB(1'b1),
.BYTEENABLEB(B1EN)
//.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
//.READDATAWIDTHB(3'b0)
);
end endgenerate
endmodule
|
`timescale 1 ns / 1 ps
module axis_variant #
(
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire cfg_flag,
input wire [AXIS_TDATA_WIDTH-1:0] cfg_data0,
input wire [AXIS_TDATA_WIDTH-1:0] cfg_data1,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg;
reg int_tvalid_reg, int_tvalid_next;
wire [AXIS_TDATA_WIDTH-1:0] int_tdata_wire;
assign int_tdata_wire = cfg_flag ? cfg_data1 : cfg_data0;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_tvalid_reg <= 1'b0;
end
else
begin
int_tdata_reg <= int_tdata_wire;
int_tvalid_reg <= int_tvalid_next;
end
end
always @*
begin
int_tvalid_next = int_tvalid_reg;
if(int_tdata_reg != int_tdata_wire)
begin
int_tvalid_next = 1'b1;
end
if(m_axis_tready & int_tvalid_reg)
begin
int_tvalid_next = 1'b0;
end
end
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2710; const double eps = 1e-9; const double pi = 3.1415926536; int dp[maxn][maxn]; string s; int main(int argc, char const *argv[]) { dp[0][0] = 1; for (int i = 1; i <= 100; i++) { for (int j = 0; j <= (i - 1) * 26; j++) { for (int k = 0; k < 26; k++) { dp[i][j + k] = (dp[i][j + k] + dp[i - 1][j]) % 1000000007; } } } int t; std::cin >> t; while (t--) { std::cin >> s; int len; len = s.size(); int sum = 0; for (int i = 0; i < len; i++) { sum += s[i] - a ; } std::cout << dp[len][sum] - 1 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long int var; scanf( %ld , &var); if (var >= 0) cout << var; else { int a, b; a = var % 10; var /= 10; b = var % 10; var /= 10; if (a > b) var = var * 10 + a; else var = var * 10 + b; cout << var; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:47:33 01/18/2017
// Design Name:
// Module Name: right_barrel_shifter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module right_barrel_shifter(
input [7:0] d_in,
input [2:0] shift_amount,
output reg [7:0] d_out
);
//Examples:
// 0 no change
// 1 : in: 10000000 out: 01000000
// 2 : in: 10000000 out: 00100000
// 3 : in: 10000000 out: 00010000
always @* begin
case (shift_amount)
0 : d_out = d_in;
1 : d_out = {d_in[0], d_in[7:1]}; //done
2 : d_out = {d_in[1:0], d_in[7:2]};
3 : d_out = {d_in[2:0], d_in[7:3]};
4 : d_out = {d_in[3:0], d_in[7:4]};
5 : d_out = {d_in[4:0], d_in[7:5]};
6 : d_out = {d_in[5:0], d_in[7:6]};
7 : d_out = 0;
endcase
end
endmodule
|
//TODO: Allow burst size = 1
//TODO: Add timeout counter to clear out FIFO
module wb_stream_reader_ctrl
#(parameter WB_AW = 32,
parameter WB_DW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 0)
(//Stream data output
input wb_clk_i,
input wb_rst_i,
output [WB_AW-1:0] wbm_adr_o,
output [WB_DW-1:0] wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output wbm_we_o ,
output wbm_cyc_o,
output wbm_stb_o,
output reg [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [WB_DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
//FIFO interface
input [WB_DW-1:0] fifo_d,
output fifo_rd,
input [FIFO_AW:0] fifo_cnt,
//Configuration interface
output reg busy,
input enable,
output reg [WB_DW-1:0] tx_cnt,
input [WB_AW-1:0] start_adr,
input [WB_AW-1:0] buf_size,
input [WB_AW-1:0] burst_size);
wire active;
wire timeout = 1'b0;
reg last_adr;
reg [$clog2(MAX_BURST_LEN-1):0] burst_cnt;
//FSM states
localparam S_IDLE = 0;
localparam S_ACTIVE = 1;
reg [1:0] state;
wire burst_end = (burst_cnt == burst_size-1);
wire fifo_ready = (fifo_cnt >= burst_size) & (fifo_cnt > 0);
always @(active or burst_end) begin
wbm_cti_o = !active ? 3'b000 :
burst_end ? 3'b111 :
3'b010; //LINEAR_BURST;
end
assign active = (state == S_ACTIVE);
assign fifo_rd = wbm_ack_i;
assign wbm_sel_o = 4'hf;
assign wbm_we_o = active;
assign wbm_cyc_o = active;
assign wbm_stb_o = active;
assign wbm_bte_o = 2'b00;
assign wbm_dat_o = fifo_d;
assign wbm_adr_o = start_adr + tx_cnt*4;
always @(posedge wb_clk_i) begin
//Address generation
last_adr = (tx_cnt == buf_size[WB_AW-1:2]-1);
if (wbm_ack_i)
if (last_adr)
tx_cnt <= 0;
else
tx_cnt <= tx_cnt+1;
//Burst counter
if(!active)
burst_cnt <= 0;
else
if(wbm_ack_i)
burst_cnt <= burst_cnt + 1;
//FSM
case (state)
S_IDLE : begin
if (busy & fifo_ready)
state <= S_ACTIVE;
if (enable)
busy <= 1'b1;
end
S_ACTIVE : begin
if (burst_end & wbm_ack_i) begin
state <= S_IDLE;
if (last_adr)
busy <= 1'b0;
end
end
default : begin
state <= S_IDLE;
end
endcase // case (state)
if(wb_rst_i) begin
state <= S_IDLE;
tx_cnt <= 0;
busy <= 1'b0;
end
end
endmodule
|
// This module defines a simple implementation of the Digital Phase Lock Loop
// (DPLL) described in Texas Instruments's SDLA005B application node
module dpll (rst, clk_in, clk_ref, clk_out, clk_out_8x);
input wire rst;
input wire clk_in;
input wire clk_ref;
output wire clk_out;
output wire clk_out_8x;
reg [7:0] k_count_up, k_count_down, n_count;
reg borrow, carry, id_out;
wire decrement, increment, down_upn;
parameter S_LOW_CYCLE = 3'b000,
S_HIGH_CYCLE = 3'b001,
S_LOW_CYCLE2 = 3'b010,
S_HIGH_CYCLE2 = 3'b011,
S_LOW_CYCLE3 = 3'b100,
S_HIGH_CYCLE3 = 3'b101;
reg [2:0] state, next;
// Phase Detector
assign down_upn = clk_in ^ clk_out;
// K Counter
always @(posedge clk_ref or posedge rst)
begin
if (rst) begin
k_count_down <= 8'h00;
k_count_up <= 8'h00;
end else begin
if (down_upn) k_count_down <= k_count_down - 1;
else k_count_up <= k_count_up + 1;
end
end
always @(k_count_down)
begin
if (k_count_down == 8'h00) borrow = 1;
else borrow = 0;
end
always @(k_count_up)
begin
if (k_count_up == 8'hFF) carry = 1;
else carry = 0;
end
edgedet edge_inst1 (
.rst(rst),
.clk(clk_ref),
.sig(borrow),
.rising_or_falling(),
.rising(decrement),
.falling()
);
edgedet edge_inst2 (
.rst(rst),
.clk(clk_ref),
.sig(carry),
.rising_or_falling(),
.rising(increment),
.falling()
);
// I/D
always @(posedge clk_ref or posedge rst)
if (rst) state <= S_LOW_CYCLE;
else state <= next;
always @(state or increment or decrement) begin
next = 'bx;
case (state)
S_LOW_CYCLE : if (decrement) next = S_LOW_CYCLE;
else if (increment) next = S_HIGH_CYCLE2;
else next = S_HIGH_CYCLE;
S_HIGH_CYCLE : if (increment) next = S_HIGH_CYCLE;
else if (decrement) next = S_LOW_CYCLE2;
else next = S_LOW_CYCLE;
S_HIGH_CYCLE2 : if (decrement) next = S_HIGH_CYCLE3;
else next = S_HIGH_CYCLE;
S_LOW_CYCLE2 : if (increment) next = S_LOW_CYCLE3;
else next = S_LOW_CYCLE;
S_HIGH_CYCLE3 : next = S_LOW_CYCLE2;
S_LOW_CYCLE3 : next = S_HIGH_CYCLE2;
endcase
end
always @(posedge clk_ref or posedge rst)
if (rst) begin
id_out <= 0;
end
else begin
id_out <= 0;
case (next)
S_HIGH_CYCLE: id_out <= 1;
S_HIGH_CYCLE2: id_out <= 1;
S_HIGH_CYCLE3: id_out <= 1;
endcase
end
// /N Counter
always @(posedge clk_ref or posedge rst)
begin
if (rst) begin
n_count <= 8'h00;
end else begin
if (id_out) n_count <= n_count + 1;
end
end
assign clk_out = n_count[7];
assign clk_out_8x = n_count[3];
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long in() { int32_t x; scanf( %d , &x); return x; } inline string getStr() { char ch[1000000]; scanf( %s , ch); return ch; } const long long MOD = 1e9 + 7; const long long base = 29; const long long MAX_N = 3e5 + 1; inline long long divide(long long a, long long b) { return (a + b - 1) / b; } vector<long long> g[MAX_N]; long long deg[MAX_N]; bool vis[MAX_N]; long long res[MAX_N]; inline void dfs(long long node, long long part) { if (vis[node] == true) return; res[node] = part; long long cnt = 0; for (long long i = 0; i < g[node].size(); i++) { long long u = g[node][i]; if (res[node] == res[u]) cnt++; } if (cnt > 1) { res[node] ^= 1; dfs(node, res[node]); vis[node] = false; return; } vis[node] = true; for (long long pt = 0; pt < g[node].size(); pt++) { long long u = g[node][pt]; if (res[u] == res[node]) { dfs(u, res[u]); vis[node] = 0; return; } } vis[node] = false; } int32_t main() { long long n = in(), m = in(); for (long long i = 0; i < m; i++) { long long v = in(), u = in(); deg[v]++, deg[u]++; g[v].push_back(u); g[u].push_back(v); } for (long long i = 1; i <= n; i++) res[i] = 1; for (long long i = 1; i <= n; i++) { dfs(i, res[i]); } for (long long i = 1; i <= n; i++) cout << res[i]; } |
// AGrises.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
// grey <= (R*8'd30 + G*8'd59 + B*8'd11)/8'd100;
`timescale 1 ps / 1 ps
module AGrises (
input clk,
input rst,
output [DATA_WIDTH-1:0] data_fifo_out,
output data_valid_fifo_out,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out,
input wire [DATA_WIDTH-1:0] data_fifo_in,
output read_fifo_in,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in,
input start,
output endf
);
parameter DATA_WIDTH=32;
parameter FIFO_DEPTH = 256;
parameter FIFO_DEPTH_LOG2 = 8;
reg [1:0] stages;
wire stages_init;
reg [1:0] run;
reg [14:0] grey_aux;
reg [7:0] grey;
reg [18:0] pixel_counter;
always @ (posedge clk or posedge rst) begin
if (rst == 1) begin
run <= 0;
end else begin
if (start == 1) begin
run <= 1;
end else begin
if (pixel_counter == 0) begin
run <= 2;
end
if (endf == 1) begin
run <= 0;
end
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
pixel_counter <= 384000;
end else begin
if (data_valid_fifo_out) begin
pixel_counter <= pixel_counter - 1;
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
stages <= 0;
end else begin
if (stages_init == 1) begin
stages <= 1;
grey_aux = data_fifo_in[23:16]*8'd30 + data_fifo_in[15:8]*8'd59 + data_fifo_in[7:0]*8'd11;
grey = 8'd2 * grey_aux[14:8];
grey = grey + (grey_aux[14:8] / 8'd2);
end else begin
if (stages == 1) begin
stages <= 2;
grey = grey + (grey_aux[14:8] / 8'd19);
grey = grey + (grey_aux[7:0] / 8'd64);
end else begin
if (stages == 2) begin
stages <= 0;
end
end
end
end
end
assign stages_init = ((usedw_fifo_in > 32)|(pixel_counter < 33)) & (usedw_fifo_out < FIFO_DEPTH) & (run == 1) & (stages == 0);
assign read_fifo_in = (run == 1) & (stages == 1);
assign data_fifo_out = {8'd0,{3{grey}}};
assign data_valid_fifo_out = (run == 1) & (stages == 2);
assign endf = (run == 2);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while(t--){ int n; cin >> n; if((n / 2020 > 0) && ((n % 2020) <= (n / 2020))){ cout << YES n ; }else{ cout << NO n ; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKBUF_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////-
// Design unit: vm (All In One)
// :
// File name : vm.v
// :
// Description: RTL Design of Vending Machine
// :
// Limitations: None
// :
// System : Verilog
// :
// Author : 1. Wan Ahmad Zainie bin Wan Mohamad (ME131135)
// :
// : 2. Azfar 'Aizat bin Mohd Isa (ME131032)
// :
//
// Revision : Version 0.1 2014-06-01
// : Version 1.0 2014-06-09 Ready for submission
// : Version 2.0 2014-06-10 Change to behavioral
////////////////////////////////////////////////////////////////////-
module vm(clk, rst, deposit, deposited, select, selected, price, cancel, maintenance,
refund, refundall, depositall, product, change, state);
input clk, rst;
input [9:0] deposit, price;
input [4:0] select;
input deposited, selected, cancel, maintenance;
output refund, refundall, depositall;
output [4:0] product;
output [9:0] change;
output [2:0] state;
wire ldRdeposit, ldRselect, ldRprice, ldA, ldRproduct, ldRchange;
wire ldRpurchase, ldMprice, ldMquantity, clrRdeposit, clrRselect;
wire clrRprice, clrA, clrRproduct, clrRchange, clrRpurchase, purchase;
du myDU(clk, rst, deposit, select, price, ldRdeposit, ldRselect, ldRprice,
ldA, ldRproduct, ldRchange, ldRpurchase, ldMprice, ldMquantity,
clrRdeposit, clrRselect, clrRprice, clrA, clrRproduct, clrRchange,
clrRpurchase, purchase, refund, product, change);
cu myCU(clk, rst, deposited, selected, cancel, maintenance, purchase,
ldRdeposit, ldRselect, ldRprice, ldA, ldRproduct, ldRchange,
ldRpurchase, ldMprice, ldMquantity, clrRdeposit, clrRselect,
clrRprice, clrA, clrRproduct, clrRchange, clrRpurchase,
refundall, depositall, state);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_bram_v6.v
// Version : 2.3
//--
//-- Description: BlockRAM module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_v6
#(
parameter DOB_REG = 0,// 1 use the output register 0 don't use the output register
parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = "NO_CHANGE";
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if (WIDTH == 72) begin : use_ramb36sdp
// use RAMB36SDP if the width is 72
RAMB36SDP #(
.DO_REG (DOB_REG)
)
ramb36sdp(
.WRCLK (user_clk_i),
.SSR (1'b0),
.WRADDR (waddr_i[ADDR_MSB:0]),
.DI (wdata_i[D_MSB:0]),
.DIP (wdata_i[DP_MSB:DP_LSB]),
.WREN (wen_i),
.WE ({8{wen_i}}),
.DBITERR (),
.ECCPARITY (),
.SBITERR (),
.RDCLK (user_clk_i),
.RDADDR (raddr_i[ADDR_MSB:0]),
.DO (rdata_o[D_MSB:0]),
.DOP (rdata_o[DP_MSB:DP_LSB]),
.RDEN (ren_i),
.REGCE (rce_i)
);
// use RAMB36's if the width is 4, 9, 18, or 36
end else if (WIDTH == 36) begin : use_ramb36
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA (wdata_i[D_MSB:0]),
.DIPA (wdata_i[DP_MSB:DP_LSB]),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB (rdata_o[D_MSB:0]),
.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH < 36 && WIDTH > 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
wire [ 4 - DPW - 1 : 0] dopb_unused;
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
.DIPA ({{ 4 - DPW {1'b0}},wdata_i[DP_MSB:DP_LSB]}),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB ({dob_unused, rdata_o[D_MSB:0]}),
.DOPB ({dopb_unused, rdata_o[DP_MSB:DP_LSB]}),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH == 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
RAMB36 #(
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
//.DIPA (wdata_i[DP_MSB:DP_LSB]),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB ({dob_unused,rdata_o[D_MSB:0]}),
//.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end // block: use_ramb36
endgenerate
endmodule // pcie_bram_v6
|
module alt_vipitc131_common_frame_counter
#(parameter
NUMBER_OF_COLOUR_PLANES = 0,
COLOUR_PLANES_ARE_IN_PARALLEL = 0,
LOG2_NUMBER_OF_COLOUR_PLANES = 0,
CONVERT_SEQ_TO_PAR = 0,
TOTALS_MINUS_ONE = 0)
(
input wire rst,
input wire clk,
input wire sclr,
// control signals
input wire enable,
input wire hd_sdn,
// frame sizes
input wire [13:0] h_total,
input wire [12:0] v_total,
// reset values
input wire [13:0] h_reset,
input wire [12:0] v_reset,
// outputs
output wire new_line,
output wire start_of_sample,
output wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks,
output reg [13:0] h_count,
output reg [12:0] v_count);
wire count_sample;
alt_vipitc131_common_sample_counter sample_counter(
.rst(rst),
.clk(clk),
.sclr(sclr),
.hd_sdn(hd_sdn),
.count_cycle(enable),
.count_sample(count_sample),
.start_of_sample(start_of_sample),
.sample_ticks(sample_ticks));
defparam sample_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
sample_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
sample_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES;
wire [13:0] h_total_int;
wire [12:0] v_total_int;
generate
if(TOTALS_MINUS_ONE) begin : totals_minus_one_generate
assign h_total_int = h_total;
assign v_total_int = v_total;
end else begin
assign h_total_int = h_total - 14'd1;
assign v_total_int = v_total - 13'd1;
end
endgenerate
always @ (posedge rst or posedge clk) begin
if(rst) begin
h_count <= 14'd0;
v_count <= 13'd0;
end else begin
if(sclr) begin
h_count <= h_reset + {{13{1'b0}}, count_sample & hd_sdn};
v_count <= v_reset;
end else if(enable) begin
if(new_line) begin
h_count <= 14'd0;
if(v_count >= v_total_int)
v_count <= 13'd0;
else
v_count <= v_count + 13'd1;
end else if(count_sample)
h_count <= h_count + 14'd1;
end
end
end
assign new_line = (h_count >= h_total_int) && count_sample;
endmodule
|
module SDRAM_test(
input reset_n, // Module reset.
inout [15:0] dram_dq, // SDRAM Data bus 16 Bits
output [11:0] dram_addr, // SDRAM Address bus 12 Bits
output dram_ldqm, // SDRAM Low-byte Data Mask
output dram_udqm, // SDRAM High-byte Data Mask
output dram_we_n, // SDRAM Write Enable
output dram_cas_n, // SDRAM Column Address Strobe
output dram_ras_n, // SDRAM Row Address Strobe
output dram_cs_n, // SDRAM Chip Select
output dram_ba_0, // SDRAM Bank Address 0
output dram_ba_1, // SDRAM Bank Address 1
input dram_clk, // SDRAM Clock
output dram_cke, // SDRAM Clock Enable
input dram_clk_locked, // SDRAM Clock PLL is locked.
output [15:0] debug_number // 16-bit number displayed on 7-segment display.
);
// State machine.
localparam STATE_INIT = 5'h00;
localparam STATE_WAIT = 5'h01; // Needs state_wait_count and state_wait_next_state.
localparam STATE_PRECHARGE_ALL = 5'h02;
localparam STATE_PRECHARGE_WAIT = 5'h03;
localparam STATE_REFRESH = 5'h04; // Needs state_wait_next_state.
localparam STATE_REFRESH_WAIT = 5'h05;
localparam STATE_INIT_REFRESH_1 = 5'h06;
localparam STATE_INIT_REFRESH_2 = 5'h07;
localparam STATE_LOAD_MODE = 5'h08;
localparam STATE_LOAD_MODE_WAIT = 5'h09;
localparam STATE_ACTIVATE = 5'h0a;
localparam STATE_ACTIVATE_WAIT = 5'h0b;
localparam STATE_WRITE = 5'h0c;
localparam STATE_WRITE_STOP = 5'h0d;
localparam STATE_READ_START = 5'h0e;
localparam STATE_READ_WAIT_1 = 5'h0f;
localparam STATE_READ_WAIT_2 = 5'h10;
localparam STATE_READ_WAIT_3 = 5'h11;
localparam STATE_READY = 5'h1f;
reg [4:0] state;
reg [15:0] state_wait_count;
reg [4:0] state_wait_next_state;
// Put some of the outputs into registers.
localparam CMD_LOAD_MODE = 3'b000;
localparam CMD_AUTO_REFRESH = 3'b001;
localparam CMD_PRECHARGE = 3'b010;
localparam CMD_ACTIVE = 3'b011;
localparam CMD_WRITE = 3'b100;
localparam CMD_READ = 3'b101;
localparam CMD_BURST_TERMINATE = 3'b110;
localparam CMD_NOP = 3'b111;
localparam DQM_ENABLE = 2'b00;
localparam DQM_DISABLE = 2'b11;
reg [15:0] dram_data_reg /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [11:0] dram_addr_reg /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [1:0] dram_dqm_reg /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg dram_cs_n_reg /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [1:0] dram_ba_reg /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg dram_cke_reg /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [2:0] dram_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
// I don't know why this one has to be fast output enable register:
reg dram_oe_reg /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
assign dram_dq = dram_oe_reg ? dram_data_reg : {16{1'bz}};
assign dram_addr = dram_addr_reg;
assign { dram_udqm, dram_ldqm } = dram_dqm_reg;
assign dram_cs_n = dram_cs_n_reg;
assign { dram_ba_1, dram_ba_0 } = dram_ba_reg;
assign dram_cke = dram_cke_reg;
assign { dram_ras_n, dram_cas_n, dram_we_n } = dram_cmd;
// Debugging.
reg [31:0] counter;
reg [15:0] seconds;
// assign debug_number = { 3'b0, state[4:0], state == STATE_READY ? seconds[7:0] : { 3'b0, state_wait_next_state } };
assign debug_number = { 3'b0, state[4:0], seconds[7:0] };
// Initialize our variables.
initial begin
counter <= 0;
seconds <= 0;
state <= STATE_INIT;
state_wait_count <= 1;
state_wait_next_state <= STATE_INIT;
dram_addr_reg <= 12'b0;
dram_dqm_reg <= DQM_DISABLE;
dram_cs_n_reg <= 1;
dram_cke_reg <= 0;
dram_cmd <= CMD_NOP;
dram_oe_reg <= 1'b0;
end
// Show a counter in seconds.
always @(posedge dram_clk or negedge reset_n) begin
if (!reset_n) begin
counter <= 0;
// seconds <= 0;
end else begin
if (counter == 166000000) begin
counter <= 0;
// seconds <= seconds + 1;
end else begin
counter <= counter + 1;
end
end
end
// State machine.
always @(posedge dram_clk or negedge reset_n) begin
if (!reset_n) begin
state <= STATE_INIT;
state_wait_count <= 1;
state_wait_next_state <= STATE_INIT;
dram_addr_reg <= 12'b0;
dram_dqm_reg <= DQM_DISABLE;
dram_cs_n_reg <= 1;
dram_cke_reg <= 0;
dram_oe_reg <= 1'b0;
dram_cmd <= CMD_NOP;
end else begin
case (state)
STATE_INIT: begin
// Wait until the PLL has locked.
if (dram_clk_locked) begin
// Tell the SDRAM to pay attention to the clock.
dram_cs_n_reg <= 0;
dram_cke_reg <= 1;
// The manual says to wait 100us; we wait 200us to be sure.
dram_cmd <= CMD_NOP;
state_wait_count <= 33200; // 200us * 166 MHz.
state_wait_next_state <= STATE_PRECHARGE_ALL;
state <= STATE_WAIT;
end
end
STATE_WAIT: begin
// Wait state_wait_count clocks, then go to state_wait_next_state.
// Never call with state_wait_count == 0.
// We compare against 1 because just the fact that we're
// invoked at all adds one clock.
if (state_wait_count == 1) begin
state <= state_wait_next_state;
end else begin
state_wait_count <= state_wait_count - 16'b1;
end
end
STATE_PRECHARGE_ALL: begin
// Precharge all banks.
dram_cmd <= CMD_PRECHARGE;
dram_addr_reg <= 12'b010000000000; // All banks, ignore dram_ba_reg.
state <= STATE_PRECHARGE_WAIT;
end
STATE_PRECHARGE_WAIT: begin
// Wait after a precharge.
// Must wait tRP = 15ns = 3 clocks. That includes the original
// command, so only 2 clocks of NOP.
dram_cmd <= CMD_NOP;
state_wait_count <= 2;
state_wait_next_state <= STATE_INIT_REFRESH_1;
state <= STATE_WAIT;
end
STATE_REFRESH: begin
// Do an auto refresh cycle. Goes to state_wait_next_state afterward.
dram_cmd <= CMD_AUTO_REFRESH;
state <= STATE_REFRESH_WAIT;
end
STATE_REFRESH_WAIT: begin
// Wait until the refresh is done.
dram_cmd <= CMD_NOP;
state_wait_count <= 10;
// state_wait_next_state is already set.
state <= STATE_WAIT;
end
STATE_INIT_REFRESH_1: begin
// First refresh in the initialization cycle.
state_wait_next_state <= STATE_INIT_REFRESH_2;
state <= STATE_REFRESH;
end
STATE_INIT_REFRESH_2: begin
// Second refresh in the initialization cycle.
state_wait_next_state <= STATE_LOAD_MODE;
state <= STATE_REFRESH;
end
STATE_LOAD_MODE: begin
// Load the mode register.
dram_addr_reg <= {
2'b00, // Reserved.
1'b0, // Burst length applies to read and write (we don't burst).
2'b00, // Standard operation.
3'b011, // CAS = 3.
1'b0, // Sequential.
3'b000 // Burst length = 1 (no bursting).
};
dram_cmd <= CMD_LOAD_MODE;
state <= STATE_LOAD_MODE_WAIT;
end
STATE_LOAD_MODE_WAIT: begin
// Wait after loading the mode register.
dram_cmd <= CMD_NOP;
state_wait_next_state <= STATE_ACTIVATE;
state_wait_count <= 3;
state <= STATE_WAIT;
end
STATE_ACTIVATE: begin
// Activate a row.
dram_cmd <= CMD_ACTIVE;
dram_addr_reg <= 12'b000000000000; // Row.
dram_ba_reg <= 2'd0; // Bank.
state <= STATE_ACTIVATE_WAIT;
end
STATE_ACTIVATE_WAIT: begin
// Wait for activation to finish.
dram_cmd <= CMD_NOP;
state_wait_count <= 3; // tRCD
state_wait_next_state <= STATE_WRITE;
state <= STATE_WAIT;
end
STATE_WRITE: begin
// Write one word.
dram_cmd <= CMD_WRITE;
dram_addr_reg <= 12'b000000000000; // Column.
dram_ba_reg <= 2'd0; // Bank.
dram_dqm_reg <= DQM_ENABLE;
dram_data_reg <= 16'h1234;
dram_oe_reg <= 1'b1;
state <= STATE_WRITE_STOP;
end
STATE_WRITE_STOP: begin
// Stop writing.
dram_cmd <= CMD_NOP;
dram_oe_reg <= 1'b0;
dram_dqm_reg <= DQM_DISABLE;
dram_data_reg <= 16'h5678;
state <= STATE_READ_START;
end
STATE_READ_START: begin
// Initiate the read of a word.
dram_cmd <= CMD_READ;
dram_addr_reg <= 12'b000000000000; // Column.
dram_ba_reg <= 2'd0; // Bank.
state <= STATE_READ_WAIT_1;
end
STATE_READ_WAIT_1: begin
// First clock after read.
// Enable output pins. This is delayed by two clocks, so we
// must do it now.
dram_dqm_reg <= DQM_ENABLE;
state <= STATE_READ_WAIT_2;
end
STATE_READ_WAIT_2: begin
// Second clock after read.
// Disable output pins.
dram_dqm_reg <= DQM_DISABLE;
state <= STATE_READ_WAIT_3;
end
STATE_READ_WAIT_3: begin
// Third clock after read. Data is ready.
seconds <= dram_dq;
state <= STATE_READY;
end
STATE_READY: begin
dram_cmd <= CMD_NOP;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int toInt(string s) { int v; istringstream sin(s); sin >> v; return v; } template <class T> string toString(T x) { ostringstream sout; sout << x; return sout.str(); } vector<string> form(string a, char s) { a += s; vector<string> v; string b; for (int i = (0); i < (int)(a.size()); ++i) { if (a[i] == s) { v.push_back(b); b = ; } else b += a[i]; } return v; } vector<int> formint(string a, char s) { vector<int> v; vector<string> w = form(a, s); for (int i = (0); i < (int)(w.size()); ++i) v.push_back(toInt(w[i])); return v; } const int mod = 1000000007; int aa[2048]; int bb[2048]; int pows(int a, int b) { if (b == 0) return 1; int k = pows(a, b / 2); k = ((long long)k * k) % mod; if (b % 2 == 1) k = ((long long)k * a) % mod; return k; } int divs(int a, int b) { return (((long long)a) * pows(b, mod - 2)) % mod; } int combi(int a, int b) { int res = 1; if (a / 2 < b) b = a - b; for (int i = a, j = 0; j < b; i--, j++) res = (((long long)res) * i) % mod; for (int i = 2; i <= b; i++) res = divs(res, i); return res; } int main(void) { int n, k; cin >> n >> k; for (int i = (0); i < (int)(n); ++i) cin >> aa[i]; if (k == 0) { for (int i = (0); i < (int)(n); ++i) { if (i > 0) cout << ; cout << aa[i]; } cout << endl; return 0; } for (int i = (0); i < (int)(n); ++i) bb[i] = combi(k + i - 1, i); for (int i = (0); i < (int)(n); ++i) { if (i != 0) cout << ; int res = 0; for (int j = (0); j < (int)(i + 1); ++j) { res = (res + ((long long)aa[j] * bb[i - j]) % mod) % mod; } cout << res; } cout << endl; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_alt_lvds_tx (
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
// data interface
tx_clk,
clk,
tx_frame,
tx_data_0,
tx_data_1,
tx_data_2,
tx_data_3,
tx_locked);
// physical interface (transmit)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
// data interface
input tx_clk;
input clk;
input [ 3:0] tx_frame;
input [ 5:0] tx_data_0;
input [ 5:0] tx_data_1;
input [ 5:0] tx_data_2;
input [ 5:0] tx_data_3;
output tx_locked;
// internal registers
reg [27:0] tx_data_n = 'd0;
reg [27:0] tx_data_p = 'd0;
// internal signals
wire core_clk;
wire [27:0] tx_data_s;
// instantiations
assign tx_clk_out_n = 1'd0;
assign tx_frame_out_n = 1'd0;
assign tx_data_out_n = 6'd0;
assign tx_data_s[24] = tx_frame[3];
assign tx_data_s[25] = tx_frame[2];
assign tx_data_s[26] = tx_frame[1];
assign tx_data_s[27] = tx_frame[0];
assign tx_data_s[20] = tx_data_3[5];
assign tx_data_s[16] = tx_data_3[4];
assign tx_data_s[12] = tx_data_3[3];
assign tx_data_s[ 8] = tx_data_3[2];
assign tx_data_s[ 4] = tx_data_3[1];
assign tx_data_s[ 0] = tx_data_3[0];
assign tx_data_s[21] = tx_data_2[5];
assign tx_data_s[17] = tx_data_2[4];
assign tx_data_s[13] = tx_data_2[3];
assign tx_data_s[ 9] = tx_data_2[2];
assign tx_data_s[ 5] = tx_data_2[1];
assign tx_data_s[ 1] = tx_data_2[0];
assign tx_data_s[22] = tx_data_1[5];
assign tx_data_s[18] = tx_data_1[4];
assign tx_data_s[14] = tx_data_1[3];
assign tx_data_s[10] = tx_data_1[2];
assign tx_data_s[ 6] = tx_data_1[1];
assign tx_data_s[ 2] = tx_data_1[0];
assign tx_data_s[23] = tx_data_0[5];
assign tx_data_s[19] = tx_data_0[4];
assign tx_data_s[15] = tx_data_0[3];
assign tx_data_s[11] = tx_data_0[2];
assign tx_data_s[ 7] = tx_data_0[1];
assign tx_data_s[ 3] = tx_data_0[0];
always @(negedge clk) begin
tx_data_n <= tx_data_s;
end
always @(posedge core_clk) begin
tx_data_p <= tx_data_n;
end
altlvds_tx #(
.center_align_msb ("UNUSED"),
.common_rx_tx_pll ("ON"),
.coreclock_divide_by (1),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.differential_drive (0),
.enable_clock_pin_mode ("UNUSED"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.intended_device_family ("Cyclone V"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"),
.lpm_type ("altlvds_tx"),
.multi_clock ("OFF"),
.number_of_channels (7),
.outclock_alignment ("EDGE_ALIGNED"),
.outclock_divide_by (2),
.outclock_duty_cycle (50),
.outclock_multiply_by (1),
.outclock_phase_shift (0),
.outclock_resource ("Regional clock"),
.output_data_rate (500),
.pll_compensation_mode ("AUTO"),
.pll_self_reset_on_loss_lock ("OFF"),
.preemphasis_setting (0),
.refclk_frequency ("250.000000 MHz"),
.registered_input ("TX_CORECLK"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.vod_setting (0),
.clk_src_is_pll ("off"))
i_altlvds_tx (
.tx_inclock (tx_clk),
.tx_coreclock (core_clk),
.tx_in (tx_data_p),
.tx_outclock (tx_clk_out_p),
.tx_out ({tx_frame_out_p, tx_data_out_p}),
.tx_locked (tx_locked),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram16x512.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram16x512 (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [8:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL address[8..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT NODEFVAL byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16x512_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int mm[110][110]; int tmp[110][110]; void draw(int a, int b, int v) { for (int lx = 0; lx < a; lx++) for (int ly = 0; ly < b; ly++) tmp[lx][ly] += v; return; } void prt(int a, int b) { for (int lx = 0; lx < a; lx++) { for (int ly = 0; ly < b; ly++) printf( %c , tmp[lx][ly] ? W : B ); puts( ); } return; } int main() { int n, m; scanf( %d %d , &n, &m); for (int lx = 0; lx < n; lx++) { char buf[200]; scanf( %s , buf); for (int ly = 0; ly < m; ly++) mm[lx][ly] = (buf[ly] == W ); } int cnt = 1; for (int lx = 0; lx < n; lx++) for (int ly = 0; ly < m; ly++) tmp[lx][ly] = mm[n - 1][m - 1]; for (int cc = n + m - 3; cc >= 0; cc--) { for (int x = 0; x <= cc; x++) { int y = cc - x; if (x >= n or y >= m) continue; if (tmp[x][y] != mm[x][y]) { draw(x + 1, y + 1, mm[x][y] - tmp[x][y]), cnt++; } } } printf( %d n , cnt); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> int a[2005]; int n, k; int main() { scanf( %d , &k); k += 2; int len = 0; a[len++] = -1; int res; while (k > 1000000) { k++; a[len++] = 1000000; k -= 1000000; } a[len++] = k; printf( %d n , len); for (int i = 0; i < len; i++) printf( %d , a[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); vector<bool> possible(1010); possible[0] = true; for (int i = 0; i < 1000; ++i) { if (!possible[i]) continue; else { possible[i + 3] = true; possible[i + 5] = true; possible[i + 7] = true; } } int t; cin >> t; for (int tt = 0; tt < t; ++tt) { int n; cin >> n; if (!possible[n]) { cout << -1 n ; continue; } else { vector<int64_t> ans(3); while (n != 0) { if (possible[n - 3]) { n -= 3; ans[0]++; } else if (possible[n - 5]) { n -= 5; ans[1]++; } else { n -= 7; ans[2]++; } } cout << ans[0] << << ans[1] << << ans[2] << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> adj[500005]; vector<pair<long long, long long>> vc[500005]; string s; bool ans[500005], hv[500005]; long long level[500005], sz[500005], heavy[500005], cnt[500005], col[500005]; void dfs(long long u, long long p, long long l = 1) { sz[u] = 1, heavy[u] = -1, level[u] = l; for (long long i = 0; i < adj[u].size(); i++) { long long v = adj[u][i]; if (v == p) continue; dfs(v, u, l + 1); sz[u] += sz[v]; if (heavy[u] == -1 || sz[v] > sz[heavy[u]]) heavy[u] = v; } } void Add(long long u, long long p) { cnt[level[u]] ^= (1 << col[u]); for (long long i = 0; i < adj[u].size(); i++) { long long v = adj[u][i]; if (v == p || hv[v]) continue; Add(v, u); } } void dsu(long long u, long long p, bool flg) { for (long long i = 0; i < adj[u].size(); i++) { long long v = adj[u][i]; if (v == p || v == heavy[u]) continue; dsu(v, u, 0); } if (~heavy[u]) dsu(heavy[u], u, 1), hv[heavy[u]] = 1; Add(u, p); for (auto v : vc[u]) { long long ht = v.first; long long id = v.second; if (__builtin_popcountll(cnt[ht]) <= 1) ans[id] = 1; } if (~heavy[u]) hv[heavy[u]] = 0; if (flg == 0) Add(u, p); } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long i, j, k, p, q, m, n; cin >> n >> m; for (i = 2; i <= n; i++) { cin >> p; adj[p].push_back(i); adj[i].push_back(p); } cin >> s; for (i = 0; i < s.size(); i++) { col[i + 1] = s[i] - a ; } for (i = 1; i <= m; i++) { cin >> p >> q; vc[p].push_back({q, i}); } dfs(1, -1); dsu(1, -1, 0); for (i = 1; i <= m; i++) { if (ans[i]) cout << Yes << n ; else cout << No << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, i, j, kol, tmp, flag[1000]; char s[1000][1000]; int main() { cin >> n >> m; for (i = 1; i <= n; i++) { cin >> s[i]; } for (j = 0; j < m; j++) { tmp = 0; for (i = 1; i <= n - 1; i++) if ((s[i][j] > s[i + 1][j]) && (flag[i] == 0)) tmp = 1; kol += tmp; if (tmp == 0) for (i = 1; i <= n - 1; i++) if ((s[i][j] < s[i + 1][j]) && (flag[i] == 0)) flag[i] = 1; } cout << kol; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int a[N]; int sum[11]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); sum[a[i]]++; } while (1) { int i, aa[11]; memset(aa, 0, sizeof(aa)); for (i = 1; i < 11; ++i) aa[i] = sum[i]; sort(aa, aa + 11); for (i = 0; i < 11; ++i) if (aa[i]) break; if (aa[10] - aa[i] > 1) { if (aa[i] == 1) { if (aa[i + 1] == aa[10]) { cout << n; break; } } } else if (aa[i] == aa[10]) { if (aa[i] == 1 || i == 10) { cout << n; break; } } else { if (aa[i] == 1) { if (aa[i + 1] == aa[10]) { cout << n; break; } } if (aa[i] == aa[9]) { cout << n; break; } } sum[a[n]]--; n--; } return 0; } |
#include <bits/stdc++.h> using namespace std; set<long long> num; void f(int x, int a, int b, long long now) { if (x == 0) { num.insert(now); return; } if (a) f(x - 1, a - 1, b, now * 10 + 4); if (b) f(x - 1, a, b - 1, now * 10 + 7); } void init() { int i; for (i = 1; i <= 5; i++) f(i * 2, i, i, 0LL); } int main() { long long n; init(); scanf( %I64d , &n); printf( %I64d , *num.upper_bound(n - 1)); } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string s; cin >> s; int ans = n; for (int i = 0; i < n / 2; i++) { string temp1 = s.substr(0, i + 1); string temp2 = s.substr(i + 1, i + 1); if (temp1 == temp2) ans = min(ans, n - i); } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; t = 1; while (t--) { solve(); } return 0; } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_SHARED_CODE
integer i = 0;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (start_event == 1'b1) begin
i <= num_cks;
end
else if (i > 1) begin
i <= i - 1;
end
end
else begin
i <= 0;
end
end
`endif // OVL_SHARED_CODE
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_next_assert #(
.num_cks(num_cks),
.check_overlapping(check_overlapping),
.check_missing_start(check_missing_start))
assert_next_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.no_overlapping(i <= 0),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_next_assume #(
.num_cks(num_cks),
.check_overlapping(check_overlapping),
.check_missing_start(check_missing_start))
assert_next_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.no_overlapping(i <= 0),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_next_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_next_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.no_overlapping(i <= 0));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_next.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_next_assert (clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable);
parameter num_cks = 1;
parameter check_overlapping = 1;
parameter check_missing_start = 1;
input clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_next_assume (clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable);
parameter num_cks = 1;
parameter check_overlapping = 1;
parameter check_missing_start = 1;
input clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_next_cover (clk, reset_n, test_expr, start_event, no_overlapping);
parameter OVL_COVER_BASIC_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n, test_expr, start_event, no_overlapping;
endmodule
|
// Quartus Prime Verilog Template
// Single port RAM with single read/write address and initial contents
// specified with an initial block
module phyIniCommand0_and
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
// Specify the initial contents. You can also use the $readmemb
// system task to initialize the RAM variable from a text file.
// See the $readmemb template page for details.
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps_Slave/ram_init0_and.txt", ram);
end
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
endmodule
|
//MODULE REFERENCE
`define tenv_clock tenv_clock
`define tenv_descstd_device tenv_descstd_device
`define tenv_usbhost tenv_usbhost
`define tenv_usbdev tenv_usbdev
module tenv_test;
//IFACE
reg start=0;
//LOCAL
localparam block_name="tenv_test";
integer seed;
integer i;
//TASKS
`include "tenv_test/tenv_test.tcase_powered.v"
`include "tenv_test/tenv_test.tcase_default.v"
`include "tenv_test/tenv_test.tcase_addressed.v"
`include "tenv_test/tenv_test.tcase_configured.v"
`include "tenv_test/tenv_test.tcase_suspended.v"
`include "tenv_test/tenv_test.tcase_trfer_bulkint.v"
`include "tenv_test/tenv_test.tcase_trfer_isoch.v"
`include "tenv_test/tenv_test.tcase_trfer_control.v"
`include "tenv_test/tenv_test.tcase_bitstream.v"
`include "tenv_test/tenv_test.tcase_reply_delay.v"
`include "tenv_test/tenv_test.trsac.v"
`include "tenv_test/tenv_test.check_data.v"
`include "tenv_test/tenv_test.check_descdev.v"
initial forever
begin
wait(start==1);
$timeformat(-9, 0, " ns", 10);
#100;
$write("%0t [%0s]: ",$realtime,block_name);
$write("--- Functional verification of \"usb_devtrsac\" ---\n");
fork
begin:TEST_SEQUENCE
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$write("FULL SPEED FUNCTION");
$write("\n");
//LAUNCH CLOCKS
`tenv_clock.x4_timehigh=10;
`tenv_clock.x4_timelow=11;
`tenv_clock.x4_en=1;
@(posedge `tenv_clock.x4);
//INIT
`tenv_usbdev.speed=1;//SELECT FULL SPEED
`tenv_usbdev.ep_enable=15'h7FFF;//ENABLE ALL EP
`tenv_usbdev.ep_isoch=15'd000_0000_0000_0000;
`tenv_usbdev.ep_intnoretry=15'b000_0000_0000_0000;
`tenv_usbhost.speed=`tenv_usbdev.speed;
`tenv_usbhost.bit_time=`tenv_clock.x4_period*4;
//TESTCASES
tcase_powered;
tcase_default;
tcase_addressed;
tcase_configured;
tcase_suspended;
tcase_trfer_bulkint;
tcase_trfer_isoch;
tcase_trfer_control;
tcase_bitstream;
tcase_reply_delay;
//STOP CLOCKS
@(negedge `tenv_clock.x4);
`tenv_clock.x4_en=0;
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$write("LOW SPEED FUNCTION");
$write("\n");
//LAUNCH CLOCKS
`tenv_clock.x4_timehigh=83;
`tenv_clock.x4_timelow=84;
`tenv_clock.x4_en=1;
@(posedge `tenv_clock.x4);
//INIT
`tenv_usbdev.speed=0;//SELECT LOW SPEED
`tenv_usbdev.ep_enable=15'h7FFF;//ENABLE ALL EP
`tenv_usbdev.ep_isoch=15'd000_0000_0000_0000;
`tenv_usbdev.ep_intnoretry=15'b000_0000_0000_0000;
`tenv_usbhost.speed=`tenv_usbdev.speed;
`tenv_usbhost.bit_time=`tenv_clock.x4_period*4;
//TESTCASES
tcase_powered;
tcase_default;
tcase_addressed;
tcase_configured;
tcase_suspended;
tcase_trfer_bulkint;
tcase_trfer_control;
tcase_bitstream;
tcase_reply_delay;
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$write("--- Functional verification of \"usb_devtrsac\" ");
$write("is successfull ---\n");
disable TIMEBOMB;
end//TEST_SEQUENCE
begin:TIMEBOMB
repeat(300) #(1000*1000);//100 ms
$write ("\n");
$write ("%0t [%0s]: ",$realtime,block_name);
$display("Error - test time is run out.");
disable TEST_SEQUENCE;
end//TIMEBOMB
join
start=0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPADV2_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPADV2_BLACKBOX_V
/**
* top_power_hvc_wpadv2: A power pad with an ESD high-voltage clamp.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpadv2 (
P_PAD ,
AMUXBUS_A,
AMUXBUS_B
);
inout P_PAD ;
inout AMUXBUS_A;
inout AMUXBUS_B;
// Voltage supply signals
supply1 OGC_HVC ;
supply1 DRN_HVC ;
supply0 SRC_BDY_HVC;
supply1 P_CORE ;
supply1 VDDIO ;
supply1 VDDIO_Q ;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH ;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q ;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPADV2_BLACKBOX_V
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 05:33:22 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_pointer_basic_0_1 -prefix
// design_1_pointer_basic_0_1_ design_1_pointer_basic_0_1_stub.v
// Design : design_1_pointer_basic_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "pointer_basic,Vivado 2018.2" *)
module design_1_pointer_basic_0_1(s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_AWVALID, s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_WDATA, s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_WVALID, s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_BRESP, s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY, s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_ARVALID, s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_RDATA, s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_RVALID, s_axi_pointer_basic_io_RREADY, ap_clk, ap_rst_n,
interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_pointer_basic_io_AWADDR[4:0],s_axi_pointer_basic_io_AWVALID,s_axi_pointer_basic_io_AWREADY,s_axi_pointer_basic_io_WDATA[31:0],s_axi_pointer_basic_io_WSTRB[3:0],s_axi_pointer_basic_io_WVALID,s_axi_pointer_basic_io_WREADY,s_axi_pointer_basic_io_BRESP[1:0],s_axi_pointer_basic_io_BVALID,s_axi_pointer_basic_io_BREADY,s_axi_pointer_basic_io_ARADDR[4:0],s_axi_pointer_basic_io_ARVALID,s_axi_pointer_basic_io_ARREADY,s_axi_pointer_basic_io_RDATA[31:0],s_axi_pointer_basic_io_RRESP[1:0],s_axi_pointer_basic_io_RVALID,s_axi_pointer_basic_io_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [4:0]s_axi_pointer_basic_io_AWADDR;
input s_axi_pointer_basic_io_AWVALID;
output s_axi_pointer_basic_io_AWREADY;
input [31:0]s_axi_pointer_basic_io_WDATA;
input [3:0]s_axi_pointer_basic_io_WSTRB;
input s_axi_pointer_basic_io_WVALID;
output s_axi_pointer_basic_io_WREADY;
output [1:0]s_axi_pointer_basic_io_BRESP;
output s_axi_pointer_basic_io_BVALID;
input s_axi_pointer_basic_io_BREADY;
input [4:0]s_axi_pointer_basic_io_ARADDR;
input s_axi_pointer_basic_io_ARVALID;
output s_axi_pointer_basic_io_ARREADY;
output [31:0]s_axi_pointer_basic_io_RDATA;
output [1:0]s_axi_pointer_basic_io_RRESP;
output s_axi_pointer_basic_io_RVALID;
input s_axi_pointer_basic_io_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 70 + 10; int n, dist[MAXN * MAXN * MAXN], u[3]; char arr[MAXN][MAXN]; int a[MAXN * MAXN * MAXN], b[MAXN * MAXN * MAXN]; struct node { int v[3] = {-1, -1, -1}; int A = -1, B = -1; node(int v1 = -1, int v2 = -1, int v3 = -1, int A_ = -1, int B_ = -1) { v[0] = v1; v[1] = v2; v[2] = v3; A = A_; B = B_; sort(this->v, this->v + 3); } int number() { return v[0] + n * v[1] + n * n * v[2]; } vector<node> adj() { vector<node> adj_; for (int j = 0; j < n; j++) { if (j == v[0] || j == v[1] || j == v[2]) continue; if (arr[v[1]][v[2]] == arr[v[0]][j]) adj_.push_back(node(v[1], v[2], j, v[0], j)); if (arr[v[0]][v[2]] == arr[v[1]][j]) adj_.push_back(node(v[0], v[2], j, v[1], j)); if (arr[v[1]][v[0]] == arr[v[2]][j]) adj_.push_back(node(v[1], v[0], j, v[2], j)); } return adj_; } } Q[MAXN * MAXN * MAXN], par[MAXN * MAXN * MAXN]; int main() { ios::sync_with_stdio(0); cin >> n; cin >> u[0] >> u[1] >> u[2]; u[0]--; u[1]--; u[2]--; memset(dist, 63, sizeof(dist)); dist[node(u[0], u[1], u[2]).number()] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> arr[i][j]; } } int L = 0, R = 0; Q[R++] = node(u[0], u[1], u[2]); while (L < R) { node tp = Q[L++]; for (auto i : tp.adj()) if (dist[i.number()] == dist[MAXN * MAXN * MAXN - 1]) { dist[i.number()] = dist[tp.number()] + 1; Q[R++] = i; par[i.number()] = tp; a[i.number()] = i.A; b[i.number()] = i.B; } } if (dist[node(0, 1, 2).number()] != dist[MAXN * MAXN * MAXN - 1]) { cout << dist[node(0, 1, 2).number()] << n ; vector<pair<int, int>> answer; node me = node(0, 1, 2); for (int i = 0; i < dist[node(0, 1, 2).number()]; i++) { answer.push_back(pair<int, int>(a[me.number()], b[me.number()])); me = par[me.number()]; } reverse(answer.begin(), answer.end()); for (auto i : answer) cout << i.first + 1 << << i.second + 1 << n ; } else cout << -1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long f[55][2][2], K, d; int a[55], n; long long C(int l, int r, int x, int y) { if (l > r) return 1; long long& F = f[l][x][y]; if (~F) return F; F = 0; for (int i = 0; i <= 1; ++i) for (int j = 0; j <= 1; ++j) if (a[l] - !i && a[r] - !j && (l < r || i == j) && (x || i <= j) && (y || i <= (!j))) F += C(l + 1, r - 1, x || (i < j), y || (i < !j)); return F; } int main() { cin >> n >> K; memset(a, -1, sizeof a); memset(f, -1, sizeof f); if (C(1, n, a[1] = 0, 0) < ++K) return cout << -1, 0; for (int i = 2; i <= n; ++i) { memset(f, -1, sizeof f); d = C(1, n, a[i] = 0, 0); K -= (a[i] = (d < K)) * d; } for (int i = 1; i <= n; ++i) cout << a[i]; } |
//reads ram and displays on vga monitor
module vga_sram(CLOCK_PX ,rst,VGA_R, VGA_G, VGA_B,VGA_HS, VGA_VS,VGA_SYNC, VGA_BLANK,FB_ADDR,fb_data,we_nIN);
input CLOCK_PX,rst;
//reg [7:0]fb_data_reg;
input we_nIN;
input [7:0] fb_data;
output VGA_BLANK, VGA_SYNC, VGA_HS, VGA_VS;
output [7:0] VGA_R, VGA_G, VGA_B;
output [18:0] FB_ADDR;
reg [7:0] VGA_R, VGA_G, VGA_B;
reg VGA_HS, VGA_VS, h_blank, v_blank, status;
reg [31:0] pixelcount, linecount;
reg red_value;
reg [9:0] rdaddress;
reg [9:0] wraddress;
reg [18:0] FB_ADDR;
reg [7:0] Rdata, Bdata;
reg UBwe, LBwe;
wire CLOCK_PX,we_nIN;
wire VGA_BLANK, VGA_SYNC;
wire [7:0] Rq,Bq, gray;
// VGA parameters 640 x 480
// horizontal
//parameter H_FRONT = 16;
//parameter H_SYNC = 96;
//parameter H_BACK = 48;
//parameter H_ACT = 640;
//parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
//parameter H_TOTAL = H_FRONT + H_SYNC + H_BACK + H_ACT;
//
//// vertical
//parameter V_FRONT = 10;
//parameter V_SYNC = 2;
//parameter V_BACK = 33;
//parameter V_ACT = 480;
//parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
//parameter V_TOTAL = V_FRONT + V_SYNC + V_BACK + V_ACT;
// Horizontal Parameter
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
// VGA parameters 1280 x 1024
// horizontal
//parameter H_FRONT = 48;
//parameter H_SYNC = 112;
//parameter H_BACK = 248;
//parameter H_ACT = 1280;
//parameter H_BLANK = H_FRONT + H_SYNC + H_BACK;
//parameter H_TOTAL = H_FRONT + H_SYNC + H_BACK + H_ACT;
//
//// vertical
//parameter V_FRONT = 1;
//parameter V_SYNC = 3;
//parameter V_BACK = 38;
//parameter V_ACT = 1024;
//parameter V_BLANK = V_FRONT + V_SYNC + V_BACK;
//parameter V_TOTAL = V_FRONT + V_SYNC + V_BACK + V_ACT;
parameter FB_SIZE = V_ACT * H_ACT;
`define fb_addr_size 19
// parameters to force a square image
parameter SH_ACT = 0;//V_ACT; // make the horizontal resolution the same as the vertical resolution
parameter S_FILLER = 0;//SH_ACT/2;
//vga pin assigns
assign VGA_SYNC = 1'b1,//VGA_HS || VGA_VS,
VGA_BLANK = h_blank || v_blank;
//sram pin assigns
//assign ce_n=1'b0,//the chip is always selected
// oe_n=1'b0,//dont car in write state, 0 in read state
// ub_n=1'b0,//the upper byte [15:8] will be read/writed each read/write command
// lb_n=1'b0;//the lower byte [7:0] will be read/writed each read/write command
//rgb2gray r2g( Rdata, 8'd0, Bdata,gray);
//linebuffer ram rdclock wrclock
//linebuffer red(gray,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,LBwe,Rq);
//linebuffer blue(gray,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,UBwe,Bq);
linebuffer red(Rdata,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,LBwe,Rq);// only need one channel for grayscale
//linebuffer blue(Bdata,rdaddress,CLOCK_PX,wraddress,CLOCK_PX,UBwe,Bq);
// pixel counter and line counter
always@(posedge CLOCK_PX or negedge rst)
begin
if (rst==1'b0)
begin
pixelcount<=32'd0;
linecount<=32'd0;
end
else
if(we_nIN==1'b1)
if (pixelcount>H_TOTAL)
begin
pixelcount<=32'd0;
if (linecount>V_TOTAL)
linecount<=32'd0;
else
linecount<= linecount+1;
end
else
pixelcount<= pixelcount+1;
else
begin
pixelcount<=32'd0;
linecount<=32'd0;
end
end
//horizontal outputs
always@(posedge CLOCK_PX or negedge rst)
begin
if (rst == 1'b0)
begin
VGA_HS<=1'b0;
h_blank<=1'b1;
VGA_R<=8'h00;
VGA_G<=8'h00;
VGA_B<=8'h00;
rdaddress<=10'b0000000100;
end
else
begin
//HSYNC
if (pixelcount< H_SYNC)
VGA_HS<=1'b0;
else
VGA_HS<=1'b1;
//Back porch and Front porch
// if ((pixelcount>=H_SYNC && pixelcount<(H_SYNC+H_BACK))|| (pixelcount>=(H_SYNC+H_BACK+H_ACT)))
if (pixelcount < H_BLANK)
h_blank<=1'b0;
else
h_blank<=1'b1;
// horizontal visible area
//if (pixelcount>(H_SYNC+H_BACK) && pixelcount<H_SYNC+H_BACK+H_ACT)
//change to make a square 1024x1024 //<=
if (linecount>=(V_BACK+V_SYNC) &&
linecount<(V_BACK+V_SYNC+V_ACT) &&
pixelcount>=(H_BACK+H_SYNC/*+S_FILLER*/) &&
pixelcount<(H_BACK+H_SYNC+H_ACT/*-S_FILLER*/) &&
we_nIN==1'b1)
begin
//read linebuffer
//VGA_R<=8'h00;
VGA_R<=Rq;//Rq and Bq should be equal and grayscale
VGA_G<=Rq;
VGA_B<=Rq;//Bq;
//incriment LB addr
rdaddress<=rdaddress+10'd1;
end
else
begin
//dont read frame buffer
//included to remove infered latch
VGA_R<=8'h00;
VGA_G<=8'h00;
VGA_B<=8'h00;
// rdaddress<=rdaddress;
rdaddress <= 10'd0;
end
end// end else rst
end//always
// vertical outputs
always@(posedge CLOCK_PX or negedge rst)
begin
if (rst ==1'b0)
begin
VGA_VS<=1'b0;
v_blank <= 1'b0;
end
else
begin
//vsync
if (linecount<V_SYNC)
VGA_VS<=1'b0;
else
VGA_VS <= 1'b1;
// Back porch or front porch
//if ((linecount >=V_SYNC && linecount<(V_BACK+V_SYNC))|| linecount>=(V_BACK+V_SYNC+V_ACT))
if (linecount < V_BLANK )
v_blank<=1'b1;
else
v_blank <= 1'b0;
//vertical visible area
// nothing else needs to be done
//linecount >= 32'd29 && linecount< 32'd629
end// end rst else
end
//fill line buffer
always@(posedge CLOCK_PX or negedge rst)
begin
if(rst==1'b0)
begin
wraddress<=10'd0;
FB_ADDR<=`fb_addr_size'd0;
end
else
// fill line buffer in the first 1024 pixels of row (only on visible rows) \/ is this right?
// commented out part that makes screen square
if(linecount>=(V_SYNC+V_BACK)&&linecount<(V_SYNC+V_BACK+V_ACT)&&pixelcount<H_ACT&&we_nIN==1'b1)
begin
Rdata<=fb_data;
//Bdata<=fb_data;// only need one channel for grayscale
//incriment on-chip ram address
wraddress<=wraddress+10'd1;
//incriment sram address
if(FB_ADDR >= FB_SIZE) begin
FB_ADDR <= `fb_addr_size'd0;// FB_ADDR might be less than 20 bits
end else begin
FB_ADDR<=FB_ADDR+`fb_addr_size'd1;
end
//enable writing to on chip rams
UBwe<=1'b1;
LBwe<=1'b1;
end
else
begin
//disable writing to on chip rams
UBwe<=1'b0;
LBwe<=1'b0;
wraddress <= 10'd0;
end
end//always
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, ans; int a[105]; while (cin >> n >> m >> k) { ans = 1000000; for (int i = 0; i < n; i++) { cin >> a[i]; } m--; for (int i = 1; m - i >= 0; i++) { if (a[m - i] <= k && a[m - i]) { ans = min(ans, i * 10); break; } } for (int i = 1; m + i < n; i++) { if (a[m + i] && k >= a[m + i]) { ans = min(ans, i * 10); break; } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x; string s1, s2; int cnt = 0; cin >> x >> ws; for (int i = x; i; i--) { cin >> s1; cin >> s2; if (s2.compare( soft ) == 0) cnt++; } if (x - cnt > cnt) cnt = x - cnt; for (int i = 0; i < 100; ++i) { if (i * i / 2 + i % 2 >= cnt && i * i >= x) { cout << i << endl; return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; char s[200010]; int n, m, head[200010], o = 0, x[2], id[200010], sz[200010], cnt = 0, tree[800010], tag[800010]; bool isnt_rt[200010]; vector<vector<int> > w; struct edge { int to, link; } e[200010]; struct seg { int x, l, r, id; bool operator<(const seg &b) const { return x < b.x; } } sg[200010]; void add_edge(int u, int v) { e[++o].to = v, e[o].link = head[u], head[u] = o, isnt_rt[v] = true; } void dfs(int u, int k) { id[u] = ++x[k], sz[u] = 1; for (int i = head[u]; i; i = e[i].link) { dfs(e[i].to, k); sz[u] += sz[e[i].to]; } } void pushup(int l, int r, int t) { if (tag[t] > 0) return tree[t] = (r - l + 1), void(); if (l == r) return tree[t] = 0, void(); tree[t] = tree[t << 1] + tree[t << 1 | 1]; } void add(int ll, int rr, int l, int r, int t, int c) { if (ll <= l && r <= rr) { tag[t] += c; pushup(l, r, t); return; } int mid = (l + r) >> 1; if (ll <= mid) add(ll, rr, l, mid, t << 1, c); if (mid < rr) add(ll, rr, mid + 1, r, t << 1 | 1, c); pushup(l, r, t); } int main() { scanf( %d%d , &n, &m), w.resize(n + 1); for (int i = 1; i <= n; i++) { w[i].resize(m + 1); scanf( %s , s + 1); for (int j = 1; j <= m; j++) { if (s[j] == L ) w[i][j] = 1; if (s[j] == U ) w[i][j] = 2; if (s[j] == L && j + 2 <= m) add_edge(((i)-1) * m + (j + 2), ((i)-1) * m + (j)); if (s[j] == R && j - 2 >= 1) add_edge(((i)-1) * m + (j - 2), ((i)-1) * m + (j)); if (s[j] == U && i + 2 <= n) add_edge(((i + 2) - 1) * m + (j), ((i)-1) * m + (j)); if (s[j] == D && i - 2 >= 1) add_edge(((i - 2) - 1) * m + (j), ((i)-1) * m + (j)); } } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (isnt_rt[((i)-1) * m + (j)]) continue; dfs(((i)-1) * m + (j), (i + j) & 1); } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { int u, v; if (w[i][j] == 1) { u = ((i)-1) * m + (j), v = ((i)-1) * m + (j + 1); if ((i + j) & 1) swap(u, v); } else if (w[i][j] == 2) { u = ((i)-1) * m + (j), v = ((i + 1) - 1) * m + (j); if ((i + j) & 1) swap(u, v); } else continue; sg[++cnt] = (seg){id[u], id[v], id[v] + sz[v] - 1, 1}; sg[++cnt] = (seg){id[u] + sz[u], id[v], id[v] + sz[v] - 1, -1}; } sort(sg + 1, sg + cnt + 1); long long ans = 0; for (int i = 1, j = 1; i <= x[0]; i++) { while (sg[j].x <= i && j <= cnt) { add(sg[j].l, sg[j].r, 1, x[1], 1, sg[j].id); j++; } ans += tree[1]; } printf( %lld n , ans); } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Wed May 7 21:01:31 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/multi_fft/multi_fft_stub.v
// Design : multi_fft
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0,Vivado 2014.1" *)
module multi_fft(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[28:0],B[28:0],P[57:0]" */;
input CLK;
input [28:0]A;
input [28:0]B;
output [57:0]P;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : if_post_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: if_post_fifo.v,v 1.4 2011/05/23 06:13:05 ssaifee Exp $
**$Date: 2011/05/23 06:13:05 $
**$Author: ssaifee $
**$Revision: 1.4 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_2/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/if_post_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v1_8_ddr_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input [3:0] empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output byte_rd_en,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
(* keep = "true", equivalent_register_removal = "no", max_fanout = 3 *) reg [3:0] my_empty /* synthesis syn_maxfan = 3 */;
// synthesis attribute MAX_FANOUT of my_empty is 3;
reg my_full;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr;
// synthesis attribute MAX_FANOUT of rd_ptr is 10;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr;
// synthesis attribute MAX_FANOUT of wr_ptr is 10;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty[1], my_full})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 4'b0000;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_full <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty, my_full);
rd_ptr <= #TCQ 2'bxx;
wr_ptr <= #TCQ 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
wire [WIDTH-1:0] mem_out;
assign d_out = my_empty[2] ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in[0] & my_empty[0];
assign byte_rd_en = !empty_in[3] || !my_empty[3];
always @(posedge clk)
if (rst) begin
my_empty <= #TCQ 4'b1111;
my_full <= #TCQ 1'b0;
rd_ptr <= #TCQ 'b0;
wr_ptr <= #TCQ 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty[1] && !my_full && rd_en_in && !empty_in[1]) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, !empty_in[1]);
end
wire wr_en;
assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full) |
(rd_en_in & !my_empty[2])));
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem [rd_ptr];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int M = 1e9 + 7; long long a[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long a, b, x, y, z; cin >> a >> b >> x >> y >> z; cout << max(0ll, y - (a - 2 * x)) + max(0ll, y - (b - 3 * z)); } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_64_TX_ENGINE.v
// Version : 1.7
//-- Description: 64 bit Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`define PIO_64_CPLD_FMT_TYPE 7'b10_01010
`define PIO_64_TX_RST_STATE 1'b0
`define PIO_64_TX_CPLD_QW1 1'b1
module PIO_64_TX_ENGINE (
clk,
rst_n,
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_tdst_rdy_n,
trn_tdst_dsc_n,
req_compl_i,
compl_done_o,
req_tc_i,
req_td_i,
req_ep_i,
req_attr_i,
req_len_i,
req_rid_i,
req_tag_i,
req_be_i,
req_addr_i,
// Read Access
rd_addr_o,
rd_be_o,
rd_data_i,
completer_id_i,
cfg_bus_mstr_enable_i
);
input clk;
input rst_n;
output [63:0] trn_td;
output [7:0] trn_trem_n;
output trn_tsof_n;
output trn_teof_n;
output trn_tsrc_rdy_n;
output trn_tsrc_dsc_n;
input trn_tdst_rdy_n;
input trn_tdst_dsc_n;
input req_compl_i;
output compl_done_o;
input [2:0] req_tc_i;
input req_td_i;
input req_ep_i;
input [1:0] req_attr_i;
input [9:0] req_len_i;
input [15:0] req_rid_i;
input [7:0] req_tag_i;
input [7:0] req_be_i;
input [12:0] req_addr_i;
output [10:0] rd_addr_o;
output [3:0] rd_be_o;
input [31:0] rd_data_i;
input [15:0] completer_id_i;
input cfg_bus_mstr_enable_i;
// Local registers
reg [63:0] trn_td;
reg [7:0] trn_trem_n;
reg trn_tsof_n;
reg trn_teof_n;
reg trn_tsrc_rdy_n;
reg trn_tsrc_dsc_n /*synthesis syn_keep = 1*/;
reg [11:0] byte_count;
reg [06:0] lower_addr;
reg compl_done_o;
reg req_compl_q;
reg [0:0] state;
// Local wires
/*
* Present address and byte enable to memory module
*/
assign rd_addr_o = req_addr_i[12:2];
assign rd_be_o = req_be_i[3:0];
/*
* Calculate byte count based on byte enable
*/
always @ (rd_be_o) begin
casex (rd_be_o[3:0])
4'b1xx1 : byte_count = 12'h004;
4'b01x1 : byte_count = 12'h003;
4'b1x10 : byte_count = 12'h003;
4'b0011 : byte_count = 12'h002;
4'b0110 : byte_count = 12'h002;
4'b1100 : byte_count = 12'h002;
4'b0001 : byte_count = 12'h001;
4'b0010 : byte_count = 12'h001;
4'b0100 : byte_count = 12'h001;
4'b1000 : byte_count = 12'h001;
4'b0000 : byte_count = 12'h001;
endcase
end
/*
* Calculate lower address based on byte enable
*/
always @ (rd_be_o or req_addr_i) begin
casex (rd_be_o[3:0])
4'b0000 : lower_addr = {req_addr_i[6:2], 2'b00};
4'bxxx1 : lower_addr = {req_addr_i[6:2], 2'b00};
4'bxx10 : lower_addr = {req_addr_i[6:2], 2'b01};
4'bx100 : lower_addr = {req_addr_i[6:2], 2'b10};
4'b1000 : lower_addr = {req_addr_i[6:2], 2'b11};
endcase
end
always @ ( posedge clk ) begin
if (!rst_n ) begin
req_compl_q <= 1'b0;
end else begin
req_compl_q <= req_compl_i;
end
end
/*
* Generate Completion with 1 DW Payload
*/
always @ ( posedge clk ) begin
if (!rst_n ) begin
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n <= 1'b1;
trn_tsrc_dsc_n <= 1'b1;
trn_td <= 64'b0;
trn_trem_n <= 8'b0;
compl_done_o <= 1'b0;
state <= `PIO_64_TX_RST_STATE;
end else begin
case ( state )
`PIO_64_TX_RST_STATE : begin
if (req_compl_q && trn_tdst_dsc_n) begin
trn_tsof_n <= 1'b0;
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n <= 1'b0;
trn_td <= { {1'b0},
`PIO_64_CPLD_FMT_TYPE,
{1'b0},
req_tc_i,
{4'b0},
req_td_i,
req_ep_i,
req_attr_i,
{2'b0},
req_len_i,
completer_id_i,
{3'b0},
{1'b0},
byte_count };
trn_trem_n <= 8'b0;
state <= `PIO_64_TX_CPLD_QW1;
end else begin
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n <= 1'b1;
trn_tsrc_dsc_n <= 1'b1;
trn_td <= 64'b0;
trn_trem_n <= 8'b0;
compl_done_o <= 1'b0;
state <= `PIO_64_TX_RST_STATE;
end
end
`PIO_64_TX_CPLD_QW1 : begin
if ((!trn_tdst_rdy_n) && (trn_tdst_dsc_n)) begin
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b0;
trn_tsrc_rdy_n <= 1'b0;
trn_td <= { req_rid_i,
req_tag_i,
{1'b0},
lower_addr,
rd_data_i };
trn_trem_n <= 8'h00;
compl_done_o <= 1'b1;
state <= `PIO_64_TX_RST_STATE;
end else if (!trn_tdst_dsc_n) begin
state <= `PIO_64_TX_RST_STATE;
trn_tsrc_dsc_n <= 1'b0;
end else
state <= `PIO_64_TX_CPLD_QW1;
end
endcase
end
end
endmodule // PIO_64_TX_ENGINE
|
#include <bits/stdc++.h> using namespace std; vector<int> ans; int n, r, fr[101][101]; int main() { cin >> n; for (int i = 0; i < n; i++) { scanf( %d , &r); for (int x, j = 0; j < r; j++) { scanf( %d , &x); fr[i][x]++; } } for (int i = 1; i <= 100; i++) { int c = 0; for (int j = 0; j <= 100; j++) { c += fr[j][i]; } if (c == n) { ans.push_back(i); } } for (int i = 0; i < ans.size(); i++) { printf( %d , ans[i]); if (i != ans.size() - 1) putchar( ); } } |
#include <bits/stdc++.h> using namespace std; int n, m, x, y, u, v, a[1010], b[1010][1010]; vector<int> vv; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %d%d , &x, &y); a[y]++; b[x][y]++; } for (int i = 0; i < m; ++i) { scanf( %d%d , &x, &y); if (a[y] && b[x][y]) { ++u; --a[y]; ++v; --b[x][y]; } else vv.push_back(y); } for (int i = 0; i < (int)vv.size(); ++i) if (a[vv[i]]) ++u, --a[vv[i]]; printf( %d %d , u, v); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / D Flip-Flop with Clock Enable and Synchronous Set
// /___/ /\ Filename : FDSE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 12/08/11 - add MSGON and XON attributes (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDSE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_S_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input D,
input S
);
reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED;
reg [0:0] IS_S_INVERTED_REG = IS_S_INVERTED;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
wire D_dly, C_dly, CE_dly;
wire S_dly;
`endif
// begin behavioral model
reg Q_out;
assign #100 Q = Q_out;
// end behavioral model
always @(glblGSR)
if (glblGSR)
assign Q_out = INIT;
else
deassign Q_out;
`ifdef XIL_TIMING
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C_dly)
if (((S_dly ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C_dly)
if (((S_dly ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end
endgenerate
`else
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C)
if (((S ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C)
if (((S ^ IS_S_INVERTED_REG) && (S !== 1'bz)) || (S === 1'bx && Q_out == 1'b1))
Q_out <= 1'b1;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end
endgenerate
`endif
`ifdef XIL_TIMING
reg notifier;
wire notifier1;
`endif
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nset;
wire in_clk_enable, in_clk_enable_p, in_clk_enable_n;
wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n;
reg init_enable = 1'b1;
wire set_clk_enable, set_clk_enable_p, set_clk_enable_n;
`endif
`ifdef XIL_TIMING
not (ngsr, glblGSR);
xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out);
not (nset, (S_dly ^ IS_S_INVERTED_REG) && (S !== 1'bz));
and (in_clk_enable, ngsr, nset, CE || (CE === 1'bz));
and (ce_clk_enable, ngsr, nset, in_out);
and (set_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG);
always @(negedge nset) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1);
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1);
assign set_clk_enable_n = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b1);
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0);
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0);
assign set_clk_enable_p = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b0);
`endif
`ifdef XIL_TIMING
specify
(C => Q) = (100:100:100, 100:100:100);
$period (negedge C &&& CE, 0:0:0, notifier);
$period (posedge C &&& CE, 0:0:0, notifier);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (negedge C, negedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,C_dly,S_dly);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (negedge C, posedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,C_dly,S_dly);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$setuphold (posedge C, negedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,C_dly,S_dly);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$setuphold (posedge C, posedge S, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,C_dly,S_dly);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge S &&& init_enable, 0:0:0, 0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge S &&& init_enable, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_fifo
*/
module test_axis_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_fifo.lxt");
$dumpvars(0, test_axis_fifo);
end
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:43:18 02/23/2016
// Design Name: DebugUnit
// Module Name: C:/Users/Juanjo/Documents/Juanjo/Facu/Arquitectura/Trabajo Final/finalArquitectura/TestDatapathPart1/PipeAndDebug/debugUnit_test.v
// Project Name: PipeAndDebug
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DebugUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module debugUnit_test;
// Inputs
reg clock;
reg reset;
reg endOfProgram;
reg [7:0] uartFifoDataIn;
reg uartDataAvailable;
reg [7:0] FE_pc;
reg [31:0] IF_ID_instruction;
reg [7:0] IF_ID_pcNext;
reg [3:0] ID_EX_aluOperation;
reg [31:0] ID_EX_sigExt;
reg [31:0] ID_EX_readData1;
reg [31:0] ID_EX_readData2;
reg ID_EX_aluSrc;
reg ID_EX_aluShiftImm;
reg [3:0] ID_EX_memWrite;
reg ID_EX_memToReg;
reg [1:0] ID_EX_memReadWidth;
reg [4:0] ID_EX_rs;
reg [4:0] ID_EX_rt;
reg [4:0] ID_EX_rd;
reg [4:0] ID_EX_sa;
reg ID_EX_regDst;
reg ID_EX_loadImm;
reg ID_EX_regWrite;
reg [4:0] EX_MEM_writeRegister;
reg [31:0] EX_MEM_writeData;
reg [31:0] EX_MEM_aluOut;
reg EX_MEM_regWrite;
reg EX_MEM_memToReg;
reg [3:0] EX_MEM_memWrite;
reg [1:0] EX_MEM_memReadWidth;
reg [4:0] MEM_WB_writeRegister;
reg [31:0] MEM_WB_aluOut;
reg [31:0] MEM_WB_memoryOut;
reg MEM_WB_regWrite;
reg MEM_WB_memToReg;
// Outputs
wire [7:0] dataToUartOutFifo;
wire readFifoFlag;
wire writeFifoFlag;
wire pipeEnable;
wire pipeReset;
wire ledStep;
wire ledCont;
wire ledIdle;
wire ledSend;
// Instantiate the Unit Under Test (UUT)
DebugUnit uut (
.clock(clock),
.reset(reset),
.endOfProgram(endOfProgram),
.uartFifoDataIn(uartFifoDataIn),
.uartDataAvailable(uartDataAvailable),
.FE_pc(FE_pc),
.IF_ID_instruction(IF_ID_instruction),
.IF_ID_pcNext(IF_ID_pcNext),
.ID_EX_aluOperation(ID_EX_aluOperation),
.ID_EX_sigExt(ID_EX_sigExt),
.ID_EX_readData1(ID_EX_readData1),
.ID_EX_readData2(ID_EX_readData2),
.ID_EX_aluSrc(ID_EX_aluSrc),
.ID_EX_aluShiftImm(ID_EX_aluShiftImm),
.ID_EX_memWrite(ID_EX_memWrite),
.ID_EX_memToReg(ID_EX_memToReg),
.ID_EX_memReadWidth(ID_EX_memReadWidth),
.ID_EX_rs(ID_EX_rs),
.ID_EX_rt(ID_EX_rt),
.ID_EX_rd(ID_EX_rd),
.ID_EX_sa(ID_EX_sa),
.ID_EX_regDst(ID_EX_regDst),
.ID_EX_loadImm(ID_EX_loadImm),
.ID_EX_regWrite(ID_EX_regWrite),
.EX_MEM_writeRegister(EX_MEM_writeRegister),
.EX_MEM_writeData(EX_MEM_writeData),
.EX_MEM_aluOut(EX_MEM_aluOut),
.EX_MEM_regWrite(EX_MEM_regWrite),
.EX_MEM_memToReg(EX_MEM_memToReg),
.EX_MEM_memWrite(EX_MEM_memWrite),
.EX_MEM_memReadWidth(EX_MEM_memReadWidth),
.MEM_WB_writeRegister(MEM_WB_writeRegister),
.MEM_WB_aluOut(MEM_WB_aluOut),
.MEM_WB_memoryOut(MEM_WB_memoryOut),
.MEM_WB_regWrite(MEM_WB_regWrite),
.MEM_WB_memToReg(MEM_WB_memToReg),
.dataToUartOutFifo(dataToUartOutFifo),
.readFifoFlag(readFifoFlag),
.writeFifoFlag(writeFifoFlag),
.pipeEnable(pipeEnable),
.pipeReset(pipeReset),
.ledStep(ledStep),
.ledCont(ledCont),
.ledIdle(ledIdle),
.ledSend(ledSend)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
endOfProgram = 0;
uartFifoDataIn = 0;
uartDataAvailable = 0;
FE_pc = 0;
IF_ID_instruction = 0;
IF_ID_pcNext = 0;
ID_EX_aluOperation = 0;
ID_EX_sigExt = 0;
ID_EX_readData1 = 0;
ID_EX_readData2 = 0;
ID_EX_aluSrc = 0;
ID_EX_aluShiftImm = 0;
ID_EX_memWrite = 0;
ID_EX_memToReg = 0;
ID_EX_memReadWidth = 0;
ID_EX_rs = 0;
ID_EX_rt = 0;
ID_EX_rd = 0;
ID_EX_sa = 0;
ID_EX_regDst = 0;
ID_EX_loadImm = 0;
ID_EX_regWrite = 0;
EX_MEM_writeRegister = 0;
EX_MEM_writeData = 0;
EX_MEM_aluOut = 0;
EX_MEM_regWrite = 0;
EX_MEM_memToReg = 0;
EX_MEM_memWrite = 0;
EX_MEM_memReadWidth = 0;
MEM_WB_writeRegister = 0;
MEM_WB_aluOut = 0;
MEM_WB_memoryOut = 0;
MEM_WB_regWrite = 0;
MEM_WB_memToReg = 0;
// Wait 100 ns for global reset to finish
#10;
reset = 1;
#4;
reset = 0;
#4;
uartFifoDataIn = "s";
#4;
uartDataAvailable = 1;
#4;
uartDataAvailable = 0;
#4;
uartFifoDataIn = "n";
uartDataAvailable = 1;
#4;
// Add stimulus here
end
always begin
clock = ~clock;
#1;
end
endmodule
|
//======================================================================
//
// Design Name: PRESENT Block Cipher
// Module Name: PRESENT_ENCRYPT_SBOX
// Language: Verilog-2001
//
// Description: Substitution Box (s-box) of Present Encryption
//
// Dependencies: none
//
// Designer: Saied H. Khayat
// Date: 3/2011
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// condition is met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`timescale 1ns/1ps
module PRESENT_ENCRYPT_SBOX (
output reg [3:0] odat,
input [3:0] idat
);
always @(idat)
case (idat)
4'h0 : odat = 4'hC;
4'h1 : odat = 4'h5;
4'h2 : odat = 4'h6;
4'h3 : odat = 4'hB;
4'h4 : odat = 4'h9;
4'h5 : odat = 4'h0;
4'h6 : odat = 4'hA;
4'h7 : odat = 4'hD;
4'h8 : odat = 4'h3;
4'h9 : odat = 4'hE;
4'hA : odat = 4'hF;
4'hB : odat = 4'h8;
4'hC : odat = 4'h4;
4'hD : odat = 4'h7;
4'hE : odat = 4'h1;
4'hF : odat = 4'h2;
endcase
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_hwbrk.v
//
// *Module Description:
// Hardware Breakpoint / Watchpoint module
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_clk, // Debug unit clock
dbg_din, // Debug register data input
dbg_rst, // Debug unit reset
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
pc // Program counter
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input dbg_clk; // Debug unit clock
input [15:0] dbg_din; // Debug register data input
input dbg_rst; // Debug unit reset
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] pc; // Program counter
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: '10' & '11' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
addr1_wr_set, addr1_rd_set,
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
wire equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
wire d_addr0_rd = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_addr1_rd = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_range_rd = equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule // omsp_dbg_hwbrk
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[300005]; int indeg[300005]; queue<int> q; int dp[300005][26], ma = 1; string s; int n, m, x, y, cnt = 0; bool co = 1; int main() { cin >> n >> m; cin >> s; for (int i = 0; i < m; i++) { cin >> x >> y; x--; y--; indeg[y]++; adj[x].push_back(y); } for (int i = 0; i < n; i++) { if (indeg[i] == 0) { q.push(i); dp[i][s[i] - a ]++; } } while (!q.empty()) { int u = q.front(); q.pop(); for (int v : adj[u]) { for (int j = 0; j < 26; j++) { dp[v][j] = max(dp[v][j], dp[u][j] + (s[v] - a == j)); } indeg[v]--; if (indeg[v] == 0) q.push(v); } cnt++; } if (cnt < n) { cout << -1 n ; } else { for (int i = 0; i < n; i++) { for (int j = 0; j < 26; j++) { if (dp[i][j] > ma) ma = dp[i][j]; } } cout << ma << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while ((t--)) { int n; cin >> n; int arr[n]; int diff[n - 1]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int ctr = 0; int min = arr[n - 1]; for (int i = n - 2; i >= 0; i--) { if (min >= arr[i]) { min = arr[i]; } else { ctr++; } } cout << ctr << n ; } return 0; } |
#include <bits/stdc++.h> const int MAXN = 210; const int mod = 1e9 + 7; void reduce(int& x) { x += x >> 31 & mod; } int mul(int x, int y) { return (long long)x * y % mod; } void fma(int& x, int y, int z) { x = ((long long)y * z + x) % mod; } struct vec { int x, y; vec() { x = y = 0; } vec(int a, int b) { x = a, y = b; } vec operator+(vec b) const { return vec(x + b.x, y + b.y); } vec operator-(vec b) const { return vec(x - b.x, y - b.y); } long long operator^(vec b) const { return (long long)x * b.y - (long long)y * b.x; } long long operator*(vec b) const { return (long long)x * b.x + (long long)y * b.y; } bool operator==(vec b) const { return x == b.x && y == b.y; } } ps[MAXN]; int n; long long cross(vec x, vec y, vec z) { return (y - x) ^ (z - x); } inline int sgn(long long x) { return x < 0 ? -1 : x > 0; } int dp[MAXN][MAXN]; int main() { std::ios_base::sync_with_stdio(false), std::cin.tie(0); std::cin >> n; for (int i = 1; i <= n; ++i) std::cin >> ps[i].x >> ps[i].y; long long area = 0; for (int i = 1; i <= n; ++i) area += ps[i] ^ ps[i == n ? 1 : i + 1]; for (int i = 1; i < n; ++i) dp[i][i + 1] = 1; for (int L = 3; L <= n; ++L) for (int l = 1; l + L - 1 <= n; ++l) { int r = l + L - 1; for (int p = l + 1; p < r; ++p) if (sgn(cross(ps[p], ps[r], ps[l])) == sgn(area)) fma(dp[l][r], dp[l][p], dp[p][r]); } std::cout << dp[1][n] << std::endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x0FFFFFFF; const long long INFLL = 0x0FFFFFFFFFFFFFFFll; const int MAXN = 300005; int n, m, x, y; vector<int> g[MAXN]; int ans[MAXN]; int getenemies(int i) { int c = 0; for (size_t j = 0; j < g[i].size(); j++) if (ans[g[i][j]] == ans[i]) c++; return c; } void solve(int p) { if (getenemies(p) > 1) { ans[p] = 1 - ans[p]; for (size_t j = 0; j < g[p].size(); j++) solve(g[p][j]); } } int main() { cin >> n >> m; while (m--) { cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } for (int i = 1; i <= n; i++) solve(i); for (int i = 1; i <= n; i++) cout << ans[i]; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 11; int a[N], b[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> a[i] >> b[i]; } vector<int> v; for (int p = 1; p <= 200; p++) { int x = 0; for (int i = 1; i <= m; i++) { int d = (a[i] / p); if (a[i] % p != 0) d++; if (b[i] != d) { x = 1; break; } } if (x == 0) { int d = (n / p); if (n % p != 0) d++; v.push_back(d); } } sort(v.begin(), v.end()); if (v[0] != v[v.size() - 1]) { cout << -1 << endl; } else cout << v[0] << endl; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long MOD2 = 998244353; double eps = 1e-12; using namespace std; template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T_container, typename T = typename enable_if< !is_same<T_container, string>::value, typename T_container::value_type>::type> ostream &operator<<(ostream &os, const T_container &v) { os << { ; string sep; for (const T &x : v) os << sep << x, sep = , ; return os << } ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,fma ) #pragma GCC optimize( unroll-loops ) template <typename T> void get_ar(T *ar, long long n) { for (long long i = 0; i < n; i++) cin >> ar[i]; } template <typename T> void printar(T *ar, long long n) { for (long long i = 0; i < n; i++) cout << ar[i] << ; cout << n ; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long imod(long long a, long long m) { return power(a, m - 2, m); } template <typename T, size_t N, size_t M> void print2dArray(T (&theArray)[N][M], long long n = N, long long m = M) { for (long long x = 0; x < n; x++) { for (long long y = 0; y < m; y++) { cout << theArray[x][y] << ; } cout << n ; } } template <typename T, size_t N> void print_ar(T (&theArray)[N], long long n = N) { for (long long x = 0; x < n; x++) { cout << theArray[x] << ; } cout << n ; } struct DSU { long long connected; vector<long long> par, sz, mi, ma; void init(long long n) { par = sz = mi = ma = vector<long long>(n + 1, 0); for (long long i = 1; i <= n; i++) par[i] = i, sz[i] = 1, mi[i] = i, ma[i] = i; connected = n; } long long getPar(long long u) { while (u != par[u]) { par[u] = par[par[u]]; u = par[u]; } return u; } long long getSize(long long u) { return sz[getPar(u)]; } void merge(long long u, long long v) { long long par1 = getPar(u), par2 = getPar(v); if (par1 == par2) return; connected--; if (sz[par1] > sz[par2]) swap(par1, par2); long long aa = min(mi[par1], mi[par2]); long long bb = max(ma[par1], ma[par2]); sz[par2] += sz[par1]; sz[par1] = 0; par[par1] = par[par2]; mi[par2] = aa; ma[par2] = bb; } }; DSU dd; vector<long long> pres, pref; long long give(long long p1) { long long l = dd.mi[p1], r = dd.ma[p1]; long long tot = pres[r] - pres[l - 1]; long long ans = pref[r] - pref[r - tot]; return ans; } void solve() { long long n, m, q, K, ans = 0, tmp; cin >> n >> m >> q; vector<long long> a(n), b(m); for (long long i = 0; i < n; i++) { cin >> a[i]; ans += a[i]; } for (long long i = 0; i < m; i++) { cin >> b[i]; } vector<vector<long long> > temp; temp.push_back({0, 0}); for (long long i = 0; i < n; i++) { temp.push_back({a[i], 1}); } for (long long i = 0; i < m; i++) { temp.push_back({b[i], 0}); } dd.init(n + m + 1); sort((temp).begin(), (temp).end()); pres.resize(n + m + 1, 0); pref.resize(n + m + 1, 0); for (long long i = 1; i < ((long long)(temp).size()); i++) { pres[i] = pres[i - 1] + temp[i][1]; pref[i] = pref[i - 1] + temp[i][0]; } vector<vector<long long> > diff; for (long long i = 1; i < ((long long)(temp).size()) - 1; i++) { diff.push_back({temp[i + 1][0] - temp[i][0], i}); } sort((diff).begin(), (diff).end()); long long cur = 0; vector<vector<long long> > quer; for (long long i = 0; i < q; i++) { long long x; cin >> x; quer.push_back({x, i}); } sort((quer).begin(), (quer).end()); vector<long long> fin(q, 0); for (auto x : quer) { long long k = x[0], ind = x[1]; while (cur < ((long long)(diff).size()) && diff[cur][0] <= k) { long long p1 = dd.getPar(diff[cur][1]), p2 = dd.getPar(diff[cur][1] + 1); ans -= give(p1); ans -= give(p2); dd.merge(p1, p2); long long pa = dd.getPar(p1); ans += give(pa); cur++; } fin[ind] = ans; } for (long long i = 0; i < q; i++) { cout << fin[i] << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; for (long long it = 1; it <= t; it++) { solve(); } return 0; } |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback () ////
//// - Julius Baxter () ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module bootrom
#(parameter addr_width = 5,
parameter b3_burst = 0)
(
input wb_clk,
input wb_rst,
input [(addr_width+2)-1:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o);
reg [addr_width-1:0] adr;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (adr)
`include "bootrom_data.vh"
/*
// Zero r0 and endless loop
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h00000000;
4 : wb_dat_o <= 32'h15000000;
*/
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
generate
if(b3_burst) begin : gen_b3_burst
reg wb_stb_i_r;
reg new_access_r;
reg burst_r;
wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
wire new_access = (wb_stb_i & !wb_stb_i_r);
wire new_burst = (burst & !burst_r);
always @(posedge wb_clk) begin
new_access_r <= new_access;
burst_r <= burst;
wb_stb_i_r <= wb_stb_i;
end
always @(posedge wb_clk)
if (wb_rst)
adr <= 0;
else if (new_access)
// New access, register address, ack a cycle later
adr <= wb_adr_i[(addr_width+2)-1:2];
else if (burst) begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr <= adr + 1;
2'b01: adr[1:0] <= adr[1:0] + 1;
2'b10: adr[2:0] <= adr[2:0] + 1;
2'b11: adr[3:0] <= adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr <= wb_adr_i[(addr_width+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o <= 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
wb_ack_o <= 1;
else
wb_ack_o <= 0;
end else begin
always @(wb_adr_i)
adr <= wb_adr_i;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Handshake synchronizer for sharing a data buffer across two clock domains
This module arbitrates a unidirectional transfer of data from port A to port B through an external buffer.
To send data (port A)
Load data into the buffer
Assert en_a for one cycle
busy_a goes high
Wait for ack_a to go high
The buffer can now be written to again
To receive data (port B)
Wait for en_b to go high
Read data
Assert ack_b for one cycle
Data buffer is now considered invalid, do not touch
*/
module HandshakeSynchronizer(
input wire clk_a,
input wire en_a,
output reg ack_a = 0,
output wire busy_a,
input wire clk_b,
output reg en_b = 0,
input wire ack_b
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Flag synchronizers
reg tx_en_in = 0;
wire tx_en_out;
reg tx_ack_in = 0;
wire tx_ack_out;
ThreeStageSynchronizer sync_tx_en
(.clk_in(clk_a), .din(tx_en_in), .clk_out(clk_b), .dout(tx_en_out));
ThreeStageSynchronizer sync_tx_ack
(.clk_in(clk_b), .din(tx_ack_in), .clk_out(clk_a), .dout(tx_ack_out));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control logic, transmit side
reg[1:0] state_a = 0;
assign busy_a = state_a[1] || en_a;
always @(posedge clk_a) begin
ack_a <= 0;
case(state_a)
//Idle - sit around and wait for input to arrive
0: begin
if(en_a) begin
tx_en_in <= 1;
state_a <= 1;
end
end
//Data sent, wait for it to be acknowledged
1: begin
if(tx_ack_out) begin
tx_en_in <= 0;
state_a <= 2;
end
end
//When acknowledge flag goes low the receiver is done with the data.
//Tell the sender and we're done.
2: begin
if(!tx_ack_out) begin
ack_a <= 1;
state_a <= 0;
end
end
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control logic, receive side
reg[1:0] state_b = 0;
always @(posedge clk_b) begin
en_b <= 0;
case(state_b)
//Idle - sit around and wait for input to arrive
0: begin
if(tx_en_out) begin
en_b <= 1;
state_b <= 1;
end
end
//Data received, wait for caller to process it
1: begin
if(ack_b) begin
tx_ack_in <= 1;
state_b <= 2;
end
end
//When transmit flag goes low the sender knows we're done
2: begin
if(!tx_en_out) begin
state_b <= 0;
tx_ack_in <= 0;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; class Solution { int n, x[2]; vector<pair<long long, int>> A; public: void run() { cin >> n >> x[0] >> x[1]; for (int i = 0; i < n; ++i) { int c; cin >> c; A.emplace_back(c, i); } sort(A.begin(), A.end()); for (int i = 0; i < n; ++i) { int a = A[i].first; int j = (x[0] + a - 1) / a + i; if (j < n and x[1] <= A[j].first * (n - j)) { cout << Yes n ; cout << j - i << << n - j << n ; for (int k = i; k < j; ++k) cout << A[k].second + 1 << n [k == j - 1]; for (int k = j; k < n; ++k) cout << A[k].second + 1 << n [k == n - 1]; return; } j = (x[1] + a - 1) / a + i; if (j < n and x[0] <= A[j].first * (n - j)) { cout << Yes n ; cout << n - j << << j - i << n ; for (int k = j; k < n; ++k) cout << A[k].second + 1 << n [k == n - 1]; for (int k = i; k < j; ++k) cout << A[k].second + 1 << n [k == j - 1]; return; } } cout << No n ; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); Solution().run(); } |
#include <bits/stdc++.h> using namespace std; int N; vector<pair<int, int> > v; vector<int> query; int ans; struct SEG { SEG(int l, int r, int sum) : l(l), r(r), sum(sum) {} int l, r; int sum; }; vector<SEG> seg; void init(int idx, int s, int e) { if (s == e) return; seg[idx].l = seg.size(); seg.push_back({-1, -1, 0}); seg[idx].r = seg.size(); seg.push_back({-1, -1, 0}); init(seg[idx].l, s, (s + e) / 2); init(seg[idx].r, (s + e) / 2 + 1, e); } void update(int idx, int s, int e, int x, int y) { seg[idx].sum += y; if (s == e) return; if (x <= (s + e) / 2) { update(seg[idx].l, s, (s + e) / 2, x, y); } else { update(seg[idx].r, (s + e) / 2 + 1, e, x, y); } } int calc(int idx, int s, int e, int x, int y) { if (x <= s && e <= y) return seg[idx].sum; if (x > e || y < s) return 0; return calc(seg[idx].l, s, (s + e) / 2, x, y) + calc(seg[idx].r, (s + e) / 2 + 1, e, x, y); } int main() { seg.push_back({-1, -1, 0}); scanf( %d , &N); init(0, 0, N - 1); for (int i = 0; i < N; i++) { int x; scanf( %d , &x); v.push_back({(x > 0) ? x : -x, i}); update(0, 0, N - 1, i, 1); } sort(v.begin(), v.end()); while (!v.empty()) { pair<int, int> now = v.back(); v.pop_back(); update(0, 0, N - 1, now.second, -1); query.push_back(now.second); while (!v.empty() && v.back().first == now.first) { query.push_back(v.back().second); update(0, 0, N - 1, v.back().second, -1); v.pop_back(); } while (!query.empty()) { int x = query.back(); query.pop_back(); ans += min(calc(0, 0, N - 1, 0, x - 1), calc(0, 0, N - 1, x + 1, N - 1)); } } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const long long int MXN = 1e18; struct node { double x, y; } p, p1, p2, p3, p4; double ji(node a, node b, node c) { return (b.x - a.x) * (c.y - a.y) - (c.x - a.x) * (b.y - a.y); } bool jug(node a) { if ((ji(p1, p2, a) * ji(p3, p4, a) >= 0) && (ji(p2, p3, a) * ji(p4, p1, a) >= 0)) return true; return false; } int main() { int n, d, m; cin >> n >> d >> m; p1.x = 0, p1.y = d; p2.x = d, p2.y = 0; p3.x = n, p3.y = n - d; p4.x = n - d, p4.y = n; int ans = 0; double a, b; for (int i = 0; i < m; i++) { cin >> p.x >> p.y; if (jug(p)) { cout << YES << endl; } else cout << NO << endl; } } |
#include <bits/stdc++.h> using namespace std; long long n, l, r, K, p; bool check(long long x) { long long t = K % (n + x); if (t == 0) t = n + x; if (t > min(p * 2, p + x)) return 0; if (t < p + max(0LL, x - n + p - 1)) return 0; return 1; } signed main() { scanf( %lld%lld%lld%lld , &n, &l, &r, &K); p = (r - l + 1 + n) % n; if (p > K) { return puts( -1 ), 0; } if (p == 0) p += n; if (n <= 100000) { for (long long i = n; i >= 0; i--) if (check(i)) { printf( %lld n , i); return 0; } puts( -1 ); return 0; } long long ans = 0; for (long long t = ceil((double)(K - 2 * p) / (double)(2 * n)); t * n + p <= K; t++) { long long y = K - n * t - p; long long x; if (t != 0) x = min((long long)floor((double)(n - p + y) / (1 + t)), (long long)y / t); else { x = (K - p + 1) + (n - p); } y = K - n * t - p - t * x; if (y < 0 || y > p || y > x || x > n) continue; ans = max(ans, x); y = K - n * t - p + 1; if (t != 0) x = min((long long)floor((double)(n - p + y) / (1 + t)), (long long)y / t); else { x = (K - p + 1) + (n - p); } y = K - n * t - p - t * x; if (y < 0 || y > p || y > x || x > n) continue; ans = max(ans, x); } printf( %lld n , ans); return 0; } |
/*
Code for Setting up ADF4158 PLL Module
By Hsiang-Yi Chung
February, 2016
*/
module PLL_ADF4158(
input clk,
input reset_n,
output reg writeData,
output reg loadEnable,
output pll_clk
);
localparam s0 = 2'b00;
localparam s1 = 2'b01;
localparam s2 = 2'b10;
localparam s3 = 2'b11;
localparam num_registers_to_set = 8;
reg [31:0] writeDataArray [num_registers_to_set - 1:0];
reg [31:0] current_register;
reg [1:0] nextState, state;
reg [4:0] bit_counter;
reg [2:0] register_counter;
reg dec_register_counter, dec_bit_counter;
assign pll_clk = clk;
initial begin
state = s0;
bit_counter = 31;
register_counter = num_registers_to_set - 1;
dec_register_counter = 0;
dec_bit_counter = 0;
loadEnable = 0;
writeDataArray[0] = 32'b1_0000_000011000110_000000000000_000; //reg 0
writeDataArray[1] = 32'b0000_0000000000000_000000000000_001; //reg 1
writeDataArray[2] = 32'b000_0_1111_0_1_1_0_00001_000000000001_010; //reg 2
writeDataArray[3] = 32'b0000000000000000_1_0_00_01_0_0_0_0_0_0_0_011; //reg 3
writeDataArray[4] = 32'b0_00000_0_11_00_11_000000000001_0000_100; //reg 4
writeDataArray[5] = 32'b00_0_0_00_0_0_0_0000_0010010101110010_101; //reg 5 DEV SEL = 0
writeDataArray[6] = 32'b00000000_0_00000011011010110000_110; //reg 6 STEP SEL = 0
writeDataArray[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0_111; //reg 7
end
always @ (negedge clk) begin
if(!reset_n) begin
state <= s0;
end
else begin
state <= nextState;
end
end
always @(negedge clk) begin
if(dec_register_counter == 1) begin
register_counter <= register_counter - 1;
end
if(dec_bit_counter == 1) begin
bit_counter <= bit_counter - 1;
end
end
always @ * begin
dec_bit_counter = 0;
dec_register_counter = 0;
loadEnable = 0;
current_register = writeDataArray[register_counter];
writeData = current_register[bit_counter];
case(state)
s0: begin
dec_bit_counter = 1;
nextState = s1;
end
s1: begin
if(bit_counter == 0) begin
nextState = s2;
end else begin
nextState = s1;
dec_bit_counter = 1;
end
end
s2: begin
loadEnable = 1;
if(register_counter != 0) begin
nextState = s0;
dec_register_counter = 1;
dec_bit_counter = 1;
end else begin
nextState = s3;
end
end
s3: begin
nextState = s3;
end
endcase
end
endmodule
|
/*
Bank of GPRs.
*/
module GpReg(
clk,
isRd1,
isWr1,
isQw1,
idReg1,
dataLo1,
dataHi1,
isRd2,
isWr2,
isQw2,
idReg2,
dataLo2,
dataHi2,
isRd3,
isWr3,
isQw3,
idReg3,
dataLo3,
dataHi3
);
input clk; //clock
input isRd1; //Is Read
input isRd2; //Is Read
input isRd3; //Is Read
input isWr1; //Is Write
input isWr2; //Is Write
input isWr3; //Is Write
input isQw1; //Is QuadWord
input isQw2; //Is QuadWord
input isQw3; //Is QuadWord
input[6:0] idReg1;
input[6:0] idReg2;
input[6:0] idReg3;
inout[31:0] dataLo1;
inout[31:0] dataHi1;
inout[31:0] dataLo2;
inout[31:0] dataHi2;
inout[31:0] dataLo3;
inout[31:0] dataHi3;
reg[31:0] regs[0:127];
reg[6:0] tIdReg1Lo;
reg[6:0] tIdReg1Hi;
reg[6:0] tIdReg2Lo;
reg[6:0] tIdReg2Hi;
reg[6:0] tIdReg3Lo;
reg[6:0] tIdReg3Hi;
//reg[31:0] tDataLo1;
//reg[31:0] tDataHi1;
//reg[31:0] tDataLo2;
//reg[31:0] tDataHi2;
//reg[31:0] tDataLo3;
//reg[31:0] tDataHi3;
//assign tIdReg1Lo[5:0] = idReg1;
//assign tIdReg1Hi[5:0] = idReg1;
//assign tIdReg1Lo[6] = 1'b0;
//assign tIdReg1Hi[6] = 1'b1;
always @ (isRd1 or isWr1) begin
// tIdReg1Lo[5:0] = idReg1;
// tIdReg1Hi[5:0] = idReg1;
// tIdReg1Lo[6] = 1'b0;
// tIdReg1Hi[6] = 1'b1;
tIdReg1Lo = idReg1;
tIdReg1Hi = idReg1 | (7'h40);
if(isRd1==1'b1)
begin
dataLo1 = regs[tIdReg1Lo];
if(isQw1==1'b1)
dataHi1 = regs[tIdReg1Hi];
end
// dataLo1 = tDataLo1;
// dataHi1 = tDataHi1;
end
always @ (isRd2 or isWr2) begin
// tIdReg2Lo[5:0] = idReg2;
// tIdReg2Hi[5:0] = idReg2;
// tIdReg2Lo[6] = 1'b0;
// tIdReg2Hi[6] = 1'b1;
tIdReg2Lo = idReg2;
tIdReg2Hi = idReg2 | (7'h40);
if(isRd2==1'b1)
begin
dataLo2 = regs[tIdReg2Lo];
if(isQw2==1'b1)
dataHi2 = regs[tIdReg2Hi];
end
end
always @ (isRd3 or isWr3) begin
// tIdReg3Lo[5:0] = idReg3;
// tIdReg3Hi[5:0] = idReg3;
// tIdReg3Lo[6] = 1'b0;
// tIdReg3Hi[6] = 1'b1;
tIdReg3Lo = idReg3;
tIdReg3Hi = idReg3 | (7'h40);
if(isRd3==1'b1)
begin
dataLo3 = regs[tIdReg3Lo];
if(isQw3==1'b1)
dataHi3 = regs[tIdReg3Hi];
end
end
//always @ (posedge clk) begin
//end
always @ (negedge clk) begin
if(isWr1==1'b1)
begin
regs[tIdReg1Lo] <= dataLo1;
if(isQw1==1'b1)
regs[tIdReg1Hi] <= dataHi1;
end
if(isWr2==1'b1)
begin
regs[tIdReg2Lo] <= dataLo2;
if(isQw2==1'b1)
regs[tIdReg2Hi] <= dataHi2;
end
if(isWr3==1'b1)
begin
regs[tIdReg3Lo] <= dataLo3;
if(isQw3==1'b1)
regs[tIdReg3Hi] <= dataHi3;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_PP_SYMBOL_V
|
`timescale 1 ns / 1 ps
module axis_level_cross #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CROSS_MASK = 8192,
parameter ALWAYS_READY = "TRUE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire signed[AXIS_TDATA_WIDTH-1:0] level,
input wire direction,
// Slave side
input wire signed [AXIS_TDATA_WIDTH-1:0] s_axis_tdata, //Data (32 bit vector)
input wire s_axis_tvalid, //Validity of Data (Don't take data if not true)
output wire s_axis_tready, //Ready to accept data
// Master side
input wire m_axis_tready,
output wire signed [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire state_out
);
reg [1:0] int_cross_reg, int_cross_next;
reg int_state_reg, int_state_next;
wire int_comp_wire; //1 bit wide (true/false) because length not declared
assign int_comp_wire = direction?s_axis_tdata<level:s_axis_tdata>level; //Internal Comparison wire. direction = 1 then take <, direction = 0 take >. C selection statement
always @(posedge aclk)
begin
if(~aresetn)
begin
int_state_reg <= 0;
end
else
begin
int_state_reg <= int_state_next;
end
end
always @(posedge aclk)
begin
int_cross_reg <= int_cross_next;
end
//Monitors transition in level
always @*
begin
int_cross_next = int_cross_reg;
int_state_next = int_state_reg;
if(s_axis_tvalid)
begin
//int_cross_next = {int_cross_reg[0:0],s_axis_tdata & CROSS_MASK? 1'b1:1'b0}; //Looks for change of sign in signal. Figure it out.
int_cross_next = {int_cross_reg[0:0],int_comp_wire}; //Concatenation. Changes either LSB or MSB I'm not sure.
end
if(int_cross_reg == 2'b10) //Looks for "pattern" in the signal
begin
int_state_next = 1'b1; //Change state if "pattern" found
end
end
if(ALWAYS_READY == "TRUE")
assign s_axis_tready = 1'b1;
else
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
assign state_out = int_state_reg;
endmodule
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* $Date: 2013-07-01 18:48:47 -0400 (Mon, 01 Jul 2013) $ *)
(* #################################### *)
(** ** Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** ** Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** ** Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
|
#include <bits/stdc++.h> using namespace std; const int Nmax = 1e5 + 5; const long long inf = 1e18; int n, k, nr, st[Nmax], A[Nmax], nextBigger[Nmax]; long long dp[Nmax], old[Nmax]; struct Ec { int a; long long b; long long operator()(int x) { return (long long)a * x + b; } }; Ec interv[Nmax]; class Batch { vector<Ec> v; double intersect(Ec A, Ec B) { return (double)(A.b - B.b) / (B.a - A.a); } bool bad(Ec a, Ec b, Ec c) { return intersect(a, c) >= intersect(a, b); } public: void clear() { v.clear(); } void add(Ec ec) { while (v.size() >= 2 && bad(v[v.size() - 2], v.back(), ec)) v.pop_back(); v.push_back(ec); } long long query(int x) { if (v.empty()) return inf; while (v.size() >= 2 && intersect(v[v.size() - 2], v.back()) <= x) v.pop_back(); return v.back()(x); } }; class SegmentTree { Batch a[Nmax << 2]; public: void update1(int node, int st, int dr, int pos, Ec ec) { a[node].add(ec); if (st == dr) return; if (pos <= ((st + dr) >> 1)) update1((node << 1), st, ((st + dr) >> 1), pos, ec); else update1(((node << 1) | 1), ((st + dr) >> 1) + 1, dr, pos, ec); } void update2(int node, int st, int dr, int L, int R, Ec ec) { if (L <= st && dr <= R) { a[node].add(ec); return; } if (L <= ((st + dr) >> 1)) update2((node << 1), st, ((st + dr) >> 1), L, R, ec); if (((st + dr) >> 1) < R) update2(((node << 1) | 1), ((st + dr) >> 1) + 1, dr, L, R, ec); } long long query1(int node, int st, int dr, int L, int R, int p) { if (L <= st && dr <= R) return a[node].query(p); long long x = inf, y = inf; if (L <= ((st + dr) >> 1)) x = query1((node << 1), st, ((st + dr) >> 1), L, R, p); if (((st + dr) >> 1) < R) y = query1(((node << 1) | 1), ((st + dr) >> 1) + 1, dr, L, R, p); return min(x, y); } long long query2(int node, int st, int dr, int pos, int p) { long long x = a[node].query(p); if (st == dr) return x; if (pos <= ((st + dr) >> 1)) x = min(x, query2((node << 1), st, ((st + dr) >> 1), pos, p)); else x = min(x, query2(((node << 1) | 1), ((st + dr) >> 1) + 1, dr, pos, p)); return x; } void clear() { int i; for (i = 1; i <= ((n + 1) << 2); ++i) a[i].clear(); } } aint; void solve() { int i; aint.clear(); for (i = n; i >= 0; --i) aint.update1(1, 0, n, i, {-i, old[i]}); nr = 0; st[0] = 0; for (i = 1; i <= n; ++i) { while (nr && A[i] >= A[st[nr]]) --nr; st[++nr] = i; interv[i] = {A[i], aint.query1(1, 0, n, st[nr - 1], st[nr] - 1, A[i])}; } aint.clear(); for (i = n; i >= 1; --i) aint.update2(1, 0, n, i, nextBigger[i] - 1, interv[i]); for (i = 1; i <= n; ++i) dp[i] = aint.query2(1, 0, n, i, i); } int main() { int i, j; cin >> n >> k; for (i = 1; i <= n; ++i) cin >> A[i]; nr = 0; st[0] = n + 1; for (i = n; i; --i) { while (nr && A[i] > A[st[nr]]) --nr; nextBigger[i] = st[nr]; st[++nr] = i; } old[0] = 0; for (i = 1; i <= n; ++i) old[i] = inf; for (i = 1; i <= k; ++i) { for (j = 1; j <= n; ++j) dp[j] = inf; dp[0] = 0; solve(); for (j = 1; j <= n; ++j) old[j] = dp[j]; } cout << dp[n] << n ; return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 13689 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w2048,
w2049,
w16,
w2033,
w512,
w1521,
w12168,
w13689;
assign w1 = i_data0;
assign w12168 = w1521 << 3;
assign w13689 = w1521 + w12168;
assign w1521 = w2033 - w512;
assign w16 = w1 << 4;
assign w2033 = w2049 - w16;
assign w2048 = w1 << 11;
assign w2049 = w1 + w2048;
assign w512 = w1 << 9;
assign o_data0 = w13689;
//multiplier_block area estimate = 6566.313589725;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
function integer min;
input integer a, b;
begin
if (a < b)
min = a;
else
min = b;
end
endfunction
genvar i;
generate begin
if (A_WIDTH == 0) begin
assign Y = 0;
end
if (A_WIDTH == 1) begin
assign Y = A;
end
if (A_WIDTH == 2) begin
wire ybuf;
OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
assign Y = ybuf;
end
if (A_WIDTH == 3) begin
wire ybuf;
OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
assign Y = ybuf;
end
if (A_WIDTH > 3) begin
localparam next_stage_sz = (A_WIDTH+2) / 3;
wire [next_stage_sz-1:0] next_stage;
for (i = 0; i < next_stage_sz; i = i+1) begin
localparam bits = min(A_WIDTH - 3*i, 3);
assign next_stage[i] = |A[3*i +: bits];
end
assign Y = |next_stage;
end
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const long long INFL = 1e18 + 123; const double PI = atan2(0, -1); mt19937 tw(960172); long long rnd(long long x, long long y) { static uniform_int_distribution<long long> d; return d(tw) % (y - x + 1) + x; } const int MAXN = 1e5 + 5; vector<int> graph[MAXN], graph2[MAXN]; int res[MAXN]; bool used[MAXN]; int dfs(int v, vector<int>* g, int c) { used[v] = true; if (res[v] == 1 - c) { cout << No n ; exit(0); } res[v] = c; for (int to : g[v]) { if (!used[to]) { dfs(to, g, c); } } return 0; } int main() { cerr << fixed << setprecision(15); cout << fixed << setprecision(15); int n, m; scanf( %d%d , &n, &m); vector<vector<int>> inp; for (int i = 0; i < n; ++i) { int l; scanf( %d , &l); inp.push_back({}); for (int j = 0; j < l; ++j) { int num; scanf( %d , &num); --num; inp.back().push_back(num); } } for (int i = 0; i < m; ++i) { res[i] = 2; } for (int i = 0; i < n - 1; ++i) { bool flag = false; for (int j = 0; j < min(((int)(inp[i]).size()), ((int)(inp[i + 1]).size())); ++j) { if (inp[i][j] != inp[i + 1][j]) { flag = true; if (inp[i][j] > inp[i + 1][j]) { if (res[inp[i][j]] == 1 || res[inp[i + 1][j]] == 0) { cout << No n ; return 0; } res[inp[i][j]] = 0; res[inp[i + 1][j]] = 1; } else { graph[inp[i + 1][j]].push_back(inp[i][j]); graph2[inp[i][j]].push_back(inp[i + 1][j]); } break; } } if (!flag && ((int)(inp[i]).size()) > ((int)(inp[i + 1]).size())) { cout << No n ; return 0; } } for (int i = 0; i < m; ++i) { if (res[i] == 0 && !used[i]) { dfs(i, graph, res[i]); } if (res[i] == 1 && !used[i]) { dfs(i, graph2, res[i]); } } cout << Yes n ; vector<int> ans; for (int i = 0; i < m; ++i) { if (res[i] == 0) { ans.push_back(i); } } cout << ((int)(ans).size()) << n ; for (int num : ans) { cout << num + 1 << ; } cout << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s18 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s18.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_SYMBOL_V
`define SKY130_FD_SC_HVL__NAND2_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 5; int main() { int num, r; cin >> num >> r; vector<pair<int, int>> arr(num + 1); vector<bool> visited(r + 2, 0); for (int i = 1; i <= num; ++i) { cin >> arr[i].first >> arr[i].second; for (int j = arr[i].first; j <= arr[i].second; ++j) { visited[j] = 1; } } long long ans = 0; for (int k = 1; k <= r; ++k) { if (visited[k] == 0) ans++; } cout << ans << n ; for (int k = 1; k <= r; ++k) { if (visited[k] == 0) cout << k << ; } } |
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// result_valid O 1
// result_value O 64 reg
// CLK I 1 clock
// RST_N I 1 reset
// put_args_x_is_signed I 1
// put_args_x I 32
// put_args_y_is_signed I 1
// put_args_y I 32
// EN_put_args I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkIntMul_32(CLK,
RST_N,
put_args_x_is_signed,
put_args_x,
put_args_y_is_signed,
put_args_y,
EN_put_args,
result_valid,
result_value);
input CLK;
input RST_N;
// action method put_args
input put_args_x_is_signed;
input [31 : 0] put_args_x;
input put_args_y_is_signed;
input [31 : 0] put_args_y;
input EN_put_args;
// value method result_valid
output result_valid;
// value method result_value
output [63 : 0] result_value;
// signals for module outputs
wire [63 : 0] result_value;
wire result_valid;
// register m_rg_isNeg
reg m_rg_isNeg;
wire m_rg_isNeg$D_IN, m_rg_isNeg$EN;
// register m_rg_signed
reg m_rg_signed;
wire m_rg_signed$D_IN, m_rg_signed$EN;
// register m_rg_state
reg [1 : 0] m_rg_state;
wire [1 : 0] m_rg_state$D_IN;
wire m_rg_state$EN;
// register m_rg_x
reg [63 : 0] m_rg_x;
wire [63 : 0] m_rg_x$D_IN;
wire m_rg_x$EN;
// register m_rg_xy
reg [63 : 0] m_rg_xy;
wire [63 : 0] m_rg_xy$D_IN;
wire m_rg_xy$EN;
// register m_rg_y
reg [31 : 0] m_rg_y;
wire [31 : 0] m_rg_y$D_IN;
wire m_rg_y$EN;
// rule scheduling signals
wire CAN_FIRE_RL_m_compute,
CAN_FIRE_put_args,
WILL_FIRE_RL_m_compute,
WILL_FIRE_put_args;
// inputs to muxes for submodule ports
wire [63 : 0] MUX_m_rg_x$write_1__VAL_1,
MUX_m_rg_x$write_1__VAL_2,
MUX_m_rg_xy$write_1__VAL_2;
wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2;
// remaining internal signals
wire [63 : 0] x__h239, x__h341, xy___1__h265;
wire [31 : 0] _theResult___fst__h509,
_theResult___fst__h512,
_theResult___fst__h563,
_theResult___fst__h566,
_theResult___snd_fst__h558;
wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34;
// action method put_args
assign CAN_FIRE_put_args = 1'd1 ;
assign WILL_FIRE_put_args = EN_put_args ;
// value method result_valid
assign result_valid = m_rg_state == 2'd2 ;
// value method result_value
assign result_value = m_rg_xy ;
// rule RL_m_compute
assign CAN_FIRE_RL_m_compute = m_rg_state == 2'd1 ;
assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ;
// inputs to muxes for submodule ports
assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h509 } ;
assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ;
assign MUX_m_rg_xy$write_1__VAL_2 = (m_rg_y == 32'd0) ? x__h239 : x__h341 ;
assign MUX_m_rg_y$write_1__VAL_1 =
(put_args_x_is_signed && put_args_y_is_signed) ?
_theResult___fst__h566 :
_theResult___snd_fst__h558 ;
assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ;
// register m_rg_isNeg
assign m_rg_isNeg$D_IN =
(put_args_x_is_signed && put_args_y_is_signed) ?
put_args_x[31] != put_args_y[31] :
IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34 ;
assign m_rg_isNeg$EN = EN_put_args ;
// register m_rg_signed
assign m_rg_signed$D_IN = 1'b0 ;
assign m_rg_signed$EN = 1'b0 ;
// register m_rg_state
assign m_rg_state$D_IN = EN_put_args ? 2'd1 : 2'd2 ;
assign m_rg_state$EN =
WILL_FIRE_RL_m_compute && m_rg_y == 32'd0 || EN_put_args ;
// register m_rg_x
assign m_rg_x$D_IN =
EN_put_args ?
MUX_m_rg_x$write_1__VAL_1 :
MUX_m_rg_x$write_1__VAL_2 ;
assign m_rg_x$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 32'd0 || EN_put_args ;
// register m_rg_xy
assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ;
assign m_rg_xy$EN =
WILL_FIRE_RL_m_compute && (m_rg_y == 32'd0 || m_rg_y[0]) ||
EN_put_args ;
// register m_rg_y
assign m_rg_y$D_IN =
EN_put_args ?
MUX_m_rg_y$write_1__VAL_1 :
MUX_m_rg_y$write_1__VAL_2 ;
assign m_rg_y$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 32'd0 || EN_put_args ;
// remaining internal signals
assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34 =
put_args_x_is_signed ?
put_args_x[31] :
put_args_y_is_signed && put_args_y[31] ;
assign _theResult___fst__h509 =
put_args_x_is_signed ? _theResult___fst__h512 : put_args_x ;
assign _theResult___fst__h512 = put_args_x[31] ? -put_args_x : put_args_x ;
assign _theResult___fst__h563 =
put_args_y_is_signed ? _theResult___fst__h566 : put_args_y ;
assign _theResult___fst__h566 = put_args_y[31] ? -put_args_y : put_args_y ;
assign _theResult___snd_fst__h558 =
put_args_x_is_signed ? put_args_y : _theResult___fst__h563 ;
assign x__h239 = m_rg_isNeg ? xy___1__h265 : m_rg_xy ;
assign x__h341 = m_rg_xy + m_rg_x ;
assign xy___1__h265 = -m_rg_xy ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (m_rg_state$EN)
m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN;
end
if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN;
if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN;
if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN;
if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN;
if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_isNeg = 1'h0;
m_rg_signed = 1'h0;
m_rg_state = 2'h2;
m_rg_x = 64'hAAAAAAAAAAAAAAAA;
m_rg_xy = 64'hAAAAAAAAAAAAAAAA;
m_rg_y = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkIntMul_32
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000 * 1000 * 1000 + 7; const double EPS = 1e-9; int bit_count(int first) { return first == 0 ? 0 : 1 + bit_count(first & (first - 1)); } inline int low_bit(int first) { return first & -first; } inline int sign(double first) { return first < -EPS ? -1 : first > EPS ? 1 : 0; } inline int sign(int first) { return (first > 0) - (first < 0); } int nextComb(int first) { if (!first) { fprintf(stderr, nextComb(0) called n ); return ((1 << 30) - 1 + (1 << 30)); } int smallest = first & -first; int ripple = first + smallest; int ones = first ^ ripple; ones = (ones >> 2) / smallest; return ripple | ones; } template <class T> inline T gcd(T a, T b) { a = abs(a); b = abs(b); while (b) { int r = a % b; a = b; b = r; } return a; } template <class T> inline T lcm(T a, T b) { return a / gcd(a, b) * b; } inline int getInt() { int a; return scanf( %d , &a) ? a : (fprintf(stderr, trying to read n ), -1); } inline double getDouble() { double a; return scanf( %lf , &a) ? a : (fprintf(stderr, trying to read n ), -1.0); } inline double myRand() { return ((double)rand() / RAND_MAX) + ((double)rand() / RAND_MAX / RAND_MAX); } inline string getLine() { string ret; getline(cin, ret, : ); return ret; } long long process(string s, int base) { long long ret = 0; for (int i = (int)0; i < (int)((int)(s).size()); ++i) { ret *= base; if (isdigit(s[i])) ret += s[i] - 0 ; else ret += s[i] - A + 10; } return ret; } bool isValid(string s, int base) { for (int i = (int)0; i < (int)((int)(s).size()); ++i) { if (isdigit(s[i]) && s[i] - 0 >= base) return false; else if (s[i] - A + 10 >= base) return false; } return true; } void myCode() { string hrs, mins; getline(cin, hrs, : ); getline(cin, mins); vector<int> ret; if (((int)(hrs).size()) < 6 && ((int)(mins).size()) < 7) { for (int i = (int)2; i < (int)100; ++i) { if (isValid(hrs, i) == true && isValid(mins, i) == true) { if (process(hrs, i) < 24 && process(mins, i) < 60) { ret.push_back(i); } } } } if (ret.empty()) printf( 0 n ); else if (ret[((int)(ret).size()) - 1] == 99) printf( -1 n ); else for (int i = (int)0; i < (int)((int)(ret).size()); ++i) printf( %d%c , ret[i], i == ((int)(ret).size()) - 1 ? n : ); } int main() { srand(time(NULL)); myCode(); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using db = long double; using str = string; using pi = pair<int, int>; template <class T> using V = vector<T>; template <class T, size_t SZ> using AR = array<T, SZ>; using vi = V<int>; using vb = V<bool>; using vpi = V<pi>; const int MOD = 1e9 + 7; const db PI = acos((db)-1); mt19937 rng(0); template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } template <class T, class U> T fstTrue(T lo, T hi, U first) { ++hi; assert(lo <= hi); while (lo < hi) { T mid = lo + (hi - lo) / 2; first(mid) ? hi = mid : lo = mid + 1; } return lo; } using T = db; const T EPS = 1e-9; using P = pair<T, T>; using vP = V<P>; using Line = pair<P, P>; int sgn(T a) { return (a > EPS) - (a < -EPS); } T sq(T a) { return a * a; } T norm(P p) { return sq(p.first) + sq(p.second); } T abs(P p) { return sqrt(norm(p)); } T arg(P p) { return atan2(p.second, p.first); } P conj(P p) { return P(p.first, -p.second); } P perp(P p) { return P(-p.second, p.first); } P dir(T ang) { return P(cos(ang), sin(ang)); } const int mx = 100005; struct Eff { int n, k; P hab[mx]; bool works(db r) { V<pair<db, int>> ch; for (int i = 1; i <= n; i++) { if (abs(hab[i]) <= 2.0 * r - EPS) { db theta_diff = PI / 2.0 - asin(abs(hab[i]) / 2.0 / r); db theta = arg(hab[i]); assert(theta_diff <= PI / 2.0); ch.push_back(make_pair(theta - theta_diff, +1)); ch.push_back(make_pair(theta + theta_diff, -1)); ch.push_back(make_pair(theta - theta_diff + 2 * PI, +1)); ch.push_back(make_pair(theta + theta_diff + 2 * PI, -1)); } } sort(begin(ch), end(ch)); int running_sum = 0; for (auto u : ch) { running_sum += u.second; if (0 <= u.first && u.first <= 2 * PI) { if (running_sum >= k) return true; } } return false; } void solve() { cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> hab[i].first >> hab[i].second; } db lo = EPS; db hi = 200005.0; for (int i = 0; i < 50; i++) { db mid = (lo + hi) / 2; if (works(mid)) { hi = mid; } else { lo = mid; } } cout << lo << n ; } }; int main() { cin.tie(0)->sync_with_stdio(0); cout << fixed << setprecision(10); Eff e; e.solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_TB_V
`define SKY130_FD_SC_LS__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ls__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_TB_V
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// USB CRC5 and CRC16 Modules ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_crc5.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_crc5.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.1.0.1 2001/02/28 08:10:42 rudi
// Initial Release
//
//
`include "usbf_defines.v"
///////////////////////////////////////////////////////////////////
//
// CRC5
//
///////////////////////////////////////////////////////////////////
module usbf_crc5(crc_in, din, crc_out);
input [4:0] crc_in;
input [10:0] din;
output [4:0] crc_out;
assign crc_out[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^
din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4];
assign crc_out[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^
crc_in[0] ^ crc_in[1] ^ crc_in[4];
assign crc_out[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^
din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^
crc_in[2] ^ crc_in[3] ^ crc_in[4];
assign crc_out[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^
din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4];
assign crc_out[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^
crc_in[2] ^ crc_in[3] ^ crc_in[4];
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e13; void solve() { long long n; cin >> n; vector<pair<long long, long long> > a(n); for (long long i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; } sort(a.begin(), a.end()); long long cnt = 1, ans = 1, w = 1; for (long long i = 1; i < n; i++) { if (a[i].first == a[i - 1].first) continue; w++; if (a[i].second > a[i - 1].second) cnt++; else { ans = max(ans, cnt); cnt = 1; } } ans = max(ans, cnt); cout << w - ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long q; cin >> q; while (q--) solve(); } |
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI stream to Avalon-ST
*/
module axis2avst #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] axis_tdata,
input wire [KEEP_WIDTH-1:0] axis_tkeep,
input wire axis_tvalid,
output wire axis_tready,
input wire axis_tlast,
input wire axis_tuser,
input wire avst_ready,
output wire avst_valid,
output wire [DATA_WIDTH-1:0] avst_data,
output wire avst_startofpacket,
output wire avst_endofpacket,
output wire [EMPTY_WIDTH-1:0] avst_empty,
output wire avst_error
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
reg frame_reg = 1'b0;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign avst_data[n*BYTE_WIDTH +: BYTE_WIDTH] = axis_tdata[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign avst_data = axis_tdata;
end
endgenerate
reg [EMPTY_WIDTH-1:0] empty;
assign avst_empty = empty;
integer k;
always @* begin
empty = KEEP_WIDTH-1;
for (k = 0; k < KEEP_WIDTH; k = k + 1) begin
if (axis_tkeep[k]) begin
empty = KEEP_WIDTH-1-k;
end
end
end
assign avst_valid = axis_tvalid;
assign avst_startofpacket = axis_tvalid & !frame_reg;
assign avst_endofpacket = axis_tlast;
assign avst_error = axis_tuser;
assign axis_tready = avst_ready;
always @(posedge clk) begin
if (axis_tvalid && axis_tready) begin
frame_reg <= !axis_tlast;
end
if (rst) begin
frame_reg <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int M = 1e5 + 5; long long mod_exp(long long cur, long long power) { long long res = 1; while (power > 0) { if (power % 2 == 0) { cur = (cur * cur) % 1000000007; } else { res = (res * cur) % 1000000007; cur = (cur * cur) % 1000000007; } power /= 2; } return res; } int main() { ios_base::sync_with_stdio(false); int i, j, n, m; cin >> n >> m; long long dp1[N], dp0[N]; dp1[0] = dp0[0] = 1; dp1[1] = dp0[1] = 2; for (i = 2; i < N; i++) { dp1[i] = (dp0[i - 1] + dp0[i - 2]) % 1000000007; dp0[i] = (dp1[i - 1] + dp1[i - 2]) % 1000000007; } long long foo = (dp1[m - 1] + dp0[m - 1]) % 1000000007; foo = (foo - 2 + 1000000007) % 1000000007; foo = (foo + dp0[n - 1] + dp1[n - 1]) % 1000000007; cout << foo << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int co, key; } num[1010]; int seven; char str[1010 * 100]; int init; bool cmp(node x, node y) { return x.co < y.co; } int main() { scanf( %d , &init); scanf( %s , str); seven = 1; int cnt = 1; int length = strlen(str); int now = 0; int pre = -1; for (int i = 1; i <= 1000; i++) num[i].co = 1; while (now < length) { if (str[now] == - ) { seven = -1; now++; } else if (str[now] == * || str[now] == + ) now++; else if (str[now] == a ) { if (now - 2 > pre && str[now - 1] == + && str[now - 2] == + ) { pre = now; num[cnt].co *= seven; num[cnt].key = 0; cnt++; now++; } else { pre = now + 2; num[cnt].co *= seven; num[cnt].key = 1; cnt++; now += 3; } seven = 1; } else { int sum = 0; while (str[now] >= 0 && str[now] <= 9 ) { sum = sum * 10 + (str[now] - 0 ); now++; } num[cnt].co = sum; } } cnt--; sort(num + 1, num + 1 + cnt, cmp); int ans = 0; for (int i = 1; i <= cnt; i++) { if (!num[i].key) { init++; ans += (num[i].co * init); } else { ans += (num[i].co * init); init++; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 10; const int MOD = 1e9 + 7; bool mark[N]; vector<int> ps, corporator[N]; int primeMul[N], primeCnt[N], nthPower[N], b[N], n, k; int _sum(int, int); int _mul(int, int); int _pow(int, int); void _push(int&, int); int main() { cin >> n >> k; fill(primeMul, primeMul + k + 1, 1); for (int i = 1; i <= k; i++) { nthPower[i] = _pow(i, n); if (i > 1 && !mark[i]) { for (int j = i; j <= k; j += i) { mark[j] = true; primeMul[j] *= i; primeCnt[j]++; } } if (primeMul[i] == i) ps.push_back(i); } for (int i : ps) for (int j = i; j <= k; j += i) corporator[j].push_back(i); b[1] = nthPower[1]; int ans = b[1] ^ 1; for (int i = 2; i <= k; i++) { b[i] = b[i - 1]; for (int c : corporator[i]) { int v = _sum(MOD - nthPower[(i - 1) / c], nthPower[i / c]); _push(b[i], primeCnt[c] & 1 ? MOD - v : v); } _push(ans, b[i] ^ i); } cout << ans << endl; } int _sum(int a, int b) { return a + b - (a + b >= MOD ? MOD : 0); } int _mul(int a, int b) { return 1LL * a * b % MOD; } int _pow(int a, int b) { if (!b) return 1; int res = _pow(a, b >> 1); res = _mul(res, res); if (b & 1) res = _mul(res, a); return res; } void _push(int& a, int b) { a = _sum(a, b); } |
#include <bits/stdc++.h> using namespace std; long long n, x, k, lb, ub, ans = -1; void init() { long long l, r; scanf( %lld%lld%lld%lld , &n, &l, &r, &k); x = (r >= l ? r - l + 1 : r + n - l + 1) % n; } void solve() { for (long long i = k, j, r; i; i = j) { j = k / (k / i + 1); r = k / i; ub = min(2 * n, i); lb = max(n, j + 1); ub = min(ub, min((2 * n + k - 2 * x + 1) / (r + 1), (k - x) / r)); lb = max(lb, (k - 2 * x + r - 1) / r); if (ub >= lb) ans = max(ans, ub); } if (x <= k && k <= x * 2) ans = max(ans, n + min(k - x, x - 1) + n - x + 1); if (!x && k == n) ans = max(ans, n + 1); printf( %lld n , ~ans ? ans - n : ans); } int main() { init(); solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, c, l; cin >> a >> b >> c >> l; long long int Total = (l + 1) * (l + 2) * (l + 3) / 6; for (long long int la = 0; la <= l; la++) { long long int mini = min(a - b - c + la, l - la); if (mini < 0) continue; long long int wrong = (mini + 1) * (mini + 2) / 2; Total -= wrong; } for (long long int lb = 0; lb <= l; lb++) { long long int mini = min(b - a - c + lb, l - lb); if (mini < 0) continue; long long int wrong = (mini + 1) * (mini + 2) / 2; Total -= wrong; } for (long long int lc = 0; lc <= l; lc++) { long long int mini = min(c - b - a + lc, l - lc); if (mini < 0) continue; long long int wrong = (mini + 1) * (mini + 2) / 2; Total -= wrong; } cout << Total << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_4_V
`define SKY130_FD_SC_HD__O22AI_4_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22ai_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_4_V
|
#include <bits/stdc++.h> using namespace std; const int logsize = 18; int n, m, q, rt = 1, t, sc, vis[100005], dfn[100005], low[100005], sid[100005], sz[100005], dep[100005], pr[100005][logsize], w[100005], mod = 1e9 + 7; stack<int> s; vector<int> g[100005], ng[100005]; int inline read() { int res = 0; char c = getchar(); for (; !isdigit(c); c = getchar()) ; for (; isdigit(c); res *= 10, res += c ^ 48, c = getchar()) ; return res; } void tarjan(int u, int p) { dfn[u] = low[u] = ++t; vis[u] = 1; s.push(u); for (int v : g[u]) { if (v == p || vis[v] == 2) continue; if (!vis[v]) { tarjan(v, u); } low[u] = min(low[u], low[v]); } if (dfn[u] == low[u]) { ++sc; for (;;) { int v = s.top(); s.pop(); vis[v] = 2; sid[v] = sc; ++sz[sc]; if (u == v) break; } } } void dfs(int u, int p) { dep[u] = u == rt ? 0 : dep[p] + 1; w[u] = u == rt ? sz[u] > 1 : w[p] + (sz[u] > 1); pr[u][0] = p; for (int v : ng[u]) { if (v == p) continue; dfs(v, u); } } void inline init() { dfs(rt, -1); for (int i = 1; i <= logsize - 1; ++i) { for (int u = 1; u <= sc; ++u) { int p = pr[u][i - 1]; if (p == -1) { pr[u][i] = -1; } else { pr[u][i] = pr[p][i - 1]; } } } } int inline lca(int u, int v) { if (dep[u] > dep[v]) { swap(u, v); } for (int i = 0; i < logsize; ++i) { if ((dep[v] - dep[u]) >> i & 1) { v = pr[v][i]; } } if (u == v) return u; for (int i = logsize - 1; i >= 0; --i) { if (pr[u][i] != pr[v][i]) { u = pr[u][i]; v = pr[v][i]; } } return pr[u][0]; } int qpow(long long a, int p) { long long res = 1; while (p) { if (p & 1) { res *= a; res %= mod; } a *= a; a %= mod; p >>= 1; } return res % mod; } int main() { ios_base::sync_with_stdio(0); n = read(); m = read(); for (int i = 1; i <= m; ++i) { int u = read(), v = read(); g[u].push_back(v); g[v].push_back(u); } for (int u = 1; u <= n; ++u) { if (!vis[u]) { tarjan(u, -1); } } for (int u = 1; u <= n; ++u) { for (int v : g[u]) { int su = sid[u], sv = sid[v]; if (su == sv) continue; ng[su].push_back(sv); } } init(); q = read(); for (int i = 1; i <= q; ++i) { int u = read(), v = read(), su = sid[u], sv = sid[v], sp = lca(su, sv); int d = w[su] + w[sv] - w[sp] * 2 + (sz[sp] > 1); cout << qpow(2, d) << n ; } } |
#include <bits/stdc++.h> using namespace std; const int N = 100000 + 10; int n; int a[N], indexes[N], parent[N], rrank[N], ccount[N]; bool used[N]; int get_set(int v) { if (v == parent[v]) return v; return parent[v] = get_set(parent[v]); } void create_set(int v) { parent[v] = v; rrank[v] = 0; ccount[v] = 1; } void merge_sets(int v, int u) { v = get_set(v); u = get_set(u); if (v != u) { if (rrank[v] > rrank[u]) swap(v, u); parent[v] = u; if (rrank[v] == rrank[u]) rrank[u]++; ccount[u] += ccount[v]; } } bool comp(int i, int j) { return a[i] < a[j]; } int solve() { int maxSize = 0, maxSets, sets = 0; int res = 0, resSets = -1; for (int i = 0; i < n; i++) { bool isMerged = false; int ind = indexes[i]; used[ind] = true; sets++; if (ind > 0 && used[ind - 1]) { isMerged = true; merge_sets(ind - 1, ind); sets--; } if (ind < n - 1 && used[ind + 1]) { isMerged = true; merge_sets(ind + 1, ind); sets--; } int sst = get_set(ind); if (ccount[sst] > maxSize) { maxSize = ccount[sst]; maxSets = 1; } else if (ccount[sst] == maxSize) { maxSets++; } if (i < n - 1 && a[indexes[i]] == a[indexes[i + 1]]) { continue; } if (maxSets == sets && sets > resSets) { resSets = sets; res = a[ind] + 1; } } return res; } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; indexes[i] = i; create_set(i); used[i] = false; } sort(indexes, indexes + n, comp); cout << solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long num(string str) { long long out = 0; for (int i = 0; i < str.length(); i++) { out *= 26; out += str.at(i) - A + 1; } return out; } string pb26(long long n) { string reverse = ; while (n > 0) { int d = (n - 1) % 26 + 1; char c = d + A - 1; reverse.push_back(c); n -= d; n /= 26; } string out = ; for (int i = reverse.length() - 1; i > -1; i--) out.push_back(reverse.at(i)); return out; } int main() { long long N; cin >> N; for (int t = 0; t < N; t++) { string S; cin >> S; bool rc = S.at(0) == R ; if (rc) { int i = 0; while (i < S.length() && S.at(i) != C ) i++; rc = i < S.length() && i > 1; if (rc) { for (int j = 1; j < i && rc; j++) { char c = S.at(j); if (c < 0 || c > 9 ) rc = false; } if (rc) { long long row = stoll(S.substr(1, i - 1)), col = stoll(S.substr(i + 1)); cout << pb26(col) << row << n ; } } } if (!rc) { int i = 0; while (true) { char c = S.at(i); if (c >= 0 && c <= 9 ) break; i++; } string col = S.substr(0, i); long long row = stoll(S.substr(i)); cout << R << row << C << num(col) << n ; } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, m = 0, k = 0, arr[101], seg[100001][3]; long long sum = 0; cin >> n >> m >> k; for (int i = 0; i < m; i++) cin >> seg[i][0] >> seg[i][1] >> seg[i][2]; for (int i = 0; i < k; i++) cin >> arr[i]; for (int i = 0; i < k; i++) { for (int j = 0; j < m; j++) { if (arr[i] < seg[j][0] || arr[i] > seg[j][1]) continue; sum += (arr[i] - seg[j][0]) + seg[j][2]; } } cout << sum; return 0; } |
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