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//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Video_System_CPU_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:55:09 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_ila_0_0_stub.v
// Design : DemoInterconnect_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ila,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[7:0],probe2[0:0],probe3[7:0]" */;
input clk;
input [0:0]probe0;
input [7:0]probe1;
input [0:0]probe2;
input [7:0]probe3;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sePuede(int rango[], int x) { if (x % 2 == 1 && rango[0] == 1 && rango[x - 1] == 1) return true; return false; } int main() { int x = 0; int impar = 0; cin >> x; int rango[x]; for (int y = 0; y < x; y++) { cin >> rango[y]; rango[y] = rango[y] % 2; } if (sePuede(rango, x)) cout << YES << endl; else cout << NO << endl; } |
// file: DemoInterconnect_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// ____aclk____72.000______0.000______50.0______499.161____686.541
// ____uart____12.000______0.000______50.0______680.336____686.541
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________12____________0.010
`timescale 1ps/1ps
module DemoInterconnect_clk_wiz_0_0_clk_wiz
(// Clock in ports
// Clock out ports
output aclk,
output uart,
// Status and control signals
input reset,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_DemoInterconnect_clk_wiz_0_0;
wire clk_in2_DemoInterconnect_clk_wiz_0_0;
IBUF clkin1_ibufg
(.O (clk_in1_DemoInterconnect_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire aclk_DemoInterconnect_clk_wiz_0_0;
wire uart_DemoInterconnect_clk_wiz_0_0;
wire clk_out3_DemoInterconnect_clk_wiz_0_0;
wire clk_out4_DemoInterconnect_clk_wiz_0_0;
wire clk_out5_DemoInterconnect_clk_wiz_0_0;
wire clk_out6_DemoInterconnect_clk_wiz_0_0;
wire clk_out7_DemoInterconnect_clk_wiz_0_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_DemoInterconnect_clk_wiz_0_0;
wire clkfbout_buf_DemoInterconnect_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
(* KEEP = "TRUE" *)
(* ASYNC_REG = "TRUE" *)
reg [7 :0] seq_reg1 = 0;
(* KEEP = "TRUE" *)
(* ASYNC_REG = "TRUE" *)
reg [7 :0] seq_reg2 = 0;
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (63.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (63),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (83.333))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_DemoInterconnect_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (aclk_DemoInterconnect_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (uart_DemoInterconnect_clk_wiz_0_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_DemoInterconnect_clk_wiz_0_0),
.CLKIN1 (clk_in1_DemoInterconnect_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_DemoInterconnect_clk_wiz_0_0),
.I (clkfbout_DemoInterconnect_clk_wiz_0_0));
BUFGCE clkout1_buf
(.O (aclk),
.CE (seq_reg1[7]),
.I (aclk_DemoInterconnect_clk_wiz_0_0));
BUFH clkout1_buf_en
(.O (aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.I (aclk_DemoInterconnect_clk_wiz_0_0));
always @(posedge aclk_DemoInterconnect_clk_wiz_0_0_en_clk or posedge reset_high) begin
if(reset_high == 1'b1) begin
seq_reg1 <= 8'h00;
end
else begin
seq_reg1 <= {seq_reg1[6:0],locked_int};
end
end
BUFGCE clkout2_buf
(.O (uart),
.CE (seq_reg2[7]),
.I (uart_DemoInterconnect_clk_wiz_0_0));
BUFH clkout2_buf_en
(.O (uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.I (uart_DemoInterconnect_clk_wiz_0_0));
always @(posedge uart_DemoInterconnect_clk_wiz_0_0_en_clk or posedge reset_high) begin
if(reset_high == 1'b1) begin
seq_reg2 <= 8'h00;
end
else begin
seq_reg2 <= {seq_reg2[6:0],locked_int};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; cin.get(); string s; getline(cin, s); vector<int> pref(n); for (int i = 0; i < n; ++i) { if (i != 0) pref[i] = pref[i - 1]; pref[i] += s[i] == ( ? +1 : -1; } if (pref[n - 1] != 0) { cout << 0 n1 1 n ; return 0; } int min_pos = min_element(pref.begin(), pref.end()) - pref.begin() + 1; if (min_pos == n) min_pos = 0; rotate(s.begin(), s.begin() + min_pos, s.end()); for (int i = 0; i < n; ++i) { pref[i] = 0; if (i != 0) pref[i] = pref[i - 1]; pref[i] += s[i] == ( ? +1 : -1; assert(pref[i] >= 0); } vector<int> merged; vector<vector<int>> pos(2); vector<vector<int>> cnt(n, vector<int>(3)); pos[0].emplace_back(-1); merged.emplace_back(-1); for (int i = 0; i < n; ++i) { if (i != 0) cnt[i] = cnt[i - 1]; if (pref[i] < 3) { cnt[i][pref[i]] += 1; if (pref[i] < 2) { merged.emplace_back(i); pos[pref[i]].emplace_back(i); } } } tuple<int, int, int> ans((int)pos[0].size() - 1, 0, 0); for (int i = 0; i + 1 < (int)pos[0].size(); ++i) { int l = pos[0][i], r = pos[0][i + 1]; int cnt_1 = cnt[r][1] - (l >= 0 ? cnt[l][1] : 0); ans = max(ans, make_tuple(cnt_1, l + 1, r)); } for (int i = 0; i + 1 < (int)merged.size(); ++i) { int l = merged[i], r = merged[i + 1]; if (s[l + 1] == s[r]) continue; int cnt_2 = cnt[r][2] - (l >= 0 ? cnt[l][2] : 0); ans = max(ans, make_tuple(cnt_2 + (int)pos[0].size() - 1, l + 1, r)); } int res, l, r; tie(res, l, r) = ans; (l += min_pos) %= n; (r += min_pos) %= n; cout << res << endl; cout << 1 + l << << 1 + r << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_1_V
`define SKY130_FD_SC_HS__FAHCIN_1_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog wrapper for fahcin with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fahcin.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
sky130_fd_sc_hs__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_2_V
`define SKY130_FD_SC_HDLL__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:45:40 05/24/2015
// Design Name:
// Module Name: binary_to_BCD_fourteen_bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Implements the standard shift and add 3 algorithm
//
//////////////////////////////////////////////////////////////////////////////////
module binary_to_BCD_fourteen_bit(
input [13:0] in,
output [3:0] ones,
output [3:0] tens,
output [3:0] hundreds,
output [3:0] thousands
);
wire [3:0] c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25;
wire [3:0] d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,d20,d21,d22,d23,d24,d25;
assign d1 = {1'b0,in[13:11]};
assign d2 = {c1[2:0],in[10]};
assign d3 = {c2[2:0],in[9]};
assign d4 = {1'b0,c1[3],c2[3],c3[3]};
assign d5 = {c3[2:0],in[8]};
assign d6 = {c4[2:0],c5[3]};
assign d7 = {c5[2:0],in[7]};
assign d8 = {c6[2:0],c7[3]};
assign d9 = {c7[2:0],in[6]};
assign d10 = {1'b0,c4[3],c6[3],c8[3]};
assign d11 = {c8[2:0],c9[3]};
assign d12 = {c9[2:0],in[5]};
assign d13 = {c10[2:0],c11[3]};
assign d14 = {c11[2:0],c12[3]};
assign d15 = {c12[2:0],in[4]};
assign d16 = {c13[2:0],c14[3]};
assign d17 = {c14[2:0],c15[3]};
assign d18 = {c15[2:0],in[3]};
assign d19 = {c16[2:0],c17[3]};
assign d20 = {c17[2:0],c18[3]};
assign d21 = {c18[2:0],in[2]};
assign d22 = {c10[3],c13[3],c16[3],c19[3]};
assign d23 = {c19[2:0],c20[3]};
assign d24 = {c20[2:0],c21[3]};
assign d25 = {c21[2:0],in[1]};
add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);
add3 m8(d8,c8);
add3 m9(d9,c9);
add3 m10(d10,c10);
add3 m11(d11,c11);
add3 m12(d12,c12);
add3 m13(d13,c13);
add3 m14(d14,c14);
add3 m15(d15,c15);
add3 m16(d16,c16);
add3 m17(d17,c17);
add3 m18(d18,c18);
add3 m19(d19,c19);
add3 m20(d20,c20);
add3 m21(d21,c21);
add3 m22(d22,c22);
add3 m23(d23,c23);
add3 m24(d24,c24);
add3 m25(d25,c25);
assign ones = {c25[2:0],in[0]};
assign tens = {c24[2:0],c25[3]};
assign hundreds = {c23[2:0],c24[3]};
assign thousands ={c22[2:0],c23[3]};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`ifdef INLINE_A //verilator inline_module
`else //verilator no_inline_module
`endif
bmod bsub3 (.clk, .n(3));
bmod bsub2 (.clk, .n(2));
bmod bsub1 (.clk, .n(1));
bmod bsub0 (.clk, .n(0));
endmodule
module bmod
(input clk,
input [31:0] n);
`ifdef INLINE_B //verilator inline_module
`else //verilator no_inline_module
`endif
cmod csub (.clk, .n);
endmodule
module cmod
(input clk, input [31:0] n);
`ifdef INLINE_C //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] clocal;
always @ (posedge clk) clocal <= n;
dmod dsub (.clk, .n);
endmodule
module dmod (input clk, input [31:0] n);
`ifdef INLINE_D //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] dlocal;
always @ (posedge clk) dlocal <= n;
int cyc;
always @(posedge clk) begin
cyc <= cyc+1;
end
always @(posedge clk) begin
if (cyc>10) begin
`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif
if (csub.clocal !== n) $stop;
if (dlocal !== n) $stop;
end
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
// Local signals
wire Y not0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 11; const long long MOD = 1e18; long long a[N], b[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long x, y, l, r; cin >> x >> y >> l >> r; vector<long long> v; long long k = 1, kk = 1; for (int i = 0; i <= 60; i++) { a[i] = k; b[i] = kk; if (k != -1 && r / k >= x && k * x <= r) k *= x; else k = -1; if (kk != -1 && r / kk >= y && kk * y <= r) kk *= y; else kk = -1; } for (int i = 0; i <= 60; i++) for (int j = 0; j <= 60; j++) if (a[i] != -1 && b[j] != -1) { long long dd = a[i] + b[j]; if (dd >= l && dd <= r) v.push_back(dd); } v.push_back(l - 1); v.push_back(r + 1); sort(v.begin(), v.end()); long long ans = 0; for (int i = 1; i < v.size(); i++) ans = max(ans, v[i] - v[i - 1] - 1); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int max_of_num; int n, test_Q, point_num[100005], f_delp[100005][2]; vector<int> vc[100005]; bool flag = false; void search1(int u, int fa) { for (int i = 0; i < vc[u].size(); i++) { int v = vc[u][i]; if (v != fa) { if (point_num[v] == 1) { if (f_delp[u][0]) { flag = true; } f_delp[u][1] = true; } else { search1(v, u); if (f_delp[v][1] && f_delp[u][1]) { flag = true; } if (f_delp[v][0] && f_delp[u][0]) { flag = true; } f_delp[u][0] = f_delp[u][0] | f_delp[v][1]; f_delp[u][1] = f_delp[u][1] | f_delp[v][0]; } } } } void connect_add(int u = 0, int v = 0) { scanf( %d%d , &u, &v); point_num[u]++; point_num[v]++; vc[u].push_back(v); vc[v].push_back(u); } void search2(int u, int fa) { int qaq = 0; for (int i = 0; i < vc[u].size(); i++) { int v = vc[u][i]; if (v != fa) { if (point_num[v] == 1) qaq++; else search2(v, u); } } if (qaq) max_of_num = max_of_num - (qaq - 1); } int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) { connect_add(); } test_Q = 0; for (int i = 1; i <= n; ++i) { if (point_num[i] > 1) { test_Q = i; } } search1(test_Q, 0); if (flag) { printf( 3 ); } else { printf( 1 ); } max_of_num = n - 1; search2(test_Q, 0); printf( %d n , max_of_num); return 0; } |
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 29-10-2018
*/
module jt12_eg_step(
input attack,
input [ 4:0] base_rate,
input [ 4:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input [ 1:0] ks,
output cnt_lsb,
output reg step,
output reg [5:0] rate,
output reg sum_up
);
reg [6:0] pre_rate;
always @(*) begin : pre_rate_calc
if( base_rate == 5'd0 )
pre_rate = 7'd0;
else
case( ks )
2'd3: pre_rate = { base_rate, 1'b0 } + { 1'b0, keycode };
2'd2: pre_rate = { base_rate, 1'b0 } + { 2'b0, keycode[4:1] };
2'd1: pre_rate = { base_rate, 1'b0 } + { 3'b0, keycode[4:2] };
2'd0: pre_rate = { base_rate, 1'b0 } + { 4'b0, keycode[4:3] };
endcase
end
always @(*)
rate = pre_rate[6] ? 6'd63 : pre_rate[5:0];
reg [2:0] cnt;
reg [4:0] mux_sel;
always @(*) begin
mux_sel = attack ? (rate[5:2]+4'd1): {1'b0,rate[5:2]};
end // always @(*)
always @(*)
case( mux_sel )
5'h0: cnt = eg_cnt[14:12];
5'h1: cnt = eg_cnt[13:11];
5'h2: cnt = eg_cnt[12:10];
5'h3: cnt = eg_cnt[11: 9];
5'h4: cnt = eg_cnt[10: 8];
5'h5: cnt = eg_cnt[ 9: 7];
5'h6: cnt = eg_cnt[ 8: 6];
5'h7: cnt = eg_cnt[ 7: 5];
5'h8: cnt = eg_cnt[ 6: 4];
5'h9: cnt = eg_cnt[ 5: 3];
5'ha: cnt = eg_cnt[ 4: 2];
5'hb: cnt = eg_cnt[ 3: 1];
default: cnt = eg_cnt[ 2: 0];
endcase
////////////////////////////////
reg [7:0] step_idx;
always @(*) begin : rate_step
if( rate[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate[5:2]==4'hf && attack)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate[5:2]==4'd0 && !attack)
step_idx = 8'b11111110; // limit slowest decay rate
else
case( rate[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate of zero keeps the level still
step = rate[5:1]==5'd0 ? 1'b0 : step_idx[ cnt ];
end
assign cnt_lsb = cnt[0];
always @(*) begin
sum_up = cnt[0] != cnt_in;
end
endmodule // eg_step |
#include <bits/stdc++.h> using namespace std; signed main() { unsigned long long a, b; cin >> a >> b; if (a < b || (a % 2 != b % 2)) { cout << -1 << endl; return 0; } unsigned long long x = (a - b) / 2; unsigned long long y = x + b; cout << x << << y << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long mulMod(long long a, long long b, long long m = 1000000007) { long long x = 0, y = a % m; while (b > 0) { if (b % 2 == 1) x = (x + y) % m; y = (y * 2) % m; b /= 2; } return x % m; } long long expMod(long long b, long long e, long long m = 1000000007) { if (!e) return 1; long long q = expMod(b, e / 2, m); q = mulMod(q, q, m); return e % 2 ? mulMod(b, q, m) : q; } long long invFact[20], fact[20]; long long inverso(long long x) { return expMod(x, 1000000007 - 2); } void pre() { fact[0] = 1; for (int i = (1); i < (20 - 2); i++) fact[i] = (fact[i - 1] * i) % 1000000007; invFact[20 - 3] = inverso(fact[20 - 3]); for (int i = 20 - 3 - 1; i >= 0; i--) invFact[i] = (invFact[i + 1] * (i + 1)) % 1000000007; return; } long long comb(long long nn, long long k) { if (k < 0 || nn < k) return 0; return (fact[nn] * invFact[k] % 1000000007) * invFact[nn - k] % 1000000007; } int n; long long win[15][15]; long long get(int mask1, int mask2) { long long ret = 1; for (int i = (0); i < (n); i++) { if ((mask1 >> i) & 1) { for (int j = (0); j < (n); j++) { if ((mask2 >> j) & 1) { ret = ((ret * win[i][j] % 1000000007) + 1000000007) % 1000000007; assert(ret >= 0); } } } } return ret; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; vector<long long> a(n); for (int i = (0); i < (n); i++) cin >> a[i]; for (int i = (0); i < (n); i++) for (int j = (0); j < (n); j++) win[i][j] = (((a[i] * inverso(a[i] + a[j])) % 1000000007) + 1000000007) % 1000000007; vector<long long> proba(1 << n, 1); long long rta = 0; for (int mask = 1; mask < (1 << n); mask++) { for (int submask = mask & (mask - 1); submask; submask = (submask - 1) & mask) { proba[mask] -= proba[submask] * get(submask, mask ^ submask); proba[mask] = ((proba[mask] % 1000000007) + 1000000007) % 1000000007; assert(proba[mask] >= 0); } rta += ((__builtin_popcount(mask) * proba[mask]) % 1000000007 * get(mask, ((1 << n) - 1) ^ mask)) % 1000000007; rta = ((rta % 1000000007) + 1000000007) % 1000000007; } cout << rta << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; double A[100], B[100]; int main() { int n, V; cin >> n >> V; double S = 0.0; for (int i = 0; i < n; i++) { cin >> A[i]; S += A[i]; } for (int i = 0; i < n; i++) A[i] *= V / S; double MIN = 1.0; for (int i = 0; i < n; i++) { cin >> B[i]; MIN = min(MIN, B[i] / A[i]); } double result = 0.0; for (int i = 0; i < n; i++) result += A[i] * MIN; cout.precision(10); cout << result; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 14:24:11 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/system_affine_rotation_generator_0_0_stub.v
// Design : system_affine_rotation_generator_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "affine_rotation_generator,Vivado 2016.4" *)
module system_affine_rotation_generator_0_0(clk_25, reset, a00, a01, a10, a11)
/* synthesis syn_black_box black_box_pad_pin="clk_25,reset,a00[31:0],a01[31:0],a10[31:0],a11[31:0]" */;
input clk_25;
input reset;
output [31:0]a00;
output [31:0]a01;
output [31:0]a10;
output [31:0]a11;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int ans = INT_MAX; char W[100001]; scanf( %100000s , W); string s = W, t = Bulbasaur ; map<char, int> I, M; for (char ch : t) ++I[ch]; for (char ch : s) ++M[ch]; for (auto p : I) { ans = min(ans, M[p.first] / p.second); } printf( %d , ans); } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_flps.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// bw_io_dtl_flps
// _____________________________________________________________________________
//
module bw_io_dtl_flps (/*AUTOARG*/
// Outputs
q, so,
// Inputs
d, clk, si, se
);
output [2:0] q;
input [2:0] d;
output so;
input clk;
input si;
input se;
//wire so_0, net51;
bw_u1_soff_2x bsff_0 (
.q (q[0]),
.so (so_0),
.ck (clk),
.d (d[0]),
.se (se),
.sd (si)
);
bw_u1_soff_2x bsff_1 (
.q (q[1]),
.so (net51),
.ck (clk),
.d (d[1]),
.se (se),
.sd (so_0)
);
bw_u1_soff_2x I28 (
.q (q[2]),
.so (so),
.ck (clk),
.d (d[2]),
.se (se),
.sd (net51)
);
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HS__OR4BB_FUNCTIONAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4bb (
VPWR,
VGND,
X ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nand0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_FUNCTIONAL_V |
`include "hi_read_tx.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const long long N = 5100; long long n, s, t, x[N], a[N], b[N], c[N], d[N], w[N]; long long dp[N][N]; inline void print(long long a[]) { for (long long i = 1; i <= n; i++) printf( %lld , a[i]); printf( n ); } inline long long read() { long long f = 1, x = 0; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = x * 10 + s - 0 ; s = getchar(); } return x * f; } signed main() { n = read(); s = read(); t = read(); for (long long i = 1; i <= n; i++) x[i] = read(); for (long long i = 1; i <= n; i++) a[i] = read() + x[i]; for (long long i = 1; i <= n; i++) b[i] = read() - x[i]; for (long long i = 1; i <= n; i++) c[i] = read() + x[i]; for (long long i = 1; i <= n; i++) d[i] = read() - x[i]; long long x = 0, y = 0; for (long long i = 0; i <= n; i++) for (long long j = 0; j <= n; j++) dp[i][j] = 1e18; if (s == 1) dp[1][1] = d[1], x--; else if (t == 1) dp[1][1] = b[1], y--; else dp[1][1] = b[1] + d[1]; for (long long i = 2; i < n; i++) { if (i == s) { for (long long j = 1; j <= i; j++) { if (j > 1) dp[i][j] = min(dp[i][j], dp[i - 1][j - 1] + d[i]); dp[i][j] = min(dp[i][j], dp[i - 1][j] + c[i]); } x--; continue; } if (i == t) { for (long long j = 1; j <= i; j++) { if (j > 1) dp[i][j] = min(dp[i][j], dp[i - 1][j - 1] + b[i]); dp[i][j] = min(dp[i][j], dp[i - 1][j] + a[i]); } y--; continue; } for (long long j = 1 + (i > s && i > t); j <= i; j++) { long long in = j + x, out = j + y; if (j > 1 || out) dp[i][j] = min(dp[i][j], dp[i - 1][j] + a[i] + d[i]); if (j > 1 || in) dp[i][j] = min(dp[i][j], dp[i - 1][j] + c[i] + b[i]); dp[i][j + 1] = min(dp[i][j + 1], dp[i - 1][j] + b[i] + d[i]); if (j > 1) dp[i][j - 1] = min(dp[i][j - 1], dp[i - 1][j] + a[i] + c[i]); } } long long ans = 1e18; if (s == n) ans = min(ans, dp[n - 1][1] + c[n]); else if (t == n) ans = min(ans, dp[n - 1][1] + a[n]); else ans = min(ans, dp[n - 1][2] + a[n] + c[n]); printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; long long bigmod(long long a, long long p) { long long ret = 1; while (p > 0) { if ((p & 1)) ret = (ret * a) % 998244353LL; p >>= 1; a = (a * a) % 998244353LL; } return ret; } long long modinverse(long long a) { return bigmod(a, 998244353LL - 2); } long long n, fre[300009], eng[300009], mat[300009]; vector<int> graph[300009]; void dfs(int u, int par) { fre[u] = eng[u] = mat[u] = 0; long long mul = 1, mul2 = 1; for (int i = 0; i < graph[u].size(); i++) { int v = graph[u][i]; if (v == par) continue; dfs(v, u); mul *= (fre[v] + eng[v]); mul2 *= (fre[v] + 2 * eng[v]); mul %= 998244353LL; mul2 %= 998244353LL; } fre[u] = mul; mat[u] = mul2; for (int i = 0; i < graph[u].size(); i++) { int v = graph[u][i]; if (v == par) continue; eng[u] += (modinverse((fre[v] + 2 * eng[v]) % 998244353LL) * mat[v]) % 998244353LL; } eng[u] %= 998244353LL; eng[u] *= mul2; eng[u] %= 998244353LL; } int main() { scanf( %lld , &n); int u, v; for (int i = 1; i < n; i++) { scanf( %d %d , &u, &v); graph[u].push_back(v); graph[v].push_back(u); } dfs(1, -1); long long ans = (fre[1] + eng[1]) % 998244353LL; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using ll = long long; using ld = long double; using namespace std; void debugi(vector<int>& vec) { int n = (int)vec.size(); for (int i = 0; i < n; i++) { cout << vec[i] << ; } cout << endl; } void debugd(vector<long double>& vec) { int n = (int)vec.size(); for (int i = 0; i < n; i++) { cout << vec[i] << ; } cout << endl; } void debugl(vector<ll>& vec) { int n = (int)vec.size(); for (int i = 0; i < n; i++) { cout << vec[i] << ; } cout << endl; } void debugmap(map<int, int>& mp) { for (auto x : mp) { cout << x.first << << x.second << , ; } cout << endl; } void debugset(set<int>& st) { for (auto x : st) { cout << x << ; } cout << endl; } void debugparri(vector<pair<int, int>>& arr) { for (int i = 0; i < (int)arr.size(); i++) { cout << [ << arr[i].first << : << arr[i].second << ] << ; } cout << endl; } void debugpi(pair<int, int>& pi) { cout << pi.first << << pi.second << endl; } void debugq(queue<int> q) { while (!q.empty()) { cout << q.front() << ; q.pop(); } cout << endl; } bool check(int n, int i, int j) { if ((0 <= i & i < n) && (0 <= j & j < n)) { return true; } return false; } ll MOD = 1e9 + 7; ll powab(ll a, ll b, ll mod) { if (b == 0) { return 1; } ll z = powab(a, b / 2, mod); ll res = (z * z * 1LL) % mod; if (b & 1) { res = (res * 1LL * a) % mod; } return res; } ll modinv(ll a, ll mod) { ll ans = powab(a, mod - 2, mod); return ans; } ll gcd(ll a, ll b) { if (b == 0) { return a; } return gcd(b, a % b); } void upd(int k, int x, vector<ll>& tree, int n) { if (k == 0) { return; } while (k <= n) { tree[k] += x; k += (k & -k); } } ll sum(int k, vector<ll>& tree, int n) { ll s = 0; while (k >= 1) { s += tree[k]; k -= (k & -k); } return s; } void solve(int tt, int t) { int n, m, k, rn; cin >> n >> m >> k; rn = n; int lim = 5050; vector<int> dp(lim), lst(lim, -1); vector<int> arr; if (m == 1) { if (k != 0) { cout << NO << endl; return; } if (n % 2 != 0) { cout << NO << endl; return; } vector<vector<char>> grid(n, vector<char>(m)); int ct = 1; for (int i = 0; i < n; i++) { if (i % 2 == 0 && ct) { grid[i][0] = a ; grid[i + 1][0] = a ; ct ^= 1; } else if (i % 2 == 0 && !ct) { grid[i][0] = b ; grid[i + 1][0] = b ; ct ^= 1; } } cout << YES << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << grid[i][j]; } cout << endl; } return; } vector<vector<int>> grid(n, vector<int>(m, -1)); dp[0] = 1; if (n % 2 != 0) { if (k < m / 2) { cout << NO << endl; return; } k -= m / 2; int ct = 1; for (int i = 0; i < m; i += 2) { if (ct) { grid[n - 1][i] = 1; grid[n - 1][i + 1] = 1; ct ^= 1; } else { grid[n - 1][i] = 0; grid[n - 1][i + 1] = 0; ct ^= 1; } } n -= 1; } if (n % 2 == 0) { for (int i = 2; i <= n; i += 2) { arr.push_back(i); } } else { for (int i = 1; i <= n; i += 2) { arr.push_back(i); } } reverse(arr.begin(), arr.end()); queue<pair<int, int>> q; q.push({0, 0}); vector<int> vis(lim); vis[0] = 1; while (!q.empty()) { int cur = q.front().first, dis = q.front().second; q.pop(); for (auto x : arr) { if (x + cur < lim) { if (vis[x + cur] == 0) { vis[x + cur] = 1; q.push({x + cur, dis + 1}); lst[x + cur] = cur; dp[x + cur] = dis + 1; } } } } n = rn; if (vis[k] == 1 && dp[k] <= m / 2) { vector<int> nums; int cur = k; while (cur != 0) { int prev = lst[cur]; nums.push_back(cur - prev); cur = prev; } int z = nums.size(), idx = 0; vector<int> curcol(m); int cl = 2; for (int i = 0; i < m; i++) { if (i % 2 == 0) { curcol[i] = 2; } else curcol[i] = 3; } for (int i = 0; i < m; i += 2) { int use = 0; if (idx < z) { use = nums[idx]; idx += 1; } int col = i, col1 = i + 1; int color = 0, st = n - 1, curcol = 2; if (grid[n - 1][i] != -1) { color = grid[n - 1][0] ^ 1; st = n - 2; } if (i != 0 && st >= 0) { if (grid[st][i - 1] == 0) color = 1; else color = 0; } while (use > 0 && st >= 0) { grid[st][col] = color; grid[st][col1] = color; use -= 1; color ^= 1; st -= 1; } } for (int i = 0; i < m; i++) { int now = curcol[i]; for (int j = 0; j < n; j += 2) { if (grid[j][i] != -1) break; grid[j][i] = now; grid[j + 1][i] = now; if (now == 2) now = 3; else now = 2; } } cout << YES << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << char(97 + grid[i][j]); } cout << endl; } return; } cout << NO << endl; return; } int main(int argc, const char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; for (int tt = 0; tt < t; tt++) { solve(tt, t); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_1_V
`define SKY130_FD_SC_LS__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; vector<long long int> v(n, 0); priority_queue<pair<long long int, pair<long long int, long long int>>> pq; pq.push({n, {0, n - 1}}); long long int count = 0; while (!pq.empty()) { long long int l = -1 * pq.top().second.first; long long int r = pq.top().second.second; long long int length = pq.top().first; pq.pop(); if (l > r) { continue; } count++; long long int mid = (l + r) / 2; v[mid] = count; pq.push({mid - l + 1, {(-1 * l), mid - 1}}); pq.push({r - mid + 1, {-1 * (mid + 1), r}}); } for (auto it : v) { cout << it << ; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; signed main() { long long n; cin >> n; vector<long long> a(n); vector<long long> ruio(n + 1, 0); vector<long long> ruit(n + 1, 0); long long ro = 0; long long rt = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 1) { ro++; } else { rt++; } ruio[i + 1] = ro; ruit[i + 1] = rt; } long long ans = rt; for (long long i = 0; i < n; i++) { long long ltmp = 0; for (long long j = 0; j < i; j++) { ltmp = max(ltmp, ruio[j] + (ruit[i + 1] - ruit[j])); } long long rtmp = 0; for (long long j = i; j < n; j++) { rtmp = max(rtmp, (ruio[j + 1] - ruio[i]) + (ruit[n] - ruit[j])); } ans = max(ans, ltmp + rtmp); } cout << ans << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__MUX2I_FUNCTIONAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`include "../u_mux_2_1_inv/sky130_fd_sc_hs__u_mux_2_1_inv.v"
`celldefine
module sky130_fd_sc_hs__mux2i (
VPWR,
VGND,
Y ,
A0 ,
A1 ,
S
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A0 ;
input A1 ;
input S ;
// Local signals
wire u_mux_2_1_inv0_out_Y;
wire u_vpwr_vgnd0_out_Y ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1_inv u_mux_2_1_inv0 (u_mux_2_1_inv0_out_Y, A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y , u_mux_2_1_inv0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_BLACKBOX_V
`define SKY130_FD_SC_HD__DFBBN_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Load/Store unit ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Interface between CPU and DC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_lsu.v,v $
// Revision 1.5 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/11/30 18:59:47 simons
// *** empty log message ***
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_lsu(
// Clock and reset
clk, rst,
// Internal i/f
addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
// External i/f to DC
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Internal i/f
//
input [31:0] addrbase;
input [31:0] addrofs;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [dw-1:0] lsu_datain;
output [dw-1:0] lsu_dataout;
output lsu_stall;
output lsu_unstall;
input du_stall;
output except_align;
output except_dtlbmiss;
output except_dmmufault;
output except_dbuserr;
//
// External i/f to DC
//
output [31:0] dcpu_adr_o;
output dcpu_cycstb_o;
output dcpu_we_o;
output [3:0] dcpu_sel_o;
output [3:0] dcpu_tag_o;
output [31:0] dcpu_dat_o;
input [31:0] dcpu_dat_i;
input dcpu_ack_i;
input dcpu_rty_i;
input dcpu_err_i;
input [3:0] dcpu_tag_i;
//
// Internal wires/regs
//
reg [3:0] dcpu_sel_o;
//
// Internal I/F assignments
//
assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
assign lsu_unstall = dcpu_ack_i;
assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
| ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
//
// External I/F assignments
//
assign dcpu_adr_o = addrbase + addrofs;
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |lsu_op;
assign dcpu_we_o = lsu_op[3];
assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
always @(lsu_op or dcpu_adr_o)
casex({lsu_op, dcpu_adr_o[1:0]})
{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
default : dcpu_sel_o = 4'b0000;
endcase
//
// Instantiation of Memory-to-regfile aligner
//
or1200_mem2reg or1200_mem2reg(
.addr(dcpu_adr_o[1:0]),
.lsu_op(lsu_op),
.memdata(dcpu_dat_i),
.regdata(lsu_dataout)
);
//
// Instantiation of Regfile-to-memory aligner
//
or1200_reg2mem or1200_reg2mem(
.addr(dcpu_adr_o[1:0]),
.lsu_op(lsu_op),
.regdata(lsu_datain),
.memdata(dcpu_dat_o)
);
//
// Abstruct the signal we are interested in
//
//always @(posedge clk or posedge rst)
//$show_signal_value(or1200_lsu, lsu_stall, lsu_unstall);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// Author: Zhangfeifei ////
//// ////
//// Advance Test Technology Laboratory, ////
//// Institute of Computing Technology, ////
//// Chinese Academy of Sciences ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: or ////
//// Tel: +86-10-6256 5533 ext. 5673 ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/ucore ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2005-2006 Zhangfeifei ////
//// ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2005.12.3 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: pipeline stage IF of ucore processor ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "ucore_defines.v"
module pps_if
(
clk_i,rst_i,
alea_i,
EX_rdy_i,dmem_rdy_i,imem_rdy_i,
//branch and exception signals
bra_i,bra_addr_i,
exc_i,exc_confirm_i,exc_addr_i,
// Bus controler interface
CTRL_addr_o,CTRL_req_o,
// Synchronous outputs to ID stage
ID_addr_o,ID_it_ok_o,// Allow hardware interruptions
ID_bra_target_o // this instruction is the target of a brach
);
parameter Tp = `TP__;
parameter STA_IDDLE = 0;
input clk_i;
input rst_i;
input EX_rdy_i;
input imem_rdy_i;
input dmem_rdy_i;
input alea_i; // Unresolved detected : send nop in the pipeline
input bra_i; // Branch occoured
input [31:0] bra_addr_i;// Address of the branch
input exc_i; // Exception occured
input exc_confirm_i; //Exception vector send
input [31:0] exc_addr_i;// Exception vector
// Bus controler interface
output [31:0] CTRL_addr_o; // Address to read in memory
output CTRL_req_o;
// Synchronous outputs to ID stage
output reg [31:0] ID_addr_o; // Address from the read instruction
output reg ID_it_ok_o; // Allow hardware interruptions
output reg ID_bra_target_o;
wire [31:0] pc_inter; // Value of the pc output, needed for an internal reading
wire lock; // Specify the authorization of the pc evolution
reg bra_reged;
reg [31:0] bra_addr_reged;
always @(posedge clk_i or posedge rst_i)
begin
if(rst_i)
begin
bra_reged <= 0 ;
bra_addr_reged <= 32'bx;
end
else if(lock & ~bra_reged)//if the pipeline is locked this cycle,register the bra
begin
bra_reged <= bra_i;
bra_addr_reged <= bra_addr_i;
end
else if(~lock) begin
bra_reged <= 0 ;
bra_addr_reged <= 32'bx;
end
end
assign pc_inter = exc_confirm_i ? exc_addr_i :
lock ? ID_addr_o :
bra_i ? bra_addr_i :
bra_reged ? bra_addr_reged : ID_addr_o +4;
wire ready;
assign ready = EX_rdy_i & dmem_rdy_i & imem_rdy_i;
assign lock = exc_confirm_i ? 1'b0 :
~ready|exc_i ? 1'b1 :
bra_i | bra_reged ? 1'b0 :
alea_i ? 1'b1 : 1'b0;
// Connexion of the PC to the memory address bus
assign CTRL_addr_o = lock ? ID_addr_o : pc_inter;
assign CTRL_req_o = ~exc_i|exc_confirm_i;//imem_rdy_i &is_ds&~bra_i ? 0 :1;
reg first_cycle;
// Set the results
always @(posedge clk_i or posedge rst_i)
begin
if(rst_i)
begin
ID_addr_o <= #Tp `ADDR_INIT_;
first_cycle <= #Tp 1'b1;
ID_it_ok_o <= #Tp 1'b0;
ID_bra_target_o <= #Tp 1'b0;
end
else begin
first_cycle <= #Tp 1'b0;
ID_it_ok_o <= #Tp 1'b1;
if (~lock & ~first_cycle)
begin
ID_addr_o <= #Tp CTRL_addr_o;
ID_bra_target_o <= #Tp bra_i | bra_reged;
end
//else ID_it_ok_o <= #Tp 1'b0;
end
end
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___250.000______0.000______50.0_______93.990_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________200____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* TIMER A */
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check the timer clock input mux. */
/* */
/* Author(s): */
/* - Olivier Girard, */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
integer my_counter;
always @ (negedge mclk)
my_counter <= my_counter+1;
wire [15:0] tar = timerA_0.tar;
// Generate TACLK as MCLK/3
integer taclk_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) taclk_cnt <= 0;
else if (taclk_cnt==2) taclk_cnt <= 0;
else taclk_cnt <= taclk_cnt+1;
always @ (taclk_cnt)
if (taclk_cnt==2) taclk = 1'b1;
else taclk = 1'b0;
// Generate INCLK as MCLK/5
integer inclk_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) inclk_cnt <= 0;
else if (inclk_cnt==4) inclk_cnt <= 0;
else inclk_cnt <= inclk_cnt+1;
always @ (inclk_cnt)
if (inclk_cnt==4) inclk = 1'b1;
else inclk = 1'b0;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
`ifdef ASIC_CLOCKING
tb_skip_finish("| (this test is not supported in ASIC mode) |");
`else
// TIMER A TEST: INPUT MUX - TACLK
//--------------------------------------------------------
// @(r15 === 16'h0000);
@(r15 === 16'h0001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h0032) tb_error("====== TIMER A TEST: INPUT MUX - TACLK =====");
// TIMER A TEST: INPUT MUX - ACLK
//--------------------------------------------------------
@(r15 === 16'h1000);
@(r15 === 16'h1001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h0005) tb_error("====== TIMER A TEST: INPUT MUX - ACLK =====");
// TIMER A TEST: INPUT MUX - SMCLK
//--------------------------------------------------------
@(r15 === 16'h2000);
@(r15 === 16'h2001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h0013) tb_error("====== TIMER A TEST: INPUT MUX - SMCLK =====");
// TIMER A TEST: INPUT MUX - INCLK
//--------------------------------------------------------
@(r15 === 16'h3000);
@(r15 === 16'h3001);
@(tar === 1);
my_counter = 0;
repeat(300) @(posedge mclk);
if (tar !== 16'h001E) tb_error("====== TIMER A TEST: INPUT MUX - INCLK =====");
`endif
stimulus_done = 1;
end
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const unsigned long long base = 2333; const int maxn = 1e2 + 55; const int maxm = 1e4 + 50; const int maxv = 1e6 + 5; const int mod = 51123987; long long Cal(string s, long long p) { long long len = s.size(); long long sum = 0; for (long long i = 0; i < len; i++) { sum = (sum * 10 + s[i] - 0 ) % p; } return sum; } long long phi(long long n) { long long res = n, m = n; for (long long i = 2; i <= sqrt(m); i++) { if (m % i == 0) res = res / i * (i - 1); while (m % i == 0) m /= i; } if (m > 1) res = res / m * (m - 1); return res; } long long Quick_pow(long long x, long long y, long long p) { long long ans = 1, res = x; while (y) { if (y & 1) ans = ans * res % p; res = res * res % p; y >>= 1; } return ans; } int main() { string b, n; long long c; cin >> b >> n >> c; long long ph = phi(c); long long bb = Cal(b, c); long long nn = Cal(n, ph); if (n.size() < 10) { long long z = 0; for (long long i = 0; i < n.size(); i++) z = (z * 10 + n[i] - 0 ); long long ans = ((bb - 1 + c) % c) * Quick_pow(bb, z - 1, c) % c; if (ans == 0) ans = c; printf( %lld n , ans); return 0; } nn = (nn - 1 + ph) % ph + ph; long long ans = ((bb - 1 + c) % c) * Quick_pow(bb, nn, c) % c; if (ans == 0) ans = c; printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int alpha[26] = {0}, dig[105] = {0}; long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } long long int lcm(long long int a, long long int b) { return ((a * b) / gcd(a, b)); } bool isPrime(int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } void getArr(int a[], int n) { for (int i = 0; i < n; i++) cin >> a[i]; } void putArr(int a[], int n) { for (int i = 0; i < n; i++) cout << a[i] << ; cout << n ; } void initAlpha(string s) { int n = s.size(); for (int i = 0; i < n; i++) alpha[s[i] - a ]++; } void initDigit(int a[], int n) { for (int i = 0; i < n; i++) dig[a[i]]++; } bool isPalindrome(string input) { if (input == string(input.rbegin(), input.rend())) return true; return false; } int numLen(int n) { int len = 0; while (n != 0) { n /= 10; len++; } return len; } void robot() { string s; char n[50]; cin >> s; int l = s.size(), k = 0; bool flag = false; for (int i = l - 1; i >= 0; i--) { if (s[i] == 0 && !flag) continue; else { n[k++] = s[i]; flag = true; } } n[k] = 0 ; if (isPalindrome(n)) cout << YES n ; else cout << NO n ; } int main() { robot(); } |
/******************************************************************************/
/* PCIe test module Ryohei Kobayashi 2015.07.12 */
/******************************************************************************/
`default_nettype none
/***** An SRL-based FIFO *****/
/******************************************************************************/
module SRL_FIFO #(parameter FIFO_SIZE = 4, // size in log scale, 4 for 16 entry
parameter FIFO_WIDTH = 64) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule
/******************************************************************************/
module USER_LOGIC #(parameter C_PCI_DATA_WIDTH = 128)
( input wire CLK,
input wire RST,
output wire CHNL_RX_CLK,
(* mark_debug = "true" *) input wire CHNL_RX,
(* mark_debug = "true" *) output wire CHNL_RX_ACK,
(* mark_debug = "true" *) input wire CHNL_RX_LAST,
(* mark_debug = "true" *) input wire [31:0] CHNL_RX_LEN,
(* mark_debug = "true" *) input wire [30:0] CHNL_RX_OFF,
(* mark_debug = "true" *) input wire [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
(* mark_debug = "true" *) input wire CHNL_RX_DATA_VALID,
(* mark_debug = "true" *) output wire CHNL_RX_DATA_REN,
output wire CHNL_TX_CLK,
(* mark_debug = "true" *) output wire CHNL_TX,
(* mark_debug = "true" *) input wire CHNL_TX_ACK,
(* mark_debug = "true" *) output wire CHNL_TX_LAST,
(* mark_debug = "true" *) output wire [31:0] CHNL_TX_LEN,
(* mark_debug = "true" *) output wire [30:0] CHNL_TX_OFF,
(* mark_debug = "true" *) output wire [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA,
(* mark_debug = "true" *) output wire CHNL_TX_DATA_VALID,
(* mark_debug = "true" *) input wire CHNL_TX_DATA_REN);
// reg [31:0] rLen;
// (* mark_debug = "true" *) reg [31:0] rCount;
// (* mark_debug = "true" *) reg [1:0] rState;
// reg [31:0] tLen;
// (* mark_debug = "true" *) reg [31:0] tCount;
// (* mark_debug = "true" *) reg [1:0] tState;
// wire [C_PCI_DATA_WIDTH-1:0] fifo_dot;
// (* mark_debug = "true" *) wire fifo_emp;
// (* mark_debug = "true" *) wire fifo_ful;
// (* mark_debug = "true" *) wire [4:0] fifo_cnt;
// SRL_FIFO #(4, C_PCI_DATA_WIDTH) fifo(CLK,
// RST,
// (CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID),
// (CHNL_TX_DATA_REN && CHNL_TX_DATA_VALID),
// CHNL_RX_DATA,
// fifo_dot,
// fifo_emp,
// fifo_ful,
// fifo_cnt);
// assign CHNL_RX_CLK = CLK;
// assign CHNL_RX_ACK = (rState == 2'd1);
// assign CHNL_RX_DATA_REN = (rState == 2'd1 && !fifo_ful);
// assign CHNL_TX_CLK = CLK;
// assign CHNL_TX = (tState == 2'd1);
// assign CHNL_TX_LAST = 1'd1;
// assign CHNL_TX_LEN = tLen; // in words
// assign CHNL_TX_OFF = 0;
// assign CHNL_TX_DATA = fifo_dot;
// assign CHNL_TX_DATA_VALID = (tState == 2'd1 && !fifo_emp);
// always @(posedge CLK) begin
// if (RST) begin
// rLen <= 0;
// rCount <= 0;
// rState <= 0;
// end else begin
// case (rState)
// 2'd0: begin // Wait for start of RX, save length
// if (CHNL_RX) begin
// rLen <= CHNL_RX_LEN;
// rCount <= 0;
// rState <= 2'd1;
// end
// end
// 2'd1: begin // Wait for last data in RX, save value
// if (CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID) rCount <= rCount + (C_PCI_DATA_WIDTH >> 5);
// if (rCount >= rLen) rState <= 2'd0;
// end
// endcase
// end
// end
// always @(posedge CLK) begin
// if (RST) begin
// tLen <= 0;
// tCount <= 0;
// tState <= 0;
// end else begin
// case (tState)
// 2'd0: begin // Prepare for TX
// if (rState == 2'd1) begin
// tLen <= rLen;
// tCount <= 0;
// tState <= 2'd1;
// end
// end
// 2'd1: begin // Start TX with save length and data value
// if (CHNL_TX_DATA_REN && CHNL_TX_DATA_VALID) tCount <= tCount + (C_PCI_DATA_WIDTH >> 5);
// if (tCount >= tLen) tState <= 2'd0;
// end
// endcase
// end
// end
reg [C_PCI_DATA_WIDTH-1:0] rData;
reg [31:0] rLen;
(* mark_debug = "true" *) reg [31:0] rCount;
(* mark_debug = "true" *) reg [1:0] rState;
assign CHNL_RX_CLK = CLK;
assign CHNL_RX_ACK = (rState == 2'd1);
assign CHNL_RX_DATA_REN = (rState == 2'd1);
assign CHNL_TX_CLK = CLK;
assign CHNL_TX = (rState == 2'd3);
assign CHNL_TX_LAST = 1'd1;
assign CHNL_TX_LEN = rLen; // in words
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = rData;
assign CHNL_TX_DATA_VALID = (rState == 2'd3);
always @(posedge CLK) begin
if (RST) begin
rLen <= 0;
rCount <= 0;
rState <= 0;
rData <= 0;
end else begin
case (rState)
2'd0: begin // Wait for start of RX, save length
if (CHNL_RX) begin
rLen <= CHNL_RX_LEN;
rCount <= 0;
rState <= 2'd1;
end
end
2'd1: begin // Wait for last data in RX, save value
if (CHNL_RX_DATA_VALID) begin
rData <= CHNL_RX_DATA;
rCount <= rCount + (C_PCI_DATA_WIDTH/32);
end
if (rCount >= rLen) rState <= 2'd2;
end
2'd2: begin // Prepare for TX
rCount <= (C_PCI_DATA_WIDTH/32);
rState <= 2'd3;
end
2'd3: begin // Start TX with save length and data value
if (CHNL_TX_DATA_REN & CHNL_TX_DATA_VALID) begin
rData <= {rCount+32'd4, rCount+32'd3, rCount+32'd2, rCount+32'd1};
rCount <= rCount + (C_PCI_DATA_WIDTH/32);
if (rCount >= rLen) rState <= 2'd0;
end
end
endcase
end
end
endmodule
`default_nettype wire
|
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*###########################################################################
# Function: Generates clocks for eLink module:
# CCLK_N/P - Epiphany Core Clock, Differential, must be connected
# directly to IO pins.
#
# lclk_p - Parallel data clock, at bit rate / 8
#
# lclk_s - Serial DDR data clock, at bit rate / 2
#
# lclk_out - DDR "Clock" clock, to generate LCLK output
# At bit rate / 2, 90deg shifted from lclk_s
#
# Inputs:
# ecfg_cclk_en - Enable the CCLK output
# ecfg_cclk_div - CCLK divider
# ecfg_cclk_pllcfg - PLL configuration (not implemented)
#
# Notes: Uses Xilinx macros throughout
#
############################################################################
*/
`timescale 1ns/1ps
module eclock (/*AUTOARG*/
// Outputs
CCLK_P, CCLK_N, lclk_s, lclk_out, lclk_p,
// Inputs
clkin, reset, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg
);
// Parameters must be set as follows:
// PFD input frequency = 1/CLKIN1_PERIOD / DIVCLK_DIVIDE (10-450MHz)
// VCO frequency = PFD input frequency * CLKFBOUT_MULT (800-1600MHz)
// Output frequency = VCO frequency / CLKOUTn_DIVIDE
parameter CLKIN_PERIOD = 10.000; // ns -> 100MHz
parameter CLKIN_DIVIDE = 1;
parameter VCO_MULT = 12; // VCO = 1200MHz
parameter CCLK_DIVIDE = 2; // CCLK = 600MHz (at /1 setting)
parameter LCLK_DIVIDE = 4; // LCLK = 300MHz (600MB/s eLink, 75MW/s parallel)
parameter FEATURE_CCLK_DIV = 1'b1;
parameter IOSTD_ELINK = "LVDS_25";
// input clock & reset
input clkin;
input reset;
// From configuration register
input ecfg_cclk_en; //cclk enable
input [3:0] ecfg_cclk_div; //cclk divider setting
input [3:0] ecfg_cclk_pllcfg; //pll configuration TODO: ??
output CCLK_P, CCLK_N;
output lclk_s;
output lclk_out;
output lclk_p;
// Wires
wire cclk_src;
wire cclk_base;
wire cclk_p_src;
wire cclk_p;
wire cclk;
wire lclk_s_src;
wire lclk_out_src;
wire lclk_p_src;
wire clkfb;
// PLL Primitive
PLLE2_BASE
#(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(VCO_MULT), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(CLKIN_PERIOD),// Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(CCLK_DIVIDE),
.CLKOUT1_DIVIDE(LCLK_DIVIDE),
.CLKOUT2_DIVIDE(LCLK_DIVIDE),
.CLKOUT3_DIVIDE(LCLK_DIVIDE * 4),
.CLKOUT4_DIVIDE(CCLK_DIVIDE * 4),
.CLKOUT5_DIVIDE(128),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(90.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(CLKIN_DIVIDE),// Master division value, (1-56)
.REF_JITTER1(0.01), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) eclk_pll
(
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(cclk_src), // 1-bit output: CLKOUT0
.CLKOUT1(lclk_s_src), // 1-bit output: CLKOUT1
.CLKOUT2(lclk_out_src), // 1-bit output: CLKOUT2
.CLKOUT3(lclk_p_src), // 1-bit output: CLKOUT3
.CLKOUT4(cclk_p_src), // 1-bit output: CLKOUT4
.CLKOUT5(), // 1-bit output: CLKOUT5
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(clkfb), // 1-bit output: Feedback clock
.LOCKED(), // 1-bit output: LOCK
.CLKIN1(clkin), // 1-bit input: Input clock
// Control Ports: 1-bit (each) inpu: PLL control ports
.PWRDWN(1'b0), // 1-bit input: Power-down
.RST(1'b0), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(clkfb) // 1-bit input: Feedback clock
);
// Output buffering
BUFG cclk_buf
(.O (cclk_base),
.I (cclk_src));
BUFG cclk_p_buf
(.O (cclk_p),
.I (cclk_p_src));
BUFG lclk_s_buf
(.O (lclk_s),
.I (lclk_s_src));
BUFG lclk_out_buf
(.O (lclk_out),
.I (lclk_out_src));
BUFG lclk_p_buf
(.O (lclk_p),
.I (lclk_p_src));
generate
if( FEATURE_CCLK_DIV ) begin : gen_cclk_div
// Create adjustable (but fast) CCLK
wire rxi_cclk_out;
reg [8:1] cclk_pattern;
reg [3:0] clk_div_sync;
reg enb_sync;
always @ (posedge cclk_p) begin // Might need x-clock TIG here
clk_div_sync <= ecfg_cclk_div;
enb_sync <= ecfg_cclk_en;
if(enb_sync)
case(clk_div_sync)
4'h0: cclk_pattern <= 8'd0; // Clock OFF
4'h7: cclk_pattern <= 8'b10101010; // Divide by 1
4'h6: cclk_pattern <= 8'b11001100; // Divide by 2
4'h5: cclk_pattern <= 8'b11110000; // Divide by 4
default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8
endcase
else
cclk_pattern <= 8'b00000000;
end // always @ (posedge lclk_p)
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_inst
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(cclk), // 1-bit output: Data path output
.SHIFTOUT1(), // SHIFTOUTn: 1-bit (each): Data output expansion
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(cclk_base), // 1-bit input: High speed clock
.CLKDIV(cclk_p), // 1-bit input: Divided clock
.D1(cclk_pattern[1]), // D1 - D8: Parallel data inputs (1-bit each)
.D2(cclk_pattern[2]),
.D3(cclk_pattern[3]),
.D4(cclk_pattern[4]),
.D5(cclk_pattern[5]),
.D6(cclk_pattern[6]),
.D7(cclk_pattern[7]),
.D8(cclk_pattern[8]),
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(reset), // 1-bit input: Reset
.SHIFTIN1(1'b0), // SHIFTINn: Data input expansion (1-bit each)
.SHIFTIN2(1'b0),
.T1(1'b0), // T1 - T4: Parallel 3-state inputs
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
end else begin : gen_fixed_cclk // Non-dividable CCLK
reg enb_sync;
always @ (posedge cclk_p)
enb_sync <= ecfg_cclk_en;
// The following does not result in timing failures,
// but doesn't seem glitch-safe
assign cclk = cclk_base & enb_sync;
end
endgenerate
// xilinx OBUFDS instantiation
//
OBUFDS
#(.IOSTANDARD (IOSTD_ELINK))
obufds_cclk_inst
(.O (CCLK_P),
.OB (CCLK_N),
.I (cclk));
endmodule // eclock
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_TB_V
`define SKY130_FD_SC_HDLL__EBUFN_TB_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__ebufn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_TB_V
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : okWireIn_sync
// Author : Caleb Fangmeier
// Description : This is a simple wrapper of the okWireIn that syncronizes
// the signals with another clock by means of a shallow fifo buffer.
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module okWireIn_sync (
input wire clk,
input wire okClk,
input wire [112:0] okHE,
input wire [7:0] ep_addr,
output reg [31:0] ep_dataout
);
wire [31:0] control_bus;
wire [31:0] q_buff;
wire rdempty;
reg rdreq;
always @( posedge clk ) begin
if ( rdreq ) begin
ep_dataout <= q_buff;
end
rdreq <= ~rdempty;
end
fifo32_shallow fifo32_shallow_inst (
.data ( control_bus ),
.rdclk ( clk ),
.rdreq ( rdreq ),
.wrclk ( okClk ),
.wrreq ( 1'b1 ),
.q ( q_buff ),
.rdempty ( rdempty ),
.wrfull ( )
);
okWireIn control_wires(
.okHE(okHE),
.ep_addr(ep_addr),
.ep_dataout(control_bus)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ax, ay, bx, by, cx, cy; void check(long long xx, long long yy) { if (cx == 0 && cy == 0) { if (xx == 0 && yy == 0) { cout << YES ; exit(0); } else return; } if ((cx * (yy)-cy * (xx)) % (cx * cx + cy * cy) != 0 || (cx * (xx) + cy * (yy)) % (cx * cx + cy * cy) != 0) return; cout << YES ; exit(0); } int main() { cin >> ax >> ay >> bx >> by >> cx >> cy; check(bx - ax, by - ay); check(bx - ay, by + ax); check(bx + ax, by + ay); check(bx + ay, by - ax); cout << NO ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR3B_PP_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool ask(int val) { cout << ? << val + 1 << endl; string resp; cin >> resp; return resp[0] == Y ? true : false; } void fix() { cout << R << endl; } int main() { int n, k; cin >> n >> k; vector<bool> check(n + 1, 0); int block = k % 2 ? 1 : k / 2; for (int blockno = 1; blockno < n / block; blockno += 1) { for (int j = 0; j < blockno && (blockno + j < n / block); j += 1) { for (int k = j; k < n / block; k += blockno) { for (int a = 0; a < block; a += 1) { if (ask(k * block + a)) { check[k * block + a + 1] = true; } } } fix(); } } int res = 0; for (int i = 1; i <= n; i += 1) { if (check[i] == 0) { res += 1; } } cout << ! << res << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:14:09 03/08/2014
// Design Name:
// Module Name: obc1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module obc1(
input clk,
input enable,
input [7:0] data_in,
output [7:0] data_out,
input [12:0] addr_in,
input reg_we_rising
);
reg [7:0] obc1_regs [7:0];
wire [6:0] oam_number = obc1_regs[6][6:0];
wire obc_bank = obc1_regs[5][0];
wire low_en = enable & ((addr_in & 13'h1a00) == 13'h1800);
wire high_en = enable & ((addr_in & 13'h1a00) == 13'h1a00);
wire reg_en = enable & ((addr_in & 13'h1ff8) == 13'h1ff0);
wire [2:0] obc_reg = addr_in[2:0];
wire oam_low_we = enable & (reg_we_rising) & (((addr_in & 13'h1ffc) == 13'h1ff0) | low_en);
wire oam_high_we = enable & (reg_we_rising) & (addr_in == 13'h1ff4);
wire snes_high_we = enable & (reg_we_rising) & high_en;
wire [9:0] oam_low_addr = (~reg_en) ? addr_in[9:0] : {~obc_bank, oam_number, addr_in[1:0]};
wire [7:0] oam_high_addr = (~reg_en) ? addr_in[5:0] : {~obc_bank, oam_number};
wire [7:0] low_douta;
wire [7:0] high_doutb;
obc_lower oam_low (
.clka(clk), // input clka
.wea(oam_low_we), // input [0 : 0] wea
.addra(oam_low_addr), // input [9 : 0] addra
.dina(data_in), // input [7 : 0] dina
.douta(low_douta) // output [7 : 0] douta
);
obc_upper oam_high (
.clka(clk), // input clka
.wea(oam_high_we), // input [0 : 0] wea
.addra(oam_high_addr), // input [7 : 0] addra
.dina(data_in[1:0]), // input [1 : 0] dina
.douta(douta), // unused
.clkb(clk), // input clkb
.web(snes_high_we), // input [0 : 0] web
.addrb(addr_in[5:0]), // input [5 : 0] addrb
.dinb(data_in),
.doutb(high_doutb) // output [7 : 0] doutb
);
assign data_out = reg_en ? obc1_regs[addr_in[2:0]]
: low_en ? low_douta
: high_en ? high_doutb
: 8'h77;
always @(posedge clk) begin
if(reg_en & reg_we_rising) begin
obc1_regs[obc_reg] <= data_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char inc(char &c) { char ret = c; if (c == z ) c = a ; else ++c; return ret; } int main() { int n; cin >> n; char t[4][n]; char c = a ; t[0][0] = t[1][0] = inc(c); for (int i = 1; i < n; ++i) { if (i % 2 == 0) { t[0][i] = t[0][i - 1] = inc(c); t[1][i] = t[1][i - 1] = inc(c); } else { t[2][i] = t[2][i - 1] = inc(c); t[3][i] = t[3][i - 1] = inc(c); } } if (n % 2 == 0) t[0][n - 1] = t[1][n - 1] = inc(c); else t[2][n - 1] = t[3][n - 1] = inc(c); for (int i = 0; i < 4; ++i) { for (int j = 0; j < n; ++j) cout << t[i][j]; cout << endl; } cout << endl; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000 ) using namespace std; int n; char s[2000][2001]; bool A[2000][2000]; int C[2][2000]; int Z[2][2000]; bool F(int x, int y) { return (x >= 0 && y >= 0 && x < n && y < n); } int main() { cin >> n; for (int(i) = (0); (i) < (n); ++(i)) { scanf( %s , s[i]); for (int(j) = (0); (j) < (n); ++(j)) if (s[i][j] == 1 ) A[i][j] = 1; } int res = 0; for (int(ii) = (n)-1; (ii) >= (1); --(ii)) { int i = ii, j = 0; while (F(i, j)) { int p = C[0][j] + C[1][i]; p %= 2; if (p != A[i][j]) { res++; C[0][j]++; C[1][i]++; } i++; j++; } } for (int(jj) = (n)-1; (jj) >= (1); --(jj)) { int j = jj, i = 0; while (F(i, j)) { int p = Z[0][j] + Z[1][i]; p %= 2; if (p != A[i][j]) { res++; Z[0][j]++; Z[1][i]++; } i++; j++; } } for (int(i) = (0); (i) < (n); ++(i)) { int p = C[0][i] + C[1][i] + Z[0][i] + Z[1][i]; p %= 2; if (p != A[i][i]) res++; } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; int o = 0, s = 0; for (int i = 0; i < n; i++) { cin >> a[i]; s = s + a[i]; if ((a[i] % 2) != 0) { o++; } } if ((s % 2) == 0) { cout << n - o; } else { cout << o; } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; const int MAXM = 1000005; const int MOD = 1000000007; const int MAMOD = 998244353; const int INF = 0x3f3f3f3f; const long long LLINF = 0x3f3f3f3f3f3f3f3f; const double PI = acos(-1.0); const double EPS = 1e-8; int a[1005], color[1005]; int pri[12] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31}; vector<int> v[12]; int main() { ios::sync_with_stdio(0); int t; cin >> t; while (t--) { int n; cin >> n; for (int j = 0; j < 11; ++j) v[j].clear(); for (int i = 1; i <= n; ++i) { cin >> a[i]; for (int j = 0; j < 11; ++j) { if (a[i] % pri[j] == 0) { color[i] = j; v[j].push_back(i); break; } } } int num[12], tot = 0; for (int i = 0; i < 11; ++i) { if (v[i].size()) num[i] = ++tot; } cout << tot << n ; for (int i = 1; i <= n; ++i) cout << num[color[i]] << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; typedef long double ld; const long long inf = 1100000000000000000; #define maxn 1000005 #define mod 1000000007 //998244353 #define int long long #define PB push_back #define eb emplace_back #define all(c) (c).begin(),(c).end() #define pii pair <int,int> #define vi vector<int> #define F first #define S second #define rep(i,a,b) for(int i=a;i<b;i++) #define rep1(i,a,b) for(int i=a;i<=b;i++) #define repd(i,a,b) for(int i=a;i>=b;--i) #define sz(x) (int)((x).size()) #define mem(a,x) memset(a,x,sizeof(a)) const long double PI=3.141592653589793238462643383279502884197169399375105820974944; void solve(){ int n, m; cin>>n>>m; int z = 720720; //lcm{1..16} int a[n][m]; rep(i, 0, n) rep(j, 0, m) cin>>a[i][j]; rep(i, 0, n){ rep(j, 0, m){ int k = z-pow(a[i][j], 4); if((i+j)%2) cout<<z<< ; else cout<<k<< ; }cout<< n ; } } signed main(){ ios_base::sync_with_stdio(false), cin.tie(nullptr); int T=1;// cin>>T; while(T--){ solve();cout<< n ; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:51:19 05/03/2016
// Design Name:
// Module Name: uart_tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_uart_tx7to7(
clk,
rst_n,
uart_ctl,
data_out,
data_sign,
data_valid,
rs_tx
);
input clk;
input rst_n;
input [2:0] uart_ctl;
input [6:0] data_out;
input data_sign;
output data_valid;
output rs_tx;
parameter bps9600 = 13'd5208, //baud is 9600bps
bps19200 = 13'd2603, //baud is 19200bps
bps38400 = 13'd1301, //baud is 38400bps
bps57600 = 13'd867, //baud is 57600bps
bps115200 = 13'd434, //baud is 115200bps
bps256000 = 13'd195; //baud is 115200bps
reg [12:0] cnt;
reg bps_sel;
reg [3:0] tran_cnt;
reg rs_tx;
reg sign_delay;
reg data_valid;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bps_sel <= 1'b0;
cnt <= 'h0;
end
else begin
case(uart_ctl)
3'h0: cnt <= (cnt == bps9600) ? 'h0 : cnt + 1'b1;
3'h1: cnt <= (cnt == bps19200) ? 'h0 : cnt + 1'b1;
3'h2: cnt <= (cnt == bps38400) ? 'h0 : cnt + 1'b1;
3'h3: cnt <= (cnt == bps57600) ? 'h0 : cnt + 1'b1;
3'h4: cnt <= (cnt == bps115200) ? 'h0 : cnt + 1'b1;
3'h5: cnt <= (cnt == bps256000) ? 'h0 : cnt + 1'b1;
default: cnt <= (cnt == bps9600) ? 'h0 : cnt + 1'b1;
endcase
bps_sel <= ~|cnt;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
sign_delay <= 1'b0;
data_valid <= 1'b0;
end
else begin
if(bps_sel) sign_delay <= 1'b0;
else if(data_sign) sign_delay <= 1'b1;
if(data_sign | sign_delay) data_valid <= 1'b0;
else if(tran_cnt== 8) data_valid <= 1'b1;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
tran_cnt <= 'h8;
end
else if (bps_sel)begin
if(tran_cnt != 8) tran_cnt <= tran_cnt + 1'b1;
else if (data_sign|sign_delay) tran_cnt <= 'h0;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
rs_tx <= 1'b1;
end
else if (bps_sel) begin
if(tran_cnt == 0) rs_tx <= 1'b0 ;
else if(tran_cnt == 8) rs_tx <= 1'b1;
else rs_tx <= data_out[tran_cnt - 1];
end
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fifo_8_to_32 #(
parameter DEPTH = 1024
) (
input wire CLK,
input wire RST,
input wire WRITE,
input wire READ,
input wire [7:0] DATA_IN,
output wire FULL,
output wire EMPTY,
output wire [31:0] DATA_OUT
);
wire FIFO_EMPTY_8;
wire FIFO_READ_8;
wire [7:0] FIFO_DATA_OUT_8;
gerneric_fifo #(
.DATA_SIZE(8),
.DEPTH(DEPTH * 4)
) fifo_8_i (
.clk(CLK),
.reset(RST),
.write(WRITE),
.read(FIFO_READ_8),
.data_in(DATA_IN),
.full(FULL),
.empty(FIFO_EMPTY_8),
.data_out(FIFO_DATA_OUT_8),
.size()
);
wire FIFO_FULL_32;
reg FIFO_WRITE_32;
wire [31:0] FIFO_DATA_IN_32;
reg [1:0] byte_cnt;
reg WAIT_FOR_FIFO_32;
always @(posedge CLK)
if(RST) begin
byte_cnt <= 0;
WAIT_FOR_FIFO_32 <= 1'b0;
end else if(~WAIT_FOR_FIFO_32 && ~FIFO_EMPTY_8 && &byte_cnt) begin
byte_cnt <= byte_cnt;
WAIT_FOR_FIFO_32 <= 1'b1;
end else if((~FIFO_EMPTY_8 && ~&byte_cnt) || (FIFO_WRITE_32 && &byte_cnt)) begin
byte_cnt <= byte_cnt + 1;
WAIT_FOR_FIFO_32 <= 1'b0;
end else begin
byte_cnt <= byte_cnt;
WAIT_FOR_FIFO_32 <= WAIT_FOR_FIFO_32;
end
wire READ_FIFO_8;
assign READ_FIFO_8 = (~FIFO_EMPTY_8 && ~WAIT_FOR_FIFO_32);
assign FIFO_READ_8 = READ_FIFO_8;
always @(posedge CLK)
if(RST) begin
FIFO_WRITE_32 <= 1'b0;
end else if(FIFO_WRITE_32) begin
FIFO_WRITE_32 <= 1'b0;
end else if(~FIFO_FULL_32 && &byte_cnt && WAIT_FOR_FIFO_32) begin
FIFO_WRITE_32 <= 1'b1;
end
reg [31:0] DATA_BUF;
always @(posedge CLK)
if(RST) begin
DATA_BUF <= 0;
end else if(READ_FIFO_8 && byte_cnt == 0) begin
DATA_BUF[7:0] <= FIFO_DATA_OUT_8;
end else if(READ_FIFO_8 && byte_cnt == 1) begin
DATA_BUF[15:8] <= FIFO_DATA_OUT_8;
end else if(READ_FIFO_8 && byte_cnt == 2) begin
DATA_BUF[23:16] <= FIFO_DATA_OUT_8;
end else if(READ_FIFO_8 && byte_cnt == 3) begin
DATA_BUF[31:24] <= FIFO_DATA_OUT_8;
end else begin
DATA_BUF <= DATA_BUF;
end
assign FIFO_DATA_IN_32 = DATA_BUF;
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(DEPTH)
) fifo_32_i (
.clk(CLK),
.reset(RST),
.write(FIFO_WRITE_32),
.read(READ),
.data_in(FIFO_DATA_IN_32),
.full(FIFO_FULL_32),
.empty(EMPTY),
.data_out(DATA_OUT),
.size()
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 00:51:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1));
endmodule
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(44.625000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(75.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
////////////////////////////////////////////////////////////////////////////////
// //
// Copyright 2006, 2007 Dennis van Weeren //
// //
// This file is part of Minimig //
// //
// Minimig is free software; you can redistribute it and/or modify //
// it under the terms of the GNU General Public License as published by //
// the Free Software Foundation; either version 3 of the License, or //
// (at your option) any later version. //
// //
// Minimig is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// Audio DMA engine //
// //
// 2 dma cycle types are defined: //
// - restart pointer (go back to the beginning of the sample): dmas active //
// - advance pointer to the next word of the sample: dmas inactive //
// //
// dma slot allocation: //
// channel #0 : $0E //
// channel #1 : $10 //
// channel #2 : $12 //
// channel #3 : $14 //
// //
////////////////////////////////////////////////////////////////////////////////
module agnus_audiodma
(
input wire clk, // bus clock
input wire clk7_en, // 7MHz clock enable
output wire dma, // true if audio dma engine uses it's cycle
input wire [ 4-1:0] audio_dmal, // audio dma data transfer request (from Paula)
input wire [ 4-1:0] audio_dmas, // audio dma location pointer restart (from Paula)
input wire [ 9-1:0] hpos, // horizontal beam counter
input wire [ 9-1:1] reg_address_in, // register address inputs
output reg [ 9-1:1] reg_address_out, // register address outputs
input wire [ 16-1:0] data_in, // bus data in
output wire [ 21-1:1] address_out // chip address out
);
// register names and adresses
parameter AUD0DAT_REG = 9'h0AA;
parameter AUD1DAT_REG = 9'h0BA;
parameter AUD2DAT_REG = 9'h0CA;
parameter AUD3DAT_REG = 9'h0DA;
// local signals
wire audlcena; // audio dma location pointer register address enable
wire [ 1: 0] audlcsel; // audio dma location pointer select
reg [ 20:16] audlch [3:0]; // audio dma location pointer bank (high word)
reg [ 15: 1] audlcl [3:0]; // audio dma location pointer bank (low word)
wire [ 20: 1] audlcout; // audio dma location pointer bank output
reg [ 20: 1] audpt [3:0]; // audio dma pointer bank
wire [ 20: 1] audptout; // audio dma pointer bank output
reg [ 1: 0] channel; // audio dma channel select
reg dmal;
reg dmas;
// location registers address enable
// active when any of the location registers is addressed
// $A0-$A3, $B0-$B3, $C0-$C3, $D0-$D3,
assign audlcena = ~reg_address_in[8] & reg_address_in[7] & (reg_address_in[6]^reg_address_in[5]) & ~reg_address_in[3] & ~reg_address_in[2];
// location register channel select
assign audlcsel = {~reg_address_in[5],reg_address_in[4]};
// audio location register bank
always @ (posedge clk) begin
if (clk7_en) begin
if (audlcena & ~reg_address_in[1]) // AUDxLCH
audlch[audlcsel] <= #1 data_in[4:0];
end
end
always @ (posedge clk) begin
if (clk7_en) begin
if (audlcena & reg_address_in[1]) // AUDxLCL
audlcl[audlcsel] <= #1 data_in[15:1];
end
end
// get audio location pointer
assign audlcout = {audlch[channel],audlcl[channel]};
// dma cycle allocation
always @ (*) begin
case (hpos)
9'b0001_0010_1 : dmal = audio_dmal[0]; //$0E
9'b0001_0100_1 : dmal = audio_dmal[1]; //$10
9'b0001_0110_1 : dmal = audio_dmal[2]; //$12
9'b0001_1000_1 : dmal = audio_dmal[3]; //$14
default : dmal = 0;
endcase
end
// dma cycle request
assign dma = dmal;
// channel dmas encoding
always @ (*) begin
case (hpos)
9'b0001_0010_1 : dmas = audio_dmas[0]; //$0E
9'b0001_0100_1 : dmas = audio_dmas[1]; //$10
9'b0001_0110_1 : dmas = audio_dmas[2]; //$12
9'b0001_1000_1 : dmas = audio_dmas[3]; //$14
default : dmas = 0;
endcase
end
// dma channel select
always @ (*) begin
case (hpos[3:2])
2'b01 : channel = 0; //$0E
2'b10 : channel = 1; //$10
2'b11 : channel = 2; //$12
2'b00 : channel = 3; //$14
endcase
end
// memory address output
assign address_out[20:1] = audptout[20:1];
// audio pointers register bank (implemented using distributed ram) and ALU
always @ (posedge clk) begin
if (clk7_en) begin
if (dmal)
audpt[channel] <= #1 dmas ? audlcout[20:1] : audptout[20:1] + 1'b1;
end
end
// audio pointer output
assign audptout[20:1] = audpt[channel];
// register address output multiplexer
always @ (*) begin
case (channel)
0 : reg_address_out[8:1] = AUD0DAT_REG[8:1];
1 : reg_address_out[8:1] = AUD1DAT_REG[8:1];
2 : reg_address_out[8:1] = AUD2DAT_REG[8:1];
3 : reg_address_out[8:1] = AUD3DAT_REG[8:1];
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_8_V
`define SKY130_FD_SC_LP__EINVN_8_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_8_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ffu_vis.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ffu_vis
// Description: This is the ffu VIS blk.
// It implements FALIGN, partitioned add and logicals.
*/
module sparc_ffu_vis(/*AUTOARG*/
// Outputs
vis_dp_rd_data,
// Inputs
dp_vis_rs1_data, dp_vis_rs2_data, ctl_vis_sel_add,
ctl_vis_sel_log, ctl_vis_sel_align, ctl_vis_add32,
ctl_vis_subtract, ctl_vis_cin, ctl_vis_align0, ctl_vis_align2,
ctl_vis_align4, ctl_vis_align6, ctl_vis_align_odd,
ctl_vis_log_sel_pass, ctl_vis_log_sel_nand, ctl_vis_log_sel_nor,
ctl_vis_log_sel_xor, ctl_vis_log_invert_rs1,
ctl_vis_log_invert_rs2, ctl_vis_log_constant,
ctl_vis_log_pass_const, ctl_vis_log_pass_rs1,
ctl_vis_log_pass_rs2
);
input [63:0] dp_vis_rs1_data;
input [63:0] dp_vis_rs2_data;
input ctl_vis_sel_add;
input ctl_vis_sel_log;
input ctl_vis_sel_align;
input ctl_vis_add32;
input ctl_vis_subtract;
input ctl_vis_cin;
input ctl_vis_align0;
input ctl_vis_align2;
input ctl_vis_align4;
input ctl_vis_align6;
input ctl_vis_align_odd;
input ctl_vis_log_sel_pass;
input ctl_vis_log_sel_nand;
input ctl_vis_log_sel_nor;
input ctl_vis_log_sel_xor;
input ctl_vis_log_invert_rs1;
input ctl_vis_log_invert_rs2;
input ctl_vis_log_constant;
input ctl_vis_log_pass_const;
input ctl_vis_log_pass_rs1;
input ctl_vis_log_pass_rs2;
output [63:0] vis_dp_rd_data;
wire [71:0] align_data1;
wire [63:0] align_rs1;
wire [63:8] align_rs2;
wire [63:0] add_out;
wire [63:0] log_out;
wire [63:0] align_out;
wire [63:0] add_in_rs1;
wire [63:0] add_in_rs2;
wire [63:0] logic_nor;
wire [63:0] logic_pass;
wire [63:0] logic_xor;
wire [63:0] logic_nand;
wire [63:0] logic_rs1;
wire [63:0] logic_rs2;
/////////////////////////////////////////////////////////////////
// Logic for partitioned addition.
//----------------------------------
// RS1 is normal RS1 data, RS2 is inverted by subtraction signal.
/////////////////////////////////////////////////////////////////
assign add_in_rs1[63:0] = dp_vis_rs1_data[63:0];
assign add_in_rs2[63:0] = dp_vis_rs2_data[63:0] ^ {64{ctl_vis_subtract}};
sparc_ffu_part_add32 part_adder_hi(.z(add_out[63:32]),
.add32(ctl_vis_add32),
.a(add_in_rs1[63:32]),
.b(add_in_rs2[63:32]),
.cin(ctl_vis_cin));
sparc_ffu_part_add32 part_adder_lo(.z(add_out[31:0]),
.add32(ctl_vis_add32),
.a(add_in_rs1[31:0]),
.b(add_in_rs2[31:0]),
.cin(ctl_vis_cin));
///////////////////////////////////////////////////////////////////////////
// Datapath for FALIGNDATA
//---------------------------------------------------------------
// FALIGNDATA concatenates rs1 and rs2 and shifts them by byte to create
// an 8 byte value. The first mux creates a 72 bit value and the
// 2nd mux picks 64 bits out of these for the output.
///////////////////////////////////////////////////////////////////////////
dp_buffer #(64) align_rs1_buf(.dout(align_rs1[63:0]), .in(dp_vis_rs1_data[63:0]));
dp_buffer #(56) align_rs2_buf(.dout(align_rs2[63:8]), .in(dp_vis_rs2_data[63:8]));
mux4ds #(72) falign_mux1(.dout(align_data1[71:0]),
.in0({align_rs1[63:0], align_rs2[63:56]}),
.in1({align_rs1[47:0], align_rs2[63:40]}),
.in2({align_rs1[31:0], align_rs2[63:24]}),
.in3({align_rs1[15:0], align_rs2[63:8]}),
.sel0(ctl_vis_align0),
.sel1(ctl_vis_align2),
.sel2(ctl_vis_align4),
.sel3(ctl_vis_align6));
dp_mux2es #(64) falign_mux2(.dout(align_out[63:0]),
.in0(align_data1[71:8]),
.in1(align_data1[63:0]),
.sel(ctl_vis_align_odd));
///////////////////////////////////////////////////////////////////////////
// Datapath for VIS logicals
//-----------------------------------------------------------------------
// VIS logicals perform 3 fundamental ops: NAND, NOR and XOR plus inverted
// versions of the inputs to create the other versions. These 3 outputs are
// muxed with a choice of 1, 0, rs1 or rs2.
///////////////////////////////////////////////////////////////////////////
// create inverted versions of data if desired
assign logic_rs1[63:0] = dp_vis_rs1_data[63:0] ^ {64{ctl_vis_log_invert_rs1}};
assign logic_rs2[63:0] = dp_vis_rs2_data[63:0] ^ {64{ctl_vis_log_invert_rs2}};
// 3 basic logical operations
assign logic_nor[63:0] = ~(logic_rs1[63:0] | logic_rs2[63:0]);
assign logic_nand[63:0] = ~(logic_rs1[63:0] & logic_rs2[63:0]);
assign logic_xor[63:0] = (logic_rs1[63:0] ^ logic_rs2[63:0]);
// mux for pass through data
mux3ds #(64) pass_mux(.dout(logic_pass[63:0]),
.in0({64{ctl_vis_log_constant}}),
.in1(logic_rs1[63:0]),
.in2(logic_rs2[63:0]),
.sel0(ctl_vis_log_pass_const),
.sel1(ctl_vis_log_pass_rs1),
.sel2(ctl_vis_log_pass_rs2));
// pick between logic outputs
mux4ds #(64) logic_mux(.dout(log_out[63:0]),
.in0(logic_nor[63:0]),
.in1(logic_nand[63:0]),
.in2(logic_xor[63:0]),
.in3(logic_pass[63:0]),
.sel0(ctl_vis_log_sel_nor),
.sel1(ctl_vis_log_sel_nand),
.sel2(ctl_vis_log_sel_xor),
.sel3(ctl_vis_log_sel_pass));
//////////////////////////////////////////////////////////
// output mux
//////////////////////////////////////////////////////////
mux3ds #(64) output_mux(.dout(vis_dp_rd_data[63:0]),
.in0(add_out[63:0]),
.in1(log_out[63:0]),
.in2(align_out[63:0]),
.sel0(ctl_vis_sel_add),
.sel1(ctl_vis_sel_log),
.sel2(ctl_vis_sel_align));
endmodule // sparc_ffu_vis
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100; char s[N]; int n, m, t[N]; int a[N * 4], b[N * 4], ab[N * 4], ba[N * 4], aba[N * 4], tag[N * 4]; void pushup(int now) { a[now] = max(a[(now << 1)], a[(now << 1 | 1)]); b[now] = min(b[(now << 1)], b[(now << 1 | 1)]); ab[now] = max(ab[(now << 1)], max(ab[(now << 1 | 1)], a[(now << 1)] - 2 * b[(now << 1 | 1)])); ba[now] = max(ba[(now << 1)], max(ba[(now << 1 | 1)], a[(now << 1 | 1)] - 2 * b[(now << 1)])); aba[now] = max(max(aba[(now << 1)], aba[(now << 1 | 1)]), max(ab[(now << 1)] + a[(now << 1 | 1)], ba[(now << 1 | 1)] + a[(now << 1)])); } void build(int now, int l, int r) { if (l + 1 == r) { a[now] = b[now] = t[l]; ab[now] = ba[now] = -t[l]; return; } int mid = (l + r) >> 1; build((now << 1), l, mid); build((now << 1 | 1), mid, r); pushup(now); } void down(int now, int val) { a[now] += val; b[now] += val; ab[now] -= val; ba[now] -= val; tag[now] += val; } void pushdown(int now) { down((now << 1), tag[now]); down((now << 1 | 1), tag[now]); tag[now] = 0; } void Insert(int now, int l, int r, int a, int b, int val) { if (a <= l && b >= r - 1) { down(now, val); return; } int mid = (l + r) >> 1; pushdown(now); if (a < mid) Insert((now << 1), l, mid, a, b, val); if (b >= mid) Insert((now << 1 | 1), mid, r, a, b, val); pushup(now); } int main() { int x, y, z; scanf( %d%d , &n, &m); n = n * 2 - 2; scanf( %s , s + 1); for (int i = 1; i <= n; ++i) { if (s[i] == ( ) t[i] = t[i - 1] + 1; else t[i] = t[i - 1] - 1; Insert(1, 1, n + 1, i, i, t[i]); } printf( %d n , aba[1]); for (int i = 0; i < m; ++i) { scanf( %d%d , &x, &y); if (x > y) swap(x, y); if (s[x] == ( ) z = -2; else z = 2; Insert(1, 1, n + 1, x, y - 1, z); swap(s[x], s[y]); printf( %d n , aba[1]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv5sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd2_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkdlyinv5sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkdlyinv5sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_4_V
`define SKY130_FD_SC_MS__A32OI_4_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFRTP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int p = 1000000007; int K; struct Ma { int g[31][31]; Ma() { memset(g, 0, sizeof(g)); } int* operator[](int x) { return g[x]; } Ma operator*(const Ma& b) const { Ma res; for (int i = 0; i <= K; i++) for (int k = 0; k <= K; k++) if (g[i][k]) for (int j = 0; j <= K; j++) res.g[i][j] = (res.g[i][j] + (long long)g[i][k] * b.g[k][j]) % p; return res; } void w() { for (int i = 0; i <= K; i++) g[i][i] = 1; } } A[105][30], res, pre[105][30], sub[105][30]; int num[105], tot; int main() { ios::sync_with_stdio(0); long long n; cin >> n >> K; while (n) num[tot++] = n % K, n /= K; for (int i = 0; i < K; i++) { for (int j = 0; j <= K; j++) A[0][i][j][j] = 1; for (int j = 0; j <= K; j++) A[0][i][j][i] = 1; } for (int i = 1; i <= tot; i++) { pre[i - 1][0] = A[i - 1][0]; for (int j = 1; j < K; j++) pre[i - 1][j] = pre[i - 1][j - 1] * A[i - 1][j]; sub[i - 1][K - 1] = A[i - 1][K - 1]; for (int j = K - 2; ~j; j--) sub[i - 1][j] = A[i - 1][j] * sub[i - 1][j + 1]; for (int j = 0; j < K; j++) { A[i][j].w(); A[i][j] = sub[i - 1][j]; if (j) A[i][j] = A[i][j] * pre[i - 1][j - 1]; } } res.g[K][K] = 1; for (int i = tot - 1, j = 0; ~i; i--) while (num[i]--) res = res * A[i][j], j = (j + 1) % K; int ans = 0; for (int i = 0; i <= K; i++) ans = (ans + res[K][i]) % p; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const double INF = 1e6; const double PI = atan2(0, -1); const int maxn = 550; inline int sgn(double x) { if (fabs(x) < EPS) return 0; return x < 0 ? -1 : 1; } inline int iseq(double x, double y) { return sgn(x - y) == 0; } struct Point { double x, y; Point(double x = 0, double y = 0) : x(x), y(y) {} double Angle() { return atan2(y, x); } }; inline Point operator+(Point A, Point B) { return Point(A.x + B.x, A.y + B.y); } inline Point operator-(Point A, Point B) { return Point(A.x - B.x, A.y - B.y); } inline Point operator*(double x, Point A) { return Point(x * A.x, x * A.y); } inline double operator*(Point A, Point B) { return A.x * B.x + A.y * B.y; } inline double operator%(Point A, Point B) { return A.x * B.y - A.y * B.x; } inline double Length2(Point A) { return A * A; } inline double Length(Point A) { return sqrt(A * A); } inline double Distance2(Point A, Point B) { return Length2(A - B); } inline double Distance(Point A, Point B) { return Length(A - B); } inline bool operator==(Point A, Point B) { return iseq(Distance(A, B), 0); } inline bool operator<(Point A, Point B) { return iseq(A.x, B.x) ? sgn(A.y - B.y) == -1 : sgn(A.x - B.x) == -1; } struct Line { Point P, Q; Line() {} Line(Point A, Point B) { P = A; Q = B; } Point Direction() { return Q - P; } }; inline int IsOnLine(Point P, Line l) { return sgn((l.P - P) % (l.Q - P)) == 0; } inline int IsOnSegment(Point P, Line l) { if (P == l.P || P == l.Q) return 1; return sgn((l.P - P) % (l.Q - P)) == 0 && sgn((l.P - P) * (l.Q - P)) <= 0; } inline bool IsSegmentOverlap(Line A, Line B) { if (iseq(A.Direction() % B.Direction(), 0)) return IsOnSegment(A.P, B) + IsOnSegment(A.Q, B) + IsOnSegment(B.P, A) + IsOnSegment(B.Q, A) >= 2; else return false; } inline bool IsSegmentIntersected(Line A, Line B) { if (IsOnSegment(A.P, B) || IsOnSegment(A.Q, B)) return true; if (IsOnSegment(B.P, A) || IsOnSegment(B.Q, A)) return true; int sgn1 = sgn((A.P - B.P) % B.Direction()), sgn2 = sgn((A.Q - B.P) % B.Direction()); int sgn3 = sgn((B.P - A.P) % A.Direction()), sgn4 = sgn((B.Q - A.P) % A.Direction()); return sgn1 * sgn2 == -1 && sgn3 * sgn4 == -1; } inline Point getLineIntersection(Line A, Line B) { Point v = A.Direction(), w = B.Direction(); Point u = B.P - A.P; return A.P + ((w % u) / (w % v)) * v; } int n; vector<Point> Rect[maxn]; double area1, area2; inline double getPolygonArea(const vector<Point> &A) { double ans = 0; for (auto j = 1u; j + 1 < A.size(); ++j) ans += (A[j] - A[0]) % (A[j] - A[0]) * 0.5; return ans; } inline bool IsInPolygon(Point P, const vector<Point> &A) { double area1 = getPolygonArea(A), area2 = 0.0; for (auto j = 0u; j + 1 < A.size(); ++j) area2 += (A[j] - P) % (A[j + 1] - P) * 0.5; return iseq(area1, area2); } inline bool IsPolygonOverlap(vector<Point> P[], int i, int j) { int sgn = 1; for (auto k = 0u; k < P[i].size(); ++k) if (!IsInPolygon(P[i][k], P[j])) { sgn = 0; break; } if (!sgn) return false; if (iseq(getPolygonArea(P[i]), getPolygonArea(P[j]))) return i < j; return true; } struct info { Point P; double ang; int delta; info() {} info(Point x, double y, int z) { P = x; ang = y; delta = z; } }; inline int operator<(const info &A, const info &B) { if (iseq(A.ang, B.ang)) return A.delta > B.delta; else return A.ang < B.ang; } inline double getPosition(Point P, Line l) { return ((P - l.P) * l.Direction()) / (l.Direction() * l.Direction()); return (P.x - l.P.x) / (l.Q.x - l.P.x); } double ans[maxn]; double getAreaUnion(vector<Point> P[], int n, double *ans) { for (int i = 1; i <= n; ++i) ans[i] = 0.0; static vector<pair<double, int>> PointList; double aans = 0; for (int i = 1; i <= n; ++i) for (auto j = 0u; j + 1 < P[i].size(); ++j) { Line A(P[i][j], P[i][j + 1]); PointList.clear(); for (int k = 1; k <= n; ++k) if (i != k) for (auto w = 0u; w + 1 < P[k].size(); ++w) { Line B(P[k][w], P[k][w + 1]); int p1 = sgn((B.P - A.P) % A.Direction()); int p2 = sgn((B.Q - A.P) % A.Direction()); if (!p1 && !p2) { if (i < k && sgn(A.Direction() * B.Direction()) == 1) { PointList.push_back( make_pair(min(1.0, max(getPosition(B.P, A), 0.0)), -1)); PointList.push_back( make_pair(min(1.0, max(getPosition(B.Q, A), 0.0)), 1)); } } else { Point tp = getLineIntersection(A, B); if (p1 >= 0 && p2 < 0) PointList.push_back( make_pair(min(1.0, max(getPosition(tp, A), 0.0)), -1)); if (p1 < 0 && p2 >= 0) PointList.push_back( make_pair(min(1.0, max(getPosition(tp, A), 0.0)), 1)); } } PointList.push_back(make_pair(0.0, 1)); PointList.push_back(make_pair(1.0, -1)); sort(PointList.begin(), PointList.end()); double S0 = A.P % A.Q * 0.5; double lst = 0; int now = 0; for (auto l = 0u, r = 0u; l < PointList.size();) { ans[now] += S0 * (PointList[l].first - lst); lst = PointList[l].first; for (r = l + 1; r < PointList.size() && iseq(PointList[r].first, lst); ++r) ; for (auto w = l; w < r; ++w) now += PointList[w].second; l = r; } } return ans[1]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= 4; ++j) { Point P; scanf( %lf%lf , &P.x, &P.y); Rect[i].push_back(P); } if (sgn((Rect[i][1] - Rect[i][0]) % (Rect[i][2] - Rect[i][0])) == -1) reverse(Rect[i].begin(), Rect[i].end()); area1 += (Rect[i][1] - Rect[i][0]) % (Rect[i][3] - Rect[i][0]); Rect[i].push_back(Rect[i][0]); } area2 = getAreaUnion(Rect, n, ans); printf( %.10lf n , area1 / area2); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A22OI_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22oi (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_BLACKBOX_V
|
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//`include "register.v"
module int_alu(out,a,b,instr,c); // 32 bit integer ALU
input[32:0]a,b; // 32 bit input registers
input[32:0]instr; // 32 bit instruction register
output[32:0]out; // 32 bit output register
reg[32:0]out;
inout register_file r; // register file
input c; // clock
function read; // read from register file
input[5:0] reg_addr;
begin
r.rsel=reg_addr;
read=r.out;
end
endfunction
function write; // write to register file
input[5:0] reg_addr;
input[32:0] data;
begin
r.wsel=reg_addr;
r.wen=1;
r.wdata=data;
write=1;
end
endfunction
always @(posedge c) begin // Only execute on clock signal
case(instr)
'b100000: write(out,(read(a)+read(b))); //add
'b100001: r[out] = r[a] + r[b]; //addu
'b001000: r[out] = r[a] + b; //addi
'b001001: r[out] = r[a] + b; //addiu
'b100100: r[out] = r[a] && r[b]; //and
'b001100: r[out] = r[a] && b; //andi
'b011010: r[out] = r[a] / r[b]; //div TODO: remainder
'b011011: r[out] = r[a] / r[b]; //divu TODO: remainder
'b011000: r[out] = r[a] * r[b]; //mult TODO: overflow
'b011001: r[out] = r[a] * r[b]; //multu TODO: overflow
'b100111: r[out] = !(r[a]|| r[b]); //nor
'b100101: r[out] = r[a] || r[b]; //or
'b001101: r[out] = r[a] || b; //ori
'b000000: r[out] = r[a] << b; //sll
'b000100: r[out] = r[a] << r[b]; //sllv
'b000011: r[out] = r[a] >> b; //sra
'b000111: r[out] = r[a] >> r[b]; //srav
'b000010: r[out] = r[a] >> b; //srl TODO: difference from sra?
'b000110: r[out] = r[a] >> r[b]; //srlv TODO: difference from srav?
'b100010: r[out] = r[a] - r[b]; //sub
'b100011: r[out] = r[a] - r[b]; //subu
'b100110: r[out] = r[a] ^ r[b]; //xor
'b001110: r[out] = r[a] ^ b; //xori TODO: ZE(b)
endcase
end
endmodule
|
module sdram_tb ();
reg clk, rst;
wire sdram_clk;
wire sdram_cle;
wire sdram_cs;
wire sdram_cas;
wire sdram_ras;
wire sdram_we;
wire sdram_dqm;
wire [1:0] sdram_ba;
wire [12:0] sdram_a;
wire [7:0] sdram_dq;
wire [24:0] addr;
wire rw;
wire [31:0] data_in, data_out;
wire busy;
wire in_valid, out_valid;
wire [7:0] leds;
sdram DUT (
.clk(clk),
.rst(rst),
.sdram_clk(sdram_clk),
.sdram_cle(sdram_cle),
.sdram_cs(sdram_cs),
.sdram_cas(sdram_cas),
.sdram_ras(sdram_ras),
.sdram_we(sdram_we),
.sdram_dqm(sdram_dqm),
.sdram_ba(sdram_ba),
.sdram_a(sdram_a),
.sdram_dq(sdram_dq),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid)
);
ram_test ram_test (
.clk(clk),
.rst(rst),
.addr(addr),
.rw(rw),
.data_in(data_in),
.data_out(data_out),
.busy(busy),
.in_valid(in_valid),
.out_valid(out_valid),
.leds(leds)
);
initial begin
clk = 1'b0;
rst = 1'b1;
repeat(4) #5 clk = ~clk;
rst = 1'b0;
forever #5 clk = ~clk; // generate a clock
end
always @* begin
end
initial begin
#300000
$finish();
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; if (a == b) { cout << a << n ; } else cout << 1 n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a[150], i, j, best, ans = 10000; cin >> n; for (i = 0; i < n; ++i) cin >> a[i]; for (i = 1; i < n - 1; ++i) { best = 0; for (j = 1; j < n; ++j) if (j != i) best = max(best, a[j] - a[j - 1]); else { best = max(best, a[j + 1] - a[j - 1]); ++j; } ans = min(ans, best); } cout << ans; return 0; } |
#include <bits/stdc++.h> typedef struct { double x; double y; double r; } circle; typedef struct { double x; double y; } pt; int x[3]; int y[3]; int r[3]; pt np(double x, double y) { pt q; q.x = x; q.y = y; return q; } double abs_d(double d1) { if (d1 > 0) return d1; return -d1; } bool flag2 = true; pt p; double dist(pt p1, pt p2) { return sqrt((p1.x - p2.x) * (p1.x - p2.x) + (p1.y - p2.y) * (p1.y - p2.y)); } void circumcenter(pt p1, pt p2, pt p3) { double K = abs_d(.5 * (p1.x * p2.y + p2.x * p3.y + p3.x * p1.y - p1.y * p2.x - p2.y * p3.x - p3.y * p1.x)); if (K < .01) { flag2 = false; return; } double a = dist(p1, p2); double b = dist(p1, p3); double c = dist(p2, p3); double R = a * b * c / 4 / K; double d = sqrt(R * R - (a / 2) * (a / 2)); double nx = (p1.x + p2.x) / 2; double ny = (p1.y + p2.y) / 2; double mx = p1.y - p2.y; double my = p2.x - p1.x; double len = sqrt(mx * mx + my * my); mx /= len; my /= len; p.x = nx + d * mx; p.y = ny + d * my; if (abs_d(dist(p, p3) - R) > .001) { p.x = nx - d * mx; p.y = ny - d * my; } } bool flag = true; pt pos1; pt pos2; void intersection(circle c1, circle c2) { pt p; p.x = -1e9; p.y = -1e9; double d = sqrt((c1.x - c2.x) * (c1.x - c2.x) + (c1.y - c2.y) * (c1.y - c2.y)); if (d > c1.r + c2.r) flag = false; if (abs_d(c1.r - c2.r) > d) flag = false; if (flag == false) return; double a = d; double b = c1.r; double c = c2.r; double s = (a + b + c) / 2; double K = sqrt(s * (s - a) * (s - b) * (s - c)); double h = 2 * K / a; double d_par = sqrt(b * b - h * h); if (b * b + d * d < c * c) d_par = -d_par; double nx = c1.x + (c2.x - c1.x) * d_par / d; double ny = c1.y + (c2.y - c1.y) * d_par / d; double oppx = c2.y - c1.y; double oppy = c1.x - c2.x; double len = sqrt(oppx * oppx + oppy * oppy); oppx /= len; oppy /= len; pos1.x = nx + h * oppx; pos1.y = ny + h * oppy; pos2.x = nx - h * oppx; pos2.y = ny - h * oppy; } int main() { for (int i = 0; i < 3; i++) { scanf( %d %d %d , &x[i], &y[i], &r[i]); } pt p1 = np(x[0], y[0]); pt p2 = np(x[1], y[1]); pt p3 = np(x[2], y[2]); if (r[0] == r[1] && r[1] == r[2]) { circumcenter(p1, p2, p3); if (flag2) { printf( %.5f %.5f , p.x, p.y); } } else { circle c1, c2, c3; if (r[0] != r[1]) { double x1 = (r[1] * p1.x + r[0] * p2.x) / (r[1] + r[0]); double y1 = (r[1] * p1.y + r[0] * p2.y) / (r[1] + r[0]); double x2 = (r[1] * p1.x - r[0] * p2.x) / (r[1] - r[0]); double y2 = (r[1] * p1.y - r[0] * p2.y) / (r[1] - r[0]); c1.x = (x1 + x2) / 2; c1.y = (y1 + y2) / 2; c1.r = sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)) / 2; } if (r[0] != r[2]) { double x1 = (r[2] * p1.x + r[0] * p3.x) / (r[2] + r[0]); double y1 = (r[2] * p1.y + r[0] * p3.y) / (r[2] + r[0]); double x2 = (r[2] * p1.x - r[0] * p3.x) / (r[2] - r[0]); double y2 = (r[2] * p1.y - r[0] * p3.y) / (r[2] - r[0]); c2.x = (x1 + x2) / 2; c2.y = (y1 + y2) / 2; c2.r = sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)) / 2; } if (r[1] != r[2]) { double x1 = (r[2] * p2.x + r[1] * p3.x) / (r[2] + r[1]); double y1 = (r[2] * p2.y + r[1] * p3.y) / (r[2] + r[1]); double x2 = (r[2] * p2.x - r[1] * p3.x) / (r[2] - r[1]); double y2 = (r[2] * p2.y - r[1] * p3.y) / (r[2] - r[1]); c3.x = (x1 + x2) / 2; c3.y = (y1 + y2) / 2; c3.r = sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)) / 2; } if (r[0] == r[1]) { intersection(c2, c3); } else if (r[0] == r[2]) { intersection(c1, c3); } else { intersection(c1, c2); } if (flag) { if (dist(pos1, p1) > dist(pos2, p1)) { printf( %.5f %.5f , pos2.x, pos2.y); } else { printf( %.5f %.5f , pos1.x, pos1.y); } } } fflush(stdin); getchar(); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 5; int main() { int x1, y1, x2, y2; while (~scanf( %d%d%d%d , &x1, &y1, &x2, &y2)) { long long x = x2 - x1 + 1; long long y = y2 - y1 + 2; long long s = x * y / 2 - x / 2; printf( %lld n , s); } } |
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> void chkmin(T1 &x, T2 y) { if (x > y) x = y; } template <typename T1, typename T2> void chkmax(T1 &x, T2 y) { if (x < y) x = y; } inline void debug(int x) { fprintf(stderr, ycx has aked ioi %d times n , x); } namespace fastio { char rbuf[1 << 23], *p1 = rbuf, *p2 = rbuf, wbuf[1 << 23], *p3 = wbuf; inline char getc() { return p1 == p2 && (p2 = (p1 = rbuf) + fread(rbuf, 1, 1 << 23, stdin), p1 == p2) ? -1 : *p1++; } inline void putc(char x) { (*p3++ = x); } template <typename T> void read(T &x) { x = 0; char c = getchar(); T neg = 0; while (!isdigit(c)) neg |= !(c ^ - ), c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); if (neg) x = (~x) + 1; } template <typename T> void recursive_print(T x) { if (!x) return; recursive_print(x / 10); putc(x % 10 ^ 48); } template <typename T> void print(T x) { if (!x) putc( 0 ); if (x < 0) putc( - ), x = ~x + 1; recursive_print(x); } template <typename T> void print(T x, char c) { if (!x) putc( 0 ); if (x < 0) putc( - ), x = ~x + 1; recursive_print(x); putc(c); } void print_final() { fwrite(wbuf, 1, p3 - wbuf, stdout); } } // namespace fastio const int MAXV = 30; const int MAXE = 300 * 2; const int INF = 0x3f3f3f3f; int n, m, p[8], q[8], cnt[8]; int S = 29, T = 30, hd[MAXV + 5], to[MAXE + 5], nxt[MAXE + 5], cap[MAXE + 5], ec = 1; void init() { memset(hd, 0, sizeof(hd)); ec = 1; } void adde(int u, int v, int f) { to[++ec] = v; cap[ec] = f; nxt[ec] = hd[u]; hd[u] = ec; to[++ec] = u; cap[ec] = 0; nxt[ec] = hd[v]; hd[v] = ec; } int dep[MAXV + 5], now[MAXV + 5]; bool getdep() { memset(dep, -1, sizeof(dep)); dep[S] = 0; queue<int> q; q.push(S); now[S] = hd[S]; while (!q.empty()) { int x = q.front(); q.pop(); for (int e = hd[x]; e; e = nxt[e]) { int y = to[e], z = cap[e]; if (!~dep[y] && z) { dep[y] = dep[x] + 1; q.push(y); now[y] = hd[y]; } } } return ~dep[T]; } int getflow(int x, int f) { if (x == T) return f; int ret = 0; for (int &e = now[x]; e; e = nxt[e]) { int y = to[e], z = cap[e]; if (dep[y] == dep[x] + 1 && z) { int w = getflow(y, min(f - ret, z)); cap[e] -= w; cap[e ^ 1] += w; ret += w; if (ret == f) return ret; } } return ret; } int dinic() { int ret = 0; while (getdep()) ret += getflow(S, INF); return ret; } int num[8][8], cc[8][8], pru[8], deg[8], vis[8]; void solve() { memset(deg, 0, sizeof(deg)); memset(vis, 0, sizeof(vis)); memset(cc, 0, sizeof(cc)); for (int i = 1; i <= m - 2; i++) deg[pru[i]]++; for (int i = 1; i <= m - 2; i++) { int pos = 0; for (int j = 1; j <= m; j++) { if (!deg[j] && !vis[j]) { pos = j; break; } } cc[min(pos, pru[i])][max(pos, pru[i])]++; deg[pru[i]]--; vis[pos] = 1; } int u1 = 1, u2 = m; while (vis[u1]) u1++; while (vis[u2]) u2--; cc[u1][u2]++; int cur = 0; init(); for (int i = 1; i <= m; i++) for (int j = i; j <= m; j++) { if (cc[i][j] > num[i][j]) return; cur++; adde(S, cur, num[i][j] - cc[i][j]); adde(cur, m * (m + 1) / 2 + i, INF); adde(cur, m * (m + 1) / 2 + j, INF); } for (int i = 1; i <= m; i++) adde(m * (m + 1) / 2 + i, T, cnt[i] - 1); if (dinic() == n - m) { for (int i = 1; i <= m; i++) for (int j = i; j <= m; j++) { if (cc[i][j]) printf( %d %d n , p[i], p[j]); } for (int i = 1; i <= m; i++) q[i] = p[i]; cur = 0; for (int i = 1; i <= m; i++) for (int j = i; j <= m; j++) { cur++; for (int e = hd[cur]; e; e = nxt[e]) { int y = to[e], z = cap[e ^ 1]; if (y == S) continue; if (y - m * (m + 1) / 2 == i) { while (z--) printf( %d %d n , ++q[i], p[j]); } else { while (z--) printf( %d %d n , ++q[j], p[i]); } } } exit(0); } } void dfs(int x) { if (x == m - 1) return solve(); for (int i = 1; i <= m; i++) pru[x] = i, dfs(x + 1); } int main() { scanf( %d , &n); for (int cur = 1; cur <= n; cur *= 10) p[++m] = cur; for (int i = 1; i < m; i++) cnt[i] = p[i + 1] - p[i]; cnt[m] = n - p[m] + 1; for (int i = 1; i < n; i++) { static char s1[9], s2[9]; scanf( %s%s , s1 + 1, s2 + 1); int l1 = strlen(s1 + 1), l2 = strlen(s2 + 1); if (l1 > l2) l1 ^= l2 ^= l1 ^= l2; num[l1][l2]++; } if (m == 1) { if (num[1][1] != n - 1) return puts( -1 ), 0; for (int i = 1; i < n; i++) printf( %d %d n , i, i + 1); return 0; } dfs(1); puts( -1 ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_2_V
`define SKY130_FD_SC_HS__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_2_V
|
#include <bits/stdc++.h> using namespace std; long long int modpow(long long int a, long long int n, long long int temp) { long long int res = 1; while (n > 0) { res = (res * res) % temp; if (n & 1) res = (res * a) % temp; n /= 2; } return res; } long long int gcd(long long int a, long long int b) { if (a == 0) return (b); else return (gcd(b % a, a)); } int main() { int n; vector<int> a; cin >> n; for (int i = 0; i < n; i++) { int t; cin >> t; a.push_back(t); } sort(a.begin(), a.end()); for (int i = 0; i < n - 1; i++) { while (a[i + 1] == a[i]) i++; if (i >= n - 1) break; if (2 * a[i] > a[i + 1]) { cout << YES ; return 0; } } cout << NO ; return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O31AI_PP_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_PP_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module nios_mem_if_ddr2_emif_0_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: digilentinc.com:ip:pmod_bridge:1.0
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PmodNAV_pmod_bridge_0_0 (
in_bottom_bus_I,
in_bottom_bus_O,
in_bottom_bus_T,
in0_I,
in1_I,
in2_I,
in3_I,
in0_O,
in1_O,
in2_O,
in3_O,
in0_T,
in1_T,
in2_T,
in3_T,
out0_I,
out1_I,
out2_I,
out3_I,
out4_I,
out5_I,
out6_I,
out7_I,
out0_O,
out1_O,
out2_O,
out3_O,
out4_O,
out5_O,
out6_O,
out7_O,
out0_T,
out1_T,
out2_T,
out3_T,
out4_T,
out5_T,
out6_T,
out7_T
);
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_Bottom_Row TRI_I" *)
output wire [3 : 0] in_bottom_bus_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_Bottom_Row TRI_O" *)
input wire [3 : 0] in_bottom_bus_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_Bottom_Row TRI_T" *)
input wire [3 : 0] in_bottom_bus_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_I" *)
output wire in0_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_I" *)
output wire in1_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_I" *)
output wire in2_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_I" *)
output wire in3_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_O" *)
input wire in0_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_O" *)
input wire in1_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_O" *)
input wire in2_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_O" *)
input wire in3_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_T" *)
input wire in0_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_T" *)
input wire in1_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_T" *)
input wire in2_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_T" *)
input wire in3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_I" *)
input wire out0_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_I" *)
input wire out1_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_I" *)
input wire out2_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_I" *)
input wire out3_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_I" *)
input wire out4_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_I" *)
input wire out5_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_I" *)
input wire out6_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_I" *)
input wire out7_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_O" *)
output wire out0_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_O" *)
output wire out1_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_O" *)
output wire out2_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_O" *)
output wire out3_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_O" *)
output wire out4_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_O" *)
output wire out5_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_O" *)
output wire out6_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_O" *)
output wire out7_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_T" *)
output wire out0_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_T" *)
output wire out1_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_T" *)
output wire out2_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_T" *)
output wire out3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_T" *)
output wire out4_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_T" *)
output wire out5_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_T" *)
output wire out6_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_T" *)
output wire out7_T;
pmod_concat #(
.Top_Row_Interface("SPI"),
.Bottom_Row_Interface("GPIO")
) inst (
.in_top_bus_I(),
.in_top_bus_O(4'B0),
.in_top_bus_T(4'B0),
.in_top_uart_gpio_bus_I(),
.in_top_uart_gpio_bus_O(2'B1),
.in_top_uart_gpio_bus_T(2'B1),
.in_top_i2c_gpio_bus_I(),
.in_top_i2c_gpio_bus_O(2'B1),
.in_top_i2c_gpio_bus_T(2'B1),
.in_bottom_bus_I(in_bottom_bus_I),
.in_bottom_bus_O(in_bottom_bus_O),
.in_bottom_bus_T(in_bottom_bus_T),
.in_bottom_uart_gpio_bus_I(),
.in_bottom_uart_gpio_bus_O(2'B1),
.in_bottom_uart_gpio_bus_T(2'B1),
.in_bottom_i2c_gpio_bus_I(),
.in_bottom_i2c_gpio_bus_O(2'B1),
.in_bottom_i2c_gpio_bus_T(2'B1),
.in0_I(in0_I),
.in1_I(in1_I),
.in2_I(in2_I),
.in3_I(in3_I),
.in4_I(),
.in5_I(),
.in6_I(),
.in7_I(),
.in0_O(in0_O),
.in1_O(in1_O),
.in2_O(in2_O),
.in3_O(in3_O),
.in4_O(1'B1),
.in5_O(1'B1),
.in6_O(1'B1),
.in7_O(1'B1),
.in0_T(in0_T),
.in1_T(in1_T),
.in2_T(in2_T),
.in3_T(in3_T),
.in4_T(1'B1),
.in5_T(1'B1),
.in6_T(1'B1),
.in7_T(1'B1),
.out0_I(out0_I),
.out1_I(out1_I),
.out2_I(out2_I),
.out3_I(out3_I),
.out4_I(out4_I),
.out5_I(out5_I),
.out6_I(out6_I),
.out7_I(out7_I),
.out0_O(out0_O),
.out1_O(out1_O),
.out2_O(out2_O),
.out3_O(out3_O),
.out4_O(out4_O),
.out5_O(out5_O),
.out6_O(out6_O),
.out7_O(out7_O),
.out0_T(out0_T),
.out1_T(out1_T),
.out2_T(out2_T),
.out3_T(out3_T),
.out4_T(out4_T),
.out5_T(out5_T),
.out6_T(out6_T),
.out7_T(out7_T)
);
endmodule
|
`timescale 1ns / 1ps
module ID_Ex(clk,Reset,Enable, Opcode,BSelector,Rd,RValue1,RValue2,ImmValue,MemRD,memWD,RegWrite,OPCODE,BSELECTOR,RD,RVALUE1,RVALUE2,IMMVALUE,MEMWD,MEMRD,REGWRITE);
input wire clk, Reset, Enable;
input [4:0] Opcode;
input [0:0] BSelector;
input [4:0] Rd;
input [31:0] RValue1,RValue2;
input [31:0] ImmValue;
input [0:0] MemRD,memWD,RegWrite;
output reg[4:0] OPCODE;
output reg[0:0] REGWRITE,MEMWD,MEMRD;
output reg[0:0] BSELECTOR;
output reg[4:0] RD;
output reg[31:0] RVALUE1,RVALUE2,IMMVALUE;
initial begin
OPCODE=5'b11111;
BSELECTOR=1'd0;
RD=5'd0;
RVALUE1=32'd0;
RVALUE2=32'd0;
IMMVALUE=32'd0;
MEMWD=1'd0;
MEMRD=1'd0;
REGWRITE=1'd0;
end
always @ (negedge clk) begin
if(Reset)begin
OPCODE=5'b11111;
BSELECTOR=1'd0;
RD=5'd0;
RVALUE1=32'd0;
RVALUE2=32'd0;
IMMVALUE=32'd0;
MEMWD=1'd0;
MEMRD=1'd0;
REGWRITE=1'd0;
end
else if (Enable)begin
OPCODE=Opcode;
BSELECTOR=BSelector;
RVALUE1=RValue1;
RVALUE2=RValue2;
IMMVALUE=ImmValue;
MEMWD=memWD;
MEMRD=MemRD;
REGWRITE=RegWrite;
RD=Rd;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; vector<vector<long long>> gr; vector<bool> used; vector<long long> tin, up; const long long Nmax = 400000; long long p[Nmax]; long long sz[Nmax]; long long timer = 0; long long diametr(long long u, vector<vector<long long>> gr) { queue<long long> q; long long n = (long long)(gr.size()); vector<long long> h(n + 1, -1); q.push(u); h[u] = 0; long long ml = u; while (!q.empty()) { long long v = q.front(); q.pop(); for (long long x : gr[v]) { if (h[x] == -1) { h[x] = h[v] + 1; if (h[x] > h[ml]) ml = x; q.push(x); } } } vector<long long> prev(n + 1, -1); h.assign(n + 1, -1); q.push(ml); h[ml] = 0; long long ms = ml; prev[ml] = ml; while (!q.empty()) { long long v = q.front(); q.pop(); for (long long x : gr[v]) { if (prev[x] == -1) { h[x] = h[v] + 1; prev[x] = v; if (h[x] > h[ms]) ms = x; q.push(x); } } } vector<long long> res; while (prev[ms] != ms) { res.push_back(ms); ms = prev[ms]; } res.push_back(ms); reverse((res).begin(), (res).end()); return (long long)(res.size()) - 1; } long long find(long long x) { if (p[x] != x) { p[x] = find(p[x]); } return p[x]; } void merge(long long x, long long y) { x = find(x); y = find(y); p[y] = x; } void restart(long long N) { for (long long i = 0; i < N; ++i) { sz[i] = 1; p[i] = i; } } vector<pair<long long, long long>> most; void dfs(long long u, long long p) { used[u] = true; tin[u] = timer++; up[u] = tin[u]; for (long long v : gr[u]) { if (used[v] && v != p) up[u] = min(up[u], tin[v]); if (!used[v]) { dfs(v, u); up[u] = min(up[u], up[v]); if (tin[u] < up[v]) { most.emplace_back(u, v); } else { merge(u, v); } } } } void solve() { long long n, m; cin >> n >> m; gr.resize(n); tin.assign(n, 0); up.assign(n, 0); used.assign(n, 0); restart(n); for (long long i = (0); i < (m); ++i) { long long u, v; cin >> u >> v; u--; --v; gr[u].push_back(v); gr[v].push_back(u); } dfs(0, -1); vector<vector<long long>> gr2(n); if (most.empty()) { cout << 0; return; } for (long long i = (0); i < ((long long)(most.size())); ++i) { long long u = most[i].first, v = most[i].second; u = find(u); v = find(v); gr2[u].push_back(v); gr2[v].push_back(u); } long long v = most[0].first; v = find(v); cout << diametr(v, gr2); } signed main() { ios::sync_with_stdio(0); cin.tie(0); long long t; t = 1; while (t--) { solve(); } return 0; } |
#include <vector> #include <algorithm> #include <queue> #include <iostream> #include <string> #include <stack> #include <map> #include <fstream> #include <random> #include <iomanip> #include <set> #include <cmath> #include <cassert> #include <unordered_set> #include <unordered_map> using namespace std; typedef long long int ll; typedef long double ld; const ll INF = 1e10; ll gcd(ll a, ll b) { return (b == 0 ? a : gcd(b, a % b)); } ll binpow(ll a, ll p) { if (p == 0) return 1; if (p % 2) { ll b = binpow(a, p - 1); return b * a; } else { ll b = binpow(a, p / 2); return b * b; } } vector<ll> get_primes(ll size) { vector<bool> is_pr(size, true); vector<ll> pr; is_pr[0] = is_pr[1] = false; for (ll i = 0; i < size; i++) { if (is_pr[i] == false) continue; pr.push_back(i); for (ll j = i *i ; j < size; j+=i) is_pr[j] = false; } return pr; } int main() { //ifstream cin( input.txt ); //ofstream cout( output.txt ); int t; cin >> t; vector<ll> primes = get_primes(4000); while (t--) { int n, k; cin >> n >> k; vector<ll> arr(n); for (int i = 0; i < n; i++) { cin >> arr[i]; for (ll p : primes) { while (arr[i] % (p * p) == 0 && arr[i] >= p * p) { arr[i] /= (p * p); } if (arr[i] < p * p) break; } } ll res = 1; set<ll> elem = { arr[0] }; for (int i = 1; i < n; i++) { if (elem.find(arr[i]) == elem.end()) { elem.insert(arr[i]); } else { elem.clear(); elem.insert(arr[i]); res++; } } cout << res << endl; } return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
// Date : Fri Nov 2 15:01:49 2018
// Host : graviton running 64-bit Debian GNU/Linux 7.11 (wheezy)
// Command : write_verilog -force -mode synth_stub
// /home/guest/cae/fpga/ntpserver/sv/ip/ocxo_clk_pll/ocxo_clk_pll_stub.v
// Design : ocxo_clk_pll
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ocxo_clk_pll(clk_in1, clk_out1, resetn, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,resetn,locked" */;
input clk_in1;
output clk_out1;
input resetn;
output locked;
endmodule
|
#include <bits/stdc++.h> using namespace std; int p2[203]; int p5[203]; int dpcur[203][5003][2]; int dpnxt[203][5003][2]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { long long int x; cin >> x; while (x % 2 == 0) { x /= 2; p2[i]++; } while (x % 5 == 0) { x /= 5; p5[i]++; } } memset(dpcur, -1, sizeof(dpcur)); memset(dpnxt, -1, sizeof(dpnxt)); dpcur[k][0][0] = 0; if (p2[1] >= p5[1]) { dpcur[k - 1][p2[1] - p5[1]][0] = p5[1]; } else { dpcur[k - 1][p5[1] - p2[1]][1] = p2[1]; } for (int i = 2; i <= n; i++) { for (int K = k; K >= max(0, k - (i - 1)); K--) { for (int excess_cnt = 0; excess_cnt <= min(5000, 60 * (i - 1)); excess_cnt++) { if (dpcur[K][excess_cnt][0] != -1) { dpnxt[K][excess_cnt][0] = max(dpnxt[K][excess_cnt][0], dpcur[K][excess_cnt][0]); int cnt2 = p2[i] + excess_cnt; int cnt5 = p5[i]; if (cnt2 >= cnt5 && K - 1 >= 0) { dpnxt[K - 1][min(cnt2 - cnt5, 5000)][0] = max(dpnxt[K - 1][min(cnt2 - cnt5, 5000)][0], dpcur[K][excess_cnt][0] + cnt5); } else if (cnt5 > cnt2 && K - 1 >= 0) { dpnxt[K - 1][min(cnt5 - cnt2, 5000)][1] = max(dpnxt[K - 1][min(cnt5 - cnt2, 5000)][1], dpcur[K][excess_cnt][0] + cnt2); } } if (dpcur[K][excess_cnt][1] != -1) { dpnxt[K][excess_cnt][1] = max(dpnxt[K][excess_cnt][1], dpcur[K][excess_cnt][1]); int cnt2 = p2[i]; int cnt5 = p5[i] + excess_cnt; if (cnt2 >= cnt5 && K - 1 >= 0) { dpnxt[K - 1][min(cnt2 - cnt5, 5000)][0] = max(dpnxt[K - 1][min(cnt2 - cnt5, 5000)][0], dpcur[K][excess_cnt][1] + cnt5); } else if (cnt5 > cnt2 && K - 1 >= 0) { dpnxt[K - 1][min(cnt5 - cnt2, 5000)][1] = max(dpnxt[K - 1][min(cnt5 - cnt2, 5000)][1], dpcur[K][excess_cnt][1] + cnt2); } } } } for (int K = k; K >= max(0, k - i); K--) { for (int excess_cnt = 0; excess_cnt <= min(5000, 60 * i); excess_cnt++) { for (int excess = 0; excess <= 1; excess++) { dpcur[K][excess_cnt][excess] = dpnxt[K][excess_cnt][excess]; } } } memset(dpnxt, -1, sizeof(dpnxt)); } int ans = 0; for (int excess_cnt = 0; excess_cnt <= 5000; excess_cnt++) { for (int excess = 0; excess <= 1; excess++) { ans = max(ans, dpcur[0][excess_cnt][excess]); } } cout << ans << n ; } |
// vim:set shiftwidth=3 softtabstop=3 expandtab:
/**
* MIPS
* basic (static) branch prediction: don't expect jumps. Possible later upgrade to saturating counter.
* pipeline
* OoO?
*/
`define BYTESIZE 8
`define WORDSIZE 4
`define BITNESS 32
//`include "alu.v"
module fpu(); //floating point optimised alu
endmodule
module instr_cache(); // cache instructions
endmodule
module instr_fetch(pc,ram,instr);
/**
* Load instruction and throw into pipeline
*/
inout pc;
input [64000:0]ram; // fake RAM
output instr;
assign instr = ram[pc];
assign pc = pc+4;
endmodule
module core(out1,out2,a1,a2,b1,b2,instr1,instr2,c);
output[64:0] out1, out2;
input[64:0] a1,a2,b1,b2;
input[8:0] instr1, instr2;
input c;
int_alu alu1(.out(out1), .a(a1), .b(b1), .instr(instr1), .c(c));
int_alu alu2(.out(out2), .a(a2), .b(b2), .instr(instr2), .c(c));
endmodule
module SparCool(inout clock); // Top module
instr_fetch IF(.pc(program_counter), .ram(memory)); // main IF
core core1(.c(clock)); // First "core", passing clock to c
core core2(.c(clock)); // Second "core"
core core3(.c(clock)); // Third core
core core4(.c(clock)); // Fourth core
assign clock=~clock; // No clock delay
endmodule |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
//
// Filename : mc_chroma_filter.v
// Created On : 2013-11-21 09:53:59
// Last Modified : 2013-11-21 18:38:15
// Revision :
// Author : Yufeng Bai
// Email :
// Description :
//-------------------------------------------------------------------
`include "enc_defines.v"
module mc_chroma_filter_hor(
frac_x,
frac_y,
A,
B,
C,
D,
out
);
input [2:0] frac_x,frac_y;
input [`PIXEL_WIDTH-1:0] A;
input [`PIXEL_WIDTH-1:0] B;
input [`PIXEL_WIDTH-1:0] C;
input [`PIXEL_WIDTH-1:0] D;
output[2*`PIXEL_WIDTH-1:0] out;
reg signed [2*`PIXEL_WIDTH-1:0] sum;
reg [`PIXEL_WIDTH-1: 0] pel_out; // pixel output directly
wire signed [2*`PIXEL_WIDTH-1:0] val_out; // val output
/*NEED TO BE OPTIMIAED*/
always @(*) begin
case(frac_x)
'd0: sum = (B*64);
'd1: sum = B*58 + C*10 - ((A + D) *2);
'd2: sum = B*54 + C*16 - ((A*2 + D) *2);
'd3: sum = B*46 + C*28 - (A*6 + D*4);
'd4: sum = 36*(B+C) - ((A+D)*4);
'd5: sum = C*46 + 28*B - (D*6 + A*4);
'd6: sum = C*54 + B*16 - (D*4 + A*2);
'd7: sum = C*58 + B*10 - ((A + D) *2);
endcase
end
// val out
assign val_out = sum - 'd8192;
// pel out
always @(*) begin
if (((sum+'d32) >> 6) < 0)
pel_out = 'd0;
else if (((sum+'d32) >> 6) > 255)begin
pel_out = 'd255;
end
else begin
pel_out = (sum+'d32) >> 6;
end
end
assign out = (frac_x == 0 || frac_y == 0 ) ? {{`PIXEL_WIDTH{1'b0}}, pel_out} : val_out;
endmodule
module mc_chroma_filter_ver(
frac_x,
frac_y,
A,
B,
C,
D,
out
);
input [2:0] frac_x,frac_y;
input signed [2*`PIXEL_WIDTH-1:0] A;
input signed [2*`PIXEL_WIDTH-1:0] B;
input signed [2*`PIXEL_WIDTH-1:0] C;
input signed [2*`PIXEL_WIDTH-1:0] D;
output reg [`PIXEL_WIDTH-1:0] out;
reg signed [4*`PIXEL_WIDTH-1:0] sum;
wire signed [2*`PIXEL_WIDTH-1:0] clip;
wire signed [2*`PIXEL_WIDTH-1:0] val, pel;
/*NEED TO BE OPTIMIAED*/
always @(*) begin
case(frac_y)
'd0: sum = (B*64);
'd1: sum = B*58 + C*10 - ((A + D) *2);
'd2: sum = B*54 + C*16 - ((A*2 + D) *2);
'd3: sum = B*46 + C*28 - (A*6 + D*4);
'd4: sum = 36*(B+C) - ((A+D)*4);
'd5: sum = C*46 + 28*B - (D*6 + A*4);
'd6: sum = C*54 + B*16 - (D*4 + A*2);
'd7: sum = C*58 + B*10 - ((A + D) *2);
endcase
end
// from val
assign val = (sum + 'd526336) >> 12;
// from pel
assign pel = (sum + 'd32) >> 6;
assign clip = (frac_x == 0) ? pel : val;
always @(*) begin
if (clip < 0)
out = 'd0;
else if (clip > 255)begin
out = 'd255;
end
else begin
out = clip;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; int x = abs(a - b); if (x % 2 == 0) { x /= 2; cout << x * (x + 1) << endl; } else { x /= 2; cout << x * (x + 1) + x + 1 << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_SYMBOL_V
`define SKY130_FD_SC_MS__CONB_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 10; int rd() { int x = 0, w = 1; char ch = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + (ch ^ 48); ch = getchar(); } return x * w; } int to[N], nt[N], hd[N], tot = 1; void adde(int x, int y) { ++tot, to[tot] = y, nt[tot] = hd[x], hd[x] = tot; } char cc[N]; int n, ans, f[N], g[N], s[N * 50], ch[N * 50][2], rt[N], tz; void inst(int o, int x) { s[o] = x; int l = 1, r = n; while (l < r) { int mid = (l + r) >> 1; if (x <= mid) o = ch[o][0] = ++tz, r = mid; else o = ch[o][1] = ++tz, l = mid + 1; s[o] = x; } } int merg(int o1, int o2) { if (!o1 || !o2) return o1 + o2; int o = ++tz; s[o] = max(s[o1], s[o2]); ch[o][0] = merg(ch[o1][0], ch[o2][0]); ch[o][1] = merg(ch[o1][1], ch[o2][1]); return o; } int quer(int o, int l, int r, int ll, int rr) { if (!o || ll > rr) return s[0]; if (ll <= l && r <= rr) return s[o]; int an = s[0], mid = (l + r) >> 1; if (ll <= mid) an = max(an, quer(ch[o][0], l, mid, ll, rr)); if (rr > mid) an = max(an, quer(ch[o][1], mid + 1, r, ll, rr)); return an; } int fa[N], tn[N][26], len[N], la = 1, tt = 1; void extd(int xx, int i) { int np = ++tt, p = la; len[np] = len[p] + 1, inst(rt[np] = ++tz, i), la = np; while (p && !tn[p][xx]) tn[p][xx] = np, p = fa[p]; if (!p) fa[np] = 1; else { int q = tn[p][xx]; if (len[q] == len[p] + 1) fa[np] = q; else { int nq = ++tt; fa[nq] = fa[q], len[nq] = len[p] + 1, memcpy(tn[nq], tn[q], sizeof(int) * 26); fa[np] = fa[q] = nq; while (p && tn[p][xx] == q) tn[p][xx] = nq, p = fa[p]; } } } void dfs1(int x) { for (int i = hd[x]; i; i = nt[i]) { int y = to[i]; dfs1(y), rt[x] = merg(rt[x], rt[y]); } } void dfs2(int x) { if (x > 1) { if (fa[x] == 1 || quer(rt[g[x]], 1, n, s[rt[x]] - len[x] + len[g[x]], s[rt[x]] - 1) > 0) ++f[x], g[x] = x; } ans = max(ans, f[x]); for (int i = hd[x]; i; i = nt[i]) { int y = to[i]; f[y] = f[x], g[y] = g[x], dfs2(y); } } int main() { n = rd(), scanf( %s , cc + 1); s[0] = -(1 << 25); for (int i = 1; i <= n; ++i) extd(cc[i] - a , i); for (int i = 2; i <= tt; ++i) adde(fa[i], i); dfs1(1); dfs2(1); printf( %d n , ans); return 0; } |
module vga640x480ice(input clk, // system clock
input clk25mhz,
input rst,
input [15:0] sram_in,
output [17:0] sram_adr_vga,
output reg data_rq_vga,
input grant_vga,
// Monochrome VGA pins
output hsync,
output vsync,
output [2:0] rgb // monochrome output, all three channels 0 or 1
);
// Pixels are fed via a small FIFO
reg fifo_en;
reg fifo_rd;
wire [15:0] fifo_in;
wire fifo_full;
wire [15:0] fifo_out;
wire fifo_empty;
reg [17:0] vmpos;
assign sram_adr_vga = vmpos[17:0];
assign fifo_in = sram_in;
parameter VMEM_END = (640*480/16) - 1;
smallfifo16 fifo1(.rst(rst),
.clk_in(clk),
.fifo_in(fifo_in),
.fifo_en(fifo_en),
.fifo_full(fifo_full),
.clk_out(clk25mhz),
.fifo_out(fifo_out),
.fifo_empty(fifo_empty),
.fifo_rd(fifo_rd));
// Just feed the FIFO with vmem contents
always @(posedge clk)
if (!rst) begin
fifo_en <= 0;
data_rq_vga <= 0;
vmpos <= 0;
end else begin // if (!rst)
if (!fifo_full && !fifo_en && !grant_vga) begin
data_rq_vga <= 1;
end if (fifo_en && data_rq_vga) begin
data_rq_vga <= 0;
fifo_en <= 0;
end else if (!fifo_full && !fifo_en && grant_vga) begin
if (vmpos < VMEM_END) vmpos <= vmpos + 1;
else begin
vmpos <= 0;
end
fifo_en <= 1;
end else begin
fifo_en <= 0;
end
end
//// bang pixels
reg [9:0] hcounter;
reg [9:0] vcounter;
reg ready;
wire visible;
parameter hlen = 640;
parameter hpulse = 96;
parameter hfp = 16;
parameter hbp = 48;
parameter vlen = 480;
parameter vfp = 10;
parameter vbp = 33;
parameter vpulse = 2;
parameter hlen1 = hlen + hpulse + hfp + hbp;
parameter vlen1 = vlen + vpulse + vfp + vbp;
assign hsync = ~((hcounter > hlen+hfp) & (hcounter < hlen+hfp+hpulse));
assign vsync = ~((vcounter > vlen+vfp) & (vcounter < vlen+vfp+vpulse));
assign visible = (hcounter < hlen)&&(vcounter < vlen);
always @(posedge clk25mhz)
if (!rst || !ready) begin // only start banging when there are some bits queued already
vcounter <= 0;
hcounter <= 0;
end else begin
if (hcounter >= hlen1-1) begin
hcounter <= 0;
if (vcounter >= vlen1-1)
vcounter <= 0;
else
vcounter <= vcounter + 1;
end else hcounter <= hcounter + 1;
end // else: !if(!rst)
// While in a visible area, keep sucking bits from the fifo, hoping it is being well fed
// on the other side.
reg [15:0] fontbits;
reg [15:0] fontnext;
wire nextbit;
assign nextbit = fontbits[15];
assign rgb = visible?{nextbit, nextbit,nextbit}:3'b0;
reg [3:0] bitcount;
reg getnext;
// What a mess!!!
always @(posedge clk25mhz)
if (!rst) begin
bitcount <= 0;
fontbits <= 0;
fontnext <= 0;
ready <= 0;
fifo_rd <= 0;
getnext <= 0;
end else begin
if (!ready) begin
if (fifo_rd) begin
fifo_rd <= 0;
fontbits <= fifo_out;
ready <= 1;
bitcount <= 15;
end else fifo_rd <= 1;
end else
if (visible) begin
if (bitcount < 15) begin
bitcount <= bitcount + 1;
fontbits <= fontbits << 1;
if (fifo_rd) begin
fontnext <= fifo_out;
fifo_rd <= 0;
getnext <= 0;
end else
if ((bitcount > 8) && getnext) begin
fifo_rd <= 1;
end
end else begin // if (bitcount < 15)
fifo_rd <= 0;
bitcount <= 0;
fontbits <= fontnext;
getnext <= 1;
end
end else begin
fifo_rd <= 0; // if (visible)
fontbits <= fontnext;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, M, T; int A[20000]; int rans; vector<int> ans; set<pair<int, int>> online; multiset<pair<int, int>> events; bool solve() { bool good = false; for (int i = 0; i < N; i++) events.insert({A[i], -1}); while (!events.empty()) { int t = events.begin()->first; int v = events.begin()->second; events.erase(events.begin()); if (v == -1) { if ((int)online.size() < M) { rans++; online.insert({t + T - 1, rans}); events.insert({t + T - 1, rans}); ans.push_back(rans); } else { pair<int, int> guy = *online.rbegin(); online.erase(guy); events.erase(events.find(guy)); guy.first = t + T - 1; online.insert(guy); events.insert(guy); ans.push_back(guy.second); } good |= (int)online.size() == M; } else online.erase({t, v}); } return good; } int main() { scanf( %d%d%d , &N, &M, &T); int hh, mm, ss; for (int i = 0; i < N; i++) { scanf( %d:%d:%d , &hh, &mm, &ss); A[i] = hh * 3600 + mm * 60 + ss; } if (!solve()) printf( No solution n ); else { printf( %d n , rans); for (auto& it : ans) printf( %d n , it); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 10, M = 2097152 + 10; long long n, x, ans, ar[N], mark[M][2]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long i = 0; i < n; i++) cin >> ar[i]; mark[0][1]++; for (long long i = 0; i < n; i++) { x ^= ar[i]; mark[x][i & 1]++; } for (long long i = 0; i < M; i++) { ans += (mark[i][0] * (mark[i][0] - 1)) / 2; ans += (mark[i][1] * (mark[i][1] - 1)) / 2; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; char def = a ; int pos = 0; string ans = ; for (int i = 0; i < n; i++) { ans += def + pos; pos = (pos + 1) % k; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; int i, cnt = 0, p = 0, n; cin >> n; cin >> s; for (i = 0; i < n; i++) if (s[i] == 0 ) cnt++; else p++; if (p > 0) { cout << 1; for (i = 0; i < cnt; i++) cout << 0; cout << endl; } else cout << 0 << endl; } |
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_const;
// Inputs
reg clk;
reg [5:0] addr;
// Outputs
wire [197:0] out;
wire effective;
reg [197:0] w_out;
reg w_effective;
// Instantiate the Unit Under Test (UUT)
const uut (
.clk(clk),
.addr(addr),
.out(out),
.effective(effective)
);
initial begin
// Initialize Inputs
addr = 0; clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
addr = 1; w_out = 0; w_effective = 1;
#(`P); check;
addr = 2; w_out = 1;
#(`P); check;
addr = 4; w_out = {6'b000101, 192'd0};
#(`P); check;
addr = 8; w_out = {6'b001001, 192'd0};
#(`P); check;
addr = 16; w_out = {6'b010101, 192'd0};
#(`P); check;
addr = 0; w_out = 0; w_effective = 0;
#(`P); check;
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== w_out || effective !== w_effective)
$display("E %d %h %h", addr, out, w_out);
end
endtask
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Oct 26 08:39:08 EDT 2015
//
// Method conflict info:
// Method: select
// Conflict-free: select
// Sequenced before: next
//
// Method: next
// Sequenced after: select
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// select O 5
// CLK I 1 clock
// RST_N I 1 reset
// select_requests I 5
// EN_next I 1
//
// Combinational paths from inputs to outputs:
// select_requests -> select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkInputArbiter(CLK,
RST_N,
select_requests,
select,
EN_next);
input CLK;
input RST_N;
// value method select
input [4 : 0] select_requests;
output [4 : 0] select;
// action method next
input EN_next;
// signals for module outputs
wire [4 : 0] select;
// register arb_token
reg [4 : 0] arb_token;
wire [4 : 0] arb_token$D_IN;
wire arb_token$EN;
// remaining internal signals
wire [1 : 0] ab__h1657,
ab__h1672,
ab__h1687,
ab__h1702,
ab__h1717,
ab__h3098,
ab__h3545,
ab__h3938,
ab__h4282,
ab__h4577;
wire NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
ab_BIT_0___h2269,
ab_BIT_0___h2376,
ab_BIT_0___h2483,
ab_BIT_0___h2590,
ab_BIT_0___h3169,
ab_BIT_0___h3305,
ab_BIT_0___h3698,
ab_BIT_0___h4042,
ab_BIT_0___h4337,
arb_token_BIT_0___h2267,
arb_token_BIT_1___h2374,
arb_token_BIT_2___h2481,
arb_token_BIT_3___h2588,
arb_token_BIT_4___h2695;
// value method select
assign select =
{ ab__h1657[1] || ab__h3098[1],
!ab__h1657[1] && !ab__h3098[1] &&
(ab__h1672[1] || ab__h3545[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h1657[1] && !ab__h3098[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// register arb_token
assign arb_token$D_IN = { arb_token[0], arb_token[4:1] } ;
assign arb_token$EN = EN_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h1717));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h2269),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h1702));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h2376),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h1687));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h2483),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h1672));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h2590),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h1657));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h3169),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h4577));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h4337),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h4282));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h4042),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h3938));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h3698),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h3545));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h3305),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h3098));
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
(ab__h1687[1] || ab__h3938[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h1687[1] && !ab__h3938[1] && !ab__h1702[1] &&
!ab__h4282[1] &&
(ab__h1717[1] || ab__h4577[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h1672[1] && !ab__h3545[1] && !ab__h1687[1] &&
!ab__h3938[1] &&
(ab__h1702[1] || ab__h4282[1]) ;
assign ab_BIT_0___h2269 = ab__h1717[0] ;
assign ab_BIT_0___h2376 = ab__h1702[0] ;
assign ab_BIT_0___h2483 = ab__h1687[0] ;
assign ab_BIT_0___h2590 = ab__h1672[0] ;
assign ab_BIT_0___h3169 = ab__h1657[0] ;
assign ab_BIT_0___h3305 = ab__h3545[0] ;
assign ab_BIT_0___h3698 = ab__h3938[0] ;
assign ab_BIT_0___h4042 = ab__h4282[0] ;
assign ab_BIT_0___h4337 = ab__h4577[0] ;
assign arb_token_BIT_0___h2267 = arb_token[0] ;
assign arb_token_BIT_1___h2374 = arb_token[1] ;
assign arb_token_BIT_2___h2481 = arb_token[2] ;
assign arb_token_BIT_3___h2588 = arb_token[3] ;
assign arb_token_BIT_4___h2695 = arb_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
arb_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
end
else
begin
if (arb_token$EN) arb_token <= `BSV_ASSIGNMENT_DELAY arb_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
arb_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkInputArbiter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2B_2_V
`define SKY130_FD_SC_HD__OR2B_2_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2b_2 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2B_2_V
|
module PS_flops_rd_ex_lsu(
in_vector_source_a,
in_vector_source_b,
in_scalar_source_a,
in_scalar_source_b,
in_imm_value0,
in_opcode,
in_lddst_stsrc_addr,
in_rd_en,
in_wr_en,
in_wfid,
in_instr_pc,
in_lds_base,
in_exec_value,
out_vector_source_a,
out_vector_source_b,
out_scalar_source_a,
out_scalar_source_b,
out_imm_value0,
out_opcode,
out_lddst_stsrc_addr,
out_rd_en,
out_wr_en,
out_wfid,
out_instr_pc,
out_lds_base,
out_exec_value,
clk,
rst
);
input clk;
input rst;
input [8191:0] in_vector_source_a;
input [2047:0] in_vector_source_b;
input [127:0] in_scalar_source_a;
input [31:0] in_scalar_source_b;
input [15:0] in_imm_value0;
input [31:0] in_opcode;
input [11:0] in_lddst_stsrc_addr;
input [3:0] in_rd_en;
input [3:0] in_wr_en;
input [5:0] in_wfid;
input [31:0] in_instr_pc;
input [15:0] in_lds_base;
input [63:0] in_exec_value;
output [8191:0] out_vector_source_a;
output [2047:0] out_vector_source_b;
output [127:0] out_scalar_source_a;
output [31:0] out_scalar_source_b;
output [15:0] out_imm_value0;
output [31:0] out_opcode;
output [11:0] out_lddst_stsrc_addr;
output [3:0] out_rd_en;
output [3:0] out_wr_en;
output [5:0] out_wfid;
output [31:0] out_instr_pc;
output [15:0] out_lds_base;
output [63:0] out_exec_value;
dff flop_vector_source_a[8191:0](
.q(out_vector_source_a),
.d(in_vector_source_a),
.clk(clk),
.rst(rst)
);
dff flop_vector_source_b[2047:0](
.q(out_vector_source_b),
.d(in_vector_source_b),
.clk(clk),
.rst(rst)
);
dff flop_scalar_source_a[127:0](
.q(out_scalar_source_a),
.d(in_scalar_source_a),
.clk(clk),
.rst(rst)
);
dff flop_scalar_source_b[31:0](
.q(out_scalar_source_b),
.d(in_scalar_source_b),
.clk(clk),
.rst(rst)
);
dff flop_imm_value0[15:0](
.q(out_imm_value0),
.d(in_imm_value0),
.clk(clk),
.rst(rst)
);
dff flop_opcode[31:0](
.q(out_opcode),
.d(in_opcode),
.clk(clk),
.rst(rst)
);
dff flop_lddst_stsrc_add[11:0](
.q(out_lddst_stsrc_addr),
.d(in_lddst_stsrc_addr),
.clk(clk),
.rst(rst)
);
dff flop_rd_en[3:0](
.q(out_rd_en),
.d(in_rd_en),
.clk(clk),
.rst(rst)
);
dff flop_wr_en[3:0](
.q(out_wr_en),
.d(in_wr_en),
.clk(clk),
.rst(rst)
);
dff flop_wfid[5:0](
.q(out_wfid),
.d(in_wfid),
.clk(clk),
.rst(rst)
);
dff flop_instr_pc[31:0](
.q(out_instr_pc),
.d(in_instr_pc),
.clk(clk),
.rst(rst)
);
dff flop_lds_base[15:0](
.q(out_lds_base),
.d(in_lds_base),
.clk(clk),
.rst(rst)
);
dff flop_exec_value[63:0](
.q(out_exec_value),
.d(in_exec_value),
.clk(clk),
.rst(rst)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int mp[505][505], f[505]; void push(int n) { for (int i = 1; i <= n; i++) cout << f[i] << ; cout << endl; } int main() { int n, m, i, j, Q, sum, x, y; while (scanf( %d%d%d , &n, &m, &Q) != EOF) { memset(f, 0, sizeof(f)); for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) scanf( %d , &mp[i][j]); int ans = 0, maxn = 0, sum = 0; for (i = 1; i <= n; i++) { sum = 0; maxn = 0; for (j = 1; j <= m; j++) { if (mp[i][j] == 1) sum++; else { maxn = max(maxn, sum); sum = 0; } } f[i] = max(maxn, sum); } while (Q--) { scanf( %d%d , &x, &y); if (mp[x][y] == 0) mp[x][y] = 1; else mp[x][y] = 0; maxn = 0, sum = 0; for (j = 1; j <= m; j++) { if (mp[x][j] == 1) sum++; else { maxn = max(maxn, sum); sum = 0; } } maxn = max(maxn, sum); f[x] = maxn; for (i = 1; i <= n; i++) maxn = max(maxn, f[i]); ans = maxn; printf( %d n , ans); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[2001], b[2001], n, k, len = 0, ans = 0, res = 0; void solve() { scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , a + i); } sort(a, a + n); for (int i = 0; i < n; i++) { if (a[i] + k <= 5) { len++; } } ans = (len / 3); printf( %d , ans); } int main() { solve(); } |
#include <bits/stdc++.h> using namespace std; const int mx = 5e5 + 10; const double eps = 1e-9; const int inf = 1e9; char a[mx]; multiset<char> ms; int main() { scanf( %s , a); int n = strlen(a); int mn = a[0] - a ; printf( Mike n ); for (int i = 1; i < n; i++) { if (a[i] - a > mn) { printf( Ann n ); } else printf( Mike n ); mn = min(mn, a[i] - a ); } } |
// TimeHoldOver_Qsys_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [24:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [24:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire i_readdatavalid, // .readdatavalid
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
TimeHoldOver_Qsys_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); int res = abs(x1 - x2) + 1 + (x1 == x2); res += abs(y1 - y2) + 1 + (y1 == y2); printf( %d n , res * 2); } |
#include <bits/stdc++.h> using namespace std; long long P[200020]; long long n, m; long long Mod = 998244353; long long Power(long long a, long long b) { if (b < 1) return 1; long long Tmp = Power(a, b / 2); Tmp = Tmp * Tmp % Mod; if (b & 1) Tmp = Tmp * a % Mod; return Tmp; } long long inv(long long a) { return Power(a, Mod - 2); } long long C(long long a, long long b) { if (b < 0 || a < 0 || a - b < 0) return 0; return P[a] * inv(P[a - b] * P[b] % Mod) % Mod; } int main() { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); cin >> n >> m; P[0] = 1; for (int i = 1; i < 200020; i++) P[i] = i * P[i - 1] % Mod; long long Ans = C(m, n - 1) * (n - 2) % Mod * Power(2, n - 3) % Mod; cout << Ans << n ; return 0; } |
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