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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O221AI_PP_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_PP_SYMBOL_V
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module GenericCounter (
CLK,
RESET,
D,
Q,
EN,
LOAD,
DOWN
);
parameter WIDTH = 8;
input CLK;
input RESET;
input [WIDTH - 1:0] D;
output reg [WIDTH - 1:0] Q;
input EN;
input LOAD;
input DOWN;
always @ (posedge CLK)
if(RESET)
Q <= 0;
else if(EN)
begin
if(LOAD)
Q <= D;
else if(DOWN)
Q <= Q - 1;
else
Q <= Q + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int main() { int n; cin >> n; int x[n], y[n], dx[n], dy[n], s[n]; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i] >> dx[i] >> dy[i] >> s[i]; } float ans = -1; int eff_s; float t1, t2; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (dx[i] * dy[j] == dx[j] * dy[i]) { if (dx[i] * (y[j] - y[i]) == dy[i] * (x[j] - x[i])) { eff_s = 0; if (dy[i] * (y[j] - y[i]) > 0) eff_s += s[i]; if (dy[j] * (y[i] - y[j]) > 0) eff_s += s[j]; if (eff_s != 0) { t1 = sqrt((y[j] - y[i]) * (y[j] - y[i]) + (x[j] - x[i]) * (x[j] - x[i])) / eff_s; if (ans == -1 || ans > t1) { ans = t1; } } } } else { t1 = (sqrt(dx[i] * dx[i] + dy[i] * dy[i]) * (dy[j] * (x[j] - x[i]) - dx[j] * (y[j] - y[i]))) / (s[i] * (dx[i] * dy[j] - dx[j] * dy[i])); t2 = (sqrt(dx[j] * dx[j] + dy[j] * dy[j]) * (dy[i] * (x[i] - x[j]) - dx[i] * (y[i] - y[j]))) / (s[j] * (dx[j] * dy[i] - dx[i] * dy[j])); if (t1 >= 0 && t2 >= 0 && (ans == -1 || ans > max(t1, t2))) { ans = max(t1, t2); } } } } if (ans == -1) cout << No show :( ; else cout << setprecision(14) << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) const long long maxn = 3000 + 10, N = 2e5 + 10, SQ = 320, base = 800287, mod = 1e9 + 7, INF = 1e18 + 10, lg = 22; const long double eps = 1e-4; long long n, m, q, dis[maxn][maxn], res[N]; long long V[N], U[N], r[N], s[N], t[N]; vector<long long> query[N]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> q; for (long long i = 0; i < m; ++i) { cin >> V[i] >> U[i]; V[i]--, U[i]--; } for (long long i = 0; i < n; ++i) { for (long long j = 0; j < n; ++j) { dis[i][j] = (i != j ? INF : m); } } for (long long i = 0; i < q; ++i) { long long l; cin >> l >> r[i] >> s[i] >> t[i]; l--, r[i]--, s[i]--, t[i]--; query[l].push_back(i); } for (long long idx = m - 1; idx >= 0; --idx) { dis[V[idx]][U[idx]] = dis[U[idx]][V[idx]] = idx; for (long long i = 0; i < n; ++i) { long long val = min(dis[V[idx]][i], dis[U[idx]][i]); dis[V[idx]][i] = dis[U[idx]][i] = val; } for (auto i : query[idx]) { if (dis[s[i]][t[i]] > r[i]) { res[i] = 0; } else { res[i] = 1; } } } for (long long i = 0; i < q; ++i) { cout << (res[i] ? Yes n : No n ); } } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool uax(T &x, T y) { return (y > x) ? x = y, true : false; } template <typename T> inline bool uin(T &x, T y) { return (y < x) ? x = y, true : false; } string to_string(char c) { return + string(1, c) + ; } string to_string(string s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } template <typename A> string to_string(A); template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + : + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool f = false; string r = { ; for (auto x : v) { if (f) r += , ; r += to_string(x); f = true; } return r += } ; } template <typename A> string to_string(vector<vector<A>> v) { string r; for (auto x : v) r += n + to_string(x); return r; } int Nerr; template <typename A> string to_string(A *p) { return to_string(vector<A>(p, p + Nerr)); } void err(istream_iterator<string>) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << =: << to_string(a) << ; ; err(++it, args...); } template <typename T> void kek(T ans) { cout << ans << endl; exit(0); } long long const INF = 1e18 + 42; const int MOD = 998244353; inline int add(int a, int b, int mod = MOD) { a += b; return a >= mod ? a - mod : a; } inline int sub(int a, int b, int mod = MOD) { a -= b; return a < 0 ? a + mod : a; } inline int mul(int a, int b, int mod = MOD) { return int((long long)a * b % mod); } inline int mpow(int base, long long ex, int mod = MOD) { int res = 1; for (; ex > 0; ex >>= 1) { if (ex & 1) res = mul(res, base, mod); base = mul(base, base, mod); } return res; } inline int inv(int a, int mod = MOD) { return mpow(a, mod - 2, mod); } inline int mdiv(int a, int b, int mod = MOD) { return mul(a, mpow(b, mod - 2, mod)); } inline void adds(int &a, int b, int mod = MOD) { a += b; if (a >= mod) a -= mod; } inline void subs(int &a, int b, int mod = MOD) { a -= b; if (a < 0) a += mod; } inline void muls(int &a, int b, int mod = MOD) { a = int((long long)a * b % mod); } inline void mdivs(int &a, int b, int mod = MOD) { a = mdiv(a, b, mod); } template <typename T, int K> struct Basis { array<T, K> bas; int n, rank; Basis() : bas(), n(), rank() {} bool add(T x) { ++n; for (int i = K - 1; i >= 0; --i) { if (x >> i & 1) { if (bas[i]) { x ^= bas[i]; } else { bas[i] = x, ++rank; return true; } } } return false; } int ways(T x) { for (int i = K - 1; i >= 0; --i) { if (x >> i & 1) x ^= bas[i]; } return x == 0 ? mpow(2, n - rank) : 0; } Basis operator+(Basis o) const { for (int i = 0; i < K; ++i) if (bas[i]) o.add(bas[i]); return o; } }; int32_t main() { cin.tie(nullptr)->sync_with_stdio(false); const int M = 35, F = 13, S = M - F; int n, m; cin >> n >> m; Basis<long long, M> basis; for (int i = 0; i < n; ++i) { long long x; cin >> x; basis.add(x); } 42; ; set<long long> s, t; for (int nask = 0; nask < (1 << F); ++nask) { long long val = 0; for (int i = 0; i < F; ++i) if (nask >> i & 1) { val ^= basis.bas[i]; } s.insert(val); } 42; ; for (int nask = 0; nask < (1 << S); ++nask) { long long val = 0; for (int i = 0; i < S; ++i) if (nask >> i & 1) { val ^= basis.bas[i + F]; } t.insert(val); } 42; ; array<array<int, (1 << F)>, F + 1> dp{}; for (auto &v : dp) fill(begin(v), end(v), -1); auto calc = [&](int b, int nask) { if (~dp[b][nask]) return dp[b][nask]; for (int i = 0; i <= F; ++i) dp[i][nask] = 0; for (long long x : s) ++dp[__builtin_popcountll(x ^ nask)][nask]; return dp[b][nask]; }; vector<int> ans(m + 1); for (long long x : t) { long long rt = x & ((1 << F) - 1); long long lf = x - rt; int cnt = __builtin_popcountll(lf); for (int i = 0; i <= F; ++i) { adds(ans[cnt + i], calc(i, (int)rt)); } } const int pw = mpow(2, n - basis.rank); for (int x : ans) { cout << mul(x, pw) << ; } cout << n ; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_fadd_32ns_32ns_32_5_full_dsp
#(parameter
ID = 0,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_fadd_3_full_dsp_32 ANN_ap_fadd_3_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200010, M = 500010; int h[N], e[M * 2], nex[M * 2], idx, n, m, nodea, nodeb, sz; int col[N]; void add(int x, int y) { e[idx] = y; nex[idx] = h[x]; h[x] = idx++; } bool dfs1(int u) { col[u] = 1; sz++; for (int i = h[u]; ~i; i = nex[i]) { int v = e[i]; if (v == nodea) continue; if (v == nodeb || col[v] == 2) return false; if (col[v] == 0) { if (!dfs1(v)) return false; } } return true; } bool dfs2(int u) { col[u] = -1; sz++; for (int i = h[u]; ~i; i = nex[i]) { int v = e[i]; if (v == nodeb) continue; if (v == nodea || col[v] == 1 || col[v] == 2) return false; if (col[v] == 0) { if (!dfs2(v)) return false; } } return true; } void modify(int u) { col[u] = 2; for (int i = h[u]; ~i; i = nex[i]) { int v = e[i]; if (col[v] == 2 || v == nodea || v == nodeb) continue; else modify(v); } } int main() { int T; cin >> T; while (T--) { scanf( %d%d%d%d , &n, &m, &nodea, &nodeb); for (int i = 0; i <= n; ++i) h[i] = -1, col[i] = 0; idx = 0; for (int i = 1; i <= m; ++i) { int x, y; scanf( %d%d , &x, &y); add(x, y); add(y, x); } int cnta = 0, cntb = 0; for (int i = h[nodea]; ~i; i = nex[i]) { int v = e[i]; sz = 0; if (col[v] == 0 && v != nodeb) { if (dfs1(v)) cnta += sz; else modify(v); } } for (int i = h[nodeb]; ~i; i = nex[i]) { int v = e[i]; sz = 0; if (col[v] == 0 && v != nodea) { if (dfs2(v)) cntb += sz; else modify(v); } } cout << 1ll * cnta * cntb << endl; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 12:28:13 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; long long int k, a[26], i, max = -1, l, sum = 0; cin >> s; cin >> k; l = s.length(); for (i = 0; i < 26; i++) { cin >> a[i]; if (max < a[i]) max = a[i]; } for (i = 0; i < l; i++) { sum = sum + (i + 1) * a[s[i] - a ]; } for (i = 0; i < k; i++) { sum += (i + l + 1) * max; } cout << sum; return 0; } |
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_8_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_8_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_8_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic use_AnB;
logic [1:0] active_command [8:0];
logic [1:0] command_A [8:0];
logic [1:0] command_B [8:0];
logic [1:0] active_command2 [8:0];
logic [1:0] command_A2 [8:0];
logic [1:0] command_B2 [8:0];
logic [1:0] active_command3 [1:0][2:0][3:0];
logic [1:0] command_A3 [1:0][2:0][3:0];
logic [1:0] command_B3 [1:0][2:0][3:0];
logic [2:0] use_A4nB4;
logic [8:0][1:0] active_command4;
logic [8:0][1:0] command_A4;
logic [8:0][1:0] command_B4;
logic [8:0] pipe1 [7:0];
logic [8:0] pipe1_input;
integer cyc;
assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0];
assign active_command2 = (use_AnB) ? command_A2 : command_B2;
// Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing
assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0];
// Check we can cope with things other than packed arrays
assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4;
always @ (posedge clk) begin
pipe1_input <= pipe1_input + 1;
pipe1[0] <= pipe1_input;
pipe1[7:1] <= pipe1[6:0];
end
logic [3:0][13:0] iq_read_data [15:0];
logic [3:0][13:0] iq_data;
logic [3:0] sel;
assign iq_data = iq_read_data[sel];
always @ (posedge clk) begin
sel = sel + 1;
end
initial begin
cyc = 0;
use_AnB = 0;
for (int i = 0; i < 7; ++i) begin
command_A[i] = 2'b00;
command_B[i] = 2'b11;
command_A2[i] = 2'b00;
command_B2[i] = 2'b11;
pipe1_input = 9'b0;
end
for (int i = 0; i < 2; ++i) begin
for (int j = 0; j < 3; ++j) begin
for (int k = 0; k < 4; ++k) begin
command_A3[i][j][k] = 2'b00;
command_B3[i][j][k] = 2'b11;
end
end
end
end
always @ (posedge clk) begin
use_AnB <= ~use_AnB;
cyc <= cyc + 1;
if (use_AnB) begin
if (active_command[3] != 2'b00) begin
$stop;
end
if (active_command2[3] != 2'b00) begin
$stop;
end
if (active_command3[0][1][2] != 2'b00) begin
$stop;
end
end
if (!use_AnB) begin
if (active_command[3] != 2'b11) begin
$stop;
end
if (active_command2[3] != 2'b11) begin
$stop;
end
end
end
logic [8:0] last_pipe;
always @(posedge clk) begin
if (cyc < 3) begin
last_pipe <= pipe1[0];
end
else begin
if (last_pipe + 1 != pipe1[0]) begin
$stop;
end
else begin
last_pipe <= pipe1[0];
end
end
if (cyc > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule : t
|
#include <bits/stdc++.h> using namespace std; long long t, n, a[100011], sum[100011], ans; map<long long, long long> mp; signed main() { scanf( %lld , &t); while (t--) { mp.clear(); scanf( %lld , &n); memset(a, 0, sizeof a); memset(sum, 0, sizeof sum); ans = 0; for (register long long i = 1; i <= n; ++i) { a[i] = getchar() - 0 ; while (a[i] < 0 || a[i] > 9) a[i] = getchar() - 0 ; a[i] = (a[i]) ? a[i] - 1 : -1; sum[i] = sum[i - 1] + a[i]; } mp[0] = 1; for (register long long i = 1; i <= n; ++i) { ans += mp[sum[i]]; ++mp[sum[i]]; } printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long M = 1000000007; long long power(long long a, long long b) { long long res = 1; for (long long i = 0; i < b; i++) res = (res * a) % M; return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t, n, m, k, i, x, ara[100], ans; cin >> t; while (t--) { cin >> n >> k; x = 0; m = k; ans = 0; while (m != 0) { ara[x] = m % 2; x++; m /= 2; } for (i = 0; i < x; i++) { if (ara[i] == 1) ans = ((ans % M) + power(n, i)) % M; } cout << ans << n ; } return 0; } |
`timescale 1ns/1ns
module arb_test();
reg clk, reset_n, wreq, fifo_full;
reg [7:0] memadrs, memdata;
wire [7:0] synth_ctrl, synth_data;
reg [7:0] test_state;
reg [7:0] wait_cnt;
synth_arb arb1(
.clk(clk),
.reset_n(reset_n),
.memadrs(memadrs),
.memdata(memdata),
.wreq(wreq),
.synth_ctrl(synth_ctrl),
.synth_data(synth_data),
.fifo_full(fifo_full));
parameter CLOCK = 10;
initial clk <= 0;
always #(CLOCK / 2) clk <= ~clk;
initial test_state <= 0;
initial reset_n <= 1;
initial wreq <= 0;
initial fifo_full <= 0;
initial memadrs <= 0;
initial memdata <= 0;
initial wait_cnt <= 0;
always @(posedge clk)
begin
case(test_state)
8'D0 : test_state <= test_state + 1;
8'D1 : begin
test_state <= test_state + 1;
reset_n <= 0;
end
8'D2 : begin
test_state <= test_state + 1;
reset_n <= 1;
end
8'D3 : begin //Normal Operation
if(wait_cnt != 8'b11111111)
begin
wait_cnt <= wait_cnt + 1;
end
else
begin
wait_cnt <= 0;
test_state <= test_state + 1;
end
end
8'D4 : begin //FIFO Full Operation Test
if(wait_cnt != 8'b00001111)
begin
wait_cnt <= wait_cnt + 1;
fifo_full <= 1;
end
else
begin
wait_cnt <= 0;
fifo_full <= 0;
test_state <= test_state + 1;
end
end
8'D5 : begin //Frequency Register Write Operation 1
if(wait_cnt != 8'b00001111)
begin
memadrs <= 8'h01;
memdata <= 8'h08;
wreq <= 1;
wait_cnt <= wait_cnt + 1;
test_state <= test_state;
end
else
begin
memadrs <= 8'h00;
memdata <= 8'h00;
wreq <= 0;
test_state <= test_state + 1;
wait_cnt <= 0;
end
end
8'D6 : begin
wreq <= 0;
test_state <= test_state + 1;
end
8'D7 : begin //Frequency Register Write Operation 2
if(wait_cnt != 8'b00001111)
begin
memadrs <= 8'h11;
memdata <= 8'h0A;
wreq <= 1;
wait_cnt <= wait_cnt + 1;
test_state <= test_state;
end
else
begin
memadrs <= 8'h00;
memdata <= 8'h00;
wreq <= 0;
test_state <= test_state + 1;
wait_cnt <= 0;
end
end
8'D8 : begin
wreq <= 0;
test_state <= test_state + 1;
end
8'D9 : test_state <= test_state;
default : test_state <= 0;
endcase
end
endmodule |
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// OmniVision Camera setup module. Configured to initialize OV7670 model.
//
// Initializes camera module using register set defined in OV7670Init and once done raises
// done_o signal.
//
// Other camera models require modification of register set and timing parameters.
// After a hardware reset delay for 1ms prior to raising rst_n.
// External pull-up register (4.7k should be enough) is required on SIOD line. FPGA`s internal
// pull-ups may not be sufficient.
//
//##################################################################################################
`timescale 1ns / 1ps
`include "macros.vh"
module CamSetup (
input clk, // Main clock.
input rst_n, // 0 - reset.
//Camera reg read/write cmd,
input [16:0] rw_cmd, //{rw, rw_addr[7:0], rw_data7:0
input rw_cmd_valid,
output reg rw_cmd_ready,
output [31:0] debug,
//camera reg resonse
output [16:0] rw_resp,
output reg rw_resp_valid,
output sioc_o, // Camera's SIOC.
inout siod_io // Camera's SIOD. Should have a pullup resistor.
);
`include "math.v"
parameter IN_FREQ = 100_000_000; // clk frequency in Hz.
parameter CAM_ID = 8'h42; // OV7670 ID. Bit 0 is Don't Care since we specify r/w op in register lookup table.
localparam SCCB_FREQ = 100_000; // SCCB frequency in Hz.
localparam T_SREG = 300; // Register setup time in ms. 300ms for OV7670.
localparam integer SREG_CYCLES = (IN_FREQ/1000)*T_SREG;
localparam SCCB_PERIOD = IN_FREQ/SCCB_FREQ/2;
reg [clog2(SCCB_PERIOD):0] sccb_clk_cnt;
reg sccb_clk;
wire [7:0] reg_data_rcvd;
reg sccb_start;
wire transact_done;
reg [clog2(SREG_CYCLES):0] reg_setup_cnt;
reg [clog2(SREG_CYCLES):0] reg_setup_cnt_nxt;
wire data_pulse;
reg [7:0] rw_addr;
reg [7:0] rw_data;
reg rw; // (0: read, 1: writea)
wire delay_cmd;
assign delay_cmd = (rw==1 && rw_addr==8'hF0 && rw_data==8'hF0);
assign data_pulse = (sccb_clk_cnt == SCCB_PERIOD/2 && sccb_clk == 0);
always @(posedge clk) begin
if(rw_cmd_valid && rw_cmd_ready) begin
rw_addr <= rw_cmd[15:8];
rw_data <= rw_cmd[7:0];
rw <= rw_cmd[16];
end
end
wire [6:0] stm;
assign debug = {1'h0, (stm[6:0]+1'b1),3'h0,rw,1'b0, cs[2:0], rw_addr[7:0], rw_data[7:0]};
assign rw_resp = rw ? {rw,rw_addr,rw_data} : {rw,rw_addr,reg_data_rcvd};
reg [2:0] cs, ns;
localparam IDLE=3'h0, CMD=3'h1, DELAY=3'h2, RW=3'h3, DONE=3'h4;
/*
inputs
rw_cmd_valid
delay_cmd
data_pulse
ack_error
transact_done
control
ns
sccb_start
reg_setup_cnt_nxt
rw_cmd_ready
rw_resp_valid
*/
always @(*) begin
(* parallel_case *) case(cs)
IDLE: begin
ns = rw_cmd_valid ? CMD : IDLE ;
sccb_start = 0;
reg_setup_cnt_nxt = 0;
rw_cmd_ready = 1;
rw_resp_valid = 0;
end
CMD: begin
ns = data_pulse ? (delay_cmd ? DELAY : RW) : CMD ;
sccb_start = (data_pulse && !delay_cmd) ? 1: 0;
reg_setup_cnt_nxt = 0;
rw_cmd_ready = 0;
rw_resp_valid = 0;
end
DELAY: begin
ns = reg_setup_cnt==SREG_CYCLES ? DONE : DELAY;
sccb_start = 0;
reg_setup_cnt_nxt = reg_setup_cnt+1'b1;
rw_cmd_ready = 0;
rw_resp_valid = 0;
end
RW: begin // TODO add ERR state and check ack_error
//ns = (data_pulse&&transact_done) ? (ack_error ? CMD : DONE) : RW ;
ns = (data_pulse&&transact_done) ? (DONE) : RW ;
sccb_start = 1;
reg_setup_cnt_nxt = 0 ;
rw_cmd_ready = 0;
rw_resp_valid = 0;
end
DONE: begin
ns = data_pulse ? IDLE : DONE;
sccb_start = 0;
reg_setup_cnt_nxt = 0;
rw_cmd_ready = 0;
rw_resp_valid = data_pulse ? 1 : 0;
end
default: begin
ns = IDLE;
sccb_start = 0;
reg_setup_cnt_nxt = 0;
rw_cmd_ready = 0;
rw_resp_valid = 0;
end
endcase
end
`REG(clk, cs, 0, ns)
// Read/Write the registers.
`REG(clk, reg_setup_cnt, 0, reg_setup_cnt_nxt)
SCCBCtrl sccbcntl
(
.clk_i(clk),
.rst_i(rst_n),
.sccb_clk_i(sccb_clk),
.data_pulse_i(data_pulse),
.addr_i(CAM_ID),
.data_i({rw_addr[7:0],rw_data[7:0]}),
.rw_i(rw),
.start_i(sccb_start),
.ack_error_o(ack_error),
.done_o(transact_done),
.data_o(reg_data_rcvd),
.sioc_o(sioc_o),
.siod_io(siod_io),
.stm(stm)
);
// Generate clock for the SCCB.
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
sccb_clk_cnt <= 0;
sccb_clk <= 0;
end else begin
if (sccb_clk_cnt < SCCB_PERIOD) begin
sccb_clk_cnt <= sccb_clk_cnt + 1'b1;
end else begin
sccb_clk <= ~sccb_clk;
sccb_clk_cnt <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int sum[200000 + 5]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , sum + i); sum[i] += i; } sort(sum, sum + n); for (int i = 1; i < n; ++i) { if (sum[i] == sum[i - 1]) { printf( :( n ); return 0; } } for (int i = 0; i < n; ++i) { printf( %d , sum[i] - i); } printf( n ); } |
#include <bits/stdc++.h> long long int mod = 1000000000 + 7; long long int inf = 1000000000000000000; using namespace std; int main() { iostream::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int ans = 1, a; cin >> a; for (int i = 0; i < 31; i++) { if ((a >> i) & 1) ans *= 2; } cout << ans << n ; } } |
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_empty_block (/*AUTOARG*/
// Outputs
rd_fifo_empty, rd_addr, rd_gray_pointer,
// Inputs
reset, rd_clk, rd_wr_gray_pointer, rd_read
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input rd_clk;
input [AW:0] rd_wr_gray_pointer;//from other clock domain
input rd_read;
//###########
//# OUTPUTS
//###########
output rd_fifo_empty;
output [AW-1:0] rd_addr;
output [AW:0] rd_gray_pointer;
//#########
//# REGS
//#########
reg [AW:0] rd_gray_pointer;
reg [AW:0] rd_binary_pointer;
reg rd_fifo_empty;
//##########
//# WIRES
//##########
wire rd_fifo_empty_next;
wire [AW:0] rd_binary_next;
wire [AW:0] rd_gray_next;
//Counter States
always @(posedge rd_clk or posedge reset)
if(reset)
begin
rd_binary_pointer[AW:0] <= {(AW+1){1'b0}};
rd_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(rd_read)
begin
rd_binary_pointer[AW:0] <= rd_binary_next[AW:0];
rd_gray_pointer[AW:0] <= rd_gray_next[AW:0];
end
//Read Address
assign rd_addr[AW-1:0] = rd_binary_pointer[AW-1:0];
//Updating binary pointer
assign rd_binary_next[AW:0] = rd_binary_pointer[AW:0] +
{{(AW){1'b0}},rd_read};
//Gray Pointer Conversion (for more reliable synchronization)!
assign rd_gray_next[AW:0] = {1'b0,rd_binary_next[AW:1]} ^
rd_binary_next[AW:0];
//# FIFO empty indication
assign rd_fifo_empty_next = (rd_gray_next[AW:0]==rd_wr_gray_pointer[AW:0]);
always @ (posedge rd_clk or posedge reset)
if(reset)
rd_fifo_empty <= 1'b1;
else
rd_fifo_empty <= rd_fifo_empty_next;
endmodule // fifo_empty_block
|
#include <bits/stdc++.h> using namespace std; int n = 0, m = 0, k; vector<string> a; int CountSpiders(int j) { int sum = 0; int jR = j, jL = j; for (int i = 1; i < n; ++i) { if (!(i % 2) && a[i][j] == U ) ++sum; if (jR > 0) { --jR; if (a[i][jR] == R ) ++sum; } if (jL < m - 1) { ++jL; if (a[i][jL] == L ) ++sum; } } return sum; } int main() { cin >> n >> m >> k; cin.ignore(100, n ); a.resize(n); for (int i = 0; i < n; ++i) getline(cin, a[i]); for (int j = 0; j < m; ++j) { cout << CountSpiders(j) << ; } } |
// bsg_hash_bank_reverse
//
// See paired module bsg_hash_bank.
// This module is the inverse; taking a bank number and an index, and producing the original address.
//
`include "bsg_defines.v"
module bsg_hash_bank_reverse #(parameter `BSG_INV_PARAM(banks_p), parameter `BSG_INV_PARAM(width_p), index_width_lp=$clog2((2**width_p+banks_p-1)/banks_p), lg_banks_lp=`BSG_SAFE_CLOG2(banks_p), debug_lp=0)
(/* input clk,*/
input [index_width_lp-1:0] index_i
, input [lg_banks_lp-1:0] bank_i
, output [width_p-1:0] o
);
if (banks_p == 1)
begin: hash1
assign o = index_i;
end
else
if (banks_p == 2)
begin: hash2
assign o = { bank_i, index_i };
end
else
if (~banks_p[0])
begin: hashpow2
assign o[width_p-1] = bank_i[0];
bsg_hash_bank_reverse #(.banks_p(banks_p >> 1),.width_p(width_p-1)) bhbr (/* .clk(clk) , */ .index_i(index_i[index_width_lp-1:0]),.bank_i(bank_i[lg_banks_lp-1:1]),.o(o[width_p-2:0]));
end
else
if ((banks_p & (banks_p+1)) == 0) // test for (2^N)-1
begin : hash3
if (width_p % lg_banks_lp)
begin : odd
wire _unused;
bsg_hash_bank_reverse #(.banks_p(banks_p),.width_p(width_p+1)) rhf
( /* .clk(clk),*/ .index_i({index_i, 1'b0}), .bank_i(bank_i), .o({o[width_p-1:0], _unused}));
end
else
begin : even
/* This is the hash function we implement.
Bank Zero, 0 XX XX --> 00 XX XX
Bank One, 0 XX XX --> 01 XX XX
Bank Two, 0 XX XX --> 10 XX XX
Bank Zero, 1 00 XX --> 11 00 XX
Bank One, 1 00 XX --> 11 01 XX
Bank Two, 1 00 XX --> 11 10 XX
Bank Zero, 1 01 00 --> 11 11 00
Bank One, 1 01 00 --> 11 11 01
Bank Two, 1 01 00 --> 11 11 10
Bank Zero, 1 01 01 --> 11 11 11
the algorithm is:
starting from the left; the first 00 you see, substitute the bank number
starting from the left; as long as you see 01, substitute 11.
*/
localparam frac_width_lp = width_p/lg_banks_lp;
wire [lg_banks_lp-1:0][frac_width_lp-1:0] unzippered;
wire [width_p-1:0] index_i_ext = (width_p) ' (index_i); // add 0's on
bsg_transpose #(.width_p(lg_banks_lp), .els_p(frac_width_lp)) unzip (.i(index_i_ext),.o(unzippered));
genvar j;
// and tuplets of lg_bank_lp-1 consecutive 0 bits
wire [frac_width_lp-1:0] zero_pair;
bsg_reduce_segmented #(.segments_p(frac_width_lp),.segment_width_p(lg_banks_lp),.nor_p(1)) brs
(.i(index_i_ext),.o(zero_pair));
wire [frac_width_lp-1:0] zero_pair_or_scan;
bsg_scan #(.width_p(frac_width_lp),.or_p(1)) scan
(.i(zero_pair),.o(zero_pair_or_scan));
// everything that is 0 should be converted to a 11
// the first 1 should be converted to the bank #
// the following 1's should just take the old bit values.
wire [frac_width_lp-1:0] first_one;
if (frac_width_lp > 1)
assign first_one = zero_pair_or_scan & ~{1'b0, zero_pair_or_scan[frac_width_lp-1:1]};
else
assign first_one = zero_pair_or_scan;
wire [lg_banks_lp-1:0][frac_width_lp-1:0] bits;
for (j = 0; j < lg_banks_lp; j=j+1)
begin: rof2
assign bits[j] = (zero_pair_or_scan & ~first_one & unzippered[j]) | (first_one & { frac_width_lp { bank_i[j] }}) | ~zero_pair_or_scan;
end
/* if (debug_lp)
begin
always @(negedge clk)
begin
$display ("%b %b -> ZP(%b) ZPS(%b) FO(%b) TB(%b) BB(%b) %b ",
index_i, bank_i, zero_pair, zero_pair_or_scan, first_one, top_bits, bot_bits, o);
end
end
*/
wire [width_p-1:0] transpose_lo;
bsg_transpose #(.els_p(lg_banks_lp), .width_p(frac_width_lp)) zip (.i({bits}),.o(transpose_lo));
assign o = transpose_lo[width_p-1:0];
end
end
else
initial
begin
assert(0) else $error("unhandled case, banks_p = ", banks_p);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_hash_bank_reverse)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_1_V
`define SKY130_FD_SC_HS__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NOR3_PP_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, d, h; vector<pair<int, int> > ans; int main() { ios::sync_with_stdio(0); cin >> n >> d >> h; if (2 * h < d || (d == 1 && n > 2)) { cout << -1 << n ; return 0; } for (int i = 2; i <= h + 1; i++) ans.push_back(make_pair(i - 1, i)); int idx = 1; bool done = false; for (int i = h + 2; i <= d + 1; i++) { ans.push_back(make_pair(idx, i)); done = true; idx = i; } if (done) idx = 1; else idx = 2; for (int i = d + 2; i <= n; i++) ans.push_back(make_pair(idx, i)); for (int i = 0; i < ans.size(); i++) cout << ans[i].first << << ans[i].second << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_BLACKBOX_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_BLACKBOX_V
|
module Control(clk,res,exp_diff,big_alu_result,
fra_result,shift_right_bits,
shift_left_bits,shift_right_en,shift_left_en,shift_right_bit,
incre_bit,decre_bit,incre_en,decre_en,mux_1_en,mux_2_en,mux_3_en,mux_4_en,mux_5_en);
integer i;
reg [7:0] n=0;
input clk,res;
input [8:0] exp_diff;
input [27:0] big_alu_result,fra_result;
output reg shift_right_en,shift_left_en,incre_en,decre_en;
output reg mux_1_en,mux_2_en,mux_3_en,mux_4_en,mux_5_en;
output reg [7:0] shift_right_bit,shift_right_bits;
output reg [7:0] shift_left_bits,incre_bit,decre_bit;
always @(posedge clk) begin
n=0;
//Enables
if(exp_diff[8])
fork
mux_1_en = 1;
mux_2_en = 0;
mux_3_en = 1;
join
else
fork
mux_1_en = 0;
mux_2_en = 1;
mux_3_en = 0;
join
//shift_right module
if(exp_diff[7:0]>25)
shift_right_bit = 25;
else
shift_right_bit = exp_diff[7:0];
shift_right_bit[7] = 1;//mark
mux_5_en = 0;
mux_4_en = 0;
//the incre_decre and shift_left_right module
if(big_alu_result[26]) // add and overflow.
fork
begin
incre_en = 1;
decre_en = 0;
incre_bit = 1;
end
begin
shift_right_en = 1;
shift_left_en = 0;
shift_right_bits = 1;
end
join
else
begin
for(i=25;big_alu_result[i]==0;i=i-1)
n=n+1;
fork
begin
decre_en = 1;
incre_en = 0;
decre_bit = n;
end
begin
shift_left_en = 1;
shift_right_en = 0;
shift_left_bits = n;
end
join
end
//Rounding module
if(fra_result)
begin
mux_5_en = 1;
mux_4_en = 1;
fork
begin
incre_en = 1;
decre_en = 0;
incre_bit = 1;
end
begin
shift_right_en = 1;
shift_left_en = 0;
shift_right_bits = 1;
end
join
end
//Reset
if(!res)
begin
shift_right_en=0;
shift_left_en=0;
incre_en=0;
decre_en=0;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 29; struct abc { int left, right, capacity, cost; } edge[12345]; int n, k, x, e = 0, cost[50], p[50]; void addEdge(int a, int b, int c, int d) { edge[e].left = a; edge[e].right = b; edge[e].capacity = c; edge[e].cost = d; e++; edge[e].left = b; edge[e].right = a; edge[e].capacity = 0; edge[e].cost = -d; e++; } bool getPath(int s, int t) { for (int i = 0; i < n; i++) cost[i] = INF; cost[s] = 0; bool upd = true; for (int it = 1; upd && it < n; it++) for (int i = upd = 0; i < e; i++) if (edge[i].capacity > 0 && cost[edge[i].left] < INF && cost[edge[i].right] > cost[edge[i].left] + edge[i].cost) { cost[edge[i].right] = cost[edge[i].left] + edge[i].cost; p[edge[i].right] = i; upd = true; } return cost[t] < INF; } int minCostMaxFlow(int s, int t) { int MaxFlow = 0, MinCost = 0, flow; while (getPath(s, t)) { MinCost += cost[t]; if (MinCost > k) return MaxFlow; flow = INF; for (int c = t; c != s; c = edge[p[c]].left) { flow = min(flow, edge[p[c]].capacity); if (edge[p[c]].cost != 0) flow = 1; } for (int c = t; c != s; c = edge[p[c]].left) { edge[p[c]].capacity -= flow; edge[p[c] ^ 1].capacity += flow; } MaxFlow += flow; } return MaxFlow; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { cin >> x; if (x) { addEdge(i, j, x, 0); addEdge(i, j, INF, 1); } } cout << minCostMaxFlow(0, n - 1); } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int oo = 0x3f3f3f3f; const int max0 = 50, maxn = 1000; int n, first; double p, q; double a[maxn + 5][max0 + 5]; double b[maxn + 5][max0 + 5]; double dp[maxn + 5][max0 + 5]; int main() { scanf( %d%d , &n, &first); p = first / 1e9, q = 1 - p; for (int i = (1), _end_ = (maxn + 1); i < _end_; ++i) for (int j = (1), _end_ = (max0); j < _end_; ++j) { if (j == 1) a[i][j] += p; if (j == 2) a[i][j] += q, b[i][j] += q; a[i][j] += a[i - 1][j - 1] * a[i][j - 1]; b[i][j] += a[i - 1][j - 1] * b[i][j - 1]; } for (int i = maxn; i >= 1; --i) for (int j = (1), _end_ = (max0); j < _end_; ++j) a[i][j] *= 1 - a[i - 1][j], b[i][j] *= 1 - a[i - 1][j]; for (int i = (1), _end_ = (max0); i < _end_; ++i) dp[maxn][i] = i; for (int i = maxn - 1; i >= 0; --i) for (int j = (1), _end_ = (max0); j < _end_; ++j) { double sum = 0; for (int k = (1), _end_ = (max0); k < _end_; ++k) { if (j == k) continue; int pos = maxn - i; if (j == 1) dp[i][j] += b[pos][k] * dp[i + 1][k], sum += b[pos][k]; else if (j > k) dp[i][j] += a[pos][k] * dp[i + 1][k], sum += a[pos][k]; } (dp[i][j] /= sum) += j; } double ans = 0; if (n <= maxn) for (int i = (1), _end_ = (max0); i < _end_; ++i) ans += a[n][i] * dp[maxn - n + 1][i]; else { double sum0 = 0, sum1 = 0; for (int i = (1), _end_ = (max0); i < _end_; ++i) sum0 += a[maxn][i] * dp[0][i]; for (int i = (1), _end_ = (max0); i < _end_; ++i) sum1 += a[maxn - 1][i] * dp[1][i]; ans = sum1 + (sum0 - sum1) * (n - maxn + 1); } printf( %.15f n , ans); return 0; } |
#include <bits/stdc++.h> long long int mod = 1000000007; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, k; cin >> n >> k; long long int p = k / n; if (k % n != 0) { p += 1; } cout << p; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Thomas Kappenman
//
// Create Date: 03/03/2015 09:33:36 PM
// Design Name:
// Module Name: PS2Receiver
// Project Name: Nexys4DDR Keyboard Demo
// Target Devices: Nexys4DDR
// Tool Versions:
// Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PS2Receiver(
input clk,
input kclk,
input kdata,
output [31:0] keycodeout
);
wire kclkf, kdataf;
reg [7:0]datacur;
reg [7:0]dataprev;
reg [3:0]cnt;
reg [31:0]keycode;
reg flag;
initial begin
keycode[31:0]<=0'h00000000;
cnt<=4'b0000;
flag<=1'b0;
end
debouncer debounce(
.clk(clk),
.I0(kclk),
.I1(kdata),
.O0(kclkf),
.O1(kdataf)
);
always@(negedge(kclkf))begin
case(cnt)
0:;//Start bit
1:datacur[0]<=kdataf;
2:datacur[1]<=kdataf;
3:datacur[2]<=kdataf;
4:datacur[3]<=kdataf;
5:datacur[4]<=kdataf;
6:datacur[5]<=kdataf;
7:datacur[6]<=kdataf;
8:datacur[7]<=kdataf;
9:flag<=1'b1;
10:flag<=1'b0;
endcase
if(cnt<=9) cnt<=cnt+1;
else if(cnt==10) cnt<=0;
end
always @(posedge flag)begin
if (dataprev!=datacur)begin
keycode[31:24]<=keycode[23:16];
keycode[23:16]<=keycode[15:8];
keycode[15:8]<=dataprev;
keycode[7:0]<=datacur;
dataprev<=datacur;
end
end
assign keycodeout=keycode;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 24.06.2017 01:05:36
// Design Name:
// Module Name: PS2_y_display
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PS2_y_display(
input clock,
input reset,
input ps2_clk,
input ps2_data,
output [7:0] anodos,
output [7:0] segmentos,
output [31:0] cifras,
output [4:0] tecla,
output kbs_tot
);
wire reloj_lento;
wire [7:0] data;
wire [2:0] control;
wire [2:0] data_type;
reg [3:0] cifra1,cifra2,cifra3,cifra4,cifra5,cifra6,cifra7,cifra8;
reg [3:0] cifra1_next,cifra2_next,cifra3_next,cifra4_next,cifra5_next,cifra6_next,cifra7_next,cifra8_next;
assign cifras={cifra1,cifra2,cifra3,cifra4,cifra5,cifra6,cifra7,cifra8};
clock_divider clock_div(
.clk(clock),
.rst (reset),
.clk_div (reloj_lento)
);
teclado tec(
.ps2_data(data),
.val(tecla),
.control(control),
.leds ()
);
kbd_ms driver_tec(
.clk(clock),
.rst(reset),
.kd(ps2_data),
.kc(ps2_clk),
.new_data(data),
.data_type(data_type),
.kbs_tot(kbs_tot),
.parity_error()
);
display dis(
.clk_display(reloj_lento),
.num(cifras),
.puntos(),
.anodos(anodos),
.segmentos(segmentos)
);
always @(*) begin
if ((kbs_tot) & (data_type==3'd1) & (control==3'b1)) begin
cifra8_next=tecla[3:0];
cifra7_next=cifra8;
cifra6_next=cifra7;
cifra5_next=cifra6;
cifra4_next=cifra5;
cifra3_next=cifra4;
cifra2_next=cifra3;
cifra1_next=cifra2;
end
else begin
cifra8_next=cifra8;
cifra7_next=cifra7;
cifra6_next=cifra6;
cifra5_next=cifra5;
cifra4_next=cifra4;
cifra3_next=cifra3;
cifra2_next=cifra2;
cifra1_next=cifra1;
end
end
always @(posedge clock) begin
if (reset) begin
cifra1<=4'b0;
cifra2<=4'b0;
cifra3<=4'b0;
cifra4<=4'b0;
cifra5<=4'b0;
cifra6<=4'b0;
cifra7<=4'b0;
cifra8<=4'b0;
end
else begin
cifra1<=cifra1_next;
cifra2<=cifra2_next;
cifra3<=cifra3_next;
cifra4<=cifra4_next;
cifra5<=cifra5_next;
cifra6<=cifra6_next;
cifra7<=cifra7_next;
cifra8<=cifra8_next;
end
end
endmodule
|
/* Buffer module testbench */
`timescale 1ns/1ns
module buffer_test();
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
// make reset
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#50
counter = counter + 1;
new_sample_val = 1'b1;
#10
new_sample_val = 1'b0;
end
buffer #(B) b1
(
//inputs
.clk(CLOCK_50),
.rst(rst),
.delta(8'b01000000), // 1 in fixed3.5
.new_sample_val(new_sample_val),
.new_sample_data(counter),
.out_sel(1'b0),
.delta_mode(1'b0),
//outputs
.pitch_shift_out(pitch_shift_out),
.pitch_shift_val(pitch_shift_val)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; const int inf = ~0u >> 2; int numa[N], numb[N], pos[N]; struct node { int val, id; node(int _val, int _id) { val = _val, id = _id; } bool operator<(const node& A) const { return val > A.val; } }; int now[N], unuse[N]; priority_queue<node> A, B; int __ans[N]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { scanf( %d , &numa[i]); pos[numa[i]] = i; } for (int i = 0; i < n; i++) { scanf( %d , &numb[i]); int val = i - pos[numb[i]]; if (val < 0) B.push(node(abs(val), i)); else A.push(node(abs(val), i)); now[i] = val; } int tmp = 0, len = 0; for (int k = n - 1; k >= 0; k--) { int pa = A.empty() ? inf : A.top().val + tmp; int pb = B.empty() ? inf : B.top().val - tmp; __ans[len++] = min(pa, pb); while (pb == 0) { int id = B.top().id; A.push(node(-tmp, id)); B.pop(); if (B.empty()) break; pb = B.top().val - tmp; } unuse[k] = 1; int np = pos[numb[k]]; now[k] = -np - tmp - 1; while (!A.empty() && (A.top().val + tmp != abs(now[A.top().id] + tmp) && unuse[A.top().id])) { unuse[A.top().id] = 0; A.pop(); } tmp++; if (np == 0) A.push(node(-tmp, k)); else B.push(node(np + tmp, k)); } cout << __ans[0] << endl; for (int i = len - 1; i; i--) printf( %d n , __ans[i]); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_4_V
`define SKY130_FD_SC_LP__NAND4_4_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 08:26:12
// Design Name:
// Module Name: Serial_in_parallel_out_enable_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Serial_in_parallel_out_enable_behavior_tb(
);
reg Clk, ShiftIn, reset, ShiftEn;
wire ShiftOut;
wire [3:0] ParallelOut;
Serial_in_parallel_out_enable_behavior DUT (.Clk(Clk), .ShiftIn(ShiftIn), .reset(reset), .ShiftEn(ShiftEn), .ShiftOut(ShiftOut), .ParallelOut(ParallelOut));
initial begin
#350 $finish;
end
initial begin
Clk = 0; ShiftIn = 1; reset = 1; ShiftEn = 0;
#10 Clk = 1;
#10 Clk = 0; reset = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1; // 50ns
#10 Clk = 0; ShiftEn = 1;
#10 Clk = 1;
#10 Clk = 0; ShiftEn = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftEn = 1;// 100ns
#10 Clk = 1; ShiftIn = 0;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftEn = 0;
#10 Clk = 1; // 150ns
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftEn = 1;// 200ns
#10 Clk = 1;
#10 Clk = 0; ShiftEn = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1; //250ns
#10 Clk = 0;
#10 Clk = 1;
#5 ShiftEn = 1;
#5 Clk = 0;
#10 Clk = 1;
#5 ShiftEn = 0;
#5 Clk = 0; // 300ns
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const long long MOD = 1e9 + 7; long long h[26][N], p[N]; int a[30], b[30]; char s[N + 10]; long long get(int i, int l, int r) { return (h[i][r] - h[i][l - 1] * p[r - l + 1]) % MOD; } int main() { int n, m, x, y, len; while (scanf( %d%d , &n, &m) != EOF) { p[0] = 1; for (int i = 1; i <= n; i++) p[i] = (p[i - 1] * 2) % MOD; scanf( %s , s + 1); for (int i = 0; i < 26; i++) for (int j = 1; j <= n; j++) h[i][j] = (h[i][j - 1] * 2 + (s[j] == a + i)) % MOD; while (m--) { scanf( %d%d%d , &x, &y, &len); for (int i = 0; i < 26; i++) { a[i] = (get(i, x, x + len - 1) + MOD) % MOD; b[i] = (get(i, y, y + len - 1) + MOD) % MOD; } sort(a, a + 26); sort(b, b + 26); bool flag = true; for (int i = 0; i < 26; i++) if (a[i] != b[i]) { flag = false; break; } printf( %s n , flag ? YES : NO ); } } } |
`timescale 1ns / 1ps
module Microphone(
output spi_clk, // SPI clock to ADC
output spi_mosi, // Data to ADC
output reg spi_cs, // Chip select for ADC
input spi_miso, // Data from ADC
input clk,
input rst,
input start_sample, // Set to 1 to sample the ADC
output reg sample_done, // Latest sample is ready to be read
output reg [9:0] sample
);
// The 10-bit ADC sample
reg sample_done_d;
reg [9:0] sample_d;
// SPI module
reg spi_start, spi_start_d;
reg spi_cs_d;
reg [7:0] spi_mosi_byte, spi_mosi_byte_d;
wire [7:0] spi_miso_byte;
wire spi_done;
SPI #(6) spi(clk, rst, spi_miso, spi_mosi, spi_clk, spi_start, spi_mosi_byte, spi_miso_byte, , spi_done);
// parameter 6 = divide 100 Mhz clock by 2^6, which ends up being 1.5625 MHz
// States
reg [3:0] state, state_d; // State of the module
reg [3:0] state_after, state_after_d; // State to go to after waiting for spi to be done
localparam SPI_START = 4'd0,
SPI_WAIT = 4'd1,
IDLE = 4'd2,
CS_LOW = 4'd3,
SEND_START = 4'd4,
SEND_CHANNEL = 4'd5,
RECV_2BITS = 4'd6,
SEND_ZEROS = 4'd7,
RECV_8BITS = 4'd8,
CS_HIGH = 4'd9;
// Sequential logic
always @ (posedge clk) begin
if(rst) begin
sample <= 10'b0;
sample_done <= 1'b0;
spi_start <= 1'b0;
spi_cs <= 1'b1;
spi_mosi_byte <= 8'b0;
state <= IDLE;
state_after <= IDLE;
end else begin
sample <= sample_d;
sample_done <= sample_done_d;
spi_start <= spi_start_d;
spi_cs <= spi_cs_d;
spi_mosi_byte <= spi_mosi_byte_d;
state <= state_d;
state_after <= state_after_d;
end
end
// Combinational logic
always @ (*) begin
sample_d = sample;
sample_done_d = 1'b0;
spi_start_d = 1'b0;
spi_cs_d = spi_cs;
spi_mosi_byte_d = spi_mosi_byte;
state_d = state;
state_after_d = state_after;
case(state)
IDLE: begin
if(start_sample == 1'b1) begin
spi_cs_d = 1'b0; // chip select low
state_d = SEND_START;
end
end
SEND_START: begin
spi_mosi_byte_d = 8'h01;
state_d = SPI_START;
state_after_d = SEND_CHANNEL;
end
SEND_CHANNEL: begin
spi_mosi_byte_d = 8'h00; // Read from ADC channel 0
state_d = SPI_START;
state_after_d = RECV_2BITS;
end
RECV_2BITS: begin
sample_d[9:8] = spi_miso_byte[1:0];
state_d = SEND_ZEROS;
end
SEND_ZEROS: begin
spi_mosi_byte_d = 8'h00; // Send zeros so we can read the last 8 bits
state_d = SPI_START;
state_after_d = RECV_8BITS;
end
RECV_8BITS: begin
sample_d[7:0] = spi_miso_byte;
state_d = IDLE;
sample_done_d = 1'b1;
spi_cs_d = 1'b1; // chip select high
end
SPI_START: begin
spi_start_d = 1'b1;
state_d = SPI_WAIT;
end
SPI_WAIT: begin
if(spi_done)
state_d = state_after; // go to state we were waiting to go to
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> arr; int maxNum = -1; int n; bool vis[1000000 + 50]; int main() { memset(vis, false, sizeof(vis)); scanf( %d , &(n)); for (int i = 0; i < n; i++) { int tmp; scanf( %d , &(tmp)); if (!vis[tmp]) { arr.push_back(tmp); vis[tmp] = true; if (tmp > maxNum) { maxNum = tmp; } } } n = arr.size(); if (arr.size() == 1) { printf( 0 n ); return 0; } sort(arr.begin(), arr.end()); int ans = 0; for (int i = 0; i < n; i++) { int num = arr[i]; int t = 2; while (1) { int pos = lower_bound(arr.begin(), arr.end(), num * t) - arr.begin() - 1; int tmp = arr[pos] % num; if (tmp > ans) { ans = tmp; } if (pos == n - 1) { break; } t++; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int num, i, count = 0, sum = 0, a; cin >> num; a = 1; while (1) { for (i = 1; i <= a; i++) { sum += i; } a++; if (sum > num) break; count++; } cout << count << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve(); void precalc(); clock_t start; bool doing = true; int main() { int t = 1; cout.sync_with_stdio(0); cin.tie(0); precalc(); cout.precision(10); cout << fixed; start = clock(); int testNum = 1; while (t--) { solve(); } return 0; } void precalc() {} int binpow(int q, int w, int mod) { if (!w) return 1; if (w & 1) return q * binpow(q, w - 1, mod) % mod; return binpow(q * q % mod, w / 2, mod); } int mod = 1000000007; int gcd(int q, int w) { while (w) { q %= w; swap(q, w); } return q; } int n, m; string s[1005]; void solve() { cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> s[i]; } vector<char> good(n - 1, false); int ans = 0; for (int i = 0; i < m; ++i) { bool need = false; for (int j = 0; j + 1 < n; ++j) { if (good[j]) { continue; } if (s[j][i] > s[j + 1][i]) { need = true; } } if (need) { ++ans; } else { for (int j = 0; j + 1 < n; ++j) { if (s[j][i] < s[j + 1][i]) { good[j] = true; } } } } cout << ans << n ; } |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Steps through the major sections of the output clock
// delay algorithm. Enabling various subblocks at the right time.
//
// Steps through each byte of the interface.
//
// Implements both the simple and complex data pattern.
//
// for each byte in interface
// begin
// Limit
// Scan - which includes DQS centering
// Precharge
// end
// set _wrlvl and _done equal to one
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_cntlr #
(parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8)
(/*AUTOARG*/
// Outputs
wrlvl_final, complex_wrlvl_final, oclk_init_delay_done,
ocd_prech_req, lim_start, complex_oclkdelay_calib_done,
oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2,
phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt,
reset_scan,
// Inputs
clk, rst, prech_done, oclkdelay_calib_start,
complex_oclkdelay_calib_start, lim_done, phy_rddata_en,
po_counter_read_val, po_rdy, scan_done
);
localparam ONE = 1;
input clk;
input rst;
output wrlvl_final, complex_wrlvl_final;
reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r;
always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns;
always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns;
assign wrlvl_final = wrlvl_final_r;
assign complex_wrlvl_final = complex_wrlvl_final_r;
// Completed initial delay increment
output oclk_init_delay_done; // may not need this... maybe for fast cal mode.
assign oclk_init_delay_done = 1'b1;
// Precharge done status from ddr_phy_init
input prech_done;
reg ocd_prech_req_ns, ocd_prech_req_r;
always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns;
output ocd_prech_req;
assign ocd_prech_req = ocd_prech_req_r;
input oclkdelay_calib_start, complex_oclkdelay_calib_start;
input lim_done;
reg lim_start_ns, lim_start_r;
always @(posedge clk) lim_start_r <= #TCQ lim_start_ns;
output lim_start;
assign lim_start = lim_start_r;
reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r;
always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns;
output complex_oclkdelay_calib_done;
assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r;
reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r;
always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns;
output oclkdelay_calib_done;
assign oclkdelay_calib_done = oclkdelay_calib_done_r;
input phy_rddata_en;
reg prde_r1, prde_r2;
always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en;
always @(posedge clk) prde_r2 <= #TCQ prde_r1;
wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en;
reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3;
always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde;
always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1;
always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2;
output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3;
assign phy_rddata_en_1 = phy_rddata_en_r1;
assign phy_rddata_en_2 = phy_rddata_en_r2;
assign phy_rddata_en_3 = phy_rddata_en_r3;
input [8:0] po_counter_read_val;
reg ocd_cntlr2stg2_dec_r;
output ocd_cntlr2stg2_dec;
assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r;
input po_rdy;
reg [3:0] po_rd_wait_ns, po_rd_wait_r;
always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns;
reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r;
always @(posedge clk) byte_r <= #TCQ byte_ns;
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
assign oclkdelay_calib_cnt = {1'b0, byte_r};
reg reset_scan_ns, reset_scan_r;
always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns;
output reset_scan;
assign reset_scan = reset_scan_r;
input scan_done;
reg [2:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
// Primary state machine.
always @(*) begin
// Default next state assignments.
byte_ns = byte_r;
complex_wrlvl_final_ns = complex_wrlvl_final_r;
lim_start_ns = lim_start_r;
oclkdelay_calib_done_ns = oclkdelay_calib_done_r;
complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r;
ocd_cntlr2stg2_dec_r = 1'b0;
po_rd_wait_ns = po_rd_wait_r;
if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1;
reset_scan_ns = reset_scan_r;
wrlvl_final_ns = wrlvl_final_r;
sm_ns = sm_r;
ocd_prech_req_ns= 1'b0;
if (rst == 1'b1) begin
// RESET next states
complex_oclkdelay_calib_done_ns = 1'b0;
complex_wrlvl_final_ns = 1'b0;
sm_ns = /*AK("READY")*/3'd0;
lim_start_ns = 1'b0;
oclkdelay_calib_done_ns = 1'b0;
reset_scan_ns = 1'b1;
wrlvl_final_ns = 1'b0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/3'd0: begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
if (oclkdelay_calib_start && ~oclkdelay_calib_done_r ||
complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r)
begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("LIMIT_START")*/3'd1:
sm_ns = /*AK("LIMIT_WAIT")*/3'd2;
/*AL("LIMIT_WAIT")*/3'd2:begin
if (lim_done) begin
lim_start_ns = 1'b0;
sm_ns = /*AK("SCAN")*/3'd3;
reset_scan_ns = 1'b0;
end
end
/*AL("SCAN")*/3'd3:begin
if (scan_done) begin
reset_scan_ns = 1'b1;
sm_ns = /*AK("COMPUTE")*/3'd4;
end
end
/*AL("COMPUTE")*/3'd4:begin
sm_ns = /*AK("PRECHARGE")*/3'd5;
ocd_prech_req_ns = 1'b1;
end
/*AL("PRECHARGE")*/3'd5:begin
if (prech_done) sm_ns = /*AK("DONE")*/3'd6;
end
/*AL("DONE")*/3'd6:begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
po_rd_wait_ns = 4'd8;
sm_ns = /*AK("STG2_2_ZERO")*/3'd7;
end else begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("STG2_2_ZERO")*/3'd7:
if (~|po_rd_wait_r && po_rdy)
if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1;
else begin
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
sm_ns = /*AK("READY")*/3'd0;
oclkdelay_calib_done_ns= 1'b1;
wrlvl_final_ns = 1'b1;
if (complex_oclkdelay_calib_start) begin
complex_oclkdelay_calib_done_ns = 1'b1;
complex_wrlvl_final_ns = 1'b1;
end
end else begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
po_rd_wait_ns = 4'd8;
end
end // else: !if(|po_counter_read_val[5:0])
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v4_0_ddr_phy_ocd_cntlr
// Local Variables:
// verilog-autolabel-prefix: "3'd"
// End:
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; string sep; for (const auto &x : v) os << sep << x, sep = , ; return os << } ; } template <typename T, size_t size> ostream &operator<<(ostream &os, const array<T, size> &arr) { os << { ; string sep; for (const auto &x : arr) os << sep << x, sep = , ; return os << } ; } template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int N, M; cin >> N >> M; vector<int> which_tower(N); vector<set<int>> towers(M); int answer = N - 1; for (int i = 0; i < N; i++) { cin >> which_tower[i]; which_tower[i]--; towers[which_tower[i]].insert(i); if (i > 0 && which_tower[i] == which_tower[i - 1]) answer--; } auto &&merge_into = [&](int from, int to) { if (towers[from].size() > towers[to].size()) swap(towers[from], towers[to]); for (auto &x : towers[from]) { answer -= int(towers[to].count(x - 1)); answer -= int(towers[to].count(x + 1)); } for (auto &x : towers[from]) towers[to].insert(x); towers[from].clear(); }; cout << answer << n ; for (int q = 0; q < M - 1; q++) { int a, b; cin >> a >> b; a--; b--; merge_into(b, a); cout << answer << n ; } } |
(* FASM_PARAMS="INV.TA1=TAS1;INV.TA2=TAS2;INV.TB1=TBS1;INV.TB2=TBS2;INV.BA1=BAS1;INV.BA2=BAS2;INV.BB1=BBS1;INV.BB2=BBS2;ZINV.QCK=Z_QCKS" *)
(* whitebox *)
module LOGIC_MACRO (QST, QDS, TBS, TAB, TSL, TA1, TA2, TB1, TB2, BAB, BSL, BA1, BA2, BB1, BB2, QDI, QEN, QCK, QRT, F1, F2, FS, TZ, CZ, QZ, FZ);
// =============== C_FRAG ===============
(* NO_SEQ *)
input wire TBS;
(* NO_SEQ *)
input wire TAB;
(* NO_SEQ *)
input wire TSL;
(* NO_SEQ *)
input wire TA1;
(* NO_SEQ *)
input wire TA2;
(* NO_SEQ *)
input wire TB1;
(* NO_SEQ *)
input wire TB2;
(* NO_SEQ *)
input wire BAB;
(* NO_SEQ *)
input wire BSL;
(* NO_SEQ *)
input wire BA1;
(* NO_SEQ *)
input wire BA2;
(* NO_SEQ *)
input wire BB1;
(* NO_SEQ *)
input wire BB2;
(* DELAY_CONST_TAB="{iopath_TAB_TZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_TZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_TZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_TZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_TZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_TZ}" *)
output wire TZ;
(* DELAY_CONST_TBS="{iopath_TBS_CZ}" *)
(* DELAY_CONST_TAB="{iopath_TAB_CZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_CZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_CZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_CZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_CZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_CZ}" *)
(* DELAY_CONST_BAB="{iopath_BAB_CZ}" *)
(* DELAY_CONST_BSL="{iopath_BSL_CZ}" *)
(* DELAY_CONST_BA1="{iopath_BA1_CZ}" *)
(* DELAY_CONST_BA2="{iopath_BA2_CZ}" *)
(* DELAY_CONST_BB1="{iopath_BB1_CZ}" *)
(* DELAY_CONST_BB2="{iopath_BB2_CZ}" *)
output wire CZ;
// Control parameters
parameter [0:0] TAS1 = 1'b0;
parameter [0:0] TAS2 = 1'b0;
parameter [0:0] TBS1 = 1'b0;
parameter [0:0] TBS2 = 1'b0;
parameter [0:0] BAS1 = 1'b0;
parameter [0:0] BAS2 = 1'b0;
parameter [0:0] BBS1 = 1'b0;
parameter [0:0] BBS2 = 1'b0;
// Input routing inverters
wire TAP1 = (TAS1) ? ~TA1 : TA1;
wire TAP2 = (TAS2) ? ~TA2 : TA2;
wire TBP1 = (TBS1) ? ~TB1 : TB1;
wire TBP2 = (TBS2) ? ~TB2 : TB2;
wire BAP1 = (BAS1) ? ~BA1 : BA1;
wire BAP2 = (BAS2) ? ~BA2 : BA2;
wire BBP1 = (BBS1) ? ~BB1 : BB1;
wire BBP2 = (BBS2) ? ~BB2 : BB2;
// 1st mux stage
wire TAI = TSL ? TAP2 : TAP1;
wire TBI = TSL ? TBP2 : TBP1;
wire BAI = BSL ? BAP2 : BAP1;
wire BBI = BSL ? BBP2 : BBP1;
// 2nd mux stage
wire TZI = TAB ? TBI : TAI;
wire BZI = BAB ? BBI : BAI;
// 3rd mux stage
wire CZI = TBS ? BZI : TZI;
// Output
assign TZ = TZI;
assign CZ = CZI;
// =============== Q_FRAG ===============
(* CLOCK *)
(* clkbuf_sink *)
input wire QCK;
// Cannot model timing, VPR currently does not support async SET/RESET
(* SETUP="QCK 1e-10" *)
(* NO_COMB *)
input wire QST;
// Cannot model timing, VPR currently does not support async SET/RESET
(* SETUP="QCK 1e-10" *)
(* NO_COMB *)
input wire QRT;
// No timing for QEN -> QZ in LIB/SDF
(* SETUP="QCK {setup_QCK_QEN}" *)
(* HOLD="QCK {hold_QCK_QEN}" *)
(* NO_COMB *)
input wire QEN;
(* SETUP="QCK {setup_QCK_QDI}" *)
(* HOLD="QCK {hold_QCK_QDI}" *)
(* NO_COMB *)
input wire QDI;
(* SETUP="QCK {setup_QCK_QDS}" *)
(* HOLD="QCK {hold_QCK_QDS}" *)
(* NO_COMB *)
input wire QDS;
(* CLK_TO_Q = "QCK {iopath_QCK_QZ}" *)
// The following DELAY_CONST_xx represent a combinational delay from a
// LOGIC input to the FF input QZI. Since when QDS=0 QZI is connected to
// CZI then let's assume that the delay is the same as to the CZ output.
(* DELAY_CONST_TBS="{iopath_TBS_CZ}" *)
(* DELAY_CONST_TAB="{iopath_TAB_CZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_CZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_CZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_CZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_CZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_CZ}" *)
(* DELAY_CONST_BAB="{iopath_BAB_CZ}" *)
(* DELAY_CONST_BSL="{iopath_BSL_CZ}" *)
(* DELAY_CONST_BA1="{iopath_BA1_CZ}" *)
(* DELAY_CONST_BA2="{iopath_BA2_CZ}" *)
(* DELAY_CONST_BB1="{iopath_BB1_CZ}" *)
(* DELAY_CONST_BB2="{iopath_BB2_CZ}" *)
// The following SETUP and HOLD should represent timings for the FF itself.
// However, these values are not given in any SDF as separate. So instead
// let's use QDI setup and hold timings.
(* SETUP="QCK {setup_QCK_QDI}" *)
(* HOLD="QCK {hold_QCK_QDI}" *)
output reg QZ;
input wire F1;
input wire F2;
input wire FS;
(* DELAY_CONST_F1="{iopath_F1_FZ}" *)
(* DELAY_CONST_F2="{iopath_F2_FZ}" *)
(* DELAY_CONST_FS="{iopath_FS_FZ}" *)
output wire FZ;
// Parameters
parameter [0:0] Z_QCKS = 1'b1;
// The QZI-mux
wire QZI = (QDS) ? QDI : CZI;
specify
(TBS => CZ) = (0,0);
(TAB => CZ) = (0,0);
(TSL => CZ) = (0,0);
(TA1 => CZ) = (0,0);
(TA2 => CZ) = (0,0);
(TB1 => CZ) = (0,0);
(TB2 => CZ) = (0,0);
(BAB => CZ) = (0,0);
(BSL => CZ) = (0,0);
(BA1 => CZ) = (0,0);
(BA2 => CZ) = (0,0);
(BB1 => CZ) = (0,0);
(BB2 => CZ) = (0,0);
(TAB => TZ) = (0,0);
(TSL => TZ) = (0,0);
(TA1 => TZ) = (0,0);
(TA2 => TZ) = (0,0);
(TB1 => TZ) = (0,0);
(TB2 => TZ) = (0,0);
(F1 => FZ) = (0,0);
(F2 => FZ) = (0,0);
(FS => FZ) = (0,0);
(QCK => QZ) = (0,0);
$setup(CZI, posedge QCK, "");
$hold(posedge QCK, CZI, "");
$setup(QDI, posedge QCK, "");
$hold(posedge QCK, QDI, "");
$setup(QST, posedge QCK, "");
$hold(posedge QCK, QST, "");
$setup(QRT, posedge QCK, "");
$hold(posedge QCK, QRT, "");
$setup(QEN, posedge QCK, "");
$hold(posedge QCK, QEN, "");
$setup(QDS, posedge QCK, "");
$hold(posedge QCK, QDS, "");
endspecify
// The flip-flop
initial QZ <= 1'b0;
always @(posedge QCK or posedge QST or posedge QRT) begin
if (QST)
QZ <= 1'b1;
else if (QRT)
QZ <= 1'b0;
else if (QEN)
QZ <= QZI;
end
// The F-mux
assign FZ = FS ? F2 : F1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; void add(int &a, int b) { a += b; if (a >= MOD) a -= MOD; } int n, K, C[1003][1003], fac[1003]; int dp[1003][1003][2][2], ans[1003]; int main() { scanf( %d%d , &n, &K); for (int i = 1; i <= n; i++) { C[i][0] = C[i][i] = 1; for (int j = 1; j < i; j++) add(C[i][j], C[i - 1][j]), add(C[i][j], C[i - 1][j - 1]); } fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = 1ll * fac[i - 1] * i % MOD; dp[0][0][1][0] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j <= i - 1; j++) for (int k = 0; k < 2; k++) for (int l = 0; l < 2; l++) if (dp[i - 1][j][k][l] > 0) { add(dp[i][j][l][0], dp[i - 1][j][k][l]); if (!k) add(dp[i][j + 1][l][0], dp[i - 1][j][k][l]); if (i < n) add(dp[i][j + 1][l][1], dp[i - 1][j][k][l]); } for (int i = 0; i <= n; i++) { for (int j = 0; j < 2; j++) for (int k = 0; k < 2; k++) add(ans[i], dp[n][i][j][k]); ans[i] = 1ll * ans[i] * fac[n - i] % MOD; } int cur = -1; for (int i = K + 1; i <= n; i++) { add(ans[K], (1ll * cur * C[i][K] % MOD * ans[i] % MOD + MOD) % MOD); cur *= -1; } printf( %d , ans[K]); } |
#include <bits/stdc++.h> using namespace std; const int N = 123456; int s[N]; int main() { int n, k, ans = 0; scanf( %d%d , &n, &k); for (int i = 0; i < n; ++i) { scanf( %d , s + i); } for (int i = 0; i < n - k; ++i) { ans = max(ans, s[i] + s[(n - k) * 2 - i - 1]); } printf( %d n , max(ans, s[n - 1])); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int T = 1; while (T--) { string s1, s2; cin >> s1 >> s2; long long int ans = 0; long long int i, j, k; i = j = k = 0; long long int n = s2.size(); long long int m = s1.size(); long long int count = 0; map<long long int, long long int> fs, ls; while (i < n && j < m) { if (s2[i] == s1[j]) { fs[i] = j; i++; j++; count = 0; } else { count++; j++; } ans = max(ans, count); } ans = max(ans, m - (j)); i = n - 1; j = m - 1; while (i >= 0 && j >= 0) { if (s2[i] == s1[j]) { i--; j--; ls[i] = j; count = 0; } else { count++; j--; } ans = max(ans, count); } for (auto x : fs) { ans = max(ans, ls[x.first] - x.second); } ans = max(ans, j + 1); cout << ans << n ; } return 0; } |
// these defines are only used for readability
`define INTEGER_INPUT_WIDTH ((STAGE_NUMBER+1) * 2)
`define INTEGER_OUTPUT_WIDTH `INTEGER_INPUT_WIDTH-2
`define REMAINDER_INPUT_WIDTH (((RADICAND_WIDTH/2) + 1) - STAGE_NUMBER)
`define RESULT_INPUT_WIDTH ((RADICAND_WIDTH/2) - STAGE_NUMBER - 1)
`define REMAINDER_OUTPUT_WIDTH (`REMAINDER_INPUT_WIDTH+1)
`define RESULT_OUTPUT_WIDTH `RESULT_INPUT_WIDTH+1
`define IS_FIRST_STAGE (STAGE_NUMBER == ((RADICAND_WIDTH/2) - 1))
`define IS_LAST_STAGE (STAGE_NUMBER == 0)
// this is the recursive sqrt remainder block
// you shouldn't have to do anything with this
module sqrt_remainder
#(
parameter RADICAND_WIDTH = 8,
parameter STAGE_NUMBER = 3
)
(
input wire [`INTEGER_INPUT_WIDTH-1:0] integer_input,
input wire [`REMAINDER_INPUT_WIDTH-1:0] remainder_previous,
input wire [(`RESULT_INPUT_WIDTH-1 + `IS_FIRST_STAGE):0] result_previous, // we need to force the first input to have a size of 1 for the first block
output reg [`INTEGER_OUTPUT_WIDTH-1:0] integer_output,
output reg signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder,
output reg [`RESULT_OUTPUT_WIDTH-1:0] result,
input wire reset,
input wire clk
);
reg phase; // state variable
// the following wires are used to force twos-complement arithmetic
wire signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_new_without_add;
assign remainder_new_without_add = {
remainder_previous[`REMAINDER_INPUT_WIDTH-2:0], // drop the sign bit
integer_input[{STAGE_NUMBER, 1'b1}], // integer_input[2 * bit + 1]
integer_input[{STAGE_NUMBER, 1'b0}] // integer_input[2 * bit]
};
wire signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_greater_than_or_equal_to_0_subtractor;
wire signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_less_than_0_addition;
assign remainder_greater_than_or_equal_to_0_subtractor = {result_previous, 2'b01};
assign remainder_less_than_0_addition = {result_previous, 2'b11};
reg signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_delay;
reg [`INTEGER_INPUT_WIDTH-1:0] integer_output_delay;
reg [(`RESULT_INPUT_WIDTH-1 + `IS_FIRST_STAGE):0] result_previous_delay;
always @(posedge clk) begin
//if (reset == 1'b0) phase <= 0;
//else begin
//if (phase == 1'b0) begin
// phase 1: calculate new remainder
if (remainder_previous[`REMAINDER_INPUT_WIDTH-1] == 1'b0) begin // if sign bit indicates the number is positive
remainder_delay <= remainder_new_without_add - remainder_greater_than_or_equal_to_0_subtractor;
end else begin
remainder_delay <= remainder_new_without_add + remainder_less_than_0_addition;
end
remainder <= remainder_delay;
// save the integer into our local shift register, while dropping the top two bits
// we need to force the output to have a size of 1 for the last block in the chain
integer_output_delay <= integer_input[(`INTEGER_OUTPUT_WIDTH-1 + `IS_LAST_STAGE):0];
integer_output <= integer_output_delay;
//end else begin
result_previous_delay <= result_previous;
// phase 2: calculate new result
if (remainder_delay[`REMAINDER_OUTPUT_WIDTH-1] != 1'b1) begin // if it is positive
result <= {result_previous_delay, 1'b1};
end else begin
result <= {result_previous_delay, 1'b0};
if (`IS_LAST_STAGE) remainder <= remainder_delay + {result_previous_delay, 2'b01};
end
//end
//phase <= ~phase;
//end
end
// initial begin
// $display("sqrt_remainder block: RADICAND_WIDTH: %d, STAGE_NUMBER: %d (IS_FIRST_STAGE: %d, IS_LAST_STAGE: %d)", RADICAND_WIDTH, STAGE_NUMBER, `IS_FIRST_STAGE, `IS_LAST_STAGE);
// $display("\tINTEGER_INPUT_WIDTH: \t\t%d", `INTEGER_INPUT_WIDTH);
// $display("\tINTEGER_OUTPUT_WIDTH: \t\t%d", `INTEGER_OUTPUT_WIDTH);
// $display("\tREMAINDER_INPUT_WIDTH: \t\t%d", `REMAINDER_INPUT_WIDTH);
// $display("\tREMAINDER_OUTPUT_WIDTH: \t\t%d", `REMAINDER_OUTPUT_WIDTH);
// $display("\tRESULT_INPUT_WIDTH: \t\t%d", `RESULT_INPUT_WIDTH);
// $display("\tRESULT_OUTPUT_WIDTH: \t\t%d", `RESULT_OUTPUT_WIDTH);
// end
endmodule |
#include <bits/stdc++.h> using namespace std; int n; vector<int> a; vector<stack<int>> ids; vector<int> b; string answer; int segtree_size; template <typename T> struct segtree { int segtree_size; vector<T> segtree; T identity; T (*UpdateFn)(T, T); void InitSegtree(int main_size, T (*UpdateFunction)(T, T), T fun_identity) { segtree_size = 1; while (segtree_size < main_size) segtree_size *= 2; segtree_size *= 2; segtree.resize(segtree_size); UpdateFn = UpdateFunction; this->identity = fun_identity; } void UpdateAllParents() { for (int i = segtree_size / 2 - 1; i > 0; i--) segtree[i] = UpdateFn(segtree[i * 2], segtree[i * 2 + 1]); } void ChangeValue(int index, T value) { segtree[index + segtree_size / 2] = value; } T GetValue(int index) { return segtree[index + segtree_size / 2]; } void Update(int pos, T value) { for (segtree[pos += segtree_size / 2] = value; pos > 1; pos /= 2) segtree[pos / 2] = UpdateFn(segtree[pos], segtree[pos ^ 1]); } T Query(int start, int finish) { T ans = this->identity; for (start += segtree_size / 2, finish += segtree_size / 2; start < finish; start /= 2, finish /= 2) { if (start % 2 == 1) ans = UpdateFn(ans, segtree[start++]); if (finish % 2 == 0) ans = UpdateFn(ans, segtree[finish--]); } return UpdateFn(ans, segtree[start]); } void Destroy() { segtree.clear(); } }; struct segtree<int> tree; void In() { cin >> n; a.resize(n); ids.resize(n + 1); b.resize(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; } void Solve() { tree.InitSegtree( n + 1, [](int a, int b) -> int { return max(a, b); }, INT_MIN); for (int i = 0; i < n; i++) tree.ChangeValue(i, a[i]); tree.UpdateAllParents(); answer = NO ; for (int i = 0; i < n; i++) ids[a[i]].push(i); for (int i = n - 1; i >= 0; i--) { if (ids[b[i]].empty()) return; int a_idx = ids[b[i]].top(); ids[b[i]].pop(); if (tree.Query(a_idx + 1, n) > b[i]) return; tree.Update(a_idx, 0); } answer = YES ; } void Out() { cout << answer << endl; tree.Destroy(); a.clear(); ids.clear(); b.clear(); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { In(); Solve(); Out(); } return 0; } |
`define ROMMatrix_NOP 4'h0
`define ROMMatrix_LDR 4'h1
`define ROMMatrix_LDC 4'h2
`define ROMMatrix_State_Reset 2'h0
`define ROMMatrix_State_Ready 2'h1
`define ROMMatrix_State_Error 2'h2
module ROMMatrix(clock,reset,inst,inst_en,out,rom_addr,rom_data_o);
parameter ROMRows = 8;
parameter ROMCols = 8;
parameter ROMDataSize = 8;
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [ROMDataSize-1:0] out;
output wire [15:0] rom_addr;
input wire [ROMDataSize-1:0] rom_data_o;
reg [1:0] s_State;
reg [7:0] s_ROMRow;
reg [7:0] s_ROMCol;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign rom_addr = s_ROMRow * ROMCols + s_ROMCol;
assign out = rom_data_o;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
always @ (posedge clock) begin
if (reset) begin
s_State <= `ROMMatrix_State_Reset;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
else begin
case (s_State)
`ROMMatrix_State_Reset: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
`ROMMatrix_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`ROMMatrix_NOP: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= s_ROMRow;
s_ROMCol <= s_ROMCol;
end
`ROMMatrix_LDR: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= w_InstImm;
s_ROMCol <= s_ROMCol;
end
`ROMMatrix_LDC: begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= s_ROMRow;
s_ROMCol <= w_InstImm;
end
default: begin
s_State <= `ROMMatrix_State_Error;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `ROMMatrix_State_Ready;
s_ROMRow <= s_ROMRow;
s_ROMCol <= s_ROMCol;
end // else: !if(inst_en)
end // case: `ROMMatrix_State_Ready
`ROMMatrix_State_Error: begin
s_State <= `ROMMatrix_State_Error;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
default: begin
s_State <= `ROMMatrix_State_Error;
s_ROMRow <= 0;
s_ROMCol <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`ROMMatrix_NOP: begin
$sformat(d_Input,"EN NOP");
end
`ROMMatrix_LDR: begin
$sformat(d_Input,"EN (LDR %D)",w_InstImm);
end
`ROMMatrix_LDC: begin
$sformat(d_Input,"EN (LDC %D)",w_InstImm);
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`ROMMatrix_State_Reset: begin
$sformat(d_State,"X");
end
`ROMMatrix_State_Ready: begin
$sformat(d_State,"R %D %D %D",s_ROMRow,s_ROMCol,rom_addr);
end
`ROMMatrix_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // ROMMatrix
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b; cin >> a; set<int> s; while (a--) { int b; cin >> b; s.insert(b); } cout << s.size() << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } int q; cin >> q; vector<int> ta(n, -1); vector<int> payouts(q, 0); for (int i = 0; i < q; i++) { int k, p, x; cin >> k; if (k == 1) { cin >> p >> x; a[p - 1] = x; ta[p - 1] = i; } else { cin >> x; payouts[i] = x; } } vector<int> maxpayouts(q, payouts[q - 1]); for (int i = q - 2; i >= 0; i--) { maxpayouts[i] = max(maxpayouts[i + 1], payouts[i]); } maxpayouts.push_back(0); for (int i = 0; i < n; i++) { int res = max(maxpayouts[ta[i] + 1], a[i]); cout << res << ; } cout << n ; } |
#include <bits/stdc++.h> using namespace std; using namespace std; struct my { int a; double b; }; bool Cmp(my a, my b) { return a.b <= b.b; } int main() { int n, m; cin >> n >> m; my mine[n]; for (int i = 0; i < n; ++i) { int a; cin >> a; double b; cin >> b; mine[i].a = a; mine[i].b = b; } sort(mine, mine + n, Cmp); int ord[n]; for (int i = 0; i < n; ++i) { ord[i] = mine[i].a; } int dp[n]; for (int i = 0; i < n; ++i) { dp[i] = 1; } for (int i = 0; i < n; i++) { for (int j = i - 1; j >= 0; j--) { if (ord[j] <= ord[i]) { dp[i] = max(dp[j] + 1, dp[i]); } } } cout << n - *max_element(dp, dp + n) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> v; vector<int> ans_lis; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; v.emplace_back(x); } sort(v.begin(), v.end()); for (int i = (int)v.size() - 1; i >= 0; i--) { if (i % 2 == 0) { ans_lis.insert(ans_lis.begin(), v[i]); } else ans_lis.emplace_back(v[i]); } bool flag = true; if (ans_lis[0] >= ans_lis.back() + ans_lis[1]) flag = false; if (ans_lis.back() >= ans_lis[0] + ans_lis[(int)ans_lis.size() - 2]) flag = false; for (int i = 1; i + 1 < (int)ans_lis.size() && flag; i++) { if (ans_lis[i] >= ans_lis[i + 1] + ans_lis[i - 1]) flag = false; } if (!flag) cout << NO << endl; else { cout << YES << endl; for (int i = 0; i < (int)ans_lis.size(); i++) cout << ans_lis[i] << ; cout << endl; } return 0; } |
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: example.v
// Version: 1.0
// Date: 30 May 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// example Your first system with the M32632 CPU
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module example ( CLK, RESET_N, NMI_N, INT_N, IN_REG, OUT_REG);
input CLK;
input RESET_N;
input NMI_N;
input INT_N;
input [7:0] IN_REG;
output [7:0] OUT_REG;
reg nmi_reg,int_reg;
wire IC_MDONE;
wire DC_MDONE;
wire ENWR;
wire WAMUX;
wire [11:2] WADDR;
wire [31:0] DRAM_Q;
wire [2:0] IWCTRL;
wire [2:0] DWCTRL;
wire IC_ACC;
wire [27:0] IDRAM_ADR;
wire DC_ACC;
wire DC_WR;
wire [27:0] DRAM_ADR;
wire [35:0] DRAM_DI;
wire [31:0] IO_A;
wire [31:0] IO_DI;
wire [3:0] IO_BE;
wire IO_RD;
wire IO_WR;
wire IO_READY;
wire ENDRAM;
wire [31:0] IO_Q;
wire W_OUT_REG;
wire RST_N;
wire [31:0] BOOT_DAT;
wire [31:0] STAT_DAT;
wire [7:0] IN_DAT;
wire [7:0] STATSIGS;
wire COP_GO;
wire [23:0] COP_OP;
wire [127:0] COP_OUT;
wire COP_DONE;
wire [63:0] COP_IN;
M32632 CPU(
// ++++++++++ Basic Signals
.BCLK(CLK),
.MCLK(~CLK),
.WRCFG(1'b1),
.BRESET(RST_N),
.NMI_N(nmi_reg),
.INT_N(int_reg),
.STATUS(),
.ILO(),
.STATSIGS(STATSIGS),
// +++++++++ General Purpose Interface
.IO_WR(IO_WR),
.IO_RD(IO_RD),
.IO_A(IO_A),
.IO_BE(IO_BE),
.IO_DI(IO_DI),
.IO_Q(IO_Q),
.IO_READY(IO_READY),
// +++++++++ DRAM Interface In
.ENDRAM(ENDRAM),
.IC_MDONE(IC_MDONE),
.DC_MDONE(DC_MDONE),
.ENWR(ENWR),
.WAMUX(WAMUX),
.WADDR(WADDR),
.DRAM_Q(DRAM_Q),
.DWCTRL(DWCTRL),
.IWCTRL(IWCTRL),
// +++++++++ DRAM Interface Out
.IC_ACC(IC_ACC),
.IDRAM_ADR(IDRAM_ADR),
.DC_ACC(DC_ACC),
.DC_WR(DC_WR),
.DRAM_ADR(DRAM_ADR),
.DRAM_DI(DRAM_DI),
// ++++++++++ DMA Interface
.HOLD(1'b1),
.HLDA(),
.FILLRAM(1'b0),
.DMA_AA(24'd0),
// ++++++++++ Coprocessor Interface
.COP_GO(COP_GO),
.COP_OP(COP_OP),
.COP_OUT(COP_OUT),
.COP_DONE(COP_DONE),
.COP_IN(COP_IN));
ex_io_bus_ctrl u_bus_ctrl(
.CLK(CLK),
.RESET_N(RESET_N),
.RST_N(RST_N),
.ENDRAM(ENDRAM),
.IO_WR(IO_WR),
.IO_RD(IO_RD),
.IO_A(IO_A[31:28]),
.IO_BE(IO_BE),
.IO_Q(IO_Q),
.IO_READY(IO_READY),
.W_OUT_REG(W_OUT_REG),
.IN_DAT(IN_DAT),
.BOOT_DAT(BOOT_DAT),
.STAT_DAT(STAT_DAT));
ex_in_reg u_in_reg(
.CLK(CLK),
.IN_REG(IN_REG),
.IN_DAT(IN_DAT));
ex_out_reg u_out_reg(
.CLK(CLK),
.OUT_REG(OUT_REG),
.W_OUT_REG(W_OUT_REG),
.DIN(IO_DI));
ex_boot_rom u_boot_rom(
.CLK(CLK),
.ADDR(IO_A[9:2]),
.DATA(BOOT_DAT));
ex_statcou u_statcou(
.CLK(CLK),
.RST_N(RST_N),
.STATSIGS(STATSIGS),
.ADDR(IO_A[4:2]),
.DATA(STAT_DAT));
ex_copro u_copro(
.CLK(CLK),
.COP_GO(COP_GO),
.COP_OP(COP_OP),
.COP_INP(COP_OUT),
.COP_DONE(COP_DONE),
.COP_OUTP(COP_IN));
ex_dram_emul u_dram_emul(
.MCLK(CLK),
.RST_N(RST_N),
.IC_ACC(IC_ACC),
.IDRAM_ADR(IDRAM_ADR),
.DC_ACC(DC_ACC),
.DC_WR(DC_WR),
.DRAM_ADR(DRAM_ADR),
.DRAM_DI(DRAM_DI),
.IC_MDONE(IC_MDONE),
.DC_MDONE(DC_MDONE),
.ENWR(ENWR),
.WAMUX(WAMUX),
.WADDR(WADDR),
.MEM_Q(DRAM_Q),
.DWCTRL(DWCTRL),
.IWCTRL(IWCTRL) );
always @(posedge CLK) // recommended to synchronize this signals
begin
nmi_reg <= NMI_N;
int_reg <= INT_N;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int C = 20, A = 40; int n, liq; int dp[1 << C]; long long k[A]; int main() { scanf( %d %d , &n, &liq); for (int i = 0; i < n; i++) for (int j = 0, first; j < n; j++) cin >> first, k[i] |= (long long)(first || i == j) << j; for (int i = 1; i < (1 << max(0, n - C)); i++) { int first = i; for (int j = 0; j < C; j++) if ((i >> j) & 1) first &= k[j + C] >> C; if (first == i) dp[i] = __builtin_popcount(i); } for (int i = 1; i < (1 << max(0, n - C)); i++) for (int j = 0; j < C; j++) if ((i >> j) & 1) dp[i] = max(dp[i], dp[i ^ (1 << j)]); int ans = 0; for (int i = 0; i < (1 << min(C, n)); i++) { int first = i, second = (1 << max(0, n - C)) - 1; for (int j = 0; j < min(C, n); j++) if ((i >> j) & 1) first &= k[j] & ((1 << C) - 1), second &= k[j] >> C; if (first != i) continue; ans = max(ans, __builtin_popcount(i) + dp[second]); } long double l = liq, a = ans; cout << fixed << setprecision(7) << (l * l * (a - 1)) / 2 / a << endl; } |
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > v; bool cmp(pair<long long, long long> &a, pair<long long, long long> &b) { if (a.first == b.first) return a.second < b.second; return b.first < a.first; } long long func(pair<long long, long long> &a, pair<long long, long long> &b, long long d) {} int main() { long long n; long long m, d; scanf( %lld %lld %lld , &n, &m, &d); pair<long long, long long> a[n]; pair<long long, long long> b[m]; for (long long i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } sort(a, a + n, cmp); for (long long i = 0; i < m; i++) { cin >> b[i].first >> b[i].second; } sort(b, b + m, cmp); long long posi = 1, totalw = 0, posj = 1, totals = 0; totalw = a[0].second + b[0].second; totals = a[0].first + b[0].first; if (totalw > d) return cout << 0, 0; while (posj < m && totalw + b[posj].second <= d) { totalw += b[posj].second; totals += b[posj].first; posj++; } long long mx = totals; while (posi < n) { totalw += a[posi].second; totals += a[posi].first; posi++; while (totalw > d) { if (posj <= 1) return cout << mx, 0; posj--; totals -= b[posj].first; totalw -= b[posj].second; } mx = max(mx, totals); } cout << mx << endl; } |
#include <bits/stdc++.h> using namespace std; int cnt(vector<vector<pair<int, int>>>& graph, int cur, int parent, int val) { int ans = 1; for (auto p : graph[cur]) { if (p.first == parent) continue; if (p.second == val) ans += cnt(graph, p.first, cur, val); } return ans; } void fill(vector<vector<pair<int, int>>>& graph, vector<pair<bool, bool>>& visited, vector<pair<int, int>>& cnt_vec, int cur, int parent, int val, int num) { if (val == 0) { visited[cur].first = true; cnt_vec[cur].first = num; } else { visited[cur].second = true; cnt_vec[cur].second = num; } for (auto p : graph[cur]) { if (p.first == parent) continue; if (p.second == val) fill(graph, visited, cnt_vec, p.first, cur, val, num); } } int process(vector<vector<pair<int, int>>>& graph, vector<pair<bool, bool>>& visited, vector<pair<int, int>>& cnt_vec, int start, int val) { int n = graph.size(), ans; ans = cnt(graph, start, -1, val); fill(graph, visited, cnt_vec, start, -1, val, ans); return ans; } int main() { int n, i, a, b, val, tmp; long long ans = 0; cin >> n; vector<vector<pair<int, int>>> graph(n + 1); for (i = 0; i < n - 1; ++i) { cin >> a >> b >> val; graph[a].push_back({b, val}); graph[b].push_back({a, val}); } vector<pair<int, int>> cnt_vec(n + 1, {0, 0}); vector<pair<bool, bool>> visited(n + 1, {false, false}); vector<int> components; for (i = 1; i <= n; ++i) { if (!visited[i].first) { tmp = process(graph, visited, cnt_vec, i, 0); if (tmp > 1) components.push_back(tmp); } if (!visited[i].second) { tmp = process(graph, visited, cnt_vec, i, 1); if (tmp > 1) components.push_back(tmp); } } for (auto num : components) ans += 1LL * num * (num - 1); for (i = 1; i <= n; ++i) ans += 1LL * (cnt_vec[i].first - 1) * (cnt_vec[i].second - 1); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, adj[25], pode[1 << 23]; int main() { scanf( %d%d , &n, &m); if (m == n * (n - 1) / 2) { puts( 0 ); return 0; } for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) adj[i] |= 1 << i, pode[1 << i] = 1; for (__typeof(m) i = (0) - ((0) > (m)); i != (m) - ((0) > (m)); i += 1 - 2 * ((0) > (m))) { int u, v; scanf( %d%d , &u, &v); u--, v--; adj[u] |= 1 << v; adj[v] |= 1 << u; } int ans = (1 << n) - 1; for (__typeof((1 << n)) i = (1) - ((1) > ((1 << n))); i != ((1 << n)) - ((1) > ((1 << n))); i += 1 - 2 * ((1) > ((1 << n)))) if (__builtin_popcount(i) < __builtin_popcount(ans) && pode[i]) { int cur = 0; for (__typeof(n) j = (0) - ((0) > (n)); j != (n) - ((0) > (n)); j += 1 - 2 * ((0) > (n))) if (i & (1 << j)) cur |= adj[j]; if (__builtin_popcount(cur) == n) ans = i; for (__typeof(n) j = (0) - ((0) > (n)); j != (n) - ((0) > (n)); j += 1 - 2 * ((0) > (n))) if ((cur & (1 << j)) && !(i & (1 << j))) pode[i | (1 << j)] = 1; } printf( %d n , __builtin_popcount(ans)); for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) if (ans & (1 << i)) printf( %d , i + 1); printf( n ); } |
#include <bits/stdc++.h> using namespace std; unordered_map<int, int> mp; int cnt[200005]; int a[200005]; int num[200005]; int l, r, t; int tot = 0; int lz[200005]; int ans[200005]; int A, B; int be[200005]; struct Query { int l, r, id, t; Query() {} Query(int _l, int _r, int _id, int _t) { l = _l, r = _r, id = _id, t = _t; } bool operator<(const Query &rhs) const { return be[l] == be[rhs.l] ? (be[r] == be[rhs.r] ? t < rhs.t : r < rhs.r) : l < rhs.l; } } q[200005]; struct Change { int x, y, lz; Change() {} Change(int _x, int _y, int _lz) { x = _x, y = _y, lz = _lz; } } p[200005]; int getid(int x) { if (!mp.count(x)) mp[x] = ++tot; return mp[x]; } void add(int x, int k) { if (num[x]) cnt[num[x]]--; num[x] += k; if (num[x]) cnt[num[x]]++; } void change(int x, int k) { if (l <= x && r >= x) { add(a[x], -1); add(k, 1); } a[x] = k; } int getres() { for (int i = 1;; i++) { if (cnt[i] == 0) return i; } } int main() { int n, m; cin >> n >> m; int len = pow(n, 0.6666); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); lz[i] = a[i] = getid(x); be[i] = (i - 1) / len + 1; } for (int i = 1; i <= m; i++) { int op, x, y; scanf( %d%d%d , &op, &x, &y); if (op == 1) { q[++A] = Query(x, y, A, B); } else { y = getid(y); p[++B] = Change(x, y, lz[x]); lz[x] = y; } } sort(q + 1, q + 1 + A); l = 1, r = 0, t = 0; for (int i = 1; i <= A; i++) { while (t < q[i].t) change(p[t + 1].x, p[t + 1].y), t++; while (t > q[i].t) change(p[t].x, p[t].lz), t--; while (l < q[i].l) add(a[l], -1), l++; while (l > q[i].l) add(a[l - 1], 1), l--; while (r < q[i].r) add(a[r + 1], 1), r++; while (r > q[i].r) add(a[r], -1), r--; ans[q[i].id] = getres(); } for (int i = 1; i <= A; i++) { cout << ans[i] << endl; } } |
`include "defines.v"
`include "connectRouter_2SNoBuffer.v"
`timescale 1ns/1ps
module tb_connectRouters(
);
reg clk, rst;
reg `control_w port_in, inj;
reg bfull;
wire `control_w port_out, eject;
wire accept, push;
connectRouter_nobuffer r(
.clk(clk),
.rst(rst),
.port_in(port_in),
.inj(inj),
.port_out(port_out),
.accept(accept),
.bfull(bfull),
.eject(eject),
.push(push)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
bfull = 0;
port_in = 144'h011111111111111111111111111111111852; // MSHR 1; valid / seq 0; source 5; dest 7
// inj = 144'h0000000000000000000000000000000fffff;
inj = 144'h0;
#1;
clk = 1;
#1;
clk = 0;
port_in = 144'h0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = 0\n, port_out %04x\n, accept %04x\n, eject %04x\n, push %04x\n",
port_out, accept, eject, push);
#1;
clk = 1;
#1;
clk = 0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = 1\n, port_out %04x\n, accept %04x\n, eject %04x\n, push %04x\n",
port_out, accept, eject, push);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ii = pair<ll, ll>; using vi = vector<ll>; using vb = vector<bool>; using vvi = vector<vi>; using vii = vector<ii>; using vvii = vector<vii>; const int INF = 2000000000; const ll LLINF = 9000000000000000000; int main() { int N; scanf( %d , &N); vi A(N, 0LL), B(N, 0LL); for (int i = 0; i < N; ++i) { int v; scanf( %d , &v); A[i] = ll(v); B[i] = A[i] + (i > 0 ? B[i - 1] : 0LL); } ll mx = 0LL; for (int i = 0; i < N; ++i) mx += ll(i + 1) * A[i]; vii lns; vector<ld> start(1, -std::numeric_limits<ld>::infinity()); lns.push_back({0, 0}); for (int i = 0; i < N; ++i) { while (lns.size() > 1 && start.back() >= ld(-B[i] - lns.back().second) / ld(lns.back().first - i - 1)) { lns.pop_back(); start.pop_back(); } start.push_back(ld(-B[i] - lns.back().second) / ld(lns.back().first - i - 1)); lns.push_back({i + 1, -B[i]}); } ll bestchange = 0LL; int D = 5; for (int i = 0; i < N; ++i) { ll change = B[i] - A[i] * ll(i + 1); int l = 0, r = int(lns.size()) - 1; while (l < r) { int m = (l + r + 1) / 2; if (start[m] > A[i]) r = m - 1; else l = m; } for (int j = max(0, l - D); j < min(int(lns.size()), l + D + 1); ++j) { if (bestchange < change + A[i] * lns[j].first + lns[j].second) { bestchange = change + A[i] * lns[j].first + lns[j].second; } } } cout << (mx + bestchange) << endl; return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_upconfig_fix_3451_v6.v
// Version : 2.4
//--
//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_upconfig_fix_3451_v6 # (
parameter UPSTREAM_FACING = "TRUE",
parameter PL_FAST_TRAIN = "FALSE",
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter TCQ = 1
)
(
input pipe_clk,
input pl_phy_lnkup_n,
input [5:0] pl_ltssm_state,
input pl_sel_lnk_rate,
input [1:0] pl_directed_link_change,
input [3:0] cfg_link_status_negotiated_width,
input [15:0] pipe_rx0_data,
input [1:0] pipe_rx0_char_isk,
output filter_pipe
);
reg reg_filter_pipe;
reg [15:0] reg_tsx_counter;
wire [15:0] tsx_counter;
wire [5:0] cap_link_width;
// Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
// the core to see the TS1s on all the lanes being configured at the same time
// R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
// 225 pipe_clk cycles-sim_fast_train
// 60000 pipe_clk cycles-without sim_fast_train
// Not taking any action when PLDIRECTEDLINKCHANGE is set
// Detect xx, COM then PAD,xx or COM,PAD then PAD,xx
// data0 will be the first symbol on lane 0, data1 will be the next symbol.
// Don't look for PAD on data1 since it's unnecessary.
// COM=0xbc and PAD=0xf7 (and isk).
// detect if (data & 0xb4) == 0xb4 and isk, and then
// if (data & 0x4b) == 0x08 or 0x43. This distinguishes COM and PAD, using
// no more than a 6-input LUT, so should be "free".
reg reg_filter_used, reg_com_then_pad;
reg reg_data0_b4, reg_data0_08, reg_data0_43;
reg reg_data1_b4, reg_data1_08, reg_data1_43;
reg reg_data0_com, reg_data1_com, reg_data1_pad;
wire data0_b4 = pipe_rx0_char_isk[0] &&
((pipe_rx0_data[7:0] & 8'hb4) == 8'hb4);
wire data0_08 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h08);
wire data0_43 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h43);
wire data1_b4 = pipe_rx0_char_isk[1] &&
((pipe_rx0_data[15:8] & 8'hb4) == 8'hb4);
wire data1_08 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h08);
wire data1_43 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h43);
wire data0_com = reg_data0_b4 && reg_data0_08;
wire data1_com = reg_data1_b4 && reg_data1_08;
wire data0_pad = reg_data0_b4 && reg_data0_43;
wire data1_pad = reg_data1_b4 && reg_data1_43;
wire com_then_pad0 = reg_data0_com && reg_data1_pad && data0_pad;
wire com_then_pad1 = reg_data1_com && data0_pad && data1_pad;
wire com_then_pad = (com_then_pad0 || com_then_pad1) && ~reg_filter_used;
wire filter_used = (pl_ltssm_state == 6'h20) &&
(reg_filter_pipe || reg_filter_used);
always @(posedge pipe_clk) begin
reg_data0_b4 <= #TCQ data0_b4;
reg_data0_08 <= #TCQ data0_08;
reg_data0_43 <= #TCQ data0_43;
reg_data1_b4 <= #TCQ data1_b4;
reg_data1_08 <= #TCQ data1_08;
reg_data1_43 <= #TCQ data1_43;
reg_data0_com <= #TCQ data0_com;
reg_data1_com <= #TCQ data1_com;
reg_data1_pad <= #TCQ data1_pad;
reg_com_then_pad <= #TCQ (~pl_phy_lnkup_n) ? com_then_pad : 1'b0;
reg_filter_used <= #TCQ (~pl_phy_lnkup_n) ? filter_used : 1'b0;
end
always @ (posedge pipe_clk) begin
if (pl_phy_lnkup_n) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end else if ((pl_ltssm_state == 6'h20) &&
reg_com_then_pad &&
(cfg_link_status_negotiated_width != cap_link_width) &&
(pl_directed_link_change[1:0] == 2'b00)) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b1;
end else if (filter_pipe == 1'b1) begin
if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd800 : 16'd400)) begin
reg_tsx_counter <= #TCQ tsx_counter + 1'b1;
reg_filter_pipe <= #TCQ 1'b1;
end else begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end
end
end
assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe;
assign tsx_counter = reg_tsx_counter;
assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg onebit /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] count /*verilator public_flat_rd */;
reg [31:0] half_count /*verilator public_flat_rd */;
reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
integer status;
sub sub();
// Test loop
initial begin
count = 0;
onebit = 1'b0;
fourthreetwoone[3] = 0; // stop icarus optimizing away
text_byte = "B";
text_half = "Hf";
text_word = "Word";
text_long = "Long64b";
text = "Verilog Test module";
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("%%Info: Checking results\n");
if (onebit != 1'b1) $stop;
if (quads[2] != 62'h12819213_abd31a1c) $stop;
if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
if (text_byte != "A") $stop;
if (text_half != "T2") $stop;
if (text_word != "Tree") $stop;
if (text_long != "44Four44") $stop;
if (text != "lorem ipsum") $stop;
end
always @(posedge clk) begin
count <= count + 2;
if (count[1])
half_count <= half_count + 2;
if (count == 1000) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
genvar i;
generate
for (i=1; i<=128; i=i+1) begin : arr
arr #(.LENGTH(i)) arr();
end endgenerate
endmodule : t
module sub;
reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/;
`ifdef iverilog
// stop icarus optimizing signals away
wire redundant = subsig1 | subsig2;
`endif
endmodule : sub
module arr;
parameter LENGTH = 1;
reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
reg check /*verilator public_flat_rw*/;
reg verbose /*verilator public_flat_rw*/;
initial begin
sig = {LENGTH{1'b0}};
rfr = {LENGTH{1'b0}};
end
always @(posedge check) begin
if (verbose) $display("%m : %x %x", sig, rfr);
if (check && sig != rfr) $stop;
check <= 0;
end
endmodule : arr
|
<?
if (elem.Label="")
panic("err_romNeedsALabelToBeExported");
romMaxSize := 1 << elem.AddrBits;
data:=elem.Data;
if (elem.autoReload) {
data=loadHex(elem.lastDataFile, elem.Bits);
}
romSize := sizeOf(data);
moduleName = format("%s_%dX%d_%s", moduleName, romMaxSize, elem.Bits, identifier(elem.Label));
dBitRange := format("[%d:0]", elem.Bits - 1);
aBitRange := format("[%d:0]", elem.AddrBits - 1);
?>module <?= moduleName ?> (
input <?= aBitRange ?> A,
input sel,
output reg <?= dBitRange ?> D
);
reg <?= dBitRange ?> my_rom [0:<?= (romSize - 1) ?>];
always @ (*) begin
if (~sel)
D = <?= elem.Bits ?>'hz;<?
if (romSize < romMaxSize) {
lastAddr := format("%d'h%x", elem.AddrBits, romSize - 1); ?>
else if (A > <?= lastAddr ?>)
D = <?= elem.Bits ?>'h0;<?
} ?>
else
D = my_rom[A];
end
initial begin<?
for (i := 0; i < romSize; i++) { ?>
my_rom[<?= i ?>] = <?= format("%d'h%x", elem.Bits, data[i]) ?>;<?
} ?>
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; int m, k, n, s, tot, del, a[N], b[N], c[N], d[N]; int main() { scanf( %d%d%d%d , &m, &k, &n, &s); del = m - k * n; for (int i = 1; i <= m; i++) scanf( %d , &a[i]); for (int i = 1, x; i <= s; i++) { scanf( %d , &x); b[x]++; if (b[x] == 1) tot++; } for (int l = 1, r = 1; r <= m; r++) { ++c[a[r]]; tot -= c[a[r]] == b[a[r]]; while (!tot && r - l + 1 > k && l <= m && c[a[l]] > b[a[l]]) --c[a[l]], l++; if (!tot && r - l + 1 >= k) { int del2 = (l - 1) % k + r - l + 1 - k; if (del2 > del) continue; printf( %d n , del2); if (!del2) return 0; for (int i = 1; i <= (l - 1) % k && del2; i++) printf( %d , i), del2--; for (int i = l; i <= r && del2; i++) if (d[a[i]] + 1 > b[a[i]]) printf( %d , i), del2--; else d[a[i]]++; return 0; } } printf( -1 ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_2_V
`define SKY130_FD_SC_LP__O21AI_2_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_2_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module gpio_atr
#(parameter BASE = 0,
parameter WIDTH = 32)
(input clk, input reset,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input rx, input tx,
inout [WIDTH-1:0] gpio,
output reg [31:0] gpio_readback
);
wire [WIDTH-1:0] ddr, in_idle, in_tx, in_rx, in_fdx;
reg [WIDTH-1:0] rgpio, igpio;
setting_reg #(.my_addr(BASE+0), .width(WIDTH)) reg_idle
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
.out(in_idle),.changed());
setting_reg #(.my_addr(BASE+1), .width(WIDTH)) reg_rx
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
.out(in_rx),.changed());
setting_reg #(.my_addr(BASE+2), .width(WIDTH)) reg_tx
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
.out(in_tx),.changed());
setting_reg #(.my_addr(BASE+3), .width(WIDTH)) reg_fdx
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
.out(in_fdx),.changed());
setting_reg #(.my_addr(BASE+4), .width(WIDTH)) reg_ddr
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
.out(ddr),.changed());
always @(posedge clk)
case({tx,rx})
2'b00: rgpio <= in_idle;
2'b01: rgpio <= in_rx;
2'b10: rgpio <= in_tx;
2'b11: rgpio <= in_fdx;
endcase // case ({tx,rx})
integer n;
always @*
for(n=0;n<WIDTH;n=n+1)
igpio[n] <= ddr[n] ? rgpio[n] : 1'bz;
assign gpio = igpio;
always @(posedge clk)
gpio_readback <= gpio;
endmodule // gpio_atr
|
/*
* bsg_mem_1rw_sync_mask_write_bit.v
*
* distributed synchronous 1-port ram for xilinx ultrascale or ultrascale plus FPGA
* Write mode: No-change | Read mode: No-change
* Note:
* There are 2 basic BRAM library primitives, RAMB18E2 and RAMB36E2 in Vivado.
* But none of them support bit-wise mask. They have Byte-wide write enable ports though.
* So we use the RAM_STYLE attribute to instruct the tool to infer distributed LUT RAM instead.
*
* To save resources, the code is written to be inferred as Single-port distributed ram RAM64X1S.
* https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf
*
*/
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_bit #(
parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter latch_last_read_p=0
, parameter enable_clock_gating_p=0
, localparam addr_width_lp = `BSG_SAFE_CLOG2(els_p)
) (
input clk_i
, input reset_i
, input [`BSG_SAFE_MINUS(width_p,1):0] data_i
, input [ addr_width_lp-1:0] addr_i
, input v_i
, input [`BSG_SAFE_MINUS(width_p,1):0] w_mask_i
, input w_i
, output [`BSG_SAFE_MINUS(width_p,1):0] data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, v_i, data_i, addr_i, w_i};
assign data_o = '0;
end
else
begin: nz
(* ram_style = "distributed" *) logic [`BSG_SAFE_MINUS(width_p,1):0] mem [els_p-1:0];
logic [`BSG_SAFE_MINUS(width_p,1):0] data_r;
always_ff @(posedge clk_i) begin
if (v_i & ~w_i)
data_r <= mem[addr_i];
end
initial
begin
$display("BSG INFO: els_p=%d width_p=%d 1RW SRAM Mask Write ram will be inferred as distributed RAM.",els_p,width_p);
end
assign data_o = data_r;
for (genvar i=0; i<width_p; i=i+1) begin
always_ff @(posedge clk_i) begin
if (v_i)
if (w_i & w_mask_i[i])
mem[addr_i][i] <= data_i[i];
end
end
end // non_zero_width
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; while (cin >> a >> b >> c >> d) { cout << (((a ^ b) & (c | d)) ^ ((b & c) | (a ^ d))) << endl; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:31 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_stub.v
// Design : system_auto_cc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
module system_auto_cc_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata,
s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst,
s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid,
s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready,
m_axi_aclk, m_axi_aresetn, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[0:0],s_axi_awaddr[27:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[127:0],s_axi_wstrb[15:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[0:0],s_axi_araddr[27:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[0:0],s_axi_rdata[127:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_awid[0:0],m_axi_awaddr[27:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[0:0],m_axi_araddr[27:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[0:0],m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [0:0]s_axi_awid;
input [27:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [127:0]s_axi_wdata;
input [15:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [27:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [127:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input m_axi_aclk;
input m_axi_aresetn;
output [0:0]m_axi_awid;
output [27:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [27:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int arr[n]; int ar[m]; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int j = 0; j < m; j++) { cin >> ar[j]; } for (int k = 0; k < n; k++) { for (int l = 0; l < m; l++) { if (ar[l] == arr[k]) { cout << arr[k] << ; } } } } |
// $Id: rtr_route_filter.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module to generate a mask of legal output port and resource class requests
// based on routing restrictions
//==============================================================================
module rtr_route_filter
(clk, route_valid, route_in_op, route_in_orc, route_out_op, route_out_orc,
errors);
`include "c_constants.v"
`include "rtr_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// nuber of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of VCs available for each class
parameter num_vcs_per_class = 1;
// number of input and output ports on router
parameter num_ports = 5;
// number of adjacent routers in each dimension
parameter num_neighbors_per_dim = 2;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 4;
// filter out illegal destination ports
// (the intent is to allow synthesis to optimize away the logic associated
// with such turns)
parameter restrict_turns = 1;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// select routing function type
parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// ID of current input port
parameter port_id = 0;
// ID of current input VC
parameter vc_id = 0;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// current message class
localparam message_class
= (vc_id / (num_resource_classes*num_vcs_per_class)) % num_message_classes;
// current resource class
localparam resource_class
= (vc_id / num_vcs_per_class) % num_resource_classes;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
input clk;
// route information is valid
input route_valid;
// raw output port
input [0:num_ports-1] route_in_op;
// raw output resource class
input [0:num_resource_classes-1] route_in_orc;
// filtered output port
output [0:num_ports-1] route_out_op;
wire [0:num_ports-1] route_out_op;
// filtered output resource class
output [0:num_resource_classes-1] route_out_orc;
wire [0:num_resource_classes-1] route_out_orc;
// internal error condition detected
output [0:1] errors;
wire [0:1] errors;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
wire [0:num_ports-1] error_op;
genvar op;
generate
for(op = 0; op < num_ports; op = op + 1)
begin:ops
case(routing_type)
`ROUTING_TYPE_PHASED_DOR:
begin
// handle network ports
if(op < (num_ports - num_nodes_per_router))
begin
if(
// for line and ring connectivity, packets can only
// turn back when they reach an intermediate node;
// however, when they reach the last intermediate
// node, they have reached their destination, and
// thus cannot turn back
(((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) &&
(op == port_id) &&
(resource_class == (num_resource_classes - 1))) ||
// likewise, for full connectivity, packets only ever
// take two successive steps in the same dimension
// when an intermediate node is reached; once again,
// this cannot happen in the last resource class
((connectivity == `CONNECTIVITY_FULL) &&
((op / num_neighbors_per_dim) ==
(port_id / num_neighbors_per_dim)) &&
(resource_class == (num_resource_classes - 1))) ||
// more generally, once a dimension has been visited,
// ports associated with that dimension will not be
// requested again until after an intermediate node
// is reached; again, this cannot happen in the last
// resource class; also, this only applies for
// network (i.e., not injection/ejection) ports
(((((dim_order == `DIM_ORDER_ASCENDING) ||
((dim_order == `DIM_ORDER_BY_CLASS) &&
((message_class % 2) == 0))) &&
((op / num_neighbors_per_dim) <
(port_id / num_neighbors_per_dim))) ||
(((dim_order == `DIM_ORDER_DESCENDING) ||
(dim_order == `DIM_ORDER_BY_CLASS) &&
((message_class % 2) == 1)) &&
((op / num_neighbors_per_dim) >
(port_id / num_neighbors_per_dim)))) &&
(resource_class == (num_resource_classes - 1)) &&
(port_id < (num_ports - num_nodes_per_router))))
begin
assign route_out_op[op] = 1'b0;
assign error_op[op] = route_in_op[op];
end
else
begin
assign route_out_op[op] = route_in_op[op];
assign error_op[op] = 1'b0;
end
end
// handle injection/ejection ports
else
begin
// a packet coming in on an injection/ejection port
// should never exit the router on the same port
if(op == port_id)
begin
assign route_out_op[op] = 1'b0;
assign error_op[op] = route_in_op[op];
end
else
begin
assign route_out_op[op] = route_in_op[op];
assign error_op[op] = 1'b0;
end
end
end
endcase
end
endgenerate
wire [0:num_resource_classes-1] error_orc;
generate
if(num_resource_classes == 1)
begin
assign route_out_orc = 1'b1;
assign error_orc = ~route_out_orc;
end
else if(num_resource_classes > 1)
begin
genvar orc;
for(orc = 0; orc < num_resource_classes; orc = orc + 1)
begin:orcs
case(routing_type)
`ROUTING_TYPE_PHASED_DOR:
begin
// at each hop, packets can either stay in the same
// resource class or advance to the next one
if((orc == resource_class) ||
(orc == (resource_class + 1)))
begin
assign route_out_orc[orc] = route_in_orc[orc];
assign error_orc[orc] = 1'b0;
end
else
begin
assign route_out_orc[orc] = 1'b0;
assign error_orc[orc] = route_in_orc[orc];
end
end
endcase
end
end
endgenerate
wire error_invalid_port;
assign error_invalid_port = route_valid & ((|error_op) | (~|route_in_op));
wire error_invalid_class;
assign error_invalid_class = route_valid & ((|error_orc) | (~|route_in_orc));
// synopsys translate_off
always @(posedge clk)
begin
if(error_invalid_port)
$display({"ERROR: Received flit's destination port violates ",
"constraints in module %m."});
if(error_invalid_class)
$display({"ERROR: Received flit's destination class violates ",
"constraints in module %m."});
end
// synopsys translate_on
assign errors[0] = error_invalid_port;
assign errors[1] = error_invalid_class;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_cpu_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[405][405]; int q[405 * 405], d[405], t, h, ans; bool vis[405]; int main() { int n, m; scanf( %d %d , &n, &m); while (m--) { int u, v; scanf( %d %d , &u, &v); a[u][v] = a[v][u] = 1; } t = h = 0; q[h++] = 1; vis[1] = 1; memset(d, -1, sizeof d); d[1] = 0; while (t < h) { int u = q[t++]; for (int i = 1; i <= n; i++) { if (vis[i] || a[u][i] == 0) continue; d[i] = d[u] + 1; vis[i] = 1; q[h++] = i; } } if (d[n] == -1) { puts( -1 ); return 0; } ans = d[n]; t = h = 0; q[h++] = 1; memset(vis, 0, sizeof vis); vis[1] = 1; memset(d, -1, sizeof d); d[1] = 0; while (t < h) { int u = q[t++]; for (int i = 1; i <= n; i++) { if (vis[i] || a[u][i]) continue; d[i] = d[u] + 1; vis[i] = 1; q[h++] = i; } } if (d[n] == -1) { puts( -1 ); return 0; } ans = max(ans, d[n]); cout << ans; } |
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "decoder4to16.v"
`include "encoder.v"
`include "decoder.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [14:0] c;
// Output of stage 2
wire [15:1] err;
wire [14:0] cx;
// Output of stage 3
wire [10:0] q;
wire [10:0] qx;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [10:0] b;
reg [10:0] r_b;
reg [3:0] e;
reg [3:0] r_e;
// 2nd stage
reg [14:0] r_c;
reg [3:0] rr_e;
reg [10:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [14:0] r_qx;
reg [10:0] rb;
reg clk,reset;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
decoder4to16 dec4to16 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_e,err);
ham_15_11_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
ham_15_11_decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,err,cx);
parity_stripper ps (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,qx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
r_qx<=0;
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include<bits/stdc++.h> #define rep(i,a,b) for(int i=a;i<b;i++) #define ret(x) return cout<<x,0; #define rety return cout<< YES ,0; #define retn return cout<< NO ,0; typedef long long ll; typedef double db; typedef long double ld; #define stt string #define ve vector<ll> #define se set<ll> #define ar array ll mod=1e9+7,mod2=998244353; using namespace std; ll fac[10000000]; ll gcd(ll x, ll y) { if(y==0) return x; return gcd(y,x%y); } ll fexp(ll a,ll b,ll m){ll ans = 1;while(b){if(b&1)ans=ans*a%m; b/=2;a=a*a%m;}return ans;} ll inverse(ll a, ll p){return fexp(a, p-2,p);} ll ncr(ll n, ll r,ll p) { if (r==0) return 1; return (fac[n]*inverse(fac[n-r],p)%p*inverse(fac[r],p)%p)%p; } // ____Z-Algorithm_____ vector<ll> za(string s) { ll n = s.size(); vector<ll> z(n); ll x = 0, y = 0,p=0; for(ll i= 1; i < n; i++) { z[i] = max(p,min(z[i-x],y-i+1)); while(i+z[i] < n && s[z[i]] == s[i+z[i]]) { x = i; y = i+z[i]; z[i]++; } } return z; } void subset(ll a[],ll k) { for (int i = 1; i < pow(2, k); i++) { for (int j = 0; j < k; j++) { if (i & 1 << j) { cout<<a[j]<< ; } } cout<<endl; } } vector<ll> pr(string s) { ll n = s.length(); vector<ll> pi(n); for (int i = 1; i < n; i++) { int j = pi[i-1]; while (j > 0 && s[i] != s[j]) j = pi[j-1]; if (s[i] == s[j]) j++; pi[i] = j; } return pi; } //---------------------------------------------------------------------/ int main() { ios::sync_with_stdio(0); cin.tie(0); ll t; cin>>t; while(t--) { int n; cin >> n; vector<int> a(n); for(int i = 0; i < n; i++) { cin >> a[i]; } cout << 3*n << endl; for(int i = 1; i <= n; i+=2) { cout << 1 << << i << << i+1 << endl; cout << 2 << << i << << i+1 << endl; cout << 2 << << i << << i+1 << endl; cout << 1 << << i << << i+1 << endl; cout << 2 << << i << << i+1 << endl; cout << 2 << << i << << i+1 << endl; } } } |
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//this is a FIFO master interface for the FX2 in "slave fifo" mode.
module slave_fifo
#(
//how many cycles max in a transfer state
parameter DATA_XFER_COUNT = 256,
parameter CTRL_XFER_COUNT = 32,
//sizes for fifo36 2 clock cascade fifos
parameter DATA_RX_FIFO_SIZE = 9,
parameter DATA_TX_FIFO_SIZE = 9,
parameter CTRL_RX_FIFO_SIZE = 9,
parameter CTRL_TX_FIFO_SIZE = 9
)
(// GPIF signals
input gpif_clk, input gpif_rst,
inout [15:0] gpif_d,
input [3:0] gpif_ctl,
output reg sloe, output reg slrd, output reg slwr, output reg pktend, output reg [1:0] fifoadr,
// FIFO interface
input fifo_clk, input fifo_rst,
output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy,
input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy,
output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy,
input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy,
output [31:0] debug
);
wire FX2_DE_pre = ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA)
wire FX2_CE_pre = ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB)
wire FX2_DF_pre = ~gpif_ctl[2]; //EP6 FX2 FIFO full (FLAGC)
wire FX2_CF_pre = ~gpif_ctl[3]; //EP8 FX2 FIFO full (FLAGD)
reg FX2_DE, FX2_CE, FX2_DF, FX2_CF;
always @(posedge gpif_clk) begin
FX2_DE <= FX2_DE_pre; //EP2 FX2 FIFO empty (FLAGA)
FX2_CE <= FX2_CE_pre; //EP4 FX2 FIFO empty (FLAGB)
FX2_DF <= FX2_DF_pre; //EP6 FX2 FIFO full (FLAGC)
FX2_CF <= FX2_CF_pre; //EP8 FX2 FIFO full (FLAGD)
end
wire [15:0] gpif_d_out_ctrl, gpif_d_out_data;
reg [15:0] gpif_d_out, gpif_d_in;
// ////////////////////////////////////////////////////////////////////
// GPIF bus master state machine
wire rx_valid, resp_valid;
reg tx_valid, ctrl_valid;
wire tx_ready, ctrl_ready;
reg rx_enable, resp_enable;
wire rx_data_enough_occ;
reg [9:0] transfer_count; //number of lines (a line is 16 bits) in active transfer
reg [3:0] state; //state machine current state
localparam STATE_IDLE = 0;
localparam STATE_THINK = 1;
localparam STATE_DATA_RX = 2;
localparam STATE_DATA_TX = 3;
localparam STATE_CTRL_RX = 4;
localparam STATE_CTRL_TX = 5;
localparam STATE_DATA_TX_SLOE = 6;
localparam STATE_CTRL_TX_SLOE = 7;
localparam STATE_DATA_RX_ADR = 8;
localparam STATE_CTRL_RX_ADR = 9;
//logs the last bus user for xfer fairness
//we only care about data rx vs. tx since ctrl pkts are so short
reg last_data_bus_hog;
localparam BUS_HOG_RX = 0;
localparam BUS_HOG_TX = 1;
wire resp_eof;
reg [1:0] idle_count;
// //////////////////////////////////////////////////////////////
// FX2 slave FIFO bus master state machine
//
always @(posedge gpif_clk)
if(gpif_rst) begin
state <= STATE_IDLE;
sloe <= 1;
slrd <= 1;
slwr <= 1;
pktend <= 1;
rx_enable <= 0;
tx_valid <= 0;
ctrl_valid <= 0;
resp_enable <= 0;
idle_count <= 0;
end
else case (state)
STATE_IDLE: begin
transfer_count <= 0;
sloe <= 1;
slrd <= 1;
slwr <= 1;
pktend <= 1;
rx_enable <= 0;
tx_valid <= 0;
ctrl_valid <= 0;
resp_enable <= 0;
if (idle_count == 2'b11) state <= STATE_THINK;
idle_count <= idle_count + 1;
end
STATE_THINK: begin
idle_count <= 0;
//handle transitions to other states
if(ctrl_ready & ~FX2_CE) begin //if there's room in the ctrl fifo and the FX2 has ctrl data
state <= STATE_CTRL_TX_SLOE;
fifoadr <= 2'b01;
sloe <= 0;
end
else if(resp_valid & ~FX2_CF) begin //if the ctrl fifo has data and the FX2 isn't full
state <= STATE_CTRL_RX_ADR;
fifoadr <= 2'b11;
end
else if(tx_ready & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX) begin //if there's room in the data fifo and the FX2 has data
state <= STATE_DATA_TX_SLOE;
last_data_bus_hog <= BUS_HOG_TX;
fifoadr <= 2'b00;
sloe <= 0;
end
else if(rx_data_enough_occ & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) begin //if the data fifo has data and the FX2 isn't full
state <= STATE_DATA_RX_ADR;
last_data_bus_hog <= BUS_HOG_RX;
fifoadr <= 2'b10;
end
else if(tx_ready & ~FX2_DE) begin
state <= STATE_DATA_TX_SLOE;
last_data_bus_hog <= BUS_HOG_TX;
fifoadr <= 2'b00;
sloe <= 0;
end
else if(rx_data_enough_occ & ~FX2_DF) begin
state <= STATE_DATA_RX_ADR;
last_data_bus_hog <= BUS_HOG_RX;
fifoadr <= 2'b10;
end
end
STATE_DATA_TX_SLOE: begin //just to assert SLOE one cycle before SLRD
state <= STATE_DATA_TX;
slrd <= 0;
end
STATE_CTRL_TX_SLOE: begin
state <= STATE_CTRL_TX;
slrd <= 0;
end
STATE_DATA_RX_ADR: begin //just to assert FIFOADR one cycle before SLWR
state <= STATE_DATA_RX;
rx_enable <= 1;
end
STATE_CTRL_RX_ADR: begin
state <= STATE_CTRL_RX;
resp_enable <= 1;
end
STATE_DATA_RX: begin
if (FX2_DF_pre || ~rx_valid || transfer_count == DATA_XFER_COUNT-1) begin
state <= STATE_IDLE;
rx_enable <= 0;
end
gpif_d_out <= gpif_d_out_data;
slwr <= ~rx_valid;
transfer_count <= transfer_count + 1;
end
STATE_DATA_TX: begin
if (FX2_DE_pre || transfer_count == DATA_XFER_COUNT-1) begin
state <= STATE_IDLE;
slrd <= 1;
end
gpif_d_in <= gpif_d;
tx_valid <= 1;
transfer_count <= transfer_count + 1;
end
STATE_CTRL_RX: begin
if (FX2_CF_pre || ~resp_valid || resp_eof || transfer_count == CTRL_XFER_COUNT-1) begin
state <= STATE_IDLE;
resp_enable <= 0;
end
pktend <= ~resp_eof;
gpif_d_out <= gpif_d_out_ctrl;
slwr <= ~resp_valid;
transfer_count <= transfer_count + 1;
end
STATE_CTRL_TX: begin
if (FX2_CE_pre || transfer_count == CTRL_XFER_COUNT-1) begin
state <= STATE_IDLE;
slrd <= 1;
end
gpif_d_in <= gpif_d;
ctrl_valid <= 1;
transfer_count <= transfer_count + 1;
end
endcase
// GPIF output data lines, tristate
assign gpif_d = (sloe)? gpif_d_out[15:0] : 16'bz;
// ////////////////////////////////////////////////////////////////////
// TX Data Path
gpmc16_to_fifo36 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE), .MIN_SPACE16(DATA_XFER_COUNT)) fifo36_to_gpmc16_tx(
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.in_data(gpif_d_in), .ready(tx_ready), .valid(tx_valid),
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.out_data(tx_data), .out_src_rdy(tx_src_rdy), .out_dst_rdy(tx_dst_rdy)
);
// ////////////////////////////////////////////
// RX Data Path
fifo36_to_gpmc16 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE), .MIN_OCC16(DATA_XFER_COUNT)) fifo36_to_gpmc16_rx(
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.in_data(rx_data), .in_src_rdy(rx_src_rdy), .in_dst_rdy(rx_dst_rdy),
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.has_data(rx_data_enough_occ),
.out_data(gpif_d_out_data), .valid(rx_valid), .enable(rx_enable)
);
// ////////////////////////////////////////////////////////////////////
// CTRL TX Data Path
gpmc16_to_fifo36 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE), .MIN_SPACE16(CTRL_XFER_COUNT)) fifo36_to_gpmc16_ctrl(
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.in_data(gpif_d_in), .ready(ctrl_ready), .valid(ctrl_valid),
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.out_data(ctrl_data), .out_src_rdy(ctrl_src_rdy), .out_dst_rdy(ctrl_dst_rdy)
);
// ////////////////////////////////////////////
// CTRL RX Data Path
fifo36_to_gpmc16 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo36_to_gpmc16_resp(
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.in_data(resp_data), .in_src_rdy(resp_src_rdy), .in_dst_rdy(resp_dst_rdy),
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
.out_data(gpif_d_out_ctrl), .valid(resp_valid), .enable(resp_enable),
.eof(resp_eof)
);
assign debug = 0;
endmodule // slave_fifo
|
#include <bits/stdc++.h> using namespace std; const int maxn = 55; const int maxm = 5e3 + 110; double dp[maxn][maxm]; struct node { int f, s; double p; } a[maxn]; int main() { int n, R; scanf( %d %d , &n, &R); for (int i = 1; i <= n; i++) { scanf( %d %d %lf , &a[i].f, &a[i].s, &a[i].p); a[i].p = a[i].p / 100.0; } double l = 0, r = 1e15, ans = 0; for (int ii = 0; ii <= 100; ii++) { double mid = (l + r) / 2.0; for (int j = 0; j <= R; j++) dp[n + 1][j] = j; for (int j = R + 1; j <= 5100; j++) dp[n + 1][j] = 0x3f3f3f3f; for (int i = n; i >= 1; i--) { for (int j = 5005; j >= 0; j--) { dp[i][j] = dp[i + 1][j + a[i].f] * a[i].p + dp[i + 1][j + a[i].s] * (1 - a[i].p); dp[i][j] = min(dp[i][j], dp[i + 1][j + a[i].f] * a[i].p + (1 - a[i].p) * (mid + (double)(j + a[i].s))); dp[i][j] = min(dp[i][j], a[i].p * ((double)(j + a[i].f) + mid) + (1 - a[i].p) * ((double)(j + mid) + a[i].s)); } } if (dp[1][0] >= mid) { ans = mid; l = mid; } else r = mid; } printf( %.9f n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; bool exceed(long long x, long long y, long long m) { return x >= m / y + 1; } long long n, k; string s; long long dp[1005][2005]; int zero = 1002; int main(void) { ios::sync_with_stdio(0); cin >> n >> k >> s; s = # + s; for (long long(i) = (0); (i) <= (n); (i)++) for (long long(j) = (-k); (j) <= (k); (j)++) dp[i][zero + j] = -1e18; dp[0][zero + 0] = 0; for (long long(i) = (0); (i) <= (n - 1); (i)++) { for (long long(j) = (-k); (j) <= (k); (j)++) { for (long long(l) = (-1); (l) <= (1); (l)++) { if (dp[i][zero + j] < -1e18 / 2) continue; if (s[i + 1] != ? ) { if (s[i + 1] != W && l == 1) continue; if (s[i + 1] != L && l == -1) continue; if (s[i + 1] != D && l == 0) continue; } long long nj = j + l; if (abs(nj) > k) continue; if (i + 1 != n && abs(nj) == k) continue; dp[i + 1][zero + nj] = j; } } } long long p = -1e18; if (dp[n][zero + k] > -1e18 / 2) p = k; if (dp[n][zero - k] > -1e18 / 2) p = -k; if (p < -1e18 / 2) { cout << NO << endl; return 0; } for (int i = n; i >= 1; i--) { if (dp[i][zero + p] == p) s[i] = D ; if (dp[i][zero + p] < p) s[i] = W ; if (dp[i][zero + p] > p) s[i] = L ; p = dp[i][zero + p]; } cout << s.substr(1) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_4_V
`define SKY130_FD_SC_LP__OR4_4_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_4_V
|
#include <bits/stdc++.h> using namespace std; long long int GC(long long int a, long long int b) { if (b == 0) return a; else return GC(b, a % b); } long long int inv_gc(long long int a, long long int b) { return a / GC(a, b) * b; } long long int Ceil(long long int a, long long int b) { return a / b + (a % b != 0); } long long int fastModExp(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b & 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b = b >> 1; } return res; } map<int, int> par, rk; void make_set() { for (char i = a ; i <= z ; i++) { par[i] = i; rk[i] = 1; } } int find(char x) { if (x == par[x]) return x; char p = find(par[x]); par[x] = p; return p; } int uni(char x, char y) { char p1 = find(x); char p2 = find(y); if (p1 == p2) return 0; if (rk[p1] > rk[p2]) { par[p2] = p1; rk[p1] += rk[p2]; } else { par[p1] = p2; rk[p2] += rk[p1]; } return 1; } map<char, int> mpx; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); make_set(); int n; vector<string> v; cin >> n; string s; for (int i = 0; i < n; i++) { cin >> s; v.push_back(s); if (s.length() > 1) { for (int i = 0; i < s.length() - 1; i++) int r = uni(s[i], s[i + 1]); } } for (int i = 0; i < v.size(); i++) { mpx[find(v[i][0])] = 1; } long long int count = 0; for (auto it = mpx.begin(); it != mpx.end(); it++) if (it->second == 1) { count++; } cout << count << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int withoutzero(int x); int main() { int a, b, c, d, e, f; cin >> a >> b; d = withoutzero(a); e = withoutzero(b); c = a + b; f = withoutzero(c); if ((d + e) == f) { cout << YES ; } else { cout << NO ; } } int withoutzero(int x) { int arr[10], i = 0, t = 0, k = 0; while (x > 0) { arr[i] = x % 10; x = x / 10; i++; } for (int j = 0; j < i; j++) { if (arr[j] != 0) { t += arr[j] * pow(10, k); k++; } } return t; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DIODE_PP_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int modulo = 1000000009; int h; long long int expo2[31]; long long int expo3[31]; long long int expo4[31]; long long int memmaneres0[1001]; long long int maneres0(int n) { long long int &mem = memmaneres0[n]; if (mem != -1) return mem; mem = 0; if (n < h) { mem = expo4[n] % modulo; return mem; } for (int t = 1; t <= h; t++) mem = (mem + expo3[t - 1] * maneres0(n - t)) % modulo; return mem; } long long int memmaneres1[1001][31]; long long int maneres1(int n, int i) { long long int &mem = memmaneres1[n][i]; if (mem != -1) return mem; mem = 0; if (n < h) { mem = expo3[i - 1] * expo4[n - i] % modulo; return mem; } for (int t = 1; t <= h; t++) { if (t < i) mem = (mem + expo2[t - 1] * maneres1(n - t, i - t)) % modulo; else if (t > i) mem = (mem + expo2[i - 1] * maneres1(n - i, t - i)) % modulo; } return mem; } long long int memmaneres2[1001][31][31]; long long int maneres2(int n, int i, int j) { long long int &mem = memmaneres2[n][i][j]; if (mem != -1) return mem; mem = 0; if (n < h) { mem = expo2[i - 1] * expo3[j - i - 1] % modulo * expo4[n - j] % modulo; return mem; } for (int t = 1; t <= h; t++) { if (t < i) mem = (mem + maneres2(n - t, i - t, j - t)) % modulo; else if (t > i and t < j) mem = (mem + maneres2(n - i, t - i, j - i)) % modulo; else if (t > j) mem = (mem + maneres2(n - i, j - i, t - i)) % modulo; } return mem; } long long int memmaneres3[1001][31][31][31]; long long int maneres3(int n, int i, int j, int k) { long long int &mem = memmaneres3[n][i][j][k]; if (mem != -1) return mem; mem = 0; if (n < h) { mem = expo2[j - i - 1] * expo3[k - j - 1] % modulo * expo4[n - k] % modulo; return mem; } if (i > 1) { mem = maneres3(n - 1, i - 1, j - 1, k - 1); } else { for (int t = i + 1; t <= h; t++) { if (t < j) mem = (mem + maneres3(n - i, t - i, j - i, k - i)) % modulo; else if (t > j and t < k) mem = (mem + maneres3(n - i, j - i, t - i, k - i)) % modulo; else if (t > k) mem = (mem + maneres3(n - i, j - i, k - i, t - i)) % modulo; } } return mem; } int main() { for (int n = 0; n < 1001; n++) for (int i = 0; i < 31; i++) for (int j = 0; j < 31; j++) for (int k = 0; k < 31; k++) memmaneres3[n][i][j][k] = -1; for (int n = 0; n < 1001; n++) for (int i = 0; i < 31; i++) for (int j = 0; j < 31; j++) memmaneres2[n][i][j] = -1; for (int n = 0; n < 1001; n++) for (int i = 0; i < 31; i++) memmaneres1[n][i] = -1; for (int n = 0; n < 1001; n++) memmaneres0[n] = -1; expo2[0] = expo3[0] = expo4[0] = 1; for (int i = 1; i < 31; i++) { expo2[i] = (2 * expo2[i - 1]) % modulo; expo3[i] = (3 * expo3[i - 1]) % modulo; expo4[i] = (4 * expo4[i - 1]) % modulo; } int n; cin >> n >> h; long long int r = 0; for (int i = 0; i < h; i++) r += expo3[i] * maneres0(n - i - 1) % modulo * 4 % modulo; for (int i = 0; i < h; i++) for (int j = i + 1; j < h; j++) r -= expo2[i] * maneres1(n - i - 1, j - i) % modulo * 12 % modulo; for (int i = 0; i < h; i++) for (int j = i + 1; j < h; j++) for (int k = j + 1; k < h; k++) r += maneres2(n - i - 1, j - i, k - i) % modulo * 24 % modulo; for (int i = 1; i < h; i++) for (int j = i + 1; j < h; j++) for (int k = j + 1; k < h; k++) r -= maneres3(n - 1, i, j, k) % modulo * 24 % modulo; r = (r % modulo + modulo) % modulo; cout << r << endl; } |
/*
This program ties the state of the LED to the state of the RESET button
*/
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy // AVR Rx buffer full
);
wire rst = ~rst_n; // make reset active high
wire [9:0] array; // this is a declaration of the 8-bit wire (I/O line)
// these signals should be high-z when not used
//append _n to wires that are active-low
//The following three lines are constant declarations
//x'yz
//x - represents the number of bits to use
//y - represents how to interpret the written number
// possible values: b(inary), he(x)
//z - represents the value
//Binary : 1,0, Z,X
// Z - High Impedence - disconnected
// X - Don't Care - could be anything
assign spi_miso = 1'bz; //The spi ports are disconnected to prevent board damage from driving them
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[6:0] = 7'b0; //these pins are set to a constant zero
assign led[7] = rst; // this pin is tied to rst
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_2_V
`define SKY130_FD_SC_LP__O32A_2_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [15:0] in = crc[15:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] outa; // From test of Test.v
wire [15:0] outb; // From test of Test.v
wire [15:0] outc; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outa (outa[15:0]),
.outb (outb[15:0]),
.outc (outc[15:0]),
// Inputs
.clk (clk),
.in (in[15:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {16'h0, outa, outb, outc};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h09be74b1b0f8c35d
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
clk, in
);
input clk;
input [15:0] in;
output reg [15:0] outa;
output reg [15:0] outb;
output reg [15:0] outc;
parameter WIDTH = 0;
always @(posedge clk) begin
outa <= {in};
outb <= {{WIDTH{1'b0}}, in};
outc <= {in, {WIDTH{1'b0}}};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, p[1005]; vector<int> T; bool ok; inline void enter() { cin >> n; for (int i = 1; i <= n; i++) cin >> p[i]; } void dfs(int u) { while (T[u] != 1) { T[u]++; u = p[u]; } cout << u << ; } inline void solve() { for (int i = 1; i <= n; i++) { T.assign(n + 4, 0); dfs(i); } } int main() { enter(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; unsigned long long x[N], y[N], f[N]; int a[N], cnt[N]; queue<int> g[N]; mt19937_64 rng(time(0)); char buf[1 << 23], *p1 = buf, *p2 = buf, obuf[1 << 23], *O = obuf; inline int rd() { int x = 0, f = 1; char ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); } while (isdigit(ch)) x = x * 10 + (ch ^ 48), ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); return x * f; } namespace Hash { const int hashmod = 999983; int v[hashmod]; bool vis[hashmod]; unsigned long long h[hashmod]; int &get(unsigned long long S) { int i = S % hashmod; for (; vis[i] && h[i] != S; i = (i + 1) % hashmod) ; if (!vis[i]) vis[i] = 1, h[i] = S; return v[i]; } } // namespace Hash int main() { int n = rd(); for (int i = 1; i <= n; ++i) { a[i] = rd(); x[i] = rng(); y[i] = rng(); } unsigned long long now = 0, ans = 0; ++Hash::get(now); int p = 0; for (int i = 1; i <= n; ++i) { if (g[a[i]].size() == 3) { int t = g[a[i]].front(); g[a[i]].pop(); while (p < t) --Hash::get(f[p++]); } g[a[i]].push(i); switch (++cnt[a[i]] % 3) { case 1: f[i] = now ^= x[a[i]]; break; case 2: f[i] = now ^= y[a[i]]; break; case 0: f[i] = now ^= x[a[i]] ^ y[a[i]]; break; } ans += Hash::get(now)++; } printf( %lld n , ans); } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module ad_dcfilter #(
// data path disable
parameter DISABLE = 0) (
// data interface
input clk,
input valid,
input [15:0] data,
output valid_out,
output [15:0] data_out,
// control interface
input dcfilt_enb,
input [15:0] dcfilt_coeff,
input [15:0] dcfilt_offset);
// internal registers
reg [15:0] dcfilt_coeff_d = 'd0;
reg [47:0] dc_offset = 'd0;
reg [47:0] dc_offset_d = 'd0;
reg valid_d = 'd0;
reg [15:0] data_d = 'd0;
reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0;
reg [15:0] data_dcfilt = 'd0;
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
// internal signals
wire [47:0] dc_offset_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// dcfilt_coeff is flopped so to remove warnings from vivado
always @(posedge clk) begin
dcfilt_coeff_d <= dcfilt_coeff;
end
// removing dc offset
always @(posedge clk) begin
dc_offset <= dc_offset_s;
dc_offset_d <= dc_offset;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
end
valid_2d <= valid_d;
data_2d <= data_d;
data_dcfilt <= data_d - dc_offset[32:17];
if (dcfilt_enb == 1'b1) begin
valid_int <= valid_2d;
data_int <= data_dcfilt;
end else begin
valid_int <= valid_2d;
data_int <= data_2d;
end
end
// dsp slice instance ((D-A)*B)+C
DSP48E1 #(
.ACASCREG (1),
.ADREG (1),
.ALUMODEREG (0),
.AREG (1),
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1),
.B_INPUT ("DIRECT"),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (1),
.DREG (0),
.INMODEREG (0),
.MASK (48'h3fffffffffff),
.MREG (1),
.OPMODEREG (0),
.PATTERN (48'h000000000000),
.PREG (1),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48"))
i_dsp48e1 (
.CLK (clk),
.A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}),
.B ({{2{dcfilt_coeff_d[15]}}, dcfilt_coeff_d}),
.C (dc_offset_d),
.D ({{9{data_d[15]}}, data_d}),
.MULTSIGNIN (1'd0),
.CARRYIN (1'd0),
.CARRYCASCIN (1'd0),
.ACIN (30'd0),
.BCIN (18'd0),
.PCIN (48'd0),
.P (dc_offset_s),
.MULTSIGNOUT (),
.CARRYOUT (),
.CARRYCASCOUT (),
.ACOUT (),
.BCOUT (),
.PCOUT (),
.ALUMODE (4'd0),
.CARRYINSEL (3'd0),
.INMODE (5'b01100),
.OPMODE (7'b0110101),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.OVERFLOW (),
.UNDERFLOW (),
.CEA1 (1'd0),
.CEA2 (1'd1),
.CEAD (1'd1),
.CEALUMODE (1'd0),
.CEB1 (1'd0),
.CEB2 (1'd1),
.CEC (1'd1),
.CECARRYIN (1'd0),
.CECTRL (1'd0),
.CED (1'd1),
.CEINMODE (1'd0),
.CEM (1'd1),
.CEP (1'd0),
.RSTA (1'd0),
.RSTALLCARRYIN (1'd0),
.RSTALUMODE (1'd0),
.RSTB (1'd0),
.RSTC (1'd0),
.RSTCTRL (1'd0),
.RSTD (1'd0),
.RSTINMODE (1'd0),
.RSTM (1'd0),
.RSTP (1'd0));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 500010; int n, a[N], rt = 1, ba[30], sta[N], top = 0; vector<int> e[N]; long long ans; void dfs(int u, int ff) { sta[++top] = u; if (ff) { long long w = a[sta[top - 1]]; int i = 1; for (; top - ba[i] > 0; i++) if (w > (long long)(i + 1) * a[sta[top - ba[i]]]) w = (long long)(i + 1) * a[sta[top - ba[i]]]; if (w > (long long)(i + 1) * a[rt]) w = (long long)(i + 1) * a[rt]; ans += w + (long long)a[u]; } for (auto v : e[u]) if (v ^ ff) dfs(v, u); --top; } int main() { ba[0] = 1; for (int i = 1; i < 25; i++) ba[i] = ba[i - 1] * 2; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] < a[rt]) rt = i; } for (int i = 1, x, y; i < n; i++) scanf( %d%d , &x, &y), e[x].push_back(y), e[y].push_back(x); dfs(rt, 0), printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> int main() { char c; std::set<char> s; while (std::cin >> c) { if ((c >= a ) && (c <= z )) { s.insert(c); } } std::cout << s.size() << n ; } |
`timescale 1 ns / 1 ps
module axi_traffic_controller_v1_0 #
(
// Users to add parameters here
parameter write_data_file = "wire_data_example",
parameter write_addr_file = "write_addr_example",
parameter read_data_file = "read_data_example",
parameter read_addr_file = "read_addr_example",
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M_AXI
parameter C_M_AXI_START_DATA_VALUE = 32'hAA000000,
parameter C_M_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter integer C_M_AXI_TRANSACTIONS_NUM = 4
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M_AXI
input wire m_axi_init_axi_txn,
output wire m_axi_error,
output wire m_axi_txn_done,
input wire m_axi_aclk,
input wire m_axi_aresetn,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output wire [2 : 0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [1 : 0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_araddr,
output wire [2 : 0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_rdata,
input wire [1 : 0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
// Instantiation of Axi Bus Interface M_AXI
axi_traffic_controller_v1_0_M_AXI # (
.write_data_file(write_data_file),
.write_addr_file(write_addr_file),
.read_data_file(read_data_file),
.read_addr_file(read_addr_file),
.C_M_START_DATA_VALUE(C_M_AXI_START_DATA_VALUE),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_M_TRANSACTIONS_NUM(C_M_AXI_TRANSACTIONS_NUM)
) axi_traffic_controller_v1_0_M_AXI_inst (
.INIT_AXI_TXN(m_axi_init_axi_txn),
.ERROR(m_axi_error),
.TXN_DONE(m_axi_txn_done),
.M_AXI_ACLK(m_axi_aclk),
.M_AXI_ARESETN(m_axi_aresetn),
.M_AXI_AWADDR(m_axi_awaddr),
.M_AXI_AWPROT(m_axi_awprot),
.M_AXI_AWVALID(m_axi_awvalid),
.M_AXI_AWREADY(m_axi_awready),
.M_AXI_WDATA(m_axi_wdata),
.M_AXI_WSTRB(m_axi_wstrb),
.M_AXI_WVALID(m_axi_wvalid),
.M_AXI_WREADY(m_axi_wready),
.M_AXI_BRESP(m_axi_bresp),
.M_AXI_BVALID(m_axi_bvalid),
.M_AXI_BREADY(m_axi_bready),
.M_AXI_ARADDR(m_axi_araddr),
.M_AXI_ARPROT(m_axi_arprot),
.M_AXI_ARVALID(m_axi_arvalid),
.M_AXI_ARREADY(m_axi_arready),
.M_AXI_RDATA(m_axi_rdata),
.M_AXI_RRESP(m_axi_rresp),
.M_AXI_RVALID(m_axi_rvalid),
.M_AXI_RREADY(m_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
/*
* lzw - Simple, Logarithmic Left Shift
* Copyright (C) 2015 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_LEFT_SHIFT
`else
`define INC_LEFT_SHIFT
`timescale 1 ns / 100 ps
module LeftShift(
ovalue,
ivalue,
amount
);
parameter LOGWORD=0;
localparam WORD=(1<<LOGWORD);
output reg [WORD-1:0] ovalue; // shifted value
input [WORD-1:0] ivalue; // original value
input [LOGWORD-1:0] amount; // amount by which to shift left
reg [WORD-1:0] rank [LOGWORD+1-1:0]; // intermediate shifts; +1 is aliased to ivalue
always @(*) begin
rank[LOGWORD] <= ivalue;
end
genvar i;
genvar j;
generate
for(i=0; i<LOGWORD; i=i+1) begin : i_left_shift // iterates over logarithmically-spaced ranks
always @(*) begin
if(amount[i]) begin
rank[i] <= rank[i+1][WORD-1-(1<<i):0] << (1<<i);
end
else begin
rank[i] <= rank[i+1];
end
end
end
endgenerate
always @(*) begin
ovalue <= rank[0];
end
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:50 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title3/title3_stub.v
// Design : title3
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module title3(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [11:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
module ternOpInModul # (
parameter integer C_NUM_SLAVE_SLOTS = 1,
parameter integer C_NUM_MASTER_SLOTS = 2,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_PROTOCOL = 0
)
(
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*(C_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*(C_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
endmodule
|
`timescale 1ns / 1ps
`include "asserts.vh"
module queue_tb();
reg [11:0] story_to;
reg clk_i, reset_i;
reg [7:0] dat_i;
reg push_i, pop_i, oe_i;
wire [7:0] dat_o;
wire full_o, empty_o;
wire [2:0] rp_to;
wire [2:0] wp_to;
wire [3:0] room_to;
queue #(
.DEPTH_BITS(3), // 8-deep queue
.DATA_BITS(8) // 8-bit data path for input and output
) q (
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(dat_i),
.push_i(push_i),
.dat_o(dat_o),
.pop_i(pop_i),
.oe_i(oe_i),
.full_o(full_o),
.empty_o(empty_o),
.rp_to(rp_to),
.wp_to(wp_to),
.room_to(room_to)
);
always begin
#20 clk_i <= ~clk_i;
end
task story;
input [11:0] expected;
begin
story_to = expected;
end
endtask
`DEFASSERT(rp,2,to)
`DEFASSERT(wp,2,to)
`DEFASSERT(room,3,to)
`DEFASSERT0(empty,o)
`DEFASSERT0(full,o)
`DEFASSERT(dat,7,o)
task tick;
begin
wait(clk_i); wait(~clk_i);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{clk_i, reset_i, dat_i, push_i, pop_i, oe_i} <= 0;
story(0);
wait(~clk_i);
reset_i <= 1;
tick;
assert_rp(0);
assert_wp(0);
assert_room(8);
assert_dat(0);
assert_empty(1);
assert_full(0);
story(2);
reset_i <= 0;
push_i <= 1;
dat_i <= 8'hFF;
tick;
assert_room(7);
assert_wp(1);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(2);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(3);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(4);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(5);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(6);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(1);
assert_wp(7);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
// Popping the queue should advance the read pointer.
story(3);
push_i <= 0;
pop_i <= 1; // Does NOT drive data outputs.
oe_i <= 1; // THIS does.
tick;
assert_room(1);
assert_wp(0);
assert_rp(1);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(0);
assert_rp(2);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(0);
assert_rp(3);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(0);
assert_rp(4);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(0);
assert_rp(5);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(0);
assert_rp(6);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(7);
assert_wp(0);
assert_rp(7);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
// The FIFO must support concurrent reads and writes.
// Testing strategy is simple:
// First, we write all $AA bytes to the queue's storage.
// From our previous tests, we know the data bus must be $FF.
story(4);
dat_i <= 8'hAA;
push_i <= 1;
pop_i <= 1; // Does NOT drive data outputs.
oe_i <= 1; // THIS does.
tick;
assert_room(8);
assert_wp(1);
assert_rp(1);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(2);
assert_rp(2);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(3);
assert_rp(3);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(4);
assert_rp(4);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(5);
assert_rp(5);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(6);
assert_rp(6);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(7);
assert_rp(7);
assert_dat(255);
assert_empty(1);
assert_full(0);
// (after writing the 8th item to the queue,
// we should wrap around, and see the first
// of the overwrites.)
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(8'hAA);
assert_empty(1);
assert_full(0);
$display("@I Done.");
$stop;
end
endmodule
|
#include <bits/stdc++.h> const double E = exp(1); const int maxn = 1e6 + 10; const int mod = 1e9 + 7; using namespace std; char ch[maxn]; int a[maxn]; bool cmp(int a, int b) { return a > b; } int main(int argc, char const *argv[]) { ios::sync_with_stdio(false); int n, k; cin >> n >> k; cin >> ch; int res = 1; for (int i = 0; i < n; i++) { if (k == 1) a[ch[i] - a ]++; else { if (ch[i] == ch[i + 1]) res++; else res = 1; if (res == k) { a[ch[i] - a ]++; res = 1; i += 1; } } } sort(a, a + 26, cmp); cout << a[0] << endl; return 0; } |
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