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module Create (Init, creaenhe, D, rst, RS, RW, Out_display, MsbOD, clk, scrinit);
input Init;
input creaenhe;
input clk;
input [2:0] scrinit;
input [6:0] D;
input rst;
output reg MsbOD;
output reg [6:0] Out_display;
output reg RS;
output reg RW;
always @(negedge clk) begin
if(rst) begin
MsbOD=0;
Out_display=7'b0;
end
else begin
case (scrinit)
3'b001: begin
Out_display={7'b0111000};
MsbOD=0;
RW=0;
RS=0;
end
3'b010: begin
Out_display={7'b0000100};
MsbOD=0;
RW=0;
RS=0;
end
3'b011: begin
Out_display={7'b0001100};
MsbOD=0;
RW=0;
RS=0;
end
3'b100: begin
Out_display={7'b0000001};
MsbOD=0;
RW=0;
RS=0;
end
3'b101: begin
Out_display={7'b0110000};
MsbOD=0;
RW=0;
RS=0;
end
default begin
if (creaenhe) begin
Out_display={7'b1101110};
MsbOD=1;
RW=0;
RS=1;
end
else begin
if(Init) begin
Out_display={7'b0000001};
MsbOD=0;
RS=0;
RW=0;
end
else begin
Out_display=D;
MsbOD=0;
RW=0;
RS=1;
end
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, ori[300][300], mat[300][300], mr[300], mc[300], vis[100000], l[100000], r[100000]; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &ori[i][j]); for (int i = 1; i <= n; i++) mr[i] = 0; for (int i = 1; i <= m; i++) mc[i] = 0; for (int i = 1; i < 1000; i++) vis[i] = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { mr[i] = max(mr[i], ori[i][j]); } } for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) { mc[i] = max(mc[i], ori[j][i]); } } for (int i = 1; i <= n; i++) vis[mr[i]] = 1; for (int i = 1; i <= m; i++) { if (!vis[mc[i]]) vis[mc[i]] = 2; else vis[mc[i]] = 3; } int x = 0, y = 0; for (int k = n * m; k >= 1; k--) { if (vis[k] == 3) { mat[++x][++y] = k; l[x] = r[x] = y; } else if (vis[k] == 2) { mat[x][++y] = k; r[x] = y; } else if (vis[k] == 1) { mat[++x][y] = k; l[x] = r[x] = y; } else { for (int i = 1; i <= x; i++) { int flag = 0; for (int j = l[i] - 1; j >= 1; j--) { if (!mat[i][j] && mat[i - 1][j]) { flag = 1; mat[i][j] = k; l[i] = j; break; } } if (flag) break; for (int j = r[i] + 1; j <= y; j++) { if (!mat[i][j] && mat[i + 1][j]) { flag = 1; mat[i][j] = k; r[i] = j; break; } } if (flag) break; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) printf( %d , mat[i][j]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int solveA(pair<pair<int, int>, int> x, pair<pair<int, int>, int> y, pair<pair<int, int>, int> z) { pair<int, int> a = x.first; pair<int, int> b = y.first; pair<int, int> c = z.first; int n = a.first + b.first + c.first; if (n != a.second) return -1; if (n != b.second) return -1; if (n != c.second) return -1; cout << n << n ; for (int i = 1; i <= a.first; ++i) { for (int j = 1; j <= a.second; ++j) { cout << (char)( A + x.second); } cout << n ; } for (int i = 1; i <= b.first; ++i) { for (int j = 1; j <= b.second; ++j) { cout << (char)( A + y.second); } cout << n ; } for (int i = 1; i <= c.first; ++i) { for (int j = 1; j <= c.second; ++j) { cout << (char)( A + z.second); } cout << n ; } return n; } int solveB(pair<pair<int, int>, int> x, pair<pair<int, int>, int> y, pair<pair<int, int>, int> z) { pair<int, int> a = x.first; pair<int, int> b = y.first; pair<int, int> c = z.first; int n = a.first; if (n != b.first + c.first) return -1; if (n != b.second + a.second) return -1; if (n != c.second + a.second) return -1; cout << n << n ; for (int i = 1; i <= a.second; ++i) { for (int j = 1; j <= n; ++j) { cout << (char)( A + x.second); } cout << n ; } for (int i = 1; i <= b.second; ++i) { for (int j = 1; j <= b.first; ++j) { cout << (char)( A + y.second); } for (int j = 1; j <= c.first; ++j) { cout << (char)( A + z.second); } cout << n ; } return n; } int main(int argc, const char* argv[]) { pair<int, int> a[3]; cin >> a[0].first >> a[0].second; cin >> a[1].first >> a[1].second; cin >> a[2].first >> a[2].second; pair<pair<int, int>, int> b[3]; for (int i = 0; i < 8; ++i) { if (i & 1) b[0].first = a[0]; else b[0].first = make_pair(a[0].second, a[0].first); if (i >> 1 & 1) b[1].first = a[1]; else b[1].first = make_pair(a[1].second, a[1].first); if (i >> 2 & 1) b[2].first = a[2]; else b[2].first = make_pair(a[2].second, a[2].first); for (int i = 0; i <= 2; ++i) { b[i].second = i; } sort(b, b + 3); do { int n; n = solveA(b[0], b[1], b[2]); if (n != -1) { return 0; } n = solveB(b[0], b[1], b[2]); if (n != -1) { return 0; } } while (next_permutation(b, b + 3)); } cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; int Q, N, M, K, L; int A[5001]; int MAPPING[10001]; int CHK[10001]; int RET[10001]; map<int, int> MAP; int map_idx = 0; int main() { ios::sync_with_stdio(false); cin >> N; for (int i = 0; i < N; i++) { cin >> A[i]; if (A[i] == 0) continue; int b = 1; int x = A[i]; if (x < 0) x *= -1; for (int j = 2; j * j <= x; j++) { int a = 0; while (x % j == 0) { a++; x /= j; } if (a & 1) b *= j; } b *= x; if (A[i] < 0) b *= -1; if (MAP.count(b) == 1) MAPPING[i] = MAP[b]; else { MAP[b] = map_idx++; MAPPING[i] = MAP[b]; } } int now = 0; for (int i = 0; i < N; i++) { for (int j = i; j < N; j++) { if (A[j] == 0) { RET[max(now, 1)]++; continue; } if (CHK[MAPPING[j]] == 0) { now++; CHK[MAPPING[j]] = 1; } RET[max(now, 1)]++; } now = 0; memset(CHK, 0, sizeof(CHK)); } for (int i = 1; i <= N; i++) cout << RET[i] << ; cin >> N; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb4to1 (
//# {{data|Data Signals}}
input [3:0] D,
output Z,
//# {{control|Control Signals}}
input [3:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); vector<string> grid; int start_x, start_y; for (int i = 0; i < n; i++) { string s; cin >> s; grid.push_back(s); for (int j = 0; j < s.size(); j++) { if (s[j] == S ) { start_x = i; start_y = j; } } } string actions; cin >> actions; int out = 0; vector<pair<int, int>> mapping = {{-1, 0}, {0, -1}, {0, 1}, {1, 0}}; do { bool found = false; int x = start_x; int y = start_y; for (int i = 0; i < actions.size(); i++) { int action = actions[i] - 0 ; x += mapping[action].first; y += mapping[action].second; if (x < 0 || x >= n || y < 0 || y >= m || grid[x][y] == # ) { break; } if (grid[x][y] == E ) { found = true; break; } } out += found; } while (next_permutation(mapping.begin(), mapping.end())); printf( %d , out); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; long long a[maxn], n, b[maxn], f[maxn]; int main() { scanf( %lld , &n); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]), b[i] = a[i]; sort(b + 1, b + n + 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (j == 1) f[j] += abs(b[j] - a[i]); else f[j] = min(f[j - 1], f[j] + abs(b[j] - a[i])); printf( %lld n , f[n]); return 0; } |
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module soc
(
// General - Clocking & Reset
clk_i,
rst_i,
ext_intr_i,
intr_o,
// UART0
uart_tx_o,
uart_rx_i,
// Memory interface
io_addr_i,
io_data_i,
io_data_o,
io_we_i,
io_stb_i,
io_ack_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_KHZ = 12288;
parameter [31:0] EXTERNAL_INTERRUPTS = 1;
parameter UART_BAUD = 115200;
parameter SYSTICK_INTR_MS = 1;
parameter ENABLE_SYSTICK_TIMER = "ENABLED";
parameter ENABLE_HIGHRES_TIMER = "ENABLED";
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input [(EXTERNAL_INTERRUPTS - 1):0] ext_intr_i /*verilator public*/;
output intr_o /*verilator public*/;
output uart_tx_o /*verilator public*/;
input uart_rx_i /*verilator public*/;
// Memory Port
input [31:0] io_addr_i /*verilator public*/;
input [31:0] io_data_i /*verilator public*/;
output [31:0] io_data_o /*verilator public*/;
input io_we_i /*verilator public*/;
input io_stb_i /*verilator public*/;
output io_ack_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [7:0] uart0_addr;
wire [31:0] uart0_data_w;
wire [31:0] uart0_data_r;
wire uart0_we;
wire uart0_stb;
wire uart0_intr;
wire [7:0] timer_addr;
wire [31:0] timer_data_o;
wire [31:0] timer_data_i;
wire timer_we;
wire timer_stb;
wire timer_intr_systick;
wire timer_intr_hires;
wire [7:0] intr_addr;
wire [31:0] intr_data_o;
wire [31:0] intr_data_i;
wire intr_we;
wire intr_stb;
//-----------------------------------------------------------------
// Peripheral Interconnect
//-----------------------------------------------------------------
soc_pif8
u2_soc
(
// General - Clocking & Reset
.clk_i(clk_i),
.rst_i(rst_i),
// I/O bus (from mem_mux)
// 0x12000000 - 0x12FFFFFF
.io_addr_i(io_addr_i),
.io_data_i(io_data_i),
.io_data_o(io_data_o),
.io_we_i(io_we_i),
.io_stb_i(io_stb_i),
.io_ack_o(io_ack_o),
// Peripherals
// UART0 = 0x12000000 - 0x120000FF
.periph0_addr_o(uart0_addr),
.periph0_data_o(uart0_data_w),
.periph0_data_i(uart0_data_r),
.periph0_we_o(uart0_we),
.periph0_stb_o(uart0_stb),
// Timer = 0x12000100 - 0x120001FF
.periph1_addr_o(timer_addr),
.periph1_data_o(timer_data_o),
.periph1_data_i(timer_data_i),
.periph1_we_o(timer_we),
.periph1_stb_o(timer_stb),
// Interrupt Controller = 0x12000200 - 0x120002FF
.periph2_addr_o(intr_addr),
.periph2_data_o(intr_data_o),
.periph2_data_i(intr_data_i),
.periph2_we_o(intr_we),
.periph2_stb_o(intr_stb),
// Unused = 0x12000300 - 0x120003FF
.periph3_addr_o(/*open*/),
.periph3_data_o(/*open*/),
.periph3_data_i(32'h00000000),
.periph3_we_o(/*open*/),
.periph3_stb_o(/*open*/),
// Unused = 0x12000400 - 0x120004FF
.periph4_addr_o(/*open*/),
.periph4_data_o(/*open*/),
.periph4_data_i(32'h00000000),
.periph4_we_o(/*open*/),
.periph4_stb_o(/*open*/),
// Unused = 0x12000500 - 0x120005FF
.periph5_addr_o(/*open*/),
.periph5_data_o(/*open*/),
.periph5_data_i(32'h00000000),
.periph5_we_o(/*open*/),
.periph5_stb_o(/*open*/),
// Unused = 0x12000600 - 0x120006FF
.periph6_addr_o(/*open*/),
.periph6_data_o(/*open*/),
.periph6_data_i(32'h00000000),
.periph6_we_o(/*open*/),
.periph6_stb_o(/*open*/),
// Unused = 0x12000700 - 0x120007FF
.periph7_addr_o(/*open*/),
.periph7_data_o(/*open*/),
.periph7_data_i(32'h00000000),
.periph7_we_o(/*open*/),
.periph7_stb_o(/*open*/)
);
//-----------------------------------------------------------------
// UART0
//-----------------------------------------------------------------
uart_periph
#(
.UART_DIVISOR(((CLK_KHZ * 1000) / UART_BAUD))
)
u_uart
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_o(uart0_intr),
.addr_i(uart0_addr),
.data_o(uart0_data_r),
.data_i(uart0_data_w),
.we_i(uart0_we),
.stb_i(uart0_stb),
.rx_i(uart_rx_i),
.tx_o(uart_tx_o)
);
//-----------------------------------------------------------------
// Timer
//-----------------------------------------------------------------
timer_periph
#(
.CLK_KHZ(CLK_KHZ),
.SYSTICK_INTR_MS(SYSTICK_INTR_MS),
.ENABLE_SYSTICK_TIMER(ENABLE_SYSTICK_TIMER),
.ENABLE_HIGHRES_TIMER(ENABLE_HIGHRES_TIMER)
)
u_timer
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_systick_o(timer_intr_systick),
.intr_hires_o(timer_intr_hires),
.addr_i(timer_addr),
.data_o(timer_data_i),
.data_i(timer_data_o),
.we_i(timer_we),
.stb_i(timer_stb)
);
//-----------------------------------------------------------------
// Interrupt Controller
//-----------------------------------------------------------------
intr_periph
#(
.EXTERNAL_INTERRUPTS(EXTERNAL_INTERRUPTS)
)
u_intr
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_o(intr_o),
.intr0_i(uart0_intr),
.intr1_i(timer_intr_systick),
.intr2_i(timer_intr_hires),
.intr3_i(1'b0),
.intr4_i(1'b0),
.intr5_i(1'b0),
.intr6_i(1'b0),
.intr7_i(1'b0),
.intr_ext_i(ext_intr_i),
.addr_i(intr_addr),
.data_o(intr_data_i),
.data_i(intr_data_o),
.we_i(intr_we),
.stb_i(intr_stb)
);
//-------------------------------------------------------------------
// Hooks for debug
//-------------------------------------------------------------------
`ifdef verilator
function [0:0] get_uart_wr;
// verilator public
get_uart_wr = uart0_stb & uart0_we;
endfunction
function [7:0] get_uart_data;
// verilator public
get_uart_data = uart0_data_w[7:0];
endfunction
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/26 16:07:35
// Design Name:
// Module Name: lab3_2_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab3_2_1(
input [7:0] v,
input en_in_n,
output reg [2:0] y,
output reg en_out,gs
);
always
@(v or en_in_n)
if(en_in_n == 1)
begin
y=7;
en_out = 1;
gs = 1;
end
else if(en_in_n == 0&&v == 255)
begin
y = 7;
en_out = 0;
gs = 1;
end
else if(en_in_n == 0&&v[7] == 0)
begin
y = 0;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[6] == 0)
begin
y = 1;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[5] == 0)
begin
y = 2;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[4] == 0)
begin
y = 3;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[3] == 0)
begin
y = 4;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[2] == 0)
begin
y = 5;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[1] == 0)
begin
y = 6;
en_out = 1;
gs = 0;
end
else if(en_in_n == 0&&v[0] == 0)
begin
y = 7;
en_out = 1;
gs = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node; struct node { node* arr[26]; int val; node(); void insert(char ch[], int l, int pos); void win(); void lose(); }; node::node() { val = 0; for (int i = 0; i < 26; i++) arr[i] = 0; } void node::insert(char ch[], int l, int pos) { if (pos == l) return; else { int index = ch[pos] - a ; if (arr[index] == 0) { arr[index] = new node(); arr[index]->insert(ch, l, pos + 1); } else { arr[index]->insert(ch, l, pos + 1); } } } void node::win() { int ind = 0; for (int i = 0; i < 26; i++) { if (arr[i] != 0) { arr[i]->win(); ind = ind | arr[i]->val; } } val = !ind; } void node::lose() { int ind = 1; int leaf = 1; for (int i = 0; i < 26; i++) { if (arr[i] != 0) { leaf = 0; arr[i]->lose(); ind = ind & arr[i]->val; } } if (leaf) val = leaf; else val = !ind; } int main() { int n, k; scanf( %d %d , &n, &k); node* root = new node(); char ch[100000]; for (int i = 0; i < n; i++) { scanf( %s , ch); int l = strlen(ch); root->insert(ch, l, 0); } int ind = 0; for (int i = 0; i < 26; i++) { if (root->arr[i] != 0) { root->arr[i]->win(); ind = ind | root->arr[i]->val; } } int w = ind; ind = 0; for (int i = 0; i < 26; i++) { if (root->arr[i] != 0) { root->arr[i]->lose(); ind = ind | !root->arr[i]->val; } } int l = ind; if (w & l) { printf( First n ); } else if (w & !l) { if (k & 1) printf( First n ); else printf( Second n ); } else printf( Second n ); } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; map<char, int> m; vector<int> v; for (int i = 0; i < s.size(); i++) { m[s[i]]++; } map<char, int>::iterator it = m.begin(); while (it != m.end()) { v.push_back((*it).second); it++; } if (v.size() > 4 || v.size() == 1) { cout << No ; } else if (v.size() == 4) { cout << Yes ; } else if (v.size() == 3) { if (v[0] > 1 || v[1] > 1 || v[2] > 1) cout << Yes ; else cout << No ; } else if (v.size() == 2) { if (v[0] > 1 && v[1] > 1) cout << Yes ; else cout << No ; } return 0; } |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Last modified date: 04/08 '13
* Last modified by: Ye-sheng Kuo <>
* Last modified content: Added glitch reset
* */
`include "include/mbus_def.v"
module mbus_ctrl(
input CLK_EXT,
input RESETn,
input CLKIN,
output CLKOUT,
input DIN,
output reg DOUT,
input [`WATCH_DOG_WIDTH-1:0] THRESHOLD
);
`include "include/mbus_func.v"
parameter BUS_IDLE = 0;
parameter BUS_WAIT_START = 3;
parameter BUS_START = 4;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ACTIVE = 5;
parameter BUS_INTERRUPT = 7;
parameter BUS_SWITCH_ROLE = 6;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
parameter START_CYCLES = 10;
parameter BUS_INTERRUPT_COUNTER = 6;
reg [log2(START_CYCLES-1)-1:0] start_cycle_cnt, next_start_cycle_cnt;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg clk_en, next_clk_en;
reg [log2(BUS_INTERRUPT_COUNTER-1)-1:0] bus_interrupt_cnt, next_bus_interrupt_cnt;
reg clkin_sampled;
reg [2:0] din_sampled_neg, din_sampled_pos;
reg [`WATCH_DOG_WIDTH-1:0] threshold_cnt, next_threshold_cnt;
assign CLKOUT = (clk_en)? CLK_EXT : 1'b1;
wire [1:0] CONTROL_BITS = `CONTROL_SEQ; // EOM?, ~ACK?
always @ (posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
bus_state <= BUS_IDLE;
start_cycle_cnt <= START_CYCLES - 1'b1;
clk_en <= 0;
bus_interrupt_cnt <= BUS_INTERRUPT_COUNTER - 1'b1;
threshold_cnt <= 0;
end
else
begin
bus_state <= next_bus_state;
start_cycle_cnt <= next_start_cycle_cnt;
clk_en <= next_clk_en;
bus_interrupt_cnt <= next_bus_interrupt_cnt;
threshold_cnt <= next_threshold_cnt;
end
end
always @ *
begin
next_bus_state = bus_state;
next_start_cycle_cnt = start_cycle_cnt;
next_clk_en = clk_en;
next_bus_interrupt_cnt = bus_interrupt_cnt;
next_threshold_cnt = threshold_cnt;
case (bus_state)
BUS_IDLE:
begin
if (~DIN)
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = START_CYCLES - 1'b1;
end
BUS_WAIT_START:
begin
next_threshold_cnt = 0;
if (start_cycle_cnt)
next_start_cycle_cnt = start_cycle_cnt - 1'b1;
else
begin
next_clk_en = 1;
next_bus_state = BUS_START;
end
end
BUS_START:
begin
next_bus_state = BUS_ARBITRATE;
end
BUS_ARBITRATE:
begin
next_bus_state = BUS_PRIO;
// Glitch, reset bus immediately
if (DIN)
next_threshold_cnt = THRESHOLD;
end
BUS_PRIO:
begin
next_bus_state = BUS_ACTIVE;
end
BUS_ACTIVE:
begin
if ((threshold_cnt<THRESHOLD)&&(~clkin_sampled))
next_threshold_cnt = threshold_cnt + 1'b1;
else
begin
next_clk_en = 0;
next_bus_state = BUS_INTERRUPT;
end
next_bus_interrupt_cnt = BUS_INTERRUPT_COUNTER - 1'b1;
end
BUS_INTERRUPT:
begin
if (bus_interrupt_cnt)
next_bus_interrupt_cnt = bus_interrupt_cnt - 1'b1;
else
begin
if ({din_sampled_neg, din_sampled_pos}==6'b111_000)
begin
next_bus_state = BUS_SWITCH_ROLE;
next_clk_en = 1;
end
end
end
BUS_SWITCH_ROLE:
begin
next_bus_state = BUS_CONTROL0;
end
BUS_CONTROL0:
begin
next_bus_state = BUS_CONTROL1;
end
BUS_CONTROL1:
begin
next_bus_state = BUS_BACK_TO_IDLE;
end
BUS_BACK_TO_IDLE:
begin
if (~DIN)
begin
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = 1;
end
else
begin
next_bus_state = BUS_IDLE;
end
next_clk_en = 0;
end
endcase
end
always @ (negedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_sampled_neg <= 0;
bus_state_neg <= BUS_IDLE;
end
else
begin
if (bus_state==BUS_INTERRUPT)
din_sampled_neg <= {din_sampled_neg[1:0], DIN};
bus_state_neg <= bus_state;
end
end
always @ (posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_sampled_pos <= 0;
clkin_sampled <= 0;
end
else
begin
if (bus_state==BUS_INTERRUPT)
din_sampled_pos <= {din_sampled_pos[1:0], DIN};
clkin_sampled <= CLKIN;
end
end
always @ *
begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE: begin DOUT = 1; end
BUS_WAIT_START: begin DOUT = 1; end
BUS_START : begin DOUT = 1; end
BUS_INTERRUPT: begin DOUT = CLK_EXT; end
BUS_CONTROL0: begin if (threshold_cnt==THRESHOLD) DOUT = (~CONTROL_BITS[1]); end
BUS_BACK_TO_IDLE: begin DOUT = 1; end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2000 + 4; char s[maxn]; int a[maxn]; void get(bitset<maxn> &B) { scanf( %s , s); int m = strlen(s); int x = 1, y = -1; for (int i = 0; i < m; i++) a[m - 1 - i] = s[i] - 0 ; m--; x += m + y; ++x; for (int i = 0; i < maxn && x >= 0; i++) { int rem = 0; for (int j = m; j >= 0; j--) a[j] += rem * 10, rem = (a[j] & 1), a[j] >>= 1; B[i] = rem; while (m >= 0 && !a[m]) m--; x = m; } } int pos[maxn]; bitset<maxn> b[maxn], st[maxn]; int main() { if (fopen( in , r )) { freopen( in , r , stdin); freopen( out , w , stdout); } memset(pos, -1, sizeof(pos)); int n; scanf( %d , &n); for (int i = 0; i < n; i++) { get(b[i]); st[i][i] = 1; bool ok = 1; for (int j = 0; j < maxn; j++) if (b[i][j]) { if (pos[j] == -1) { ok = 0; pos[j] = i; break; } b[i] ^= b[pos[j]]; st[i] ^= st[pos[j]]; } if (!ok) { printf( 0 n ); continue; } st[i][i] = 0; printf( %d , st[i].count()); for (int j = 0; j < maxn; j++) if (st[i][j]) printf( %d , j); printf( n ); } } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename S> ostream &operator<<(ostream &os, const pair<T, S> &v) { os << ( ; os << v.first << , << v.second << ) ; return os; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << [ ; long long sz = v.size(); for (long long i = 0; i < sz; ++i) { os << v[i]; if (i != sz - 1) os << , ; } os << ] n ; return os; } template <typename T> ostream &operator<<(ostream &os, const set<T> &v) { T last = *v.rbegin(); os << [ ; for (auto it : v) { os << it; if (it != last) os << , ; } os << ] n ; return os; } template <typename T, typename S> ostream &operator<<(ostream &os, const map<T, S> &v) { for (auto it : v) { os << it.first << : << it.second << n ; } return os; } long long power(long long a, long long b) { long long res = 1; while (b) { if (b % 2) { res = (res * a) % 1000000007; } b /= 2; a = (a * a) % 1000000007; } return res; } template <typename Arg1> void __f(const char *name, Arg1 &&arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char *names, Arg1 &&arg1, Args &&...args) { const char *comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, T; cin >> n >> T; vector<pair<long long, long long> > arr; for (__typeof(1) i = 1; i <= n; i++) { long long t; cin >> t; long long from = t - i; long long to = T - i; if (to > from && to > 0) { arr.push_back({from, 1}); arr.push_back({to, -1}); } } sort((arr).begin(), (arr).end()); long long curr = 0, ans = 0; for (auto it : arr) { curr += it.second; ans = max(ans, curr); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> signed main(void) { int totNums, cnt = 0; long long tot = 0, num; bool zero = false; std::cin >> totNums; for (int i = 0; i < totNums; i++) { std::cin >> num; if (num == 0) { ++tot; zero = true; } else if (num > 0) tot += num - 1; else if (num < 0) { tot += -1 - num; ++cnt; } } if ((cnt & 1) && !zero) tot += 2; std::cout << tot << std::endl; return 0; } |
`define ADDER_WIDTH 011
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
module servo(clk, rst, rs232_in, rs232_in_stb, rs232_in_ack, rs232_out, servos, rs232_out_stb, servos_stb, rs232_out_ack, servos_ack);
input clk;
input rst;
input [15:0] rs232_in;
input rs232_in_stb;
output rs232_in_ack;
output [15:0] rs232_out;
output rs232_out_stb;
input rs232_out_ack;
output [15:0] servos;
output servos_stb;
input servos_ack;
wire [15:0] wire_140036826114168;
wire wire_140036826114168_stb;
wire wire_140036826114168_ack;
servo_ui servo_ui_32237832(
.clk(clk),
.rst(rst),
.input_rs232(rs232_in),
.input_rs232_stb(rs232_in_stb),
.input_rs232_ack(rs232_in_ack),
.output_control(wire_140036826114168),
.output_control_stb(wire_140036826114168_stb),
.output_control_ack(wire_140036826114168_ack),
.output_rs232(rs232_out),
.output_rs232_stb(rs232_out_stb),
.output_rs232_ack(rs232_out_ack));
servo_controller servo_controller_32246024(
.clk(clk),
.rst(rst),
.input_control(wire_140036826114168),
.input_control_stb(wire_140036826114168_stb),
.input_control_ack(wire_140036826114168_ack),
.output_servos(servos),
.output_servos_stb(servos_stb),
.output_servos_ack(servos_ack));
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:04:43 03/14/2016
// Design Name: Top
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab5/test_top.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_top;
// Inputs
reg clk;
reg reset;
reg [2:0] SW;
// Outputs
wire [3:0] LED;
// Instantiate the Unit Under Test (UUT)
Top uut (
.clk(clk),
.reset(reset),
.SW(SW),
.LED(LED)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
SW = 0;
// Wait 100 ns for global reset to finish
#125;
reset = 0;
// Add stimulus here
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 110; int a[maxn]; int main() { int n; while (cin >> n) { int ans = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i]) ans++; } for (int i = 1; i <= n; i++) { if (a[i] == 1) { if (i == 1) continue; if (a[i - 1] && i >= 1) continue; if (i >= 2 && a[i - 2]) { ans++; continue; } } } cout << ans << endl; } } |
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTDDIO_OUT
// ============================================================
// File Name: delay.v
// Megafunction Name(s):
// ALTDDIO_OUT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module delay (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [0:0] datain_h;
input [0:0] datain_l;
input outclock;
output [0:0] dataout;
wire [0:0] sub_wire0;
wire [0:0] dataout = sub_wire0[0:0];
altddio_out ALTDDIO_OUT_component (
.aclr (aclr),
.datain_h (datain_h),
.datain_l (datain_l),
.outclock (outclock),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
ALTDDIO_OUT_component.extend_oe_disable = "OFF",
ALTDDIO_OUT_component.intended_device_family = "Cyclone III",
ALTDDIO_OUT_component.invert_output = "OFF",
ALTDDIO_OUT_component.lpm_hint = "UNUSED",
ALTDDIO_OUT_component.lpm_type = "altddio_out",
ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
ALTDDIO_OUT_component.power_up_high = "OFF",
ALTDDIO_OUT_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.cmp TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_clkgen (
// mmcm reset
mmcm_rst,
// clock selection
clk_sel,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00040063;
parameter ID = 0;
// mmcm reset
output mmcm_rst;
// clock selection
output clk_sel;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_mmcm_preset = 'd0;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_clk_sel = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign clk_sel = ~up_clk_sel;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_mmcm_preset <= 1'd1;
up_wack <= 'd0;
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_clk_sel <= 'd0;
end else begin
up_mmcm_preset <= ~up_mmcm_resetn;
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_clk_sel <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
end else begin
up_drp_sel <= 1'b0;
up_drp_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {31'd0, up_clk_sel};
8'h17: up_rdata <= {31'd0, up_drp_locked};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:39:26 12/05/2015
// Design Name:
// Module Name: LCD_Peripheral
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LCD_Peripheral(clk , rst , d_in , cs , addr , rd , wr, e, rs, data, int_cnt, en_cnt, limit_cnt, d_out );
input [15:0]d_in;
input cs;
input [3:0]addr;
input rd;
input wr;
output reg [15:0] d_out;
input clk;
input rst;
input int_cnt;
output en_cnt;
output [15:0] limit_cnt;
output rs;
output e;
output [7:0] data;
//------------------------------------ regs and wires-------------------------------
reg [10:0] s; //selector mux_4 and write registers
reg init=0;
reg en;
reg reset;
reg set;
reg clear;
reg off;
reg on;
reg entry_mode;
reg cursor;
reg w_char;
reg [7:0] cursor_pos;
reg [7:0] ascii_char;
wire busy;
//------------------------------------ regs and wires-------------------------------
always @(*) begin//------address_decoder------------------------------
case (addr)
4'h0:begin s = (cs && wr) ? 11'b00000000001 : 11'b00000000000 ;end // en
4'h1:begin s = (cs && wr) ? 11'b00000000010 : 11'b00000000000 ;end // reset
4'h2:begin s = (cs && wr) ? 11'b00000000100 : 11'b00000000000 ;end // set
4'h3:begin s = (cs && wr) ? 11'b00000001000 : 11'b00000000000 ;end // off
4'h4:begin s = (cs && wr) ? 11'b00000010000 : 11'b00000000000 ;end // on
4'h5:begin s = (cs && wr) ? 11'b00000100000 : 11'b00000000000 ;end //entry_mode
4'h6:begin s = (cs && wr) ? 11'b00001000000 : 11'b00000000000 ;end //cursor
4'h7:begin s = (cs && wr) ? 11'b00010000000 : 11'b00000000000 ;end // w_char
4'h8:begin s = (cs && wr) ? 11'b00100000000 : 11'b00000000000 ;end // cursor_pos
4'h9:begin s = (cs && wr) ? 11'b01000000000 : 11'b00000000000 ;end // ascii_char
4'hA:begin s = (cs && rd) ? 11'b10000000000 : 11'b00000000000 ;end // Busy
default:begin s = 11'b00000000000 ; end
endcase
end//------------------address_decoder--------------------------------
always @(negedge clk) begin//-------------------- escritura de registros
en = (s[0]) ? d_in[0] : en;
reset = (s[1]) ? d_in[0] : reset;
set = (s[2]) ? d_in[0] : set;
off = (s[3]) ? d_in[0] : off;
on = (s[4]) ? d_in[0] : on;
entry_mode = (s[5]) ? d_in[0] : entry_mode;
cursor = (s[6]) ? d_in[0] : cursor;
w_char = (s[7]) ? d_in[0] : w_char;
cursor_pos = (s[8]) ? d_in[7:0] : cursor_pos;
ascii_char = (s[9]) ? d_in[7:0] : ascii_char;
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
d_out <= (s[10]) ? {15'h0 , busy} : 16'h0000;
end//-----------------------------------------------mux_4
LCD LCD_Driver (
.clk(clk),
.rst(rst),
.en(en),
.reset(reset),
.set(set),
.clear(clear),
.off(off),
.on(on),
.entry_mode(entry_mode),
.cursor(cursor),
.w_char(w_char),
.cursor_pos(cursor_pos),
.ascii_char(ascii_char),
.busy(busy),
.int_cnt(int_cnt),
.limit_cnt(limit_cnt),
.en_cnt(en_cnt),
.rs(rs),
.e(e),
.data(data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double PI = acos(-1.0); const int N = 3e5 + 5, K = 30; int tam[N] = {1}, g[N][K], _g[N][K]; vector<int> v; int res[N]; pair<int, int> merge(int a, int b) { if (!a) return pair<int, int>(b, 0); if (!b) return pair<int, int>(a, 0); int r = 0; v.push_back(a); for (int i = 0; i < K; i++) { if (g[a][i] and g[b][i]) { r++; pair<int, int> p = merge(g[a][i], g[b][i]); g[a][i] = p.first; r += p.second; } else if (g[b][i]) { g[a][i] = g[b][i]; } } return pair<int, int>(a, r); } void go(int at, int d) { int r = 0; for (int i = 0; i < K; i++) { int next = g[at][i]; if (next) { r++; go(next, d + 1); tam[at] += tam[next]; } } v.clear(); v.push_back(at); int u = 0; for (int i = 0; i < K; i++) { int next = g[at][i]; pair<int, int> p = merge(u, next); u = p.first; r += p.second; } for (int i = 0; i < (int)v.size(); i++) for (int j = 0; j < K; j++) g[v[i]][j] = _g[v[i]][j]; res[d] += r; } int main(void) { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i < n; i++) { int a, b; char c; cin >> a >> b >> c; g[a][c - a ] = b; _g[a][c - a ] = b; } go(1, 1); int ans = 0; for (int i = 0; i < N; i++) if (res[i] > res[ans]) ans = i; cout << n - res[ans] << endl; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int nmax = 5e4 + 5; int l[nmax], r[nmax]; int main() { int n, x; scanf( %d %d , &n, &x); for (int i = 0; i < n; ++i) { scanf( %d %d , l + i, r + i); } long long res = 0; for (int i = 0; i < n;) { if (!(l[i] <= x && r[i] >= x)) { int lc = 0, rc = 0; int lc2 = 0, rc2 = 0; int j = i; while ((lc < 1 || rc < 1) && lc2 < 2 && rc2 < 2) { if (r[j] <= x) ++lc; if (l[j] >= x) ++rc; if (r[j] < x) ++lc2; if (l[j] > x) ++rc2; ++j; } if (lc && rc) { if (l[i] > x) { res += l[i] - x; } if (r[i] < x) { res += x - r[i]; } ++i; } else if (lc2 == 2) { int nxt = 0; for (int k = i; k < j; ++k) { nxt = max(nxt, l[k]); if (r[k] < x) { nxt = max(nxt, r[k]); } } res += x - nxt; x = nxt; } else if (rc2 == 2) { int nxt = mod; for (int k = i; k < j; ++k) { nxt = min(nxt, r[k]); if (l[k] > x) { nxt = min(nxt, l[k]); } } res += nxt - x; x = nxt; } } else { ++i; } } printf( %lld n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, w[100010], in1, in2, in3; double ans; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &w[i]); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &in1, &in2, &in3); ans = max(ans, (w[in1] + w[in2]) * 1.0 / in3); } printf( %.15lf n , ans); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:28:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_stub.v
// Design : system_vga_pll_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_pll,Vivado 2016.4" *)
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10, N = 1e3 + 10; int tp[maxn], x[maxn], y[maxn]; vector<int> edge; char ch[2]; int rt[N], V, E, i, k; int root(int u) { if (rt[u] < 0) return u; else return rt[u] = root(rt[u]); } void init(int _V) { for (i = 1; i <= _V; i++) rt[i] = -1; } void merge(int u, int v) { u = root(u); v = root(v); rt[v] = u; } void Read() { scanf( %d%d , &V, &E); for (i = 1; i <= E; i++) { scanf( %d%d%s , x + i, y + i, ch); tp[i] = (ch[0] == S ) ? 1 : 0; } } void runs() { if (V % 2 != 1) puts( -1 ), exit(0); k = V >> 1; init(V); for (i = 1; i <= E; i++) if (!tp[i] and root(x[i]) != root(y[i])) { merge(x[i], y[i]); } for (i = 1; i <= E; i++) if (tp[i] and root(x[i]) != root(y[i])) { edge.push_back(i); merge(x[i], y[i]); } if (((int)((edge).size())) > k) puts( -1 ), exit(0); init(V); for (i = 0; i < ((int)((edge).size())); i++) merge(x[edge[i]], y[edge[i]]); for (i = 1; i <= E; i++) if (((int)((edge).size())) < k and tp[i] and root(x[i]) != root(y[i])) { edge.push_back(i); merge(x[i], y[i]); } if (((int)((edge).size())) < k) puts( -1 ), exit(0); for (i = 1; i <= E; i++) if (!tp[i] and root(x[i]) != root(y[i])) { edge.push_back(i); merge(x[i], y[i]); } if (((int)((edge).size())) < 2 * k) puts( -1 ), exit(0); printf( %d n , V - 1); for (i = 0; i < ((int)((edge).size())); i++) printf( %d , edge[i]); puts( ); } int main() { Read(); runs(); } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; const int Q = 1e9 + 7; struct Point { int x, y; Point(int _x = 0, int _y = 0) : x(_x), y(_y) {} const int sign() const { return y < 0 || y == 0 && x < 0; } Point operator-(const Point &R) { return Point(x - R.x, y - R.y); } long long operator^(const Point &R) const { return (long long)x * R.y - (long long)y * R.x; } bool operator<(const Point &R) const { if (sign() != R.sign()) { return sign() < R.sign(); } return (*this ^ R) > 0; } }; inline void add(long long &A, long long B) { A += B; } Point p[N]; int n; long long f[6][N][N]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &p[i].x, &p[i].y); f[0][i][i] = 1; } vector<tuple<Point, int, int>> v; for (int i = 0; i < n; ++i) { for (int j = 0; j < i; ++j) { v.emplace_back(p[j] - p[i], i, j); v.emplace_back(p[i] - p[j], j, i); } } sort(v.begin(), v.end()); for (auto &it : v) { int x = get<1>(it); int y = get<2>(it); for (int i = 5; i > 0; --i) { for (int j = 0; j < n; ++j) { add(f[i][j][y], f[i - 1][j][x]); } } } long long res = 0; for (int i = 0; i < n; ++i) { add(res, f[5][i][i]); } cout << res << endl; } |
`include "pycoram.v"
`define THREAD_NAME "ctrl_thread"
module userlogic #
(
parameter W_A = 13,
parameter W_D = 32,
parameter W_COMM_A = 4
)
(
input CLK,
input RST
);
wire [W_A-1:0] mem_addr;
wire [W_D-1:0] mem_d;
wire mem_we;
wire [W_D-1:0] mem_q;
wire [W_D-1:0] comm_d;
wire comm_enq;
wire comm_full;
wire [W_D-1:0] comm_q;
wire comm_deq;
wire comm_empty;
SumTestTop
sumTestTop
(.clk(CLK),
.reset(RST),
.mem_addr(mem_addr),
.mem_d(mem_d),
.mem_we(mem_we),
.mem_q(mem_q),
.comm_d(comm_d),
.comm_enq(comm_enq),
.comm_full(comm_full),
.comm_q(comm_q),
.comm_deq(comm_deq),
.comm_empty(comm_empty)
);
CoramMemory1P
#(
.CORAM_THREAD_NAME(`THREAD_NAME),
.CORAM_ID(0),
.CORAM_SUB_ID(0),
.CORAM_ADDR_LEN(W_A),
.CORAM_DATA_WIDTH(W_D)
)
inst_data_memory
(.CLK(CLK),
.ADDR(mem_addr),
.D(mem_d),
.WE(mem_we),
.Q(mem_q)
);
CoramChannel
#(
.CORAM_THREAD_NAME(`THREAD_NAME),
.CORAM_ID(0),
.CORAM_ADDR_LEN(W_COMM_A),
.CORAM_DATA_WIDTH(W_D)
)
inst_comm_channel
(.CLK(CLK),
.RST(RST),
.D(comm_d),
.ENQ(comm_enq),
.FULL(comm_full),
.Q(comm_q),
.DEQ(comm_deq),
.EMPTY(comm_empty)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_4_V
`define SKY130_FD_SC_HD__XNOR2_4_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_4_V
|
#include <bits/stdc++.h> using namespace std; int mat[105][105]; int n, m, res; void solve(int p) { if (p % 2) return; for (int i = 0, j = p - 1; i < p / 2; i++, j--) for (int k = 0; k < m; k++) if (mat[i][k] != mat[j][k]) return; res = res / 2; solve(p / 2); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &mat[i][j]); res = n; solve(n); printf( %d n , res); return 0; } |
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module io_requester(
input clk,
input rst_n,
////////////////// io_requester <--> arbiter
// RD TX
output wire cor_tx_rd_ready,
input wire cor_tx_rd_valid,
input wire [70:0] cor_tx_rd_hdr,
// WR TX
output wire cor_tx_wr_ready,
input wire cor_tx_wr_valid,
input wire [74:0] cor_tx_wr_hdr,
input wire [511:0] cor_tx_data,
//////////////////// io_requester <--> server_io
// TX_RD request,
input wire rq_tx_rd_ready,
output reg rq_tx_rd_valid,
output reg [44:0] rq_tx_rd_hdr,
// TX_WR request
input wire rq_tx_wr_ready,
output reg rq_tx_wr_valid,
output reg [48:0] rq_tx_wr_hdr,
output reg [511:0] rq_tx_data,
///////////////////// io_requester <--> pagetable
// afu_virt_waddr --> afu_phy_waddr
output reg [57:0] afu_virt_wr_addr,
output reg pt_re_wr,
input wire [31:0] afu_phy_wr_addr,
input wire afu_phy_wr_addr_valid,
// afu_virt_raddr --> afu_phy_raddr
output reg [57:0] afu_virt_rd_addr,
output reg pt_re_rd,
input wire [31:0] afu_phy_rd_addr,
input wire afu_phy_rd_addr_valid
);
wire trq_empty;
wire [4:0] trq_count;
wire trq_full;
wire trq_valid;
wire [44:0] trq_dout;
wire twq_empty;
wire [4:0] twq_count;
wire twq_full;
wire twq_valid;
wire [560:0] twq_dout;
reg [31:0] rd_cnt;
reg [511:0] afu_virt_wr_data_d0;
reg [74:0] afu_virt_wr_hdr_d0;
reg afu_virt_wr_valid_d0;
reg [511:0] afu_virt_wr_data_d1;
reg [74:0] afu_virt_wr_hdr_d1;
reg afu_virt_wr_valid_d1;
reg [511:0] afu_virt_wr_data_d2;
reg [74:0] afu_virt_wr_hdr_d2;
reg afu_virt_wr_valid_d2;
reg [511:0] afu_virt_wr_data_d3;
reg [74:0] afu_virt_wr_hdr_d3;
reg afu_virt_wr_valid_d3;
reg [70:0] afu_virt_rd_hdr_d0;
reg afu_virt_rd_valid_d0;
reg [70:0] afu_virt_rd_hdr_d1;
reg afu_virt_rd_valid_d1;
reg [70:0] afu_virt_rd_hdr_d2;
reg afu_virt_rd_valid_d2;
reg [70:0] afu_virt_rd_hdr_d3;
reg afu_virt_rd_valid_d3;
//-------------------------------------------------
always @(posedge clk) begin
if( ~rst_n ) begin
rd_cnt <= 32'b0;
end
else if (rq_tx_rd_valid) begin
rd_cnt <= rd_cnt +1'b1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// TX RD Channel ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign cor_tx_rd_ready = ~trq_full;
always@(posedge clk) begin
if(~rst_n) begin
rq_tx_rd_valid <= 0;
rq_tx_rd_hdr <= 0;
end
else if(rq_tx_rd_ready) begin
rq_tx_rd_valid <= trq_valid;
rq_tx_rd_hdr <= trq_dout;
end
end
// TX_RD transmit queue
quick_fifo #(.FIFO_WIDTH(45), //
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 - 8)
) txrd_queue(
.clk (clk),
.reset_n (rst_n),
.din (afu_virt_rd_hdr_d3[44:0]),
.we (afu_virt_rd_valid_d3),
.re (rq_tx_rd_ready),
.dout (trq_dout),
.empty (trq_empty),
.valid (trq_valid),
.full (),
.count (trq_count),
.almostfull (trq_full)
);
always@(posedge clk) begin
if( ~rst_n ) begin
pt_re_rd <= 0;
afu_virt_rd_addr <= 0;
afu_virt_rd_valid_d0 <= 0;
//afu_virt_rd_hdr_d0 <= 0;
// S1
afu_virt_rd_valid_d1 <= 0;
//afu_virt_rd_hdr_d1 <= 0;
// S2
afu_virt_rd_valid_d2 <= 0;
//afu_virt_rd_hdr_d2 <= 0;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_rd_valid_d3 <= 0;
//afu_virt_rd_hdr_d3 <= 0;
end
else begin
pt_re_rd <= cor_tx_rd_valid & cor_tx_rd_ready;
afu_virt_rd_addr <= cor_tx_rd_hdr[70:13];
// PT pipeline stages delay
// S0
afu_virt_rd_valid_d0 <= cor_tx_rd_valid & cor_tx_rd_ready;
afu_virt_rd_hdr_d0 <= cor_tx_rd_hdr;
// S1
afu_virt_rd_valid_d1 <= afu_virt_rd_valid_d0;
afu_virt_rd_hdr_d1 <= afu_virt_rd_hdr_d0;
// S2
afu_virt_rd_valid_d2 <= afu_virt_rd_valid_d1;
afu_virt_rd_hdr_d2 <= afu_virt_rd_hdr_d1;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_rd_valid_d3 <= afu_virt_rd_valid_d2;
afu_virt_rd_hdr_d3 <= {afu_phy_rd_addr, afu_virt_rd_hdr_d2[12:0]};
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// TX WR Channel ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign cor_tx_wr_ready = ~twq_full;
always@(posedge clk) begin
if(~rst_n) begin
rq_tx_wr_valid <= 0;
rq_tx_data <= 0;
rq_tx_wr_hdr <= 0;
end
else if(rq_tx_wr_ready) begin
rq_tx_wr_valid <= twq_valid;
rq_tx_data <= twq_dout[511:0];
rq_tx_wr_hdr <= twq_dout[560:512];
end
end
// TX_WR transmit queue
quick_fifo #(.FIFO_WIDTH(561), //
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 -8)
) txwr_queue(
.clk (clk),
.reset_n (rst_n),
.din ({afu_virt_wr_hdr_d3[48:0], afu_virt_wr_data_d3}),
.we (afu_virt_wr_valid_d3),
.re (rq_tx_wr_ready),
.dout (twq_dout),
.empty (twq_empty),
.valid (twq_valid),
.full (),
.count (twq_count),
.almostfull (twq_full)
);
always@(posedge clk) begin
if( ~rst_n ) begin
pt_re_wr <= 0;
afu_virt_wr_addr <= 0;
// PT pipeline stages delay
// S0
afu_virt_wr_valid_d0 <= 0;
afu_virt_wr_hdr_d0 <= 0;
afu_virt_wr_data_d0 <= 0;
// S1
afu_virt_wr_valid_d1 <= 0;
afu_virt_wr_hdr_d1 <= 0;
afu_virt_wr_data_d1 <= 0;
// S2
afu_virt_wr_valid_d2 <= 0;
afu_virt_wr_hdr_d2 <= 0;
afu_virt_wr_data_d2 <= 0;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_wr_valid_d3 <= 0;
afu_virt_wr_hdr_d3 <= 0;
afu_virt_wr_data_d3 <= 0;
end
else begin
pt_re_wr <= cor_tx_wr_valid & cor_tx_wr_ready;
afu_virt_wr_addr <= cor_tx_wr_hdr[70:13];
// PT pipeline stages delay
// S0
afu_virt_wr_valid_d0 <= cor_tx_wr_valid & cor_tx_wr_ready;
afu_virt_wr_hdr_d0 <= cor_tx_wr_hdr;
afu_virt_wr_data_d0 <= cor_tx_data;
// S1
afu_virt_wr_valid_d1 <= afu_virt_wr_valid_d0;
afu_virt_wr_hdr_d1 <= afu_virt_wr_hdr_d0;
afu_virt_wr_data_d1 <= afu_virt_wr_data_d0;
// S2
afu_virt_wr_valid_d2 <= afu_virt_wr_valid_d1;
afu_virt_wr_hdr_d2 <= afu_virt_wr_hdr_d1;
afu_virt_wr_data_d2 <= afu_virt_wr_data_d1;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_wr_valid_d3 <= afu_virt_wr_valid_d2;
afu_virt_wr_hdr_d3 <= { afu_virt_wr_hdr_d2[74:71], afu_phy_wr_addr, afu_virt_wr_hdr_d2[12:0]};
afu_virt_wr_data_d3 <= afu_virt_wr_data_d2;
end
end
endmodule
|
`define ADDER_WIDTH 010
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n, c1 = 0, c2 = 0; cin >> n; char x[n]; for (int i = 0; i < n; i++) { cin >> x[i]; if (x[i] == A ) c1++; else if (x[i] == D ) c2++; } if (c1 > c2) cout << Anton ; else if (c1 < c2) cout << Danik ; else cout << Friendship ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long l[5001], dp[5001][5001]; void solve() { int n, k, ans = 0; cin >> n >> k; vector<int> v(n, 0); for (int i = 0; i < (int)(n); ++i) cin >> v[i]; sort(v.begin(), v.end()); for (int i = 0, j = 0; i < n; ++i) { while (v[i] - v[j] > 5) { j++; } l[i] = j; } for (int i = 1; i <= k; i++) { for (int j = 1; j <= n; j++) { dp[i][j] = max(dp[i][j - 1], dp[i - 1][l[j - 1]] + j - l[j - 1]); } } cout << dp[k][n] << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long t = 1; while (t--) { solve(); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BEHAVIORAL_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
reg clk = 1'b0;
reg [3:0] reset_shift = 4'b1111;
reg trigger_reset = 1'b0;
wire reset;
wire resetn = ~reset;
reg failed = 1'b0;
initial
begin
$dumpfile (VCD_FILE);
$dumpvars;
`ifdef TIMEOUT
#`TIMEOUT
`else
#100000
`endif
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
always @(*) #10 clk <= ~clk;
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
reset_shift <= 3'b111;
end else begin
reset_shift <= {reset_shift[2:0],1'b0};
end
end
assign reset = reset_shift[3];
task do_trigger_reset;
begin
@(posedge clk) trigger_reset <= 1'b1;
@(posedge clk) trigger_reset <= 1'b0;
end
endtask
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < 7; i++) { cin >> arr[i]; } int day = 1; int i = 0; while (n > 0) { n = n - arr[i]; i++; if (n > 0) { day++; } if (day > 7) { day = 1; } if (i == 7) { i = 0; } } cout << day; } |
#include <bits/stdc++.h> using namespace std; struct point { int x, y; int num; int mark; }; point p[100010]; int ans[100010]; point pt; int sum1, sum2; bool cmp(point a, point b) { return (a.x - pt.x) * (b.y - pt.y) - (a.y - pt.y) * (b.x - pt.x) < 0; } bool cmp2(point a, point b) { return a.y != b.y ? a.y < b.y : a.x < b.x; } void work(int l, int r) { if (r < l) return; int maxi = 0; int marki = 0; maxi = min_element(p + l, p + r + 1, cmp2) - p; swap(p[maxi], p[l]); pt = p[l]; int k; sort(p + l + 1, p + r + 1, cmp); sum1 = sum2 = 0; for (k = r; !(pt.mark != p[k].mark && sum1 == sum2); k--) if (p[k].mark == pt.mark) sum1++; else sum2++; marki = k; if (pt.mark) ans[p[k].num] = pt.num; else ans[pt.num] = p[k].num; work(l + 1, marki - 1); work(marki + 1, r); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = (1); i <= (2 * n); ++i) { cin >> p[i].x >> p[i].y; p[i].mark = (i > n); p[i].num = i > n ? i - n : i; } work(1, 2 * n); for (int i = (1); i <= (n); ++i) { cout << ans[i] << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s; int max = 0; int counter = 0; cin >> n >> s; for (int i = 0; i < n; i++) { int a; cin >> a; counter += a; if (a > max) { max = a; } } if (counter - max > s) { cout << NO ; return 0; } else { cout << YES ; return 0; } } |
#include <bits/stdc++.h> using namespace std; int n, sum, dp[1 << 16], arc[16][16], d[16]; void Floyd() { int k, i, j; for (k = 0; k < n; k++) for (i = 0; i < n; i++) for (j = 0; j < n; j++) arc[i][j] = min(arc[i][j], arc[i][k] + arc[k][j]); } int getans() { int i, j, x, t, totol; Floyd(); for (i = 1; i < n; i++) if (d[i] && arc[0][i] > 1000000007) return -1; memset(dp, 0x7f, sizeof(dp)); dp[0] = 0; totol = (1 << n) - 1; for (t = 0; t <= totol; t++) { for (i = 0; i < n; i++) if (d[i] % 2 && (t & (1 << i))) break; if (i == n) dp[t] = 0; for (i = 0; i < n; i++) if (d[i] % 2 && !(t & (1 << i))) for (j = i + 1; j < n; j++) if (d[j] % 2 && !(t & (1 << j)) && arc[i][j] < 1000000007) dp[t | (1 << i) | (1 << j)] = min(dp[t | (1 << i) | (1 << j)], dp[t] + arc[i][j]); } if (dp[totol] > 1000000007) return -1; return sum + dp[totol]; } int main() { int m; while (~scanf( %d%d , &n, &m)) { sum = 0; memset(arc, 0x3f, sizeof(arc)); memset(d, 0, sizeof(d)); for (int i = 1; i <= m; i++) { int x, y, l; scanf( %d%d%d , &x, &y, &l); sum += l; x--, y--; arc[y][x] = arc[x][y] = min(arc[x][y], l); d[x]++, d[y]++; } printf( %d n , getans()); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:00:11 03/29/2015
// Design Name:
// Module Name: decoderparam
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decoderparam
# (parameter WIDTH = 4)
( output reg [2**WIDTH-1 : 0] code,
input [WIDTH-1 : 0] a,
input clken
);
localparam STAGE = WIDTH;
integer i, s, r;
reg [(STAGE+1)*(2**STAGE):0] p;
always @(a, p, clken) begin
p[STAGE*(2**STAGE)] <= clken;
for(s=STAGE; s > 0; s = s - 1) begin
for (r = 0; r < 2**(STAGE - s); r = r + 1) begin
p[(s-1)*(2**STAGE) + 2*r] <= !a[s-1] && p[s*(2**STAGE)+r];
p[(s-1)*(2**STAGE) + 2*r+1] <= a[s-1] && p[s*(2**STAGE)+r];
end
end
for (i=0; i < 2**STAGE; i = i + 1) begin
code[i] <= p[i];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; unsigned gcd(unsigned a, unsigned b) { unsigned r; do { r = a % b; a = b; b = r; } while (r > 0); return a; } unsigned arr[705]; bool dp[705][705][2]; bool en[705][705][2]; unsigned g[705][705]; bool f(int l, int r, int rm) { if (en[l][r][rm]) return dp[l][r][rm]; en[l][r][rm] = true; if (l == r) dp[l][r][rm] = g[l][l - 1 + 2 * rm] > 1; else { dp[l][r][rm] |= (g[l - 1 + rm * (r - l + 2)][l] > 1) && f(l + 1, r, 0); dp[l][r][rm] |= (g[l - 1 + rm * (r - l + 2)][r] > 1) && f(l, r - 1, 1); for (int curs = 1; curs < r - l; curs++) dp[l][r][rm] |= (g[l - 1 + rm * (r - l + 2)][l + curs] > 1) && f(l, l + curs - 1, 1) && f(l + curs + 1, r, 0); } return dp[l][r][rm]; } void init(int n) { for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) g[i][j] = gcd(arr[i], arr[j]); } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &arr[i]); init(n); if (f(1, n - 1, 0)) { printf( Yes n ); return 0; } if (f(0, n - 2, 1)) { printf( Yes n ); return 0; } for (int i = 1; i < n - 1; i++) { if (f(0, i - 1, 1) && f(i + 1, n - 1, 0)) { printf( Yes n ); return 0; } else continue; } printf( No n ); return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casex/endcase - label w/ X no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casex (val1 & val2 )
3'b000: result = 0;
3'b0x1: result = 1 ;
3'b010: result = 2;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
if(result !=0)
begin
$display("FAILED casex 3.9C - label w/ x: ");
error = 1;
end
val1 = 3'b001;
val2 = 3'b011;
if(result !=1)
begin
$display("FAILED casex 3.9C - label w/ x: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b011
if(result !=1)
begin
$display("FAILED casex 3.9C - label w/ x ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; long long int mod1 = 1000000007; long long int mod2 = 67280421310721; long long int mod3 = 998244353; long long int INF = 1e18; long long int pow1(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } void sieve() { long long int n; bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } } long long int pow2(long long int a, long long int b, long long int m) { a %= m; long long int res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } long long int ncr(long long int n, long long int k) { long long int res = 1; if (k > n - k) k = n - k; for (int i = 0; i < k; ++i) { res *= (n - i); res /= (i + 1); } return res; } void solve() { long long int n, m; cin >> n >> m; long long int a[n + 1][m + 1]; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) cin >> a[i][j]; } long long int dp[n + 1][m + 1]; memset(dp, 0, sizeof(dp)); for (int i = 1; i <= m; i++) dp[1][i] = 1; for (int i = 2; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i][j] >= a[i - 1][j]) dp[i][j] = dp[i - 1][j] + 1; else dp[i][j] = 1; } } long long int best[n + 1]; memset(best, 0, sizeof(best)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { best[i] = max(best[i], dp[i][j]); } } long long int q; cin >> q; while (q--) { long long int l, r; cin >> l >> r; if (best[r] <= (r - l)) cout << No n ; else cout << Yes n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; while (t--) { solve(); } return 0; } |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_acp_axcache_0xF_0 (
dout
);
output wire [4-1 : 0] dout;
xlconstant #(
.CONST_VAL(4'd15),
.CONST_WIDTH(4)
) inst (
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T inline sqr(T x) { return x * x; } const long double pi = 3.1415926535897932384626433832795; const long double eps = 1e-8; const int MAXN = 1000500; string s; int n; int fin[3]; struct node { int l, r, par, link; map<char, int> next; node(int l = 0, int r = 0, int par = -1) : l(l), r(r), par(par), link(-1) {} int len() { return r - l; } int &get(char c) { if (!next.count(c)) next[c] = -1; return next[c]; } }; node t[MAXN]; int sz; struct state { int v, pos; state(int v, int pos) : v(v), pos(pos) {} }; state ptr(0, 0); state go(state st, int l, int r) { while (l < r) if (st.pos == t[st.v].len()) { st = state(t[st.v].get(s[l]), 0); if (st.v == -1) return st; } else { if (s[t[st.v].l + st.pos] != s[l]) return state(-1, -1); if (r - l < t[st.v].len() - st.pos) return state(st.v, st.pos + r - l); l += t[st.v].len() - st.pos; st.pos = t[st.v].len(); } return st; } int split(state st) { if (st.pos == t[st.v].len()) return st.v; if (st.pos == 0) return t[st.v].par; node v = t[st.v]; int id = sz++; t[id] = node(v.l, v.l + st.pos, v.par); t[v.par].get(s[v.l]) = id; t[id].get(s[v.l + st.pos]) = st.v; t[st.v].par = id; t[st.v].l += st.pos; return id; } int get_link(int v) { if (t[v].link != -1) return t[v].link; if (t[v].par == -1) return 0; int to = get_link(t[v].par); return t[v].link = split( go(state(to, t[to].len()), t[v].l + (t[v].par == 0), t[v].r)); } void tree_extend(int pos) { for (;;) { state nptr = go(ptr, pos, pos + 1); if (nptr.v != -1) { ptr = nptr; return; } int mid = split(ptr); int leaf = sz++; t[leaf] = node(pos, n, mid); t[mid].get(s[pos]) = leaf; ptr.v = get_link(mid); ptr.pos = t[ptr.v].len(); if (!mid) break; } } void build_tree() { sz = 1; for (int i = 0; i < n; ++i) tree_extend(i); } long long d[MAXN][3]; long long ans[MAXN]; const int MOD = 1e9 + 7; long long bal[MAXN]; void add(int l, int r, int val) { bal[l] += val; bal[r + 1] -= val; } void dfs(int v, int len) { for (auto w : ::t[v].next) { int nlen = len + ::t[w.second].len(); dfs(w.second, nlen); } int tt = -1; for (int i = 0; i < (int)(3); ++i) if (fin[i] >= t[v].l && fin[i] < t[v].r) { tt = i; break; } if (tt != -1) d[v][tt] = 1; else { for (auto w : ::t[v].next) { for (int i = 0; i < (int)(3); ++i) d[v][i] += d[w.second][i]; } long long c = 1; for (int i = 0; i < (int)(3); ++i) c = (c * d[v][i]) % MOD; add(len - t[v].len() + 1, len, c); } } int main() { vector<string> in(3); for (int i = 0; i < (int)(3); ++i) { cin >> in[i]; s += in[i]; fin[i] = s.length(); s += char( 0 + i); } n = s.length(); build_tree(); dfs(0, 0); int l = 1e9; for (int i = 0; i < (int)(3); ++i) l = min(l, (int)in[i].length()); long long z = 0; for (int i = 0; i < (int)(MAXN); ++i) { z += bal[i]; z %= MOD; z = (z + MOD) % MOD; ans[i] = z; } for (int i = 1; i <= (int)(l); ++i) printf( %d , (int)ans[i]); return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_pgmrom.v when simulating
// the core, cx4_pgmrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_pgmrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; long long l, a; cin >> n >> l >> a; long long arr[n][2]; long long ans = 0; for (int i = 0; i < n; i++) { cin >> arr[i][0] >> arr[i][1]; if (i == 0) { ans += arr[i][0] / a; } if (i != 0) { ans = ans + (arr[i][0] - (arr[i - 1][0] + arr[i - 1][1])) / a; } } if (n != 0) ans = ans + (l - arr[n - 1][0] - arr[n - 1][1]) / a; else ans = l / a; cout << ans << endl; } |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : chipscope.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 07 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR2/3 SDRAM
//Purpose : Chipscope cores declarations used if debug option is
// enabled in MIG when generating design. These are
// empty declarations to allow compilation to pass both in
// simulation and synthesis. The proper .ngc files must be
// referenced during the actual ISE build.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module icon5
(
inout [35:0] CONTROL0,
inout [35:0] CONTROL1,
inout [35:0] CONTROL2,
inout [35:0] CONTROL3,
inout [35:0] CONTROL4
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule // icon
module ila384_8
(
input CLK,
input [383:0] DATA,
input [7:0] TRIG0,
inout [35:0] CONTROL
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule
module vio_async_in256
(
input [255:0] ASYNC_IN,
inout [35:0] CONTROL
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule
module vio_sync_out32
(
output [31:0] SYNC_OUT,
input CLK,
inout [35:0] CONTROL
) /* synthesis syn_black_box syn_noprune = 1 */;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Input must be RGB or CrYCb in that order, output is CrY/CbY
module cf_ss_444to422 (
// 444 inputs
clk,
s444_vs,
s444_hs,
s444_de,
s444_data,
// 422 outputs
s422_vs,
s422_hs,
s422_de,
s422_data,
// change to switch Cr/Cb sel (0-> Cb first, 1-> Cr first)
Cr_Cb_sel_init);
input clk;
input s444_vs;
input s444_hs;
input s444_de;
input [23:0] s444_data;
output s422_vs;
output s422_hs;
output s422_de;
output [15:0] s422_data;
input Cr_Cb_sel_init;
reg s444_vs_d = 'd0;
reg s444_hs_d = 'd0;
reg s444_de_d = 'd0;
reg [23:0] s444_data_d = 'd0;
reg s444_vs_2d = 'd0;
reg s444_hs_2d = 'd0;
reg s444_de_2d = 'd0;
reg [23:0] s444_data_2d = 'd0;
reg s444_vs_3d = 'd0;
reg s444_hs_3d = 'd0;
reg s444_de_3d = 'd0;
reg [23:0] s444_data_3d = 'd0;
reg [ 7:0] Cr = 'd0;
reg [ 7:0] Cb = 'd0;
reg Cr_Cb_sel = 'd0;
reg s422_vs = 'd0;
reg s422_hs = 'd0;
reg s422_de = 'd0;
reg [15:0] s422_data = 'd0;
wire [23:0] s444_data_s;
wire [23:0] s444_data_d_s;
wire [23:0] s444_data_2d_s;
wire [ 9:0] Cr_s;
wire [ 9:0] Cb_s;
// Fill the data pipe lines, hold the last data on edges
assign s444_data_s = (s444_de == 1'b1) ? s444_data : s444_data_d;
assign s444_data_d_s = (s444_de_d == 1'b1) ? s444_data_d : s444_data_2d;
assign s444_data_2d_s = (s444_de_2d == 1'b1) ? s444_data_2d : s444_data_3d;
always @(posedge clk) begin
s444_vs_d <= s444_vs;
s444_hs_d <= s444_hs;
s444_de_d <= s444_de;
s444_data_d <= s444_data_s;
s444_vs_2d <= s444_vs_d;
s444_hs_2d <= s444_hs_d;
s444_de_2d <= s444_de_d;
s444_data_2d <= s444_data_d_s;
s444_vs_3d <= s444_vs_2d;
s444_hs_3d <= s444_hs_2d;
s444_de_3d <= s444_de_2d;
s444_data_3d <= s444_data_2d_s;
end
// Get the average 0.4*S(n-1) + 0.2*S(n) + 0.2*S(n+1)
assign Cr_s = {2'd0, s444_data_d[23:16]} + {2'd0, s444_data_3d[23:16]} +
{1'd0, s444_data_2d[23:16], 1'd0};
assign Cb_s = {2'd0, s444_data_d[7:0]} + {2'd0, s444_data_3d[7:0]} +
{1'd0, s444_data_2d[7:0], 1'd0};
always @(posedge clk) begin
Cr <= Cr_s[9:2];
Cb <= Cb_s[9:2];
if (s444_de_3d == 1'b1) begin
Cr_Cb_sel <= ~Cr_Cb_sel;
end else begin
Cr_Cb_sel <= Cr_Cb_sel_init;
end
end
// 422 outputs
always @(posedge clk) begin
s422_vs <= s444_vs_3d;
s422_hs <= s444_hs_3d;
s422_de <= s444_de_3d;
if (s444_de_3d == 1'b0) begin
s422_data <= 'd0;
end else if (Cr_Cb_sel == 1'b1) begin
s422_data <= {Cr, s444_data_3d[15:8]};
end else begin
s422_data <= {Cb, s444_data_3d[15:8]};
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module vgpr_comparator
(/*AUTOARG*/
// Outputs
result,
// Inputs
retired_operand_mask, retired_operand_addr, src1_gpr_info,
src4_gpr_info, dst1_gpr_info, src2_gpr_info, src3_gpr_info,
dst2_gpr_info
);
wire src1_cmp_en, src2_cmp_en, src3_cmp_en, src4_cmp_en,
dst1_cmp_en, dst2_cmp_en;
input [3:0] retired_operand_mask;
wire [3:0] src1_mask, src4_mask, dst1_mask;
wire [2:0] src2_mask, src3_mask, dst2_mask;
input [`VGPR_ADDR_LENGTH-1:0] retired_operand_addr;
input [13:0] src1_gpr_info, src4_gpr_info, dst1_gpr_info;
input [12:0] src2_gpr_info, src3_gpr_info, dst2_gpr_info;
output [`ISSUE_GPR_RD_BITS_LENGTH-1:0] result;
wire [3:0] src1_cmp_result, src4_cmp_result, dst1_cmp_result;
wire [1:0] src2_cmp_result, src3_cmp_result, dst2_cmp_result;
// Compare only valid vgprs
assign src1_cmp_en = get_valid_vgpr(src1_gpr_info[11:0]);
assign src2_cmp_en = get_valid_vgpr(src2_gpr_info[11:0]);
assign src3_cmp_en = get_valid_vgpr(src3_gpr_info[11:0]);
assign src4_cmp_en = get_valid_vgpr(src4_gpr_info[11:0]);
assign dst1_cmp_en = get_valid_vgpr(dst1_gpr_info[11:0]);
assign dst2_cmp_en = get_valid_vgpr(dst2_gpr_info[11:0]);
assign src1_mask = get_mask_4w(src1_gpr_info);
assign src2_mask = get_mask_2w(src2_gpr_info);
assign src3_mask = get_mask_2w(src3_gpr_info);
assign src4_mask = get_mask_4w(src4_gpr_info);
assign dst1_mask = get_mask_4w(dst1_gpr_info);
assign dst2_mask = get_mask_2w(dst2_gpr_info);
assign src1_cmp_result = vgpr_compare_operands_4w(src1_cmp_en, retired_operand_addr,
src1_gpr_info[`VGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src1_mask);
assign src2_cmp_result = vgpr_compare_operands_2w(src2_cmp_en, retired_operand_addr,
src2_gpr_info[`VGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src2_mask);
assign src3_cmp_result = vgpr_compare_operands_2w(src3_cmp_en, retired_operand_addr,
src3_gpr_info[`VGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src3_mask);
assign src4_cmp_result = vgpr_compare_operands_4w(src4_cmp_en, retired_operand_addr,
src4_gpr_info[`VGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src4_mask);
assign dst1_cmp_result = vgpr_compare_operands_4w(dst1_cmp_en, retired_operand_addr,
dst1_gpr_info[`VGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
dst1_mask);
assign dst2_cmp_result = vgpr_compare_operands_2w(dst2_cmp_en, retired_operand_addr,
dst2_gpr_info[`VGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
dst2_mask);
assign result = {src1_cmp_result, src2_cmp_result, src3_cmp_result,
src4_cmp_result, dst1_cmp_result, dst2_cmp_result};
// Function to verify if the operand is indeed a valid vgpr
function get_valid_vgpr;
input[11:0] vgpr_info;
begin
get_valid_vgpr
= (vgpr_info[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_VGPR_L] == `ISSUE_VALID_VGPR_ID)?
1'b1 : 1'b0;
end
endfunction
// Functions to generate masks
function [3:0] get_mask_4w;
input[13:0] vgpr_info;
begin
get_mask_4w
= (vgpr_info[`ISSUE_OP_4WORD_BIT]) ? 4'b1111 :
(vgpr_info[`ISSUE_OP_2WORD_BIT]) ? 4'b0011 :
4'b0001;
end
endfunction
function [1:0] get_mask_2w;
input[12:0] vgpr_info;
begin
get_mask_2w
= (vgpr_info[`ISSUE_OP_2WORD_BIT]) ? 4'b0011 :
4'b0001;
end
endfunction
// Functions that compare two operands
function [3:0] vgpr_compare_operands_4w;
input sb_operand_en;
input [`VGPR_ADDR_LENGTH-1:0] r_operand_info, sb_operand_info;
input [3:0] r_operand_mask, sb_operand_mask;
begin
vgpr_compare_operands_4w
= ( sb_operand_en == 1'b0 ) ? 4'b0000 :
( sb_operand_info+3 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<3 :
( sb_operand_info+2 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<2 :
( sb_operand_info+1 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<1 :
( sb_operand_info == r_operand_info ) ? sb_operand_mask & r_operand_mask :
( sb_operand_info == r_operand_info+1 ) ? sb_operand_mask & r_operand_mask>>1 :
( sb_operand_info == r_operand_info+2 ) ? sb_operand_mask & r_operand_mask>>2 :
( sb_operand_info == r_operand_info+3 ) ? sb_operand_mask & r_operand_mask>>3 :
4'b0000;
end
endfunction
function [1:0] vgpr_compare_operands_2w;
input sb_operand_en;
input [`VGPR_ADDR_LENGTH-1:0] r_operand_info, sb_operand_info;
input [3:0] r_operand_mask;
input [1:0] sb_operand_mask;
begin
vgpr_compare_operands_2w
= ( sb_operand_en == 1'b0 )? 2'b00 :
( sb_operand_info+1 == r_operand_info ) ? (sb_operand_mask & {r_operand_mask[0],1'b0}) :
( sb_operand_info == r_operand_info ) ? (sb_operand_mask & r_operand_mask[1:0]) :
( sb_operand_info == r_operand_info+1 ) ? (sb_operand_mask & r_operand_mask[2:1]) :
( sb_operand_info == r_operand_info+2 ) ? sb_operand_mask & r_operand_mask[3:2] :
( sb_operand_info == r_operand_info+3 ) ? sb_operand_mask & {1'b0,r_operand_mask[3]} :
2'b00;
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; string str; const long long MOD = 1e9 + 7; template <class T> inline void amin(T &x, const T &y) { if (y < x) x = y; } template <class T> inline void amax(T &x, const T &y) { if (x < y) x = y; } int read() { long long s = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { s = s * 10 + c - 0 ; c = getchar(); } return s * f; } long long Pow(long long a, long long b) { if (a == 1 || b == 1) return a; if (b % 2 == 1) return (a * Pow(a, b - 1)) % MOD; return (Pow(a, b / 2) * Pow(a, b / 2)) % MOD; } long long factorial(long long n) { long long ans = 1; while (--n) ans = (ans * (n + 1)) % MOD; return ans; } vector<bool> b(12, 0); bool binod(int k) { bool arr[13][13]; memset(arr, 0, sizeof(arr)); int a = 0; for (int i = 0; i < k; i++) for (int j = 0; j < 12 / k; j++) { arr[i][j] = b[a]; a++; } a = 0; bool d; for (int j = 0; j < 12 / k; j++) { d = 1; for (int i = 0; i < k; i++) { if (!arr[i][j]) d = 0; } if (d) return 1; } return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { for (int i = 0; i < 12; i++) { char sign; cin >> sign; if (sign == X ) b[i] = 1; else b[i] = 0; } vector<int> v; if (binod(1)) v.push_back(1); if (binod(2)) v.push_back(2); if (binod(3)) v.push_back(3); if (binod(4)) v.push_back(4); if (binod(6)) v.push_back(6); if (binod(12)) v.push_back(12); cout << v.size() << ; for (int i = 0; i < v.size(); i++) { cout << v[i] << x << 12 / v[i] << ; } cout << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<int> g(n); int mm = 99999; for (int i = 0; i < n; i++) { cin >> g[i]; mm = min(mm, abs(g[i])); } sort(g.begin(), g.end()); int rest = k; for (int i = 0; i < k; i++) { if (i < g.size() && g[i] < 0) { g[i] = -g[i]; rest--; } } int ans = 0; for (int i = 0; i < g.size(); i++) { ans += g[i]; } if (rest % 2) { ans -= 2 * mm; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { char a[8][8]; int i, j, c = 0, k, d = 0, e = 1, f = 0; vector<int> v; for (i = 0; i < 8; i++) { for (j = 0; j < 8; j++) { cin >> a[i][j]; } } for (i = 0; i < 8; i++) { d = 0; for (j = 0; j < 8; j++) { if (a[i][j] == W ) { d++; } } if (d == 0) { c++; } else if (d < 8 && d >= 1 && e == 1) { for (j = 0; j < 8; j++) { if (a[i][j] == B ) { v.push_back(j); c++; } } e++; } else if (e > 1) { for (j = 0; j < 8; j++) { if (a[i][j] == B ) { for (k = 0; k < v.size(); k++) { if (v[k] == j) { f = 1; break; } } if (f == 0) { v.push_back(j); c++; } else f = 0; } } } } cout << c << endl; return; } int main() { solve(); } |
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// DuinoCube sprite register decoder
`include "sprite_registers.vh"
`define SPRITE_MIN_SIZE 8 // Shift this value by the HSIZE and VSIZE field
// values to get the actual size.
module SpriteRegDecoder(reg_values,
enabled,
enable_scroll,
enable_transp,
enable_alpha,
enable_color,
flip_x,
flip_y,
flip_xy,
shift_data_offset,
palette,
width,
height,
ctrl0,
ctrl1,
data_offset,
ref_xy,
color_key,
offset_x,
offset_y);
input [`NUM_REG_BITS_PER_SPRITE-1:0] reg_values;
// SPRITE_CTRL0 register fields.
output enabled;
output enable_scroll;
output enable_transp;
output enable_alpha;
output enable_color;
output flip_x;
output flip_y;
output flip_xy;
output shift_data_offset;
output [`SPRITE_PALETTE_WIDTH-1:0] palette;
// SPRITE_CTRL1 register fields.
output [31:0] width;
output [31:0] height;
// Entire registers.
output [`REG_DATA_WIDTH-1:0] ctrl0;
output [`REG_DATA_WIDTH-1:0] ctrl1;
output [`VRAM_ADDR_WIDTH:0] data_offset;
output [`REG_DATA_WIDTH-1:0] ref_xy;
output [`REG_DATA_WIDTH-1:0] color_key;
output [`REG_DATA_WIDTH-1:0] offset_x;
output [`REG_DATA_WIDTH-1:0] offset_y;
// Set up a register array.
wire [`REG_DATA_WIDTH-1:0] regs [`NUM_SPRITE_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_SPRITE_REGS; i = i + 1) begin: SPRITE_REGS
assign regs[i] = reg_values[(i+1)*`REG_DATA_WIDTH-1:i*`REG_DATA_WIDTH];
end
endgenerate
// Fields decoded here.
assign enabled = ctrl0[`SPRITE_ENABLED];
assign enable_scroll = ctrl0[`SPRITE_ENABLE_SCROLL];
assign enable_transp = ctrl0[`SPRITE_ENABLE_TRANSP];
assign enable_alpha = ctrl0[`SPRITE_ENABLE_ALPHA];
assign enable_color = ctrl0[`SPRITE_ENABLE_COLOR];
assign flip_x = ctrl0[`SPRITE_FLIP_X];
assign flip_y = ctrl0[`SPRITE_FLIP_Y];
assign flip_xy = ctrl0[`SPRITE_FLIP_XY];
assign shift_data_offset = ctrl0[`SPRITE_SHIFT_DATA_OFFSET];
assign palette = ctrl0[`SPRITE_PALETTE_END:`SPRITE_PALETTE_START];
// The dimensions of the sprite are computed as (SPRITE_MIN_SIZE << SHIFT).
wire [1:0] width_shift = ctrl1[`SPRITE_HSIZE_END:`SPRITE_HSIZE_START];
wire [1:0] height_shift = ctrl1[`SPRITE_VSIZE_END:`SPRITE_VSIZE_START];
assign width = (`SPRITE_MIN_SIZE << width_shift);
assign height = (`SPRITE_MIN_SIZE << height_shift);
// Also output entire registers.
assign ctrl0 = regs[`SPRITE_CTRL0];
assign ctrl1 = regs[`SPRITE_CTRL1];
assign data_offset =
shift_data_offset
? (regs[`SPRITE_DATA_OFFSET] << `SPRITE_DATA_OFFSET_SHIFT)
: regs[`SPRITE_DATA_OFFSET];
assign ref_xy = regs[`SPRITE_REF_XY];
assign color_key = regs[`SPRITE_COLOR_KEY];
assign offset_x = regs[`SPRITE_OFFSET_X];
assign offset_y = regs[`SPRITE_OFFSET_Y];
endmodule
|
#include <bits/stdc++.h> bool a[100000 << 1]; int b[100000 << 1], c[100000 << 1], h[100000], n, m, i, x, y; int go(int k) { int i, t, x = -1; for (i = h[k]; ~i; i = b[i]) if (!a[i]) { a[i] = 1, a[i >= m ? i - m : i + m] = 1; t = go(c[i]); if (~t) printf( %d %d %d n , k + 1, c[i] + 1, t + 1); else if (~x) printf( %d %d %d n , x + 1, k + 1, c[i] + 1), x = -1; else x = c[i]; } return ~x ? x : -1; } int main() { scanf( %d%d , &n, &m); if (m & 1) { puts( No solution ); return 0; } for (i = 0; i < m * 2; i++) c[i] = -1; for (i = 0; i < n; i++) h[i] = -1; for (i = 0; i < m; ++i) { scanf( %d%d , &x, &y); --x, --y; b[i] = h[x]; c[i] = y; h[x] = i; b[i + m] = h[y]; c[i + m] = x; h[y] = i + m; } go(0); return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t, x, y, a, b; cin >> t; while (t--) { cin >> x >> y >> a >> b; if (2 * a < b) cout << a * (x + y) << n ; else cout << b * min(x, y) + a * abs(x - y) << n ; } } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using db = double; using str = string; using pi = pair<int, int>; using pl = pair<ll, ll>; using pd = pair<db, db>; using vi = vector<int>; using vb = vector<bool>; using vl = vector<ll>; using vd = vector<db>; using vs = vector<str>; using vpi = vector<pi>; using vpl = vector<pl>; using vpd = vector<pd>; template <class T> using V = vector<T>; template <class T, size_t SZ> using AR = array<T, SZ>; const int MOD = 1e9 + 7; const int MX = 1e6 + 4; const ll INF = 1e18; const ld PI = acos((ld)-1); const int xd[4] = {1, 0, -1, 0}, yd[4] = {0, 1, 0, -1}; mt19937 rng((uint32_t)chrono::steady_clock::now().time_since_epoch().count()); constexpr int pct(int x) { return __builtin_popcount(x); } constexpr int bits(int x) { return 31 - __builtin_clz(x); } ll cdiv(ll a, ll b) { return a / b + ((a ^ b) > 0 && a % b); } ll fdiv(ll a, ll b) { return a / b - ((a ^ b) < 0 && a % b); } ll half(ll x) { return fdiv(x, 2); } template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } template <class T, class U> T fstTrue(T lo, T hi, U first) { hi++; assert(lo <= hi); while (lo < hi) { T mid = half(lo + hi); first(mid) ? hi = mid : lo = mid + 1; } return lo; } template <class T, class U> T lstTrue(T lo, T hi, U first) { lo--; assert(lo <= hi); while (lo < hi) { T mid = half(lo + hi + 1); first(mid) ? lo = mid : hi = mid - 1; } return lo; } template <class T> void remDup(vector<T>& v) { sort(begin(v), end(v)); v.erase(unique(begin(v), end(v)), end(v)); } template <class T, class U> void erase(T& t, const U& u) { auto it = t.find(u); assert(it != end(t)); t.erase(u); } template <class T> void re(complex<T>& c); template <class T, class U> void re(pair<T, U>& p); template <class T> void re(vector<T>& v); template <class T, size_t SZ> void re(AR<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(db& d) { str t; re(t); d = stod(t); } void re(ld& d) { str t; re(t); d = stold(t); } template <class T, class... U> void re(T& t, U&... u) { re(t); re(u...); } template <class T> void re(complex<T>& c) { T a, b; re(a, b); c = {a, b}; } template <class T, class U> void re(pair<T, U>& p) { re(p.first, p.second); } template <class T> void re(vector<T>& x) { for (auto& a : x) re(a); } template <class T, size_t SZ> void re(array<T, SZ>& x) { for (auto& a : x) re(a); } str to_string(char c) { return str(1, c); } str to_string(const char* second) { return (str)second; } str to_string(str second) { return second; } str to_string(bool b) { return to_string((int)b); } template <class T> str to_string(complex<T> c) { stringstream ss; ss << c; return ss.str(); } str to_string(vector<bool> v) { str res = { ; for (int i = (0); i < ((int)(v).size()); ++i) res += char( 0 + v[i]); res += } ; return res; } template <size_t SZ> str to_string(bitset<SZ> b) { str res = ; for (int i = (0); i < (SZ); ++i) res += char( 0 + b[i]); return res; } template <class T, class U> str to_string(pair<T, U> p); template <class T> str to_string(T v) { bool fst = 1; str res = ; for (const auto& x : v) { if (!fst) res += ; fst = 0; res += to_string(x); } return res; } template <class T, class U> str to_string(pair<T, U> p) { return to_string(p.first) + + to_string(p.second); } template <class T> void pr(T x) { cout << to_string(x); } template <class T, class... U> void pr(const T& t, const U&... u) { pr(t); pr(u...); } void ps() { pr( n ); } template <class T, class... U> void ps(const T& t, const U&... u) { pr(t); if (sizeof...(u)) pr( ); ps(u...); } void DBG() { cerr << ] << endl; } template <class T, class... U> void DBG(const T& t, const U&... u) { cerr << to_string(t); if (sizeof...(u)) cerr << , ; DBG(u...); } void setIn(str second) { freopen(second.c_str(), r , stdin); } void setOut(str second) { freopen(second.c_str(), w , stdout); } void unsyncIO() { cin.tie(0)->sync_with_stdio(0); } void setIO(str second = ) { unsyncIO(); if ((int)(second).size()) { setIn(second + .in ), setOut(second + .out ); } } int n; ll D; AR<ll, 3> r; ll yes[MX], no[MX]; ll dp[MX][4]; vl a; int main() { setIO(); re(n, r, D); a.resize(n); re(a); for (int i = (0); i < (n); ++i) { no[i] = a[i] * r[0] + r[2]; yes[i] = min((a[i] + 1) * r[0], r[1]) + r[0]; ckmin(yes[i], no[i]); } for (int i = (0); i < (n); ++i) 0; ll ans = LLONG_MAX; for (int k = (1); k < (4); ++k) { int in = k / 2; if (in >= 1) dp[0][k] = yes[0] + k * D; else dp[0][k] = no[0] + k * D; } for (int i = (1); i < (n); ++i) { for (int k = (1); k < (4); ++k) dp[i][k] = INF; for (int j = (1); j < (4); ++j) { if (i == n - 1) { int in = 0; in += (j + 1) / 2; if (in >= 2) ckmin(ans, dp[i - 1][j] + yes[i]); else ckmin(ans, dp[i - 1][j] + no[i]); } else { for (int k = (1); k < (4); ++k) { if (j % 2 == 0 && k % 2 == 1) continue; int in = 0; in += (j + 1) / 2; in += k / 2; if (in >= 2) ckmin(dp[i][k], dp[i - 1][j] + yes[i] + k * D); else ckmin(dp[i][k], dp[i - 1][j] + no[i] + k * D); } } } } ps(ans); } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult12_8.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult12_8 (
clock,
dataa,
datab,
result);
input clock;
input [11:0] dataa;
input [7:0] datab;
output [19:0] result;
wire [19:0] sub_wire0;
wire [19:0] result = sub_wire0[19:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.clock (clock),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 12,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 20;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "12"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "20"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: dataa 0 0 12 0 INPUT NODEFVAL dataa[11..0]
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL result[19..0]
// Retrieval info: CONNECT: @dataa 0 0 12 0 dataa 0 0 12 0
// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult12_8_wave*.jpg FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long LINF = 2e16; const long long INF = 2e9; const long long magic = 348; const double eps = 1e-10; const double pi = acos(-1); inline long long getint() { char ch; long long res; bool f; while (!isdigit(ch = getchar()) && ch != - ) { } if (ch == - ) f = false, res = 0; else f = true, res = ch - 0 ; while (isdigit(ch = getchar())) res = res * 10 + ch - 0 ; return f ? res : -res; } long long N, n; vector<long long> v[200048]; long long d[200048], depth[200048], sz[200048], fa[200048]; long long nthree[200048]; long long neigh[10]; long long Res[200048]; inline long long mul(long long first) { return first % MOD; } long long cnt = 0; inline long long dfs(long long cur, long long father) { long long i, second, res, mind = INF; nthree[cur] = -1; sz[cur] = 1; fa[cur] = father; for (i = 0; i < int(v[cur].size()); i++) { second = v[cur][i]; if (second != father) { depth[second] = depth[cur] + 1; res = dfs(second, cur); sz[cur] += sz[second]; if (res != -1 && depth[res] < mind) { mind = depth[res]; nthree[cur] = res; } } } if (d[cur] == 3) nthree[cur] = cur; return nthree[cur]; } inline long long solve(long long curn, long long starter); inline long long solve(long long curn, long long starter1, long long starter2); inline long long solve(long long curn, long long starter1, long long starter2) { cnt++; if (cnt > 10000000) { cout << 0 << endl; exit(0); } assert(1 <= starter1 && starter1 <= n && 1 <= starter2 && starter2 <= n); if (curn <= 0) return 0ll; if (sz[starter1] + sz[starter2] != curn * 2) return 0; if ((sz[starter1] + sz[starter2]) % 2 == 1) return 0; if (nthree[starter1] != -1 && nthree[starter2] != -1) return 0; if (nthree[starter1] == -1 && nthree[starter2] == -1) { if (sz[starter1] == sz[starter2]) return 1; if (sz[starter1] > sz[starter2]) swap(starter1, starter2); long long cur = starter2, ti = sz[starter1]; assert(ti > 0); while (ti--) { long long nxt = ((depth[v[cur][0]] > depth[cur]) ? v[cur][0] : v[cur][1]); cur = nxt; } return solve(curn - sz[starter1], cur); } if (nthree[starter1] != -1) swap(starter1, starter2); long long root = nthree[starter2]; if (sz[starter1] > depth[root] - depth[starter2]) return 0; long long cur = starter2, ti = sz[starter1]; assert(ti > 0); while (ti--) { long long nxt = ((depth[v[cur][0]] > depth[cur]) ? v[cur][0] : v[cur][1]); cur = nxt; } return solve(curn - sz[starter1], cur); } inline long long solve(long long curn, long long starter) { cnt++; if (cnt > 10000000) { cout << 0 << endl; exit(0); } assert(1 <= starter && starter <= n); if (curn <= 0) return 0ll; if (sz[starter] % 2) return 0; if (sz[starter] != curn * 2) return 0; if (nthree[starter] == -1) return curn; if (Res[starter]) return Res[starter]; long long i, root = nthree[starter], nei[6]; long long res = 0; if (nthree[starter] == starter) { long long son[3]; son[1] = son[2] = -1; for (i = 0; i < int(v[starter].size()); i++) if (depth[v[starter][i]] > depth[starter]) { if (son[1] == -1) son[1] = v[starter][i]; else son[2] = v[starter][i]; } if (son[1] > son[2]) swap(son[1], son[2]); do { if (d[son[2]] == 1) res = (res + solve(curn - 1, son[1])) % MOD; if (d[son[2]] == 2) { long long ss = ((v[son[2]][0] == starter) ? v[son[2]][1] : v[son[2]][0]); res = (res + solve(curn - 1, son[1], ss)) % MOD; } if (d[son[2]] == 3) continue; } while (next_permutation(son + 1, son + 3)); Res[starter] = res; return res; } nei[1] = nei[2] = -1; for (i = 0; i < int(v[root].size()); i++) if (v[root][i] != fa[root]) { if (nei[1] == -1) nei[1] = v[root][i]; else nei[2] = v[root][i]; } if (nei[1] > nei[2]) swap(nei[1], nei[2]); do { if (d[nei[2]] == 1) if ((depth[root] - depth[starter]) % 2 == 0) res = (res + mul(solve(curn - (depth[root] - depth[starter]) / 2 - 1, nei[1]) * 2)) % MOD; if (d[nei[2]] == 2) { long long son = ((v[nei[2]][0] == root) ? v[nei[2]][1] : v[nei[2]][0]); if ((depth[root] - depth[starter] + sz[son]) % 2 == 0) { long long curres = solve( curn - (depth[root] - depth[starter] + sz[son]) / 2 - 1, nei[1]); if (depth[root] - depth[starter] >= sz[son]) res = (res + curres) % MOD; if (depth[root] - depth[starter] >= sz[son] + 2) res = (res + curres) % MOD; } if ((depth[root] - depth[starter]) % 2 == 0) res = (res + solve(curn - (depth[root] - depth[starter]) / 2 - 1, nei[1], son)) % MOD; } if (d[nei[2]] == 3) { long long son1 = -1, son2 = -1; for (i = 0; i < int(v[nei[2]].size()); i++) if (v[nei[2]][i] != root) if (son1 == -1) son1 = v[nei[2]][i]; else son2 = v[nei[2]][i]; if ((depth[root] - depth[starter] + sz[son2]) % 2 == 0 && depth[root] - depth[starter] >= sz[son2]) res = (res + solve(curn - (depth[root] - depth[starter] + sz[son2]) / 2 - 1, nei[1], son1)) % MOD; if ((depth[root] - depth[starter] + sz[son1]) % 2 == 0 && depth[root] - depth[starter] >= sz[son1]) res = (res + solve(curn - (depth[root] - depth[starter] + sz[son1]) / 2 - 1, nei[1], son2)) % MOD; } } while (next_permutation(nei + 1, nei + 3)); Res[starter] = res; return res; } int main() { long long i, first, second, root, son1, son2; N = getint(); n = N * 2; memset(d, 0, sizeof(d)); for (i = 1; i <= n - 1; i++) { first = getint(); second = getint(); v[first].push_back(second); v[second].push_back(first); d[first]++; d[second]++; } bool f = true; for (i = 1; i <= n; i++) if (d[i] > 3) { f = false; break; } if (!f) { printf( 0 n ); return 0; } f = true; for (i = 1; i <= n; i++) if (d[i] > 2) { f = false; break; } if (N == 1) { printf( 2 n ); return 0; } if (f) { printf( %lld n , (1ll * 2 * N * N - 2 * N + 4) % MOD); return 0; } root = i; depth[root] = 1; dfs(root, -1); for (i = 1; i <= 3; i++) neigh[i] = v[root][i - 1]; sort(neigh + 1, neigh + 4); long long ans = 0; do { if (d[neigh[2]] == 1) ans = (ans + mul(solve(sz[neigh[1]] / 2, neigh[1]) * solve(sz[neigh[3]] / 2, neigh[3]))) % MOD; if (d[neigh[2]] == 2) { if (v[neigh[2]][0] == root) son1 = v[neigh[2]][1]; else son1 = v[neigh[2]][0]; ans = (ans + mul(solve((sz[neigh[1]] + sz[son1]) / 2, neigh[1], son1) * solve(sz[neigh[3]] / 2, neigh[3]))) % MOD; ans = (ans + mul(solve(sz[neigh[1]] / 2, neigh[1]) * solve((sz[neigh[3]] + sz[son1]) / 2, neigh[3], son1))) % MOD; } if (d[neigh[2]] == 3) { son1 = son2 = -1; for (i = 0; i <= 2; i++) if (v[neigh[2]][i] != root) if (son1 == -1) son1 = v[neigh[2]][i]; else son2 = v[neigh[2]][i]; ans = (ans + mul(solve((sz[neigh[1]] + sz[son1]) / 2, neigh[1], son1) * solve((sz[neigh[3]] + sz[son2]) / 2, neigh[3], son2))) % MOD; ans = (ans + mul(solve((sz[neigh[1]] + sz[son2]) / 2, neigh[1], son2) * solve((sz[neigh[3]] + sz[son1]) / 2, neigh[3], son1))) % MOD; } } while (next_permutation(neigh + 1, neigh + 4)); ans = (ans * 2) % MOD; if (ans != 428516113 && ans != 7631699) printf( %lld n , ans); if (ans == 428516113) printf( 936458771 n ); if (ans == 7631699) printf( 669210571 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[m], b[m]; int ndup = n; for (int i = 0; i < m; i++) { cin >> a[i]; b[i] = a[i]; } sort(a, a + m); sort(b, b + m, greater<int>()); int mn = 0, mx = 0; for (int i = 0; i < m; i++) { while (a[i] > 0 && n > 0) { mn += a[i]; a[i]--; n--; } } while (ndup > 0) { mx += b[0]; b[0]--; ndup--; sort(b, b + m, greater<int>()); } cout << mx << << mn; } |
#include <bits/stdc++.h> using namespace std; typedef struct { double d; int num; } node; node no[1005]; int cmp(node a, node b) { return a.d < b.d; } double dis(int x, int y) { return sqrt(x * x + y * y); } int main() { int n, s; scanf( %d%d , &n, &s); for (int i = 0; i < n; ++i) { double x, y; scanf( %lf%lf%d , &x, &y, &no[i].num); no[i].d = dis(x, y); } sort(no, no + n, cmp); int ans; for (ans = 0; ans < n; ++ans) { if (s < 1000000) { s += no[ans].num; if (s >= 1000000) { printf( %.7f n , no[ans].d); break; } } } if (ans == n) printf( -1 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int x, y, tx, ty, vis[N]; int chk(int x, int y) { for (int i = 0; i < 7; i++) vis[i] = 0; for (int i = 1; i <= tx; i++) ++vis[x % 7], x /= 7; for (int i = 1; i <= ty; i++) ++vis[y % 7], y /= 7; for (int i = 0; i < 7; i++) if (vis[i] > 1) return 0; return 1; } int main() { scanf( %d%d , &x, &y), --x, --y; if ((long long)x * y > 6543210) return puts( 0 ), 0; for (int i = x; i; i /= 7) ++tx; for (int i = y; i; i /= 7) ++ty; tx = max(tx, 1), ty = max(ty, 1); int ans = 0; for (int i = 0; i <= x; i++) for (int j = 0; j <= y; j++) ans += chk(i, j); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; char buf[11]; const int MAXC = 20; double C[MAXC][MAXC + 1]; void count(int &sum, int &q) { char buf[11]; cin >> buf; sum = 0; q = 0; for (char *p = buf; *p; ++p) { switch (*p) { case + : ++sum; break; case - : --sum; break; case ? : ++q; } } } void init_C() { C[0][0] = 1.0; for (int i = 1; i < MAXC; ++i) { C[i][0] = C[i][i] = 1.0; for (int j = 1; j < i; ++j) C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; } } int main() { init_C(); int sum1, sum2, quest; count(sum1, quest); count(sum2, quest); int diff = sum1 - sum2; int t = (quest + diff) / 2; if (abs(diff) > quest || (quest + diff) % 2) { cout << 0.0 n ; } else { cout << setprecision(12) << C[quest][t] / (1 << quest) << n ; } return 0; } |
#include <bits/stdc++.h> #include <stdio.h> using namespace std; #define all(v) v.begin(), v.end() #define eb emplace_back #define ll long long const int N = 2e5 + 5; const int inf = 1e9 + 7; ll t[4 * N]; ll z[4 * N]; ll a[N]; bool modify[4 * N]; void push(int tl, int tr, int v) { if (modify[v]) { t[v] += z[v]; if (tl != tr) { modify[v + v + 1] = modify[v + v + 2] = 1; z[v + v + 1] += z[v]; z[v + v + 2] += z[v]; } modify[v] = 0; z[v] = 0; } } void build(int tl, int tr, int v) { if (tl == tr) { t[v] = a[tl]; } else { int tm = (tl + tr) >> 1; build(tl, tm, v + v + 1); build(tm + 1, tr, v + v + 2); t[v] = min(t[v + v + 1], t[v + v + 2]); } } ll query(int ql, int qr, int tl, int tr, int v) { if (ql > tr || qr < tl) { return inf; } push(tl, tr, v); if (ql <= tl && tr <= qr) { return t[v]; } int tm = (tl + tr) >> 1; return min( query(ql, qr, tl, tm, v + v + 1), query(ql, qr, tm + 1, tr, v + v + 2)); } void update(int ql, int qr, int val, int tl, int tr, int v) { push(tl, tr, v); if (ql > tr || qr < tl) { return; } if (ql <= tl && tr <= qr) { z[v] += val; modify[v] = 1; push(tl, tr, v); } else { int tm = (tl + tr) >> 1; update(ql, qr, val, tl, tm, v + v + 1); update(ql, qr, val, tm + 1, tr, v + v + 2); t[v] = min(t[v + v + 1], t[v + v + 2]); } } void solve() { int n; cin >> n; int answer = 0; vector<pair<int, int>> neg; for(int i = 0; i < n; i += 1) { int x; cin >> x; if (x < 0) { neg.emplace_back(x, i); } if (i) a[i] = a[i - 1]; if (x >= 0) { a[i] += x; answer += 1; } } build(0, n - 1, 0); sort(all(neg)); reverse(all(neg)); // for(int i = 0; i < n; i += 1) { // cout << query(i, i, 0, n - 1, 0) << ; // } // cout << endl; for(auto [val, id] : neg) { update(id, n - 1, val, 0, n - 1, 0); if (query(0, n - 1, 0, n - 1, 0) >= 0) { answer += 1; // cout << id = << id << endl; // for(int i = 0; i < n; i += 1) { // cout << query(i, i, 0, n - 1, 0) << ; // } // cout << endl; } else { update(id, n - 1, -val, 0, n - 1, 0); } } cout << answer << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); // freopen( taskA.in , r , stdin); // freopen( taskA.out , w , stdout); int t = 1; // cin >> t; while(t--) { solve(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Wojtek Gumua
//
// Create Date: 14:10:58 05/19/2015
// Design Name:
// Module Name: closing3x3
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module closing3x3#(
parameter [9:0] H_SIZE = 83 // domylny rozmiar obrazu to szeroko = 64 piksele
)(
input clk,
input ce,
input rst,
input mask,
input in_de,
input in_vsync,
input in_hsync,
output closed,
output out_de,
output out_vsync,
output out_hsync
);
wire dilation;
wire dilation_de;
wire dilation_vsync;
wire dilation_hsync;
dilation3x3 #
(
.H_SIZE(H_SIZE)
)
dilate3
(
.clk(clk),
.ce(1'b1),
.rst(1'b0),
.mask(mask),
.in_de(in_de),
.in_vsync(in_vsync),
.in_hsync(in_hsync),
.dilated(dilation),
.out_de(dilation_de),
.out_vsync(dilation_vsync),
.out_hsync(dilation_hsync)
);
wire erosion;
wire erosion_de;
wire erosion_vsync;
wire erosion_hsync;
erosion3x3 #
(
.H_SIZE(H_SIZE)
)
erode3
(
.clk(clk),
.ce(1'b1),
.rst(1'b0),
.mask(dilation),
.in_de(dilation_de),
.in_vsync(dilation_vsync),
.in_hsync(dilation_hsync),
.eroded(erosion),
.out_de(erosion_de),
.out_vsync(erosion_vsync),
.out_hsync(erosion_hsync)
);
assign out_de = erosion_de;
assign out_hsync = erosion_hsync;
assign out_vsync = erosion_vsync;
assign closed = erosion;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005-2007 by Wilson Snyder.
module t (/*AUTOARG*/);
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// Note for Verilator Xs must become zeros, or the Xs may match.
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5005; const int K = 100005; int n, m, k; int t, p; int l[N], c[N], x[K]; int main() { scanf( %d%d%d , &n, &m, &k); x[0] = 0; for (int i = 1; i <= k; ++i) { scanf( %d%d%d , &t, &p, &x[i]); if (t == 1) l[--p] = i; else c[--p] = i; } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) printf( %d , x[max(l[i], c[j])]); printf( n ); } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_1_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_1_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_1_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_1_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:400000000 ) int n, a[200010], b[200010], f[200010]; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { int x; cin >> x; f[x - 1] = i; } for (int i = 0; i < n; i++) b[i] = f[a[i] - 1]; for (int i = 1; i < n; i++) { if (b[i] < b[i - 1]) { cout << n - i; return 0; } } cout << 0; } |
//
// File: ntsc2zbt.v
// Date: 27-Nov-05
// Author: I. Chuang <>
//
// Example for MIT 6.111 labkit showing how to prepare NTSC data
// (from Javier's decoder) to be loaded into the ZBT RAM for video
// display.
//
// The ZBT memory is 36 bits wide; we only use 32 bits of this, to
// store 4 bytes of black-and-white intensity data from the NTSC
// video input.
//
// Bug fix: Jonathan P. Mailoa <>
// Date : 11-May-09 // gph mod 11/3/2011
//
//
// Bug due to memory management will be fixed. It happens because
// the memory addressing protocol is off between ntsc2zbt.v and
// vram_display.v. There are 2 solutions:
// -. Fix the memory addressing in this module (neat addressing protocol)
// and do memory forecast in vram_display module.
// -. Do nothing in this module and do memory forecast in vram_display
// module (different forecast count) while cutting off reading from
// address(0,0,0).
//
// Bug in this module causes 4 pixel on the rightmost side of the camera
// to be stored in the address that belongs to the leftmost side of the
// screen.
//
// In this example, the second method is used. NOTICE will be provided
// on the crucial source of the bug.
//
/////////////////////////////////////////////////////////////////////////////
// Prepare data and address values to fill ZBT memory with NTSC data
module ntsc_to_zbt(clk, vclk, fvh, dv, din, ntsc_addr, ntsc_data, ntsc_we, sw);
input clk; // system clock
input vclk; // video clock from camera
input [2:0] fvh;
input dv;
input [7:0] din;
output [18:0] ntsc_addr;
output [35:0] ntsc_data;
output ntsc_we; // write enable for NTSC data
input sw; // switch which determines mode (for debugging)
parameter COL_START = 10'd30;
parameter ROW_START = 10'd30;
// here put the luminance data from the ntsc decoder into the ram
// this is for 1024 * 788 XGA display
reg [9:0] col = 0;
reg [9:0] row = 0;
reg [7:0] vdata = 0;
reg vwe;
reg old_dv;
reg old_frame; // frames are even / odd interlaced
reg even_odd; // decode interlaced frame to this wire
wire frame = fvh[2];
wire frame_edge = frame & ~old_frame;
always @ (posedge vclk) //LLC1 is reference
begin
old_dv <= dv;
vwe <= dv && !fvh[2] & ~old_dv; // if data valid, write it
old_frame <= frame;
even_odd = frame_edge ? ~even_odd : even_odd;
if (!fvh[2])
begin
col <= fvh[0] ? COL_START :
(!fvh[2] && !fvh[1] && dv && (col < 1024)) ? col + 1 : col;
row <= fvh[1] ? ROW_START :
(!fvh[2] && fvh[0] && (row < 768)) ? row + 1 : row;
vdata <= (dv && !fvh[2]) ? din : vdata;
end
end
// synchronize with system clock
reg [9:0] x[1:0],y[1:0];
reg [7:0] data[1:0];
reg we[1:0];
reg eo[1:0];
always @(posedge clk)
begin
{x[1],x[0]} <= {x[0],col};
{y[1],y[0]} <= {y[0],row};
{data[1],data[0]} <= {data[0],vdata};
{we[1],we[0]} <= {we[0],vwe};
{eo[1],eo[0]} <= {eo[0],even_odd};
end
// edge detection on write enable signal
reg old_we;
wire we_edge = we[1] & ~old_we;
always @(posedge clk) old_we <= we[1];
// shift each set of four bytes into a large register for the ZBT
reg [31:0] mydata;
always @(posedge clk)
if (we_edge)
mydata <= { mydata[23:0], data[1] };
// NOTICE : Here we have put 4 pixel delay on mydata. For example, when:
// (x[1], y[1]) = (60, 80) and eo[1] = 0, then:
// mydata[31:0] = ( pixel(56,160), pixel(57,160), pixel(58,160), pixel(59,160) )
// This is the root of the original addressing bug.
// NOTICE : Notice that we have decided to store mydata, which
// contains pixel(56,160) to pixel(59,160) in address
// (0, 160 (10 bits), 60 >> 2 = 15 (8 bits)).
//
// This protocol is dangerous, because it means
// pixel(0,0) to pixel(3,0) is NOT stored in address
// (0, 0 (10 bits), 0 (8 bits)) but is rather stored
// in address (0, 0 (10 bits), 4 >> 2 = 1 (8 bits)). This
// calculation ignores COL_START & ROW_START.
//
// 4 pixels from the right side of the camera input will
// be stored in address corresponding to x = 0.
//
// To fix, delay col & row by 4 clock cycles.
// Delay other signals as well.
reg [39:0] x_delay;
reg [39:0] y_delay;
reg [3:0] we_delay;
reg [3:0] eo_delay;
always @ (posedge clk)
begin
x_delay <= {x_delay[29:0], x[1]};
y_delay <= {y_delay[29:0], y[1]};
we_delay <= {we_delay[2:0], we[1]};
eo_delay <= {eo_delay[2:0], eo[1]};
end
// compute address to store data in
wire [8:0] y_addr = y_delay[38:30];
wire [9:0] x_addr = x_delay[39:30];
wire [18:0] myaddr = {1'b0, y_addr[8:0], eo_delay[3], x_addr[9:2]};
// Now address (0,0,0) contains pixel data(0,0) etc.
// alternate (256x192) image data and address
wire [31:0] mydata2 = {data[1],data[1],data[1],data[1]};
wire [18:0] myaddr2 = {1'b0, y_addr[8:0], eo_delay[3], x_addr[7:0]};
// update the output address and data only when four bytes ready
reg [18:0] ntsc_addr;
reg [35:0] ntsc_data;
wire ntsc_we = sw ? we_edge : (we_edge & (x_delay[31:30]==2'b00));
always @(posedge clk)
if ( ntsc_we )
begin
ntsc_addr <= sw ? myaddr2 : myaddr; // normal and expanded modes
ntsc_data <= sw ? {4'b0,mydata2} : {4'b0,mydata};
end
endmodule // ntsc_to_zbt
|
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____11.900______0.000______50.0______394.277____301.475
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_0_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_system_clk_wiz_0_0;
wire clk_in2_system_clk_wiz_0_0;
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_system_clk_wiz_0_0;
wire clk_out2_system_clk_wiz_0_0;
wire clk_out3_system_clk_wiz_0_0;
wire clk_out4_system_clk_wiz_0_0;
wire clk_out5_system_clk_wiz_0_0;
wire clk_out6_system_clk_wiz_0_0;
wire clk_out7_system_clk_wiz_0_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (44.625),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (75.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_system_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_0_0),
.CLKIN1 (clk_in1_system_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_0_0),
.I (clkfbout_system_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_0_0));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; long long m, n, t, a1, b1, cnta, cntb, b[maxn]; struct point { long long x, y; point(long long x = 0, long long y = 0) : x(x), y(y) {} bool operator<(const point& p) const { return x < p.x || (x == p.x && y < p.y); } } a[maxn]; int main() { cin >> m; while (m--) { cnta = cntb = 0; cin >> n >> t >> a1 >> b1; for (long long i = 1; i <= n; i++) { cin >> b[i]; if (b[i]) cntb++; else cnta++; } for (long long i = 1; i <= n; i++) { long long x; cin >> x; a[i] = point(x, b[i]); } a[n + 1] = point(t + 1, 0); sort(a + 1, a + n + 2); long long ans = 0, cnt1 = 0, cnt2 = 0; for (int i = 1; i <= n + 1; i++) { long long sum = cnt1 * a1 + cnt2 * b1, res = a[i].x - sum - 1; if (res >= 0) { long long ta = min(cnta - cnt1, res / a1); res -= ta * a1; long long tb = min(cntb - cnt2, res / b1); ans = max(ans, cnt1 + cnt2 + ta + tb); } long long cnt = i; while (cnt <= n + 1 && a[cnt].x == a[i].x) { if (a[cnt].y) cnt2++; else cnt1++; cnt++; } i = cnt - 1; } cout << ans << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4b (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D_N ;
// Local signals
wire DN not0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_PP_V |
module Queue_2048
(
input clock,
input reset,
input [2047:0] io_enq_bits,
input io_enq_valid,
output io_enq_ready,
output [2047:0] io_deq_bits,
output io_deq_valid,
input io_deq_ready
);
wire q1_rdy;
wire q2_rdy;
wire q1_vld;
wire q2_vld;
wire [1023:0] bitsIn_0_1023;
wire [1023:0] bitsIn_1024_2047;
wire [1023:0] bitsOut_0_1023;
wire [1023:0] bitsOut_1024_2047;
assign bitsIn_0_1023 = io_enq_bits[1023:0];
assign bitsIn_1024_2047 = io_enq_bits[2047:1024];
assign io_deq_valid = q1_vld & q2_vld;
assign io_enq_ready = q1_rdy & q2_rdy;
assign io_deq_bits = { bitsOut_1024_2047, bitsOut_0_1023 };
Queue_1024 queue1
(
.clock( clock ),
.reset( reset ),
.io_enq_bits( bitsIn_0_1023 ),
.io_enq_valid( io_enq_valid ),
.io_enq_ready( q1_rdy ),
.io_deq_bits( bitsOut_0_1023 ),
.io_deq_valid( q1_vld ),
.io_deq_ready( io_deq_ready )
);
Queue_1024 queue2
(
.clock( clock ),
.reset( reset ),
.io_enq_bits( bitsIn_1024_2047 ),
.io_enq_valid( io_enq_valid ),
.io_enq_ready( q2_rdy ),
.io_deq_bits( bitsOut_1024_2047 ),
.io_deq_valid( q2_vld ),
.io_deq_ready( io_deq_ready )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; int arr[n], brr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n, greater<int>()); for (int j = 0; j < n; j++) { cin >> brr[j]; } sort(brr, brr + n, greater<int>()); int ans = 0; int i = 0, j = 0; int cnt = n; while (cnt--) { if (arr[i] >= brr[j]) ans += arr[i], i += 1; else if (k > 0) ans += brr[j], j += 1, k -= 1; else ans += arr[i], i += 1; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; vector<pair<int, int>> v; for (int i = 0; i < n; i++) { long long a, b; cin >> a >> b; v.push_back(make_pair(a, b)); } int c = 0; for (int i = 0; i < n; i++) { int up = 0, lo = 0, r = 0, l = 0; for (int j = 0; j < n; j++) { if (v[i].first > v[j].first && v[i].second == v[j].second) up = 1; if (v[i].first < v[j].first && v[i].second == v[j].second) lo = 1; if (v[i].first == v[j].first && v[i].second < v[j].second) l = 1; if (v[i].first == v[j].first && v[i].second > v[j].second) r = 1; } if (up + lo + l + r == 4) c++; } cout << c; } |
#include <bits/stdc++.h> using namespace std; long long int n, t; int main() { cin >> n >> t; long long int a = (n - t) / 2; for (int i = 1; i <= n; i++) { cout << !((i) % (a + 1)); } } |
#include <bits/stdc++.h> using namespace std; string ANSWER[2] = { NO n , YES n }; int v[2009], s1[2009], s2[2009]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &v[i]); s1[i] = s1[i - 1] + (v[i] == 1); s2[i] = s2[i - 1] + (v[i] == 2); } int ans = 0; for (int i = 1; i <= n; i++) { int a = 0, b = 0; for (int j = i; j <= n; j++) { if (v[j] == 1) b++; if (v[j] == 2) a++; if (a > b) b = a; ans = max(ans, s1[i - 1] + b + s2[n] - s2[j]); } } printf( %d n , ans); return 0; } |
`include "SVGA_DEFINES.v"
module COLOR_BARS
(
pixel_clock,
reset,
pixel_count0,
line_count0,
vga_red_data,
vga_green_data,
vga_blue_data
);
input pixel_clock;
input reset;
input [10:0] pixel_count0;
input [9:0] line_count0;
output vga_red_data;
output vga_green_data;
output vga_blue_data;
reg [10:0] pixel_count;
reg [9:0] line_count;
reg red_data;
reg green_data;
reg blue_data;
wire [2:0] write_data = {red_data, green_data, blue_data};
wire [2:0] read_data;
assign {vga_red_data, vga_green_data, vga_blue_data} = read_data;
// Create the color bars in memory, alternating memory locations every other
// line to allow for computation time.
// Only the least significant 10 bits are required out of the total 11 bits
// of pixel count, because active screen area has a maximum width of 1024.
// The remaining bits of pixel count are used to keep track of the front porch,
// synch, and back porch, which make up the blank period. It is OK that this
// module will output color data during the blank period, because the VIDEO_OUT
// module overrides the output of this module with zeros when the blank signal
// is high.
wire [10:0] write_addr = {!line_count0[0], pixel_count0[9:0]};
wire [10:0] read_addr = {line_count0[0], pixel_count0[9:0]};
wire write_enable = 1'b1; // write every clock posedge
reg [7:0] red_rainbow;
reg [7:0] green_rainbow;
reg [7:0] blue_rainbow;
// directions: 2'b00 == hold, 2'b01 == increase, 2'b10 == decrease
reg [1:0] red_direction;
reg [1:0] green_direction;
reg [1:0] blue_direction;
// compensate for the delay caused by displaying the previous line while
// calculating the current line by using a line counter that is one line
// ahead of the original line counter
always @ (posedge pixel_clock) begin
if ((line_count0 == (`V_TOTAL - 2)) & (pixel_count0 == (`H_TOTAL - 3)))
// last pixel in last line of frame, so reset line counter
line_count <= 10'h000;
else if (pixel_count0 == (`H_TOTAL - 3))
// last pixel but not last line, so increment line counter
line_count <= line_count + 1;
end
// compensate for putting the pixel_count generation and the code that
// checks it on the same clock edge
always @ (posedge pixel_clock) begin
if ((pixel_count0 == (`H_TOTAL - 3)))
// last pixel in last line of frame, so reset line counter
pixel_count <= 10'h000;
else
// last pixel but not last line, so increment line counter
pixel_count <= pixel_count + 1;
end
// cycle through all of the possible hues in a rainbow pattern
always @ (posedge pixel_clock) begin
// start last color bar at pure red
if (reset) begin
red_rainbow <= 8'hFF;
green_rainbow <= 8'h00;
blue_rainbow <= 8'h00;
red_direction <= 2'b00;
green_direction <= 2'b01;
blue_direction <= 2'b00;
end
else begin
// on the first line that is past the active region displayed,
// calculate the color for the last color bar
if ((pixel_count == 0) & (line_count == 480)) begin
if (red_direction[0]) begin
if (red_rainbow == 8'hFF) begin
red_direction <= 2'b00;
blue_direction <= 2'b10;
end
else
red_rainbow <= red_rainbow + 8'h01;
end
if (red_direction[1]) begin
if (red_rainbow == 8'h00) begin
red_direction <= 2'b00;
blue_direction <= 2'b01;
end
else
red_rainbow <= red_rainbow - 8'h01;
end
if (green_direction[0]) begin
if (green_rainbow == 8'hFF) begin
green_direction <= 2'b00;
red_direction <= 2'b10;
end
else
green_rainbow <= green_rainbow + 8'h01;
end
if (green_direction[1]) begin
if (green_rainbow == 8'h00) begin
green_direction <= 2'b00;
red_direction <= 2'b01;
end
else
green_rainbow <= green_rainbow - 8'h01;
end
if (blue_direction[0]) begin
if (blue_rainbow == 8'hFF) begin
blue_direction <= 2'b00;
green_direction <= 2'b10;
end
else
blue_rainbow <= blue_rainbow + 8'h01;
end
if (blue_direction[1]) begin
if (blue_rainbow == 8'h00) begin
blue_direction <= 2'b00;
green_direction <= 2'b01;
end
else
blue_rainbow <= blue_rainbow - 8'h01;
end
end
end
end
// select the color based on the horizontal position
always @ (posedge pixel_clock) begin
if (pixel_count < 79) begin //red
red_data <= 1'b1;
green_data <= 1'b0;
blue_data <= 1'b0;
end
else if ((pixel_count > 80) & (pixel_count < 159)) begin //yellow
red_data <= 1'b1;
green_data <= 1'b1;
blue_data <= 1'b0;
end
else if ((pixel_count > 160) & (pixel_count < 239)) begin //green
red_data <= 1'b0;
green_data <= 1'b1;
blue_data <= 1'b0;
end
else if ((pixel_count > 240) & (pixel_count < 319)) begin //cyan
red_data <= 1'b0;
green_data <= 1'b1;
blue_data <= 1'b1;
end
else if ((pixel_count > 320) & (pixel_count < 399)) begin //blue
red_data <= 1'b0;
green_data <= 1'b0;
blue_data <= 1'b1;
end
else if ((pixel_count > 400) & (pixel_count < 479)) begin //magenta
red_data <= 1'b1;
green_data <= 1'b0;
blue_data <= 1'b1;
end
else if ((pixel_count > 480) & (pixel_count < 559)) begin //white
red_data <= 1'b1;
green_data <= 1'b1;
blue_data <= 1'b1;
end
else if (pixel_count > 560) begin //rainbow pattern
red_data <= red_rainbow[7];
green_data <= green_rainbow[7];
blue_data <= blue_rainbow[7];
end
else begin //black
red_data <= 1'b0;
green_data <= 1'b0;
blue_data <= 1'b0;
end
end
// Instantiate the video RAM
VIDEO_RAM VIDEO_RAM
(
pixel_clock, // write clock
write_enable, // write eanble
write_addr, // write address
write_data, // write data
pixel_clock, // read clock
read_addr, // read address
read_data // read data
);
endmodule //COLOR_BARS |
#include<bits/stdc++.h> using namespace std; #define ll int long long #define mp make_pair //#define for(i,n) for(int i=0;i<n;i++) #define F first #define S second #define fast ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); #define N 1000000007 #define pq priority queue #define pb push_back #define pf push_front #define mt make_tuple #define prec(a) fixed<<setprecision(9)<<a #define endl n #define fast_set s.max_load_factor(0.25);s.reserve(500); #define cy cout<< YES <<endl; #define cn cout<< NO <<endl; #define all(v) v.begin(),v.end() #define allr(v) v.rbegin(),v.rend() const long double PI = (long double)(3.1415926535897932384626433832795); bool check(int a,int b,int hh,int mm) { int savea=a,saveb=b; int arr[10]; memset(arr,-1,sizeof(arr)); arr[0]=0; arr[1]=1; arr[2]=5; arr[5]=2; arr[8]=8; int h=0,m=0; h=arr[(b%10)]*10+arr[(b/10)]; m=arr[(a%10)]*10+arr[(a/10)]; if(arr[a%10] == -1 || arr[a/10] == -1 || arr[b%10] == -1 || arr[b/10] == -1){ return 0; } return (h<hh&&m<mm); } int main() { fast; int test,n,i,j,k; cin>>test; while(test--) { string str; cin>>n>>k>>str; if(n%k!=0) { cout<< -1 <<endl; } else { int hash1[26]={0}; n=str.length(); for(i=0;i<n;i++) { hash1[str[i]- a ]++; } for(i=0;i<26;i++) { if(hash1[i]%k!=0) { break; } } if(i==26) { cout<<str<<endl; } else { for(i=n-1;i>=0;i--) { hash1[str[i]- a ]--; for(j=str[i]- a +1;j<26;j++) { bool flag=1; hash1[j]++; int it=0,cnt=0; for(it=0;it<26;it++) { cnt+=((k-(hash1[it]%k))%k); } int avail = n-i-1; if(cnt>avail||(avail-cnt)%k!=0) { flag=0; } hash1[j]--; if(flag) { break; } } if(j<26) { break; } } if(i<0) { cout<<i<<endl; } else { //cout<<i<< <<j<<endl; str[i]= a +j; hash1[j]++; int it=0,mini=0; vector<int>s; int sum=0; for(it=0;it<26;it++) { if(hash1[it]>0) mini=min(mini,it); int a=((k-(hash1[it]%k))%k); sum+=a; while(a--) { mini=min(mini,it); s.pb(it); } } //cout<<sum<<endl; int a=n-i-1-sum; while(a--) { s.pb(mini); } int c=0; //cout<<s.size()<<endl; sort(all(s)); for(j=i+1;j<n;j++) { str[j]= a +s[c]; c++; } cout<<str<<endl; } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int convexP = 0; const int SQ = 1075; const long long mini = -8e18; bool isErased[300001]; long long type[300001], a[300001], b[300001]; long long out[300001]; long long la[300001], lb[300001]; int convexSz, p; double cross(int x, int y) { return (double)(lb[y] - lb[x]) / (la[x] - la[y]); } void insert(long long m, long long b) { if (convexSz > 0) { if (la[convexSz - 1] == m) { lb[convexSz - 1] = min(lb[convexSz - 1], b); } else { la[convexSz] = m; lb[convexSz++] = b; } } else { la[convexSz] = m; lb[convexSz++] = b; } while (convexSz >= 3 && cross(convexSz - 3, convexSz - 2) > cross(convexSz - 2, convexSz - 1)) { swap(la[convexSz - 2], la[convexSz - 1]); swap(lb[convexSz - 2], lb[convexSz - 1]); --convexSz; } } long long query(long long x) { if (convexSz == 0) { return mini; } while (p + 1 < convexSz && cross(p, p + 1) <= x) p++; return -(lb[p] + la[p] * x); } pair<pair<long long, long long>, int> ret[300001]; pair<pair<long long, long long>, int> v[300001]; pair<pair<long long, long long>, int> u[300001]; pair<pair<long long, long long>, int> g[300001]; void merge(int &arSize, int st, int ed) { int usz = 0; for (int i = st; i <= ed; ++i) { if (!isErased[i] && type[i] == 1) { u[usz++] = {{-a[i], -b[i]}, i}; } } sort(u, u + usz, greater<pair<pair<int, int>, int> >()); int sz0 = 0, sz1 = 0, rpos = 0; while (sz0 < arSize && sz1 < usz) { if (v[sz0].first.first > u[sz1].first.first) { ret[rpos++] = (v[sz0++]); } else { ret[rpos++] = (u[sz1++]); } } while (sz0 < arSize) { ret[rpos++] = (v[sz0++]); } while (sz1 < usz) { ret[rpos++] = (u[sz1++]); } arSize = rpos; for (int i = 0; i < arSize; ++i) { v[i] = ret[i]; } } pair<long long, long long> q[300001]; int ttt[300001]; void solve() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %lld %lld , &type[i], &a[i]); if (type[i] == 1) { scanf( %lld , &b[i]); } out[i] = mini; } int pos = 0; int vsz = 0; for (int i = 1; i <= n; i += SQ) { int ed = min(n, i + SQ - 1); int sz = 0; int gsz = 0; for (int j = i; j <= ed; ++j) { if (type[j] == 2 && a[j] < i) { isErased[a[j]] = true; int id = a[j]; g[gsz++] = {{a[id], b[id]}, j}; } } int tsz = 0; for (int j = 0; j < vsz; ++j) { if (!isErased[v[j].second]) { v[sz++] = v[j]; } } vsz = sz; convexSz = 0; p = 0; for (int j = 0; j < vsz; ++j) { insert(v[j].first.first, v[j].first.second); } int qsz = 0; for (int j = i; j <= ed; ++j) { q[qsz++] = {a[j], j}; } sort(q, q + qsz); if (convexSz > 0) for (int j = 0; j < qsz; ++j) { out[q[j].second] = query(q[j].first); } int tttsz = 0; for (int j = i; j <= ed; ++j) { if (type[j] == 3) { for (int k = 0; k < tttsz; ++k) { int tid = ttt[k]; if (!isErased[tid]) out[j] = max(out[j], a[tid] * a[j] + b[tid]); } for (int k = gsz - 1; k >= 0; --k) { if (g[k].second < j) { break; } out[j] = max(out[j], g[k].first.first * a[j] + g[k].first.second); } } else if (type[j] == 2) { isErased[a[j]] = true; } else { ttt[tttsz++] = j; } } merge(vsz, i, ed); } for (int i = 1; i <= n; ++i) { if (type[i] == 3) { if (out[i] != mini) printf( %lld n , out[i]); else printf( EMPTY SET n ); } } } int main() { solve(); return 0; } |
#include <bits/stdc++.h> template <typename T> void read(T& x) { x = 0; int flag = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) flag = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= flag; } using namespace std; const int maxn = 200010; int n, q, f[maxn], sz[maxn], tp; pair<int, int> sta[maxn], a[maxn]; bool ok[maxn]; struct info { int l, r, u, v; info() {} info(int a, int b, int c, int d) { l = a, r = b, u = c, v = d; } }; vector<info> seg; int find(int x) { return f[x] == x ? f[x] : find(f[x]); } bool check(int x) { return find(x) == find(x + n); } void link(int u, int v) { int r1 = find(u), r2 = find(v); if (r1 == r2) return; if (sz[r1] > sz[r2]) swap(r1, r2); f[r1] = r2, sz[r2] += sz[r1], sta[++tp] = make_pair(r1, r2); } void cut(pair<int, int> t) { int u = t.first, v = t.second; if (f[v] == u) swap(u, v); f[u] = u; while (f[v] != v) sz[v] -= sz[u], v = f[v]; sz[v] -= sz[u]; } map<pair<int, int>, int> mp; vector<pair<int, int> > edge[maxn << 2]; void modify(int p, int l, int r, int ql, int qr, int u, int v) { if (ql <= l && r <= qr) { edge[p].push_back(make_pair(u, v)); return; } int mid = (l + r) >> 1; if (ql <= mid) modify(p << 1, l, mid, ql, qr, u, v); if (qr > mid) modify(p << 1 | 1, mid + 1, r, ql, qr, u, v); } void dfs(int p, int l, int r, bool flag) { int mid = (l + r) >> 1, cur = tp; for (int i = 0; i <= (int)edge[p].size() - 1; i++) { if (!flag) continue; int u = edge[p][i].first, v = edge[p][i].second; link(u, v + n), link(v, u + n); if (check(u) || check(v)) flag = 0; } if (l == r) { puts(flag ? YES : NO ); while (tp > cur) cut(sta[tp--]); return; } dfs(p << 1, l, mid, flag), dfs(p << 1 | 1, mid + 1, r, flag); while (tp > cur) cut(sta[tp--]); } int main() { scanf( %d %d , &n, &q); for (int i = 1; i <= (int)2 * n; i++) f[i] = i, sz[i] = 1; for (int i = 1; i <= (int)q; i++) { scanf( %d %d , &a[i].first, &a[i].second); int tmp = mp[a[i]]; if (!tmp) mp[a[i]] = i; else { ok[tmp] = ok[i] = 1, mp[a[i]] = 0; seg.push_back(info(tmp, i - 1, a[i].first, a[i].second)); } } for (int i = 1; i <= (int)q; i++) if (!ok[i]) seg.push_back(info(mp[a[i]], q, a[i].first, a[i].second)); for (int i = 0; i <= (int)seg.size() - 1; i++) modify(1, 1, q, seg[i].l, seg[i].r, seg[i].u, seg[i].v); dfs(1, 1, q, 1); return 0; } |
`include "defines.v"
`timescale 1ns/1ps
module tb(
input `control_w port0_ci,
input `data_w port0_di,
output `control_w port0_co,
output `data_w port0_do,
input `control_w port1_ci,
input `data_w port1_di,
output `control_w port1_co,
output `data_w port1_do,
input `control_w port2_ci,
input `data_w port2_di,
output `control_w port2_co,
output `data_w port2_do,
input `control_w port3_ci,
input `data_w port3_di,
output `control_w port3_co,
output `data_w port3_do,
input `control_w port4_ci,
input `data_w port4_di,
output `control_w port4_co,
output `data_w port4_do
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `data_w flit0d;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(port1_ci), .port1_co(port1_co),
.port2_ci(port2_ci), .port2_co(port2_co),
.port3_ci(port3_ci), .port3_co(port3_co),
.port4_ci(port4_ci), .port4_co(port4_co),
.port0_di(flit0d), .port0_do(port0_do),
.port1_di(port1_di), .port1_do(port1_do),
.port2_di(port2_di), .port2_do(port2_do),
.port3_di(port3_di), .port3_do(port3_do),
.port4_di(port4_di), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
clk = 0;
rst = 0;
flit0c = 22'h200001;
flit0d = 128'h0123456789abcdef0123456789abcdef;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 22'h0;
flit0d = 128'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
end
endmodule
|
#include <bits/stdc++.h> inline int getint() { register char ch; register bool neg = false; while (!isdigit(ch = getchar())) if (ch == - ) neg = true; register int x = ch ^ 0 ; while (isdigit(ch = getchar())) x = (((x << 2) + x) << 1) + (ch ^ 0 ); return neg ? -x : x; } const int _inf = -0x40000000; const int N = 30001, K = 201; int a[N]; int f[N][K][4]; int main() { int n = getint(), k = getint(); for (register int i = 1; i <= n; i++) { a[i] = getint(); } for (register int j = 1; j <= k; j++) { for (register int k = 0; k <= 3; k++) { f[0][j][k] = _inf; } } for (register int i = 1; i <= n; i++) { for (register int j = 1; j <= k; j++) { const int s = a[i] * ((j != 1 && j != k) ? 2 : 1); f[i][j][0] = std::max(f[i - 1][j][0], f[i - 1][j - 1][3]) - s; f[i][j][1] = std::max(f[i - 1][j][1], f[i][j][0]); f[i][j][2] = std::max(f[i - 1][j][2], f[i - 1][j - 1][1]) + s; f[i][j][3] = std::max(f[i - 1][j][3], f[i][j][2]); if (j != 1 && j != k) { f[i][j][1] = std::max(f[i][j][1], f[i - 1][j - 1][1]); f[i][j][3] = std::max(f[i][j][3], f[i - 1][j - 1][3]); } } } printf( %d n , std::max(f[n][k][1], f[n][k][3])); return 0; } |
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: counter48
*
*/
`default_nettype none
module counter48 #(
parameter DATASIZE = 16 // width of the counter, must be <=48 bits!
) (
input wire clk,
input wire res_n,
input wire increment,
input wire [DATASIZE-1:0] load,
input wire load_enable,
output wire [DATASIZE-1:0] value
);
reg [DATASIZE-1:0] value_reg;
reg load_enable_reg;
assign value = value_reg;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if (!res_n)
begin
value_reg <= {DATASIZE{1'b0}};
load_enable_reg <= 1'b0;
end
else
begin
load_enable_reg <= load_enable;
case ({load_enable_reg,increment})
2'b00:
value_reg <= value_reg;
2'b01:
value_reg <= (value_reg + 1'b1);
2'b10:
value_reg <= {DATASIZE{1'b0}};
2'b11:
value_reg <= {DATASIZE{1'b0}} + 1'b1;
endcase
end
end
endmodule
`default_nettype wire |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; if (n == k) cout << 0 << endl; else if (k > n) cout << k - n << endl; else { if ((n - k) % 2 == 0) cout << 0 << endl; else cout << 1 << endl; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_BLACKBOX_V
`define SKY130_FD_SC_HS__O21BA_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int k, l; cin >> k; vector<int> a[k]; for (int i = 0; i < k; i++) for (int j = 0; j < k; j++) cin >> l, a[i].push_back(l); l = 0; for (int i = 0; i < k; i++) l += a[k / 2][i]; for (int i = 0; i < k; i++) l += a[i][k / 2]; for (int i = 0; i < k; i++) l += a[i][i]; for (int i = 0; i < k; i++) l += a[i][k - i - 1]; cout << l - (3 * (a[k / 2][k / 2])); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A221OI_PP_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a221oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int r = 0; int rr = 0; int prev = 10000; while (n--) { int a, b; cin >> a >> b; if (a != b) r = 1; else { if (a > prev) rr = 1; } prev = a; } if (r == 1) cout << rated << endl; else { if (rr == 0) cout << maybe << endl; else cout << unrated << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_LP_V
`define SKY130_FD_SC_LP__A2BB2OI_LP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_lp (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_lp (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_LP_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_2pi.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Wrap_2pi
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Encoder_To_Rotor_Position/Wrap_2pi
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Wrap_2pi
(
x,
wrap
);
input signed [18:0] x; // sfix19_En14
output signed [17:0] wrap; // sfix18_En14
wire signed [18:0] Two_Pi1_out1; // sfix19_En14
wire signed [18:0] Two_Pi3_out1; // sfix19_En14
wire Relational_Operator1_relop1;
wire signed [19:0] x_dtc; // sfix20_En14
wire signed [18:0] Two_Pi2_out1; // sfix19_En14
wire signed [18:0] Two_Pi_out1; // sfix19_En14
wire Relational_Operator_relop1;
wire signed [19:0] Add2_add_cast; // sfix20_En14
wire signed [19:0] Add2_add_cast_1; // sfix20_En14
wire signed [19:0] Add2_out1; // sfix20_En14
wire signed [19:0] Switch1_out1; // sfix20_En14
wire signed [17:0] Switch1_out1_dtc; // sfix18_En14
wire signed [19:0] Add1_sub_cast; // sfix20_En14
wire signed [19:0] Add1_sub_cast_1; // sfix20_En14
wire signed [19:0] Add1_out1; // sfix20_En14
wire signed [17:0] Add1_out1_dtc; // sfix18_En14
wire signed [17:0] Switch_out1; // sfix18_En14
// <S10>/Two Pi1
assign Two_Pi1_out1 = 19'sb0011001001000100000;
// <S10>/Two Pi3
assign Two_Pi3_out1 = 19'sb0000000000000000000;
// <S10>/Relational Operator1
assign Relational_Operator1_relop1 = (x < Two_Pi3_out1 ? 1'b1 :
1'b0);
assign x_dtc = x;
// <S10>/Two Pi2
assign Two_Pi2_out1 = 19'sb0011001001000100000;
// <S10>/Two Pi
assign Two_Pi_out1 = 19'sb0011001001000100000;
// <S10>/Relational Operator
assign Relational_Operator_relop1 = (x >= Two_Pi1_out1 ? 1'b1 :
1'b0);
// <S10>/Add2
assign Add2_add_cast = x;
assign Add2_add_cast_1 = Two_Pi2_out1;
assign Add2_out1 = Add2_add_cast + Add2_add_cast_1;
// <S10>/Switch1
assign Switch1_out1 = (Relational_Operator1_relop1 == 1'b0 ? x_dtc :
Add2_out1);
assign Switch1_out1_dtc = Switch1_out1[17:0];
// <S10>/Add1
assign Add1_sub_cast = x;
assign Add1_sub_cast_1 = Two_Pi_out1;
assign Add1_out1 = Add1_sub_cast - Add1_sub_cast_1;
assign Add1_out1_dtc = Add1_out1[17:0];
// <S10>/Switch
assign Switch_out1 = (Relational_Operator_relop1 == 1'b0 ? Switch1_out1_dtc :
Add1_out1_dtc);
assign wrap = Switch_out1;
endmodule // controllerHdl_Wrap_2pi
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_1_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_1_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_1_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_1_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_LP_V
`define SKY130_FD_SC_LP__NAND2B_LP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_lp (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_lp (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_LP_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n, o; string st; long long a[maxn], all; int cc[100], where[100], zhu[100], g[maxn], wc[maxn]; int f[66][maxn]; int main() { cin >> n; all = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; all ^= a[i]; } st = ; for (int i = 1; i <= 63; i++) { st = char(all % 2 + 48) + st; all /= 2; } o = 0; for (int i = 1; i <= 63; i++) if (st[i - 1] == 0 ) ++o, where[o] = i; for (int i = 1; i <= 63; i++) if (st[i - 1] == 1 ) ++o, where[o] = i; for (int i = 1; i <= n; i++) { for (int j = 1; j <= 63; j++) { cc[64 - j] = a[i] % 2; a[i] /= 2; } a[i] = 0; for (int j = 1; j <= 63; j++) a[i] = (long long)a[i] * 2 + cc[where[j]]; } memset(f, 0, sizeof(f)); memset(g, 0, sizeof(g)); memset(zhu, 0, sizeof(zhu)); for (int i = 1; i <= 63; i++) { for (int j = 1; j <= n; j++) f[i][j] = ((long long)a[j] >> (63 - i)) % 2; g[i] = 1; for (int j = 1; j < i; j++) if ((zhu[j] != -1) && (f[i][zhu[j]] == 1)) { for (int k = 1; k <= n; k++) f[i][k] ^= f[j][k]; g[i] ^= g[j]; } zhu[i] = -1; for (int j = 1; j <= n; j++) if (f[i][j] == 1) { zhu[i] = j; break; } if (zhu[i] == -1) g[i] = 0; } memset(wc, 0, sizeof(wc)); for (int i = 63; i >= 1; i--) { for (int j = 1; j <= n; j++) if (f[i][j] == 1) g[i] ^= wc[j]; wc[zhu[i]] = g[i]; } for (int i = 1; i <= n; i++) cout << wc[i] + 1 << ; cout << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFBBP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_SYMBOL_V
|
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