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#include <bits/stdc++.h> using namespace std; template <typename TYPE> void readint(TYPE &x) { x = 0; int f = 1; char c; for (c = getchar(); !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= f; } void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } const long long MOD = 998244353LL, MAX = 3e5 + 5; const int INF = 2e9; int n; long long ans; long long a[MAX]; long long fc[MAX]; long long pot(long long x, long long y) { if (!y) return 1LL; if (y & 1) return (x * pot(x, y - 1)) % MOD; else { long long k = pot(x, y / 2); return (k * k) % MOD; } } long long inv(long long t) { return pot(t, MOD - 2); } void read(int w[], int n) { for (long long i = 0; i < n; i++) { cin >> w[i]; } } void solve() { cin >> n; fc[0] = 1LL; for (long long i = 0; i < 2 * n; i++) cin >> a[i]; if (n == 1) { cout << (a[1] - a[0]) * 2; return; } sort(a, a + 2 * n); for (long long i = 1; i < n * 2 + 1; i++) fc[i] = (fc[i - 1] * i) % MOD; for (long long i = 0; i < n; i++) ans += (a[2 * n - 1 - i] - a[i]); ans %= MOD; { string _s = ans ; replace(_s.begin(), _s.end(), , , ); stringstream _ss(_s); istream_iterator<string> _it(_ss); err(_it, ans); }; ans = (ans * (fc[n * 2])) % MOD; ans *= inv((fc[n] * fc[n]) % MOD); ans %= MOD; ans %= MOD; cout << ans; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 50000 + 10; struct query { int type, x, y; } qu[maxn]; int n, fa[maxn]; long long val[maxn], sz[maxn]; vector<int> v[maxn]; bool mark[maxn], have[maxn]; long long d[maxn]; int dfs(int x) { sz[x] = 1; int ret = 0; for (auto i : v[x]) ret += dfs(i), sz[x] += sz[i]; for (auto i : v[x]) d[i] = (sz[x] - sz[i]) * val[x]; have[x] = ((ret || mark[x]) ? 1 : 0); if (ret >= 2 || mark[x]) { mark[x] = 1; return 1; } else return ret; } struct P { int to, ssum; long long dsum; }; vector<P> v2[maxn]; int fa2[maxn]; long long sz2[maxn], sz2sum[maxn]; long long pnum[maxn]; bool leaf[maxn]; void dfs2(int x, bool isfir = 0) { if (v2[x].empty()) { if (!isfir) return; pnum[x] = sz[x] * sz[x]; for (auto i : v[x]) pnum[x] -= sz[i] * sz[i]; return; } sz[x] = 1 + sz2[x]; pnum[x] = 0; for (auto i : v2[x]) dfs2(i.to, isfir), sz[x] += sz[i.to] + i.ssum, pnum[x] -= (sz[i.to] + i.ssum) * (sz[i.to] + i.ssum); pnum[x] += sz[x] * sz[x] - sz2sum[x]; } int getid(int x, int y) { for (int i = 0;; i++) if (v2[x][i].to == y) return i; } void build_graph(int num) { fill(mark, mark + n + 1, 0); fill(have, have + n + 1, 0); fill(leaf, leaf + n + 1, 1); for (int i = 1; i <= n; i++) v[i].clear(), v2[i].clear(); for (int i = 2; i <= n; i++) v[fa[i]].push_back(i); for (int i = 0; i < num; i++) { mark[qu[i].x] = 1; if (qu[i].type == 1) mark[qu[i].y] = 1; } mark[1] = 1; dfs(1); for (int i = 1; i <= n; i++) if (mark[i]) { sz2[i] = sz2sum[i] = 0; for (auto j : v[i]) if (!have[j]) sz2[i] += sz[j], sz2sum[i] += sz[j] * sz[j]; if (i == 1) continue; int j, ssum = 0; long long dsum = 0LL; for (j = i;; j = fa[j]) { dsum += d[j]; if (mark[fa[j]]) break; } ssum = sz[j] - sz[i]; j = fa[j]; v2[j].push_back((P){i, ssum, dsum}); fa2[i] = j; leaf[j] = 0; } } bool first = 1; void process(int num) { build_graph(num); long long nowans = 0LL, tot = (long long)n * n; for (int i = 1; i <= n; i++) { long long add = sz[i] * sz[i]; for (auto j : v[i]) add -= sz[j] * sz[j]; nowans += add * val[i]; } if (first) printf( %.15f n , ((double)nowans) / tot), first = 0; dfs2(1, 1); for (int i = 0; i < num; i++) { if (qu[i].type == 2) { int x = qu[i].x, nval = qu[i].y; nowans += pnum[x] * (nval - val[x]); for (auto &j : v2[x]) j.dsum += (sz[x] - j.ssum - sz[j.to]) * (nval - val[x]); val[x] = nval; printf( %.15f n , ((double)nowans) / tot); continue; } int x = qu[i].y, y = qu[i].x, id; for (int j = x; j != 1; j = fa2[j]) if (j == y || y == 1) { swap(x, y); break; } fa[y] = x; long long dif = 0LL; for (int j = y; j != 1; j = fa2[j]) { sz[fa2[j]] -= sz[y]; for (auto &k : v2[fa2[j]]) if (k.to != j) k.dsum -= val[fa2[j]] * sz[y]; else dif -= k.dsum; } int f = fa2[y]; id = getid(f, y); sz2[f] += v2[f][id].ssum; sz2sum[f] += (long long)v2[f][id].ssum * v2[f][id].ssum; swap(v2[f][id], v2[f][v2[f].size() - 1]); v2[f].pop_back(); v2[x].push_back((P){y, 0, val[x] * sz[x]}); fa2[y] = x; if (v2[f].empty()) pnum[f] = sz[f] * sz[f] - sz2sum[f]; for (int j = y; j != 1; j = fa2[j]) { sz[fa2[j]] += sz[y]; for (auto &k : v2[fa2[j]]) if (k.to != j) k.dsum += val[fa2[j]] * sz[y]; else dif += k.dsum; } nowans += 2 * dif * sz[y]; printf( %.15f n , ((double)nowans) / tot); dfs2(1); } } int main() { scanf( %d , &n); fa[1] = 1; for (int i = 2; i <= n; i++) scanf( %d , &fa[i]); for (int i = 1; i <= n; i++) scanf( %I64d , &val[i]); int Q; scanf( %d , &Q); int sq = (int)sqrt(Q + 0.5); for (int i = 0; i < Q; i++) { char c[5]; scanf( %s%d%d , c, &qu[i % sq].x, &qu[i % sq].y); qu[i % sq].type = (c[0] == P ? 1 : 2); if ((i % sq) == sq - 1 || i == Q - 1) process(i % sq + 1); } } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, ans; struct Node { int val, p, cnt; int pre, nxt; } a[N]; struct Comp { bool operator()(const pair<int, int> &x, const pair<int, int> &y) { return x.first == y.first ? x.second < y.second : x.first > y.first; } }; set<pair<int, int>, Comp> st; void solve() { scanf( %d , &n); int p = -1, k = 0; for (int i = 0; i < n; i++) { int tmp; scanf( %d , &tmp); if (tmp != k) { if (p != -1) a[p].nxt = i; a[i].pre = p; k = tmp; p = i; a[i].p = i; a[i].val = tmp; a[i].nxt = -1; a[i].cnt = 1; } else { a[p].cnt++; } } for (int i = 0; i < n; i++) if (a[i].cnt) st.insert(make_pair(a[i].cnt, i)); while (!st.empty()) { auto it = st.begin(); int pos = it->second; int pp = a[pos].pre, nn = a[pos].nxt; ans++; st.erase(it); if (pp != -1) a[pp].nxt = nn; if (nn != -1) a[nn].pre = pp; if (pp != -1 && nn != -1 && a[pp].val == a[nn].val) { int nnn = a[nn].nxt; a[nnn].pre = pp; a[pp].nxt = nnn; st.erase(st.find(make_pair(a[nn].cnt, nn))); st.erase(st.find(make_pair(a[pp].cnt, pp))); a[pp].cnt += a[nn].cnt; st.insert(make_pair(a[pp].cnt, pp)); } } printf( %d n , ans); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; long long c[1010][1010]; const int mod = 1e9 + 7; void pre() { for (int i = 0; i <= 1005; i++) { c[i][0] = c[i][i] = 1; } for (int i = 1; i <= 1005; i++) { for (int j = 0; j <= i; j++) { c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % mod; ; } } } int main(int argc, char const *argv[]) { scanf( %d%d%d , &n, &m, &k); pre(); if (2 * k > n - 1 || 2 * k > m - 1) { printf( 0 ); } else { printf( %lld n , c[n - 1][k * 2] * c[m - 1][k * 2] % mod); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; set<int> st; for (int i = 0; i < n; i++) { cin >> a[i]; st.insert(a[i]); } set<int>::iterator it = st.begin(); it++; if (it == st.end()) cout << NO ; else cout << (*it); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[100005], b[100005]; int l[100005], r[100005]; using pii = pair<int, int>; using ppi = pair<pii, int>; int tr[100005 * 2]; int get(int k) { int res = 0; for (; k; k -= k & -k) res += tr[k]; return res; } void update(int k) { for (; k <= m; k += k & -k) tr[k]++; } void calc(int *g, int *gg) { vector<ppi> V; for (int i = 1; i <= n; i++) V.push_back(ppi(pii(min(a[i], b[i]), max(a[i], b[i])), i)); sort(V.begin(), V.end(), [](const ppi &x, const ppi &y) { return x.first.second < y.first.second; }); int cnt = 0; memset(tr, 0, sizeof tr); for (auto x : V) { g[x.second] = cnt - get(x.first.first); update(x.first.first); cnt++; } reverse(V.begin(), V.end()); memset(tr, 0, sizeof tr); cnt = 0; for (auto x : V) { gg[x.second] = cnt - get(x.first.second) + get(x.first.first); update(x.first.first); cnt++; } memset(tr, 0, sizeof tr); for (auto x : V) update(x.first.second); for (auto x : V) gg[x.second] += get(x.first.first); return; } int main() { scanf( %d , &n); m = 2 * n; for (int i = 1; i <= n; i++) scanf( %d %d , &a[i], &b[i]); calc(l, r); long long ans = 0; for (int i = 1; i <= n; i++) { int t = n - 1 - l[i] - r[i]; ans += 1ll * t * (l[i] + r[i]); } ans >>= 1; for (int i = 1; i <= n; i++) ans += 1ll * l[i] * r[i]; ans = 1ll * n * (n - 1) * (n - 2) / 6 - ans; cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for lpflow_isobufsrc with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_2_V
`define SKY130_FD_SC_HDLL__A21BOI_2_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 200200; int head[MAX], nxt[MAX * 2], to[MAX * 2], dpthMx[MAX], dpthMn[MAX], Ecnt, n; int ch[MAX], sz; void dfs(int cur, int par) { for (int i = head[cur]; ~i; i = nxt[i]) if (to[i] != par) { dfs(to[i], cur); dpthMn[cur] = min(dpthMn[cur], dpthMn[to[i]] + 1); dpthMx[cur] = max(dpthMx[cur], dpthMx[to[i]] + 1); } if (dpthMn[cur] == MAX) dpthMn[cur] = 0; } int getNxt(int cur) { int mx3[3]{}, mn3[3]{}; for (int i = head[cur]; ~i; i = nxt[i]) { mn3[0] = mx3[0] = to[i]; sort(mn3, mn3 + 3, [](int a, int b) { return dpthMn[a] > dpthMn[b]; }); sort(mx3, mx3 + 3, [](int a, int b) { return dpthMx[a] < dpthMx[b]; }); } if (dpthMx[mx3[2]] - dpthMx[mx3[1]] < 2) return 0; dpthMx[cur] = dpthMx[mx3[1]] + 1; dpthMn[cur] = mn3[2] != mx3[2] ? (dpthMn[mn3[2]] + 1) : mn3[1] ? (dpthMn[mn3[1]] + 1) : 0; return mx3[2]; } void addEdge(int u, int v) { nxt[Ecnt] = head[u]; head[u] = Ecnt; to[Ecnt++] = v; } int main() { scanf( %d , &n); memset(head, -1, (n + 1) * sizeof head[0]); dpthMx[0] = -1; dpthMn[0] = MAX; fill(dpthMn, dpthMn + n + 1, MAX); for (int i = 1, u, v; i < n; ++i) { scanf( %d%d , &u, &v); addEdge(u, v); addEdge(v, u); } dfs(1, 0); int cen = 1, ncen; while (ncen = getNxt(cen)) cen = ncen; dpthMx[0] = 0; for (int i = head[cen]; ~i; i = nxt[i]) { if (dpthMx[to[i]] != dpthMn[to[i]]) return puts( -1 ), 0; ch[sz++] = dpthMx[to[i]] + 1; } sort(ch, ch + sz); sz = unique(ch, ch + sz) - ch; if (sz > 2) return puts( -1 ), 0; ch[sz] = 0; int ans = ch[0] + ch[1]; while (!(ans & 1)) ans >>= 1; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> int main() { long n(0); scanf( %ld , &n); std::map<long, long> solutions; bool possible(1); for (int k = 0; k < n; k++) { long number(0), participant(0); scanf( %ld %ld , &number, &participant); if (solutions.find(participant) != solutions.end()) { if (number > 1 + solutions[participant]) { possible = 0; break; } if (number > solutions[participant]) { solutions[participant] = number; } } else { if (number > 0) { possible = 0; break; } else { solutions.insert(std::pair<long, long>(participant, 0)); } } } puts(possible ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m; int s, p, i, j, k, z; string s1, s2; int const md = 1000000; stack<char> st; int a[5]; int main() { int k1 = 0, k2 = 0, k3 = 0; cin >> k1 >> k2; for (i = 1; i <= k1; i++) { cin >> k3; n = n * k2 + k3; } cin >> k1 >> k2; for (i = 1; i <= k1; i++) { cin >> k3; m = m * k2 + k3; } if (n > m) cout << > ; else if (n < m) cout << < ; else cout << = ; } |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:35 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_rst_ps7_0_100M_0/gcd_block_design_rst_ps7_0_100M_0_stub.v
// Design : gcd_block_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module gcd_block_design_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A21OI_BEHAVIORAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int Q, n, m, ans[600005], a[505][505]; char S[505]; struct O { int p, q, x, y, i; } o[600005], O[600005]; bitset<505> f[505][505], g[505][505]; void go(int l, int r, int p, int q) { if (p > q) return; int mi = l + r >> 1, L, R, t; for (int i = 1; i <= n; ++i) if (!a[i][mi]) g[i][mi].reset(); else g[i][mi] = g[i - 1][mi], g[i][mi].set(i); for (int j = mi + 1; j <= r; ++j) for (int i = 1; i <= n; ++i) { g[i][j].reset(); if (!a[i][j]) continue; if (a[i][j - 1]) g[i][j] |= g[i][j - 1]; if (a[i - 1][j]) g[i][j] |= g[i - 1][j]; } for (int i = n; i; --i) if (!a[i][mi]) f[i][mi].reset(); else f[i][mi] = f[i + 1][mi], f[i][mi].set(i); for (int j = mi - 1; j >= l; --j) for (int i = n; i; --i) { f[i][j].reset(); if (!a[i][j]) continue; if (a[i][j + 1]) f[i][j] |= f[i][j + 1]; if (a[i + 1][j]) f[i][j] |= f[i + 1][j]; } L = p; R = q; for (int i = p; i <= q; ++i) if (o[i].q < mi && o[i].y < mi) O[L++] = o[i]; else if (o[i].q > mi && o[i].y > mi) O[R--] = o[i]; t = L; for (int i = p; i <= q; ++i) if (o[i].q <= mi && o[i].y >= mi) O[t++] = o[i]; for (int i = p; i <= q; ++i) o[i] = O[i]; for (int i = L; i <= R; ++i) if (o[i].p <= o[i].x && o[i].q <= o[i].y) ans[o[i].i] = (f[o[i].p][o[i].q] & g[o[i].x][o[i].y]).any(); if (l == r) return; go(l, mi - 1, p, L - 1); go(mi + 1, r, R + 1, q); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { scanf( %s , S + 1); for (int j = 1; j <= m; ++j) a[i][j] = S[j] == . ; } scanf( %d , &Q); for (int i = 1; i <= Q; ++i) scanf( %d%d%d%d , &o[i].p, &o[i].q, &o[i].x, &o[i].y), o[i].i = i; go(1, m, 1, Q); for (int i = 1; i <= Q; ++i) puts(ans[i] ? Yes : No ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, k, l; int main() { cin >> n >> m >> k >> l; long long x = m * ((k + l) / m + ((k + l) % m == 0 ? 0 : 1)); if (x <= n) cout << x / m << endl; else cout << -1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_TB_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; long long mult(long long a, long long b, long long p = 1000000007) { long long ans = ((a % p) * (b % p)) % p; return (ans + p) % p; } long long add(long long a, long long b, long long p = 1000000007) { long long ans = (a % p + b % p) % p; return (ans + p) % p; } long long fpow(long long n, long long k, long long p = 1000000007) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } long long inv(long long a, long long p = 1000000007) { return fpow(a, p - 2, p); } long long n, m, k; int32_t main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> n >> m >> k; vector<pair<long long, long long> > arr(n); vector<long long> orig(n); for (long long i = 0; i < n; i++) { cin >> arr[i].first; arr[i].second = i; orig[i] = arr[i].first; } sort(arr.begin(), arr.end(), greater<pair<long long, long long> >()); vector<bool> has(n, 0); long long s = 0; for (long long i = 0; i < m * k; i++) { s += arr[i].first; has[arr[i].second] = 1; } cout << s << endl; vector<long long> ans; long long ov = 0; for (long long i = 0; i < n;) { long long cnt = 0, j = i; while (cnt < m) { if (has[j] == 1) { cnt++; } j++; } ov++; i = j; if (ov == k) break; cout << i << ; ans.push_back(i); } cout << endl; return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97_transceiver(
input sys_clk,
input sys_rst,
input ac97_clk,
input ac97_rst_n,
/* to codec */
input ac97_sin,
output reg ac97_sout,
output reg ac97_sync,
/* to system, upstream */
output up_stb,
input up_ack,
output up_sync,
output up_data,
/* to system, downstream */
output down_ready,
input down_stb,
input down_sync,
input down_data
);
/* Upstream */
reg ac97_sin_r;
always @(negedge ac97_clk) ac97_sin_r <= ac97_sin;
reg ac97_syncfb_r;
always @(negedge ac97_clk) ac97_syncfb_r <= ac97_sync;
wire up_empty;
asfifo #(
.data_width(2),
.address_width(6)
) up_fifo (
.data_out({up_sync, up_data}),
.empty(up_empty),
.read_en(up_ack),
.clk_read(sys_clk),
.data_in({ac97_syncfb_r, ac97_sin_r}),
.full(),
.write_en(1'b1),
.clk_write(~ac97_clk),
.rst(sys_rst)
);
assign up_stb = ~up_empty;
/* Downstream */
/* Set SOUT and SYNC to 0 during RESET to avoid ATE/Test Mode */
wire ac97_sync_r;
always @(negedge ac97_rst_n, posedge ac97_clk) begin
if(~ac97_rst_n)
ac97_sync <= 1'b0;
else
ac97_sync <= ac97_sync_r;
end
wire ac97_sout_r;
always @(negedge ac97_rst_n, posedge ac97_clk) begin
if(~ac97_rst_n)
ac97_sout <= 1'b0;
else
ac97_sout <= ac97_sout_r;
end
wire down_full;
asfifo #(
.data_width(2),
.address_width(6)
) down_fifo (
.data_out({ac97_sync_r, ac97_sout_r}),
.empty(),
.read_en(1'b1),
.clk_read(ac97_clk),
.data_in({down_sync, down_data}),
.full(down_full),
.write_en(down_stb),
.clk_write(sys_clk),
.rst(sys_rst)
);
assign down_ready = ~down_full;
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { ios::sync_with_stdio(0); solve(); return 0; } pair<pair<double, double>, pair<double, double> > rects[100]; void solve() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> rects[i].first.first >> rects[i].first.second >> rects[i].second.first >> rects[i].second.second; if (rects[i].first.first > rects[i].second.first) swap(rects[i].first.first, rects[i].second.first); if (rects[i].first.second > rects[i].second.second) swap(rects[i].first.second, rects[i].second.second); for (int j = 0; j < i; j++) { double cx = 0, cy = 0, m = 0; for (int k = j + 1; k <= i; k++) { double l = fabs(rects[k].first.first - rects[k].second.first); double lll = l * l * l; m += lll; double x = (rects[k].first.first + rects[k].second.first) / 2.0; double y = (rects[k].first.second + rects[k].second.second) / 2.0; cx += lll * x; cy += lll * y; } cx /= m; cy /= m; if (rects[j].first.first > cx || rects[j].first.second > cy || rects[j].second.first < cx || rects[j].second.second < cy) { cout << i; return; } } } cout << n; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 100 + 100; int a1, a2, b1, b2; int main() { cin >> a1 >> a2 >> b1 >> b2; if ((b2 >= a1 - 1 && b2 <= 2 * (a1 + 1)) || (b1 >= a2 - 1 && b1 <= 2 * (a2 + 1))) cout << YES << endl; else cout << NO << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_SYMBOL_V
`define SKY130_FD_SC_MS__O41A_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; pair<int, int> p[maxn]; int a[maxn]; int b[maxn]; int n, k, cnt; bool F(int a, int b) { return a > b; } void solve() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) scanf( %d , b + i); sort(a + 1, a + n + 1); sort(b + 1, b + n + 1, F); int i = 1, t = 1; while (true) { if (b[t] + a[i++] >= k) cnt++, t++; if (t > n || i > n) break; } printf( 1 %d , cnt); } int main() { solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFSBP_PP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; template <typename T, size_t N> int SIZE(const T (&t)[N]) { return N; } template <typename T> int SIZE(const T &t) { return t.size(); } string to_string(const string s, int x1 = 0, int x2 = 1e9) { return + ((x1 < s.size()) ? s.substr(x1, x2 - x1 + 1) : ) + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(const bool b) { return (b ? true : false ); } string to_string(const char c) { return string({c}); } template <size_t N> string to_string(const bitset<N> &b, int x1 = 0, int x2 = 1e9) { string t = ; for (int __iii__ = min(x1, SIZE(b)), __jjj__ = min(x2, SIZE(b) - 1); __iii__ <= __jjj__; ++__iii__) { t += b[__iii__] + 0 ; } return + t + ; } template <typename A, typename... C> string to_string(const A(&v), int x1 = 0, int x2 = 1e9, C... coords); int l_v_l_v_l = 0, t_a_b_s = 0; template <typename A, typename B> string to_string(const pair<A, B> &p) { l_v_l_v_l++; string res = ( + to_string(p.first) + , + to_string(p.second) + ) ; l_v_l_v_l--; return res; } template <typename A, typename... C> string to_string(const A(&v), int x1, int x2, C... coords) { int rnk = rank<A>::value; string tab(t_a_b_s, ); string res = ; bool first = true; if (l_v_l_v_l == 0) res += n ; res += tab + [ ; x1 = min(x1, SIZE(v)), x2 = min(x2, SIZE(v)); auto l = begin(v); advance(l, x1); auto r = l; advance(r, (x2 - x1) + (x2 < SIZE(v))); for (auto e = l; e != r; e = next(e)) { if (!first) { res += , ; } first = false; l_v_l_v_l++; if (e != l) { if (rnk > 1) { res += n ; t_a_b_s = l_v_l_v_l; }; } else { t_a_b_s = 0; } res += to_string(*e, coords...); l_v_l_v_l--; } res += ] ; if (l_v_l_v_l == 0) res += n ; return res; } void dbgm() { ; } template <typename Heads, typename... Tails> void dbgm(Heads H, Tails... T) { cout << to_string(H) << | ; dbgm(T...); } const long long MOD = (int)1e9 + 7; const long long INF = 2e18 + 5; struct hashLL { size_t operator()(long long x) const { x = (x ^ (x >> 30)) * UINT64_C(0xbf58476d1ce4e5b9); x = (x ^ (x >> 27)) * UINT64_C(0x94d049bb133111eb); x = x ^ (x >> 31); return x; } }; long long inv(long long a, long long b) { return 1 < a ? b - inv(b % a, a) * b / a : 1; } long long gcd(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } long long distsq(long long x1, long long y1, long long x2, long long y2) { return (x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1); } const int N = 100001; long long n, m, k, x, y, w; unordered_map<int, unordered_map<int, int>> g; string s; pair<long long, long long> solve(long long curr, long long par) { long long returnwt = 0; long long endwt = 0; vector<long long> v; for (auto p : g[curr]) { long long child = p.first; long long wt = p.second; if (child == par) continue; returnwt += wt; pair<long long, long long> x = solve(child, curr); returnwt += x.first; returnwt += wt; if (-wt - wt - x.first + x.second + wt < endwt) { endwt = -wt - wt - x.first + x.second + wt; } } return {returnwt, returnwt + endwt}; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 0; i < (n - 1); i++) { cin >> x >> y >> w; g[x][y] = w; g[y][x] = w; } long long res = solve(1, 0).second; cout << res << n ; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// $Id: unencoded_cam_lut_sm.v 5697 2009-06-17 22:32:11Z tyabe $
//
// Module: unencoded_cam_lut_sm.v
// Project: NF2.1
// Author: Jad Naous <>
// Description: controls an unencoded muli-match cam and provides a LUT.
// Matches data and provides reg access
//
// The sizes of the compare input and the data to store in the LUT can be
// specified either by number of words or by exact size. The benefit of the
// first is that you don't have to calculate the exact number of words used
// in the parent module, but then the granularity of your matches will be
// in increments of `CPCI_NF2_DATA_WIDTH bits, which might or might not matter
///////////////////////////////////////////////////////////////////////////////
module wildcard_lut_action
#(
parameter DATA_WIDTH = 32,
parameter CMP_WIDTH = 64,
parameter LUT_DEPTH = 16,
parameter LUT_DEPTH_BITS = 4,
parameter CURRENT_TABLE_ID=0
)
(// --- Interface for lookups
input lookup_req,
input [CMP_WIDTH-1:0] lookup_cmp_data,
output reg lookup_ack,
output reg lookup_hit,
output reg [DATA_WIDTH-1:0] lookup_data,
output reg [LUT_DEPTH_BITS-1:0] lookup_address,
// --- CAM interface
input cam_busy,
input cam_match,
input [LUT_DEPTH_BITS-1:0] cam_match_addr,
output [CMP_WIDTH-1:0] cam_cmp_din,
// --- Watchdog Timer Interface
input table_flush,
// --- Misc
input reset,
input clk,
input skip_lookup,
input bram_cs,
input bram_we,
input [`PRIO_WIDTH-1:0]bram_addr,
input [319:0]lut_actions_in,
output [319:0]lut_actions_out
);
assign cam_cmp_din = skip_lookup?0:lookup_cmp_data;
reg [LUT_DEPTH_BITS-1:0] prio;
//assign prio=reg_addr_prio[LUT_DEPTH_BITS-1:0];
reg [`OPENFLOW_ACTION_WIDTH-1:0] lut_actions[LUT_DEPTH-1:0];
reg [`OPENFLOW_ACTION_WIDTH-1:0] lut_actions_tmp;
reg wea;
reg ena;
reg [3:0]addra;
reg bram_cs_en;
reg bram_we_en;
reg [LUT_DEPTH_BITS-1:0]bram_addr_en;
/*BRam
#(
.width(`OPENFLOW_ACTION_WIDTH),
.depth(LUT_DEPTH_BITS)
)lut_action_bram
( .clk(clk),
.cs(bram_cs_en),
.we(bram_we_en),
.addr(bram_addr_en),
.din(lut_actions_in),
.dout(lut_actions_out)
);*/
lut_action_bram lut_action_bram
( .clka(clk),
.ena(bram_cs_en),
.wea(bram_we_en),
.addra(bram_addr_en),
.dina(lut_actions_in),
.douta(lut_actions_out)
);
reg [LUT_DEPTH_BITS-1:0]clear_counter;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
function integer ceildiv;
input integer num;
input integer divisor;
begin
if (num <= divisor)
ceildiv = 1;
else begin
ceildiv = num / divisor;
if (ceildiv * divisor < num)
ceildiv = ceildiv + 1;
end
end
endfunction
//-------------------- Internal Parameters ------------------------
localparam NUM_DATA_WORDS_USED = ceildiv(DATA_WIDTH,`CPCI_NF2_DATA_WIDTH);
localparam NUM_CMP_WORDS_USED = ceildiv(CMP_WIDTH, `CPCI_NF2_DATA_WIDTH);
localparam NUM_REGS_USED = (2 // for the read and write address registers
+ NUM_DATA_WORDS_USED // for data associated with an entry
+ NUM_CMP_WORDS_USED // for the data to match on
+ NUM_CMP_WORDS_USED); // for the don't cares
localparam READ_ADDR = NUM_REGS_USED-2;
localparam WAIT=0,
MATCH_BUSY=1,
MATCH=2,
MATCH_WAIT=3,
DONE=4;
reg [3:0]cur_st,nxt_st;
always@(posedge clk)
if(reset)
cur_st<=0;
else cur_st<=nxt_st;
always@(*)
begin
nxt_st=cur_st;
case(cur_st)
WAIT: if(!cam_busy & lookup_req & !skip_lookup)
begin
//if(cur_st==READY) nxt_st=MATCH;
//else nxt_st=MATCH_BUSY;
nxt_st=MATCH;
end
else if(!cam_busy & lookup_req & skip_lookup)
nxt_st=DONE;
MATCH_BUSY:nxt_st=WAIT;
MATCH: nxt_st=MATCH_WAIT;
MATCH_WAIT:nxt_st=DONE;
DONE: nxt_st=WAIT;
default:nxt_st=WAIT;
endcase
end
always@(posedge clk)
if(reset)
lookup_ack<=0;
else if(cur_st==DONE)
lookup_ack<=1;
else if(cur_st==MATCH_BUSY)
lookup_ack<=1;
else
lookup_ack<=0;
always@(posedge clk)
if(reset)
lookup_hit<=0;
else if(cur_st==DONE)
lookup_hit<=cam_match;
else if(MATCH_BUSY)
lookup_hit<=0;
else
lookup_hit<=0;
always@(posedge clk)
if(reset)
bram_cs_en<=0;
//else if(bram_cs) bram_cs_en=1;
else if(cur_st==MATCH)
bram_cs_en<=1;
else bram_cs_en<=bram_cs;
always@(posedge clk)
if(reset)
bram_we_en<=0;
//else if(bram_cs) bram_we_en=bram_we;
else if(cur_st==MATCH)
bram_we_en<=0;
else bram_we_en<=bram_we;
always@(posedge clk)
if(reset)
bram_addr_en<=0;
//else if(bram_cs) bram_addr_en=bram_addr;
else if(cur_st==MATCH)
bram_addr_en<=cam_match_addr;
else bram_addr_en<=bram_addr;
always@(posedge clk)
if(reset)
lookup_data<=0;
else
lookup_data<=cam_match?lut_actions_out:0;
always@(posedge clk)
if(reset)
lookup_address<=0;
else if(cur_st==MATCH_BUSY)
lookup_address<=0;
else if(cur_st==DONE)
lookup_address<=cam_match?cam_match_addr:0;
else lookup_address<=0;
/*
//---------------------- Wires and regs----------------------------
always @(*) begin
cam_match_encoded_addr = LUT_DEPTH[LUT_DEPTH_BITS-1:0] - 1'b1;
for (i = LUT_DEPTH-2; i >= 0; i = i-1) begin
if (cam_match_unencoded_addr[i]) begin
cam_match_encoded_addr = i[LUT_DEPTH_BITS-1:0];
end
end
end
always @(posedge clk) begin
if(reset || table_flush) begin
lookup_latched <= 0;
cam_match_found <= 0;
cam_lookup_done <= 0;
rd_req_latched <= 0;
lookup_ack <= 0;
lookup_hit <= 0;
cam_we <= 0;
cam_wr_addr <= 0;
cam_din <= 0;
cam_data_mask <= 0;
wr_ack <= 0;
rd_ack <= 0;
state <= RESET;
lookup_address <= 0;
reset_count <= 0;
cam_match_unencoded_addr <= 0;
cam_match_encoded <= 0;
cam_match_found_d1 <= 0;
end // if (reset)
else begin
// defaults
lookup_latched <= 0;
cam_match_found <= 0;
cam_lookup_done <= 0;
rd_req_latched <= 0;
lookup_ack <= 0;
lookup_hit <= 0;
cam_we <= 0;
cam_din <= 0;
cam_data_mask <= 0;
wr_ack <= 0;
rd_ack <= 0;
if (state == RESET && !cam_busy) begin
if(reset_count == LUT_DEPTH) begin
state <= READY;
cam_we <= 1'b0;
end
else begin
reset_count <= reset_count + 1'b1;
cam_we <= 1'b1;
cam_wr_addr <= reset_count[LUT_DEPTH_BITS-1:0];
cam_din <= RESET_CMP_DATA;
cam_data_mask <= RESET_CMP_DMASK;
lut_wr_data <= RESET_DATA;
end
end
else if (state == READY) begin
lookup_latched <= lookup_req;
cam_match_found <= lookup_latched & cam_match;
cam_lookup_done <= lookup_latched;
cam_match_unencoded_addr <= cam_match_addr;
cam_match_encoded <= cam_lookup_done;
cam_match_found_d1 <= cam_match_found;
lut_rd_addr <= (!cam_match_found && rd_req) ? rd_addr : cam_match_encoded_addr;
rd_req_latched <= (!cam_match_found && rd_req);
lookup_ack <= cam_match_encoded;
lookup_hit <= cam_match_found_d1;
lut_rd_data <= lut[lut_rd_addr];
lookup_address <= lut_rd_addr;
rd_ack <= rd_req_latched;
if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1) begin
cam_we <= 1;
cam_wr_addr <= wr_addr;
cam_din <= wr_cmp_data ;
cam_data_mask <= wr_cmp_dmask;
wr_ack <= 1;
lut_wr_data <= wr_data;
end
else begin
cam_we <= 0;
wr_ack <= 0;
end // else: !if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1)
end // else: !if(state == RESET)
end // else: !if(reset)
// separate this out to allow implementation as BRAM
end // always @ (posedge clk)*/
endmodule // cam_lut_sm
|
#include <bits/stdc++.h> using namespace std; const int64_t Nmax = 2e5 + 10; const int64_t mod = 1000000007; vector<int64_t> prime; int64_t is_power_of_two(int64_t a) { return a && (!(a & (a - 1))); } int64_t isperfectsquare(int64_t a) { double b = sqrt(a); return (b - ceil(b) == 0); } int64_t pow(int64_t a, int64_t b, int64_t m) { a = a % m; int64_t res = 1; while (b > 0) { if (b & 1) { res = res * a % m; } a = a * a % m; b = b / 2; } return res; } int64_t mod_add(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (((a + b) % m) + m) % m; } int64_t mod_mul(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (((a * b) % m) + m) % m; } int64_t mod_sub(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (((a - b) % m) + m) % m; } int64_t mod_div(int64_t a, int64_t b, int64_t m) { a = a % m; b = b % m; return (mod_mul(a, pow(b, m - 2, m), m)); } void sieve(int64_t n) { bool isprime[n + 1]; memset(isprime, true, sizeof(isprime)); prime.push_back(2); for (int64_t i = 3; i <= sqrt(n); i += 2) { if (isprime[i]) { for (int64_t j = i * i; j <= n; j += i) { isprime[j] = false; } } } for (int64_t i = 3; i <= n; i += 2) { if (isprime[i]) { prime.push_back(i); } } } vector<pair<int64_t, int64_t>> Getprimefactors(int64_t n) { vector<pair<int64_t, int64_t>> pr; for (int64_t i = 2; i <= sqrt(n); i++) { int64_t cnt = 0; while (n % i == 0) { cnt++; n /= i; } if (cnt) pr.push_back({i, cnt}); } if (n > 1) { pr.push_back({n, 1}); } return pr; } void solve() { int64_t n, od = 0, ev = 0, ans = 0, ans1 = 0; cin >> n; vector<int64_t> a(n), even, odd; for (int64_t i = 0; i <= n - 1; i++) { cin >> a[i]; if (a[i] & 1) { od++; odd.push_back(i); } else { ev++; even.push_back(i); } } if (abs(od - ev) > 1) { cout << -1 n ; return; } if (n & 1) { int64_t p = 0; if (od > ev) { for (int64_t i = 0; i < n; i += 2) { ans += abs(odd[p] - i); p++; } } else { for (int64_t i = 0; i < n; i += 2) { ans += abs(even[p] - i); p++; } } cout << ans << n ; } else { int64_t p = 0; for (int64_t i = 0; i < n; i += 2) { ans += abs(odd[p] - i); p++; } p = 0; for (int64_t i = 1; i <= n; i += 2) { ans1 += abs(odd[p] - i); p++; } cout << min(ans1, ans) << n ; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int64_t t = 1; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; void Rd(int &res) { res = 0; char p; while (p = getchar(), p < 0 ) ; do { res = (res << 1) + (res << 3) + (p ^ 48); } while (p = getchar(), p >= 0 ); } void Pt(long long x) { if (x == 0) return; Pt(x / 10); putchar(x % 10 ^ 48); } void Ps(long long x) { if (x < 0) { putchar( - ); x = -x; } if (x == 0) putchar( 0 ); else Pt(x); } long long ans[100005]; struct W { int x, y, id; bool operator<(const W &a) const { return x < a.x; } }; vector<W> son[2][100005 * 3]; bool mark[4][100005 * 3]; int n, m, k; int id(int x, int y, int f) { if (f == 0 || f == 3) return y - x + 100005; return x + y + 100005; } void dfs(int x, int y, int f, long long t) { int FF = id(x, y, f); if (mark[f][FF]) return; mark[f][FF] = 1; if (f == 0) { int heng = n - x, shu = m - y; int kkk = y - x + 100005; vector<W>::iterator it = son[0][kkk].begin(); for (; it != son[0][kkk].end(); it++) { W op = (*it); int mm = op.x - x; if (ans[op.id] == -1) ans[op.id] = t + mm; } son[0][kkk].clear(); if (heng > shu) { dfs(x + shu, m, 1, t + shu); } else if (shu > heng) { dfs(n, y + heng, 2, t + heng); } else if (shu == heng) { return; } } else if (f == 1) { int heng = n - x, shu = y; int kkk = x + y + 100005; vector<W>::iterator it = son[1][kkk].begin(); for (; it != son[1][kkk].end(); it++) { W op = (*it); int mm = op.x - x; if (ans[op.id] == -1) ans[op.id] = t + mm; } son[1][kkk].clear(); if (heng > shu) { dfs(x + shu, 0, 0, t + shu); } else if (shu > heng) { dfs(n, y - heng, 3, t + heng); } else if (shu == heng) { return; } } else if (f == 2) { int heng = x, shu = m - y; int kkk = x + y + 100005; vector<W>::iterator it = son[1][kkk].begin(); for (; it != son[1][kkk].end(); it++) { W op = (*it); int mm = x - op.x; if (ans[op.id] == -1) ans[op.id] = t + mm; } son[1][kkk].clear(); if (heng > shu) { dfs(x - shu, m, 3, t + shu); } else if (shu > heng) { dfs(0, y + heng, 0, t + heng); } else if (shu == heng) { return; } } else if (f == 3) { int heng = x, shu = y; int kkk = y - x + 100005; vector<W>::iterator it = son[0][kkk].begin(); for (; it != son[0][kkk].end(); it++) { W op = (*it); int mm = x - op.x; if (ans[op.id] == -1) ans[op.id] = t + mm; } son[0][kkk].clear(); if (heng > shu) { dfs(x - shu, 0, 2, t + shu); } else if (shu > heng) { dfs(0, y - heng, 1, t + heng); } else if (shu == heng) { return; } } } int main() { memset(ans, -1, sizeof(ans)); Rd(n), Rd(m), Rd(k); for (int i = 1; i <= k; i++) { int x, y; Rd(x), Rd(y); int tot = x + y + 100005; son[1][tot].push_back((W){x, y, i}); tot = y - x + 100005; son[0][tot].push_back((W){x, y, i}); } dfs(0, 0, 0, 0); for (int i = 1; i <= k; i++) Ps(ans[i]), puts( ); return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [4*PAYLOAD_WIDTH-1:0] rd_data;
reg [4*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<4; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 4*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [4*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[4*DATA_WIDTH-1:0];
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:34:06 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_mid/bg_mid_stub.v
// Design : bg_mid
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bg_mid(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[14:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [14:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog wrapper for lpflow_clkbufkapwr with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkbufkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
|
#include <bits/stdc++.h> using namespace std; int n, k; const int N = 1e7 + 100; bool a[N]; int main() { cin >> n >> k; vector<long long> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; a[v[i]] = 1; } int q; cin >> q; for (int test = 0; test < q; test++) { long long w; int ans = 1000; cin >> w; for (int t = 1; t <= k; t++) { for (int i = 0; i < n; i++) { long long rem = w - t * v[i]; if (rem < 0) continue; if (rem == 0) ans = min(ans, t); for (int e = 1; t + e <= k; e++) { if (rem % e != 0) continue; long long x = rem / e; if (x >= N) continue; if (a[x]) ans = min(e + t, ans); } } } if (ans != 1000) cout << ans; else cout << -1; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int ni() { int a; scanf( %d , &a); return a; } double nf() { double a; scanf( %lf , &a); return a; } char sbuf[100005]; string ns() { scanf( %s , sbuf); return sbuf; } long long nll() { long long a; scanf( %lld , &a); return a; } template <class T> void out(T a, T b) { bool first = true; for (T i = a; i != b; ++i) { if (!first) printf( ); first = false; cout << *i; } printf( n ); } template <class T> void outl(T a, T b) { for (T i = a; i != b; ++i) { cout << *i << n ; } } int n, m; int moo(char c) { if (c <= 9 && c >= 0 ) return c - 0 ; return c - A + 10; } int a[6][6]; bool inside(int a) { return a >= 0 && a < 6; } char ss[1005]; vector<string> ans; void add(char c, int z, int num) { int j; sprintf(ss, %c%d n , c, z + 1); while (num) { if (c == L ) { int t = a[z][0]; for (j = (0); j < (((5))); ++j) a[z][j] = a[z][j + 1]; a[z][5] = t; } if (c == R ) { int t = a[z][5]; for (j = (0); j < (((5))); ++j) a[z][5 - j] = a[z][4 - j]; a[z][0] = t; } if (c == U ) { int t = a[0][z]; for (j = (0); j < (((5))); ++j) a[j][z] = a[j + 1][z]; a[5][z] = t; } if (c == D ) { int t = a[5][z]; for (j = (0); j < (((5))); ++j) a[5 - j][z] = a[4 - j][z]; a[0][z] = t; } ans.push_back(ss); --num; } } int main() { int i, j, k; for (i = (0); i < (((6))); ++i) { string s = ns(); for (j = (0); j < (((6))); ++j) a[i][j] = moo(s[j]); } startOver: int done = 0; for (i = (0); i < (((15))); ++i) { for (j = (0); j < (((15))); ++j) { int y = j; int x = i - j; if (inside(x) && inside(y)) { int xx = -1, yy = -1; int ii, jj; for (ii = (0); ii < ((6)); ++ii) for (jj = (0); jj < ((6)); ++jj) if (a[ii][jj] == y * 6 + x) xx = jj, yy = ii; ; if (x == 5 && y == 0) x = 5; if (xx == x && yy == y) { } else { bool needUp = 0; if (yy == 5 && xx == 5) { if (y == 5) { y = 4; add( U , x, 1); needUp = 1; } if (x < 4) add( L , 5, 4 - x); else if (x > 4) add( R , 5, 1); add( D , x, 5 - y); add( L , 5, 1); add( U , x, 5 - y); if (x != 5) add( R , 5, 5 - x); if (needUp) { add( D , x, 1); y = 5; } } else { if (yy == 5 && xx != 4) { yy = 4; add( U , xx, 1); needUp = 1; } if (xx < 4) add( L , 5, 4 - xx); else if (xx > 4) add( R , 5, 1); add( D , xx, 5 - yy); add( L , 5, 1); add( U , xx, 5 - yy); if (xx != 5) add( R , 5, 5 - xx); if (needUp) { add( D , xx, 1); yy = 5; } needUp = 0; if (y == 5) { y = 4; add( U , x, 1); needUp = 1; } if (x != 5) add( L , 5, 5 - x); add( D , x, 5 - y); add( R , 5, 1); add( U , x, 5 - y); if (x < 4) add( R , 5, 4 - x); else if (x > 4) add( L , 5, 1); if (needUp) { add( D , x, 1); y = 5; } } } if (a[y][x] != y * 6 + x) { printf( %d %d n , x, y); return 0; } ++done; } if (done == 34) { if (a[5][5] != 35) { add( L , 5, 3); goto startOver; } printf( %d n , ans.size()); for (i = (0); i < (((ans.size()))); ++i) printf( %s , ans[i].c_str()); return 0; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 5010; vector<int> G[maxn]; int d[maxn][maxn][2]; void check(int &a, int b) { if (a > b) a = b; } int dfs(int u, int fa) { int num = G[u].size(), tot = 0, now = 0; d[u][0][0] = 0; d[u][0][1] = 0; if (num == 1) { d[u][0][1] = INF; d[u][1][1] = 0; return 1; } for (int i = 0; i < num; ++i) { int v = G[u][i]; if (v == fa) continue; now = dfs(v, u); tot += now; for (int j = tot; j >= 0; --j) { int mn0, mn1; mn0 = mn1 = INF; for (int k = 0; k <= now; ++k) { check(mn0, min(d[u][j - k][0] + d[v][k][0], d[u][j - k][0] + d[v][k][1] + 1)); check(mn1, min(d[u][j - k][1] + d[v][k][0] + 1, d[u][j - k][1] + d[v][k][1])); } d[u][j][0] = mn0; d[u][j][1] = mn1; } } return tot; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n - 1; ++i) { int u, v; scanf( %d %d , &u, &v); G[u].push_back(v); G[v].push_back(u); } if (n == 2) { puts( 1 ); return 0; } int cnt = 0, p = 1; memset(d, INF, sizeof d); for (int i = 1; i <= n; ++i) { if (G[i].size() == 1) ++cnt; else p = i; } dfs(p, 0); int ans = min(d[p][cnt / 2][0], d[p][cnt / 2][1]); printf( %d n , ans); return 0; } |
//---------------------------------------------------------------------
//
// Company: UNSW
// Original Author: Lingkan Gong
// Project Name: XDRS Demo
//
// Create Date: 17/07/2012
// Design Name: lpfilter
//
//---------------------------------------------------------------------
`timescale 1ns/1ns
module lpfilter
#(parameter
C_TYPE = 0
)
(
input clk ,
input rstn ,
//-- to/from producer/consumer ----
output p_prdy ,
input p_crdy , // TODO: NOT USED by the LowPass Filter
input p_cerr , // TODO: NOT USED by the LowPass Filter
output [31:0] p_data ,
input c_prdy ,
output c_crdy ,
output c_cerr ,
input [31:0] c_data ,
//-- to/from reconfiguration controller----
input rc_reqn ,
output rc_ackn
);
wire fir_nd;
wire fir_rfd;
wire [15:0] fir_din;
wire start_sync;
generate begin : gen_lpfir
if (C_TYPE == 0) begin : gen_mac
wire fir_rfd_from_core;
gfirMAC #(
.C_IWIDTH (16),
.C_OWIDTH (32),
.C_CWIDTH (16),
.C_CLENGTH (21)
) fir (
.clk ( clk ),
.sclr ( ~rstn ),
.nd ( fir_nd ),
.rfd ( fir_rfd_from_core ),
.rdy ( p_prdy ),
.din ( fir_din ),
.dout ( p_data )
);
assign fir_rfd = fir_rfd_from_core & rstn; // WAR. See demo2.bug.12
end else if (C_TYPE == 1) begin : gen_tf
gfirTF #(
.C_IWIDTH (16),
.C_OWIDTH (32),
.C_CWIDTH (16),
.C_CLENGTH (21)
) fir (
.clk ( clk ),
.sclr ( ~rstn ),
.en ( fir_nd & rstn ), // WAR. See demo2.bug.12
.din ( fir_din ),
.dout ( p_data )
);
reg nd_1;
always @(posedge clk) begin
if (~rstn) begin
nd_1 <= 1'b0;
end else begin
nd_1 <= fir_nd;
end
end
assign p_prdy = nd_1;
assign fir_rfd = 1'b1 & rstn; // WAR. See demo2.bug.12
end
end endgenerate
assign fir_nd = (start_sync)? 1'b1 : c_prdy;
assign fir_din = (start_sync)? 16'h0 : c_data[15:0]; // TODO: Ignore MSB ????
assign c_crdy = (start_sync)? 1'b0 : fir_rfd;
assign c_cerr = (start_sync)? 1'b1 : 1'b0; // Cancel all requrests from consumer if (c_prdy)
pipeline_sync #(
.C_SYNCCNT (32)
) sync_0 (
.clk ( clk ),
.rstn ( rstn ),
//-- to/from core----
.rdy ( p_prdy ),
.start_sync ( start_sync ),
//-- to/from reconfiguration controller----
.rc_reqn ( rc_reqn ),
.rc_ackn ( rc_ackn )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { register long long x = 0; char zf = 1; char ch; while (ch != - && !isdigit(ch)) ch = getchar(); if (ch == - ) zf = -1, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * zf; } void write(long long y) { if (y < 0) putchar( - ), y = -y; if (y > 9) write(y / 10); putchar(y % 10 + 0 ); } inline void writeln(const long long y) { write(y); putchar( n ); } inline int min(const int x, const int y) { return x < y ? x : y; } inline int max(const int x, const int y) { return x > y ? x : y; } int i, j, k, m, n, x, y, z, cnt, la[1000010], fa[1000010], size[1000010], top, g = 0; int ask(int x) { while (fa[x] != x) x = fa[x]; return x; } void merge(int x, int y) { if (x == y) return; if (size[x] > size[y]) swap(x, y); la[++top] = x; fa[x] = y; size[y] += size[x]; } void undo() { int La = la[top]; size[fa[La]] -= size[La]; fa[La] = La; top--; } struct ed { int x, y, z; inline bool operator<(const ed s) const { return z < s.z; } } q[1000010]; struct query { int id, x, y, val; inline bool operator<(const query s) const { if (val == s.val) return id < s.id; return val < s.val; } } A[1000010]; int ans[1000010]; int main() { n = read(); m = read(); for (register int i = 1; i <= n; i++) size[i] = 1, fa[i] = i; for (register int i = 1; i <= m; i++) { x = read(); y = read(); z = read(); q[i] = {x, y, z}; } k = read(); for (register int e = 1; e <= k; e++) { z = read(); ans[e] = 1; for (register int i = 1; i <= z; i++) { x = read(); A[++cnt] = {e, q[x].x, q[x].y, q[x].z}; } } sort(q + 1, q + m + 1); sort(A + 1, A + cnt + 1); int qd = 1; for (register int i = 1; i <= cnt;) { while (q[qd].z < A[i].val) merge(ask(q[qd].x), ask(q[qd].y)), qd++; top = 0; do { if (ask(A[i].x) == ask(A[i].y)) ans[A[i].id] = 0; merge(ask(A[i].x), ask(A[i].y)); i++; } while (A[i].val == A[i - 1].val && A[i].id == A[i - 1].id); while (top) undo(); } for (register int i = 1; i <= k; i++) puts(ans[i] ? YES : NO ); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Very simple test for interface pathclearing
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(2) itopa();
ifc #(4) itopb();
sub ca (.isub(itopa.out_modport),
.clk);
sub cb (.isub(itopb.out_modport),
.clk);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];
itopb.valuei <= cyc[3:0];
if (cyc==1) begin
if (itopa.WIDTH != 2) $stop;
if (itopb.WIDTH != 4) $stop;
if ($bits(itopa.valueo) != 2) $stop;
if ($bits(itopb.valueo) != 4) $stop;
if ($bits(itopa.out_modport.valueo) != 2) $stop;
if ($bits(itopb.out_modport.valueo) != 4) $stop;
end
if (cyc==4) begin
if (itopa.valueo != 2'b11) $stop;
if (itopb.valueo != 4'b0011) $stop;
end
if (cyc==5) begin
if (itopa.valueo != 2'b00) $stop;
if (itopb.valueo != 4'b0100) $stop;
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface ifc
#(parameter WIDTH = 1);
// verilator lint_off MULTIDRIVEN
logic [WIDTH-1:0] valuei;
logic [WIDTH-1:0] valueo;
// verilator lint_on MULTIDRIVEN
modport out_modport (input valuei, output valueo);
endinterface
// Note not parameterized
module sub
(
ifc.out_modport isub,
input clk
);
always @(posedge clk) isub.valueo <= isub.valuei + 1;
endmodule
|
#include <bits/stdc++.h> const long double PI = acos(-1.0); using namespace std; int n, m; long long dp[505][505]; int a[505]; long long cal(int l, int r) { if (l >= r) return 1; long long &ret = dp[l][r]; if (ret != -1) return ret; ret = 0; int mn = n + 1, idx = 0; for (int i = l; i <= r; i++) { if (a[i] < mn) { mn = a[i]; idx = i; } } long long lft = cal(l, idx - 1); long long rgh = cal(idx + 1, r); for (int i = l; i < idx; i++) { lft += cal(l, i) * cal(i + 1, idx - 1); lft %= 998244353; } for (int i = idx + 1; i <= r; i++) { rgh += cal(idx + 1, i) * cal(i + 1, r); rgh %= 998244353; } lft %= 998244353; rgh %= 998244353; ret = rgh * lft; ret %= 998244353; return ret; } void init() { memset(dp, -1, sizeof dp); } void read_input() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; } void solve() { init(); cal(0, n - 1); } void print_ans() { cout << cal(0, n - 1) << n ; } int main() { int t = 1; while (t--) { read_input(); solve(); print_ans(); if (t) init(); } } |
#include <bits/stdc++.h> long long gcd(long long A, long long B) { return A > B ? gcd(B, A) : A ? gcd(B % A, A) : B; } long long lcm(long long A, long long B) { return A / gcd(A, B) * B; } long long pow(long long A, long long B, long long P) { if (!B) return 1 % P; if (B == 1) return A % P; long long h = pow(A, B / 2, P); h *= h; h %= P; if (B % 2) h *= A; return h % P; } using namespace std; int n, m, q, i, j, I, J; int a[41][41]; int sum[41][41]; int res[41][41][41][41]; int all[41][41][41][41]; char ch; int get(int i, int j, int I, int J) { return sum[I][J] - sum[i - 1][J] - sum[I][j - 1] + sum[i - 1][j - 1]; } bool f(int k) { if (k == 0) return true; else return false; } int main() { cin >> n >> m >> q; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { cin >> ch; a[i][j] = ch - 0 ; sum[i][j] = sum[i - 1][j] + sum[i][j - 1] - sum[i - 1][j - 1] + a[i][j]; } for (i = n; i >= 1; i--) for (j = m; j >= 1; j--) if (!a[i][j]) { all[i][j][i][j] = 1; for (I = i - 1; I >= 1; I--) all[I][j][i][j] = all[I + 1][j][i][j] + f(get(I, j, i, j)); for (J = j - 1; J >= 1; J--) all[i][J][i][j] = all[i][J + 1][i][j] + f(get(i, J, i, j)); for (I = i - 1; I >= 1; I--) for (J = j - 1; J >= 1; J--) all[I][J][i][j] = all[I][J + 1][i][j] + all[I + 1][J][i][j] - all[I + 1][J + 1][i][j] + f(get(I, J, i, j)); } for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { if (!a[i][j]) res[i][j][i][j] = 1; for (I = i + 1; I <= n; I++) res[i][j][I][j] = res[i][j][I - 1][j] + all[i][j][I][j]; for (J = j + 1; J <= m; J++) res[i][j][i][J] = res[i][j][i][J - 1] + all[i][j][i][J]; for (I = i + 1; I <= n; I++) for (J = j + 1; J <= m; J++) res[i][j][I][J] = res[i][j][I][J - 1] + res[i][j][I - 1][J] - res[i][j][I - 1][J - 1] + all[i][j][I][J]; } while (q--) { cin >> i >> j >> I >> J; cout << res[i][j][I][J] << endl; } } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RMEM.v when simulating
// the core, RMEM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RMEM(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [12 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_4_V
`define SKY130_FD_SC_LS__A31OI_4_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31oi_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_4_V
|
#include <bits/stdc++.h> using namespace std; struct point { int x; int y; }; struct vec { int x; int y; }; point r_array[12], b_array[12]; int root[12]{}, ocupied[12]{}; int r, b; double cross(point a, point b, point c) { vec v1 = {c.x - a.x, c.y - a.y}; vec v2 = {b.x - a.x, b.y - a.y}; return (v1.x * v2.y - v1.y * v2.x); } bool r_check(int r1_index, int b1_index, int r2_index, int b2_index) { point r1_cor = r_array[r1_index]; point r2_cor = r_array[r2_index]; point b1_cor = b_array[b1_index]; point b2_cor = b_array[b2_index]; double kq_r1 = cross(r1_cor, r2_cor, b2_cor); double kq_b1 = cross(b1_cor, r2_cor, b2_cor); double kq_r2 = cross(r2_cor, r1_cor, b1_cor); double kq_b2 = cross(b2_cor, r1_cor, b1_cor); if (kq_r1 * kq_b1 > 0) return 0; if (kq_r2 * kq_b2 > 0) return 0; return 1; } bool check() { bool kq = 1; for (int i = 1; i < r; i++) for (int j = i + 1; j <= r; j++) { kq = min(kq, r_check(i, root[i], j, root[j])); if (kq == 0) return 0; } return kq; } bool sinh(int r_pos) { if (r_pos > r) { return check(); } for (int i = 1; i <= b; i++) { if (ocupied[i]) continue; ocupied[i] = 1; root[r_pos] = i; bool kq = sinh(r_pos + 1); ocupied[i] = 0; if (kq) return kq; } } int main() { cin >> r >> b; for (int i = 1; i <= r; i++) cin >> r_array[i].x >> r_array[i].y; for (int i = 1; i <= b; i++) cin >> b_array[i].x >> b_array[i].y; if (r != b) { cout << No ; return 0; } bool kq = sinh(1); if (kq) puts( Yes ); else puts( No ); } |
#include<bits/stdc++.h> using namespace std; const int N=1e5+77,B=330; int n,q,a[N],t[N],b[N],l[N],r[N],m,g[N]; int nx(int x){return max(1,a[x]-t[b[x]]); } int jp(int x){if(t[b[x]]>=B)return nx(x); return g[x]; } void reb(int x) { for(int i=l[x]; i<=r[x]; i++) { int j=nx(i); if(j<l[x]) g[i]=j; else g[i]=g[j]; } } void update(int x,int y,int v) { if(b[x]==b[y]) { for(int i=x; i<=y; i++) a[i]=max(1,a[i]-v); reb(b[x]); return; } for(int i=x; i<=r[b[x]]; i++) a[i]=max(1,a[i]-v); reb(b[x]); for(int i=b[x]+1; i<b[y]; i++) { t[i]=min(t[i]+v,n); if(t[i]<B) reb(i); } for(int i=l[b[y]]; i<=y; i++) a[i]=max(1,a[i]-v); reb(b[y]); } void lca(int u,int v) { int lu=u,lv=v; while(u!=v) { if(u<v) swap(u,v),swap(lu,lv); lu=u; u=jp(u); } u=lu,v=lv; while(u!=v) { if(u<v) swap(u,v); u=nx(u); } printf( %d n ,u); } int main() { scanf( %d%d ,&n,&q); for(int i=2; i<=n; i++) scanf( %d ,&a[i]); for(int x=1; x<=n; x+=B) { int y=min(x+B-1,n); m++; l[m]=x,r[m]=y; for(int i=x; i<=y; i++) b[i]=m; reb(m); } while(q--) { int t; scanf( %d ,&t); if(t==1) { int x,y,v; scanf( %d%d%d ,&x,&y,&v); update(x,y,v); } else { int u,v; scanf( %d%d ,&u,&v); lca(u,v); } } } |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: shiftreg.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: A simple parameterized shift register.
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
module shiftreg
#(
parameter C_DEPTH=10,
parameter C_WIDTH=32
)
(
input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA
);
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
wire [(C_DEPTH+1)*C_WIDTH-1:0] wDataShift;
reg [C_WIDTH-1:0] rDataShift[C_DEPTH:0];
assign wDataShift[(C_WIDTH*0)+:C_WIDTH] = WR_DATA;
always @(posedge CLK) begin
rDataShift[0] <= WR_DATA;
end
genvar i;
generate
for (i = 1 ; i <= C_DEPTH; i = i + 1) begin : gen_sr_registers
assign wDataShift[(C_WIDTH*i)+:C_WIDTH] = rDataShift[i-1];
always @(posedge CLK) begin
rDataShift[i] <= rDataShift[i-1];
end
end
endgenerate
assign RD_DATA = wDataShift;
endmodule
|
#include <bits/stdc++.h> using namespace std; void cppio() { ios_base::sync_with_stdio(0); cin.tie(0); } const int maxn = int(2e5) + 10; int n; int a[maxn]; int p, q; long long first, second; int gcd(int a, int b) { if (!b) { first = 1, second = 0; return a; } int q = a / b; int ret = gcd(b, a % b); tie(first, second) = make_pair(second, first - second * q); return ret; } int ans[maxn][3]; int main() { cppio(); cin >> n; for (int i = 1; i <= (n); ++i) cin >> a[i]; if (n == 1) { cout << 1 1 n << (-a[1]) << n1 1 n0 n1 1 n0 n ; return 0; } cout << 1 << << n << n0 ; for (int i = 2; i <= n; ++i) { cout << (-n * 1ll * a[i]) << ; } cout << n ; cout << 1 << << 1 << n ; cout << (-a[1]) << n ; cout << 2 << << n << n ; for (int i = 2; i <= n; ++i) { int first = a[i]; cout << ((n - 1) * 1ll * first) << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int b, k; cin >> b >> k; int ans = 0; for (int i = 1; i <= k; i++) { int x; cin >> x; if (i != k) ans = (ans + b * x % 2) % 2; else ans = (ans + x % 2) % 2; } if (ans % 2 == 0) { cout << even ; } else cout << odd ; } |
#include <bits/stdc++.h> using namespace std; long long modpow(long long a, long long p, long long mod) { long long ret = 1; while (p) { if (p & 1) ret = (ret * a) % mod; a = (a * a) % mod; p /= 2; } return ret; } long long power(long long a, long long p) { long long ret = 1; while (p) { if (p & 1) ret = (ret * a); a = (a * a); p /= 2; } return ret; } int compare(const void* a, const void* b) { return (*(int*)a - *(int*)b); } int main() { int i, j, k, tmp; ios_base::sync_with_stdio(0); cin.tie(NULL); int n, m; cin >> n >> m; vector<pair<int, int> > f(n); vector<int> b(m); vector<int> f1(n); int fch[100010] = {0}; int fin[100010] = {0}; for (i = 0; i < n; i++) { cin >> j; f[i] = make_pair(j, i); f1[i] = j; fch[j] += 1; fin[j] = i; } for (i = 0; i < m; i++) { cin >> b[i]; } vector<int> a(m); int flam = 0; int flim = 0; for (i = 0; i < m; i++) { if (fch[b[i]] == 0) { flim = 1; } if (fch[b[i]] > 1) { flam = 1; } a[i] = fin[b[i]] + 1; } if (flim == 1) { cout << Impossible << endl; return 0; } if (flam == 1) { cout << Ambiguity << endl; return 0; } cout << Possible << endl; for (i = 0; i < m; i++) cout << a[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, i, j, k, d; cin >> n >> m; vector<int> arr(101, 0); for (i = 0; i < m; i++) { int no; cin >> no; arr[no]++; } for (d = m; d >= 1; d--) { vector<int> cc(arr); int k = 0; for (i = 0; i < cc.size(); i++) { if (cc[i] >= d) { k += (floor(cc[i] / d)); } } if (k >= n) { cout << d << endl; return 0; } } cout << 0 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; string A[505]; bool a[505][505]; int star[505][505]; int col[505][505]; int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) cin >> A[i]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) a[i][j] = A[i][j] == 1 ; for (int i = 1; i < n - 1; i++) for (int j = 1; j < m - 1; j++) { if (a[i][j] && a[i - 1][j] && a[i + 1][j] && a[i][j - 1] && a[i][j + 1]) star[i][j] = 1; } for (int j = 0; j < m; j++) { col[j][0] = 0; for (int i = 0; i < n; i++) col[j][i + 1] = col[j][i] + int(star[i][j]); } long long res = 0; for (int i1 = 0; i1 < n; i1++) for (int i2 = i1 + 3; i2 < n + 1; i2++) { int z[m]; for (int j = 1; j < m - 1; j++) z[j] = col[j][i2 - 1] - col[j][i1 + 1]; int s = 0, j2 = 1; for (int j1 = 1; j1 < m - 1; j1++) { while (s < k) s += z[j2++]; res += m - j2; s -= z[j1]; } } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; void fre() { freopen( c://test//input.in , r , stdin); freopen( c://test//output.out , w , stdout); } template <class T1, class T2> inline void gmax(T1 &a, T2 b) { if (b > a) a = b; } template <class T1, class T2> inline void gmin(T1 &a, T2 b) { if (b < a) a = b; } const int N = 0, M = 0, Z = 1e9 + 7, ms63 = 0x3f3f3f3f; long long n; int main() { while (~scanf( %lld , &n)) { for (long long i = 3;; i *= 3) { if (n % i != 0) { long long ans = n / i + 1; printf( %lld n , ans); break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int flag1; flag1 = 0; int flag2 = 0; for (int i = 0; i < n; i++) { if (s[i] == I ) { flag1++; } if (s[i] == A ) { flag2++; } } if (flag1 == 0) { cout << flag2 << endl; } else if (flag1 == 1) { cout << 1 << endl; } else { cout << 0 << endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: ACA_I_N32_Q8
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ACA_I_N32_Q8(
input [31:0] in1,
input [31:0] in2,
output [32:0] res
);
wire [8:0] temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9,temp10;
wire [8:0] temp11,temp12,temp13,temp14,temp15,temp16,temp17,temp18,temp19;
wire [8:0] temp20,temp21,temp22,temp23,temp24,temp25;
assign temp1[8:0] = in1[7:0] + in2[7:0];
assign temp2[8:0] = in1[8:1] + in2[8:1];
assign temp3[8:0] = in1[9:2] + in2[9:2];
assign temp4[8:0] = in1[10:3] + in2[10:3];
assign temp5[8:0] = in1[11:4] + in2[11:4];
assign temp6[8:0] = in1[12:5] + in2[12:5];
assign temp7[8:0] = in1[13:6] + in2[13:6];
assign temp8[8:0] = in1[14:7] + in2[14:7];
assign temp9[8:0] = in1[15:8] + in2[15:8];
assign temp10[8:0] = in1[16:9] + in2[16:9];
assign temp11[8:0] = in1[17:10] + in2[17:10];
assign temp12[8:0] = in1[18:11] + in2[18:11];
assign temp13[8:0] = in1[19:12] + in2[19:12];
assign temp14[8:0] = in1[20:13] + in2[20:13];
assign temp15[8:0] = in1[21:14] + in2[21:14];
assign temp16[8:0] = in1[22:15] + in2[22:15];
assign temp17[8:0] = in1[23:16] + in2[23:16];
assign temp18[8:0] = in1[24:17] + in2[24:17];
assign temp19[8:0] = in1[25:18] + in2[25:18];
assign temp20[8:0] = in1[26:19] + in2[26:19];
assign temp21[8:0] = in1[27:20] + in2[27:20];
assign temp22[8:0] = in1[28:21] + in2[28:21];
assign temp23[8:0] = in1[29:22] + in2[29:22];
assign temp24[8:0] = in1[30:23] + in2[30:23];
assign temp25[8:0] = in1[31:24] + in2[31:24];
assign res[32:0] = {temp25[8:7],temp24[7],temp23[7],temp22[7],temp21[7],temp20[7],temp19[7],temp18[7],temp17[7],temp16[7],temp15[7],temp14[7],temp13[7],temp12[7],temp11[7],temp10[7],temp9[7],temp8[7],temp7[7],temp6[7],temp5[7],temp4[7],temp3[7],temp2[7],temp1[7:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << setprecision(20); auto solve = [&]() -> string { long long int n, k, a, b; cin >> n >> k >> a >> b; long long int remG = a; long long int remB = b; string ans; vector<long long int> rem({remG, remB}); vector<long long int> lab({ G , B }); long long int cur = (remG > remB) ? 0 : 1; while (true) { if (rem[cur] == 0) { return NO ; } else if (rem[cur] < rem[1 - cur]) { ans += lab[cur]; rem[cur] -= 1; } else { long long int t = min(rem[cur], k); for (long long int i = 0; i < t; i++) ans += lab[cur]; rem[cur] -= t; } if (rem[0] == 0 && rem[1] == 0) return ans; cur = 1 - cur; } }; cout << solve() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct ppp { int x1, x2, y1, y2; void make_pair(int x1_, int x2_, int y1_, int y2_) { x1 = x1_; x2 = x2_; y1 = y1_; y2 = y2_; } } a[120]; long long ans; int n, m, i, j, k, x, y, l, r, P[220], tot, Pn, u, d; char c[1010][1010]; int Find(int x) { return lower_bound(P + 1, P + Pn + 1, x) - P; } int main() { scanf( %d%d%*d , &n, &m); for (i = 1; i <= n; ++i) scanf( %s , c[i] + 1); for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) if (c[i][j] == * ) { k = j; while (c[i][k] == * ) k++; k--; l = i; while (c[l][j] == * ) l++; l--; for (x = i; x <= l; ++x) for (y = j; y <= k; ++y) c[x][y] = . ; a[++tot].make_pair(i, l, j, k); P[++Pn] = i; P[++Pn] = l; } P[++Pn] = 0; P[++Pn] = n + 1; sort(P + 1, P + Pn + 1); Pn = unique(P + 1, P + Pn + 1) - P - 1; for (i = 1; i <= tot; ++i) a[i].x1 = Find(a[i].x1), a[i].x2 = Find(a[i].x2); for (u = 2; u < Pn; ++u) { for (d = u; d < Pn; ++d) { long long tmp = 0; vector<pair<int, int> > Q; for (i = 1; i <= tot; ++i) { if (a[i].x2 < u || a[i].x1 > d) continue; if (a[i].x1 >= u && a[i].x2 <= d) Q.push_back(make_pair(a[i].y1, -1)), Q.push_back(make_pair(a[i].y2, 1)); else Q.push_back(make_pair(a[i].y1, -100)), Q.push_back(make_pair(a[i].y2, 100)); } sort(Q.begin(), Q.end()); int num = Q.size(), C, suml, sumr, cc; Q.push_back(make_pair(m + 1, 0)); for (int C = 1; C <= 3; ++C) { suml = sumr = 0; cc = 0; for (l = 0, r = 0; r < num; ++r) { sumr += Q[r].second; cc += max(0, Q[r].second); if (!sumr) { while (suml || cc > C) { suml -= Q[l].second; cc -= max(0, Q[l].second); l++; } if (!suml && cc == C) tmp += (Q[r + 1].first - Q[r].first) * (Q[l].first - (!l ? 0 : Q[l - 1].first)); } } } ans += tmp * (P[u] - P[u - 1]) * (P[d + 1] - P[d]); } } printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; bool sortinrev(const pair<int, int> &a, const pair<int, int> &b) { return (a.first > b.first); } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); double x1, x2, y1, y2, r; cin >> r >> x1 >> y1 >> x2 >> y2; double d = sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)); double a = d / (2 * r); int b; if ((int)a * 2 * r == d) b = 0; else b = 1; if (b == 0) cout << (int)a; else cout << (int)a + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, res; cin >> n; res = n / 5; if (n % 5 != 0) res++; cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; long long n, d; while (t--) { cin >> n >> d; long long arr[n]; for (long long i = 0; i < n; i++) cin >> arr[i]; int count = 0; int i = 1; while (i < n && d > 0 && d >= i) { if ((arr[i] * i) <= d) { count += arr[i]; d = d - (arr[i] * i); } else { int t = d / i; count += t; d = d % i; } i++; } cout << arr[0] + count << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e6 + 5, Mod = 1e9 + 7, Lg = 27, P = 727, Sq = 350; const long long Inf = 3e18 + 10; long long ans; long long gcd(long long x, long long y) { if (x > y) swap(y, x); if (!x) return y; return gcd(x, y % x); } void solve(long long x, long long y, long long d1, long long z, long long w, long long d2) { long long t = y - x + 1; long long g = gcd(d1, d2); long long d = abs(x - z); long long q = d / g; if (x < z) { x += q * g; if (x < z) x += g; } else { x -= q * g; if (x > y) x -= g; } if (x < z || x > w) return; ans = max(ans, min(t, w - x + 1)); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); long long x, y, d1, z, w, d2; cin >> x >> y >> d1 >> z >> w >> d2; solve(x, y, d1, z, w, d2); solve(z, w, d2, x, y, d1); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 2000000000; const long double eps = 1e-07; int n; int a[200000]; int d[200000]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); d[0] = -inf; for (int i = 1; i <= n; ++i) d[i] = inf; for (int i = 0; i < n; i++) { int l = 0; int r = n; while (r - l > 2) { int m = (l + r) / 2; if (d[m] < a[i]) { l = m; } else r = m; } for (int j = r; j >= l; --j) if (d[j] < a[i]) { d[j + 1] = a[i]; break; } } int ans = -inf; for (int i = 1; i <= n; ++i) if (d[i] != inf) ans = max(ans, i); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long power(long long a, long long b) { if (b == 1) return a; if (b == 0) return 1; long long ans = power(a, b / 2); ans = (ans * ans); if (b & 1) ans = (ans * a); return ans; } void solve() { long long n, k; cin >> n >> k; if (n == 1) { cout << 0 << n ; return; } if (k == 1) { cout << n - 1 << n ; return; } long long x = 1; long long cnt = 0; while (x < k && n - x >= 0) { cnt++; x *= 2; } n -= x; cnt += (n + k - 1) / k; cout << cnt << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long tt = 1; cin >> tt; while (tt--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int infinity = 10000000; int railway[401][401]; int calculatedistance(int start, int end, bool bus) { bool visitedtown[401]; int distance[401]; queue<int> myQueue; for (int i = 1; i <= 400; i++) visitedtown[i] = false; for (int i = 1; i <= 400; i++) distance[i] = infinity; distance[start] = 0; visitedtown[start] = true; myQueue.push(start); while (!myQueue.empty()) { int town = myQueue.front(); myQueue.pop(); for (int i = 1; i <= end; i++) if (i != town) { if (bus) { if (!railway[town][i]) if (!visitedtown[i]) if (distance[town] + 1 < distance[i]) { distance[i] = distance[town] + 1; visitedtown[i] = true; myQueue.push(i); } } else { if (railway[town][i]) if (!visitedtown[i]) if (distance[town] + 1 < distance[i]) { distance[i] = distance[town] + 1; visitedtown[i] = true; myQueue.push(i); } } } } return distance[end]; } int main() { int n, m, u, v; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) railway[i][j] = 0; for (int i = 0; i < m; i++) { cin >> u >> v; railway[u][v] = 1; railway[v][u] = 1; } int bdis = calculatedistance(1, n, true); int tdis = calculatedistance(1, n, false); if (bdis == infinity || tdis == infinity) { cout << -1 ; return 0; } if (bdis != tdis) { cout << max(bdis, tdis); return 0; } int disb = infinity; for (int i = 2; i < n; i++) disb = min(disb, calculatedistance(1, i, false) + calculatedistance(i, n, false)); int dist; for (int i = 2; i < n; i++) dist = min(dist, calculatedistance(1, i, true) + calculatedistance(i, n, true)); cout << min(disb, dist); return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int two(int n) { return 1 << n; } inline void set_bit(int& n, int b) { n |= two(b); } inline void unset_bit(int& n, int b) { n &= ~two(b); } inline int last_bit(int n) { return n & (-n); } template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } int dx[] = {-1, 0, 1, 0}, dy[] = {0, 1, 0, -1}; const double pi = 2 * acos(0.0); const int mod = 1000000; int main() { std::ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; long long m, n; cin >> m >> n; double res = m; for (int i = 1; i < m; i++) { res -= pow(i / double(m), n); } cout << fixed << setprecision(10) << res; } |
#include <bits/stdc++.h> int _min(int a, int b) { if (a < b) return a; return b; } int _max(int a, int b) { if (a > b) return a; return b; } int main() { int i, j, k; int n; int x1, y1, x2, y2, x3, y3, res; scanf( %d %d , &x1, &y1); scanf( %d %d , &x2, &y2); scanf( %d %d , &x3, &y3); if ((x1 == x2 && x1 == x3) || (y1 == y2 && y1 == y3)) { printf( 1 ); return 0; } if (x1 == x2) { int min = _min(y1, y2); int max = _max(y1, y2); if (y3 <= min || y3 >= max) { printf( 2 ); return 0; } } if (y1 == y2) { int min = _min(x1, x2); int max = _max(x1, x2); if (x3 <= min || x3 >= max) { printf( 2 ); return 0; } } if (x1 == x3) { int min = _min(y1, y3); int max = _max(y1, y3); if (y2 <= min || y2 >= max) { printf( 2 ); return 0; } } if (y1 == y3) { int min = _min(x1, x3); int max = _max(x1, x3); if (x2 <= min || x2 >= max) { printf( 2 ); return 0; } } if (x3 == x2) { int min = _min(y3, y2); int max = _max(y3, y2); if (y1 <= min || y1 >= max) { printf( 2 ); return 0; } } if (y3 == y2) { int min = _min(x3, x2); int max = _max(x3, x2); if (x1 <= min || x1 >= max) { printf( 2 ); return 0; } } printf( 3 ); return 0; } |
#include <bits/stdc++.h> int a[100100]; int f[100100][3]; int s[100100]; char tmp[100100]; int n; void maximize(int &x, const int &y) { if (x < y) x = y; } void swap(int &a, int &b) { int sw; sw = a; a = b; b = sw; } void init(void) { scanf( %d , &n); int i; for (i = 1; i <= n; i = i + 1) scanf( %d , &a[i]); scanf( %s , tmp); for (i = 0; i < n; i = i + 1) s[i + 1] = tmp[i] - 48; for (i = 1; i <= n; i = i + 1) { if (i >= n + 1 - i) break; swap(a[i], a[n + 1 - i]); swap(s[i], s[n + 1 - i]); } } void optimize(void) { int i, j, k; memset(f, -1, sizeof f); f[0][0] = 0; for (i = 0; i < n; i = i + 1) for (j = 0; j < 2; j = j + 1) if (f[i][j] >= 0) for (k = 0; k < 2; k = k + 1) if (j || (k <= s[i + 1])) maximize(f[i + 1][j || (k < s[i + 1])], f[i][j] + a[i + 1] * k); if (f[n][0] > f[n][1]) printf( %d , f[n][0]); else printf( %d , f[n][1]); } int main(void) { init(); optimize(); return 0; } |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:ov7670_top:1.0
// IP Revision: 6
(* X_CORE_INFO = "ov7670_top,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_ov7670_top_0_1,ov7670_top,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_ov7670_top_0_1 (
clk,
scl,
sda,
ov7670_reset,
pwdn,
xclk,
pclk,
href,
vsync,
data,
M_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TLAST,
M_AXIS_TUSER,
M_AXIS_TDATA
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire clk;
output wire scl;
inout wire sda;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ov7670_signal_reset RST" *)
output wire ov7670_reset;
output wire pwdn;
output wire xclk;
input wire pclk;
input wire href;
input wire vsync;
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire M_AXIS_TREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire M_AXIS_TVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire M_AXIS_TLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *)
output wire M_AXIS_TUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [23 : 0] M_AXIS_TDATA;
ov7670_top inst (
.clk(clk),
.scl(scl),
.sda(sda),
.ov7670_reset(ov7670_reset),
.pwdn(pwdn),
.xclk(xclk),
.pclk(pclk),
.href(href),
.vsync(vsync),
.data(data),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TVALID(M_AXIS_TVALID),
.M_AXIS_TLAST(M_AXIS_TLAST),
.M_AXIS_TUSER(M_AXIS_TUSER),
.M_AXIS_TDATA(M_AXIS_TDATA)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 502; int n, k; int a[maxn], b[maxn], c[maxn]; bool check(int l, int r) { if (l == r) return true; for (int i = l + 1; i <= r; ++i) if (a[i] != a[l]) return true; return false; } bool print(int p, int r, int dir) { printf( %d %c n , p, dir == -1 ? L : R ); if (dir == -1) --p; a[p] += a[p + 1]; for (++p; p < r; ++p) a[p] = a[p + 1]; return true; } bool solve(int l, int r) { if (l == r) return false; int i, mx = -1; for (i = l; i <= r; ++i) mx = max(mx, a[i]); for (i = l; i <= r; ++i) { if (a[i] != mx) continue; if (i == l && a[i] > a[i + 1]) return print(l, r, 1); if (i == r && a[i] > a[i - 1]) return print(r, r, -1); if (i != l && i != r && a[i] > a[i + 1]) return print(i, r, 1); if (i != l && i != r && a[i] > a[i - 1]) return print(i, r, -1); } return puts( WTF??? ); } int main() { int i, j, s = 0; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]); scanf( %d , &k); for (i = 1; i <= k; ++i) scanf( %d , &b[i]); for (i = j = 1; i <= n; ++i) { s += a[i]; if (s < b[j]) continue; if (s > b[j]) return puts( NO ), 0; c[j] = i; s = 0; if (++j > k && i < n) return puts( NO ), 0; } if (j != k + 1) return puts( NO ), 0; for (i = 1; i <= k; ++i) if (!check(c[i - 1] + 1, c[i])) return puts( NO ), 0; puts( YES ); for (i = k; i; --i) while (solve(c[i - 1] + 1, c[i])) --c[i]; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 10:03:53
// Design Name:
// Module Name: _4bit_down_counter_with_synch_load_enable_clear_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _4bit_down_counter_with_synch_load_enable_clear_tb(
);
reg Clock, Clear, Enable, Load;
wire [3:0] Q;
_4bit_down_counter_with_synch_load_enable_clear DUT (.Clock(Clock), .Clear(Clear), .Enable(Enable), .Load(Load), .Q(Q));
initial begin
#300 $finish;
end
initial begin
Clock = 0; Clear = 0; Enable = 0; Load = 0;
#5 Clock = 1;
#5 Clock = 0; // 10ns
#5 Clock = 1;
#5 Clock = 0; Enable = 1;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; Clear = 1;
#5 Clock = 1;
#5 Clock = 0; // 50ns
#5 Clock = 1;
#5 Clock = 0; Clear = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; Load = 1;
#5 Clock = 1;
#5 Clock = 0; Load = 0; // 90ns
#5 Clock = 1;
#5 Clock = 0; // 100ns
#5 Clock = 1;
#5 Clock = 0; // 110ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 150ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; Enable = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 190ns
#5 Clock = 1;
#5 Clock = 0; // 200ns
#5 Clock = 1;
#5 Clock = 0; Enable = 1; // 210ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 250ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 290ns
#5 Clock = 1;
#5 Clock = 0; // 300ns
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_1_V
`define SKY130_FD_SC_HDLL__SDFXBP_1_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, x, y, n, ans, t; cin >> t; while (t--) { ans = LLONG_MAX; cin >> a >> b >> x >> y >> n; if (n >= (a - x + b - y)) cout << x * y << n ; else { if ((a - n) >= x) ans = (a - n) * b; else { if (b - (x - a + n) >= y) ans = min(ans, x * (b - (x - a + n))); } if ((b - n) >= y) ans = min(ans, (b - n) * a); else { if (a - (y - b + n) >= x) ans = min(ans, y * (a - (y - b + n))); } cout << ans << n ; } } } |
#include <bits/stdc++.h> using namespace std; bool sign[30010]; int num[2]; int value[30010]; int start[3][2] = {{0, 1}, {0, 2}, {1, 2}}; int n; bool Legal(int pos) { if (pos == n - 1) return true; int d = value[pos + 1] - value[pos]; for (int i = pos + 2; i < n; i++) { if (value[i] - value[i - 1] != d) return false; } return true; } bool Legal2() { int temp = -INT_MAX; int d = INT_MAX; bool ok = true; for (int i = n - 1; i >= 0; i--) { if (!sign[i]) { if (temp == -INT_MAX) { temp = value[i]; continue; } if (d == INT_MAX) { d = value[i] - temp; temp = value[i]; } else if (value[i] - temp != d) { ok = false; break; } else temp = value[i]; } } if (ok) return true; ok = true; temp = -INT_MAX; d = INT_MAX; for (int i = n - 1; i >= 0; i--) { if (!sign[i]) { if (temp == -INT_MAX) { temp = value[i]; continue; } if (d == INT_MAX) { d = value[i] - temp; temp = value[i]; } else if (value[i] - temp != d) return false; else temp = value[i]; } if (sign[i] && ok) { sign[i] = false; if (temp == -INT_MAX) { temp = value[i]; continue; } if (d == INT_MAX) { d = value[i] - temp; temp = value[i]; } else if (value[i] - temp != d) { sign[i] = true; ok = false; } else temp = value[i]; } } return true; } void Print() { for (int i = 0; i < n; i++) if (sign[i]) printf( %d , value[i]); printf( n ); for (int i = 0; i < n; i++) if (!sign[i]) printf( %d , value[i]); printf( n ); } int main() { cin >> n; for (int i = 0; i < n; i++) scanf( %d , &value[i]); if (n <= 4) { if (n == 2) cout << value[0] << endl << value[1] << endl; else if (n == 3) cout << value[0] << endl << value[1] << << value[2] << endl; else { cout << value[0] << << value[1] << endl; cout << value[2] << << value[3] << endl; } return 0; } if (value[0] + value[2] == 2 * value[1]) { if (value[0] == value[1]) { if (value[n - 1] == value[0]) { for (int i = 0; i < n - 1; i++) printf( %d , value[0]); printf( n ); printf( %d n , value[0]); return 0; } else { int pos = 3; for (; pos < n; pos++) if (value[pos] != value[0]) break; if (Legal(pos)) { for (int i = 0; i < pos; i++) printf( %d , value[0]); printf( n ); for (int i = pos; i < n; i++) printf( %d , value[i]); printf( n ); return 0; } } } else { int temp = value[2]; sign[0] = sign[1] = sign[2] = true; int d = value[1] - value[0]; int tot = 3; for (int i = 3; i < n; i++) { if (value[i] - temp != d) continue; else { temp = value[i]; sign[i] = true; tot++; } } if (Legal2()) { if (tot == n) sign[n - 1] = false; Print(); return 0; } } } for (int sss = 0; sss < 3; sss++) { memset(sign, false, sizeof(sign)); int temp = value[start[sss][1]]; int d = temp - value[start[sss][0]]; sign[start[sss][0]] = sign[start[sss][1]] = true; for (int i = 3; i < n; i++) { if (value[i] - temp != d) continue; else { temp = value[i]; sign[i] = true; } } if (Legal2()) { Print(); return 0; } } printf( No solution n ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long bigmod(long long n, long long pow, long long m) { long long ret = 1; while (pow) { if (pow % 2) { ret *= n; ret %= m; } n *= n; n %= m; pow /= 2; } return ret; } long long arr[3 * 100009]; int main() { long long n, a, sum = 0, sum1 = 0; scanf( %I64d , &n); for (long long i = 1; i <= n; i++) scanf( %I64d , &arr[i]); sort(arr + 1, arr + n + 1); for (long long i = 1; i <= n; i++) { sum += (arr[i] * (bigmod((long long)2, i - 1, 1000000000 + 7))); sum -= (arr[i] * (bigmod((long long)2, n - i, 1000000000 + 7))); sum %= 1000000000 + 7; } printf( %I64d n , sum); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_TB_V
`define SKY130_FD_SC_LP__MUX4_TB_V
/**
* mux4: 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A0 = 1'b1;
#240 A1 = 1'b1;
#260 A2 = 1'b1;
#280 A3 = 1'b1;
#300 S0 = 1'b1;
#320 S1 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A0 = 1'b0;
#440 A1 = 1'b0;
#460 A2 = 1'b0;
#480 A3 = 1'b0;
#500 S0 = 1'b0;
#520 S1 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 S1 = 1'b1;
#720 S0 = 1'b1;
#740 A3 = 1'b1;
#760 A2 = 1'b1;
#780 A1 = 1'b1;
#800 A0 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 S1 = 1'bx;
#920 S0 = 1'bx;
#940 A3 = 1'bx;
#960 A2 = 1'bx;
#980 A1 = 1'bx;
#1000 A0 = 1'bx;
end
sky130_fd_sc_lp__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; long long deg[123456]; long long N, S, i, s, e; long long cnt; long double ans; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> N >> S; for (i = 1; i < N; i++) { cin >> s >> e; deg[s - 1]++; deg[e - 1]++; } for (i = 0; i < N; i++) if (deg[i] == 1) cnt++; ans = (long double)S * (long double)2 / (long double)cnt; cout << fixed << setprecision(20) << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 10; const int mod = 998244353; int f[N][N], g[N][N]; int mn[N][N], indl[N], indr[N]; bool bz[N][N]; int a[1000001]; int n, m; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d , &a[i]); int x = m; m = 1; for (int i = 2; i <= x; i++) if (a[i] != a[m]) a[++m] = a[i]; for (int i = 1; i <= m; i++) { if (!indl[a[i]]) indl[a[i]] = i; indr[a[i]] = i; } if (m > 3 * n) { printf( 0 n ); return 0; } for (int i = 1; i <= n; i++) for (int j = indl[i]; j <= indr[i]; j++) if (a[j] < i) { printf( 0 n ); return 0; } for (int i = 1; i <= m; i++) { mn[i][i] = a[i]; for (int j = i + 1; j <= m; j++) mn[i][j] = min(mn[i][j - 1], a[j]); } for (int i = 1; i <= m + 1; i++) f[i][i - 1] = g[i][i - 1] = 1; for (int i = 1; i <= m; i++) for (int l = 1; l + i - 1 <= m; l++) { int r = i + l - 1; int x = mn[l][r], idl = indl[x], idr = indr[x]; if (idl > r || idr < l) continue; int v = 1; int lll = idl; while (lll != idr) { int rrr = lll + 1; while (a[rrr] != a[lll]) rrr++; v = (long long)v * f[lll + 1][rrr - 1] % mod; lll = rrr; } for (int mid = idr; mid <= r; mid++) g[l][r] = (g[l][r] + (long long)f[l][idl - 1] * f[mid + 1][r] % mod * v % mod * f[idr + 1][mid] % mod) % mod; for (int ll = l; ll <= idl; ll++) f[l][r] = (f[l][r] + (long long)g[ll][r] * f[l][ll - 1]) % mod; } printf( %d n , f[1][m]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long arr[1010], brr[1010]; int main() { long long n, i, j, x, y, ans; cin >> n; for (i = 1; i <= n; i++) cin >> arr[i]; for (i = 1; i <= n; i++) cin >> brr[i]; ans = 0; for (i = 1; i <= n; i++) { x = arr[i]; y = brr[i]; ans = max(ans, x + y); for (j = i + 1; j <= n; j++) { x = (x | arr[j]); y = (y | brr[j]); ans = max(ans, x + y); } } cout << ans; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:45:55 04/23/2017
// Design Name:
// Module Name: decrypt_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt_tb ;
reg clk_tb, reset_tb, ack_tb, enable_tb;
wire done_tb;
wire [7:0][7:0] message_tb, DESkey_tb;
wire [7:0][7:0] decrypted_tb;
parameter CLK_PERIOD = 20;
decrypt d(
message_tb,
DESkey_tb,
decrypted_tb,
done_tb,
clk_tb,
reset_tb,
enable_tb,
ack_tb
);
initial
begin : CLK_GENERATOR
clk_tb = 0;
forever
begin
#(CLK_PERIOD / 2) clk_tb = ~clk_tb;
end
end
initial
begin : RESET_GENERATOR
reset_tb = 1;
#(2 * CLK_PERIOD) reset_tb = 1;
end
initial
begin : STIMULUS
message_tb = 8'h0;
DESkey_tb = 8'h0;
enable_tb = 0;
ack_tb = 0;
wait(!reset_tb);
@(posedge clk_tb);
//test 1
@(posedge clk_tb);
#1;
message_tb = "waterbot";
DESkey = "hellodar";
enable_tb = 1;
@(posedge clk_tb);
#5;
enable_tb = 0;
wait(done_tb);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long double optN(long long m, int k) { long double ret = 1; m *= k; long long nowC = k; for (int i = 1; i <= k; ++i) { if (m < nowC * i) { ret += m / i; return ret; } ret += nowC; m -= nowC * i; if (m / (i + 1.) / nowC <= (k - i) / (i + 1.)) return ret + m / (i + 1); nowC *= k - i; nowC /= (i + 1); } return ret; }; int main() { int CASE; cin >> CASE; for (int TCASE = 1; TCASE <= CASE; ++TCASE) { long long n, m; cin >> n >> m; long long l = 0, r = (0x3f3f3f3f); while (l < r) { long long mid = l + r >> 1; if (optN(m, mid) >= n) r = mid; else l = mid + 1; } cout << l << endl; } return 0; } |
`timescale 1 ns / 1 ps
module axi_axis_reader #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// Slave side
output wire s_axis_tready,
input wire [AXI_DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH){1'b0}};
end
else
begin
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @*
begin
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if(s_axi_arvalid)
begin
int_rvalid_next = 1'b1;
int_rdata_next = s_axis_tvalid ? s_axis_tdata : {(AXI_DATA_WIDTH){1'b0}};
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign s_axi_rresp = 2'd0;
assign s_axi_arready = 1'b1;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
assign s_axis_tready = s_axi_rready & int_rvalid_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9; int main() { int n; cin >> n; long long int a; cin >> a; while (1) { if (a % 2 == 0) a /= 2; else if (a % 3 == 0) a /= 3; else break; } bool f = 1; for (int i = 0; i < n; i++) { long long int b; cin >> b; while (1) { if (b % 2 == 0) b /= 2; else if (b % 3 == 0) b /= 3; else break; } if (a != b) f = 0; a = b; } if (f) cout << YES << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000000; int aa[N + 1]; int main() { int n; cin >> n; long long ans = 0; for (int i = 0; i <= n; i++) aa[i] = i; int n_ = n; for (int h = 20; n_ > 0;) { while (h >= 0 && (n_ & 1 << h) == 0) h--; int m = n_ - ((1 << h) - 1); reverse(aa + n_ - m * 2 + 1, aa + n_ + 1); n_ -= m * 2; ans += m * 2LL * ((1 << h + 1) - 1); } cout << ans << n ; for (int i = 0; i <= n; i++) cout << aa[i] << ; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int getint() { unsigned int c; int x = 0; while (((c = getchar()) - 0 ) >= 10) { if (c == - ) return -getint(); if (!~c) exit(0); } do { x = (x << 3) + (x << 1) + (c - 0 ); } while (((c = getchar()) - 0 ) < 10); return x; } long long MOD = 1000000007; const int MAXN = 100011; struct modint { long long v; modint() : v(0) {} modint(int v) : v(v > MOD ? v - MOD : v) {} modint(long long v) : v(v % MOD) {} void null() { v = -1; } bool is_null() { return v == -1; } }; const modint mod = MOD; modint& operator+=(modint& x, modint y) { return x = x.v + y.v; } modint& operator-=(modint& x, modint y) { return x = x.v - y.v + MOD; } modint& operator*=(modint& x, modint y) { return x = (long long)x.v * y.v; } modint operator+(modint x, modint y) { return x += y; } modint operator-(modint x, modint y) { return x -= y; } modint operator*(modint x, modint y) { return x *= y; } modint operator-(modint x) { return x = modint(0) - x; } modint minv[MAXN], mfct[MAXN], mifc[MAXN]; modint mod_inv(const modint& a) { if (a.v < MAXN and minv[a.v].v) return minv[a.v]; if (a.v == 1) return minv[a.v] = 1; modint res = modint(MOD) - modint(MOD / a.v) * mod_inv(MOD % a.v); if (a.v < MAXN) minv[a.v] = res; return res; } modint& operator/=(modint& x, modint y) { return x *= mod_inv(y); } modint operator/(modint x, modint y) { return x /= y; } modint mod_pow(modint x, long long n) { modint res = 1; for (; n; x *= x, n >>= 1) if (n & 1) res *= x; return res; } modint mod_fact(int n) { if (mfct[n].v) return mfct[n]; mfct[0] = 1; for (long long i = 1; i < MAXN; i++) mfct[i] = mfct[i - 1] * i; return mfct[n]; } modint mod_ifact(int n) { return mifc[n].v ? mifc[n] : mifc[n] = mod_inv(mod_fact(n)); } modint mod_cmb(int n, int k) { if (k < 0 or n < k) return 0; return mod_fact(n) * mod_ifact(k) * mod_ifact(n - k); } ostream& operator<<(ostream& os, modint a) { os << a.v; return os; } const int N = 1000111000; vector<int> am; void make_lucky(long long n) { if (n > N) return; if (n) am.push_back(n); make_lucky(n * 10 + 7), make_lucky(n * 10 + 4); } map<int, int> mp; int cnt[1111], other, k, nn; long long dp[100111]; int main() { int i, j, tcc, tc = 1 << 28; make_lucky(0); nn = am.size(); for (i = 0; i < am.size(); i++) mp[am[i]] = i; for (tcc = 0; tcc < tc; tcc++) { memset(cnt, 0, sizeof(cnt)); other = 0; int n = getint(); k = getint(); for (i = 0; i < n; i++) { int t = getint(); if (mp.count(t)) cnt[mp[t]]++; else other++; } for (i = 0; i <= k; i++) dp[i] = 0; dp[0] = 1; for (i = 0; i < nn; i++) if (cnt[i]) { for (j = k - 1; ~j; j--) dp[j + 1] += dp[j] * cnt[i]; for (j = 0; j <= k; j++) dp[j] %= MOD; } modint res = 0; for (i = 0; i <= k; i++) { res += dp[i] * mod_cmb(other, k - i); } printf( %d n , (int)res.v); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] result; // From test of Test.v
// End of automatics
Test test (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'he58508de5310b541
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input clk,
input [63:0] crc,
input [31:0] cyc,
output wire [31:0] result);
wire enable = crc[32];
wire [31:0] d = crc[31:0];
logic [31:0] y;
always @(d iff enable == 1) begin
y <= d;
end
wire reset = (cyc < 10);
assert property (@(posedge clk iff enable)
disable iff (reset)
(crc != '0));
// Aggregate outputs into a single result vector
assign result = {32'h0, y};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s; while (cin >> n >> s) { int ans = s; for (int i = 0; i < n; ++i) { int f, t; cin >> f >> t; if (ans < f + t) { ans = f + t; } } cout << ans << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V |
#include <iostream> #include <algorithm> #include <string.h> #include <queue> #include <vector> #define INF 987654321 using namespace std; int main() { int t; scanf( %d ,&t); while(t--){ int a,b,flag=0; scanf( %d %d ,&a,&b); if(a==b)printf( YES n ); else if(a>b)printf( NO n ); else{ //์ฌ๊ธฐ๊ฐ ์ค์ ๋ก ๊ณ์ฐํด์ผ๋๋ ๋ถ๋ถ. //2^n๊ผด์ ๋ฌด์กฐ๊ฑด 1->2->4->8->16์ผ๋ก๋ง ์ด๋์ด ๊ฐ๋ฅํจ. // 3=11์ผ๋ก์, 3+1, 3+10, 3+11 3๊ฐ๊ฐ ๊ฐ๋ฅํจ. 3->4,5,6๋ค ๊ฐ๋ฅํ๋ค. // 7=111์ผ๋ก์, 7->8,9,10,11,12,13,14๋ค ๊ฐ๋ฅํ๋ค. // ๊ฒฐ๊ตญ ์ฐ๋ฆฌ๊ฐ ๊ทธ๋ผ ์ฐพ์์ผ ๋๋ ๊ฐ์ 5,6๊ณผ ๊ฐ์ ์ค๊ฐ์ ๋น๋๊ฐ์ด ์๋ ๊ฐ๋ค. // 5 = 101์ผ๋ก, 5+1, 5+100, 5+101. 5->6,9,10๋ก ์ด๋์ด ๊ฐ๋ฅ. // 6 = 110์ผ๋ก, 6+10, 6+100, 6+110. 6->8,10,12๋ก ์ด๋์ด ๊ฐ๋ฅ. // ๊ฒฐ๋ก . 3์ 11,13,14๋ฅผ ๋ชป๊ฐ. 8 =1000, 9=1001, 10=1010, 11=1011 // ์ ๊ทธ๋ผ 3=11 ์ซ์๊ฐ 2๊ฐ๋ค๋ณด๋, 11๊ณผ ๊ฐ์ด 3๊ฐ๊ฐ ํ์ํ ๊ณณ์ ๋ชป๊ฐ๋ค. for(int i=0;i<30;i++) { if((a>>i)&1)flag++; if((b>>i)&1)flag--; if(flag<0) { printf( NO n ); break; } } if(flag>=0) { printf( YES n ); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int x[100005]; int main() { int n; long long mn, mx, md, re, ans; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %I64d , &x[i]); sort(x, x + n); mn = x[n - 1]; mx = x[0] + x[n - 1]; while (mn <= mx) { re = 0; md = (mx + mn) / 2; for (int i = 0; i < n; i++) re += (md - x[i]); if (re >= md) { ans = md; mx = md - 1; } else mn = md + 1; } printf( %I64d , ans); } |
module top;
parameter real rpar = 2.0;
real rvar;
real rarr [1:0];
real rout, rtmp;
wire real wrarr [1:0];
wire real wrbslv, wrpslv, wruplv, wrdolv;
wire real wrbstr, wrpstr, wruptr, wrdotr;
wire real wrpbs = rpar[0];
wire real wrpps = rpar[0:0];
wire real wrpup = rpar[0+:1];
wire real wrpdo = rpar[0-:1];
wire real wrbs = rvar[0];
wire real wrps = rvar[0:0];
wire real wrup = rvar[0+:1];
wire real wrdo = rvar[0-:1];
wire real wrabs = rarr[0][0];
wire real wraps = rarr[0][0:0];
wire real wraup = rarr[0][0+:1];
wire real wrado = rarr[0][0-:1];
assign wrbslv[0] = rvar;
assign wrpslv[0:0] = rvar;
assign wruplv[0+:1] = rvar;
assign wrdolv[0-:1] = rvar;
assign wrarr[0][0] = rvar;
assign wrarr[0][0:0] = rvar;
assign wrarr[0][0+:1] = rvar;
assign wrarr[0][0-:1] = rvar;
tran(wrbstr[0], wrarr[1]);
tran(wrpstr[0:0], wrarr[1]);
tran(wruptr[0+:1], wrarr[1]);
tran(wrdotr[0-:1], wrarr[1]);
submod1 s1 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
submod2 s2 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
submod3 s3 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
initial begin
rtmp = rpar[0];
rtmp = rpar[0:0];
rtmp = rpar[0+:1];
rtmp = rpar[0-:1];
rtmp = rvar[0];
rtmp = rvar[0:0];
rtmp = rvar[0+:1];
rtmp = rvar[0-:1];
rtmp = rarr[0][0];
rtmp = rarr[0][0:0];
rtmp = rarr[0][0+:1];
rtmp = rarr[0][0-:1];
rout[0] = 2.0;
rout[0:0] = 2.0;
rout[0+:1] = 2.0;
rout[0-:1] = 2.0;
rarr[0][0] = 1.0;
rarr[0][0:0] = 1.0;
rarr[0][0+:1] = 1.0;
rarr[0][0-:1] = 1.0;
end
endmodule
module submod1(arg1, arg2, arg3, arg4);
input arg1, arg2, arg3, arg4;
wire real arg1, arg2, arg3, arg4;
initial $display("In submod1 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule
module submod2(arg1, arg2, arg3, arg4);
output arg1, arg2, arg3, arg4;
real arg1, arg2, arg3, arg4;
initial $display("In submod2 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule
module submod3(arg1, arg2, arg3, arg4);
inout arg1, arg2, arg3, arg4;
wire real arg1, arg2, arg3, arg4;
initial $display("In submod3 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 7; long long l[N], r[N]; long long a[N]; bool used[N]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; string second; cin >> second; for (long long i = 0; i < n; ++i) cin >> a[i]; set<pair<long long, long long> > ms; for (long long i = 0; i < n; ++i) { l[i] = i - 1; r[i] = i + 1; } r[n] = n; for (long long i = 0; i < n - 1; ++i) { if (second[i] != second[i + 1]) { ms.insert(make_pair(abs(a[i] - a[i + 1]), i)); } } vector<pair<long long, long long> > ans; while (ms.size()) { long long i = ms.begin()->second; ms.erase(ms.begin()); if (used[i] || used[r[i]]) continue; ans.push_back(make_pair(i, r[i])); used[i] = used[r[i]] = 1; long long tl = l[i]; long long tr = r[r[i]]; ms.erase(make_pair(abs(a[tl] - a[i]), tl)); ms.erase(make_pair(abs(a[tr] - a[r[i]]), r[i])); if (tl != -1) r[tl] = tr; if (tr != n) l[tr] = tl; if (tl != -1 && tr != n && second[tl] != second[tr]) { ms.insert(make_pair(abs(a[tl] - a[tr]), tl)); } } cout << ans.size() << n ; for (auto e : ans) cout << e.first + 1 << << e.second + 1 << n ; } |
#include <bits/stdc++.h> using namespace std; inline int getidx(const vector<int>& ar, int x) { return lower_bound(ar.begin(), ar.end(), x) - ar.begin(); } inline long long GCD(long long a, long long b) { long long n; if (a < b) swap(a, b); while (b != 0) { n = a % b; a = b; b = n; } return a; } inline long long LCM(long long a, long long b) { if (a == 0 || b == 0) return GCD(a, b); return a / GCD(a, b) * b; } inline long long CEIL(long long n, long long d) { return n / d + (long long)(n % d != 0); } inline long long ROUND(long long n, long long d) { return n / d + (long long)((n % d) * 2 >= d); } inline long long POW(long long a, long long n) { if (n < 0) return 0; long long ret = 1; while (n) { if (n % 2) ret *= a; a = a * a; n /= 2; } return ret; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } template <class T> ostream& operator<<(ostream& os, vector<T> v) { os << [ ; int cnt = 0; for (auto vv : v) { os << vv; if (++cnt < v.size()) os << , ; } return os << ] ; } template <class T> ostream& operator<<(ostream& os, set<T> v) { os << [ ; int cnt = 0; for (auto vv : v) { os << vv; if (++cnt < v.size()) os << , ; } return os << ] ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> p) { return os << ( << p.first << , << p.second << ) ; } const int INF = 0x3fffffff, MOD = 1e9 + 7; int n; map<int, int> dp; set<int> non0; void input() { cin >> n; } int solve() { dp[-INF] = 1, dp[INF] = 0; non0.insert(-INF); while (n--) { int x; string qur; cin >> qur >> x; if (qur == ADD ) { auto it = dp.lower_bound(x); --it; dp[x] = it->second; non0.insert(x); } else { auto hi = dp.find(x); auto lo = prev(hi); lo->second = (lo->second + hi->second) % MOD; non0.insert(lo->first); non0.erase(hi->first); dp.erase(hi); for (auto it = non0.begin(); it != non0.end();) { if (*it == lo->first) ++it; else dp[*it] = 0, it = non0.erase(it); } } } int ans = 0; for (auto p : dp) { ans = (ans + p.second) % MOD; } cout << ans << n ; return 0; } void execute() { input(), solve(); } int main(void) { cin.tie(0); ios_base::sync_with_stdio(false); execute(); return 0; } |
#include <bits/stdc++.h> using namespace std; inline int ni() { int a; scanf( %d , &a); return a; } inline double nf() { double a; scanf( %lf , &a); return a; } template <class T> void out(T a, T b) { bool first = true; for (T i = a; i != b; i++) { if (!first) printf( ); first = false; cout << *i; } puts( ); } template <class T> void outl(T a, T b) { for (T i = a; i != b; i++) cout << *i << n ; } const int MAXN = 5010; int gcd(int x, int y) { while (x) { y %= x; swap(x, y); } return y; } int n, m; int a[MAXN], b[MAXN], g[MAXN]; long long d[MAXN]; long long balance[MAXN], gb[MAXN]; int main() { n = ni(); m = ni(); for (int i = 0; i < (int)(n); i++) a[i] = ni(); for (int i = 0; i < (int)(m); i++) b[i] = ni(); sort(b, b + m); g[0] = a[0]; for (int i = 1; i < n; i++) g[i] = gcd(g[i - 1], a[i]); for (int i = 0; i < (int)(n); i++) { int c = a[i]; for (int j = 2; j * j <= c; j++) { if (c % j) continue; bool flag = binary_search(b, b + m, j); while (c % j == 0) { if (flag) balance[i]--; else balance[i]++; c /= j; } } if (c != 1) { bool flag = binary_search(b, b + m, c); if (flag) balance[i]--; else balance[i]++; } } for (int i = 0; i < (int)(n); i++) { int c = g[i]; for (int j = 2; j * j <= c; j++) { if (c % j) continue; bool flag = binary_search(b, b + m, j); while (c % j == 0) { if (flag) gb[i]--; else gb[i]++; c /= j; } } if (c != 1) { bool flag = binary_search(b, b + m, c); if (flag) gb[i]--; else gb[i]++; } } for (int i = n - 1; i >= 0; i--) { d[i] = -(1LL << 60); long long sum = 0; for (int j = i; j < n; j++) { sum += balance[j]; d[i] = max(d[i], d[j + 1] + sum - ((j - i + 1) * 1LL) * gb[j]); } d[i] = max(d[i], sum); } cout << d[0] << endl; } |
#include <bits/stdc++.h> int main() { int n, a[102], sum1 = 0, sum2 = 0; int s, t; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); scanf( %d %d , &s, &t); if (s == t) { printf( 0 n ); } else { int i; if (s > t) { s ^= t; t ^= s; s ^= t; } for (i = s - 1; i < t - 1; i++) sum1 += a[i]; for (i = t - 1; i < n; i++) sum2 += a[i]; for (i = 0; i < s - 1; i++) sum2 += a[i]; int ans; sum1 > sum2 ? (ans = sum2) : (ans = sum1); printf( %d n , ans); } return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream to LocalLink bridge
*/
module axis_ll_bridge #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] axis_tdata,
input wire axis_tvalid,
output wire axis_tready,
input wire axis_tlast,
/*
* LocalLink output
*/
output wire [DATA_WIDTH-1:0] ll_data_out,
output wire ll_sof_out_n,
output wire ll_eof_out_n,
output wire ll_src_rdy_out_n,
input wire ll_dst_rdy_in_n
);
reg last_tlast = 1'b1;
always @(posedge clk or posedge rst) begin
if (rst) begin
last_tlast = 1'b1;
end else begin
if (axis_tvalid & axis_tready) last_tlast = axis_tlast;
end
end
// high for packet length 1 -> cannot set SOF and EOF in same cycle
// invalid packets are discarded
wire invalid = axis_tvalid & axis_tlast & last_tlast;
assign axis_tready = ~ll_dst_rdy_in_n;
assign ll_data_out = axis_tdata;
assign ll_sof_out_n = ~(last_tlast & axis_tvalid & ~invalid);
assign ll_eof_out_n = ~(axis_tlast & ~invalid);
assign ll_src_rdy_out_n = ~(axis_tvalid & ~invalid);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; bool visited[2][maxn]; int d[2][maxn]; string s[2]; int main() { int n, k; cin >> n >> k; cin >> s[0] >> s[1]; int dx[3] = {0, 0, 1}; int dy[3] = {1, -1, k}; queue<pair<bool, int>> q; q.push(make_pair(0, 0)); visited[0][0] = 1; while (q.size()) { pair<bool, int> k = q.front(); q.pop(); bool x = k.first; int y = k.second; for (int i = 0; i < 3; i++) { bool xx = x ^ dx[i]; int yy = y + dy[i]; if (yy >= n) { cout << YES << endl; exit(0); } if (yy >= 0 && s[xx][yy] == - && !visited[xx][yy] && yy > d[x][y]) { q.push(make_pair(xx, yy)); visited[xx][yy] = 1; d[xx][yy] = d[x][y] + 1; } } } cout << NO << endl; } |
#include <bits/stdc++.h> using namespace std; char ans[1010][1010]; int len[1010]; void upd(int n, int c) { ans[n][len[n]++] = c; } char all[1 << 21]; int main() { int n, k, l; scanf( %d%d%d , &n, &l, &k); scanf( %s , all); sort(all, all + strlen(all)); int cur = 0; int beg = 1; while (beg < k) { int beg_ = beg; while (beg <= k) { upd(beg, all[cur]); beg++; cur++; } beg = beg_; for (int i = k; i >= beg_; i--) if (ans[i][len[i] - 1] != ans[k][len[k] - 1]) { beg = i + 1; break; } if (len[k] == l) break; } while (len[k] < l) upd(k, all[cur++]); for (int i = 1; i <= n; i++) { while (len[i] < l) upd(i, all[cur++]); } for (int i = 1; i <= n; i++) puts(ans[i]); } |
#include <bits/stdc++.h> using namespace std; int n, k, c[1001], i, x, a, b; int main() { cin >> n >> k; for (int x, i = 1; i <= n; ++i) { cin >> x; c[x]++; } for (i = 1; i <= k; ++i) { a = a + c[i] / 2 * 2; b = b + c[i] % 2; } cout << a + (b + 1) / 2; } |
#include <bits/stdc++.h> using namespace std; const int MAXM = 111111; vector<int> v[MAXM]; int n, m, lim, x, lower, upper; inline bool check(int score) { for (int i = 1; i <= m; ++i) for (int j = score - 1; j < (int)v[i].size(); ++j) { int k = j - score + 1; if (v[i][j] - v[i][k] - lim <= score - 1) return true; } return false; } int main() { scanf( %d %d %d , &n, &m, &lim); for (int i = 0; i < n; ++i) { scanf( %d , &x); v[x].push_back(i); } lower = 0, upper = n; while (lower < upper) { int mid = (lower + upper + 1) / 2; if (check(mid)) lower = mid; else upper = mid - 1; } printf( %d n , lower); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; const int inf = 0x3f3f3f3f; int deep[maxn], fa[maxn][32]; vector<int> edge[maxn]; int flag[maxn]; void dfs(int u) { flag[u] = 1; for (auto i : edge[u]) { int t = i; if (flag[t]) continue; deep[t] = deep[u] + 1; fa[t][0] = u; dfs(t); } } int lca(int x, int y) { if (deep[x] > deep[y]) swap(x, y); for (int i = 30; i >= 0; i--) if (deep[fa[y][i]] >= deep[x]) y = fa[y][i]; if (x == y) return x; for (int i = 30; i >= 0; i--) if (fa[x][i] != fa[y][i]) { x = fa[x][i], y = fa[y][i]; } return fa[x][0]; } void init(int n) { deep[1] = 1; fa[1][0] = 1; dfs(1); for (int i = (1); i < (30); i++) for (int j = (1); j < (n + 1); j++) fa[j][i] = fa[fa[j][i - 1]][i - 1]; } int dis(int a, int b) { return deep[a] + deep[b] - 2 * deep[lca(a, b)]; } int main() { int n, q; cin >> n >> q; for (int i = (1); i < (n); i++) { int p; cin >> p; edge[p].push_back(i + 1); edge[i + 1].push_back(p); } init(n); while (q--) { int aans = 0; int ii[3]; cin >> ii[0] >> ii[1] >> ii[2]; for (int i = (0); i < (3); i++) aans = max(dis(ii[i], ii[(i + 1) % 3]) + dis(ii[i], ii[(i + 2) % 3]) - dis(ii[(i + 1) % 3], ii[(i + 2) % 3]) >> 1, aans); cout << aans + 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 2; long long n, a[maxn], k, ans[maxn]; long long Check(long long m) { long long res = 0, l, r, mid; for (int i = 1; i <= n; i++) { l = 1; r = a[i]; while (l <= r) { mid = (l + r) / 2; if (a[i] - 3 * mid * (mid + 1) - 1 >= m) l = mid + 1; else r = mid - 1; } ans[i] = r; res += r; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; long long l = -4e18, r = 4e18, mid; while (l <= r) { mid = (l + r) / 2; if (Check(mid) >= k) l = mid + 1; else r = mid - 1; } long long sum = Check(l); for (int i = 1; i <= n; i++) if (sum < k && ans[i] < a[i] && a[i] - 3 * (ans[i] + 1) * (ans[i] + 2) - 1 == l - 1) { sum++; ans[i]++; } for (int i = 1; i <= n; i++) cout << ans[i] << ; } |
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