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`timescale 1ns / 1ps
module hazard_unit( input clk, // isn't needed for now
input rst, // isn't needed for now
input [4:0] ex_dst_reg,
input [4:0] mem_dst_reg,
input [4:0] id_rs,
input [4:0] id_rt,
input wb_done_i,
output pstop_o,
input [5:0] mem_opcode,
input [5:0] ex_opcode,
input [5:0] id_opcode,
input id_rt_is_source,
input ex_reg_write,
input mem_reg_write,
output pc_write,
output if_id_write_en,
output hazard_detected_o );
localparam LW = 6'b100011,
SW = 6'b101011,
BEQ = 6'b000100;
assign pc_write = ~hazard_detected_o;
assign if_id_write_en = ~hazard_detected_o;
reg mem_wait_r;
reg hazard_detected;
assign hazard_detected_o = hazard_detected;
assign pstop_o = mem_wait_r;
always@(posedge clk, posedge rst) begin
if(rst)
mem_wait_r = 0;
else if (wb_done_i)
mem_wait_r = 0;
else if (id_opcode == LW || id_opcode == SW)
mem_wait_r = (id_opcode == LW || id_opcode == SW);
end
reg [1:0] coincidence;
always @* begin
coincidence = 0;
if (ex_reg_write && ( (id_rs == ex_dst_reg) | ( (id_rt == ex_dst_reg) && id_rt_is_source)))
coincidence[0] = 1'b1;
else if (mem_reg_write && ( (id_rs == mem_dst_reg) | ( (id_rt == mem_dst_reg) && id_rt_is_source)))
coincidence[1] = 1'b1;
end
always @* begin
hazard_detected = 0;
if (coincidence [0]) begin
if ( id_opcode == BEQ && ex_opcode == LW )
hazard_detected = 1;
else if ( id_opcode == BEQ && ex_opcode != LW)
hazard_detected = 1;
else if ( id_opcode != BEQ && ex_opcode == LW)
hazard_detected = 1;
end
else if (coincidence [1]) begin
if (id_opcode == BEQ && mem_opcode == LW)
hazard_detected = 1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/02/15 11:13:29 mohor
// Format of the file changed a bit.
//
// Revision 1.4 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
//
`include "timescale.v"
module eth_rxcounters
(
MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCntOut; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
wire [15:0] ByteCntDelayed;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
assign ByteCntDelayed = ByteCnt + 16'd4;
assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt;
assign ByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntEq1 = ByteCnt == 16'd1;
assign ByteCntEq2 = ByteCnt == 16'd2;
assign ByteCntEq3 = ByteCnt == 16'd3;
assign ByteCntEq4 = ByteCnt == 16'd4;
assign ByteCntEq5 = ByteCnt == 16'd5;
assign ByteCntEq6 = ByteCnt == 16'd6;
assign ByteCntEq7 = ByteCnt == 16'd7;
assign ByteCntGreat2 = ByteCnt > 16'd2;
assign ByteCntSmall7 = ByteCnt < 16'd7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= IFGCounter[4:0] + 5'd1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 4'd1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
module spi_flash_top
(
// Wishbone signals
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
);
parameter divider_len = 2;
parameter divider = 0;
parameter Tp = 1;
// Wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input [4:2] wb_adr_i; // lower address bits
input [31:0] wb_dat_i; // databus input
output [31:0] wb_dat_o; // databus output
input [3:0] wb_sel_i; // byte select inputs
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
// SPI signals
output [`SPI_SS_NB-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
input miso_pad_i; // master in slave out
reg [31:0] wb_dat_o;
reg wb_ack_o;
// Internal signals
// reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register
wire [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
reg [`SPI_SS_NB-1:0] ss; // Slave select register
wire [`SPI_MAX_CHAR-1:0] rx; // Rx register
wire [5:0] char_len;
reg char_len_ctrl; // char len
reg go; // go
wire spi_ctrl_sel; // ctrl register select
wire spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire lsb; // lsb first on line
wire ass; // automatic slave select
// Address decoder
assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
assign spi_tx_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
// Read from registers
// Wb data out
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_dat_o <= #Tp 32'b0;
else
case (wb_adr_i[`SPI_OFS_BITS])
`SPI_RX_0: wb_dat_o <= rx;
`SPI_CTRL: wb_dat_o <= {18'd0, ctrl};
`SPI_DEVIDE: wb_dat_o <= divider;
`SPI_SS: wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss};
default: wb_dat_o <= rx;
endcase
end
// Wb acknowledge
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_ack_o <= #Tp 1'b0;
else
wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
// Ctrl register
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
{go,char_len_ctrl} <= #Tp 2'b01;
else if(spi_ctrl_sel && wb_we_i && !tip)
begin
if (wb_sel_i[0])
char_len_ctrl <= #Tp wb_dat_i[5];
if (wb_sel_i[1])
go <= #Tp wb_dat_i[8];
end
else if(tip && last_bit && pos_edge)
go <= #Tp 1'b0;
end
assign char_len = char_len_ctrl ? 6'd32 : 6'd8;
`ifdef SPI_CTRL_ASS
assign ass = 1'b1;
`else
assign ass = 1'b0;
`endif
`ifdef SPI_CTRL_LSB
assign lsb = 1'b1;
`else
assign lsb = 1'b0;
`endif
`ifdef SPI_CTRL_RX_NEGEDGE
assign rx_negedge = 1'b1;
`else
assign rx_negedge = 1'b0;
`endif
`ifdef SPI_CTRL_TX_NEGEDGE
assign tx_negedge = 1'b1;
`else
assign tx_negedge = 1'b0;
`endif
assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
// Slave select register
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
ss <= #Tp {`SPI_SS_NB{1'b0}};
else if(spi_ss_sel && wb_we_i && !tip)
if (wb_sel_i[0])
ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
spi_flash_clgen
#
(
.divider_len(divider_len),
.divider(divider)
)
clgen
(
.clk_in(wb_clk_i),
.rst(wb_rst_i),
.go(go),
.enable(tip),
.last_clk(last_bit),
.clk_out(sclk_pad_o),
.pos_edge(pos_edge),
.neg_edge(neg_edge)
);
spi_flash_shift shift
(
.clk(wb_clk_i),
.rst(wb_rst_i),
.len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.latch(spi_tx_sel & wb_we_i),
.byte_sel(wb_sel_i),
.go(go),
.pos_edge(pos_edge),
.neg_edge(neg_edge),
.lsb(lsb),
.rx_negedge(rx_negedge),
.tx_negedge(tx_negedge),
.tip(tip),
.last(last_bit),
.p_in(wb_dat_i),
.p_out(rx),
.s_clk(sclk_pad_o),
.s_in(miso_pad_i),
.s_out(mosi_pad_o)
);
endmodule
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 2-11-2018
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
100% compared with Alexey Khokholov (Nuke.YKT) work with identical results.
*/
module jt12_pg_comb(
input [ 2:0] block,
input [10:0] fnum,
// Phase Modulation
input [ 4:0] lfo_mod,
input [ 2:0] pms,
// output [ 7:0] pm_out,
// Detune
input [ 2:0] detune,
output [ 4:0] keycode,
output signed [5:0] detune_out,
// Phase increment
output [16:0] phinc_out,
// Phase add
input [ 3:0] mul,
input [19:0] phase_in,
input pg_rst,
// input signed [7:0] pm_in,
input signed [5:0] detune_in,
input [16:0] phinc_in,
output [19:0] phase_out,
output [ 9:0] phase_op
);
wire signed [8:0] pm_offset;
/* pm, pg_dt and pg_inc operate in parallel */
jt12_pm u_pm(
.lfo_mod ( lfo_mod ),
.fnum ( fnum ),
.pms ( pms ),
.pm_offset ( pm_offset )
);
jt12_pg_dt u_dt(
.block ( block ),
.fnum ( fnum ),
.detune ( detune ),
.keycode ( keycode ),
.detune_signed( detune_out )
);
jt12_pg_inc u_inc(
.block ( block ),
.fnum ( fnum ),
.pm_offset ( pm_offset ),
.phinc_pure ( phinc_out )
);
// pg_sum uses the output from the previous blocks
jt12_pg_sum u_sum(
.mul ( mul ),
.phase_in ( phase_in ),
.pg_rst ( pg_rst ),
.detune_signed ( detune_in ),
.phinc_pure ( phinc_in ),
.phase_out ( phase_out ),
.phase_op ( phase_op )
);
endmodule // jt12_pg_comb |
`include "constants.vh"
`default_nettype none
module tag_decoder
(
input wire [`SPECTAG_LEN-1:0] in,
output reg [2:0] out
);
always @ (*) begin
out = 0;
case (in)
5'b00001: out = 0;
5'b00010: out = 1;
5'b00100: out = 2;
5'b01000: out = 3;
5'b10000: out = 4;
default: out = 0;
endcase // case (in)
end
endmodule // tag_decoder
module miss_prediction_fix_table
(
input wire clk,
input wire reset,
output reg [`SPECTAG_LEN-1:0] mpft_valid,
input wire [`SPECTAG_LEN-1:0] value_addr,
output wire [`SPECTAG_LEN-1:0] mpft_value,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prsuccess_tag,
input wire [`SPECTAG_LEN-1:0] setspec1_tag, //inst1_spectag
input wire setspec1_en, //inst1_isbranch & ~inst1_inv
input wire [`SPECTAG_LEN-1:0] setspec2_tag,
input wire setspec2_en
);
reg [`SPECTAG_LEN-1:0] value0;
reg [`SPECTAG_LEN-1:0] value1;
reg [`SPECTAG_LEN-1:0] value2;
reg [`SPECTAG_LEN-1:0] value3;
reg [`SPECTAG_LEN-1:0] value4;
wire [2:0] val_idx;
tag_decoder td(
.in(value_addr),
.out(val_idx)
);
assign mpft_value = {
value4[val_idx],
value3[val_idx],
value2[val_idx],
value1[val_idx],
value0[val_idx]
};
/*
wire [`SPECTAG_LEN-1:0] value0_wdec =
(~setspec1_tag[0] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00001) ? mpft_valid : 5'b0))) |
(~setspec2_tag[0] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00001) ? mpft_valid : 5'b0)));
*/
wire [`SPECTAG_LEN-1:0] wdecdata = mpft_valid | (setspec1_en ? setspec1_tag : 0);
wire [`SPECTAG_LEN-1:0] value0_wdec =
(~setspec1_tag[0] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00001) ? mpft_valid : 5'b0))) |
(~setspec2_tag[0] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00001) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value1_wdec =
(~setspec1_tag[1] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00010) ? mpft_valid : 5'b0))) |
(~setspec2_tag[1] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00010) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value2_wdec =
(~setspec1_tag[2] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b00100) ? mpft_valid : 5'b0))) |
(~setspec2_tag[2] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b00100) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value3_wdec =
(~setspec1_tag[3] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b01000) ? mpft_valid : 5'b0))) |
(~setspec2_tag[3] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b01000) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value4_wdec =
(~setspec1_tag[4] || ~setspec1_en ? 5'b0 :
(setspec1_tag |
((setspec1_tag == 5'b10000) ? mpft_valid : 5'b0))) |
(~setspec2_tag[4] || ~setspec2_en ? 5'b0 :
(setspec2_tag |
((setspec2_tag == 5'b10000) ? wdecdata : 5'b0)));
wire [`SPECTAG_LEN-1:0] value0_wprs =
(prsuccess_tag[0] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value1_wprs =
(prsuccess_tag[1] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value2_wprs =
(prsuccess_tag[2] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value3_wprs =
(prsuccess_tag[3] ? 5'b0 : ~prsuccess_tag);
wire [`SPECTAG_LEN-1:0] value4_wprs =
(prsuccess_tag[4] ? 5'b0 : ~prsuccess_tag);
always @ (posedge clk) begin
if (reset | prmiss) begin
mpft_valid <= 0;
end else if (prsuccess) begin
mpft_valid <= mpft_valid & ~prsuccess_tag;
end else begin
mpft_valid <= mpft_valid |
(setspec1_en ? setspec1_tag : 0) |
(setspec2_en ? setspec2_tag : 0);
end
end
always @ (posedge clk) begin
if (reset | prmiss) begin
value0 <= 0;
value1 <= 0;
value2 <= 0;
value3 <= 0;
value4 <= 0;
end else begin
value0 <= prsuccess ? (value0 & value0_wprs) : (value0 | value0_wdec);
value1 <= prsuccess ? (value1 & value1_wprs) : (value1 | value1_wdec);
value2 <= prsuccess ? (value2 & value2_wprs) : (value2 | value2_wdec);
value3 <= prsuccess ? (value3 & value3_wprs) : (value3 | value3_wdec);
value4 <= prsuccess ? (value4 & value4_wprs) : (value4 | value4_wdec);
end
end
endmodule // miss_prediction_fix_table
`default_nettype wire
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// SPI hub: arbitrating between AVR and Z80 accesses to SDcard via SPI.
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module spihub(
input wire fclk,
input wire rst_n,
// pins to SDcard
output reg sdcs_n,
output wire sdclk,
output wire sddo,
input wire sddi,
// zports SDcard iface
input wire zx_sdcs_n_val,
input wire zx_sdcs_n_stb,
input wire zx_sd_start,
input wire [7:0] zx_sd_datain,
output wire [7:0] zx_sd_dataout,
// slavespi SDcard iface
input wire avr_lock_in,
output reg avr_lock_out,
input wire avr_sdcs_n,
input wire avr_sd_start,
input wire [7:0] avr_sd_datain,
output wire [7:0] avr_sd_dataout
);
// spi2 module control
wire [7:0] sd_datain;
wire [7:0] sd_dataout;
wire sd_start;
// single dataout to all ifaces
assign zx_sd_dataout = sd_dataout;
assign avr_sd_dataout = sd_dataout;
// spi2 module itself
spi2 spi2(
.clock(fclk),
.sck(sdclk),
.sdo(sddo ),
.sdi(sddi ),
.start(sd_start ),
.din (sd_datain ),
.dout (sd_dataout),
.speed(2'b00)
);
// control locking/arbitrating between ifaces
always @(posedge fclk, negedge rst_n)
if( !rst_n )
avr_lock_out <= 1'b0;
else // posedge fclk
begin
if( sdcs_n )
avr_lock_out <= avr_lock_in;
end
// control cs_n to SDcard
always @(posedge fclk, negedge rst_n)
if( !rst_n )
sdcs_n <= 1'b1;
else // posedge fclk
begin
if( avr_lock_out )
sdcs_n <= avr_sdcs_n;
else // !avr_lock_out
if( zx_sdcs_n_stb )
sdcs_n <= zx_sdcs_n_val;
end
// control start and outgoing data to spi2
assign sd_start = avr_lock_out ? avr_sd_start : zx_sd_start;
//
assign sd_datain = avr_lock_out ? avr_sd_datain : zx_sd_datain;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: master_interface
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: This module manages the data that is to be written to the PmodGYRO, and
// produces the signals to initiate a data transfer via the spi_interface
// component. Once the master_interface receives a handshake from the
// spi_interface component data has been read from the PmodGYRO and is stored.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module master_interface(
begin_transmission,
recieved_data,
end_transmission,
clk,
rst,
start,
slave_select,
send_data,
temp_data,
x_axis_data,
y_axis_data,
z_axis_data
);
// ==============================================================================
// Port Declarations
// ==============================================================================
output begin_transmission;
input [7:0] recieved_data;
input end_transmission;
input clk;
input rst;
input start;
output slave_select;
output [7:0] send_data;
output [7:0] temp_data;
output [15:0] x_axis_data;
output [15:0] y_axis_data;
output [15:0] z_axis_data;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
reg begin_transmission;
reg slave_select;
reg [7:0] send_data;
reg [7:0] temp_data;
reg [15:0] x_axis_data;
reg [15:0] y_axis_data;
reg [15:0] z_axis_data;
parameter [2:0] StateTYPE_idle = 0,
StateTYPE_setup = 1,
StateTYPE_temp = 2,
StateTYPE_run = 3,
StateTYPE_hold = 4,
StateTYPE_wait_ss = 5,
StateTYPE_wait_run = 6;
reg [2:0] STATE;
reg [2:0] previousSTATE;
// setup control register 1 to enable x, y, and z. CTRL_REG1 (0x20)
// with read and multiple bytes not selected
// output data rate of 100 Hz
// will output 8.75 mdps/digit at 250 dps maximum
parameter [15:0] SETUP_GYRO = 16'h0F20;
// address of X_AXIS (0x28) with read and multiple bytes selected (0xC0)
parameter [7:0] DATA_READ_BEGIN = 8'hE8;
// address of TEMP (0x26) with read selected (0x80)
parameter [7:0] TEMP_READ_BEGIN = 8'hA6;
parameter MAX_BYTE_COUNT = 6;
reg [2:0] byte_count;
parameter [11:0] SS_COUNT_MAX = 12'hFFF;
reg [11:0] ss_count;
parameter [23:0] COUNT_WAIT_MAX = 24'h7FFFFF; //X"000FFF";
reg [23:0] count_wait;
reg [47:0] axis_data;
// ==============================================================================
// Implementation
// ==============================================================================
//---------------------------------------------------
// Master Controller FSM
//---------------------------------------------------
always @(posedge clk)
begin: spi_interface
begin
if (rst == 1'b1) begin
slave_select <= 1'b1;
byte_count <= 0;
count_wait <= {24{1'b0}};
axis_data <= {48{1'b0}};
x_axis_data <= {16{1'b0}};
y_axis_data <= {16{1'b0}};
z_axis_data <= {16{1'b0}};
ss_count <= {12{1'b0}};
STATE <= StateTYPE_idle;
previousSTATE <= StateTYPE_idle;
end
else
case (STATE)
// idle
StateTYPE_idle :
begin
slave_select <= 1'b1;
if (start == 1'b1)
begin
byte_count <= 0;
axis_data <= {48{1'b0}};
STATE <= StateTYPE_setup;
end
end
// setup
StateTYPE_setup :
if (byte_count < 2)
begin
if(byte_count == 0) begin
send_data <= SETUP_GYRO[7:0];
end
else begin
send_data <= SETUP_GYRO[15:8];
end
slave_select <= 1'b0;
byte_count <= byte_count + 1'b1;
begin_transmission <= 1'b1;
previousSTATE <= StateTYPE_setup;
STATE <= StateTYPE_hold;
end
else
begin
byte_count <= 0;
previousSTATE <= StateTYPE_setup;
STATE <= StateTYPE_wait_ss;
end
// temp
StateTYPE_temp :
if (byte_count == 0)
begin
slave_select <= 1'b0;
send_data <= TEMP_READ_BEGIN;
byte_count <= byte_count + 1'b1;
begin_transmission <= 1'b1;
previousSTATE <= StateTYPE_temp;
STATE <= StateTYPE_hold;
end
else if (byte_count == 1)
begin
send_data <= 8'h00;
byte_count <= byte_count + 1'b1;
begin_transmission <= 1'b1;
previousSTATE <= StateTYPE_temp;
STATE <= StateTYPE_hold;
end
else
begin
byte_count <= 0;
previousSTATE <= StateTYPE_temp;
STATE <= StateTYPE_wait_ss;
end
// run
StateTYPE_run :
if (byte_count == 0)
begin
slave_select <= 1'b0;
send_data <= DATA_READ_BEGIN;
byte_count <= byte_count + 1'b1;
begin_transmission <= 1'b1;
previousSTATE <= StateTYPE_run;
STATE <= StateTYPE_hold;
end
else if (byte_count <= 6)
begin
send_data <= 8'h00;
byte_count <= byte_count + 1'b1;
begin_transmission <= 1'b1;
previousSTATE <= StateTYPE_run;
STATE <= StateTYPE_hold;
end
else
begin
byte_count <= 0;
x_axis_data <= axis_data[15:0];
y_axis_data <= axis_data[31:16];
z_axis_data <= axis_data[47:32];
previousSTATE <= StateTYPE_run;
STATE <= StateTYPE_wait_ss;
end
// hold
StateTYPE_hold :
begin
begin_transmission <= 1'b0;
if (end_transmission == 1'b1)
begin
if (previousSTATE == StateTYPE_temp & byte_count != 1)
temp_data <= recieved_data;
else if (previousSTATE == StateTYPE_run & byte_count != 1) begin
case (byte_count)
3'd2 : axis_data[7:0] <= recieved_data;
3'd3 : axis_data[15:8] <= recieved_data;
3'd4 : axis_data[23:16] <= recieved_data;
3'd5 : axis_data[31:24] <= recieved_data;
3'd6 : axis_data[39:32] <= recieved_data;
3'd7 : axis_data[47:40] <= recieved_data;
default : ;
endcase
end
STATE <= previousSTATE;
end
end
// wait_ss
StateTYPE_wait_ss :
begin
begin_transmission <= 1'b0;
if (ss_count == SS_COUNT_MAX)
begin
slave_select <= 1'b1;
ss_count <= {12{1'b0}};
STATE <= StateTYPE_wait_run;
end
else
ss_count <= ss_count + 1'b1;
end
// wait_run
StateTYPE_wait_run :
begin
begin_transmission <= 1'b0;
if (start == 1'b0)
STATE <= StateTYPE_idle;
if (count_wait == COUNT_WAIT_MAX)
begin
count_wait <= {24{1'b0}};
if (previousSTATE == StateTYPE_temp)
STATE <= StateTYPE_run;
else
STATE <= StateTYPE_temp;
end
else
count_wait <= count_wait + 1'b1;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:35:11 11/08/2015
// Design Name:
// Module Name: prf_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prf_tb( );
reg clk, rst, RegDest_compl, tbclk2x; //clk, rst, write enable, testbench 2x clk
reg [5:0] p_rs, p_rt, p_rd; //reg addresses
reg [31:0] wr_data_in;
wire [31:0] rd_data_rs, rd_data_rt;
phy_reg_file prf(
clk,
rst,
//Read interface
p_rs, //Read Address 1
p_rt, //Read Address 2
rd_data_rs, //Read Data out1
rd_data_rt, //Read Data out2
//Write interface
p_rd, //From CDB.Tag (complete stage)
wr_data_in, //From CDB.Value (complete stage)
RegDest_compl //RegDest from complete stage, it is 1 if this instruction writes register
);
always #5 clk = ~clk;
//always #2.5 tbclk2x = ~tbclk2x;
initial begin
clk = 0;
rst = 1;
RegDest_compl = 0;
p_rs = 6'b0;
p_rt = 6'b0;
p_rd = 6'b0;
wr_data_in = 32'h0;
@(posedge clk);
repeat (2) @(posedge clk); //rst needs to be asserted for 3 cycles
@(negedge clk) rst = 0;
repeat (10) @(posedge clk); //wait 10 clk cycles before clk2x is valid
p_rs = 6'h1;
@(posedge clk)
wr_data_in = 32'hDEADBEEF;
RegDest_compl = 1'b1;
p_rs = 6'h0;
@(posedge clk) //RegDest_compl = 1'b0;
p_rt = 6'h2;
p_rd = 6'h4;
p_rs = 6'h4;
wr_data_in = 32'habababab;
@(posedge clk) RegDest_compl = 1'b0;
//repeat (3) @(posedge clk);
//p_rt = 6'h0;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize(4) using namespace std; const int N = 9; const int C = 840; int n; long long dp[C * N]; long long cnt[N], M; int main() { scanf( %lld , &M); for (int i = 1; i < N; ++i) scanf( %lld , &cnt[i]); memset(dp, -1, sizeof(dp)); dp[0] = 0; for (int i = 1; i < N; ++i) { for (int j = C * N - 1; j >= 0; --j) { int c = C / i; if (cnt[i] < c) c = cnt[i]; for (int k = 1; k <= c; ++k) { if (j - k * i >= 0) { if (~dp[j - k * i]) dp[j] = max(dp[j], dp[j - k * i] + (cnt[i] - k) / (C / i)); } } } } long long ans = 0; for (int i = 0; i < (N - 1) * C; ++i) { if (~dp[i]) { if (M >= i) ans = max(ans, i + min(dp[i], (M - i) / C) * C); } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct Node { int val; int op; int cl; Node(int x, int y, int z) { val = x; op = y; cl = z; } Node() { Node(0, 0, 0); }; }; string s; vector<Node> ST; Node temp; int n, t, x, y, t1, t2; void update(int root, int l, int r, int pos) { if (l > pos || r < pos) return; if (l == r) { if (s[pos - 1] == ( ) ST[root].op = 1; if (s[pos - 1] == ) ) ST[root].cl = 1; return; } int mid = (l + r) / 2; update(root * 2, l, mid, pos); update(root * 2 + 1, mid + 1, r, pos); ST[root].val = ST[root * 2].val + ST[root * 2 + 1].val + min(ST[root * 2].op - ST[root * 2].val, ST[root * 2 + 1].cl - ST[root * 2 + 1].val); ST[root].op = ST[root * 2].op + ST[root * 2 + 1].op; ST[root].cl = ST[root * 2].cl + ST[root * 2 + 1].cl; } Node get(int root, int l, int r, int u, int v) { if (u > r || v < l) return Node(0, 0, 0); if (u == l && v == r) return ST[root]; int mid = (l + r) / 2; if (v <= mid) return get(root * 2, l, mid, u, v); else if (u > mid) return get(root * 2 + 1, mid + 1, r, u, v); else { Node n1 = get(root * 2, l, mid, u, mid), n2 = get(root * 2 + 1, mid + 1, r, mid + 1, v); int t1 = n1.val + n2.val + min(n1.op - n1.val, n2.cl - n2.val); return Node(t1, n1.op + n2.op, n1.cl + n2.cl); } } int main() { cin >> s; n = s.size(); for (int i = 0; i < 4 * n; ++i) ST.push_back(Node(0, 0, 0)); for (int i = 1; i <= n; ++i) update(1, 1, n, i); cin >> t; while (t--) { cin >> x >> y; cout << get(1, 1, n, x, y).val * 2 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const double v = 1.41421356237; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int t = 1; cin >> t; while (t--) { long long int x1, y1, z1, x2, y2, z2; cin >> x1 >> y1 >> z1 >> x2 >> y2 >> z2; long long int m, sum = 0; m = min(z1, y2); sum += (2 * m); m = min(x1, z2); x1 -= m; z2 -= m; m = min(y1, x2); y1 -= m; x2 -= m; sum -= (2 * min(y1, z2)); cout << sum << endl; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Jie Xu.
// SPDX-License-Identifier: CC0-1.0
// change these two parameters to see the speed differences
`define DATA_WIDTH 8
`define REP_COUNT4 `DATA_WIDTH/4
`define REP_COUNT2 `DATA_WIDTH/2
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] count4 = 0;
reg [1:0] count2 = 0;
reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}};
reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] res1;
reg [`DATA_WIDTH-1:0] res2;
reg [`DATA_WIDTH-1:0] res3;
reg [`DATA_WIDTH-1:0] res4;
drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1));
drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2));
drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3));
drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4));
always@(posedge clk)
begin
count2 <= count2 + 1;
count4 <= count4 + 1;
a <= {`REP_COUNT4{count4}};
b <= {`REP_COUNT4{count4}};
c <= {`REP_COUNT2{count2}};
d <= {`REP_COUNT2{count2}};
if (res1 != (a)) begin
$stop;
end
if (res2 != (a&b)) begin
$stop;
end
if (res3 != (a&b&c)) begin
$stop;
end
if (res4 != (a&b&c&d)) begin
$stop;
end
if (count4 > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module drv1
(input colSelA,
output datao
);
assign datao = colSelA;
endmodule
module drv2
(input colSelA,
input colSelB,
output datao
);
assign datao = colSelB & colSelA;
endmodule
module drv3
(input colSelA,
input colSelB,
input colSelC,
output datao
);
assign datao = colSelB & colSelA & colSelC;
endmodule
module drv4
(input colSelA,
input colSelB,
input colSelC,
input colSelD,
output datao
);
assign datao = colSelB & colSelA & colSelC & colSelD;
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of K580WG75 CRT controller
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580wg75.v
//
// Warning: This realization is not fully operational.
module k580wg75(
input clk,
input ce,
input iaddr,
input[7:0] idata,
input iwe_n,
input ird_n,
input vrtc,
input hrtc,
input dack,
input[7:0] ichar,
output reg drq,
output reg irq,
output[7:0] odata,
output[3:0] line,
output reg[6:0] ochar,
output lten,
output vsp,
output rvv,
output hilight,
output[1:0] lattr,
output[1:0] gattr );
reg[7:0] init0;
reg[7:0] init1;
reg[7:0] init2;
reg[7:0] init3;
reg enable,inte,dmae;
reg[2:0] dmadelay;
reg[1:0] dmalen;
reg[6:0] curx;
reg[5:0] cury;
wire[6:0] maxx = init0[6:0];
wire[5:0] maxy = init1[5:0];
wire[3:0] underline = init2[7:4];
wire[3:0] charheight = init2[3:0];
wire linemode = init3[7];
wire fillattr = init3[6]; // 0 - transparent, 1 - normal fill
wire curblink = init3[5]; // 0 - blink
wire curtype = init3[4]; // 0 - block, 1 - underline
reg[4:0] chline;
reg[5:0] attr;
reg[5:0] exattr;
reg[3:0] iposf;
reg[3:0] oposf;
reg[6:0] ipos;
reg[7:0] opos;
reg[5:0] ypos;
reg[4:0] frame;
reg lineff,exwe_n,exrd_n,exvrtc,exhrtc,err,vspfe;
reg[6:0] fifo0[15:0];
reg[6:0] fifo1[15:0];
reg[7:0] buf0[79:0];
reg[7:0] buf1[79:0];
reg[2:0] pstate;
reg istate;
wire vcur = opos=={1'b0,curx} && ypos==cury && (frame[3]|curblink);
wire[7:0] obuf = lineff ? buf0[opos] : buf1[opos];
assign odata = {1'b0,inte,irq,1'b0,err,enable,2'b0};
assign line = linemode==0 ? chline[4:1] : chline[4:1]==0 ? charheight : chline[4:1]+4'b1111;
assign lten = ((attr[5] || (curtype && vcur)) && chline[4:1]==underline);
assign vsp = (attr[1] && frame[4]) || (underline[3]==1'b1 && (chline[4:1]==0||chline[4:1]==charheight)) || !enable || vspfe || ypos==0;
assign rvv = attr[4] ^ (curtype==0 && vcur && chline[4:1]<=underline);
assign gattr = attr[3:2];
assign hilight = attr[0];
always @(posedge clk) begin
exwe_n <= iwe_n; exrd_n <= ird_n;
if (ird_n & ~exrd_n) begin
irq <= 0; err <= 0;
end
if (iwe_n & ~exwe_n) begin
if (iaddr) begin
case (idata[7:5])
3'b000: {enable,inte,pstate} <= 5'b00001;
3'b001: {enable,inte,dmadelay,dmalen} <= {2'b11,idata[4:0]};
3'b010: enable <= 0;
3'b011: pstate <= 3'b101;
3'b100: pstate <= 3'b101;
3'b101: inte <= 1'b1;
3'b110: inte <= 1'b0;
3'b111: enable <= 0; // to do
endcase
end else begin
case (pstate)
3'b001: {init0,pstate} <= {idata,3'b010};
3'b010: {init1,pstate} <= {idata,3'b011};
3'b011: {init2,pstate} <= {idata,3'b100};
3'b100: {init3,pstate} <= {idata,3'b000};
3'b101: {curx,pstate} <= {idata[6:0]+1'b1,3'b110};
3'b110: {cury,pstate} <= {idata[5:0]+1'b1,3'b000};
default: {err,pstate} <= 4'b1000;
endcase
end
end
if (ce) begin
exvrtc <= vrtc; exhrtc <= hrtc;
if (exvrtc & ~vrtc) begin
chline <= 0; ypos <= 0; dmae <= 1'b1; vspfe <= 0;
iposf <= 0; ipos <= 0; oposf <= 0; opos <= 0;
attr <= 0; exattr <= 0; frame <= frame + 1'b1;
end else
if (exhrtc & ~hrtc) begin
if (chline=={charheight,1'b1}) begin
chline <= 0; lineff <= ~lineff;
exattr <= attr; iposf <= 0; ipos <= 0;
ypos <= ypos + 1'b1;
if (ypos==maxy) irq <= 1'b1;
end else begin
chline <= chline + 1'b1;
attr <= exattr;
end
oposf <= 0; opos <= {2'b0,maxx[6:1]}+8'hD0;
end else if (ypos!=0) begin
if (obuf[7:2]==6'b111100) begin
if (obuf[1]) vspfe <= 1'b1;
end else
opos <= opos + 1'b1;
if (opos > maxx)
ochar <= 0;
else begin
casex (obuf[7:6])
2'b0x: ochar <= obuf[6:0];
2'b10: begin
if (fillattr) begin
ochar <= 0;
end else begin
ochar <= lineff ? fifo0[oposf] : fifo1[oposf];
oposf <= oposf + 1'b1;
end
attr <= obuf[5:0];
end
2'b11: ochar <= 0;
endcase
end
end
if (dack && drq) begin
drq <= 0;
case (istate)
1'b0: begin
if (ichar[7:4]==4'b1111 && ichar[0]==1'b1) begin
ipos <= 7'h7F;
if (ichar[1]==1'b1) dmae <= 0;
end else begin
ipos <= ipos + 1'b1;
end
istate <= ichar[7:6]==2'b10 ? ~fillattr : 1'b0;
end
1'b1: begin
iposf <= iposf + 1'b1;
istate <= 0;
end
endcase
case ({istate,lineff})
2'b00: buf0[ipos] <= ichar;
2'b01: buf1[ipos] <= ichar;
2'b10: fifo0[iposf] <= ichar[6:0];
2'b11: fifo1[iposf] <= ichar[6:0];
endcase
end else begin
drq <= ipos > maxx || ypos > maxy ? 1'b0 : dmae&enable;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i; scanf( %d , &n); long long int a[n]; set<long long int> x; map<long long int, set<int> > m; for (i = 0; i < n; i++) { scanf( %lld , &a[i]); x.insert(a[i]); m[a[i]].insert(i); } while (!x.empty()) { long long int j = *x.begin(); if (m[j].size() >= 2) { m[j].erase(m[j].begin()); int k = *(m[j].begin()); m[j].erase(m[j].begin()); m[2 * j].insert(k); x.insert(2 * j); } else { x.erase(x.begin()); } } vector<pair<int, long long int> > ans; map<long long int, set<int> >::iterator it; for (it = m.begin(); it != m.end(); it++) { if ((it->second).size() == 1) { ans.push_back(make_pair(*(it->second).begin(), it->first)); } } sort(ans.begin(), ans.end()); cout << ans.size() << endl; for (i = 0; i < ans.size(); i++) { printf( %lld , ans[i].second); } printf( n ); } |
// lattice ice5lp4k rxadc v2
// 07-17-16 E. Brombaugh
module rxadc_2 #(
parameter isz = 10,
fsz = 26,
dsz = 16
)
(
// SPI slave port
input SPI_CSL,
input SPI_MOSI,
output SPI_MISO,
input SPI_SCLK,
// rxadc board interface
input rxadc_clk,
output rxadc_dfs,
input rxadc_otr,
input [9:0] rxadc_dat,
// I2S DAC output
output dac_mclk,
output dac_sdout,
output dac_sclk,
output dac_lrck,
// I2S MCU interface
input mcu_sdin,
output mcu_sdout,
output mcu_sclk,
output mcu_lrck,
// RGB output
output wire o_red,
output wire o_green,
output wire o_blue
);
// This should be unique so firmware knows who it's talking to
parameter DESIGN_ID = 32'h2ADC0003;
//------------------------------
// Instantiate ADC clock buffer
//------------------------------
wire adc_clk;
SB_GB clk_gbuf(
.USER_SIGNAL_TO_GLOBAL_BUFFER(!rxadc_clk),
.GLOBAL_BUFFER_OUTPUT(adc_clk)
);
//------------------------------
// Instantiate HF Osc with div 1
//------------------------------
wire clk;
SB_HFOSC #(.CLKHF_DIV("0b00")) OSCInst0 (
.CLKHFEN(1'b1),
.CLKHFPU(1'b1),
.CLKHF(clk)
) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
//------------------------------
// reset generators
//------------------------------
reg [3:0] reset_pipe = 4'hf;
reg reset = 1'b1;
always @(posedge clk)
begin
reset <= |reset_pipe;
reset_pipe <= {reset_pipe[2:0],1'b0};
end
reg [3:0] adc_reset_pipe = 4'hf;
reg adc_reset = 1'b1;
always @(posedge adc_clk)
begin
adc_reset <= |adc_reset_pipe;
adc_reset_pipe <= {adc_reset_pipe[2:0],1'b0};
end
//------------------------------
// Internal SPI slave port
//------------------------------
wire [31:0] wdat;
reg [31:0] rdat;
wire [6:0] addr;
wire re, we, spi_slave_miso;
spi_slave
uspi(.clk(clk), .reset(reset),
.spiclk(SPI_SCLK), .spimosi(SPI_MOSI),
.spimiso(SPI_MISO), .spicsl(SPI_CSL),
.we(we), .re(re), .wdat(wdat), .addr(addr), .rdat(rdat));
//------------------------------
// Writeable registers
//------------------------------
reg [13:0] cnt_limit_reg;
reg [9:0] dpram_raddr;
reg dpram_trig;
reg [25:0] ddc_frq;
reg dac_mux_sel;
reg ddc_ns_ena;
always @(posedge clk)
if(reset)
begin
cnt_limit_reg <= 14'd2499; // 1/4 sec blink rate
dpram_raddr <= 10'h000; // read address
dpram_trig <= 1'b0;
ddc_frq <= 26'h0;
dac_mux_sel <= 1'b0;
ddc_ns_ena <= 1'b0;
end
else if(we)
case(addr)
7'h01: cnt_limit_reg <= wdat;
7'h02: dpram_raddr <= wdat;
7'h03: dpram_trig <= wdat;
7'h10: ddc_frq <= wdat;
7'h11: dac_mux_sel <= wdat;
7'h12: ddc_ns_ena <= wdat;
endcase
//------------------------------
// readable registers
//------------------------------
reg dpram_wen;
reg [10:0] dpram_rdat;
always @(*)
case(addr)
7'h00: rdat = DESIGN_ID;
7'h01: rdat = cnt_limit_reg;
7'h02: rdat = dpram_raddr;
7'h03: rdat = {dpram_raddr,dpram_rdat};
7'h04: rdat = dpram_wen;
7'h10: rdat = ddc_frq;
7'h11: rdat = dac_mux_sel;
7'h12: rdat = ddc_ns_ena;
default: rdat = 32'd0;
endcase
//------------------------------
// register ADC input data
//------------------------------
reg [9:0] dpram_waddr;
reg [10:0] dpram_wdat;
always @(posedge adc_clk)
dpram_wdat <= {rxadc_otr,rxadc_dat};
//------------------------------
// 1k x 11 dual-port RAM
//------------------------------
reg [10:0] mem [1023:0];
always @(posedge adc_clk) // Write memory.
begin
if(dpram_wen)
mem[dpram_waddr] <= dpram_wdat;
end
always @(posedge clk) // Read memory.
dpram_rdat <= mem[dpram_raddr];
//------------------------------
// write state machine - runs from 40MHz clock
//------------------------------
reg [2:0] dpram_trig_sync;
always @(posedge adc_clk)
if(adc_reset)
begin
dpram_waddr <= 10'h000;
dpram_trig_sync <= 3'b000;
dpram_wen <= 1'b0;
end
else
begin
dpram_trig_sync <= {dpram_trig_sync[1:0],dpram_trig};
if(~dpram_wen)
begin
if(dpram_trig_sync[2])
dpram_wen <= 1'b1;
dpram_waddr <= 10'h000;
end
else
begin
if(dpram_waddr == 10'h3ff)
dpram_wen <= 1'b0;
dpram_waddr <= dpram_waddr + 1;
end
end
//------------------------------
// DDC instance
//------------------------------
wire signed [dsz-1:0] ddc_i, ddc_q;
wire ddc_v;
ddc_2 #(
.isz(isz),
.fsz(fsz),
.osz(dsz)
)
u_ddc(
.clk(adc_clk), .reset(adc_reset),
.in(dpram_wdat[isz-1:0]),
.frq(ddc_frq),
.ns_ena(ddc_ns_ena),
.valid(ddc_v),
.i_out(ddc_i), .q_out(ddc_q)
);
//------------------------------
// Strap ADC Data Format for 2's comp
//------------------------------
assign rxadc_dfs = 1'b0;
//------------------------------
// handoff between ddc and i2s
//------------------------------
reg signed [dsz-1:0] ddc_i_l, ddc_q_l;
wire audio_ena;
always @(posedge adc_clk)
if(adc_reset)
begin
ddc_i_l <= 16'h0000;
ddc_q_l <= 16'h0000;
end
else
begin
if(audio_ena)
begin
ddc_i_l <= ddc_i;
ddc_q_l <= ddc_q;
end
end
//------------------------------
// I2S serializer
//------------------------------
wire sdout;
i2s_out
ui2s(.clk(adc_clk), .reset(adc_reset),
.l_data(ddc_i_l), .r_data(ddc_q_l),
.mclk(dac_mclk), .sdout(sdout), .sclk(dac_sclk), .lrclk(dac_lrck),
.load(audio_ena));
// Hook up I2S to DAC and MCU I2S pins
assign mcu_lrck = dac_lrck;
assign mcu_sclk = dac_sclk;
assign dac_sdout = (dac_mux_sel == 1'b1) ? mcu_sdin : sdout;
assign mcu_sdout = sdout;
//------------------------------
// Instantiate LF Osc
//------------------------------
wire CLKLF;
SB_LFOSC OSCInst1 (
.CLKLFEN(1'b1),
.CLKLFPU(1'b1),
.CLKLF(CLKLF)
) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
//------------------------------
// Divide the clock
//------------------------------
reg [13:0] clkdiv;
reg onepps;
always @(posedge CLKLF)
begin
if(clkdiv == 14'd0)
begin
onepps <= 1'b1;
clkdiv <= cnt_limit_reg;
end
else
begin
onepps <= 1'b0;
clkdiv <= clkdiv - 14'd1;
end
end
//------------------------------
// LED signals
//------------------------------
reg [2:0] state;
always @(posedge CLKLF)
begin
if(onepps)
state <= state + 3'd1;
end
//------------------------------
// Instantiate RGB DRV
//------------------------------
wire red_pwm_i = state[0];
wire grn_pwm_i = state[1];
wire blu_pwm_i = state[2];
SB_RGB_DRV RGB_DRIVER (
.RGBLEDEN (1'b1), // Enable current for all 3 RGB LED pins
.RGB0PWM (red_pwm_i), // Input to drive RGB0 - from LEDD HardIP
.RGB1PWM (grn_pwm_i), // Input to drive RGB1 - from LEDD HardIP
.RGB2PWM (blu_pwm_i), // Input to drive RGB2 - from LEDD HardIP
.RGBPU (led_power_up_i), //Connects to LED_DRV_CUR primitive
.RGB0 (o_red),
.RGB1 (o_green),
.RGB2 (o_blue)
);
defparam RGB_DRIVER.RGB0_CURRENT = "0b000111";
defparam RGB_DRIVER.RGB1_CURRENT = "0b000111";
defparam RGB_DRIVER.RGB2_CURRENT = "0b000111";
//------------------------------
// Instantiate LED CUR DRV
//------------------------------
SB_LED_DRV_CUR LED_CUR_inst (
.EN (1'b1), //Enable to supply reference current to the LED drivers
.LEDPU (led_power_up_i) //Connects to SB_RGB_DRV primitive
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : system_mig_7series_0_0.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Wed Feb 01 2012
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Revision History :
//*****************************************************************************
//`define SKIP_CALIB
`timescale 1ps/1ps
module system_mig_7series_0_0 (
// Inouts
inout [15:0] ddr3_dq,
inout [1:0] ddr3_dqs_n,
inout [1:0] ddr3_dqs_p,
// Outputs
output [13:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [0:0] ddr3_cs_n,
output [1:0] ddr3_dm,
output [0:0] ddr3_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output mmcm_locked,
input aresetn,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [0:0] s_axi_awid,
input [27:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [127:0] s_axi_wdata,
input [15:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [0:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [0:0] s_axi_arid,
input [27:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [0:0] s_axi_rid,
output [127:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
input [11:0] device_temp_i,
// The 12 MSB bits of the temperature sensor transfer
// function need to be connected to this port. This port
// will be synchronized w.r.t. to fabric clock internally.
output [11:0] device_temp,
`ifdef SKIP_CALIB
output calib_tap_req,
input calib_tap_load,
input [6:0] calib_tap_addr,
input [7:0] calib_tap_val,
input calib_tap_load_done,
`endif
input sys_rst
);
// Start of IP top instance
system_mig_7series_0_0_mig u_system_mig_7series_0_0_mig (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
// Reference Clock Ports
.clk_ref_i (clk_ref_i),
.device_temp_i (device_temp_i),
.device_temp (device_temp),
`ifdef SKIP_CALIB
.calib_tap_req (calib_tap_req),
.calib_tap_load (calib_tap_load),
.calib_tap_addr (calib_tap_addr),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
`endif
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; double arr[n]; double temp = 0; for (int i = 0; i < n; i++) { cin >> temp; arr[i] = temp; } long long sum = 0; double fractpart, intpart; int arr2[n]; for (int i = 0; i < n; i++) { arr2[i] = ((int)floor(arr[i])); sum += arr2[i]; } int count = -sum; int total = 0, index = 0; while (count != 0) { if (arr[index] - floor(arr[index]) < 0.000001) { index++; continue; } count--; arr2[index]++; index++; } for (int i = 0; i < n; i++) { cout << arr2[i] << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_4_V
`define SKY130_FD_SC_MS__NOR3B_4_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_4_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This is a fifo that keeps track of the number of valids it must issue,
// while taking into account downstream stalls.
//
// This is mostly used in conjunction with vfabric_register, where we
// output the same configured value for every valid signal we get.
//
module vfabric_counter_fifo (
clock, resetn, i_counter_reset, i_datain_valid, o_datain_stall,
o_dataout_valid, i_dataout_stall
);
parameter DEPTH=2048;
localparam COUNTER_BITS = $clog2(DEPTH)+1;
input clock, resetn, i_counter_reset;
input i_datain_valid, i_dataout_stall;
output o_dataout_valid, o_datain_stall;
reg [COUNTER_BITS-1:0] valid_counter;
reg [COUNTER_BITS:0] valid_counter_neg;
wire input_accepted, output_acknowledged;
assign input_accepted = i_datain_valid;
assign output_acknowledged = o_dataout_valid & ~i_dataout_stall;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
valid_counter <= {COUNTER_BITS{1'b0}};
valid_counter_neg <= {(COUNTER_BITS+1){1'b0}};
end
else if (i_counter_reset)
begin
valid_counter <= {COUNTER_BITS{1'b0}};
valid_counter_neg <= {(COUNTER_BITS+1){1'b0}};
end
else
begin
valid_counter <= valid_counter + input_accepted - output_acknowledged;
valid_counter_neg <= valid_counter_neg - input_accepted + output_acknowledged;
end
end
assign o_datain_stall = valid_counter[COUNTER_BITS-1];
assign o_dataout_valid = valid_counter_neg[COUNTER_BITS];
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, x, c, a[200001], tin[200001], tout[200001], sz[200001], seg[524288]; string s; bool lazy[524288]; vector<int> G[200001]; void dfs(int i) { tin[i] = ++c; ++sz[i]; for (int j : G[i]) { dfs(j); sz[i] += sz[j]; } tout[i] = c; } void upd(int l, int r, int s = 1, int e = n, int i = 1) { if (lazy[i]) { seg[i] = (e - s + 1) - seg[i]; if (s != e) { lazy[2 * i] ^= 1; lazy[2 * i + 1] ^= 1; } lazy[i] = 0; } if (s > r || e < l) return; if (s >= l && e <= r) { seg[i] = (e - s + 1) - seg[i]; if (s != e) { lazy[2 * i] ^= 1; lazy[2 * i + 1] ^= 1; } return; } int mid = (s + e) / 2; upd(l, r, s, mid, 2 * i); upd(l, r, mid + 1, e, 2 * i + 1); seg[i] = seg[2 * i] + seg[2 * i + 1]; } int que(int l, int r, int s = 1, int e = n, int i = 1) { if (lazy[i]) { seg[i] = (e - s + 1) - seg[i]; if (s != e) { lazy[2 * i] ^= 1; lazy[2 * i + 1] ^= 1; } lazy[i] = 0; } if (s > r || e < l) return 0; if (s >= l && e <= r) return seg[i]; int mid = (s + e) / 2; return que(l, r, s, mid, 2 * i) + que(l, r, mid + 1, e, 2 * i + 1); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 2; i <= n; ++i) { cin >> x; G[x].push_back(i); } for (int i = 1; i <= n; ++i) cin >> a[i]; dfs(1); for (int i = 1; i <= n; ++i) if (a[i]) upd(tin[i], tin[i]); cin >> m; while (m--) { cin >> s >> x; if (s == pow ) upd(tin[x], tout[x]); else cout << que(tin[x], tout[x]) << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int size; cin >> size; while (size--) { int nums; cin >> nums; while (nums--) cout << 1 << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int main() { cin >> n >> m; bool flg = false; int a; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> a; if (a == 1 && (i == 0 || i == n - 1 || j == 0 || j == m - 1)) flg = true; } if (flg) cout << 2 << endl; else cout << 4 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1E-9; int cnt; double a, b, m, vx, vy, vz, t, f; double ansx, ansz; int main() { scanf( %lf%lf%lf , &a, &b, &m); scanf( %lf%lf%lf , &vx, &vy, &vz); t = -m / vy; ansx = a / 2 + t * vx; ansz = t * vz; while (ansx < 0) ansx += a; while (ansz < 0) ansz += b; while (ansx + eps > a) ansx -= a; while (ansz + eps > b) ansz -= b; cnt = (int)(fabs(t / (b / vz)) + eps); if (cnt % 2) ansz = b - ansz; cnt = 0; if (t + eps > fabs((a / 2) / vx)) { cnt = 1; t -= fabs(a / 2 / vx); } cnt += (int)(fabs(t / (a / vx)) + eps); if (cnt % 2) ansx = a - ansx; printf( %.10lf %.10lf n , ansx, ansz); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using ll = long long; using ull = unsigned long long; using ld = long double; using namespace std; int n; void solve() { cin >> n; if (n % 2 == 0) { cout << NO ; return; } cout << YES n ; vector<int> v(2 * n + 1); for (int i = 1; i <= n; i++) { if (i % 2) { v[i] = 2 * i - 1; v[i + n] = 2 * i; } else { v[i] = 2 * i; v[i + n] = 2 * i - 1; } } for (int i = 1; i <= 2 * n; i++) cout << v[i] << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> #pragma GCC optimize( unroll-loops , omit-frame-pointer , inline ) #pragma GCC option( arch=native , tune=native , no-zero-upper ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) #pragma GCC optimize( Ofast ) using namespace std; const long double pi = acos(-1); const long long int M = 1e9 + 7, N = 1e7 + 5, INF = 1e18; void solve() { long long int x, y, z, a, b, c, f1, f2, f3, f4, f5, f6, s = 0; cin >> x >> y >> z >> a >> b >> c >> f1 >> f2 >> f3 >> f4 >> f5 >> f6; if (y < 0) s += f1; if (y > b) s += f2; if (z > c) s += f4; if (z < 0) s += f3; if (x > a) s += f6; if (x < 0) s += f5; cout << s << n ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int n; vector<long long int> BIT((int)1e6 + 5, 0); void _update(int x) { while (x <= n) { BIT[x]++; x += x & -x; } } int query(int x) { long long int sum = 0; while (x > 0) { sum += BIT[x]; x -= x & -x; } return sum; } int main() { long long int k; cin >> n >> k; long long int res = 1; k = min(n - k, k); int pos = 1; for (int i = 0; i < n; i++) { res++; int fi = pos + k; if (fi > n) { fi -= n; } if (fi > pos) { res += query(fi - 1) - query(pos); } else { res += query(fi - 1) + query(n) - query(pos); } _update(pos); _update(fi); pos = fi; cout << res << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int N = 2005; const int M = 730; int Head[M * 10], Next[M * 100], vet[M * 100]; int a[N], b[N], d[M * 10], vis[15], p[M][5], dis[M], Dis[M], P[10], len[M], U[M][12], D[M][12]; int n, cnt, edgenum; pair<int, int> c[M]; queue<int> q; inline int F(int x, int y) { return (x - 1) * cnt + y; } inline void addedge(int u, int v) { edgenum++; vet[edgenum] = v; Next[edgenum] = Head[u]; Head[u] = edgenum; } int main() { scanf( %d , &n); int ans = INF; for (int i = 1; i <= n; i++) scanf( %d%d , &a[i], &b[i]); len[cnt = 1] = 0; for (int i = 1; i <= 9; i++) { len[++cnt] = 1; p[cnt][1] = i; for (int j = i; j <= 9; j++) { len[++cnt] = 2; p[cnt][1] = i, p[cnt][2] = j; for (int k = j; k <= 9; k++) { len[++cnt] = 3; p[cnt][1] = i, p[cnt][2] = j, p[cnt][3] = k; for (int t = k; t <= 9; t++) len[++cnt] = 4, p[cnt][1] = i, p[cnt][2] = j, p[cnt][3] = k, p[cnt][4] = t; } } } for (int i = 2; i <= cnt; i++) { memset(vis, 0, sizeof(vis)); for (int j = 1; j <= len[i]; j++) vis[p[i][j]] = 1; for (int j = 1; j <= 9; j++) { if (!vis[j]) continue; int res = j, cur = 0; for (int k = 1; k <= len[i]; k++) if (p[i][k] == res) res = -1; else P[++cur] = p[i][k]; for (int k = 1; k <= cnt; k++) { if (len[k] != cur) continue; bool flag = 1; for (int t = 1; t <= cur; t++) flag &= (P[t] == p[k][t]); if (flag) { D[i][j] = k; U[k][j] = i; break; } } } } memset(dis, 0x3f, sizeof(dis)); dis[1] = a[1] - 1; for (int j = 1; j < 9; j++) for (int k = 1; k <= cnt; k++) addedge(F(j, k), F(j + 1, k)), addedge(F(j + 1, k), F(j, k)); for (int j = 1; j <= 9; j++) for (int k = 1; k <= cnt; k++) if (D[k][j]) addedge(F(j, k), F(j, D[k][j])); for (int i = 1; i <= n; i++) { memset(Dis, 0x3f, sizeof(Dis)); for (int j = 1; j <= cnt; j++) if (U[j][b[i]]) Dis[U[j][b[i]]] = min(Dis[U[j][b[i]]], dis[j] + 1); for (int j = 1; j <= cnt; j++) dis[j] = Dis[j]; memset(d, 0x3f, sizeof(d)); for (int j = 1; j <= cnt; j++) d[F(a[i], j)] = dis[j], c[j] = make_pair(dis[j], j); sort(c + 1, c + 1 + cnt); for (int j = 1; j <= cnt; j++) if (c[j].first != INF) q.push(F(a[i], c[j].second)); while (!q.empty()) { int u = q.front(); q.pop(); for (int e = Head[u]; e; e = Next[e]) { int v = vet[e]; if (d[v] > d[u] + 1) d[v] = d[u] + 1, q.push(v); } } if (i == n) for (int j = 1; j <= 9; j++) ans = min(ans, d[F(j, 1)]); else for (int j = 1; j <= cnt; j++) dis[j] = d[F(a[i + 1], j)]; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 48 + 10; vector<int> adj[MAX_N]; vector<int> ziro; bool mark[MAX_N]; int ans[MAX_N][3]; int poi = 0; vector<int> dfs(int v) { vector<int> ret; ret.push_back(v); mark[v] = 1; for (auto i : adj[v]) if (!mark[i]) { vector<int> vec = dfs(i); while (vec.size()) { ret.push_back(vec.back()); vec.pop_back(); } } return ret; } int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--, b--; adj[a].push_back(b); adj[b].push_back(a); } for (int i = 0; i < n; i++) if (adj[i].empty()) ziro.push_back(i); for (int i = 0; i < n; i++) if (!mark[i]) { vector<int> vec = dfs(i); if (vec.size() > 3) { cout << -1; return 0; } else if (vec.size() == 3) { for (int j = 0; j < 3; j++) ans[poi][j] = vec[j]; poi++; } else if (vec.size() == 2) { if (ziro.empty()) { cout << -1; return 0; } for (int j = 0; j < 2; j++) ans[poi][j] = vec[j]; ans[poi][2] = ziro.back(); ziro.pop_back(); poi++; } } if (ziro.size() % 3 != 0) { cout << -1; return 0; } while (ziro.size()) { for (int i = 0; i < 3; i++) { ans[poi][i] = ziro.back(); ziro.pop_back(); } poi++; } for (int i = 0; i < poi; i++) { for (int j = 0; j < 3; j++) cout << ans[i][j] + 1 << ; cout << n ; } } |
// megafunction wizard: %ALTFP_ABS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_ABS
// ============================================================
// File Name: acl_fp_fabs_double.v
// Megafunction Name(s):
// ALTFP_ABS
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_abs CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 10.0SP1 cbx_altfp_abs 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 63
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_fabs_double_altfp_abs_v4b
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [62:0] result_pipe;
wire aclr;
wire [63:0] data_w;
wire gnd_w;
// synopsys translate_off
initial
result_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_pipe <= 63'b0;
else if (clk_en == 1'b1) result_pipe <= data_w[62:0];
assign
aclr = 1'b0,
data_w = {gnd_w, data[62:0]},
gnd_w = 1'b0,
result = {data_w[63], result_pipe[62:0]};
endmodule //acl_fp_fabs_double_altfp_abs_v4b
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_fabs_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_fabs_double_altfp_abs_v4b acl_fp_fabs_double_altfp_abs_v4b_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_abs"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fabs_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fabs_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fabs_double.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fabs_double_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fabs_double_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fabs_double.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fabs_double.cmp TRUE TRUE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O2111AI_FUNCTIONAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_FUNCTIONAL_V |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asy_64_1.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asy_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 64,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_64_1_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; int start[200010], finish[200010], cnt, n, m, a[200010], dis[200010]; long long tree[2][8 * 200010]; vector<int> adj[200010], nodes[2], starts[2]; void update(int v, int vl, int vr, int l, int r, int val, int k) { int mid = (vl + vr) / 2; if (l <= vl && vr <= r) { tree[k][v] += val; return; } if (vr < l || r < vl) return; update(2 * v, vl, mid, l, r, val, k); update(2 * v + 1, mid + 1, vr, l, r, val, k); } long long getVal(int v, int vl, int vr, int idx, int k) { int mid = (vl + vr) / 2; if (vl == vr) return tree[k][v]; if (idx <= mid) return tree[k][v] + getVal(2 * v, vl, mid, idx, k); else return tree[k][v] + getVal(2 * v + 1, mid + 1, vr, idx, k); } void dfs(int v, int f, int d) { cnt++; start[v] = cnt; nodes[d % 2].push_back(v); starts[d % 2].push_back(start[v]); dis[v] = d % 2; for (__typeof(((int)((adj[v]).size())) - 1) i = (0); i <= (((int)((adj[v]).size())) - 1); i++) if (adj[v][i] != f) dfs(adj[v][i], v, d + 1); finish[v] = cnt; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (__typeof(n) i = (1); i <= (n); i++) cin >> a[i]; for (__typeof(n - 1) i = (1); i <= (n - 1); i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1, -1, 0); for (__typeof(n) i = (1); i <= (n); i++) { int k = dis[i]; int idx = lower_bound((starts[k]).begin(), (starts[k]).end(), start[i]) - starts[k].begin(); idx++; update(1, 1, n, idx, idx, a[i], k); } starts[0].push_back((1000 * 1000 * 1000)); starts[1].push_back((1000 * 1000 * 1000)); for (__typeof(m) i = (1); i <= (m); i++) { int q, x, v; cin >> q; if (q == 1) { cin >> x >> v; int k = dis[x]; int idx1 = lower_bound((starts[k]).begin(), (starts[k]).end(), start[x]) - starts[k].begin(); int idx2 = lower_bound((starts[k]).begin(), (starts[k]).end(), finish[x]) - starts[k].begin(); int idx3 = lower_bound((starts[1 - k]).begin(), (starts[1 - k]).end(), start[x]) - starts[1 - k].begin(); int idx4 = lower_bound((starts[1 - k]).begin(), (starts[1 - k]).end(), finish[x]) - starts[1 - k].begin(); if (idx2 >= ((int)((nodes[k]).size())) || finish[nodes[k][idx2]] != finish[x]) idx2--; if (idx4 >= ((int)((nodes[1 - k]).size())) || finish[nodes[1 - k][idx4]] != finish[x]) idx4--; idx1++; idx2++; idx3++; idx4++; if (idx1 <= idx2) update(1, 1, n, idx1, idx2, v, k); if (idx3 <= idx4) update(1, 1, n, idx3, idx4, -v, 1 - k); } else { cin >> x; int k = dis[x]; int idx = lower_bound((starts[k]).begin(), (starts[k]).end(), start[x]) - starts[k].begin(); idx++; cout << getVal(1, 1, n, idx, k) << endl; } } return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:16:42 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/clk_adc/clk_adc_stub.v
// Design : clk_adc
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_adc(clk_in1_p, clk_in1_n, clk_250Mhz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1_p,clk_in1_n,clk_250Mhz,locked" */;
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { if (a > b) return a; else return b; } long long min(long long a, long long b) { if (a < b) return a; else return b; } long long power(long long B, long long P) { if (P == 0) return 1; long long X = power(B, P / 2); if (P % 2 == 0) return X * X; else return B * X * X; } long long fx4[] = {1, -1, 0, 0}; long long fy4[] = {0, 0, 1, -1}; long long D[300005], C[300005]; int main() { long long T, N, M, X, Y, W, K, Q, R, P; cin >> N; for (int i = 1; i < N; i++) { cin >> X >> Y; D[X]++; D[Y]++; } for (int i = 1; i <= N; i++) { if (D[i] == 2) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; } |
// File : ../RTL/hostController/hctxportarbiter.v
// Generated : 11/10/06 05:37:22
// From : ../RTL/hostController/hctxportarbiter.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// hctxPortArbiter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//`include "timescale.v"
module HCTxPortArbiter (HCTxPortCntl, HCTxPortData, HCTxPortWEnable, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
input [7:0] SOFCntlCntl;
input [7:0] SOFCntlData;
input SOFCntlReq;
input SOFCntlWEn;
input clk;
input [7:0] directCntlCntl;
input [7:0] directCntlData;
input directCntlReq;
input directCntlWEn;
input rst;
input [7:0] sendPacketCntl;
input [7:0] sendPacketData;
input sendPacketReq;
input sendPacketWEn;
output [7:0] HCTxPortCntl;
output [7:0] HCTxPortData;
output HCTxPortWEnable;
output SOFCntlGnt;
output directCntlGnt;
output sendPacketGnt;
reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg [7:0] HCTxPortData, next_HCTxPortData;
reg HCTxPortWEnable, next_HCTxPortWEnable;
wire [7:0] SOFCntlCntl;
wire [7:0] SOFCntlData;
reg SOFCntlGnt, next_SOFCntlGnt;
wire SOFCntlReq;
wire SOFCntlWEn;
wire clk;
wire [7:0] directCntlCntl;
wire [7:0] directCntlData;
reg directCntlGnt, next_directCntlGnt;
wire directCntlReq;
wire directCntlWEn;
wire rst;
wire [7:0] sendPacketCntl;
wire [7:0] sendPacketData;
reg sendPacketGnt, next_sendPacketGnt;
wire sendPacketReq;
wire sendPacketWEn;
// Constants
`define DIRECT_CTRL_MUX 2'b10
`define SEND_PACKET_MUX 2'b00
`define SOF_CTRL_MUX 2'b01
// diagram signals declarations
reg [1:0]muxCntl, next_muxCntl;
// BINARY ENCODED state machine: HCTxArb
// State codes definitions:
`define START_HARB 3'b000
`define WAIT_REQ 3'b001
`define SEND_SOF 3'b010
`define SEND_PACKET 3'b011
`define DIRECT_CONTROL 3'b100
reg [2:0] CurrState_HCTxArb;
reg [2:0] NextState_HCTxArb;
// Diagram actions (continuous assignments allowed only: assign ...)
// SOFController/directContol/sendPacket mux
always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
directCntlWEn or directCntlData or directCntlCntl or
directCntlWEn or directCntlData or directCntlCntl or
sendPacketWEn or sendPacketData or sendPacketCntl)
begin
case (muxCntl)
`SOF_CTRL_MUX :
begin
HCTxPortWEnable <= SOFCntlWEn;
HCTxPortData <= SOFCntlData;
HCTxPortCntl <= SOFCntlCntl;
end
`DIRECT_CTRL_MUX :
begin
HCTxPortWEnable <= directCntlWEn;
HCTxPortData <= directCntlData;
HCTxPortCntl <= directCntlCntl;
end
`SEND_PACKET_MUX :
begin
HCTxPortWEnable <= sendPacketWEn;
HCTxPortData <= sendPacketData;
HCTxPortCntl <= sendPacketCntl;
end
default :
begin
HCTxPortWEnable <= 1'b0;
HCTxPortData <= 8'h00;
HCTxPortCntl <= 8'h00;
end
endcase
end
//--------------------------------------------------------------------
// Machine: HCTxArb
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or muxCntl or sendPacketGnt or directCntlGnt or CurrState_HCTxArb)
begin : HCTxArb_NextState
NextState_HCTxArb <= CurrState_HCTxArb;
// Set default values for outputs and signals
next_SOFCntlGnt <= SOFCntlGnt;
next_muxCntl <= muxCntl;
next_sendPacketGnt <= sendPacketGnt;
next_directCntlGnt <= directCntlGnt;
case (CurrState_HCTxArb)
`START_HARB:
NextState_HCTxArb <= `WAIT_REQ;
`WAIT_REQ:
if (SOFCntlReq == 1'b1)
begin
NextState_HCTxArb <= `SEND_SOF;
next_SOFCntlGnt <= 1'b1;
next_muxCntl <= `SOF_CTRL_MUX;
end
else if (sendPacketReq == 1'b1)
begin
NextState_HCTxArb <= `SEND_PACKET;
next_sendPacketGnt <= 1'b1;
next_muxCntl <= `SEND_PACKET_MUX;
end
else if (directCntlReq == 1'b1)
begin
NextState_HCTxArb <= `DIRECT_CONTROL;
next_directCntlGnt <= 1'b1;
next_muxCntl <= `DIRECT_CTRL_MUX;
end
`SEND_SOF:
if (SOFCntlReq == 1'b0)
begin
NextState_HCTxArb <= `WAIT_REQ;
next_SOFCntlGnt <= 1'b0;
end
`SEND_PACKET:
if (sendPacketReq == 1'b0)
begin
NextState_HCTxArb <= `WAIT_REQ;
next_sendPacketGnt <= 1'b0;
end
`DIRECT_CONTROL:
if (directCntlReq == 1'b0)
begin
NextState_HCTxArb <= `WAIT_REQ;
next_directCntlGnt <= 1'b0;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : HCTxArb_CurrentState
if (rst)
CurrState_HCTxArb <= `START_HARB;
else
CurrState_HCTxArb <= NextState_HCTxArb;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : HCTxArb_RegOutput
if (rst)
begin
muxCntl <= 2'b00;
SOFCntlGnt <= 1'b0;
sendPacketGnt <= 1'b0;
directCntlGnt <= 1'b0;
end
else
begin
muxCntl <= next_muxCntl;
SOFCntlGnt <= next_SOFCntlGnt;
sendPacketGnt <= next_sendPacketGnt;
directCntlGnt <= next_directCntlGnt;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int Maxn = 200 * 1000 + 10; int n, arr[Maxn], ind[Maxn], ans; int main() { cin >> n; for (int i = 0; i < n; i++) scanf( %d , &arr[i]); int a; for (int i = 0; i < n; i++) { scanf( %d , &a); ind[a] = i; } int prev = 0; for (int i = 0; i < n; i++) { if (ind[arr[i]] < prev) { cout << n - i << endl; return 0; } prev = ind[arr[i]]; } cout << 0 << endl; return 0; } |
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
// Sampling rates: 2kHz ~ 55.5 kHz. in 0.85Hz steps
module jt10_adpcm_dt(
input rst_n,
input clk, // CPU clock
input cen, // optional clock enable, if not needed leave as 1'b1
input [3:0] data,
input chon, // high if this channel is on
output signed [15:0] pcm
);
localparam stepw = 15;
reg signed [15:0] x1, x2, x3, x4, x5, x6;
reg [stepw-1:0] step1, step2, step6;
reg [stepw+1:0] step3, step4, step5;
assign pcm = x2;
reg [18:0] d2l;
reg [15:0] d3,d4;
reg [3:0] d2;
reg sign2, sign3, sign4, sign5;
reg [7:0] step_val;
reg [22:0] step2l;
always @(*) begin
casez( d2[3:1] )
3'b0_??: step_val = 8'd57;
3'b1_00: step_val = 8'd77;
3'b1_01: step_val = 8'd102;
3'b1_10: step_val = 8'd128;
3'b1_11: step_val = 8'd153;
endcase // data[2:0]
d2l = d2 * step2; // 4 + 15 = 19 bits -> div by 8 -> 16 bits
step2l = step_val * step2; // 15 bits + 8 bits = 23 bits -> div 64 -> 17 bits
end
// Original pipeline: 6 stages, 6 channels take 36 clock cycles
// 8 MHz -> /12 divider -> 666 kHz
// 666 kHz -> 18.5 kHz = 55.5/3 kHz
reg chon2, chon3, chon4, chon5;
reg signEqu4, signEqu5;
reg [3:0] data2;
always @( posedge clk or negedge rst_n )
if( ! rst_n ) begin
x1 <= 'd0; step1 <= 'd127;
x2 <= 'd0; step2 <= 'd127;
x3 <= 'd0; step3 <= 'd127;
x4 <= 'd0; step4 <= 'd127;
x5 <= 'd0; step5 <= 'd127;
x6 <= 'd0; step6 <= 'd127;
d2 <= 'd0; d3 <= 'd0; d4 <= 'd0;
sign2 <= 'b0;
sign3 <= 'b0;
sign4 <= 'b0; sign5 <= 'b0;
chon2 <= 'b0; chon3 <= 'b0; chon4 <= 'b0; chon5 <= 1'b0;
end else if(cen) begin
// I
d2 <= {data[2:0],1'b1};
sign2 <= data[3];
data2 <= data;
x2 <= x1;
step2 <= step1;
chon2 <= chon;
// II multiply and obtain the offset
d3 <= d2l[18:3]; // 16 bits
sign3 <= sign2;
x3 <= x2;
step3 <= step2l[22:6];
chon3 <= chon2;
// III 2's complement of d3 if necessary
d4 <= sign3 ? ~d3+16'b1 : d3;
sign4 <= sign3;
signEqu4 <= sign3 == x3[15];
x4 <= x3;
step4 <= step3;
chon4 <= chon3;
// IV Advance the waveform
x5 <= x4+d4;
sign5 <= sign4;
signEqu5 <= signEqu4;
step5 <= step4;
chon5 <= chon4;
// V: limit or reset outputs
if( chon5 ) begin
if( signEqu5 && (sign5!=x5[15]) )
x6 <= sign5 ? 16'h8000 : 16'h7FFF;
else
x6 <= x5;
if( step5 < 127 )
step6 <= 15'd127;
else if( step5 > 24576 )
step6 <= 15'd24576;
else
step6 <= step5[14:0];
end else begin
x6 <= 'd0;
step6 <= 'd127;
end
// VI: close the loop
x1 <= x6;
step1 <= step6;
end
endmodule // jt10_adpcm |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t, n, k; cin >> t; while (t--) { cin >> n >> k; if (k % 2) { if (n % 2) { n -= k - 1; if (n > 0) { cout << YES n ; for (int i = (0); i < (k - 1); ++i) { cout << 1 ; } cout << n << n ; } else { cout << NO n ; } } else { n -= (k - 1) * 2; if (n > 0) { cout << YES n ; for (int i = (0); i < (k - 1); ++i) { cout << 2 ; } cout << n << n ; } else { cout << NO n ; } } } else { if (n % 2) { cout << NO n ; } else { n -= (k - 1); if (n > 0) { cout << YES n ; for (int i = (0); i < (k - 1); ++i) { cout << 1 ; } cout << n << n ; } else { cout << NO n ; } } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_1_V
`define SKY130_FD_SC_LP__NAND2B_1_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_1 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_1 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; bool f[N][N]; int x[3005], y[3005]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> x[i] >> y[i]; f[x[i] + 1000][y[i] + 1000] = true; } int ans = 0; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if ((x[i] + x[j]) % 2 != 0 || (y[i] + y[j]) % 2 != 0) continue; int x_md = (x[i] + x[j]) / 2; int y_md = (y[i] + y[j]) / 2; if (f[x_md + 1000][y_md + 1000] == 1) ans++; } } cout << ans << endl; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 31808 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w496,
w497,
w31808;
assign w1 = i_data0;
assign w31 = w32 - w1;
assign w31808 = w497 << 6;
assign w32 = w1 << 5;
assign w496 = w31 << 4;
assign w497 = w1 + w496;
assign o_data0 = w31808;
//multiplier_block area estimate = 2757.58561077206;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: capture_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [4:0] rdusedw;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 5 0 OUTPUT NODEFVAL "rdusedw[4..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 5 0 @rdusedw 0 0 5 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_bb.v TRUE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 19:07:10
// Design Name:
// Module Name: can_qsampler
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module can_qsampler
(
input wire GCLK, // Main clock
input wire RES, // Reset module
inout wire CAN, // CAN bus inout
input wire din, // Bit to transmit
output reg dout, // Received bit
output reg cntmn, // Contamination detector
output reg cntmn_ready, // See if cntmn is valid
output reg sync // Timeslot start flag
);
parameter QUANTA = 20; // Level hold time
parameter SP = 15; // Sample point
reg din_latch = 1'b0; // Latch din at timeslot start
reg [63:0] qcnt = 64'd0; // Timeslot counter
// CAN Read with resync
reg can_sample;
always @(posedge GCLK) begin
can_sample <= CAN;
// Sample data
if (qcnt == SP) begin
dout <= CAN;
cntmn_ready <= 1'b1;
// Contamination flag:
if (din_latch != CAN) begin
cntmn <= 1'b1;
end
else begin
cntmn <= 1'b0;
end
end
else if (qcnt < SP) begin
cntmn_ready <= 1'b0;
end
// Reset circuit
else if (RES == 1'b1) begin
dout <= 1'b0;
cntmn <= 1'b0;
end
// Reset circuit
if (RES == 1'b1) begin
qcnt <= 64'd0;
sync <= 1'b0;
end
// Reset counter
else if (qcnt == QUANTA) begin
qcnt <= 64'd0;
sync <= 1'b1; // Hold for 1 tact
cntmn <= 1'b0;
cntmn_ready <= 1'b0;
end
// Resync circuit
else if ((qcnt > SP) & (can_sample != dout)) begin
qcnt <= 64'd0;
sync <= 1'b1; // Hold for 1 tact
cntmn <= 1'b0;
cntmn_ready <= 1'b0;
end
// Counter
else begin
qcnt <= qcnt + 64'd1;
sync <= 1'b0;
end
end
// CAN Write
assign CAN = (din_latch == 1'b0) ? 1'b0 : 1'bZ;
always @(negedge GCLK) begin
if (qcnt == 64'd0) begin
din_latch <= din; // CAN Write
end
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimization( unroll-loops ) std::pair<int, int> DR[] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}, {-1, 1}, {-1, -1}, {1, 1}, {1, -1}}; using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { ~debug() { cerr << endl; } template <class c> typename enable_if<sizeof dud<c>(0) != 1, debug&>::type operator<<(c i) { cerr << boolalpha << i; return *this; } template <class c> typename enable_if<sizeof dud<c>(0) == 1, debug&>::type operator<<(c i) { return *this << range(begin(i), end(i)); } template <class c, class b> debug& operator<<(pair<b, c> d) { return *this << ( << d.first << , << d.second << ) ; } template <class c> debug& operator<<(rge<c> d) { *this << [ ; for (auto it = d.b; it != d.e; ++it) *this << , + 2 * (it == d.b) << *it; return *this << ] ; } }; long long gcd(long long a, long long b) { if (b) return gcd(b, a % b); return a; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long n, m, a, b, g[3005 * 3005], val[3005][3005], mn[3005][3005], x, y, z, ans; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> n >> m >> a >> b; cin >> g[0] >> x >> y >> z; for (long long i = 1; i < n * m; i++) { g[i] = (g[i - 1] * x + y) % z; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { val[i][j] = g[i * m + j]; } } for (long long j = 0; j < m; j++) { deque<long long> dq; for (long long i = 0; i < a; i++) { while ((long long)((dq).size()) && val[dq.back()][j] >= val[i][j]) dq.pop_back(); dq.push_back(i); } mn[0][j] = val[dq.front()][j]; for (long long i = 1; i <= n - a; i++) { if (dq.front() == i - 1) dq.pop_front(); while ((long long)((dq).size()) && val[dq.back()][j] >= val[i + a - 1][j]) dq.pop_back(); dq.push_back(i + a - 1); mn[i][j] = val[dq.front()][j]; } } for (long long i = 0; i <= n - a; i++) { deque<long long> dq; for (long long j = 0; j < b; j++) { while ((long long)((dq).size()) && mn[i][dq.back()] >= mn[i][j]) dq.pop_back(); dq.push_back(j); } ans += mn[i][dq.front()]; for (long long j = 1; j <= m - b; j++) { if (dq.front() == j - 1) dq.pop_front(); while ((long long)((dq).size()) && mn[i][dq.back()] >= mn[i][j + b - 1]) dq.pop_back(); dq.push_back(j + b - 1); ans += mn[i][dq.front()]; } } return cout << ans, 0; return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// spiMasterSpmcBI.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// SpartanMC bus interface to spiMaster control and status regs ////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// - changed by Carsten Bruns, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "spiMaster_defines.v"
module spiMasterSpmcBI (
busClk,
rstFromWire,
dataIn,
dataOut,
address,
writeEn,
select,
spiSysClk,
spiTransType,
spiTransCtrl,
spiTransStatus,
spiDirectAccessTxData,
spiDirectAccessRxData,
rstSyncToBusClkOut,
rstSyncToSpiClkOut,
SDWriteError,
SDReadError,
SDInitError,
SDAddr,
spiClkDelay,
forceEmptyWrSyncToSpiClk,
forceEmptyRdSyncToSpiClk
);
parameter SDCARD_CLOCK = 16000000;
input [17:0] dataIn;
input [2:0] address;
input writeEn;
input select;
input busClk;
input spiSysClk;
output [17:0] dataOut;
output [1:0] spiTransType;
output spiTransCtrl;
input spiTransStatus;
output [7:0] spiDirectAccessTxData;
reg [7:0] spiDirectAccessTxData;
input [7:0] spiDirectAccessRxData;
input rstFromWire;
output rstSyncToBusClkOut;
output rstSyncToSpiClkOut;
input [1:0] SDWriteError;
input [1:0] SDReadError;
input [1:0] SDInitError;
output [31:0] SDAddr;
reg [31:0] SDAddr;
output [7:0] spiClkDelay;
reg [7:0] spiClkDelay;
output forceEmptyWrSyncToSpiClk;
output forceEmptyRdSyncToSpiClk;
wire [17:0] dataIn;
wire [2:0] address;
wire writeEn;
wire select;
wire clk;
reg [17:0] dataOut;
reg [1:0] spiTransType;
reg spiTransCtrl;
wire rstFromWire;
reg rstSyncToBusClkOut;
reg rstSyncToSpiClkOut;
//internal wire and regs
reg [5:0] rstShift;
reg rstFromBus;
reg [7:0] spiDirectAccessTxDataSTB;
reg [7:0] spiDirectAccessRxDataSTB;
reg [1:0] spiTransTypeSTB;
reg spiTransCtrlSTB;
reg spiTransStatusSTB;
reg rstSyncToSpiClkFirst;
reg [5:0] spiTransCtrlShift;
reg spiTransStatusReg1;
reg spiTransStatusReg2;
reg spiTransStatusReg3;
reg [1:0] SDWriteErrorSTB;
reg [1:0] SDReadErrorSTB;
reg [1:0] SDInitErrorSTB;
reg spiTransCtrl_reg1;
reg spiTransCtrl_reg2;
reg spiTransCtrl_reg3;
//fifo empty signals
reg forceEmptyWrReg;
reg forceEmptyWr;
reg forceEmptyWrToggle;
reg [2:0] forceEmptyWrToggleSyncToSpiClk;
reg forceEmptyRdReg;
reg forceEmptyRd;
reg forceEmptyRdToggle;
reg [2:0] forceEmptyRdToggleSyncToSpiClk;
//sync write demux
always @(posedge busClk)
begin
if (rstSyncToBusClkOut == 1'b1) begin
spiTransTypeSTB <= `DIRECT_ACCESS;
spiTransCtrlSTB <= `TRANS_STOP;
spiDirectAccessTxDataSTB <= 8'h00;
spiClkDelay <= `FAST_SPI_CLK;
end
else begin
if (writeEn == 1'b1 && select == 1'b1 && address == `SPI_MASTER_CONTROL_REG && dataIn[0] == 1'b1 )
rstFromBus <= 1'b1;
else
rstFromBus <= 1'b0;
if (writeEn == 1'b1 && select == 1'b1 && address == `TRANS_CTRL_REG && dataIn[0] == 1'b1 )
spiTransCtrlSTB <= 1'b1;
else
spiTransCtrlSTB <= 1'b0;
if (writeEn == 1'b1 && select == 1'b1 && address == `TRANS_CTRL_REG && dataIn[3] == 1'b1 )
forceEmptyWr <= 1'b1;
else
forceEmptyWr <= 1'b0;
if (writeEn == 1'b1 && select == 1'b1 && address == `TRANS_CTRL_REG && dataIn[4] == 1'b1 )
forceEmptyRd <= 1'b1;
else
forceEmptyRd <= 1'b0;
if (writeEn == 1'b1 && select == 1'b1) begin
case (address)
`TRANS_CTRL_REG: spiTransTypeSTB <= dataIn[2:1];
`SD_ADDR_17_0_REG: SDAddr[17:0] <= dataIn[17:0];
`SD_ADDR_31_18_REG: SDAddr[31:18] <= dataIn[13:0];
`SPI_CLK_DEL_REG: spiClkDelay <= dataIn;
`DIRECT_ACCESS_DATA_REG: spiDirectAccessTxDataSTB <= dataIn;
endcase
end
end
end
// async read mux
always @(address or spiTransTypeSTB or spiTransCtrlSTB or
spiTransStatusSTB or spiDirectAccessRxDataSTB or
SDAddr or SDInitErrorSTB or SDReadErrorSTB or SDWriteErrorSTB or
spiClkDelay)
begin
case (address)
`SPI_MASTER_VERSION_REG: dataOut <= `SPI_MASTER_VERSION_NUM;
`TRANS_CTRL_REG: dataOut <= { 14'b0000000, spiTransStatusSTB, spiTransTypeSTB[1:0],spiTransCtrlSTB};
`TRANS_ERROR_REG: dataOut <= {2'b00, SDWriteErrorSTB, SDReadErrorSTB, SDInitErrorSTB};
`SD_ADDR_17_0_REG: dataOut <= SDAddr[17:0];
`SD_ADDR_31_18_REG: dataOut <= {4'd0, SDAddr[31:18]};
`SPI_CLK_DEL_REG: dataOut <= spiClkDelay;
`DIRECT_ACCESS_DATA_REG: dataOut <= spiDirectAccessRxDataSTB;
default: dataOut <= 18'd0;
endcase
end
// reset control
//generate 'rstSyncToBusClk'
//assuming that 'busClk' < 5 * 'spiSysClk'.
always @(posedge busClk) begin
if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
rstShift <= 6'b111111;
else
rstShift <= {1'b0, rstShift[5:1]};
end
always @(rstShift)
rstSyncToBusClkOut <= rstShift[0];
// double sync across clock domains to generate 'rstSyncToSpiClkOut'
always @(posedge spiSysClk) begin
rstSyncToSpiClkFirst <= rstSyncToBusClkOut;
rstSyncToSpiClkOut <= rstSyncToSpiClkFirst;
end
// spi transaction control
//assuming that 'busClk' < 5 * 'spiSysClk'.
always @(posedge busClk) begin
if (rstSyncToBusClkOut == 1'b1)
spiTransCtrlShift <= 6'b000000;
else if (spiTransCtrlSTB == 1'b1)
spiTransCtrlShift <= 6'b111111;
else
spiTransCtrlShift <= {1'b0, spiTransCtrlShift[5:1]};
end
//re-sync to spiSysClk
always @(posedge spiSysClk) begin
if (rstSyncToSpiClkOut == 1'b1) begin
spiTransCtrl_reg1 <= 1'b0;
spiTransCtrl_reg2 <= 1'b0;
spiTransCtrl_reg3 <= 1'b0;
end
else begin
spiTransCtrl_reg1 <= spiTransCtrlShift[0];
spiTransCtrl_reg2 <= spiTransCtrl_reg1;
spiTransCtrl_reg3 <= spiTransCtrl_reg2;
if (spiTransCtrl_reg3 == 1'b0 && spiTransCtrl_reg2 == 1'b1)
spiTransCtrl <= `TRANS_START;
else
spiTransCtrl <= `TRANS_STOP;
end
end
//re-sync from busClk to spiSysClk.
always @(posedge spiSysClk) begin
if (rstSyncToSpiClkOut == 1'b1) begin
spiTransType <= `DIRECT_ACCESS;
spiDirectAccessTxData <= 8'h00;
end
else begin
spiDirectAccessTxData <= spiDirectAccessTxDataSTB;
spiTransType <= spiTransTypeSTB;
end
end
//re-sync from spiSysClk to busClk
always @(posedge busClk) begin
if (rstSyncToBusClkOut == 1'b1) begin
spiTransStatusSTB <= `TRANS_NOT_BUSY;
spiTransStatusReg1 <= `TRANS_NOT_BUSY;
spiTransStatusReg2 <= `TRANS_NOT_BUSY;
spiTransStatusReg3 <= `TRANS_NOT_BUSY;
end
else begin
spiTransStatusReg1 <= spiTransStatus;
spiTransStatusReg2 <= spiTransStatusReg1;
spiTransStatusReg3 <= spiTransStatusReg2;
if (spiTransCtrlSTB == `TRANS_START)
spiTransStatusSTB <= `TRANS_BUSY;
else if (spiTransStatusReg3 == `TRANS_BUSY && spiTransStatusReg2 == `TRANS_NOT_BUSY)
spiTransStatusSTB <= `TRANS_NOT_BUSY;
end
spiDirectAccessRxDataSTB <= spiDirectAccessRxData;
SDWriteErrorSTB <= SDWriteError;
SDReadErrorSTB <= SDReadError;
SDInitErrorSTB <= SDInitError;
end
//detect rising edge of 'forceEmptyWr', and generate toggle signal
always @(posedge busClk) begin
if (rstSyncToBusClkOut == 1'b1) begin
forceEmptyWrReg <= 1'b0;
forceEmptyWrToggle <= 1'b0;
end
else begin
if (forceEmptyWr == 1'b1)
forceEmptyWrReg <= 1'b1;
else
forceEmptyWrReg <= 1'b0;
if (forceEmptyWr == 1'b1 && forceEmptyWrReg == 1'b0)
forceEmptyWrToggle <= ~forceEmptyWrToggle;
end
end
// double sync across clock domains to generate 'forceEmptyWrSyncToSpiClk'
always @(posedge spiSysClk) begin
forceEmptyWrToggleSyncToSpiClk <= {forceEmptyWrToggleSyncToSpiClk[1:0], forceEmptyWrToggle};
end
assign forceEmptyWrSyncToSpiClk = forceEmptyWrToggleSyncToSpiClk[2] ^ forceEmptyWrToggleSyncToSpiClk[1];
//detect rising edge of 'forceEmpty', and generate toggle signal
always @(posedge busClk) begin
if (rstSyncToBusClkOut == 1'b1) begin
forceEmptyRdReg <= 1'b0;
forceEmptyRdToggle <= 1'b0;
end
else begin
if (forceEmptyRd == 1'b1)
forceEmptyRdReg <= 1'b1;
else
forceEmptyRdReg <= 1'b0;
if (forceEmptyRd == 1'b1 && forceEmptyRdReg == 1'b0)
forceEmptyRdToggle <= ~forceEmptyRdToggle;
end
end
// double sync across clock domains to generate 'forceEmptySyncToSpiClk'
always @(posedge spiSysClk) begin
forceEmptyRdToggleSyncToSpiClk <= {forceEmptyRdToggleSyncToSpiClk[1:0], forceEmptyRdToggle};
end
assign forceEmptyRdSyncToSpiClk = forceEmptyRdToggleSyncToSpiClk[2] ^ forceEmptyRdToggleSyncToSpiClk[1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_SYMBOL_V
`define SKY130_FD_SC_LP__A311O_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//-- ACC1 (Apollo CPU Core 1)
//-----------------------------------------------------------------------------
//-- (C) August 2016. Juan Gonzaelz-Gomez (Obijuan)
//-- Released under the GPL license
//-----------------------------------------------------------------------------
//-- ACC1 is the ACC0 with the following features:
//--
//-- * Control Unit that can execute the instructions: TCF and NOOP
//-- * It has 2 modes of execution: manual or automatic
//-- * In automatic mode the instructions are executed one after another
//-- without pressing any button
//-- * In manual mode, the instructions are execute one by one, by pressing
//-- the sw1 button
//-- * The Time in automtic mode can be configure by verilog parameters
//-- * The current mode is shown in the LED7 (1: manual, 0 automatic)
//-----------------------------------------------------------------------------
`default_nettype none
//------------------------------------------------------------
//-- TOP MODULE
//------------------------------------------------------------
module ACC1 (
input wire clk, //-- System clock
input wire next, //-- Process next instruction/data
input wire selmode, //-- Toggle Mode: Manual / automatic
output wire d0, //-- Output leds
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
//--------------------------------------------
//-- CONSTANTS
//--------------------------------------------
//-- Constants for the modes: automatic/manual
localparam MANUAL_MODE = 1'b1;
localparam AUTOMATIC_MODE = 1'b0;
//-- Constant for the speed of automatic mode (Number of bits for the timmer)
localparam SLOW = 24; //-- 1.4 secs
localparam MEDIUM = 22; //-- 350 ms
localparam FAST = 20; //-- 90 ms
//-- AGC Opcodes
localparam TCF = 3'b001; //-- Transfer Control Fixed. Unconditional jump
//-------------------------------------------------
//-- PARAMETERS & CONFIGURATION
//-------------------------------------------------
//-- Rom file
parameter ROMFILE = "rom.list";
//-- Parameters for the memory
localparam AW = 12; //-- Address bus
localparam DW = 16; //-- Data bus
//-- Initial address
localparam BOOT_ADDR = 12'h800;
//-- Initial G-reg value (shown in leds initially)
localparam G_INIT = 15'hAA00;
//-- Default mode configuration (Uncomment one of the options)
//localparam DEFAULT_MODE = AUTOMATIC_MODE;
localparam DEFAULT_MODE = MANUAL_MODE;
//-- Configuration for the timer of the automatic mode
//-- Uncomment one of the options
//localparam AUTOMATIC_MODE_SPEED = SLOW;
localparam AUTOMATIC_MODE_SPEED = MEDIUM;
//localparam AUTOMATIC_MODE_SPEED = FAST;
//----------------------------------------------------------
//-- ROM MEMORY
//----------------------------------------------------------
//-- ROM output data
wire [DW-1: 0] rom_dout;
//-- Instantiate the ROM memory (2K)
genrom #(
.ROMFILE(ROMFILE),
.AW(AW-1),
.DW(DW))
ROM (
.clk(clk),
.cs(S[AW-1]), //-- Bit A11 for the chip select
.addr(S[AW-2:0]), //-- Bits A10 - A0 for addressing the Rom (2K)
.data_out(rom_dout)
);
//-----------------------------------------------------------
//-- INPUT BUTTONS CONFIGURATION
//-----------------------------------------------------------
//-- Configure the pull-up resistors for clk and rst inputs
wire next_p; //-- Next input with pull-up activated
wire selmode_p; //-- Selmode button with pull-up activated
wire sw1;
wire sw2;
//-- Button 1 pull-up
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(next),
.D_IN_0(next_p)
);
//-- Button 2 pull-up
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(selmode),
.D_IN_0(selmode_p)
);
//-- Buttons with positive logic: (1 pressed, 0 not presssed)
assign sw1 = ~next_p;
assign sw2 = ~selmode_p;
//-- switch button debounced
wire sw1_deb;
wire sw2_deb;
//-- Debouncer for button 1
debounce_pulse deb1 (
.clk(clk),
.sw_in(sw1),
.sw_out(sw1_deb)
);
//-- Debouncer for button 2
debounce_pulse deb2 (
.clk(clk),
.sw_in(sw2),
.sw_out(sw2_deb)
);
//-- This debouncer is used with the timer for generating a 1-cycle width pulse
//-- Not for debouncing
debounce_pulse deb3 (
.clk(clk),
.sw_in(timer_trig),
.sw_out(timer_trig_pulse)
);
//------------------------------------
//-- S REGISTER: Addressing memory
//------------------------------------
//-- Define de S-reg
reg [AW-1: 0] S = BOOT_ADDR;
//-- Register with paralell load (WS) and increment (INCS)
always @(posedge clk) begin
if (WS)
S <= dir12;
else
if (INCS)
S <= S + 1;
end
//---------------------------------------------------------
//-- G REGISTER: Store Instruction/data read from memory
//---------------------------------------------------------
//-- Define de G-reg
reg [14:0] G = G_INIT;
//-- G has different fields
wire [2:0] opcode = G[14:12]; //-- Opcode: 3 bits
wire [11:0] dir12 = G[11:0]; //-- Dir12: 12 bits
//-- Register with parallel load (WG)
always @(posedge clk)
if (WG)
G <= rom_dout[14:0];
//-----------------------------------------
//-- LEDS
//-----------------------------------------
//-- The 7 more significant bits of G regs are shown in leds
assign {d6,d5,d4,d3,d2,d1,d0} = G[14:8];
//-- The LED7 is for displaying the mode (automatic/manual)
assign d7 = mode;
//------------------------------------------
//-- Timer for the automatic mode
//------------------------------------------
wire timer_trig;
wire timer_trig_pulse;
prescaler #(
.N(AUTOMATIC_MODE_SPEED)
) timer_automatic (
.clk_in(clk),
.ena(1'b1),
.clk_out(timer_trig)
);
//-------------------------------------------------
//-- Flip-flip T for toggling the mode
//-------------------------------------------------
reg mode = DEFAULT_MODE;
//-- Flip-flip T. The input is the button 2
always @(posedge clk) begin
//-- Change the mode when the SW2 is pressed
if (sw2_deb)
mode = ~mode;
end
//-- Mux for choosing manual/automatic event signal
wire event_trig = (mode == MANUAL_MODE) ? sw1_deb : timer_trig_pulse;
//---------------------------------------------------
//-- CONTROL UNIT
//---------------------------------------------------
//-- fsm states
localparam FETCH = 0;
localparam READ_OP = 1;
localparam EXEC0 = 2;
localparam WAIT = 3;
//-- Registers for storing the states
reg [1:0] state = WAIT;
reg [1:0] next_state;
//---------------- Control signals
reg WG = 0; //-- Load the G register
reg INCS = 0; //-- Increment the S register
reg WS = 0; //-- Load the S register
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
WG = 0;
INCS = 0;
WS = 0;
case (state)
FETCH: begin
next_state = READ_OP;
end
READ_OP: begin
WG = 1; //-- Read the opcode into the G register
INCS = 1; //-- Increment the S reg
next_state = EXEC0;
end
EXEC0: begin
//-- If opcode is TCF, load the register S
if (opcode == TCF)
WS = 1;
next_state = WAIT;
end
WAIT: begin
//-- Wait until an event is trigger (timer or sw1 pressed)
if (event_trig)
next_state = FETCH;
end
default: begin
end
endcase
end
endmodule
//-----------------------------------------------------------------
//-- OTHER MODULES
//-----------------------------------------------------------------
// -- Generic ROM
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list") //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1: 0] addr, //-- Address bus
output reg [DW-1: 0] data_out); //-- Data bus
//-- Total position of the address
localparam NPOS = 2 ** AW;
//-- Memory
reg [DW-1: 0] rom [0: NPOS-1];
always @(negedge clk) begin
if (cs)
data_out <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
module debounce_pulse(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in==0)
next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debouncer_pulse
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
#include <bits/stdc++.h> using namespace std; class Solution { public: void solve(std::istream& in, std::ostream& out) { string s; in >> s; int n = s.size(); for (size_t i = 0; i < n; i++) { int x = (s[i] - 0 ); if (x % 8 == 0) { out << YES << n << x; return; } } for (size_t i = 0; i < n; i++) { for (size_t j = i + 1; j < n; j++) { int x = 10 * (s[i] - 0 ) + (s[j] - 0 ); if (x % 8 == 0) { out << YES << n << x; return; } } } for (size_t i = 0; i < n; i++) { for (size_t j = i + 1; j < n; j++) { for (size_t k = j + 1; k < n; k++) { int x = 100 * (s[i] - 0 ) + 10 * (s[j] - 0 ) + (s[k] - 0 ); if (x % 8 == 0) { out << YES << n << x; return; } } } } out << NO ; } }; void solve(std::istream& in, std::ostream& out) { out << std::setprecision(12); Solution solution; solution.solve(in, out); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); istream& in = cin; ostream& out = cout; solve(in, out); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:33554432 ) using namespace std; const double PI = 2 * acos(0.0); const double EPS = 1e-8; const int INF = (1 << 30) - 1; int n; string s; vector<int> p; set<int> ans; void add01(char c1, char c2, int a, int b) { for (int i = 0; i < a; ++i) s[p[i]] = c1; for (int i = 0; i < b; ++i) s[p[a + i]] = c2; } int getans() { int i = n - 1; while (s[i] != 0 ) --i; int j = n - 1; while (s[j] != 1 ) --j; if (i < j) return 1; else return 2; } void printbin(int n) { cout << n / 2 << n % 2 << endl; } int main() { cin >> s; if ((int)((s).size()) % 2 == 1) s = 0 + s; n = (int)((s).size()); int cnt = 0, cnt1 = 0, cnt0 = 0; for (int i = 0; i < n; ++i) if (s[i] == ? ) { ++cnt; p.push_back(i); } else if (s[i] == 1 ) ++cnt1; else if (s[i] == 0 ) ++cnt0; if (cnt0 >= cnt1 + cnt + 2) { cout << 00 ; return 0; } if (cnt1 >= cnt0 + cnt + 2) { cout << 11 ; return 0; } if (cnt0 + cnt >= cnt1 + 2) ans.insert(0); if (cnt1 + cnt >= cnt0 + 2) ans.insert(3); add01( 0 , 1 , n / 2 - cnt0, n / 2 - cnt1); ans.insert(getans()); add01( 1 , 0 , n / 2 - cnt1, n / 2 - cnt0); ans.insert(getans()); for (set<int>::iterator i = ans.begin(); i != ans.end(); ++i) printbin(*i); return 0; }; |
#include <bits/stdc++.h> using namespace std; int setBit(int n, int pos) { return n | (1 << pos); } int resetBit(int n, int pos) { return n & ~(1 << pos); } bool checkBit(int n, int pos) { return n & (1 << pos); } inline long long bigmod(long long p, long long e, long long M) { long long ret = 1; while (e > 0) { if (e % 2) ret = (ret * p) % M; p = (p * p) % M; e /= 2; } return ret; } inline long long power(long long x, long long y) { long long ans = 1; while (y > 0) { if (y % 2) ans *= x; x *= x; y /= 2; } return ans; } template <class T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> T lcm(T a, T b) { return a * (b / gcd(a, b)); } int n, k, a, b, c, d; int vis[1003]; int main() { cin >> n >> k >> a >> b >> c >> d; if (k < n + 1 || n == 4) { cout << -1; return 0; } vis[a] = vis[b] = vis[c] = vis[d] = 1; printf( %d %d , a, c); for (int i = 1; i <= n; i++) { if (vis[i] == 0) { printf( %d , i); } } printf( %d %d n , d, b); printf( %d %d , c, a); for (int i = 1; i <= n; i++) { if (vis[i] == 0) { printf( %d , i); } } printf( %d %d , b, d); } |
#include <bits/stdc++.h> using namespace std; long long ans = -((long long)1 << 62); int n, u, r; int a[105]; int b[105]; int k[105]; int p[105]; void process(int m, int op) { if (((u - m) & 1) == 0) { long long an = 0; for (int i = 1; i <= n; i++) an += a[i] * k[i]; ans = max(an, ans); } if (m == u) { return; } if (op == 0) { for (int i = 1; i <= n; i++) a[i] ^= b[i]; process(m + 1, 1); for (int i = 1; i <= n; i++) a[i] ^= b[i]; } vector<int> a1; a1.push_back(1); for (int i = 1; i <= n; i++) a1.push_back(a[i]); for (int i = 1; i <= n; i++) a[i] = a1[p[i]] + r; process(m + 1, 0); for (int i = 1; i <= n; i++) a[i] = a1[i]; } int main() { scanf( %d %d %d , &n, &u, &r); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); for (int i = 1; i <= n; i++) scanf( %d , &k[i]); for (int i = 1; i <= n; i++) scanf( %d , &p[i]); process(0, 0); printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int p, q, l, r; cin >> p >> q >> l >> r; vector<pair<int, int> > z_timing, x_timing; int start, stop; for (int i = 0; i < p; i++) { cin >> start >> stop; z_timing.push_back(make_pair(start, stop)); } for (int i = 0; i < q; i++) { cin >> start >> stop; x_timing.push_back(make_pair(start, stop)); } int answer = 0; for (int i = l; i <= r; i++) { for (int j = 0; j < q; j++) { bool has_intersected = false; start = x_timing[j].first + i; stop = x_timing[j].second + i; for (int k = 0; k < p; k++) { if (start <= z_timing[k].second && stop >= z_timing[k].first) { answer++; has_intersected = true; break; } } if (has_intersected == true) { break; } } } cout << answer; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; constexpr int N = 2e5 + 5; int t, a, b, p; string s; void Solve() { cin >> t; while (t--) { cin >> a >> b >> p >> s; s.pop_back(); vector<ll> suf; suf.resize(s.size()); char last = 0 ; for (int i = s.size() - 1; i >= 0; i--) { if (s[i] != last) suf[i] = (s[i] == A ? a : b); last = s[i]; } for (int i = suf.size() - 2; i >= 0; i--) suf[i] += suf[i + 1]; int id = 0; while (id < suf.size() && suf[id] > p) id++; cout << id + 1 << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); Solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A311OI_FUNCTIONAL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_FUNCTIONAL_V |
`timescale 1ns/10ps
module VGA2Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire vga_hsync;
wire vga_vsync;
wire vga_r;
wire vga_g;
wire vga_b;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#100000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`VGA2_LDR,8'h00};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h20};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1100};
inst_en = 1;
#4 inst = {`VGA2_LDI,4'bxxxx,4'b1010};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1010};
inst_en = 0;
#4 inst = {`VGA2_LDR,8'h04};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,16'hBEEF};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h3F};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#8 inst = {`VGA2_LDR,8'h00};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h20};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1100};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test writing to another row.
#8 inst = {`VGA2_LDR,8'h01};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h04};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1010};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test writing a less-intense value.
#8 inst = {`VGA2_LDR,8'h00};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h40};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b0110};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
end // initial begin
VGA2
vga (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // VGA2Sim
|
#include <bits/stdc++.h> using namespace std; int head[(1000 + 10)], to[(1000 + 10) * (1000 + 10)], pre[(1000 + 10) * (1000 + 10)], tot; bool vis[(1000 + 10)], color[(1000 + 10)]; int tag[(1000 + 10)], cc, L[(1000 + 10)], dis[(1000 + 10)]; int n, m; void adde(int u, int v) { to[++tot] = v, pre[tot] = head[u], head[u] = tot; } void dfs(int u) { tag[u] = cc; for (int i = head[u]; i; i = pre[i]) { int v = to[i]; if (vis[v]) { if (color[u] == color[v]) { printf( -1 ); exit(0); } else continue; } vis[v] = 1, color[v] = 1 ^ color[u]; dfs(v); } } void bfs(int u) { memset(dis, 0xff, sizeof(dis)); dis[u] = 0; int& res = L[tag[u]]; queue<int> Q; Q.push(u); while (!Q.empty()) { int v = Q.front(); Q.pop(); for (int i = head[v]; i; i = pre[i]) { int vv = to[i]; if (dis[vv] != -1) continue; dis[vv] = dis[v] + 1; Q.push(vv); res = max(res, dis[vv]); } } } int main() { scanf( %d %d , &n, &m); while (m--) { int u, v; scanf( %d %d , &u, &v); adde(u, v), adde(v, u); } for (int i = 1; i <= n; i++) { if (!vis[i]) { vis[i] = 1; cc++; dfs(i); } } for (int i = 1; i <= n; i++) bfs(i); int ans = 0; for (int i = 1; i <= cc; i++) ans += L[i]; printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { int n, m, k; cin >> n >> m >> k; vector<int> p(n); for (int i = 0; i < n; ++i) cin >> p[i]; vector<int> s(n); for (int i = 0; i < n; ++i) cin >> s[i]; vector<int> c(k); for (int i = 0; i < k; ++i) cin >> c[i]; vector<vector<int>> schools(m + 1, vector<int>()); for (int i = 0; i < n; ++i) { schools[s[i]].push_back(p[i]); } int ans = 0; for (int i = 0; i < k; ++i) { int cur = c[i]; int school = s[cur - 1]; int power = p[cur - 1]; vector<int> ss = schools[school]; sort(ss.rbegin(), ss.rend()); if (ss[0] != power) ans++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 * 100; int n; pair<int, int> sora[maxn + 100]; int lpos = 0; bool seen[maxn + 100]; bool comp(pair<int, int> a, pair<int, int> b) { if (a.first < b.first) return true; else { if (a.first == b.first) return a.second < b.second; else return false; } } int main() { cin >> n; for (int i = 0; i < n; i++) { int temp; scanf( %d , &temp); sora[i] = make_pair(temp, i); } sort(sora, sora + n, comp); int co = 0; for (int i = 0; i < n; i++) { seen[sora[i].second] = true; while (lpos < n && seen[lpos]) lpos++; if (lpos > i || lpos == n) { co++; } } cout << co << endl; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_sstl_dq_bscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_sstl_dq_bscan(update_dr ,data_out ,out_type ,serial_out ,
bso ,odt_enable ,oe ,clk ,shift_dr ,bypass_in ,serial_in ,
bypass_enable ,data_in ,ps_select ,rcv_in ,drv_oe ,odt_enable_mask
,se ,test_mode ,to_core ,hiz_l ,clock_dr ,bsi ,mode_ctrl );
output data_out ;
output serial_out ;
output bso ;
output odt_enable ;
output oe ;
output to_core ;
input update_dr ;
input out_type ;
input clk ;
input shift_dr ;
input bypass_in ;
input serial_in ;
input bypass_enable ;
input data_in ;
input ps_select ;
input rcv_in ;
input drv_oe ;
input odt_enable_mask ;
input se ;
input test_mode ;
input hiz_l ;
input clock_dr ;
input bsi ;
input mode_ctrl ;
wire test_mode_oe ;
wire bso_1 ;
wire bso_2 ;
wire bso_3 ;
wire odt_enable_in ;
wire net138 ;
wire net144 ;
bw_io_jp_sstl_bscan bscan_input (
.in (rcv_in ),
.update_dr (update_dr ),
.mode_ctl (mode_ctrl ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.bsr_so (bso_1 ),
.out (to_core ),
.bsr_si (bsi ) );
bw_io_jp_sstl_oebscan bscan_oe (
.bsr_si (bso_3 ),
.update_dr (update_dr ),
.in (drv_oe ),
.bsr_hiz_l (hiz_l ),
.test_mode_oe (test_mode_oe ),
.mode_ctl (mode_ctrl ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.out_type (out_type ),
.bsr_so (bso ),
.out (oe ) );
bw_io_dq_pscan pscan (
.serial_in (serial_in ),
.serial_out (serial_out ),
.bypass_in (bypass_in ),
.out_type (out_type ),
.clk (clk ),
.bypass (net138 ),
.ps_select (ps_select ),
.rcv_in (rcv_in ) );
bw_u1_nor2_1x odt_nor2 (
.z (odt_enable_in ),
.a (drv_oe ),
.b (odt_enable_mask ) );
bw_io_jp_sstl_dq_bscan bscan_output (
.se (se ),
.mode_ctl (mode_ctrl ),
.bypass_enable (bypass_enable ),
.clock_dr (clock_dr ),
.in (data_in ),
.ps_in (serial_out ),
.bsr_so (bso_3 ),
.ps_select (ps_select ),
.out (data_out ),
.bypass (net138 ),
.shift_dr (shift_dr ),
.bsr_si (bso_2 ),
.update_dr (update_dr ) );
bw_u1_inv_0p6x I46 (
.z (test_mode_oe ),
.a (net144 ) );
bw_io_jp_sstl_odt_oebscan bscan_odt_en (
.test_mode_oe (test_mode_oe ),
.bsr_hiz_l (hiz_l ),
.in (odt_enable_in ),
.update_dr (update_dr ),
.mode_ctl (mode_ctrl ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.bsr_so (bso_2 ),
.out (odt_enable ),
.bsr_si (bso_1 ) );
bw_u1_muxi21_0p6x I47 (
.z (net144 ),
.d0 (test_mode ),
.d1 (se ),
.s (ps_select ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 605; int nask(vector<int> tmp) { if (!tmp.size() || tmp.size() == 1) return 0; cout << ? << tmp.size() << endl; for (int i = (0), iend = ((int)tmp.size() - 1); i <= iend; i++) cout << tmp[i] << ; cout << endl; cout.flush(); int ans; cin >> ans; if (ans == -1) exit(0); return ans; } int dask(int u, vector<int> tar) { int cntsig = nask(tar); tar.push_back(u); int cnttot = nask(tar); return cnttot - cntsig; } int n; bool vis[maxn]; int bl[maxn]; int find(int u, vector<int> tmp) { vector<int> c1, c2; if (tmp.size() == 1) return tmp[0]; for (int i = (0), iend = ((int)(tmp.size()) - 1); i <= iend; i++) { if (c1.size() < tmp.size() / 2) c1.push_back(tmp[i]); else c2.push_back(tmp[i]); } if (dask(u, c1)) return find(u, c1); else return find(u, c2); } vector<int> half[2]; vector<int> side[maxn]; void dfs(int u) { half[bl[u]].push_back(u); while (1) { vector<int> tmp; for (int i = (1), iend = (n); i <= iend; i++) if (!vis[i]) tmp.push_back(i); if (dask(u, tmp) == 0) return; int tar = find(u, tmp); side[u].push_back(tar); side[tar].push_back(u); vis[tar] = 1; bl[tar] = bl[u] ^ 1; dfs(tar); } } int stk[maxn], top; vector<int> ans; void cfs(int u, int tar) { stk[++top] = u; if (u == tar) { for (int i = (1), iend = (top); i <= iend; i++) ans.push_back(stk[i]); return; } for (int i = (0), iend = (side[u].size() - 1); i <= iend; i++) { int v = side[u][i]; if (!vis[v]) { vis[v] = 1; cfs(v, tar); } } top--; } void ans_out(int u, int v) { memset(vis, 0, sizeof(vis)); vis[u] = 1; cfs(u, v); cout << N << ans.size() << endl; for (int i = (0), iend = ((int)(ans.size()) - 1); i <= iend; i++) cout << ans[i] << ; return; } int main() { ios::sync_with_stdio(0); cin >> n; vis[1] = 1; dfs(1); if (!nask(half[0]) && !nask(half[1])) { cout << Y << half[0].size() << endl; for (int i = (0), iend = ((int)(half[0].size()) - 1); i <= iend; i++) cout << half[0][i] << ; return 0; } else { for (int i = (0), iend = (1); i <= iend; i++) for (int j = (0), jend = ((int)(half[i].size()) - 1); j <= jend; j++) { vector<int> tmp; int u = half[i][j]; for (int k = (0), kend = ((int)(half[i].size()) - 1); k <= kend; k++) if (half[i][k] != u) tmp.push_back(half[i][k]); if (dask(u, tmp)) { for (int k = (0), kend = ((int)(tmp.size()) - 1); k <= kend; k++) { vector<int> gg; gg.push_back(u); gg.push_back(tmp[k]); if (nask(gg)) { ans_out(u, tmp[k]); return 0; } } } } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string fld; cin >> fld; int l = 1, r = 2 * n; int ans = -1; while (l <= r) { int mid = (l + r) >> 1; int posbl = 1; int back = -1, flag = 0; for (int i = 0; i < n; i++) { if (fld[i] == * ) if (i > back && flag == 0) back = i, flag = 1; if (fld[i] == P ) { if (back == -1) { back = i + mid; } else { if (i <= back) { back = max(back, i + mid); } else { if (flag == 1) { if (i - back > mid) { posbl = 0; break; } else if (i - back <= mid && mid <= (2 * (i - back))) back = max(i, (mid - (i - back)) / 2 + i); else { back = max(mid - (2 * (i - back)) + i, (mid - (i - back)) / 2 + i); } } else { back = i + mid; } } } flag = 0; } } if (flag == 1) posbl = 0; if (posbl == 1) { r = mid - 1; ans = mid; } else l = mid + 1; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MX = 100000 + 10; long long n, arr[MX]; struct node { long long bit_[3]; node() { memset(bit_, 0, sizeof(bit_)); } }; vector<node> tree; void add(long long inode, long long ptr, long long num) { if (ptr < 0) return; long long q = (num >> ptr) & 1; if (tree[inode].bit_[q] == 0) { tree.push_back(node()); tree[inode].bit_[q] = (int)tree.size() - 1; } add(tree[inode].bit_[q], ptr - 1, num); } long long find_fit(long long x) { int ptr = 45; long long nd = 0; long long sol = 0; while (ptr >= 0) { sol *= 2; long long q = !((x >> ptr) & 1); if (q == 1) { if (tree[nd].bit_[1] != 0) { nd = tree[nd].bit_[1]; sol++; } else nd = tree[nd].bit_[0]; } else { if (tree[nd].bit_[0] != 0) nd = tree[nd].bit_[0]; else { nd = tree[nd].bit_[1]; sol++; } } ptr--; } return sol; } int main() { tree.push_back(node()); cin >> n; long long q = 0; add(0, 45, 0); for (int i = 0; i < n; i++) { cin >> arr[i]; q ^= arr[i]; add(0, 45, q); } q = 0; long long ans = 0; for (int i = n - 1; i >= 0; i--) { q ^= arr[i]; long long p = find_fit(q); ans = max(ans, p ^ q); } cout << ans << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runcount; initial runcount = 0;
reg [31:0] clkrun; initial clkrun = 0;
reg [31:0] clkcount; initial clkcount = 0;
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
reg run0;
always @ (/*AS*/runnerm1) begin
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
$write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
always @ (posedge run0) begin
// Do something that forces another combo run
clkcount <= clkcount + 1;
runner[8:4] <= runner[8:4] - 1;
runner[3:0] <= 3;
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
$write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
runner <= 0;
end
8'd01: begin
runner <= 32'h35;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (runcount!=32'he) $stop;
if (clkcount!=32'h3) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 123456789; const long long inf = 123456789000000000; const double EPS = 1e-10; const double PI = 2 * asin(1.0); const long long mod = 1e9 + 7; inline int cmp(double x, double y = 0, double tol = EPS) { return (x <= y + tol) ? (x + tol < y) ? -1 : 0 : 1; } int main() { string s; cin >> s; long long par, impar, ap, ai, bp, bi; par = impar = ap = ai = bp = bi = 0LL; for (int i = 0; i < ((int)s.size()); ++i) { impar++; if (i % 2 == 0) { if (s[i] == a ) { par += ai; impar += ap; ap++; } else { par += bi; impar += bp; bp++; } } else { if (s[i] == a ) { par += ap; impar += ai; ai++; } else { par += bp; impar += bi; bi++; } } } cout << par << << impar << endl; } |
module wb_bfm_memory
#(//Wishbone parameters
parameter dw = 32,
parameter aw = 32,
parameter DEBUG = 0,
// Memory parameters
parameter memory_file = "",
parameter mem_size_bytes = 32'h0000_8000, // 32KBytes
parameter rd_min_delay = 0,
parameter rd_max_delay = 4)
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [dw-1:0] wb_dat_o);
`include "wb_bfm_params.v"
localparam bytes_per_dw = (dw/8);
localparam mem_words = (mem_size_bytes/bytes_per_dw);
//Counters for read and write accesses
integer reads = 0;
integer writes = 0;
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
wb_bfm_slave
#(.aw (aw))
bfm0
(.wb_clk (wb_clk_i),
.wb_rst (wb_rst_i),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_cti_i (wb_cti_i),
.wb_bte_i (wb_bte_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.wb_rty_o (wb_rty_o));
reg [aw-1:0] address;
reg [dw-1:0] data;
integer i;
integer delay;
integer seed;
always begin
bfm0.init();
address = bfm0.address; //Fetch start address
if(bfm0.op === WRITE)
writes = writes + 1;
else
reads = reads + 1;
while(bfm0.has_next) begin
//Set error on out of range accesses
if(address[31:2] > mem_words) begin
$display("%0d : Error : Attempt to access %x, which is outside of memory", $time, address);
bfm0.error_response();
end else begin
if(bfm0.op === WRITE) begin
bfm0.write_ack(data);
if(DEBUG) $display("%d : ram Write 0x%h = 0x%h %b", $time, address, data, bfm0.mask);
for(i=0;i < 4; i=i+1)
if(bfm0.mask[i])
mem[address[31:2]][i*8+:8] = data[i*8+:8];
end else begin
data = {aw{1'b0}};
for(i=0;i < 4; i=i+1)
if(bfm0.mask[i])
data[i*8+:8] = mem[address[31:2]][i*8+:8];
if(DEBUG) $display("%d : ram Read 0x%h = 0x%h %b", $time, address, data, bfm0.mask);
delay = $dist_uniform(seed, rd_min_delay, rd_max_delay);
repeat(delay) @(posedge wb_clk_i);
bfm0.read_ack(data);
end
end
if(bfm0.cycle_type === BURST_CYCLE)
address = bfm0.next_addr(address, bfm0.burst_type);
end
end
endmodule // wb_bfm_memory
|
#include <bits/stdc++.h> using namespace std; int main() { long long h, n; cin >> h >> n; long long l = 1, r = (1LL << h), ret = 0, cur = 0, dir = 0; while (cur < h) { long long size = (1LL << (h - cur)), mid = (l + r) / 2; if (dir == 0) { if (n <= mid) ++ret, r = mid, dir = 1; else ret += size, l = mid + 1; } else { if (n <= mid) ret += size, r = mid; else ++ret, l = mid + 1, dir = 0; } ++cur; } cout << ret << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; long long ans = 0; for (int i = 30; i >= 0; i--) { vector<int> v1; int cnt1 = 0, cnt2 = 0; for (int x : v) { if (x & (1 << i)) { cnt1++; } else { cnt2++; v1.push_back(x); } } ans += (1LL * cnt1 * (cnt1 - 1)); int len = v.size(); while (len--) v.pop_back(); for (int x : v1) v.push_back(x); } cout << ans / 2 << n ; ; } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) const int maxn = 2e5 + 5; struct node { int idx, p; bool operator<(const node &b) const { return p < b.p; } } ver[100005], hor[100005]; int vcnt, hcnt; vector<node> V1[maxn], V2[maxn]; int tempx[100005], tempy[100005]; int ansx[100005], ansy[100005]; int main() { int n, w, h; cin >> n >> w >> h; int g, p, t; for (int i = 1; i <= n; i++) { scanf( %d , &g); if (g == 1) { vcnt++; scanf( %d%d , &p, &t); V1[p - t + 100000].push_back({i, p}); } else { hcnt++; scanf( %d%d , &p, &t); V2[p - t + 100000].push_back({i, p}); } } for (int i = 0; i < maxn; i++) { sort(V1[i].begin(), V1[i].end()); sort(V2[i].begin(), V2[i].end()); } for (int i = 0; i < maxn; i++) { int cnt = 0; for (int j = 0; j < V1[i].size(); j++) { tempx[cnt] = V1[i][j].p; tempy[cnt] = h; cnt++; } for (int j = V2[i].size() - 1; j >= 0; j--) { tempx[cnt] = w; tempy[cnt] = V2[i][j].p; cnt++; } cnt = 0; for (int j = V2[i].size() - 1; j >= 0; j--) { ansx[V2[i][j].idx] = tempx[cnt]; ansy[V2[i][j].idx] = tempy[cnt]; cnt++; } for (int j = 0; j < V1[i].size(); j++) { ansx[V1[i][j].idx] = tempx[cnt]; ansy[V1[i][j].idx] = tempy[cnt]; cnt++; } } for (int i = 1; i <= n; i++) { printf( %d %d n , ansx[i], ansy[i]); } return 0; } |
//*****************************************************************************
//(c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : qdr_phy_write_data_io.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Nov 12, 2008
// \___\/\___\
//
//Device: 7 Series
//Design: QDRII+ SRAM
//
//Purpose:
// This module
// 1. Is the top level module for write data
// 2. Instantiates the I/O modules for the memory write data
//
//Revision History:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_phy_write_data_io #
(
parameter BURST_LEN = 4, //Burst Length
parameter DATA_WIDTH = 72, //Data Width
parameter BW_WIDTH = 8, //Byte Write Width
parameter TCQ = 100 //Register Delay
)
(
input clk, //main system half freq clk
input rst_clk, //main write path reset
input cal_done, //calibration done
input wr_cmd0,
input wr_cmd1,
input [1:0] init_wr_cmd,
input [DATA_WIDTH*2-1:0] init_wr_data0, //init state machine data 0
input [DATA_WIDTH*2-1:0] init_wr_data1, //init state machine data 1
input [DATA_WIDTH*2-1:0] wr_data0, //user write data 0
input [DATA_WIDTH*2-1:0] wr_data1, //user write data 1
input [BW_WIDTH*2-1:0] wr_bw_n0, //user byte writes 0
input [BW_WIDTH*2-1:0] wr_bw_n1, //user byte writes 1
output reg [DATA_WIDTH-1:0] iob_data_rise0, //OSERDES d rise0
output reg [DATA_WIDTH-1:0] iob_data_fall0, //OSERDES d fall0
output reg [DATA_WIDTH-1:0] iob_data_rise1, //OSERDES d rise1
output reg [DATA_WIDTH-1:0] iob_data_fall1, //OSERDES d fall1
output reg [BW_WIDTH-1:0] iob_bw_rise0, //OSERDES bw rise0
output reg [BW_WIDTH-1:0] iob_bw_fall0, //OSERDES bw fall0
output reg [BW_WIDTH-1:0] iob_bw_rise1, //OSERDES bw rise1
output reg [BW_WIDTH-1:0] iob_bw_fall1, //OSERDES bw fall1
output wire [DATA_WIDTH*4-1:0] dbg_phy_wr_data //cs debug - wr data
);
//Wire Declarations
wire [DATA_WIDTH-1:0] mux_data_rise0;
wire [DATA_WIDTH-1:0] mux_data_fall0;
wire [DATA_WIDTH-1:0] mux_data_rise1;
wire [DATA_WIDTH-1:0] mux_data_fall1;
reg [DATA_WIDTH-1:0] mux_data_rise0_r;
reg [DATA_WIDTH-1:0] mux_data_fall0_r;
reg [DATA_WIDTH-1:0] mux_data_rise1_r;
reg [DATA_WIDTH-1:0] mux_data_fall1_r;
reg [DATA_WIDTH-1:0] mux_data_fall1_2r;
wire [BW_WIDTH-1:0] mux_bw_rise0;
wire [BW_WIDTH-1:0] mux_bw_fall0;
wire [BW_WIDTH-1:0] mux_bw_rise1;
wire [BW_WIDTH-1:0] mux_bw_fall1;
reg [BW_WIDTH-1:0] mux_bw_rise0_r;
reg [BW_WIDTH-1:0] mux_bw_fall0_r;
reg [BW_WIDTH-1:0] mux_bw_rise1_r;
reg [BW_WIDTH-1:0] mux_bw_fall1_r;
reg [BW_WIDTH-1:0] mux_bw_fall1_2r;
//Debug ChipScope Signals
assign dbg_phy_wr_data = {mux_data_rise0, mux_data_fall0,
mux_data_rise1, mux_data_fall1};
//Select the data/bw from either the user or the init state machine based on
//if calibration is done.
assign mux_data_rise0 = (cal_done && (wr_cmd0 || wr_cmd1) ) ?
wr_data0[DATA_WIDTH*2-1 : DATA_WIDTH] : (~ cal_done && |init_wr_cmd)?
init_wr_data0[DATA_WIDTH*2-1 : DATA_WIDTH] : 'b0;
assign mux_data_fall0 = (cal_done && (wr_cmd0 || wr_cmd1) ) ?
wr_data0[DATA_WIDTH-1 : 0] : (~ cal_done && |init_wr_cmd)?
init_wr_data0[DATA_WIDTH-1 : 0]: 'b0;
assign mux_data_rise1 = (cal_done && (wr_cmd0 || wr_cmd1) ) ?
wr_data1[DATA_WIDTH*2-1 : DATA_WIDTH] : (~ cal_done && |init_wr_cmd)?
init_wr_data1[DATA_WIDTH*2-1 : DATA_WIDTH]: 'b0;
assign mux_data_fall1 = (cal_done && (wr_cmd0 || wr_cmd1) ) ?
wr_data1[DATA_WIDTH-1 : 0] : (~ cal_done && |init_wr_cmd)?
init_wr_data1[DATA_WIDTH-1 : 0]: 'b0;
assign mux_bw_rise0 = (cal_done && (wr_cmd0 || wr_cmd1) ) ? wr_bw_n0[BW_WIDTH*2-1 : BW_WIDTH] :
{BW_WIDTH{1'b0}};
assign mux_bw_fall0 = (cal_done && (wr_cmd0 || wr_cmd1) ) ? wr_bw_n0[BW_WIDTH-1 : 0] :
{BW_WIDTH{1'b0}};
assign mux_bw_rise1 = (cal_done && (wr_cmd0 || wr_cmd1) ) ? wr_bw_n1[BW_WIDTH*2-1 : BW_WIDTH] :
{BW_WIDTH{1'b0}};
assign mux_bw_fall1 = (cal_done && (wr_cmd0 || wr_cmd1) ) ? wr_bw_n1[BW_WIDTH-1 : 0] :
{BW_WIDTH{1'b0}};
//When in BL4 mode, use the double registered version of the data/bw so they
//appear on the edge after the write command was issued. When in BL2
//mode use the single registered data/bw so they appear on the same edge
//as the write command.
always @ (posedge clk)
begin
if (rst_clk) begin
mux_data_rise0_r <=#TCQ 0;
mux_data_fall0_r <=#TCQ 0;
mux_data_rise1_r <=#TCQ 0;
mux_data_fall1_r <=#TCQ 0;
mux_data_fall1_2r <=#TCQ 0;
//Initialize active low bw to 1 - to fill entire width use -1
mux_bw_rise0_r <=#TCQ -1;
mux_bw_fall0_r <=#TCQ -1;
mux_bw_rise1_r <=#TCQ -1;
mux_bw_fall1_r <=#TCQ -1;
mux_bw_fall1_2r <=#TCQ -1;
end else begin
mux_data_rise0_r <=#TCQ mux_data_rise0;
mux_data_fall0_r <=#TCQ mux_data_fall0;
mux_data_rise1_r <=#TCQ mux_data_rise1;
mux_data_fall1_r <=#TCQ mux_data_fall1;
mux_data_fall1_2r <=#TCQ mux_data_fall1_r;
mux_bw_rise0_r <=#TCQ mux_bw_rise0;
mux_bw_fall0_r <=#TCQ mux_bw_fall0;
mux_bw_rise1_r <=#TCQ mux_bw_rise1;
mux_bw_fall1_r <=#TCQ mux_bw_fall1;
mux_bw_fall1_2r <=#TCQ mux_bw_fall1_r;
end
end
//select the registered data or not based on the burst length. In BL4 the
//data should come on the next rising edge after a wr_n command.
//Because the address/control are shifted by .25 of a clock cycle, the
//data needs to be delayed in order to line up with on the cycle after the
//write command is issued. In order to reduce jitter on the data, we dont
//want to delay this by using an IODELAY for that .25 of a cycle. So for
//this shift the D0, D1, D2, D3 ports to the oserdes need to be off by one.
//D0 -> D3_r, D1 -> D0, D2 -> D1, D3 -> D2
//In BL2 the data should arrive on the same cycle as the command. To keep
//the data in line with the command, the same idea is used as that in BL4
//mode, by only delaying the data on D0.
always @ (posedge clk)
begin
iob_data_rise0 <=#TCQ (BURST_LEN == 4) ? mux_data_fall1_2r :
mux_data_fall1_r;
iob_data_fall0 <=#TCQ (BURST_LEN == 4) ? mux_data_rise0_r :
mux_data_rise0;
iob_data_rise1 <=#TCQ (BURST_LEN == 4) ? mux_data_fall0_r :
mux_data_fall0;
iob_data_fall1 <=#TCQ (BURST_LEN == 4) ? mux_data_rise1_r :
mux_data_rise1;
iob_bw_rise0 <=#TCQ (BURST_LEN == 4) ? mux_bw_fall1_2r : mux_bw_fall1_r;
iob_bw_fall0 <=#TCQ (BURST_LEN == 4) ? mux_bw_rise0_r : mux_bw_rise0;
iob_bw_rise1 <=#TCQ (BURST_LEN == 4) ? mux_bw_fall0_r : mux_bw_fall0;
iob_bw_fall1 <=#TCQ (BURST_LEN == 4) ? mux_bw_rise1_r : mux_bw_rise1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t, n, i; cin >> n; int a[n]; for (i = 0; i < n; i++) cin >> a[i]; long long int ans = 0; long long int pre[n + 1]; memset(pre, 0, sizeof(pre)); for (i = 1; i < n + 1; i++) pre[i] = pre[i - 1] + a[i - 1]; set<long long int> s; int start = -1; for (i = 0; i < n; i++) { if (start < i) { start = i; s.insert(pre[i]); } while (start < n && !s.count(pre[start + 1])) { start++; s.insert(pre[start]); } s.erase(pre[i]); ans += start - i; } cout << ans << endl; } |
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int ans = 0; int score = -1; for (int i = 0; i < n; i++) { int sub, subsc = 0; scanf( %d , &sub); subsc += sub; scanf( %d , &sub); subsc += sub; scanf( %d , &sub); subsc += sub; scanf( %d , &sub); subsc += sub; if (subsc > score) { ans++; } if (!i) score = subsc; } printf( %d , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:02:31 02/17/2016
// Design Name:
// Module Name: AR_RXD
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AR_RXD_2(
input clk,
input wire in1, //Èìïóëüñû êàíàëà 1
input wire in0, //Èìïóëüñû êàíàëà 0
output [7:0] sr_adr,
output [22:0]sr_dat,
output wire ce_wr);
reg [31:0] tmp_buf = 32'd0;
reg [31:0] out_buf = 32'd0;
assign sr_adr = out_buf [31:24];
genvar i;
generate
for (i = 0; i <= 22 ; i = i + 1)
begin: data_loop
assign sr_dat[i] = out_buf [23 - i];
end
endgenerate
assign par_bit = out_buf [0];
reg [1:0] Nvel = 3;
parameter Fclk = 50000000 ; //50 MHz
parameter V1Mb = ; // 1000 kb/s
parameter V100kb = 100000 ; // 100 kb/s
parameter V50kb = 50000 ; // 50 kb/s
parameter V12_5kb = 12500 ; // 12.5 kb/s
wire [10:0]AR_Nt = (Nvel [1:0] == 3)? (Fclk / (2 * V1Mb)) : //1000.000 kb/s
(Nvel [1:0] == 2)? (Fclk / (2 * V100kb)) : // 100.000 kb/s
(Nvel [1:0] == 1)? (Fclk / (2 * V50kb)) : // 50.000 kb/s
(Fclk / (2 * V12_5kb)); // 12.500 kb/s
reg [10:0] cb_tce = 0; // Ñ÷åò÷èê òàêòà
wire ce_tact = (cb_tce == AR_Nt); // Tce_tact=1/(2*VEL)
parameter WaitNextData = 0;
parameter RecData = 1;
parameter WaitPos = 2;
parameter WaitNeg = 3;
parameter Done = 4;
parameter Clear = 5;
reg [2:0] cur_state = WaitNextData;
reg clr_before_next = 0;
reg act_par_bit = 0;
reg ok_check = 0;
assign ce_wr = ok_check;
reg [5:0] rec_bit_num = 0;
parameter MaxTimeOut = 20;
reg [3:0] time_out = 0;
always @(posedge clk)
begin
if (cur_state == WaitNextData)
begin
cur_state <= (in1 | in0) ? Clear : WaitNextData;
clr_before_next <= 1;
cb_tce <= 0;
time_out <= 0;
end
else
begin
cb_tce <= (ce_tact) ? 1 : cb_tce + 1;
end
if (cur_state == WaitPos)
begin
time_out <= ce_tact ? time_out : time_out + 1;
cur_state <= (time_out > MaxTimeOut) ? Clear : (rec_bit_num == 32) ? Done : (in1 | in0) ? RecData : WaitPos;
end
else if (cur_state == RecData)
begin
tmp_buf <= in1 ? (tmp_buf << 1 | 1) : in0 ? (tmp_buf << 1) : tmp_buf;
act_par_bit <= act_par_bit ^ in1;
rec_bit_num <= rec_bit_num + 1;
time_out <= 0;
cur_state <= WaitNeg;
end
else if (cur_state == WaitNeg)
begin
cur_state <= (!in1 & !in0) ? WaitPos : WaitNeg;
end
else if (cur_state == Done)
begin
out_buf <= tmp_buf;
ok_check <= act_par_bit;
cur_state <= WaitNextData;
end
else if (cur_state == Clear)
begin
tmp_buf <= 0;
out_buf <= 0;
act_par_bit <= 0;
ok_check <= 0;
rec_bit_num <= 0;
time_out <= 0;
cur_state <= clr_before_next ? WaitPos : WaitNextData;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isIntersect(int x1, int y1, int x2, int y2, int x3, int y3, int x4, int y4) { double t1 = (y3 - y4) * (x1 - x3) + (x4 - x3) * (y1 - y3); double t2 = (x4 - x3) * (y1 - y2) - (x1 - x2) * (y4 - y3); double r1 = t1 / t2; double f1 = (y1 - y2) * (x1 - x3) + (x2 - x1) * (y1 - y3); double f2 = (x4 - x3) * (y1 - y2) - (x1 - x2) * (y4 - y3); double r2 = f1 / f2; if (r1 >= 0 && r1 <= 1 && r2 >= 0 && r2 <= 1) { return true; } return false; } double isInside(int x0, int y0, int x1, int y1, int x2, int y2) { double num = (y2 - y1) * x0 - (x2 - x1) * y0 + x2 * y1 - y2 * x1; num = abs(num); double den = sqrt(pow(y2 - y1, 2) + pow(x2 - x1, 2)); return num / den; } int main() { int first[4][2]; int second[4][2]; int minX = 200; int maxY = -200; int minY = 200; int maxX = -200; int min1X = 200; int max1X = -200; int min2Y = 200; int max2Y = -200; for (int i = 0; i < 4; i++) { for (int j = 0; j < 2; j++) { cin >> first[i][j]; if (j == 0) { minX = min(minX, first[i][j]); maxX = max(maxX, first[i][j]); } else { minY = min(minY, first[i][j]); maxY = max(maxY, first[i][j]); } } } for (int i = 0; i < 4; i++) { for (int j = 0; j < 2; j++) { cin >> second[i][j]; if (j == 0) { min1X = min(min1X, second[i][j]); max1X = max(max1X, second[i][j]); } else { min2Y = min(min2Y, second[i][j]); max2Y = max(max2Y, second[i][j]); } } } for (int i = 0; i < 4; i++) { if (second[i][0] >= minX && second[i][0] <= maxX && second[i][1] >= minY && second[i][1] <= maxY) { cout << YES ; return 0; } if (isInside(first[i][0], first[i][1], second[0][0], second[0][1], second[2][0], second[2][1]) + isInside(first[i][0], first[i][1], second[1][0], second[1][1], second[3][0], second[3][1]) <= (max2Y - min2Y) / 2) { cout << YES ; return 0; } } for (int i = 0; i < 4; i++) { int j = (i + 1) % 4; for (int ii = 0; ii < 4; ii++) { int jj = (ii + 1) % 4; if (isIntersect(first[i][0], first[i][1], first[j][0], first[j][1], second[ii][0], second[ii][1], second[jj][0], second[jj][1])) { cout << YES ; return 0; } } } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> arr[60][60]; int path[60][60][110]; int adj[60][60]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); adj[x][y] = 1; int k; scanf( %d , &k); while (k--) { int val; scanf( %d , &val); arr[x][y].push_back(val); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (!adj[i][j]) continue; int p = -1; for (int k = 1; k < arr[i][j].size(); k++) { if (arr[i][j][k - 1] == i && arr[i][j][k] == j) { if (p == -1) p = k - 1; else if (p >= 0) p = -2; } } if (p < 0) continue; int len = 1; vector<int> path; queue<int> q; int cur = i; path.push_back(cur); for (int k = p - 1; k >= 0; k--) { q.push(arr[i][j][k]); } int flag = 1; while (!q.empty()) { int x = q.front(); q.pop(); len++, path.push_back(x); if (!adj[x][cur]) { flag = 0; break; } for (int k = (int)arr[x][cur].size() - 1; k >= 0; k--) { q.push(arr[x][cur][k]); } cur = x; } if (!flag) continue; reverse(path.begin(), path.end()); int L = cur; cur = j, len++, path.push_back(cur); for (int k = p + 2; k < arr[i][j].size(); k++) { q.push(arr[i][j][k]); } while (!q.empty()) { int x = q.front(); q.pop(); len++, path.push_back(x); if (!adj[cur][x]) { flag = 0; break; } for (int k = 0; k < arr[cur][x].size(); k++) { q.push(arr[cur][x][k]); } cur = x; } if (!flag) break; int R = cur; if (len <= 2 * n) { printf( %d n , path.size()); for (int i = 0; i < path.size(); i++) { printf( %d , path[i]); } printf( n ); return 0; } } } printf( 0 n ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:49:18 09/03/2013
// Design Name:
// Module Name: timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timer(clk, rst, start_timer, time_value, expired);
input clk;
input rst;
input start_timer;
input [3:0] time_value;
output expired;
reg cuenta_finalizada;
reg [3:0] contador;
//Reloj a 1Hz
wire div_clk;
initial
begin
contador <= 4'b0001;
cuenta_finalizada <= 0;
end
//Divisor de reloj
clock_divider mod_divider(clk,rst,div_clk);
//
assign expired = start_timer & cuenta_finalizada;
//
always @( posedge div_clk, negedge start_timer)
begin
if(~start_timer)
begin
cuenta_finalizada <= 0;
contador <= 4'b0001; //Reset
end
else
begin
if(contador == time_value)
begin
contador <= 4'b0001;
cuenta_finalizada <= 1;
end
else
contador <= contador + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > g(300005); int a[300005], s1[300005], s2[300005]; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i(1); i <= n; i++) { cin >> a[i]; } for (int i(0); i < n - 1; i++) { int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } long long mx = -1e15, kol = 0, kkol = 0, mxx = -1e15; for (int i(1); i <= n; i++) { if (a[i] > mx) { if (mx + 1 == a[i]) { mxx = mx; kkol = kol; } else { mxx = a[i] - 1; kkol = 0; } kol = 1; mx = a[i]; continue; } if (a[i] == mx) kol++; if (a[i] == mxx) kkol++; } for (int i(1); i <= n; i++) { for (int j(0); j < g[i].size(); j++) { if (a[g[i][j]] == mx) s1[i]++; else if (a[g[i][j]] == mxx) s2[i]++; } } long long ans = mx; if (kol > 1) ans = mx + 1; int ces = 0; for (int i(1); i <= n; i++) { if (s1[i] == kol - 1 && a[i] == mx && kol > 1) { cout << mx + 1 << endl; exit(0); } if (s1[i] == kol && kol > 1) { cout << mx + 1 << endl; return 0; } if (a[i] == mx && s1[i] > 1 && ces == 0) { ans = max(ans, mx + 1); ces = 1; continue; } if (a[i] == mx && s1[i] > 1 && ces == 1) { ans = max(ans, mx + 2); continue; } if (s1[i] > 1 && ces == 0) { ces = 1; ans = max(mx + 1, ans); continue; } if (s1[i] > 1 && ces == 1) { ans = max(ans, mx + 2); continue; } if (s2[i] > 0 && a[i] == mxx) { ans = max(ans, mx + 1); continue; } if (s1[i] == 1 && s2[i] > 0 && ces == 0) { ans = max(ans, mx + 1); ces = 1; continue; } if (s1[i] == 1 && s2[i] > 0 && ces == 1) { ans = max(ans, mx + 2); continue; } if (s1[i] == 0 && kol > 1 && a[i] == mx) { ans = max(ans, mx + 2); ces = 1; continue; } if (s1[i] == kol && s2[i] == 0 && kkol > 0 && a[i] != mx) { ans = max(ans, mx + 1); continue; } if (a[i] == mx && kol == 1 && s2[i] == kkol) { cout << mx << endl; exit(0); } } cout << ans << endl; } |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:16777216 ) const char DEBUG = 0; mt19937 gen(chrono::high_resolution_clock::now().time_since_epoch().count()); struct pp { int pos, id; }; long long pos[200000]; int type[200000]; int res[100000]; vector<int> arr; int get_id1(int x) { int l = 0, r = arr.size(); while (r - l > 1) { int m = (l + r) / 2; if (arr[m] >= x) r = m; else l = m; } return l; } int get_id2(int x) { int l = -1, r = arr.size() - 1; while (r - l > 1) { int m = (l + r) / 2; if (arr[m] <= x) l = m; else r = m; } return r; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin.sync_with_stdio(0); cout.tie(0); cout.sync_with_stdio(0); int n, m; cin >> n >> m; for (int i = 0; i < n + m; i++) cin >> pos[i]; for (int i = 0; i < n + m; i++) cin >> type[i]; for (int i = 0; i < n + m; i++) if (type[i]) arr.push_back(pos[i]); for (int i = 0; i < n + m; i++) { if (type[i]) continue; long long d1 = 1000000000000000000LL, d2 = 1000000000000000000LL; int p1 = get_id1(pos[i]); int p2 = get_id2(pos[i]); d1 = abs(arr[p1] - pos[i]); d2 = abs(arr[p2] - pos[i]); if (d1 < d2) res[p1]++; else if (d2 < d1) res[p2]++; else { if (arr[p1] < arr[p2]) res[p1]++; else res[p2]++; } } for (int i = 0; i < m; i++) cout << res[i] << ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) #pragma GCC target( avx,avx2 ) using namespace std; const long double eps = 1e-6; long double inf = 0; const long long mod = 1e9 + 7; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int count_dels(long long m) { int c = 0; for (long long i = 1; i * i <= m; ++i) { if (m % i != 0) continue; ++c; if (i != m / i) ++c; } return c; } int main() { cin.tie(0), cout.tie(0), ios_base::sync_with_stdio(0); int t; cin >> t; while (t--) { long long a, m; cin >> a >> m; long long d = gcd(a, m); long long m1 = m / d; long long ans = m1; for (long long i = 2; i * i <= m1; ++i) { if (m1 % i == 0) { ans -= ans / i; while (m1 % i == 0) m1 /= i; } } if (m1 != 1) ans -= ans / m1; cout << ans << n ; } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, multiplier. This is a simple partial product adder
// that generates the product of the two inputs.
`timescale 1ps/1ps
module cf_csc_1_mul (
// data_p = data_a (signed) * data_b (unsigned)
clk,
data_a,
data_b,
data_p,
// ddata_out is internal pipe-line matched for ddata_in
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
parameter DW = DELAY_DATA_WIDTH - 1;
input clk;
input [16:0] data_a;
input [ 7:0] data_b;
output [24:0] data_p;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
reg p1_sign = 'd0;
reg [DW:0] p1_ddata = 'd0;
reg [23:0] p1_data_p_0 = 'd0;
reg [23:0] p1_data_p_1 = 'd0;
reg [23:0] p1_data_p_2 = 'd0;
reg [23:0] p1_data_p_3 = 'd0;
reg [23:0] p1_data_p_4 = 'd0;
reg p2_sign = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [23:0] p2_data_p_0 = 'd0;
reg [23:0] p2_data_p_1 = 'd0;
reg p3_sign = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [23:0] p3_data_p_0 = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [24:0] data_p = 'd0;
wire [16:0] p1_data_a_1p_17_s;
wire [16:0] p1_data_a_1n_17_s;
wire [23:0] p1_data_a_1p_s;
wire [23:0] p1_data_a_1n_s;
wire [23:0] p1_data_a_2p_s;
wire [23:0] p1_data_a_2n_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_a_1p_17_s = {1'b0, data_a[15:0]};
assign p1_data_a_1n_17_s = ~p1_data_a_1p_17_s + 1'b1;
assign p1_data_a_1p_s = {{7{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s};
assign p1_data_a_1n_s = {{7{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s};
assign p1_data_a_2p_s = {{6{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s, 1'b0};
assign p1_data_a_2n_s = {{6{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s, 1'b0};
// pipe line stage 1, get the partial products
always @(posedge clk) begin
p1_sign <= data_a[16];
p1_ddata <= ddata_in;
case (data_b[1:0])
2'b11: p1_data_p_0 <= p1_data_a_1n_s;
2'b10: p1_data_p_0 <= p1_data_a_2n_s;
2'b01: p1_data_p_0 <= p1_data_a_1p_s;
default: p1_data_p_0 <= 24'd0;
endcase
case (data_b[3:1])
3'b011: p1_data_p_1 <= {p1_data_a_2p_s[21:0], 2'd0};
3'b100: p1_data_p_1 <= {p1_data_a_2n_s[21:0], 2'd0};
3'b001: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b010: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b101: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
3'b110: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
default: p1_data_p_1 <= 24'd0;
endcase
case (data_b[5:3])
3'b011: p1_data_p_2 <= {p1_data_a_2p_s[19:0], 4'd0};
3'b100: p1_data_p_2 <= {p1_data_a_2n_s[19:0], 4'd0};
3'b001: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b010: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b101: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
3'b110: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
default: p1_data_p_2 <= 24'd0;
endcase
case (data_b[7:5])
3'b011: p1_data_p_3 <= {p1_data_a_2p_s[17:0], 6'd0};
3'b100: p1_data_p_3 <= {p1_data_a_2n_s[17:0], 6'd0};
3'b001: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b010: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b101: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
3'b110: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
default: p1_data_p_3 <= 24'd0;
endcase
case (data_b[7])
1'b1: p1_data_p_4 <= {p1_data_a_1p_s[15:0], 8'd0};
default: p1_data_p_4 <= 24'd0;
endcase
end
// pipe line stage 2, get the sum (intermediate 5 -> 2)
always @(posedge clk) begin
p2_sign <= p1_sign;
p2_ddata <= p1_ddata;
p2_data_p_0 <= p1_data_p_0 + p1_data_p_1 + p1_data_p_4;
p2_data_p_1 <= p1_data_p_2 + p1_data_p_3;
end
// pipe line stage 2, get the sum (final 2 -> 1)
always @(posedge clk) begin
p3_sign <= p2_sign;
p3_ddata <= p2_ddata;
p3_data_p_0 <= p2_data_p_0 + p2_data_p_1;
end
// output registers (truncation occurs after addition, see cf_csc_1_add.v)
always @(posedge clk) begin
ddata_out <= p3_ddata;
data_p <= {p3_sign, p3_data_p_0};
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; map<pair<int, int>, bool> mp; bool check(int x, int y, int z) { if (y < x) swap(x, y); if (z < y) swap(z, y); if (y < x) swap(x, y); if (x + y > z && z > y && mp.count({x, y}) == 0) { mp[{x, y}] = 1; return 1; } else return 0; } int main() { int n; cin >> n; long long ans = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { if ((i ^ j) <= n && check(i, j, (i ^ j))) ans++; } } cout << ans; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 24844 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w2048,
w2049,
w8196,
w6147,
w64,
w6211,
w24844;
assign w1 = i_data0;
assign w2048 = w1 << 11;
assign w2049 = w1 + w2048;
assign w24844 = w6211 << 2;
assign w6147 = w8196 - w2049;
assign w6211 = w6147 + w64;
assign w64 = w1 << 6;
assign w8196 = w2049 << 2;
assign o_data0 = w24844;
//multiplier_block area estimate = 4886.48160088529;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
// usbHostSlave_h.v
//////////////////////////////////////////////////////////////////////
`ifdef usbHostSlave_h_vdefined
`else
`define usbHostSlave_h_vdefined
// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
// control reads and writes to USB flash dongle
// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
// speed, and TX resume is always low speed.
// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
// in missing receive packets.
// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
// by adding kludged delay to softranmit. This needs to be fixed properly.
// This version has undergone limited testing
// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
// with uClinux, and is known to work with a full speed USB flash stick.
// Moving Opencores project status from Beta to done.
// TODO: Test isochronous mode, and low speed mode using uClinux driver
// Create a seperate clock domain for the bus interface
// Add frame period adjustment capability
// Add compilation flags for slave only and host only versions
// Create data bus width options beyond 8-bit
// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
// Removed TX and RX fifo status registers, and removed
// TX fifo data count register.
// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
// Fixed slave mode bug which caused receive fifo to be filled with
// incoming data when the slave was responding with a NAK, and the
// data should have been discarded.
// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
// there was no detected activity on the USB data lines. This caused an infrequent
// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
// the higher level state machines are actively looking for receive packets.
// Modified USB RX data clock recovery, so that data is sampled during the middle
// of a USB bit period. Fixed a bug which could result in double sampling
// of USB RX data if clock phase adjustments were required in the middle of a
// USB packet.
// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
// during migration to ActiveHDL 7.1. Released SystemC test bench.
// Re-generated .v files using ActiveHDL 7.1
// Replaced individual timescale directives with `include "timescale.v
// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
// 'usbHostSlaveAvalonWrap'
// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
// synchronizer to incoming USB wire data to avoid
// metastability, and delay hazards. Not entirely sure, but it appears that
// this bug caused more problems with some of the newer low power FPGAs
// Maybe because they are more prone to problems with metastable
// inputs that feed logic functions causing excessive high speed
// toggle activity, and disrupting nearby cicuits.
// Version 2.0 - June 16th 2008. Added two new top level modules which
// allow the instantiation of only host (usbHost.v), or only device
// features. Added double sync stages between usbClk, and busClk domains
// to fix possible metastability issues. Also modified synchronization to
// allow operation with busClk frequency less than usbClk frequency (down to
// 24MHz). Integrated full support for USB PHY. Prior to this modification
// the user would need to instantiate a GPIO module to control USB speed,
// D+ and D- pull-up control, and VBUS detect. Fixed bug in bus interface wb_ack.
// Modified cross-clock synchronisation of fifo resets
// Added usbDevice, a standalone usb device implementation of usbhostslave
// no additional hardware or software required
// Version 2.1 - October 8th 2010. Fixed issues related to accessing low speed device via hub.
// Changed USB PHY 'USBFullSpeed' edge rate control pin so that it is wired to
// 'fullSpeedPolarityToSIE', rather than 'fullSpeedBitRateToSIE'.
// Introduced delay into 'fullSpeedRate' in module writeUSBWireData.v. Thus matching
// data delay with control delay.
// Created new control flow constant DATA_STOP_PRE. This allows PREAMBLE PID to completed
// without SEO (EOP), and ensures line state is left at state J.
// Prevented PREAMBLE PID from preceding SOF when PREAMBLE is enabled.
// Version 2.2 - March 18th 2011. Fixed more issues related to accessing low speed device via hub.
// Added 2 bit delay time from detection of low speed SEO (ie end of packet) to notification of
// higher level modules. This satisfies USB spec requirement of 2 bit times min turn around time
// Fixed SOF transmission to avoid collision with incoming ACK response in low speed mode.
// Fixed possible problem for full speed too.
// Most significant nibble corresponds to major revision.
// Least significant nibble corresponds to minor revision.
`define USBHOSTSLAVE_VERSION_NUM 8'h22
//Host slave common registers
`define HOST_SLAVE_CONTROL_REG 1'b0
`define HOST_SLAVE_VERSION_REG 1'b1
`endif //usbHostSlave_h_vdefined
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_vinterp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx_q,
input [16:0] diff_cx_r,
input diff_cy_positive,
input [16:0] diff_cy_q,
input [16:0] diff_cy_r,
input diff_dx_positive,
input [16:0] diff_dx_q,
input [16:0] diff_dx_r,
input diff_dy_positive,
input [16:0] diff_dy_q,
input [16:0] diff_dy_r,
input signed [11:0] drx,
input signed [11:0] dry,
input [10:0] dst_squareh,
output pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x,
output reg signed [11:0] y,
output signed [17:0] tsx,
output signed [17:0] tsy,
output signed [17:0] tex,
output signed [17:0] tey
);
reg load;
reg next_point;
always @(posedge sys_clk) begin
if(load)
x <= drx;
end
/* Interpolators */
tmu2_geninterp18 i_cx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ax),
.positive(diff_cx_positive),
.q(diff_cx_q),
.r(diff_cx_r),
.divisor({6'd0, dst_squareh}),
.o(tsx)
);
tmu2_geninterp18 i_cy(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ay),
.positive(diff_cy_positive),
.q(diff_cy_q),
.r(diff_cy_r),
.divisor({6'd0, dst_squareh}),
.o(tsy)
);
tmu2_geninterp18 i_bx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(bx),
.positive(diff_dx_positive),
.q(diff_dx_q),
.r(diff_dx_r),
.divisor({6'd0, dst_squareh}),
.o(tex)
);
tmu2_geninterp18 i_by(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(by),
.positive(diff_dy_positive),
.q(diff_dy_q),
.r(diff_dy_r),
.divisor({6'd0, dst_squareh}),
.o(tey)
);
/* y datapath */
always @(posedge sys_clk) begin
if(load)
y <= dry;
else if(next_point)
y <= y + 12'd1;
end
/* Controller */
reg [10:0] remaining_points;
always @(posedge sys_clk) begin
if(load)
remaining_points <= dst_squareh - 11'd1;
else if(next_point)
remaining_points <= remaining_points - 11'd1;
end
wire last_point = remaining_points == 11'd0;
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter BUSY = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
assign busy = state;
assign pipe_ack_o = ~state;
assign pipe_stb_o = state;
always @(*) begin
next_state = state;
load = 1'b0;
next_point = 1'b0;
case(state)
IDLE: begin
if(pipe_stb_i) begin
load = 1'b1;
next_state = BUSY;
end
end
BUSY: begin
if(pipe_ack_i) begin
if(last_point)
next_state = IDLE;
else
next_point = 1'b1;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 400010; int n; int fa[MAXN][21]; int dep[MAXN]; int LCA(int x, int y) { if (dep[x] < dep[y]) swap(x, y); for (int i = 20; i >= 0; i--) { if (dep[x] - (1 << i) >= dep[y]) { x = fa[x][i]; } } if (x == y) return x; for (int i = 20; i >= 0; i--) { if (fa[x][i] != fa[y][i]) { x = fa[x][i]; y = fa[y][i]; } } return fa[x][0]; } int main() { scanf( %d , &n); int L, R; L = R = 1; int mx = 0; int p; for (int i = 2; i <= n; i++) { scanf( %d , &p); fa[i][0] = p; dep[i] = dep[p] + 1; for (int j = 1; j <= 20; j++) { fa[i][j] = fa[fa[i][j - 1]][j - 1]; } int z = LCA(i, L); int ans1 = dep[i] + dep[L] - 2 * dep[z]; z = LCA(i, R); int ans2 = dep[i] + dep[R] - 2 * dep[z]; if (ans1 > ans2 && ans1 > mx) { mx = ans1; R = i; } if (ans2 >= ans1 && ans2 > mx) { L = i; mx = ans2; } if (i == n) printf( %d n , mx); else printf( %d , mx); } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n - 1); vector<int> b(n - 1); for (auto &d : a) cin >> d; for (auto &d : b) cin >> d; for (int u = 0; u <= 3; ++u) { vector<int> ans; ans.push_back(u); bool flagg = true; for (int i = 0; i < n - 1; ++i) { bool flag = false; int t = -1; for (int j = 0; j <= 3; ++j) { if (((j & *ans.rbegin()) == b[i]) && ((j | *ans.rbegin()) == a[i])) { flag = true; t = j; break; } } if (!flag) { flagg = false; break; } ans.push_back(t); } if (flagg) { cout << YES << endl; for (auto s : ans) cout << s << ; return 0; } } cout << NO ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int arr[1000005]; int n, m, k; int main() { scanf( %d%d%d , &n, &m, &k); memset(arr, 0, sizeof arr); for (int i = 0; i < m; ++i) { int number; scanf( %d , &number); arr[number] = 1; } bool flg = 0; int where = 1; if (arr[where] == 1) flg = 1; while (k--) { int num1, num2; scanf( %d%d , &num1, &num2); if (num1 == where && !flg) { where = num2; if (arr[where] == 1) flg = 1; } else if (num2 == where && !flg) { where = num1; if (arr[where] == 1) flg = 1; } } printf( %d , where); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSRECEIVER_PP_BLACKBOX_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busreceiver (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_PP_BLACKBOX_V
|
`ifdef cyclonev
`define LCELL cyclonev_lcell_comb
`define MAC cyclonev_mac
`define MLAB cyclonev_mlab_cell
`define IBUF cyclonev_io_ibuf
`define OBUF cyclonev_io_obuf
`define CLKENA cyclonev_clkena
`endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
`define MAC cyclone10gx_mac
`define MLAB cyclone10gx_mlab_cell
`define IBUF cyclone10gx_io_ibuf
`define OBUF cyclone10gx_io_obuf
`define CLKENA cyclone10gx_clkena
`endif
module __MISTRAL_VCC(output Q);
MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module __MISTRAL_GND(output Q);
MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
endmodule
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter [31:0] LUT = 32'h0000_0000;
`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter [15:0] LUT = 16'h0000;
`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
endmodule
module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
endmodule
module MISTRAL_ALUT2(input A, B, output Q);
parameter [3:0] LUT = 4'h0;
`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
endmodule
module MISTRAL_NOT(input A, output Q);
NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
endmodule
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
parameter _TECHMAP_CELLNAME_ = "";
// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
// which takes in a hexadecimal string that could be used to initialise RAM.
// In the vendor simulation models, this appears to work fine, but Quartus,
// either intentionally or not, forgets about this parameter and initialises the
// RAM to zero.
//
// Because of this, RAM initialisation is presently disabled, but the source
// used to generate mem_init0 is kept (commented out) in case this gets fixed
// or an undocumented way to get Quartus to initialise from mem_init0 is found.
`MLAB #(
.logical_ram_name(_TECHMAP_CELLNAME_),
.logical_ram_depth(32),
.logical_ram_width(1),
.mixed_port_feed_through_mode("Dont Care"),
.first_bit_number(0),
.first_address(0),
.last_address(31),
.address_width(5),
.data_width(1),
.byte_enable_mask_width(1),
.port_b_data_out_clock("NONE"),
// .mem_init0($sformatf("%08x", INIT))
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.ena0(A1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter _TECHMAP_CELLNAME_ = "";
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input CLK1, A1EN, B1EN;
output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented.
cyclonev_ram_block #(
.operation_mode("dual_port"),
.logical_ram_name(_TECHMAP_CELLNAME_),
.port_a_address_width(CFG_ABITS),
.port_a_data_width(CFG_DBITS),
.port_a_logical_ram_depth(2**CFG_ABITS),
.port_a_logical_ram_width(CFG_DBITS),
.port_a_first_address(0),
.port_a_last_address(2**CFG_ABITS - 1),
.port_a_first_bit_number(0),
.port_b_address_width(CFG_ABITS),
.port_b_data_width(CFG_DBITS),
.port_b_logical_ram_depth(2**CFG_ABITS),
.port_b_logical_ram_width(CFG_DBITS),
.port_b_first_address(0),
.port_b_last_address(2**CFG_ABITS - 1),
.port_b_first_bit_number(0),
.port_b_address_clock("clock0"),
.port_b_read_enable_clock("clock0")
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portawe(A1EN),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.portbre(B1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(27),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(27),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(54),
.operation_mode("M27x27")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(18),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(18),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(36),
.operation_mode("M18x18_FULL")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(9),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(9),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(18),
.operation_mode("M9x9")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_IB(input PAD, output O);
`IBUF #(
.bus_hold("false"),
.differential_mode("false")
) _TECHMAP_REPLACE_ (
.i(PAD),
.o(O)
);
endmodule
module MISTRAL_OB(output PAD, input I, OE);
`OBUF #(
.bus_hold("false"),
.differential_mode("false")
) _TECHMAP_REPLACE_ (
.i(I),
.o(PAD),
.oe(OE)
);
endmodule
module MISTRAL_IO(output PAD, input I, OE, output O);
`IBUF #(
.bus_hold("false"),
.differential_mode("false")
) ibuf (
.i(PAD),
.o(O)
);
`OBUF #(
.bus_hold("false"),
.differential_mode("false")
) obuf (
.i(I),
.o(PAD),
.oe(OE)
);
endmodule
module MISTRAL_CLKBUF (input A, output Q);
`CLKENA #(
.clock_type("auto"),
.ena_register_mode("always enabled"),
.ena_register_power_up("high"),
.disable_mode("low"),
.test_syn("high")
) _TECHMAP_REPLACE_ (
.inclk(A),
.ena(1'b1),
.outclk(Q)
);
endmodule
|
module RxUart_tb ();
reg clk; ///< System clock
reg rst; ///< Reset FIFO
reg x16BaudStrobe; ///< Strobe at 16x baud rate
reg read; ///< Read strobe for buffer
reg write; ///< Write strobe
reg [7:0] dataIn; ///< Data to transmit
wire [7:0] dataOut; ///< Data from receive buffer
wire rxDataPresent; ///< Receive buffer not empty
wire rxHalfFull; ///< Receive buffer half full
wire rxFull; ///< Receive buffer full
wire serial;
wire txDataPresent; ///< Data present in transmit buffer
wire txHalfFull; ///< Transmit buffer is half full
wire txFull; ///< Transmit buffer is full
reg [2:0] baudStrobeCount;
integer i;
always #1 clk = ~clk;
always @(posedge clk) baudStrobeCount <= baudStrobeCount + 2'd1;
always @(posedge clk) x16BaudStrobe <= baudStrobeCount == 'd0;
initial begin
clk = 1'b0;
rst = 1'b1;
x16BaudStrobe = 1'b0;
read = 1'b0;
end
RxUart #(
.LOG2_DEPTH(4) ///< log2(depth of FIFO). Must be an integer
)
uut
(
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO
.x16BaudStrobe(x16BaudStrobe), ///< Strobe at 16x baud rate
.read(read), ///< Read strobe for buffer
.serialIn(serial), ///< Serial Receive
.dataOut(dataOut), ///< [7:0] Data from receive buffer
.dataPresent(rxDataPresent), ///< Receive buffer not empty
.halfFull(rxHalfFull), ///< Receive buffer half full
.full(rxFull) ///< Receive buffer full
);
TxUart #(
.LOG2_DEPTH(4) ///< log2(depth of FIFO). Must be an integer
)
stimulus
(
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO
.x16BaudStrobe(x16BaudStrobe), ///< Strobe at 16x baud rate
.dataIn(dataIn), ///< [7:0] Data to transmit
.write(write), ///< Write strobe
// Outputs
.serialOut(serial), ///< Serial transmit
.dataPresent(txDataPresent), ///< Data present in transmit buffer
.halfFull(txHalfFull), ///< Transmit buffer is half full
.full(txFull) ///< Transmit buffer is full
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_BLACKBOX_V
`define SKY130_FD_SC_HS__O211A_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211a (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 10; const long long INF = 1e18; const long double EPS = 1e-12; int a[300005]; map<int, int> mi; int l_, r_; long long pre[300005]; int b[300005]; int main() { int n; scanf( %d , &n); for (int i = (int)1; i < (int)n + 1; i++) { scanf( %d , &a[i]); } for (int i = (int)1; i < (int)n + 1; i++) { if (mi[a[i]] == 0) mi[a[i]] = i; } for (int i = (int)1; i < (int)n + 1; i++) { pre[i] = pre[i - 1]; if (a[i] >= 0) pre[i] += (long long)(a[i]); } long long ans = -(long long)(1e12); l_ = 0; r_ = 0; for (int i = n; i >= 1; i--) { int x = a[i]; int l = mi[x]; if (i == mi[x]) continue; long long net = pre[i - 1] - pre[l]; net += 2LL * (long long)(x); if (net > ans) { ans = net; l_ = l; r_ = i; } } int cnt = 0; for (int i = 0; i < (int)n + 1; i++) b[i] = 0; for (int i = (int)1; i < (int)n + 1; i++) { if (i == l_ || i == r_) { b[i] = 1; continue; } if (l_ < i && i < r_ && a[i] > 0) { b[i] = 1; } else { b[i] = 0; cnt++; } } cout << ans << << cnt << endl; for (int i = (int)1; i < (int)n + 1; i++) { if (b[i] == 0) { printf( %d , i); } } cout << endl; return 0; } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: multiplier.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module multiplier (
dataa,
datab,
result);
input wire [15:0] dataa;
input wire [15:0] datab;
output wire [31:0] result;
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (result),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL multiplier.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL multiplier.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL multiplier.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL multiplier.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL multiplier_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL multiplier_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int a[105]; double t[105]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } int cnt; for (int d = -1000; d <= 1000; d++) { if (d != 0) { for (int i = 0; i < n; i++) { t[i] = a[i] * 1.0 / d; } cnt = 0; for (int i = 0; i < n; i++) { if (t[i] > 0) { cnt++; } } if (cnt >= (n + 1) / 2) { cout << d << endl; return 0; } } } cout << 0 << endl; return 0; } |
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