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#include <bits/stdc++.h> const int MAX_LEN = 1010; using namespace std; template <typename U, typename V> string to_string(pair<U, V>); string to_string(const string& e_) { return + e_ + ; } string to_string(char e_) { return + string(1, e_) + ; } string to_string(bool e_) { return e_ ? true : false ; } template <typename T> string to_string(T e_) { string s_ = [ ; for (const auto& x_ : e_) s_ += to_string(x_) + ; return s_ + ] ; } template <typename U, typename V> string to_string(pair<U, V> e_) { return ( + to_string(e_.first) + , + to_string(e_.second) + ) ; } void dbg_str() { ; } template <typename U, typename... V> void dbg_str(U u, V... v) { ; dbg_str(v...); } long long int n, m; long long int ans, mn; long long int lx, hx, wx; struct rd { long long int l; long long int w; long long int h; }; vector<rd> rooms; vector<rd> rolls; int main() { scanf( %lld , &n); for (int i = 0; i < n; i++) { scanf( %lld %lld %lld , &lx, &wx, &hx); rooms.push_back({lx, wx, hx}); } scanf( %lld , &m); for (int i = 0; i < m; i++) { scanf( %lld %lld %lld , &lx, &wx, &hx); rolls.push_back({lx, wx, hx}); } ans = 0; for (int i = 0; i < n; i++) { mn = 1e14; for (int j = 0; j < m; j++) { long long int totw = (rolls[j].l / rooms[i].h) * rolls[j].w; if (!totw) continue; long long int nr = (long long int)ceil(((double)2 * (rooms[i].l + rooms[i].w)) / totw); mn = min(mn, nr * rolls[j].h); } ans += mn; } printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > ans; vector<int> e[100010]; void dfs(int x, int p, int entry) { ans.emplace_back(x, entry); if (x == 1) { for (int it : e[x]) if (it != p) dfs(it, x, ++entry), ans.emplace_back(1, entry); } else { int cur = entry; int sz = e[x].size() - 1; if (entry - 1 >= sz) { cur = entry - 1 - sz; ans.emplace_back(x, cur); for (int it : e[x]) if (it != p) { cur++; dfs(it, x, cur), ans.emplace_back(x, cur); } } else { for (int it : e[x]) if (it != p) { ++cur; dfs(it, x, cur), ans.emplace_back(x, cur); if (cur == sz + 1) { cur = 0; ans.emplace_back(x, 0); } } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 1, u, v; i < n; i++) { cin >> u >> v; e[u].emplace_back(v); e[v].emplace_back(u); } dfs(1, 0, 0); cout << ans.size() << n ; for (auto &[u, v] : ans) cout << u << << v << n ; } |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ac_ROM_reg(
rdaddress,
clock,
wraddress,
data,
wren,
q);
parameter AC_ROM_DATA_WIDTH = "";
parameter AC_ROM_ADDRESS_WIDTH = "";
input [(AC_ROM_ADDRESS_WIDTH-1):0] rdaddress;
input clock;
input [(AC_ROM_ADDRESS_WIDTH-1):0] wraddress;
input [(AC_ROM_DATA_WIDTH-1):0] data;
input wren;
output reg [(AC_ROM_DATA_WIDTH-1):0] q;
reg [(AC_ROM_DATA_WIDTH-1):0] ac_mem[(2**AC_ROM_ADDRESS_WIDTH-1):0];
always @(posedge clock)
begin
if(wren)
ac_mem[wraddress] <= data;
q <= ac_mem[rdaddress];
end
endmodule//ir_rw_manager_ac_ROM
|
#include <bits/stdc++.h> using namespace std; struct node { int num; string ss; }; unordered_map<string, node> mm; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; while (cin >> n) { mm.clear(); for (int i = 0; i < n; i++) { string s; cin >> s; for (int j = 0; j < s.length(); j++) { for (int k = 1; k <= (s.length() - j); k++) { string sb = s.substr(j, k); if (mm.find(sb) != mm.end() && mm[sb].ss != s) { mm[sb].num++; mm[sb].ss = s; } else if (mm.find(sb) == mm.end()) { node temp; temp.num = 1; temp.ss = s; mm[sb] = temp; } } } } int q; cin >> q; for (int i = 0; i < q; i++) { string s; cin >> s; if (mm.find(s) != mm.end()) { cout << mm[s].num << << mm[s].ss << endl; } else { cout << 0 << - << endl; } } } return 0; } |
#include <stdio.h> #include <sys/time.h> #define N 100000 #define Q 100000 #define A 100000 #define B 2154 /* B = floor(Q^(2/3)) = floor(N^(2/3)) */ #define INF 0x3f3f3f3f int min(int a, int b) { return a < b ? a : b; } unsigned int X; void srand_() { struct timeval tv; gettimeofday(&tv, NULL); X = tv.tv_sec ^ tv.tv_usec; if (X % 2 == 0) X++; } int rand_() { return (X *= 3) >> 1; } int tt[Q], ll[Q], rr[Q], kk[Q], ans[Q]; int compare(int h1, int h2) { return h1 / B != h2 / B ? h1 / B - h2 / B : (ll[h1] / B != ll[h2] / B ? ll[h1] / B - ll[h2] / B : rr[h1] - rr[h2]); } void sort(int *hh, int l, int r) { while (l < r) { int i = l, j = l, k = r, h = hh[l + rand_() % (r - l)], tmp; while (j < k) { int c = compare(hh[j], h); if (c == 0) j++; else if (c < 0) { tmp = hh[i], hh[i] = hh[j], hh[j] = tmp; i++, j++; } else { k--; tmp = hh[j], hh[j] = hh[k], hh[k] = tmp; } } sort(hh, l, i); l = k; } } int kk_[N + 1], prev[N + 1], next[N + 1]; void incr(int i) { if (next[i] != i + 1) { prev[i + 1] = i, next[i + 1] = next[i]; next[i] = i + 1; if (next[i + 1] != -1) prev[next[i + 1]] = i + 1; } kk_[i + 1]++; if (--kk_[i] == 0) { if (prev[i] != -1) next[prev[i]] = next[i]; if (next[i] != -1) prev[next[i]] = prev[i]; } } void decr(int i) { if (prev[i] != i - 1) { next[i - 1] = i, prev[i - 1] = prev[i]; prev[i] = i - 1; if (prev[i - 1] != -1) next[prev[i - 1]] = i - 1; } kk_[i - 1]++; if (--kk_[i] == 0) { if (prev[i] != -1) next[prev[i]] = next[i]; if (next[i] != -1) prev[next[i]] = prev[i]; } } int solve(int k) { int ans, i, j; ans = INF; for (i = next[0], j = 0; i != -1; i = next[i]) { while (next[j] != -1 && k > 0) k -= kk_[j = next[j]]; if (k > 0) break; ans = min(ans, j - i); k += kk_[i]; } return ans == INF ? -1 : ans; } int main() { static int aa[N], aa_[N], old[Q], new_[Q], hh[Q], cnt[A + 1]; int n, q, q_, h, h_, i, l, r; srand_(); scanf( %d%d , &n, &q); for (i = 0; i < n; i++) scanf( %d , &aa[i]), aa_[i] = aa[i]; q_ = 0; for (h = 0; h < q; h++) { scanf( %d , &tt[h]); if (tt[h] == 1) { scanf( %d%d%d , &ll[h], &rr[h], &kk[h]), ll[h]--, rr[h]--; hh[q_++] = h; } else { int a; scanf( %d%d , &i, &a), i--; ll[h] = rr[h] = i, old[h] = aa_[i], new_[h] = aa_[i] = a; } } sort(hh, 0, q_); kk_[0] = INF, prev[0] = next[0] = -1; for (h_ = 0, h = 0, l = 0, r = -1; h_ < q_; h_++) { int h1 = hh[h_], l1 = ll[h1], r1 = rr[h1]; while (h < h1) { if (tt[h] == 2) { i = ll[h]; if (l <= i && i <= r) decr(cnt[aa[i]]--); aa[i] = new_[h]; if (l <= i && i <= r) incr(cnt[aa[i]]++); } h++; } while (h > h1) { h--; if (tt[h] == 2) { i = ll[h]; if (l <= i && i <= r) decr(cnt[aa[i]]--); aa[i] = old[h]; if (l <= i && i <= r) incr(cnt[aa[i]]++); } } while (l > l1) incr(cnt[aa[--l]]++); while (r < r1) incr(cnt[aa[++r]]++); while (l < l1) decr(cnt[aa[l++]]--); while (r > r1) decr(cnt[aa[r--]]--); ans[h1] = solve(kk[h1]); } for (h = 0; h < q; h++) if (tt[h] == 1) printf( %d n , ans[h]); return 0; } |
`default_nettype none
//All DFF* have INIT, but the hardware is always initialised to the reset
//value regardless. The parameter is ignored.
// DFFN D Flip-Flop with Negative-Edge Clock
module \$_DFF_N_ (input D, C, output Q);
DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFF D Flip-Flop
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFE D Flip-Flop with Clock Enable
module \$_DFFE_PP_ (input D, C, E, output Q);
DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
module \$_DFFE_NP_ (input D, C, E, output Q);
DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFR D Flip-Flop with Synchronous Reset
module \$_SDFF_PP0_ (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
module \$_SDFF_NP0_ (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
module \$_SDFFE_PP0P_ (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
module \$_SDFFE_NP0P_ (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFS D Flip-Flop with Synchronous Set
module \$_SDFF_PP1_ (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
module \$_SDFF_NP1_ (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
module \$_SDFFE_PP1P_ (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
module \$_SDFFE_NP1P_ (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFP D Flip-Flop with Asynchronous Preset
module \$_DFF_PP1_ (input D, C, R, output Q);
DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
module \$_DFF_NP1_ (input D, C, R, output Q);
DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFC D Flip-Flop with Asynchronous Clear
module \$_DFF_PP0_ (input D, C, R, output Q);
DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
module \$_DFF_NP0_ (input D, C, R, output Q);
DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
module \$_DFFE_PP1P_ (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
module \$_DFFE_NP1P_ (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
module \$_DFFE_PP0P_ (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
module \$_DFFE_NP0P_ (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else
if (WIDTH == 5) begin
wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
end else
if (WIDTH == 6) begin
wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's reg2mem aligner ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Aligns register data to memory alignment. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// Internal regs and wires
//
reg [7:0] memdata_hh;
reg [7:0] memdata_hl;
reg [7:0] memdata_lh;
reg [7:0] memdata_ll;
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
default : memdata_hh = regdata[31:24];
endcase
end
//
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
default : memdata_hl = regdata[7:0];
endcase
end
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
default : memdata_lh = regdata[15:8];
endcase
end
//
// Mux to memdata[7:0]
//
always @(regdata)
memdata_ll = regdata[7:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 1000001; const int MI = 100001; const int MT = 10001; int main() { long long int n, ans = 0; cin >> n; ans = (n * (n + 1)) / 2; n--; for (int i = 0; i < n; ++i) { int x; scanf( %d , &x); ans -= x; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a[120], i, j, res; while (scanf( %d %d , &n, &m) == 2) { for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } bool flag = true; int k = 0; while (flag) { for (i = 1; i <= n; i++) { if (a[i]) { if (a[i] <= m) { a[i] = 0; k++; if (k == n) { flag = false; res = i; } } else if (a[i] > m) { a[i] -= m; } } } } printf( %d n , res); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:01:19 03/26/2016
// Design Name:
// Module Name: mem
// Project Name:
// Target Devices:
// Tool versions:
// Description: ƬÉÏ´æ´¢£¬²ÉÓÃXilinx Block memory Éú³É
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mem(
clk_i,
mem_cyc_i,
mem_stb_i,
mem_we_i, //1ΪÏòÄ£¿éд£¬0Ϊ¶Á
mem_ack_o,
mem_adr_i, //µØÖ·ÊäÈë
mem_dat_i, //Êý¾ÝÊäÈë
mem_dat_o, //Êý¾ÝÊä³ö
readorg //ÐźÅÓÐЧʱ£¬memoryÓëÉϲãÄ£¿éͨÐÅ
);
input clk_i;
input readorg;
input mem_cyc_i;
input mem_stb_i;
input mem_we_i;
output reg mem_ack_o = 1'b0;
input[21:0] mem_adr_i;
input[31:0] mem_dat_i ;
output[31:0] mem_dat_o;
wire mem_stb_i;
reg [31:0] mem_dat_o=0;
reg mem_en_1; //block memoryµÄʹÄÜÐźÅ
reg D_mem_en_1;
wire [31:0] dat_out_mem_1;
wire [31:0] dat_out_D_mem_1;
blk_mem_gen_0 mem_1 (
.clka(clk_i), // input wire clka
.ena(mem_en_1), // input wire ena
.wea(mem_we_i), // input wire [0 : 0] wea
.addra(mem_adr_i[21:2]), // input wire [17 : 0] addra
.dina(mem_dat_i), // input wire [31 : 0] dina
.douta(dat_out_mem_1) // output wire [31 : 0] douta
);
blk_mem_gen_0 D_mem_1 (
.clka(clk_i), // input wire clka
.ena(D_mem_en_1), // input wire ena
.wea(mem_we_i), // input wire [0 : 0] wea
.addra(mem_adr_i[21:2]), // input wire [17 : 0] addra
.dina(mem_dat_i), // input wire [31 : 0] dina
.douta(dat_out_D_mem_1) // output wire [31 : 0] douta
);
always @(posedge clk_i) begin
if(mem_cyc_i && mem_stb_i) begin
if (!mem_we_i) begin //¶Ámemory
if (readorg) begin //ÉϲãÄ£¿é´ÓsobelµÄmemoryÖжÁ
mem_en_1 <= 0;
D_mem_en_1 <=1;
mem_dat_o <= dat_out_D_mem_1;
mem_ack_o = 1'b1;
end
else begin //comp´ÓmemoryÖжÁ
mem_en_1 <= 1;
D_mem_en_1 <=0;
mem_dat_o <= dat_out_mem_1;
mem_ack_o = 1'b1;
end
end
else if(mem_we_i) begin //дmemory
if (readorg) begin //ÉϲãÄ£¿é½«Í¼Æ¬ÐÅϢдµ½sobelµÄmemoryÖÐ
mem_en_1 <= 1;
D_mem_en_1 <=0;
mem_ack_o = 1'b1;
end
else begin //compÄ£¿é½«½á¹ûдµ½memoryÖÐ
mem_en_1 <= 0;
D_mem_en_1 <=1;
mem_ack_o = 1'b1;
end
end
else begin
mem_ack_o = 1'b0;
end
end
else begin
mem_ack_o = 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v[2]; long long get(long long a, long long b) { return (a + b != 0); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; string s; long long ans, x, y, a, b, c, d; long long minx, maxx, miny, maxy, maxl, maxr, maxu, maxd; while (t--) { cin >> s; x = 0; y = 0; minx = 0; maxx = 0; miny = 0; maxy = 0; maxl = 0; maxr = 0; maxu = 0; maxd = 0; for (auto it : s) { if (it == W ) y++; if (it == S ) y--; if (it == A ) x--; if (it == D ) x++; maxx = max(maxx, x); minx = min(minx, x); maxy = max(maxy, y); miny = min(miny, y); maxu = max(maxu, y - miny); maxd = max(maxd, maxy - y); maxr = max(maxr, x - minx); maxl = max(maxl, maxx - x); } a = max(maxl, maxr); b = max(get(maxl, maxr), a - (maxl != maxr)); c = max(maxu, maxd); d = max(get(maxu, maxd), c - (maxu != maxd)); a++; b++; c++; d++; ans = min(a * d, b * c); cout << ans << n ; } return 0; } |
module rs232_timer(
// outputs high on output "done" after delay
// inputs
clk,
reset_n, // asynchronous
start,
extra_delay,
// outputs
done,
state
);
`include "parameters_global.v"
input clk;
input reset_n;
input start;
input extra_delay;
output reg done;
output reg [`rs232_timer_state_width-1:0] state;
reg [`rs232_timer_counter_width-1:0] counter; // incremented every 20ns @ 50Mhz master clock
reg extra_delay_latch;
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
begin
state <= #`DEL RS232_TIMER_STATE_IDLE;
counter <= #`DEL `rs232_timer_counter_width'h0;
done <= #`DEL 0;
extra_delay_latch <= #`DEL 0;
end
else
begin
case (state) // synthesis parallel_case
RS232_TIMER_STATE_IDLE: // 0h
begin
if (start) // sample start signal. when high -> start timer
begin
state <= #`DEL RS232_TIMER_STATE_RUNNING;
extra_delay_latch <= #`DEL extra_delay;
end
end
RS232_TIMER_STATE_RUNNING:
begin
if (~extra_delay_latch)
begin
if (counter >= rs232_delay)
begin
counter <= #`DEL 0;
state <= #`DEL RS232_TIMER_STATE_DONE;
done <= #`DEL 1'b1;
end
else
begin
counter <= #`DEL counter + 1;
end
end
else
begin
if (counter >= rs232_delay + rs232_extra_delay)
begin
counter <= #`DEL 0;
state <= #`DEL RS232_TIMER_STATE_DONE;
done <= #`DEL 1'b1;
end
else
begin
counter <= #`DEL counter + 1;
end
end
end
RS232_TIMER_STATE_DONE:
begin
done <= #`DEL 1'b0;
state <= #`DEL RS232_TIMER_STATE_IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; int l[500], r[500], d[500], ans[500]; for (int i = 0; i < q; i++) { cin >> l[i] >> r[i] >> d[i]; int quo; if (d[i] < l[i]) { ans[i] = d[i]; } else { quo = int(r[i] / d[i]); ans[i] = d[i] * (quo + 1); } } for (int i = 0; i < q; i++) { cout << ans[i] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_INT = 1000 * 1000 * 1000; int n, m; vector<int> ver; vector<int> hor; int main() { cin >> n >> m; ver.reserve(n + 1); ver.resize(n); for (int i = 0; i < n; ++i) cin >> ver.at(i), ver.at(i) += 1; ver.push_back(MAX_INT + 1); sort(ver.begin(), ver.end()); for (int i = 0; i < m; ++i) { int x1, x2, y; cin >> x1 >> x2 >> y; if (x1 == 1) hor.push_back(x2 + 1); } sort(hor.begin(), hor.end()); int bestAns = n + m; for (int i = 0; i < ver.size(); ++i) { auto it = lower_bound(hor.begin(), hor.end(), ver.at(i)); int mustBreak = distance(it, hor.end()); bestAns = min(bestAns, i + mustBreak); } cout << bestAns << endl; } |
/* wb_cdc_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*Testbench for wb_cdc
*/
`default_nettype none
module wb_cdc_tb
#(parameter AUTORUN = 1);
localparam aw = 32;
localparam dw = 32;
localparam MEM_SIZE = 256;
reg wbm_clk = 1'b1;
reg wbm_rst = 1'b1;
reg wbs_clk = 1'b1;
reg wbs_rst = 1'b1;
wire [aw-1:0] wbm_m2s_adr;
wire [dw-1:0] wbm_m2s_dat;
wire [3:0] wbm_m2s_sel;
wire wbm_m2s_we ;
wire wbm_m2s_cyc;
wire wbm_m2s_stb;
wire [dw-1:0] wbm_s2m_dat;
wire wbm_s2m_ack;
wire [aw-1:0] wbs_m2s_adr;
wire [dw-1:0] wbs_m2s_dat;
wire [3:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [dw-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire done;
integer TRANSACTIONS;
generate
if (AUTORUN) begin
vlog_tb_utils vtu();
vlog_tap_generator #("wb_cdc.tap", 1) vtg();
initial begin
run;
vtg.ok("wb_cdc: All tests passed!");
$finish;
end
end
endgenerate
task run;
begin
transactor.bfm.reset;
@(posedge wbs_clk) wbs_rst = 1'b0;
@(posedge wbm_clk) wbm_rst = 1'b0;
if($value$plusargs("transactions=%d", TRANSACTIONS))
transactor.set_transactions(TRANSACTIONS);
transactor.display_settings;
transactor.run();
transactor.display_stats;
end
endtask
always #5 wbm_clk <= ~wbm_clk;
always #3 wbs_clk <= ~wbs_clk;
wb_bfm_transactor
#(.MEM_HIGH (MEM_SIZE-1),
.AUTORUN (0),
.VERBOSE (0))
transactor
(.wb_clk_i (wbm_clk),
.wb_rst_i (1'b0),
.wb_adr_o (wbm_m2s_adr),
.wb_dat_o (wbm_m2s_dat),
.wb_sel_o (wbm_m2s_sel),
.wb_we_o (wbm_m2s_we),
.wb_cyc_o (wbm_m2s_cyc),
.wb_stb_o (wbm_m2s_stb),
.wb_cti_o (),
.wb_bte_o (),
.wb_dat_i (wbm_s2m_dat),
.wb_ack_i (wbm_s2m_ack),
.wb_err_i (1'b0),
.wb_rty_i (1'b0),
//Test Control
.done());
wb_cdc
#(.AW(aw))
dut
(.wbm_clk (wbm_clk),
.wbm_rst (wbm_rst),
// Master Interface
.wbm_adr_i (wbm_m2s_adr),
.wbm_dat_i (wbm_m2s_dat),
.wbm_sel_i (wbm_m2s_sel),
.wbm_we_i (wbm_m2s_we ),
.wbm_cyc_i (wbm_m2s_cyc),
.wbm_stb_i (wbm_m2s_stb),
.wbm_dat_o (wbm_s2m_dat),
.wbm_ack_o (wbm_s2m_ack),
// Wishbone Slave interface
.wbs_clk (wbs_clk),
.wbs_rst (wbs_rst),
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack & !wbs_rst));
wb_bfm_memory
#(.DEBUG (0),
.mem_size_bytes(MEM_SIZE))
mem
(.wb_clk_i (wbs_clk),
.wb_rst_i (wbs_rst),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (3'b000),
.wb_bte_i (2'b00),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (),
.wb_rty_o ());
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long arr[2 * n]; for (long long i = 0; i < 2 * n; i++) cin >> arr[i]; long long m = 0; for (long long i = 0; i < 2 * n; i++) { if (arr[i] != arr[i + 1]) { for (long long j = i + 1; j < 2 * n; j++) { if (arr[i] == arr[j]) { for (long long k = j; k > i + 1; k--) { swap(arr[k], arr[k - 1]); m++; } break; } } i++; } else i++; } cout << m; } |
#include <bits/stdc++.h> using namespace std; struct W { int t, l, r; } w[100010]; int n, m, s, f; int main() { while (cin >> n >> m >> s >> f) { for (int i = (0); i < (m); i++) { cin >> w[i].t >> w[i].l >> w[i].r; } int t = 1, p = 0; int dir = f > s ? 1 : -1; while (s != f) { if (p < m && w[p].t == t && ((w[p].l <= s && s <= w[p].r) || (w[p].l <= s + dir && s + dir <= w[p].r))) { cout << X ; } else { s += dir; cout << (dir == 1 ? R : L ); } if (++t > w[p].t) p++; } cout << endl; } return 0; } |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_shifter.v
// Title : Barrel shifter
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_shifter (
// ----- Inputs -------
clk_i,
rst_i,
stall_x,
direction_x,
sign_extend_x,
operand_0_x,
operand_1_x,
// ----- Outputs -------
shifter_result_m
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_x; // Stall instruction in X stage
input direction_x; // Direction to shift
input sign_extend_x; // Whether shift is arithmetic (1'b1) or logical (1'b0)
input [`LM32_WORD_RNG] operand_0_x; // Operand to shift
input [`LM32_WORD_RNG] operand_1_x; // Operand that specifies how many bits to shift by
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] shifter_result_m; // Result of shift
wire [`LM32_WORD_RNG] shifter_result_m;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg direction_m;
reg [`LM32_WORD_RNG] left_shift_result;
reg [`LM32_WORD_RNG] right_shift_result;
reg [`LM32_WORD_RNG] left_shift_operand;
wire [`LM32_WORD_RNG] right_shift_operand;
wire fill_value;
wire [`LM32_WORD_RNG] right_shift_in;
integer shift_idx_0;
integer shift_idx_1;
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Select operands - To perform a left shift, we reverse the bits and perform a right shift
always @(*)
begin
for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1)
left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0];
end
assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x;
// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT)
? operand_0_x[`LM32_WORD_WIDTH-1]
: 1'b0;
// Determine bits to shift in for right shift or rotate
assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}};
// Reverse bits to get left shift result
always @(*)
begin
for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1)
left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1];
end
// Select result
assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result;
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Perform right shift
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
right_shift_result <= #1 {`LM32_WORD_WIDTH{1'b0}};
direction_m <= #1 `FALSE;
end
else
begin
if (stall_x == `FALSE)
begin
right_shift_result <= #1 {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG];
direction_m <= #1 direction_x;
end
end
end
endmodule
|
//Need at least one LUT per frame base address we want
`ifndef N_LUT
`define N_LUT 100
`endif
`ifndef N_BRAM
`define N_BRAM 8
`endif
`ifndef N_DI
`define N_DI 1
`endif
module top(input clk, stb, [DIN_N-1:0] di, output do);
parameter integer DIN_N = `N_DI;
parameter integer DOUT_N = `N_LUT + `N_BRAM;
wire [DIN_N-1:0] di_buf;
genvar i;
generate
for (i = 0; i < `N_DI; i = i+1) begin:di_bufs
IBUF ibuf(.I(di[i]), .O(di_buf[i]));
end
endgenerate
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di_buf};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din[7:0]),
.dout(dout)
);
endmodule
module roi(input clk, input [7:0] din, output [`N_LUT + `N_BRAM-1:0] dout);
genvar i;
generate
for (i = 0; i < `N_LUT; i = i+1) begin:luts
LUT6 #(
.INIT(64'h8000_0000_0000_0001 + (i << 16))
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(dout[i])
);
end
endgenerate
genvar j;
generate
for (j = 0; j < `N_BRAM; j = j+1) begin:brams
(* KEEP, DONT_TOUCH *)
RAMB36E1 #(
.INIT_00(256'h8000000000000000000000000000000000000000000000000000000000000000 + (j << 16))
) bram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[j + `N_LUT]),
.DOBDO(),
.DOPADOP(),
.DOPBDOP());
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100005], vis[100005], b[100005], h[100005], g[100005]; int main() { int n, m = 0; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == i) { g[a[i]] = ++m; h[m] = i; } } for (int i = 1; i <= n; i++) { if (!g[a[i]]) { cout << -1; return 0; } } cout << m << endl; for (int i = 1; i <= n; i++) { cout << g[a[i]] << ; } cout << endl; for (int i = 1; i <= m; i++) cout << h[i] << ; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); int n, m; long long minb[100010]; long long maxg[100010]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { scanf( %lld , minb + i); } sort(minb, minb + n); for (int i = 0; i < m; i++) { scanf( %lld , maxg + i); } sort(maxg, maxg + m); long long ans = 0; if (minb[n - 1] > maxg[0]) { cout << -1 << endl; return 0; } if (m == 1) { if (minb[n - 1] != maxg[0]) { cout << -1 << endl; return 0; } else { for (int i = 0; i < n; i++) { ans += minb[i]; } cout << ans << endl; return 0; } } for (int i = 0; i < n - 1; i++) { ans += minb[i] * m; } for (int i = 1; i < m; i++) { ans += maxg[i]; } if (minb[n - 1] == maxg[0]) { ans += minb[n - 1]; } else { if (n == 1) { cout << -1 << endl; return 0; } else { ans += minb[n - 1] + maxg[0] - minb[n - 2]; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; for (int i = n + 1; i <= m; i++) { int count = 0; for (int j = 2; j < i; j++) { if (i % j == 0) count++; } if (count == 0) { if (m == i) { cout << YES << endl; return 0; } else break; } } cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; void solve() { int n, ans = 0; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; ans = max(ans, a[i] - i - 1); } cout << ans << n ; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> a; int n, j; string s; map<long long, int> f; long long h(string s) { long long res = 0; for (int i = 0; i < s.length(); i++) res = res * 28 + (s[i] - a ) + 1; return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { cin >> s; a.push_back(s); } long long j; for (int i = n - 1; i >= 0; i--) { j = h(a[i]); f[j]++; if (f[j] == 1) cout << a[i] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (a == 0) return b; return gcd(b % a, a); } long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { int n; cin >> n; long long int n1 = 0, n0 = 0, x1 = 0, x0 = 0; string a, b; cin >> a >> b; for (int i = 0; i < n; i++) { if (a[i] == 0 && b[i] == 1 ) n0++; if (a[i] == 1 && b[i] == 1 ) n1++; if (a[i] == 1 && b[i] == 0 ) x1++; if (a[i] == 0 && b[i] == 0 ) x0++; } long long int ans = 0; for (int i = 0; i < n; i++) { if (b[i] == 0 ) { if (a[i] == 1 ) ans += n0; else ans += n1; } } ans += x1 * x0; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, t; int s[100013]; int g[17][100013]; int lg[100013]; vector<pair<int, int> > sorted; int gcd(int a, int b) { return (b == 0) ? a : gcd(b, a % b); } int find_l(int gcf, int ind) { int left = 0, right = sorted.size() - 1; while (left < right) { int mid = (left + right) / 2; if (sorted[mid].first == gcf && sorted[mid].second == ind) { break; } if (sorted[mid].first < gcf || (sorted[mid].first == gcf && sorted[mid].second < ind)) { left = mid + 1; } else { right = mid; } } return (left + right) / 2; } int find_r(int gcf, int ind) { int left = 0, right = sorted.size() - 1; while (left < right) { int mid = (left + right + 1) / 2; if (sorted[mid].first == gcf && sorted[mid].second == ind) { break; } if (sorted[mid].first < gcf || (sorted[mid].first == gcf && sorted[mid].second < ind)) { left = mid; } else { right = mid - 1; } } return (left + right + 1) / 2; } int query(int l, int r) { int tmp = l; int gcf = 0; for (int i = 16; i >= 0; i--) if ((r - l + 1) & (1 << i)) { gcf = gcd(gcf, g[i][l]), l = l + (1 << i); } l = tmp; vector<pair<int, int> >::iterator left = lower_bound(sorted.begin(), sorted.end(), make_pair(gcf, l)); vector<pair<int, int> >::iterator right = upper_bound(sorted.begin(), sorted.end(), make_pair(gcf, r)); return r - l + 1 - max(0, (int)(right - left)); } int main() { scanf( %d , &n); int l = 0; for (int i = 1; i <= n; i++) { scanf( %d , &s[i]); sorted.push_back(make_pair(s[i], i)); if (i == (1 << (l + 1))) l++; lg[i] = l; } sort(sorted.begin(), sorted.end()); for (int i = 1; i <= n; i++) { g[0][i] = s[i]; } for (int i = 1; i <= 16; i++) { for (int j = 1; j <= n; j++) { g[i][j] = gcd(g[i - 1][j], g[i - 1][min(n, j + (1 << (i - 1)))]); } } scanf( %d , &t); for (int i = 0; i < t; i++) { int l, r; scanf( %d%d , &l, &r); printf( %d n , query(l, r)); } } |
#include <bits/stdc++.h> using namespace std; int cnt = 0; vector<int> ans; vector<vector<int> > adj; void dfs(int u, int col) { if (ans[u] != -1) return; ans[u] = col; for (int i = 0; i < adj[u].size(); ++i) dfs(adj[u][i], col); } char conv(int first) { if (first == 0) return b ; if (first == 1) return a ; if (first == 2) return c ; } int main() { cout.setf(ios::fixed); cout.precision(7); ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; adj = vector<vector<int> >(n); vector<int> deg(n, 0); for (int asdf = 0; asdf < m; ++asdf) { int first, second; cin >> first >> second; --first; --second; adj[first].push_back(second); adj[second].push_back(first); ++deg[first]; ++deg[second]; } ans = vector<int>(n, -1); int qt = 0; for (int i = 0; i < n; ++i) if (deg[i] == n - 1) { ans[i] = 0; ++qt; } for (int i = 0; i < n; ++i) if (ans[i] == -1) { ++cnt; dfs(i, cnt); } bool ok = true; if (cnt >= 3) ok = false; int n1 = 0, m1 = 0, n2 = 0, m2 = 0; for (int i = 0; i < n; ++i) { if (ans[i] == 1) { ++n1; m1 += deg[i] - qt; } else if (ans[i] == 2) { ++n2; m2 += deg[i] - qt; } } if (n1 * (n1 - 1) != m1) ok = false; if (n2 * (n2 - 1) != m2) ok = false; if (not ok) cout << No n ; else { cout << Yes n ; for (int i = 0; i < n; ++i) cout << conv(ans[i]); cout << n ; } } |
//syscontrol handles the startup of the FGPA,
//after fpga config, it automatically does a global system reset and asserts boot.
//the boot signal puts gary in a special mode so that the bootrom
//is mapped into the system memory map. The firmware in the bootrom
//then loads the kickstart via the diskcontroller into the kickstart ram area.
//When kickstart has been loaded, the bootrom asserts bootdone by selecting both cia's at once.
//This resets the system for a second time but it also de-asserts boot.
//Thus, the system now boots as a regular amiga.
//Subsequent resets by asserting mrst will not assert boot again.
//
// JB:
// 2008-07-11 - reset to bootloader
// 2009-03-13 - shorter reset
// 2009-08-17 - reset generator modification
module minimig_syscontrol
(
input clk, //bus clock
input clk7_en,
input cnt, //pulses for counting
input mrst, //master/user reset input
output reset //global synchronous system reset
);
//local signals
reg smrst0, smrst1; //registered input
reg [2:0] rst_cnt = 0; //reset timer SHOULD BE CLEARED BY CONFIG
wire _rst; //local reset signal
//asynchronous mrst input synchronizer
always @(posedge clk) begin
if (clk7_en) begin
smrst0 <= mrst;
smrst1 <= smrst0;
end
end
//reset timer and mrst control
always @(posedge clk) begin
if (clk7_en) begin
if (smrst1)
rst_cnt <= 3'd0;
else if (!_rst && cnt)
rst_cnt <= rst_cnt + 3'd1;
end
end
assign _rst = rst_cnt[2];
//global reset output
assign reset = ~_rst;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> bool maximize(T &x, const T &y) { if (x < y) x = y; else return false; return true; } const int N = 5e5 + 10; int n, q, md; int dx[N]; int d[N][21]; int query(int x, int y) { if (d[x][20] < y) return -1; int ret = 0; for (int i = 20; i >= 0; i--) if (d[x][i] < y) { x = d[x][i]; ret += 1 << i; } return ret + 1; } int main() { if (fopen( exam.inp , r )) freopen( exam.inp , r , stdin), freopen( exam.out , w , stdout); scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); maximize(dx[x], y); maximize(md, y); } for (int i = 1; i <= md; i++) maximize(dx[i], dx[i - 1]); for (int i = 0; i <= md; i++) d[i][0] = dx[i]; for (int j = 1; j <= 20; j++) for (int i = 0; i <= md; i++) d[i][j] = d[d[i][j - 1]][j - 1]; while (q--) { int x, y; scanf( %d%d , &x, &y); printf( %d n , query(x, y)); } } |
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// result_valid O 1
// result_value O 128 reg
// CLK I 1 clock
// RST_N I 1 reset
// put_args_x_is_signed I 1
// put_args_x I 64
// put_args_y_is_signed I 1
// put_args_y I 64
// EN_put_args I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkIntMul_64(CLK,
RST_N,
put_args_x_is_signed,
put_args_x,
put_args_y_is_signed,
put_args_y,
EN_put_args,
result_valid,
result_value);
input CLK;
input RST_N;
// action method put_args
input put_args_x_is_signed;
input [63 : 0] put_args_x;
input put_args_y_is_signed;
input [63 : 0] put_args_y;
input EN_put_args;
// value method result_valid
output result_valid;
// value method result_value
output [127 : 0] result_value;
// signals for module outputs
wire [127 : 0] result_value;
wire result_valid;
// register m_rg_isNeg
reg m_rg_isNeg;
wire m_rg_isNeg$D_IN, m_rg_isNeg$EN;
// register m_rg_signed
reg m_rg_signed;
wire m_rg_signed$D_IN, m_rg_signed$EN;
// register m_rg_state
reg [1 : 0] m_rg_state;
wire [1 : 0] m_rg_state$D_IN;
wire m_rg_state$EN;
// register m_rg_x
reg [127 : 0] m_rg_x;
wire [127 : 0] m_rg_x$D_IN;
wire m_rg_x$EN;
// register m_rg_xy
reg [127 : 0] m_rg_xy;
wire [127 : 0] m_rg_xy$D_IN;
wire m_rg_xy$EN;
// register m_rg_y
reg [63 : 0] m_rg_y;
wire [63 : 0] m_rg_y$D_IN;
wire m_rg_y$EN;
// rule scheduling signals
wire CAN_FIRE_RL_m_compute,
CAN_FIRE_put_args,
WILL_FIRE_RL_m_compute,
WILL_FIRE_put_args;
// inputs to muxes for submodule ports
wire [127 : 0] MUX_m_rg_x$write_1__VAL_1,
MUX_m_rg_x$write_1__VAL_2,
MUX_m_rg_xy$write_1__VAL_2;
wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2;
// remaining internal signals
wire [127 : 0] x__h236, x__h338, xy___1__h262;
wire [63 : 0] _theResult___fst__h506,
_theResult___fst__h509,
_theResult___fst__h560,
_theResult___fst__h563,
_theResult___snd_fst__h555;
wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34;
// action method put_args
assign CAN_FIRE_put_args = 1'd1 ;
assign WILL_FIRE_put_args = EN_put_args ;
// value method result_valid
assign result_valid = m_rg_state == 2'd2 ;
// value method result_value
assign result_value = m_rg_xy ;
// rule RL_m_compute
assign CAN_FIRE_RL_m_compute = m_rg_state == 2'd1 ;
assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ;
// inputs to muxes for submodule ports
assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h506 } ;
assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ;
assign MUX_m_rg_xy$write_1__VAL_2 = (m_rg_y == 64'd0) ? x__h236 : x__h338 ;
assign MUX_m_rg_y$write_1__VAL_1 =
(put_args_x_is_signed && put_args_y_is_signed) ?
_theResult___fst__h563 :
_theResult___snd_fst__h555 ;
assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ;
// register m_rg_isNeg
assign m_rg_isNeg$D_IN =
(put_args_x_is_signed && put_args_y_is_signed) ?
put_args_x[63] != put_args_y[63] :
IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34 ;
assign m_rg_isNeg$EN = EN_put_args ;
// register m_rg_signed
assign m_rg_signed$D_IN = 1'b0 ;
assign m_rg_signed$EN = 1'b0 ;
// register m_rg_state
assign m_rg_state$D_IN = EN_put_args ? 2'd1 : 2'd2 ;
assign m_rg_state$EN =
WILL_FIRE_RL_m_compute && m_rg_y == 64'd0 || EN_put_args ;
// register m_rg_x
assign m_rg_x$D_IN =
EN_put_args ?
MUX_m_rg_x$write_1__VAL_1 :
MUX_m_rg_x$write_1__VAL_2 ;
assign m_rg_x$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 64'd0 || EN_put_args ;
// register m_rg_xy
assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ;
assign m_rg_xy$EN =
WILL_FIRE_RL_m_compute && (m_rg_y == 64'd0 || m_rg_y[0]) ||
EN_put_args ;
// register m_rg_y
assign m_rg_y$D_IN =
EN_put_args ?
MUX_m_rg_y$write_1__VAL_1 :
MUX_m_rg_y$write_1__VAL_2 ;
assign m_rg_y$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 64'd0 || EN_put_args ;
// remaining internal signals
assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34 =
put_args_x_is_signed ?
put_args_x[63] :
put_args_y_is_signed && put_args_y[63] ;
assign _theResult___fst__h506 =
put_args_x_is_signed ? _theResult___fst__h509 : put_args_x ;
assign _theResult___fst__h509 = put_args_x[63] ? -put_args_x : put_args_x ;
assign _theResult___fst__h560 =
put_args_y_is_signed ? _theResult___fst__h563 : put_args_y ;
assign _theResult___fst__h563 = put_args_y[63] ? -put_args_y : put_args_y ;
assign _theResult___snd_fst__h555 =
put_args_x_is_signed ? put_args_y : _theResult___fst__h560 ;
assign x__h236 = m_rg_isNeg ? xy___1__h262 : m_rg_xy ;
assign x__h338 = m_rg_xy + m_rg_x ;
assign xy___1__h262 = -m_rg_xy ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (m_rg_state$EN)
m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN;
end
if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN;
if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN;
if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN;
if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN;
if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_isNeg = 1'h0;
m_rg_signed = 1'h0;
m_rg_state = 2'h2;
m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_rg_y = 64'hAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkIntMul_64
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemb function - Only read part of data file
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
/* pre init the array to all zeroes. */
for(count = 0; count <= 7; count = count + 1)
array[count] = 8'h0;
$readmemb("ivltests/readmemb1.dat",array,0,3);
for(count = 0; count <= 3; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(array[4] !== 8'h0)
begin
error = 1;
$display("FAILED - array[4] == %h, s/b 0",
array[count]);
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
module alt_vipvfr131_common_avalon_mm_slave
#(parameter
AV_ADDRESS_WIDTH = 5,
AV_DATA_WIDTH = 16,
NO_OUTPUTS = 1,
NO_INTERRUPTS = 1, // NO_INTERRUPTS < AV_DATA_WIDTH!!!
NO_REGISTERS = 4,
ALLOW_INTERNAL_WRITE = 0) // writing to registers internally allowed or not
(
input wire rst,
input wire clk,
// control
input wire [AV_ADDRESS_WIDTH-1:0] av_address,
input wire av_read,
output reg [AV_DATA_WIDTH-1:0] av_readdata,
input wire av_write,
input wire [AV_DATA_WIDTH-1:0] av_writedata,
output av_irq,
// internal
output reg enable,
input clear_enable, // clear go bit from internally
output reg [NO_REGISTERS-1:0] triggers,
output wire [(AV_DATA_WIDTH * NO_REGISTERS)-1:0] registers,
input wire [(AV_DATA_WIDTH * NO_REGISTERS)-1:0] registers_in,
input wire [NO_REGISTERS-1:0] registers_write,
input wire [NO_INTERRUPTS-1:0] interrupts,
input wire [NO_OUTPUTS-1:0] stopped);
wire global_stopped;
wire clear_interrupts;
wire [NO_REGISTERS-1:0] triggers_nxt;
reg [AV_DATA_WIDTH-1:0] internal_registers[NO_REGISTERS-1:0];
reg [AV_DATA_WIDTH-1:0] interrupt_register;
reg [NO_INTERRUPTS-1:0] interrupt_enables;
assign global_stopped = &stopped;
assign clear_interrupts = av_write && (av_address == 2); // clear selected interrupts when writing to interrupt register
// Interrupt register implemenation
generate
genvar j;
for (j = 0; j < AV_DATA_WIDTH; j = j+1) begin : interrupt_reg_loop
always @(posedge clk or posedge rst)
if (rst)
interrupt_register[j] <= 1'b0;
else if (j <= NO_INTERRUPTS & j > 0)
interrupt_register[j] <= clear_interrupts ? interrupt_register[j] & ~av_writedata[j] : // clear selected interrupts
interrupt_enables[j-1] ? interrupt_register[j] | interrupts[j-1] : 1'b0; // write enabled interrupts
end
endgenerate
always @ (posedge clk or posedge rst) begin
if(rst) begin
enable <= 1'b0;
interrupt_enables <= {NO_INTERRUPTS{1'b0}};
av_readdata <= {AV_DATA_WIDTH{1'b0}};
end else begin
if (clear_enable) begin
enable <= 1'b0;
end
if(av_write && (av_address == 0)) begin
enable <= av_writedata[0];
interrupt_enables <= av_writedata[NO_INTERRUPTS:1];
end
if(av_read) begin
case(av_address)
0: av_readdata <= {{(AV_DATA_WIDTH-NO_INTERRUPTS-1){1'b0}}, interrupt_enables, enable};
1: av_readdata <= {{AV_DATA_WIDTH-1{1'b0}}, global_stopped};
2: av_readdata <= {{(AV_DATA_WIDTH-NO_INTERRUPTS-1){1'b0}}, interrupt_register[NO_REGISTERS:1], 1'b0}; // bit 0 unused
default: av_readdata <= internal_registers[av_address - 3];
endcase
end
end
end
// av_irq is high if any of the individual enabled interrupts are high
assign av_irq = |interrupt_register[NO_REGISTERS:1]; // bit 0 of Interrupt register unused
// Register implementation
generate
genvar i;
for(i = 0; i < NO_REGISTERS; i = i+1) begin : register_loop
assign triggers_nxt[i] = (av_write && av_address == i + 3);
localparam base_address = i * AV_DATA_WIDTH;
assign registers[base_address + AV_DATA_WIDTH - 1:base_address] = internal_registers[i];
// registers can be written to from master (av_writedata) or (if ALLOW_INTERNAL_WRITE = 1) from internal side (registers_in)
always @ (posedge clk or posedge rst) begin
if(rst) begin
internal_registers[i] <= {AV_DATA_WIDTH{1'b0}};
triggers[i] <= 1'b0;
end else begin
if(triggers_nxt[i]) begin // master has priority to write into registers
internal_registers[i] <= av_writedata;
triggers[i] <= triggers_nxt[i];
end else if (ALLOW_INTERNAL_WRITE == 1 && registers_write[i]) begin // update from internal side only if master not writing at same time!
internal_registers[i] <= registers_in[base_address + AV_DATA_WIDTH - 1:base_address];
triggers[i] <= 1'b0; // if triggers[i] is 1 then av_writedata instead of register_in will have been written
end
end
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:19:44 10/07/2014
// Design Name:
// Module Name: pwm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pwm #(parameter MAX_WAVE = 24) (
input clk,
input rst,
input [MAX_WAVE-1:0] period,
input [MAX_WAVE-1:0] compare,
output pwm
);
reg pwm_d, pwm_q;
reg [MAX_WAVE-1:0] ctr_d, ctr_q;
assign pwm = pwm_q;
always@(ctr_q) begin
// reset ctr when we get to period, else increment
if (ctr_q > period) begin
ctr_d = 1'b0;
end else begin
ctr_d = ctr_q + 1'b1;
end
// set pwm based on ctr and compare threshold
if (compare > ctr_d) begin
pwm_d = 1'b0;
end else begin
pwm_d = 1'b1;
end
end
always@(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
pwm_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
pwm_q <= pwm_d;
end
end
endmodule
|
/*
* integer4ge - a verilog test for integer greater-or-equal conditional >=
*
* Copyright (C) 2000 Steve Wilson
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
`timescale 100s/1s
module test;
reg [3:0] result;
reg error;
integer num1;
wire [3:0] result1;
assign result1 = 1 + (num1 /4);
initial
begin
error = 0;
num1 = 32'h24 ;
result = 1 + (num1 / 4);
#1;
if(result !== 4'ha)
begin
$display("FAILED - division didn't work s/b A, is %h",result);
error = 1;
end
if(result1 !== 4'ha)
begin
$display("FAILED - assign division didn't work s/b A, is %h",result1);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_FUNCTIONAL_PP_V |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 17:04:31 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Instructions/Instructions_stub.v
// Design : Instructions
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *)
module Instructions(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[799:0]" */;
input clka;
input [9:0]addra;
output [799:0]douta;
endmodule
|
#include <bits/stdc++.h> int mod, n, a, b, good; std::set<std::pair<int, int> > set; std::pair<int, int> make_pair(int i, int j) { return {std::min(i, j), std::max(i, j)}; } int main() { scanf( %d%d , &mod, &n); for (int i = 0; i < n; i++) { scanf( %d%d , &a, &b); set.insert(make_pair(a - 1, b - 1)); } for (int k = 1; k < mod && !good; k++) { if (mod % k == 0) { good = true; for (auto p = set.begin(); good && p != set.end(); p++) if (!set.count(make_pair((p->first + k) % mod, (p->second + k) % mod))) good = false; } } printf( %s n , good ? yes : no ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MN = 1e4 + 20; vector<int> adj[MN], topo; vector<pair<int, int>> edge; int scc, st, s[MN], h[MN], t[MN]; bool os[MN]; stack<int> ms; int n, m; void add(int u, int v) { adj[u + m].push_back(v); adj[v + m].push_back(u); adj[u].push_back(v + m); adj[v].push_back(u + m); } void dfs(int v) { os[v] = 1; s[v] = h[v] = ++st; ms.push(v); for (int i : adj[v]) { if (!s[i]) dfs(i); if (os[i]) h[v] = min(h[v], h[i]); } if (h[v] == s[v]) { for (int i = ms.top();; i = ms.top()) { ms.pop(); os[i] = 0; h[i] = h[v]; t[i] = topo.size(); if (i == v) break; } scc++; topo.push_back(h[v]); } } int main() { cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--; v--; if (v > u) swap(u, v); for (int j = 0; j < i; j++) { if (u == edge[j].first || u == edge[j].second || v == edge[j].first || v == edge[j].second) continue; if ((u < edge[j].first && u > edge[j].second) ^ (v < edge[j].first && v > edge[j].second)) add(i, j); } edge.push_back({u, v}); } for (int i = 0; i < 2 * m; i++) if (!s[i]) dfs(i); reverse(topo.begin(), topo.end()); for (int i = 0; i < m; i++) { if (h[i] == h[i + m]) return cout << Impossible , 0; } for (int i = 0; i < m; i++) { t[i] < t[i + m] ? cout << i : cout << o ; } return 0; } |
//
// 2 read-port, 1 write-port ram
//
// reads are synchronous
//
//
module bsg_mem_2r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
wire unused = reset_i;
if ((width_p == 32) && (els_p == 32))
begin: macro
tsmc16_2rf_lg5_w32_all mem0
(
// read port
.CLKA (clk_i)
,.AA (r0_addr_i)
,.CENA(~r0_v_i)
// output
,.QA (r0_data_o)
// write port
,.CLKB(clk_i)
,.AB (w_addr_i)
,.DB (w_data_i)
,.CENB(~w_v_i)
,.STOV (1'd0 ) // Self-timing Override - disabled
,.EMAA (3'd3 ) // Extra Margin Adjustment - default value
,.EMAB (3'd3 ) // Extra Margin Adjustment - default value
,.EMASA(1'd1 ) // Extra Margin Adjustment Sense Amp. - default value
,.RET1N(1'b1 ) // Retention Mode (active low) - disabled
);
tsmc16_2rf_lg5_w32_all mem1
(
.CLKA (clk_i)
,.AA (r1_addr_i)
,.CENA(~r1_v_i)
// output
,.QA (r1_data_o)
// write port
,.CLKB(clk_i)
,.AB (w_addr_i)
,.DB (w_data_i)
,.CENB(~w_v_i)
,.STOV (1'd0 ) // Self-timing Override - disabled
,.EMAA (3'd3 ) // Extra Margin Adjustment - default value
,.EMAB (3'd3 ) // Extra Margin Adjustment - default value
,.EMASA(1'd1 ) // Extra Margin Adjustment Sense Amp. - default value
,.RET1N(1'b1 ) // Retention Mode (active low) - disabled
);
end // block: macro
else
begin: notmacro
bsg_mem_2r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
end
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w_sync)
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const int N = 2e5 + 10; const int MX = 1e9; int n, t; int ar[N], mn[N]; unordered_map<int, int> bit; void upd(int x, int val) { x++; while (x <= t) { bit[x] += val; x += (x & (-x)); } } int ask(int x) { x++; int ret = 0; while (x) { ret += bit[x]; x -= (x & (-x)); } return ret; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> t; t = min(t, n + MX + 10); for (int i = 1; i <= n; i++) { cin >> ar[i]; mn[i] = max(ar[i] - i, 0); } int ans = 0; for (int i = 1; i <= n; i++) { upd(mn[i], 1); int mul = t - i - 1; if (mul >= 0) { ans = max(ans, ask(mul)); } } cout << ans << n ; return 0; } |
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module I2C_Controller (
CLOCK,
I2C_SCLK, //I2C CLOCK
I2C_SDAT, //I2C DATA
I2C_DATA, //DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
GO, //GO transfor
END, //END transfor
ACK, //ACK
RESET,
//TEST
SD_COUNTER,
SDO
);
input CLOCK;
input [23:0]I2C_DATA;
input GO;
input RESET;
inout I2C_SDAT;
output I2C_SCLK;
output END;
output ACK;
//TEST
output [5:0] SD_COUNTER;
output SDO;
reg SDO;
reg SCLK;
reg END;
reg [23:0]SD;
reg [5:0]SD_COUNTER;
wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK : 1'd0 );
wire I2C_SDAT=SDO ? 1'bz : 1'b0 ;
reg ACK1,ACK2,ACK3;
wire ACK=ACK1 | ACK2 |ACK3;
//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER + 6'd1;
end
end
//----
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[23];
6'd4 : SDO=SD[22];
6'd5 : SDO=SD[21];
6'd6 : SDO=SD[20];
6'd7 : SDO=SD[19];
6'd8 : SDO=SD[18];
6'd9 : SDO=SD[17];
6'd10 : SDO=SD[16];
6'd11 : SDO=1'b1;//ACK
//SUB ADDR
6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[14];
6'd14 : SDO=SD[13];
6'd15 : SDO=SD[12];
6'd16 : SDO=SD[11];
6'd17 : SDO=SD[10];
6'd18 : SDO=SD[9];
6'd19 : SDO=SD[8];
6'd20 : SDO=1'b1;//ACK
//DATA
6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[6];
6'd23 : SDO=SD[5];
6'd24 : SDO=SD[4];
6'd25 : SDO=SD[3];
6'd26 : SDO=SD[2];
6'd27 : SDO=SD[1];
6'd28 : SDO=SD[0];
6'd29 : SDO=1'b1;//ACK
//stop
6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end
6'd31 : SCLK=1'b1;
6'd32 : begin SDO=1'b1; END=1; end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long i, j, k, l, m, n, t, a[211111], b[211111], c[111111], d, s; string p[111111], q[111111]; int main() { cin >> n; for (i = 1; i <= n; i++) scanf( %I64d , &a[i]); for (i = 1; i <= n; i++) scanf( %I64d , &b[i]); i = 1; j = 1; while (i <= n) { while (a[i] != b[j] && j <= n) j++; if (j <= n) i++; else break; } if (i > n) { cout << 0; return 0; } cout << n - i + 1; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__AND2B_BEHAVIORAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n; void draw(int k) { for (int i = 0; i < n - k; i++) { cout << ; } for (int i = 0; i < k; i++) { cout << i << ; } for (int i = k; ~i; i--) { cout << i << (i ? : n ); } } int main() { cin >> n; for (int i = 0; i < n; i++) { draw(i); } for (int i = n; ~i; i--) { draw(i); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, x; int a[105]; long double dp[2][105][10005]; const long double threshold = 1e-12; int main() { scanf( %d%d , &n, &x); long double s = 0.0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); s += a[i]; } dp[0][0][0] = 1.0; for (int i = 0; i < n; i++) { int now = i & 1, nxt = now ^ 1; memset(dp[nxt], 0, sizeof(dp[nxt])); for (int j = 0; j <= i; j++) { for (int k = 0; k <= 10000; k++) { dp[nxt][j][k] += dp[now][j][k]; dp[nxt][j + 1][k + a[i + 1]] += dp[now][j][k] * (j + 1) / (n - j); } } } long double ans = 0.0; for (int i = 0; i <= n - 1; i++) for (int j = 0; j <= s; j++) ans += dp[n & 1][i][j] * (min((s - j) / (n - i), ((long double)n / (n - i) + 1) * x / 2.0)); printf( %.10Lf n , ans); return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Manually created global mem, to avoid qsys hex generation bug
// qsys will always generate a .hex file to initialize the
// altsyncram - EVEN if you specify not to init the ram,
// for big ram's, this causes qsys to hang
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module bram_256x67M (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter DEPTH = 67108864;
parameter NWORDS_A = 67108864;
parameter ADDR_WIDTH = 26; // this should be $clog( DEPTH ), but qsys dies;
output [255: 0] readdata;
// ADDR_WIDTH
input [ 25: 0] address;
input [ 31: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [255: 0] writedata;
reg [255: 0] readdata;
wire [255: 0] readdata_ram;
wire wren;
always @(posedge clk)
begin
if (clken)
readdata <= readdata_ram;
end
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata_ram),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = DEPTH,
the_altsyncram.numwords_a = NWORDS_A,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 256,
the_altsyncram.width_byteena_a = 32,
the_altsyncram.widthad_a = ADDR_WIDTH;
//////////////// END SIMULATION-ONLY CONTENTS
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:06 08/03/2009
// Design Name:
// Module Name: ctrl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MCtrl(input clk,
input reset,
input [31:0] Inst_in,
input zero,
input overflow,
input MIO_ready,
output reg MemRead,
output reg MemWrite,
output reg[2:0]ALU_operation,
output [4:0]state_out,
output reg CPU_MIO,
output reg IorD,
output reg IRWrite,
output reg [1:0]RegDst,
output reg RegWrite,
output reg [1:0]MemtoReg,
output reg ALUSrcA,
output reg [1:0]ALUSrcB,
output reg [1:0]PCSource,
output reg PCWrite,
output reg PCWriteCond,
output reg Branch
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct SegmentTreeLazy { typedef long long T; const T inf = (T)1e18; const T not_found = -2; SegmentTreeLazy(vector<T> &v) { n = static_cast<int>(v.size()); int pow2 = 1; while (pow2 < n) pow2 <<= 1; mx.resize(2 * pow2, -inf); mn.resize(2 * pow2, inf); change.resize(2 * pow2); mode.resize(2 * pow2); build(v, 1, 0, n); } int query_zero_idx(int L, int R) { return query_zero_idx(1, 0, n, L, R); } void set(int L, int R, T x) { update(Mode::assign, 1, 0, n, L, R, x); } void inc(int L, int R, T x) { update(Mode::increment, 1, 0, n, L, R, x); } private: int n; enum class Mode { increment, assign }; vector<T> mx; vector<T> mn; vector<T> change; vector<Mode> mode; inline int left(int p) { return p << 1; } inline int right(int p) { return (p << 1) + 1; } void build(vector<T> &v, int pos, int lo, int hi) { if (lo + 1 < hi) { int mid = lo + (hi - lo) / 2; build(v, left(pos), lo, mid); build(v, right(pos), mid, hi); mx[pos] = max(mx[left(pos)], mx[right(pos)]); mn[pos] = min(mn[left(pos)], mn[right(pos)]); } else { mx[pos] = mn[pos] = v[lo]; } } T query_zero_idx(int pos, int lo, int hi, int L, int R) { if (R <= lo or hi <= L) return not_found; if (L <= lo and hi <= R) { if (mx[pos] < 0 or mn[pos] > 0) return not_found; else if (mx[pos] == 0 and mn[pos] == 0) return lo; else if (lo + 1 == hi) return -1; } propagate(pos, lo, hi); int mid = lo + (hi - lo) / 2; int idx = query_zero_idx(left(pos), lo, mid, L, R); if (idx != not_found) return idx; return query_zero_idx(right(pos), mid, hi, L, R); } void update(Mode m, int pos, int lo, int hi, int L, int R, T x) { if (R <= lo or hi <= L) { return; } if (L <= lo and hi <= R) { if (m == Mode::assign) { mx[pos] = x; mn[pos] = x; change[pos] = x; mode[pos] = Mode::assign; } else { mx[pos] += x; mn[pos] += x; change[pos] += x; } } else { propagate(pos, lo, hi); int mid = lo + (hi - lo) / 2; update(m, left(pos), lo, mid, L, R, x); update(m, right(pos), mid, hi, L, R, x); mx[pos] = max(mx[left(pos)], mx[right(pos)]); mn[pos] = min(mn[left(pos)], mn[right(pos)]); } } void propagate(int pos, int lo, int hi) { if (mode[pos] == Mode::assign or change[pos]) { int mid = lo + (hi - lo) / 2; update(mode[pos], left(pos), lo, mid, lo, mid, change[pos]); update(mode[pos], right(pos), mid, hi, mid, hi, change[pos]); change[pos] = 0; mode[pos] = Mode::increment; } } }; void solve() { int n, q, p; long long sum = 0, x; cin >> n >> q; vector<long long> diff, v; diff.reserve(n); for (int i = 0; i < n; ++i) { cin >> x; v.push_back(x); diff.push_back(x - sum); sum += x; } SegmentTreeLazy st(diff); int king = st.query_zero_idx(0, n); for (int i = 0; i < q; ++i) { cin >> p >> x; p -= 1; st.inc(p, p + 1, x - v[p]); st.inc(p + 1, n, v[p] - x); v[p] = x; if (king == st.not_found or king >= p) { king = st.query_zero_idx(p, n); } cout << king + 1 << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5; int l = 0; int r = 0; int res = 0; int f[maxn + 11][55]; int a[maxn + 11]; int cnt[maxn + 11]; void add(int x) { if (!cnt[a[x]]) res++; cnt[a[x]]++; } void del(int x) { cnt[a[x]]--; if (!cnt[a[x]]) res--; } int calc(int L, int R) { while (r < R) add(++r); while (r > R) del(r--); while (l > L) add(--l); while (l < L) del(l++); return res; } void solve(int k, int l, int r, int al, int ar) { int mid = (l + r) >> 1; if (l > r || al > ar) return; int ind = 0; for (int i = al; i <= min(ar, mid - 1); i++) { if (f[i][k - 1] + calc(i + 1, mid) > f[mid][k]) { f[mid][k] = f[i][k - 1] + calc(i + 1, mid); ind = i; } } solve(k, l, mid - 1, al, ind); solve(k, mid + 1, r, ind, ar); } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= k; i++) solve(i, 1, n, 0, n); cout << f[n][k] << endl; } |
// soc_design_niosII_core.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_niosII_core (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [16:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire [3:0] d_burstcount, // .burstcount
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [16:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
output wire [3:0] i_burstcount, // .burstcount
input wire i_readdatavalid, // .readdatavalid
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
soc_design_niosII_core_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_burstcount (d_burstcount), // .burstcount
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_burstcount (i_burstcount), // .burstcount
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300000 + 10; long long num[maxn], dp[maxn][15]; void Solve() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %lld , &num[i]); long long ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (j == 1) dp[i][j] = max(dp[i - 1][m] + num[i] - k, num[i] - k); else { if (i < j) break; dp[i][j] = dp[i - 1][j - 1] + num[i]; } ans = max(ans, dp[i][j]); } } printf( %lld n , ans); } int main() { Solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_PP_V |
// Check the various variable array selects (large to small).
module top;
reg passed;
wire [1:0] a [4:1];
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [1:0] ar [4:1];
wire [1:0] c [0:-3];
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [1:0] cr [0:-3];
wire [1:0] res_a0 = a[s0];
wire [1:0] res_a1 = a[s1];
wire [1:0] res_a2 = a[s2];
wire [1:0] res_c3 = c[s3];
wire [1:0] res_c4 = c[s4];
reg res_a [4:1];
reg res_c [0:-3];
assign a[1] = 2'd0;
assign a[2] = 2'b1;
assign a[3] = 2'd2;
assign a[4] = 2'd3;
assign c[-3] = 2'd0;
assign c[-2] = 2'b1;
assign c[-1] = 2'd2;
assign c[0] = 2'd3;
initial begin
#1;
passed = 1'b1;
ar[1] = 2'd0;
ar[2] = 2'b1;
ar[3] = 2'd2;
ar[4] = 2'd3;
cr[-3] = 2'd0;
cr[-2] = 2'b1;
cr[-1] = 2'd2;
cr[0] = 2'd3;
// Check procedural R-value variable bit selects of a net.
$display("a[s0]: %b", a[s0]);
if (a[s0] !== 2'bxx) begin
$display("Failed a[s0], expected 2'bxx, got %b", a[s0]);
passed = 1'b0;
end
$display("a[s1]: %b", a[s1]);
if (a[s1] !== 2'bxx) begin
$display("Failed a[s1], expected 2'bxx, got %b", a[s1]);
passed = 1'b0;
end
$display("a[s2]: %b", a[s2]);
if (a[s2] !== 2'bxx) begin
$display("Failed a[s2], expected 2'bxx, got %b", a[s2]);
passed = 1'b0;
end
$display("c[s3]: %b", c[s3]);
if (c[s3] !== 2'b11) begin
$display("Failed c[s3], expected 2'b11, got %b", c[s3]);
passed = 1'b0;
end
$display("c[s4]: %b", c[s4]);
if (c[s4] !== 2'b11) begin
$display("Failed c[s4], expected 2'b11, got %b", c[s4]);
passed = 1'b0;
end
// Check procedural R-value variable bit selects of a reg.
$display("ar[s0]: %b", ar[s0]);
if (ar[s0] !== 2'bxx) begin
$display("Failed ar[s0], expected 2'bxx, got %b", ar[s0]);
passed = 1'b0;
end
$display("ar[s1]: %b", ar[s1]);
if (ar[s1] !== 2'bxx) begin
$display("Failed ar[s1], expected 2'bxx, got %b", ar[s1]);
passed = 1'b0;
end
$display("ar[s2]: %b", ar[s2]);
if (ar[s2] !== 2'bxx) begin
$display("Failed ar[s2], expected 2'bxx, got %b", ar[s2]);
passed = 1'b0;
end
$display("cr[s3]: %b", cr[s3]);
if (cr[s3] !== 2'b11) begin
$display("Failed cr[s3], expected 2'b11, got %b", cr[s3]);
passed = 1'b0;
end
$display("cr[s4]: %b", cr[s4]);
if (cr[s4] !== 2'b11) begin
$display("Failed cr[s4], expected 2'b11, got %b", cr[s4]);
passed = 1'b0;
end
// Check continuous assignment R-value variable bit selects.
if (res_a0 !== 2'bxx) begin
$display("Failed res_a0, expected 2'bxx, got %b", res_a0);
passed = 1'b0;
end
if (res_a1 !== 2'bxx) begin
$display("Failed res_a1, expected 2'bxx, got %b", res_a1);
passed = 1'b0;
end
if (res_a2 !== 2'bxx) begin
$display("Failed res_a2, expected 2'bxx, got %b", res_a2);
passed = 1'b0;
end
if (res_c3 !== 2'b11) begin
$display("Failed res_c3, expected 2'b11, got %b", res_c3);
passed = 1'b0;
end
if (res_c4 !== 2'b11) begin
$display("Failed res_c4, expected 2'b11, got %b", res_c4);
passed = 1'b0;
end
// Check procedural L-value variable bit selects.
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s0] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s1] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s2] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_c[-3] = 1'bx;
res_c[-2] = 1'bx;
res_c[-1] = 1'bx;
res_c[0] = 1'bx;
res_c[s3] = 1'b0;
if (res_c[-3] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-3], got %b", res_c[-3]);
passed = 1'b0;
end
if (res_c[-2] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-2], got %b", res_c[-2]);
passed = 1'b0;
end
if (res_c[-1] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-1], got %b", res_c[-1]);
passed = 1'b0;
end
if (res_c[0] !== 1'b0) begin
$display("Failed res_c[s3], expected 1'b0 for [0], got %b", res_c[0]);
passed = 1'b0;
end
res_c[-3] = 1'bx;
res_c[-2] = 1'bx;
res_c[-1] = 1'bx;
res_c[0] = 1'bx;
res_c[s4] = 1'b0;
if (res_c[-3] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-3], got %b", res_c[-3]);
passed = 1'b0;
end
if (res_c[-2] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-2], got %b", res_c[-2]);
passed = 1'b0;
end
if (res_c[-1] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-1], got %b", res_c[-1]);
passed = 1'b0;
end
if (res_c[0] !== 1'b0) begin
$display("Failed res_c[s4], expected 1'b0 for [0], got %b", res_c[0]);
passed = 1'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
module auto_module
( input my_clk,
input my_rst_n,
output manually_listed,
/*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
//ex: input in_pure;
//ex: output out_pure;
/*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
//ex: input req_credit, // To auto_i of auto_intf.sv
//ex: input [63:0] req_data, // To auto_i of auto_intf.sv
//ex: input req_val, // To auto_i of auto_intf.sv
/*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
//ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
//ex: input rsp_credit, // To auto_i of auto_intf.sv
//ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
);
auto_intf auto_i
(// Inputs
.clk (my_clk),
.rst_n (my_rst_n));
/*AUTOASSIGNMODPORT("automodport_if", "req_mon_mp", "auto_i" )*/
//ex: assign auto_i.req_credit = req_credit;
//ex: assign auto_i.req_data = req_data;
//ex: assign auto_i.req_val = req_val;
/*AUTOASSIGNMODPORT("automodport_if", "rsp_drv_mp", "auto_i" )*/
//ex: assign rsp_cmd = auto_i.rsp_cmd;
//ex: assign rsp_data = auto_i.rsp_data;
//ex: assign auto_i.rsp_credit = rsp_credit;
/*AUTOASSIGNMODPORT("automodport_if", "r.*", "auto_i" )*/
initial begin
`cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
`cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXBP_2_V
`define SKY130_FD_SC_LS__SDFXBP_2_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxbp_2 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXBP_2_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& out, const vector<T>& vec) { out << [ ; for (int x : vec) out << x << , ; out << ] ; return out; } int main() { int M; long long N, A, D; cin >> N >> M >> A >> D; vector<long long> T; for (int m = 0; m < M; ++m) { long long t; cin >> t; T.push_back(t); } T.push_back(N * A); ++M; sort(T.begin(), T.end()); long long last = -D - 1; long long ans = 0; for (int i = 0; i < M;) { while (i < M && last >= T[i]) { ++i; } if (i == M) { break; } last = max(last, 0LL); long long u = last / A + 1; if (u < N && u * A < T[i]) { long long v = D / A + 1; long long w = ((T[i] - 1) / A - u) / v + 1; last = A * (u + v * (w - 1)) + D; ans += w; } if (last < T[i]) { last = T[i] + D; ++ans; } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; int n, k, m; int arr[50]; int sub[50]; int result = 0; int task_tot_time = 0; void take(int score, int t) { if (0 >= t) return; int tt = t; int ss = score; for (decltype(0) i = 0; i < k; i++) { int su = sub[i]; while (su > 0) { if (arr[i] > tt) break; ss++; tt -= arr[i]; su--; } } result = max(result, ss); if (t >= task_tot_time) { int task_left = sub[0]; for (decltype(1) i = 1; i < k; i++) task_left = min(task_left, sub[i]); if (task_left == 0) return; for (decltype(0) i = 0; i < k; i++) sub[i]--; result = max(result, score + k + 1); take(score + k + 1, t - task_tot_time); } } int main() { scanf( %d , &n) == 0, scanf( %d , &k) == 0, scanf( %d , &m) == 0; for (decltype(0) i = 0; i < k; i++) { scanf( %d , &arr[i]) == 0; task_tot_time += arr[i]; } for (decltype(0) i = 0; i < k; i++) sub[i] = n; sort(arr, arr + k); take(0, m); printf( %d , result); } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, n, t, x; string s = ; cin >> t; for (i = 0; i < t; i++) { s += o ; } int ara[t + 5]; ara[0] = 1; ara[1] = 1; s[0] = O ; s[1] = O ; for (i = 2; i <= t; i++) { ara[i] = ara[i - 1] + ara[i - 2]; if (ara[i] <= t) s[ara[i] - 1] = O ; if (ara[i] > t) break; else continue; } cout << s << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100; int n, k[N]; double p[N], p_log[N], p_log_1[N]; priority_queue<pair<double, int>> s; inline double P(int i, int k) { double x = pow(p[i], k); if (x > 1e-6) return log(1 - x); x = -x; return x - x * x / 2 + x * x * x / 3; } void add(int i) { s.push(make_pair(P(i, k[i] + 1) - P(i, k[i]), i)); } int main() { ios_base::sync_with_stdio(0), cin.tie(0); cin >> n; if (n == 1) { puts( 1 ); return 0; } for (int i = 0; i < (int)(n); i++) { int a; cin >> a; p[i] = 1 - a * 1e-2; p_log[i] = log(p[i]); p_log_1[i] = log(1 - p[i]); } double sum = 0; int cnt = n; for (int i = 0; i < (int)(n); i++) sum += P(i, k[i] = 1); double res = exp(sum) * cnt; for (int i = 0; i < (int)(n); i++) add(i); while (cnt <= 1e6) { cnt++; int i = s.top().second; s.pop(); sum -= P(i, k[i]); double x = cnt * exp(sum + p_log[i] * k[i]) * (1 - p[i]); res += x; sum += P(i, ++k[i]); add(i); } printf( %.15f n , (double)res); fprintf(stderr, time = %.2f, cnt = %d n , 1. * clock() / CLOCKS_PER_SEC, cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, c, d[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> a >> b >> c; a = a % b; d[a]++; int t; for (int i = 1; i <= 100005; ++i) { t = a * 10 / b; if (t == c) { cout << i; exit(0); } a = ((a * 10) % b); d[a]++; if (d[a] == 2) { cout << -1 ; exit(0); } } } |
#include <bits/stdc++.h> using namespace std; set<int> st[2]; map<int, int> mp; int ar[110]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> ar[i]; mp[ar[i]]++; } int idx = 0; map<int, int>::iterator it1; for (it1 = mp.begin(); it1 != mp.end(); it1++) { if (it1->second == 1) { st[idx].insert(it1->first); idx = !idx; } } if (st[0].size() == st[1].size()) { string ans(n, A ); for (int i = 0; i < n; i++) { if (st[1].count(ar[i])) ans[i] = B ; } cout << YES n ; for (int i = 0; i < n; i++) cout << ans[i]; return 0; } else { string res(n, A ); for (int i = 0; i < n; i++) { if (st[1].count(ar[i])) { res[i] = B ; } } int id = -1; map<int, int>::iterator it; for (it = mp.begin(); it != mp.end(); it++) { if (it->second >= 3) { id = it->first; break; } } if (id == -1) { cout << NO ; return 0; } bool flag = false; for (int i = 0; i < n; i++) { if (ar[i] == id) { if (!flag) { flag = true; res[i] = B ; } } } cout << YES n ; for (int i = 0; i < n; i++) { cout << res[i]; } return 0; } return 0; } |
`include "delay.v"
`include "arbiter.v"
module uartmm(input clk,
input rst,
input RX,
output TX,
output [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
wire uart_RXD;
inpin _rcxd(.clk(clk), .pin(RX), .rd(uart_RXD));
reg qin_we, qin_re, qout_we, qout_re;
wire qout_oready, qin_oready;
wire [7:0] qin_idata;
reg [7:0] qout_idata;
wire [7:0] qin_wdata;
wire [7:0] qout_wdata;
wire uart_valid, uart_busy;
// Insert the byte incoming from mm port 65539 into the uart output queue, if
// queue is not full.
always @(posedge clk)
if (!rst) begin
qout_we <= 0;
qout_idata <= 0;
end else
if (qout_we) begin
qout_we <= 0;
end else if ((addr_b == 65539) & data_b_we &
!qin_full) begin
qout_idata <= data_b[7:0];
qout_we <= 1;
end
// If uart is ready to transmit and the output queue is not empty, send one byte
always @(posedge clk)
if (!rst) qout_re <= 0;
else if (qout_re) begin
qout_re <= 0;
end
else if (qout_oready & !uart_busy) begin
qout_re <= 1;
end
// If uart has a valid output, push it into the input queue
always @(posedge clk)
if (!rst) begin
qin_we <= 0;
end else if (qin_we) begin
qin_we <= 0;
end else if (uart_valid & !qin_full) begin
qin_we <= 1;
end
reg cmd;
wire addr_b_cmd =
(addr_b == 65539);
reg out_tmp;
assign data_b = cmd?{24'b0,qin_wdata}:{30'b0,out_tmp};
// Manage the output
always @(posedge clk)
if (!rst) begin
cmd <= 0;
qin_re <= 0;
out_tmp <= 0;
strobe_b <= 0;
end else begin
cmd <= addr_b_cmd;
if (qin_re) qin_re <= 0;
else if ((addr_b == 65539) & qin_oready) begin // UART DATA IN
qin_re <= 1;
strobe_b <= 1;
end else if (addr_b == 65537) begin // UART IN READY
out_tmp <= qin_oready;
strobe_b <= 1;
end else if (addr_b == 65538) begin // UART OUT READY
out_tmp <= !qout_full;
strobe_b <= 1;
end else strobe_b <= 0;
end
// Modules
delayqueue _qin (.clk(clk),
.rst(rst),
.we(qin_we),
.idata(qin_idata),
.re(qin_re),
.wdata(qin_wdata),
.oready(qin_oready),
.full(qin_full));
delayqueue _qout (.clk(clk),
.rst(rst),
.we(qout_we),
.idata(qout_idata),
.re(qout_re),
.wdata(qout_wdata),
.oready(qout_oready),
.full(qout_full));
buart _uart (
.clk(clk),
.resetq(rst),
.rx(uart_RXD),
.tx(TX),
.rd(qin_we),
.wr(qout_re),
.valid(uart_valid),
.busy(uart_busy),
.tx_data(qout_wdata),
.rx_data(qin_idata));
endmodule
module ledwriter (input clk,
input rst,
output reg [7:0] LED,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
always @(posedge clk)
if (~rst) begin
LED <= 0;
end else begin
if (addr_b == 65540)
LED <= data_b_in[7:0];
end
endmodule
// TODO:
// implement a 2-port RAM by using a double clock frequency + a single port
`define STR(a) `"a`"
`ifndef C2_RAM_DEPTH
`define C2_RAM_DEPTH 1024
`endif
module socram(input clk,
input rst,
output reg [31:0] data_a,
input [31:0] addr_a,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
parameter RAM_DEPTH = `C2_RAM_DEPTH;
parameter INIT_FILE = `STR(`INIT_FILE_PATH);
reg [31:0] mem [0:RAM_DEPTH-1];
initial begin
if (INIT_FILE != "")
$readmemh(INIT_FILE, mem);
end
always @(posedge clk)
begin
if (data_b_we & (addr_b[31:16] == 0)) begin
mem[addr_b] <= data_b_in;
end
data_a <= mem[addr_a];
data_b <= mem[addr_b];
strobe_b <= (addr_b[31:16] == 0);
end
endmodule // socram
module mul16x16 (input [15:0] a,
input [15:0] b,
output [31:0] o);
assign o = a * b;
endmodule // mul16x16
module hls_Mul(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire [15:0] a = p0r[31:16];
wire [15:0] b = p0r[15:0];
wire [15:0] c = p1r[31:16];
wire [15:0] d = p1r[15:0];
wire [15:0] ad = a * d;
wire [15:0] bc = b * c;
wire [31:0] bd = b * d;
reg [15:0] adr;
reg [31:0] p0r;
reg [31:0] p1r;
reg [31:0] t1;
reg [31:0] t2;
assign out = t2;
always @(posedge clk)
begin
p0r <= p0; p1r <= p1;
t1 <= bd + {bc[15:0], 16'b0}; adr <= ad[15:0];
t2 <= t1 + {adr[15:0], 16'b0};
end
endmodule // hls_Mul
`include "../rtl/mul.v"
module hls_MulFSM(input clk,
input reset,
input req,
output ack,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
mul32x32_fsm S(.clk(clk),
.rst(reset),
.req(req),
.ack(ack),
.p0(p0),
.p1(p1),
.out(out));
endmodule // hls_MulFSM
`include "vgafifo.v"
`include "vga640x480ice.v"
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_2_V
`define SKY130_FD_SC_HD__O221AI_2_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_2_V
|
#include <bits/stdc++.h> const int inf = INT_MAX; const int MAX = 1e3 + 8; const long long MOD = 1e9 + 7; const int TOT_PRIMES = 1e6 + 9; const int MAX_A = 71; const int LN = 20; using namespace std; int main() { int n, k; cin >> n >> k; int a[32]; memset(a, 0, sizeof(a)); for (int i = 0; i < n; i++) { int res = 0; for (int j = 0; j < k; j++) { int x; cin >> x; res = x + res * 2; } a[res] = 1; } int f = 0; for (int i = 0; i < (1 << k); i++) { for (int j = 0; j < (1 << k); j++) { if ((!(i & j)) && a[i] && a[j]) f = 1; } } if (f) cout << YES ; else cout << NO ; } |
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module rx_data_control_p(
input posedge_clk,
input rx_resetn,
input bit_c_3,
input bit_c_2,
input bit_c_1,
input bit_c_0,
input bit_d_9,
input bit_d_8,
input bit_d_0,
input bit_d_1,
input bit_d_2,
input bit_d_3,
input bit_d_4,
input bit_d_5,
input bit_d_6,
input bit_d_7,
input last_is_control,
input last_is_data,
input is_control,
input [5:0] counter_neg,
output reg [8:0] dta_timec_p,
output reg parity_rec_d,
output reg parity_rec_d_gen,
output reg [2:0] control_p_r,
output reg [2:0] control_l_r,
output reg parity_rec_c,
output reg parity_rec_c_gen
);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
parity_rec_d <= 1'b0;
parity_rec_d_gen <= 1'b0;
dta_timec_p <= 9'd0;
end
else
begin
if(!is_control && counter_neg == 6'd32)
begin
dta_timec_p <= {bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
parity_rec_d <= bit_d_9;
if(last_is_control)
begin
parity_rec_d_gen <= !(bit_d_8^control_p_r[0]^control_p_r[1]);
end
else if(last_is_data)
begin
parity_rec_d_gen <= !(bit_d_8^dta_timec_p[7]^dta_timec_p[6]^dta_timec_p[5]^dta_timec_p[4]^dta_timec_p[3]^dta_timec_p[2]^dta_timec_p[1]^dta_timec_p[0]);
end
end
else
begin
dta_timec_p <= dta_timec_p;
parity_rec_d <= parity_rec_d;
parity_rec_d_gen <= parity_rec_d_gen;
end
end
end
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
control_p_r <= 3'd0;
control_l_r <= 3'd0;
parity_rec_c <= 1'b0;
parity_rec_c_gen<= 1'b0;
end
else
begin
if(!is_control && counter_neg == 6'd32)
begin
control_p_r <= 3'd0;
control_l_r <= 3'd0;
end
else if(is_control && counter_neg == 6'd4)
begin
control_p_r <= {bit_c_2,bit_c_1,bit_c_0};
control_l_r <= control_p_r;
parity_rec_c <= bit_c_3;
if(last_is_control)
begin
parity_rec_c_gen <= !(bit_c_2^control_p_r[0]^control_p_r[1]);
end
else if(last_is_data)
begin
parity_rec_c_gen <= !(bit_c_2^dta_timec_p[7]^dta_timec_p[6]^dta_timec_p[5]^dta_timec_p[4]^dta_timec_p[3]^dta_timec_p[2]^dta_timec_p[1]^dta_timec_p[0]);
end
end
else
begin
control_p_r <= control_p_r;
parity_rec_c <= parity_rec_c;
parity_rec_c_gen <= parity_rec_c_gen;
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9144_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac_data_2_3,
dac_data_3_0,
dac_data_3_1,
dac_data_3_2,
dac_data_3_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [255:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
input [15:0] dac_data_2_0;
input [15:0] dac_data_2_1;
input [15:0] dac_data_2_2;
input [15:0] dac_data_2_3;
input [15:0] dac_data_3_0;
input [15:0] dac_data_3_1;
input [15:0] dac_data_3_2;
input [15:0] dac_data_3_3;
// internal registers
reg [255:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 256'd0;
end else begin
tx_data[255:248] <= dac_data_3_3[ 7: 0];
tx_data[247:240] <= dac_data_3_2[ 7: 0];
tx_data[239:232] <= dac_data_3_1[ 7: 0];
tx_data[231:224] <= dac_data_3_0[ 7: 0];
tx_data[223:216] <= dac_data_3_3[15: 8];
tx_data[215:208] <= dac_data_3_2[15: 8];
tx_data[207:200] <= dac_data_3_1[15: 8];
tx_data[199:192] <= dac_data_3_0[15: 8];
tx_data[191:184] <= dac_data_2_3[ 7: 0];
tx_data[183:176] <= dac_data_2_2[ 7: 0];
tx_data[175:168] <= dac_data_2_1[ 7: 0];
tx_data[167:160] <= dac_data_2_0[ 7: 0];
tx_data[159:152] <= dac_data_2_3[15: 8];
tx_data[151:144] <= dac_data_2_2[15: 8];
tx_data[143:136] <= dac_data_2_1[15: 8];
tx_data[135:128] <= dac_data_2_0[15: 8];
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns/1ps
module ntsc_gen(clk,v_sync,v_data);
parameter DATA_BITS = 4;
input clk;
output reg [DATA_BITS-1:0] v_data;
output v_sync;
wire [DATA_BITS-1:0] data;
wire [DATA_BITS-1:0] sync;
//50 Mhz clock
reg [9:0] xpos = 0;
reg [8:0] ypos = 0;
reg [3:0] counter = 0;
reg [7:0] colorburst = 8'b01100100;
always @(posedge clk) begin
colorburst <= {colorburst[5:0],colorburst[7:6]};
if(xpos == 903) begin
xpos <= 0;
if(ypos == 261)
ypos <= 0;
else
ypos <= ypos + 1;
end
else
xpos <= xpos + 1;
end
wire active = xpos < 640 && ypos < 200;
wire hsync = 717 <= xpos && xpos < 784;
wire vsync = 224 <= ypos && ypos < 227;
wire burst = 798 <= xpos && xpos < 834 ;
assign data = active ? {colorburst[5:4] + (ypos[5] ? colorburst[3:2] : colorburst[7:6]),2'b0} :0;
assign sync = (!(hsync || vsync)) ? 4'b0011 : 4'b0000;
assign v_sync = active || !(hsync || vsync);
//assign v_data = ((data+v_sync) <= (1<<DATA_BITS) - 1) ? (data+v_sync) : 2'b11;
always @*
if(burst)
v_data = colorburst[1:0] + sync - 1;
else
v_data <= data + sync;
endmodule
|
#include <bits/stdc++.h> const int maxn = 100000 + 5; using namespace std; int main() { int n, a[maxn]; cin >> n; bool flag = false; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (int i = 2; i < n; i++) { int x = a[i], y = a[i - 1]; int z = a[i - 2]; if ((y + z) > x && (x - y) < z) flag = true; } if (flag) cout << YES ; else cout << NO ; return 0; } |
`default_nettype none
module gci_std_display_data_read #(
parameter P_AREA_H = 640,
parameter P_AREA_Y = 480,
parameter P_READ_FIFO_DEPTH = 64,
parameter P_READ_FIFO_DEPTH_N = 6,
parameter P_MEM_ADDR_N = 19
)(
//System
input wire iGCI_CLOCK,
input wire iDISP_CLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Read Request
input wire iRD_ENA,
input wire iRD_SYNC,
output wire oRD_VALID,
output wire [7:0] oRD_DATA_R,
output wire [7:0] oRD_DATA_G,
output wire [7:0] oRD_DATA_B,
//Memory IF
output wire oIF_REQ,
input wire iIF_ACK,
output wire oIF_FINISH,
output wire oIF_ENA,
input wire iIF_BUSY,
output wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
input wire iIF_VALID,
input wire [31:0] iIF_DATA
);
//Main State
localparam P_L_MAIN_STT_IDLE = 2'h0;
localparam P_L_MAIN_STT_IF_REQ = 2'h1;
localparam P_L_MAIN_STT_WORK = 2'h2;
localparam P_L_MAIN_STT_IF_FINISH = 2'h3;
//Read State
localparam P_L_READ_STT_IDLE = 1'h0;
localparam P_L_READ_STT_READ = 1'h1;
localparam P_L_READ_STT_END = 1'h2;
//Main State
reg [1:0] b_main_state;
//Read State
reg b_read_state;
reg [P_MEM_ADDR_N-1:0] b_read_addr;
reg [P_READ_FIFO_DEPTH_N-1:0] b_read_count;
//FIFO
wire vramfifo0_full;
wire vramfifo0_empty;
wire [23:0] vramfifo0_data;
wire vramfifo1_full;
wire vramfifo1_empty;
wire [7:0] vramfifo1_data_r, vramfifo1_data_g, vramfifo1_data_b;
//Output Buffer
reg b_out_buff_valid;
reg [7:0] b_out_buff_r, b_out_buff_g, b_out_buff_b;
//Condition
wire if_request_condition = vramfifo0_empty;
wire read_state_start_condition = (b_main_state == P_L_MAIN_STT_WORK);
/***************************************************
Main State
***************************************************/
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
else if(iRESET_SYNC)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
else begin
case(b_main_state)
P_L_MAIN_STT_IDLE:
begin
if(if_request_condition)begin
b_main_state <= P_L_MAIN_STT_IF_REQ;
end
end
P_L_MAIN_STT_IF_REQ:
begin
if(iIF_ACK)begin
b_main_state <= P_L_MAIN_STT_WORK;
end
end
P_L_MAIN_STT_WORK:
begin
if(b_read_state == P_L_READ_STT_END)begin
b_main_state <= P_L_MAIN_STT_IF_FINISH;
end
end
P_L_MAIN_STT_IF_FINISH:
begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
endcase
end
end
/***************************************************
Read State
***************************************************/
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_read_state <= P_L_READ_STT_IDLE;
b_read_addr <= {P_MEM_ADDR_N{1'b0}};
b_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
end
else if(iRESET_SYNC)begin
b_read_state <= P_L_READ_STT_IDLE;
b_read_addr <= {P_MEM_ADDR_N{1'b0}};
b_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
end
else begin
case(b_read_state)
P_L_READ_STT_IDLE:
begin
b_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
if(read_state_start_condition)begin
b_read_state <= P_L_READ_STT_READ;
end
end
P_L_READ_STT_READ:
begin
if(b_read_count < {P_READ_FIFO_DEPTH_N{1'b0}})begin
if(!iIF_BUSY)begin //Busy Check
b_read_addr <= func_read_next_addr(b_read_addr);
b_read_count <= b_read_count + {{P_READ_FIFO_DEPTH_N-1{1'b0}}, 1'b1};
end
end
else begin
b_read_state <= P_L_READ_STT_END;
end
end
P_L_READ_STT_END:
begin
b_read_state <= P_L_READ_STT_IDLE;
end
default:
begin
b_read_state <= P_L_READ_STT_IDLE;
end
endcase
end
end //Read State
function [P_MEM_ADDR_N-1:0] func_read_next_addr;
input [P_MEM_ADDR_N-1:0] func_now_addr;
begin
if(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin
func_read_next_addr = func_now_addr + 1;
end
else begin
func_read_next_addr = {P_MEM_ADDR_N{1'b0}};
end
end
endfunction
/***************************************************
Output FIFO
***************************************************/
gci_std_sync_fifo #(24, P_READ_FIFO_DEPTH, P_READ_FIFO_DEPTH_N) VRAMREAD_FIFO0(
.inRESET(inRESET),
.iREMOVE(iRESET_SYNC),
.iCLOCK(iGCI_CLOCK),
.iWR_EN(iIF_VALID && !vramfifo0_full),
.iWR_DATA(iIF_DATA[23:0]),
.oWR_FULL(vramfifo0_full),
.oWR_ALMOST_FULL(),
.iRD_EN(!vramfifo0_empty && !vramfifo1_full),
.oRD_DATA(vramfifo0_data),
.oRD_EMPTY(vramfifo0_empty)
);
gci_std_async_fifo #(24, P_READ_FIFO_DEPTH, P_READ_FIFO_DEPTH_N) VRAMREAD_FIFO1(
.inRESET(inRESET),
.iREMOVE(iRESET_SYNC),
.iWR_CLOCK(iGCI_CLOCK),
.iWR_EN(!vramfifo0_empty && !vramfifo1_full),
.iWR_DATA(vramfifo0_data),
.oWR_FULL(vramfifo1_full),
.iRD_CLOCK(iDISP_CLOCK),
.iRD_EN(!vramfifo1_empty && iRD_ENA),
.oRD_DATA({vramfifo1_data_r, vramfifo1_data_g, vramfifo1_data_b}),
.oRD_EMPTY(vramfifo1_empty)
);
/***************************************************
Output Buffer
***************************************************/
always@(posedge iDISP_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_out_buff_valid <= 1'b0;
b_out_buff_r <= 8'h0;
b_out_buff_g <= 8'h0;
b_out_buff_b <= 8'h0;
end
else begin
b_out_buff_valid <= iRD_ENA;
b_out_buff_r <= vramfifo1_data_r;
b_out_buff_g <= vramfifo1_data_g;
b_out_buff_b <= vramfifo1_data_b;
end
end
/***************************************************
Assign
***************************************************/
assign oRD_VALID = b_out_buff_valid;
assign oRD_DATA_R = b_out_buff_r;
assign oRD_DATA_G = b_out_buff_g;
assign oRD_DATA_B = b_out_buff_b;
assign oIF_REQ = (b_main_state == P_L_MAIN_STT_IF_REQ);
assign oIF_FINISH = (b_main_state == P_L_MAIN_STT_IF_FINISH);
assign oIF_ENA = !iIF_BUSY && (b_read_state == P_L_READ_STT_READ);
assign oIF_ADDR = b_read_addr;
/***************************************************
Assertion
***************************************************/
`ifdef GCI_STD_DISP_SVA_ASSERTION
proterty PRO_FIFO_NEVER_NOT_EMPTY;
@(posedge iDISP_CLOCK) disable iff (!inRESET) (!vramfifo1_empty |=> !vramfifo1_empty);
endproperty
assert property(PRO_FIFO_NEVER_NOT_EMPTY);
`endif
endmodule
`default_nettype wire
|
`timescale 1 ns / 1 ps
module system (
input clk,
input resetn,
output trap,
output reg [7:0] out_byte,
output reg out_byte_en
);
// 0x2000 32bit words = 0x8000 Byte = 32kByte memory
parameter MEMW_SIZE = 16'h8000;
integer tb_idx;
wire mem_valid;
wire mem_instr;
reg mem_ready;
reg mem_ready_last;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
wire uart_cs;
wire [3:0] uart_wstrb;
wire [31:0] uart_rdata;
wire [31:0] irqs;
wire [31:0] eois;
picorv32 picorv32_core (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.irq(irqs),
.eoi(eois)
);
`ifndef MEM_FILENAME
simuart uart(
.clk(clk),
.cs(uart_cs),
.bus_addr(mem_addr),
.bus_wr_val(mem_wdata),
.bus_bytesel(uart_wstrb),
.bus_ack(),
.bus_data(uart_rdata),
.inter(irqs[0]),
.intack(eois[0])
);
`else
assign uart_rdata = 32'b0;
assign irqs = 32'b0;
`endif
assign irqs[31:1] = 31'b0;
assign uart_cs = mem_addr[31:4] == 28'h1000000 && mem_valid;
assign uart_wstrb = mem_wstrb & mem_ready;
reg [31:0] memory [0:MEMW_SIZE-1];
initial begin
for (tb_idx=0; tb_idx < MEMW_SIZE; tb_idx=tb_idx+1)
memory[tb_idx] = 32'b0;
`ifdef MEM_FILENAME
$readmemh(`MEM_FILENAME, memory);
`else
$readmemh("../firmware.hex", memory);
`endif
end
reg [31:0] m_read_data;
reg m_read_en;
always @(posedge clk) begin
m_read_en <= 0;
mem_ready <= mem_valid && !mem_ready_last && !mem_ready && m_read_en;
mem_ready_last <= mem_ready;
out_byte_en <= 0;
(* parallel_case *)
case (1)
mem_valid && !mem_ready && !mem_wstrb && (mem_addr >> 2) < MEMW_SIZE: begin
m_read_en <= 1;
m_read_data <= memory[mem_addr >> 2];
mem_rdata <= m_read_data;
end
mem_valid && !mem_ready && |mem_wstrb && (mem_addr >> 2) < MEMW_SIZE: begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
mem_ready <= 1;
end
mem_valid && !mem_ready && !mem_wstrb && uart_cs: begin
m_read_en <= 1;
mem_rdata <= uart_rdata;
//mem_rdata <= m_read_data;
end
mem_valid && !mem_ready && |mem_wstrb && mem_addr == 32'h2000_0000: begin
out_byte_en <= 1;
out_byte <= mem_wdata;
mem_ready <= 1;
end
mem_valid && !mem_ready && |mem_wstrb : begin
mem_ready <= 1;
end
endcase
if (resetn && out_byte_en) begin
$write("%c", out_byte);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_TB_V
`define SKY130_FD_SC_HD__A31O_TB_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__a31o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_TB_V
|
#include <bits/stdc++.h> using namespace std; int cap[1000000], flow[1000000]; int to[1000000], _prev[1000000], last[10000], used[10000], level[10000]; struct MaxFlow { int V, E; MaxFlow(int n) { int i; V = n; E = 0; for ((i) = 0; (i) < (int)(V); (i)++) last[i] = -1; } void add_edge(int x, int y, int f) { cap[E] = f; flow[E] = 0; to[E] = y; _prev[E] = last[x]; last[x] = E; E++; cap[E] = 0; flow[E] = 0; to[E] = x; _prev[E] = last[y]; last[y] = E; E++; } bool bfs(int s, int t) { int i; for ((i) = 0; (i) < (int)(V); (i)++) level[i] = -1; queue<int> q; q.push(s); level[s] = 0; while (!q.empty()) { int x = q.front(); q.pop(); for (i = last[x]; i >= 0; i = _prev[i]) if (level[to[i]] == -1 && cap[i] > flow[i]) { q.push(to[i]); level[to[i]] = level[x] + 1; } } return (level[t] != -1); } int dfs(int v, int t, int f) { int i; if (v == t) return f; for (i = used[v]; i >= 0; used[v] = i = _prev[i]) if (level[to[i]] > level[v] && cap[i] > flow[i]) { int tmp = dfs(to[i], t, min(f, cap[i] - flow[i])); if (tmp > 0) { flow[i] += tmp; flow[i ^ 1] -= tmp; return tmp; } } return 0; } int maxflow(int s, int t) { int i; while (bfs(s, t)) { for ((i) = 0; (i) < (int)(V); (i)++) used[i] = last[i]; while (dfs(s, t, (1 << 29)) != 0) ; } int ans = 0; for (i = last[s]; i >= 0; i = _prev[i]) ans += flow[i]; return ans; } }; int dx[] = {1, -1, 0, 0}, dy[] = {0, 0, 1, -1}; int X, Y; string board[30]; int dist[30][30][30][30]; int A, B; int cx, cy, ct; int ax[500], ay[500], at[500]; int bx[500], by[500], bt[500]; queue<int> q; void bfs(int s, int t) { int i, j; for ((i) = 0; (i) < (int)(X); (i)++) for ((j) = 0; (j) < (int)(Y); (j)++) dist[s][t][i][j] = (1 << 29); if (board[s][t] == # ) return; dist[s][t][s][t] = 0; q.push(s); q.push(t); while (!q.empty()) { int x = q.front(); q.pop(); int y = q.front(); q.pop(); for ((i) = 0; (i) < (int)(4); (i)++) { int x2 = x + dx[i], y2 = y + dy[i]; if (x2 >= 0 && x2 < X && y2 >= 0 && y2 < Y && board[x2][y2] != # && dist[s][t][x2][y2] == (1 << 29)) { dist[s][t][x2][y2] = dist[s][t][x][y] + 1; q.push(x2); q.push(y2); } } } } bool check(long long T) { int i, j, k; MaxFlow mf(A + A + 2 * (X * Y) + 2); int V = A + A + 2 * (X * Y) + 2; for ((i) = 0; (i) < (int)(A); (i)++) mf.add_edge(V - 2, i, 1); for ((i) = 0; (i) < (int)(A); (i)++) mf.add_edge(A + i, V - 1, 1); for ((i) = 0; (i) < (int)(X * Y); (i)++) mf.add_edge(A + A + i, A + A + X * Y + i, 1); for ((i) = 0; (i) < (int)(A); (i)++) for ((j) = 0; (j) < (int)(X); (j)++) for ((k) = 0; (k) < (int)(Y); (k)++) { int d = dist[ax[i]][ay[i]][j][k]; if (d != (1 << 29) && (long long)d * at[i] <= T) mf.add_edge(i, A + A + j * Y + k, 1); } for ((i) = 0; (i) < (int)(A); (i)++) for ((j) = 0; (j) < (int)(X); (j)++) for ((k) = 0; (k) < (int)(Y); (k)++) { int d = dist[bx[i]][by[i]][j][k]; if (d != (1 << 29) && (long long)d * bt[i] <= T) mf.add_edge(A + A + X * Y + j * Y + k, A + i, 1); } int f = mf.maxflow(V - 2, V - 1); return (f == A); } int main(void) { int i, j; cin >> X >> Y >> A >> B; for ((i) = 0; (i) < (int)(X); (i)++) cin >> board[i]; for ((i) = 0; (i) < (int)(X); (i)++) for ((j) = 0; (j) < (int)(Y); (j)++) bfs(i, j); cin >> cx >> cy >> ct; for ((i) = 0; (i) < (int)(A); (i)++) cin >> ax[i] >> ay[i] >> at[i]; for ((i) = 0; (i) < (int)(B); (i)++) cin >> bx[i] >> by[i] >> bt[i]; cx--; cy--; for ((i) = 0; (i) < (int)(A); (i)++) { ax[i]--; ay[i]--; } for ((i) = 0; (i) < (int)(B); (i)++) { bx[i]--; by[i]--; } if (A < B) { ax[A] = cx; ay[A] = cy; at[A] = ct; A++; } else { bx[B] = cx; by[B] = cy; bt[B] = ct; B++; } if (A != B) { cout << -1 << endl; return 0; } long long low = -1, high = (1ll << 40); while (high - low > 1) { long long mid = (low + high) / 2; if (check(mid)) high = mid; else low = mid; } if (high == (1ll << 40)) high = -1; cout << high << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); char input[n + 5][n + 5]; for (int i = 0; i < n; i++) scanf( %s , input[i]); int row[n], col[n], count_row = 0, count_col = 0; for (int i = 0; i < n; i++) row[i] = -1; for (int j = 0; j < n; j++) col[j] = -1; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { if (input[i][j] == . ) { row[i] = j; col[j] = i; } } for (int i = 0; i < n; i++) { if (row[i] != -1) count_row++; if (col[i] != -1) count_col++; } if (count_row != n && count_col != n) printf( -1 n ); else if (count_row == n) { for (int i = 0; i < n; i++) printf( %d %d n , i + 1, row[i] + 1); } else for (int j = 0; j < n; j++) printf( %d %d n , col[j] + 1, j + 1); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_BLACKBOX_V
/**
* top_power_hvc_wpad: A power pad with an ESD high-voltage clamp.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpad (
P_PAD ,
AMUXBUS_A ,
AMUXBUS_B ,
OGC_HVC ,
DRN_HVC ,
SRC_BDY_HVC,
P_CORE ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
inout P_PAD ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout OGC_HVC ;
inout DRN_HVC ;
inout SRC_BDY_HVC;
inout P_CORE ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_BLACKBOX_V
|
//IEEE Floating Point Multiplier (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [47:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
//if a is zero return NaN
if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[47:24];
guard <= product[23];
round_bit <= product[22];
sticky <= (product[21:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_FUNCTIONAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvpwrvgnd ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_4_V
`define SKY130_FD_SC_MS__AND4_4_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_4_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e6 + 7; struct Data { long long min, max, resl, resr; }; struct TNode { long long L, R; TNode *left, *right; Data d; long long val; }; TNode *new_node(long long L, long long R) { return new TNode({L, R, nullptr, nullptr, {INF, -1, -1, -1}, 0}); } Data safe(TNode *root) { if (!root) { return {INF, -1, -1, -1}; } return root->d; } Data upd(Data a, Data b) { Data c; c.min = min(a.min, b.min); c.max = max(a.max, b.max); c.resl = max({a.resl, b.resl, a.max - 2 * b.min}); c.resr = max({a.resr, b.resr, b.max - 2 * a.min}); return c; } void relax(TNode *root) { if (!root) return; root->d = upd(safe(root->left), safe(root->right)); } void add_val(TNode *root, long long val) { if (!root) return; root->val += val; (root->d).min += val; (root->d).max += val; (root->d).resl -= val; (root->d).resr -= val; } void push(TNode *root) { if (!root) return; add_val(root->left, root->val); add_val(root->right, root->val); root->val = 0; } vector<long long> pref; TNode *build_tree(long long L, long long R) { TNode *root = new_node(L, R); if (R - L == 1) { root->d = {pref[L], pref[L], -pref[L], -pref[L]}; } else { long long M = (L + R) / 2; root->left = build_tree(L, M); root->right = build_tree(M, R); relax(root); } return root; } void add_seg(TNode *root, long long L, long long R, long long val) { if (L >= root->R || root->L >= R) { return; } if (L <= root->L && root->R <= R) { add_val(root, val); return; } push(root); add_seg(root->left, L, R, val); add_seg(root->right, L, R, val); relax(root); } Data get_res(TNode *root, long long L, long long R) { if (L >= root->R || root->L >= R) { return {INF, -1, -1, -1}; } if (L <= root->L && root->R <= R) { return root->d; } push(root); Data res = upd(get_res(root->left, L, R), get_res(root->right, L, R)); relax(root); return res; } long long m; pair<long long, long long> get_max(TNode *root) { if (root->R - root->L == 1) { return {(root->d).max, root->L}; } push(root); pair<long long, long long> ret; if (safe(root->left).max > safe(root->right).max) { ret = get_max(root->left); } else { ret = get_max(root->right); } relax(root); return ret; } void print(TNode *root) { if (root->R - root->L == 1) { cout << (root->d).max << ; return; } push(root); print(root->left); print(root->right); relax(root); } long long query(TNode *root) { auto t = get_max(root); long long pos = t.second, val = t.first; Data a = get_res(root, 0, pos); Data b = get_res(root, pos + 1, m); return max(max(a.resl, b.resr) + val, 0LL); } int main() { ios_base::sync_with_stdio(false); long long n, q; cin >> n >> q; string s; cin >> s; pref.push_back(0); for (long long i = 0; i < 2 * (n - 1); i++) { pref.push_back(pref.back() + (s[i] == ( ? 1 : -1)); } m = 2 * n - 1; TNode *root = build_tree(0, m); cout << query(root) << n ; for (long long i = 0; i < q; i++) { long long a, b; cin >> a >> b; a--, b--; if (a > b) swap(a, b); if (s[a] != s[b]) { if (s[a] == ( ) { add_seg(root, a + 1, b + 1, -2); } else { add_seg(root, a + 1, b + 1, 2); } swap(s[a], s[b]); } cout << query(root) << n ; } } |
`timescale 1ns / 1ps
`define SIMULATION
module div_16_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg init_in;
reg [15:0]A;
reg [15:0]B;
wire [15:0] Result;
wire done;
div_16 uut (.clk(clk) , .rst(rst) , .init_in(start) , .A(A) , .B(B) , .Result(Result) , .done(done));
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; A = 16'd35; B = 16'd5; //in_A = 8'hAA; in_B = 8'h24; 41/9 = 4*9 +5
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
end
end
initial begin: TEST_CASE
$dumpfile("div_16_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*120) $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long solve(int n) { int x = n; long long cnt = 0, ans = 0; while (x) { x = x / 10; cnt++; } ans = n * cnt + cnt - 1; int k = 1; for (int i = 0; i < cnt - 1; i++) { k = k * 10; ans = ans - k; } return ans; } int main() { int n; long long ans; scanf( %d , &n); if (n < 10) { cout << n; } else { cout << solve(n); } return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 48, ch = getchar(); } return x * f; } bool vis[1000100]; int c[100]; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int main() { srand(time(0)); int n = read(), que = 60; int l = 0, r = 1e9, op; while (l <= r) { int mid = (l + r) / 2; que--; printf( > %d n , mid); fflush(stdout); scanf( %d , &op); if (op) l = mid + 1; else r = mid - 1; } int mx = l; for (int i = 1; i <= que && i <= n; i++) { int p = rand() * rand() % n + 1; while (vis[p]) p = rand() * rand() % n + 1; vis[p] = 1; printf( ? %d n , p); fflush(stdout); scanf( %d , &c[i]); } int N = min(que, n); sort(c + 1, c + N + 1); int g = mx - c[1]; for (int i = 2; i <= N; i++) { if (c[i] == mx) continue; g = gcd(g, mx - c[i]); g = gcd(g, c[i] - c[i - 1]); } printf( ! %d %d n , mx - (n - 1) * g, g); fflush(stdout); return 0; } |
#include <bits/stdc++.h> using namespace std; inline void smin(int &a, const int &b) { if (b < a) a = b; } inline void smax(int &a, const int &b) { if (b > a) a = b; } int first[4], second[4], f[4], ans; vector<int> dst, vx, vy; pair<int, int> p[4], mp[4]; inline void solve(int X, int Y, int d) { p[0] = pair<int, int>(X, Y), p[1] = pair<int, int>(X, Y + d), X += d; p[2] = pair<int, int>(X, Y), p[3] = pair<int, int>(X, Y + d); for (int i = 4; i--;) f[i] = i; do { int mx = 0; for (int i = 4; i--;) { if (first[i] == p[f[i]].first) smax(mx, abs(second[i] - p[f[i]].second)); else if (second[i] == p[f[i]].second) smax(mx, abs(first[i] - p[f[i]].first)); else mx = 0x3f3f3f3f; } if (mx < ans) { ans = mx; for (int i = 4; i--;) mp[i] = p[f[i]]; } } while (next_permutation(f, f + 4)); } inline void solve(int d) { vx.clear(), vy.clear(); for (int i = 4; i--;) { vx.push_back(first[i] - d), vx.push_back(first[i]), vx.push_back(first[i] + d); vy.push_back(second[i] - d), vy.push_back(second[i]), vy.push_back(second[i] + d); for (int j = i; j--;) { int xmn = min(first[i], first[j]), xmx = max(first[i], first[j]); int ymn = min(second[i], second[j]), ymx = max(second[i], second[j]); for (int k = 4; k--;) if (k != i && k != j) { smin(xmn, first[k] - d), smax(xmx, first[k] - d); smin(ymn, second[k] - d), smax(ymx, second[k] - d); } vx.push_back(xmn + xmx >> 1), vy.push_back(ymn + ymx >> 1); } } for (int first : vx) for (int second : vy) solve(first, second, d); } int main() { int t; scanf( %d , &t); while (t--) { dst.clear(); for (int i = 0; i < 4; i++) { scanf( %d %d , first + i, second + i); for (int j = 0; j < i; j++) { dst.push_back(abs(first[i] - first[j])); dst.push_back(abs(second[i] - second[j])); } } sort(dst.begin(), dst.end()); dst.resize(unique(dst.begin(), dst.end()) - dst.begin()); ans = 0x3f3f3f3f; for (int first : dst) solve(first); if (ans < 0x3f3f3f3f) { printf( %d n , ans); for (int i = 0; i < 4; i++) printf( %d %d n , mp[i].first, mp[i].second); } else puts( -1 ); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtp (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, GATE, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_SYMBOL_V
`define SKY130_FD_SC_LP__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_SYMBOL_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; int V[100]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int T; cin >> T; while (T--) { int K; cin >> K; const int R = 2 * K + 1; N = 2 * R; int p0 = -1; for (int i = 0; i < N; i++) { string s; cin >> s; if (s == E ) { V[i] = 0; p0 = i; } else { V[i] = stoi(s); } } assert(p0 != -1); string ans; while (p0 % R) { ans += l ; swap(V[p0], V[p0 - 1]); p0--; } if (p0 == R) { ans += u ; swap(V[p0], V[p0 - R]); p0 -= R; } assert(p0 == 0); bool parity = 0; for (int i = 0; i < N; i++) { for (int j = i + 1; j < N; j++) { if (V[j] < V[i]) parity ^= 1; } } if (parity) { cout << SURGERY FAILED << n ; continue; } for (int i = 0; i < K; i++) { ans += r ; swap(V[p0], V[p0 + 1]); p0++; } assert(p0 == K); ans += d ; swap(V[p0], V[p0 + R]); p0 += R; auto VtoF = [&](int v) { assert(v != 0); if (v <= K) { return v + K; } else if (v == K + 1) { return R; } else if (v <= R) { return 2 * R - (v - (K + 1)); } else if (v <= R + K) { return (K + 1) - (v - R); } else { return R + (v - R - K); } }; deque<int> lhs; deque<int> rhs; for (int i = K - 1; i >= 0; i--) { lhs.push_front(VtoF(V[i])); } for (int i = 0; i < K; i++) { lhs.push_front(VtoF(V[R + i])); } for (int i = K + 1; i < R; i++) { rhs.push_front(VtoF(V[i])); } for (int i = R - 1; i > K; i--) { rhs.push_front(VtoF(V[R + i])); } int mid = VtoF(V[K]); assert(int(lhs.size()) == 2 * K); assert(int(rhs.size()) == 2 * K); auto rotL = [&]() { ans += L ; lhs.push_back(mid); mid = lhs.front(); lhs.pop_front(); }; auto unrotL = [&]() { ans += X ; lhs.push_front(mid); mid = lhs.back(); lhs.pop_back(); }; auto rotR = [&]() { ans += R ; rhs.push_back(mid); mid = rhs.front(); rhs.pop_front(); }; auto unrotR = [&]() { ans += Y ; rhs.push_front(mid); mid = rhs.back(); rhs.pop_back(); }; for (int z = 0; z < 2 * N; z++) { if (mid <= R) { rotL(); } else { rotR(); } } for (int z = 0; z < R; z++) { rotL(); for (int i = 0; i < R - 1; i++) { if (lhs.front() < mid) { rotR(); rotL(); unrotR(); unrotL(); rotR(); } rotL(); } } assert(mid == R); mid = 2 * R; bool f = false; for (int z = 0; z < R; z++) { rotR(); for (int i = 0; i < R - 1; i++) { if (rhs.front() < mid) { f ? unrotL() : rotL(); rotR(); f ? rotL() : unrotL(); unrotR(); f ? unrotL() : rotL(); f = !f; } rotR(); } } assert(f == false); for (int i = 0; i < K; i++) { ans += r ; } cout << SURGERY COMPLETE << n ; cout << ans << n ; cout << L << << string(K, l ) + u + string(K, r ) + d << n ; cout << X << << u + string(K, l ) + d + string(K, r ) << n ; cout << R << << string(K, r ) + u + string(K, l ) + d << n ; cout << Y << << u + string(K, r ) + d + string(K, l ) << n ; cout << DONE << n ; } return 0; } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : buf_ram_1p_6x85.v
// Author : Yibo FAN
// Created : 2014-04-07
// Description : buf ram for coefficient
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module buf_ram_1p_6x85 (
clk ,
ce ,
we ,
addr ,
data_i ,
data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
input ce ;
input we ;
input [9:0] addr ;
input [5:0] data_i ;
output [5:0] data_o ;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
`ifdef RTL_MODEL
ram_1p #(.Addr_Width(10), .Word_Width(6))
u_ram_1p_6x85 (
.clk ( clk ),
.cen_i ( ~ce ),
.oen_i ( 1'b0 ),
.wen_i ( ~we ),
.addr_i ( addr ),
.data_i ( data_i ),
.data_o ( data_o )
);
`endif
`ifdef FPGA_MODEL
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog wrapper for dlybuf4s18kapwr with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s18kapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s18kapwr_1 (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlybuf4s18kapwr base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s18kapwr_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlybuf4s18kapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1_V
|
`timescale 1ns / 1ps
module ball(
input [9:0] paddle_x,
//input [9:0] paddle_y,
input reset,
input start,
input clk,
input clk_50mh,
output [9:0] x_out,
output [9:0] y_out,
output erase_enable,
output [5:0] e_pos,
output reg [2:0] play_sound1,
//output reg play_sound2,
output reg [1:0] active_data
);
parameter
SCREEN_W = 640,
SCREEN_H = 480,
BALL_SIZE = 7,
BLOCK_SPACING_X = 10'd40,
BLOCK_SPACING_Y = 10'd20,
FIRST_ROW_Y = 10'd40,
SECOND_ROW_Y = 10'd90,
THIRD_ROW_Y = 10'd140,
FOURTH_ROW_Y = 10'd190,
FIFTH_ROW_Y = 10'd240,
BLOCK_WIDTH = 10'd80,
BLOCK_HEIGHT = 10'd30;
reg [9:0] ball_x;
reg [9:0] ball_y;
reg signed [9:0] ball_dx;
reg signed [9:0] ball_dy;
assign x_out = ball_x;
assign y_out = ball_y;
reg erase_e;
reg [5:0] erase_pos;
reg [5:0] address;
reg win;
//reg p_sound //assign play_sound1 = p_sound;
reg [1:0] active [24:0];
reg [9:0] temp1;
reg [9:0] temp2;
reg [5:0] i;
reg start_movement;
//reg [5:0] j;
assign e_pos = erase_pos;
assign erase_enable = erase_e;
always @ (posedge clk_50mh) begin
end
always @ (posedge clk) begin
erase_e = 0;
if(start)
start_movement = 1;
if(!start_movement)begin
ball_x = paddle_x + BALL_SIZE + 10'd40;
end
if(start_movement)begin
if((ball_x) <= 0 || ball_x >= SCREEN_W - BALL_SIZE) //screen boundaries check
begin
ball_dx = ball_dx * -1;
end
if(ball_y <= 1) //screen boundaries check
begin
play_sound1 = 3'b001;
ball_dy = ball_dy * -1;
//erase_e = 1;
end
if(ball_y > SCREEN_H - BALL_SIZE) //screen boundaries check
begin
play_sound1 = 3'b100;
ball_dy = 0;
//erase_e = 1;
end
address = address + 10'd1;
if(address >= 10'd10)
address = 10'd0;
/*if (ball_y >= FIFTH_ROW_Y)
address = 10'd19;
else if (ball_y >= FOURTH_ROW_Y && (address > 19))
address = 10'd14;
else if (ball_y >= THIRD_ROW_Y && (address > 14))
address = 10'd9;
else if (ball_y >= SECOND_ROW_Y && (address > 9))
address = 10'd5;
else if (ball_y >= 0 &&( (address > 4)))
address = 10'd0;*/
if (address<5) begin
temp1 = FIRST_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *address;
end
else if (address < 10) begin
temp1 = SECOND_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-5);
end
/*else if (address < 15) begin
temp1 = THIRD_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-10);
end
else if (address < 20) begin
temp1 = FOURTH_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-15);
end
else if (address < 25) begin
temp1 = FIFTH_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-20);
end*/
if(active[address] < 3) begin
if(
(ball_y >= temp1 && ball_y <= (temp1 + BLOCK_HEIGHT) ) &&
(( (ball_x + BALL_SIZE) >= (temp2) && (ball_x - BALL_SIZE) <= temp2 )
||
( (ball_x + BALL_SIZE) >= (temp2 + BLOCK_WIDTH) && (ball_x - BALL_SIZE) <= (temp2 + BLOCK_WIDTH) )
)
) begin
erase_e = 1;
erase_pos = address;
ball_dx = ball_dx * -1;
active[address] = active[address] + 1;
play_sound1 = active[address];
active_data = active[address];
end
else if ( (ball_x >= temp2 && ball_x <= (temp2 + BLOCK_WIDTH)) &&
(( (ball_y + BALL_SIZE) >= (temp1) && (ball_y - BALL_SIZE) <= temp1 ) ||
( (ball_y + BALL_SIZE) >= (temp1 + BLOCK_HEIGHT) && (ball_y - BALL_SIZE) <= (temp1 + BLOCK_HEIGHT) )
))
begin
erase_e = 1;
erase_pos = address;
ball_dy = ball_dy * -1;
active[address] = active[address] + 1;
play_sound1 = active[address];
active_data = active[address];
end
end
if (address<5) begin
temp1 = THIRD_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address);
end
else if (address < 10) begin
temp1 = FOURTH_ROW_Y;
temp2 = BLOCK_SPACING_X + (BLOCK_WIDTH + BLOCK_SPACING_X) *(address-5);
end
if(active[address + 10'd10] < 3) begin
if(
(ball_y >= temp1 && ball_y <= (temp1 + BLOCK_HEIGHT) ) &&
(( (ball_x + BALL_SIZE) >= (temp2) && (ball_x - BALL_SIZE) <= temp2 )
||
( (ball_x + BALL_SIZE) >= (temp2 + BLOCK_WIDTH) && (ball_x - BALL_SIZE) <= (temp2 + BLOCK_WIDTH) )
)
) begin
erase_e = 1;
erase_pos = address + 10'd10;
ball_dx = ball_dx * -1;
active[address + 10'd10] = active[address + 10'd10] + 1;
play_sound1 = active[address + 10'd10];
active_data = active[address + 10'd10];
end
else if ( (ball_x >= temp2 && ball_x <= (temp2 + BLOCK_WIDTH)) &&
(( (ball_y + BALL_SIZE) >= (temp1) && (ball_y - BALL_SIZE) <= temp1 ) ||
( (ball_y + BALL_SIZE) >= (temp1 + BLOCK_HEIGHT) && (ball_y - BALL_SIZE) <= (temp1 + BLOCK_HEIGHT) )
))
begin
erase_e = 1;
erase_pos = address + 10'd10;
ball_dy = ball_dy * -1;
active[address + 10'd10] = active[address + 10'd10] + 1;
play_sound1 = active[address + 10'd10];
active_data = active[address + 10'd10];
end
end
win = 1;
for (i = 0; i < 20; i = i + 1) begin
if (active[i] < 3)
win = 0;
end
//p_sound = erase_e;
//play_sound2 = 0;
if( ball_dy > 0 && (ball_x > paddle_x && ball_x < (paddle_x + 100)) && ( ( (ball_y + BALL_SIZE) >= 10'd439 && (ball_y - BALL_SIZE) < 10'd440) ) ) //paddle collision
begin
ball_dy = ball_dy * -1;
play_sound1 = 3'b100;
if ((ball_x < paddle_x + 25 || ball_x > paddle_x + 75) && (ball_dx == 1 || ball_dx == -1)) begin
ball_dx = ball_dx * 2;
end
else if (ball_dx == 2) begin
ball_dx = 1;
end
else if (ball_dx == -2) begin
ball_dx = -1;
end
end
if (win) begin
ball_dx = 10'd0;
ball_dy = 10'd0;
end
ball_x = ball_x + ball_dx;
ball_y = ball_y + ball_dy;
end
if(reset)begin
ball_x = 10'd270;
ball_y = 10'd440 - BALL_SIZE;
ball_dx = -10'd1;
ball_dy = -10'd1;
start_movement = 0;
for (i = 0; i < 20; i = i + 1) begin
active[i] = 0;
end
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file virtex5_pmem.v when simulating
// the core, virtex5_pmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module virtex5_pmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex5_pmem is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, lg = 20, N = 1e5 + 5; int ans[N]; bool vis[N]; vector<pair<int, int> > g[N]; struct node { node *ch[11]; node *sp[lg]; int val, lvl, last; node() { memset(ch, 0, sizeof ch); memset(sp, 0, sizeof sp); val = lvl = last = 0; } }; struct cmp { bool operator()(const pair<node *, int> a, const pair<node *, int> b) const { if (b.first->lvl != a.first->lvl) return a.first->lvl < b.first->lvl; node *u = (node *)b.first; node *v = (node *)a.first; for (int i = lg - 1; i >= 0; i--) { if (u->sp[i] != v->sp[i]) { u = u->sp[i]; v = v->sp[i]; } } if (v->last != u->last) return v->last < u->last; return a.second < b.second; } }; vector<int> digits[N]; void build() { for (int i = 1; i < N; i++) { int j = i; while (j) digits[i].push_back(j % 10), j /= 10; reverse(digits[i].begin(), digits[i].end()); } } void build(node *a) { for (int i = 1; i < lg; i++) { a->sp[i] = a->sp[i - 1]->sp[i - 1]; } } void dij() { node *root = new node(); root->sp[0] = root; build(root); set<pair<node *, int>, cmp> st; st.insert({root, 1}); while (st.size()) { node *cur = (*st.begin()).first; int temp = (*st.begin()).second; st.erase(st.begin()); if (vis[temp] == 0) { vis[temp] = 1; ans[temp] = cur->val; } else continue; for (int i = 0; i < g[temp].size(); i++) { int v = g[temp][i].first; int cost = g[temp][i].second; node *temp = cur; for (auto dig : digits[cost]) { if (!temp->ch[dig]) { temp->ch[dig] = new node(); temp->ch[dig]->lvl = temp->lvl + 1; temp->ch[dig]->val = ((temp->val * 1ll * 10) % mod + dig) % mod; temp->ch[dig]->sp[0] = temp; temp->ch[dig]->last = dig; build(temp->ch[dig]); } temp = temp->ch[dig]; } st.insert({temp, v}); } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); build(); int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; g[u].push_back({v, i}); g[v].push_back({u, i}); } dij(); for (int i = 2; i <= n; i++) cout << ans[i] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int Get() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } const long long mod = 1e9 + 7; const long long Mod = 998244353; int n, m; long long f[2005][15]; struct road { int to, next; } s[2005 << 1]; int h[2005], cnt; void add(int i, int j) { s[++cnt] = (road){j, h[i]}; h[i] = cnt; } vector<int> e[2005]; long long fac[2005], ifac[2005]; long long ksm(long long t, long long x) { long long ans = 1; for (; x; x >>= 1, t = t * t % mod) if (x & 1) ans = ans * t % mod; return ans; } long long Hash[2005]; long long Hash2[2005]; const long long p = 666233, p2 = 134341; unsigned long long p3 = 233333; int size[2005]; bool cmp(int a, int b) { if (size[a] != size[b]) return size[a] < size[b]; if (Hash[a] != Hash[b]) return Hash[a] < Hash[b]; return Hash2[a] < Hash2[b]; } long long t[2005]; vector<int> sn[2005]; int dep[2005], mxdep[2005]; void dfs1(int v, int fr) { size[v] = 1; mxdep[v] = dep[v]; for (int i = 0; i < e[v].size(); i++) { int to = e[v][i]; if (to == fr) continue; sn[v].push_back(to); dep[to] = dep[v] + 1; dfs1(to, v); mxdep[v] = max(mxdep[v], mxdep[to]); size[v] += size[to]; } sort(sn[v].begin(), sn[v].end(), cmp); t[v] = 1; for (int i = 0; i < sn[v].size(); i++) { int j = i; while (j + 1 < sn[v].size() && size[sn[v][i]] == size[sn[v][j + 1]] && Hash[sn[v][i]] == Hash[sn[v][j + 1]] && Hash2[sn[v][j]] == Hash2[sn[v][j + 1]]) j++; t[v] = t[v] * ifac[j - i + 1] % mod; i = j; } Hash2[v] = Hash[v] = ( ; long long now = 1, now2 = 1; for (int i = 0; i < sn[v].size(); i++) { Hash[v] = ((Hash[v] * now % mod) ^ Hash[sn[v][i]]) % mod; Hash2[v] = ((Hash2[v] * now2 % Mod) ^ Hash2[sn[v][i]]) % Mod; now = now * p % mod; now2 = now2 * p2 % Mod; } Hash[v] = (Hash[v] * p + ) ) % mod; Hash2[v] = (Hash2[v] * p + ) ) % Mod; } int st[2005], top; int cal(int v, int u) { if (!top) return 0; static long long ans[1 << 13], g[1 << 13]; int num = sn[u].size(); for (int i = 0; i < 1 << num; i++) ans[i] = 0; ans[0] = 1; for (int i = 1; i <= top; i++) { memcpy(g, ans, sizeof(g)); int now = st[i]; for (int j = 0; j < num; j++) { if (!f[now][sn[u][j]]) continue; int t = 1 << j; for (int sta = 0; sta < 1 << num; sta++) { if (!(sta & t)) g[sta | t] = (g[sta | t] + ans[sta] * f[now][sn[u][j]]) % mod; } } memcpy(ans, g, sizeof(g)); } return ans[(1 << num) - 1] * t[u] % mod; } long long ans; int rt; void solve(int v, int fr) { for (int i = 1; i <= m; i++) if (sn[i].size() == 0) f[v][i] = 1; for (int i = h[v]; i; i = s[i].next) { int to = s[i].to; if (to == fr) continue; solve(to, v); } top = 0; for (int i = h[v]; i; i = s[i].next) { if (s[i].to == fr) continue; st[++top] = s[i].to; } for (int i = 1; i <= m; i++) { if (sn[i].size()) { f[v][i] = cal(v, i); } } (ans += f[v][rt]) %= mod; } map<pair<int, int>, int> vis; int work() { for (int i = 1; i <= m; i++) sn[i].clear(); for (int i = 1; i <= m; i++) Hash[i] = Hash2[i] = 0; dep[rt] = 1; dfs1(rt, 0); if (vis.find(make_pair(Hash[rt], Hash2[rt])) != vis.end()) return 0; vis[make_pair(Hash[rt], Hash2[rt])] = 1; memset(f, 0, sizeof(f)); ans = 0; solve(1, 0); return ans; } int main() { n = Get(); int a, b; for (int i = 1; i < n; i++) { a = Get(), b = Get(); add(a, b), add(b, a); } m = Get(); fac[0] = 1; for (int i = 1; i <= m; i++) fac[i] = fac[i - 1] * i % mod; ifac[m] = ksm(fac[m], mod - 2); for (int i = m - 1; i >= 0; i--) ifac[i] = ifac[i + 1] * (i + 1) % mod; for (int i = 1; i < m; i++) { a = Get(), b = Get(); e[a].push_back(b); e[b].push_back(a); } long long tot = 0; for (rt = m; rt >= 1; rt--) (tot += work()) %= mod; cout << tot << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__XNOR3_BEHAVIORAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_BEHAVIORAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer FIFO ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implementation of store buffer FIFO. ////
//// ////
//// To Do: ////
//// - N/A ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb_fifo.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.3 2002/11/06 13:53:41 simons
// SB mem width fixed.
//
// Revision 1.2 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb_fifo(
clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
);
parameter dw = 68;
parameter fw = `OR1200_SB_LOG;
parameter fl = `OR1200_SB_ENTRIES;
//
// FIFO signals
//
input clk_i; // Clock
input rst_i; // Reset
input [dw-1:0] dat_i; // Input data bus
input wr_i; // Write request
input rd_i; // Read request
output [dw-1:0] dat_o; // Output data bus
output full_o; // FIFO full
output empty_o;// FIFO empty
//
// Internal regs
//
reg [dw-1:0] mem [fl-1:0];
reg [dw-1:0] dat_o;
reg [fw+1:0] cntr;
reg [fw-1:0] wr_pntr;
reg [fw-1:0] rd_pntr;
reg empty_o;
reg full_o;
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
full_o <= #1 1'b0;
empty_o <= #1 1'b1;
wr_pntr <= #1 {fw{1'b0}};
rd_pntr <= #1 {fw{1'b0}};
cntr <= #1 {fw+2{1'b0}};
dat_o <= #1 {dw{1'b0}};
end
else if (wr_i && rd_i) begin // FIFO Read and Write
mem[wr_pntr] <= #1 dat_i;
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
if (empty_o) begin
dat_o <= #1 dat_i;
end
else begin
dat_o <= #1 mem[rd_pntr];
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
else if (wr_i && !full_o) begin // FIFO Write
mem[wr_pntr] <= #1 dat_i;
cntr <= #1 cntr + 1'b1;
empty_o <= #1 1'b0;
if (cntr >= (fl-1)) begin
full_o <= #1 1'b1;
cntr <= #1 fl;
end
if (wr_pntr >= fl-1)
wr_pntr <= #1 {fw{1'b0}};
else
wr_pntr <= #1 wr_pntr + 1'b1;
end
else if (rd_i && !empty_o) begin // FIFO Read
dat_o <= #1 mem[rd_pntr];
cntr <= #1 cntr - 1'b1;
full_o <= #1 1'b0;
if (cntr <= 1) begin
empty_o <= #1 1'b1;
cntr <= #1 {fw+2{1'b0}};
end
if (rd_pntr >= fl-1)
rd_pntr <= #1 {fw{1'b0}};
else
rd_pntr <= #1 rd_pntr + 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; const int MOD = 998244353; int n; char s[N]; int solve() { scanf( %d , &n); scanf( %s , s); bool ok = true; for (int i = 0; i < n;) { int j = i; while (j < n && s[j] == s[i]) ++j; if (s[i] == 0 && i == 0) { for (int k = i; k < j; ++k) printf( 0 ); } else if (s[i] == 1 && j == n) { for (int k = i; k < j; ++k) printf( 1 ); } else if (s[i] == 1 && ok) { printf( 0 ); ok = false; } i = j; } printf( n ); return 0; } int main() { int t = 1; scanf( %d , &t); while (t--) solve(); return 0; } |
// file: in_dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____96.002______0.000______50.0______408.330_____60.000
// CLK_OUT2___120.002______0.000______50.0______366.664_____60.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________48.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "in_dcm,clk_wiz_v3_2,{component_name=in_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.833,clkin2_period=20.833,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module in_dcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk2x;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (2),
.CLKFX_MULTIPLY (5),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.833),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("2X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (clk2x),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
assign clkfb = CLK_OUT1;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clk2x));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkfx));
endmodule
|
// --------------------------------------------------------------------
// ng_INT Central register Module
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_INT(
input CPO4, // Clock Pulse Interrupt1
input CPO5, // Clock Pulse Interrupt3
input KB_STR, // Keyboard Interrupt4
input CLK2, // Clock Pulse 2
input [100:0] CP, // Control Pulse
input [ 15:0] WRITE_BUS, // Control Pulse
output [ 15:0] INT_BUS, // INT Register output
output IRQ // Interrupt request
);
// --------------------------------------------------------------------
// JTAG Debugging Probes
// --------------------------------------------------------------------
//JTAG_Probe INT_OUT16(.probe(INT_BUS));
// 3 3 3 3 1 1 1 1
//JTAG_Probe INT_TST16(.probe({RPCELL,pri_level,pri_out, rst_RUPT, KRPT, CLRP, pri_EO,IT_SEL}));
// 15 14 13 12 11 10 9 8 7, 6, 5, 4, 3, 2, 1, 0
JTAG_Probe INT_TST2(.probe({IRQ,rgINH,rgINH1,KB_STR,RPT,INH,CLINH,CLINH1,WOVI,rgRUPT1,rgRUPT3,rgRUPT4,WRITE_BUS[15],WRITE_BUS[14],KRPT,CLRP }));
// --------------------------------------------------------------------
// Output Assignments
// --------------------------------------------------------------------
assign IRQ = !(IT_INH & IT_INH1 & pri_EO & IT_SEL);
// --------------------------------------------------------------------
// Control Signal Assignments
// --------------------------------------------------------------------
wire GENRST = CP[`CPX(`GENRST)]; // General reset signal
wire RPT = CP[`CPX(`RPT)]; // Read RUPT opcode
wire CLRP = CP[`CPX(`CLRP)]; // Clear RPCELL
wire INH = CP[`CPX(`INH)]; // Set INHINT
wire CLINH = CP[`CPX(`CLINH)]; // Clear INHINT
wire CLINH1 = CP[`CPX(`CLINH1)]; // Clear INHINT1
wire WOVI = CP[`CPX(`WOVI)]; // Write overflow RUPT inhibit
wire KRPT = CP[`CPX(`KRPT)]; // Knock down Rupt priority
// --------------------------------------------------------------------
// Register Storage
// --------------------------------------------------------------------
reg rgINH; // Inhibit Interrupt register
reg rgINH1; // Inhibit 1 Interrupt register
reg rgRUPT1; // Interrupt register 1
reg rgRUPT3; // Interrupt register 3
reg rgRUPT4; // Interrupt register 4
reg [2:0] RPCELL; // RP Register
// --------------------------------------------------------------------
// Interrupt Inhibit Logic
//
// NOTE: A JK FF can be instantiated using this code:
// always@(negedge CLK or negedge CLN or negedge PRN)
// if (!CLN) Q <= 0;
// else if(!PRN) Q <= 1;
// else Q <= ~Q & J | Q & ~K;
// --------------------------------------------------------------------
reg rgINH_i; // internal Inhibit Interrupt register
always@(posedge CLK2)
rgINH_i <= (~rgINH_i & !(INH & GENRST)) | (rgINH_i & CLINH);
always@(negedge CLK2) rgINH <= rgINH_i; // Transfer to outputs on negative edge
reg rgINH1_i; // internal Inhibit Interrupt register
wire IT_INH1_J = (WRITE_BUS[15] ^ WRITE_BUS[14]) & ~WOVI;
always@(posedge CLK2)
if(!GENRST) rgINH1_i <= 1'b0;
else rgINH1_i <= (~rgINH1_i & IT_INH1_J) | (rgINH1_i & CLINH1);
always@(negedge CLK2) rgINH1 <= rgINH1_i; // Transfer to outputs on negative edge
wire IT_INH = !rgINH;
wire IT_INH1 = !rgINH1;
// --------------------------------------------------------------------
// Interrupt Latches
// --------------------------------------------------------------------
wire IT_RST = !(CLK2 & !GENRST); // Reset Signal sync with clock
wire rst_RUPT1 = rst_RUPT[0] & IT_RST; // Rupt reset wires
reg rgRUPT1_i; // Interrupt register 1
always@(posedge CPO4 or negedge rst_RUPT1) // Interrupt latch 1
if(!rst_RUPT1) rgRUPT1_i <= 1'b0; // Release latch
else rgRUPT1_i <= 1'b1; // Set latch
always@(negedge CPO4 or negedge rst_RUPT1) rgRUPT1 <= rgRUPT1_i;
wire rst_RUPT3 = rst_RUPT[1] & IT_RST; // Rupt reset wires
reg rgRUPT3_i; // Interrupt register 3
always@(posedge CPO5 or negedge rst_RUPT3) // Interrupt latch 3
if(!rst_RUPT3) rgRUPT3_i <= 1'b0; // Release latch
else rgRUPT3_i <= 1'b1; // Set latch
always@(negedge CPO5 or negedge rst_RUPT3) rgRUPT3 <= rgRUPT3_i;
reg rgRUPT4_i;
always@(posedge KB_STR or negedge rst_RUPT4) // Interrupt latch 4
if(!rst_RUPT4) rgRUPT4_i <= 1'b0; // Release latch
else if(KB_STR) rgRUPT4_i <= 1'b1; // Set latch
always@(negedge KB_STR or negedge rst_RUPT4) rgRUPT4 <= rgRUPT4_i;
wire rst_RUPT4 = IT_RST & rst_RUPT[2]; // Rupt reset wires
// --------------------------------------------------------------------
// Prioritize the interrupts
// --------------------------------------------------------------------
wire [2:0] pri_level = {rgRUPT1, rgRUPT3, rgRUPT4}; // Priority level
reg [2:0] pri_out; // seected priority
always @(pri_level) begin
casex(pri_level)
3'b1XX : pri_out <= 3'b001; // priority 6, pri_out = 1
3'b01X : pri_out <= 3'b011; // priority 4, pri_out = 3
3'b001 : pri_out <= 3'b100; // priority 3, pri_out = 4
default : pri_out <= 3'b111; // priority X, pri_out = 7
endcase
end
wire pri_EO = |pri_level; // =1 if were any activated
// --------------------------------------------------------------------
// Instantiate Register RPCELL at address
// 2004 = RUPT 1 (TIME3)(octal RUPT addr)
// 2014 = RUPT 3 (TIME4)
// 2020 = RUPT 4 (KBD)
// --------------------------------------------------------------------
always @(posedge CLK2) begin
if(!GENRST) RPCELL <= 3'h0;
else if(!CLRP) RPCELL <= 3'h0;
else if(!RPT) RPCELL <= pri_out;
end
wire IT_SEL = !(|RPCELL);
assign INT_BUS = {11'b0000_0100_000,RPCELL,2'b00};
// --------------------------------------------------------------------
// Interrupt Reset Logic
// --------------------------------------------------------------------
reg [2:0] rst_RUPT; // Rupt reset
always @(posedge CLK2) begin
if(!KRPT) begin
case(pri_out)
3'b001 : rst_RUPT <= 3'b110; // Priority 1
3'b011 : rst_RUPT <= 3'b101; // Priority 3
3'b100 : rst_RUPT <= 3'b011; // Priority 4
default: rst_RUPT <= 3'b111; // Priority 7
endcase
end
else rst_RUPT <= 3'b111;
end
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; set<pair<int, int> > h; vector<int> d(n), s(n); for (int i = 0; i < n; i++) { cin >> d[i] >> s[i]; if (d[i]) { h.insert({d[i], i}); } } vector<pair<int, int> > ans; while (!h.empty()) { pair<int, int> v = *h.begin(); h.erase(h.begin()); int w = s[v.second]; h.erase(make_pair(d[w], w)); d[w]--; s[w] ^= v.second; ans.push_back({v.second, w}); if (d[w]) h.insert(make_pair(d[w], w)); } cout << ans.size() << n ; for (auto& x : ans) { cout << x.first << << x.second << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void input(vector<long long>& v, long n) { for (long long i = 0; i < n; i++) { long long in; cin >> in; v.push_back(in); } } void output(vector<long long> v) { for (long long i = 0; i < v.size(); i++) cout << v[i] << ; } long long max_of_three(long long a, long long b, long long c) { if (a >= b && a >= c) return a; else if (b >= a && b >= c) return b; else return c; } long long max_of_4(long long a, long long b, long long c, long long d) { if (a >= b && a >= c && a >= d) return a; else if (b >= a && b >= c && b >= d) return b; else if (c >= a && c >= d && c >= b) return c; else return d; } map<long long, long long> frequency(vector<long long> v) { map<long long, long long> m; for (long long i = 0; i < v.size(); i++) { if (m.find(v[i]) != m.end()) m[v[i]]++; else { m.insert({v[i], 1}); } } return m; } long long max_occuring_int(std::map<long long, long long> m) { long long max_x = 0; long long i = 0, n = m.size(); std::map<long long, long long>::iterator it = m.begin(); for (i = 0; i < n; i++) { if (it->second > max_x) max_x = it->second; it++; } return max_x; } vector<long long> give_unique_in_vector(vector<long long> v) { sort((v).begin(), (v).end()); auto it = unique((v).begin(), (v).end()); v.resize(std::distance(v.begin(), it)); vector<long long> x = v; return x; } bool isVowel(char c) { return (c == a | c == e || c == i || c == o || c == u || c == y || c == A || c == E || c == I || c == O || c == U || c == Y ); } string removeWord(string str, string word) { if (str.find(word) != string::npos) { size_t p = -1; string tempWord = word + ; while ((p = str.find(word)) != string::npos) str.replace(p, tempWord.length(), ); tempWord = + word; while ((p = str.find(word)) != string::npos) str.replace(p, tempWord.length(), ); } return str; } long long calc(long long i, long long j, long long n) { return (i + 1 - 1) * n + j + 1; } bool compare_descending(long long a, long long b) { return a > b; } void solve() { int n, k, i; string s; cin >> n >> k >> s; if (n - k < k - 1) { for (i = k - 1; i < n - 1; i++) cout << RIGHT n ; for (i; i >= 0; i--) { cout << PRINT << s[i] << endl; if (i != 0) cout << LEFT n ; } } else { for (i = k - 1; i > 0; i--) cout << LEFT n ; for (i; i < n; i++) { cout << PRINT << s[i] << endl; if (i != n - 1) cout << RIGHT n ; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int t, n, p[100002]; bool id[100002]; int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 1; i <= n; i++) { int a; scanf( %d , &a); p[a] = i; id[i] = true; } id[n + 1] = 0; bool succeed = true; int num = 1; int tp = p[1]; p[1] = 0; id[tp] = 0; for (int i = 2; i <= n; i++) { if (id[tp + 1] == false) { id[p[i]] = false; tp = p[i]; } else { if (tp + 1 != p[i]) { succeed = false; break; } else { id[tp + 1] = false; tp = tp + 1; } } } if (succeed) printf( Yes n ); else printf( No n ); } } |
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