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module ereset (/*AUTOARG*/
// Outputs
reset, chip_resetb,
// Inputs
hard_reset, soft_reset
);
//inputs
input hard_reset; // hardware reset from external block
input soft_reset; // soft reset drive by register (level)
//outputs
output reset; //reset for elink
output chip_resetb; //reset for epiphany
//Reset for link logic
assign reset = hard_reset | soft_reset;
//May become more sophisticated later..
//(for example, for epiphany reset, you might want to include some
//some hard coded logic to avoid reset edge errata)
//also, for multi chip boards, since the coordinates are sampled on
//the rising edge of chip_resetb it may be beneficial to have one
//reset per chip and to stagger the
assign chip_resetb = ~(hard_reset | soft_reset);
endmodule // ereset
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
Contributed by Fred Huettig <>
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A221OI_PP_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a221oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_PP_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:54:19 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110;
NAND2XLTS U51 ( .A(n33), .B(n87), .Y(n89) );
XOR2X1TS U52 ( .A(n62), .B(in2[11]), .Y(n94) );
NAND2X1TS U53 ( .A(n71), .B(in1[13]), .Y(n87) );
NAND2X1TS U54 ( .A(n74), .B(n36), .Y(n58) );
NAND2BX1TS U55 ( .AN(in2[13]), .B(n59), .Y(n74) );
NAND2X1TS U56 ( .A(n67), .B(n36), .Y(n68) );
CMPR32X2TS U57 ( .A(n100), .B(in1[6]), .C(n99), .CO(n55), .S(res[6]) );
OR2X2TS U58 ( .A(n51), .B(n35), .Y(n34) );
INVX4TS U59 ( .A(n35), .Y(n36) );
NOR2X4TS U60 ( .A(n53), .B(in2[8]), .Y(n57) );
INVX4TS U61 ( .A(add_sub), .Y(n35) );
CLKINVX6TS U62 ( .A(in2[1]), .Y(n44) );
CLKINVX6TS U63 ( .A(in2[3]), .Y(n42) );
CLKINVX6TS U64 ( .A(in2[0]), .Y(n43) );
INVX8TS U65 ( .A(in2[2]), .Y(n41) );
NAND2BX2TS U66 ( .AN(in2[11]), .B(n61), .Y(n67) );
NOR2XLTS U67 ( .A(n61), .B(n35), .Y(n62) );
INVX2TS U68 ( .A(n78), .Y(n77) );
NOR2X4TS U69 ( .A(n67), .B(in2[12]), .Y(n59) );
NOR2X4TS U70 ( .A(n65), .B(in2[10]), .Y(n61) );
AO21X2TS U71 ( .A0(n33), .A1(n70), .B0(n72), .Y(n37) );
NAND2X2TS U72 ( .A(n76), .B(in1[15]), .Y(n78) );
XNOR2X2TS U73 ( .A(n58), .B(in2[14]), .Y(n73) );
NOR2X2TS U74 ( .A(n59), .B(n35), .Y(n60) );
ADDFHX2TS U75 ( .A(n56), .B(in1[7]), .CI(n55), .CO(n97), .S(res[7]) );
OAI31X1TS U76 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(n36), .Y(n106) );
NAND2X2TS U77 ( .A(n83), .B(n82), .Y(n85) );
NOR2X2TS U78 ( .A(n73), .B(in1[14]), .Y(n81) );
NAND2X2TS U79 ( .A(n73), .B(in1[14]), .Y(n82) );
NOR2X2TS U80 ( .A(n39), .B(n86), .Y(n38) );
INVX2TS U81 ( .A(n86), .Y(n33) );
NAND2X2TS U82 ( .A(n69), .B(in1[12]), .Y(n90) );
OR2X2TS U83 ( .A(n69), .B(in1[12]), .Y(n46) );
XNOR2X2TS U84 ( .A(n68), .B(in2[12]), .Y(n69) );
NOR2BX2TS U85 ( .AN(in1[5]), .B(n110), .Y(n99) );
NAND2BXLTS U86 ( .AN(in1[5]), .B(n110), .Y(res[5]) );
XNOR2X2TS U87 ( .A(n50), .B(in2[5]), .Y(n110) );
NAND2BXLTS U88 ( .AN(in1[4]), .B(n109), .Y(res[4]) );
OAI21XLTS U89 ( .A0(in2[1]), .A1(n102), .B0(n101), .Y(res[1]) );
OAI21XLTS U90 ( .A0(in2[2]), .A1(n104), .B0(n103), .Y(res[2]) );
OAI21XLTS U91 ( .A0(in2[3]), .A1(n106), .B0(n105), .Y(res[3]) );
XOR2X1TS U92 ( .A(n108), .B(in2[4]), .Y(n109) );
OR2X1TS U93 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
XNOR2X1TS U94 ( .A(n34), .B(in2[7]), .Y(n56) );
OAI21X1TS U95 ( .A0(n74), .A1(in2[14]), .B0(n36), .Y(n75) );
AO21X2TS U96 ( .A0(n79), .A1(n45), .B0(n77), .Y(res[16]) );
NAND2X2TS U97 ( .A(n45), .B(n78), .Y(n80) );
OR2X2TS U98 ( .A(n76), .B(in1[15]), .Y(n45) );
NOR2X2TS U99 ( .A(n49), .B(n35), .Y(n50) );
AFHCONX4TS U100 ( .A(in1[10]), .B(n95), .CI(n96), .CON(n93), .S(res[10]) );
AOI21X4TS U101 ( .A0(n91), .A1(n38), .B0(n37), .Y(n84) );
XNOR2X1TS U102 ( .A(n79), .B(n80), .Y(res[15]) );
OAI21X4TS U103 ( .A0(n84), .A1(n81), .B0(n82), .Y(n79) );
XNOR2X2TS U104 ( .A(n75), .B(in2[15]), .Y(n76) );
AFHCONX4TS U105 ( .A(in1[8]), .B(n98), .CI(n97), .CON(n63), .S(res[8]) );
AFHCINX4TS U106 ( .CIN(n63), .B(n64), .A(in1[9]), .S(res[9]), .CO(n96) );
NOR2X8TS U107 ( .A(n47), .B(in2[6]), .Y(n51) );
NAND2X4TS U108 ( .A(n47), .B(add_sub), .Y(n48) );
NAND2X8TS U109 ( .A(n49), .B(n40), .Y(n47) );
AFHCINX4TS U110 ( .CIN(n93), .B(n94), .A(in1[11]), .S(res[11]), .CO(n91) );
NOR2X8TS U111 ( .A(n107), .B(in2[4]), .Y(n49) );
XOR2X4TS U112 ( .A(n60), .B(in2[13]), .Y(n71) );
NAND2BX4TS U113 ( .AN(in2[7]), .B(n51), .Y(n53) );
NAND2BX4TS U114 ( .AN(in2[9]), .B(n57), .Y(n65) );
INVX2TS U115 ( .A(in2[5]), .Y(n40) );
NOR2X2TS U116 ( .A(n71), .B(in1[13]), .Y(n86) );
INVX2TS U117 ( .A(n90), .Y(n70) );
INVX2TS U118 ( .A(n46), .Y(n39) );
XNOR2X1TS U119 ( .A(n48), .B(in2[6]), .Y(n100) );
XNOR2X1TS U120 ( .A(n54), .B(in2[8]), .Y(n98) );
NAND2X1TS U121 ( .A(n53), .B(n36), .Y(n54) );
XOR2X1TS U122 ( .A(n52), .B(in2[9]), .Y(n64) );
NOR2X1TS U123 ( .A(n57), .B(n35), .Y(n52) );
XNOR2X1TS U124 ( .A(n92), .B(n91), .Y(res[12]) );
NAND2X1TS U125 ( .A(n46), .B(n90), .Y(n92) );
XOR2X1TS U126 ( .A(n89), .B(n88), .Y(res[13]) );
AOI21X1TS U127 ( .A0(n91), .A1(n46), .B0(n70), .Y(n88) );
XOR2X1TS U128 ( .A(n85), .B(n84), .Y(res[14]) );
INVX2TS U129 ( .A(n81), .Y(n83) );
NAND4X8TS U130 ( .A(n44), .B(n43), .C(n42), .D(n41), .Y(n107) );
INVX2TS U131 ( .A(n87), .Y(n72) );
NAND2X1TS U132 ( .A(n65), .B(n36), .Y(n66) );
XNOR2X1TS U133 ( .A(n66), .B(in2[10]), .Y(n95) );
NAND2X1TS U134 ( .A(in2[0]), .B(n36), .Y(n102) );
AOI21X1TS U135 ( .A0(in2[1]), .A1(n102), .B0(in1[1]), .Y(n101) );
OAI21X1TS U136 ( .A0(in2[1]), .A1(in2[0]), .B0(n36), .Y(n104) );
AOI21X1TS U137 ( .A0(in2[2]), .A1(n104), .B0(in1[2]), .Y(n103) );
AOI21X1TS U138 ( .A0(in2[3]), .A1(n106), .B0(in1[3]), .Y(n105) );
NAND2X1TS U139 ( .A(n107), .B(n36), .Y(n108) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL6_syn.sdf");
endmodule
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`ifdef GPU_PIPELINE_ADDER
`include "adder_half_precision.v"
`endif
`ifdef GPU_PIPELINE_MULT
`include "mult_half_precision.v"
`endif
`ifdef GPU_PIPELINE_DIVIDER
`include "div_half_precision.v"
`endif
`ifdef GPU_PIPELINE
`include "adder_half_precision.v"
`include "mult_half_precision.v"
`include "div_half_precision.v"
`include "graphics_pipeline.v"
`endif
`ifdef GPU_MEMORY_UART
`include "mem_ctrl.v"
`endif
`ifdef GPU_MEMORY_CONTROLLER
`include "mem_ctrl.v"
`include "sram.v"
`endif
module gpu_tb();
import gpu_pkg::*;
import uvm_pkg::*;
//Modules in Graphic Pipeline
wire [15:0] in0_adder, in1_adder, out_adder;
wire [15:0] in0_mult, in1_mult, out_mult;
wire [15:0] in0_divider, in1_divider, out_divider;
wire excep_divider;
//Graphic Pipeline
wire [15:0] camVerX, camVerY, camVerZ;
wire [15:0] camDc;
wire [15:0] cosRoll, cosPitch, cosYaw;
wire [15:0] senRoll, senPitch, senYaw;
wire [15:0] scaleX, scaleY, scaleZ;
wire [15:0] transX, transY, transZ;
wire [15:0] vertexX, vertexY, vertexZ;
wire [15:0] outX, outY;
wire outException;
//Memory Controller
wire [7:0] rx_byte, tx_byte;
wire rx_ready, tx_ready, tx_sent, rx_error;
wire [21:0] sram_address;
wire [15:0] sram_data;
wire validRequest, write, completeRequest;
logic clk;
//Interfaces
adder_ifc adder_ifc();
mult_ifc mult_ifc();
divider_ifc divider_ifc();
pipeline_ifc pipeline_ifc();
uart_ifc uart_ifc();
sram_ifc sram_ifc();
`ifdef GPU_PIPELINE_ADDER
adderhalfprecision adder(
.o_Sum(out_adder),
.i_Addend1(in0_adder),
.i_Addend2(in1_adder)
);
`endif
`ifdef GPU_PIPELINE_MULT
multhalfprecision multiplier(
.o_Product(out_mult),
.i_Factor1(in0_mult),
.i_Factor2(in1_mult)
);
`endif
`ifdef GPU_PIPELINE_DIVIDER
divhalfprecision divider(
.o_Quotient(out_divider),
.o_Exception(Excep_divider),
.i_Dividend(in0_divider),
.i_Divisor(in1_divider)
);
`endif
`ifdef GPU_PIPELINE
graphicspipeline pipeline(
.o_X(outX),
.o_Y(outY),
.o_Exception(outException),
.i_CamVerX(camVerX), .i_CamVerY(camVerY), .i_CamVerZ(camVerZ),
.i_CamDc(camDc),
.i_CosRoll(cosRoll), .i_CosPitch(cosPitch), .i_CosYaw(cosYaw),
.i_SenRoll(senRoll), .i_SenPitch(senPitch), .i_SenYaw(senYaw),
.i_ScaleX(scaleX), .i_ScaleY(scaleY), .i_ScaleZ(scaleZ),
.i_TranslX(transX), .i_TranslY(transY), .i_TranslZ(transZ),
.i_VertexX(vertexX), .i_VertexY(vertexY), .i_VertexZ(vertexZ)
);
`endif
`ifdef GPU_MEMORY_UART
mem_ctrl mem_controller(
.iClock(clk),
.iRxByte(rx_byte),
.oTxByte(tx_byte),
.iRxReady(rx_ready),
.oTxReady(tx_ready),
.iTxSent(tx_sent),
.iRxError(rx_error),
.ioData(sram_data),
.iValidRead(completeRequest),
.oAddress(sram_address),
.oValidRequest(validRequest),
.oWrite(write)
);
`endif
//--------------------------------------------
//Adder Module
assign in0_adder = adder_ifc.in0_adder;
assign in1_adder = adder_ifc.in1_adder;
assign adder_ifc.out_adder = out_adder;
assign adder_ifc.base.clk = clk;
//--------------------------------------------
//Mult Module
assign in0_mult = mult_ifc.in0_mult;
assign in1_mult = mult_ifc.in1_mult;
assign mult_ifc.out_mult = out_mult;
assign mult_ifc.base.clk = clk;
//--------------------------------------------
//Divider Module
assign in0_divider = divider_ifc.in0_divider;
assign in1_divider = divider_ifc.in1_divider;
assign divider_ifc.out_divider = out_divider;
assign divider_ifc.base.clk = clk;
//--------------------------------------------
//Pipeline Module
assign camVerX = pipeline_ifc.camVerX;
assign camVerY = pipeline_ifc.camVerY;
assign camVerZ = pipeline_ifc.camVerZ;
assign camDc = pipeline_ifc.camDc;
assign cosRoll = pipeline_ifc.cosRoll;
assign cosPitch = pipeline_ifc.cosPitch;
assign cosYaw = pipeline_ifc.cosYaw;
assign senRoll = pipeline_ifc.senRoll;
assign senPitch = pipeline_ifc.senPitch;
assign senYaw = pipeline_ifc.senYaw;
assign scaleX = pipeline_ifc.scaleX;
assign scaleY = pipeline_ifc.scaleY;
assign scaleZ = pipeline_ifc.scaleZ;
assign transX = pipeline_ifc.transX;
assign transY = pipeline_ifc.transY;
assign transZ = pipeline_ifc.transZ;
assign vertexX = pipeline_ifc.vertexX;
assign vertexY = pipeline_ifc.vertexY;
assign vertexZ = pipeline_ifc.vertexZ;
assign pipeline_ifc.outX = outX;
assign pipeline_ifc.outY = outY;
assign pipeline_ifc.outException = outException;
assign pipeline_ifc.base.clk = clk;
//--------------------------------------------
//UART Module
assign rx_byte = uart_ifc.rx_byte;
assign uart_ifc.tx_byte = tx_byte;
assign rx_ready = uart_ifc.rx_ready;
assign uart_ifc.tx_ready = tx_ready;
assign tx_sent = uart_ifc.tx_sent;
assign rx_error = uart_ifc.rx_error;
assign uart_ifc.base.clk = clk;
//--------------------------------------------
//SRAM Module
assign sram_ifc.address = sram_address;
assign sram_ifc.validRequest = validRequest;
assign sram_ifc.write = write;
assign completeRequest = sram_ifc.completeRequest;
assign sram_ifc.data = sram_data;
assign sram_ifc.base.clk = clk;
always #5 clk <= !clk;
initial begin
uvm_resource_db#(virtual adder_ifc)::set(.scope("*"), .name("adder_ifc"), .val(adder_ifc));
uvm_resource_db#(virtual mult_ifc)::set(.scope("*"), .name("mult_ifc"), .val(mult_ifc));
uvm_resource_db#(virtual divider_ifc)::set(.scope("*"), .name("divider_ifc"), .val(divider_ifc));
uvm_resource_db#(virtual pipeline_ifc)::set(.scope("*"), .name("pipeline_ifc"), .val(pipeline_ifc));
uvm_resource_db#(virtual uart_ifc)::set(.scope("*"), .name("uart_ifc"), .val(uart_ifc));
uvm_resource_db#(virtual sram_ifc)::set(.scope("*"), .name("sram_ifc"), .val(sram_ifc));
clk = 0;
run_test("gpu_test");
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT4.v,v 1.10 2007/06/05 00:00:54 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 4-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT4.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf.
// 03/11/05 - Add LOC paramter;
// 06/04/07 - Add wire declaration to internal signal.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT4 (O, I0, I1, I2, I3);
parameter INIT = 16'h0000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, I2, I3;
wire a0, a1, a2, a3;
wire o_out_tmp;
reg o_out;
reg tmp;
buf b0 (a0, I0);
buf b1 (a1, I1);
buf b2 (a2, I2);
buf b3 (a3, I3);
buf b4 (O, o_out_tmp);
assign o_out_tmp = o_out;
always @( a3 or a2 or a1 or a0 ) begin
tmp = a0 ^ a1 ^ a2 ^ a3;
if ( tmp == 0 || tmp == 1)
o_out = INIT[{a3, a2, a1, a0}];
else
o_out = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {a1, a0}),
lut4_mux4 ( INIT[11:8], {a1, a0}),
lut4_mux4 ( INIT[7:4], {a1, a0}),
lut4_mux4 ( INIT[3:0], {a1, a0}) }, {a3, a2});
end
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] ^ d[1]) == 0 && (d[2] ^ d[3]) == 0 && (d[0] ^ d[2]) == 0)
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] == d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] == d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] == d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] == d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i; string s; cin >> t; while (t--) { cin >> s; int cap = 0, sm = 0, dig = 0; for (i = 0; i < s.size(); i++) { if (s[i] >= 65 && s[i] <= 90) { cap++; } else if (s[i] >= 97 && s[i] <= 122) { sm++; } else if (s[i] >= 48 && s[i] <= 57) { dig++; } } if (sm == 0) { if (cap > 1) { for (i = 0; i < s.size(); i++) { if (s[i] >= 65 && s[i] <= 90) { s[i] = a ; break; } } } else if (dig > 1) { for (i = 0; i < s.size(); i++) { if (s[i] >= 48 && s[i] <= 57) { s[i] = a ; break; } } } else { s = s + a ; } } if (cap == 0) { if (sm > 1) { for (i = 0; i < s.size(); i++) { if (s[i] >= 97 && s[i] <= 122) { s[i] = A ; break; } } } else if (dig > 1) { for (i = 0; i < s.size(); i++) { if (s[i] >= 48 && s[i] <= 57) { s[i] = A ; break; } } } else { s = s + A ; } } if (dig == 0) { if (cap > 1) { for (i = 0; i < s.size(); i++) { if (s[i] >= 65 && s[i] <= 90) { s[i] = 1 ; break; } } } else if (sm > 1) { for (i = 0; i < s.size(); i++) { if (s[i] >= 97 && s[i] <= 122) { s[i] = 1 ; break; } } } else { s = s + 1 ; } } cout << s << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; struct P { int t, id; bool operator<(const P &tmp) const { if (t != tmp.t) return t < tmp.t; return id < tmp.id; } } p[N]; priority_queue<int, vector<int>, greater<int> > qu; queue<int> q; set<int> s; long long ans[N]; int n, t; long long now = 0, ed = -1, nid = 0; void gao() { if (qu.empty()) return; int x = qu.top(); if (!s.empty() && (*s.begin()) < x) return; if (q.empty()) ed += t; qu.pop(); q.push(x); s.insert(x); } int main() { scanf( %d%d , &n, &t); for (int i = 0; i < n; i++) scanf( %d , &p[i].t), p[i].id = i; sort(p, p + n); while (true) { if (nid < n && (ed >= p[nid].t || q.empty())) { now = p[nid].t; if (!s.empty() && (*s.begin()) < p[nid].id) qu.push(p[nid].id); else if (ed == p[nid].t) qu.push(p[nid].id); else { if (q.empty()) ed = now + t; q.push(p[nid].id); s.insert(p[nid].id); } nid++; } else if (!q.empty()) { int x = q.front(); q.pop(); now = max(now, ed); s.erase(x); ans[x] = ed; if (!q.empty()) ed += t; gao(); } else break; } for (int i = 0; i < n; i++) printf( %lld , ans[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_SYMBOL_V
`define SKY130_FD_SC_LP__DECAPKAPWR_SYMBOL_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decapkapwr ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [7:0] crc;
wire [61:59] ah = crc[5:3];
wire [61:59] bh = ~crc[4:2];
wire [41:2] al = {crc,crc,crc,crc,crc};
wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]};
reg sel;
wire [61:28] q = ( sel
? func(ah, al)
: func(bh, bl));
function [61:28] func;
input [61:59] inh;
input [41:2] inl;
reg [42:28] func_mid;
reg carry;
begin
carry = &inl[27:2];
func_mid = {1'b0,inl[41:28]} + {14'b0, carry};
func[61:59] = inh + {2'b0, func_mid[42]};
func[58:42] = {17{func_mid[41]}};
func[41:28] = func_mid[41:28];
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
//$write("%d %x\n", cyc, q);
if (cyc!=0) begin
cyc <= cyc + 1;
sel <= ~sel;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
sel <= 1'b1;
crc <= 8'h12;
end
if (cyc==2) if (q!=34'h100000484) $stop;
if (cyc==3) if (q!=34'h37fffeddb) $stop;
if (cyc==4) if (q!=34'h080001212) $stop;
if (cyc==5) if (q!=34'h1fffff7ef) $stop;
if (cyc==6) if (q!=34'h200000848) $stop;
if (cyc==7) if (q!=34'h380001ebd) $stop;
if (cyc==8) if (q!=34'h07fffe161) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module foo (/*AUTOARG*/
// Outputs
d,
// Inputs
b, a
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input a; // To foo2 of foo2.v
input b; // To foo2 of foo2.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output d; // From foo2 of foo2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
// End of automatics
foo2 foo2 (/*AUTOINST*/
// Outputs
.d (d),
// Inputs
.a (a),
.b (b));
endmodule
module foo2 (/*AUTOARG*/
// Outputs
d,
// Inputs
a, b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
// End of automatics
input a;
input b;
output d;
//{ Behavioral verilog code here}
endmodule
|
module top;
reg pass = 1'b1;
integer delay;
reg [3:0] in = 4'h0;
reg [7:0] result [1:0];
initial begin
result[0] <= #10 8'h00;
if ($simtime != 0 || result[0] !== 8'bx) begin
$display("Failed #10 blocked at %0t, expected 8'hxx, got %h",
$simtime, result[0]);
pass = 1'b0;
end
@(result[0]);
if ($simtime != 10 || result[0] !== 8'h00) begin
$display("Failed #10 at %0t, expected 8'h00, got %h",
$simtime, result[0]);
pass = 1'b0;
end
result[0][8:5] <= #10 4'hb;
@(result[0]);
if ($simtime != 20 || result[0] !== 8'h60) begin
$display("Failed MSB #10 at %0t, expected 8'h60, got %h",
$simtime, result[0]);
pass = 1'b0;
end
result[0][1:-2] <= #10 4'hb;
@(result[0]);
if ($simtime != 30 || result[0] !== 8'h62) begin
$display("Failed LSB #10 at %0t, expected 8'h62, got %h",
$simtime, result[0]);
pass = 1'b0;
end
delay = 20;
result[1] <= #delay 8'h00;
if ($simtime != 30 || result[1] !== 8'bx) begin
$display("Failed #delay blocked at %0t, expected 8'hxx, got %h",
$simtime, result[1]);
pass = 1'b0;
end
@(result[1]);
if ($simtime != 50 || result[1] !== 8'h00) begin
$display("Failed #delay at %0t, expected 8'h00, got %h",
$simtime, result[1]);
pass = 1'b0;
end
result[1][8:5] <= #delay 4'hb;
@(result[1]);
if ($simtime != 70 || result[1] !== 8'h60) begin
$display("Failed MSB #delay at %0t, expected 8'h60, got %h",
$simtime, result[1]);
pass = 1'b0;
end
result[1][1:-2] <= #delay 4'hb;
@(result[1]);
if ($simtime != 90 || result[1] !== 8'h62) begin
$display("Failed LSB #delay at %0t, expected 8'h62, got %h",
$simtime, result[1]);
pass = 1'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 7; const long long INF = 1LL << 60; const long long mod = 1e9 + 7; const long double eps = 1e-8; const long double pi = acos(-1.0); template <class T> inline bool chmax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } template <class T> inline bool chmin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } struct P { long long x, y; }; long double ex(P s, P t, P r) { long double x1 = (long double)t.x - (long double)s.x; long double y1 = (long double)t.y - (long double)s.y; long double x2 = (long double)r.x - (long double)s.x; long double y2 = (long double)r.y - (long double)s.y; return x1 * y2 - x2 * y1; } bool cross(P a, P b, P s, P t) { if (ex(a, b, s) * ex(a, b, t) > 0) return false; if (ex(b, a, s) * ex(b, a, t) > 0) return false; if (ex(t, s, a) * ex(t, s, b) > 0) return false; return ex(s, t, a) * ex(s, t, b) < eps; } pair<bool, pair<long double, long double>> intersection_ls(P a1, P a2, P b1, P b2) { long double d1 = abs(ex(b1, a1, b2)); long double d2 = abs(ex(b1, a2, b2)); if (!cross(a1, a2, b1, b2)) { return {false, {0.0, 0.0}}; } return {true, {a1.x + (a2.x - a1.x) * d1 / (d1 + d2), a1.y + (a2.y - a1.y) * d1 / (d1 + d2)}}; } long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } void solve() { long long n; cin >> n; vector<pair<P, P>> vec; long long ans = 0; for (long long i = 0; i < n; i++) { long long ax, ay, bx, by; cin >> ax >> ay >> bx >> by; vec.push_back({P{ax, ay}, P{bx, by}}); ans += gcd(abs(ax - bx), abs(ay - by)) + 1; } map<pair<long long, long long>, long long> mp; for (long long i = 0; i < n; i++) { for (long long j = i + 1; j < n; ++j) { auto res = intersection_ls(vec[i].first, vec[i].second, vec[j].first, vec[j].second); if (!res.first) continue; long double X = res.second.first, Y = res.second.second; if (floor(X + eps) < X + 2 * eps && floor(X + eps) > X - 2 * eps) { if (floor(Y + eps) < Y + 2 * eps && floor(Y + eps) > Y - 2 * eps) { mp[{floor(X + eps), floor(Y + eps)}]++; } } } } for (auto p : mp) { long long k = 2; while (k * (k - 1) / 2 <= p.second) { if (k * (k - 1) / 2 == p.second) { ans -= (k - 1); break; } ++k; } } cout << ans << endl; } signed main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_LP_V
`define SKY130_FD_SC_LP__OR4_LP_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_lp (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_lp (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_LP_V
|
#include <bits/stdc++.h> int a[100005], s[100005]; int main() { int l, r, q1, q2, i, N, S; scanf( %d%d%d%d%d , &N, &l, &r, &q1, &q2); s[0] = 0; for (i = 1; i <= N; i++) { scanf( %d , &a[i]); s[i] = s[i - 1] + a[i]; } int mx = s[N] * l + q1 * (N - 1); for (i = 0; i <= N; i++) { int t = s[i] * l + (s[N] - s[i]) * r; int p = N - 2 * i; if (p < 0) p = -p; if (p) p--; if (l > r) t += p * q2; else t += p * q1; if (t < mx) mx = t; } printf( %d n , mx); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; using vi = vector<int>; const int N = 4e5; vi cnt(N, 0); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int a; cin >> a; string s; cin >> s; int n = s.size(); for (int i = 0; i < n; i++) { int sum = 0; for (int j = i; j < n; j++) { sum += int(s[j] - 0 ); cnt[sum]++; } } ll ans = 0; if (a == 0) { for (int i = 0; i < N; i++) ans += cnt[i]; ans = 2 * cnt[0] * ans - 1LL * cnt[0] * cnt[0]; } else { for (int i = 1; i < N; i++) { if (a % i) continue; int b = a / i; if (b >= N) continue; ans += 1LL * cnt[i] * cnt[b]; } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; int n, m, f[2001] = {0}; bool p, a[2001][2001]; string st; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> st; for (int j = 0; j < m; j++) if (st[j] == 1 ) { a[i][j + 1] = true; f[j + 1]++; } else a[i][j + 1] = false; } for (int i = 1; i <= n; i++) { p = true; for (int j = 1; j <= m; j++) if (f[j] == 1 && a[i][j] == 1) p = false; if (p) { cout << YES ; return 0; } } cout << NO ; } |
#include <bits/stdc++.h> using namespace std; int n; long long val[2001000]; int f[2001000], pre[2001000]; void getans(long long F) { for (int i = 1; i <= n + n; i++) f[i] = 0, pre[i] = i; int pl = 1; int ans = 0x7fffffff; for (int i = n + 1; i <= n + n; i++) { while (pl < i && val[i] - val[pl] > F) pl++; f[i] = f[pl] + 1; pre[i] = pre[pl]; if (i - pre[i] >= n) ans = min(ans, f[i]); } printf( %d n , ans); } void solve() { int q; scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) scanf( %lld , &val[i]), val[i + n] = val[i]; for (int i = 2; i <= n + n; i++) val[i] += val[i - 1]; for (int i = 1; i <= q; i++) { long long t; scanf( %lld , &t); getans(t); } } int main() { solve(); fclose(stdin); fclose(stdout); return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long TESTS = 1; while (TESTS--) { long long n, x, y; cin >> n >> x >> y; string s; cin >> s; long long cnt = 0; char c = s[0]; for (auto i : s) if (i == c) continue; else { if (c == 0 ) cnt++; c = i; } if (c == 0 ) cnt++; if (!cnt) return cout << 0, 0; if (x < y) cout << x * (cnt - 1) + y; else cout << cnt * y; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int bas = 23333; const long long mod = 9999999999973ll; int N, M, S[26], L[555]; char C[255][255]; long long H[26], W[255][255][255], G[555]; int manacher(int n) { int k = 0, m = 0, res = 0; memset(L, 0, sizeof(L)); for (int i = 1; i <= n; i++) { if (G[i] == -1) { continue; } int l = (m > i) ? min(L[2 * k - i], m - i) : 1; while (G[i - l] != -1 && G[i + l] != -1 && G[i - l] == G[i + l]) { l++; } if (l + i > m) { m = l + i; k = i; } L[i] = l; res += l; } return (res - N - 1) >> 1; } int main() { scanf( %d%d n , &N, &M); long long h = 1; for (int i = 0; i < 26; i++) { h = h * bas % mod; H[i] = h; } for (int i = 1; i <= N; i++) { scanf( %s , C[i] + 1); for (int j = 1; j <= M; j++) { C[i][j] -= a ; W[i][j][j] = H[C[i][j]]; for (int k = j - 1; k > 0; k--) { W[i][k][j] = W[i][k + 1][j] + H[C[i][k]]; if (W[i][k][j] >= mod) { W[i][k][j] -= mod; } } memset(S, 0, sizeof(S)); int cnt = 0; for (int k = j; k > 0; k--) { S[C[i][k]]++; if (S[C[i][k]] & 1) { cnt++; } else { cnt--; } if (cnt > 1) { W[i][k][j] = -1; } } } } long long ANS = 0; for (int j = 1; j <= M; j++) { for (int k = j; k <= M; k++) { memset(G, 0, sizeof(G)); G[0] = -1; G[(N + 1) << 1] = -1; for (int i = 1; i <= N; i++) { G[i << 1] = W[i][j][k]; } ANS += manacher((N << 1) | 1); } } printf( %lld , ANS); return 0; } |
#include <bits/stdc++.h> using namespace std; const int OO = 1e9; const long long INF = 1e18; const int irand(int lo, int hi) { return ((double)rand() / (RAND_MAX + 1.0)) * (hi - lo + 1) + lo; } const long long lrand(long long lo, long long hi) { return ((double)rand() / (RAND_MAX + 1.0)) * (hi - lo + 1) + lo; } template <typename T> T getnum() { int sign = 1; T ret = 0; char c; do { c = getchar(); } while (c == || c == n ); if (c == - ) sign = -1; else ret = c - 0 ; while (1) { c = getchar(); if (c < 0 || c > 9 ) break; ret = 10 * ret + c - 0 ; } return sign * ret; } inline void ini(int& x) { x = getnum<int>(); } inline void scani(int& x) { scanf( %d , &x); } const int N = 1e5 + 5; int n; int a[N], b[N]; long long ans = 0; vector<pair<int, int> > ins; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.setf(ios::fixed); cout.setf(ios::showpoint); cout.precision(10); cin >> n; string str; cin >> str; for (int i = 0; i < n; i++) { a[i + 1] = str[i] - 0 ; } cin >> str; for (int i = 0; i < n; i++) { b[i + 1] = str[i] - 0 ; } int difa = 0, difb = 0; for (int i = 1; i <= n; i += 1) { if (i & 1) { difa += a[i]; difb += b[i]; } else { difa -= a[i]; difb -= b[i]; } } if (difa != difb) { cout << -1 << n ; return 0; } int f = 2; for (int i = 1; i <= n - 1; i += 1) { if (f == i) f++; while (a[i] > b[i]) { a[i]--; while (1) { assert(f <= n); if ((f - i) & 1) { if (a[f] == 0) { f++; } else { a[f]--; break; } } else { if (a[f] == 9) { f++; } else { a[f]++; break; } } } ans += f - i; if (ins.size() < 100000) { for (int j = f - 1; j >= i; j -= 1) { if ((j - i) & 1) { ins.push_back({j, 1}); } else { ins.push_back({j, -1}); } } } } while (a[i] < b[i]) { a[i]++; while (1) { assert(f <= n); if ((f - i) & 1) { if (a[f] == 9) { f++; } else { a[f]++; break; } } else { if (a[f] == 0) { f++; } else { a[f]--; break; } } } ans += f - i; if (ins.size() < 100000) { for (int j = f - 1; j >= i; j -= 1) { if ((j - i) & 1) { ins.push_back({j, -1}); } else { ins.push_back({j, 1}); } } } } } cout << ans << n ; for (int i = 0; i < min(100000, (int)ins.size()); i++) { cout << ins[i].first << << ins[i].second << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n, m, k; set<int> a[maxn], b[maxn]; set<int, greater<int> > c[maxn], d[maxn]; int main() { scanf( %d%d%d , &n, &m, &k); int x, y, nx, ny, lx = 0, ly = 0, rx = n + 1, ry = m + 1, dir = 1; long long ans = 1; for (int i = 1; i <= k; i++) { scanf( %d%d , &x, &y); a[x].insert(y), c[x].insert(y); b[y].insert(x), d[y].insert(x); } x = 1, y = 1; for (int i = 1;; i++) { nx = x, ny = y; if (dir == 1) { auto t = a[x].lower_bound(y); ny = ((t == a[x].end()) ? ry : min(*t, ry)) - 1, lx = x; } if (dir == 2) { auto t = b[y].lower_bound(x); nx = ((t == b[y].end()) ? rx : min(*t, rx)) - 1, ry = y; } if (dir == 3) { auto t = c[x].lower_bound(y); ny = ((t == c[x].end()) ? ly : max(*t, ly)) + 1, rx = x; } if (dir == 4) { auto t = d[y].lower_bound(x); nx = ((t == d[y].end()) ? lx : max(*t, lx)) + 1, ly = y; } if (x == nx && y == ny && i > 1) break; ans += abs(nx - x) + abs(ny - y), x = nx, y = ny, dir = (dir < 4) ? dir + 1 : 1; } if (ans == (long long)n * m - k) printf( Yes n ); else printf( No n ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:03:15 02/21/2016
// Design Name:
// Module Name: Contador_Ascendente_Descendente
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_Ascendente_Descendente
# (parameter N = 4) // Para definir el número de bits del contador
(
input wire clk,
input wire reset,
input wire enUP,
input wire enDOWN,
output wire [N-1:0] q
);
//Signal Declarations
reg [N-1:0] q_act, q_next;
//Body of "state" registers
always@(posedge clk,posedge reset)
if(reset)
q_act <= 0;
else
q_act <= q_next;
//Specified functions of the counter
always@*
if(enUP)
q_next = q_act + 1'b1;
else if (enDOWN)
q_next = q_act - 1'b1;
else
q_next = q_act;
//Output Logic
assign q = q_act;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; vector<long long> p; int main() { int n, q; cin >> n >> q; string s; cin >> s; p.resize(1e5 + 1); p[0] = 1; for (int i = 1; i <= 1e5; i++) { p[i] = (p[i - 1] * 2) % MOD; } vector<long long> kum(n + 1); kum[0] = 0; for (int i = 0; i < n; i++) { if (s[i] == 1 ) { kum[i + 1] = kum[i] + 1; } else { kum[i + 1] = kum[i]; } } for (int i = 0; i < q; i++) { int l, r; cin >> l >> r; long long kol_1 = kum[r] - kum[l - 1]; long long kol_0 = r - l + 1 - kol_1; long long ans_1 = p[kol_1] - 1; long long ans_0 = ans_1 * (p[kol_0] - 1); cout << (ans_1 + ans_0) % MOD << n ; } return 0; } |
#include <bits/stdc++.h> int main() { int n, d, t, x, y, z, m; scanf( %d %d %d , &n, &d, &m); z = n - d; while (m--) { scanf( %d %d , &x, &y); if (x > n || y > n) { printf( NO n ); } else { if (y >= abs(x - d) && y <= n - (abs(z - x))) { printf( YES n ); } else { printf( NO n ); } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_SYMBOL_V
`define SKY130_FD_SC_HS__DLRTN_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int MAX = 2e5 + 5; const long long MAX2 = 11; const long long MOD = 998244353; const long long MOD2 = 1000005329; const long long INF = 2e18; const int dr[] = {1, 0, -1, 0, 1, 1, -1, -1, 0}; const int dc[] = {0, 1, 0, -1, 1, -1, 1, -1, 0}; const double pi = acos(-1); const double EPS = 1e-9; const int block = 2000; int n, m, a, b, c, v[205][205], ans; pair<double, pair<int, int> > e[205 * 205]; double le, ri, m1, m2, n1, n2, a1, a2, u[205][205], nx; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) if (i != j) v[i][j] = MOD; for (int i = 1; i <= m; ++i) { cin >> a >> b >> c; e[i] = {c, {a, b}}; v[a][b] = v[b][a] = min(v[a][b], c); } for (int k = 1; k <= n; ++k) for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) v[i][j] = min(v[i][j], v[i][k] + v[k][j]); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) u[i][j] = v[i][j]; ans = 1e9; for (int i = 1; i <= m; ++i) { a = e[i].second.first, b = e[i].second.second; le = 0.0, ri = e[i].first; for (int k = 1; k <= 40; ++k) { m1 = (le + le + ri) / 3.0, n1 = e[i].first - m1; m2 = (le + ri + ri) / 3.0, n2 = e[i].first - m2; a1 = a2 = 0.0; for (int j = 1; j <= n; ++j) { a1 = max(a1, min(u[a][j] + m1, u[b][j] + n1)); a2 = max(a2, min(u[a][j] + m2, u[b][j] + n2)); } if (a1 < a2) ri = m2; else le = m1; } ans = min(ans, (int)round(a1 * 2.0)); nx = m1; le = 0.0, ri = nx; for (int k = 1; k <= 40; ++k) { m1 = (le + le + ri) / 3.0, n1 = e[i].first - m1; m2 = (le + ri + ri) / 3.0, n2 = e[i].first - m2; a1 = a2 = 0.0; for (int j = 1; j <= n; ++j) { a1 = max(a1, min(u[a][j] + m1, u[b][j] + n1)); a2 = max(a2, min(u[a][j] + m2, u[b][j] + n2)); } if (a1 < a2) ri = m2; else le = m1; } ans = min(ans, (int)round(a1 * 2.0)); le = nx, ri = e[i].first; for (int k = 1; k <= 40; ++k) { m1 = (le + le + ri) / 3.0, n1 = e[i].first - m1; m2 = (le + ri + ri) / 3.0, n2 = e[i].first - m2; a1 = a2 = 0.0; for (int j = 1; j <= n; ++j) { a1 = max(a1, min(u[a][j] + m1, u[b][j] + n1)); a2 = max(a2, min(u[a][j] + m2, u[b][j] + n2)); } if (a1 < a2) ri = m2; else le = m1; } ans = min(ans, (int)round(a1 * 2.0)); } if (ans & 1) cout << ans / 2 << .5 n ; else cout << ans / 2 << .0 n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<int> gru; for (int i = 0; i < n; i++) { gru.push_back(i + 1); } long long lead = 1; for (int i = 0; i < k; i++) { long long a; cin >> a; lead += a; lead = lead % gru.size(); if (lead == 0) { lead = gru.size(); } cout << gru[lead - 1] << ; gru.erase(gru.begin() + lead - 1); } } |
#include <bits/stdc++.h> using namespace std; void read_file(bool outToFile = true) {} int main() { read_file(); string a, b; char str[1000000 + 1]; while (scanf( %s , str) != EOF) { a = str; scanf( %s , str); b = str; int n = a.length(), m = b.length(); if (n != m) { printf( NO n ); continue; } if (n == 1) { string ans = a == b ? YES : NO ; printf( %s n , ans.c_str()); continue; } bool aHasOne, bHasOne; aHasOne = bHasOne = 0; for (int i = 0; i < n; i++) { if (a[i] == 1 ) aHasOne = 1; if (b[i] == 1 ) bHasOne = 1; } string ans = aHasOne == bHasOne ? YES : NO ; printf( %s n , ans.c_str()); } } |
#include <bits/stdc++.h> long long cmpfunc(const void* a, const void* b) { return (*(long long*)a - *(long long*)b); } int main(void) { long long int test, i, j, n, count, flag = 0, o1 = 0, o2 = 0, b1, x, m, l, max, sum2, min, f, r, o, sum1, sum = 0, y, count1 = 0, a[1000000]; scanf( %lld , &n); count = 0; f = 0; for (i = 0; i < n; i++) { scanf( %lld , &x); if (a[x] == 0 && x != 0) { count++; a[x]++; } } printf( %lld n , count); return 0; } |
#include <bits/stdc++.h> #define N 410 #define ll long long #define ull unsigned long long //#define mo (ll)((ll)1e9+7) #define squ(x) ((x)*(x)) #define db double #define all(x) x.begin(),x.end() #define cmax(a,b) a=max(a,b) #define cmin(a,b) a=min(a,b) #define rep(i,l,r) for(register int i=l;i<=r;++i) #define drep(i,r,l)for(register int i=r;i>=l;--i) #define pb push_back #define inline inline __attribute__((always_inline)) using namespace std; inline ll read() { ll x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) {if (ch == - )f = -1; ch = getchar();} while (ch >= 0 && ch <= 9 ) {x = x * 10 + ch - 0 ; ch = getchar();} return x * f; } ll mo; ll dp[N][N]; int fac[N], inv[N], bit[N]; ll Pow(ll a, ll b) { ll res = 1; a %= mo; for (; b; b >>= 1, a = a * a % mo) if (b & 1) res = res * a % mo; return res; } void init_inv(int n) { fac[0] = 1; rep(i, 1, n)fac[i] = (ll)fac[i - 1] * i % mo; inv[n] = Pow(fac[n], mo - 2); drep(i, n, 1) inv[i - 1] = (ll)inv[i] * i % mo; } ll C(int n, int m) { if (n < m)return 0; return 1ll * fac[n] * inv[m] % mo * inv[n - m] % mo; } int main() { int n = read(); mo = read(); init_inv(n); bit[0] = 1; rep(i, 1, 400)bit[i] = bit[i - 1] * 1ll * 2 % mo; dp[0][0] = 1; rep(i, 0, n)rep(j, 0, i)if (dp[i][j] > 0) { rep(k, 1, n - i)(dp[i + k + 1][j + k] += dp[i][j] * 1ll * C(j + k, k) % mo * bit[k - 1] % mo) %= mo; } ll ans = 0; rep(i, 1, n)(ans += dp[n + 1][i]) %= mo; printf( %lld n , ans); return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_join
*/
module test_axis_frame_join_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter TAG_ENABLE = 1;
parameter TAG_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg [TAG_WIDTH-1:0] tag = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready,
tag
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_axis_frame_join_4.lxt");
$dumpvars(0, test_axis_frame_join_4);
end
axis_frame_join #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.TAG_ENABLE(TAG_ENABLE),
.TAG_WIDTH(TAG_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// config
.tag(tag),
// status
.busy(busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s, len; scanf( %d%d%d , &n, &s, &len); vector<int> a(n); for (int &t : a) scanf( %d , &t); if (len > n) { puts( -1 ); return 0; } multiset<int> ms; vector<int> dp(n + 1, 1 << 20); for (int r = 0; r < len; r++) { ms.insert(a[r]); } auto getDif = [](multiset<int> &ms) { return *ms.rbegin() - *ms.begin(); }; int ans = -1; dp[0] = 0; if (getDif(ms) <= s) dp[len] = 1; int st = 0; multiset<int> best; best.insert(dp[0]); for (int r = len; r < n; r++) { best.insert(dp[r - len + 1]); ms.insert(a[r]); while (!best.empty() && getDif(ms) > s) { best.erase(best.find(dp[st++])); ms.erase(ms.find(a[r - ms.size() + 1])); } if (!best.empty()) dp[r + 1] = *best.begin() + 1; } cout << (dp[n] >= (1 << 20) ? -1 : dp[n]) << endl; } |
/*
Project: RECON 2017
Author: Jeff Lieu <>
Description: recon_0_top level
*/
/* Note that the PORT_0_WIDTH doesn't propagate to the NIOS system */
module recon_0_top #(parameter PORT_0_WIDTH = 32) (
input sys_clk,
input sys_rstn,
inout [ PORT_0_WIDTH-1:0] port_0_io,
output uart_0_txd,
input uart_0_rxd
);
wire [PORT_0_WIDTH-1:0] port_0_out;
wire [PORT_0_WIDTH-1:0] port_0_in;
wire [PORT_0_WIDTH-1:0] port_0_oe;
wire [PORT_0_WIDTH-1:0] port_0_opdrn;
wire cpu_clk, locked;
/*
PLL is put at the top to be shared across boards
THe output of the CPU clock is required to be 80MHz
*/
alt_pll pll(
.areset (~sys_rstn),
.inclk0 (sys_clk),
.c0 (cpu_clk),
.locked (locked));
buttonDebouncer
#( /* Debounce time - Count in nanosecond */
.pDEBOUNCE_PERIOD (100_000_000),
/* Clock Input period - Count in nanosecond */
.pCLKIN_PERIOD (20 ),
/* Size of button array */
.pARRAY_SIZE (1 ),
/*
Polarity configures the edge detection which edge would cause a tick
Buttons are default to active low, which means a "Button Down" event is generated when the signal level fall from High to Low
Active high (pPOLARITY = 1) means a Button Down when the signal level changes from Low to High
*/
.pPOLARITY (0)) resetDebounce
(
.clk (sys_clk),
.buttons (sys_rstn),
.buttonState (sys_rstn_db), /* In Verilog, you can have an implied net declaration */
.buttonUpTick (),
.buttonDwTick ()
);
/* NIOS System - Configured and Generated by QSYS */
recon_0 (
.clk_clk (cpu_clk), // clk.clk
.recon_io_0_io_port_io_out (port_0_out), // recon_io_0_io_port.io_out
.recon_io_0_io_port_io_opdrn (port_0_opdrn), // .io_opdrn
.recon_io_0_io_port_io_in (port_0_in), // .io_in
.recon_io_0_io_port_io_oe (port_0_oe), // .io_oe
.recon_timer_0_clock_tick_second (), // recon_timer_0_clock_tick.second
.recon_timer_0_clock_tick_millisecond (), // .millisecond
.recon_timer_0_clock_tick_microsec (), // .microsec
.reset_reset_n (sys_rstn_db), // reset.reset_n
.uart_0_rxd (uart_0_rxd),
.uart_0_txd (uart_0_txd)
);
/* You can Insert your own Debouncer for the Button Here if required */
genvar IO;
generate
for (IO = 0; IO<PORT_0_WIDTH;IO=IO+1)
begin : assign_io
assign port_0_io[IO] = (port_0_oe[IO]==1'b0||(port_0_out[IO]==1'b1&&port_0_opdrn[IO]==1'b1))?1'bz:port_0_out[IO];
assign port_0_in[IO] = port_0_io[IO];
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long n, m, s[7]; long long lin[100005][1 << 7], cov[1 << 7]; char ch[100005], ans[100005]; vector<long long> e[100005]; bool hall(long long x) { for (long long ss = 0; ss <= (1 << 6) - 1; ss++) { long long sum = 0; for (long long i = 1; i <= 6; i++) if (ss >> i - 1 & 1) sum += s[i]; if (lin[x][ss] < sum) return 0; } return 1; } signed main() { scanf( %s , ch + 1); n = strlen(ch + 1); for (long long i = 1; i <= n; i++) s[ch[i] - a + 1]++; cin >> m; for (long long i = 1, p; i <= m; i++) { string pat; cin >> p >> pat; for (long long j = 0; j < pat.length(); j++) e[p].push_back(pat[j] - a + 1), cov[p] |= 1 << pat[j] - a ; } for (long long i = 1; i <= n; i++) if (e[i].size() == 0) { cov[i] = (1 << 6) - 1; for (long long j = 1; j <= 6; j++) e[i].push_back(j); } for (long long i = n; i >= 1; i--) { for (long long s = 0; s <= (1 << 6) - 1; s++) if (s & cov[i]) lin[i][s] = lin[i + 1][s] + 1; else lin[i][s] = lin[i + 1][s]; } for (long long i = 1; i <= n; i++) { sort(e[i].begin(), e[i].end()); for (long long j = 0; j < e[i].size(); j++) { s[e[i][j]]--; if (hall(i + 1)) { ans[i] = (char)(e[i][j] + a - 1); break; } s[e[i][j]]++; } } if (strlen(ans + 1) < n) return puts( Impossible ), 0; for (long long i = 1; i <= n; i++) cout << ans[i]; return puts( ), 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_1_V
`define SKY130_FD_SC_LP__DLRBN_1_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_1_V
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
fritz
memory phase
*/
module cpu_mem(rst, clk, cpu_stall, ex_c_rfw, ex_c_wbsource, ex_c_drw,
ex_alu_r, ex_rfb, ex_rf_waddr, ex_jalra, ex_rt,
wb_wdata, p_c_rfw, p_c_wbsource, p_alu_r, dmem_data,
p_rf_waddr, p_jalra, dmem_addr, dmem_drw, dmem_in,
p_dout);
input rst, clk, cpu_stall;
input ex_c_rfw;
input [1:0] ex_c_wbsource;
input [1:0] ex_c_drw;
input [31:0] ex_alu_r;
input [31:0] ex_rfb;
input [4:0] ex_rf_waddr;
input [31:0] ex_jalra;
input [4:0] ex_rt;
input [31:0] wb_wdata;
output reg p_c_rfw;
output reg [1:0] p_c_wbsource;
output reg [31:0] p_alu_r;
output [31:0] dmem_data;
output reg [4:0] p_rf_waddr;
output reg [31:0] p_jalra;
output [31:0] dmem_addr;
output [1:0] dmem_drw;
input [31:0] dmem_in;
output reg [31:0] p_dout;
assign dmem_addr = ex_alu_r;
assign dmem_drw = ex_c_drw;
/* forwarding logic */
wire forward = p_c_rfw & (ex_rt == p_rf_waddr) & (p_rf_waddr != 0);
assign dmem_data = forward ? wb_wdata : ex_rfb;
always @(posedge clk) begin
if (!cpu_stall) begin
if (rst) begin
p_c_rfw <= 0;
p_c_wbsource <= 0;
p_alu_r <= 0;
p_rf_waddr <= 0;
p_jalra <= 0;
p_dout <= 0;
end else begin
p_c_rfw <= ex_c_rfw;
p_c_wbsource <= ex_c_wbsource;
p_alu_r <= ex_alu_r;
p_rf_waddr <= ex_rf_waddr;
p_jalra <= ex_jalra;
p_dout <= dmem_in;
end
/* debug statements, not synthesized by Xilinx */
//$display("MEM: %x %x %x %x %x %x", ex_rt, p_rf_waddr, wb_wdata, p_c_rfw, forward, dmem_data);
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:02:35 07/09/2015
// Design Name:
// Module Name: VIDEOGEN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VIDEOGEN
( input PixelClk,
input PixelClk2,
output reg [7:0] Red,
output reg [7:0] Green,
output reg [7:0] Blue,
output reg HSync,
output reg VSync,
output reg VideoEnable,
output reg [10:0] GetRow,
output reg StartBuffer,
input [8:0] BufferAddr,
input [15:0] BufferData,
input BufferWrite,
input [7:0] PalAddr,
input [31:0] PalData,
input PalWrite,
input [5:0] XOffsetData,
input [9:0] YOffsetData,
input OffsetWrite
);
`define H_SYNC_START 32
`define H_SYNC_STOP 129
`define H_VIDEO_START 258
`define H_VIDEO_STOP 1217
`define V_SYNC_START 1
`define V_SYNC_STOP 4
`define V_VIDEO_START 20
`define V_VIDEO_STOP 559
integer Row;
integer Col;
reg [23:0] Pixel;
wire [31:0] RowBufOut;
wire [31:0] PaletteOut;
reg [9:0] ReadBufAddr;
reg [5:0] XOffset;
reg [9:0] YOffset;
initial
begin
Row = 0;
Col = 0;
HSync = 0;
VSync = 0;
VideoEnable = 0;
GetRow = 11'h000;
StartBuffer = 0;
Pixel = 24'h000000;
ReadBufAddr = 10'h000;
Red = 8'h00;
Green = 8'h00;
Blue = 8'h00;
XOffset = 0;
YOffset = 0;
end
always @(posedge PixelClk2)
begin
if (OffsetWrite == 1)
begin
XOffset = XOffsetData;
YOffset = YOffsetData;
end
end
always @(negedge PixelClk2)
begin
Pixel = PaletteOut[23:0];
ReadBufAddr = ((Col < (`H_VIDEO_START - 2)) ? 10'h000 : (Col - (`H_VIDEO_START - 2))) + XOffset;
end
always @(posedge PixelClk)
begin
if ((StartBuffer == 1) && (BufferWrite == 1))
StartBuffer = 0;
if (Col < `H_VIDEO_STOP) Col = Col + 1;
else begin
Col = 0;
if (Row < `V_VIDEO_STOP)
begin
Row = Row + 1;
if (Row >= `V_VIDEO_START)
begin
GetRow = (Row - `V_VIDEO_START) + YOffset;
StartBuffer = 1;
end
end
else Row = 0;
end
HSync = ((Col < `H_SYNC_START) || (Col > `H_SYNC_STOP)) ? 0 : 1;
VSync = ((Row < `V_SYNC_START) || (Row > `V_SYNC_STOP)) ? 0 : 1;
if ((Col < `H_VIDEO_START) || (Row < `V_VIDEO_START))
begin
VideoEnable = 0;
Red = 8'h00;
Green = 8'h00;
Blue = 8'h00;
end
else
begin
VideoEnable = 1;
Red = Pixel[23:16];
Green = Pixel[15:8];
Blue = Pixel[7:0];
end
end
RAMB16BWER #(.DATA_WIDTH_A(18), // Port A Write Only 16 bit.
.DATA_WIDTH_B(9), // Port B Read Only 8 bit.
.DOA_REG(0),
.DOB_REG(0),
.EN_RSTRAM_A("FALSE"),
.EN_RSTRAM_B("FALSE"),
.SIM_DEVICE("SPARTAN6")
) ROWBUFFER (.DOA(),
.DOPA(),
.DOB(RowBufOut),
.DOPB(),
.ADDRA({1'b0,BufferAddr,4'b0000}),
.CLKA(PixelClk2),
.ENA(1'b1),
.REGCEA(1'b0),
.RSTA(1'b0),
.WEA({BufferWrite,BufferWrite,BufferWrite,BufferWrite}),
.DIA({16'h0000,BufferData}),
.DIPA(4'h0),
.ADDRB({1'b0,ReadBufAddr,3'b000}),
.CLKB(PixelClk2),
.ENB(1'b1),
.REGCEB(1'b0),
.RSTB(1'b0),
.WEB(4'h0),
.DIB(32'h00000000),
.DIPB(4'b0));
RAMB16BWER #(.DATA_WIDTH_A(36), // Port A Read Only 32 bit.
.DATA_WIDTH_B(36), // Port B Read/Write 32 bit.
.DOA_REG(0),
.DOB_REG(0),
.EN_RSTRAM_A("FALSE"),
.EN_RSTRAM_B("FALSE"),
.SIM_DEVICE("SPARTAN6"),
.INIT_00(256'h0000FFFF00FFFF0000FF00FF000000FF0000FF0000FF000000FFFFFF00000000)
) PALETTE (.DOA(PaletteOut),
.DOPA(),
.DOB(),
.DOPB(),
.ADDRA({1'b0,RowBufOut[7:0],5'b00000}),
.CLKA(PixelClk2),
.ENA(1'b1),
.REGCEA(1'b0),
.RSTA(1'b0),
.WEA(4'h0),
.DIA(32'h00000000),
.DIPA(4'h0),
.ADDRB({1'b0,PalAddr,5'b00000}),
.CLKB(PixelClk2),
.ENB(1'b1),
.REGCEB(1'b0),
.RSTB(1'b0),
.WEB({PalWrite,PalWrite,PalWrite,PalWrite}),
.DIB(PalData),
.DIPB(4'b0));
endmodule
|
#include <bits/stdc++.h> int main() { int n; std::cin >> n; int t, c; int max = 0, cur = 0, lt = -1; for (int i = 0; i < n; i++) { std::cin >> t >> c; if (lt != -1) { cur += lt - t; } if (cur < 0) cur = 0; cur += c; if (cur > max) max = cur; lt = t; } if (cur < c) cur = c; std::cout << lt + cur << << max; return 0; } |
module qsys (
clk_clk,
reset_reset_n,
sdram_clock_areset_conduit_export,
sdram_clock_c0_clk,
sdram_read_control_fixed_location,
sdram_read_control_read_base,
sdram_read_control_read_length,
sdram_read_control_go,
sdram_read_control_done,
sdram_read_control_early_done,
sdram_read_user_read_buffer,
sdram_read_user_buffer_output_data,
sdram_read_user_data_available,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n,
sdram_write_control_fixed_location,
sdram_write_control_write_base,
sdram_write_control_write_length,
sdram_write_control_go,
sdram_write_control_done,
sdram_write_user_write_buffer,
sdram_write_user_buffer_input_data,
sdram_write_user_buffer_full);
input clk_clk;
input reset_reset_n;
input sdram_clock_areset_conduit_export;
output sdram_clock_c0_clk;
input sdram_read_control_fixed_location;
input [31:0] sdram_read_control_read_base;
input [31:0] sdram_read_control_read_length;
input sdram_read_control_go;
output sdram_read_control_done;
output sdram_read_control_early_done;
input sdram_read_user_read_buffer;
output [63:0] sdram_read_user_buffer_output_data;
output sdram_read_user_data_available;
output [12:0] sdram_wire_addr;
output [1:0] sdram_wire_ba;
output sdram_wire_cas_n;
output sdram_wire_cke;
output sdram_wire_cs_n;
inout [15:0] sdram_wire_dq;
output [1:0] sdram_wire_dqm;
output sdram_wire_ras_n;
output sdram_wire_we_n;
input sdram_write_control_fixed_location;
input [31:0] sdram_write_control_write_base;
input [31:0] sdram_write_control_write_length;
input sdram_write_control_go;
output sdram_write_control_done;
input sdram_write_user_write_buffer;
input [15:0] sdram_write_user_buffer_input_data;
output sdram_write_user_buffer_full;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int main() { scanf( %d , &n); if (n == 1) { puts( white ); cout << 1 << << 2 << endl; return 0; } if (n & 1) { puts( black ); return 0; } puts( white ); cout << 1 << << 2 << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__MAJ3_FUNCTIONAL_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__maj3 (
VPWR,
VGND,
X ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
// Local signals
wire csi_opt_296, and0_out ;
wire csi_opt_296, and1_out ;
wire or0_out ;
wire or1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_PP_V |
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 30-10-2018
*/
module jt12_eg_comb(
input keyon_now,
input keyoff_now,
input [2:0] state_in,
input [9:0] eg_in,
// envelope configuration
input [4:0] arate, // attack rate
input [4:0] rate1, // decay rate
input [4:0] rate2, // sustain rate
input [3:0] rrate,
input [3:0] sl, // sustain level
// SSG operation
input ssg_en,
input [2:0] ssg_eg,
// SSG output inversion
input ssg_inv_in,
output ssg_inv_out,
output [4:0] base_rate,
output [2:0] state_next,
output pg_rst,
///////////////////////////////////
// II
input step_attack,
input [ 4:0] step_rate_in,
input [ 4:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input [ 1:0] ks,
output cnt_lsb,
output step,
output [5:0] step_rate_out,
output sum_up_out,
///////////////////////////////////
// III
input pure_attack,
input pure_step,
input [ 5:1] pure_rate,
input pure_ssg_en,
input [ 9:0] pure_eg_in,
output [9:0] pure_eg_out,
input sum_up_in,
///////////////////////////////////
// IV
input [ 6:0] lfo_mod,
input amsen,
input [ 1:0] ams,
input [ 6:0] tl,
input [ 9:0] final_eg_in,
input final_ssg_inv,
output [9:0] final_eg_out
);
// I
jt12_eg_ctrl u_ctrl(
.keyon_now ( keyon_now ),
.keyoff_now ( keyoff_now ),
.state_in ( state_in ),
.eg ( eg_in ),
// envelope configuration
.arate ( arate ), // attack rate
.rate1 ( rate1 ), // decay rate
.rate2 ( rate2 ), // sustain rate
.rrate ( rrate ),
.sl ( sl ), // sustain level
// SSG operation
.ssg_en ( ssg_en ),
.ssg_eg ( ssg_eg ),
// SSG output inversion
.ssg_inv_in ( ssg_inv_in ),
.ssg_inv_out ( ssg_inv_out ),
.base_rate ( base_rate ),
.state_next ( state_next ),
.pg_rst ( pg_rst )
);
// II
jt12_eg_step u_step(
.attack ( step_attack ),
.base_rate ( step_rate_in ),
.keycode ( keycode ),
.eg_cnt ( eg_cnt ),
.cnt_in ( cnt_in ),
.ks ( ks ),
.cnt_lsb ( cnt_lsb ),
.step ( step ),
.rate ( step_rate_out ),
.sum_up ( sum_up_out )
);
// III
wire [9:0] egin, egout;
jt12_eg_pure u_pure(
.attack ( pure_attack ),
.step ( pure_step ),
.rate ( pure_rate ),
.ssg_en ( pure_ssg_en ),
.eg_in ( pure_eg_in ),
.eg_pure( pure_eg_out ),
.sum_up ( sum_up_in )
);
// IV
jt12_eg_final u_final(
.lfo_mod ( lfo_mod ),
.amsen ( amsen ),
.ams ( ams ),
.tl ( tl ),
.ssg_inv ( final_ssg_inv ),
.eg_pure_in ( final_eg_in ),
.eg_limited ( final_eg_out )
);
endmodule // jt12_eg_comb |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file digit.v when simulating
// the core, digit. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module digit(
clka,
addra,
douta
);
input clka;
input [13 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("digit.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(10240),
.C_READ_DEPTH_B(10240),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(10240),
.C_WRITE_DEPTH_B(10240),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_4_V
`define SKY130_FD_SC_HS__MUX2_4_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2_4 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFRTP_BEHAVIORAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) f = ch == - ? -1 : f, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * f; } const int N = 200050; int sta[3][N], f[3][N], F[3]; int n, m, s, e; int pos[N]; void dp() { for (int t = 0; t < 3; t++) for (int i = sta[t][0] - 1; i >= 1; i--) f[t][i] = f[t][i + 1] + max(sta[t][i + 1] - sta[t][i] - s, 0); } int binary_search(int t, int x) { int ret, l = 1, r = sta[t][0], mid; while (l <= r) { mid = l + r >> 1; if (sta[t][mid] >= x) ret = mid, r = mid - 1; else l = mid + 1; } return ret; } int main() { pos[0] = e = read(), s = read(), n = read(), m = read(); for (int i = 0; i < 3; i++) sta[i][++sta[i][0]] = pos[0]; for (int i = 1, tp; i <= n; i++) { tp = read(), pos[i] = read(); if (pos[i] >= e) continue; switch (tp) { case 3: sta[2][++sta[2][0]] = pos[i]; case 2: sta[1][++sta[1][0]] = pos[i]; case 1: sta[0][++sta[0][0]] = pos[i]; } } sort(sta[0] + 1, sta[0] + sta[0][0] + 1), sort(sta[1] + 1, sta[1] + sta[1][0] + 1), sort(sta[2] + 1, sta[2] + sta[2][0] + 1); dp(); for (int i = 1, x; i <= m; i++) { x = read(); for (int t = 0; t < 3; t++) { int y = binary_search(t, x); F[t] = f[t][y] + max(sta[t][y] - x - s, 0); } if (F[0] > 0) printf( -1 -1 n ); else printf( %d %d n , F[1], F[2] - F[1]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFBBN_PP_SYMBOL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; long double PI = 4 * atan(1); pair<int, int> p[3]; set<pair<int, int> > second; bool cmp(pair<int, int> p1, pair<int, int> p2) { return p1.second > p2.second; } int main() { ios::sync_with_stdio(0), cin.tie(0); for (int i = 0; i < 3; i++) { cin >> p[i].first >> p[i].second; second.insert(p[i]); } sort(p, p + 3, cmp); while (p[2].second != p[1].second) { p[2].second++; second.insert(p[2]); } sort(p, p + 3, cmp); while (p[0].first != p[2].first) { if (p[0].first > p[2].first) p[2].first++; else p[2].first--; second.insert(p[2]); } while (p[0].first != p[1].first) { if (p[0].first > p[1].first) p[1].first++; else p[1].first--; second.insert(p[1]); } p[1] = p[2]; while (p[2].second != p[0].second) { p[2].second++; second.insert(p[2]); } cout << second.size() << n ; for (pair<int, int> p1 : second) { cout << p1.first << << p1.second << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_1_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_1_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv5sd3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd3_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkdlyinv5sd3 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd3_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkdlyinv5sd3 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_1_V
|
// Check behaviour with out-of-range and undefined array indices
// on LHS of procedural continuous (reg) assignment.
module top;
reg [1:0] array1[2:1];
reg [1:0] array2[1:0];
reg [1:0] var1;
`ifndef VLOG95
real array3[2:1];
real array4[1:0];
real var2;
`endif
reg failed;
initial begin
failed = 0;
array1[1] = 2'd0;
array1[2] = 2'd0;
array2[0] = 2'd0;
array2[1] = 2'd0;
assign array1[0] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[0];
assign array1[1] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd1) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[1];
assign array1[2] = var1;
var1 = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd1)) failed = 1;
var1 = 2'd2;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd2)) failed = 1;
deassign array1[2];
assign array1[3] = var1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[3];
assign array2['bx] = 2'd1;
#1 $display("array = %h %h", array2[1], array2[0]);
if ((array2[0] !== 2'd0) || (array2[1] !== 2'd0)) failed = 1;
deassign array2['bx];
`ifndef VLOG95
array3[1] = 0.0;
array3[2] = 0.0;
array4[0] = 0.0;
array4[1] = 0.0;
assign array3[0] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[0];
assign array3[1] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[1];
assign array3[2] = var2;
var2 = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1;
var2 = 2.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1;
deassign array3[2];
assign array3[3] = var2;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[3];
assign array4['bx] = 1.0;
#1 $display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
deassign array4['bx];
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n, d; cin >> n >> d; long long k = 0, c = 0, a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; c = 0; for (long long i = 1; i < n; i++) { if (a[i - 1] < a[i]) continue; k = a[i - 1] - a[i] + d; c += k / d; a[i] += (k / d) * d; } cout << c; } |
#include <bits/stdc++.h> using namespace std; long long t, n; char str[200005]; void solve() { long long i, b = 0, c, s = 1, min = 0; char a; a = str[0]; str[n] = str[0]; for (i = 1; i < n; ++i) { if (str[i] != a) { b = i; break; } else { s++; } } if (b) { for (i = n - 1; i >= b; --i) { if (str[i] != a) { c = i; break; } else { s++; } } } if (b) { min += s / 3; a = str[b]; s = 1; for (i = b + 1; i <= c; ++i) { if (str[i] == a) { s++; } else { a = str[i]; min += s / 3; s = 1; } } min += s / 3; cout << min << n ; } else { min += (s + 2) / 3; cout << min << n ; } } void nhap() { long long i; cin >> n; cin >> str; } int main() { long long i; cin >> t; for (i = 1; i <= t; ++i) { nhap(); solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } void solve() { int m, d, w; long long int ans = 0, lim, g, x, y; scanf( %d%d%d , &m, &d, &w); lim = min(m, d); if (d == 1) ans = lim * lim; else { g = gcd(d - 1, w); w /= g; x = lim / w; y = lim % w; ans = y * (x + 1) * (x + 1) + (w - y) * x * x; } ans -= lim; ans >>= 1; printf( %lld n , ans); return; } int main() { int t; scanf( %d , &t); while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int T; cin >> T; for (int t = 1; t <= T; ++t) { int64_t n; cin >> n; if (n == 1) { cout << 0 << n ; continue; } int count = 0; int first = 1; int64_t res = INT_MAX; for (int i = 1; i <= 63500; ++i) { first += 1; count += 1; int64_t sum = first; res = min(res, (((n - sum) + (first - 1)) / first) + count); } cout << res << n ; } } |
/*
* land2 - a verilog test for logical and operator && in boolean context
*
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ()
* Modified by SDW to self test.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module land2;
reg Clk;
reg a;
reg b;
reg c;
reg error;
wire q;
wire q_calc;
tand tand_m(q, q_calc, a, b, c);
initial Clk = 0;
always #10 Clk = ~Clk;
always @(posedge Clk)
begin
#1;
if(q != q_calc)
begin
$display("FAILED - expr && using %b%b%b is %b s/b %b",
a, b, c, q,q_calc);
error = 1;
end
end
reg [3:0] bvec;
integer xa;
integer xb;
integer xc;
initial begin
bvec = 4'bzx10 ;
error = 0;
for(xa = 0; xa <= 3; xa = xa + 1)
for(xb = 0; xb <= 3; xb = xb + 1)
for(xc = 0; xc <= 3; xc = xc + 1)
begin
@(posedge Clk)
a = bvec[xa];
b = bvec[xb];
c = bvec[xc];
end // for (var3 = 0; var3 <= 3; var3 = var3 + 1)
if(error == 0 ) $display("PASSED");
$finish;
end
endmodule
module tand(q, q_calc, a, b, c);
output q;
output q_calc;
input a;
input b;
input c;
wire q = ( (a===b) && (b===c) );
reg q_calc;
always @(a or b or c)
begin
if(a === b)
begin
if( b === c)
q_calc = 1'b1;
else
q_calc = 1'b0;
end
else
q_calc = 1'b0;
end
endmodule // foo
|
`include "../src/include/abs.v"
`include "../src/include/single_step_motor.v"
`include "../src/include/block_ram.v"
`include "../src/step_motor.v"
module test_step_motor();
parameter integer C_STEP_NUMBER_WIDTH = 16;
parameter integer C_SPEED_DATA_WIDTH = 16;
parameter integer C_SPEED_ADDRESS_WIDTH = 4;
parameter integer C_MICROSTEP_WIDTH = 3;
parameter integer C_CLK_DIV_NBR = 16;
parameter integer C_MOTOR_NBR = 2;
parameter integer C_ZPD_SEQ = 8'b01;
localparam integer C_MS = 2;
reg clk;
reg resetn;
reg br_init;
reg br_wr_en;
reg [C_SPEED_DATA_WIDTH-1:0] br_data;
reg m0_zpd;
wire m0_drive;
wire m0_dir;
wire [C_MICROSTEP_WIDTH-1:0] m0_ms;
wire m0_xen;
wire m0_xrst;
wire s0_ntsign;
wire s0_zpsign;
wire s0_ptsign;
wire s0_state;
reg [C_STEP_NUMBER_WIDTH-1:0] s0_min_pos = 0;
reg [C_STEP_NUMBER_WIDTH-1:0] s0_max_pos = 100;
wire [C_SPEED_DATA_WIDTH-1:0] s0_rt_speed;
wire [C_STEP_NUMBER_WIDTH-1:0] s0_position;
reg [C_SPEED_DATA_WIDTH-1:0] s0_speed;
reg [C_STEP_NUMBER_WIDTH-1:0] s0_step;
reg s0_start;
reg s0_stop;
reg s0_abs;
reg [C_MICROSTEP_WIDTH-1:0] s0_ms = 0;
reg s0_xen = 0;
reg s0_xrst = 0;
reg m1_zpd = 0;
wire m1_drive;
wire m1_dir;
wire [C_MICROSTEP_WIDTH-1:0] m1_ms;
wire m1_xen;
wire m1_xrst;
wire s1_ntsign;
wire s1_zpsign;
wire s1_ptsign;
wire s1_state;
reg [C_STEP_NUMBER_WIDTH-1:0] s1_min_pos = 0;
reg [C_STEP_NUMBER_WIDTH-1:0] s1_max_pos = 100;
wire [C_SPEED_DATA_WIDTH-1:0] s1_rt_speed;
reg [C_SPEED_DATA_WIDTH-1:0] s1_speed;
reg [C_STEP_NUMBER_WIDTH-1:0] s1_step;
reg s1_start;
reg s1_stop;
reg s1_abs;
reg [C_MICROSTEP_WIDTH-1:0] s1_ms = 0;
reg s1_xen = 0;
reg s1_xrst = 0;
step_motor # (
.C_STEP_NUMBER_WIDTH (C_STEP_NUMBER_WIDTH ),
.C_SPEED_DATA_WIDTH (C_SPEED_DATA_WIDTH ),
.C_SPEED_ADDRESS_WIDTH(C_SPEED_ADDRESS_WIDTH),
.C_MICROSTEP_WIDTH (C_MICROSTEP_WIDTH ),
.C_CLK_DIV_NBR (C_CLK_DIV_NBR ),
.C_MOTOR_NBR (C_MOTOR_NBR ),
.C_ZPD_SEQ (C_ZPD_SEQ )
) motor_inst (
.clk(clk),
.resetn(resetn),
.br_init (br_init),
.br_wr_en(br_wr_en),
.br_data (br_data),
.m0_zpd (m0_zpd ),
.m0_drive (m0_drive ),
.m0_dir (m0_dir ),
.m0_ms (m0_ms ),
.m0_xen (m0_xen ),
.m0_xrst (m0_xrst ),
.s0_ntsign(s0_ntsign),
.s0_zpsign(s0_zpsign),
.s0_ptsign(s0_ptsign),
.s0_min_pos(s0_min_pos),
.s0_max_pos(s0_max_pos),
.s0_speed (s0_speed ),
.s0_rt_speed(s0_rt_speed),
.s0_position(s0_position),
.s0_step (s0_step ),
.s0_start (s0_start ),
.s0_stop (s0_stop ),
.s0_abs (s0_abs ),
.s0_ms (s0_ms ),
.s0_state (s0_state ),
.s0_xen (s0_xen ),
.s0_xrst (s0_xrst ),
.s0_ext_sel(1'b0),
.m1_zpd (m1_zpd ),
.m1_drive (m1_drive ),
.m1_dir (m1_dir ),
.m1_ms (m1_ms ),
.m1_xen (m1_xen ),
.m1_xrst (m1_xrst ),
.s1_ntsign(s1_ntsign),
.s1_zpsign(s1_zpsign),
.s1_ptsign(s1_ptsign),
.s1_min_pos(s1_min_pos),
.s1_max_pos(s1_max_pos),
.s1_speed (s1_speed ),
.s1_rt_speed(s1_rt_speed),
.s1_step (s1_step ),
.s1_start (s1_start ),
.s1_stop (s1_stop ),
.s1_abs (s1_abs ),
.s1_ms (s1_ms ),
.s1_state (s1_state ),
.s1_xen (s1_xen ),
.s1_xrst (s1_xrst ),
.s1_ext_sel(1'b0)
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
br_wr_en <= 0;
br_data <= 30;
end
else if (br_init && ({$random}%2)) begin
br_wr_en <= 1;
br_data <= br_data - 2;
end
else begin
br_wr_en <= 0;
end
end
reg ctl_clk;
initial begin
ctl_clk <= 1'b1;
forever #3 ctl_clk <= ~ctl_clk;
end
initial begin
br_init <= 1'b1;
repeat (5) #3 br_init <= 1'b1;
repeat (10) #3 br_init <= 1'b1;
forever #2 br_init <= 1'b0;
end
always @ (posedge ctl_clk) begin
if (resetn == 1'b0) begin
s0_start <= 0;
end
else if (s0_state == 1'b0 && ~s0_start && ({$random}%1000 == 0) && ~br_init) begin
s0_speed <= 15;
s0_step <= 30;
s0_abs <= 0;
s0_start <= 1;
s0_ms <= C_MS;
end
else begin
s0_start <= 0;
end
end
reg [31:0] clk_cnt = 0;
always @ (posedge ctl_clk) begin
if (resetn == 1'b0)
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
end
always @ (posedge ctl_clk) begin
if (resetn == 1'b0)
m0_zpd <= 0;
else if (clk_cnt == 1000)
m0_zpd <= 0;
end
reg [31:0] s1_cnt = 1000;
always @ (posedge ctl_clk) begin
if (~br_init && s1_cnt != 0)
s1_cnt <= s1_cnt - 1;
end
always @ (posedge ctl_clk) begin
if (resetn == 1'b0) begin
s1_start <= 0;
end
else if (s1_state == 1'b0 && ~s1_start && s1_cnt == 1) begin
s1_speed <= 2;
s1_step <= 30;
//s1_abs <= 0;
s1_start <= 1;
end
else begin
s1_start <= 0;
end
end
endmodule
|
//
// fixed for 9.1 jan 21 2010 cruben
//
//`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
wire sda_padoen_o;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int a1[2][6] = {{1, 3, 4, 5, 2, 6}, {3, 2, 6, 4, 1, 5}}; int i, j, k, n, m; int a[10], f[10]; char p[10]; string s; set<string> yao, laji; void sou(string a, int ty) { if (laji.count(a)) return; int i, j; if (ty) laji.insert(a); for (i = 0; i <= 1; i++) { string b; for (j = 0; j <= 5; j++) b += a[a1[i][j] - 1]; sou(b, 1); } } void dfs(int x, string a) { if (x > 6) { if (!laji.count(a)) { yao.insert(a); sou(a, 0); } return; } int i; for (i = 1; i <= 6; i++) if (!f[i]) { f[i] = 1; dfs(x + 1, a + p[i]); f[i] = 0; } } int main() { scanf( %s , p + 1); dfs(1, s); printf( %d n , yao.size()); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_BLACKBOX_V
`define SKY130_FD_SC_LP__A41O_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUFBUF_BEHAVIORAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Input Buffer with Offset Calibration
// /___/ /\ Filename : IBUFDSE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDSE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
parameter USE_IBUFDISABLE = "FALSE"
)(
output O,
input I,
input IB,
input IBUFDISABLE,
input [3:0] OSC,
input [1:0] OSC_EN
);
// define constants
localparam MODULE_NAME = "IBUFDSE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 0;
localparam DIFF_TERM_TRUE = 1;
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam USE_IBUFDISABLE_FALSE = 0;
localparam USE_IBUFDISABLE_TRUE = 1;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
wire DIFF_TERM_BIN;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire USE_IBUFDISABLE_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg O_out;
reg O_OSC_in;
wire O_delay;
wire IBUFDISABLE_in;
wire IB_in;
wire I_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire IBUFDISABLE_delay;
wire IB_delay;
wire I_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE;
assign #(in_delay) IB_delay = IB;
assign #(in_delay) I_delay = I;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign IBUFDISABLE_in = IBUFDISABLE_delay;
assign IB_in = IB_delay;
assign I_in = I_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
integer OSC_int = 0;
assign O_delay = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= 1'bx;
end
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_FALSE;
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign USE_IBUFDISABLE_BIN =
(USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE :
(USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE :
USE_IBUFDISABLE_FALSE;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-105] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-103] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_IBUFDISABLE_REG != "FALSE") &&
(USE_IBUFDISABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(I_in or IB_in or DQS_BIAS_BIN or IBUFDISABLE_in or USE_IBUFDISABLE_BIN) begin
if (USE_IBUFDISABLE_BIN == 1'b1 && IBUFDISABLE_in == 1'b1)
O_out <= 1'b0;
else if ((USE_IBUFDISABLE_BIN == 1'b1 && IBUFDISABLE_in == 1'b0) || (USE_IBUFDISABLE_BIN == 1'b0)) begin
if (I_in == 1'b1 && IB_in == 1'b0)
O_out <= 1'b1;
else if (I_in == 1'b0 && IB_in == 1'b1)
O_out <= 1'b0;
else if ((I_in === 1'bz || I_in == 1'b0) && (IB_in === 1'bz || IB_in == 1'b1))
if (DQS_BIAS_BIN == 1'b1)
O_out <= 1'b0;
else
O_out <= 1'bx;
else if ((I_in === 1'bx) || (IB_in === 1'bx))
O_out <= 1'bx;
end
else begin
O_out <= 1'bx;
end
end
endmodule
`endcelldefine
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: pipeline.v
// Version: 1.00
// Verilog Standard: Verilog-2001
// Description: Standard 0-delay pipeline implementation. Takes WR_DATA on
// WR_READY and WR_VALID. RD_DATA is read on RD_READY and
// RD_VALID. C_DEPTH specifies the latency between RD and WR ports
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module pipeline
#(
parameter C_DEPTH = 10,
parameter C_WIDTH = 10,
parameter C_USE_MEMORY = 1
)
(
input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
input WR_DATA_VALID,
output WR_DATA_READY,
output [C_WIDTH-1:0] RD_DATA,
output RD_DATA_VALID,
input RD_DATA_READY
);
generate
if (C_USE_MEMORY & C_DEPTH > 2) begin
mem_pipeline
#(
.C_PIPELINE_INPUT (1),
.C_PIPELINE_OUTPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH (C_DEPTH),
.C_WIDTH (C_WIDTH))
pipeline_inst
(/*AUTOINST*/
// Outputs
.WR_DATA_READY (WR_DATA_READY),
.RD_DATA (RD_DATA[C_WIDTH-1:0]),
.RD_DATA_VALID (RD_DATA_VALID),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (WR_DATA[C_WIDTH-1:0]),
.WR_DATA_VALID (WR_DATA_VALID),
.RD_DATA_READY (RD_DATA_READY));
end else begin
reg_pipeline
#(/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH (C_DEPTH),
.C_WIDTH (C_WIDTH))
pipeline_inst
(/*AUTOINST*/
// Outputs
.WR_DATA_READY (WR_DATA_READY),
.RD_DATA (RD_DATA[C_WIDTH-1:0]),
.RD_DATA_VALID (RD_DATA_VALID),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (WR_DATA[C_WIDTH-1:0]),
.WR_DATA_VALID (WR_DATA_VALID),
.RD_DATA_READY (RD_DATA_READY));
end
endgenerate
endmodule // pipeline
module mem_pipeline
#(
parameter C_DEPTH = 10,
parameter C_WIDTH = 10,
parameter C_PIPELINE_INPUT = 0,
parameter C_PIPELINE_OUTPUT = 1
)
(
input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
input WR_DATA_VALID,
output WR_DATA_READY,
output [C_WIDTH-1:0] RD_DATA,
output RD_DATA_VALID,
input RD_DATA_READY
);
localparam C_INPUT_REGISTERS = C_PIPELINE_INPUT?1:0;
localparam C_OUTPUT_REGISTERS = C_PIPELINE_OUTPUT?1:0;
wire RST;
wire [C_WIDTH-1:0] wRdData;
wire wRdDataValid;
wire wRdDataReady;
wire [C_WIDTH-1:0] wWrData;
wire wWrDataValid;
wire wWrDataReady;
assign RST = RST_IN;
reg_pipeline
#(
// Parameters
.C_DEPTH (C_INPUT_REGISTERS),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
reg_in
(
// Outputs
.RD_DATA (wRdData),
.RD_DATA_VALID (wRdDataValid),
// Inputs
.RD_DATA_READY (wRdDataReady),
/*AUTOINST*/
// Outputs
.WR_DATA_READY (WR_DATA_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (WR_DATA[C_WIDTH-1:0]),
.WR_DATA_VALID (WR_DATA_VALID));
fifo
#(
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH - C_PIPELINE_INPUT - C_PIPELINE_OUTPUT),
.C_DELAY (C_DEPTH - C_PIPELINE_INPUT - C_PIPELINE_OUTPUT)
/*AUTOINSTPARAM*/)
fifo_inst
(
// Outputs
.RD_DATA (wWrData),
.WR_READY (wRdDataReady),
.RD_VALID (wWrDataValid),
// Inputs
.WR_DATA (wRdData),
.WR_VALID (wRdDataValid),
.RD_READY (wWrDataReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
reg_pipeline
#(
// Parameters
.C_DEPTH (C_OUTPUT_REGISTERS),
.C_WIDTH (C_WIDTH)
/*AUTOINSTPARAM*/)
reg_OUT
(
// Outputs
.WR_DATA_READY (wWrDataReady),
// Inputs
.WR_DATA (wWrData),
.WR_DATA_VALID (wWrDataValid),
/*AUTOINST*/
// Outputs
.RD_DATA (RD_DATA[C_WIDTH-1:0]),
.RD_DATA_VALID (RD_DATA_VALID),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.RD_DATA_READY (RD_DATA_READY));
endmodule // mem_pipeline
/* verilator lint_off UNOPTFLAT */
module reg_pipeline
#(
parameter C_DEPTH = 10,
parameter C_WIDTH = 10
)
(
input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
input WR_DATA_VALID,
output WR_DATA_READY,
output [C_WIDTH-1:0] RD_DATA,
output RD_DATA_VALID,
input RD_DATA_READY
);
genvar i;
wire wReady [C_DEPTH:0];
reg [C_WIDTH-1:0] _rData [C_DEPTH:1], rData [C_DEPTH:0];
reg _rValid [C_DEPTH:1], rValid [C_DEPTH:0];
// Read interface
assign wReady[C_DEPTH] = RD_DATA_READY;
assign RD_DATA = rData[C_DEPTH];
assign RD_DATA_VALID = rValid[C_DEPTH];
// Write interface
assign WR_DATA_READY = wReady[0];
always @(*) begin
rData[0] = WR_DATA;
rValid[0] = WR_DATA_VALID;
end
generate
for( i = 1 ; i <= C_DEPTH; i = i + 1 ) begin : gen_stages
assign #1 wReady[i-1] = ~rValid[i] | wReady[i];
// Data Registers
always @(*) begin
_rData[i] = rData[i-1];
end
// Enable the data register when the corresponding stage is ready
always @(posedge CLK) begin
if(wReady[i-1]) begin
rData[i] <= #1 _rData[i];
end
end
// Valid Registers
always @(*) begin
if(RST_IN) begin
_rValid[i] = 1'b0;
end else begin
_rValid[i] = rValid[i-1] | (rValid[i] & ~wReady[i]);
end
end
// Always enable the valid registers
always @(posedge CLK) begin
rValid[i] <= #1 _rValid[i];
end
end
endgenerate
endmodule
/* verilator lint_on UNOPTFLAT */
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(228); const int N = 404; int mod; int fact[N], d0[N], d[N], d2[N][N]; int main() { int qq; cin >> qq >> mod; fact[0] = 1; for (int i = 1; i < N; ++i) fact[i] = (1LL * fact[i - 1] * i) % mod; d[1] = 1; d0[1] = 1; for (int n = 2; n < N; ++n) { d0[n] = fact[n]; for (int k = 1; k < n; ++k) d0[n] = (d0[n] - 1LL * d0[k] * fact[n - k]) % mod; if (d0[n] < 0) d0[n] += mod; } d2[0][0] = 1; for (int n = 1; n < N; ++n) { d2[n][1] = fact[n]; for (int k = 2; k <= n; ++k) for (int x = 1; x < n; ++x) d2[n][k] = (d2[n][k] + 1LL * fact[x] * d2[n - x][k - 1]) % mod; } for (int n = 2; n < N; ++n) { int dz = 0; for (int x = 1; x < n - 1; ++x) for (int y = x; y < n - 1; ++y) { int c = fact[y - x + 1]; c = (1LL * c * d0[x]) % mod; c = (1LL * c * d0[n - y - 1]) % mod; dz += c; if (dz >= mod) dz -= mod; } dz = (dz * 2) % mod; int cd = fact[n]; cd = (cd - dz + mod) % mod; for (int k = 3; k < n; ++k) { cd = (cd - 1LL * d2[n][k] * d[k]) % mod; } if (n != 2) { for (int x = 1; x < n; ++x) cd = (cd - 1LL * d0[x] * d0[n - x]) % mod; for (int x = 1; x < n; ++x) cd = (cd - 1LL * d0[x] * d0[n - x]) % mod; } cd = (cd + mod) % mod; d[n] = cd; } while (qq--) { int x; cin >> x; cout << d[x] << n ; } } |
#include <bits/stdc++.h> using namespace std; struct compleks { double x, y; }; compleks operator*(compleks a, compleks b) { compleks c; c.x = a.x * b.x - a.y * b.y; c.y = a.x * b.y + a.y * b.x; return c; } compleks operator-(compleks a, compleks b) { compleks c; c.x = a.x - b.x, c.y = a.y - b.y; return c; } compleks operator+(compleks a, compleks b) { compleks c; c.x = a.x + b.x, c.y = a.y + b.y; return c; } int pos[65536 * 8]; void fft(compleks a[], int typ) { for (int i = 0; i < 65536 * 8; i++) if (pos[i] > i) swap(a[i], a[pos[i]]); for (int p = 1; p < 65536 * 8; p <<= 1) { int m = p + p; compleks wx; wx.x = cos(2 * 3.141592653589793 / m * typ), wx.y = sin(2 * 3.141592653589793 / m * typ); for (int i = 0; i < 65536 * 8; i += m) { compleks w; w.x = 1, w.y = 0; for (int j = 0; j < p; j++, w = w * wx) { compleks e = a[i + j], f = a[i + j + p] * w; a[i + j] = e + f, a[i + j + p] = e - f; } } } if (typ == -1) for (int i = 0; i < 65536 * 8; i++) a[i].x /= 65536 * 8, a[i].y /= 65536 * 8; } void getpos() { for (int i = 0; i < 65536 * 8; i++) pos[i] = (pos[i >> 1] >> 1) | ((i & 1) << 16 + 3 - 1); } int a[65536 * 8]; int n; int x; int pre[65536 * 8]; int cnt[65536 * 8]; compleks c[65536 * 8], d[65536 * 8]; int main() { cin >> n >> x; cnt[0]++; long long di = 0; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), pre[i] = pre[i - 1] + (a[i] < x), di += cnt[pre[i]], cnt[pre[i]]++; getpos(); for (int i = 0; i <= n; i++) c[i].x = cnt[i], d[-i + 65536 * 8 / 2].x = cnt[i]; fft(c, 1); fft(d, 1); for (int i = 0; i < 65536 * 8; i++) c[i] = c[i] * d[i]; fft(c, -1); for (int i = 0; i <= n; i++) { long long ai = (long long)(c[i + 65536 * 8 / 2].x + 0.5); if (i == 0) ai = di; printf( %lld , ai); } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_address_generator (
input clk,
input resetn,
input req_valid,
output reg req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] request_id,
input sync_id,
input eot,
input enable,
input pause,
output reg enabled,
input addr_ready,
output reg addr_valid,
output [31:0] addr,
output [ 7:0] len,
output [ 2:0] size,
output [ 1:0] burst,
output [ 2:0] prot,
output [ 3:0] cache
);
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8);
localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH);
`include "inc_id.h"
assign burst = 2'b01;
assign prot = 3'b000;
assign cache = 4'b0011;
assign len = length;
assign size = $clog2(C_DMA_DATA_WIDTH/8);
reg [7:0] length = 'h0;
reg [31-C_BYTES_PER_BEAT_WIDTH:0] address = 'h00;
reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
assign addr = {address, {C_BYTES_PER_BEAT_WIDTH{1'b0}}};
reg addr_valid_d1;
reg last = 1'b0;
// If we already asserted addr_valid we have to wait until it is accepted before
// we can disable the address generator.
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (~addr_valid)
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (addr_valid == 1'b0) begin
if (eot == 1'b1)
length <= last_burst_len;
else
length <= MAX_BEATS_PER_BURST - 1;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
last <= 1'b0;
end else if (addr_valid == 1'b0) begin
last <= eot;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
address <= 'h00;
last_burst_len <= 'h00;
req_ready <= 1'b1;
addr_valid <= 1'b0;
end else begin
if (~enabled) begin
req_ready <= 1'b1;
end else if (req_ready) begin
if (req_valid && enable) begin
address <= req_address;
req_ready <= 1'b0;
last_burst_len <= req_last_burst_length;
end
end else begin
if (addr_valid && addr_ready) begin
address <= address + MAX_BEATS_PER_BURST;
addr_valid <= 1'b0;
if (last)
req_ready <= 1'b1;
end else if (id != request_id && enable) begin
addr_valid <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <='h0;
addr_valid_d1 <= 1'b0;
end else begin
addr_valid_d1 <= addr_valid;
if ((addr_valid && ~addr_valid_d1) ||
(sync_id && id != request_id))
id <= inc_id(id);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, x, y, fail; int G[305][305], v[305], u[305], l[305], z[305]; long long int A, B, C, a[305], b[305], d[305]; int rx[305 * 305 * 2], ry[305 * 305 * 2], rc[305 * 305 * 2], cnt; void dfs(int x) { v[x] = 1; A += a[x]; B += b[x]; for (int i = (0); i < (n); i++) if (!v[i] && G[x][i]) G[x][i] = G[i][x] = 2, dfs(i); l[m++] = x; } void add(int x, int y, long long int c) { rx[cnt] = x + 1, ry[cnt] = y + 1, rc[cnt++] = (int)c; } void pull(int x, long long int d) { z[x] = 1; for (int i = (0); i < (n); i++) if (G[x][i] == 2 && !u[i] && d && !z[i]) { if (a[i] >= d) { a[i] -= d; a[x] += d; add(i, x, d); d = 0; } else { pull(i, d - a[i]); long long int t = min(d, a[i]); a[x] += t; a[i] -= t; d -= t; add(i, x, t); } } } void push(int x, long long int d) { z[x] = 1; for (int i = (0); i < (n); i++) if (G[x][i] == 2 && !u[i] && d && !z[i]) { if (C - a[i] >= d) { a[x] -= d; a[i] += d; add(x, i, d); d = 0; } else { push(i, d - (C - a[i])); long long int t = min(d, C - a[i]); a[i] += t; a[x] -= t; d -= t; add(x, i, t); } } } int main() { scanf( %d%I64d%d , &n, &C, &m); for (int i = (0); i < (n); i++) scanf( %I64d , &a[i]); for (int i = (0); i < (n); i++) scanf( %I64d , &b[i]); while (m--) { scanf( %d%d , &x, &y), x--, y--; G[x][y] = G[y][x] = 1; } for (int i = (0); i < (n); i++) if (!v[i]) { A = B = 0; m = 0; dfs(i); if (A != B) { fail = 1; break; } for (int j = (0); j < (m); j++) { int r = l[j]; memset(z, 0, sizeof(z)); if (a[r] > b[r]) push(r, a[r] - b[r]); if (a[r] < b[r]) pull(r, b[r] - a[r]); u[r] = 1; } } if (fail) puts( NO ); else { printf( %d n , cnt); for (int i = (0); i < (cnt); i++) printf( %d %d %d n , rx[i], ry[i], rc[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long expo(long long x, long long n, long long m) { if (n == 0) return 1; else if (n % 2 == 0) return expo((x * x) % m, n / 2, m); else return (x * expo((x * x) % m, (n - 1) / 2, m)) % m; } string DtoB(int j) { string s = ; for (int i = 32; i >= 0; i--) { int k = j >> i; if (k & 1) s += 1 ; else s += 0 ; } return s; } void solve() { int n; cin >> n; int arr[n]; int s[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; s[i] = arr[i]; } sort(s, s + n); map<int, int> m; for (int i = 0; i < n; i++) m[s[i]] = i; vector<vector<int> > ans; int visit[n]; memset(visit, 0, sizeof(visit)); ; for (int i = 0; i < n; i++) { if (visit[i] == 0) { vector<int> p; for (int j = i; visit[j] == 0; j = m[arr[j]]) { p.push_back(j + 1); visit[j] = 1; } ans.push_back(p); } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) { cout << ans[i].size() << ; for (int j = 0; j < ans[i].size(); j++) cout << ans[i][j] << ; cout << endl; } return; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7, NMAX = 160; int N, M; int DP[NMAX][2][2][NMAX][NMAX], SUM[NMAX][2][2][NMAX][NMAX]; void Mod(int &value) { value -= MOD; if (value < 0) value += MOD; } void ComputeSums(int i) { int j, k, left, right; for (j = 0; j < 2; ++j) for (k = 0; k < 2; ++k) for (left = 1; left <= M; ++left) for (right = 1; right <= M; ++right) { SUM[i][j][k][left][right] = DP[i][j][k][left][right] + SUM[i][j][k][left - 1][right]; Mod(SUM[i][j][k][left][right]); SUM[i][j][k][left][right] += SUM[i][j][k][left][right - 1]; Mod(SUM[i][j][k][left][right]); SUM[i][j][k][left][right] -= SUM[i][j][k][left - 1][right - 1] - MOD; Mod(SUM[i][j][k][left][right]); } } int GetSum(int i, int j, int k, int leftx, int lefty, int rightx, int righty) { int ret = SUM[i][j][k][lefty][righty] - SUM[i][j][k][lefty][rightx - 1] + MOD; Mod(ret); ret -= SUM[i][j][k][leftx - 1][righty] - MOD; Mod(ret); ret += SUM[i][j][k][leftx - 1][rightx - 1]; Mod(ret); return ret; } int main() { ios_base::sync_with_stdio(false); int i, res = 0, left, right; cin >> N >> M; for (i = 1; i <= N; ++i) { for (left = 1; left <= M; ++left) for (right = left; right <= M; ++right) { DP[i][0][0][left][right] = 1; DP[i][0][0][left][right] += GetSum(i - 1, 0, 0, left, right, left, right); Mod(DP[i][0][0][left][right]); res += DP[i][0][0][left][right]; Mod(res); } for (left = 1; left <= M; ++left) for (right = left; right <= M; ++right) { DP[i][0][1][left][right] += GetSum(i - 1, 0, 1, left, right, right, M); Mod(DP[i][0][1][left][right]); DP[i][0][1][left][right] += GetSum(i - 1, 0, 0, left, right, right + 1, M); Mod(DP[i][0][1][left][right]); res += DP[i][0][1][left][right]; Mod(res); } for (left = 1; left <= M; ++left) for (right = left; right <= M; ++right) { DP[i][1][0][left][right] += GetSum(i - 1, 1, 0, 1, left, left, right); Mod(DP[i][1][0][left][right]); DP[i][1][0][left][right] += GetSum(i - 1, 0, 0, 1, left - 1, left, right); Mod(DP[i][1][0][left][right]); res += DP[i][1][0][left][right]; Mod(res); } for (left = 1; left <= M; ++left) for (right = left; right <= M; ++right) { DP[i][1][1][left][right] += GetSum(i - 1, 0, 0, 1, left - 1, right + 1, M); Mod(DP[i][1][1][left][right]); DP[i][1][1][left][right] += GetSum(i - 1, 0, 1, 1, left - 1, right, M); Mod(DP[i][1][1][left][right]); DP[i][1][1][left][right] += GetSum(i - 1, 1, 0, 1, left, right + 1, M); Mod(DP[i][1][1][left][right]); DP[i][1][1][left][right] += GetSum(i - 1, 1, 1, 1, left, right, M); Mod(DP[i][1][1][left][right]); res += DP[i][1][1][left][right]; Mod(res); } ComputeSums(i); } cout << res << n ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optmize( Ofast ) using namespace std; const int maxn = 20009; const int inf = 1e8; int n, m, K, T; int e[1 << 10][maxn << 1]; int head[maxn], cntedge = 1; int from[maxn], to[maxn], cap[maxn], flow[maxn], nex[maxn]; void Addedge(int x, int y, int z) { nex[++cntedge] = head[x]; from[cntedge] = x; to[cntedge] = y; cap[cntedge] = z; flow[cntedge] = 0; head[x] = cntedge; } int cur[maxn]; int d[maxn]; int vis[maxn]; int q[maxn], r; int Bfs() { for (int i = 1; i <= n; ++i) vis[i] = 0; vis[1] = 1; d[1] = 0; q[r = 1] = 1; for (int l = 1; l <= r; ++l) { int x = q[l]; for (int i = head[x]; i; i = nex[i]) { int v = to[i]; if ((cap[i] > flow[i]) && (!vis[v])) { vis[v] = 1; d[v] = d[x] + 1; q[++r] = v; } } } return vis[n]; } int Dfs(int x, int a) { if ((x == n) || (a == 0)) return a; int nowflow = 0, f = 0; for (int i = cur[x]; i; i = nex[i]) { cur[x] = i; int v = to[i]; if (d[x] + 1 == d[v]) { f = Dfs(v, min(a, cap[i] - flow[i])); nowflow += f; a -= f; flow[i] += f; flow[i ^ 1] -= f; if (a == 0) break; } } return nowflow; } int p[maxn], pf[maxn] = {0, 1000000}; int augment() { for (int i = 1; i <= n; ++i) vis[i] = 0; q[r = 1] = 1; int flag = 0; for (int l = 1; l <= r; ++l) { int x = q[l]; for (int i = head[x]; i; i = nex[i]) { int v = to[i]; if ((cap[i] > flow[i]) && (!vis[v])) { vis[v] = 1; p[v] = i; q[++r] = v; pf[v] = min(pf[x], cap[i] - flow[i]); if (v == n) { flag = 1; break; } } } if (flag) break; } if (!vis[n]) return 0; int f = pf[n], x = n; while (x != 1) { flow[p[x]] += f; flow[p[x] ^ 1] -= f; x = from[p[x]]; } return f; } int Maxflow() { int flow = 0; while (Bfs()) { for (int i = 1; i <= n; ++i) cur[i] = head[i]; flow += Dfs(1, inf); } return flow; } int f[1024]; int sum[1 << 10]; int lg2[1 << 11]; int w[maxn]; int read() { int r = 0, k = 1; char c = getchar(); for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) k = -1; for (; c >= 0 && c <= 9 ; c = getchar()) r = r * 10 + c - 0 ; return r * k; } int main() { scanf( %d%d%d%d , &n, &m, &K, &T); for (int i = 1; i <= m; ++i) { int x, y, z; scanf( %d%d%d , &x, &y, &z); Addedge(x, y, z); Addedge(y, x, 0); } f[0] = Maxflow(); for (int i = 2; i <= cntedge; ++i) e[0][i] = flow[i]; for (int s = 1; s < (1 << K); ++s) { for (int i = 1; i <= K; ++i) { if (s & (1 << (i - 1))) { cap[i << 1] = 25; } else { cap[i << 1] = 0; } } int pre = s ^ (s & (-s)); for (int i = 2; i <= cntedge; ++i) flow[i] = e[pre][i]; f[s] = f[pre]; int tmp; while (tmp = augment()) f[s] += tmp; for (int i = 2; i <= cntedge; ++i) e[s][i] = flow[i]; } for (int s = 0; s < (1 << K); ++s) { int t = (~s) & ((1 << K) - 1); if (t < s) swap(f[s], f[t]); } for (int i = 1; i <= 10; ++i) lg2[1 << i] = i; while (T--) { for (int i = 1; i <= K; ++i) w[i] = read(); int ans = f[0]; for (int s = 1; s < (1 << K); ++s) { int l = s & (-s); sum[s] = sum[s ^ l] + w[lg2[l] + 1]; ans = min(ans, sum[s] + f[s]); } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> const int N = 100001; using namespace std; long long a[N], sum[N]; int main() { int n; while (scanf( %d , &n) == 1) { for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); for (int i = 1, j; i < n; i++) { for (j = 0; (1 << j) + i <= n; j++) ; j--; a[i + (1 << j)] += a[i]; } long long ans = 0; for (int i = 1; i < n; i++) { ans += a[i]; printf( %I64d n , ans); } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long cross(pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c) { pair<long long, long long> v1 = make_pair(b.first - a.first, b.second - a.second); pair<long long, long long> v2 = make_pair(c.first - a.first, c.second - a.second); if ((long long)v1.first * (long long)v2.second - (long long)v2.first * (long long)v1.second > 0) return 1; else if ((long long)v1.first * (long long)v2.second - (long long)v2.first * (long long)v1.second < 0) return -1; return 0; } int main(int argc, char* argv[]) { long long n; cin >> n; vector<long long> arr(n); for (long long i = 0; i < n; i++) { cin >> arr[i]; } vector<pair<long long, long long> > p; p.push_back(make_pair(-1, 0)); long long s = 0; for (long long i = 0; i < n; i++) { s += arr[i]; p.push_back(make_pair(i, s)); } stack<pair<long long, long long> > ch; ch.push(p[0]); ch.push(p[1]); for (long long i = 2; i < n + 1; i++) { pair<long long, long long> top = ch.top(); ch.pop(); while (ch.size() > 0 && cross(ch.top(), top, p[i]) == -1) { top = ch.top(); ch.pop(); } ch.push(top); ch.push(p[i]); } vector<pair<long long, long long> > vec; while (ch.size()) { vec.push_back(ch.top()); ch.pop(); } reverse(vec.begin(), vec.end()); vector<double> cev; long long cur = 0; for (long long i = -1; i < n; i++) { if (vec[cur].first == i) cev.push_back(vec[cur].second); else { if (cur < vec.size() - 1 && vec[cur + 1].first <= i) { cur++; i--; continue; } long long x1 = vec[cur + 1].first - vec[cur].first; long long y1 = vec[cur + 1].second - vec[cur].second; long long x2 = i - vec[cur].first; cev.push_back((((double)x2 * (double)y1) / (double)x1) + vec[cur].second); } } for (long long i = 0; i < cev.size() - 1; i++) { cout << setprecision(13) << double(cev[i + 1] - cev[i]) << ; } cout << endl; } |
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 100005; int a[maxn], lefts[maxn], rights[maxn]; int main() { int n, l, r, q1, q2; cin >> n >> l >> r >> q1 >> q2; memset(lefts, 0, sizeof(lefts)); memset(rights, 0, sizeof(rights)); for (int i = 0; i < n; i++) { cin >> a[i]; lefts[i + 1] += (lefts[i] + a[i]); } for (int i = n - 1; i >= 0; i--) { rights[n - i] += (rights[n - i - 1] + a[i]); } int sum = 0, ans = INF; for (int i = 0; i <= n; i++) { sum = 0; sum += ((lefts[i] * l) + rights[n - i] * r); if (i > (n - i)) sum += ((2 * i - n - 1) * q1); else if (i < (n - i)) sum += ((n - 2 * i - 1) * q2); ans = min(ans, sum); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int MaxN = 3e5 + 5; map<int, int> mp; struct node { int x, y; } arr[MaxN], brr[MaxN]; struct qnode { int x, y; bool operator>(const qnode &p) const { return p.y > y; } } st; bool cmp(node b, node c) { if (b.x == c.x) return b.y < c.y; return b.x < c.x; } int main() { int n, m, u, v, pp; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &pp), mp[pp] = i; int x = -1, y = inf; for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); arr[i].x = min(mp[u], mp[v]); arr[i].y = max(mp[u], mp[v]); } sort(arr, arr + m, cmp); priority_queue<qnode, vector<qnode>, greater<qnode> > pq; for (int i = 0; i < m; i++) { if (pq.empty()) { st.x = arr[i].x, st.y = arr[i].y; pq.push(st); continue; } while (!pq.empty() && arr[i].y <= pq.top().y) { pq.pop(); } st.x = arr[i].x, st.y = arr[i].y; pq.push(st); } int num = 0; while (!pq.empty()) { st = pq.top(); pq.pop(); brr[num].x = st.x, brr[num].y = st.y, num++; } long long p = (long long)(brr[num - 1].x) * (n - brr[num - 1].y + 1); for (int i = num - 1; i >= 1; i--) p += (long long)(brr[i - 1].x - brr[i].x) * (n - brr[i - 1].y + 1); long long ans = (long long)n + (long long)n * (n - 1) / 2; printf( %I64d n , ans - p); } |
#include <bits/stdc++.h> using namespace std; const int MAXP = 18; const int MAXN = 1000001; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int n, p; string cad; int freq[MAXP]; int val[1 << MAXP]; int vis[1 << MAXP]; vector<pair<int, int> > lista[1 << MAXP]; bool mat[MAXP][MAXP]; bool invalid[1 << MAXP]; bool marked[MAXP][MAXP][1 << MAXP]; int mapea(int i) { return cad[i] - a ; } int dfs(int u) { if (vis[u]) return val[u]; vis[u] = 1; int ans = 0; for (int j = 0; j < p; j++) { if (u & 1 << j) continue; int v = u | 1 << j; if (!invalid[v]) ans = max(ans, dfs(v) + freq[j]); } return val[u] = ans; } void compute(int a, int b) { int id = 0, last = -1, mask; while (id < n) { if (mapea(id) == b && last != -1 && mask) { lista[mask].push_back(pair<int, int>(a, b)); mask = 0; last = -1; } if (mapea(id) == a) { last = id; mask = 0; } if (mapea(id) != a && mapea(id) != b) mask |= 1 << mapea(id); id++; } } void bfs(int mask, int a, int b) { queue<int> q; q.push(mask); invalid[mask] = 1; marked[a][b][mask] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < p; i++) { if (i == a || i == b) continue; int v = u | 1 << i; if (!marked[a][b][v]) { invalid[v] = 1; marked[a][b][v] = 1; q.push(v); } } } invalid[(1 << p) - 1] = 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> p; cin >> cad; for (int i = 0; i < n; i++) freq[mapea(i)]++; for (int i = 0; i < p; i++) for (int j = 0; j < p; j++) { cin >> mat[i][j]; if (!mat[i][j]) compute(i, j); } for (int i = 0; i < 1 << p; i++) for (int j = 0; j < lista[i].size(); j++) bfs(i, lista[i][j].first, lista[i][j].second); cout << n - dfs(0) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[105], c[105]; int findz(int n) { return a[n] == n ? a[n] : a[n] = findz(a[n]); } void un(int x, int y) { a[findz(x)] = findz(y); } int main() { int n, l, f; cin >> n >> l; int count = 0; int wei = 0; memset(c, 0, sizeof(c)); for (int i = 1; i <= l; i++) a[i] = i; for (int i = 0; i < n; i++) { int z; cin >> z; if (z >= 1) { cin >> f; c[f]++; } else count++; for (int j = 1; j < z; j++) { int b; cin >> b; c[b]++; un(f, b); } } set<int> s; for (int i = 1; i <= l; i++) { s.insert(findz(i)); if (c[i] == 0) wei++; } if (s.size() - wei == 0) { cout << count; } else { cout << count + s.size() - wei - 1; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1010; int n, k, m; int p10[maxn]; inline void init() { p10[0] = 1; for (register int i = 1; i <= 1000; i++) { p10[i] = (p10[i - 1] * 10) % k; } } long long f[1010][110][2]; long long dfs(long long pos, long long statu, bool fg) { if (pos == n + 1) { if (fg) return 1; return 0; } if (~f[pos][statu][fg]) { return f[pos][statu][fg]; } long long ans = 0; if (pos != n) ans += dfs(pos + 1, statu, fg); for (register int i = 1; i <= 9; i++) { ans += dfs(pos + 1, (statu + i * p10[pos - 1]) % k, fg || (!((statu + i * p10[pos - 1]) % k))); ans %= m; } f[pos][statu][fg] = ans; return ans; } int main() { memset(f, -1, sizeof(f)); scanf( %d%d%d , &n, &k, &m); init(); printf( %lld n , dfs(1, 0, 0)); return 0; } |
module message_printer (
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data
);
localparam STATE_SIZE = 1;
localparam IDLE = 0,
PRINT_MESSAGE = 1;
localparam MESSAGE_LEN = 14;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [3:0] addr_d, addr_q;
message_rom message_rom (
.clk(clk),
.addr(addr_q),
.data(tx_data)
);
always @(*) begin
state_d = state_q; // default values
addr_d = addr_q; // needed to prevent latches
new_tx_data = 1'b0;
case (state_q)
IDLE: begin
addr_d = 4'd0;
if (new_rx_data && rx_data == "h")
state_d = PRINT_MESSAGE;
end
PRINT_MESSAGE: begin
if (!tx_busy) begin
new_tx_data = 1'b1;
addr_d = addr_q + 1'b1;
if (addr_q == MESSAGE_LEN-1)
state_d = IDLE;
end
end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
addr_q <= addr_d;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, m, k; cin >> n >> m >> k; long long s = 2 * n * m; if (s % k != 0) { cout << NO ; return 0; } s /= k; long long x2, x3, y2, y3; x2 = n; if (s % n == 0) y3 = s / n; else y3 = s / n + 1; long long r = y3 * n - s; y2 = 1, x3 = r; cout << YES n ; cout << 0 0 n ; cout << x2 << << y2 << n ; cout << x3 << << y3 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007LL; int n, k; string s; long long A[30]; long long ans, aux; int last[30]; int main() { cin >> n >> k >> s; memset(last, -1, sizeof(last)); int m = s.length(); ans = 1LL; for (int i = 0; i < m; i++) { aux = ans; ans = (2 * ans + MOD - A[s[i] - a ]) % MOD; A[s[i] - a ] = aux; last[s[i] - a ] = i; } for (int j = 0; j < n; j++) { int mini = (1 << 30); int let; for (int i = 0; i < k; i++) { if (last[i] < mini) { mini = last[i]; let = i; } } aux = ans; ans = (2 * ans + MOD - A[let]) % MOD; A[let] = aux; last[let] = m + j; } cout << ans << endl; } |
`default_nettype none
/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
/**
@brief Bitstream memory and read/write logic, plus parsing to shuffle it off to various peripherals
*/
module XC2CBitstream(
jtag_tck,
config_erase,
config_read_en, config_read_addr, config_read_data,
config_write_en, config_write_addr, config_write_data,
left_zia_config, right_zia_config,
left_and_config, right_and_config,
left_or_config, right_or_config,
left_mc_config, right_mc_config,
global_ce, global_sr_invert, global_sr_en, global_tris_invert, global_tris_en
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
parameter ADDR_BITS = 0;
parameter MEM_DEPTH = 0;
parameter SHREG_WIDTH = 0;
input wire jtag_tck;
input wire config_erase;
input wire config_read_en;
input wire[ADDR_BITS-1:0] config_read_addr;
output reg[SHREG_WIDTH-1:0] config_read_data = 0;
input wire config_write_en;
input wire[ADDR_BITS-1:0] config_write_addr;
input wire[SHREG_WIDTH-1:0] config_write_data;
output reg[40*8-1:0] left_zia_config;
output reg[40*8-1:0] right_zia_config;
output reg[80*56-1:0] left_and_config;
output reg[80*56-1:0] right_and_config;
output reg[16*56-1:0] left_or_config;
output reg[16*56-1:0] right_or_config;
output reg[27*16-1:0] left_mc_config;
output reg[27*16-1:0] right_mc_config;
output reg[2:0] global_ce;
output reg global_sr_invert;
output reg global_sr_en;
output reg[3:0] global_tris_invert;
output reg[3:0] global_tris_en;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The SRAM copy of the config bitstream (directly drives device behavior)
reg[SHREG_WIDTH-1:0] ram_bitstream[MEM_DEPTH-1:0];
/*
Row configuration, left to right:
1 259 Transfer bit (ignored)
9 258:250 FB2 macrocells
112 249:138 FB2 PLA
16 137:122 ZIA (interleaved)
112 121:10 FB1 PLA
9 9:1 FB1 macrocells
1 0 Transfer bit (ignored)
*/
integer row;
initial begin
for(row=0; row<MEM_DEPTH; row=row+1)
ram_bitstream[row] <= {SHREG_WIDTH{1'b1}}; //copied from blank EEPROM = all 1s
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// TODO: The EEPROM copy of the config bitstream (used to configure ram_bitstream at startup)
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// JTAG access - we have a separate, untouched copy of the raw bitstream (including transfer bits etc) for readouts
//KNOWN ISSUE: partial bitstream writes after an erase are not correctly emulated by this code.
//The entire bitstream must be written in one go to get correct readback.
//Note that actual device behavior is correct, only readback is busticated.
reg read_as_blank = 0;
reg[SHREG_WIDTH-1:0] config_read_data_raw = 0;
reg[SHREG_WIDTH-1:0] ram_bitstream_for_readback[MEM_DEPTH-1:0];
initial begin
for(row=0; row<MEM_DEPTH; row=row+1)
ram_bitstream_for_readback[row] <= {SHREG_WIDTH{1'b1}}; //copied from blank EEPROM = all 1s
end
//Read/write the EEPROM
always @(posedge jtag_tck) begin
if(config_read_en)
config_read_data_raw <= ram_bitstream_for_readback[config_read_addr];
if(config_write_en) begin
ram_bitstream[config_write_addr] <= config_write_data;
ram_bitstream_for_readback[config_write_addr] <= config_write_data;
read_as_blank <= 0;
end
//Wipe the config memory
//TODO: go multicycle?
//If we go multicycle, how do we handle this with no clock? Real chip is self-timed internally
if(config_erase) begin
read_as_blank <= 1;
for(row=0; row<MEM_DEPTH; row=row+1)
ram_bitstream[row] <= {SHREG_WIDTH{1'b1}};
end
end
//Muxing for readout
always @(*) begin
if(read_as_blank)
config_read_data <= {SHREG_WIDTH{1'b1}};
else
config_read_data <= config_read_data_raw;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Shuffle the bitstream out to various IP blocks
integer nbit;
integer nterm;
integer toprow;
integer orow;
integer mcell;
integer mcblock;
always @(*) begin
for(row=0; row<48; row=row+1) begin
toprow = row - 8;
orow = row - 20;
mcell = row / 3;
mcblock = row % 3;
//Rows 0..19: MC-AND-ZIA-AND-MC
//Rows 20...27: MC-OR--GLB-OR--MC
//Rows 28..47: MC-AND-ZIA-AND-MC
//The ZIA is bits 137:122
//MSB is FB1, next is FB2.
//We have stuff at the top and bottom of array, with global config in the middle
if(row > 27) begin
for(nbit=0; nbit<8; nbit=nbit+1) begin
right_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][137 - nbit*2];
left_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][136 - nbit*2];
end
end
else if(row < 20) begin
for(nbit=0; nbit<8; nbit=nbit+1) begin
right_zia_config[row*8 + nbit] <= ram_bitstream[row][137 - nbit*2];
left_zia_config[row*8 + nbit] <= ram_bitstream[row][136 - nbit*2];
end
end
//We have PLA AND stuff at the top and bottom of array, with OR array in the middle
//Each row is two bits from PT0, two from PT1, two from PT2, etc
//Right side: 249:138 (mirrored)
//Left side: 121:10
if(row > 27) begin
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][249 - nterm*2 - 1];
right_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][249 - nterm*2 - 0];
left_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][10 + nterm*2 + 0];
left_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][10 + nterm*2 + 1];
end
end
else if(row < 20) begin
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][249 - nterm*2 - 1];
right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][249 - nterm*2 - 0];
left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][10 + nterm*2 + 0];
left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][10 + nterm*2 + 1];
end
end
//PLA OR array
//One bit per product term, two OR terms per row
if( (row >= 20) && (row <= 27) ) begin
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_or_config[(orow*2)*56 + nterm] <= ram_bitstream[row][249 - nterm*2 - 1];
right_or_config[(orow*2+1)*56 + nterm] <= ram_bitstream[row][249 - nterm*2 - 0];
left_or_config[(orow*2)*56 + nterm] <= ram_bitstream[row][10 + nterm*2 + 0];
left_or_config[(orow*2+1)*56 + nterm] <= ram_bitstream[row][10 + nterm*2 + 1];
end
end
//Macrocells
//9 bits per row, takes 3 rows to provision one macrocell
//Right side: 258:250 (mirrored)
//Left side: 9:1
for(nbit=0; nbit<9; nbit=nbit+1) begin
left_mc_config[mcell*27 + (2 - mcblock)*9 + nbit] <= ram_bitstream[row][9 - nbit];
right_mc_config[mcell*27 + (2 - mcblock)*9 + nbit] <= ram_bitstream[row][250 + nbit];
end
end
//Pull out global config bits (no rhyme or reason here!)
global_ce[0] <= ram_bitstream[23][133];
global_ce[1] <= ram_bitstream[23][132];
global_ce[2] <= ram_bitstream[23][131];
//GSR enable
global_sr_invert <= !ram_bitstream[23][130];
global_sr_en <= ram_bitstream[23][129];
//GTS invert/enable
global_tris_invert[0] <= ram_bitstream[24][133];
global_tris_en[0] <= ram_bitstream[24][132];
global_tris_invert[1] <= ram_bitstream[24][131];
global_tris_en[1] <= ram_bitstream[24][130];
global_tris_invert[2] <= ram_bitstream[25][133];
global_tris_en[2] <= ram_bitstream[25][132];
global_tris_invert[3] <= ram_bitstream[25][131];
global_tris_en[3] <= ram_bitstream[25][130];
//All other global config is meaningless as we don't have a pad ring
//TODO: read row 48 (SEC/done) and 49 (usercode)
end
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR3 controller ODT block
//
// File : alt_ddrx_ddr3_odt_gen.v
//
// Abstract : DDR3 ODT signal generator block
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_ddr3_odt_gen
# (parameter
DWIDTH_RATIO = 2,
TCL_BUS_WIDTH = 4,
CAS_WR_LAT_BUS_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_cas_wr_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input ctl_reset_n;
input [TCL_BUS_WIDTH-1:0] mem_tcl;
input [CAS_WR_LAT_BUS_WIDTH-1:0] mem_cas_wr_lat;
input do_write;
input do_read;
output int_odt_l;
output int_odt_h;
wire do_write;
wire int_do_read;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
reg int_odt_l_int;
reg int_odt_l_int_r;
wire int_odt_l;
wire int_odt_h;
reg [2:0] doing_write_count;
reg [2:0] doing_read_count;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
assign diff_unreg = mem_tcl - mem_cas_wr_lat;
assign int_do_read = (diff > 1) ? do_read_r : do_read;
generate
if (DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = int_odt_l_int;
assign int_odt_l = int_odt_l_int;
end
else // half rate
begin
assign int_odt_h = int_odt_l_int | do_write | (int_do_read & ~|diff);
assign int_odt_l = int_odt_l_int | int_odt_l_int_r;
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
diff <= 0;
else
diff <= diff_unreg;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_r <= 0;
else
do_read_r <= do_read;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (do_write)
doing_write_count <= 1;
else if ((DWIDTH_RATIO == 2 && doing_write_count == 4) || (DWIDTH_RATIO != 2 && doing_write_count == 1))
doing_write_count <= 0;
else if (doing_write_count > 0)
doing_write_count <= doing_write_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read_count <= 0;
else
if (int_do_read)
doing_read_count <= 1;
else if ((DWIDTH_RATIO == 2 && doing_read_count == 4) || (DWIDTH_RATIO != 2 && doing_read_count == 1))
doing_read_count <= 0;
else if (doing_read_count > 0)
doing_read_count <= doing_read_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_odt_l_int <= 1'b0;
else
if (do_write || int_do_read)
int_odt_l_int <= 1'b1;
else if (doing_write_count > 0 || doing_read_count > 0)
int_odt_l_int <= 1'b1;
else
int_odt_l_int <= 1'b0;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_odt_l_int_r <= 1'b0;
else
int_odt_l_int_r <= int_odt_l_int;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { string str, ch[103]; int n; cin >> str >> n; for (int i = 1; i <= n; i++) cin >> ch[i]; sort(ch + 1, ch + 1 + n); for (int i = 1; i <= n; i++) { int len = str.length(); string t = ch[i].substr(0, len); if (t == str) { cout << ch[i] << endl; return 0; } } cout << str << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int tc, cs = 1, n, k, a, b, c, d; while (cin >> n >> k) { cin >> a >> b >> c >> d; if (k < n + 1 || n == 4) { printf( %d n , -1); } else { printf( %d %d , a, c); for (int i = 1; i < n + 1; i++) { if (i != a && i != b && i != c && i != d) { printf( %d , i); } } printf( %d %d n , d, b); printf( %d %d , c, a); for (int i = 1; i < n + 1; i++) { if (i != a && i != b && i != c && i != d) { printf( %d , i); } } printf( %d %d n , b, d); } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_PP_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.1 (win64) Build Fri Apr 14 18:55:03 MDT 2017
// Date : Mon Aug 14 17:02:30 2017
// Host : ACER-BLUES running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.v
// Design : clk_wiz_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module clk_wiz_1
(clk_txd,
clk_rxd,
resetn,
locked,
clk_in1);
output clk_txd;
output clk_rxd;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_rxd;
wire clk_txd;
wire locked;
wire resetn;
clk_wiz_1_clk_wiz_1_clk_wiz inst
(.clk_in1(clk_in1),
.clk_rxd(clk_rxd),
.clk_txd(clk_txd),
.locked(locked),
.resetn(resetn));
endmodule
(* ORIG_REF_NAME = "clk_wiz_1_clk_wiz" *)
module clk_wiz_1_clk_wiz_1_clk_wiz
(clk_txd,
clk_rxd,
resetn,
locked,
clk_in1);
output clk_txd;
output clk_rxd;
input resetn;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_1;
wire clk_rxd;
wire clk_rxd_clk_wiz_1;
wire clk_txd;
wire clk_txd_clk_wiz_1;
wire clkfbout_buf_clk_wiz_1;
wire clkfbout_clk_wiz_1;
wire locked;
wire reset_high;
wire resetn;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_1),
.O(clkfbout_buf_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_txd_clk_wiz_1),
.O(clk_txd));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_rxd_clk_wiz_1),
.O(clk_rxd));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(10),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_1),
.CLKFBOUT(clkfbout_clk_wiz_1),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_1),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_txd_clk_wiz_1),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_rxd_clk_wiz_1),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; long long mod = 0; const int N = 100005; vector<array<int, 2>> v[N]; vector<set<int>> g(N); vector<int> depth(N, 0); vector<vector<int>> p(N, vector<int>(17, 0)); vector<long long> up(N, 0); vector<long long> down(N, 0); vector<int> sz(N, 0); vector<int> ch[N]; vector<int> st[N]; vector<long long> pw(N, 1); vector<long long> inv(N, 1); long long res = 0; int root = 0; void dfs(int a) { depth[a] = depth[p[a][0]] + 1; for (int i = 1; i < 17; i++) p[a][i] = p[p[a][i - 1]][i - 1]; for (auto [to, k] : v[a]) { if (to == p[a][0]) continue; p[to][0] = a; down[to] = (10 * down[a] + k) % mod; up[to] = (pw[depth[a] - 1] * k + up[a]) % mod; dfs(to); } } int lca(int a, int b) { if (depth[a] > depth[b]) swap(a, b); for (int i = 16; i >= 0; i--) if (depth[p[b][i]] >= depth[a]) b = p[b][i]; if (a == b) return a; for (int i = 16; i >= 0; i--) { if (p[a][i] != p[b][i]) { a = p[a][i]; b = p[b][i]; } } return p[a][0]; } int dist(int a, int b) { return depth[a] + depth[b] - 2 * depth[lca(a, b)]; } long long h(int a, int b) { int l = lca(a, b); long long x = (((up[a] - up[l] + mod) % mod) * inv[depth[l] - 1]) % mod; long long y = (((down[b] - pw[depth[b] - depth[l]] * down[l]) % mod) + mod) % mod; long long z = (pw[depth[b] - depth[l]] * x + y) % mod; return z; } void find_sz(int a, int par = 0) { sz[a] = 1; for (int to : g[a]) { if (to == par) continue; find_sz(to, a); sz[a] += sz[to]; } } int find_centroid(int a, int par, int n) { for (int to : g[a]) { if (to == par) continue; if (sz[to] > n / 2) return find_centroid(to, a, n); } return a; } void build_cd(int a, int par = 0) { find_sz(a); int n = sz[a]; int centroid = find_centroid(a, 0, n); if (par == 0) root = centroid; ch[par].push_back(centroid); for (int to : g[centroid]) { g[to].erase(centroid); build_cd(to, centroid); } } long long fpow(long long b, long long e) { long long x = 1; while (e) { if (e & 1) x = (x * b) % mod; b = (b * b) % mod; e /= 2; } return x; } long long find_inv() { long long x = mod; long long tmp = mod; for (long long i = 2; i * i <= tmp; i++) { if ((tmp % i) == 0) { x /= i; x *= (i - 1); } while ((tmp % i) == 0) tmp /= i; } if (tmp > 1) { x /= tmp; x *= (tmp - 1); } return fpow(10, x - 1); } void solve(int a) { map<int, int> m; for (int to : ch[a]) { solve(to); for (int x : st[to]) { m[h(x, a)]++; st[a].push_back(x); } } res += m[0]; st[a].push_back(a); for (int to : ch[a]) { for (int x : st[to]) m[h(x, a)]--; for (int x : st[to]) { long long z = h(a, x); if (z == 0) res++; long long val = (((-z * inv[dist(a, x)]) % mod) + mod) % mod; res += m[val]; } for (int x : st[to]) m[h(x, a)]++; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n >> mod; for (int i = 0; i < n - 1; i++) { int a, b, k; cin >> a >> b >> k; a++; b++; v[a].push_back({b, k}); v[b].push_back({a, k}); g[a].insert(b); g[b].insert(a); } for (int i = 1; i <= n; i++) pw[i] = (10 * pw[i - 1]) % mod; inv[1] = find_inv(); for (int i = 2; i <= n; i++) inv[i] = (inv[i - 1] * inv[1]) % mod; dfs(1); build_cd(1); solve(root); cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int t, n, cnt = 0, ans = 0, tot = 0, num[maxn] = {}, zz[maxn] = {}, b[maxn] = {}; vector<int> k[maxn]; int powmod(int a, int b) { int ans = 1; for (; b; b >>= 1, a = a * a) if (b & 1) ans = ans * a; return ans; } int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } void div(int n) { int m = n; for (int i = 2; i * i <= n; i++) { if (m % i == 0) { zz[++cnt] = i, num[cnt] = 0; while (m % i == 0) m /= i, num[cnt]++; } } if (m > 1) zz[++cnt] = m, num[cnt] = 1; } void dfs(int x, int y, int z) { if (x > cnt) { if (y != 1) k[z].push_back(y); return; } dfs(x + 1, y, z); if (z == 0) z = x; for (int i = 1; i <= num[x]; i++) dfs(x + 1, y * powmod(zz[x], i), z); } void calc() { for (int i = 1; i < tot; i++) if (gcd(b[i], b[i + 1]) == 1) ans++; if (gcd(b[tot], b[1]) == 1) ans++; } int main() { scanf( %d , &t); while (t--) { ans = tot = cnt = 0; scanf( %d , &n); div(n); for (int i = 1; i <= cnt; i++) k[i].clear(); dfs(1, 1, 0); for (int i = 1; i <= cnt; i++) { int x = -1, y = -1; for (int j = 0; j < k[i].size(); j++) { if (k[i][j] % zz[((i + cnt - 2) % cnt + cnt) % cnt + 1] == 0) { x = k[i][j], k[i].erase(k[i].begin() + j); break; } } for (int j = 0; j < k[i].size(); j++) { if (k[i][j] % zz[i % cnt + 1] == 0) { y = k[i][j], k[i].erase(k[i].begin() + j); break; } } if (x != -1) b[++tot] = x; for (int j = 0; j < k[i].size(); j++) b[++tot] = k[i][j]; if (y != -1) b[++tot] = y; } for (int i = 1; i <= tot; i++) printf( %d , b[i]); calc(); printf( n%d n , ans); } return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Inverse_Clarke_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Inverse_Clarke_Transform
// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Clarke_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Inverse_Clarke_Transform
(
alpha_voltage,
beta_voltage,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2
);
input signed [17:0] alpha_voltage; // sfix18_En10
input signed [17:0] beta_voltage; // sfix18_En10
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
wire signed [35:0] voltage_phase_a; // sfix36_En26
wire signed [35:0] Gain1_out1; // sfix36_En26
wire signed [35:0] Gain_out1; // sfix36_En26
wire signed [35:0] voltage_phase_b; // sfix36_En26
wire signed [37:0] Add1_cast; // sfix38_En26
wire signed [37:0] Add1_cast_1; // sfix38_En26
wire signed [37:0] Add1_sub_cast; // sfix38_En26
wire signed [37:0] Add1_sub_temp; // sfix38_En26
wire signed [35:0] voltage_phase_c; // sfix36_En26
wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3]
wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3]
// Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities
// The alpha and beta components are dependent on time and speed.
//
// Inverse Clarke Transform
// <S43>/Data Type Conversion
assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}};
// <S43>/Gain1
assign Gain1_out1 = 56756 * beta_voltage;
// <S43>/Gain
assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}};
// <S43>/Add
assign voltage_phase_b = Gain1_out1 - Gain_out1;
// <S43>/Add1
assign Add1_cast = Gain_out1;
assign Add1_cast_1 = - (Add1_cast);
assign Add1_sub_cast = Gain1_out1;
assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast;
assign voltage_phase_c = Add1_sub_temp[35:0];
// <S43>/Mux
assign Mux_out1[0] = voltage_phase_a;
assign Mux_out1[1] = voltage_phase_b;
assign Mux_out1[2] = voltage_phase_c;
// <S43>/Current_Data_Type
assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[0][30:13])));
assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[1][30:13])));
assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[2][30:13])));
assign phase_voltages_0 = Current_Data_Type_out1[0];
assign phase_voltages_1 = Current_Data_Type_out1[1];
assign phase_voltages_2 = Current_Data_Type_out1[2];
endmodule // velocityControlHdl_Inverse_Clarke_Transform
|
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//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_regfile_we (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const long long INFLL = 1000000000000000000LL; const int h = 300000000; int l, r; int pr[(h >> 6) + 1]; int main() { scanf( %d%d , &l, &r); int res = 0; int r2 = (r - 1) / 2; pr[0] |= 1; for (int i = (1), _b = ((sqrt(2.0 * r2 + 1) + 1) / 2); i < _b; ++i) if ((~pr[i >> 5]) & (1 << (i & 31))) for (int i2 = 2 * i + 1, v = i * (i + 1) << 1; v <= r2; v += i2) pr[v >> 5] |= 1 << (v & 31); if (l <= 2 && 2 <= r) ++res; for (int v = 2; v <= r2; v += 2) if (l <= 2 * v + 1 && (~pr[v >> 5]) & (1 << (v & 31))) ++res; printf( %d n , res); return 0; } |
// file: timer_tb.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module timer_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
timer_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; vector<vector<int> > pre; vector<int> starts; vector<int> coproc; vector<int> cnts; vector<int> nexts; void dfs(int v, int co) { for (int p : pre[v]) { cnts[p]--; if (cnts[p] == 0) { if (coproc[p] == co) { nexts.push_back(p); } else { dfs(p, co); } } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, m; cin >> n >> m; coproc.resize(n); for (int i = 0; i < n; i++) { cin >> coproc[i]; } pre.resize(n); cnts.assign(n, 0); for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; pre[v].push_back(u); cnts[u]++; } for (int i = 0; i < n; i++) { if (cnts[i] == 0) { if (coproc[i]) nexts.push_back(i); else starts.push_back(i); } } int cnt = 0; while (starts.size() + nexts.size()) { for (auto v : starts) { dfs(v, 1); } starts.swap(nexts); nexts.clear(); if (starts.size()) { cnt++; } for (auto v : starts) { dfs(v, 0); } starts.swap(nexts); nexts.clear(); } cout << cnt << n ; return false; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int(_) = 0; (_) < (n); (_)++) { string S, T; cin >> S >> T; S.push_back( A ); T.push_back( A ); vector<pair<char, int> > sl, tl; char ns = S[0]; int cs = 1; for (int i = 1; i <= (int)(((int)(S).size()) - 1); i++) { if (S[i] == ns) cs++; else { sl.push_back(make_pair(ns, cs)); ns = S[i]; cs = 1; } } char nt = T[0]; int ct = 1; for (int i = 1; i <= (int)(((int)(T).size()) - 1); i++) { if (T[i] == nt) ct++; else { tl.push_back(make_pair(nt, ct)); nt = T[i]; ct = 1; } } bool ans = true; if (((int)(sl).size()) != ((int)(tl).size())) ans = false; for (int(i) = 0; (i) < (((int)(sl).size())); (i)++) { if (sl[i].first != tl[i].first) ans = false; if (sl[i].second > tl[i].second) ans = false; } if (ans) cout << YES << endl; else cout << NO << endl; } } |
// This module is a small fifo which has a bsg_channel_narrow
// on its output, that would send out each data in several steps
// based on the input and output width. width_p is the FIFO data
// width and width_out_p is the output width. els_p is the number
// of elements in fifo and lsb_to_msb_p determined the directions
// of sending the data. ready_THEN_valid_p determined input
// handshake protocol.
`include "bsg_defines.v"
module bsg_fifo_1r1w_narrowed
#( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter `BSG_INV_PARAM(width_out_p )
, parameter lsb_to_msb_p = 1
, parameter ready_THEN_valid_p = 0
)
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output v_o
, output [width_out_p-1:0] data_o
, input yumi_i
);
// Internal signals
logic [width_p-1:0] data;
logic yumi;
// FIFO of els_p elements of width width_p
bsg_fifo_1r1w_small #(.width_p(width_p)
,.els_p(els_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) main_fifo
( .clk_i(clk_i)
, .reset_i(reset_i)
, .data_i(data_i)
, .v_i(v_i)
, .ready_o(ready_o)
, .v_o(v_o)
, .data_o(data)
, .yumi_i(yumi)
);
// selecting from two FIFO outputs and sending one out at a time
bsg_channel_narrow #( .width_in_p(width_p)
, .width_out_p(width_out_p)
, .lsb_to_msb_p(lsb_to_msb_p)
) output_narrower
( .clk_i(clk_i)
, .reset_i(reset_i)
, .data_i(data)
, .deque_o(yumi)
, .data_o(data_o)
, .deque_i(yumi_i)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_narrowed)
|
// -----------------------------------------------------------
// PLI byte transport HDL interface
//
// @author jyeap, gkwan
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [7 : 0] source_data;
input source_ready;
input sink_valid;
input [7 : 0] sink_data;
output reg sink_ready;
output reg resetrequest;
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(.PURPOSE(PURPOSE)) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)
);
always @* begin
source_valid = jtag_source_valid;
source_data = jtag_source_data;
sink_ready = jtag_sink_ready;
resetrequest = jtag_resetrequest;
//synthesis translate_off
source_valid = pli_out_valid;
source_data = pli_out_data;
sink_ready = pli_in_ready;
resetrequest = 0;
//synthesis translate_on
end
endmodule
|
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