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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000010LL; const int mod = 1000000007; const int MAXN = 100010; int n, m, u, v, x, y, t, a, b, ans, node, cnt; bool ok[MAXN]; bool mark[MAXN]; vector<int> G[MAXN]; vector<int> out; void dfs(int node, int par) { mark[node] = true; cnt -= ok[node]; ok[node] ^= 1; for (int v : G[node]) { if (mark[v]) continue; out.push_back(v); dfs(v, node); out.push_back(node); ok[node] ^= 1; } if (ok[node] && par) { out.push_back(par); out.push_back(node); ok[par] ^= 1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; while (m--) { cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } for (int i = 1; i <= n; i++) { cin >> ok[i]; if (ok[i]) cnt++; if (!node && ok[i]) node = i; } if (!node) return cout << 0 << n , 0; ; dfs(node, 0); if (cnt) return cout << -1 << n , 0; ; if (!ok[node]) cout << out.size() + 1 << endl << node << ; else cout << out.size() << endl; for (int i : out) cout << i << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b, n, s; cin >> a >> b >> n >> s; if ((min(s / n, a) * n + b) >= s) { cout << YES << endl; } else { cout << NO << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_2_V
`define SKY130_FD_SC_LS__DFXBP_2_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxbp_2 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_2_V
|
#include <bits/stdc++.h> using namespace std; long long a[1000010]; int main() { int n; scanf( %d , &n); long long sum = 0; for (int i = 1; i <= n; ++i) { scanf( %lld , &a[i]); sum += a[i]; } if (sum <= 1) { printf( -1 n ); return 0; } long long ans = 9999999999999999; for (int i = 2; i * i <= sum; ++i) { if (sum % i) continue; long long cnt = 0, pre = 0; while (sum % i == 0) sum /= i; for (int j = 1; j <= n; ++j) { pre = (pre + a[j]) % i; cnt += min(pre, i - pre); } ans = min(ans, cnt); } if (sum > 1) { long long pre = 0, cnt = 0; for (int j = 1; j <= n; ++j) { pre = (pre + a[j]) % sum; cnt += min(pre, sum - pre); } ans = min(ans, cnt); } printf( %lld , ans); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
interface intf;
logic logic_in_intf;
modport source(output logic_in_intf);
modport sink(input logic_in_intf);
endinterface
module modify_interface
(
input logic value,
intf.source intf_inst
);
assign intf_inst.logic_in_intf = value;
endmodule
function integer return_3();
return 3;
endfunction
module t
#(
parameter N = 6
)();
intf ifs[N-1:0] ();
logic [N-1:0] data;
assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1};
generate
genvar i;
for (i = 0;i < 3; i++) begin
assign ifs[i].logic_in_intf = data[i];
end
endgenerate
modify_interface m3 (
.value(data[return_3()]),
.intf_inst(ifs[return_3()]));
modify_interface m4 (
.value(data[4]),
.intf_inst(ifs[4]));
modify_interface m5 (
.value(~ifs[4].logic_in_intf),
.intf_inst(ifs[5]));
generate
genvar j;
for (j = 0;j < N-1; j++) begin
initial begin
if (ifs[j].logic_in_intf != data[j]) $stop;
end
end
endgenerate
initial begin
if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V
`define SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapmet1 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_errman_ram8x26.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
Description:
This is the 4x50 dual port RAM for the header information of the
outstanding Completion packets in the error manager.
The RAM output is registered.
***********************************************************************/
`define FFD 1
module cmm_errman_ram8x26 (
rddata, // Output
wrdata, // Inputs
wr_ptr,
rd_ptr,
we,
rst,
clk
);
output [49:0] rddata;
input [49:0] wrdata;
input [2:0] wr_ptr;
input [2:0] rd_ptr;
input we;
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
//******************************************************************//
// Construct the RAM. //
//******************************************************************//
reg [49:0] lutram_data [0:7];
always @(posedge clk) begin
if (we)
lutram_data[wr_ptr] <= #`FFD wrdata;
end
//******************************************************************//
// Register the outputs. //
//******************************************************************//
reg [49:0] reg_rdata;
always @(posedge clk or posedge rst)
begin
if (rst) reg_rdata <= #`FFD 50'h0000_0000_0000;
else reg_rdata <= #`FFD lutram_data[rd_ptr];
end
assign rddata = reg_rdata;
//******************************************************************//
// //
//******************************************************************//
endmodule
|
module simf_tb;
//wires
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value, rfa_queue_entry_serviced;
reg [5:0] issue_wfid;
reg [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg1, issue_dest_reg2;
reg [15:0] issue_imm_value0;
reg [31:0] issue_imm_value1, issue_opcode, sgpr_rd_data, exec_rd_m0_value,
issue_instr_pc;
reg [63:0] exec_rd_exec_value, exec_rd_vcc_value;
reg [2047:0] vgpr_source1_data, vgpr_source2_data, vgpr_source3_data;
wire vgpr_source1_rd_en, vgpr_source2_rd_en, vgpr_source3_rd_en, vgpr_wr_en,
exec_rd_en, exec_wr_vcc_en, sgpr_rd_en, sgpr_wr_en, issue_alu_ready,
vgpr_instr_done, rfa_queue_entry_valid;
wire [5:0] exec_rd_wfid, exec_wr_vcc_wfid, vgpr_instr_done_wfid;
wire [8:0] sgpr_rd_addr, sgpr_wr_addr;
wire [9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_source3_addr,
vgpr_dest_addr;
wire [31:0] tracemon_retire_pc;
wire [63:0] vgpr_wr_mask, exec_wr_vcc_value, sgpr_wr_data;
wire [2047:0] vgpr_dest_data;
//instantiation of dut
simf simf(
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3), //TODO implement this.
.issue_dest_reg1(issue_dest_reg1),
.issue_dest_reg2(issue_dest_reg2), //TODO implement this
.issue_imm_value0(issue_imm_value0),
.issue_imm_value1(issue_imm_value1),
.issue_opcode(issue_opcode),
.issue_wfid(issue_wfid),
.issue_alu_select(issue_alu_select),
.vgpr_source1_data(vgpr_source1_data),
.vgpr_source2_data(vgpr_source2_data),
.vgpr_source3_data(vgpr_source3_data), //TODO implement this
.sgpr_rd_data(sgpr_rd_data),
.exec_rd_exec_value(exec_rd_exec_value),
.exec_rd_vcc_value(exec_rd_vcc_value),
.exec_rd_m0_value(exec_rd_m0_value), //TODO implement this
.exec_rd_scc_value(exec_rd_scc_value),
.issue_instr_pc(issue_instr_pc),
.rfa_queue_entry_serviced(rfa_queue_entry_serviced),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source3_rd_en(vgpr_source3_rd_en), //TODO
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.vgpr_source3_addr(vgpr_source3_addr), //TODO implement
.vgpr_dest_addr(vgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_wr_en(vgpr_wr_en),
.vgpr_wr_mask(vgpr_wr_mask),
.exec_rd_wfid(exec_rd_wfid),
.exec_rd_en(exec_rd_en),
.exec_wr_vcc_wfid(exec_wr_vcc_wfid),
.exec_wr_vcc_en(exec_wr_vcc_en),
.exec_wr_vcc_value(exec_wr_vcc_value),
.sgpr_rd_en(sgpr_rd_en),
.sgpr_rd_addr(sgpr_rd_addr),
.sgpr_wr_addr(sgpr_wr_addr), //TODO
.sgpr_wr_en(sgpr_wr_en), //TODO
.sgpr_wr_data(sgpr_wr_data), //TODO
.issue_alu_ready(issue_alu_ready),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.vgpr_instr_done(vgpr_instr_done),
.rfa_queue_entry_valid(rfa_queue_entry_valid),
.tracemon_retire_pc(tracemon_retire_pc),
.clk(clk),
.rst(rst)
);
//stimulii
initial begin
forever #5 clk = ~clk;
end
initial begin
#3 clk = 1'b0;
#16 rst = 1'b1;
issue_alu_select = 1'b0;
rfa_queue_entry_serviced = 1'b0;
#10 rst = 1'b0;
#10000;
$finish;
end
initial begin
#31;
$display("ISSUING FLOAT ADD\n");
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_source_reg3 = {32{1'bx}};
issue_dest_reg1 = {2'b10,10'd31};
issue_dest_reg2 = {12{1'bx}};
issue_imm_value0 = {16{1'bx}};
issue_imm_value1 = {32{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h003}; //V_ADD_F32
issue_wfid = 6'd15;
issue_alu_select = 1'b1;
sgpr_rd_data = {32{1'bx}};
exec_rd_exec_value = 64'hf0ff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
exec_rd_m0_value = {32{1'bx}};
exec_rd_scc_value = 1'bx;
issue_instr_pc = 32'hdead_f00d;
rfa_queue_entry_serviced = 1'b0;
vgpr_source1_data = {64{32'h4205_9999}}; //33.4
vgpr_source2_data = {64{32'h41B7_3333}}; //22.9
vgpr_source3_data = {64{32'hx}};
#10;
issue_alu_select = 1'b0;
#1000;
$display("ISSUING FLOAT SUB\n");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h004}; //V_SUB_F32
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h4205_9999}}; //33.4
vgpr_source2_data = {64{32'h41B7_3333}}; //22.9
#10;
issue_alu_select = 1'b0;
#10;
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#1000;
$display("ISSUING FLOAT MUL");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h008}; //V_MUL_F32
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h4205_9999}}; //33.4
vgpr_source2_data = {64{32'h41B7_3333}}; //22.9
#10;
issue_alu_select = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
end
//monitors
initial begin
if ($test$plusargs("print_outputs")) begin
$monitor($time, ": issue_alu_select = %b, issue_alu_ready = %b \n \
rfa_queue_entry_serviced = %h, rfa_queue_entry_valid = %h \n \
vgpr_dest_data = %h",
issue_alu_select, issue_alu_ready,
rfa_queue_entry_serviced, rfa_queue_entry_valid,
vgpr_dest_data[31:0]
);
// $monitor("$time: vgpr_dest_data = %h", vgpr_dest_data);
//$monitor("$time: rfa_queue_entry_serviced = %b", rfa_queue_entry_serviced);
end
end
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,simf_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 23:43:00 02/04/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: Switch_Debounce_Synchronizer
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v15.0
// Description: Asynchronous signal synchronizer and signal debouncer.
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Switch_Debounce_Synchronizer
#(
parameter CLK_RATE_HZ = 50000000, // Hz
parameter DEBOUNCE_TIME = 10000, // ns
parameter SIG_OUT_INIT = 1'b0
)
(
// Input Signals (asynchronous)
input SIG_IN,
// Output Signals (synchronized to CLK domain)
output reg SIG_OUT,
// System Signals
input CLK
);
// Include StdFunctions for bit_index()
`include "StdFunctions.vh"
//
// Compute Debounce Counter Parameters
//
localparam DBNC_TICKS = DEBOUNCE_TIME / (.0 / CLK_RATE_HZ);
localparam DBNC_COUNT_WIDTH = bit_index(DBNC_TICKS);
localparam DBNC_COUNT_LOADVAL = {1'b1, {(DBNC_COUNT_WIDTH){1'b0}}} - DBNC_TICKS;
reg [2:0] dbnc_reg;
reg [DBNC_COUNT_WIDTH:0] dbnc_count_reg;
wire dbnc_transition;
wire dbnc_count_done;
//
// Initial register values
//
initial
begin
dbnc_reg = 3'h0;
dbnc_count_reg = DBNC_COUNT_LOADVAL;
SIG_OUT = SIG_OUT_INIT;
end
//
// Synchronize Input Signal to the CLK Domain
//
wire sw_sync;
CDC_Input_Synchronizer
#(
.SYNC_REG_LEN( 1 )
)
sw_synchronizer
(
// Input Signal
.ASYNC_IN( SIG_IN ),
// Output Signal
.SYNC_OUT( sw_sync ),
// System Signals
.CLK( CLK )
);
//
// Bus Signal State Transition Detector
//
assign dbnc_transition = dbnc_reg[1] ^ dbnc_reg[0];
always @(posedge CLK)
begin
dbnc_reg <= { dbnc_reg[1:0], sw_sync };
end
//
// Debounce Counter
//
assign dbnc_count_done = dbnc_count_reg[DBNC_COUNT_WIDTH];
always @(posedge CLK)
begin
if (dbnc_transition)
dbnc_count_reg <= DBNC_COUNT_LOADVAL;
else if (!dbnc_count_done)
dbnc_count_reg <= dbnc_count_reg + 1'b1;
end
//
// Bus Signal Output Register
//
always @(posedge CLK)
begin
if (dbnc_count_done)
SIG_OUT <= dbnc_reg[2];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; string s; cin >> n; cin >> s; map<char, long long int> M; long long int i; for (i = 0; i < n; i++) { M[s[i]]++; } long long int z = n / 3; if (M[ 0 ] < z) { for (i = 0; i < n; i++) { if (M[s[i]] > z && s[i] != 0 && M[ 0 ] < z) { M[s[i]]--; s[i] = 0 ; M[ 0 ]++; } } } if (M[ 2 ] < z) { for (i = n - 1; i >= 0; i--) { if (M[s[i]] > z && s[i] != 2 && M[ 2 ] < z) { M[s[i]]--; s[i] = 2 ; M[ 2 ]++; } } } if (M[ 1 ] < z) { for (i = n - 1; i >= 0; i--) { if (M[s[i]] > z && s[i] == 0 && M[ 1 ] < z) { M[s[i]]--; s[i] = 1 ; M[ 1 ]++; } } for (i = 0; i < n; i++) { if (M[s[i]] > z && s[i] == 2 && M[ 1 ] < z) { M[s[i]]--; s[i] = 1 ; M[ 1 ]++; } } } cout << s << endl; return 0; } |
#include <bits/stdc++.h> int aa[100005]; int main(void) { int n; while (~scanf( %d , &n)) { for (int i = 0; i < n; i++) { scanf( %d , &aa[i]); } for (int i = 0; i < n - 1; i++) { printf( %d , aa[i] + aa[i + 1]); } printf( %d n , aa[n - 1]); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 14:48:00 09/10/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: CLS_LED_Output_Fader
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: CLS LED Output Fader
//
// The LED Output Fader will set the LEDR output to full brightness
// when the LED_FULL_ON signal is asserted. When released,
// the LED output is decreased one step per FADE_TIMER_TICK.
// Any changes to the LED output should happen on the assertion
// of PWM_TIMER_TICK.
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module CLS_LED_Output_Fader
(
// Input Signals
input LED_FULL_ON,
input [6:0] PWM_CHANNEL_SIGS,
input PWM_TIMER_TICK,
input FADE_TIMER_TICK,
// Output Signals
output reg LEDR,
// System Signals
input CLK
);
//
// Initialize Register values
//
reg [2:0] led_mux_select;
reg [2:0] led_brightness_reg;
initial
begin
LEDR <= 1'b0;
led_mux_select <= 3'h0;
led_brightness_reg <= 3'h0;
end
//
// Current Brightness Register
//
// Set the register to full brightness when LED_FULL_ON asserts.
// Decrement register until 0 on each FADE_TIMER_TICK assertion.
//
// !! LAB 3: Add led_brightness_reg implementation here !!
always @(posedge CLK)
begin
if (LED_FULL_ON)
led_brightness_reg <= 3'h7;
else if ((FADE_TIMER_TICK == 1) && (led_brightness_reg != 3'h0))
led_brightness_reg <= led_brightness_reg - 1'b1;
else if (FADE_TIMER_TICK)
led_brightness_reg <= 3'h0;
end
//
// Syncronize mux changes with the PWM timer tick
//
// Load led_mux_select with led_brightness_reg value when
// PWM_TIMER_TICK asserts.
//
// !! LAB 3: Add led_mux_select implementation here !!
always @(posedge CLK)
begin
if(PWM_TIMER_TICK)
led_mux_select <= led_brightness_reg;
end
//
// LED Output PWM Multiplexer
//
// !! LAB 3: Add LEDR implementation here !!
always @(posedge CLK)
begin
case (led_mux_select)
3'b000: LEDR <= 1'b0;
3'b001: LEDR <= PWM_CHANNEL_SIGS[0];
3'b010: LEDR <= PWM_CHANNEL_SIGS[1];
3'b011: LEDR <= PWM_CHANNEL_SIGS[2];
3'b100: LEDR <= PWM_CHANNEL_SIGS[3];
3'b101: LEDR <= PWM_CHANNEL_SIGS[4];
3'b110: LEDR <= PWM_CHANNEL_SIGS[5];
3'b111: LEDR <= PWM_CHANNEL_SIGS[6];
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using lint = long long; using pi = pair<lint, lint>; const int MAXN = 100005; int n, m, sum; int cnt[MAXN]; set<int> s[MAXN]; int p[MAXN]; vector<tuple<int, int, int>> dap; void MOVE(int dst, int src, int v) { vector<int> mutation; for (auto &i : s[dst]) { if (s[src].find(i) == s[src].end()) { continue; } s[src].erase(i); mutation.push_back(i); } while (v--) { auto x = *s[src].begin(); s[src].erase(x); s[dst].insert(x); dap.emplace_back(src + 1, dst + 1, x); } for (auto &i : mutation) s[src].insert(i); } int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { int x; scanf( %d , &x); sum += x; p[i] = i; for (int j = 0; j < x; j++) { int v; scanf( %d , &v); s[i].insert(v); } } for (int i = 0; i < sum; i++) { cnt[n - 1 - i % n]++; } sort(p, p + n, [&](const int &a, const int &b) { return s[a].size() < s[b].size(); }); int lx = -1, ly = 1e9; for (int i = 0; i < n; i++) { if (s[p[i]].size() < cnt[i]) { lx = i; } if (s[p[i]].size() > cnt[i]) ly = min(ly, i); } if (lx == -1) { puts( 0 ); return 0; } while (true) { while (lx >= 0 && s[p[lx]].size() == cnt[lx]) lx--; while (ly < n && s[p[ly]].size() == cnt[ly]) ly++; if (lx == -1) break; int thres0 = cnt[lx] - s[p[lx]].size(); int thres1 = s[p[ly]].size() - cnt[ly]; MOVE(p[lx], p[ly], min(thres0, thres1)); } printf( %d n , dap.size()); for (auto &i : dap) { int x, y, z; tie(x, y, z) = i; printf( %d %d %d n , x, y, z); } } |
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_8_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11
)
(
input wire S_AXI_ACLK,
input wire S_AXI_ARESET,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [7:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 1'b0;
localparam P_READ_DATA = 1'b1;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
end
end else if (S_AXI_AWVALID & S_AXI_WVALID) begin
if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
s_axi_wready_i <= 1'b1;
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
end
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [7:0] read_cnt;
reg [1:0] write_cs;
reg [0:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = s_axi_bid_i;
assign S_AXI_RID = s_axi_rid_i;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rvalid_i <= 1'b1;
if (S_AXI_ARLEN == 0) begin
s_axi_rlast_i <= 1'b1;
end else begin
s_axi_rlast_i <= 1'b0;
end
read_cs <= P_READ_DATA;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: four_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module four_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/four_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/four_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/four_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, t, i; cin >> t; for (i = 0; i < t; i++) { cin >> a >> b; cout << a + b; cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const pair<int, int> MOD = make_pair(1e9 + 7, 1e9 + 9); const int base = 1e6 + 3; const int N = 1e5 + 100, B = 600; pair<int, int> operator+(pair<int, int> a, pair<int, int> b) { return make_pair((a.first + b.first) % MOD.first, (a.second + b.second) % MOD.second); } pair<int, int> operator-(pair<int, int> a, pair<int, int> b) { return make_pair((a.first - b.first + MOD.first) % MOD.first, (a.second - b.second + MOD.second) % MOD.second); } pair<int, int> operator*(pair<int, int> a, int x) { return make_pair(1ll * a.first * x % MOD.first, 1ll * a.second * x % MOD.second); } pair<int, int> operator*(pair<int, int> a, pair<int, int> b) { return make_pair(1ll * a.first * b.first % MOD.first, 1ll * a.second * b.second % MOD.second); } int n, K, q; int a[N]; vector<pair<int, int>> open_Hash[B], close_Hash[B]; pair<int, int> base_pow[N], inv_pow[N]; int good[N]; int bm(int b, int p, int m) { if (p == 0) return 1; int t = bm(b, p / 2, m); t = 1ll * t * t % m; if (p & 1) return 1ll * b * t % m; return t; } void pre() { base_pow[0] = {1, 1}; inv_pow[0] = {1, 1}; for (int i = 1; i < N; i++) { base_pow[i] = base_pow[i - 1] * base; inv_pow[i].first = bm(base_pow[i].first, MOD.first - 2, MOD.first); inv_pow[i].second = bm(base_pow[i].second, MOD.second - 2, MOD.second); } } bool recal(int l, int r, vector<pair<int, int>> &close, vector<pair<int, int>> &open) { vector<int> stk; for (int i = l; i <= r; i++) { if (a[i] < 0 && stk.size() > 0 && stk.back() == abs(a[i])) stk.pop_back(); else stk.push_back(a[i]); } close.clear(); open.clear(); bool pos = false; for (int i = 0; i < stk.size(); i++) { if (stk[i] > 0) pos = true; if (stk[i] < 0 && pos) return false; } for (int i = 0; i < stk.size(); i++) { if (stk[i] > 0) break; int x = abs(stk[i]); int kth = close.size(); close.push_back(base_pow[kth] * x); } for (int i = 1; i < close.size(); i++) { close[i] = close[i - 1] + close[i]; } for (int i = (int)stk.size() - 1; i >= 0; i--) { if (stk[i] < 0) break; int x = abs(stk[i]); int kth = open.size(); open.push_back(base_pow[kth] * x); } for (int i = 1; i < open.size(); i++) { open[i] = open[i - 1] + open[i]; } return true; } bool find_hash(vector<pair<int, int>> &all_open, int sz, pair<int, int> hhh) { assert(sz > 0); int psz = 0; pair<int, int> h = {0, 0}; while (psz < sz && all_open.size() > 0) { auto t = all_open.back(); all_open.pop_back(); int which_block = t.first, idx = t.second; int cur_sz = open_Hash[which_block].size() - idx; assert(cur_sz > 0); if (cur_sz + psz < sz) { pair<int, int> hh = (open_Hash[which_block].back() - (idx > 0 ? open_Hash[which_block][idx - 1] : make_pair(0, 0))) * inv_pow[idx]; hh = hh * base_pow[psz]; h = h + hh; psz += cur_sz; } else { int lage = sz - psz; pair<int, int> hh = (open_Hash[which_block][idx + lage - 1] - (idx > 0 ? open_Hash[which_block][idx - 1] : make_pair(0, 0))) * inv_pow[idx]; hh = hh * base_pow[psz]; h = h + hh; if (idx + lage < open_Hash[which_block].size()) all_open.push_back({which_block, idx + lage}); psz += lage; } } if (psz < sz) return 0; if (hhh != h) return 0; return 1; } int query(int l, int r) { int bl = l / B, br = r / B; if (bl == br) { vector<pair<int, int>> p, s; int x = recal(l, r, p, s); if (x && (int)p.size() == 0 && (int)s.size() == 0) return 1; return 0; } if (recal(l, (bl + 1) * B - 1, close_Hash[B - 2], open_Hash[B - 2]) == 0) return 0; if (close_Hash[B - 2].size() > 0) return 0; vector<pair<int, int>> all_open; if (open_Hash[B - 2].size() > 0) all_open.push_back({B - 2, 0}); for (int b = bl + 1; b < br; b++) { if (!good[b]) return 0; if (close_Hash[b].size() == 0) { if (open_Hash[b].size() > 0) all_open.push_back({b, 0}); continue; } int sz = close_Hash[b].size(); if (!find_hash(all_open, sz, close_Hash[b].back())) return 0; if (open_Hash[b].size() > 0) all_open.push_back({b, 0}); } if (recal(br * B, r, close_Hash[B - 1], open_Hash[B - 1]) == 0) return 0; if (open_Hash[B - 1].size() > 0) return 0; if (close_Hash[B - 1].size() > 0 && !find_hash(all_open, close_Hash[B - 1].size(), close_Hash[B - 1].back())) return 0; if (all_open.size() > 0) return 0; return 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); pre(); cin >> n >> K; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0, j = 0; i < n; i += B, j++) { good[j] = recal(i, min(i + B - 1, n - 1), close_Hash[j], open_Hash[j]); } int q; cin >> q; while (q--) { int t; cin >> t; if (t == 1) { int idx, x; cin >> idx >> x; idx--; a[idx] = x; int b = idx / B; int l = b * B, r = min(l + B - 1, n - 1); good[b] = recal(l, r, close_Hash[b], open_Hash[b]); } else { int l, r; cin >> l >> r; l--, r--; if (query(l, r)) cout << Yes << endl; else cout << No << endl; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A32OI_FUNCTIONAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_FUNCTIONAL_PP_V |
// file: testclk_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.mmcm_adv_inst.LOCKED)
module testclk_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 3.906*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (3.906*2*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (3.906*2*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (3.906*2*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (3.906*2*4*1000/8.000);
time prev_rise4;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", /period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", /period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", /period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", /period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
testclk_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_SYMBOL_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A211O_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211o (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { if (b == 0) return 1; if (b % 2 == 0) return power(a * a % 1000000007, b / 2); return a * power(a, b - 1) % 1000000007; } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } long long a[100000]; int main() { long long n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long ans = 0; for (int i = 0; i < n / 2; i++) { ans += a[i] * a[n - i - 1] * 2; ans %= 10007; } if (n % 2) ans += a[n / 2] * a[n / 2]; ans %= 10007; cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_decrement_assert #(
.width(width),
.value(value))
assert_decrement_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_decrement_assume #(
.width(width),
.value(value))
assert_decrement_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_decrement_cover #(
.width(width),
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_decrement_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_decrement.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_decrement_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter value = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_decrement_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter value = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_decrement_cover (clk, reset_n, test_expr);
parameter width = 8;
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n;
input [width-1:0] test_expr;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_SYMBOL_V
`define SKY130_FD_SC_LP__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_SYMBOL_V
|
//
// Copyright (c) 1999 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Test the divide (/) operator
module top () ;
reg [7:0] a, b, result;
wire [7:0] wa, wb, wresult;
assign wa = a;
assign wb = b;
assign wresult = wa / wb;
always @(a or b)
result = a / b;
initial begin
#1 a = 0; b = 1;
# 1;
if( result !== 8'b0)
begin
$display("FAILED - Divide 0/1 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'b0)
begin
$display("FAILED - Divide 0/1 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 1;
#1 if( result !== 8'b1)
begin
$display("FAILED - Divide 1/1 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'b1)
begin
$display("FAILED - Divide 1/1 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 5; b = 2;
#1 if( result !== 8'd2)
begin
$display("FAILED - Divide 5/2 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'd2)
begin
$display("FAILED - Divide 5/2 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 8'd255; b = 5;
#1 if( result !== 51)
begin
$display("FAILED - Divide 255/5 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 51)
begin
$display("FAILED - Divide 255/5 wire assign failed - is %b",wresult);
$finish;
end
#1 a = 1'bx; b = 3;
#1 if( result !== 8'bxxxx_xxxx)
begin
$display("FAILED - Divide x/3 reg assign failed - is %b",result);
$finish;
end
if( wresult !== 8'bxxxx_xxxx)
begin
$display("FAILED - Divide x/3 wire assign failed - is %b",wresult);
$finish;
end
$display("PASSED");
end
endmodule
|
`include "defines.v"
`include "nodeRouter.v"
`timescale 1ns/1ps
/*
input `control_w port0_ci,
input `control_w port1_ci,
input `control_w portl0_ci,
input `control_w portl1_ci,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_co,
output `control_w port1_co,
output `control_w portl0_co,
output `control_w portl1_co,
*/
module tb(
);
wire ack0, ack1;
reg clk, rst;
reg `control_w flit0c, flit1c, flitl0, flitl1;
wire `control_w port0_co, port1_co, portl0_co, portl1_co;
nodeRouter r(
.clk(clk),
.rst(rst),
.port0_ci(144'h0), .port0_co(port0_co),
.port1_ci(144'h0), .port1_co(port1_co),
.portl0_ci(144'h0), .portl0_co(portl0_co),
.portl1_ci(144'h0), .portl1_co(portl1_co),
.portl0_ack(ack0), .portl1_ack(ack1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
#1;
clk = 1;
#1;
clk = 0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
#1;
clk = 1;
#1;
clk = 0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, m; int nt, kt, mt; int su[100004]; long long sum = 0; double res; int main() { scanf( %d%d%d , &n, &k, &m); nt = n; kt = k; mt = m; for (int i = 0; i < n; i++) { scanf( %d , su + i); sum += su[i]; } res = 1.0 * sum / n; sort(su, su + n); long long ts = 0; for (int i = 1; i <= n; i++) { ts += su[n - i]; long long rm = m - n + i; long long te = i; long long tk = k; if (rm < 0) { continue; } res = max(res, (ts + min(rm, te * tk)) * 1.0 / te); } printf( %lf n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<vector<int>> a(n, vector<int>(m)), n_s(1001, vector<int>(1001)), n_c(1001, vector<int>(1001)); vector<int> m_s(1001), m_c(1001); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) { vector<pair<int, int>> num; for (int j = 0; j < m; j++) num.push_back(make_pair(a[i][j], j)); sort(num.begin(), num.end()); int h = 0; for (int k = 0; k < num.size(); k++) { if (k && num[k].first != num[k - 1].first) h++; n_s[i][num[k].second] = h; } m_s[i] = h; } for (int i = 0; i < m; i++) { vector<pair<int, int>> num; for (int j = 0; j < n; j++) num.push_back(make_pair(a[j][i], j)); sort(num.begin(), num.end()); int h = 0; for (int k = 0; k < num.size(); k++) { if (k && num[k].first != num[k - 1].first) h++; n_c[i][num[k].second] = h; } m_c[i] = h; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int l_s = n_s[i][j]; int l_c = n_c[j][i]; int g_s = m_s[i] - l_s; int g_c = m_c[j] - l_c; cout << max(l_s, l_c) + 1 + max(g_s, g_c) << ; } cout << endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:20:54 03/02/2016
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(
output zero,
output [31:0] aluRes,
input [31:0] input1,
input [31:0] input2,
input [3:0] aluCtr
);
reg zero;
reg [31:0] aluRes;
always @ (input1 or input2 or aluCtr)
begin
if(aluCtr == 4'b0010) //+
aluRes = input1 + input2;
else if(aluCtr == 4'b0110) //-
begin
aluRes = input1 - input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0000) //&
begin
aluRes = input1 & input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0001) //|
begin
aluRes = input1 | input2;
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
else if(aluCtr == 4'b0111) //slt
begin
if(input1 < input2)
begin
zero = 0;
aluRes = 1;
end
else
begin
zero = 1;
aluRes = 0;
end
end
else if(aluCtr == 4'b1100) //NOR
begin
aluRes = ~(input1 | input2);
if(aluRes == 0)
zero = 1;
else
zero = 0;
end
end
endmodule
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
fritz
instruction decode phase
*/
module cpu_id(rst, clk, cpu_stall, if_pc, if_inst, wb_rfw,
wb_rf_waddr, wb_rf_wdata, p_rfa, p_rfb, p_se,
p_shamt, p_func, p_rf_waddr, p_c_rfw, p_c_wbsource,
p_c_drw, p_c_alucontrol, p_c_j, p_c_b, p_c_jjr,
p_jaddr, p_pc, p_c_rfbse, p_rs, p_rt, c_stall, int_flush);
input rst, clk, cpu_stall;
input [31:0] if_pc;
input [31:0] if_inst;
input wb_rfw;
input [4:0] wb_rf_waddr;
input [31:0] wb_rf_wdata;
input int_flush;
output reg [31:0] p_rfa;
output reg [31:0] p_rfb;
output reg [31:0] p_se;
output reg [4:0] p_shamt;
output reg [5:0] p_func;
output reg [4:0] p_rf_waddr;
output reg p_c_rfw;
output reg [1:0] p_c_wbsource;
output reg [1:0] p_c_drw;
output reg [5:0] p_c_alucontrol;
output reg p_c_j;
output reg p_c_b;
output reg p_c_jjr;
output reg [25:0] p_jaddr;
output reg [31:0] p_pc;
output reg p_c_rfbse;
output reg [4:0] p_rs;
output reg [4:0] p_rt;
output c_stall;
reg [31:0] rf [31:1];
wire [5:0] opcode = if_inst[31:26];
wire [4:0] rf_rs = if_inst[25:21];
wire [4:0] rf_rt = if_inst[20:16];
wire [4:0] rf_rd = if_inst[15:11];
wire [15:0] imm = if_inst[15:0];
wire [4:0] shamt = if_inst[10:6];
wire [5:0] func = if_inst[5:0];
wire [25:0] jaddr = if_inst[25:0];
wire [31:0] rfa = rf_rs == 0 ? 0 : rf[rf_rs];
wire [31:0] rfb = rf_rt == 0 ? 0 : rf[rf_rt];
/* hazard logic */
wire stall = (p_c_rfw & (p_c_alucontrol == 6'h23) & ((p_rt == rf_rs) | (p_rt == rf_rt)) & (p_rt != 0) & (opcode != 6'h2b));
assign c_stall = stall;
/* control logic */
wire c_rfw = (
opcode != 6'h04 &&
opcode != 6'h05 &&
opcode != 6'h2b &&
opcode != 6'h02 &&
!stall); /* secret bug, jump register asserts write enable but the assembler sets rd = 0 */
wire [1:0] c_wbsource =
(opcode == 6'h23) ? 2'h1 :
(opcode == 6'h03) ? 2'h2 :
(opcode == 6'h00 && func == 6'h09) ? 2'h2 : 0;
wire [1:0] c_drw = (opcode == 6'h2b && !stall) ? 2'b01 :
(opcode == 6'h23 && !stall) ? 2'b10 : 2'b00; /* c_drw[1] = read, c_drw[0] = write, 00 = nop */
wire [5:0] c_alucontrol = opcode;
wire c_se = (opcode == 6'h0c || opcode == 6'h0d) ? 0 : 1;
wire c_rfbse = (opcode == 6'h00 || opcode == 6'h04 || opcode == 6'h05) ? 0 : 1;
wire c_jjr =
opcode == 6'h02 ? 0 :
opcode == 6'h03 ? 0 : 1;
wire [1:0] c_rd_rt_31 =
(opcode == 6'h03) ? 2'b10 : /* jal */
(opcode == 6'h00) ? 2'b00 : 2'b01;
/* internal logic */
wire [31:0] signext_imm = {{16{imm[15]}},imm};
wire [31:0] zeroext_imm = {{16{1'b0}},imm};
wire [31:0] se = c_se ? signext_imm : zeroext_imm;
wire [4:0] rd_rt_31 =
(c_rd_rt_31 == 2'b00) ? rf_rd :
(c_rd_rt_31 == 2'b01) ? rf_rt :
(c_rd_rt_31 == 2'b10) ? 5'b11111 : rf_rd;
wire c_j =
((opcode == 6'h02) ||
(opcode == 6'h03) ||
(opcode == 6'h00 && func == 6'h08) ||
(opcode == 6'h00 && func == 6'h09)) && !stall;
wire c_b = ((opcode == 6'h04) || (opcode == 6'h05)) && !stall;
always @(posedge clk) begin
if (!cpu_stall) begin
if (rst || int_flush) begin
p_rfa <= 0;
p_rfb <= 0;
p_shamt <= 0;
p_func <= 0;
p_rf_waddr <= 0;
p_c_rfw <= 0;
p_c_wbsource <= 0;
p_c_drw <= 0;
p_c_alucontrol <= 0;
p_c_j <= 0;
p_c_b <= 0;
p_c_jjr <= 0;
p_jaddr <= 0;
p_pc <= 0;
p_c_rfbse <= 0;
p_rs <= 0;
p_rt <= 0;
p_se <= 0;
end else begin
p_rfa <= rfa;
p_rfb <= rfb;
p_shamt <= shamt;
p_func <= func;
p_rf_waddr <= rd_rt_31;
p_c_rfw <= c_rfw;
p_c_wbsource <= c_wbsource;
p_c_drw <= c_drw;
p_c_alucontrol <= c_alucontrol;
p_c_j <= c_j;
p_c_b <= c_b;
p_c_jjr <= c_jjr;
p_jaddr <= jaddr;
p_pc <= if_pc;
p_c_rfbse <= c_rfbse;
p_rs <= rf_rs;
p_rt <= rf_rt;
p_se <= se;
end
/* debug statements, not synthesized by Xilinx */
//$display("ID: INST: %x", if_inst);
end
end
always @(negedge clk) begin
/* regfile */
if (wb_rfw && wb_rf_waddr != 5'd0) begin
rf[wb_rf_waddr] <= wb_rf_wdata;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: sec_monitor.v
// Project: ngnp
// Description: compares currently executed instruction address to monitoring graph contents
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sec_monitor(
// --- Misc
input core_sp_clk,
input [31:0] pp_mem_addr,
input reset,
output drop_packet
);
//-------------------- Internal Parameters ------------------------
//---------------------- Wires and regs----------------------------
//only connections in this file, this is the upper level module that connects the stages
wire [31:0] proc_addr; //connect sp address to stage 1 address where we need to fetch it
wire [12:2] bbr_addr; //signal from stage 2 to the memories to start lookup
wire [12:2] dupl_bbr_addr; //signal from stage 3 to the bbram to start lookup
// memory wires
wire [31:0] bbr_data_out; //output of memory basic block ram, which goes as input to stage 3
wire [31:0] nhr_data_out; //output of memory next hop ram, which goes as input to stage 3
wire [31:0] dupl_bbr_data_out; //output of duplicate memory basic block ram, which goes as input to stage 4
wire fifo_rd_en;
wire fifo_wr_en;
// fifo wires
wire [31:0] data_fifo_in;
// wire [31:0] data_fifo_out;
//wire empty;
//wire full;
wire [31:0] jump_block;
wire [31:0] fifo_previous_block;
wire [31:0] fifo_previous_nhop;
wire [9:0] data_count;
wire [31:0] previous_bblock;
wire [31:0] previous_nhop;
wire [31:0] carry_bblock;
wire [31:0] carry_nhop;
stage1 st1(
.core_sp_clk (core_sp_clk),
.reset (reset),
.ppu_mem_addr (pp_mem_addr),
.index_addr (bbr_addr),
.fifo_write (fifo_wr_en)
);
stage2 st2(
.core_sp_clk (core_sp_clk),
.reset (reset),
.bblock (bbr_data_out),
.nhop (nhr_data_out),
.previous_bblock (previous_bblock),
.previous_nhop (previous_nhop),
.fifo_read (fifo_rd_en)
);
stage3 st3(
.core_sp_clk (core_sp_clk),
.reset (reset),
.previous_bblock (previous_bblock),
.previous_nhop (previous_nhop),
.fifo_pr_bblock (fifo_previous_block),
.fifo_pr_nhop (fifo_previous_nhop),
.jump_index_addr (dupl_bbr_addr),
.jump_bblock (jump_block)
);
stage4 st4(
.core_sp_clk (core_sp_clk),
.reset (reset),
.dupl_bblock (dupl_bbr_data_out),
.jump_bblock (jump_block),
.pkt_drop (drop_packet)
);
bb_ram bbr(
.clk (core_sp_clk),
.addr (bbr_addr[12:2]),
.data_in (),
.data_out (bbr_data_out),
.we (4'b0000),
.en (1'b1),
.reset (reset)
);
next_hop_ram nhr(
.clk (core_sp_clk),
.addr (bbr_addr[12:2]),
.data_in (),
.data_out (nhr_data_out),
.we (4'b0000),
.en (1'b1),
.reset (reset)
);
bb_ram duplicate_bbr(
.clk (core_sp_clk),
.addr (dupl_bbr_addr[12:2]),
.data_in (),
.data_out (dupl_bbr_data_out),
.we (),
.en (1'b1),
.reset (reset)
);
fifo_generator_v4_4 fifo (
.clk(core_sp_clk),
.din(bbr_data_out), // Bus [31 : 0]
.rd_en(fifo_rd_en),
.rst(reset),
.wr_en(fifo_wr_en),
.data_count(data_count), // Bus [9 : 0]
.dout(fifo_previous_block), // Bus [31 : 0]
.empty(empty),
.full(full),
.valid(valid),
.wr_ack(wr_ack));
fifo_generator_v4_4 nhop_fifo (
.clk(core_sp_clk),
.din(nhr_data_out), // Bus [31 : 0]
.rd_en(fifo_rd_en),
.rst(reset),
.wr_en(fifo_wr_en),
.data_count(), // Bus [9 : 0]
.dout(fifo_previous_nhop), // Bus [31 : 0]
.empty(),
.full(),
.valid(),
.wr_ack());
/* wire [31:0] tmp_data_out;
reg [12:2] tmp_addr;
wire [12:2] tmp_addr_inc;
assign tmp_addr_inc = (tmp_addr == 11'b11111111111) ? 0 : (tmp_addr + 1'b1);
always @(posedge core_sp_clk) begin
if(reset) begin
tmp_addr <= 0;
end else begin
tmp_addr <= tmp_addr_inc;
end
end
bb_ram bbr(
.clk (core_sp_clk),
.addr (tmp_addr),
.data_in (),
.data_out (tmp_data_out),
.we (4'b0000),
.en (1'b1),
.reset (reset)
);
*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long INF = 2e9 + 10, MAX = 2100, MOD = 1e9 + 7, MAXL = 25; void OUT(long double o, int x) { cout << fixed << setprecision(x) << o; return; } long long dp[MAX][MAX], ra[MAX], a[MAX], re[200000], w[MAX]; vector<int> v[MAX]; pair<long long, long long> c[MAX]; set<int> st; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, t; cin >> n >> m >> t; for (int i = 1; i <= m; i++) { int l, r; cin >> l >> r; for (int j = l + 1; j <= r; j++) ra[j] = 1; } for (int i = 1; i <= t; i++) { cin >> c[i].first >> c[i].second; st.insert(c[i].second); } int cnt = 0; for (int i = 1; i <= 2000; i++) w[i] = INF; for (int u : st) { re[u] = ++cnt; w[cnt] = u; } for (int i = 1; i <= t; i++) v[c[i].first].push_back(re[c[i].second]); for (int i = 1; i <= 2000; i++) dp[0][i] = INF; for (int u : v[0]) dp[0][u] = 0; for (int i = 1; i <= n; i++) { long long mi = INF; for (int j = 1; j <= 2000; j++) mi = min(mi, dp[i - 1][j] + w[j]); if (!ra[i]) mi = min(mi, dp[i - 1][0]); dp[i][0] = mi; for (int j = 1; j <= 2000; j++) dp[i][j] = dp[i - 1][j] + w[j]; for (int u : v[i]) dp[i][u] = min(dp[i][u], mi); } long long ans = INF; for (int i = 0; i <= 2000; i++) ans = min(ans, dp[n][i]); if (ans < INF) cout << ans; else cout << -1; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_rptr_vddcom.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_rptr_vddcom(vdd18,vdd_com);
input vdd18;
output vdd_com;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult32u (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 32;
parameter INPUT2_WIDTH = 32;
input enable;
input clock;
input [INPUT1_WIDTH - 1 : 0] dataa;
input [INPUT2_WIDTH - 1 : 0] datab;
output reg[31:0] result;
wire [INPUT1_WIDTH + INPUT2_WIDTH - 1 : 0] sub_wire0;
lpm_mult lpm_mult_component (
.clock (clock),
.datab (datab),
.clken (enable),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = INPUT1_WIDTH,
lpm_mult_component.lpm_widthb = INPUT2_WIDTH,
lpm_mult_component.lpm_widthp = INPUT1_WIDTH + INPUT2_WIDTH;
always@(posedge clock)
begin
if (enable)
result <= {0, sub_wire0[INPUT1_WIDTH + INPUT2_WIDTH - 1 : 0]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { long long x, y; } A[100005]; int pos1[100005], pos2[100005], pos3[100005], pos4[100005]; int cmp1(int a, int b) { return A[a].x < A[b].x; } int cmp2(int a, int b) { return A[a].x > A[b].x; } int cmp3(int a, int b) { return A[a].y < A[b].y; } int cmp4(int a, int b) { return A[a].y > A[b].y; } int mark[100005]; int main() { int i, n, k, p1, p2, p3, p4; long long x1, x2, y1, y2; scanf( %d%d , &n, &k); for (i = 1; i <= n; ++i) { scanf( %lld%lld%lld%lld , &x1, &y1, &x2, &y2); A[i].x = x1 + x2; A[i].y = y1 + y2; pos1[i] = pos2[i] = pos3[i] = pos4[i] = i; } sort(pos1 + 1, pos1 + n + 1, cmp1); sort(pos2 + 1, pos2 + n + 1, cmp2); sort(pos3 + 1, pos3 + n + 1, cmp3); sort(pos4 + 1, pos4 + n + 1, cmp4); int now = 0, tot; long long ans = 1LL << 62; for (p1 = 0; p1 <= k; ++p1) { for (p2 = 0; p2 <= k; ++p2) { for (p3 = 0; p3 <= k; ++p3) { for (p4 = 0; p4 <= k; ++p4) { now++; tot = 0; for (i = 1; i <= p1; ++i) if (mark[pos1[i]] != now) mark[pos1[i]] = now, tot++; for (i = 1; i <= p2; ++i) if (mark[pos2[i]] != now) mark[pos2[i]] = now, tot++; for (i = 1; i <= p3; ++i) if (mark[pos3[i]] != now) mark[pos3[i]] = now, tot++; for (i = 1; i <= p4; ++i) if (mark[pos4[i]] != now) mark[pos4[i]] = now, tot++; if (tot != k) continue; long long max_x = -0x7fffffff, min_x = 0x7fffffff, max_y = -0x7fffffff, min_y = 0x7fffffff; for (i = 1; i <= n; ++i) if (mark[i] != now) { max_x = (max_x > A[i].x ? max_x : A[i].x); min_x = (min_x > A[i].x ? A[i].x : min_x); max_y = (max_y > A[i].y ? max_y : A[i].y); min_y = (min_y > A[i].y ? A[i].y : min_y); } long long x = max_x - min_x, y = max_y - min_y; x = (2LL > x ? 2LL : x); y = (2LL > y ? 2LL : y); ans = (ans > x * y ? x * y : ans); } } } } printf( %lld n , ans / 4); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 5; long long v[MAX]; long long GCD(long long a, long long b) { if (!b) return a; if (!a) return b; return GCD(b, a % b); } int main() { long long mx = 0; long long n; cin >> n; for (int i = 1; i <= n; i++) { cin >> v[i]; mx = max(v[i], mx); } long long G = 0; for (int i = 1; i <= n; i++) { G = GCD(mx - v[i], G); } long long ans1 = 0; for (int i = 1; i <= n; i++) { ans1 += (mx - v[i]) / G; } cout << ans1 << << G << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, row, column; int a[5005]; int cnt[1005]; int main() { int i, j, k, l; int x, y; int tc, t; int res = 0; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); cnt[a[i]]++; } j = *(max_element(cnt, cnt + 1001)); if (j > (n + 1) / 2) puts( NO ); else puts( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; using vi = vector<long long int>; using vvi = vector<vi>; using vb = vector<bool>; using vc = vector<char>; using vs = vector<string>; using vld = vector<long double>; using pii = pair<long long int, long long int>; using psi = pair<string, long long int>; using pci = pair<char, long long int>; using vpii = vector<pii>; long long int mod = 1e9 + 7; long long int const maxn = 2e5 + 5; long long int const inf = 1e18; long long int add(long long int a, long long int b) { return ((a % mod) + (b % mod)) % mod; } long long int mul(long long int a, long long int b) { return ((a % mod) * (b % mod)) % mod; } long long int powm(long long int x, long long int n, long long int M) { long long int result = 1; while (n > 0) { if (n % 2 == 1) result = (result * x) % M; x = (x * x) % M; n = n / 2; } return result; } long long int modinverse(long long int a, long long int m) { return powm(a, m - 2, m); } bool prime(long long int x) { if (x <= 1) return false; for (int i = 2; i <= sqrt(x); i++) if (x % i == 0) return false; return true; } long long int divisor(long long int x) { long long int cnt = 0; for (int i = 1; i <= sqrt(x); i++) { if (x % i == 0) { if (i != x / i) cnt += 2; else cnt += 1; } } return cnt; } vector<long long int> sieve(long long int n) { bool prim[n + 1]; memset(prim, true, sizeof(prim)); for (long long int p = 2; p * p <= n; p++) { if (prim[p] == true) { for (int i = p * p; i <= n; i += p) prim[i] = false; } } vector<long long int> v; for (int i = 2; i <= n; i++) if (prim[i]) v.push_back(i); return v; } vvi adj(maxn); vb vis(maxn, false); long long int x, y; void dfs(long long int u) { if (vis[u] == true) return; vis[u] = true; if (x == -1 and y == -1) { x = u; y = u; } x = min(x, u); y = max(y, u); for (auto v : adj[u]) { if (!vis[v]) { dfs(v); } } } int main() { int t; t = 1; while (t--) { long long int n, m; cin >> n >> m; vpii ans; for (long long int i = 0; i < m; i++) { long long int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } for (long long int i = 1; i <= n; i++) { if (!vis[i]) { x = -1; y = -1; dfs(i); ans.push_back({x, y}); } } sort(ans.begin(), ans.end()); long long int cnt = 0; for (long long int i = 1; i <= (long long int)ans.size() - 1; i++) { if (ans[i - 1].second >= ans[i].first) { cnt++; ans[i].second = max(ans[i - 1].second, ans[i].second); } } cout << cnt << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const long long mo = 1e9 + 7; const long long inf = 1e9; const long long Inf = 1e18; long long w[N], a[N]; int x[N], y[N]; int main() { int n, m, k; scanf( %d%d%d , &n, &k, &m); for (int i = (1); i <= (n); ++i) scanf( %lld , &w[i]); sort(w + 1, w + n + 1); for (int i = (1); i <= (m); ++i) w[i] += w[i - 1], a[i] = w[i]; for (int i = (1); i <= (k); ++i) scanf( %d%d , &x[i], &y[i]); for (int i = (1); i <= (m); ++i) for (int j = (1); j <= (k); ++j) if (x[j] <= i) a[i] = min(a[i - x[j]] + w[i] - w[i - x[j] + y[j]], a[i]); printf( %lld n , a[m]); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_s_no_pg/sky130_fd_sc_hs__u_df_p_s_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dfstp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_BEHAVIORAL_PP_V |
/**
* bsg_id_pool.v
*
* This module maintains of a pool of IDs, and supports allocation and deallocation of these IDs.
*
*/
`include "bsg_defines.v"
module bsg_id_pool
#(parameter `BSG_INV_PARAM(els_p)
, parameter id_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input clk_i,
input reset_i
// next available id
, output logic [id_width_lp-1:0] alloc_id_o
, output logic alloc_v_o
, input alloc_yumi_i
// id to return
, input dealloc_v_i
, input [id_width_lp-1:0] dealloc_id_i
);
// keeps track of which id has been allocated.
logic [els_p-1:0] allocated_r;
// next id to dealloc
logic [els_p-1:0] dealloc_decode;
bsg_decode_with_v #(
.num_out_p(els_p)
) d1 (
.i(dealloc_id_i)
,.v_i(dealloc_v_i)
,.o(dealloc_decode)
);
// find the next available id.
logic [id_width_lp-1:0] alloc_id_lo;
logic alloc_v_lo;
logic [els_p-1:0] one_hot_out;
// We use this v_o instead of the v_o of bsg_encode_one_hot
// because it has better critical path
bsg_priority_encode_one_hot_out #(
.width_p(els_p)
,.lo_to_hi_p(1)
) pe0 (
.i(~allocated_r | dealloc_decode)
,.o(one_hot_out)
,.v_o(alloc_v_lo)
);
bsg_encode_one_hot #(
.width_p(els_p)
,.lo_to_hi_p(1)
) enc0 (
.i(one_hot_out)
,.addr_o(alloc_id_lo)
,.v_o()
);
assign alloc_id_o = alloc_id_lo;
assign alloc_v_o = alloc_v_lo;
// next id to alloc
wire [els_p-1:0] alloc_decode = one_hot_out & {els_p{alloc_yumi_i}};
// Immediately allocating the deallocated id is allowed.
bsg_dff_reset_set_clear #(
.width_p(els_p)
) dff_alloc0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.set_i(alloc_decode)
,.clear_i(dealloc_decode)
,.data_o(allocated_r)
);
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (dealloc_v_i) begin
assert(allocated_r[dealloc_id_i]) else $error("Cannot deallocate an id that hasn't been allocated.");
assert(dealloc_id_i < els_p) else $error("Cannot deallocate an id that is outside the range.");
end
if (alloc_yumi_i)
assert(alloc_v_o) else $error("Handshaking error. alloc_yumi_i raised without alloc_v_o.");
if (alloc_yumi_i & dealloc_v_i & (alloc_id_o == dealloc_id_i))
assert(allocated_r[dealloc_id_i]) else $error("Cannot immediately dellocate an allocated id.");
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_id_pool)
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; const long long int MOD = 1000000007; const long long int MAXN = 100005; long long int k, dp[MAXN]; long long int recurse(long long int n) { if (n == 0) return 1; if (dp[n] != -1) return dp[n]; long long int ans = 0; if (n >= k) { ans = (ans + recurse(n - k)) % MOD; } if (n > 0) { ans = (ans + recurse(n - 1)) % MOD; } return (dp[n] = ans); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t >> k; long long int a, b; memset(dp, -1, sizeof(dp)); dp[0] = 0; for (long long int i = 1; i < 100001; ++i) { dp[i] = recurse(i); } for (long long int i = 1; i < 100001; ++i) { dp[i] = (dp[i] + dp[i - 1]) % MOD; } while (t--) { cin >> a >> b; cout << ((MOD + dp[b] - dp[a - 1])) % MOD << endl; } return 0; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn transaction asynchronous fifo.
*
*/
module rcn_fifo_async
(
input rst_in,
input clk_in,
input clk_out,
input [68:0] rcn_in,
input push,
output full,
output [68:0] rcn_out,
input pop,
output empty
);
parameter DEPTH = 16; // max 64 (can hold DEPTH-1 before full)
reg [1:0] cross_in;
reg [5:0] head_in;
reg [5:0] head_snapshot;
reg [5:0] tail_in;
reg [1:0] cross_out;
reg [5:0] head_out;
reg [5:0] tail_out;
reg [5:0] tail_snapshot;
always @ (posedge clk_in)
cross_in <= cross_out;
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
cross_out <= 2'b00;
else
case (cross_in)
2'b00: cross_out <= 2'b01;
2'b01: cross_out <= 2'b11;
2'b11: cross_out <= 2'b10;
default: cross_out <= 2'b00;
endcase
wire [5:0] head_in_next = (head_in == (DEPTH - 1)) ? 6'd0 : head_in + 6'd1;
wire fifo_full = (head_in_next == tail_in);
always @ (posedge clk_in or posedge rst_in)
if (rst_in)
begin
head_in <= 6'd0;
head_snapshot <= 6'd0;
tail_in <= 6'd0;
end
else
begin
if (push)
head_in <= head_in_next;
case (cross_in)
2'b01: head_snapshot <= head_in;
2'b10: tail_in <= tail_snapshot;
endcase
end
wire [5:0] tail_out_next = (tail_out == (DEPTH - 1)) ? 6'd0 : tail_out + 6'd1;
wire fifo_empty = (tail_out == head_out);
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
begin
head_out <= 6'd0;
tail_out <= 6'd0;
tail_snapshot <= 6'd0;
end
else
begin
if (pop)
tail_out <= tail_out_next;
case (cross_out)
2'b01: tail_snapshot <= tail_out;
2'b10: head_out <= head_snapshot;
endcase
end
reg [67:0] fifo[(DEPTH - 1):0];
always @ (posedge clk_in)
if (push)
fifo[head_in] <= rcn_in[67:0];
assign full = fifo_full;
assign empty = fifo_empty;
assign rcn_out = {!fifo_empty, fifo[tail_out]};
endmodule
|
#include <iostream> #include <vector> #include <cstring> #include <algorithm> #include <cassert> #include <deque> #include <map> #include <queue> #include <climits> #include <set> #include <stack> #include <cmath> #include <array> #include <unordered_map> #include <unordered_set> using namespace std; #define ll long long #define MAX 100000 #define MAX1 10000 #define MAX2 100000 #define inf 1000000000 #define eps 1e-12 #define MOD 1000000007 int main() { ios_base::sync_with_stdio(0); cin.tie(0); #ifndef ONLINE_JUDGE freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); #endif int t; cin >> t; while (t-- > 00) { int n; cin >> n; int a[n + 5], i; bool is = true; for (i = 1; i <= n; ++i) { cin >> a[i]; is &= a[i] == i; } if (is) { cout << 0 << n ; continue; } cout << (a[1] == 1 or a[n] == n ? 1 : (a[1] == n and a[n] == 1) ? 3 : 2) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (i % 2 == 1) { cout << # ; } else { if ((i / 2) % 2 == 0) { if (j == 1) { cout << # ; } else { cout << . ; } } else { if (j == m) { cout << # ; } else { cout << . ; } } } } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; struct Node { int l, r; pair<int, int> v; int mid() { return (l + r) >> 1; } }; struct HNode { int m, p; long long x, y, r, d; bool operator<(const HNode &cur) const { return d < cur.d; } }; Node tree[4 * 250005]; HNode hook[250005]; int n; vector<int> has; void push_up(int pos) { tree[pos].v = min(tree[pos << 1].v, tree[pos << 1 | 1].v); } void build(int pos, int l, int r) { tree[pos].l = l; tree[pos].r = r; if (l == r) { tree[pos].v = make_pair(hook[l].m, l); return; } int mid = tree[pos].mid(); build(pos << 1, l, mid); build(pos << 1 | 1, mid + 1, r); push_up(pos); } void update(int pos, int idx, int mass) { if (tree[pos].l == tree[pos].r) { tree[pos].v.first = mass; return; } int mid = tree[pos].mid(); if (idx <= mid) update(pos << 1, idx, mass); else update(pos << 1 | 1, idx, mass); push_up(pos); } pair<int, int> query(int pos, int l, int r) { if (l <= tree[pos].l && tree[pos].r <= r) return tree[pos].v; int mid = tree[pos].mid(); pair<int, int> ret = make_pair(0x3fffffff, 0x3fffffff); if (l <= mid) ret = min(ret, query(pos << 1, l, r)); if (r > mid) ret = min(ret, query(pos << 1 | 1, l, r)); return ret; } int bifind(long long v) { int l = 1, r = n, mid; if (hook[r].d <= v) return r; if (hook[l].d > v) return -1; while (l + 1 < r) { mid = (l + r) >> 1; if (hook[mid].d <= v) l = mid; else r = mid; } return l; } int main() { int i, j, k; while (scanf( %I64d%I64d%d%I64d%d , &hook[0].x, &hook[0].y, &hook[0].p, &hook[0].r, &n) != EOF) { for (i = 1; i <= n; i++) scanf( %I64d%I64d%d%d%I64d , &hook[i].x, &hook[i].y, &hook[i].m, &hook[i].p, &hook[i].r); for (i = 0; i <= n; i++) { hook[i].r *= hook[i].r; hook[i].d = (hook[0].x - hook[i].x) * (hook[0].x - hook[i].x) + (hook[0].y - hook[i].y) * (hook[0].y - hook[i].y); } sort(hook + 1, hook + 1 + n); has.clear(); has.push_back(0); build(1, 1, n); for (i = 0; i < has.size(); i++) { int rs = bifind(hook[has[i]].r); while (rs != -1) { pair<int, int> cur = query(1, 1, rs); if (cur.first <= hook[has[i]].p) { update(1, cur.second, 0x3fffffff); has.push_back(cur.second); } else break; } } printf( %d n , has.size() - 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; int n, m, q, a[N][N], op, x, y, R[N][N], L[N][N], U[N][N], D[N][N]; void update() { if (a[x][y]) { a[x][y] = 0; D[x][y] = U[x][y] = R[x][y] = L[x][y] = 0; for (int i = x - 1; i >= 1 && a[i][y]; --i) D[i][y] = x - i; for (int i = x + 1; i <= n && a[i][y]; ++i) U[i][y] = i - x; for (int j = y - 1; j >= 1 && a[x][j]; --j) R[x][j] = y - j; for (int j = y + 1; j <= m && a[x][j]; ++j) L[x][j] = j - y; } else { a[x][y] = 1; D[x][y] = 1 + D[x + 1][y]; U[x][y] = 1 + U[x - 1][y]; L[x][y] = 1 + L[x][y - 1]; R[x][y] = 1 + R[x][y + 1]; int i, j; for (i = x - 1; i >= 1 && a[i][y]; --i) D[i][y] = x - i + D[x][y]; for (i = x + 1; i <= n && a[i][y]; ++i) U[i][y] = i - x + U[x][y]; for (j = y - 1; j >= 1 && a[x][j]; --j) R[x][j] = y - j + R[x][y]; for (j = y + 1; j <= m && a[x][j]; ++j) L[x][j] = j - y + L[x][y]; } } int solve() { int ret = 0; int u, d, l, r, w; u = d = x; w = N; while (u >= 1 || d <= n) { w = min(w, max(R[u][y], R[d][y])); for (; u >= 1 && R[u][y] >= w; --u) ; for (; d <= n && R[d][y] >= w; ++d) ; ret = max(ret, (d - u - 1) * w); } u = d = x; w = N; while (u >= 1 || d <= n) { w = min(w, max(L[u][y], L[d][y])); for (; u >= 1 && L[u][y] >= w; --u) ; for (; d <= n && L[d][y] >= w; ++d) ; ret = max(ret, (d - u - 1) * w); } l = r = y; w = N; while (l >= 1 || r <= m) { w = min(w, max(D[x][l], D[x][r])); for (; l >= 1 && D[x][l] >= w; --l) ; for (; r <= m && D[x][r] >= w; ++r) ; ret = max(ret, (r - l - 1) * w); } l = r = y; w = N; while (l >= 1 || r <= m) { w = min(w, max(U[x][l], U[x][r])); for (; l >= 1 && U[x][l] >= w; --l) ; for (; r <= m && U[x][r] >= w; ++r) ; ret = max(ret, (r - l - 1) * w); } return ret; } void init() { int l, r, u, d; for (int i = 1; i <= n; ++i) { for (r = 1; r <= m && a[i][r] == 0; ++r) R[i][r] = 0; l = r; while (l <= m) { for (; r <= m && a[i][r]; ++r) ; for (; l <= r; ++l) R[i][l] = r - l; ++r; } for (l = m; l >= 1 && a[i][l] == 0; --l) L[i][l] = 0; r = l; while (r >= 1) { for (; l >= 1 && a[i][l]; --l) ; for (; r >= l; --r) L[i][r] = r - l; --l; } } for (int j = 1; j <= m; ++j) { for (d = 1; d <= n && a[d][j] == 0; ++d) D[d][j] = 0; u = d; while (u <= n) { for (; d <= n && a[d][j]; ++d) ; for (; u <= d; ++u) D[u][j] = d - u; ++d; } for (u = n; u >= 1 && a[u][j] == 0; --u) U[u][j] = 0; d = u; while (d >= 1) { for (; u >= 1 && a[u][j]; --u) ; for (; d >= u; --d) U[d][j] = d - u; --u; } } } int main() { cin >> n >> m >> q; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { scanf( %d , &a[i][j]); } } init(); while (q--) { scanf( %d%d%d , &op, &x, &y); if (op == 1) update(); else printf( %d n , solve()); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFSTP_PP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n; cin >> n; set<int> v; int a; for (int i = 0; i < n; ++i) { cin >> a; v.insert(a); } v.erase(0); cout << v.size(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_1_V
`define SKY130_FD_SC_HS__NAND4B_1_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4b_1 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4b_1 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_1_V
|
#include <bits/stdc++.h> using namespace std; long long mod = (long long)1000000007; int M, K; int par[100000 + 5]; vector<int> adj[100000 + 5]; long long dp[100000 + 5][11][3]; struct bin_tree_type { int le; int ri; }; bin_tree_type tree[100000 + 5]; long long exp(long long ret, int pow) { if (pow == 0) { return 1; } long long sav = 1; while (pow ^ 1) { if (pow & 1) { sav *= ret; sav %= mod; } pow >>= 1; ret *= ret; ret %= mod; } ret *= sav; ret %= mod; return ret; } long long inv(long long inp) { return exp(inp, mod - 2); } void dfs_lcrs(int nod, int pt) { int lastchild = -1; par[nod] = pt; for (int ke : adj[nod]) { if (ke == pt) { continue; } if (lastchild == -1) { tree[nod].le = ke; } else { tree[lastchild].ri = ke; } dfs_lcrs(ke, nod); lastchild = ke; } } long long DP(int nod, int rem, int status) { if (nod == 0) { if (rem == 0) { return 1; } else { return 0; } } long long &ret = dp[nod][rem][status]; if (ret >= 0) { return ret; } ret = 0; if (rem && status != 2) { if (status == 1) { long long sumc = 0; for (int i = 0; i <= rem - 1; i++) { sumc += DP(tree[nod].le, i, 2) * DP(tree[nod].ri, rem - 1 - i, 1); sumc %= mod; } ret += sumc; } else { long long mult; if (nod != 1) { mult = ((long long)(K - 1) * inv(M - 1)) % mod; } else { mult = 1; } long long sumc = 0; for (int i = 0; i <= rem - 1; i++) { sumc += DP(tree[nod].le, i, 2) * DP(tree[nod].ri, rem - 1 - i, 1); sumc %= mod; } sumc *= mult; sumc %= mod; ret += sumc; } } if (status == 0) { long long mult = M - 1; long long sumc = 0; for (int i = 0; i <= rem; i++) { sumc += DP(tree[nod].le, i, 0) * DP(tree[nod].ri, rem - i, 0); sumc %= mod; } sumc *= mult; sumc %= mod; ret += sumc; } else if (status == 1) { long long mult = M - 1; long long sumc = 0; for (int i = 0; i <= rem; i++) { sumc += DP(tree[nod].le, i, 0) * DP(tree[nod].ri, rem - i, 1); sumc %= mod; } sumc *= mult; sumc %= mod; ret += sumc; } else if (status == 2) { long long mult = K - 1; long long sumc = 0; for (int i = 0; i <= rem; i++) { sumc += DP(tree[nod].le, i, 1) * DP(tree[nod].ri, rem - i, 2); sumc %= mod; } sumc *= mult; sumc %= mod; ret += sumc; } return ret; } int main() { memset(dp, -1, sizeof(dp)); int N, a, b, X; long long has = 0; scanf( %d %d , &N, &M); int edge = N - 1; while (edge--) { scanf( %d %d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } scanf( %d %d , &K, &X); if (K == 1 && N > 1) { printf( %lld n , exp(M - 1, N)); return 0; } dfs_lcrs(1, 1); for (int i = X; i >= 0; i--) { has += DP(1, i, 0); has %= mod; } printf( %lld n , has); } |
/* == HW1 P11 & P12 == */
/* 11: Develope a small set of test patterns that will (1) test a half-adder
* circuit, (2) test a full-adder circuit, (3) exahausively test a 4-bit ripple
* carry adder, and (4) test a 16 bit ripple carry adder by verifying that the
* conectivity between the 4-bit slices are connected correctly, given that the
* 4-bit slices themselves have been verified
*/
/* 12: Develop and exercise a testbench (including a test plan) to verify
* a gate-level model of a full adder
*/
/* For problem 11 & 12, please develop the verilog code for a 4 bit ripple
* carry adder first and verify it by simulation. Then develop the rest of the
* code to answer question 11 and 12
*/
module half_adder(output S, C, input A, B);
xor sum(S,A,B);
and carry(C,A,B);
endmodule
module full_adder(output S, Cout, input A,B,Cin);
wire s1, c1, c2;
half_adder ha1(s1,c1, A ,B ),
ha2(S ,c2, s1,Cin);
or carry(Cout, c1,c2);
endmodule
module r4_adder(output [3:0]S, output Cout, input [3:0]A, B, input Cin);
wire c1, c2, c3;
full_adder fa1(S[0], c1, A[0], B[0], Cin),
fa2(S[1], c2, A[1], B[1], c1),
fa3(S[2], c3, A[2], B[2], c2),
fa4(S[3], Cout, A[3], B[3], c3);
endmodule
module r16_adder(output [15:0]S, output Cout, input [15:0] A, B, input Cin);
wire c1, c2, c3;
r4_adder a1(S[ 3: 0], c1, A[ 3: 0], B[ 3: 0], Cin),
a2(S[ 7: 4], c2, A[ 7: 4], B[ 7: 4], c1),
a3(S[11: 8], c3, A[11: 8], B[11: 8], c2),
a4(S[15:12], Cout, A[15:12], B[15:12], c3);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<int, long long> mp; const int maxn = 1e6 + 10; char str[maxn]; int num[30]; int main() { int n; scanf( %d , &n); while (n--) { scanf( %s , str); memset(num, 0, sizeof num); int len = strlen(str); for (int i = 0; i < len; i++) { num[str[i] - a ]++; } int state = 0; for (int i = 0; i < 26; i++) { if (num[i] & 1) { state |= (1 << i); } } mp[state]++; } long long ans = 0; for (map<int, long long>::iterator it = mp.begin(); it != mp.end(); it++) { ans += (it->second) * ((it->second) - 1) / 2; int state = it->first; for (int i = 0; i < 26; i++) { if ((state >> i) & 1) { int tmp = (1 << i) ^ (state); ans += mp[tmp] * mp[state]; } } } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_2_V
`define SKY130_FD_SC_HDLL__SDFXTP_2_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_2 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_2_V
|
// This is a 4 to 1 mux that inputs from the 4 cpus and outputs to the monitors
// Author: Kekai Hu. Mar 1, 2013
module mux_41(
input [1:0] sel,
input [3:0] four_bit_hash_0,
input new_inst_signal_0,
input processor_reset_seq_0,
input sp_pkt_done_0,
input sp_interrupt_wire_0,
input [3:0] four_bit_hash_1,
input new_inst_signal_1,
input processor_reset_seq_1,
input sp_pkt_done_1,
input sp_interrupt_wire_1,
input [3:0] four_bit_hash_2,
input new_inst_signal_2,
input processor_reset_seq_2,
input sp_pkt_done_2,
input sp_interrupt_wire_2,
input [3:0] four_bit_hash_3,
input new_inst_signal_3,
input processor_reset_seq_3,
input sp_pkt_done_3,
input sp_interrupt_wire_3,
output [3:0] four_bit_hash_out,
output new_inst_signal_out,
output processor_reset_seq_out,
output sp_pkt_done_out,
output sp_interrupt_wire_out
);
reg [3:0] four_bit_hash_out_reg;
reg new_inst_signal_out_reg;
reg processor_reset_seq_out_reg;
reg sp_pkt_done_out_reg;
reg sp_interrupt_wire_out_reg;
always @(*) begin
case (sel)
2'b00: begin
four_bit_hash_out_reg = four_bit_hash_0;
new_inst_signal_out_reg = new_inst_signal_0;
processor_reset_seq_out_reg = processor_reset_seq_0;
sp_pkt_done_out_reg = sp_pkt_done_0;
sp_interrupt_wire_out_reg = sp_interrupt_wire_0;
end
2'b01: begin
four_bit_hash_out_reg = four_bit_hash_1;
new_inst_signal_out_reg = new_inst_signal_1;
processor_reset_seq_out_reg = processor_reset_seq_1;
sp_pkt_done_out_reg = sp_pkt_done_1;
sp_interrupt_wire_out_reg = sp_interrupt_wire_1;
end
2'b10:begin
four_bit_hash_out_reg = four_bit_hash_2;
new_inst_signal_out_reg = new_inst_signal_2;
processor_reset_seq_out_reg = processor_reset_seq_2;
sp_pkt_done_out_reg = sp_pkt_done_2;
sp_interrupt_wire_out_reg = sp_interrupt_wire_2;
end
2'b11:begin
four_bit_hash_out_reg = four_bit_hash_3;
new_inst_signal_out_reg = new_inst_signal_3;
processor_reset_seq_out_reg = processor_reset_seq_3;
sp_pkt_done_out_reg = sp_pkt_done_3;
sp_interrupt_wire_out_reg = sp_interrupt_wire_3;
end
endcase
end
assign four_bit_hash_out = four_bit_hash_out_reg;
assign new_inst_signal_out = new_inst_signal_out_reg;
assign processor_reset_seq_out = processor_reset_seq_out_reg;
assign sp_pkt_done_out = sp_pkt_done_out_reg;
assign sp_interrupt_wire_out = sp_interrupt_wire_out_reg;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_burst #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
input flush,
output reg busy,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
output reg pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-5-1:0] burst_addr, /* in 256-bit words */
/* 16-bit granularity selection that needs to be expanded
* to 8-bit granularity selection to drive the FML lines.
*/
output reg [15:0] burst_sel,
output reg [255:0] burst_do
);
wire burst_hit = dadr[fml_depth-1-1:4] == burst_addr;
/* Always memorize input in case we have to ack a cycle we cannot immediately handle */
reg [15:0] color_r;
reg [fml_depth-1-1:0] dadr_r;
always @(posedge sys_clk) begin
if(pipe_stb_i & pipe_ack_o) begin
color_r <= color;
dadr_r <= dadr;
end
end
/* Write to the burst storage registers */
reg clear_en;
reg write_en;
reg use_memorized;
wire [15:0] color_mux = use_memorized ? color_r : color;
wire [fml_depth-1-1:0] dadr_mux = use_memorized ? dadr_r : dadr;
always @(posedge sys_clk) begin
if(sys_rst)
burst_sel = 16'd0;
else begin
if(clear_en)
burst_sel = 16'd0;
if(write_en) begin
burst_addr = dadr_mux[fml_depth-1-1:4]; /* update tag */
case(dadr_mux[3:0]) /* unmask */
4'd00: burst_sel = burst_sel | 16'h8000;
4'd01: burst_sel = burst_sel | 16'h4000;
4'd02: burst_sel = burst_sel | 16'h2000;
4'd03: burst_sel = burst_sel | 16'h1000;
4'd04: burst_sel = burst_sel | 16'h0800;
4'd05: burst_sel = burst_sel | 16'h0400;
4'd06: burst_sel = burst_sel | 16'h0200;
4'd07: burst_sel = burst_sel | 16'h0100;
4'd08: burst_sel = burst_sel | 16'h0080;
4'd09: burst_sel = burst_sel | 16'h0040;
4'd10: burst_sel = burst_sel | 16'h0020;
4'd11: burst_sel = burst_sel | 16'h0010;
4'd12: burst_sel = burst_sel | 16'h0008;
4'd13: burst_sel = burst_sel | 16'h0004;
4'd14: burst_sel = burst_sel | 16'h0002;
4'd15: burst_sel = burst_sel | 16'h0001;
endcase
case(dadr_mux[3:0]) /* register data */
4'd00: burst_do[255:240] = color_mux;
4'd01: burst_do[239:224] = color_mux;
4'd02: burst_do[223:208] = color_mux;
4'd03: burst_do[207:192] = color_mux;
4'd04: burst_do[191:176] = color_mux;
4'd05: burst_do[175:160] = color_mux;
4'd06: burst_do[159:144] = color_mux;
4'd07: burst_do[143:128] = color_mux;
4'd08: burst_do[127:112] = color_mux;
4'd09: burst_do[111: 96] = color_mux;
4'd10: burst_do[ 95: 80] = color_mux;
4'd11: burst_do[ 79: 64] = color_mux;
4'd12: burst_do[ 63: 48] = color_mux;
4'd13: burst_do[ 47: 32] = color_mux;
4'd14: burst_do[ 31: 16] = color_mux;
4'd15: burst_do[ 15: 0] = color_mux;
endcase
end
end
end
wire empty = (burst_sel == 16'd0);
reg state;
reg next_state;
parameter RUNNING = 1'b0;
parameter DOWNSTREAM = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= RUNNING;
else
state <= next_state;
end
/*
* generate pipe_ack_o using an assign statement to work around a bug in CVER
*/
assign pipe_ack_o = (state == RUNNING) & (~flush | empty);
always @(*) begin
next_state = state;
busy = 1'b1;
// CVER WA (see above) pipe_ack_o = 1'b0;
pipe_stb_o = 1'b0;
write_en = 1'b0;
clear_en = 1'b0;
use_memorized = 1'b0;
case(state)
RUNNING: begin
busy = 1'b0;
if(flush & ~empty)
next_state = DOWNSTREAM;
else begin
// CVER WA (see above) pipe_ack_o = 1'b1;
if(pipe_stb_i) begin
if(burst_hit | empty)
write_en = 1'b1;
else
next_state = DOWNSTREAM;
end
end
end
DOWNSTREAM: begin
pipe_stb_o = 1'b1;
use_memorized = 1'b1;
if(pipe_ack_i) begin
clear_en = 1'b1;
write_en = 1'b1;
next_state = RUNNING;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; using ld = long double; using vi = vector<int>; using vll = vector<ll>; using vd = vector<double>; using vvi = vector<vi>; int ctoi(char c) { return c - 0 ; } int slen(string s) { return s.length(); } int vsize(vi a) { return (int)a.size(); } int in() { int x; cin >> x; return x; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int N; cin >> N; vi d(N); for (auto& x : d) cin >> x; int mn = abs(d[N - 1] - d[0]); int a = N - 1, b = 0; for (int i = 1; i < N; i++) { if (abs(d[i] - d[i - 1]) < mn) { mn = abs(d[i] - d[i - 1]); a = i; b = i - 1; } } cout << a + 1 << << b + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 510; const int inf = 0x3f3f3f3f; int n; long long d[maxn][maxn]; int w(int i, int j, int k) { return i * j * k; } int main() { int n; scanf( %d , &n); memset(d, 0x3f, sizeof(d)); for (int i = 1; i <= n; i++) { d[i][i + 2] = w(i, i + 1, i + 2); d[i][i] = 0; d[i][i + 1] = 0; } for (int i = n - 2; i >= 1; i--) { for (int j = i + 2; j <= n; j++) { for (int k = i + 1; k < j; k++) { d[i][j] = min(d[i][j], d[i][k] + d[k][j] + w(i, j, k)); } } } printf( %I64d , d[1][n]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int func1(long long int i) { long long int m = i; return i * (i + 1) * (2 * i + 1) / 6 - (m + m + 2) * i * (i + 1) / 2 + (m + m + 1 + m * m) * i; } long long int func2(long long int x, long long int i) { return x * (i + i * i - i * (i + 1) / 2); } int main() { long long int inp, tem, ans = 0, tem2; cin >> inp; vector<pair<long long int, long long int> > v; bool flag = 0; for (int i = 0; i < 100000000; i++) if (ans > 0) ans += 1; ans = 0; for (long long int i = 1; func1(i) <= inp; i++) { tem = inp - func1(i); if (!tem) { flag = 1; v.push_back(make_pair(i, i)); } else { tem2 = func2(1, i); if (tem % tem2 == 0) v.push_back(make_pair(i, i + tem / tem2)); } } if (!flag) cout << 2 * v.size(); else cout << 2 * v.size() - 1; cout << n ; for (int i = 0; i < v.size(); i++) cout << v[i].first << << v[i].second << n ; int i = v.size() - 1; if (flag) i--; for (; i >= 0; i--) cout << v[i].second << << v[i].first << n ; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_2_V
`define SKY130_FD_SC_LP__A221O_2_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_2_V
|
module peripheral_ultra(clk , rst , d_in , cs , addr , rd , wr, d_out, trigg, echo );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output trigg;
output echo;
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and demux_4
reg enable;
wire [7:0] dout; // distancia
wire done;
//------------------------------------ regs and wires-------------------------------
ultrasonido ultra(.clk(clk), .reset(rst),.d(dout), .trigg(trigg), .ECHO(echo), .ENABLE(enable), .DONE(done));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end //enable
4'h2:begin s = (cs && rd) ? 5'b00010 : 5'b00000 ;end //done
4'h4:begin s = (cs && rd) ? 5'b00100 : 5'b00000 ;end //data
default:begin s=5'b00000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
if (s[0]==1)
begin
enable=1;
end
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
5'b00010: d_out[0]= done;
5'b00100: d_out[0]= dout;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int m, k, d[2000], s[2000], n = 0, big = 0, ans = 0; cin >> m >> k; for (int i = 0; i < m; i++) cin >> d[i]; for (int i = 0; i < m; i++) cin >> s[i]; for (int i = 0; i < m; i++) { n += s[i]; if (s[i] > big) big = s[i]; while (n < d[i]) { n += big; ans += k; } n -= d[i]; ans += d[i]; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string a = , b = , s1, s2; cin >> s1 >> s2; if (s1[0] == X ) a += s1[1]; else if (s1[1] == X ) a += s1[0]; else a += s1; if (s2[1] == X ) a += s2[0]; else if (s2[0] == X ) a += s2[1]; else { a += s2[1]; a += s2[0]; } cin >> s1 >> s2; if (s1[0] == X ) b += s1[1]; else if (s1[1] == X ) b += s1[0]; else b += s1; if (s2[1] == X ) b += s2[0]; else if (s2[0] == X ) b += s2[1]; else { b += s2[1]; b += s2[0]; } if ((a[0] == b[0] && a[2] == b[2]) || (a[1] == b[0] && a[0] == b[2]) || (a[2] == b[0] && a[1] == b[2])) cout << YES ; else cout << NO ; return 0; } |
module tx (
clk,
reset_,
baud,
txdata,
tx_enable,
tx_ready,
tx);
input clk;
input reset_;
input baud; // Baud enable
input [7:0] txdata; // Parallel data to transmit
input tx_enable; // When asserted, txdata is sampled for transmission
output tx_ready; // Asserted when transmit complete (ready for next byte)
output tx; // Serial transmit data
reg tx;
reg [1:0] state;
reg [7:0] txdata_sampled;
reg [2:0] txpos;
// Transmitter states
parameter ST_IDLE = 2'd0;
parameter ST_TXSTART = 2'd1;
parameter ST_TXDATA = 2'd2;
parameter ST_TXSTOP = 2'd3;
assign tx_ready = state == ST_IDLE;
// State machine
always@ (posedge clk or negedge reset_)
if (!reset_)
state <= ST_IDLE;
else if (state == ST_IDLE && tx_enable)
state <= ST_TXSTART;
else if (state == ST_TXSTART && baud)
state <= ST_TXDATA;
else if (state == ST_TXDATA && baud && txpos == 3'd7)
state <= ST_TXSTOP;
else if (state == ST_TXSTOP && baud)
state <= ST_IDLE;
// Serial transmit data
always@ (posedge clk or negedge reset_)
if (!reset_)
tx <= 1'b1;
else if (state == ST_TXSTART && baud)
tx <= 1'b0;
else if (state == ST_TXDATA && baud)
tx <= txdata_sampled[txpos];
else if (state == ST_TXSTOP && baud)
tx <= 1'b1;
// Transmit position (bit of txdata being sent)
always@ (posedge clk or negedge reset_)
if (!reset_)
txpos <= 3'd0;
else if (state == ST_IDLE)
txpos <= 3'd0;
else if (state == ST_TXDATA && baud)
txpos <= txpos + 3'd1;
// Local copy of txdata
always@ (posedge clk or negedge reset_)
if (!reset_)
txdata_sampled <= 8'h0;
else if (tx_enable && tx_ready)
txdata_sampled <= txdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, s; cin >> n >> s; int a[s]; memset(a, 0, sizeof a); for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; a[x - 1] = max(a[x - 1], y); } int t = 0; for (int i = 0; i < s; i++) { t += max(a[s - i - 1] - t, 0); t++; } cout << t << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int b[5000]; int f[5000]; int main() { scanf( %d , &n); for (int i = 0; i < (int)(n); i++) scanf( %d , b + i); for (int i = 0; i < (int)(n); i++) b[i]--; for (int i = 0; i < n; i++) { int c[5000] = {}; pair<int, int> best = make_pair(0, 0); for (int j = i; j < n; j++) { c[b[j]]++; best = max(best, make_pair(c[b[j]], -b[j])); f[-best.second]++; } } for (int i = 0; i < (int)(n); i++) printf( %d , f[i]); puts( ); return 0; } |
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/18/2016
Founction: I2C top module
Note:
****************************************************************************/
module I2C_MASTER(clk,rst_n,sda,scl,RD_EN,WR_EN,receive_status,tx_start,tx_data,tx_complete,bps_start_t,capture_rst
);
input clk;
input rst_n;
input RD_EN;
input WR_EN;
input tx_complete;
input bps_start_t;
input capture_rst;
reg WR,RD;
output scl;
output receive_status;
output tx_start;
output [7:0] tx_data;
wire [7:0] tx_data;
inout sda;
reg scl_clk;
reg receive_status;
reg[7:0] clk_div;
reg[7:0] send_count;
wire[7:0] data;
reg[7:0] data_reg;
reg end_ready;
wire ack;
wire tx_end;
reg[7:0] send_memory[31:0];
reg[7:0] receive_memory[31:0];
check_pin check_pin_instance(
.clk(clk),
.rst_n(rst_n),
.tx_start(tx_start),
.capture_ready((send_count == 10'd32) && RD_EN && end_ready),
.tx_data(tx_data),
.tx_complete(tx_complete),
.tx_end(tx_end),
.bps_start_t(bps_start_t),
.receive_status(receive_status),
.capture_rst(capture_rst)
);
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
end_ready <= 1'b0;
else
end_ready <= tx_end ? 1'b0 : 1'b1;
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
scl_clk <= 1'b0;
clk_div <= 'h0;
send_memory[0] <= 8'd0;
send_memory[1] <= 8'd1;
send_memory[2] <= 8'd2;
send_memory[3] <= 8'd3;
send_memory[4] <= 8'd4;
send_memory[5] <= 8'd5;
send_memory[6] <= 8'd6;
send_memory[7] <= 8'd7;
send_memory[8] <= 8'd8;
send_memory[9] <= 8'd9;
send_memory[10] <= 8'd10;
send_memory[11] <= 8'd11;
send_memory[12] <= 8'd12;
send_memory[13] <= 8'd13;
send_memory[14] <= 8'd14;
send_memory[15] <= 8'd15;
send_memory[16] <= 8'd16;
send_memory[17] <= 8'd17;
send_memory[18] <= 8'd18;
send_memory[19] <= 8'd19;
send_memory[20] <= 8'd20;
send_memory[21] <= 8'd21;
send_memory[22] <= 8'd22;
send_memory[23] <= 8'd23;
send_memory[24] <= 8'd24;
send_memory[25] <= 8'd25;
send_memory[26] <= 8'd26;
send_memory[27] <= 8'd27;
send_memory[28] <= 8'd28;
send_memory[29] <= 8'd29;
send_memory[30] <= 8'd30;
send_memory[31] <= 8'd31;
end
else begin
if(clk_div > 'd200)begin
scl_clk <= ~scl_clk;
clk_div <= 'h0;
end
else
clk_div <= clk_div + 1'b1;
end
end
always @(posedge ack or negedge rst_n)begin
if(!rst_n)begin
send_count <= 'h0;
end
else begin
if((send_count < 10'd32) && (ack))begin
send_count <= send_count + 1'b1;
receive_memory[send_count] <= RD_EN ? data : 8'h0;
end
else begin
send_count <= send_count;
end
end
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
receive_status <= 1'b0;
else
receive_status <=(receive_memory[31]== 31) ? 1'b1 : 1'b0;
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
WR <= 1'b0;
RD <= 1'b0;
data_reg <= 'h0;
end
else begin
if(send_count == 8'd32)begin
WR <= 1'b0;
RD <= 1'b0;
end
else begin
if(RD_EN)
RD <= 1'b1;
else if(WR_EN)begin
WR <= 1'b1;
data_reg <= send_memory[send_count];
end
end
end
end
assign data = WR_EN ? data_reg : 8'hz;
I2C_wr I2C_wr_instance(
.sda(sda),
.scl(scl),
.ack(ack),
.rst_n(rst_n),
.clk(scl_clk),
.WR(WR),
.RD(RD),
.data(data)
);
endmodule |
#include <bits/stdc++.h> using namespace std; long long t = 1; void solve() { long long n, x, y, cnt = 0, p = 1; cin >> n; vector<long long> arr(n + 1), vis(n + 1, 0); vector<vector<long long> > v(n + 1); for (long long i = 0; i < n - 1; i += 1) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } queue<long long> q1, q; for (long long i = 0; i < n; i += 1) { cin >> x; arr[i] = x; q1.push(x); } q.push(1); q1.pop(); while (!q.empty()) { x = q.front(); vector<long long> vv; set<long long> s; cnt = 0; for (long long i = 0; i < int((v[x]).size()); i += 1) { if (vis[v[x][i]] == 0) { cnt++; vv.push_back(v[x][i]); } } vis[q.front()] = 1; q.pop(); for (long long i = p; i < p + cnt; i += 1) { s.insert(arr[i]); q.push(arr[i]); vis[arr[i]] = 1; } for (long long i = 0; i < int((vv).size()); i += 1) { if (((s).find(vv[i]) != (s).end())) { s.erase(vv[i]); } else { cout << No ; return; } } p = p + cnt; } cout << Yes ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); while (t--) solve(); return 0; } |
#include <bits/stdc++.h> const int maxn = 1e5 + 1; int n, m, l = 1; long long a; char s[maxn]; int main() { scanf( %d%d%s , &n, &m, s + 1); for (int i = 1; i <= n; i++) if (s[i] != s[i - 1]) a += n * (m - 1); for (int i = 2; i <= n; i++) if (l == 1 && s[i] != s[i - 1] || l > 1 && s[i] == s[i - 2]) ++l; else if (a -= 1ll * l * (l - 1) >> 1) l = 1 + (s[i] != s[i - 1]); printf( %lld n , a -= 1ll * l * (l - 1) >> 1); return 0; } |
#include <bits/stdc++.h> using namespace std; double DP[2][2510][2510]; double X[2510], Y[2510]; double dis(int a, int b) { return sqrt((X[a] - X[b]) * (X[a] - X[b]) + (Y[a] - Y[b]) * (Y[a] - Y[b])); } int main() { ios::sync_with_stdio(false); memset(DP, 0, sizeof(DP)); int N; cin >> N; for (int i = 0; i < N; i++) cin >> X[i] >> Y[i]; for (int i = 2; i <= N; i++) { for (int s = 0; s < N; s++) { int e = s + i - 2; e %= N; int t; t = (s - 1 + N) % N; DP[0][t][e] = max(DP[0][t][e], DP[0][s][e] + dis(s, t)); t = (e + 1) % N; DP[1][s][t] = max(DP[1][s][t], DP[0][s][e] + dis(s, t)); t = (s - 1 + N) % N; DP[0][t][e] = max(DP[0][t][e], DP[1][s][e] + dis(e, t)); t = (e + 1) % N; DP[1][s][t] = max(DP[1][s][t], DP[1][s][e] + dis(e, t)); } } double res = 0; for (int i = 0; i < N; i++) { int j = (i - 1 + N) % N; res = max(res, DP[0][i][j]); res = max(res, DP[1][i][j]); } cout.precision(20); cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int dir[4][2] = {{0, 1}, {1, 0}, {0, -1}, {-1, 0}}; int ans[505][505]; int col = 1, n, coz = 0; int main() { std::ios::sync_with_stdio(false); scanf( %d , &n); if (n < 3) { printf( -1 ); return 0; } int now_ = 0, cot = n; int x = 1, y = 0; int rest = n * n; while (rest != 9) { for (int i = 1; i <= cot; i++) { coz++; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz; } rest -= cot; col++; if (col % 2 == 0) cot--; now_ = (now_ + 1) % 4; } x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 1; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 2; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 4; now_ = (now_ + 1) % 4; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 5; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 9; now_ = (now_ + 1) % 4; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 6; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 7; now_ = (now_ + 1) % 4; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 8; now_ = (now_ + 1) % 4; x += dir[now_][0]; y += dir[now_][1]; ans[x][y] = coz + 3; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) printf( %d , ans[i][j]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mk = 100005; long long n; vector<long long> g[mk]; long long find(long long A) { if (A == 0) return 0; long long tmp = A & 3; long long R = (find(A / 4) << 2); if (tmp == 0) return R; if (tmp == 1) return (R | 2); if (tmp == 2) return (R | 3); if (tmp == 3) return (R | 1); } void init() { long long test; cin >> test; for (long long i = 1; i <= test; i++) { long long n; cin >> n; long long root = 1; while (root * 4 <= n) root *= 4; n -= (root - 1); long long A = (root | ((n - 1) / 3)); long long B = find(A); long long C = A ^ B; if (n % 3 == 1) cout << A; if (n % 3 == 2) cout << B; if (n % 3 == 0) cout << C; cout << n ; } } signed main() { init(); } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:11:12 05/19/2015
// Design Name: top
// Module Name: E:/mips_pipeline/code/test_top.v
// Project Name: mips_pipeline
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_top;
// Inputs
reg CCLK;
reg [3:0] SW;
reg BTNN;
reg BTNE;
reg BTNS;
reg BTNW;
// Outputs
wire [7:0] LED;
wire LCDE;
wire LCDRS;
wire LCDRW;
wire [3:0] LCDDAT;
// Instantiate the Unit Under Test (UUT)
top uut (
.CCLK(CCLK),
.SW(SW),
.BTNN(BTNN),
.BTNE(BTNE),
.BTNS(BTNS),
.BTNW(BTNW),
.LED(LED),
.LCDE(LCDE),
.LCDRS(LCDRS),
.LCDRW(LCDRW),
.LCDDAT(LCDDAT)
);
initial begin
// Initialize Inputs
CCLK = 0;
SW = 0;
BTNN = 0;
BTNE = 0;
BTNS = 0;
BTNW = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#5 BTNE = 1; #5 BTNE = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; SW[3]=1;#5 BTNN = 1 ;SW[3]=0;#5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
#5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0; #5 BTNN = 1; #5 BTNN = 0;
end
always #1 CCLK=~CCLK;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/09/2015 12:10:35 PM
// Design Name:
// Module Name: BRAM_Matrix
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BRAM_Matrix #(
parameter N = 6,
parameter WIDTH = 16,
parameter M_WIDTH = 2*WIDTH+N-1,
parameter ADDR = 12
)(
// CLOCK
input clk_USR,
input clk_MAT,
// USER MEMORY A
input A_USR_wr,
input [ADDR-1:0] A_USR_addr,
input [N*WIDTH-1:0] A_USR_din,
// USER MEMORY B
input B_USR_wr,
input [ADDR-1:0] B_USR_addr,
input [N*WIDTH-1:0] B_USR_din,
// USER MEMORY C
input C_USR_rd,
input [ADDR-1:0] C_USR_addr,
output [N*M_WIDTH-1:0] C_USR_dout,
// MATRIX MEMORY A
input A_MAT_rd,
input [ADDR-1:0] A_MAT_addr,
output [N*WIDTH-1:0] A_MAT_dout,
// MATRIX MEMORY B
input B_MAT_rd,
input [ADDR-1:0] B_MAT_addr,
output [N*WIDTH-1:0] B_MAT_dout,
// MATRIX MEMORY C
input C_MAT_wr,
input [ADDR-1:0] C_MAT_addr,
input [N*M_WIDTH-1:0] C_MAT_din
);
dpram A_MEM (
.clka (clk_USR),
.wea (A_USR_wr),
.addra (A_USR_addr),
.dina (A_USR_din),
.douta (),
.clkb (clk_MAT),
.web (1'b0),
.addrb (A_MAT_addr),
.dinb (),
.doutb (A_MAT_dout)
);
defparam A_MEM.DATA = N*WIDTH;
defparam A_MEM.ADDR = ADDR;
dpram B_MEM (
.clka (clk_USR),
.wea (B_USR_wr),
.addra (B_USR_addr),
.dina (B_USR_din),
.douta (),
.clkb (clk_MAT),
.web (1'b0),
.addrb (B_MAT_addr),
.dinb (),
.doutb (B_MAT_dout)
);
defparam B_MEM.DATA = N*WIDTH;
defparam B_MEM.ADDR = ADDR;
dpram C_MEM (
.clka (clk_USR),
.wea (1'b0),
.addra (C_USR_addr),
.dina (),
.douta (C_USR_dout),
.clkb (clk_MAT),
.web (C_MAT_wr),
.addrb (C_MAT_addr),
.dinb (C_MAT_din),
.doutb ()
);
defparam C_MEM.DATA = N*M_WIDTH;
defparam C_MEM.ADDR = ADDR;
endmodule
|
module scaler_relay # (
parameter integer C_DATA_WIDTH = 12,
parameter integer C_PASSTHROUGH = 0
) (
input wire clk,
input wire resetn,
input wire s_valid,
input wire [C_DATA_WIDTH-1:0] s_data ,
output wire s_ready,
output wire m_valid,
output wire [C_DATA_WIDTH-1:0] m_data ,
input wire m_ready
);
generate
if (C_PASSTHROUGH) begin
assign m_valid = s_valid;
assign m_data = s_data;
assign s_ready = m_ready;
end
else begin
reg relay_valid[1:0];
reg [C_DATA_WIDTH-1:0] relay_data [1:0];
wire snext;
assign snext = s_valid && s_ready;
assign m_valid = relay_valid[0];
assign m_data = relay_data[0];
wire mneed;
assign mneed = ~relay_valid[0] || m_ready;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
relay_valid[1] <= 0;
end
else if (snext) begin
if (relay_valid[1] || ~mneed) begin
relay_valid[1] <= 1;
relay_data[1] <= s_data;
end
end
else if (mneed) begin
relay_valid[1] <= 0;
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
relay_valid[0] <= 0;
relay_data [0] <= 0;
end
else if (mneed) begin
if (relay_valid[1]) begin
relay_valid[0] <= 1;
relay_data [0] <= relay_data[1];
end
else if (snext) begin
relay_valid[0] <= 1;
relay_data [0] <= s_data;
end
else begin
relay_valid[0] <= 0;
end
end
end
reg r_sready;
assign s_ready = r_sready;
always @ (posedge clk) begin
if (resetn == 1'b0)
r_sready <= 0;
else begin
case ({relay_valid[1], relay_valid[0]})
2'b00, 2'b10:
r_sready <= 1;
2'b01:
r_sready <= (~r_sready || m_ready);
2'b11:
r_sready <= (~r_sready && m_ready);
endcase
end
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; string s; int main() { ios_base::sync_with_stdio(0); cin >> s; vector<int> a; vector<int> b; int n = s.size(); for (int i = 0; i < n; i++) { if (s[i] == l ) a.push_back(i + 1); if (s[i] == r ) b.push_back(i + 1); } for (int i = 0; i < b.size(); i++) cout << b[i] << n ; for (int i = a.size() - 1; i >= 0; i--) cout << a[i] << n ; return 0; } |
//-----------------------------------------------------
// PROYECTO 1 : SD HOST
// Archivo : probador.v
// Descripcion : generador de estimulos para el bloque de datos
// Estudiante : Mario Castresana Avendaño - A41267
//-----------------------------------------------------
module probador(
//señales para DATA_control
output reg CLK,
output reg RESET_L,
output reg writeRead_Regs_DATA,
output reg [3:0] blockCount_Regs_DATA,
output reg multipleData_Regs_DATA,
output reg timeout_Enable_Regs_DATA,
output reg [15:0] timeout_Reg_Regs_DATA,
output reg new_DAT_DMA_DATA,
output reg serial_Ready_Phy_DATA,
output reg timeout_Phy_DATA,
output reg complete_Phy_DATA,
output reg ack_IN_Phy_DATA,
output reg fifo_OK_FIFO_DATA
//señales para DATA_PHYSICAL
);
// Generar CLK
always
begin
#5 CLK= ! CLK;
end
//Generar pruebas
initial begin
//dumps
$dumpfile("testDATA.vcd");
$dumpvars(0,testbench);
// Initialize Inputs
CLK = 0;
new_DAT_DMA_DATA = 0;
serial_Ready_Phy_DATA = 0;
blockCount_Regs_DATA = 4'b1111; //procesar 15 bloques
timeout_Reg_Regs_DATA = 16'd100; //ciclos para timeout
writeRead_Regs_DATA = 1; // Escritura (leer del FIFO para pasar a SD)
multipleData_Regs_DATA = 0; //no es operacion multi trama
fifo_OK_FIFO_DATA = 0; //FIFO en espera
complete_Phy_DATA = 0;
ack_IN_Phy_DATA = 0;
//pulso de RESET_L
#50
RESET_L = 1;
#10
RESET_L = 0;
#30
RESET_L = 1;
//Aqui ya pasa a IDLE
$display("Aqui ya pasa a IDLE");
//pasamos a setting outputs
#50
new_DAT_DMA_DATA = 1;
$display("Aqui ya pasa a SETTING OUTPUTS");
#100
serial_Ready_Phy_DATA = 1;
//pasamos a checkear el FIFO
$display("Aqui ya pasa a Check FIFO");
//nos quedamos 50 ciclos en Check FIFO
#50
fifo_OK_FIFO_DATA = 1;
//pasamos al estado transmit
$display("Aqui ya pasa a transmit");
#50
//esperamos 50 ciclo en transmit y pasamos a ACK
complete_Phy_DATA = 1;
//aqui terminamos la transmicion mandando un ACK out a capa física
//y esperando un ACK in
#30
ack_IN_Phy_DATA = 1;
new_DAT_DMA_DATA = 0;
$display("De vuelta a IDLE");
#200
$display("-----FIN------");
$finish(2);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_2_V
`define SKY130_FD_SC_HS__DFSBP_2_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SET_B
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_2_V
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// Basic RAM wrapper, 1 read 1 write port on common clock.
module ram_block (
clk,
data,
rdaddress,
wraddress,
wren,
q
);
parameter DAT_WIDTH = 36;
parameter ADDR_WIDTH = 7;
input clk;
input [DAT_WIDTH-1:0] data;
input [ADDR_WIDTH-1:0] rdaddress;
input [ADDR_WIDTH-1:0] wraddress;
input wren;
output [DAT_WIDTH-1:0] q;
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clk),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DAT_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = (1<<ADDR_WIDTH),
altsyncram_component.numwords_b = (1<<ADDR_WIDTH),
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "AUTO",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DAT_WIDTH,
altsyncram_component.width_b = DAT_WIDTH,
altsyncram_component.width_byteena_a = 1;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; enum { MOD0 = 1000000000, MOD7 = 1000000007, MOD9 = 1000000009 }; template <typename T> class FenwickTree { vector<T> tree; public: FenwickTree<T>() : tree() {} FenwickTree<T>(vector<T> a) : tree(a.size() + 1, 0) { for (size_t i = 0; i < a.size(); ++i) { add(i, a[i]); } } size_t size() const { return tree.size() ? tree.size() - 1 : 0; } void add(size_t index, T value) { for (; ++index <= size(); index |= index - 1) { tree[index] += value; } } T sum(size_t right) { T ret{}; for (; right; right &= right - 1) { ret += tree[right]; } return ret; } T sum(size_t left, size_t right) { return sum(right) - sum(left); } }; int a[200000]; FenwickTree<long long> ft; int t[800000]; int n; void build(int x = 0, int L = 0, int R = n - 1) { if (L == R) { t[x] = a[L]; return; } int M = (L + R) / 2; build(2 * x + 1, L, M); build(2 * x + 2, M + 1, R); t[x] = max(t[2 * x + 1], t[2 * x + 2]); } void upd(int index, int val, int x = 0, int L = 0, int R = n - 1) { if (L == R) { t[x] = val; return; } int M = (L + R) / 2; if (index <= M) { upd(index, val, 2 * x + 1, L, M); } else { upd(index, val, 2 * x + 2, M + 1, R); } t[x] = max(t[2 * x + 1], t[2 * x + 2]); } int get(long long val, int from, int x = 0, int L = 0, int R = n - 1) { if (t[x] < val || R < from) { return n; } else if (L == R) { return L; } int M = (L + R) / 2; if (M < from) { return get(val, from, 2 * x + 2, M + 1, R); } else if (t[2 * x + 1] >= val) { int s = get(val, from, 2 * x + 1, L, M); if (s < n) { return s; } } return get(val, from, 2 * x + 2, M + 1, R); } int get_ans() { long long cur = 0; int index = 0; if (a[0] == 0) { return 1; } while (index < n) { cur += a[index]; index = get(cur, index + 1); cur = ft.sum(index); if (a[index] == cur) { break; } } return index >= n ? -1 : index + 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int q; cin >> n >> q; vector<long long> b; for (int i = 0; i < n; ++i) { cin >> a[i]; b.push_back(a[i]); } ft = FenwickTree<long long>(b); build(); while (q--) { int p, x; cin >> p >> x; --p; ft.add(p, x - a[p]); a[p] = x; upd(p, x); cout << get_ans() << n ; } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Input Delay Controller
// /___/ /\ Filename : IDELAYCTRL.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter and initialized outpus.
// 04/10/07 - CR 436682 fix, disable activity when rst is high
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IDELAYCTRL (RDY, REFCLK, RST);
output RDY;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
reg notifier;
`endif
input REFCLK;
input RST;
wire refclk_in;
wire rst_in;
time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg lost, rdy_out = 0;
assign RDY = rdy_out;
assign refclk_in = REFCLK;
assign rst_in = RST;
always @(rst_in, lost) begin
if ((rst_in == 1'b1) || (lost == 1))
rdy_out <= 1'b0;
else if (rst_in == 1'b0 && lost == 0)
rdy_out <= 1'b1;
end
initial begin
clock_edge <= 0;
clock_high <= 0;
clock_low <= 0;
lost <= 1;
period <= 0;
end
always @(posedge refclk_in) begin
if(rst_in == 1'b0) begin
clock_edge <= $time;
if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
period <= $time - clock_edge;
else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
period <= 0;
else if ((period == 0) && (clock_edge != 0))
period <= $time - clock_edge;
end
end
always @(posedge refclk_in) begin
clock_low <= 1'b0;
clock_high <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_posedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_low != 1'b1) && (clock_posedge != 1'b1))
lost <= 1;
end
always @(posedge refclk_in) begin
clock_negedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_posedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_high <= 1'b0;
clock_low <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_negedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_high != 1'b1) && (clock_negedge != 1'b1))
lost <= 1;
end
//*** Timing Checks Start here
specify
(posedge RST => (RDY +: 0)) = (0:0:0, 0:0:0);
(RST => RDY) = (0:0:0, 0:0:0);
(REFCLK => RDY) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge REFCLK, 0:0:0, notifier);
$period (posedge REFCLK, 0:0:0, notifier);
$width (negedge REFCLK, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge REFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDELAYCTRL
`endcelldefine
|
// file: dcm_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module dcm_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
#(PER1*50);
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
dcm_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
#include <bits/stdc++.h> using namespace std; set<int> cn[10000]; int nx[10000]; string xm[10000]; int main() { int m; cin >> m; ; map<string, int> mx; int n = 0; for (int i = (0); i < m; i++) { string a, b; cin >> a >> b; if (!mx.count(a)) mx[a] = n, xm[n++] = a; if (!mx.count(b)) mx[b] = n, xm[n++] = b; cn[mx[a]].insert(mx[b]); cn[mx[b]].insert(mx[a]); } cout << n << endl; for (int i = (0); i < n; i++) { memset(nx, 0, sizeof(nx)); int my = -1, cmy = 0; for (auto f : cn[i]) { for (auto fx : cn[f]) { if (fx == i || cn[fx].count(i)) continue; nx[fx]++; if (nx[fx] > my) my = nx[fx], cmy = 1; else if (nx[fx] == my) cmy++; } } if (cmy == 0) { cmy = n - 1 - cn[i].size(); } cout << xm[i] << << cmy << endl; } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_dexp_64ns_64ns_64_18_full_dsp
#(parameter
ID = 8,
NUM_STAGE = 18,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dexp_16_full_dsp_64 ANN_ap_dexp_16_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 9; bool p[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; vector<int> k; for (int i = 2; i <= 1e6; i++) { if (p[i]) continue; k.push_back(i); for (int j = i + i; j <= 1e6; j += i) { p[j] = 1; } } int t; cin >> t; while (t--) { long long x; cin >> x; long long m = sqrtl(x); long long r = upper_bound(k.begin(), k.end(), x) - k.begin(); long long l = upper_bound(k.begin(), k.end(), m) - k.begin(); cout << r - l + 1 << n ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; template <class T1, class T2> ostream &operator<<(ostream &os, const pair<T1, T2> &p) { os << { << p.first << , << p.second << } ; return os; } const int N = 1e6 + 5; const long long oo = 998244353; long long fact[N]; long long fact_inv[N]; long long extended_euclidean(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = extended_euclidean(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } long long mod_inverse(long long a, long long m) { long long x, y; long long g = extended_euclidean(a, m, x, y); if (g != 1) { cout << No solution! ; return -1; } else { x = (x % m + m) % m; return x; } } long long ncr(int n, int r) { return n < r ? 0 : ((1LL * fact[n] % oo * fact_inv[r] % oo) % oo * fact_inv[n - r]) % oo; } void pre(int N) { fact[0] = 1; for (long long i = 1; i < N; i++) { fact[i] = (i * fact[i - 1]) % oo; } fact_inv[N - 1] = mod_inverse(fact[N - 1], oo); for (long long i = N - 2; i >= 0; i--) { fact_inv[i] = (i + 1LL) * fact_inv[i + 1] % oo; } } long long bigmod(long long a, long long p, long long m) { long long res = 1; long long x = a; while (p) { if (p & 1) { res = (res * x) % m; } x = (x * x) % m; p = p >> 1; } return res; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); pre(N); int n; cin >> n; int a = 0, b = 0; int totww = 0, totwb = 0; int totbb = 0, totbw = 0; int tot__ = 0; while (n--) { string s; cin >> s; if (s == WW ) a++; else if (s == W? or s == ?W ) b++; else if (s == B? or s == ?B ) a--, b++; else if (s == BB ) a--; else if (s == ?? ) b += 2, a--; totww += s == WW ; totwb += s == W? ; totwb += s == WB ; totwb += s == ?B ; totbb += s == BB ; totbw += s == B? ; totbw += s == BW ; totbw += s == ?W ; tot__ += s == ?? ; } a = -a; long long ans = 0; if (a <= b and a >= 0) { ans = ncr(b, a); if (totww == 0 and totbb == 0) { long long x = bigmod(2, tot__, oo); ans = (ans - x + oo) % oo; ans += totbw == 0; ans += totwb == 0; } } ans = (ans + oo) % oo; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long LINF = 0x3f3f3f3f3f3f3f3f; const long long NLINF = 0xf7f7f7f7f7f7f7f7; const int INF = 0x3f3f3f3f, NINF = 0xf7f7f7f7; const int MOD1 = 1e9 + 7, MOD2 = 1e9 + 9; const int N = 1e5 + 10; vector<int> sz; int t, n, lst; int main() { for (scanf( %d , &t); t--;) { scanf( %d , &n), lst = -1; printf( 1 ); while (n > 0) { ; int k = 1; while (k * (k - 1) / 2 <= n) k++; k--; if (lst != -1) sz.emplace_back(lst - k); lst = k, n -= k * (k - 1) / 2; } sz.emplace_back(lst); ; reverse(sz.begin(), sz.end()); for (auto &x : sz) { for (int i = 0; i < x; i++) printf( 3 ); printf( 7 ); } sz.clear(); printf( n ); } } |
#include <bits/stdc++.h> int n, fa[200005][2], sz[200005][2]; long long ans; int find(int x, int c) { return fa[x][c] == x ? x : (fa[x][c] = find(fa[x][c], c)); } void merge(int x, int y, int c) { x = find(x, c), y = find(y, c); if (x == y) return; fa[y][c] = fa[x][c], sz[x][c] += sz[y][c]; } int main() { scanf( %d , &n); for (register int i = 1; i <= n; ++i) fa[i][0] = fa[i][1] = i, sz[i][0] = sz[i][1] = 1; for (register int i = 1, u, v, w; i < n; ++i) scanf( %d%d%d , &u, &v, &w), merge(u, v, w); for (register int i = 1; i <= n; ++i) ans += 1ll * sz[find(i, 0)][0] * sz[find(i, 1)][1] - 1; printf( %lld , ans); } |
//////////////////////////////////////////////////////////////////////
//// ////
//// CRC_gen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:17 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module CRC_gen (
Reset ,
Clk ,
Init ,
Frame_data ,
Data_en ,
CRC_rd ,
CRC_end ,
CRC_out
);
input Reset ;
input Clk ;
input Init ;
input [7:0] Frame_data ;
input Data_en ;
input CRC_rd ;
output [7:0] CRC_out ;
output CRC_end ;
//******************************************************************************
//internal signals
//******************************************************************************
reg [7:0] CRC_out ;
reg [31:0] CRC_reg;
reg CRC_end;
reg [3:0] Counter;
//******************************************************************************
//******************************************************************************
//input data width is 8bit, and the first bit is bit[0]
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
CRC_reg <=32'hffffffff;
else if (Init)
CRC_reg <=32'hffffffff;
else if (Data_en)
CRC_reg <=NextCRC(Frame_data,CRC_reg);
else if (CRC_rd)
CRC_reg <={CRC_reg[23:0],8'hff};
always @ (CRC_rd or CRC_reg)
if (CRC_rd)
CRC_out <=~{
CRC_reg[24],
CRC_reg[25],
CRC_reg[26],
CRC_reg[27],
CRC_reg[28],
CRC_reg[29],
CRC_reg[30],
CRC_reg[31]
};
else
CRC_out <=0;
//caculate CRC out length ,4 cycles
//CRC_end aligned to last CRC checksum data
always @(posedge Clk or posedge Reset)
if (Reset)
Counter <=0;
else if (!CRC_rd)
Counter <=0;
else
Counter <=Counter + 1;
always @ (Counter)
if (Counter==3)
CRC_end=1;
else
CRC_end=0;
endmodule
|
/*
* Utility functions for verilog testbenches
*
* Copyright (C) 2016 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
//I have been patched
module vlog_functions;
task progress_bar;
input [8*32:1] msg;
input integer current;
input integer total;
begin
if(!(current%(total/10)))
$display("%0s %0d/%0d", msg, current, total);
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ex_gcd(long long a, long long b, long long &x, long long &y) { int d = a; if (b == 0) { x = 1; y = 0; } else { d = ex_gcd(b, a % b, y, x); y -= a / b * x; } return d; } int main() { long long a, b, c; long long x, y; cin >> a >> b >> c; int gcd = ex_gcd(a, b, x, y); if (-c % gcd) cout << -1; else { long long k = (-c) / gcd; cout << k * x << << k * y; } return 0; } |
#include<bits/stdc++.h> using namespace std; typedef long long int ll; #define MAX 2000000000 vector<ll> feaseable; void setfun(){ for(ll i = 3; i<MAX; i+=2){ ll sq = i * i; if(sq>MAX){ break; } ll c = (sq + 1)/2; feaseable.push_back(c); } } int main(){ int t; cin>>t; setfun(); while(t--){ int n; cin>>n; auto x = upper_bound(feaseable.begin(),feaseable.end(),n); int ans = x - feaseable.begin(); cout<<ans<<endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:19:54 04/26/2017
// Design Name:
// Module Name: decrypt_dumb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt_dumb(
input [63:0] message,
input [63:0] DESkey,
output reg [63:0] decrypted,
output done,
input clk,
input reset,
input enable,
input ack
);
// 8 of 8 bits
reg [63:0] rand;
initial begin
rand = {8'd238, 8'd107, 8'd12, 8'd79, 8'd36, 8'd116, 8'd4, 8'd112};
end
reg [7:0] firstBit, secondBit, thirdBit;
// 8 of 3 bits
reg [23:0] randIdx;
reg [2:0] state;
localparam
INITIAL = 3'd1,
DECRYPT = 3'd2,
DONE = 3'd4;
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
state <= INITIAL;
randIdx = 24'd0;
end
else
begin
case (state)
INITIAL:
begin : STATE_INITIAL
if (enable)
state <= DECRYPT;
end
DECRYPT:
begin: STATE_DECRYPT
integer i;
for (i = 0; i < 8; i = i + 1) begin
firstBit[i] = (DESkey[8*i+2 +: 2] ^ DESkey[8*i+6 +: 2]) > 2'd1;
secondBit[i] = (DESkey[8*i +: 2] ^ DESkey[8*i+4 +: 2]) > 2'd1;
thirdBit[i] = (DESkey[8*i +: 4] ^ DESkey[8*i+4 +: 4]) > 3'd3;
randIdx[3 * i +: 3] = {firstBit[i], secondBit[i], thirdBit[i]};
decrypted[8 * i +: 8] <= message[8 * i +: 8] ^ rand[randIdx[3 * i +: 3] +: 8];
end
state <= DONE;
end
DONE:
begin: STATE_DONE
if (ack)
state <= INITIAL;
end
endcase
end
end
assign done = state == DONE;
endmodule
|
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