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#include <bits/stdc++.h> using namespace std; int main() { srand(time(0)); if (rand() % 2 == 0) cout << Odd ; else cout << Even ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MK2
`ifndef DEBUG
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b010};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[150]; int b[150]; int n, k; string s; bool ok[400005], dem = -1; int main() { cin.tie(NULL); cin >> n >> k; cin.ignore(); cin >> s; for (int i = 1; i <= 50; i++) a[i] = 0; for (int i = 0; i < n; i++) { a[int(s[i]) - 96]++; b[int(s[i]) - 96]++; } bool o = true; int i = 1; while (k >= 1) { if (a[i] >= 1) { a[i]--; k--; } else i++; } int d = i; int k = 0; for (int i = 0; i < n; i++) { if (int(s[i]) - 96 > d) cout << s[i]; else if (int(s[i]) - 96 == d && k + a[d] >= b[d]) cout << s[i]; else if (int(s[i]) - 96 == d) k++; } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int in() { int N = 0; register char c = getchar_unlocked(); while (c < 48 || c > 57) { c = getchar_unlocked(); } while (c > 47 && c < 58) { N = (N << 3) + (N << 1) + (c - 48); c = getchar_unlocked(); } return N; } inline long long int inl() { long long int N = 0; register char c = getchar_unlocked(); while (c < 48 || c > 57) { c = getchar_unlocked(); } while (c > 47 && c < 58) { N = (N << 3) + (N << 1) + (c - 48); c = getchar_unlocked(); } return N; } inline int inp() { int N = 0, sign = 1; register char c = getchar_unlocked(); while (c < 48 || c > 57) { if (c == - ) sign = 0; c = getchar_unlocked(); } while (c > 47 && c < 58) { N = (N << 3) + (N << 1) + (c - 48); c = getchar_unlocked(); } return (sign ? N : (-N)); } inline long long int inpl() { long long int N = 0, sign = 1; register char c = getchar_unlocked(); while (c < 48 || c > 57) { if (c == - ) sign = 0; c = getchar_unlocked(); } while (c > 47 && c < 58) { N = (N << 3) + (N << 1) + (c - 48); c = getchar_unlocked(); } return (sign ? N : (-N)); } inline bool inb() { char c = getchar_unlocked(); while (c < 48 || c > 57) { c = getchar_unlocked(); } return (c == 0 ? 0 : 1); } inline long long int ModP(long long int b, long long int e) { b %= 1000000007; long long int r = 1; while (e > 0) { if (e & 1) r = (r * b) % 1000000007; b = (b * b) % 1000000007; e >>= 1; } return r; } bool pri[10] = {1, 1, 0, 0}; vector<int> prm; inline void prime_init() { int i, j; for (i = 3; i * i < 10; i += 2) { if (!pri[i]) { for (j = i * i; j <= 10; j += 2 * i) { pri[j] = 1; } } } } inline void prime_asgn() { int i; prm.push_back(2); for (i = 3; i < 10; i += 2) if (!pri[i]) prm.push_back(i); } inline bool prime_check(long long int i) { if (i == 1) return 0; if (i < 4) return 1; if (i & 1) { if (i < 10) { if (!pri[i]) return 1; else return 0; } else { int j, x; for (j = 1; ((x = prm[j]) * x) <= i; j++) { if (!(i % x)) return 0; } return 1; } } else return 0; } inline bool rngprm_check(int i) { if (i == 1) return 0; if (i < 4) return 1; if (i & 1) { if (!pri[i]) return 1; else return 0; } else return 0; } inline int npf(long long int s) { int j, x; int c; for (c = j = 0; ((x = prm[j]) * prm[j]) <= s; j++) { if (!(s % x)) { c++; while (!(s % x)) { s /= x; } } } if (s > 1) c++; return (c); } inline int nf(long long int s) { if (s == 1) return 1; int j, x, f = 1; int c = 1; for (j = 0; ((x = prm[j]) * prm[j]) <= s; c = 1, j++) { if (!(s % x)) { while (!(s % x)) { s /= x; c++; } f = f * c; } } if (s > 1) { f = f << 1; } return (f); } vector<pair<int, int> > nfa; inline void nfx(long long int s) { nfa.clear(); if (s == 1) return; int j, x, c = 0; for (j = 0; ((x = prm[j]) * prm[j]) <= s; c = 0, j++) { if (!(s % x)) { while (!(s % x)) { s /= x; c++; } nfa.push_back(make_pair((x), (c))); } } if (s > 1) { nfa.push_back(make_pair((s), (1))); } } vector<long long int> factors; inline void factr() { factors.clear(); factors.push_back(1); long long int i, y, p, q, j; for (pair<int, int> x : nfa) { y = factors.size(); p = x.first; q = x.second; for (j = 0; j < q; j++) { for (i = 0; i < y; i++) { factors.push_back(factors[i] * p); } p *= x.first; } } } long long int fc[10]; inline long long int InverseEuler(long long int n) { return ModP(n, 1000000007 - 2); } inline long long int nCr(int n, int r) { if (r > n) return 0; return (fc[n] * ((InverseEuler(fc[r]) * InverseEuler(fc[n - r])) % 1000000007)) % 1000000007; } inline void facs() { fc[0] = fc[1] = 1; for (long long int i = 2; i < 10; i++) { fc[i] = (i * fc[i - 1]) % 1000000007; } } int main() { int h1 = in(), a1 = in(), c1 = in(), h2 = in(), a2 = in(), s = 0, h = 0, i; vector<int> a; while (h2 > 0) { if ((h2 - a1) > 0 && h1 <= a2) { h++; a.push_back(1); h1 += c1; } else { h2 -= a1; s++; } h1 -= a2; } cout << h + s << n ; for (i = 0; i < (h); ++i) cout << HEAL n ; for (i = 0; i < (s); ++i) cout << STRIKE n ; return 0; } |
`timescale 1ns / 1ps
module control(clk, lsb_B, init, Z, ld_rst, shift, acc, done);
input clk;
input lsb_B;
input init;
input Z;
output reg ld_rst;
output reg shift;
output reg acc;
output reg done;
reg [2:0] current_state;
reg [2:0] next_state;
parameter start=3'b000, check=3'b001, acum=3'b010, shft=3'b011, end1=3'b100;
always @(lsb_B or init or Z or current_state)begin
case(current_state)
start: begin
acc=1'b0;
ld_rst=1'b1;
shift=1'b0;
done=1'b0;
if (init == 1'b1) next_state<=check;
else next_state<=start;
end
check: begin
acc=1'b0;
ld_rst=1'b0;
shift=1'b0;
done=1'b0;
if (lsb_B == 1'b1) next_state<=acum;
else next_state<=shft;
end
acum: begin
acc=1'b1;
ld_rst=1'b0;
shift=1'b0;
done=1'b0;
next_state<=shft;
end
shft: begin
acc=1'b0;
ld_rst=1'b0;
shift=1'b1;
done=1'b0;
if (Z == 1'b1) next_state<=end1;
else next_state<=check;
end
end1: begin
acc=1'b0;
ld_rst=1'b0;
shift=1'b0;
done=1'b1;
next_state<=start;
end
default:
begin
acc=1'b0;
ld_rst=1'b1;
shift=1'b0;
done=1'b0;
next_state<=start;
end
endcase
end
always @(negedge clk) begin
current_state<=next_state;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod1 = 1e9 + 7, mod = 998244353; const long long N = 3e5 + 7; long long ncr[N]; void fact(long long A) { auto binexp = [&](long long a, long long b) { long long res = 1; while (b) { if (b & 1) res *= a; a *= a; b >>= 1; a %= mod; res %= mod; } return res; }; ncr[0] = 1; for (long long i = 1; i <= A; i++) ncr[i] = ncr[i - 1] * (A - i + 1) % mod * binexp(i, mod - 2) % mod; } void a_b_l() { long long n; cin >> n; n <<= 1; long long ar[n]; for (long long i = 0; i < n; i++) cin >> ar[i]; sort(ar, ar + n); long long k = 0; for (long long i = 0; i < n / 2; i++) { k += ar[n - i - 1] - ar[i]; k %= mod; } fact(n); long long ans = k * ncr[n / 2] % mod; cout << ans << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); ; long long t = 1; while (t--) a_b_l(); } |
// Library - static, Cell - th44w3, View - schematic
// LAST TIME SAVED: May 23 17:58:12 2014
// NETLIST TIME: May 23 17:58:31 2014
`timescale 1ns / 1ns
module th44w3 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w3";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N6 ( .d(net042), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net042), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(y), .s(net042), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net042), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net042), .b(cds_globals.gnd_));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net027), .d(net34));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net49), .d(net32));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net027));
pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net027));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
#include <bits/stdc++.h> bool m1; FILE *Input = stdin, *Output = stdout; const int maxn = 1e5 + 5; struct Edge { int to, next; Edge(){}; Edge(int ar1, int ar2) { to = ar1; next = ar2; } } Tree_List[maxn << 1], Tree2_List[maxn << 2]; int Numt[maxn], tott, deg[maxn], totn; int Numt2[maxn << 1], tott2, size[maxn << 1], Max_Len2; int Start_Mark, End_Mark, All_Mark[maxn << 1]; int Start, End, All[maxn << 1], Max_Len, next[maxn]; bool Found, onLine[maxn << 1], Mark[maxn << 1]; bool m2; void Add_Tree(int ar1, int ar2) { Tree_List[++tott] = Edge(ar2, Numt[ar1]); Numt[ar1] = tott; } void Add_Tree2(int ar1, int ar2) { Tree2_List[++tott2] = Edge(ar2, Numt2[ar1]); Numt2[ar1] = tott2; } void Get_next(int ar1, int ar2) { next[ar1] = ar1; for (int i = Numt[ar1]; i; i = Tree_List[i].next) { int hh = Tree_List[i].to; if (hh == ar2) continue; Get_next(hh, ar1); if (deg[ar1] == 2) next[ar1] = next[hh]; } } void Link(int ar1, int ar2) { for (int i = Numt[ar1]; i; i = Tree_List[i].next) { int hh = Tree_List[i].to; if (hh == ar2 || next[hh] == ar1) continue; if (deg[next[hh]] == 1 || deg[ar1] == 1) { Add_Tree2(ar1, next[hh]); Add_Tree2(next[hh], ar1); Link(next[hh], ar1); } else { Add_Tree2(ar1, hh); Add_Tree2(hh, ar1); Link(hh, ar1); } } } void Get_One_Mark(int ar1, int ar2, int ar3) { if (Mark[ar1] && ar3 > Max_Len) { Start_Mark = ar1; Max_Len = ar3; } for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_One_Mark(hh, ar1, ar3 + 1); } } void Get_the_Other_Mark(int ar1, int ar2, int ar3) { if (Mark[ar1] && ar3 > Max_Len) { End_Mark = ar1; Max_Len = ar3; } for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_the_Other_Mark(hh, ar1, ar3 + 1); } } void Get_One(int ar1, int ar2, int ar3) { if (ar3 > Max_Len) { Start = ar1; Max_Len = ar3; } for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_One(hh, ar1, ar3 + 1); } } void Get_the_Other(int ar1, int ar2, int ar3) { if (ar3 > Max_Len) { End = ar1; Max_Len = ar3; } for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_the_Other(hh, ar1, ar3 + 1); } } void Get_All(int ar1, int ar2, int ar3) { All[++All[0]] = ar1; if (ar1 == ar3) { Found = 1; return; } for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_All(hh, ar1, ar3); if (Found) return; } All[0]--; } void Get_All_Mark(int ar1, int ar2, int ar3) { if (Mark[ar1]) All[++All[0]] = ar1; if (ar1 == ar3) { Found = 1; return; } for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_All_Mark(hh, ar1, ar3); if (Found) return; } if (Mark[ar1]) All[0]--; } void Get_Two(int ar1, int ar2, int ar3) { if (ar3 > Max_Len) { Max_Len2 = Max_Len; End = Start; Max_Len = ar3; Start = ar1; } else if (ar3 > Max_Len2) { Max_Len2 = ar3; End = ar1; } for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_Two(hh, ar1, ar3 + 1); } } void Get_size(int ar1, int ar2) { size[ar1] = 1; for (int i = Numt2[ar1]; i; i = Tree2_List[i].next) { int hh = Tree2_List[i].to; if (hh == ar2) continue; Get_size(hh, ar1); size[ar1] += size[hh]; } } int main() { int n; while (fscanf(Input, %d , &n) == 1) { memset(Numt, 0, sizeof(Numt)); memset(Numt2, 0, sizeof(Numt2)); memset(deg, 0, sizeof(deg)); memset(Mark, 0, sizeof(Mark)); memset(onLine, 0, sizeof(onLine)); tott = 0; totn = n; tott2 = 0; for (int i = 1; i < n; i++) { int h1, h2; fscanf(Input, %d %d , &h1, &h2); Add_Tree(h1, h2); Add_Tree(h2, h1); deg[h1]++; deg[h2]++; } int Root = 1; while (Root <= n && deg[Root] == 2) Root++; if (Root > n) abort(); Get_next(Root, 0); Link(Root, 0); bool Could = 1; Max_Len = 0; Get_One(Root, 0, 0); Max_Len = 0; Get_the_Other(Start, 0, 0); Found = All[0] = 0; Get_All(Start, 0, End); for (int i = 1; i <= All[0]; i++) onLine[All[i]] = 1; for (int i = 1; i <= All[0]; i++) { bool flag = 0; for (int j = Numt2[All[i]]; j; j = Tree2_List[j].next) { int hh = Tree2_List[j].to; if (onLine[hh]) continue; Get_size(hh, All[i]); if (size[hh] > 3) { flag = 1; break; } if (size[hh] == 2) abort(); } if (flag) { Could = 0; break; } } if (Could) fprintf(Output, Yes n ); else fprintf(Output, No n ); } fclose(Input); fclose(Output); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long a[100000]; long long n, i; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); a[0] = 1; for (i = 1; i <= n - 1; i++) { if (a[i] == a[i - 1] || a[i] == a[i - 1] + 1) continue; else a[i] = a[i - 1] + 1; } cout << a[n - 1] + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { pair<int, int> a, b, c; int s = 0; cin >> a.first >> a.second >> b.first >> b.second >> c.first >> c.second; s = a.first * a.second + b.first * b.second + c.first * c.second; if ((int)sqrt(s + 0.0) * (int)sqrt(s + 0.0) != s) { cout << -1; return 0; } s = sqrt(s + 0.0); if (a.first < a.second) swap(a.first, a.second); if (b.first < b.second) swap(b.first, b.second); if (c.first < c.second) swap(c.first, c.second); char mp[] = { A , B , C }; if (a.first < b.first) { swap(a, b); swap(mp[0], mp[1]); } if (b.first < c.first) { swap(mp[1], mp[2]); swap(b, c); } if (a.first < b.first) { swap(mp[0], mp[1]); swap(a, b); } if (a.first == s) { if (b.first == c.first && a.first == b.first) { if (a.second + b.second + c.second == s) { cout << s << endl; for (int i = 0; i < a.second; ++i, cout << endl) for (int j = 0; j < a.first; ++j) cout << mp[0]; for (int i = 0; i < b.second; ++i, cout << endl) for (int j = 0; j < b.first; ++j) cout << mp[1]; for (int i = 0; i < c.second; ++i, cout << endl) for (int j = 0; j < c.first; ++j) cout << mp[2]; } } else if (b.second + c.second == a.first && a.second + b.first == s && b.first == c.first) { cout << s << endl; for (int i = 0; i < a.second; ++i, cout << endl) for (int j = 0; j < a.first; ++j) cout << mp[0]; for (int i = 0; i < b.first; ++i, cout << endl) for (int j = 0; j < s; ++j) if (j < b.second) cout << mp[1]; else cout << mp[2]; } else if (b.first + c.first == a.first && a.second + b.second == s && b.second == c.second) { cout << s << endl; for (int i = 0; i < a.second; ++i, cout << endl) for (int j = 0; j < a.first; ++j) cout << mp[0]; for (int i = 0; i < s - a.second; ++i, cout << endl) for (int j = 0; j < s; ++j) if (j < b.first) cout << mp[1]; else cout << mp[2]; } else if (b.first + c.second == a.first && a.second + b.second == s && b.second == c.first) { cout << s << endl; for (int i = 0; i < a.second; ++i, cout << endl) for (int j = 0; j < a.first; ++j) cout << mp[0]; for (int i = 0; i < s - a.second; ++i, cout << endl) for (int j = 0; j < s; ++j) if (j < b.first) cout << mp[1]; else cout << mp[2]; } else cout << -1; } else cout << -1; } |
module Platform (
clk_clk,
hex0_2_export,
hex3_5_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
i2c_SDAT,
i2c_SCLK,
keys_export,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n,
switches_export,
xck_clk);
input clk_clk;
output [20:0] hex0_2_export;
output [20:0] hex3_5_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
inout i2c_SDAT;
output i2c_SCLK;
input [2:0] keys_export;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
input [9:0] switches_export;
output xck_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[500][500] = {0}, arr[500], n; int check(int i, int j) { if (dp[i][j] != 0) return dp[i][j]; if (i > j) return 0; if (i == j) { dp[i][j] = 1; return 1; } int a = 1 + check(i + 1, j); int m = 1e9, it; for (it = i + 2; it <= j; it++) { if (arr[i] == arr[it]) { if (m > check(i + 1, it - 1) + check(it + 1, j)) { m = check(i + 1, it - 1) + check(it + 1, j); } } } int c = 1e9; if (arr[i] == arr[i + 1]) c = 1 + check(i + 2, j); dp[i][j] = min(min(c, a), m); return dp[i][j]; } int main() { cin >> n; int i, j, k, l; for (i = 0; i < n; i++) { cin >> arr[i]; } check(0, n - 1); cout << dp[0][n - 1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T sgn(T x) { return x < 0 ? -1 : x != 0; } template <typename T> T gcd(T a, T b) { return a ? gcd(b % a, a) : b; } void reads(string& x) { char kk[((long long)5e2 + 123)]; scanf( %s , kk); x = kk; } long long n, m, ans; long long v, r[((long long)5e2 + 123)], c[((long long)5e2 + 123)]; long long lp[(long long)1e6 + 1]; vector<long long> pr; void sieve() { for (long long i = 2; i <= 1e6; ++i) { if (lp[i] == 0) { lp[i] = i; pr.push_back(i); } for (long long j = 0; j < (long long)pr.size() && pr[j] <= lp[i] && i * pr[j] <= 1e6; ++j) lp[i * pr[j]] = pr[j]; } } void solve() { sieve(); scanf( %lld %lld , &n, &m); for (long long i = 0; i < n; i++) for (long long j = 0; j < m; j++) { scanf( %lld , &v); v = (*lower_bound(pr.begin(), pr.end(), v) - v); r[i] += v; c[j] += v; } ans = 1e9; for (long long i = 0; i < n; i++) ans = min(ans, r[i]); for (long long i = 0; i < m; i++) ans = min(ans, c[i]); printf( %lld n , ans); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); } |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_autostart (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_TB_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_TB_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s18.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__clkdlybuf4s18 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_TB_V
|
#include <bits/stdc++.h> using namespace std; int k, n, a; int d[1001]; bool vis[1001], flag; int main() { scanf( %d%d , &n, &k); int cut = 0; for (int i = 2; i <= k; i++) { if (k % i) continue; int crt = 1; while (k % i == 0) { crt *= i; k /= i; } d[cut++] = crt; } for (int i = 0; i < n; i++) { scanf( %d , &a); for (int j = 0; j < cut; j++) { if (a % d[j] == 0) { vis[j] = true; } } } flag = true; for (int j = 0; j < cut; j++) { flag &= vis[j]; } if (flag) printf( Yes n ); else printf( No n ); return 0; } |
#include <bits/stdc++.h> using namespace std; pair<int, int> operator+(const pair<int, int> &a, const pair<int, int> &b) { return make_pair(a.first + b.first, a.second + b.second); } pair<int, int> operator-(const pair<int, int> &a, const pair<int, int> &b) { return make_pair(a.first - b.first, a.second - b.second); } pair<int, int> &operator+=(pair<int, int> &a, const pair<int, int> &b) { a.first += b.first; a.second += b.second; return a; } pair<int, int> &operator-=(pair<int, int> &a, const pair<int, int> &b) { a.first -= b.first; a.second -= b.second; return a; } template <class T, class U> bool cmp_second(const pair<T, U> &a, const pair<T, U> &b) { return a.second < b.second; } template <class T> T gcd(T a, T b) { a = abs(a); b = abs(b); while (b) { T t = b; b = a % b; a = t; } return a; } template <class T> pair<T, T> ext_gcd(T a, T b) { T a0 = 1, a1 = 0, b0 = 0, b1 = 1; if (a < 0) { a = -a; a0 = -1; } if (b < 0) { b = -b; b1 = -1; } while (b) { T t, q = a / b; t = b; b = a - b * q; a = t; t = b0; b0 = a0 - b0 * q; a0 = t; t = b1; b1 = a1 - b1 * q; a1 = t; } return make_pair(a0, a1); } inline int sg(int x) { return x ? (x > 0 ? 1 : -1) : 0; } int main(void) { int len, skip; scanf( %d %d , &(len), &(skip)); len++; skip++; long long sol = 0; for (int a = skip; a <= len - a; a++) { int b = len - a; int ab3 = a * b * 3; int cnt = 0; for (int c = skip; c <= len - skip; c++) { int dmax = (ab3 - 1) / (a + c) - b; dmax = min(dmax, len - skip); dmax = max(dmax, skip - 1); if (dmax < skip) break; cnt += dmax - (skip - 1); } sol += cnt + (a < len - a ? cnt : 0); } sol *= 3; cout << sol << endl; return 0; } |
`timescale 1ns /1ps
//Memory.
module Memory(
input wire [31:0] wData,
input wire clk,
input wire enable,
input wire rw,
input wire reset,
input wire [9:0] add,
output reg [31:0] rData
);
reg [31:0] mem [1023:0];
integer i;
always @(posedge clk) begin
if (reset) begin
for(i = 0; i < 1024; i = i + 1) begin
mem[i] = 32'h00000000;
end
rData = 32'h00000000;
//Program: Integral
mem[0] = 32'h68100000;
mem[1] = 32'hC00;
mem[2] = 32'h80000800;
mem[3] = 32'h80000800;
mem[4] = 32'h80000800;
mem[5] = 32'h800;
mem[6] = 32'h80;
mem[7] = 32'h0;
mem[8] = 32'h59002000;
mem[9] = 32'h59804000;
mem[10] = 32'h5A006000;
mem[11] = 32'h5A808000;
mem[12] = 32'h5B00A000;
mem[13] = 32'h5B80C000;
mem[14] = 32'h7AB02400;
mem[15] = 32'h1DBD8000;
mem[16] = 32'h6580E000;
mem[17] = 32'h68340000;
mem[18] = 32'h1AAC0000;
mem[19] = 32'h19440000;
mem[20] = 32'h19AC8000;
mem[21] = 32'hC4D0000;
mem[22] = 32'hD250000;
mem[23] = 32'hDD58000;
mem[24] = 32'hABA8000;
mem[25] = 32'h681C0000;
end
else begin
if (enable) begin
//rw 0 read, 1 write
if (!rw) rData = mem[add];
else mem[add] = wData;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[5000005]; int len[1000005]; int idx[1000005]; int sum[1000005]; int sz = 0; int dp[1000005][20]; int p[1000005]; int main() { int n, r, c; scanf( %d%d%d , &n, &r, &c); gets(s); gets(s); int cnt = 0, slen = 0; for (int i = 0; s[i]; i++, slen++) { if (s[i] == && cnt != 0) { len[sz] = cnt; idx[sz++] = i - cnt; cnt = 0; } else cnt++; } if (cnt > 0) { len[sz] = cnt; idx[sz++] = slen - cnt; cnt = 0; } sum[0] = len[0]; for (int i = 1; i < n; i++) sum[i] = sum[i - 1] + 1 + len[i]; for (int i = n - 1; i >= 0; i--) { int id = upper_bound(sum, sum + n, (i > 0 ? sum[i - 1] + 1 : 0) + c) - sum; if (id > n) id = n; dp[i][0] = id - i; } for (int j = 2, t = 1; j <= r; j *= 2, t++) { for (int i = n - 1; i >= 0; i--) dp[i][t] = dp[i][t - 1] + dp[i + dp[i][t - 1]][t - 1]; } int maid = -1, ma = 0; for (int i = 0; i < n; i++) { int idx = i, rr = r, cur = 0; for (int j = 20; j >= 0; j--) { if (rr >= (1 << j)) { rr -= (1 << j); cur += dp[idx][j]; idx += dp[idx][j]; } } if (cur > ma) maid = i, ma = cur; } int cn = 1, cs = dp[maid][0]; for (int i = maid; i < maid + ma; i++) { s[idx[i] + len[i]] = 0; if (cn < cs) { printf( %s , s + idx[i]); cn++; } else { printf( %s n , s + idx[i]); cs = dp[i + 1][0]; cn = 1; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_2_V
`define SKY130_FD_SC_HDLL__DIODE_2_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_2 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_2_V
|
#include <bits/stdc++.h> using namespace std; char str[1000001]; int main() { int n; scanf( %d , &n); scanf( %s , str); int sum = 0; int ln = -1; int i, j, k, ans = 0; for (i = 0; i < n; i++) { if (str[i] == ( ) { sum++; if (sum == 0) { ans += i - ln + 1; ln = -1; } } else { sum--; if (sum < 0 && ln == -1) ln = i; } } if (sum != 0) { printf( -1 n ); } else printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long ans; int n, a, b; vector<pair<int, int> > v; int main() { ans = 0; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d %d , &a, &b); v.push_back(make_pair(b, a)); } sort(v.begin(), v.end()); for (int i = 0, j = 0; i < v.size(); ++i) { if (v[i].second > j) { j = v[i].first; ++ans; } } printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 4; bool isPrime(int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long test = 1; cin >> test; for (int qw = 1; qw <= test; qw++) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int sum = 0; for (int i = 0; i < n; i++) sum += a[i]; if (!isPrime(sum)) { cout << n << endl; for (int i = 1; i <= n; i++) cout << i << ; cout << endl; } else { int flag = 0; for (int i = 0; i < n; i++) { if (!isPrime(sum - a[i])) { cout << n - 1 << endl; flag = 1; for (int j = 0; j < n; j++) { if (i != j) cout << j + 1 << ; } cout << endl; } if (flag == 1) break; } } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_BEHAVIORAL_V
`define SKY130_FD_SC_HS__FAHCON_BEHAVIORAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire u_vpwr_vgnd1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , u_vpwr_vgnd1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int clique_size(vector<int> *graph, vector<int> &govs, int *visited, int starting) { visited[starting] = 1; int size = 1; for (int i = 0; i < graph[starting].size(); i++) { if (!visited[graph[starting][i]]) { size += clique_size(graph, govs, visited, graph[starting][i]); } } return size; } int main(int argc, char *argv[]) { vector<int> graph[1001]; vector<int> govs; int visited[1001] = {0}; int n, m, k; cin >> n >> m >> k; for (int i = 0; i < k; i++) { int c; cin >> c; govs.push_back(c); } for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } int connected_points = 0; int max_state_size = 0; int answer = 0; for (int i = 0; i < k; i++) { int count = clique_size(graph, govs, visited, govs[i]); connected_points += count; max_state_size = (count > max_state_size) ? count : max_state_size; answer += count * (count - 1) / 2; } int remaining = n - connected_points; answer -= max_state_size * (max_state_size - 1) / 2; max_state_size += remaining; answer += max_state_size * (max_state_size - 1) / 2; cout << answer - m << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V |
module peripheral_adc(input clk_in,
input cs,
input wr
input rd,
input din,
input rst,
input reg [3:0]addr,
output reg [7:0]d_out,
output clk_div, //ns
output done); //ns
// regs and wires :v
reg [3:0] s;
wire clk_div; //clk_div
wire done; //done
wire dout; //d0 :v
// regs and wires :v
adc ad(.Din(din), .clk_in(clk_in), .reset(rst), .D0f(dout), .clk_div(clk_div), .done(done), .rd(rd));
//addr decoder
always @(*) begin
case (addr)
4'h0:begin s = (cs && rd) ? 3'b001 : 5'b000 ;end //clk_div
4'h2:begin s = (cs && rd) ? 3'b010 : 5'b000 ;end //done
4'h4:begin s = (cs && rd) ? 3'b100 : 5'b000 ;end //D0
default:begin s=3'b000 ; end
endcase
end
//addre decoder
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
3'b001: d_out[0]= clk_div;
3'b010: d_out[0]= done;
3'b100: d_out[7:0]= dout;
default: d_out=0;
endcase
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for to_integer() function.
module to_int_test;
logic unsigned [7:0] unsign;
logic signed [7:0] sign;
to_int dut(unsign, sign);
initial begin
unsign = 8'b11001100;
sign = 8'b11001100;
#1;
if(dut.s_natural !== 204)
begin
$display("FAILED 1");
$finish();
end
if(dut.s_integer !== -52)
begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
end
endmodule
|
#define rep(i,n) for(int i=0;i<(int)(n);i++) #define ALL(v) v.begin(),v.end() typedef long long ll; #include<bits/stdc++.h> using namespace std; int main(){ ios::sync_with_stdio(false); std::cin.tie(nullptr); int t; cin>>t; while(t--){ int xa,ya,xb,yb,xf,yf; cin>>xa>>ya>>xb>>yb>>xf>>yf; if(xa==xb && xf==xa && (yf-ya)*(yf-yb)<0) cout<<abs(ya-yb)+2<<endl; else if(ya==yb && yf==ya && (xf-xa)*(xf-xb)<0) cout<<abs(xa-xb)+2<<endl; else cout<<abs(xa-xb)+abs(ya-yb)<<endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct mat { int num[4][4]; }; int p[100009]; mat mult(mat &a, mat &b) { mat ret; for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) { long long t = 0; for (int k = 0; k < 4; k++) t += 1ll * a.num[i][k] * b.num[k][j]; ret.num[i][j] = t % 1000000007; } return ret; } int cal(string &a, string &b) { if (b.size() > a.size()) return 0; int ret = 0; p[0] = -1; for (int j, i = 0; b[i]; i++) { for (j = p[i]; j >= 0 && b[i] != b[j]; j = p[j]) ; p[i + 1] = j + 1; } for (int j = 0, i = 0; a[i]; i++) { for (; j >= 0 && a[i] != b[j]; j = p[j]) ; j++; if (j == b.size()) ret++, j = p[j]; } return ret; } mat m1, m2; int query(long long n, string &q) { if (n == 1) { return q == a ? 1 : 0; } if (n == 2) { return q == b ? 1 : 0; } string s1 = a , s2 = b , s = b ; for (n -= 2; n && s1.size() < q.size(); n--, s1 = s2, s2 = s) s = s2 + s1; int f1 = cal(s1, q), f2 = cal(s, q); if (!n) return f2; s = s2.substr(s2.size() - q.size() + 1, q.size() - 1) + s2.substr(0, q.size() - 1); int t1 = cal(s, q); s = s1.substr(s1.size() - q.size() + 1, q.size() - 1) + s1.substr(0, q.size() - 1); int t2 = cal(s, q); m1.num[0][0] = m1.num[0][1] = m1.num[0][2] = m1.num[1][0] = m1.num[2][2] = m1.num[3][3] = 1; m2.num[0][0] = m2.num[0][1] = m2.num[0][3] = m2.num[1][0] = m2.num[2][2] = m2.num[3][3] = 1; mat res, t = mult(m2, m1); bool flag = 0; if (n % 2) res = m1, flag = 1; for (n /= 2; n; n >>= 1, t = mult(t, t)) if (n & 1) { if (!flag) res = t, flag = 1; else res = mult(res, t); } return (1ll * res.num[0][0] * f2 + 1ll * res.num[0][1] * f1 + 1ll * res.num[0][2] * t1 + 1ll * res.num[0][3] * t2) % 1000000007; } int main() { long long n, m; cin >> n >> m; string s; while (m--) cin >> s, cout << query(n, s) << endl; } |
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache_pmem_mux
(
// Inputs
input clk_i
,input rst_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
,input select_i
,input [ 3:0] inport0_wr_i
,input inport0_rd_i
,input [ 7:0] inport0_len_i
,input [ 31:0] inport0_addr_i
,input [ 31:0] inport0_write_data_i
,input [ 3:0] inport1_wr_i
,input inport1_rd_i
,input [ 7:0] inport1_len_i
,input [ 31:0] inport1_addr_i
,input [ 31:0] inport1_write_data_i
// Outputs
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
,output inport0_accept_o
,output inport0_ack_o
,output inport0_error_o
,output [ 31:0] inport0_read_data_o
,output inport1_accept_o
,output inport1_ack_o
,output inport1_error_o
,output [ 31:0] inport1_read_data_o
);
//-----------------------------------------------------------------
// Output Mux
//-----------------------------------------------------------------
reg [ 3:0] outport_wr_r;
reg outport_rd_r;
reg [ 7:0] outport_len_r;
reg [ 31:0] outport_addr_r;
reg [ 31:0] outport_write_data_r;
reg select_q;
always @ *
begin
case (select_i)
1'd1:
begin
outport_wr_r = inport1_wr_i;
outport_rd_r = inport1_rd_i;
outport_len_r = inport1_len_i;
outport_addr_r = inport1_addr_i;
outport_write_data_r = inport1_write_data_i;
end
default:
begin
outport_wr_r = inport0_wr_i;
outport_rd_r = inport0_rd_i;
outport_len_r = inport0_len_i;
outport_addr_r = inport0_addr_i;
outport_write_data_r = inport0_write_data_i;
end
endcase
end
assign outport_wr_o = outport_wr_r;
assign outport_rd_o = outport_rd_r;
assign outport_len_o = outport_len_r;
assign outport_addr_o = outport_addr_r;
assign outport_write_data_o = outport_write_data_r;
// Delayed version of selector to match phase of response signals
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
select_q <= 1'b0;
else
select_q <= select_i;
assign inport0_ack_o = (select_q == 1'd0) && outport_ack_i;
assign inport0_error_o = (select_q == 1'd0) && outport_error_i;
assign inport0_read_data_o = outport_read_data_i;
assign inport0_accept_o = (select_i == 1'd0) && outport_accept_i;
assign inport1_ack_o = (select_q == 1'd1) && outport_ack_i;
assign inport1_error_o = (select_q == 1'd1) && outport_error_i;
assign inport1_read_data_o = outport_read_data_i;
assign inport1_accept_o = (select_i == 1'd1) && outport_accept_i;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFRTN_PP_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; inline long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } long long n; long long f[35][35][2]; inline long long power(long long x, long long y) { if (y < 0) return 1; long long ans = 1; for (; y; y >>= 1) { if (y & 1) ans = ans * x % mod; x = x * x % mod; } return ans; } signed main() { n = read(); f[31][0][1] = 1; for (long long i = 30; i >= 0; i--) { if (!((n >> i) & 1)) { for (long long j = 0; j <= 30 - i; j++) { f[i][j + 1][0] = (f[i][j + 1][0] + f[i + 1][j][0]) % mod; f[i][j][0] = (f[i][j][0] + f[i + 1][j][0] * power(2, j) % mod) % mod; f[i][j][1] = (f[i][j][1] + f[i + 1][j][1] * power(2, j - 1) % mod) % mod; } } else { for (long long j = 0; j <= 30 - i; j++) { f[i][j + 1][0] = (f[i][j + 1][0] + f[i + 1][j][0]) % mod; f[i][j][0] = (f[i][j][0] + f[i + 1][j][0] * power(2, j) % mod) % mod; f[i][j + 1][1] = (f[i][j + 1][1] + f[i + 1][j][1]) % mod; f[i][j][0] = (f[i][j][0] + f[i + 1][j][1] * power(2, j - 1) % mod) % mod; if (j) f[i][j][1] = (f[i][j][1] + f[i + 1][j][1] * power(2, j - 1) % mod) % mod; } } } long long ans = 1; for (long long i = 1; i <= 30; i++) ans = (ans + f[0][i][0] + f[0][i][1]) % mod; printf( %lld n , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:45:55 04/23/2017
// Design Name:
// Module Name: decrypt_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt_tb ;
reg clk_tb, reset_tb, ack_tb, enable_tb;
wire done_tb;
wire [7:0][7:0] message_tb, DESkey_tb;
wire [7:0][7:0] decrypted_tb;
parameter CLK_PERIOD = 20;
decrypt d(
message_tb,
DESkey_tb,
decrypted_tb,
done_tb,
clk_tb,
reset_tb,
enable_tb,
ack_tb
);
initial
begin : CLK_GENERATOR
clk_tb = 0;
forever
begin
#(CLK_PERIOD / 2) clk_tb = ~clk_tb;
end
end
initial
begin : RESET_GENERATOR
reset_tb = 1;
#(2 * CLK_PERIOD) reset_tb = 1;
end
initial
begin : STIMULUS
message_tb = 8'h0;
DESkey_tb = 8'h0;
enable_tb = 0;
ack_tb = 0;
wait(!reset_tb);
@(posedge clk_tb);
//test 1
@(posedge clk_tb);
#1;
message_tb = "waterbot";
DESkey = "hellodar";
enable_tb = 1;
@(posedge clk_tb);
#5;
enable_tb = 0;
wait(done_tb);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d n , &n); string str; getline(cin, str); int ans = 0; int subans = 0; for (int i = 0; i < n; i++) { if (str[i] != ) { int ascii = (int)str[i]; if (ascii >= 65 && ascii <= 90) { subans++; } ans = max(ans, subans); } else { subans = 0; } } cout << ans << endl; } |
`include "mpc4922.v"
`include "lineto.v"
module top(
output led_r,
output led_b,
output gpio_2, // cs
output gpio_46, // clk
output gpio_47 // do
);
wire reset = 0;
wire clk_48mhz, clk = clk_48mhz;
SB_HFOSC osc(1,1,clk_48mhz);
reg [11:0] lineto_x;
reg [11:0] lineto_y;
reg lineto_strobe;
wire lineto_ready;
wire axis;
wire [11:0] value_x;
wire [11:0] value_y;
reg dac_strobe;
wire dac_ready;
lineto #(.BITS(12)) drawer(
.clk(clk),
.reset(reset),
.strobe(lineto_strobe),
.x_in(lineto_x),
.y_in(lineto_y),
.ready(lineto_ready),
.x_out(value_x),
.y_out(value_y),
.axis(axis)
);
mpc4922 dac(
.clk(clk),
.reset(reset),
.cs_pin(gpio_2),
.clk_pin(gpio_46),
.data_pin(gpio_47),
.value(axis ? value_x : value_y),
.axis(axis),
.strobe(dac_strobe),
.ready(dac_ready)
);
reg [15:0] counter;
always @(posedge clk) begin
counter <= counter + 1;
led_r = !(counter < value_x);
led_b = 1; //!dac_strobe; //!(counter < value_y);
end
always @(posedge clk)
begin
dac_strobe <= 0;
lineto_strobe <= 0;
if (!dac_ready || dac_strobe)
begin
// do nothing
end else //if (counter == 0)
begin
dac_strobe <= 1;
lineto_x <= lineto_x + 3;
lineto_y <= lineto_y + 2;
end
if (lineto_ready)
lineto_strobe <= 1;
end
endmodule
|
module InterruptController (
input wire rst,
input wire clk,
input wire fastClk,
output reg irq,
input wire turnOffIRQ,
output reg[31:0] intAddr,
output reg[15:0] intData,
inout wire ps2CLK,
inout wire ps2DATA,
input wire[31:0] addr,
input wire re,
input wire we,
input wire[3:0] irData,
input wire irPressed,
input wire[31:0] bp0Addr, bp1Addr, bp2Addr, bp3Addr, bpAddr, keyboardAddr, irAddr,
input wire bp0En, bp1En, bp2En, bp3En, keyboardEn, irEn
);
wire[8:0] pressedKey;
wire pressed;
KeyboardReader reader (
.rst (rst),
.clk (fastClk),
.ps2CLK (ps2CLK),
.ps2DATA (ps2DATA),
.pressedKey (pressedKey),
.pressed (pressed)
);
wire isBP0 = (addr == bp0Addr) & bp0En & (re | we);
wire isBP1 = (addr == bp1Addr) & bp1En & (re | we);
wire isBP2 = (addr == bp2Addr) & bp2En & (re | we);
wire isBP3 = (addr == bp3Addr) & bp3En & (re | we);
reg keyPressedSync, irPressedSync;
reg clk0, clk1, clk2;
always @(posedge fastClk) begin
if (rst) begin
clk0 <= 0;
clk1 <= 0;
clk2 <= 0;
end
else begin
clk0 <= clk;
clk1 <= clk0;
clk2 <= clk1;
end
end
wire posedgeClk = ~clk2 & clk1;
always @(posedge clk) begin
if (rst) begin
irq <= 0;
intAddr <= 32'd0;
intData <= 16'd0;
end else if (isBP0) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd0;
end else if (isBP1) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd1;
end else if (isBP2) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd2;
end else if (isBP3) begin
irq <= 1;
intAddr <= bpAddr;
intData <= 16'd3;
end else if (keyPressedSync) begin
irq <= 1;
intAddr <= keyboardAddr;
intData <= pressedKey;
end else if (irPressedSync) begin
irq <= 1;
intAddr <= irAddr;
intData <= irData;
end else if (turnOffIRQ) begin
irq <= 0;
end
end
always @(posedge fastClk) begin
if (rst) begin
keyPressedSync <= 0;
end else if (pressed) begin
keyPressedSync <= 1;
end else if (posedgeClk) begin
keyPressedSync <= 0;
end
end
always @(posedge fastClk) begin
if (rst) begin
irPressedSync <= 0;
end else if (irPressed) begin
irPressedSync <= 1;
end else if (posedgeClk) begin
irPressedSync <= 0;
end
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
my_DSP
#(
.LOC("DSP48E2_X0Y120")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 11]),
.dout(dout[ 0 +: 5])
);
endmodule
// ---------------------------------------------------------------------
module my_DSP (input clk, input [10:0] din, output [4:0] dout);
parameter LOC = "";
(* LOC=LOC *)
DSP48E2 #(
// Feature Control Attributes: Data Path Selection
.AMULTSEL("A"), // Selects A input to multiplier (A, AD)
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
.BMULTSEL("B"), // Selects B input to multiplier (AD, B)
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
.PREADDINSEL("A"), // Selects input to pre-adder (A, B)
.RND(48'h000000000000), // Rounding Constant
.USE_MULT("MULTIPLY"), // Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
.USE_SIMD("ONE48"), // SIMD selection (FOUR12, ONE48, TWO24)
.USE_WIDEXOR("FALSE"), // Use the Wide XOR function (FALSE, TRUE)
.XORSIMD("XOR24_48_96"), // Mode of operation for the Wide XOR (XOR12, XOR24_48_96)
// Pattern Detector Attributes: Pattern Detection Configuration
.AUTORESET_PATDET("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH
.AUTORESET_PRIORITY("RESET"), // Priority of AUTORESET vs. CEP (CEP, RESET).
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
.SEL_MASK("MASK"), // C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
.SEL_PATTERN("PATTERN"), // Select pattern value (C, PATTERN)
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect (NO_PATDET, PATDET)
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
.IS_ALUMODE_INVERTED(4'b0000), // Optional inversion for ALUMODE
.IS_CARRYIN_INVERTED(1'b0), // Optional inversion for CARRYIN
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_INMODE_INVERTED(5'b00000), // Optional inversion for INMODE
.IS_OPMODE_INVERTED(9'b000000000), // Optional inversion for OPMODE
.IS_RSTALLCARRYIN_INVERTED(1'b0), // Optional inversion for RSTALLCARRYIN
.IS_RSTALUMODE_INVERTED(1'b0), // Optional inversion for RSTALUMODE
.IS_RSTA_INVERTED(1'b0), // Optional inversion for RSTA
.IS_RSTB_INVERTED(1'b0), // Optional inversion for RSTB
.IS_RSTCTRL_INVERTED(1'b0), // Optional inversion for RSTCTRL
.IS_RSTC_INVERTED(1'b0), // Optional inversion for RSTC
.IS_RSTD_INVERTED(1'b0), // Optional inversion for RSTD
.IS_RSTINMODE_INVERTED(1'b0), // Optional inversion for RSTINMODE
.IS_RSTM_INVERTED(1'b0), // Optional inversion for RSTM
.IS_RSTP_INVERTED(1'b0), // Optional inversion for RSTP
// Register Control Attributes: Pipeline Register Configuration
.ACASCREG(1), // Number of pipeline stages between A/ACIN and ACOUT (0-2)
.ADREG(1), // Pipeline stages for pre-adder (0-1)
.ALUMODEREG(1), // Pipeline stages for ALUMODE (0-1)
.AREG(1), // Pipeline stages for A (0-2)
.BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0-2)
.BREG(1), // Pipeline stages for B (0-2)
.CARRYINREG(1), // Pipeline stages for CARRYIN (0-1)
.CARRYINSELREG(1), // Pipeline stages for CARRYINSEL (0-1)
.CREG(1), // Pipeline stages for C (0-1)
.DREG(1), // Pipeline stages for D (0-1)
.INMODEREG(1), // Pipeline stages for INMODE (0-1)
.MREG(1), // Multiplier pipeline stages (0-1)
.OPMODEREG(1), // Pipeline stages for OPMODE (0-1)
.PREG(1) // Number of pipeline stages for P (0-1)
)
DSP48E2_inst (
// Cascade outputs: Cascade Ports
.ACOUT(), // 30-bit output: A port cascade
.BCOUT(), // 18-bit output: B cascade
.CARRYCASCOUT(), // 1-bit output: Cascade carry
.MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade
.PCOUT(), // 48-bit output: Cascade output
// Control outputs: Control Inputs/Status Bits
.OVERFLOW(), // 1-bit output: Overflow in add/acc
.PATTERNBDETECT(dout[0]), // 1-bit output: Pattern bar detect
.PATTERNDETECT(dout[1]), // 1-bit output: Pattern detect
.UNDERFLOW(), // 1-bit output: Underflow in add/acc
// Data outputs: Data Ports
.CARRYOUT(dout[2]), // 4-bit output: Carry
.P(dout[3]), // 48-bit output: Primary data
.XOROUT(dout[4]), // 8-bit output: XOR data
// Cascade inputs: Cascade Ports
.ACIN(), // 30-bit input: A cascade data
.BCIN(), // 18-bit input: B cascade
.CARRYCASCIN(), // 1-bit input: Cascade carry
.MULTSIGNIN(), // 1-bit input: Multiplier sign cascade
.PCIN(), // 48-bit input: P cascade
// Control inputs: Control Inputs/Status Bits
.ALUMODE(din[0]), // 4-bit input: ALU control
.CARRYINSEL(din[1]), // 3-bit input: Carry select
.CLK(clk), // 1-bit input: Clock
.INMODE(din[2]), // 5-bit input: INMODE control
.OPMODE(din[3]), // 9-bit input: Operation mode
// Data inputs: Data Ports
.A(din[4]), // 30-bit input: A data
.B(din[5]), // 18-bit input: B data
.C(din[6]), // 48-bit input: C data
.CARRYIN(din[7]), // 1-bit input: Carry-in
.D(din[8]), // 27-bit input: D data
// Reset/Clock Enable inputs: Reset/Clock Enable Inputs
.CEA1(1'b1), // 1-bit input: Clock enable for 1st stage AREG
.CEA2(1'b1), // 1-bit input: Clock enable for 2nd stage AREG
.CEAD(1'b1), // 1-bit input: Clock enable for ADREG
.CEALUMODE(din[9]), // 1-bit input: Clock enable for ALUMODE
.CEB1(1'b1), // 1-bit input: Clock enable for 1st stage BREG
.CEB2(1'b1), // 1-bit input: Clock enable for 2nd stage BREG
.CEC(1'b1), // 1-bit input: Clock enable for CREG
.CECARRYIN(1'b1), // 1-bit input: Clock enable for CARRYINREG
.CECTRL(1'b1), // 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
.CED(1'b1), // 1-bit input: Clock enable for DREG
.CEINMODE(din[10]), // 1-bit input: Clock enable for INMODEREG
.CEM(1'b1), // 1-bit input: Clock enable for MREG
.CEP(1'b1), // 1-bit input: Clock enable for PREG
.RSTA(1'b0), // 1-bit input: Reset for AREG
.RSTALLCARRYIN(1'b0), // 1-bit input: Reset for CARRYINREG
.RSTALUMODE(1'b0), // 1-bit input: Reset for ALUMODEREG
.RSTB(1'b0), // 1-bit input: Reset for BREG
.RSTC(1'b0), // 1-bit input: Reset for CREG
.RSTCTRL(1'b0), // 1-bit input: Reset for OPMODEREG and CARRYINSELREG
.RSTD(1'b0), // 1-bit input: Reset for DREG and ADREG
.RSTINMODE(1'b0), // 1-bit input: Reset for INMODEREG
.RSTM(1'b0), // 1-bit input: Reset for MREG
.RSTP(1'b0) // 1-bit input: Reset for PREG
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_FUNCTIONAL_V |
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Thanks Rudolf Usselmann yours was a better implementation than mine
Copyright (C) 2000-2002
Rudolf Usselmann
www.asics.ws
*/
`timescale 1 ns/1 ps
module wishbone_interconnect (
//control signals
input clk,
input rst,
//wishbone master signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output o_m_int,
${PORTS}
);
${ADDRESSES}
parameter ADDR_FF = 8'hFF;
//state
//wishbone slave signals
//this should be parameterized
wire [7:0]slave_select;
wire [31:0] interrupts;
assign slave_select = i_m_adr[31:24];
${DATA}
${ACK}
${INT}
assign o_m_int = (interrupts != 0);
${ASSIGN}
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<string> rs; if (n == 1) { rs.push_back( a ); rs.push_back( a ); rs.push_back( b ); rs.push_back( b ); } else if (n == 2) { rs.push_back( aa ); rs.push_back( bb ); rs.push_back( aa ); rs.push_back( bb ); } else if (n == 3) { rs.push_back( aac ); rs.push_back( bbc ); rs.push_back( add ); rs.push_back( abb ); } else if (n == 4) { rs.push_back( aabb ); rs.push_back( cddc ); rs.push_back( ceec ); rs.push_back( aabb ); } else if (n % 2 == 0) { int b = 0; int c = 5; int d = 10; string pal1 = ; string pal2 = z ; string pal3 = z ; for (int i = 0; i < n / 2; i++) { b = (b + 1) % 24; c = (c + 1) % 24; d = (d + 1) % 24; pal1 += string(2, char( a + b)); if (i == n / 2 - 1) continue; pal2 += string(2, char( a + c)); pal3 += string(2, char( a + d)); } pal2 += z ; pal3 += z ; rs.push_back(pal1); rs.push_back(pal2); rs.push_back(pal3); rs.push_back(pal1); } else if (n % 2 != 0) { int b = 0; int c = 5; int d = 10; string pal1 = ; string pal2 = ; string pal3 = z ; for (int i = 0; i < n / 2; i++) { b = (b + 1) % 24; c = (c + 1) % 24; d = (d + 1) % 24; pal1 += string(2, char( a + b)); pal2 += string(2, char( a + c)); pal3 += string(2, char( a + d)); } string pal4 = z + pal1; pal1 += z ; pal2 += z ; rs.push_back(pal1); rs.push_back(pal2); rs.push_back(pal3); rs.push_back(pal4); } for (int i = int(0); i < int(4); i++) { cout << rs[i] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, k, ar[1000005], br[1000005]; int main() { scanf( %lld %lld , &n, &k); long long min_ = 0, max_ = 0; for (int i = 1; i < n + 1; i++) { ar[i] = br[i] = i; min_ += i; max_ += max((long long)i, n - i + 1); } if (k < min_) { cout << -1 ; return 0; } else { long long tot = min_; long long t = n - 1; k -= min_; for (int i = 1; i < n + 1; i++) { if (i >= n + 1 - i) break; if (k > t) { tot += t; min_ += t; swap(br[i], br[n + 1 - i]); } else { tot += k; min_ += k; swap(br[i], br[i + k]); break; } k -= t; t -= 2; } cout << tot << n ; } for (int i = 1; i < n + 1; i++) cout << ar[i] << ; cout << n ; for (int i = 1; i < n + 1; i++) cout << br[i] << ; cout << n ; } |
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ()
//
// Copyright (c) 2004 Guy Hutchison ()
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
module tv80n (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
reg nxt_mreq_n;
reg nxt_iorq_n;
reg nxt_rd_n;
reg nxt_wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @*
begin
nxt_mreq_n = 1;
nxt_rd_n = 1;
nxt_iorq_n = 1;
nxt_wr_n = 1;
if (mcycle[0])
begin
if (tstate[1] || tstate[2])
begin
nxt_rd_n = ~ intcycle_n;
nxt_mreq_n = ~ intcycle_n;
nxt_iorq_n = intcycle_n;
end
end // if (mcycle[0])
else
begin
if ((tstate[1] || tstate[2]) && !no_read && !write)
begin
nxt_rd_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write)
begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && !wait_n)) && write)
begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
end // always @ *
always @(negedge clk)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
end
else
begin
rd_n <= #1 nxt_rd_n;
wr_n <= #1 nxt_wr_n;
iorq_n <= #1 nxt_iorq_n;
mreq_n <= #1 nxt_mreq_n;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
always @(posedge clk)
begin
if (!reset_n)
begin
di_reg <= #1 0;
end
else
begin
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk)
endmodule // t80n
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1 ns / 1 ps
`default_nettype none
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
`resetall
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:50:02 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_mutex_0_0_stub.v
// Design : DemoInterconnect_mutex_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mutex,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(S0_AXI_ACLK, S0_AXI_ARESETN, S0_AXI_AWADDR,
S0_AXI_AWVALID, S0_AXI_AWREADY, S0_AXI_WDATA, S0_AXI_WSTRB, S0_AXI_WVALID, S0_AXI_WREADY,
S0_AXI_BRESP, S0_AXI_BVALID, S0_AXI_BREADY, S0_AXI_ARADDR, S0_AXI_ARVALID, S0_AXI_ARREADY,
S0_AXI_RDATA, S0_AXI_RRESP, S0_AXI_RVALID, S0_AXI_RREADY, S1_AXI_ACLK, S1_AXI_ARESETN,
S1_AXI_AWADDR, S1_AXI_AWVALID, S1_AXI_AWREADY, S1_AXI_WDATA, S1_AXI_WSTRB, S1_AXI_WVALID,
S1_AXI_WREADY, S1_AXI_BRESP, S1_AXI_BVALID, S1_AXI_BREADY, S1_AXI_ARADDR, S1_AXI_ARVALID,
S1_AXI_ARREADY, S1_AXI_RDATA, S1_AXI_RRESP, S1_AXI_RVALID, S1_AXI_RREADY, S2_AXI_ACLK,
S2_AXI_ARESETN, S2_AXI_AWADDR, S2_AXI_AWVALID, S2_AXI_AWREADY, S2_AXI_WDATA, S2_AXI_WSTRB,
S2_AXI_WVALID, S2_AXI_WREADY, S2_AXI_BRESP, S2_AXI_BVALID, S2_AXI_BREADY, S2_AXI_ARADDR,
S2_AXI_ARVALID, S2_AXI_ARREADY, S2_AXI_RDATA, S2_AXI_RRESP, S2_AXI_RVALID, S2_AXI_RREADY)
/* synthesis syn_black_box black_box_pad_pin="S0_AXI_ACLK,S0_AXI_ARESETN,S0_AXI_AWADDR[31:0],S0_AXI_AWVALID,S0_AXI_AWREADY,S0_AXI_WDATA[31:0],S0_AXI_WSTRB[3:0],S0_AXI_WVALID,S0_AXI_WREADY,S0_AXI_BRESP[1:0],S0_AXI_BVALID,S0_AXI_BREADY,S0_AXI_ARADDR[31:0],S0_AXI_ARVALID,S0_AXI_ARREADY,S0_AXI_RDATA[31:0],S0_AXI_RRESP[1:0],S0_AXI_RVALID,S0_AXI_RREADY,S1_AXI_ACLK,S1_AXI_ARESETN,S1_AXI_AWADDR[31:0],S1_AXI_AWVALID,S1_AXI_AWREADY,S1_AXI_WDATA[31:0],S1_AXI_WSTRB[3:0],S1_AXI_WVALID,S1_AXI_WREADY,S1_AXI_BRESP[1:0],S1_AXI_BVALID,S1_AXI_BREADY,S1_AXI_ARADDR[31:0],S1_AXI_ARVALID,S1_AXI_ARREADY,S1_AXI_RDATA[31:0],S1_AXI_RRESP[1:0],S1_AXI_RVALID,S1_AXI_RREADY,S2_AXI_ACLK,S2_AXI_ARESETN,S2_AXI_AWADDR[31:0],S2_AXI_AWVALID,S2_AXI_AWREADY,S2_AXI_WDATA[31:0],S2_AXI_WSTRB[3:0],S2_AXI_WVALID,S2_AXI_WREADY,S2_AXI_BRESP[1:0],S2_AXI_BVALID,S2_AXI_BREADY,S2_AXI_ARADDR[31:0],S2_AXI_ARVALID,S2_AXI_ARREADY,S2_AXI_RDATA[31:0],S2_AXI_RRESP[1:0],S2_AXI_RVALID,S2_AXI_RREADY" */;
input S0_AXI_ACLK;
input S0_AXI_ARESETN;
input [31:0]S0_AXI_AWADDR;
input S0_AXI_AWVALID;
output S0_AXI_AWREADY;
input [31:0]S0_AXI_WDATA;
input [3:0]S0_AXI_WSTRB;
input S0_AXI_WVALID;
output S0_AXI_WREADY;
output [1:0]S0_AXI_BRESP;
output S0_AXI_BVALID;
input S0_AXI_BREADY;
input [31:0]S0_AXI_ARADDR;
input S0_AXI_ARVALID;
output S0_AXI_ARREADY;
output [31:0]S0_AXI_RDATA;
output [1:0]S0_AXI_RRESP;
output S0_AXI_RVALID;
input S0_AXI_RREADY;
input S1_AXI_ACLK;
input S1_AXI_ARESETN;
input [31:0]S1_AXI_AWADDR;
input S1_AXI_AWVALID;
output S1_AXI_AWREADY;
input [31:0]S1_AXI_WDATA;
input [3:0]S1_AXI_WSTRB;
input S1_AXI_WVALID;
output S1_AXI_WREADY;
output [1:0]S1_AXI_BRESP;
output S1_AXI_BVALID;
input S1_AXI_BREADY;
input [31:0]S1_AXI_ARADDR;
input S1_AXI_ARVALID;
output S1_AXI_ARREADY;
output [31:0]S1_AXI_RDATA;
output [1:0]S1_AXI_RRESP;
output S1_AXI_RVALID;
input S1_AXI_RREADY;
input S2_AXI_ACLK;
input S2_AXI_ARESETN;
input [31:0]S2_AXI_AWADDR;
input S2_AXI_AWVALID;
output S2_AXI_AWREADY;
input [31:0]S2_AXI_WDATA;
input [3:0]S2_AXI_WSTRB;
input S2_AXI_WVALID;
output S2_AXI_WREADY;
output [1:0]S2_AXI_BRESP;
output S2_AXI_BVALID;
input S2_AXI_BREADY;
input [31:0]S2_AXI_ARADDR;
input S2_AXI_ARVALID;
output S2_AXI_ARREADY;
output [31:0]S2_AXI_RDATA;
output [1:0]S2_AXI_RRESP;
output S2_AXI_RVALID;
input S2_AXI_RREADY;
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program is designed to test non-constant bit selects in the
* concatenated l-value of procedural assignment.
*/
module main;
reg [3:0] vec;
reg a;
integer i;
initial begin
vec = 4'b0000;
a = 0;
if (vec !== 4'b0000) begin
$display("FAILED -- initialized vec to %b", vec);
$finish;
end
for (i = 0 ; i < 4 ; i = i + 1) begin
{ a, vec[i] } = 2'b11;
end
if (vec !== 4'b1111) begin
$display("FAILED == vec (%b) is not 1111", vec);
$finish;
end
if (a !== 1'b1) begin
$display("FAILED -- a (%b) is not 1", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int fl = 1; cin >> s; for (int i = 0; i < s.size(); ++i) { if (s[i] == 1 || s[i] == 2 ) fl = 0; else if (s[i] == 3 && s[s.size() - i - 1] != 3 ) fl = 0; else if (s[i] == 7 && s[s.size() - i - 1] != 7 ) fl = 0; else if (s[i] == 4 && s[s.size() - i - 1] != 6 ) fl = 0; else if (s[i] == 6 && s[s.size() - i - 1] != 4 ) fl = 0; else if (s[i] == 5 && s[s.size() - i - 1] != 9 ) fl = 0; else if (s[i] == 9 && s[s.size() - i - 1] != 5 ) fl = 0; else if (s[i] == 8 && s[s.size() - i - 1] != 0 ) fl = 0; else if (s[i] == 0 && s[s.size() - i - 1] != 8 ) fl = 0; } if (fl == 1) cout << Yes ; else cout << No ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_1_V
`define SKY130_FD_SC_HD__XNOR3_1_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_1_V
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<long long> a(n + 1), b(n + 1); for (int i = 1; i <= n; i++) cin >> a[i] >> b[i]; long long k; cin >> k; long long x; for (int i = 1; i <= n; i++) if (k >= a[i] && k <= b[i]) { x = i; break; } cout << n - x + 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(0); solve(); } |
#include <bits/stdc++.h> using namespace std; int k, t; char n1[10005]; char n2[10005]; int swapindex[2]; bool same(char x[], char y[], int n) { for (int i = 0; i < n; i++) { if (x[i] != y[i]) { return false; } } return true; } int ham(char x[], char y[], int n) { int temp = 0; for (int i = 0; i < n; i++) { if (x[i] != y[i]) { temp++; } } return temp; } int main() { cin >> k; for (int i = 0; i < k; i++) { cin >> t; for (int l = 0; l < t; l++) { cin >> n1[l]; } for (int l = 0; l < t; l++) { cin >> n2[l]; } if (ham(n1, n2, t) == 2) { int temp = 0; for (int i = 0; i < t; i++) { if (n1[i] != n2[i]) { swapindex[temp] = i; temp++; } } swap(n1[swapindex[0]], n2[swapindex[1]]); if (same(n1, n2, t)) { cout << Yes << endl; } else { cout << No << endl; } } else { cout << No << endl; } } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of Instruction cache data rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_ram.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.6 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we[0]),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isPrime(long long int n) { for (long long int i = 2; i <= sqrt(n); i++) if (n % i == 0) return 0; return 1; } long long knap_0_1(long long wt[], long long val[], long long n, long long w) { long long kp[n + 1][w + 1]; for (long long i = 0; i <= n; i++) { for (long long j = 0; j <= w; j++) { if (i == 0 || j == 0) kp[i][j] = 0; else if (wt[i - 1] <= j) kp[i][j] = max(val[i - 1] + kp[i - 1][j - wt[i - 1]], kp[i - 1][j]); else kp[i][j] = kp[i - 1][j]; } } return kp[n][w]; } long long compute_xor_1_n(long long n) { switch (n & 3) { case 0: return n; case 1: return 1; case 2: return n + 1; case 3: return 0; } } bool isPowerOfTwo(long long x) { return x && (!(x & (x - 1))); } void bfs(vector<long long> g[], long long vis[], long long i, vector<long long> &v) { queue<long long> q; q.push(i); vis[i] = 1; while (!q.empty()) { long long x = q.front(); q.pop(); v.push_back(x); for (long long j = 0; j < g[x].size(); j++) { if (vis[g[x][j]] == 0) { vis[g[x][j]] = 1; q.push(g[x][j]); } } } } long long binary_Expo(long long x, long long n) { long long result = 1; while (n > 0) { if (n % 2 == 1) result = result * x; x = x * x; n = n / 2; } return result; } long long mod_Expo(long long x, long long n, long long M) { long long result = 1; while (n > 0) { if (n % 2 == 1) result = (result * x) % M; x = (x * x) % M; n = n / 2; } return result; } long long GCD(long long A, long long B) { if (B == 0) return A; else return GCD(B, A % B); } long long bs(long long a[], long long l, long long r, long long x, long long n) { while (r >= l) { long long m = l + (r - l) / 2; } return -1; } void SieveOfEratosthenes(int n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } for (int p = 2; p <= n; p++) if (prime[p]) cout << p << ; cout << endl; } long long s1[8] = {1, 1, 1, -1, -1, -1, 0, 0}; long long f1[8] = {-1, 0, 1, -1, 0, 1, -1, 1}; void dfs(long long a1, long long a2, long long b1, long long b2, long long c1, long long c2, long long &first, long long n, vector<long long> vis[]) { vis[b1][b2] = 1; if (a1 == b1 || a2 == b2 || (abs(a1 - b1) == abs(a2 - b2))) return; if (b1 == c1 && b2 == c2) { first = 1; return; } for (long long i = 0; i < 8; i++) { if (b1 + f1[i] <= 0 || b2 + s1[i] <= 0 || b1 + f1[i] > n || b2 + s1[i] > n || vis[b1 + f1[i]][b2 + s1[i]] == 1) continue; dfs(a1, a2, b1 + f1[i], b2 + s1[i], c1, c2, first, n, vis); if (first == 1) return; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long a1, a2, b1, b2, c1, c2; cin >> a1 >> a2; cin >> b1 >> b2; cin >> c1 >> c2; long long first = 0; vector<long long> vis[n + 1]; for (long long i = 0; i < n + 1; i++) for (long long j = 0; j < n + 1; j++) vis[i].push_back(0); dfs(a1, a2, b1, b2, c1, c2, first, n, vis); if (first) cout << YES << endl; else cout << NO << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc = 0;
reg [31:0] in;
wire [31:0] out;
t_extend_class_v sub (.in(in), .out(out));
always @ (posedge clk) begin
cyc <= cyc + 8'd1;
if (cyc == 8'd1) begin
in <= 32'h10;
end
if (cyc == 8'd2) begin
if (out != 32'h11) $stop;
end
if (cyc == 8'd9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_extend_class_v (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output logic [31:0] out;
always @* begin
// When "in" changes, call my method
out = $c("this->m_myobjp->my_math(", in, ")");
end
`systemc_header
#include "t_extend_class_c.h" // Header for contained object
`systemc_interface
t_extend_class_c* m_myobjp; // Pointer to object we are embedding
`systemc_ctor
m_myobjp = new t_extend_class_c(); // Construct contained object
`systemc_dtor
delete m_myobjp; // Destruct contained object
`verilog
endmodule
|
#include <bits/stdc++.h> using namespace std; const double inf = 1e9; const double eps = 1e-7; int main() { int n, width, height, begin0, begin1; cin >> n >> width >> height >> begin0 >> begin1; vector<pair<int, pair<double, double>>> a(n + 1); a[0] = make_pair(0, make_pair(1, begin1 - begin0)); for (int i = 1; i <= n; ++i) { int x, y; cin >> a[i].first >> x >> y; a[i].second = make_pair(1 - (double)height / y, (double)x * height / y); } auto check = [&](double v) { double l = begin0, r = begin0; for (int i = 1; i <= n; ++i) { double delta = v * (a[i].first - a[i - 1].first); double k0 = a[i - 1].second.first, b0 = a[i - 1].second.second; double k1 = a[i].second.first, b1 = a[i].second.second; double k = k0 / k1, tl, tr; if (k1 > 0) { tl = (b0 - delta - b1) / k1; tr = (b0 + delta - b1) / k1; } else { tl = (b0 + delta - b1) / k1; tr = (b0 - delta - b1) / k1; } if (fabs(k0 - k1) < eps) { tl = max(tl, -delta); tr = min(tr, delta); if (tl > tr + eps) { return false; } l += tl; r += tr; } else { double ml = (tl + delta) / (1 - k), mr = (tr - delta) / (1 - k); double nl = inf, nr = -inf; if (k > 1) { { double left = max(l, mr), right = min(r, ml); if (right >= left - eps) { nl = min(nl, left - delta); nr = max(nr, right + delta); } } { double left = max(l, max(ml, mr)), right = r; if (right >= left - eps) { right = min(right, (delta - tl) / (k - 1)); if (right >= left - eps) { nl = min(nl, k * left + tl); nr = max(nr, right + delta); } } } { double left = l, right = min(r, min(ml, mr)); if (right >= left - eps) { left = max(left, -(delta + tr) / (k - 1)); if (right >= left - eps) { nl = min(nl, left - delta); nr = max(nr, k * right + tr); } } } { double left = max(l, ml), right = min(r, mr); if (right >= left - eps) { nl = min(nl, k * left + tl); nr = max(nr, k * right + tr); } } } else { { double left = max(l, ml), right = min(r, mr); if (right >= left - eps) { if (k > 0) { nl = min(nl, k * left + tl); nr = max(nr, k * right + tr); } else { nl = min(nl, k * right + tl); nr = max(nr, k * left + tr); } } } { double left = l, right = min(r, min(ml, mr)); if (right >= left - eps) { left = max(left, (tl - delta) / (1 - k)); if (right >= left - eps) { if (k > 0) { nl = min(nl, k * left + tl); } else { nl = min(nl, k * right + tl); } nr = max(nr, right + delta); } } } { double left = max(l, max(ml, mr)), right = r; if (right >= left - eps) { right = min(right, (tr + delta) / (1 - k)); if (right >= left - eps) { nl = min(nl, left - delta); if (k > 0) { nr = max(nr, k * right + tr); } else { nr = max(nr, k * left + tr); } } } } { double left = max(l, mr), right = min(r, ml); if (right >= left - eps) { nl = min(nl, left - delta); nr = max(nr, right + delta); } } } if (nl > nr + eps) { return false; } l = nl; r = nr; } l = max(l, (double)0); r = min(r, (double)width); if (k1 > 0) { l = max(l, -b1 / k1); r = min(r, (width - b1) / k1); } else { l = max(l, (width - b1) / k1); r = min(r, -b1 / k1); } if (l > r + eps) { return false; } } return true; }; if (!check(width + 1)) { cout << -1 << endl; } else { double l = 0, r = width; for (int t = 0; t < 50; ++t) { double m = (l + r) / 2; if (check(m)) { r = m; } else { l = m; } } cout << fixed << setprecision(6) << r << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A2BB2O_PP_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_PP_BLACKBOX_V
|
//-----------------------------------------------------
// This is FSM demo program using always block
// Design Name : fsm_using_always
// File Name : fsm_using_always.v
//-----------------------------------------------------
module fsm_using_always (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//-------------Input Ports-----------------------------
input clock,reset,req_0,req_1;
//-------------Output Ports----------------------------
output gnt_0,gnt_1;
//-------------Input ports Data Type-------------------
wire clock,reset,req_0,req_1;
//-------------Output Ports Data Type------------------
reg gnt_0,gnt_1;
//-------------Internal Constants--------------------------
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//-------------Internal Variables---------------------------
reg [SIZE-1:0] state ;// Seq part of the FSM
reg [SIZE-1:0] next_state ;// combo part of FSM
//----------Code startes Here------------------------
always @ (state or req_0 or req_1)
begin : FSM_COMBO
next_state = 3'b000;
case(state)
IDLE : if (req_0 == 1'b1) begin
next_state = GNT0;
end else if (req_1 == 1'b1) begin
next_state= GNT1;
end else begin
next_state = IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
next_state = GNT0;
end else begin
next_state = IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
next_state = GNT1;
end else begin
next_state = IDLE;
end
default : next_state = IDLE;
endcase
end
//----------Seq Logic-----------------------------
always @ (posedge clock)
begin : FSM_SEQ
if (reset == 1'b1) begin
state <= #1 IDLE;
end else begin
state <= #1 next_state;
end
end
//----------Output Logic-----------------------------
always @ (posedge clock)
begin : OUTPUT_LOGIC
if (reset == 1'b1) begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
else begin
case(state)
IDLE : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
GNT0 : begin
gnt_0 <= #1 1'b1;
gnt_1 <= #1 1'b0;
end
GNT1 : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b1;
end
default : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
endcase
end
end // End Of Block OUTPUT_LOGIC
endmodule // End of Module arbiter |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using ll = long long int; using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c *x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug &operator<<(const c &) { return *this; } }; template <typename T> void ara_read(T &v, ll n) { ll temp; for (ll i = 0; i < n; i++) { scanf( %lld , &temp); v.emplace_back(temp); } } template <typename T> void ara_print(T &v) { for (ll x : v) printf( %lld , x); puts( ); } const int INF = 1e9 + 99; using Pair = pair<int, int>; using vec = vector<ll>; void bruteforce(int l, int r, vec &v) { return; set<ll> myset; for (ll x : v) { for (ll i = l; i <= r; i++) myset.insert(i + x); } printf( BruteForce : %d n , (int)myset.size()); } void improved(vec &v, vec &pref, int n) { ll l, r; scanf( %lld%lld , &l, &r); ll w = r - l + 1; ll ind = lower_bound(v.begin(), --v.end(), w) - v.begin(); ll ans = (n - ind) * w + pref[ind]; printf( %lld , ans); } int main() { int n; scanf( %d , &n); vec v(n); for (ll &x : v) scanf( %lld , &x); sort(v.begin(), v.end()); for (int i = 0; i < n - 1; i++) v[i] = v[i + 1] - v[i]; sort(v.begin(), --v.end()); int q; scanf( %d , &q); vec pref(n); for (int i = 1; i < n; i++) pref[i] = pref[i - 1] + v[i - 1]; for (int i = 0; i < q; i++) improved(v, pref, n); puts( ); return 0; } |
`include "shiftRegister.v"
`include "memory.v"
`include "finiteStateMachine.v"
`include "programCounter.v"
`include "serialClock.v"
`include "mosiFF.v"
`include "delayCounter.v"
module toplevel(led, gpioBank1, gpioBank2, clk, sw, btn); // possible inputs from fpga
output [7:0] led;
output [3:0] gpioBank1;
output [3:0] gpioBank2;
input clk;
input[7:0] sw;
input[3:0] btn;
parameter memBits = 10;
parameter memAddrWidth = 16;
parameter dataBits = 8;
// serialClock
wire sclk, sclkPosEdge, sclkNegEdge;
wire sclk8PosEdge;
// memory
wire writeEnable;
wire[memAddrWidth-1:0] addr;
wire[memBits-1:0] dataIn, dataOut;
// programCounter
wire[memAddrWidth-1:0] memAddr;
wire reset;
assign addr = memAddr;
// shiftRegister
wire parallelLoad, serialDataIn; //not used
wire[dataBits-1:0] parallelDataOut; // also not used
wire[dataBits-1:0] parallelDataIn;
wire serialDataOut;
assign parallelLoad = sclk8PosEdge;
assign parallelDataIn = dataOut;
// finiteStateMachine
wire[memBits-1:0] instr; // probably change this to reflect envelope diagram
wire cs, dc;
wire[dataBits-1:0] parallelData;
assign instr = dataOut;
// mosiFF
wire md, mq;
assign md = serialDataOut;
wire cd, cq;
assign cd = cs;
wire dd, dq;
assign dd = dc;
// delayCounter
wire delayEn, pcEn;
// OUTPUTS
assign gpioBank1[0] = mq; // mosi
assign gpioBank1[1] = cq; // mosi again because why not
assign gpioBank1[2] = dq; // chip select
assign gpioBank1[3] = sclkPosEdge; // data/command
//assign led[7:0] = parallelDataOut[7:0];
assign led[3:0] = memAddr[3:0];
assign led[4] = sclk;
assign led[5] = mq;
assign led[6] = cs;
assign led[7] = dc;
assign reset = sw[0];
assign gpioBank2[0] = !btn[1];
assign gpioBank2[1] = !btn[1];
assign gpioBank2[2] = !btn[1];
assign gpioBank2[3] = !btn[1];
// Magic
serialClock #(19) sc(clk, sclk, sclkPosEdge, sclkNegEdge, sclk8PosEdge);
memory m(clk, writeEnable, addr, dataIn, dataOut);
programCounter pc(clk, sclkPosEdge, pcEn, memAddr, sclk8PosEdge, reset);
shiftRegister sr(clk, sclkPosEdge, parallelLoad, parallelDataIn, serialDataIn, parallelDataOut, serialDataOut, sclk8PosEdge);
finiteStateMachine fsm(clk, sclkPosEdge, instr, cs, dc, delayEn, parallelData);
mosiFF mff(clk, sclkNegEdge, md, mq);
mosiFF csff(clk, sclkNegEdge, cd, cq);
mosiFF dcff(clk, sclkNegEdge, dd, dq);
delayCounter delC(clk, delayEn, pcEn);
endmodule
|
`include "core.h"
`default_nettype none
module decode_authcheck(
input wire [31:0] iINSTRUCTION,
input wire iKERNEL_ACCESS,
input wire [13:0] iMMU_FLAGS,
output wire [2:0] oIRQ41
);
/*************************************************
Instruction Check
[0] : IRQ41 Privilege error.(Page)
*************************************************/
function func_instruction_fault_check;
input [31:0] func_instruction;
input func_kernel; //[1]Kernel
input [5:0] func_mmu_flags;
begin
if(func_kernel)begin //Kernell Mode
func_instruction_fault_check = 1'b0;
end
else begin
case(func_instruction[30:21])
`FAULT_INSTRUCTION_SRTISR,
`FAULT_INSTRUCTION_SRKPDTR,
`FAULT_INSTRUCTION_SRPDTW,
`FAULT_INSTRUCTION_SRIEIW,
`FAULT_INSTRUCTION_SRTISW,
`FAULT_INSTRUCTION_SRKPDTW,
`FAULT_INSTRUCTION_SRMMUW,
`FAULT_INSTRUCTION_HALT,
`FAULT_INSTRUCTION_IDTS : func_instruction_fault_check = 1'b1;
default : func_instruction_fault_check = 1'b0;
endcase
end
end
endfunction
assign oIRQ41 = func_instruction_fault_check(iINSTRUCTION, iKERNEL_ACCESS, iMMU_FLAGS[5:0]);
endmodule
`default_nettype wire
|
// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is the bitplane part of denise
// It accepts data from the bus and converts it to serial video data (6 bits).
// It supports all ocs modes and also handles the pf1<->pf2 priority handling in
// a seperate module.
module denise_bitplanes
(
input clk, // system bus clock
input clk7_en,
input reset,
input c1, // 35ns clock enable signals (for synchronization with clk)
input c3,
input aga,
input [8:1] reg_address_in, // register address
input [15:0] data_in, // bus data in
input [48-1:0] chip48, // big chipram read
input hires, // high resolution mode select
input shres, // super high resolution mode select
input [8:0] hpos, // horizontal position (70ns resolution)
output [8:1] bpldata // bitplane data out
);
//register names and adresses
parameter BPLCON1 = 9'h102;
parameter BPL1DAT = 9'h110;
parameter BPL2DAT = 9'h112;
parameter BPL3DAT = 9'h114;
parameter BPL4DAT = 9'h116;
parameter BPL5DAT = 9'h118;
parameter BPL6DAT = 9'h11a;
parameter BPL7DAT = 9'h11c;
parameter BPL8DAT = 9'h11e;
parameter FMODE = 9'h1fc;
//local signals
reg [15:0] bplcon1; // bplcon1 register
reg [15:0] fmode; // fmod reg
reg [63:0] bpl1dat; // buffer register for bit plane 2
reg [63:0] bpl2dat; // buffer register for bit plane 2
reg [63:0] bpl3dat; // buffer register for bit plane 3
reg [63:0] bpl4dat; // buffer register for bit plane 4
reg [63:0] bpl5dat; // buffer register for bit plane 5
reg [63:0] bpl6dat; // buffer register for bit plane 6
reg [63:0] bpl7dat; // buffer register for bit plane 5
reg [63:0] bpl8dat; // buffer register for bit plane 6
reg load; // bpl1dat written => load shif registers
reg [7:0] extra_delay_f0; // extra delay when not alligned ddfstart
reg [7:0] extra_delay_f12;
reg [7:0] extra_delay_f3;
reg [7:0] extra_delay_r;
reg [7:0] pf1h; // playfield 1 horizontal scroll
reg [7:0] pf2h; // playfield 2 horizontal scroll
reg [7:0] pf1h_del; // delayed playfield 1 horizontal scroll
reg [7:0] pf2h_del; // delayed playfield 2 horizontal scroll
//--------------------------------------------------------------------------------------
// horizontal scroll depends on horizontal position when BPL0DAT in written
// visible display scroll is updated on fetch boundaries
// increasing scroll value during active display inserts blank pixels
always @(hpos)
case (hpos[3:2])
2'b00 : extra_delay_f0 = 8'b00_0000_00;
2'b01 : extra_delay_f0 = 8'b00_1100_00;
2'b10 : extra_delay_f0 = 8'b00_1000_00;
2'b11 : extra_delay_f0 = 8'b00_0100_00;
endcase
always @(hpos)
case (hpos[4:3])
2'b00 : extra_delay_f12 = 8'b00_0000_00;
2'b01 : extra_delay_f12 = 8'b01_1000_00;
2'b10 : extra_delay_f12 = 8'b01_0000_00;
2'b11 : extra_delay_f12 = 8'b00_1000_00;
endcase
always @(hpos)
case (hpos[5:4])
2'b00 : extra_delay_f3 = 8'b00_0000_00;
2'b01 : extra_delay_f3 = 8'b11_0000_00;
2'b10 : extra_delay_f3 = 8'b10_0000_00;
2'b11 : extra_delay_f3 = 8'b01_0000_00;
endcase
always @ (posedge clk) begin
if (clk7_en) begin
if (load) extra_delay_r <= #1 (fmode[1:0] == 2'b00) ? extra_delay_f0 : (fmode[1:0] == 2'b11) ? extra_delay_f3 : extra_delay_f12;
end
end
//playfield 1 effective horizontal scroll
always @(posedge clk)
if (clk7_en) begin
if (load)
pf1h <= {bplcon1[11:10],bplcon1[3:0],bplcon1[9:8]};
end
always @(posedge clk)
if (clk7_en) begin
pf1h_del <= pf1h + extra_delay_r;
end
//playfield 2 effective horizontal scroll
always @(posedge clk)
if (clk7_en) begin
if (load)
pf2h <= {bplcon1[15:14],bplcon1[7:4],bplcon1[13:12]};
end
always @(posedge clk)
if (clk7_en) begin
pf2h_del <= pf2h + extra_delay_r;
end
//writing bplcon1 register : horizontal scroll codes for even and odd bitplanes
always @(posedge clk)
if (clk7_en) begin
if (reset)
bplcon1 <= #1 16'h3300;
if ((reg_address_in[8:1] == BPLCON1[8:1]))
bplcon1 <= #1 aga ? data_in[15:0] : {2'b00,2'b11,2'b00,2'b11,data_in[7:0]};
end
// fmode
always @ (posedge clk) begin
if (clk7_en) begin
if (reset)
fmode <= #1 16'h0000;
else if (aga && (reg_address_in[8:1] == FMODE[8:1]))
fmode <= #1 data_in;
end
end
reg [47:0] chip48_fmode=0;
always @ (*) begin
case (fmode[1:0])
2'b11 : chip48_fmode[47:0] = chip48[47:0];
2'b10,
2'b01 : chip48_fmode[47:0] = {chip48[47:32], 32'h00000000};
default : chip48_fmode[47:0] = 48'h000000000000;
endcase
end
//--------------------------------------------------------------------------------------
//bitplane buffer register for plane 1
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL1DAT[8:1])
bpl1dat <= {data_in,chip48_fmode};
end
//bitplane buffer register for plane 2
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL2DAT[8:1])
bpl2dat <= {data_in,chip48_fmode};
end
//bitplane buffer register for plane 3
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL3DAT[8:1])
bpl3dat <= {data_in,chip48_fmode};
end
//bitplane buffer register for plane 4
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL4DAT[8:1])
bpl4dat <= {data_in,chip48_fmode};
end
//bitplane buffer register for plane 5
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL5DAT[8:1])
bpl5dat <= {data_in,chip48_fmode};
end
//bitplane buffer register for plane 6
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL6DAT[8:1])
bpl6dat <= {data_in,chip48_fmode};
end
//bitplane buffer register for plane 7
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL7DAT[8:1])
bpl7dat <= {data_in,chip48_fmode};
end
//bitplane buffer register for plane 8
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1] == BPL8DAT[8:1])
bpl8dat <= {data_in,chip48_fmode};
end
//generate load signal when plane 1 is written
always @(posedge clk)
if (clk7_en) begin
load <= reg_address_in[8:1] == BPL1DAT[8:1] ? 1'b1 : 1'b0;
end
//--------------------------------------------------------------------------------------
//instantiate bitplane 1 parallel to serial converters, this plane is loaded directly from bus
denise_bitplane_shifter bplshft1
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl1dat),
.scroll(pf1h_del),
.out(bpldata[1])
);
//instantiate bitplane 2 to 6 parallel to serial converters, (loaded from buffer registers)
denise_bitplane_shifter bplshft2
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl2dat),
.scroll(pf2h_del),
.out(bpldata[2])
);
denise_bitplane_shifter bplshft3
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl3dat),
.scroll(pf1h_del),
.out(bpldata[3])
);
denise_bitplane_shifter bplshft4
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl4dat),
.scroll(pf2h_del),
.out(bpldata[4])
);
denise_bitplane_shifter bplshft5
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl5dat),
.scroll(pf1h_del),
.out(bpldata[5])
);
denise_bitplane_shifter bplshft6
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl6dat),
.scroll(pf2h_del),
.out(bpldata[6])
);
denise_bitplane_shifter bplshft7
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl7dat),
.scroll(pf1h_del),
.out(bpldata[7])
);
denise_bitplane_shifter bplshft8
(
.clk(clk),
.clk7_en(clk7_en),
.c1(c1),
.c3(c3),
.load(load),
.hires(hires),
.shres(shres),
.fmode(fmode[1:0]),
.data_in(bpl8dat),
.scroll(pf2h_del),
.out(bpldata[8])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int pos[100005]; pair<int, int> tree[100005]; bool func(pair<int, int> x, pair<int, int> y) { return (x.first) < (y.first); } int main() { int n; for (int i = 1; i < 100005; i++) { pos[i] = 2e9 + 1000; } pos[0] = -2e9; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d , &tree[i].first, &tree[i].second); } sort(tree, tree + n, func); int mx = 0, g; for (int i = 0; i < n; i++) { if (i != 0 && tree[i].first - tree[i].second <= tree[i - 1].first) { } else { g = lower_bound(pos, pos + n, tree[i].first - tree[i].second) - pos; pos[g] = min(pos[g], tree[i].first); mx = max(mx, g); } if (i != n - 1 && tree[i].first + tree[i].second >= tree[i + 1].first) { } else { g = lower_bound(pos, pos + n, tree[i].first) - pos; pos[g] = min(pos[g], tree[i].first + tree[i].second); mx = max(mx, g); } } printf( %d , mx); } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; if (a < b) swap(a, b); cout << b << << (a - b) / 2 << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 3; const long long MOD = 1e9 + 7; const long long INF = 2e9; const int fullmask = (1 << 10) - 1; long long fpow(int n, int p) { if (!p) return 1; if (p == 1) return n; long long tmp = fpow(n, p / 2); if (p & 1) return tmp * tmp % MOD * n % MOD; return tmp * tmp % MOD; } long long Hash[10][10]; int k, n, m, u, v, w, c[10], ans; vector<pair<int, int> > g[N]; void solve(int id) { if (id > k) { long long op = 0; for (int i = 1; i <= k; i++) op += Hash[i][c[i]], op %= MOD; if (op == ((fpow(2, n + 1) - 2 + MOD) % MOD)) ans++; return; } for (int i = 1; i <= id; i++) { c[id] = i; solve(id + 1); } } void process() { cin >> n >> m >> k; for (int i = 1; i <= m; i++) { cin >> u >> v >> w; g[u].push_back(pair<int, int>(w, v)); } for (int i = 1; i <= n; i++) sort(g[i].begin(), g[i].end()); for (int i = 1; i <= n; i++) { int deg = g[i].size(); for (int j = 1; j <= deg; j++) { int v = g[i][j - 1].second; Hash[deg][j] += fpow(2, v); Hash[deg][j] %= MOD; } } solve(1); cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(); process(); } |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous DDR input
*/
module ssio_ddr_in #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q1,
output wire [WIDTH-1:0] output_q2
);
wire clk_int;
wire clk_io;
generate
if (TARGET == "XILINX") begin
// use Xilinx clocking primitives
if (CLOCK_INPUT_STYLE == "BUFG") begin
// buffer RX clock
BUFG
clk_bufg (
.I(input_clk),
.O(clk_int)
);
// pass through RX clock to logic and input buffers
assign clk_io = clk_int;
assign output_clk = clk_int;
end else if (CLOCK_INPUT_STYLE == "BUFR") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to logic
BUFR #(
.BUFR_DIVIDE("BYPASS")
)
clk_bufr (
.I(clk_int),
.O(output_clk),
.CE(1'b1),
.CLR(1'b0)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO2") begin
// pass through RX clock to input buffers
BUFIO2 #(
.DIVIDE(1),
.DIVIDE_BYPASS("TRUE"),
.I_INVERT("FALSE"),
.USE_DOUBLER("FALSE")
)
clk_bufio (
.I(input_clk),
.DIVCLK(clk_int),
.IOCLK(clk_io),
.SERDESSTROBE()
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end
end else begin
// pass through RX clock to input buffers
assign clk_io = input_clk;
// pass through RX clock to logic
assign clk_int = input_clk;
assign output_clk = clk_int;
end
endgenerate
iddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(WIDTH)
)
data_iddr_inst (
.clk(clk_io),
.d(input_d),
.q1(output_q1),
.q2(output_q2)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21bai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_V |
//--------------------------------------------------------------------------
// --
// OneWireMaster --
// A synthesizable 1-wire master peripheral --
// Copyright 1999-2005 Dallas Semiconductor Corporation --
// --
//--------------------------------------------------------------------------
// --
// Purpose: Provides timing and control of Dallas 1-wire bus --
// through a memory-mapped peripheral --
// File: clk_prescaler.v --
// Date: February 1, 2005 --
// Version: v2.100 --
// Authors: Rick Downs and Charles Hill, --
// Dallas Semiconductor Corporation --
// --
// Note: This source code is available for use without license. --
// Dallas Semiconductor is not responsible for the --
// functionality or utility of this product. --
// --
// REV: Significant changes to improve synthesis - English --
// Ported to Verilog - Sandelin --
//--------------------------------------------------------------------------
module clk_prescaler(
CLK, CLK_EN, div_1, div_2, div_3, MR, pre_0, pre_1, clk_1us);
input CLK;
input CLK_EN; // enables the divide chain
input div_1; // divider select bit 1
input div_2; // divider select bit 2
input div_3; // divider select bit 3
input MR;
input pre_0; // prescaler select bit 0
input pre_1; // prescaler select bit 1
output clk_1us; // OD, STD mode fsm clock
wire CLK;
wire MR;
wire pre_0;
wire pre_1;
wire div_1;
wire div_2;
wire div_3;
wire clk_prescaled; // prescaled clock output
// reg clk_1us; // 1us timebase for 1-wire STD and OD trans
wire clk_1us; // 1us timebase for 1-wire STD and OD trans
reg clk_div; // divided clk for hdrive
reg en_div; // enable use of divided clk for hdrive
reg clk_prescaled_reg;
reg [6:0] div_cnt;
reg [2:0] ClkPrescale;
parameter [2:0] s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100,
s5=3'b101, s6=3'b110;
//--------------------------------------------------------------------------
// Clock Prescaler
//--------------------------------------------------------------------------
wire rst_clk = MR || !CLK_EN;
always @(posedge rst_clk or posedge CLK)
if(rst_clk)
ClkPrescale <= s0;
else
case(ClkPrescale)
s0: ClkPrescale <= s1;
s1: ClkPrescale <= s2;
s2: if(pre_0 && !pre_1)
ClkPrescale <= s0;
else
ClkPrescale <= s3;
s3: ClkPrescale <= s4;
s4: if(!pre_0 && pre_1)
ClkPrescale <= s0;
else
ClkPrescale <= s5;
s5: ClkPrescale <= s6;
s6: ClkPrescale <= s0;
default: ClkPrescale<=s0;
endcase
reg en_clk;
//
// Create prescaled clock
//
always @(posedge MR or posedge CLK)
if (MR)
clk_prescaled_reg<=1;
else
clk_prescaled_reg <= (!ClkPrescale[0] && !ClkPrescale[1]
&& !ClkPrescale[2]);
//assign clk_prescaled = (!pre_0 && !pre_1 && CLK_EN)?CLK:clk_prescaled_reg;
always @(posedge MR or negedge CLK)
if (MR)
en_clk <= 1'b1;
else
en_clk <= CLK_EN && ((!pre_0 && !pre_1) || (ClkPrescale[2:0] == 3'b000));
assign clk_prescaled = en_clk & CLK;
//--------------------------------------------------------------------------
// Clock Divider
// using clk_prescaled as its input, this divide-by-2 chain does the
// other clock division
//--------------------------------------------------------------------------
always @(posedge MR or posedge CLK)
if (MR)
div_cnt <= 7'h00;
else if (en_clk)
div_cnt <= div_cnt + 1;
reg clk_1us_en;
always @(posedge MR or negedge CLK)
if (MR)
clk_1us_en <= 1'b1;
else
case ({div_3, div_2, div_1})
3'b000 : clk_1us_en <= CLK_EN;
3'b001 : clk_1us_en <= ~div_cnt[0];
3'b010 : clk_1us_en <= (div_cnt[1:0] == 2'h1);
3'b011 : clk_1us_en <= (div_cnt[2:0] == 3'h3);
3'b100 : clk_1us_en <= (div_cnt[3:0] == 4'h7);
3'b101 : clk_1us_en <= (div_cnt[4:0] == 5'h0f);
3'b110 : clk_1us_en <= (div_cnt[5:0] == 6'h1f);
3'b111 : clk_1us_en <= (div_cnt[6:0] == 7'h3f);
endcase
reg clk_1us_en_d1;
// always @(clk_1us_en or en_clk or CLK)
// assign clk_1us_gen <= clk_1us_en && en_clk && CLK;
//negedge CLK to match clk_1us_en procedure above
always @(negedge CLK)
if(!en_clk)
clk_1us_en_d1 <= 1'b0;
else
clk_1us_en_d1 <= clk_1us_en;
//Pulse generator - only stays high 1 CLK cycle
assign clk_1us = (!clk_1us_en_d1 && clk_1us_en);
endmodule // clk_prescaler
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10; const int INF = int(1e9); int main() { int n; char str1[maxn], str2[maxn]; while (~scanf( %d , &n)) { scanf( %s %s , str1, str2); int h, m; h = (str1[0] - 0 ) * 10 + str1[1] - 0 ; m = (str2[0] - 0 ) * 10 + str2[1] - 0 ; int ans = 0; while (h % 10 != 7 && m % 10 != 7) { if (m - n < 0) { m = m - n + 60; if (h == 0) h = 23; else h--; } else m = m - n; ans++; } printf( %d n , ans); } return 0; } |
//-----------------------------------------------------------------------------
// File : spi_master.v
// Creation date : 10.04.2017
// Creation time : 15:38:03
// Description : A minimalistic example for SPI master IP-XACT document.
// Created by : TermosPullo
// Tool : Kactus2 3.4.20 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:template:spi_master:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/template/spi_master/1.0/spi_master.1.0.xml
//-----------------------------------------------------------------------------
module spi_master(
// Interface: master_if
input data_in,
output clk_out,
output reg data_out,
output reg slave_select1_out,
output reg slave_select2_out,
output reg slave_select3_out,
// These ports are not in any interface
input clk_in, // The mandatory clock, as this is synchronous logic.
input rst_in // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam BYTE_SIZE = 8; // How many bits are transferred per transaction
localparam BYTE_INDEX_SIZE = $clog2(BYTE_SIZE); // How many bits are needed to index a byte.
// Input and output bytes.
reg [BYTE_SIZE-1:0] data_recv;
reg [BYTE_SIZE-1:0] data_send;
// Used to iterate through the bytes.
reg [BYTE_INDEX_SIZE-1:0] send_iterator;
reg [BYTE_INDEX_SIZE-1:0] recv_iterator;
// The state.
reg [1:0] state;
// The available states.
parameter [1:0]
S_WAIT = 2'd0,
S_TRANSFER = 2'd1,
S_DEASSERT = 2'd2;
assign clk_out = clk_in;
always @(posedge clk_in or posedge rst_in) begin
if(rst_in == 1'b1) begin
state <= S_WAIT; // Wait signals from the masters at reset.
data_recv <= 0;
data_send <= 8'h55;
data_out <= 1'bz;
send_iterator <= 0;
recv_iterator <= 0;
// These are active low -> Initiallty high.
slave_select1_out <= 1;
slave_select2_out <= 1;
slave_select3_out <= 1;
end
else begin
if (state == S_WAIT) begin
slave_select1_out <= 0;
state <= S_TRANSFER;
end
else if (state == S_TRANSFER) begin
data_out <= data_send[send_iterator];
if (send_iterator > 0 && recv_iterator < BYTE_SIZE-1) begin
data_recv[recv_iterator] <= data_in;
recv_iterator = recv_iterator +1;
end
if (recv_iterator >= BYTE_SIZE-1) begin
state <= S_DEASSERT;
end
else
send_iterator <= send_iterator + 1;
end
else if (state == S_DEASSERT) begin
data_recv[BYTE_SIZE-1] <= data_in;
state <= S_WAIT;
slave_select1_out <= 1;
data_out <= 1'bz;
send_iterator <= 0;
recv_iterator <= 0;
@(posedge clk_in);
end
else
$display("ERROR: Unkown state: %d", state);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int r, c, x = 0, y, z; cin >> r >> c; while (r != 0) { if (r % 2 != 0) { for (int i = 0; i < c; i++) { cout << # ; } cout << n ; } else { if (!x) { for (int i = 0; i < c - 1; i++) { cout << . ; } cout << # ; cout << n ; x++; } else { cout << # ; for (int i = 0; i < c - 1; i++) { cout << . ; } cout << n ; x = 0; } } r = r - 1; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline string tostring(const T &x) { ostringstream os; os << x; return os.str(); } inline int toint(const string &s) { istringstream is(s); int x; is >> x; return x; } inline int todecimal(string s) { int a = 0; for (int i = 0; i < s.size(); i++) a = 2 * a + (s[i] - 0 ); return a; } inline string tobinary(int a) { string s; while (a != 0) { s = (char)(a % 2 + 0 ) + s; a >>= 1; } return s; } template <typename T> inline T sqr(T x) { return x * x; } template <typename T> T gcd(T a, T b) { return (b == 0) ? abs(a) : gcd(b, a % b); } inline int isvowel(char c) { if (c == a || c == e || c == i || c == o || c == u ) return 1; return 0; } inline int isprime(int a) { for (int i = 2; i * i <= a; i++) if (!(a % i)) return 0; return 1; } inline void inp(int &n) { n = 0; int ch = getchar(); int sign = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) sign = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar(); n = n * sign; } const int dx4[4] = {0, 0, 1, -1}; const int dy4[4] = {1, -1, 0, 0}; const int dx8[8] = {0, 0, 1, 1, 1, -1, -1, -1}; const int dy8[8] = {1, -1, 0, 1, -1, 1, 0, -1}; class node { public: int x, y, z; node(int a, int b, int c) { x = a; y = b; z = c; } }; bool operator<(const node &a, const node &b) { return a.x > b.x; } bool compare(const node &a, const node &b) { return a.x < b.x; } int n, m; void solve() { cout << n + m - 1 << endl; for (int i = 0; i < m; i++) { cout << 1 << << i + 1 << endl; } for (int i = 0; i < n - 1; i++) { cout << i + 2 << << 1 << endl; } } void input() { cin >> n >> m; } int main() { int testcase = 1; for (int i = 0; i < testcase; i++) { input(); solve(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int INFint = 2147483647; const long long INF = 9223372036854775807ll; const long long MOD = 1000000007ll; const long double EPS = 1e-9; int p[1000]; int a[1000]; int b[1000]; int cnt; void dfs(int v) { p[v] = 1; for (int i = 1; i <= cnt; i++) { if (!p[i]) { if ((a[v] > a[i] && a[v] < b[i]) || (b[v] > a[i] && b[v] < b[i])) dfs(i); } } } int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 0; i < n; i++) { int t, x, y; cin >> t >> x >> y; if (t == 1) { cnt++; a[cnt] = x; b[cnt] = y; } else { memset(p, 0, sizeof(p)); dfs(x); if (p[y]) { cout << YES << endl; } else cout << NO << endl; } } fprintf(stderr, nTIME = %lf n , 1.0 * clock() / CLOCKS_PER_SEC); return 0; } |
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : ;
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int u, v; cin >> u >> v; if (u > v) printf( NO n ); else if (u == v) printf( YES n ); else { int U = 0, V = 0, fail = 0; // (u) 1 0111 0111 -> 1 1010 0110 (v) // bit0: {0, 1, 2, 4, 5, 6, 8} -> bit1: {1, 2, 5, 7, 8} for (int i = 0; i < 30; i++) { U += u >> i & 1; V += v >> i & 1; fail |= U < V; } printf(fail ? NO n : YES n ); } } return 0; } /* 3 12 YES 6 9 NO */ |
/*
* Palette register file for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_palette_regs_fml (
input clk,
// VGA read interface
input [3:0] attr,
output reg [7:0] index,
// CPU interface
input [3:0] address,
input write,
output reg [7:0] read_data,
input [7:0] write_data
);
// Registers
reg [7:0] palette [0:15];
// Behaviour
// VGA read interface
always @(posedge clk) index <= palette[attr];
// CPU read interface
always @(posedge clk) read_data <= palette[address];
// CPU write interface
always @(posedge clk)
if (write) palette[address] <= write_data;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_TB_V
`define SKY130_FD_SC_LP__DFBBN_TB_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfbbn.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__dfbbn dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_TB_V
|
#include <bits/stdc++.h> using namespace std; const int maxlongint = 2147483647; const int inf = 1000000000; int main() { int a, b, c, d, e, f, ans = 0, k = -1, n1, n2; cin >> a >> b >> c >> d >> e >> f; ans = a * b + c * d + e * f; for (n1 = 1; n1 <= 1000; n1++) if (n1 * n1 == ans) { k = n1; break; } if (k == -1) { cout << -1 << endl; return 0; } if (b == k) swap(a, b); if (d == k) swap(c, d); if (f == k) swap(e, f); if (a == k && c == k && e == k) { cout << k << endl; for (n1 = 1; n1 <= b; n1++) { for (n2 = 1; n2 <= k; n2++) putchar( A ); printf( n ); } for (n1 = 1; n1 <= d; n1++) { for (n2 = 1; n2 <= k; n2++) putchar( B ); printf( n ); } for (n1 = 1; n1 <= f; n1++) { for (n2 = 1; n2 <= k; n2++) putchar( C ); printf( n ); } return 0; } int sd = 0; if (c == k) { sd = 1; swap(a, c); swap(b, d); } else if (e == k) { sd = 2; swap(a, e); swap(b, f); } if (a != k) { cout << -1 << endl; return 0; } if (d == k - b) swap(c, d); if (f == k - b) swap(e, f); if (c != k - b || e != k - b) { cout << -1 << endl; return 0; } { cout << k << endl; for (n1 = 1; n1 <= b; n1++) { for (n2 = 1; n2 <= k; n2++) putchar( A + sd); printf( n ); } for (n1 = 1; n1 <= k - b; n1++) { if (sd != 1) for (n2 = 1; n2 <= d; n2++) putchar( B ); else for (n2 = 1; n2 <= d; n2++) putchar( A ); if (sd != 2) for (n2 = 1; n2 <= f; n2++) putchar( C ); else for (n2 = 1; n2 <= f; n2++) putchar( A ); printf( n ); } return 0; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n, m; vector<vector<char>> grid; pair<int, int> start, endloc; int memo[1000][1000][4]; bool dfs(pair<int, int> loc, int turns, int dir) { if (loc == endloc) return true; memo[loc.first][loc.second][dir] = turns; vector<pair<int, int>> next; next.push_back({loc.first - 1, loc.second}); next.push_back({loc.first + 1, loc.second}); next.push_back({loc.first, loc.second - 1}); next.push_back({loc.first, loc.second + 1}); for (int i = 0; i < 4; i++) { pair<int, int> nextLoc = next[i]; if (i != dir && turns == 0) continue; if (nextLoc.first < 0 || nextLoc.first >= n) continue; if (nextLoc.second < 0 || nextLoc.second >= m) continue; if (grid[nextLoc.first][nextLoc.second] == * ) continue; int turnDiff = 0; if (i != dir) turnDiff = 1; if (memo[nextLoc.first][nextLoc.second][i] >= turns - turnDiff) continue; if (dfs(nextLoc, turns - turnDiff, i)) return true; } return false; } int main() { ios::sync_with_stdio(0); cin >> n >> m; memset(memo, -1, sizeof memo); grid = vector<vector<char>>(n, vector<char>(m, )); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char curr; cin >> curr; if (curr == S ) { start = {i, j}; } else if (curr == T ) { endloc = {i, j}; } grid[i][j] = curr; } } for (int i = 0; i < 4; i++) { if (dfs(start, 2, i)) { cout << YES << endl; return 0; } } cout << NO << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog wrapper for lpflow_clkinvkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkinvkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: DE2 Music Synthesizer
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Joe Yang :| 10/25/2006 :| Initial Revision
// --------------------------------------------------------------------
/////////////////////////////////////////////
//// 2Channel-Music-Synthesizer /////
/////////////////////////////////////////////
/*******************************************/
/* KEY & SW List */
/* KEY[0]: I2C reset */
/* KEY[1]: Demo Sound repeat */
/* KEY[2]: Keyboard code Reset */
/* KEY[3]: Keyboard system Reset */
/* SW[0] : 0 Brass wave ,1 String wave */
/* SW[1] : 0 CH1_ON ,1 CH1_OFF */
/* SW[2] : 0 CH2_ON ,1 CH2_OFF */
/* SW[9] : 0 DEMO Sound ,1 KeyBoard Play */
/*******************************************/
module DE2_synthesizer (
//////////////////// Clock Input ////////////////////
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
//////////////////// Push Button ////////////////////
START_KEY1,
START_KEY2,
//////////////////// DPDT Switch ////////////////////
SW_MUTE,
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
TD_RESET, // TV Decoder Reset
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
//////////////////////// Push Button ////////////////////////
input START_KEY1;
input START_KEY2;
//////////////////////// DPDT Switch ////////////////////////
input SW_MUTE;
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
output TD_RESET; // TV Decoder Reset
////////////////////////////////////////////////////////////////////
assign TD_RESET = 1;
// I2C
wire I2C_END;
I2C_AV_Config u7 ( // Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( 1'b1 ),
.o_I2C_END ( I2C_END ),
// I2C Side
.I2C_SCLK ( I2C_SCLK ),
.I2C_SDAT ( I2C_SDAT )
);
// AUDIO SOUND
wire AUD_CTRL_CLK;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign AUD_XCK = AUD_CTRL_CLK;
// AUDIO PLL
VGA_Audio_PLL u1 (
.areset ( ~I2C_END ),
.inclk0 ( CLOCK_27 ),
.c1 ( AUD_CTRL_CLK )
);
// Music Synthesizer Block //
// TIME & CLOCK Generater //
reg [31:0]VGA_CLK_o;
wire keyboard_sysclk = VGA_CLK_o[11];
wire demo_clock1 = VGA_CLK_o[10];
wire demo_clock2 = VGA_CLK_o[18];
always @( posedge CLOCK_50 ) VGA_CLK_o = VGA_CLK_o + 1;
// DEMO SOUND //
// DEMO Sound (CH1) //
wire [7:0]demo_code1;
wire [7:0]demo_code2;
wire [7:0]demo_code;
assign demo_code = (START_KEY1 == 1'b0) ? demo_code1 : demo_code2;
demo_sound1 ticking1(
.clock ( demo_clock1 ),
.key_code( demo_code1 ),
.k_tr ( START_KEY1 )
);
demo_sound2 johncena(
.clock ( demo_clock2 ),
.key_code( demo_code2 ),
.k_tr ( START_KEY2 )
);
////////////Sound Select/////////////
wire [15:0]sound1;
wire sound_off1;
// Staff Display & Sound Output //
staff st1(
.scan_code1( demo_code ),
.sound1( sound1 ),
.sound_off1( sound_off1 )
);
// 2CH Audio Sound output -- Audio Generater //
adio_codec ad1 (
// AUDIO CODEC //
.oAUD_BCK ( AUD_BCLK ),
.oAUD_DATA( AUD_DACDAT ),
.oAUD_LRCK( AUD_DACLRCK ),
.iCLK_18_4( AUD_CTRL_CLK ),
// KEY //
.iRST_N( 1'b1 ),
.iSrc_Select( 2'b00 ),
// Sound Control //
.key1_on( ~SW_MUTE & sound_off1 ),//CH1 ON / OFF
.sound1( sound1 )// CH1 Freq
);
endmodule
|
/*
* Titor - System - Simple counter that rolls over at a specified value that can be chained with different radixes
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Radix_Counter
`else
`define INC_Radix_Counter
`timescale 1 ns / 100 ps
// Sean Moore
module Radix_Counter(
carry_in, carry_out, count,
reset,
clk
);
parameter RADIX = 0;
`include "definition/Definition.v"
input carry_in;
output carry_out;
output reg [WORD-1:0] count;
input reset;
input clk;
assign carry_out = (count == RADIX-1) && carry_in;
always @(posedge clk) begin
if(reset) count <= 0;
else if(carry_in && carry_out) count <= 0;
else if(carry_in) count <= count+1;
else count <= count;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, n, r, S, Z, s1, s2, s3, s4, s5, s6, s7, s8, x, y, z, m, j, l, k, t; long long a[500005]; long long b[300045]; long long c[300001]; long long d[100001]; long long e[101][101]; pair<long long, long long> aa[200001]; pair<long long, long long> bb[200001]; double h, w, u, v, uu, vv; string q1; string q2; string q3; string q4; string s; string q; string sq[50005]; string qs[3001]; map<string, long long> g; map<string, long long>::iterator it; cin >> n; for (i = 1; i <= 100; i++) { b[i] = 0; } for (l = 1; l <= n; l++) { cin >> m; for (i = 1; i <= m; i++) { cin >> x; b[x]++; } } for (i = 1; i <= 100; i++) { if (b[i] == n) cout << i << ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; while (scanf( %d , &n) == 1) { string s; cin >> s; s = # + s; bool used[n + 1]; memset(used, 0, sizeof used); int d[n + 1]; for (int i = 1; i <= n; i++) { scanf( %d , d + i); } int pos = 1; bool ok = false; while (!used[pos]) { used[pos] = true; if (s[pos] == < ) { pos -= d[pos]; } else { pos += d[pos]; } if (pos <= 0 || pos > n) { ok = true; break; } } if (ok) { puts( FINITE ); } else { puts( INFINITE ); } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DECAPKAPWR_BEHAVIORAL_PP_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__decapkapwr (
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int mxN1 = 1e5, mxN2 = 1 << 18, INF = 1e9; struct dat { int len = 0, max; vector<pair<int, int>> pref, suf; } tree[mxN2]; int n, q, qt; string ss[mxN1]; inline void cmb(dat &d, dat &a, dat &b) { d.len = a.len + b.len; d.max = max(a.max, b.max); for (int i1 = 0, i2 = 0; i1 < a.suf.size() - 1;) { if (a.suf[i1].first <= b.pref[i2].first) { d.max = max(a.suf[i1].first * (a.suf[i1].second + b.pref[i2].second + 1), d.max); ++i1; } else { d.max = max(b.pref[i2].first * (a.suf[i1].second + b.pref[i2].second + 1), d.max); ++i2; } } int i1 = 0, i2 = 0; d.pref.clear(); if (a.pref[0].second == a.len) for (; b.pref[i2].first < a.pref[0].first; ++i2) d.pref.push_back(make_pair(b.pref[i2].first, a.len + b.pref[i2].second)); for (; i1 < a.pref.size();) { if (a.pref[i1].first <= b.pref[i2].first) { d.pref.push_back( make_pair(a.pref[i1].first, a.pref[i1].second == a.len ? a.len + b.pref[i2].second : a.pref[i1].second)); ++i1; } else ++i2; } i1 = 0, i2 = 0; d.suf.clear(); if (b.suf[0].second == b.len) for (; a.suf[i2].first < b.suf[0].first; ++i2) d.suf.push_back(make_pair(a.suf[i2].first, b.len + a.suf[i2].second)); for (; i1 < b.suf.size();) { if (b.suf[i1].first <= a.suf[i2].first) { d.suf.push_back(make_pair(b.suf[i1].first, b.suf[i1].second == b.len ? b.len + a.suf[i2].second : b.suf[i1].second)); ++i1; } else ++i2; } } void bld(int l, int r, int i) { if (l == r) { int j = 0; for (; j < ss[l].size() && j < ss[l + 1].size() && ss[l][j] == ss[l + 1][j]; ++j) ; tree[i].len = 1; tree[i].max = max(j * 2, (int)max(ss[l].size(), ss[l + 1].size())); tree[i].pref = {make_pair(j, 1), make_pair(INF, 0)}; tree[i].suf = {make_pair(j, 1), make_pair(INF, 0)}; } else { int m = (l + r) / 2; bld(l, m, 2 * i); bld(m + 1, r, 2 * i + 1); cmb(tree[i], tree[2 * i], tree[2 * i + 1]); } } void upd(int i2, int i, int l, int r) { if (l == r) { int j = 0; for (; j < ss[l].size() && j < ss[l + 1].size() && ss[l][j] == ss[l + 1][j]; ++j) ; tree[i].max = max(j * 2, (int)max(ss[l].size(), ss[l + 1].size())); tree[i].pref[0].first = tree[i].suf[0].first = j; } else { int m = (l + r) / 2; if (i2 <= m) upd(i2, 2 * i, l, m); else upd(i2, 2 * i + 1, m + 1, r); cmb(tree[i], tree[2 * i], tree[2 * i + 1]); } } dat qry(int l2, int r2, int i, int l, int r) { if (l2 <= l && r <= r2) return tree[i]; dat res; int m = (l + r) / 2; bool lc = l2 <= m, rc = m < r2; if (lc && rc) { dat lr = qry(l2, r2, 2 * i, l, m), rr = qry(l2, r2, 2 * i + 1, m + 1, r); cmb(res, lr, rr); } else if (lc) res = qry(l2, r2, 2 * i, l, m); else res = qry(l2, r2, 2 * i + 1, m + 1, r); return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> q; for (int i = 0; i < n; ++i) cin >> ss[i]; if (n > 1) bld(0, n - 2, 1); while (q--) { cin >> qt; if (qt == 1) { int a, b; cin >> a >> b; --a, --b; cout << (a == b ? ss[a].size() : qry(a, b - 1, 1, 0, n - 2).max) << n ; } else { int x; cin >> x; --x; cin >> ss[x]; if (n > 1) { if (x) upd(x - 1, 1, 0, n - 2); upd(x, 1, 0, n - 2); } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for lpflow_isobufsrc with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
|
#include <bits/stdc++.h> long long memo[100005][205]; std::pair<long long, int> pre[100005]; int n; struct q4 { int s, t, d, pin; long long w; bool operator<(const q4& wx) const { return ((w > wx.w) || ((w == wx.w) && (d > wx.d))); } }; std::vector<q4> Q[100005]; std::multiset<q4> X; long long BALLIA(int z, int m) { if (m < 0) return 100000000000000001; else if (z > n) return 0; if (memo[z][m] != -1) return memo[z][m]; long long ans = 100000000000000001; if (pre[z] != std::make_pair(0LL, 0)) ans = std::min(pre[z].first + BALLIA(pre[z].second + 1, m), BALLIA(z + 1, m - 1)); else ans = BALLIA(z + 1, m); memo[z][m] = ans; return ans; } int main(void) { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); std::cout.tie(NULL); memset(memo, -1, sizeof(memo)); int m, k; std::cin >> n >> m >> k; for (int i = 1; i <= n; i++) pre[i] = std::make_pair(0LL, 0); for (int i = 1; i <= k; i++) { int s, t, d; long long w; std::cin >> s >> t >> d >> w; Q[s].push_back({s, t, d, 1, w}); Q[t + 1].push_back({s, t, d, -1, w}); } for (int i = 1; i <= n; i++) { for (auto u : Q[i]) { if (u.pin == 1) X.insert(u); else X.erase(X.find({u.s, u.t, u.d, 1, u.w})); } if (!X.empty()) pre[i] = std::make_pair((*X.begin()).w, (*X.begin()).d); else pre[i] = std::make_pair(0LL, 0); } long long ans = BALLIA(1, m); std::cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_1_V
`define SKY130_FD_SC_LP__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:10:52 08/30/2014
// Design Name:
// Module Name: lab4dpath
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab4dpath(x1,x2,x3,y,clk);
input [9:0] x1,x2,x3;
input clk;
output [9:0] y;
//mult12x12 input (a,b[11:0] output (p[23:0])
wire [11:0] s2, v1, v2, v3;
wire [23:0] t1, t2, t3;
//dff io ports
reg [9:0] d1, d2, d3, q1, q2, q3;
//input dff
always @(posedge clk) begin
d1 <= x1;
d2 <= x2;
d3 <= x3;
end
//output dff
always @(posedge clk) begin
q1 <= d1;
q2 <= d2;
q3 <= d3;
end
assign v1 = {q1, 2'b00};
assign v2 = {q2, 2'b00};
assign v3 = {q3, 2'b00};
mult12x12l2 i1 (.clk(clk), .a(12'b110000000000), .b(v1), .p(t1));
mult12x12l2 i2 (.clk(clk), .a(12'b010100000000), .b(v2), .p(t2));
mult12x12l2 i3 (.clk(clk), .a(12'b110000000000), .b(v3), .p(t3));
assign s2 = t1[22:11] + t2[22:11] + t3[22:11];
//assign y to upper bits of s2
assign y = s2[11:2];
endmodule
|
#include <bits/stdc++.h> int ar[100000]; using namespace std; int main() { int n; cin >> n; int c = 0, ans = 0; int r; for (int i = 0; i < 2 * n; i++) { cin >> r; if (ar[r]) { ar[r] = 0; c--; } else { c++; ar[r] = 1; } if (ans < c) ans = c; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vector<int>>; using pii = pair<int, int>; constexpr int N = 300001; struct Ed { int u, v; bool s; }; vector<pii> g[N], t[N]; int d[N], low[N], biconn[N]; bool scored[N], vis[N]; int tim = 1, compno = 1; pii p[N]; void dfs(int u, int p) { low[u] = d[u] = tim++; for (const auto& pr : g[u]) { if (pr.first == p) continue; if (d[pr.first] != 0) { low[u] = min(low[u], d[pr.first]); } else { dfs(pr.first, u); low[u] = min(low[u], low[pr.first]); } } } void comp(int u, int p, int c) { if (biconn[u] != 0) return; if (low[u] == d[u]) c = ++compno; biconn[u] = c; for (const auto& pr : g[u]) { if (pr.second && biconn[pr.first] == c) scored[c] = true; if (pr.first == p && biconn[p] != c) { t[c].push_back({biconn[p], pr.second}); t[biconn[p]].push_back({c, pr.second}); } else if (biconn[pr.first] == 0) comp(pr.first, u, c); } } void solve() { int n, m, x, y, z, a, b; cin >> n >> m; while (m--) { cin >> x >> y >> z; g[x].push_back({y, z}); g[y].push_back({x, z}); } cin >> a >> b; dfs(a, -1); comp(a, -1, 1); a = biconn[a]; b = biconn[b]; queue<int> q; q.push(a); vis[a] = true; while (!q.empty()) { int u = q.front(); q.pop(); for (const auto& v : t[u]) if (!vis[v.first]) { p[v.first] = {u, v.second}; q.push(v.first); vis[v.first] = true; } } bool ok = scored[a]; while (!ok && b != a) { if (scored[b] || p[b].second) ok = true; b = p[b].first; } cout << (ok ? YES n : NO n ); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> #pragma GCC target( fma ) #pragma GCC optimize( unroll-loops,-Ofast ) using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long a[500005]; int n; set<long long> buck[1000]; long long c[1000]; void fix(int v) { int l = v * 700; int r = (v + 1) * 700; r = min(r, n); buck[v].clear(); for (int i = l; i < r; ++i) { a[i] += c[v]; buck[v].insert(a[i]); } c[v] = 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int q; cin >> n >> q; for (int i = 0; i < n; i++) { cin >> a[i]; buck[i / 700].insert(a[i]); } while (q--) { int t, l, r, x; cin >> t; if (t == 1) { cin >> l >> r >> x; --l; --r; if (l / 700 == r / 700) { for (int i = l; i <= r; i++) a[i] += x; fix(r / 700); continue; } if (l % 700 != 0) { for (; l % 700 != 0; ++l) { a[l] += x; } fix(l / 700 - 1); } l /= 700; if (r % 700 != 700 - 1) { for (; r % 700 != 700 - 1; --r) { a[r] += x; } fix(r / 700 + 1); } r /= 700; for (; l <= r; l++) c[l] += x; } else { cin >> x; l = r = -1; for (int i = 0; i <= n / 700; ++i) { if (buck[i].count(x - c[i])) { for (int j = i * 700; 1; ++j) { if (a[j] == x - c[i]) { l = j; break; } } break; } } for (int i = n / 700; i >= 0; --i) { if (buck[i].count(x - c[i])) { for (int j = i * 700 + 700 - 1; 1; --j) { if (a[j] == x - c[i]) { r = j; break; } } break; } } if (l == -1) { cout << -1 << n ; } else { cout << r - l << n ; } } } } |
#include <bits/stdc++.h> using namespace std; signed solve(); signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int tests = 1; while (tests--) solve(); return 0; } signed solve() { int n, k; cin >> n >> k; if (n <= 1ll * k * (k - 1)) { cout << YES n ; for (int i = 0; i < n; ++i) { cout << (i % k) + 1 << << (i / k + i % k + 1) % k + 1 << n ; } } else { cout << NO n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n; int x[100005], y[100005], num_, num; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; if (x[i] > 0) { num++; } else { num_++; } } if (num == 1 || num_ == 1 || num == 0 || num_ == 0) { cout << Yes << endl; return 0; } else { cout << No << endl; return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 100005; template <typename T> void readv(vector<T>& v, int n) { for (int i = 0; i < n; ++i) { T tmp; cin >> tmp; v.push_back(tmp); } } struct cmp { bool operator()(const pair<int, int>& i1, const pair<int, int>& i2) const { int sign = (i1.second - i1.first) - (i2.second - i2.first); if (sign != 0) return sign > 0; return i1.first > i2.first; } }; set<pair<int, int>, cmp> intervals; map<int, pair<int, int> > ileft, iright; void insert_intvl(const pair<int, int>& intvl) { intervals.insert(intvl); ileft[intvl.second + 1] = intvl; iright[intvl.first - 1] = intvl; } void erase_intvl(const pair<int, int>& intvl) { intervals.erase(intvl); ileft.erase(intvl.second + 1); iright.erase(intvl.first - 1); } map<int, int> points; class node { public: node() : left(0), right(0), size(0) {} node *left, *right; int size; }; node root; void add_node(node* nd, int x, int shift) { nd->size++; if (shift < 0) { return; } if ((x & (1 << shift)) == 0) { if (!nd->left) { nd->left = new node; } add_node(nd->left, x, shift - 1); } else { if (!nd->right) { nd->right = new node; } add_node(nd->right, x, shift - 1); } } void remove_node(node* nd, int x, int shift) { nd->size -= 1; if (shift < 0) return; if ((x & (1 << shift)) == 0) { remove_node(nd->left, x, shift - 1); } else { remove_node(nd->right, x, shift - 1); } } int query_tree(node* nd, int b, int e, int l, int r, int shift) { if ((e < l) || (b > r)) { return 0; } if ((b >= l) && (e <= r)) { return nd->size; } int mid = (b + e) / 2; int s1 = nd->left ? query_tree(nd->left, b, mid, l, r, shift - 1) : 0; int s2 = nd->right ? query_tree(nd->right, mid + 1, e, l, r, shift - 1) : 0; return s1 + s2; } const int BITS = 30; void add_emp(int e, int p) { add_node(&root, p, BITS - 1); points[e] = p; } void remove_emp(int e) { remove_node(&root, points[e], BITS - 1); points.erase(e); } int query(int l, int r) { return query_tree(&root, 0, (1 << BITS) - 1, l, r, BITS); } int main(int argc, char** argv) { int n, q; cin >> n >> q; intervals.insert(make_pair(1, n)); for (int i = 0; i < q; ++i) { int e; cin >> e; if (e == 0) { int l, r; cin >> l >> r; cout << query(l, r) << endl; } else { if (points.count(e) == 0) { pair<int, int> longest = *intervals.begin(); erase_intvl(longest); int mid = (longest.first + longest.second + 1) / 2; if (longest.first <= (mid - 1)) { insert_intvl(make_pair(longest.first, mid - 1)); } if ((mid + 1) <= longest.second) { insert_intvl(make_pair(mid + 1, longest.second)); } add_emp(e, mid); } else { int pe = points[e]; pair<int, int> intvl = make_pair(pe, pe); if (ileft.count(pe) == 1) { intvl.first = ileft[pe].first; erase_intvl(ileft[pe]); } if (iright.count(pe) == 1) { intvl.second = iright[pe].second; erase_intvl(iright[pe]); } insert_intvl(intvl); remove_emp(e); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int cnt(long long int x) { long long int ans = 0; while (x) { x /= 2; ans++; } return ans; } int main() { int t; cin >> t; while (t--) { long long int d, m; cin >> d >> m; long long int temp = cnt(d) - 1; long long int ans = d - pow(2, temp) + 2; for (long long int i = temp - 1; i >= 0; i--) { ans = ans * (pow(2, i) + 1); ans %= m; } ans = (ans - 1) % m; if (ans < 0) ans = m + ans; cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100050, maxm = 5050; int n, m, K, p, h[maxn], a[maxn]; long long hh[maxn], ans; long long tim[maxn]; int cnt[maxm]; bool judg(long long x) { int i, j; long long tis = 0; for (i = 0; i < m; i++) cnt[i] = 0; for (i = 0; i < n; i++) tis += tim[i] = max(0LL, (hh[i] - x - 1 + p) / p); if (tis > K * m) return 0; for (i = 0; i < n; i++) { int now = 0, h0 = h[i]; for (j = 0; j < tim[i]; j++) { long long t = h0 + 1LL * (m - now) * a[i] - 1LL * (tim[i] - j - 1) * p - x, tn; if (h0 < t) tn = now + (t - h0 - 1) / a[i] + 1; else tn = now; if (tn >= m) return 0; h0 = max(0LL, h0 + (tn - now) * a[i] - p); cnt[now = tn]++; } } for (i = m - 1; i >= 0; i--) { cnt[i] += cnt[i + 1]; if (cnt[i] > (m - i) * K) return 0; } return 1; } int main() { int i, j; long long l = 0, r = 0, mid; scanf( %d%d%d%d , &n, &m, &K, &p); for (i = 0; i < n; i++) scanf( %d%d , &h[i], &a[i]), r = max(r, hh[i] = h[i] + 1LL * a[i] * m); while (l < r) { mid = (l + r) >> 1; if (judg(mid)) r = mid; else l = mid + 1; } ans = l; printf( %I64d n , ans); return 0; } |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
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