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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 5; template <class T> void read(vector<T> &arr) { for (auto &x : arr) cin >> x; } template <class T> void read(T &x) { cin >> x; } template <class T> void write(vector<T> &arr) { for (auto x : arr) cout << x << ; cout << n ; } template <class T> void write(vector<vector<T>> &arr) { for (auto &x : arr) { for (auto &y : x) cout << y << ; cout << n ; } } template <class T> void write(T &x) { cout << x; } void solve() { long long n; cin >> n; vector<long long> arr(n); read(arr); long long ans = 0; bool isStarted = false; for (long long i = 0; i < n; ++i) { if (arr[i] == 1) { isStarted = true; } if (arr[i] == 0 && isStarted) ans++; } for (long long i = n - 1; i > -1; --i) { if (arr[i] == 1) break; if (arr[i] == 0) ans--; } cout << ans << n ; } int32_t main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long t = 1; cin >> t; while (t--) { solve(); } return 0; } |
module sgpr_comparator
(/*AUTOARG*/
// Outputs
result,
// Inputs
retired_operand_mask, retired_operand_addr, src1_gpr_info,
src4_gpr_info, dst1_gpr_info, src2_gpr_info, src3_gpr_info,
dst2_gpr_info
);
wire src1_cmp_en, src2_cmp_en, src3_cmp_en, src4_cmp_en,
dst1_cmp_en, dst2_cmp_en;
input [3:0] retired_operand_mask;
wire [3:0] src1_mask, src4_mask, dst1_mask;
wire [2:0] src2_mask, src3_mask, dst2_mask;
input [`SGPR_ADDR_LENGTH-1:0] retired_operand_addr;
input [13:0] src1_gpr_info, src4_gpr_info, dst1_gpr_info;
input [12:0] src2_gpr_info, src3_gpr_info, dst2_gpr_info;
output [`ISSUE_GPR_RD_BITS_LENGTH-1:0] result;
wire [3:0] src1_cmp_result, src4_cmp_result, dst1_cmp_result;
wire [1:0] src2_cmp_result, src3_cmp_result, dst2_cmp_result;
// Compare only valid sgprs
assign src1_cmp_en = get_valid_sgpr(src1_gpr_info[11:0]);
assign src2_cmp_en = get_valid_sgpr(src2_gpr_info[11:0]);
assign src3_cmp_en = get_valid_sgpr(src3_gpr_info[11:0]);
assign src4_cmp_en = get_valid_sgpr(src4_gpr_info[11:0]);
assign dst1_cmp_en = get_valid_sgpr(dst1_gpr_info[11:0]);
assign dst2_cmp_en = get_valid_sgpr(dst2_gpr_info[11:0]);
assign src1_mask = get_mask_4w(src1_gpr_info);
assign src2_mask = get_mask_2w(src2_gpr_info);
assign src3_mask = get_mask_2w(src3_gpr_info);
assign src4_mask = get_mask_4w(src4_gpr_info);
assign dst1_mask = get_mask_4w(dst1_gpr_info);
assign dst2_mask = get_mask_2w(dst2_gpr_info);
assign src1_cmp_result = sgpr_compare_operands_4w(src1_cmp_en, retired_operand_addr,
src1_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src1_mask);
assign src2_cmp_result = sgpr_compare_operands_2w(src2_cmp_en, retired_operand_addr,
src2_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src2_mask);
assign src3_cmp_result = sgpr_compare_operands_2w(src3_cmp_en, retired_operand_addr,
src3_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src3_mask);
assign src4_cmp_result = sgpr_compare_operands_4w(src4_cmp_en, retired_operand_addr,
src4_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src4_mask);
assign dst1_cmp_result = sgpr_compare_operands_4w(dst1_cmp_en, retired_operand_addr,
dst1_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
dst1_mask);
assign dst2_cmp_result = sgpr_compare_operands_2w(dst2_cmp_en, retired_operand_addr,
dst2_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
dst2_mask);
assign result = {src1_cmp_result, src2_cmp_result, src3_cmp_result,
src4_cmp_result, dst1_cmp_result, dst2_cmp_result};
// Function to verify if the operand is indeed a valid sgpr
function get_valid_sgpr;
input[11:0] sgpr_info;
begin
get_valid_sgpr
= (sgpr_info[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)?
1'b1 : 1'b0;
end
endfunction
// Functions to generate masks
function [3:0] get_mask_4w;
input[13:0] sgpr_info;
begin
get_mask_4w
= (sgpr_info[`ISSUE_OP_4WORD_BIT]) ? 4'b1111 :
(sgpr_info[`ISSUE_OP_2WORD_BIT]) ? 4'b0011 :
4'b0001;
end
endfunction
function [1:0] get_mask_2w;
input[12:0] sgpr_info;
begin
get_mask_2w
= (sgpr_info[`ISSUE_OP_2WORD_BIT]) ? 4'b0011 :
4'b0001;
end
endfunction
// Functions that compare two operands
function [3:0] sgpr_compare_operands_4w;
input sb_operand_en;
input [`SGPR_ADDR_LENGTH-1:0] r_operand_info, sb_operand_info;
input [3:0] r_operand_mask, sb_operand_mask;
begin
sgpr_compare_operands_4w
= ( sb_operand_en == 1'b0 ) ? 4'b0000 :
( sb_operand_info+3 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<3 :
( sb_operand_info+2 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<2 :
( sb_operand_info+1 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<1 :
( sb_operand_info == r_operand_info ) ? sb_operand_mask & r_operand_mask :
( sb_operand_info == r_operand_info+1 ) ? sb_operand_mask & r_operand_mask>>1 :
( sb_operand_info == r_operand_info+2 ) ? sb_operand_mask & r_operand_mask>>2 :
( sb_operand_info == r_operand_info+3 ) ? sb_operand_mask & r_operand_mask>>3 :
4'b0000;
end
endfunction
function [1:0] sgpr_compare_operands_2w;
input sb_operand_en;
input [`SGPR_ADDR_LENGTH-1:0] r_operand_info, sb_operand_info;
input [3:0] r_operand_mask;
input [1:0] sb_operand_mask;
begin
sgpr_compare_operands_2w
= ( sb_operand_en == 1'b0 )? 2'b00 :
( sb_operand_info+1 == r_operand_info ) ? (sb_operand_mask & {r_operand_mask[0],1'b0}) :
( sb_operand_info == r_operand_info ) ? (sb_operand_mask & r_operand_mask[1:0]) :
( sb_operand_info == r_operand_info+1 ) ? (sb_operand_mask & r_operand_mask[2:1]) :
( sb_operand_info == r_operand_info+2 ) ? sb_operand_mask & r_operand_mask[3:2] :
( sb_operand_info == r_operand_info+3 ) ? sb_operand_mask & {1'b0,r_operand_mask[3]} :
2'b00;
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int q; void solve(long long int x) { for (long long int i = 2; i * i <= x; i++) { if (x % i == 0) { long long int temp = x / i; for (long long int j = 2; j * j <= temp; j++) { if (temp % j == 0) { cout << 1 << n ; cout << i * j; return; } } cout << 2; return; } } cout << 1 << n ; cout << 0; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> q; if (q == 1) { cout << 1 << n ; cout << 0; return 0; } solve(q); return 0; } |
#include <bits/stdc++.h> using namespace std; const int NN = 5050; const int MM = 27272; int a[MM], b[MM]; vector<int> adj[NN]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , a + i, b + i); adj[a[i]].push_back(b[i]); } int mx = 0; for (int i = 1; i <= n; i++) { mx = max(mx, (int)adj[i].size()); sort(adj[i].begin(), adj[i].end()); } for (int i = 1; i <= n; i++) { int ans = 0; for (int j = 1; j <= n; j++) if (!adj[j].empty()) { int it = lower_bound(adj[j].begin(), adj[j].end(), j) - adj[j].begin(); if (it == adj[j].size()) it = 0; int ed = adj[j][it]; if (ed < j) ed += n; if (j < i) ed += n; int sz = adj[j].size(); ans = max(ans, (sz - 1) * n + ed - i); } cout << ans << ; } return 0; } |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 2;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = pow(10, 9) + 7; const long long MAX = LONG_LONG_MAX; void solve() { int n; cin >> n; vector<string> a(n, ); for (int i = 0; i < n; i += 1) cin >> a[i]; for (int i = 0; i < n; i += 1) { for (int j = 0; j < n; j += 1) { if (a[i][j] == 1 ) { if (i == n - 1 || j == n - 1) { continue; } if (a[i + 1][j] == 1 || a[i][j + 1] == 1 ) { continue; } else { cout << NO ; return; } } } } cout << YES ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; cin >> t; while (t > 0) { solve(); t--; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int a[] = {0, 1, 1, 1, 2, 1, 2, 1, 5, 2, 2, 1, 5, 1, 2, 1, 14, 1, 5, 1, 5, 2, 2, 1, 15, 2, 2, 5, 4, 1, 4, 1, 51, 1, 2, 1, 14, 1, 2, 2, 14, 1, 6, 1, 4, 2, 2, 1, 52, 2, 5, 1, 5, 1, 15, 2, 13, 2, 2, 1, 13, 1, 2, 4, 267, 1, 4, 1, 5, 1, 4, 1, 50, 1, 2, 3, 4, 1, 6, 1, 52, 15, 2, 1, 15, 1, 2, 1, 12, 1, 10, 1, 4, 2}; int main() { int n; cin >> n; cout << a[n] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFXBP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 200000000; struct Point { int x, y; Point(int _x, int _y) { x = _x; y = _y; } }; bool operator<(const Point a, const Point b) { return a.x < b.x; } long long solve(vector<Point> v) { int n = (int)v.size(); vector<int> MINI(n + 1); vector<int> MAXI(n + 1); MINI[n] = inf; MAXI[n] = -inf; for (int i = n - 1; i >= 0; i--) { MINI[i] = min(v[i].y, MINI[i + 1]); MAXI[i] = max(v[i].y, MAXI[i + 1]); } long long lo = 0, hi = 1LL * inf * inf, mi; int mini2, maxi2; while (lo <= hi) { mi = (lo + hi) / 2; bool ok = 0; int mini = inf, maxi = -inf; for (int i = 0, j = -1; i < n; i++) { ok = 1; while (j + 1 <= i) { if (1LL * (v[j + 1].x - v[i].x) * (v[j + 1].x - v[i].x) > mi) { mini = min(mini, v[j + 1].y); maxi = max(maxi, v[j + 1].y); j++; } else { break; } } mini2 = min(mini, MINI[i + 1]), maxi2 = max(maxi, MAXI[i + 1]); if (maxi2 < mini2) { ok = 1; } else { if (1LL * (maxi2 - mini2) * (maxi2 - mini2) > mi) ok = 0; if (1LL * mini2 * mini2 + 1LL * v[i].x * v[i].x > mi) { ok = 0; } if (1LL * maxi2 * maxi2 + 1LL * v[i].x * v[i].x > mi) { ok = 0; } if (1LL * mini2 * mini2 + 1LL * v[j + 1].x * v[j + 1].x > mi) { ok = 0; } if (1LL * maxi2 * maxi2 + 1LL * v[j + 1].x * v[j + 1].x > mi) { ok = 0; } } if (!ok) { } else { ok = 1; break; } } if (ok) hi = mi - 1; else lo = mi + 1; } return lo; } int main() { int n; vector<Point> v; cin >> n; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; v.push_back(Point(x, y)); } sort(v.begin(), v.end()); long long ans = solve(v); ans = min(1LL * (v[0].x - v[n - 1].x) * (v[0].x - v[n - 1].x), ans); for (int i = 0; i < n; i++) { swap(v[i].x, v[i].y); } sort(v.begin(), v.end()); ans = min(1LL * (v[0].x - v[n - 1].x) * (v[0].x - v[n - 1].x), ans); ans = min(ans, solve(v)); cout << ans << endl; } |
#include <bits/stdc++.h> int gcd(int a, int b) { int r; while (b != 0) { r = a % b; a = b; b = r; } return a; } int main() { int n, m; int deg1, deg2; scanf( %d %d , &n, &m); for (int i = 0, a; i <= n; i++) { scanf( %d , &a); if (i == 0) deg1 = a; } for (int i = 0, a; i <= m; i++) { scanf( %d , &a); if (i == 0) deg2 = a; } if (n > m) { if (deg1 > 0 && deg2 > 0 || (deg1 < 0 && deg2 < 0)) printf( Infinity ); else printf( -Infinity ); } else if (m > n) printf( 0/1 ); else { while (gcd(deg1, deg2) != 1) { int r = gcd(deg1, deg2); deg1 /= r; deg2 /= r; } if (deg1 < 0 && deg2 < 0 || (deg1 > 0 && deg2 > 0)) printf( %d/%d , deg1, deg2); else printf( -%d/%d , abs(deg1), abs(deg2)); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_SYMBOL_V
`define SKY130_FD_SC_LP__O21BA_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n, m, i; cin >> n >> m; long long int arr[n + 5]; map<long long int, long long int> ma; queue<long long int> q; for (i = 0; i < n; i++) { cin >> arr[i]; ma[arr[i]] = 0; q.push(arr[i]); } long long int result = 0, cnt = 0; long long int ans[m + 5]; while (!q.empty()) { if (cnt >= m) break; long long int x = q.front(); if (!ma.count(x + 1)) { q.push(x + 1); ans[cnt] = x + 1; ma[x + 1] = ma[x] + 1; result += ma[x + 1]; cnt++; } if (cnt >= m) break; if (!ma.count(x - 1)) { q.push(x - 1); ans[cnt] = x - 1; ma[x - 1] = ma[x] + 1; result += ma[x - 1]; cnt++; } q.pop(); } cout << result << n ; for (i = 0; i < m; i++) cout << ans[i] << ; cout << n ; return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback () ////
//// - Julius Baxter () ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module rom
#(parameter addr_width = 5,
parameter b3_burst = 0)
(
input wb_clk,
input wb_rst,
input [(addr_width+2)-1:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o);
reg [addr_width-1:0] adr;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (adr)
// Zero r0 and endless loop
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h00000000;
4 : wb_dat_o <= 32'h15000000;
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
generate
if(b3_burst) begin : gen_b3_burst
reg wb_stb_i_r;
reg new_access_r;
reg burst_r;
wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
wire new_access = (wb_stb_i & !wb_stb_i_r);
wire new_burst = (burst & !burst_r);
always @(posedge wb_clk) begin
new_access_r <= new_access;
burst_r <= burst;
wb_stb_i_r <= wb_stb_i;
end
always @(posedge wb_clk)
if (wb_rst)
adr <= 0;
else if (new_access)
// New access, register address, ack a cycle later
adr <= wb_adr_i[(addr_width+2)-1:2];
else if (burst) begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr <= adr + 1;
2'b01: adr[1:0] <= adr[1:0] + 1;
2'b10: adr[2:0] <= adr[2:0] + 1;
2'b11: adr[3:0] <= adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr <= wb_adr_i[(addr_width+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o <= 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
wb_ack_o <= 1;
else
wb_ack_o <= 0;
end else begin
always @(wb_adr_i)
adr <= wb_adr_i;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> using V = vector<T>; const long long int mod = 1000000007; struct sb { size_t c, ind; unsigned long long int a, b; }; bool cmp(sb a, sb b) { return a.c < b.c; } struct s { unsigned long long int sub; size_t lastsub; int before; bool can; } DP[51][101][51]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); size_t N, M; unsigned long long int K; cin >> N >> M >> K; V<sb> subs(M); for (__typeof(M) i = (0) - ((0) > (M)); i != (M) - ((0) > (M)); i += ((0) > (M) ? -1 : 1)) cin >> subs[i].a >> subs[i].b >> subs[i].c, subs[i].ind = i; sort((subs).begin(), (subs).end(), cmp); pair<size_t, unsigned long long int> ans; for (__typeof(M) i = (0) - ((0) > (M)); i != (M) - ((0) > (M)); i += ((0) > (M) ? -1 : 1)) { for (__typeof(subs[i].b + 1) j = (subs[i].a) - ((subs[i].a) > (subs[i].b + 1)); j != (subs[i].b + 1) - ((subs[i].a) > (subs[i].b + 1)); j += ((subs[i].a) > (subs[i].b + 1) ? -1 : 1)) { size_t l = j - subs[i].a; DP[i][l][1].sub = j; DP[i][l][1].lastsub = 0; DP[i][l][1].before = -1; DP[i][l][1].can = true; for (__typeof(N + 1) k = (2) - ((2) > (N + 1)); k != (N + 1) - ((2) > (N + 1)); k += ((2) > (N + 1) ? -1 : 1)) { DP[i][l][k].sub = 0; DP[i][l][k].lastsub = 0; DP[i][l][k].before = -1; DP[i][l][k].can = false; for (__typeof(0) z = (i) - ((i) > (0)); z != (0) - ((i) > (0)); z += ((i) > (0) ? -1 : 1)) { if (subs[z].c == subs[i].c) continue; if (j % K == 0 && j / K >= subs[z].a && (j / K - subs[z].a) <= subs[z].b - subs[z].a) { if (DP[z][j / K - subs[z].a][k - 1].can && DP[z][j / K - subs[z].a][k - 1].sub + j >= DP[i][l][k].sub) { DP[i][l][k].sub = DP[z][j / K - subs[z].a][k - 1].sub + j; DP[i][l][k].lastsub = j / K - subs[z].a; DP[i][l][k].can = true; DP[i][l][k].before = z; } } if (j >= K + subs[z].a && (j - K - subs[z].a) <= subs[z].b - subs[z].a) { if (DP[z][j - K - subs[z].a][k - 1].can && DP[z][j - K - subs[z].a][k - 1].sub + j >= DP[i][l][k].sub) { DP[i][l][k].sub = DP[z][j - K - subs[z].a][k - 1].sub + j; DP[i][l][k].lastsub = j - K - subs[z].a; DP[i][l][k].can = true; DP[i][l][k].before = z; } } } } if (DP[i][l][N].can && DP[i][l][N].sub >= DP[ans.first][ans.second][N].sub) ans = {i, l}; } } if (!DP[ans.first][ans.second][N].can) { cout << NO << endl; return 0; } cout << YES << endl; V<pair<size_t, unsigned long long int> > res; for (__typeof(1) i = (N + 1) - ((N + 1) > (1)); i != (1) - ((N + 1) > (1)); i += ((N + 1) > (1) ? -1 : 1)) { res.push_back({subs[ans.first].ind + 1, subs[ans.first].a + ans.second}); ans = {DP[ans.first][ans.second][i].before, DP[ans.first][ans.second][i].lastsub}; } for (__typeof(0) i = (N) - ((N) > (0)); i != (0) - ((N) > (0)); i += ((N) > (0) ? -1 : 1)) cout << res[i].first << << res[i].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << , ; err(++it, args...); } namespace fastIO { bool IOerror = 0; inline char nc() { static char buf[100000], *p1 = buf + 100000, *pend = buf + 100000; if (p1 == pend) { p1 = buf; pend = buf + fread(buf, 1, 100000, stdin); if (pend == p1) { IOerror = 1; return -1; } } return *p1++; } inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } inline void read(int &x) { char ch; while (blank(ch = nc())) ; if (IOerror) return; for (x = ch - 0 ; (ch = nc()) >= 0 && ch <= 9 ; x = x * 10 + ch - 0 ) ; } } // namespace fastIO using namespace fastIO; const double PI = acos(-1.0); const double eps = 1e-8; const int maxn = 3e5 + 7; const int N = 1e4 + 10; const int mod = 998244353; long long qp(long long b, long long n) { long long r = 1; if (n < 0) n += mod - 1; b %= mod; for (; n; n >>= 1, b = b * b % mod) if (n & 1) r = r * b % mod; return r; } int sgn(double x) { if (x < -eps) return -1; return x > eps ? 1 : 0; } int n; long long dp[3][N]; long long sum[N], suf[N]; int a[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); sort(a + 1, a + 1 + n); long long _c2 = (n * (n - 1) / 2); for (int i = 1; i <= n; ++i) { for (int j = i + 1; j <= n; ++j) { dp[0][a[j] - a[i]]++; } } for (int i = 1; i <= n; ++i) { for (int j = i + 1; j <= n; ++j) { dp[1][a[j] - a[i]]++; } } for (int i = 1; i <= 10000; ++i) { for (int j = 1; j < i; ++j) { int k = i - j; dp[2][i] += dp[0][j] * dp[1][k]; } sum[i] = sum[i - 1] + dp[2][i]; } double ans = 0; for (int i = 10000; i >= 1; --i) { ans += sum[i - 1] * dp[0][i]; } printf( %.12lf n , 1.0 * ans / _c2 / _c2 / _c2); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int v = 0; map<int, int> s; for (int i = 19; s.size() < 10010; i += 9) { int kk = i; int c = 0; while (kk > 0) { c += kk % 10; kk /= 10; } if (c == 10) s[v++] = i; } cout << s[n - 1]; return 0; } |
#include <bits/stdc++.h> using namespace std; int Ans, Cap[55][55], From[55], K, N, T[55]; vector<int> E[55]; bool dijkstra() { priority_queue<pair<int, int>, vector<pair<int, int>>, greater<pair<int, int>>> q; vector<int> d(55, 1005); d[1] = 0; q.push(make_pair(0, 1)); while (!q.empty()) { pair<int, int> p = q.top(); q.pop(); int n = p.second, c = p.first; if (n == N) return true; for (int i = 1; i <= N; i++) if (Cap[n][i] && c < d[i]) { d[i] = c; From[i] = n; T[i] = 0; q.push(make_pair(c, i)); } for (int v : E[n]) if (c + 1 < d[v]) { d[v] = c + 1; From[v] = n; T[v] = 1; q.push(make_pair(c + 1, v)); } } return false; } int main() { cin >> N >> K; for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) { cin >> Cap[i][j]; if (Cap[i][j]) E[i].push_back(j); } while (true) { if (!dijkstra()) break; int cost = 0, flow = 1000000, n = N; while (From[n] > 0) { if (T[n] == 0) flow = min(flow, Cap[From[n]][n]); n = From[n]; } n = N; while (From[n] > 0) { if (T[n]) cost++; else Cap[From[n]][n] -= flow, Cap[n][From[n]] += flow; n = From[n]; } if (cost * flow <= K) { K -= cost * flow; Ans += flow; } else { Ans += K / cost; break; } } cout << Ans; } |
#include <bits/stdc++.h> using namespace std; const int N = 105; char arr[N], dp[N][N * N], ndp[N][N * N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; int sz = 0; for (int i = 0; i < n; i++) { int x; cin >> x; arr[x]++; if (arr[x] == 1) sz++; } dp[0][0] = 1; for (int i = 1; i < N; i++) { for (int x1 = 0; x1 < N; x1++) for (int x2 = 0; x2 < N * N; x2++) ndp[x1][x2] = 0; for (int f = 0; f <= arr[i]; f++) for (int x1 = 0; x1 < N; x1++) for (int x2 = 0; x2 < N * N; x2++) if (x2 + f * i < N * N && x1 + f < N) ndp[x1 + f][x2 + f * i] = min(100, ndp[x1 + f][x2 + f * i] + dp[x1][x2]); for (int x1 = 0; x1 < N; x1++) for (int x2 = 0; x2 < N * N; x2++) dp[x1][x2] = ndp[x1][x2]; } if (sz <= 2) { cout << n << n ; return 0; } int ans = 0; for (int i = 1; i < N; i++) for (int f = 1; f <= arr[i]; f++) if (dp[f][f * i] == 1) ans = max(ans, f); cout << ans << n ; return 0; } |
`timescale 1ns/1ps
module search_engine(
clk,
reset,
key_valid,
key,
bv_valid,
bv,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input key_valid;
input [26:0]key;
output bv_valid;
output[35:0]bv;
input localbus_cs_n;
input localbus_rd_wr;
input[31:0] localbus_data;
input localbus_ale;
output localbus_ack_n;
output[31:0] localbus_data_out;
reg localbus_ack_n;
reg [31:0] localbus_data_out;
wire bv_valid;
wire[35:0] bv;
reg set_valid_1,set_valid_2,set_valid_3;
reg read_valid_1,read_valid_2,read_valid_3;
//reg [8:0] read_addr_1,read_addr_2,read_addr_3;
wire data_out_valid_1,data_out_valid_2,data_out_valid_3;
wire[35:0] data_out_1,data_out_2,data_out_3;
wire[35:0] bv_1,bv_2,bv_3;
wire stage_enable_1,stage_enable_2,stage_enable_3;
//---state----//
reg [3:0] set_state;
parameter idle = 4'd0,
ram_set = 4'd1,
ram_read = 4'd2,
wait_read = 4'd3,
wait_back = 4'd4;
//--------------reg--------------//
//--search--//
//--set--//
reg [31:0] localbus_addr;
reg [44:0] set_data;//addr_9+36;
reg [12:0] set_data_1;//addr_9+localbus[31]_vald+localbus[2:0]; 1st;
reg [35:0] data_out;
reg [8:0] read_addr;
//-----------------------search_state-----------------//
//-----------------------set_state---------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
set_valid_1 <= 1'b0;set_valid_2 <= 1'b0;set_valid_3 <= 1'b0;
read_valid_1<= 1'b0;read_valid_2<= 1'b0;read_valid_3<= 1'b0;
localbus_addr <= 32'b0;
data_out <= 36'd0;
set_data <= 45'b0;
set_data_1 <= 13'b0;
read_addr <= 9'b0;
localbus_data_out <= 32'b0;
localbus_ack_n <= 1'b1;
end
else
begin
case(set_state)
idle:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set;
end
else
begin
set_state <= ram_read;
end
end
end
ram_set:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'd0: set_data_1 <= {localbus_addr[11:3],localbus_data[31],localbus_data[2:0]};//????zq0825
1'd1:
begin
set_data <= {set_data_1,localbus_data};
case(localbus_addr[13:12])
3'd0: set_valid_1 <= 1'b1;
3'd1: set_valid_2 <= 1'b1;
3'd2: set_valid_3 <= 1'b1;
3'd3: set_valid_3 <= 1'b0;
endcase
end
endcase
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
ram_read:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'b0:
begin
read_addr <= localbus_addr[11:3];
case(localbus_addr[13:12])
3'd0: read_valid_1 <= 1'b1;
3'd1: read_valid_2 <= 1'b1;
3'd2: read_valid_3 <= 1'b1;
3'd3: read_valid_3 <= 1'b1;
endcase
end
1'b1: localbus_data_out <= data_out[31:0];
endcase
if(localbus_addr[0] == 1'b0)
begin
set_state <= wait_read;
end
else
begin
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
end
wait_read:
begin
read_valid_1 <= 1'b0;read_valid_2 <= 1'b0;read_valid_3 <= 1'b0;
if((data_out_valid_1 == 1'b1) || (data_out_valid_2 == 1'b1) || (data_out_valid_3 == 1'b1))
begin
case({data_out_valid_1,data_out_valid_2,data_out_valid_3})
3'd4:
begin
data_out <= data_out_1;
localbus_data_out <= {data_out_1[35],28'b0,data_out_1[34:32]};
end
3'd2:
begin
data_out <= data_out_2;
localbus_data_out <= {data_out_2[35],28'b0,data_out_2[34:32]};
end
3'd1:
begin
data_out <= data_out_3;
localbus_data_out <= {data_out_3[35],28'b0,data_out_3[34:32]};
end
default:
begin
data_out <= 36'b0;
localbus_data_out <= 32'b0;
end
endcase
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
end
wait_back:
begin
set_valid_1 <= 1'b0;set_valid_2 <= 1'b0;set_valid_3 <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
//-----------------stage_1------------------//
lookup_9bit stage_1_1(
.clk(clk),
.reset(reset),
.set_valid(set_valid_1),
.set_data(set_data),
.read_valid(read_valid_1),
.read_addr(read_addr),
.data_out_valid(data_out_valid_1),
.data_out(data_out_1),
.key_valid(key_valid),
.key(key[26:18]),
//.bv_valid(),
.bv(bv_1),
.stage_enable(stage_enable_1)
);
//--stage_1_2--//
lookup_9bit stage_1_2(
.clk(clk),
.reset(reset),
.set_valid(set_valid_2),
.set_data(set_data),
.read_valid(read_valid_2),
.read_addr(read_addr),
.data_out_valid(data_out_valid_2),
.data_out(data_out_2),
.key_valid(key_valid),
.key(key[17:9]),
//.bv_valid(),
.bv(bv_2),
.stage_enable()
);
//--stage_1_3--//
lookup_9bit stage_1_3(
.clk(clk),
.reset(reset),
.set_valid(set_valid_3),
.set_data(set_data),
.read_valid(read_valid_3),
.read_addr(read_addr),
.data_out_valid(data_out_valid_3),
.data_out(data_out_3),
.key_valid(key_valid),
.key(key[8:0]),
//.bv_valid(),
.bv(bv_3),
.stage_enable()
);
//--stage_2--//
hold1clk stage_2(
.clk(clk),
.reset(reset),
.stage_enable_in(stage_enable_1),
.stage_enable_out(stage_enable_2)
);
//--stage_3--//
bv_and stage_3(
.clk(clk),
.reset(reset),
.stage_enable_in(stage_enable_2),
.stage_enable_out(stage_enable_3),
.bv_1(bv_1),
.bv_2(bv_2),
.bv_3(bv_3),
.bv_valid(bv_valid),
.bv(bv)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_2_V
`define SKY130_FD_SC_HDLL__O21AI_2_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAX = 1123; int ans[MAX]; int main() { int n; cin >> n; memset(ans, INF, sizeof(ans)); for (int i = 0; i < 10; i++) { vector<int> data1, data2; for (int j = 1; j <= n; j++) { if (j & (1 << i)) data1.push_back(j); else data2.push_back(j); } if (data1.size()) { cout << data1.size() << endl; for (int j = 0; j < data1.size(); j++) { cout << data1[j] << ; } for (int j = 1; j <= n; j++) { int t; cin >> t; if ((j & (1 << i)) == 0) { ans[j] = min(ans[j], t); } } cout << endl; fflush(stdout); } if (data2.size()) { cout << data2.size() << endl; for (int j = 0; j < data2.size(); j++) { cout << data2[j] << ; } for (int j = 1; j <= n; j++) { int t; cin >> t; if (j & (1 << i)) ans[j] = min(ans[j], t); } cout << endl; fflush(stdout); } } fflush(stdout); cout << -1 << endl; for (int i = 1; i <= n; i++) cout << ans[i] << ; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// MMCM_OR_BUFR_N with DRP and device specific
`timescale 1ns/100ps
module ad_mmcm_drp (
// clocks
clk,
clk2,
mmcm_rst,
clk_sel,
mmcm_clk_0,
mmcm_clk_1,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter MMCM_DEVICE_TYPE = 0;
localparam MMCM_DEVICE_7SERIES = 0;
localparam MMCM_DEVICE_VIRTEX6 = 1;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_CLKIN2_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
// clocks
input clk;
input clk2;
input mmcm_rst;
input clk_sel;
output mmcm_clk_0;
output mmcm_clk_1;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg [15:0] up_drp_rdata = 'd0;
reg up_drp_ready = 'd0;
reg up_drp_locked_m1 = 'd0;
reg up_drp_locked = 'd0;
// internal signals
wire bufg_fb_clk_s;
wire mmcm_fb_clk_s;
wire mmcm_clk_0_s;
wire mmcm_clk_1_s;
wire mmcm_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp read and locked
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_rdata <= 'd0;
up_drp_ready <= 'd0;
up_drp_locked_m1 <= 1'd0;
up_drp_locked <= 1'd0;
end else begin
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_locked_m1 <= mmcm_locked_s;
up_drp_locked <= up_drp_locked_m1;
end
end
// instantiations
generate
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin
MMCM_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end
endgenerate
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_V |
// file: MIPS_CPU_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module MIPS_CPU_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_MIPS_CPU_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_MIPS_CPU_clk_wiz_0_0;
wire clkfbout_buf_MIPS_CPU_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_MIPS_CPU_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_MIPS_CPU_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_MIPS_CPU_clk_wiz_0_0),
.CLKIN1 (clk_in1_MIPS_CPU_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_MIPS_CPU_clk_wiz_0_0),
.I (clkfbout_MIPS_CPU_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_MIPS_CPU_clk_wiz_0_0));
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the pipe
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "pipe.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipe();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the pipe
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire op; // Output signal out
// Declare "reg" signals: inputs to the DUT
reg ip; // Input signal - in
reg clk; // Input signal - clock
reg rst; // Input signal - reset
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pp"
*/
pipeline_buffer pp (
// instance_name(signal name),
// Signal name can be the same as the instance name
ip,op,clk,rst);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clk = 0;
#5 clk = 1;
// Period = 10 ns
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
ip = 1'd0;
rst = 1'd0;
// @t=9,
#9
ip = 1'd1;
rst = 1'd0;
// @t=19,
#10
ip = 1'd0;
rst = 1'd0;
// @t=29,
#10
ip = 1'd1;
rst = 1'd0;
// @t=39,
#10
ip = 1'd1;
rst = 1'd0;
// @t=49,
#10
ip = 1'd1;
rst = 1'd0;
// @t=59,
#10
ip = 1'd0;
rst = 1'd0;
// @t=69,
#10
ip = 1'd1;
rst = 1'd0;
// @t=79,
#10
ip = 1'd0;
rst = 1'd0;
// @t=89,
#10
ip = 1'd1;
rst = 1'd0;
// @t=99,
#10
ip = 1'd0;
rst = 1'd0;
// @t=109,
#10
ip = 1'd1;
rst = 1'd0;
// @t=119,
#10
ip = 1'd0;
rst = 1'd0;
// @t=129,
#10
ip = 1'd1;
rst = 1'd0;
// @t=139,
#10
ip = 1'd0;
rst = 1'd0;
// @t=149,
#10
ip = 1'd1;
rst = 1'd0;
// @t=159,
#10
ip = 1'd1;
rst = 1'd0;
// @t=169,
#10
ip = 1'd1;
rst = 1'd0;
// @t=179,
#10
ip = 1'd0;
rst = 1'd0;
// @t=189,
#10
ip = 1'd1;
rst = 1'd0;
// @t=199,
#10
ip = 1'd0;
rst = 1'd0;
// @t=209,
#10
ip = 1'd1;
rst = 1'd0;
// @t=219,
#10
ip = 1'd1;
rst = 1'd0;
// @t=229,
#10
ip = 1'd1;
rst = 1'd0;
// @t=239,
#10
ip = 1'd1;
rst = 1'd0;
// @t=249,
#10
ip = 1'd1;
rst = 1'd0;
// @t=259,
#10
ip = 1'd0;
rst = 1'd0;
// @t=269,
#10
ip = 1'd1;
rst = 1'd0;
// @t=279,
#10
ip = 1'd1;
rst = 1'd1;
// @t=289,
#10
ip = 1'd1;
rst = 1'd0;
// @t=299,
#10
ip = 1'd0;
rst = 1'd0;
// @t=309,
#10
ip = 1'd1;
rst = 1'd0;
// @t=319,
#10
ip = 1'd1;
rst = 1'd0;
// @t=329,
#10
ip = 1'd0;
rst = 1'd0;
// @t=339,
#10
ip = 1'd1;
rst = 1'd0;
// @t=349,
#10
ip = 1'd0;
rst = 1'd0;
// @t=359,
#10
ip = 1'd1;
rst = 1'd0;
// @t=369,
#10
ip = 1'd1;
rst = 1'd0;
// @t=379,
#10
ip = 1'd1;
rst = 1'd0;
// @t=389,
#10
ip = 1'd1;
rst = 1'd0;
// @t=399,
#10
ip = 1'd0;
rst = 1'd0;
// @t=409,
#10
ip = 1'd1;
rst = 1'd0;
// @t=419,
#10
ip = 1'd1;
rst = 1'd0;
// @t=429,
#10
ip = 1'd1;
rst = 1'd0;
// @t=439,
#10
ip = 1'd1;
rst = 1'd0;
// @t=449,
#10
ip = 1'd1;
rst = 1'd0;
// @t=459,
#10
ip = 1'd0;
rst = 1'd0;
// @t=469,
#10
ip = 1'd1;
rst = 1'd0;
// @t=479,
#10
ip = 1'd0;
rst = 1'd0;
// @t=489,
#10
ip = 1'd0;
rst = 1'd0;
// @t=499,
#10
ip = 1'd0;
rst = 1'd0;
// @t=509,
#10
ip = 1'd0;
rst = 1'd0;
// @t=519,
#10
ip = 1'd1;
rst = 1'd0;
// @t=529,
#10
ip = 1'd1;
rst = 1'd0;
// @t=539,
#10
ip = 1'd0;
rst = 1'd0;
// @t=549,
#10
ip = 1'd1;
rst = 1'd0;
// @t=559,
#10
ip = 1'd1;
rst = 1'd0;
// @t=569,
#10
ip = 1'd1;
rst = 1'd0;
// @t=579,
#10
ip = 1'd1;
rst = 1'd0;
// @t=589,
#10
ip = 1'd0;
rst = 1'd0;
// @t=599,
#10
ip = 1'd1;
rst = 1'd0;
// @t=609,
#10
ip = 1'd0;
rst = 1'd0;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_addr_gen.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// The address for the memory and the various user commands can be given
// through this module. It instantiates the block RAM which stores all the
// information in particular sequence. The data stored should be in a
// sequence starting from LSB:
// column address, row address, bank address, commands.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_addr_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter ROW_WIDTH = 14
)
(
input clk,
input rst,
input wr_addr_en,
output reg [2:0] app_af_cmd,
output reg [30:0] app_af_addr,
output reg app_af_wren
);
// RAM initialization patterns
// NOTE: Not all bits in each range may be used (e.g. in an application
// using only 10 column bits, bits[11:10] of ROM output will be unused
// COLUMN = [11:0]
// ROW = [27:12]
// BANK = [30:28]
// CHIP = [31]
// COMMAND = [35:32]
localparam RAM_INIT_00 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_01 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_02 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_03 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_04 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_05 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_06 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INIT_07 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INITP_00 = {128'h11111111_00000000_11111111_00000000,
128'h11111111_00000000_11111111_00000000};
reg wr_addr_en_r1;
reg [2:0] af_cmd_r;
reg [30:0] af_addr_r;
reg af_wren_r;
wire [15:0] ramb_addr;
wire [35:0] ramb_dout;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
reg [5:0] wr_addr_cnt;
reg wr_addr_en_r0;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//*****************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
//***************************************************************************
// ADDRESS generation for Write and Read Address FIFOs:
// ROM with address patterns
// 512x36 mode is used with addresses 0-127 for storing write addresses and
// addresses (128-511) for storing read addresses
// INIP_OO: read 1
// INIP_OO: write 0
//***************************************************************************
assign ramb_addr = {5'b00000, wr_addr_cnt, 5'b00000};
RAMB36 #
(
.READ_WIDTH_A (36),
.READ_WIDTH_B (36),
.DOA_REG (1), // register to help timing
.INIT_00 (RAM_INIT_00),
.INIT_01 (RAM_INIT_01),
.INIT_02 (RAM_INIT_02),
.INIT_03 (RAM_INIT_03),
.INIT_04 (RAM_INIT_04),
.INIT_05 (RAM_INIT_05),
.INIT_06 (RAM_INIT_06),
.INIT_07 (RAM_INIT_07),
.INITP_00 (RAM_INITP_00)
)
u_wr_rd_addr_lookup
(
.CASCADEOUTLATA (),
.CASCADEOUTLATB (),
.CASCADEOUTREGA (),
.CASCADEOUTREGB (),
.DOA (ramb_dout[31:0]),
.DOB (),
.DOPA (ramb_dout[35:32]),
.DOPB (),
.ADDRA (ramb_addr),
.ADDRB (16'h0000),
.CASCADEINLATA (),
.CASCADEINLATB (),
.CASCADEINREGA (),
.CASCADEINREGB (),
.CLKA (clk),
.CLKB (clk),
.DIA (32'b0),
.DIB (32'b0),
.DIPA (4'b0),
.DIPB (4'b0),
.ENA (1'b1),
.ENB (1'b1),
.REGCEA (1'b1),
.REGCEB (1'b1),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (4'b0000),
.WEB (4'b0000)
);
// register backend enables / FIFO enables
// write enable for Command/Address FIFO is generated 2 CC after WR_ADDR_EN
// (takes 2 CC to come out of test RAM)
always @(posedge clk)
if (rst_r1) begin
app_af_wren <= 1'b0;
wr_addr_en_r0 <= 1'b0;
wr_addr_en_r1 <= 1'b0;
af_wren_r <= 1'b0;
end else begin
wr_addr_en_r0 <= wr_addr_en;
wr_addr_en_r1 <= wr_addr_en_r0;
af_wren_r <= wr_addr_en_r1;
app_af_wren <= af_wren_r;
end
// FIFO addresses
always @(posedge clk) begin
af_addr_r <= {30{1'b0}};
af_addr_r[COL_WIDTH-1:0] <= ramb_dout[COL_WIDTH-1:0];
af_addr_r[ROW_WIDTH+COL_WIDTH-1:COL_WIDTH]
<= ramb_dout[ROW_WIDTH+11:12];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1:ROW_WIDTH+COL_WIDTH]
<= ramb_dout[BANK_WIDTH+27:28];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH]
<= ramb_dout[31];
// only reads and writes are supported for now
af_cmd_r <= {1'b0, ramb_dout[33:32]};
app_af_cmd <= af_cmd_r;
app_af_addr <= af_addr_r;
end
// address input for RAM
always @ (posedge clk)
if (rst_r1)
wr_addr_cnt <= 6'b000000;
else if (wr_addr_en)
wr_addr_cnt <= wr_addr_cnt + 1;
endmodule
|
// DEFINES
`define BITS 32 // Bit width of the operands
module dscg(clock,
reset,
cos,
one,
s1,
s2,
s1_out,
s2_out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] cos;
input [`BITS-1:0] one;
input [`BITS-1:0] s1;
input [`BITS-1:0] s2;
output [`BITS-1:0] s1_out;
output [`BITS-1:0] s2_out;
wire [`BITS-1:0] add1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] sub5;
wire [`BITS-1:0] x6;
wire [`BITS-1:0] x7;
wire [`BITS-1:0] s1_out;
wire [`BITS-1:0] s2_out;
reg [`BITS-1:0] x3_reg1;
reg [`BITS-1:0] x3_reg2;
reg [`BITS-1:0] x3_reg3;
reg [`BITS-1:0] x3_reg4;
reg [`BITS-1:0] x3_reg5;
reg [`BITS-1:0] x3_reg6;
reg [`BITS-1:0] x7_reg1;
reg [`BITS-1:0] x7_reg2;
reg [`BITS-1:0] x7_reg3;
reg [`BITS-1:0] x7_reg4;
reg [`BITS-1:0] x7_reg5;
reg [`BITS-1:0] x7_reg6;
//assign add1 = cos + one;
wire [7:0] add1_control;
fpu_add add1_add
(
.clk(clock),
.opa(cos),
.opb(one),
.out(add1),
.control(add1_control)
);
//assign x2 = add1 * s2;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(add1),
.opb(s2),
.out(x2),
.control(x2_control)
);
//assign x3 = cos * s1;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(cos),
.opb(s1),
.out(x3),
.control(x3_control)
);
//assign s1_out = x2 + x3_reg1;
wire [7:0] s1_out_control;
fpu_add s1_out_add
(
.clk(clock),
.opa(x2),
.opb(x3_reg6),
.out(s1_out),
.control(s1_out_control)
);
//assign sub5 = one - cos;
wire [7:0] sub5_control;
fpu_add sub5_add
(
.clk(clock),
.opa(one),
.opb(cos),
.out(sub5),
.control(sub5_control)
);
//assign x6 = sub5 * s1;
wire [7:0] x6_control;
fpu_mul x6_mul
(
.clk(clock),
.opa(sub5),
.opb(s1),
.out(x6),
.control(x6_control)
);
//assign x7 = cos * s2;
wire [7:0] x7_control;
fpu_mul x7_mul
(
.clk(clock),
.opa(cos),
.opb(s2),
.out(x7),
.control(x7_control)
);
//assign s2_out = x6 + x7_reg1;
wire [7:0] s2_out_control;
fpu_add s2_out_add
(
.clk(clock),
.opa(x6),
.opb(x7_reg6),
.out(s2_out),
.control(s2_out_control)
);
always @(posedge clock)
begin
x3_reg1 <= x3;
x3_reg2 <= x3_reg1;
x3_reg3 <= x3_reg2;
x3_reg4 <= x3_reg3;
x3_reg5 <= x3_reg4;
x3_reg6 <= x3_reg5;
x7_reg1 <= x7;
x7_reg2 <= x7_reg1;
x7_reg3 <= x7_reg2;
x7_reg4 <= x7_reg3;
x7_reg5 <= x7_reg4;
x7_reg6 <= x7_reg5;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_2_V
`define SKY130_FD_SC_LS__DFRBP_2_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_2_V
|
//==================================================================================================
// Filename : Comparators.v
// Created On : 2016-09-22 10:07:30
// Last Modified : 2016-09-22 14:51:38
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:11:30 08/20/2015
// Design Name:
// Module Name: Sixth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// `include "Comparator_Less.v"
// `include "Greater_Comparator.v"
module FORMATTER
//Module Parameter
//EW = 9 ; Single Precision Format
//EW = 11; Double Precision Format
# (parameter EW = 9)
/* # (parameter EW = 12)*/
(
input wire [EW-1:0] exp, //exponent of the fifth phase
output wire overflow, //overflow flag
output wire underflow //underflow flag
);
wire [EW-1:0] U_limit; //Max Normal value of the standar ieee 754
wire [EW-1:0] L_limit; //Min Normal value of the standar ieee 754
//Compares the exponent with the Max Normal Value, if the exponent is
//larger than U_limit then exist overflow
Greater_Comparator #(.W(EW)) GTComparator (
.Data_A(exp),
.Data_B(U_limit),
.gthan(overflow)
);
//Compares the exponent with the Min Normal Value, if the exponent is
//smaller than L_limit then exist underflow
Comparator_Less #(.W(EW)) LTComparator (
.Data_A(exp),
.Data_B(L_limit),
.less(underflow)
);
//This generate sentence creates the limit values based on the
//precision format
`ifdef GEN
generate
if(EW == 9) begin
assign U_limit = 9'hfe;
assign L_limit = 9'h01;
end
else begin
assign U_limit = 12'b111111111110;
assign L_limit = 12'b000000000001;
end
endgenerate
`endif
assign U_limit = {{(EW-1){1'b1}},1'b0};
assign L_limit = {{(EW-1){1'b0}},1'b1};
endmodule
|
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
// Takes input messages to set taps.
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output wire out_nd,
output wire [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output wire error
);
filter #(WIDTH, 1, `FILTER_LENGTH, `FILTER_ID) filter_0
(
.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.in_m(in_m),
.in_msg(in_msg),
.in_msg_nd(in_msg_nd),
.out_data(out_data),
.out_nd(out_nd),
.out_m(out_m),
.out_msg(out_msg),
.out_msg_nd(out_msg_nd),
.error(error)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const int mod = inf + 7; const double eps = 1e-9; const double pi = acos(-1.0); long double a, b, c, d; pair<long double, long double> get(pair<long double, long double> a, pair<long double, long double> b) { long double x[4] = {a.first * b.first, a.second * b.first, a.first * b.second, a.second * b.second}; sort(x, x + 4); return make_pair(x[0], x[3]); } bool ok(pair<long double, long double> a, pair<long double, long double> b) { long double l = max(a.first, b.first); long double r = min(a.second, b.second); return l < r + 1e-21; } bool ok(long double ans) { pair<long double, long double> x = make_pair(a - ans, a + ans); pair<long double, long double> y = make_pair(b - ans, b + ans); pair<long double, long double> z = make_pair(c - ans, c + ans); pair<long double, long double> t = make_pair(d - ans, d + ans); pair<long double, long double> first = get(x, t); pair<long double, long double> second = get(y, z); return ok(first, second); } long double mx(long double a, long double b, long double c, long double d) { return max(abs(a), max(abs(b), max(abs(c), abs(d)))); } int main() { cin >> a >> b >> c >> d; long double l = 0, r = mx(a, b, c, d); for (int i = 0; i < 20000; i++) { long double mid = (l + r) / 2.0; if (ok(mid)) { r = mid; } else l = mid; } printf( %.10f n , (double)r); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[16 - 1 : 0] a; // synthesis attribute keep a "true"
input[8 - 1 : 0] b; // synthesis attribute keep b "true"
output[24 - 1 : 0] p;
reg[16 - 1 : 0] a_reg;
reg[8 - 1 : 0] b_reg;
wire [24 - 1 : 0] tmp_product;
reg[24 - 1 : 0] buff0;
reg[24 - 1 : 0] buff1;
reg[24 - 1 : 0] buff2;
reg[24 - 1 : 0] buff3;
reg[24 - 1 : 0] buff4;
reg[24 - 1 : 0] buff5;
reg[24 - 1 : 0] buff6;
assign p = buff6;
assign tmp_product = a_reg * b_reg;
always @ (posedge clk) begin
if (ce) begin
a_reg <= a;
b_reg <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0 nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int LOG = 22; int32_t main() { ios::sync_with_stdio(false); int n; cin >> n; vector<int> tab(n); vector<int> dp(1 << LOG); vector<pair<int, int> > samples(1 << LOG, {-1, -1}); auto update = [&](int a, int i) { if (i == -1) return; if (samples[a].first != -1) samples[a].second = i; samples[a].first = i; }; for (int i = 0; i < n; i++) { cin >> tab[i]; dp[tab[i]]++; update(tab[i], i); } for (int i = 0; i < LOG; i++) { for (int m = 0; m < (1 << LOG); m++) { if (m & (1 << i)) { dp[m] += dp[m ^ (1 << i)]; update(m, samples[m ^ (1 << i)].first); update(m, samples[m ^ (1 << i)].second); } } } for (int i = 0; i < n; i++) { int a = tab[i] ^ ((1 << LOG) - 1); if (samples[a].first == i) cout << (samples[a].second == -1 ? -1 : tab[samples[a].second]) << ; else cout << (samples[a].first == -1 ? -1 : tab[samples[a].first]) << ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int ans = 0; int temp; stack<int> st; for (int i = 0; i < n; ++i) { cin >> temp; while (!st.empty() && st.top() < temp) { ans = max(ans, (st.top() ^ temp)); st.pop(); } if (!st.empty()) ans = max(ans, (st.top() ^ temp)); st.push(temp); } temp = st.top(); st.pop(); while (!st.empty()) { ans = max(ans, (st.top() ^ temp)); temp = st.top(); st.pop(); } cout << ans, cout << endl; return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_core(clock, resetn, dataa, datab, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input valid_in, stall_in;
output valid_out, stall_out;
input enable;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
parameter FINITE_MATH_ONLY = 0;
parameter REMOVE_STICKY = 0;
// Total Latency = 12-7.
wire [26:0] input_a_mantissa;
wire [26:0] input_b_mantissa;
wire input_a_sign, input_b_sign;
wire [8:0] input_a_exponent;
wire [8:0] input_b_exponent;
wire [26:0] left_mantissa;
wire [26:0] right_mantissa;
wire left_sign, right_sign, align_valid_out;
wire [8:0] align_exponent;
wire stall_align;
wire conversion_valid, alignment_stall;
acl_fp_convert_to_internal left(
.clock(clock),
.resetn(resetn),
.data(dataa),
.mantissa(input_a_mantissa),
.exponent(input_a_exponent),
.sign(input_a_sign),
.valid_in(valid_in),
.valid_out(conversion_valid),
.stall_in(alignment_stall),
.stall_out(stall_out),
.enable(enable));
defparam left.HIGH_CAPACITY = HIGH_CAPACITY;
defparam left.FLUSH_DENORMS = FLUSH_DENORMS;
defparam left.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_convert_to_internal right(
.clock(clock),
.resetn(resetn),
.data(datab),
.mantissa(input_b_mantissa),
.exponent(input_b_exponent),
.sign(input_b_sign),
.valid_in(valid_in),
.valid_out(),
.stall_in(alignment_stall),
.stall_out(),
.enable(enable));
defparam right.HIGH_CAPACITY = HIGH_CAPACITY;
defparam right.FLUSH_DENORMS = FLUSH_DENORMS;
defparam right.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_custom_align alignment(
.clock(clock),
.resetn(resetn),
.input_a_mantissa(input_a_mantissa),
.input_a_exponent(input_a_exponent),
.input_a_sign(input_a_sign),
.input_b_mantissa(input_b_mantissa),
.input_b_exponent(input_b_exponent),
.input_b_sign(input_b_sign),
.left_mantissa(left_mantissa),
.left_exponent(align_exponent),
.left_sign(left_sign),
.right_mantissa(right_mantissa),
.right_exponent(),
.right_sign(right_sign),
.valid_in(conversion_valid),
.valid_out(align_valid_out),
.stall_in(stall_align),
.stall_out(alignment_stall),
.enable(enable));
defparam alignment.HIGH_CAPACITY = HIGH_CAPACITY;
defparam alignment.FLUSH_DENORMS = FLUSH_DENORMS;
defparam alignment.HIGH_LATENCY = HIGH_LATENCY;
defparam alignment.ROUNDING_MODE = ROUNDING_MODE;
defparam alignment.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
defparam alignment.REMOVE_STICKY = REMOVE_STICKY;
wire [27:0] resulting_mantissa;
wire [8:0] resulting_exponent;
wire resulting_sign;
wire valid_sum;
wire stall_sum;
acl_fp_custom_add_op op(
.clock(clock),
.resetn(resetn),
.left_mantissa(left_mantissa),
.right_mantissa(right_mantissa),
.left_sign(left_sign),
.right_sign(right_sign),
.common_exponent(align_exponent),
.resulting_mantissa(resulting_mantissa),
.resulting_exponent(resulting_exponent),
.resulting_sign(resulting_sign),
.valid_in(align_valid_out),
.valid_out(valid_sum),
.stall_in(stall_sum),
.stall_out(stall_align),
.enable(enable));
defparam op.HIGH_CAPACITY = HIGH_CAPACITY;
wire stall_from_norm;
wire [27:0] new_mantissa;
wire [8:0] new_exponent;
wire new_sign, new_valid;
generate
if ((HIGH_CAPACITY==1) && (HIGH_LATENCY==1))
begin
// Staging register.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [27:0] mantissa_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [7:0] exponent_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg sign_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg staging_valid;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
staging_valid <= 1'b0;
mantissa_str <= 28'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
exponent_str <= 8'bxxxxxxxx;
sign_str <= 1'bx;
end
else
begin
if (~stall_from_norm)
staging_valid <= 1'b0;
else if (~staging_valid)
staging_valid <= valid_sum;
if (~staging_valid)
begin
mantissa_str <= resulting_mantissa;
exponent_str <= resulting_exponent;
sign_str <= resulting_sign;
end
end
end
assign new_mantissa = staging_valid ? mantissa_str : resulting_mantissa;
assign new_exponent = staging_valid ? exponent_str : resulting_exponent;
assign new_sign = staging_valid ? sign_str : resulting_sign;
assign new_valid = valid_sum | staging_valid;
assign stall_sum = staging_valid;
end
else
begin
assign new_mantissa = resulting_mantissa;
assign new_exponent = resulting_exponent;
assign new_sign = resulting_sign;
assign new_valid = valid_sum;
assign stall_sum = stall_from_norm;
end
endgenerate
wire rednorm_valid_out, stall_from_round;
wire [26:0] mantissa_norm;
wire [8:0] exponent_norm;
wire sign_norm;
acl_fp_custom_reduced_normalize rednorm(
.clock(clock),
.resetn(resetn),
.mantissa(new_mantissa),
.exponent(new_exponent),
.sign(new_sign),
.stall_in(stall_from_round),
.valid_in(new_valid),
.stall_out(stall_from_norm),
.valid_out(rednorm_valid_out),
.enable(enable),
.mantissa_out(mantissa_norm),
.exponent_out(exponent_norm),
.sign_out(sign_norm));
defparam rednorm.HIGH_CAPACITY = HIGH_CAPACITY;
defparam rednorm.FLUSH_DENORMS = FLUSH_DENORMS;
defparam rednorm.HIGH_LATENCY = HIGH_LATENCY;
defparam rednorm.REMOVE_STICKY = REMOVE_STICKY;
defparam rednorm.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
wire round_valid_out, stall_from_ieee;
wire [26:0] mantissa_round;
wire [8:0] exponent_round;
wire sign_round;
acl_fp_custom_round_post round(
.clock(clock),
.resetn(resetn),
.mantissa(mantissa_norm),
.exponent(exponent_norm),
.sign(sign_norm),
.mantissa_out(mantissa_round),
.exponent_out(exponent_round),
.sign_out(sign_round),
.valid_in(rednorm_valid_out),
.valid_out(round_valid_out),
.stall_in(stall_from_ieee),
.stall_out(stall_from_round),
.enable(enable));
defparam round.HIGH_CAPACITY = HIGH_CAPACITY;
defparam round.FLUSH_DENORMS = FLUSH_DENORMS;
defparam round.HIGH_LATENCY = HIGH_LATENCY;
defparam round.ROUNDING_MODE = ROUNDING_MODE;
defparam round.REMOVE_STICKY = REMOVE_STICKY;
defparam round.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_convert_to_ieee toieee(
.clock(clock),
.resetn(resetn),
.mantissa(mantissa_round),
.exponent(exponent_round),
.sign(sign_round),
.result(result),
.valid_in(round_valid_out),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_from_ieee),
.enable(enable));
defparam toieee.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__FAHCIN_FUNCTIONAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_FUNCTIONAL_V |
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
spd module
@modified by Zhiyang Ong on November 1, 2007
The output out signal must be of the data type reg
I had to reallocate this data-type reg.
Correction: It is relabelled to the wire data type since
it is not used again, or explicitly assigned a value in
this module
*/
`include "spdu.v"
`include "demux2to4.v"
`include "selector.v"
module spd (d0, d1, d2, d3, pm0, pm1, pm2, pm3, out, clk, reset);
// outputs
output out;
// inputs
input d0, d1, d2, d3;
input [3:0] pm0, pm1, pm2, pm3;
input clk, reset;
// @modified by Zhiyang Ong on November 1, 2007
// Registers...
// reg out;
/*
reg selectord0, selectord1;
reg spdu0out0, spdu0out1, spdu0out2, spdu0out3;
reg spdu1out0, spdu1out1, spdu1out2, spdu1out3;
reg spdu2out0, spdu2out1, spdu2out2, spdu2out3;
reg spdu3out0, spdu3out1, spdu3out2, spdu3out3;
reg spdu4out0, spdu4out1, spdu4out2, spdu4out3;
reg spdu5out0, spdu5out1, spdu5out2, spdu5out3;
reg spdu6out0, spdu6out1, spdu6out2, spdu6out3;
reg spdu7out0, spdu7out1, spdu7out2, spdu7out3;
reg spdu8out0, spdu8out1, spdu8out2, spdu8out3;
reg spdu9out0, spdu9out1, spdu9out2, spdu9out3;
reg spdu10out0, spdu10out1, spdu10out2, spdu10out3;
reg spdu11out0, spdu11out1, spdu11out2, spdu11out3;
reg spdu12out0, spdu12out1, spdu12out2, spdu12out3;
reg spdu13out0, spdu13out1, spdu13out2, spdu13out3;
reg spdu14out0, spdu14out1, spdu14out2, spdu14out3;
*/
// wires
// @Modified by Zhiyang Ong on November 1, 2007
wire out;
wire selectord0, selectord1;
wire spdu0out0, spdu0out1, spdu0out2, spdu0out3;
wire spdu1out0, spdu1out1, spdu1out2, spdu1out3;
wire spdu2out0, spdu2out1, spdu2out2, spdu2out3;
wire spdu3out0, spdu3out1, spdu3out2, spdu3out3;
wire spdu4out0, spdu4out1, spdu4out2, spdu4out3;
wire spdu5out0, spdu5out1, spdu5out2, spdu5out3;
wire spdu6out0, spdu6out1, spdu6out2, spdu6out3;
wire spdu7out0, spdu7out1, spdu7out2, spdu7out3;
wire spdu8out0, spdu8out1, spdu8out2, spdu8out3;
wire spdu9out0, spdu9out1, spdu9out2, spdu9out3;
wire spdu10out0, spdu10out1, spdu10out2, spdu10out3;
wire spdu11out0, spdu11out1, spdu11out2, spdu11out3;
wire spdu12out0, spdu12out1, spdu12out2, spdu12out3;
wire spdu13out0, spdu13out1, spdu13out2, spdu13out3;
wire spdu14out0, spdu14out1, spdu14out2, spdu14out3;
spdu spdu0(1'b0,
1'b0,
1'b1,
1'b1, d0, d1, d2, d3,
spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, clk, reset);
spdu spdu1(spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, d0, d1, d2, d3,
spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, clk, reset);
spdu spdu2(spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, d0, d1, d2, d3,
spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, clk, reset);
spdu spdu3(spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, d0, d1, d2, d3,
spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, clk, reset);
spdu spdu4(spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, d0, d1, d2, d3,
spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, clk, reset);
spdu spdu5(spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, d0, d1, d2, d3,
spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, clk, reset);
spdu spdu6(spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, d0, d1, d2, d3,
spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, clk, reset);
spdu spdu7(spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, d0, d1, d2, d3,
spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, clk, reset);
spdu spdu8(spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, d0, d1, d2, d3,
spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, clk, reset);
spdu spdu9(spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, d0, d1, d2, d3,
spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, clk, reset);
spdu spdu10(spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, d0, d1, d2, d3,
spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, clk, reset);
spdu spdu11(spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, d0, d1, d2, d3,
spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, clk, reset);
spdu spdu12(spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, d0, d1, d2, d3,
spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, clk, reset);
spdu spdu13(spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, d0, d1, d2, d3,
spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, clk, reset);
spdu spdu14(spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, d0, d1, d2, d3,
spdu14out0,
spdu14out1,
spdu14out2,
spdu14out3, clk, reset);
selector selector1 (pm0, pm1, pm2, pm3, selectord0, selectord1);
demux demux1 (spdu14out0, spdu14out1, spdu14out2, spdu14out3,
selectord0, selectord1, out);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2016 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//
// Special cases of "string parameters" :
// This table compares obtain results from big-3 simulators to Verilator
// expected behavior. Base specified integer literals are also included as
// string detection may impact results for such cases.
//
// | Option/Param file | simulator 1 | simulator 2 | simulator 3 | verilator |
// |---------------------|-------------|-------------|-------------|-------------|
// | -gC0='"AB CD"' | AB CD | UNSUPPORTED | AB CD | AB CD |
// | -gC1=\"AB\ CD\" | AB CD | UNSUPPORTED | UNSUPPORTED | AB CD |
// | -gC2="\"AB CD\"" | AB CD | AB CD | AB CD | AB CD |
// | -gC3="\"AB\ CD\"" | AB CD | AB\\ CD | AB CD | AB CD |
// | -gC4=32'h600D600D | UNSUPPORTED | 32'h600D600D| 32'h600D600D| 32'h600D600D|
// | -gC5=32\'h600D600D | 32'h600D600D| UNSUPPORTED | UNSUPPORTED | 32'h600D600D|
// | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D|
// | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED |
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); $stop; end while(0);
module t;
parameter string1 = "Original String";
parameter string2 = "Original String";
parameter string11 = "Original String";
parameter string12 = "Original String";
parameter string21 = "Original String";
parameter string22 = "Original String";
parameter real11 = 0.1;
parameter real12 = 0.1;
parameter real21 = 0.1;
parameter real22 = 0.1;
parameter real31 = 0.1;
parameter real32 = 0.1;
parameter real41 = 0.1;
parameter real42 = 0.1;
parameter real51 = 0.1;
parameter real52 = 0.1;
parameter int11 = 1;
parameter int12 = 1;
parameter int21 = 1;
parameter int22 = 1;
parameter int31 = 1;
parameter int32 = 1;
parameter int41 = 1;
parameter int42 = 1;
parameter int51 = 1;
parameter int52 = 1;
parameter int61 = 1;
parameter int62 = 1;
parameter int71 = 1;
parameter int72 = 1;
initial begin
`check(string1,"New String");
`check(string2,"New String");
`check(string11,"New String");
`check(string12,"New String");
`check(string21,"New String");
`check(string22,"New String");
`check(real11,0.2);
`check(real12,0.2);
`check(real21,400);
`check(real22,400);
`check(real31,20);
`check(real32,20);
`check(real41,582.5);
`check(real42,582.5);
`check(real51,145.5);
`check(real52,145.5);
`check(int11,16);
`check(int12,16);
`check(int21,16);
`check(int22,16);
`check(int31,123);
`check(int32,123);
`check(int41,32'hdeadbeef);
`check(int42,32'hdeadbeef);
`check(int51,32'hdeadbeef);
`check(int52,32'hdeadbeef);
`check(int61,32'hdeadbeef);
`check(int62,32'hdeadbeef);
`check(int71,-1000);
`check(int72,-1000);
// Check parameter assigned simple integer literal is signed
if ((int11 << 27) >>> 31 != -1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: COMMAND_RAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module COMMAND_RAM (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [10:0] rdaddress;
input [11:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
// Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_RAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; int n; while (cin >> n) { cin >> s; int gold = 0, cnt = 0, prev = 0, ans = 0; for (auto ch : s) { if (ch == G ) gold++, cnt++; else prev = cnt, cnt = 0; ans = max(ans, prev + cnt + 1); } ans = min(ans, gold); cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long cnt, ans, i, j, temp, flag; string s, heavy = heavy , metal = metal ; int main() { cin >> s; for (i = 0; i < s.length(); i++) { temp = i; flag = 0; for (j = 0; j < 5; j++) { if (s[temp] == heavy[j]) ++temp; else break; } if (j == 5) flag = 1, ++cnt; if (flag) { i = temp - 2; continue; } temp = i; for (j = 0; j < 5; j++) { if (s[temp] == metal[j]) ++temp; else break; } if (j == 5) flag = 1, ans += cnt; if (flag) { i = temp - 2; continue; } } cout << ans; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ohat.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ohat (
address,
clock,
q);
input [15:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../Samples/Drums/TR606KIT/606OHAT.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../Samples/Drums/TR606KIT/606OHAT.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../Samples/Drums/TR606KIT/606OHAT.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ohat.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ohat.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ohat.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ohat.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ohat_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ohat_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int res; int tox[] = {0, 0, 1, -1}; int toy[] = {1, -1, 0, 0}; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); string s; cin >> s; while (s.back() == 0 ) s.erase(s.size() - 1, 1), res++; while (s != 1 ) { while (s.size() && s.back() == 1 ) s.erase(s.size() - 1, 1), res++; res++; if (!s.size()) break; s.back() = 1 ; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; long long f[110][2][2]; int ans[110]; int n; long long k; long long calc(long long x, long long a, long long b) { if (f[x][a][b] != -1) return f[x][a][b]; f[x][a][b] = 0; int y = n - x + 1; if (x > y) return f[x][a][b] = 1; for (int i = 0; i < 2; i++) if (ans[x] == -1 || ans[x] == i) for (int j = 0; j < 2; j++) if (ans[y] == -1 || ans[y] == j) if (i == j || x < y) if (a || i <= j) if (b || i + j <= 1) f[x][a][b] += calc(x + 1, a || (i < j), b || ((i + j) <= 0)); return f[x][a][b]; } int main() { scanf( %d %I64d , &n, &k); k++; memset(f, -1, sizeof(f)); memset(ans, -1, sizeof(ans)); if (calc(1, 0, 0) < k) return puts( -1 ), 0; for (int i = 1; i <= n; i++) { memset(f, -1, sizeof(f)); ans[i] = 0; if (calc(1, 0, 0) < k) { k -= calc(1, 0, 0); ans[i] = 1; } } for (int i = 1; i <= n; i++) printf( %d , ans[i]); puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_2_V
`define SKY130_FD_SC_LS__TAPMET1_2_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog wrapper for tapmet1 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapmet1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapmet1_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapmet1 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapmet1_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapmet1 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_2_V
|
#include <bits/stdc++.h> using namespace std; vector<long long> a; bool valido; vector<vector<long long>> adj; long long d; void dfs(long long u, long long p = 0) { if (!valido) return; for (long long v : adj[u]) if (v != p) dfs(v, u); if (a[u] % d == 0) { a[p]++; } else { a[u]++; if (p == 0 || a[u] % d != 0) valido = 0; } } int32_t main() { long long t; cin >> t; while (t--) { long long n; cin >> n; a.resize(n + 1); adj = vector<vector<long long>>(n + 1); for (long long i = 0; i < n - 1; i++) { long long a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } vector<long long> freq(n + 1); freq[1] = 2; for (long long i = 1; i < n - 1; i++) freq[1] = 2 * freq[1] % 998244353; for (d = 2; d <= n - 1; d++) { if ((n - 1) % d == 0) { valido = 1; fill(a.begin(), a.end(), 0); dfs(1); freq[d] = valido; } } vector<long long> res(n + 1); for (long long d = n; d >= 1; d--) { res[d] = freq[d]; for (long long mult = 2 * d; mult <= n; mult += d) { res[d] = res[d] - res[mult] + 998244353; res[d] %= 998244353; } } for (long long d = 1; d <= n; d++) { cout << res[d] << ; } cout << endl; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
// bug1475
module t (/*AUTOARG*/
// Outputs
ID_45, IDa_f4c,
// Inputs
clk, ID_d9f, IDa_657, ID_477
);
input clk;
output reg ID_45;
input ID_d9f;
input IDa_657;
output reg IDa_f4c;
reg ID_13;
input ID_477;
reg ID_489;
reg ID_8d1;
reg IDa_183;
reg IDa_91c;
reg IDa_a96;
reg IDa_d6b;
reg IDa_eb9;
wire ID_fc8 = ID_d9f & ID_13; //<<
wire ID_254 = ID_d9f & ID_13;
wire ID_f40 = ID_fc8 ? ID_8d1 : 0;
wire ID_f4c = ID_fc8 ? 0 : ID_477;
wire ID_442 = IDa_91c;
wire ID_825 = ID_489;
always @(posedge clk) begin
ID_13 <= ID_f40;
ID_8d1 <= IDa_eb9;
ID_489 <= ID_442;
ID_45 <= ID_825;
IDa_d6b <= IDa_a96;
IDa_f4c <= ID_f4c;
if (ID_254) begin
IDa_91c <= IDa_d6b;
IDa_183 <= IDa_657;
IDa_a96 <= IDa_657;
IDa_eb9 <= IDa_183;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_SYMBOL_V
`define SKY130_FD_SC_LS__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; int x[20005], y[20005], c[20005], ans[20005], LOC; bool cmp(const int &u, const int &v) { return (x[u] - x[LOC]) * (y[v] - y[LOC]) - (y[u] - y[LOC]) * (x[v] - x[LOC]) < 0; } void solve(int l, int r) { if (l > r) return; int loc = l; for (int i = (l), LIM = (r); i <= LIM; i++) if (x[c[i]] < x[c[loc]]) loc = i; swap(c[loc], c[l]); LOC = c[l]; sort(c + l + 1, c + r + 1, cmp); int s0 = 0, s1 = 0, k = -100000; for (int i = (l + 1), LIM = (r); i <= LIM; i++) { if (s0 == s1 && ((c[i] <= n) ^ (c[l] <= n))) { if (k == -100000 || max(k - l - 1, r - k) > max(i - l - 1, r - i)) k = i; } if (c[i] <= n) s0++; else s1++; } ans[c[l]] = c[k], ans[c[k]] = c[l]; solve(l + 1, k - 1), solve(k + 1, r); } int main() { scanf( %d , &n); for (int i = (1), LIM = (2 * n); i <= LIM; i++) scanf( %d%d , &x[i], &y[i]), c[i] = i; solve(1, 2 * n); for (int i = (1), LIM = (n); i <= LIM; i++) printf( %d n , ans[i] - n); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:17:42 07/10/2015
// Design Name:
// Module Name: Test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Test
( input PixelClk2,
input VSync,
output reg [5:0] XOffsetData,
output reg [9:0] YOffsetData,
output reg OffsetWrite
);
integer StatusL1;
integer Xdir;
integer Ydir;
initial
begin
StatusL1 = 0;
XOffsetData = 0;
YOffsetData = 0;
OffsetWrite = 0;
Xdir = 1;
Ydir = 1;
end
always @(negedge PixelClk2)
begin
case(StatusL1)
0: begin
XOffsetData = 0;
YOffsetData = 0;
Xdir = 1;
Ydir = 1;
StatusL1 = 1;
end
1: begin
if (VSync == 1) StatusL1 = 2;
end
2: begin
if (VSync == 0) StatusL1 = 3;
end
3: begin
OffsetWrite = 1;
StatusL1 = 4;
end
4: begin
OffsetWrite = 0;
if (XOffsetData == 6'b111111) Xdir = -1;
else if (XOffsetData == 6'b000000) Xdir = 1;
else Xdir = Xdir;
if (YOffsetData == 10'b1111111111) Ydir = -1;
else if (YOffsetData == 10'b0000000000) Ydir = 1;
else Ydir = Ydir;
StatusL1 = 5;
end
5: begin
XOffsetData = XOffsetData + Xdir;
YOffsetData = YOffsetData + Ydir;
StatusL1 = 1;
end
6: begin
StatusL1 = 6;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
module t (/*AUTOARG*/);
bit fail;
localparam signed [3:0] bug737_p1 = 4'b1000;
wire [3:0] bug737_a = 4'b1010;
reg [5:0] bug737_y;
reg signed [3:0] w4_s;
reg signed [4:0] w5_s;
reg [3:0] w4_u;
reg [4:0] w5_u;
reg signed [8:0] w9_s;
real r;
initial begin
// verilator lint_off WIDTH
bug737_y = bug737_a + (bug737_p1 + 4'sb0);
`checkh(bug737_y, 6'b010010); //bug737
// 6u +[6u] 4s +[6s] 6s
bug737_y = 6'b001010 + (4'sb1000 + 6'sb0);
`checkh(bug737_y, 6'b010010); //bug737, getx 000010
// 6u +[6u] 4s +[6s] 6s
bug737_y = 6'b001010 + (4'b1000 + 6'sb0);
`checkh(bug737_y, 6'b010010); //ok
bug737_y = 6'b001010 + (6'sb111000 + 6'sb0);
`checkh(bug737_y, 6'b000010); //ok
// v--- sign extends to 6-bits
bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0);
`checkh(bug737_y, 6'b000010); //ok
// From t_math_signed_3
w4_s = 4'sb1111 - 1'b1;
`checkh(w4_s,33'he);
w4_s = 4'sb1111 - 5'b00001;
`checkh(w4_s,33'he);
w4_s = 4'sb1111 - 1'sb1;
`checkh(w4_s,4'h0);
w5_s = 4'sb1111 - 1'sb1;
`checkh(w5_s,4'h0);
w4_s = 4'sb1111 - 4'sb1111;
`checkh(w4_s,4'h0);
w5_s = 4'sb1111 - 4'sb1111;
`checkh(w5_s,5'h0);
// The assign LHS being signed or unsigned does not matter per IEEE
// The upper add being signed DOES matter propagating to lower
w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add
`checkh(w4_s,4'he);
w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend
`checkh(w4_s,4'h0);
w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend
`checkh(w4_s,4'he); // BUG, Verilator says 'h0
w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS
`checkh(w5_u, 5'b10000);
w4_u = 4'b1111 + 4'b0001; // Normal case
`checkh(w4_u, 4'b0000);
// Another example of promotion, the add is 4 bits wide
w4_u = 3'b111 + 3'b010;
`checkh(w4_u, 4'b1001);
//
w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter
`checkh(w4_u, 4'sb1111);
w4_s = 3'sb111 * 3'sb001; // Signed output
`checkh(w4_s, 4'sb1111);
w4_s = 3'b111 * 3'sb001; // Unsigned output
`checkh(w4_s, 4'b0111);
// Conditionals get width from parent; are assignment-like
w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11);
`checkh(w4_u, 4'b0100);
w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000);
`checkh(w4_u, 4'b0000);
// If RHS is larger, that larger size is used
w4_u = 5'b10000 / 5'b00100;
`checkh(w4_u, 4'b0100);
// bug754
w5_u = 4'sb0010 << -2'sd1; // << 3
`ifdef VCS
`checkh(w5_u, 5'b00000); // VCS E-2014.03 bug
`else
`checkh(w5_u, 5'b10000); // VCS E-2014.03 bug
`endif
w5_u = 4'sb1000 << 0; // Sign extends
`checkh(w5_u, 5'b11000);
// Reals do not propagate to children
r = 1.0 + ( 1 + (1 / 2));
`checkf(r, 2.0);
// Self determined sign extension
r = $itor(3'sb111);
`checkf(r, -1.0);
// If any part of case is real, all is real
case (22)
22.0: ;
22.1: $stop;
default: $stop;
endcase
// bug759
w5_u = { -4'sd7 };
`checkh(w5_u, 5'b01001);
w5_u = {2{ -2'sd1 }};
`checkh(w5_u, 5'b01111);
// Don't break concats....
w5_u = {{0{1'b1}}, -4'sd7 };
`checkh(w5_u, 5'b01001);
w9_s = { -4'sd7, -4'sd7 };
`checkh(w9_s, 9'b010011001);
{w5_u, {w4_u}} = 9'b10101_1100;
`checkh(w5_u, 5'b10101);
`checkh(w4_u, 4'b1100);
{w4_u} = 4'b1011;
`checkh(w4_u, 4'b1011);
if (fail) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int n = 3; long long r, g, b; void reset() { if (r >= g) swap(r, g); if (r >= b) swap(r, b); if (g >= b) swap(g, b); } int main() { while (cin >> r >> g >> b) { reset(); if ((r + g) * 2 <= b) cout << r + g << endl; else cout << (r + g + b) / 3 << endl; } return 0; } |
/**
* $Id: axi_slave.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya symplified AXI slave.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* AXI slave used also for simple bus master.
*
*
* /------\
* WR ADDRESS ----> | WR |
* WR DATA ----> | | -----------
* WR RESPONSE <---- | CH | |
* \------/ /--------\
* | SIMPLE | ---> WR/RD ADDRRESS
* AXI | | ---> WR DATA
* | RP | <--- RD DATA
* | BUS | <--- ACKNOWLEDGE
* /------\ \--------/
* RD ADDRESS ----> | RD | |
* RD DATA <---- | CH | -----------
* \------/
*
*
* Because AXI bus is quite complex simplier bus was created.
*
* It combines write and read channel, where write has bigger priority. Command
* is then send forward to red pitaya bus. When wite or read acknowledge is
* received AXI response is created and new AXI is accepted.
*
* To prevent AXI lockups because no response is received, this slave creates its
* own after 32 cycles (ack_cnt).
*
*/
module axi_slave #(
parameter AXI_DW = 64 , // data width (8,16,...,1024)
parameter AXI_AW = 32 , // address width
parameter AXI_IW = 8 , // ID width
parameter AXI_SW = AXI_DW >> 3 // strobe width - 1 bit for every data byte
)(
// global signals
input axi_clk_i , //!< AXI global clock
input axi_rstn_i , //!< AXI global reset
// axi write address channel
input [ AXI_IW-1: 0] axi_awid_i , //!< AXI write address ID
input [ AXI_AW-1: 0] axi_awaddr_i , //!< AXI write address
input [ 4-1: 0] axi_awlen_i , //!< AXI write burst length
input [ 3-1: 0] axi_awsize_i , //!< AXI write burst size
input [ 2-1: 0] axi_awburst_i , //!< AXI write burst type
input [ 2-1: 0] axi_awlock_i , //!< AXI write lock type
input [ 4-1: 0] axi_awcache_i , //!< AXI write cache type
input [ 3-1: 0] axi_awprot_i , //!< AXI write protection type
input axi_awvalid_i , //!< AXI write address valid
output axi_awready_o , //!< AXI write ready
// axi write data channel
input [ AXI_IW-1: 0] axi_wid_i , //!< AXI write data ID
input [ AXI_DW-1: 0] axi_wdata_i , //!< AXI write data
input [ AXI_SW-1: 0] axi_wstrb_i , //!< AXI write strobes
input axi_wlast_i , //!< AXI write last
input axi_wvalid_i , //!< AXI write valid
output axi_wready_o , //!< AXI write ready
// axi write response channel
output [ AXI_IW-1: 0] axi_bid_o , //!< AXI write response ID
output reg [ 2-1: 0] axi_bresp_o , //!< AXI write response
output reg axi_bvalid_o , //!< AXI write response valid
input axi_bready_i , //!< AXI write response ready
// axi read address channel
input [ AXI_IW-1: 0] axi_arid_i , //!< AXI read address ID
input [ AXI_AW-1: 0] axi_araddr_i , //!< AXI read address
input [ 4-1: 0] axi_arlen_i , //!< AXI read burst length
input [ 3-1: 0] axi_arsize_i , //!< AXI read burst size
input [ 2-1: 0] axi_arburst_i , //!< AXI read burst type
input [ 2-1: 0] axi_arlock_i , //!< AXI read lock type
input [ 4-1: 0] axi_arcache_i , //!< AXI read cache type
input [ 3-1: 0] axi_arprot_i , //!< AXI read protection type
input axi_arvalid_i , //!< AXI read address valid
output axi_arready_o , //!< AXI read address ready
// axi read data channel
output [ AXI_IW-1: 0] axi_rid_o , //!< AXI read response ID
output reg [ AXI_DW-1: 0] axi_rdata_o , //!< AXI read data
output reg [ 2-1: 0] axi_rresp_o , //!< AXI read response
output reg axi_rlast_o , //!< AXI read last
output reg axi_rvalid_o , //!< AXI read response valid
input axi_rready_i , //!< AXI read response ready
// RP system read/write channel
output [ AXI_AW-1: 0] sys_addr_o , //!< system bus read/write address.
output [ AXI_DW-1: 0] sys_wdata_o , //!< system bus write data.
output reg [ AXI_SW-1: 0] sys_sel_o , //!< system bus write byte select.
output reg sys_wen_o , //!< system bus write enable.
output reg sys_ren_o , //!< system bus read enable.
input [ AXI_DW-1: 0] sys_rdata_i , //!< system bus read data.
input sys_err_i , //!< system bus error indicator.
input sys_ack_i //!< system bus acknowledge signal.
);
//---------------------------------------------------------------------------------
// AXI slave Module
//---------------------------------------------------------------------------------
wire ack ;
reg [ 6-1: 0] ack_cnt ;
reg rd_do ;
reg [ AXI_IW-1: 0] rd_arid ;
reg [ AXI_AW-1: 0] rd_araddr ;
reg rd_error ;
wire rd_errorw ;
reg wr_do ;
reg [ AXI_IW-1: 0] wr_awid ;
reg [ AXI_AW-1: 0] wr_awaddr ;
reg [ AXI_IW-1: 0] wr_wid ;
reg [ AXI_DW-1: 0] wr_wdata ;
reg wr_error ;
wire wr_errorw ;
assign wr_errorw = (axi_awlen_i != 4'h0) || (axi_awsize_i != 3'b010); // error if write burst and more/less than 4B transfer
assign rd_errorw = (axi_arlen_i != 4'h0) || (axi_arsize_i != 3'b010); // error if read burst and more/less than 4B transfer
always @(posedge axi_clk_i)
if (axi_rstn_i == 1'b0) begin
rd_do <= 1'b0 ;
rd_error <= 1'b0 ;
end else begin
if (axi_arvalid_i && !rd_do && !axi_awvalid_i && !wr_do) // accept just one read request - write has priority
rd_do <= 1'b1 ;
else if (axi_rready_i && rd_do && ack)
rd_do <= 1'b0 ;
if (axi_arvalid_i && axi_arready_o) begin // latch ID and address
rd_arid <= axi_arid_i ;
rd_araddr <= axi_araddr_i ;
rd_error <= rd_errorw ;
end
end
always @(posedge axi_clk_i)
if (axi_rstn_i == 1'b0) begin
wr_do <= 1'b0 ;
wr_error <= 1'b0 ;
end else begin
if (axi_awvalid_i && !wr_do && !rd_do) // accept just one write request - if idle
wr_do <= 1'b1 ;
else if (axi_bready_i && wr_do && ack)
wr_do <= 1'b0 ;
if (axi_awvalid_i && axi_awready_o) begin // latch ID and address
wr_awid <= axi_awid_i ;
wr_awaddr <= axi_awaddr_i ;
wr_error <= wr_errorw ;
end
if (axi_wvalid_i && wr_do) begin // latch ID and write data
wr_wid <= axi_wid_i ;
wr_wdata <= axi_wdata_i ;
end
end
assign axi_awready_o = !wr_do && !rd_do ;
assign axi_wready_o = (wr_do && axi_wvalid_i) || (wr_errorw && axi_wvalid_i) ;
assign axi_bid_o = wr_awid ;
assign axi_arready_o = !rd_do && !wr_do && !axi_awvalid_i ;
assign axi_rid_o = rd_arid ;
always @(posedge axi_clk_i)
if (axi_rstn_i == 1'b0) begin
axi_bvalid_o <= 1'b0 ;
axi_bresp_o <= 2'h0 ;
axi_rlast_o <= 1'b0 ;
axi_rvalid_o <= 1'b0 ;
axi_rresp_o <= 2'h0 ;
end else begin
axi_bvalid_o <= wr_do && ack ;
axi_bresp_o <= {(wr_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
axi_rlast_o <= rd_do && ack ;
axi_rvalid_o <= rd_do && ack ;
axi_rresp_o <= {(rd_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
axi_rdata_o <= sys_rdata_i ;
end
// acknowledge protection
always @(posedge axi_clk_i)
if (axi_rstn_i == 1'b0) begin
ack_cnt <= 6'h0 ;
end else begin
if ((axi_arvalid_i && axi_arready_o) || (axi_awvalid_i && axi_awready_o)) // rd || wr request
ack_cnt <= 6'h1 ;
else if (ack)
ack_cnt <= 6'h0 ;
else if (|ack_cnt)
ack_cnt <= ack_cnt + 6'h1 ;
end
assign ack = sys_ack_i || ack_cnt[5] || (rd_do && rd_errorw) || (wr_do && wr_errorw); // bus acknowledge or timeout or error
//------------------------------------------
// Simple slave interface
always @(posedge axi_clk_i)
if (axi_rstn_i == 1'b0) begin
sys_wen_o <= 1'b0 ;
sys_ren_o <= 1'b0 ;
sys_sel_o <= {AXI_SW{1'b0}} ;
end else begin
sys_wen_o <= wr_do && axi_wvalid_i && !wr_errorw ;
sys_ren_o <= axi_arvalid_i && axi_arready_o && !rd_errorw ;
sys_sel_o <= {AXI_SW{1'b1}} ;
end
assign sys_addr_o = rd_do ? rd_araddr : wr_awaddr ;
assign sys_wdata_o = wr_wdata ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__CLKBUF_BEHAVIORAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int t, n; cin >> t; while (t--) { cin >> n; int a = 0, b = 0, k = 2; for (int i = 0; i < n / 2 - 1; i++) { a += k; k *= 2; } for (int i = 0; i < n / 2; i++) { b += k; k *= 2; } a += k; cout << abs(a - b) << endl; } } |
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_sync_fifo
*
*/
`default_nettype none
module openhmc_sync_fifo #(
`ifdef CAG_ASSERTIONS
parameter DISABLE_EMPTY_ASSERT = 0,
parameter DISABLE_SHIFT_OUT_ASSERT = 0,
parameter DISABLE_XCHECK_ASSERT = 0,
`endif
parameter DATASIZE = 8,
parameter ADDRSIZE = 8
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----Signals
//----------------------------------
input wire [DATASIZE-1:0] d_in,
input wire shift_in,
input wire shift_out,
output wire [DATASIZE-1:0] d_out,
output wire empty
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire si, so; // internal gated shift signals
reg full_r1, full_r2;
wire full_1, full_2, full_3;
reg full_m2, full_m1;
reg [DATASIZE-1:0] d_out_r1, d_out_r2;
wire [DATASIZE-1:0] d_out_m2, d_out_2, d_out_3;
wire mux_rm_2;
reg [ADDRSIZE -1:0] ra_m, wa_m; //addr after register similar to signal internal to sram
reg [ADDRSIZE -1:0] ra, wa; // address calculated for the next read
wire wen, ren;
wire m_empty;
assign full_1 = full_r1 || full_m1 || (full_m2 && full_r2);
assign full_2 = full_r2 || full_m2;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
d_out_r1 <= {DATASIZE {1'b0}};
d_out_r2 <= {DATASIZE {1'b0}};
full_r1 <= 1'b0;
full_r2 <= 1'b0;
end else begin
// Register stage 1 (conditions shouldn't overlap)
if ((full_2 && !full_1 && si && !so) || // fill stage
(full_1 && m_empty && si && so)) begin // shift through
d_out_r1 <= d_in;
full_r1 <= 1'b1;
end
if (full_r1 && so && (!si || !m_empty)) begin // shift out
full_r1 <= 1'b0;
end
// Register stage 2 (conditions shouldn't overlap)
if (full_3 && ((!full_2 && si && !so) || // fill stage
(full_2 && !full_1 && si && so))) begin // shift through
d_out_r2 <= d_in;
full_r2 <= 1'b1;
end
if (full_r1 && so) begin // shift through
d_out_r2 <= d_out_r1;
full_r2 <= 1'b1;
end
if (full_m2 && ((!full_r2 && !so) || // Rescue
(full_r2 && so))) begin
d_out_r2 <= d_out_m2;
full_r2 <= 1'b1;
end
if (full_r2 &&
((!full_r1 && !full_m2 && so && !si) || // shift out
(full_m1 && si && so))) begin // shift through with RAM
full_r2 <= 1'b0;
end
end
end
// assign outputs and inputs to module interface
assign d_out = d_out_3;
assign empty = !full_3; // if the last stage is empty, the fifo is empty
assign si = shift_in;
assign so = shift_out;
wire [ADDRSIZE:0] fifo_ram_count = wa_m - ra_m;
assign mux_rm_2 = full_r2; // mux control of SRAM data bypass if only one value in stage r2
assign d_out_2 = mux_rm_2 ? d_out_r2 : d_out_m2; // additional data mux for SRAM bypass
// write port control of SRAM
assign wen = si && !so && full_1 // enter new value into SRAM, because regs are filled
|| si && !m_empty; // if a value is in the SRAM, then we have to shift through or shift in
// read port control of SRAM
assign ren = so && !m_empty;
assign m_empty = (wa_m == ra_m);
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
full_m1 <= 1'b0;
full_m2 <= 1'b0;
end else begin
full_m1 <= ren; // no control of m1
full_m2 <= full_m1
|| full_m2 && !so && full_r2; // no rescue possible
end
end
// pointer management
always @(*) begin
wa = wa_m + 1'b1; // wa_m is the address stored in mem addr register
ra = ra_m + 1'b1;
end
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
wa_m <= {ADDRSIZE {1'b0}};
ra_m <= {ADDRSIZE {1'b0}};
end else begin
if (wen) begin
wa_m <= wa; // next mem write addr to mem addr register
end
if (ren) begin
ra_m <= ra;
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
openhmc_sync_fifo_reg_stage #(.DWIDTH(DATASIZE))
sync_fifo_reg_stage_3_I (
.clk(clk),
.res_n(res_n),
.d_in(d_in),
.d_in_p(d_out_2),
.p_full(full_2),
.n_full(1'b1),
.si(si),
.so(so),
.full(full_3),
.d_out(d_out_3)
);
openhmc_ram #(
.DATASIZE(DATASIZE), // Memory data word width
.ADDRSIZE(ADDRSIZE), // Number of memory address bits
.PIPELINED(1)
)
ram(
.clk(clk),
.wen(wen),
.wdata(d_in),
.waddr(wa),
.ren(ren),
.raddr(ra),
.rdata(d_out_m2)
);
`ifdef CAG_ASSERTIONS
if (DISABLE_SHIFT_OUT_ASSERT == 0)
shift_out_and_empty: assert property (@(posedge clk) disable iff(!res_n) (shift_out |-> !empty));
if (DISABLE_XCHECK_ASSERT == 0)
dout_known: assert property (@(posedge clk) disable iff(!res_n) (!empty |-> !$isunknown(d_out)));
final
begin
if (DISABLE_EMPTY_ASSERT == 0)
begin
empty_not_set_assert: assert (empty);
end
end
`endif // CAG_ASSERTIONS
endmodule
`default_nettype wire
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length Encoder, intermediate results ////
//// ////
//// - Translate DC and AC coeff. into: ////
//// 1) zero-run-length ////
//// 2) bit-size for amplitude ////
//// 3) amplitude ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rle1.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rle1.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rle1(clk, rst, ena, go, din, rlen, size, amp, den, dcterm);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input go;
input [11:0] din; // data input
output [ 3:0] rlen; // run-length
output [ 3:0] size; // size (or category)
output [11:0] amp; // amplitude
output den; // data output enable
output dcterm; // DC-term (start of new block)
reg [ 3:0] rlen, size;
reg [11:0] amp;
reg den, dcterm;
//
// variables
//
reg [5:0] sample_cnt;
reg [3:0] zero_cnt;
wire is_zero;
reg state;
parameter dc = 1'b0;
parameter ac = 1'b1;
//
// module body
//
//
// function declarations
//
// Function abs; absolute value
function [10:0] abs;
input [11:0] a;
begin
if (a[11])
abs = (~a[10:0]) +11'h1;
else
abs = a[10:0];
end
endfunction
// Function cat, calculates category for Din
function [3:0] cat;
input [11:0] a;
reg [10:0] tmp;
begin
// get absolute value
tmp = abs(a);
// determine category
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : cat = 4'hb; // 1024..2047
11'b01?_????_???? : cat = 4'ha; // 512..1023
11'b001_????_???? : cat = 4'h9; // 256.. 511
11'b000_1???_???? : cat = 4'h8; // 128.. 255
11'b000_01??_???? : cat = 4'h7; // 64.. 127
11'b000_001?_???? : cat = 4'h6; // 32.. 63
11'b000_0001_???? : cat = 4'h5; // 16.. 31
11'b000_0000_1??? : cat = 4'h4; // 8.. 15
11'b000_0000_01?? : cat = 4'h3; // 4.. 7
11'b000_0000_001? : cat = 4'h2; // 2.. 3
11'b000_0000_0001 : cat = 4'h1; // 1
11'b000_0000_0000 : cat = 4'h0; // 0 (DC only)
endcase
end
endfunction
// Function modamp, calculate additional bits per category
function [10:0] rem;
input [11:0] a;
reg [10:0] tmp, tmp_rem;
begin
tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];
if(0)
begin
// get absolute value
tmp = abs(a);
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : rem = tmp_rem & 11'b111_1111_1111;
11'b01?_????_???? : rem = tmp_rem & 11'b011_1111_1111;
11'b001_????_???? : rem = tmp_rem & 11'b001_1111_1111;
11'b000_1???_???? : rem = tmp_rem & 11'b000_1111_1111;
11'b000_01??_???? : rem = tmp_rem & 11'b000_0111_1111;
11'b000_001?_???? : rem = tmp_rem & 11'b000_0011_1111;
11'b000_0001_???? : rem = tmp_rem & 11'b000_0001_1111;
11'b000_0000_1??? : rem = tmp_rem & 11'b000_0000_1111;
11'b000_0000_01?? : rem = tmp_rem & 11'b000_0000_0111;
11'b000_0000_001? : rem = tmp_rem & 11'b000_0000_0011;
11'b000_0000_0001 : rem = tmp_rem & 11'b000_0000_0001;
11'b000_0000_0000 : rem = tmp_rem & 11'b000_0000_0000;
endcase
end
else
rem = tmp_rem;
end
endfunction
// detect zero
assign is_zero = ~|din;
// assign dout
always @(posedge clk)
if (ena)
amp <= #1 rem(din);
// generate sample counter
always @(posedge clk)
if (ena)
if (go)
sample_cnt <= #1 1; // count AC-terms, 'go=1' is sample-zero
else
sample_cnt <= #1 sample_cnt +1;
// generate zero counter
always @(posedge clk)
if (ena)
if (is_zero)
zero_cnt <= #1 zero_cnt +1;
else
zero_cnt <= #1 0;
// statemachine, create intermediate results
always @(posedge clk or negedge rst)
if(!rst)
begin
state <= #1 dc;
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
else if (ena)
case (state) // synopsys full_case parallel_case
dc:
begin
rlen <= #1 0;
size <= #1 cat(din);
if(go)
begin
state <= #1 ac;
den <= #1 1'b1;
dcterm <= #1 1'b1;
end
else
begin
state <= #1 dc;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
end
ac:
if(&sample_cnt) // finished current block
begin
state <= #1 dc;
if (is_zero) // last sample zero? send EOB
begin
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
else
begin
rlen <= #1 zero_cnt;
size <= #1 cat(din);
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
end
else
begin
state <= #1 ac;
rlen <= #1 zero_cnt;
dcterm <= #1 1'b0;
if (is_zero)
begin
size <= #1 0;
den <= #1 &zero_cnt;
end
else
begin
size <= #1 cat(din);
den <= #1 1'b1;
end
end
endcase
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:28:04 05/12/2015
// Design Name:
// Module Name: sbox_perm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sbox_perm(
in,
out
);
input [32:1] in;
output reg [32:1] out;
always @ (in)
begin
out[1]<=in[16];
out[2]<=in[7];
out[3]<=in[20];
out[4]<=in[21];
out[5]<=in[29];
out[6]<=in[12];
out[7]<=in[28];
out[8]<=in[17];
out[9]<=in[1];
out[10]<=in[15];
out[11]<=in[23];
out[12]<=in[26];
out[13]<=in[5];
out[14]<=in[18];
out[15]<=in[31];
out[16]<=in[10];
out[17]<=in[2];
out[18]<=in[8];
out[19]<=in[24];
out[20]<=in[14];
out[21]<=in[32];
out[22]<=in[27];
out[23]<=in[3];
out[24]<=in[9];
out[25]<=in[19];
out[26]<=in[13];
out[27]<=in[30];
out[28]<=in[6];
out[29]<=in[22];
out[30]<=in[11];
out[31]<=in[4];
out[32]<=in[25];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long NMAX = 300000 + 5; const long long inf = 922337203685477580LL; vector<vector<pair<long long, long long> > > g(NMAX); vector<vector<int> > id(NMAX); long long dis[NMAX]; long long last[NMAX]; long long a[NMAX]; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = 0; i < m; i++) { int a, b, c; cin >> a >> b >> c; g[a].push_back({b, c}); g[b].push_back({a, c}); id[a].push_back(i); id[b].push_back(i); } int s; cin >> s; for (int i = 1; i <= n; i++) dis[i] = inf; dis[s] = 0; for (int i = 1; i <= n; i++) last[i] = inf; last[s] = 0; set<pair<int, int> > q; q.insert({0, s}); while (!q.empty()) { int w = q.begin()->second; q.erase(q.begin()); for (int i = 0; i < g[w].size(); i++) { int to = g[w][i].first; int len = g[w][i].second; if (dis[w] + len < dis[to] || (dis[w] + len <= dis[to] && len < last[to])) { q.erase(make_pair(dis[to], to)); dis[to] = dis[w] + len; last[to] = len; a[to] = id[w][i] + 1; q.insert(make_pair(dis[to], to)); } } } for (int i = 1; i <= n; i++) ans += last[i]; cout << ans << endl; for (int i = 1; i <= n; i++) { if (i != s) { cout << a[i] << ; } } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 5, mod = 1e9 + 7; int koszt[31], tmp[31]; int main() { int a, b, c, d, e, f, g, z, k, n, m, q; scanf( %d , &n); for (a = 1; a <= 30; a++) koszt[a] = 1000000000; while (n--) { scanf( %d , &a); if (a == 1000) { for (b = 0; b <= 30; b++) tmp[b] = 1000000000; for (b = 1; b <= 30; b++) tmp[b] = koszt[b - 1] + 1000; for (b = 0; b <= 30; b++) for (c = b + 1; c <= 30 && c - b <= 10; c++) tmp[b] = min(tmp[b], koszt[c] + 1000 - (c - b) * 100); } else { for (b = 0; b <= 30; b++) tmp[b] = 1000000000; for (b = 2; b <= 30; b++) tmp[b] = koszt[b - 2] + 2000; for (b = 0; b <= 30; b++) for (c = b + 1; c <= 30 && c - b <= 20; c++) tmp[b] = min(tmp[b], koszt[c] + 2000 - (c - b) * 100); } for (b = 0; b <= 30; b++) koszt[b] = tmp[b]; } b = koszt[0]; for (a = 1; a <= 30; a++) b = min(b, koszt[a]); printf( %d , b); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int n, m; int long long dp[maxn]; vector<pair<int long long, int long long>> veci[maxn]; set<pair<int long long, int long long>> st; bool mark[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; fill_n(dp, maxn, 1e18); while (m--) { int long long a, b, c; cin >> a >> b >> c; veci[a].push_back({b, c}); veci[b].push_back({a, c}); } for (int i = 1; i <= n; i++) { int long long a; cin >> a; st.insert({a, i}); } while (st.size() > 0) { auto x = *st.begin(); st.erase(x); if (mark[x.second]) continue; dp[x.second] = x.first; mark[x.second] = 1; for (auto y : veci[x.second]) st.insert({dp[x.second] + (2 * y.second), y.first}); } for (int i = 1; i <= n; i++) cout << dp[i] << ; } |
// Test system function calls in constant functions
module constfunc6();
function [7:0] clog2(input [7:0] a);
clog2 = $clog2(a);
endfunction
function real log10(input [7:0] a);
log10 = $log10(a);
endfunction
function real sqrt(input real a);
sqrt = $sqrt(a);
endfunction
function real pow_i(input [7:0] a, input [7:0] b);
pow_i = $pow(a, b);
endfunction
function real pow_r(input real a, input real b);
pow_r = $pow(a, b);
endfunction
function signed [7:0] abs_i(input signed [7:0] a);
abs_i = $abs(a);
endfunction
function real abs_r(input real a);
abs_r = $abs(a);
endfunction
function [7:0] min_i(input [7:0] a, input [7:0] b);
min_i = $min(a, b);
endfunction
function [7:0] max_i(input [7:0] a, input [7:0] b);
max_i = $max(a, b);
endfunction
function real min_r(input real a, input real b);
min_r = $min(a, b);
endfunction
function real max_r(input real a, input real b);
max_r = $max(a, b);
endfunction
localparam [7:0] clog2Result = clog2(25);
localparam real log10Result = log10(100);
localparam real sqrtResult = sqrt(25.0);
localparam [7:0] powIResult = pow_i(4, 3);
localparam [7:0] absIResult = abs_i(-25);
localparam [7:0] minIResult = min_i(25, 30);
localparam [7:0] maxIResult = max_i(25, 30);
localparam real powRResult = pow_r(4.0, 3.0);
localparam real absRResult = abs_r(-25.0);
localparam real minRResult = min_r(25.0, 30.0);
localparam real maxRResult = max_r(25.0, 30.0);
reg failed;
initial begin
failed = 0;
$display("%0d", clog2Result);
$display("%0g", log10Result);
$display("%0g", sqrtResult);
$display("%0d", powIResult);
$display("%0g", powRResult);
$display("%0d", absIResult);
$display("%0g", absRResult);
$display("%0d", minIResult);
$display("%0g", minRResult);
$display("%0d", maxIResult);
$display("%0g", maxRResult);
if (clog2Result !== 8'd5) failed = 1;
if (log10Result != 2.0) failed = 1;
if ( sqrtResult != 5.0) failed = 1;
if ( powIResult !== 8'd64) failed = 1;
if ( powRResult != 64.0) failed = 1;
if ( absIResult !== 8'd25) failed = 1;
if ( absRResult != 25.0) failed = 1;
if ( minIResult !== 8'd25) failed = 1;
if ( minRResult != 25.0) failed = 1;
if ( maxIResult !== 8'd30) failed = 1;
if ( maxRResult != 30.0) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int M = 20; struct edge1 { int v, w; }; struct edge2 { int u, v, w; } e[N]; struct qry { int u, w, id; } q[N]; vector<edge1> G[N]; int n, m, c, a[N], dep[N], ans1[N], ans2[N], f[N][M], g[N][M]; void add(int u, int v, int w) { G[u].push_back((edge1){v, w}), G[v].push_back((edge1){u, w}); } void dfs(int u, int fa) { f[u][0] = fa, dep[u] = dep[fa] + 1; for (auto e : G[u]) if (e.v != fa) g[e.v][0] = e.w, dfs(e.v, u); } int dist(int x, int y) { int ans = 0; if (dep[x] < dep[y]) swap(x, y); for (int i = 18; i >= 0; --i) if (dep[f[x][i]] >= dep[y]) ans = max(ans, g[x][i]), x = f[x][i]; if (x == y) return ans; for (int i = 18; i >= 0; --i) if (f[x][i] != f[y][i]) ans = max(ans, max(g[x][i], g[y][i])), x = f[x][i], y = f[y][i]; return max(ans, max(g[x][0], g[y][0])); } namespace dsu { int fa[N], sz[N], pl[N], mxw[N], val[N]; void reset() { for (int i = 1; i <= n; ++i) fa[i] = pl[i] = i, val[i] = a[i], mxw[i] = 0, sz[i] = 1; } int find(int x) { return fa[x] == x ? fa[x] : fa[x] = find(fa[x]); } void Merge(int a, int b) { int x = find(a), y = find(b); if (sz[x] > sz[y]) swap(x, y); if (val[x] > val[y]) val[y] = val[x], mxw[y] = mxw[x], pl[y] = pl[x]; else if (val[x] == val[y]) mxw[y] = max(max(mxw[x], mxw[y]), dist(pl[x], pl[y])); fa[x] = y, sz[y] += sz[x]; } } // namespace dsu bool cmp1(edge2 a, edge2 b) { return a.w > b.w; } bool cmp2(qry a, qry b) { return a.w > b.w; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n - 1; ++i) { scanf( %d%d%d%d , &e[i].u, &e[i].v, &e[i].w, &c); add(e[i].u, e[i].v, c); } dfs(1, 0); for (int j = 1; j <= 18; ++j) for (int i = 1; i <= n; ++i) f[i][j] = f[f[i][j - 1]][j - 1], g[i][j] = max(g[i][j - 1], g[f[i][j - 1]][j - 1]); for (int i = 1; i <= m; ++i) scanf( %d%d , &q[i].w, &q[i].u), q[i].id = i; sort(e + 1, e + n, cmp1); sort(q + 1, q + m + 1, cmp2); dsu ::reset(); for (int i = 1, j = 1; i <= m; ++i) { for (; j <= n - 1 && e[j].w >= q[i].w; ++j) dsu ::Merge(e[j].u, e[j].v); int res = dsu ::mxw[dsu ::find(q[i].u)]; res = max(res, dist(q[i].u, dsu ::pl[dsu ::find(q[i].u)])); ans1[q[i].id] = dsu ::val[dsu ::find(q[i].u)], ans2[q[i].id] = res; } for (int i = 1; i <= m; ++i) printf( %d %d n , ans1[i], ans2[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_SYMBOL_V
`define SKY130_FD_SC_MS__A2111O_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { double n, m; while (cin >> m >> n) { double res = 0; for (double i = 1; i <= m; i++) { res += i * (pow(i / m, n) - pow((i - 1) / m, n)); } cout << res << endl; } return 0; } |
// hps_design_SMP_CORE_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_SMP_CORE_hps_io (
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [7:0] mem_dq, // .mem_dq
inout wire mem_dqs, // .mem_dqs
inout wire mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
hps_design_SMP_CORE_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
/*----------------------------------------------------------------------
*
* module description here
*
*---------------------------------------------------------------------*/
module foo
(/*AUTOARG*/
// Outputs
result_0, result_1,
// Inputs
clk, reset, enable_a
);
//----------------------------------------
input clk;
input reset;
input enable_a;
output result_0;
output result_1;
//----------------------------------------
/*----------------------------------------------------------------*/
/*-AUTOUNUSED-*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*-AUTOREGINPUT-*/
/*AUTOREG*/
/*AUTOWIRE*/
/*------------------------------------------------------------------
*
* local definitions and connections.
*
* */
wire enable_0, enable_1;
assign enable_0 = 1'd1;
assign enable_1 = enable_a;
/*------------------------------------------------------------------
*
*
*
* */
/* bar AUTO_TEMPLATE (
.enable (enable_@),
.result (result_@),
) */
bar bar0
(/*AUTOINST*/
// Outputs
.result (result_0), // Templated
// Inputs
.clk (clk),
.enable (enable_0), // Templated
.reset (reset));
bar bar1
(/*AUTOINST*/
// Outputs
.result (result_1), // Templated
// Inputs
.clk (clk),
.enable (enable_1), // Templated
.reset (reset));
/*----------------------------------------------------------------*/
endmodule // foo
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
/*----------------------------------------------------------------------
*
* module description here
*
*---------------------------------------------------------------------*/
module bar
(/*AUTOARG*/
// Outputs
result,
// Inputs
clk, enable, reset
);
//----------------------------------------
input clk;
input enable;
input reset;
output result;
//----------------------------------------
/*----------------------------------------------------------------*/
/*-AUTOUNUSED-*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*-AUTOREGINPUT-*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg result;
// End of automatics
/*AUTOWIRE*/
/*------------------------------------------------------------------
*
* local definitions and connections.
*
* */
/*------------------------------------------------------------------
*
*
*
* */
always @ (posedge clk) begin
if (reset) begin
result <= 1'd0;
end else begin
result <= enable;
end
end
/*----------------------------------------------------------------*/
endmodule // bar
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } struct KMP { int n, at; string s; vector<int> nxt; vector<int> nxtdiff; void init(int _n) { n = _n, at = 0, s = string(n, ? ), nxt = nxtdiff = vector<int>(n + 1, 0); } void add(char c) { s[at++] = c; int x = nxt[at - 1]; while (x != 0 && s[x] != c) x = nxt[x]; if (at >= 2 && s[x] == c) ++x; nxt[at] = x; nxtdiff[at - 1] = s[nxt[at - 1]] != c ? nxt[at - 1] : nxtdiff[nxt[at - 1]]; } }; struct RMQ { int n; vector<int> val; void init(int _n) { n = _n; val = vector<int>(4 * n, 0); } void _set(int x, int l, int r, int IDX, int VAL) { if (l == r) { val[x] = VAL; } else { int m = l + (r - l) / 2; if (IDX <= m) _set(2 * x + 1, l, m, IDX, VAL); else _set(2 * x + 2, m + 1, r, IDX, VAL); val[x] = min(val[2 * x + 1], val[2 * x + 2]); } } void set(int idx, int v) { _set(0, 0, n - 1, idx, v); } int _get(int x, int l, int r, int L, int R) { if (L <= l && r <= R) { return val[x]; } else { int m = l + (r - l) / 2, ret = INT_MAX; if (L <= m) ret = min(ret, _get(2 * x + 1, l, m, L, R)); if (m + 1 <= R) ret = min(ret, _get(2 * x + 2, m + 1, r, L, R)); return ret; } } int get(int l, int r) { return _get(0, 0, n - 1, l, r); } }; const int BASE = 1000000000; const int BASEDIGITS = 9; struct BigInt { vector<int> val; BigInt() {} }; void print(const BigInt &a) { if (((int)(a.val).size()) == 0) { printf( 0 ); return; } for (int i = ((int)(a.val).size()) - 1; i >= 0; --i) { if (i == ((int)(a.val).size()) - 1) printf( %d , a.val[i]); else printf( %0*d , BASEDIGITS, a.val[i]); } } BigInt operator+(const BigInt &a, unsigned long long b) { BigInt c = a; for (int i = 0; b > 0; ++i) { if (i >= ((int)(c.val).size())) c.val.push_back(0); b += c.val[i]; c.val[i] = b % BASE; b /= BASE; } return c; } BigInt operator+(const BigInt &a, const BigInt &b) { BigInt c; int carry = 0; for (int i = 0; i < ((int)(a.val).size()) || i < ((int)(b.val).size()) || carry > 0; ++i) { if (i < ((int)(a.val).size())) carry += a.val[i]; if (i < ((int)(b.val).size())) carry += b.val[i]; c.val.push_back(carry % BASE); carry /= BASE; } return c; } BigInt operator-(const BigInt &a, unsigned long long b) { BigInt c = a; for (int i = 0; b > 0; ++i) { assert(i < ((int)(c.val).size())); int cur = b % BASE; b /= BASE; if (cur <= c.val[i]) c.val[i] -= cur; else c.val[i] += BASE - cur, ++b; } while (((int)(c.val).size()) > 0 && c.val.back() == 0) c.val.pop_back(); return c; } int operator%(const BigInt &a, int b) { int ret = 0; for (int i = ((int)(a.val).size()) - 1; i >= 0; --i) ret = ((unsigned long long)ret * BASE + a.val[i]) % b; return ret; } int operator&(const BigInt &a, int b) { return (a % (1 << 30)) & b; } struct RelaxableSet { BigInt sum; map<int, int> cnt; void init() { sum = BigInt(); cnt = map<int, int>(); } void relax(int lim) { int rem = 0; while (((int)(cnt).size()) > 0) { auto it = prev(cnt.end()); if (it->first <= lim) break; sum = sum - (unsigned long long)it->first * it->second, rem += it->second, cnt.erase(it); } if (rem > 0) cnt[lim] += rem, sum = sum + (unsigned long long)lim * rem; } void remove(int val) { auto it = cnt.find(val); assert(it != cnt.end()); if (it->second == 1) cnt.erase(it); else --it->second; sum = sum - val; } void add(int val) { ++cnt[val]; sum = sum + val; } void print() { for (auto it = cnt.begin(); it != cnt.end(); ++it) printf( %d=%d , it->first, it->second); puts( ); } }; const int MAXN = 600000; const int MASK = (1 << 30) - 1; int n; char c[MAXN]; int w[MAXN]; BigInt ans[MAXN]; KMP kmp; RMQ rmq; RelaxableSet have; void solve() { kmp.init(n); rmq.init(n); have.init(); BigInt prv; for (int i = (0); i < (n); ++i) { char cc = (prv + (unsigned long long)(c[i] - a )) % 26 + a ; int ww = w[i] ^ (prv & MASK); kmp.add(cc); int len = i; while (len >= 1) { if (kmp.s[len] != cc) { int val = rmq.get(i - len, i - 1); have.remove(val); len = kmp.nxt[len]; } else { len = kmp.nxtdiff[len]; } } rmq.set(i, ww); have.relax(ww); if (cc == kmp.s[0]) have.add(ww); ans[i] = prv + have.sum; prv = ans[i]; } } void run() { scanf( %d , &n); for (int i = (0); i < (n); ++i) scanf( %c%d , &c[i], &w[i]); solve(); for (int i = (0); i < (n); ++i) print(ans[i]), puts( ); } int main() { run(); return 0; } |
#include <bits/stdc++.h> using namespace std; inline void read(register int *n) { register char c; *n = 0; do { c = getchar(); } while (c < 0 || c > 9 ); do { *n = c - 0 + *n * 10; c = getchar(); } while (c >= 0 && c <= 9 ); } long long C[2048][2048], fac[1000001], dfac[1000001], D[2048][2048]; long long pmod(long long x, long long y) { if (y == 0) return 1; if (y % 2) return pmod(x, y - 1) * x % 1000000007; long long r = pmod(x, y / 2); return r * r % 1000000007; } long long calc(long long n, long long k, long long c = 0) { long long res = 0; for (register int i = (0); i < (int)(k + 1); ++i) { long long tmp = C[k][i] * pmod(i + c, n); tmp %= 1000000007; if (i % 2) res -= tmp; else res += tmp; res %= 1000000007; } return res; } inline long long binom(long long n, long long r) { if (r < 0 || r > n) return 0; long long res = 1; res = res * fac[n] % 1000000007; res = res * dfac[r] % 1000000007; res = res * dfac[n - r] % 1000000007; return res; } int main() { for (register int i = (0); i < (int)(1000001); ++i) fac[i] = (i ? fac[i - 1] * i : 1) % 1000000007, dfac[i] = pmod(fac[i], 1000000007 - 2); for (register int i = (0); i < (int)(2048); ++i) for (register int j = (0); j < (int)(i + 1); ++j) C[i][j] = (j == 0 || j == i) ? 1 : (C[i - 1][j - 1] + C[i - 1][j]); for (register int i = (0); i < (int)(2048); ++i) for (register int j = (0); j < (int)(2048); ++j) if (i == 0) D[i][j] = j == 0; else if (j <= 1) D[i][j] = j; else D[i][j] = (j * D[i - 1][j] + D[i - 1][j - 1]) % 1000000007; int n, m, k; cin >> n >> m >> k; if (m == 1) { cout << pmod(k, n) << endl; return 0; } long long res = 0; for (register int x = (1); x < (int)(min(k, n) + 1); ++x) for (int y = 0; y <= x; y++) if (x * 2 - y <= k) { long long tmp = binom(k, x * 2 - y); tmp = tmp * binom(x * 2 - y, x - y) % 1000000007; tmp = tmp * binom(x, x - y) % 1000000007; tmp = tmp * D[n][x] % 1000000007; tmp = tmp * D[n][x] % 1000000007; tmp = tmp * fac[x] % 1000000007; tmp = tmp * fac[x] % 1000000007; tmp = tmp * pmod(y, n * (m - 2)); res = (res + tmp) % 1000000007; } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<set<int> > g; vector<int> ans; vector<bool> used; void dfs(int v, int p) { used[v] = true; ans.push_back(v); for (set<int>::iterator i = g[v].begin(); i != g[v].end(); i++) { if (!used[*i] && g[*i].count(p)) dfs(*i, v); } } int main() { int n; scanf( %d , &n); g.resize(n); used.resize(n, false); for (int i = 0; i < 2 * n; i++) { int a, b; scanf( %d %d , &a, &b); a--; b--; g[a].insert(b); g[b].insert(a); if (g[a].size() > 4 || g[b].size() > 4) { puts( -1 ); return 0; } } ans.push_back(0); used[0] = true; int st, p = -1; for (set<int>::iterator i = g[0].begin(); i != g[0].end(); i++) { int temp = 0, mp; for (set<int>::iterator j = g[0].begin(); j != g[0].end(); j++) { if (g[*i].count(*j)) { temp++; mp = *j; } } if (temp == 1 && n > 6 || temp && n < 7) { st = *i; p = mp; break; } } if (p == -1) { puts( -1 ); return 0; } ans.push_back(p); used[p] = true; dfs(st, p); if (ans.size() != n) { puts( -1 ); return 0; } for (int i = 0; i < ans.size(); i++) { printf( %d , ans[i] + 1); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_transmitter.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Jacob Gorban, ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_transmitter.v,v $
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "timescale.v"
`include "uart_defines.v"
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset);
input clk;
input wb_rst_i;
input [7:0] lcr;
input tf_push;
input [7:0] wb_dat_i;
input enable;
input tx_reset;
output stx_pad_o;
output [2:0] state;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
reg [2:0] state;
reg [4:0] counter;
reg [2:0] bit_counter; // counts the bits to be sent
reg [6:0] shift_out; // output shift register
reg stx_o_tmp;
reg parity_xor; // parity of the word
reg tf_pop;
reg bit_out;
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
wire tf_push;
wire tf_underrun;
wire tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
assign tf_data_in = wb_dat_i;
uart_fifo fifo_tx( // error bit signal is not used in transmitter FIFO
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( tf_data_in ),
.data_out( tf_data_out ),
.push( tf_push ),
.pop( tf_pop ),
.underrun( tf_underrun ),
.overrun( tf_overrun ),
.count( tf_count ),
.error_bit(), // Ta ni priklopljen. Prej je manjkal, dodal Igor
.fifo_reset( tx_reset ),
.reset_status(1'b0)
);
// TRANSMITTER FINAL STATE MACHINE
parameter s_idle = 3'd0;
parameter s_send_start = 3'd1;
parameter s_send_byte = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop = 3'd4;
parameter s_pop_byte = 3'd5;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
state <= #1 s_idle;
stx_o_tmp <= #1 1'b1;
counter <= #1 5'b0;
shift_out <= #1 7'b0;
bit_out <= #1 1'b0;
parity_xor <= #1 1'b0;
tf_pop <= #1 1'b0;
bit_counter <= #1 3'b0;
end
else
if (enable)
begin
case (state)
s_idle : if (~|tf_count) // if tf_count==0
begin
state <= #1 s_idle;
stx_o_tmp <= #1 1'b1;
end
else
begin
tf_pop <= #1 1'b0;
stx_o_tmp <= #1 1'b1;
state <= #1 s_pop_byte;
end
s_pop_byte : begin
tf_pop <= #1 1'b1;
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : begin
bit_counter <= #1 3'b100;
parity_xor <= #1 ^tf_data_out[4:0];
end
2'b01 : begin
bit_counter <= #1 3'b101;
parity_xor <= #1 ^tf_data_out[5:0];
end
2'b10 : begin
bit_counter <= #1 3'b110;
parity_xor <= #1 ^tf_data_out[6:0];
end
2'b11 : begin
bit_counter <= #1 3'b111;
parity_xor <= #1 ^tf_data_out[7:0];
end
endcase
{shift_out[6:0], bit_out} <= #1 tf_data_out;
state <= #1 s_send_start;
end
s_send_start : begin
tf_pop <= #1 1'b0;
if (~|counter)
counter <= #1 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= #1 0;
state <= #1 s_send_byte;
end
else
counter <= #1 counter - 5'b00001;
stx_o_tmp <= #1 1'b0;
end
s_send_byte : begin
if (~|counter)
counter <= #1 5'b01111;
else
if (counter == 5'b00001)
begin
if (bit_counter > 3'b0)
begin
bit_counter <= #1 bit_counter - 1;
{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};
state <= #1 s_send_byte;
end
else // end of byte
if (~lcr[`UART_LC_PE])
begin
state <= #1 s_send_stop;
end
else
begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: bit_out <= #1 parity_xor;
2'b01: bit_out <= #1 1'b1;
2'b10: bit_out <= #1 ~parity_xor;
2'b11: bit_out <= #1 1'b0;
endcase
state <= #1 s_send_parity;
end
counter <= #1 0;
end
else
counter <= #1 counter - 5'b00001;
stx_o_tmp <= #1 bit_out; // set output pin
end
s_send_parity : begin
if (~|counter)
counter <= #1 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= #1 4'b0;
state <= #1 s_send_stop;
end
else
counter <= #1 counter - 5'b00001;
stx_o_tmp <= #1 bit_out;
end
s_send_stop : begin
if (~|counter)
begin
casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor
3'b100: counter <= #1 5'b10101; // 1.5 stop bit
3'b1xx: counter <= #1 5'b11101; // 2 stop bits
endcase
end
else
if (counter == 5'b00001)
begin
counter <= #1 0;
state <= #1 s_idle;
end
else
counter <= #1 counter - 5'b00001;
stx_o_tmp <= #1 1'b1;
end
default : // should never get here
state <= #1 s_idle;
endcase
end // end if enable
end // transmitter logic
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2 * 1000 + 5; const long long INF = 1000ll * 1000 * 1000 * 1000 * 1000 * 1000; int n, k, dp[maxn], a[maxn]; bool check(long long x) { for (int i = 1; i <= n; i++) { dp[i] = i - 1; for (int j = 1; j < i; j++) { if (abs(a[i] - a[j]) <= (i - j) * x) dp[i] = min(dp[i], dp[j] + i - j - 1); if (dp[i] + n - i <= k) return true; } } return false; } int main() { cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; if (n == 1) { cout << 0 << endl; return 0; } long long l = -1, r = INF + 1, mid; while (r - l > 1) { mid = (l + r) >> 1; if (check(mid)) r = mid; else l = mid; } cout << r << endl; return 0; } |
#include <bits/stdc++.h> using LL = int64_t; int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); int n; std::cin >> n; std::vector<int> a(n); for (int &i : a) std::cin >> i; std::sort(a.begin(), a.end()); int maxa = a.back(); std::vector<std::vector<int>> mx(maxa + 1); for (auto &i : mx) i.assign(2, -1); std::vector<int> cnt(maxa + 1); for (int i : a) ++cnt[i]; for (int i = 1; i <= maxa; ++i) { if (cnt[i] >= 2) mx[i][0] = mx[i][1] = i; else if (cnt[i] == 1) { mx[i][0] = i; mx[i][1] = mx[i - 1][0]; } else mx[i] = mx[i - 1]; cnt[i] += cnt[i - 1]; } LL ans = 0; for (int y = 2; y <= maxa; ++y) { int more[] = {-1, -1}; LL cnty = 0; for (int k = 1; k <= maxa / y; ++k) cnty += (LL)k * (cnt[std::min((k + 1) * y - 1, maxa)] - cnt[k * y - 1]); for (int k = maxa / y; k >= 0; --k) { more[1] = std::max(more[1], mx[std::min((k + 1) * y - 1, maxa)][0] - k * y); if (more[0] < more[1]) std::swap(more[0], more[1]); more[1] = std::max(more[1], mx[std::min((k + 1) * y - 1, maxa)][1] - k * y); int x = std::min((LL)(k * y + more[0]) / 2, cnty - k); if (x >= 2) ans = std::max(ans, LL(x) * y); if (more[1] != -1) { x = std::min((LL)k * y + more[1], cnty - 2 * k); if (x >= 2) ans = std::max(ans, LL(x) * y); } if (n - cnt[std::max(0, k * y + more[0] - 1)] >= 2) { x = std::min((LL)k * y + more[0], cnty - 2 * k - 1); if (x >= 2) ans = std::max(ans, LL(x) * y); } } } std::cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 101; long long n; pair<long long, long long> a[N]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long i = 0; i < n; ++i) cin >> a[i].first >> a[i].second; long long p; cin >> p; for (long long i = n - 1; i >= 0; --i) { if (a[i].first <= p) { cout << n - i << n ; exit(0); } } } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:256000000 ) using namespace std; const int INF = 1000000000; const long long LINF = 4000000000000000000LL; const double eps = 1e-9; void prepare() {} struct Chat { string name, text; unsigned int hname; set<unsigned int> words; vector<int> possibles; }; int n, m; vector<Chat> chats; vector<string> names; vector<int> res; vector<unsigned int> hnames; int p[100500]; unsigned int getHash(string s) { unsigned int h = 0; for (int i = (0); i < (((int)(s).size())); i++) h = h * 3137 + s[i]; return h; } Chat readChat() { Chat chat; string s; getline(cin, s); int ix = s.find( : ); chat.name = s.substr(0, ix); chat.hname = getHash(chat.name); chat.text = s.substr(ix + 1); s = chat.text; for (int i = (0); i < (((int)(s).size())); i++) { if (!isalnum(s[i])) s[i] = ; } stringstream ss(s); while (ss >> s) { chat.words.insert(getHash(s)); } return chat; } void read() { names.clear(); hnames.clear(); chats.clear(); string s; scanf( %d , &n); getline(cin, s); getline(cin, s); stringstream ss(s); while (ss >> s) { names.push_back(s); hnames.push_back(getHash(s)); } scanf( %d , &m); getline(cin, s); for (int i = (0); i < ((m)); i++) { chats.push_back(readChat()); } } bool rec(int cc) { if (cc >= m) return true; int id = p[cc]; for (int i = (0); i < (((int)(chats[id].possibles).size())); i++) { int prid = chats[id].possibles[i]; unsigned int pr = hnames[prid]; if ((id == 0 || chats[id - 1].hname != pr) && (id + 1 >= m || chats[id + 1].hname != pr)) { unsigned int ph = chats[id].hname; chats[id].hname = pr; res[id] = prid; if (rec(cc + 1)) return true; chats[id].hname = ph; } } return false; } bool cmp(const int &a, const int &b) { return chats[a].possibles.size() < chats[b].possibles.size(); } bool solve() { res.clear(); res.resize(m); for (int i = (0); i < ((m)); i++) { if (chats[i].name != ? ) { int id = find((names).begin(), (names).end(), chats[i].name) - names.begin(); chats[i].possibles.push_back(id); continue; } for (int j = (0); j < ((n)); j++) { if (!chats[i].words.count(hnames[j])) chats[i].possibles.push_back(j); } } for (int i = (0); i < ((m)); i++) p[i] = i; sort(p, p + m, cmp); if (rec(0)) { for (int i = (0); i < ((m)); i++) { printf( %s:%s n , names[res[i]].c_str(), chats[i].text.c_str()); } } else { printf( Impossible n ); } return false; } int main() { prepare(); int t; scanf( %d , &t); for (int i = (0); i < ((t)); i++) { read(); while (solve()) ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[300001]; int f[300001]; vector<int> g[33]; map<vector<int>, int> mp; vector<pair<vector<int>, int> > v; vector<int> cur; int br = 0; int n; void F(int pos, int mask) { if (pos == br) { v.push_back({cur, mask}); return; } F(pos + 1, mask); if (g[pos].empty() || g[pos].size() == n) return; for (auto to : g[pos]) cur[to]++; F(pos + 1, (mask ^ (1 << pos))); for (auto to : g[pos]) cur[to]--; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) f[i] = __builtin_popcount(a[i]); set<int> st; for (int i = 1; i <= n; i++) st.insert(f[i] % 2); if (st.size() == 2) { cout << -1; return 0; } for (int i = 1; i <= n; i++) f[i] /= 2; for (int i = 1; i <= n; i++) { for (int j = 0; j < 30; j++) { if (a[i] & (1 << j)) continue; g[j].push_back(i - 1); } } cur.resize(n); for (int i = 0; i < n; i++) cur[i] = 0; br = 15; F(0, 0); for (auto cur : v) { mp[cur.first] = cur.second; } for (int i = 0; i < n; i++) cur[i] = 0; br = 30; F(15, 0); for (auto x : v) { vector<int> cur = x.first; int mask = x.second; for (int t = 0; t <= 60; t++) { vector<int> to(n, t); for (int i = 0; i < n; i++) to[i] -= f[i + 1] + cur[i]; if (mp.find(to) != mp.end()) { cout << (mask ^ mp[to]); return 0; } } } cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long n1, long long n2) { if (!n1) return n2; if (!n2) return n1; if (n1 % n2 == 0) return n2; return gcd(n2, n1 % n2); } long long powmod(long long base, long long exponent) { base %= 1000000007; long long ans = 1; while (exponent) { if (exponent & 1) ans = (ans * base) % 1000000007; base = (base * base) % 1000000007; exponent /= 2; } ans %= 1000000007; return ans; } int arr[1000100 + 1]; int cnt[1000100 + 1]; int pw[1000100 + 1]; int dp[1000100 + 1]; int main() { int n, i, j, k; pw[0] = 1; for (i = 1; i <= 1000100; i++) { pw[i] = (2 * pw[i - 1]) % 1000000007; } scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &arr[i]); cnt[arr[i]]++; } for (i = 1; i <= 1000100; i++) for (j = i; j <= 1000100; j += i) dp[i] += cnt[j]; for (i = 1; i <= 1000100; i++) if (dp[i]) { dp[i] = (1LL * dp[i] * pw[dp[i] - 1]) % 1000000007; } long long answer = 0; for (i = 1000100; i >= 2; i--) { for (j = 2 * i; j <= 1000100; j += i) { dp[i] -= dp[j]; if (dp[i] < 0) dp[i] += 1000000007; } answer = (answer + 1LL * i * dp[i]) % 1000000007; } printf( %lld n , answer); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, x[1500][1500], y[1500][1500], vis[1510][1500]; char ans[1500][1500]; struct node { int x, y; }; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; vector<node> a; int main() { cin >> n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { scanf( %d%d , &x[i][j], &y[i][j]); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (x[i][j] != -1 && !vis[x[i][j]][y[i][j]]) { if (x[x[i][j]][y[i][j]] == -1 || x[x[i][j]][y[i][j]] != x[i][j] || y[x[i][j]][y[i][j]] != y[i][j]) { printf( INVALID n ); return 0; } a.push_back(node{x[i][j], y[i][j]}); ans[x[i][j]][y[i][j]] = X ; vis[x[i][j]][y[i][j]] = 1; } } } queue<node> q; for (int j = 0; j < a.size(); j++) { q.push(a[j]); while (!q.empty()) { node now = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int xx = now.x + dx[i]; int yy = now.y + dy[i]; if (xx <= 0 || yy <= 0 || xx > n || yy > n || x[xx][yy] != a[j].x || y[xx][yy] != a[j].y) continue; if (!vis[xx][yy]) { vis[xx][yy] = 1; q.push(node{xx, yy}); if (i == 0) ans[xx][yy] = L ; if (i == 1) ans[xx][yy] = R ; if (i == 2) ans[xx][yy] = U ; if (i == 3) ans[xx][yy] = D ; } } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (x[i][j] != -1 && !vis[i][j]) { printf( INVALID n ); return 0; } if (x[i][j] == -1 && !vis[i][j]) { q.push(node{i, j}); vis[i][j] = 1; int flag = 0; while (!q.empty()) { node now = q.front(); q.pop(); for (int k = 0; k < 4; k++) { int xx = now.x + dx[k]; int yy = now.y + dy[k]; if (xx <= 0 || yy <= 0 || xx > n || yy > n || x[xx][yy] != -1) continue; if (x[xx][yy] == -1 && vis[xx][yy]) { if (!flag) { if (k == 0) ans[i][j] = R ; if (k == 1) ans[i][j] = L ; if (k == 2) ans[i][j] = D ; if (k == 3) ans[i][j] = U ; flag = 1; } } if (!vis[xx][yy]) { vis[xx][yy] = 1; q.push(node{xx, yy}); if (k == 0) ans[xx][yy] = L ; if (k == 1) ans[xx][yy] = R ; if (k == 2) ans[xx][yy] = U ; if (k == 3) ans[xx][yy] = D ; if (!flag) { if (k == 0) ans[i][j] = R ; if (k == 1) ans[i][j] = L ; if (k == 2) ans[i][j] = D ; if (k == 3) ans[i][j] = U ; flag = 1; } } } if (!flag) { printf( INVALID n ); return 0; } } } } } printf( VALID n ); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { printf( %c , ans[i][j]); } cout << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_SYMBOL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd1 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, t, twoc, onec, opt, old; int main() { cin >> n; cin >> t; if (t == 1) onec++; else twoc++; old = t; for (int i = 1; i < n; i++) { cin >> t; if (t == 1) { if (old == 2) onec = 1; else onec++; } else { if (old == 1) twoc = 1; else twoc++; } opt = max(opt, min(onec, twoc)); old = t; } cout << opt * 2; return 0; } |
#include <bits/stdc++.h> using namespace std; constexpr long long INF = 2e18; constexpr long long MOD = 1e9 + 7; constexpr long long MAXN = 2e5 + 3; struct Matrix { static constexpr long long MOD = 1e9 + 7; static constexpr long long MAXN = 200, MAXM = 200; array<array<long long, MAXM>, MAXN> mat = {}; long long n, m; Matrix(const long long n, const long long m) : n(n), m(m) {} static long long mod(long long n) { n %= MOD; if (n < 0) n += MOD; return n; } Matrix identity() { assert(n == m); Matrix mat_identity(n, m); for (long long i = 0; i < n; ++i) mat_identity.mat[i][i] = 1; return mat_identity; } Matrix operator*(const Matrix &other) const { assert(m == other.n); Matrix ans(n, other.m); for (long long i = 0; i < n; ++i) for (long long j = 0; j < m; ++j) for (long long k = 0; k < m; ++k) ans.mat[i][j] = mod(ans.mat[i][j] + mat[i][k] * other.mat[k][j]); return ans; } Matrix expo(long long p) { assert(p >= 0); Matrix ans = identity(), cur_power(n, m); cur_power.mat = mat; while (p) { if (p & 1) ans = ans * cur_power; cur_power = cur_power * cur_power; p >>= 1; } return ans; } }; void solve() { long long n; cin >> n; long long b, k, x; cin >> b >> k >> x; vector<long long> fq(10); for (long long i = 0; i < n; ++i) { long long x; cin >> x; ++fq[x]; } Matrix mat(x, x); for (long long j = 0; j < x; ++j) for (long long d = 0; d <= 9; ++d) mat.mat[(10 * j + d) % x][j] += fq[d]; mat = mat.expo(b); Matrix ini(x, 1); ini.mat[0][0] = 1; mat = mat * ini; cout << mat.mat[k].front() << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int md = 1e9 + 7; int __gcd(int a, int b) { if (b == 0) return a; return __gcd(b, a % b); } int poww(int a, int b) { int res = 1; while (b) { if (b & 1) { res *= a; res %= md; } a *= a; a %= md; b >>= 1; } return res; } void ainp(int arr[], int n) { for (int i = 1; i <= n; i++) cin >> arr[i]; } const int N = 1e5 + 5; void fun() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } int n; int a[N], cache[N][10]; int dp(int idx, int cur) { if (idx == n) return 1; int &ans = cache[idx][cur]; if (ans != -1) return ans; ans = 0; if (a[idx + 1] > a[idx]) { for (int i = cur + 1; i <= 5; i++) ans |= dp(idx + 1, i); } else if (a[idx + 1] == a[idx]) { for (int i = 1; i <= 5; i++) { if (i == cur) continue; ans |= dp(idx + 1, i); } } else { for (int i = 1; i < cur; i++) ans |= dp(idx + 1, i); } return ans; } void path(int idx, int cur) { cout << cur << ; if (idx == n) return; if (a[idx + 1] > a[idx]) { for (int i = cur + 1; i <= 5; i++) if (dp(idx + 1, i)) return path(idx + 1, i); } else if (a[idx + 1] == a[idx]) { for (int i = 1; i <= 5; i++) { if (i == cur) continue; if (dp(idx + 1, i)) return path(idx + 1, i); } } else { for (int i = 1; i < cur; i++) if (dp(idx + 1, i)) return path(idx + 1, i); } } signed main() { fun(); memset(cache, -1, sizeof(cache)); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= 5; i++) { if (dp(1, i)) { path(1, i); return 0; } } cout << -1 ; return 0; } |
#include <bits/stdc++.h> using namespace std; int cmp(string s1, string s2) { if (s1 == rock && s2 == scissors ) return 1; if (s1 == scissors && s2 == paper ) return 1; if (s1 == paper && s2 == rock ) return 1; return 0; } int main() { string s1, s2, s3; cin >> s1 >> s2 >> s3; if (cmp(s1, s2) && cmp(s1, s3)) { putchar( F ); return 0; } if (cmp(s2, s1) && cmp(s2, s3)) { putchar( M ); return 0; } if (cmp(s3, s1) && cmp(s3, s2)) { putchar( S ); return 0; } putchar( ? ); } |
#include <bits/stdc++.h> using namespace std; char comp[200005]; vector<pair<int, int> > edge[200005]; vector<int> father[200005]; vector<string> ans; int dis[200005], n, k; queue<pair<int, int> > q; void dfs(int u) { if (ans.size() >= k) return; if (u == n + 1) { ans.push_back(comp + 1); return; } for (int i = 0; i < father[u].size(); i++) { comp[father[u][i]] = 1 ; dfs(u + 1); comp[father[u][i]] = 0 ; } } int main() { char a[10]; int m; cin >> n >> m >> k; for (int i = 1; i <= m; i++) { int u, v; scanf( %d %d , &u, &v); edge[u].push_back(make_pair(v, i)); edge[v].push_back(make_pair(u, i)); } memset(dis, -1, sizeof(dis)); for (int i = 1; i <= m; i++) comp[i] = 0 ; q.push(make_pair(1, 0)); dis[1] = 0; while (!q.empty()) { pair<int, int> pa = q.front(); q.pop(); int u = pa.first, d = pa.second; for (int i = 0; i < edge[u].size(); i++) { int v = edge[u][i].first; if (dis[v] == -1) { dis[v] = d + 1; q.push(make_pair(v, d + 1)); } } } for (int i = 2; i <= n; i++) { for (int j = 0; j < edge[i].size(); j++) { if (dis[i] == dis[edge[i][j].first] + 1) father[i].push_back(edge[i][j].second); } } dfs(2); if (ans.size() >= k) { cout << k << endl; for (int i = 0; i < k; i++) cout << ans[i] << endl; } else { cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int i; char n[100010], m; stack<char> s; scanf( %s , n); for (i = 0; n[i] != 0; i++) { if (s.empty()) { s.push(n[i]); } else { m = s.top(); if (m == n[i]) s.pop(); else s.push(n[i]); } } if (s.empty()) printf( Yes n ); else printf( No n ); return 0; } |
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
/* verilator lint_off UNUSED */
module qm_icache(
input wire [31:0] address,
input wire reset,
input wire clk,
// to the consumer (CPU fetch stage)
output reg hit,
output reg stall,
output reg [31:0] data,
input wire enable,
// to the memory controller (no wishbone yet...)
// the cache is currently only backed in 1GBit RAM via this controller
// this RAM is mapped 0x80000000 - 0x90000000
output wire mem_cmd_clk, // we will keep this synchronous to the input clock
output reg mem_cmd_en,
output reg [2:0] mem_cmd_instr,
output reg [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_addr,
input wire mem_cmd_full,
input wire mem_cmd_empty,
output wire mem_rd_clk,
output reg mem_rd_en,
input wire [6:0] mem_rd_count,
input wire mem_rd_full,
input wire [31:0] mem_rd_data,
input wire mem_rd_empty
);
// 4k cache lines -> 16kword cache
reg [144:0] lines [4095:0];
/// internal signals
// the bit used to mark valid lines (flips when we flush the cache)
reg valid_bit;
wire [11:0] index;
wire index_valid;
wire [15:0] index_tag;
wire [15:0] address_tag;
wire [1:0] address_word;
assign index = address[15:4];
assign index_valid = lines[index][144];
assign index_tag = lines[index][143:128];
assign address_tag = address[31:16];
assign address_word = address[3:2];
assign mem_rd_clk = clk;
assign mem_cmd_clk = clk;
// reset condition
generate
genvar i;
for (i = 0; i < 4096; i = i + 1) begin: ruchanie
always @(posedge clk) begin
if (reset) begin
lines[0] <= {145'b0};
end
end
end
endgenerate
always @(posedge clk) begin
if (reset) begin
valid_bit <= 1;
memory_read_state <= 0;
mem_cmd_en <= 0;
mem_cmd_bl <= 0;
mem_cmd_instr <= 0;
mem_cmd_addr <= 0;
mem_rd_en <= 0;
end
end
// read condition
always @(*) begin
if (enable) begin
// is this in the RAM region?
if (32'h80000000 <= address && address < 32'h90000000) begin
// do we have a hit?
if (index_valid == valid_bit && index_tag == address_tag) begin
if (address_word == 2'b00)
data = lines[index][31:0];
else if (address_word == 2'b01)
data = lines[index][63:32];
else if (address_word == 2'b10)
data = lines[index][95:64];
else
data = lines[index][127:96];
hit = 1;
stall = 0;
end else begin
hit = 0;
stall = 1;
end
end else begin
hit = 1;
stall = 0;
data = 32'h00000000;
end
end else begin
hit = 0;
stall = 0;
end
end
// if we are stalling, it means that our consumer is waiting for us to
// read memory and provide it data
reg [2:0] memory_read_state;
always @(posedge clk) begin
if (stall && !reset && enable) begin
case (memory_read_state)
0: begin // assert command
mem_cmd_instr <= 1; // read
mem_cmd_bl <= 3; // four words
mem_cmd_addr <= {1'b0, address[28:0]};
mem_cmd_en <= 0;
memory_read_state <= 1;
end
1: begin // assert enable
mem_cmd_en <= 1;
memory_read_state <= 2;
mem_rd_en <= 1;
end
2: begin // wait for first word
mem_cmd_en <= 0;
if (!mem_rd_empty) begin
lines[index][31:0] <= mem_rd_data;
memory_read_state <= 3;
end
end
3: begin // wait for second word
if (!mem_rd_empty) begin
lines[index][63:32] <= mem_rd_data;
memory_read_state <= 4;
end
end
4: begin // wait for third word
if (!mem_rd_empty) begin
lines[index][95:64] <= mem_rd_data;
memory_read_state <= 5;
end
end
5: begin // wait for fourth word
if (!mem_rd_empty) begin
lines[index][127:96] <= mem_rd_data;
memory_read_state <= 0;
mem_rd_en <= 0;
// write tag
lines[index][143:128] <= address_tag;
// and valid bit - our cominatorial logic will now turn
// off stalling and indicate a hit to the consumer
lines[index][144] <= valid_bit;
end
end
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
// Created by Actel SmartDesign Tue Apr 29 08:58:52 2014
// Testbench Template
// This is a basic testbench that instantiates your design with basic
// clock and reset pins connected. If your design has special
// clock/reset or testbench driver requirements then you should
// copy this file and modify it.
//////////////////////////////////////////////////////////////////////
`timescale 1ns/100ps
module testbench;
parameter SYSCLK_PERIOD = 100; // 10MHz
reg SYSCLK;
reg NSYSRESET;
initial
begin
SYSCLK = 1'b0;
NSYSRESET = 1'b0;
end
//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
#(SYSCLK_PERIOD * 10 )
NSYSRESET = 1'b1;
end
//////////////////////////////////////////////////////////////////////
// 10MHz Clock Driver
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test: cc3000fpga_MSS
//////////////////////////////////////////////////////////////////////
cc3000fpga_MSS cc3000fpga_MSS_0 (
// Inputs
.MSSPREADY({1{1'b0}}),
.MSSPSLVERR({1{1'b0}}),
.MSSPRDATA({32{1'b0}}),
.UART_0_RXD({1{1'b0}}),
.UART_1_RXD({1{1'b0}}),
.SPI_1_DI({1{1'b0}}),
.GPIO_2_IN({1{1'b0}}),
.MSS_RESET_N(NSYSRESET),
// Outputs
.M2F_GPO_1( ),
.M2F_GPO_0( ),
.FAB_CLK( ),
.M2F_RESET_N( ),
.MSSPSEL( ),
.MSSPENABLE( ),
.MSSPWRITE( ),
.M2F_GPO_3( ),
.M2F_GPO_9( ),
.MSSPADDR( ),
.MSSPWDATA( ),
.UART_0_TXD( ),
.UART_1_TXD( ),
.SPI_1_DO( ),
.GPIO_4_OUT( ),
// Inouts
.SPI_1_CLK( ),
.SPI_1_SS( )
);
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : bus_slave_mux.v
//Project Name : azpr_soc
//Description : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_slave_mux.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : lichangbeiju
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : lichangbeiju
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.21 - lichangbeiju - Add io port.
//****************************************************************************************************
`include "../sys_include.h"
`include "bus.h"
module bus_slave_mux(
//slave 0
input wire s0_cs_n ,//01 chip select
input wire [`WordDataBus] s0_rd_data ,//32 write data
input wire s0_rdy_n ,//01
//slave 1
input wire s1_cs_n ,//01 chip select
input wire [`WordDataBus] s1_rd_data ,//32 write data
input wire s1_rdy_n ,//01
//slave 2
input wire s2_cs_n ,//01 chip select
input wire [`WordDataBus] s2_rd_data ,//32 write data
input wire s2_rdy_n ,//01
//slave 3
input wire s3_cs_n ,//01 chip select
input wire [`WordDataBus] s3_rd_data ,//32 write data
input wire s3_rdy_n ,//01
//slave 4
input wire s4_cs_n ,//01 chip select
input wire [`WordDataBus] s4_rd_data ,//32 write data
input wire s4_rdy_n ,//01
//slave 5
input wire s5_cs_n ,//01 chip select
input wire [`WordDataBus] s5_rd_data ,//32 write data
input wire s5_rdy_n ,//01
//slave 6
input wire s6_cs_n ,//01 chip select
input wire [`WordDataBus] s6_rd_data ,//32 write data
input wire s6_rdy_n ,//01
//slave 7
input wire s7_cs_n ,//01 chip select
input wire [`WordDataBus] s7_rd_data ,//32 write data
input wire s7_rdy_n ,//01
//share
output reg [`WordDataBus] m_rd_data ,//32
output reg m_rdy_n //01 Ready
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
always @(*) begin : BUS_SLAVE_MULTIPLEX
if(s0_cs_n == `ENABLE_N)
begin
m_rd_data = s0_rd_data;
m_rdy_n = s0_rdy_n;
end
else if(s1_cs_n == `ENABLE_N)
begin
m_rd_data = s1_rd_data;
m_rdy_n = s1_rdy_n;
end
else if(s2_cs_n == `ENABLE_N)
begin
m_rd_data = s2_rd_data;
m_rdy_n = s2_rdy_n;
end
else if(s3_cs_n == `ENABLE_N)
begin
m_rd_data = s3_rd_data;
m_rdy_n = s3_rdy_n;
end
else if(s4_cs_n == `ENABLE_N)
begin
m_rd_data = s4_rd_data;
m_rdy_n = s4_rdy_n;
end
else if(s5_cs_n == `ENABLE_N)
begin
m_rd_data = s5_rd_data;
m_rdy_n = s5_rdy_n;
end
else if(s6_cs_n == `ENABLE_N)
begin
m_rd_data = s6_rd_data;
m_rdy_n = s6_rdy_n;
end
else if(s7_cs_n == `ENABLE_N)
begin
m_rd_data = s7_rd_data;
m_rdy_n = s7_rdy_n;
end
else
begin
m_rd_data = `WORD_DATA_W'h0;
m_rdy_n = `DISABLE_N;
end
end
//------------------------------------------------------------------------------------------------
// 3.2 the master owner control logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using db = double; using str = string; using pi = pair<int, int>; using pl = pair<ll, ll>; using pd = pair<db, db>; using vi = vector<int>; using vb = vector<bool>; using vl = vector<ll>; using vd = vector<db>; using vs = vector<str>; using vpi = vector<pi>; using vpl = vector<pl>; using vpd = vector<pd>; template <class T> using V = vector<T>; template <class T, size_t SZ> using AR = array<T, SZ>; template <class T> using PR = pair<T, T>; const int MOD = 1e9 + 7; const int MX = 2e5 + 5; const ll INF = 1e18; const ld PI = acos((ld)-1); const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; mt19937 rng((uint32_t)chrono::steady_clock::now().time_since_epoch().count()); template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; constexpr int pct(int x) { return __builtin_popcount(x); } constexpr int bits(int x) { return 31 - __builtin_clz(x); } ll cdiv(ll a, ll b) { return a / b + ((a ^ b) > 0 && a % b); } ll fdiv(ll a, ll b) { return a / b - ((a ^ b) < 0 && a % b); } template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } template <class T, class U> T fstTrue(T lo, T hi, U first) { hi++; assert(lo <= hi); while (lo < hi) { T mid = lo + (hi - lo) / 2; first(mid) ? hi = mid : lo = mid + 1; } return lo; } template <class T, class U> T lstTrue(T lo, T hi, U first) { lo--; assert(lo <= hi); while (lo < hi) { T mid = lo + (hi - lo + 1) / 2; first(mid) ? lo = mid : hi = mid - 1; } return lo; } template <class T> void remDup(vector<T>& v) { sort(begin(v), end(v)); v.erase(unique(begin(v), end(v)), end(v)); } template <class T, class U> void erase(T& t, const U& u) { auto it = t.find(u); assert(it != end(t)); t.erase(u); } template <class T> void re(complex<T>& c); template <class T, class U> void re(pair<T, U>& p); template <class T> void re(vector<T>& v); template <class T, size_t SZ> void re(AR<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(db& d) { str t; re(t); d = stod(t); } void re(ld& d) { str t; re(t); d = stold(t); } template <class T, class... U> void re(T& t, U&... u) { re(t); re(u...); } template <class T> void re(complex<T>& c) { T a, b; re(a, b); c = {a, b}; } template <class T, class U> void re(pair<T, U>& p) { re(p.first, p.second); } template <class T> void re(vector<T>& x) { for (auto& a : x) re(a); } template <class T, size_t SZ> void re(AR<T, SZ>& x) { for (auto& a : x) re(a); } template <class T> void rv(int& n, vector<T>& x) { re(n); x.resize(n); for (auto& a : x) re(a); } str to_string(char c) { return str(1, c); } str to_string(const char* second) { return (str)second; } str to_string(str second) { return second; } str to_string(bool b) { return to_string((int)b); } template <class T> str to_string(complex<T> c) { stringstream ss; ss << c; return ss.str(); } str to_string(vector<bool> v) { str res = { ; for (int i = (0); i < ((int)(v).size()); ++i) res += char( 0 + v[i]); res += } ; return res; } template <size_t SZ> str to_string(bitset<SZ> b) { str res = ; for (int i = (0); i < (SZ); ++i) res += char( 0 + b[i]); return res; } template <class T, class U> str to_string(pair<T, U> p); template <class T> str to_string(T v) { bool fst = 1; str res = ; for (const auto& x : v) { if (!fst) res += ; fst = 0; res += to_string(x); } return res; } template <class T, class U> str to_string(pair<T, U> p) { return to_string(p.first) + + to_string(p.second); } template <class T> void pr(T x) { cout << to_string(x); } template <class T, class... U> void pr(const T& t, const U&... u) { pr(t); pr(u...); } void ps() { pr( n ); } template <class T, class... U> void ps(const T& t, const U&... u) { pr(t); if (sizeof...(u)) pr( ); ps(u...); } void DBG() { cerr << ] << endl; } template <class T, class... U> void DBG(const T& t, const U&... u) { cerr << to_string(t); if (sizeof...(u)) cerr << , ; DBG(u...); } void setIn(str second) { freopen(second.c_str(), r , stdin); } void setOut(str second) { freopen(second.c_str(), w , stdout); } void unsyncIO() { cin.tie(0)->sync_with_stdio(0); } void setIO(str second = ) { unsyncIO(); if ((int)(second).size()) { setIn(second + .in ), setOut(second + .out ); } } int N; vl A; void solve(int tc) { re(N); A.resize(N); re(A); vl fst(N), lst(N); for (int i = (0); i < (N - 1); ++i) { ll dif = A[i] - A[i + 1]; if (dif >= 0) { fst[i] += dif; } else { lst[i + 1] -= dif; } } ll sum = 0; for (int i = (0); i < (N); ++i) sum += fst[i]; 0; if (sum > A[0]) ps( NO ); else ps( YES ); } int main() { setIO(); int TC; re(TC); for (int i = (1); i < (TC + 1); ++i) solve(i); } |
// $Id: rtr_flit_type_check.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// flit type checker module
//==============================================================================
module rtr_flit_type_check
(clk, reset, active, flit_valid, flit_head, flit_tail, error);
`include "c_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
parameter reset_type = `RESET_TYPE_ASYNC;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
input clk;
input reset;
input active;
input flit_valid;
input flit_head;
input flit_tail;
output error;
wire error;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
wire packet_active_s, packet_active_q;
assign packet_active_s = flit_valid ?
((packet_active_q | flit_head) & ~flit_tail) :
packet_active_q;
c_dff
#(.width(1),
.reset_type(reset_type))
packet_activeq
(.clk(clk),
.reset(reset),
.active(active),
.d(packet_active_s),
.q(packet_active_q));
assign error = flit_valid & (flit_head ~^ packet_active_q);
// synopsys translate_off
always @(posedge clk)
begin
if(error)
$display("ERROR: Received flit with unexpected type in module %m.");
end
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n <= 2) cout << -1 ; else if (n == 3) cout << 210 ; else { int mod = 1; for (int i = 1; i < n; ++i) mod = (mod * 10) % 210; if (n > 3) cout << 1 ; for (int i = 0; i < n - 4; ++i) cout << 0 ; if (210 - mod < 100) cout << 0 ; cout << 210 - mod; } } |
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Encoder Unit ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_encoder.v,v 1.3 2002/10/31 12:51:44 rherveille Exp $
//
// $Date: 2002/10/31 12:51:44 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_encoder.v,v $
// Revision 1.3 2002/10/31 12:51:44 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 18:58:51 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.1 2002/10/23 09:07:01 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_encoder(
clk,
ena,
dstrb,
din,
qnt_val,
qnt_cnt,
size,
rlen,
amp,
douten,
SE,
SI,
SO
);
//
// parameters
//
////////////////////////////////////////////////////////////////////
// //
// ITU-T.81, ITU-T.83 & Coefficient resolution notes //
// //
////////////////////////////////////////////////////////////////////
// //
// Worst case error (all input values -128) is //
// zero (i.e. no errors) when using 15bit coefficients //
// //
// Using less bits for the coefficients produces a biterror //
// approx. equal to (15 - used_coefficient-bits). //
// i.e. 14bit coefficients, errors in dout-bit[0] only //
// 13bit coefficients, errors in dout-bits[1:0] //
// 12bit coefficients, errors in dout-bits[2:0] etc. //
// Tests with real non-continous tone image data have shown that //
// even when using 13bit coefficients errors remain in the lsb //
// only (i.e. dout-bit[0] //
// //
// The amount of coefficient-bits needed is dependent on the //
// desired quality. //
// The JPEG-standard compliance specs.(ITU-T.83) prescribe //
// that the output of the combined DCT AND Quantization unit //
// shall not exceed 1 for the desired quality. //
// //
// This means for high quantization levels, lesser bits //
// for the DCT unit can be used. //
// //
// Looking at the recommended "quantization tables for generic //
// compliance testing of DCT-based processes" (ITU-T.83 annex B) //
// it can be noticed that relatively large quantization values //
// are being used. Errors in the lower-order bits should //
// therefore not be visible. //
// Tests with real continuous and non-continous tone image data //
// have shown that when using the examples quantization tables //
// from ITU-T.81 annex K 10bit coefficients are sufficient to //
// comply to the ITU-T.83 specs. Compliance tests have been met //
// using as little as 9bit coefficients. //
// For certain applications some of the lower-order bits could //
// actually be discarded. When looking at the luminance and //
// chrominance example quantization tables (ITU-T.81 annex K) //
// it can be seen that the smallest quantization value is ten //
// (qnt_val_min = 10). This means that the lowest 2bits can be //
// discarded (set to zero '0') without having any effect on the //
// final result. In this example 11 bit or 12 bit coefficients //
// would be sufficient. //
// //
////////////////////////////////////////////////////////////////////
parameter coef_width = 11;
parameter di_width = 8; // no function yet
//
// inputs & outputs
//
input SE;
input SI;
output SO;
input clk; // system clock
input ena; // clock enable
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width-1:0] din;
input [7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // quantization value address
output [ 3:0] size; // size
output [ 3:0] rlen; // run-length
output [11:0] amp; // amplitude
output douten; // data output enable
//
// variables
//
wire rst = 1'b1; // active low asynchronous reset
wire fdct_doe, qnr_doe;
wire [11:0] fdct_dout;
reg [11:0] dfdct_dout;
wire [10:0] qnr_dout;
reg dqnr_doe;
//
// module body
//
// Hookup FDCT & ZigZag module
fdct #(coef_width, di_width, 12)
fdct_zigzag(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout(fdct_dout),
.douten(fdct_doe)
);
// delay 'fdct_dout' => wait for synchronous quantization RAM/ROM
always @(posedge clk)
if(ena)
dfdct_dout <= #1 fdct_dout;
// Hookup QNR (Quantization and Rounding) unit
jpeg_qnr
qnr(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(fdct_doe),
.din(dfdct_dout),
.qnt_val(qnt_val),
.qnt_cnt(qnt_cnt),
.dout(qnr_dout),
.douten(qnr_doe)
);
// delay douten 1 clk_cycle => account for delayed fdct_res & qnt_val
always @(posedge clk)
if(ena)
dqnr_doe <= #1 qnr_doe;
//
// TODO: Insert DC differential generator here.
//
wire [11:0] dc_diff_dout = {qnr_dout[10], qnr_dout};
wire dc_diff_doe = dqnr_doe;
// Hookup Run Length Encoder
jpeg_rle
rle(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dc_diff_doe),
.din(dc_diff_dout),
.size(size),
.rlen(rlen),
.amp(amp),
.douten(douten),
.bstart()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { int tot = 0, fh = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fh = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { tot = tot * 10 + c - 0 ; c = getchar(); } return tot * fh; } void getstr(char *a) { char c = getchar(); int len = 0; while (!((c >= A && c <= Z ) || (c >= a && c <= z ) || (c >= 0 && c <= 9 ))) c = getchar(); while ((c >= A && c <= Z ) || (c >= a && c <= z ) || (c >= 0 && c <= 9 )) { a[++len] = c; c = getchar(); } } const int maxn = 200100; int n, t, q, ans, block, num, belong[maxn]; long long a[maxn], L[2000], R[2000], sum[2000], tag[2000]; void build() { block = sqrt(n); num = n / block; if (num * block != n) num++; for (int i = 1; i <= num; i++) { L[i] = block * (i - 1) + 1; R[i] = block * i; R[num] = n; for (int j = L[i]; j <= R[i]; j++) { belong[j] = i; sum[i] += a[j]; } } } int fd(int l, int r, int lim) {} int main() { n = read(); q = read(); for (int i = 1; i <= n; i++) a[i] = read(); build(); while (q--) { t = read(); if (t == 1) { int x = read(); long long y = read(); for (int i = 1; i < belong[x]; i++) if (tag[i] == 0) { if (a[R[i]] < y) { if (a[L[i]] <= y) { tag[i] = y; sum[i] = (R[i] - L[i] + 1ll) * tag[i]; } else { sum[i] = 0; for (int j = L[i]; j <= R[i]; j++) { a[j] = max(a[j], y); sum[i] += a[j]; } } } } else { if (tag[i] < y) { tag[i] = y; sum[i] = (R[i] - L[i] + 1ll) * tag[i]; } } int cur = belong[x]; sum[cur] = 0; for (int i = L[cur]; i <= R[cur]; i++) if (i <= x) { a[i] = max(a[i], max(y, tag[cur])); sum[cur] += a[i]; } else { a[i] = max(a[i], tag[cur]); sum[cur] += a[i]; } tag[cur] = 0; } else { int x = read(); long long y = read(); ans = 0; int cur = belong[x]; for (int i = x; i <= R[cur]; i++) { long long tmp = max(tag[cur], a[i]); if (y >= tmp) { y -= tmp; ans++; tmp = max(tag[cur], a[R[cur]]); if (tmp > y) break; } } for (int i = belong[x] + 1; i <= num; i++) { long long tmp = sum[i]; if (y >= tmp) { y -= tmp; ans += R[i] - L[i] + 1; } else { tmp = max(tag[i], a[R[i]]); if (tmp > y) continue; for (int j = L[i]; j <= R[i]; j++) { tmp = max(tag[i], a[j]); if (y >= tmp) { y -= tmp; ans++; tmp = max(tag[i], a[R[i]]); if (tmp > y) break; } } } } cout << ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; bool visit[4]; long long dfs(vector<long long> &v, vector<char> &chars) { long long res = LLONG_MAX; if (v.size() == 1) { return v.front(); } for (int i = 0; i < v.size() - 1; i++) { for (int j = i + 1; j < v.size(); j++) { vector<long long> tmp = v; tmp.erase(tmp.begin() + i); tmp.erase(tmp.begin() + j - 1); long long r = 0; if (chars.front() == + ) { r = v[i] + v[j]; } else { r = v[i] * v[j]; } tmp.push_back(r); vector<char> ch = chars; ch.erase(ch.begin()); res = min(res, dfs(tmp, ch)); } } return res; } int main() { vector<long long> v(4); vector<char> chars(3); for (int i = 0; i < 4; i++) { cin >> v[i]; } for (int i = 0; i < 3; i++) { cin >> chars[i]; } cout << dfs(v, chars) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> v; int main() { string x, y; int cnt = 0; char temp; int n; cin >> n; n = n + n - 1; for (int i = 0; i < n; i++) { cin >> x; if (x == ** ) continue; cin >> y; x += y; sort(v.begin(), v.end()); if (binary_search(v.begin(), v.end(), x)) continue; cnt++; v.push_back(x); for (int j = 1; j <= 3; j++) { y = ; if (j == 1) { y += x[2]; y += x[0]; y += x[3]; y += x[1]; v.push_back(y); } else if (j == 2) { y += x[3]; y += x[2]; y += x[1]; y += x[0]; v.push_back(y); } else if (j == 3) { y += x[1]; y += x[3]; y += x[0]; y += x[2]; v.push_back(y); } } } cout << cnt; return 0; } |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: win_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module win_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [6:0] rdaddress;
input [6:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef SIMULATION
altsyncram_component.init_file = "../../dgn/rtl/altera/win_ram.mif",
`else //for syn
altsyncram_component.init_file = "../rtl/altera/win_ram.mif",
`endif
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "win_ram.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "win_ram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL "rdaddress[6..0]"
// Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL "wraddress[6..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
// Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL win_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL win_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL win_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL win_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL win_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL win_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the encoder
// Import the modules that will be tested for in this testbench
`include "ham_15_11_encoder.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_encoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [14:0] cout;
// Declare "reg" signals: inputs to the DUT
reg [10:0] b;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
ham_15_11_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
b,cout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
b = 11'b11010110000;
$display(b[1]," << b1 b2 >>",b[2]);
$display(b[3]," << b1 b2 >>",b[4]);
// @ t=0,
#1;
b = 11'b11100011100;
#1;
b = 11'b11001110101;
#1;
b = 11'b11110111001;
#1;
b = 11'b11111000010;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
module arbiter(
// I-Port
input [63:0] idat_i,
input [63:0] iadr_i,
input iwe_i,
input icyc_i,
input istb_i,
input [1:0] isiz_i,
input isigned_i,
output iack_o,
output [63:0] idat_o,
// D-Port
input [63:0] ddat_i,
input [63:0] dadr_i,
input dwe_i,
input dcyc_i,
input dstb_i,
input [1:0] dsiz_i,
input dsigned_i,
output dack_o,
output [63:0] ddat_o,
// X-Port
output [63:0] xdat_o,
output [63:0] xadr_o,
output xwe_o,
output xcyc_o,
output xstb_o,
output [1:0] xsiz_o,
output xsigned_o,
input xack_i,
input [63:0] xdat_i,
// Miscellaneous
input clk_i,
input reset_i
);
reg reserve_i, reserve_d;
wire en_i = (~reset_i & icyc_i & ~dcyc_i) |
(~reset_i & icyc_i & dcyc_i & reserve_i & ~reserve_d);
wire en_d = (~reset_i & ~icyc_i & dcyc_i) |
(~reset_i & icyc_i & dcyc_i & ~reserve_i) |
(~reset_i & icyc_i & dcyc_i & reserve_i & reserve_d);
assign xdat_o = (en_i ? idat_i : 64'd0) | (en_d ? ddat_i : 64'd0);
assign xadr_o = (en_i ? iadr_i : 64'd0) | (en_d ? dadr_i : 64'd0);
assign xwe_o = (en_i & iwe_i) | (en_d & dwe_i);
assign xcyc_o = (en_i & icyc_i) | (en_d & dcyc_i);
assign xstb_o = (en_i & istb_i) | (en_d & dstb_i);
assign xsiz_o = (en_i ? isiz_i : 2'd0) | (en_d ? dsiz_i : 2'd0);
assign xsigned_o = (en_i & isigned_i) | (en_d & dsigned_i);
assign iack_o = (en_i & xack_i);
assign dack_o = (en_d & xack_i);
assign idat_o = (en_i ? xdat_i : 64'd0);
assign ddat_o = (en_d ? xdat_i : 64'd0);
always @(posedge clk_i) begin
reserve_i <= en_i;
reserve_d <= en_d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[5000]; int n, m; int c[100][100]; char t[100][100]; bool used[100][100]; char clr[5000]; bool valid(int i, int j) { return (0 <= i && i < n && 0 <= j && j < m); }; int di[4] = {-1, 1, 0, 0}; int dj[4] = {0, 0, -1, 1}; void dfs(int i, int j, int color) { used[i][j] = true; c[i][j] = color; for (int k = 0; k < 4; k++) { int i1 = i + di[k]; int j1 = j + dj[k]; if (valid(i1, j1) && t[i1][j1] == t[i][j] && !used[i1][j1]) dfs(i1, j1, color); } } void add_edge(int i, int j) { g[i].push_back(j); g[j].push_back(i); } void dfs1(int i, int j) { used[i][j] = true; for (int k = 0; k < 4; k++) { int i1 = i + di[k]; int j1 = j + dj[k]; if (valid(i1, j1)) { if (t[i1][j1] == t[i][j] && !used[i1][j1]) dfs1(i1, j1); if (t[i1][j1] != t[i][j]) add_edge(c[i1][j1], c[i][j]); } } } int l = 0; bool _used[10000]; int h[3000]; int q[10000]; int bfs(int v) { for (int i = 0; i < l; i++) { _used[i] = false; h[i] = 1000 * 1000 * 1000; }; int rp = 0; int wp = 1; q[0] = v; h[v] = 0; while (rp != wp) { v = q[rp]; rp++; for (int i = 0; i < g[v].size(); i++) { int u = g[v][i]; if (h[u] > h[v] + 1) { h[u] = h[v] + 1; q[wp] = u; wp++; } } } int vmax = 0; for (int i = 0; i < l; i++) vmax = max(vmax, h[i]); return vmax; } int main() { scanf( %d%d n , &n, &m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) scanf( %c , &t[i][j]); scanf( n ); } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (!used[i][j]) { clr[l] = t[i][j]; dfs(i, j, l++); } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) used[i][j] = false; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (!used[i][j]) dfs1(i, j); int best = 1000 * 1000 * 1000; for (int i = 0; i < l; i++) { int cur = bfs(i); if (clr[i] == W && (cur & 1)) cur++; if (clr[i] == B && (cur % 2 == 0)) cur++; best = min(best, cur); } cout << best << endl; return 0; } |
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