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//-------------------------------------------------------------------
//-- baudtx2_tb.v
//-- Banco de pruebas para la tranmision de datos continua
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`include "baudgen.vh"
module baudtx2_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx2 #(`B115200)
dut(
.clk(clk),
.load(dtr),
.tx(tx)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("baudtx2_tb.vcd");
$dumpvars(0, baudtx2_tb);
//-- Primer envio: cargar y enviar
#10 dtr <= 0;
#300 dtr <= 1;
//-- Segundo envio
#10000 dtr <=0;
#2000 dtr <=1;
//-- Tercer envio
#10000 dtr <=0;
#2000 dtr <=1;
#5000 $display("FIN de la simulacion");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; string s[n]; long long flg = 1; long long ar[n]; for (long long i = 0; i < n; i++) { cin >> s[i]; long long flag = 0; long long pos = -1; for (long long j = 0; j < n; j++) { if (s[i][j] == . ) { flag = 1; pos = j; break; } } if (flag == 0) { flg = 0; } ar[i] = pos; } if (!flg) { flg = 1; long long ar[n]; for (long long i = 0; i < n; i++) { long long flag = 0; long long pos = -1; for (long long j = 0; j < n; j++) { if (s[j][i] == . ) { flag = 1; pos = j; break; } } if (flag == 0) { flg = 0; break; } ar[i] = pos; } if (!flg) cout << -1; else { for (long long i = 0; i < n; i++) { cout << ar[i] + 1 << << i + 1 << n ; } } return 0; } else { for (long long i = 0; i < n; i++) { cout << i + 1 << << ar[i] + 1 << n ; } } } |
#include <bits/stdc++.h> using namespace std; int n, seq[100005]; char s[2][55]; string a[100005], b[100005], cur; void solve() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s %s , s[0], s[1]); a[i] = s[0]; b[i] = s[1]; } for (int i = 0; i < n; i++) { scanf( %d , &seq[i]); seq[i]--; } if (a[seq[0]] < b[seq[0]]) cur = a[seq[0]]; else cur = b[seq[0]]; for (int i = 1; i < n; i++) { if (cur < a[seq[i]] && cur < b[seq[i]]) { if (a[seq[i]] < b[seq[i]]) cur = a[seq[i]]; else cur = b[seq[i]]; } else if (cur < a[seq[i]]) cur = a[seq[i]]; else if (cur < b[seq[i]]) cur = b[seq[i]]; else { puts( NO ); return; } } puts( YES ); } int main(void) { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, k, l, m, n, t, x, y; cin >> n; if (n % 2 == 0) cout << n + 4 << << 4 << endl; else cout << n + 9 << << 9 << endl; return 0; } |
`timescale 1ns / 1ps
//__________________________________________________uart_rx
`define IDLE 1'd0
`define RECV_BIT 1'd1
//__________Test Bench
`define BIT_TMR_MAX 10'd869 // #10240 <-- 115200 : tb #1738
//`define BIT_TMR_MAX 14'd10417//14'b10100010110000 // 14'd10416 #10417
//______________________________________________________________________
// `define BIT_INDEX_MAX 4'd9
module uart_rx(
input clk,
input rst,
input rxd,
output [7:0] data_rx,
output busy
);
//____________________________________________________________Global
reg [8:0] rxdata;
assign data_rx[7:0] = rxdata[8:1];
reg busy_reg;
assign busy = busy_reg;
reg [9:0] bitTmr;
reg [3:0] bitIndex;
reg rxState;
reg [9:0] bitCnt_0;
reg [9:0] bitCnt_1;
/*
wire rxBit;
assign rxBit =( (rxState != `RECV_BIT) ? dummy :
( (bitIndex == 1) ? rxdata[0] :
( (bitIndex == 2) ? rxdata[1] :
( (bitIndex == 3) ? rxdata[2] :
( (bitIndex == 4) ? rxdata[3] :
( (bitIndex == 5) ? rxdata[4] :
( (bitIndex == 6) ? rxdata[5] :
( (bitIndex == 7) ? rxdata[6] :
(bitIndex == 8) ? rxdata[7] :
dummy //when bitIndex == 0 : start signal(0) is not data
)
)
)
)
)
)
)
);
*/
always@(posedge clk) begin
if(rst)
begin
rxState <= `IDLE;
busy_reg <= 0;
end
else
begin
case(rxState)
`IDLE :
begin
bitIndex <= 0;
bitTmr <= 0;
bitCnt_0 <= 0;
bitCnt_1 <= 0;
if( rxd == 0 )
begin
rxState <= `RECV_BIT;
end
else
rxState <= `IDLE;
end
`RECV_BIT :
begin
if (bitTmr == `BIT_TMR_MAX-1)
begin
bitTmr <= 0;
bitCnt_0 <= 0;
bitCnt_1 <= 0;
if (bitIndex == 4'd9-1)
begin
// done!
busy_reg <= 1;
rxState <= `IDLE;
end
else
begin
busy_reg <= 0;
bitIndex <= bitIndex + 1'b1;
rxState <= `RECV_BIT;
end
end
else
begin
if(rxd == 0)
bitCnt_0 <= bitCnt_0 + 1'b1;
else
bitCnt_1 <= bitCnt_1 + 1'b1;
if( bitCnt_0 > bitCnt_1 )
rxdata[bitIndex] <= 0;
else
rxdata[bitIndex] <= 1;
bitTmr <= bitTmr + 1'b1;
rxState <= `RECV_BIT;
end
end
default :
begin
rxState <= `IDLE;
busy_reg <= 0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1, -1, -1, 1, 1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; template <class T> inline T biton(T n, T pos) { return n | ((T)1 << pos); } template <class T> inline T bitoff(T n, T pos) { return n & ~((T)1 << pos); } template <class T> inline T ison(T n, T pos) { return (bool)(n & ((T)1 << pos)); } template <class T> inline T gcd(T a, T b) { while (b) { a = a % b; swap(a, b); } return a; } template <class T> inline T bigmod(T p, T e, T m) { T ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % m; p = (p * p) % m; } return (T)ret; }; void solve() { string s, c; cin >> s >> c; if (s < c) { cout << s << endl; return; } int n = (int)s.size(); map<char, vector<int>> mn; map<char, set<char>> st; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (s[i] >= s[j]) { if (st[s[i]].count(s[j]) == 0) { mn[s[i]].push_back({j}); st[s[i]].insert(s[j]); } } } } for (int i = 0; i < n; i++) { for (auto m : mn) { for (auto j : m.second) { swap(s[i], s[j]); if (s < c) { cout << s << endl; return; } swap(s[i], s[j]); } } } cout << --- << endl; } int main() { ios_base::sync_with_stdio(false); cout.setf(ios::fixed); cout.precision(10); cout.tie(nullptr); cin.tie(nullptr); int t = 1; cin >> t; while (t--) { solve(); } return 0; } |
#include<bits/stdc++.h> using namespace std; int t,f,i,j,p,q,x,y,dx[128],dy[128]; char s[5008]; int main() { for(dx[ L ]=-(dx[ R ]=1),dy[ D ]=-(dy[ U ]=1),scanf( %d ,&t); t--; f?0:printf( 0 0 n )) for(scanf( %s ,s),f=i=p=q=0; s[i]; x||y?++i: (printf( %d %d n ,p,q),f=i=strlen(s))) for(p+=dx[s[i]],q+=dy[s[j=i]],j=x=y=0; s[j]; x+=dx[s[j]], y+=dy[s[j]],x==p&&y==q?(x-=dx[s[j]],y-=dy[s[j]]):0,++j); exit(0); } |
#include <bits/stdc++.h> using namespace std; const long long INF = 2e18; const long long INFINT = 2e9; const int N = 1000006; const int NN = 1006; const int MOD = 1000000007; int main() { ios_base::sync_with_stdio(0); long double n, h; cin >> n >> h; long double s = 1.0 * 1 * h / 2; long double k = 1.0 * s / n; long double mda = k; for (int i = 0; i < n - 1; i++) { long double l = 0; long double r = h; for (int it = 0; it < 10000; it++) { long double mid = 1.0 * (l + r) / 2; if ((1.0 * mid / h) * mid / 2 < k) { l = mid; } else { r = mid; } } cout << fixed << setprecision(9) << l << ; k = mda * (i + 2); } } |
#include <bits/stdc++.h> using namespace std; long long mod = 998244353; long long fast_exp(long long a, long long b) { if (b <= 0) return 1; else { long long res = 1; res = fast_exp(a, b / 2); res = (res * res) % mod; if (b % 2 == 1) res = (res * a) % mod; return res; } } long long n, m, k; long long dp[5001][5010] = {}; long long inv; int main() { cin >> n >> m >> k; dp[0][0] = 1; for (long long i = 0; i < k; i++) { for (long long j = 0; j < 5001; j++) { dp[i + 1][j] = (dp[i + 1][j] + (j)*dp[i][j]) % mod; dp[i + 1][j + 1] = (dp[i + 1][j + 1] + (n - j) * dp[i][j]) % mod; } } inv = fast_exp(m, mod - 2); long long num = 0; long long beg = fast_exp(m, n); for (long long i = 0; i <= 5001; i++) { num = (num + beg * dp[k][i]) % mod; beg = (beg * inv) % mod; } long long denom = fast_exp(m, n); denom = fast_exp(denom, mod - 2); cout << (num * denom) % mod << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using std::bitset; const double Pi = acos(-1); inline long long read() { long long x = 0; bool fu = 0; char ch = 0; while (ch > 9 || ch < 0 ) { ch = getchar(); if (ch == - ) fu = 1; } while (ch <= 9 && ch >= 0 ) x = (x * 10 - 48 + ch), ch = getchar(); return fu ? -x : x; } long long n, mod, w[100002], q, l, r; map<long long, long long> phi; inline long long go(long long num) { long long rt = num; for (long long i = 2; i * i <= num; i++) { if (num % i == 0) rt = rt * (i - 1) / i; while (num % i == 0) num /= i; } if (num > 1) rt = rt * (num - 1) / num; return rt; } inline long long pw(long long x, long long p, long long mod) { bool flag = 0; long long rt = 1; while (p) { if (p & 1) { if (rt * x >= mod) flag = 1; rt = rt * x % mod; } if (x * x >= mod) flag = 1; x = x * x % mod, p >>= 1; } return rt + flag * mod; } inline long long dfs(long long pos, long long mod) { if (pos > r || mod == 1) return 1; return pw(w[pos], dfs(pos + 1, phi[mod]), mod); } signed main() { cin >> n >> mod; l = mod; phi[1] = 1; while (l > 1) phi[l] = go(l), l = phi[l]; for (register long long i = 1, iend = n; i <= iend; ++i) w[i] = read(); cin >> q; while (q--) { l = read(), r = read(); cout << dfs(l, mod) % mod << n ; } return 0; } |
module main;
reg [2:0] Q;
reg clk, clr, up, down;
(*ivl_synthesis_off *)
initial begin
clk = 0;
up = 0;
down = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED");
$finish;
end
up = 1;
clr = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b010) begin
$display("FAILED");
$finish;
end
up = 0;
down = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
down = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
/*
* This statement models a snythesizable UP/DOWN counter. The up
* and down cases are enabled by up and down signals. If both
* signals are absent, the synthesizer should take the implicit
* case that Q <= Q;
*/
(* ivl_synthesis_on *)
always @(posedge clk, posedge clr)
if (clr) begin
Q <= 0;
end else begin
if (up)
Q <= Q + 1;
else if (down)
Q <= Q - 1;
end
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int arr[n]; int freq[101] = {0}; for (int i = 0; i < n; i++) { cin >> arr[i]; freq[arr[i]]++; } sort(freq, freq + 101, greater<int>()); int max = freq[0]; int num = 0; for (int i = 0; i < 101; i++) { if (freq[i] > 0) { num++; } } int b; int a = (float)k; int c = (float)max; if (k > max) { b = 1; } else if (c % a == 0) { b = max / k; } else if (k < max && a % c != 0) { b = (max / k) + 1; } cout << (b * k * num) - n << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { char a[1000000], b[1000000]; int n; cin >> n >> a; int l = strlen(a); for (int i = 1; i < n; i++) { cin >> b; for (int j = 0; j < l; j++) { if (a[j] == ? ) a[j] = b[j]; else if (b[j] == ? ) continue; else if (a[j] != b[j]) a[j] = 0 ; } } for (int i = 0; i < l; i++) { if (a[i] == 0 ) a[i] = ? ; else if (a[i] == ? ) a[i] = x ; } cout << a; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, i = 1; int main() { cin >> n; while ((n % i) == 0) i *= 3; cout << n / i + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, int> Ts; string size[101] = { S , M , L , XL , XXL }; inline int to_size(string s) { for (int i = 0; i < 5; ++i) { if (s == size[i]) return i; } } int main() { int a[11], k; string pe[10010]; for (int i = 0; i < 5; ++i) cin >> a[i]; for (int i = 0; i < 5; ++i) { Ts[size[i]] = a[i]; } cin >> k; for (int i = 0; i < k; ++i) cin >> pe[i]; for (int i = 0; i < k; ++i) { int pe1 = to_size(pe[i]); for (int j = 0; j <= 4; ++j) { if (pe1 + j <= 4) { if (Ts[size[pe1 + j]] > 0) { Ts[size[pe1 + j]]--; cout << size[pe1 + j] << endl; break; } } if (pe1 - j >= 0) { if (Ts[size[pe1 - j]] > 0) { Ts[size[pe1 - j]]--; cout << size[pe1 - j] << endl; break; } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 201000; struct str { long long nr; char c; }; int n, m; str a[2 * N], b[N], l[N]; vector<int> poz; bool cmp(str a, str b) { return (a.nr == b.nr && a.c == b.c); } int z[2 * N]; void calcpot() { int i, j; for (i = 1; i <= n; ++i) l[i] = a[i]; int nr = 0; for (i = 2; i < n; ++i) { a[++nr] = l[i]; } for (i = 1; i <= m; ++i) a[++nr] = b[i]; int el, pmax = 0; for (i = 2; i <= nr; ++i) { if (i >= pmax) { for (j = i; cmp(a[j], a[j - i + 1]) && j <= nr; ++j) ; --j; z[i] = j - i + 1; pmax = j; el = i; } else { z[i] = min(z[i - el + 1], pmax - i + 1); for (j = i + z[i] - 1; cmp(a[j], a[j - i + 1]) && j <= nr; ++j) ; --j; z[i] = j - i + 1; if (j > pmax) { pmax = j; el = i; } } if (i > n - 2 && z[i] >= n - 2) { poz.push_back(i - (n - 2)); } } } void calc() { int i, j; calcpot(); int r = 0; for (i = 0; i < poz.size(); ++i) { int e = poz[i]; if (e > 1 && e + n - 2 <= m) { if (l[1].c == b[e - 1].c && l[1].nr <= b[e - 1].nr) if (l[n].c == b[e + n - 2].c && l[n].nr <= b[e + n - 2].nr) ++r; } } cout << r; } int main() { int i, j; cin >> m >> n; for (i = 1; i <= m; ++i) { scanf( %I64d-%c , &b[i].nr, &b[i].c); if (i > 1 && b[i].c == b[i - 1].c) { b[i - 1].nr += b[i].nr; --m; --i; } } for (i = 1; i <= n; ++i) { scanf( %I64d-%c , &a[i].nr, &a[i].c); if (i > 1 && a[i].c == a[i - 1].c) { a[i - 1].nr += a[i].nr; --n; --i; } } if (n == 1) { long long r = 0; for (i = 1; i <= m; ++i) { if (a[1].c == b[i].c) r += max(0LL, b[i].nr - a[1].nr + 1); } cout << r; return 0; } if (n == 2) { if (m == 1) { cout << 0; return 0; } long long r = 0; for (i = 1; i < m; ++i) { if (a[1].c == b[i].c && a[2].c == b[i + 1].c && a[1].nr <= b[i].nr && a[2].nr <= b[i + 1].nr) ++r; } cout << r; return 0; } if (m < n) { cout << 0; return 0; } calc(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300500; int T[N], L[N], C[N]; int m; int len = 0; const int inf = 100500; int A[N]; int fs = -1, pos = -1; void apply() { for (int i = 0; i < m; i++) { if (i == m - 1) { pos = len; fs = m - 1; goto end; } if (T[i] == 1) { A[len++] = L[i]; if (len >= inf) { fs = i + 1; pos = len; goto end; } } else { assert(L[i] <= len); for (int q = 0; q < C[i]; q++) { for (int j = 0; j < L[i]; j++) { A[len++] = A[j]; } if (len >= inf) { for (int u = m - 1; u >= i; u--) T[u + 1] = T[u], L[u + 1] = L[u], C[u + 1] = C[u]; ++m; C[i + 1] = C[i] - q - 1; C[i] = q + 1; fs = i + 1; pos = len; goto end; } } } } end:; } inline int blen(int o) { if (T[o] == 1) return 1; else return L[o] * C[o]; } int main() { scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &T[i]); if (T[i] == 1) scanf( %d , &L[i]); else scanf( %d %d , &L[i], &C[i]); } T[m] = 0; L[m] = -42; m++; apply(); int n; scanf( %d , &n); int curg = fs; long long l = pos, r = pos + blen(fs); for (int i = 0; i < n; i++) { long long x; scanf( %I64d , &x); --x; int ans = -1; if (x < len) ans = A[(int)x]; else { while (r <= x && curg < m - 1) l = r, r += blen(++curg); assert(l <= x && x < r); if (T[curg] == 1) ans = L[curg]; else ans = A[(x - l) % L[curg]]; } printf( %d%c , ans, n [i + 1 == n]); } } |
#include <bits/stdc++.h> using namespace std; const long long md = 1e9 + 7; int main() { cout.precision(12); iostream::sync_with_stdio(0); cin.tie(0), cout.tie(0); const int MX = 1e6 + 1; vector<int> pr(MX, 1); vector<int> o; for (int i = 2; i < MX; i++) { if (!pr[i]) continue; o.push_back(i); for (long long j = i * 1ll * i; j < MX; j += i) pr[j] = 0; } long long n, x, y; cin >> n >> x >> y; unordered_map<long long, long long> q; vector<long long> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; long long c = a[i]; for (int j : o) { if (j * 1ll * j > a[i]) break; if (a[i] % j) continue; while (a[i] % j == 0) a[i] /= j; q[j]++; } if (a[i] != 1) q[a[i]]++; a[i] = c; } long long mx = 0; for (auto i : q) mx = max(mx, i.second); if (x <= y) { cout << (n - mx) * x << n ; return 0; } long long ans = (n - q[2]) * y; for (auto i : q) { if (i.second <= q[2]) continue; long long res = 0; bool ch = 1; for (long long e : a) { long long d = (i.first - (e % i.first)) % i.first; res += min(x, y * d); if (res > ans) { ch = 0; break; } } if (ch) ans = min(ans, res); } cout << ans; return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: rd_bitslip.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:34 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Shifts and delays data from ISERDES, in both memory clock and internal
// clock cycles. Used to uniquely shift/delay each byte to align all bytes
// in data word
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: rd_bitslip.v,v 1.2 2010/02/26 08:58:34 pboya Exp $
**$Date: 2010/02/26 08:58:34 $
**$Author: pboya $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/rd_bitslip.v,v $
******************************************************************************/
`timescale 1ps/1ps
module rd_bitslip #
(
parameter TCQ = 100
)
(
input clk,
input [1:0] bitslip_cnt,
input [1:0] clkdly_cnt,
input [5:0] din,
output reg [3:0] qout
);
reg din2_r;
reg [3:0] slip_out;
reg [3:0] slip_out_r;
reg [3:0] slip_out_r2;
reg [3:0] slip_out_r3;
//***************************************************************************
always @(posedge clk)
din2_r <= #TCQ din[2];
// Can shift data from ISERDES from 0-3 fast clock cycles
// NOTE: This is coded combinationally, in order to allow register to
// occur after MUXing of delayed outputs. Timing may be difficult to
// meet on this logic, if necessary, the register may need to be moved
// here instead, or another register added.
always @(bitslip_cnt or din or din2_r)
case (bitslip_cnt)
2'b00: // No slip
slip_out = {din[3], din[2], din[1], din[0]};
2'b01: // Slip = 0.5 cycle
slip_out = {din[4], din[3], din[2], din[1]};
2'b10: // Slip = 1 cycle
slip_out = {din[5], din[4], din[3], din[2]};
2'b11: // Slip = 1.5 cycle
slip_out = {din2_r, din[5], din[4], din[3]};
endcase
// Can delay up to 3 additional internal clock cycles - this accounts
// not only for delays due to DRAM, PCB routing between different bytes,
// but also differences within the FPGA - e.g. clock skew between different
// I/O columns, and differences in latency between different circular
// buffers or whatever synchronization method (FIFO) is used to get the
// data into the global clock domain
always @(posedge clk) begin
slip_out_r <= #TCQ slip_out;
slip_out_r2 <= #TCQ slip_out_r;
slip_out_r3 <= #TCQ slip_out_r2;
end
always @(posedge clk)
case (clkdly_cnt)
2'b00: qout <= #TCQ slip_out;
2'b01: qout <= #TCQ slip_out_r;
2'b10: qout <= #TCQ slip_out_r2;
2'b11: qout <= #TCQ slip_out_r3;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_0_V
`define SKY130_FD_SC_HD__O311AI_0_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311ai_0 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311ai_0 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_0_V
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 2e5 + 7; const long long INF = 3e18 + 7; long long n, t; long long a[MAXN], p[MAXN], l[MAXN], r[MAXN]; long long ans[MAXN]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> t; for (long long i = 0; i < n; ++i) cin >> a[i]; for (long long i = 0; i < n; ++i) { cin >> p[i]; --p[i]; } for (long long i = 0; i < n - 1; ++i) { if (p[i + 1] < p[i]) { cout << No n ; exit(0); } } for (long long i = 0; i < n; ++i) { l[i] = 1; r[i] = INF; } for (long long i = 0; i < n; ++i) { l[p[i]] = max(l[p[i]], a[i] + t); } for (long long i = 0; i < n; ++i) { l[i] = max(l[i], a[i] + t); } long long mx = -1; for (long long i = 0; i < n - 1; ++i) { mx = max(mx, p[i]); if (i < mx) { l[i] = max(l[i], a[i + 1] + t); } } for (long long i = 0; i < n - 1; ++i) { if (p[i] < i) { r[p[i]] = min(r[p[i]], a[p[i]] + t - 1); } else { r[p[i]] = min(r[p[i]], a[p[i] + 1] + t - 1); } } for (long long i = 0; i < n; ++i) { if (!i) ans[i] = l[i]; else ans[i] = max(ans[i - 1] + 1, l[i]); } for (long long i = 0; i < n - 1; ++i) { if (ans[i + 1] <= a[i]) { cout << No n ; exit(0); } if (!(l[i] <= ans[i] && ans[i] <= r[i])) { cout << No n ; exit(0); } } cout << Yes n ; for (long long i = 0; i < n; ++i) { cout << ans[i] << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, mx[400000], mn[400000]; long long seg[400000 * 4]; vector<long long> compress(vector<long long> x) { vector<long long> ans = x; vector<pair<long long, long long>> p; p.push_back({0, 0}); for (long long i = 1; i < x.size(); i++) { p.push_back({x[i], i}); } sort(p.begin(), p.end()); ans[p[1].second] = 1; for (long long i = 2; i < p.size(); i++) { if (p[i].first > p[i - 1].first) ans[p[i].second] = ans[p[i - 1].second] + 1; else ans[p[i].second] = ans[p[i - 1].second]; } return ans; } void update(long long pos, long long val, long long l1, long long r1, long long node) { if (l1 == r1) { seg[node] = val; return; } long long mid = (l1 + r1) / 2; if (pos <= mid) { update(pos, val, l1, mid, 2 * node); } else update(pos, val, mid + 1, r1, 2 * node + 1); seg[node] = max(seg[2 * node], seg[2 * node + 1]); } long long queri(long long l, long long r, long long l1, long long r1, long long node) { if (l1 > r or r1 < l) return 0; if (l <= l1 and r1 <= r) return seg[node]; long long mid = (l1 + r1) / 2; return max(queri(l, r, l1, mid, 2 * node), queri(l, r, mid + 1, r1, 2 * node + 1)); } void solv() { cin >> n; vector<long long> a(n + 1); set<long long> s; for (long long i = 1; i < n + 1; i++) { cin >> a[i]; s.insert(a[i]); mx[i] = 0; mn[i] = 400000; } a = compress(a); for (long long i = 1; i < n + 1; i++) { mx[a[i]] = i; mn[a[i]] = min(mn[a[i]], i); } long long l = 1; long long len = 0; for (long long i = 1; i < s.size() + 1; i++) { update(i, mx[i], 1, n, 1); } for (long long i = 1; i < s.size() + 1; i++) { while (queri(l, i - 1, 1, n, 1) > mn[i] and l < i) l++; len = max(len, i - l + 1); } long long c = s.size(); cout << c - len << n ; } signed main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); long long q; cin >> q; while (q--) solv(); } |
#include <bits/stdc++.h> using namespace std; const long long BIG = 1000000000000000000LL; void solve(); signed main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; } const long long borne = 3 * (long long)(1e5) + 5; long long tab[borne]; long long som[borne]; long long nbElem, nbParties; void solve() { cin >> nbElem >> nbParties; for (long long i = (0); i < (nbElem); ++i) { cin >> tab[i]; } som[0] = tab[0]; for (long long i = (1); i < (nbElem); ++i) som[i] = tab[i] + som[i - 1]; vector<long long> ww(nbElem - 1); for (long long i = (0); i < (nbElem - 1); ++i) ww[i] = som[i]; sort(ww.begin(), ww.end()); long long res = nbParties * som[nbElem - 1]; for (long long i = (0); i < (nbParties - 1); ++i) res -= ww[i]; cout << res << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_V |
/**
* @module forward_unit
* @author sabertazimi
* @email
* @brief data hazards detection and forward signals generation
* @input ID_rs rs value in ID stage
* @input ID_rt rt value in ID stage
* @input EX_rs rs value in EX stage
* @input EX_rt rt value in EX stage
* @input MEM_rt rt value in MEM stage
* @input MEM_ramwe ramwe signal in MEM stage
* @input MEM_regwe regwe signal in MEM stage
* @input WB_regwe regwe signal in WB stage
* @input MEM_RW RW value in MEM stage
* @input WB_RW RW value in WB stage
* @output ID_forwardA forward signal for R1out in ID stage
* @output ID_forwardB forward signal for R2out in ID stage
* @output EX_forwardA forward signal for ALUXin in EX stage
* @output EX_forwardB forward signal for ALUYin in EX stage
* @output MEM_forward forward signal for RAMin in MEM stage
*/
module forward_unit
(
input [4:0] ID_rs,
input [4:0] ID_rt,
input [4:0] EX_rs,
input [4:0] EX_rt,
input [4:0] MEM_rt,
input MEM_ramwe,
input MEM_regwe,
input WB_regwe,
input [4:0] MEM_RW,
input [4:0] WB_RW,
output reg [1:0] ID_forwardA,
output reg [1:0] ID_forwardB,
output reg [1:0] EX_forwardA,
output reg [1:0] EX_forwardB,
output MEM_forward
);
// ID stage forward
// for branch usage in decode stage
// for WB.RegData -> ID/EX pipeline register data hazard
always @ ( * ) begin
if ((ID_rs != 0) && (ID_rs == MEM_RW) && MEM_regwe) begin
ID_forwardA <= 2'b10; // from MEM stage
end else if ((ID_rs != 0) && (ID_rs == WB_RW) && WB_regwe) begin
ID_forwardA <= 2'b01; // from WB stage
end else begin
ID_forwardA <= 2'b00; // no forwarding
end
end
always @ ( * ) begin
if ((ID_rt != 0) && (ID_rt == MEM_RW) && MEM_regwe) begin
ID_forwardB <= 2'b10; // from MEM stage
end else if ((ID_rt != 0) && (ID_rt == WB_RW) && WB_regwe) begin
ID_forwardB <= 2'b01; // from WB stage
end else begin
ID_forwardB <= 2'b00; // no forwarding
end
end
// EX stage forward
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb r-r-alu: $rd => $rs/$rt
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb r-imm-alu: $rd => $rs/$rt
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb load: $rt => $rs/$rt
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb jal : $ra => $rs/$rt
always @ ( * ) begin
if ((EX_rs != 0) && (EX_rs == MEM_RW) && MEM_regwe) begin
EX_forwardA <= 2'b10; // from memory MEM stage
end else if ((EX_rs != 0) && (EX_rs == WB_RW) && WB_regwe) begin
EX_forwardA <= 2'b01; // from WB stage
end else begin
EX_forwardA <= 2'b00; // no forwarding
end
end
always @ ( * ) begin
if ((EX_rt != 0) && (EX_rt == MEM_RW) && MEM_regwe) begin
EX_forwardB <= 2'b10; // from memory access stage
end else if ((EX_rt != 0) && (EX_rt == WB_RW) && WB_regwe) begin
EX_forwardB <= 2'b01; // from write back stage
end else begin
EX_forwardB <= 2'b00; // no forwarding
end
end
// MEM stage forward
// ex/mem sw + mem/wb load: $rt => $rt
assign MEM_forward = (WB_regwe && MEM_ramwe && MEM_rt != 0 && MEM_rt == WB_RW);
endmodule // forward_unit
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 2e6 + 99; const long long INF = 1e12; const long long mod = 1e9 + 7; set<pair<long long, long long>> dif; set<pair<long long, long long>>::iterator it; long long N, M, row[1000], col[1000], mark[500][500], imp[500][500], arr[500][500]; void dfs() { row[1] = 0; for (long long A = 1; A <= M; A++) { if (mark[1][A]) col[A] = 1 - row[1]; else col[A] = row[1]; } for (long long A = 2; A <= N; A++) { if (mark[A][1]) row[A] = 1 - col[1]; else row[A] = col[1]; } dif.clear(); for (long long A = 2; A <= N; A++) for (long long B = 2; B <= M; B++) if (abs(col[B] - row[A]) != mark[A][B]) dif.insert(make_pair(A, B)); return; } void out_() { cout << YES n ; for (long long A = 1; A <= N; A++) cout << row[A]; cout << n ; for (long long A = 1; A <= M; A++) cout << col[A]; exit(0); } signed main() { ios_base::sync_with_stdio(false); cin >> N >> M; for (long long A = 1; A <= N; A++) for (long long B = 1; B <= M; B++) cin >> arr[A][B]; for (long long A = 1; A <= N; A++) { for (long long B = 1; B <= M; B++) { if (!arr[A][B]) mark[A][B] = 1; else mark[A][B] = 0; } } for (long long A = 1; A <= M; A++) imp[1][A] = 1; for (long long A = 1; A <= N; A++) imp[A][1] = 1; dfs(); if (dif.empty()) out_(); for (long long A = 1; A <= N; A++) { for (long long B = 1; B <= M; B++) { mark[A][B] = 1 - mark[A][B]; if (imp[A][B]) { dfs(); if (dif.empty()) out_(); else { it = dif.end(); it--; if (dif.begin()->first == A and it->first == A) { for (auto A : dif) mark[A.first][A.second] ^= 1; out_(); } } } } } cout << NO ; return 0; } |
#include <bits/stdc++.h> #define mp make_pair #define mt make_tuple #define fi first #define se second #define pb push_back #define all(x) (x).begin(), (x).end() #define rall(x) (x).rbegin(), (x).rend() #define forn(i, n) for (int i = 0; i < (int)(n); ++i) #define for1(i, n) for (int i = 1; i <= (int)(n); ++i) #define ford(i, n) for (int i = (int)(n) - 1; i >= 0; --i) #define fore(i, a, b) for (int i = (int)(a); i <= (int)(b); ++i) using namespace std; typedef pair<int, int> pii; typedef vector<int> vi; typedef vector<pii> vpi; typedef vector<vi> vvi; typedef long long i64; typedef vector<i64> vi64; typedef vector<vi64> vvi64; typedef pair<i64, i64> pi64; typedef double ld; template<class T> bool uin(T &a, T b) { return a > b ? (a = b, true) : false; } template<class T> bool uax(T &a, T b) { return a < b ? (a = b, true) : false; } const int maxn = 200001, maxk = 30; vector<pii> e[maxn]; int ban[maxn]; int fib[maxk]; int w[maxn]; void dfsw(int v, int p, int k, int &c) { bool isC = true; w[v] = 1; for (auto [u, id]: e[v]) { if (u == p || ban[id]) continue; dfsw(u, v, k, c); isC &= 2 * w[u] <= fib[k]; w[v] += w[u]; } isC &= 2 * (fib[k] - w[v]) <= fib[k]; if (isC) c = v; } void dfsw2(int v, int p, int k, vector<pii> &es) { w[v] = 1; for (auto [u, id]: e[v]) { if (u == p || ban[id]) continue; dfsw2(u, v, k, es); w[v] += w[u]; if (w[u] == fib[k - 2]) { es.pb({id, u}); } } } bool check(int v, int k) { if (k <= 3) return true; dfsw(v, -1, k, v); int trash; vector<pii> es; dfsw2(v, -1, k, es); for (auto [id, u]: es) { ban[id] = 1; if (check(u, k - 2) && check(v, k - 1)) return true; } return false; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.precision(10); cout << fixed; #ifdef LOCAL_DEFINE freopen( input.txt , rt , stdin); #endif int n; cin >> n; forn(i, n - 1) { int u, v; cin >> u >> v; --u; --v; e[u].pb({v, i}); e[v].pb({u, i}); } fib[0] = fib[1] = 1; int p; for (p = 2; fib[p - 1] < n; ++p) { fib[p] = fib[p - 1] + fib[p - 2]; } --p; if (n == fib[p] && check(0, p)) cout << YES n ; else cout << NO n ; #ifdef LOCAL_DEFINE cerr << Time elapsed: << 1.0 * clock() / CLOCKS_PER_SEC << s. n ; #endif return 0; } |
/*
* Copyright (c) 1998-2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test is inspired by (and tests) PR#12. The interesting aspect of
* this is the multiply in the parameter passed to module foo instance yak.
*/
`define ONE 1
`define TWO 2
module foo(in,out);
parameter blah = 2;
input in;
output out;
initial begin
if (blah != 4) begin
$display("FAILED -- parameter override of blah failed: %d", blah);
$finish;
end
$display("PASSED");
end
endmodule
module bar;
foo #(`ONE * 2 + `TWO) yak (,);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int inf = 1e9 + 9; const long long MOD = 1e9 + 696969; const long long INF = 1e18; int n, m, k, a, b, c, w, h; char s[1000100]; int dp[1000100][26], last[1000100][26]; pair<int, int> SECOND, MIN; inline pair<int, int> minexc(int x) { if (x != MIN.second) return MIN; return SECOND; } char ret[1000100]; int main() { scanf( %d%d , &n, &k) ?: 0; scanf( %s , s + 1) ?: 0; for (int i = 1; i <= n; ++i) for (int j = 0; j < k; ++j) dp[i][j] = inf; MIN = {0, -1}; SECOND = {0, 0}; for (int i = 1; i <= n; ++i) { for (int j = 0; j < k; ++j) if (s[i] == (char)j + A ) { dp[i][j] = minexc(j).first; last[i][j] = minexc(j).second; } else dp[i][j] = minexc(j).first + 1, last[i][j] = minexc(j).second; MIN = {inf, inf}; SECOND = {inf, inf}; for (int j = 0; j < k; ++j) if (dp[i][j] < MIN.first) { SECOND = MIN; MIN = make_pair(dp[i][j], j); } else if (dp[i][j] < SECOND.first) SECOND = make_pair(dp[i][j], j); } int res = inf, poz = inf; for (int i = 0; i < k; ++i) if (dp[n][i] < res) res = dp[n][i], poz = i; cout << res << endl; if (res == 0) { for (int i = 1; i <= n; ++i) printf( %c , s[i]); exit(0); } for (int i = n; i > 0; --i) { ret[i] = poz + A ; poz = last[i][poz]; } for (int i = 1; i <= n; ++i) printf( %c , ret[i]); } |
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const long long mod = 1e9 + 7; int main() { cin.tie(0); ios_base::sync_with_stdio(0); unsigned long long n; cin >> n; unsigned long long c = 2 * 3 * 4 * 5 * 7 * 3; if (c > n) { cout << 0 n ; return 0; } cout << n / c << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlygate4s50 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int nm = 100002; int n, d; long long x; int a[nm], b[nm], vt[nm]; int c[nm]; int nc; int getNextX() { x = (x * 37 + 10007) % 1000000007; return x; } void init() { int i; for (i = 0; i < n; i = i + 1) { a[i] = i + 1; } for (i = 0; i < n; i = i + 1) { swap(a[i], a[getNextX() % (i + 1)]); } for (i = 0; i < n; i = i + 1) { if (i < d) b[i] = 1; else b[i] = 0; } for (i = 0; i < n; i = i + 1) { swap(b[i], b[getNextX() % (i + 1)]); } } int main() { scanf( %d%d%I64d , &n, &d, &x); init(); int i, j, k; for (i = 0; i < n; ++i) { vt[a[i]] = i; if (b[i]) c[++nc] = i; } for (i = 0; i < n; ++i) { for (j = n; j > n - 100 && j > 0; --j) if (vt[j] <= i && b[i - vt[j]]) break; if (j > n - 100 && j > 0) { printf( %d n , j); continue; } k = 0; for (j = 1; j <= nc && c[j] <= i; ++j) k = max(k, a[i - c[j]]); printf( %d n , k); } } |
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "decoder4to16.v"
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [14:0] c;
// Output of stage 2
wire [15:1] err;
wire [14:0] cx;
// Output of stage 3
wire [10:0] q;
wire [10:0] qx;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [10:0] b;
reg [10:0] r_b;
reg [3:0] e;
reg [3:0] r_e;
// 2nd stage
reg [14:0] r_c;
reg [3:0] rr_e;
reg [10:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [14:0] r_qx;
reg [10:0] rb;
reg clk,reset;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
decoder4to16 dec4to16 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_e,err);
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,err,cx);
parity_stripper ps (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,qx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
r_qx<=0;
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_0_V
`define SKY130_FD_SC_LP__O311A_0_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_0 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_0_V
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef vector<int> vi; typedef vector<int> vll; typedef pair<int, int> pii; #define F first #define S second #define PB push_back #define MP make_pair #define ALL(v) v.begin(), v.end() #define rALL(v) v.rbegin(), v.rend() #define INF 1000000007LL #define MOD 998244353LL const int LIM = 2e5 + 5; void solve() { int n, x, f, res = 0; cin >> n; for(int i = 0; i < n; i++) { cin >> x; f = 0; for(int j = 1; j * j <= x; j++) if(j * j == x) { f = 1; break; } if(f == 0) res = 1; } if(res) cout << YES n ; else cout << NO n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; string s, ans; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; cin.ignore(numeric_limits<streamsize>::max(), n ); cin >> s; bool flag = true; int cnt = 0, max_cnt = 0; for (int i = 0; i < n - 1; ++i) { string sub = s.substr(i, 2); cnt = 0; for (int j = 0; j < n - 1; ++j) { flag = true; for (int k = 0; k < 2; ++k) { if (sub[k] != s[j + k]) flag = false; } if (flag) ++cnt; if (cnt > max_cnt) { max_cnt = cnt; ans = sub; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, z, p, i, j, k, ans, t, a[105], b[105], d[105], f[105][10005]; bool cmp(int x, int y) { return x > y; } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]), z += a[i]; for (i = 1; i <= n; i++) scanf( %d , &b[i]), d[i] = b[i]; sort(d + 1, d + n + 1, cmp); memset(f, 0x80, sizeof(f)); f[0][0] = 0; for (i = 1; i <= n; i++) { p += d[i]; if (p >= z) { ans = i; break; } } for (i = 1; i <= n; i++) for (j = p; j >= b[i]; j--) for (k = 1; k <= ans; k++) f[k][j] = max(f[k][j], f[k - 1][j - b[i]] + a[i]); for (i = z; i <= p; i++) t = max(t, f[ans][i]); printf( %d %d , ans, z - t); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; int n, m, q[N], a[N]; int main() { scanf( %d , &m); for (int i = (0); i < (m); ++i) scanf( %d , &q[i]); int mn = *min_element(q, q + m); scanf( %d , &n); for (int i = (0); i < (n); ++i) scanf( %d , &a[i]); sort(a, a + n); int ans = 0; for (int i = n - 1, c = 0; i >= 0; --i) { ans += a[i], ++c; if (c >= mn) c = 0, i -= 2; } printf( %d , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLXBP_PP_SYMBOL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a, b, i, x, t, rem; cin >> n >> a >> b; for (i = 0; i < n; i++) { cin >> x; t = (x * a) % b; if (t / a >= 1) rem = t / a; else rem = 0; cout << rem << ; } return 0; } |
#include <bits/stdc++.h> int n; int main() { int i; long long ans, sumx, sumy, x, y; scanf( %d , &n); ans = sumx = sumy = 0; for (i = 0; i < n; i++) { scanf( %I64d%I64d , &x, &y); ans += (long long)x * x * n + y * y * n; sumx += x; sumy += y; } printf( %I64d , ans - sumx * sumx - sumy * sumy); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V |
`default_nettype none
module pipeline_control_hundler_read(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//System Register
input wire [31:0] iSYSREG_IDTR,
//Request
input wire iRD_START,
input wire [6:0] iRD_IRQ_NUM,
output wire oRD_FINISH,
output wire [31:0] oRD_HUNDLER,
//Load Store
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_ASID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA
);
localparam L_PARAM_INTHUNDLE_STT_IDLE = 1'b0;
localparam L_PARAM_INTHUNDLE_STT_LOAD = 1'b1;
reg b_inthundl_read_state;
reg b_inthundl_read;
reg b_inthundl_readend;
reg [31:0] b_inthundl_idt_data;
wire [31:0] inthundle_read_addr = iSYSREG_IDTR + {iRD_IRQ_NUM, 3'h0} + 32'h4;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_IDLE;
b_inthundl_read <= 1'b0;
b_inthundl_readend <= 1'b0;
b_inthundl_idt_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_IDLE;
b_inthundl_read <= 1'b0;
b_inthundl_readend <= 1'b0;
b_inthundl_idt_data <= 32'h0;
end
else begin
case(b_inthundl_read_state)
L_PARAM_INTHUNDLE_STT_IDLE:
begin
if(iRD_START)begin
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_LOAD;
b_inthundl_read <= 1'b1;
end
else begin
b_inthundl_read <= 1'b0;
end
b_inthundl_readend <= 1'b0;
end
L_PARAM_INTHUNDLE_STT_LOAD:
begin
//Read Request
if(!iLDST_BUSY && b_inthundl_read)begin
b_inthundl_read <= 1'b0;
end
//Get Check
if(iLDST_REQ)begin
b_inthundl_readend <= 1'b1;
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_IDLE;
b_inthundl_idt_data <= iLDST_DATA;
end
end
endcase
end
end
assign oRD_FINISH = b_inthundl_readend;
assign oRD_HUNDLER = b_inthundl_idt_data;
assign oLDST_USE = b_inthundl_read_state == L_PARAM_INTHUNDLE_STT_LOAD;
assign oLDST_REQ = b_inthundl_read;
assign oLDST_ORDER = 2'h2; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
assign oLDST_RW = 1'b0; //0=Read 1=Write
assign oLDST_ASID = 14'h0;
assign oLDST_MMUMOD = 2'h0;
assign oLDST_PDT = 32'h0;
assign oLDST_ADDR = inthundle_read_addr;
assign oLDST_DATA = 32'h0;
endmodule
`default_nettype wire |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sample_iterator_get_offset (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
i_index,
i_sample,
indices_req_din,
indices_req_full_n,
indices_req_write,
indices_rsp_empty_n,
indices_rsp_read,
indices_address,
indices_datain,
indices_dataout,
indices_size,
sample_buffer_size,
sample_length,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 2'b00;
parameter ap_ST_st2_fsm_1 = 2'b1;
parameter ap_ST_st3_fsm_2 = 2'b10;
parameter ap_ST_st4_fsm_3 = 2'b11;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_30 = 32'b110000;
parameter ap_const_lv32_37 = 32'b110111;
parameter ap_const_lv56_0 = 56'b00000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [15:0] i_index;
input [15:0] i_sample;
output indices_req_din;
input indices_req_full_n;
output indices_req_write;
input indices_rsp_empty_n;
output indices_rsp_read;
output [31:0] indices_address;
input [55:0] indices_datain;
output [55:0] indices_dataout;
output [31:0] indices_size;
input [31:0] sample_buffer_size;
input [15:0] sample_length;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg indices_req_write;
reg indices_rsp_read;
reg [1:0] ap_CS_fsm = 2'b00;
wire [31:0] tmp_4_fu_92_p1;
reg [31:0] tmp_4_reg_134;
reg [7:0] indices_stride_load_new_reg_139;
wire [63:0] tmp_fu_81_p1;
wire [15:0] tmp_s_fu_113_p0;
wire [7:0] tmp_s_fu_113_p1;
wire [23:0] tmp_s_fu_113_p2;
wire [31:0] tmp_17_cast_fu_119_p1;
reg [1:0] ap_NS_fsm;
wire [23:0] tmp_s_fu_113_p00;
wire [23:0] tmp_s_fu_113_p10;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st3_fsm_2 == ap_CS_fsm) & ~(indices_rsp_empty_n == ap_const_logic_0))) begin
indices_stride_load_new_reg_139 <= {{indices_datain[ap_const_lv32_37 : ap_const_lv32_30]}};
tmp_4_reg_134 <= tmp_4_fu_92_p1;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm)) | (ap_ST_st4_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// indices_req_write assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
indices_req_write = ap_const_logic_1;
end else begin
indices_req_write = ap_const_logic_0;
end
end
/// indices_rsp_read assign process. ///
always @ (ap_CS_fsm or indices_rsp_empty_n)
begin
if (((ap_ST_st3_fsm_2 == ap_CS_fsm) & ~(indices_rsp_empty_n == ap_const_logic_0))) begin
indices_rsp_read = ap_const_logic_1;
end else begin
indices_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or indices_rsp_empty_n)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
ap_ST_st2_fsm_1 :
ap_NS_fsm = ap_ST_st3_fsm_2;
ap_ST_st3_fsm_2 :
if (~(indices_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
ap_ST_st4_fsm_3 :
ap_NS_fsm = ap_ST_st1_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign ap_return = (tmp_17_cast_fu_119_p1 + tmp_4_reg_134);
assign indices_address = tmp_fu_81_p1;
assign indices_dataout = ap_const_lv56_0;
assign indices_req_din = ap_const_logic_0;
assign indices_size = ap_const_lv32_1;
assign tmp_17_cast_fu_119_p1 = $unsigned(tmp_s_fu_113_p2);
assign tmp_4_fu_92_p1 = indices_datain[31:0];
assign tmp_fu_81_p1 = $unsigned(i_index);
assign tmp_s_fu_113_p0 = tmp_s_fu_113_p00;
assign tmp_s_fu_113_p00 = $unsigned(i_sample);
assign tmp_s_fu_113_p1 = tmp_s_fu_113_p10;
assign tmp_s_fu_113_p10 = $unsigned(indices_stride_load_new_reg_139);
assign tmp_s_fu_113_p2 = ($signed({{1'b0}, {tmp_s_fu_113_p0}}) * $signed({{1'b0}, {tmp_s_fu_113_p1}}));
endmodule //sample_iterator_get_offset
|
#include <bits/stdc++.h> using namespace std; int a[1000000], g[1000000], h[1000000]; int d[1000000]; int dp[1000000]; int up[1000000]; int h1[1000000]; int h2[1000000]; int t1[1000000]; int t2[1000000]; vector<int> v[1000000]; int x, y, n, m; int maxy, one_kek, two_kek; void dfs(int x, int pr = -1) { h[x] = 1; d[x] = g[x]; h1[x] = 0; h2[x] = 0; t1[x] = 0; t2[x] = 0; for (int i = 0; i < v[x].size(); i++) { int to = v[x][i]; if (to == pr) continue; dfs(to, x); if (d[to] == 0) continue; d[x] += d[to]; h[x] += h[to]; if (1 + h1[to] > h2[x]) { h2[x] = 1 + h1[to]; t2[x] = to; if (h2[x] > h1[x]) { swap(h1[x], h2[x]); swap(t1[x], t2[x]); } } } if (d[x] == 0) return; } void dfs1(int x, int pr = -1) { if (d[x] == 0) return; if (pr == -1) dp[x] = h1[x]; else { if (t1[pr] == x) up[x] = 1 + max(up[pr], h2[pr]); else up[x] = 1 + max(up[pr], h1[pr]); dp[x] = max(h1[x], up[x]); } for (int i = 0; i < v[x].size(); i++) { int to = v[x][i]; if (to == pr) continue; dfs1(to, x); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 1; i < n; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } for (int i = 1; i <= m; i++) { cin >> a[i]; g[a[i]]++; } if (m == 1) { cout << a[1] << n << 0; return 0; } dfs(a[1]); dfs1(a[1]); for (int i = 1; i <= m; i++) { if (dp[a[i]] > maxy) { maxy = dp[a[i]]; one_kek = a[i]; } else if (dp[a[i]] == maxy) one_kek = min(one_kek, a[i]); } cout << one_kek << n << h[a[1]] * 2 - 2 - maxy << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
|
`include "timescale.v"
`include "i2c_master_defines.v"
module opencores_i2c
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
write_n, read_n, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input write_n;
input read_n;
//input wb_we_i; // WISHBONE write enable input
//input wb_stb_i; // WISHBONE strobe input
input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
// Wire wb_stb_i and wb_we_i;
wire write_n;
wire read_n;
wire wb_we_i;
wire wb_stb_i;
assign wb_we_i = !write_n | read_n;
assign wb_stb_i = !write_n | !read_n;
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
Require Import Iron.Language.SystemF2Effect.Value.Relation.TyJudge.
(* Uniqueness of typing.
Checking an expression always returns a unique type an effect. *)
Lemma typex_unique
: forall ke te se sp x t1 e1 t2 e2
, TypeX ke te se sp x t1 e1
-> TypeX ke te se sp x t2 e2
-> t1 = t2 /\ e1 = e2.
Proof.
intros. gen ke te se sp t1 e1 t2 e2.
induction x using exp_mutind with
(PV := fun v1 => forall ke te se sp t1 t1'
, TypeV ke te se sp v1 t1
-> TypeV ke te se sp v1 t1'
-> t1 = t1');
intros;
try (solve [inverts_type; try congruence]);
inverts_type; auto.
- Case "VLam".
spec IHx H9 H10.
burn.
- Case "VLAM".
spec IHx H8 H7.
burn.
- Case "XVal".
spec IHx H6 H5.
burn.
- Case "XLet".
spec IHx1 H11 H13.
spec IHx2 H12 H14.
rip.
- Case "XApp".
spec IHx H7 H6.
spec IHx0 H10 H11.
subst. inverts IHx. auto.
- Case "VAPP".
spec IHx H7 H6.
inverts IHx. auto.
- Case "XOp1".
spec IHx H10 H11.
subst.
rip; congruence.
- Case "XPrivate".
spec IHx H8 H10.
rip; congruence.
- Case "XExtend".
spec IHx H11 H13.
rip; congruence.
- Case "XAlloc".
spec IHx H10 H11.
subst. burn.
- Case "XRead".
spec IHx H10 H11.
inverts IHx. auto.
Qed.
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { cin.sync_with_stdio(0); cout.sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, r[100], b[100], sumr, sumb, ans = 1, check = 1; cin >> n; for (int i = 0; i < n; i++) cin >> r[i]; for (int i = 0; i < n; i++) cin >> b[i]; sumr = accumulate(r, r + n, 0); sumb = accumulate(b, b + n, 0); if ((sumr == sumb && sumb == 0) || (sumr == sumb && sumb == n)) { cout << -1; return 0; } if (sumr > sumb) { cout << 1; return 0; } for (int i = 0; i < n; i++) if (r[i] && !b[i]) { check = 0; break; } if (check) { cout << -1; return 0; } RELOOP:; ans++; for (int i = 0; i < n; i++) if (r[i] && !b[i]) sumr++; if (sumr <= sumb) goto RELOOP; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i; int n, m1; cin >> n >> m1; int a[n + 1]; for (i = 1; i <= n; i++) cin >> a[i]; int t, r; stack<pair<int, int> > s; pair<int, int> use; for (i = 1; i <= m1; i++) { cin >> t >> r; while (!s.empty() && (s.top().second <= (r))) { s.pop(); } if (!s.empty() && (s.top().second > r && s.top().first == t)) continue; s.push(make_pair(t, r)); } int prev = 0; vector<pair<int, int> > m; while (!s.empty()) { m.push_back(s.top()); s.pop(); } int size = m.size(); set<pair<int, int> > s1, s2; for (i = 1; i <= m[size - 1].second; i++) { s1.insert(make_pair(-a[i], i)); s2.insert(make_pair(a[i], i)); } int r_end; pair<int, int> num; for (i = size - 1; i >= 0; i--) { r = m[i].second; if (i) r_end = m[i - 1].second; else r_end = 0; t = m[i].first; if (t == 1) { for (int j = r; j > r_end; j--) { num = *(s1.begin()); s1.erase(num); s2.erase(make_pair(-num.first, num.second)); a[j] = -num.first; } } else { for (int j = r; j > r_end; j--) { num = *(s2.begin()); s2.erase(num); s1.erase(make_pair(-num.first, num.second)); a[j] = num.first; } } } for (i = 1; i <= n; i++) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> int sg[100010], f[100010], pre[100010]; int used[100010]; int n; int cal(int n) { for (int m = 2;; m++) { int tot = m * (m - 1) / 2; if (tot > n) break; tot = n - tot; if (tot % m) continue; int s = tot / m; int t = s + m - 1; int v = sg[t] ^ sg[s - 1]; used[v] = n; if (v == 0 && pre[n] == 0) pre[n] = m; } int ret = 0; for (; used[ret] == n; ret++) ; return ret; } int main() { int i, j, k; scanf( %d , &n); for (i = 3; i <= n; i++) { f[i] = cal(i); sg[i] = sg[i - 1] ^ f[i]; } if (f[n]) printf( %d n , pre[n]); else puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; #define N 200020 int cnt, last[N], n, ans; struct edge { int to, next; } e[N << 1]; inline void add(int u, int v) { e[++cnt] = {v, last[u]}, last[u] = cnt; e[++cnt] = {u, last[v]}, last[v] = cnt; } int dfs(int x, int fa) { vector<pair<int, int> > q; q.clear(); for (int i = last[x]; i; i = e[i].next) { int y = e[i].to; if (y == fa)continue; q.push_back({dfs(y, x), y}); } if (!q.size())return 0; sort(q.begin(), q.end()); for (int i = 1; i < q.size(); ++i) { ans = max(q[i - (x == 1)].first + 2, ans); } return q[(q.size() - 1) * (x == 1)].first + 1; } inline void solve() { scanf( %d , &n); for (int i = 1; i <= n; ++i)last[i] = 0; cnt = 0; for (int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); add(u, v); } ans = 0; ans = max(ans, dfs(1, 0)); printf( %d n , ans); } int main() { int T = 1; scanf( %d , &T); for (int i = 1; i <= T; ++i)solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; string Decod, s; cin >> n >> s; int i = 0; while (n) { if (n % 2 != 0) { Decod += s[i]; } else { Decod = s[i] + Decod; } n = n - 1; i++; } cout << Decod << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_2_V
`define SKY130_FD_SC_HDLL__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_2_V
|
#include <bits/stdc++.h> #pragma warning(disable : 4786) #pragma comment(linker, /STACK:16777216 ) using namespace std; int A[100005]; int I[100005]; int D[100005]; int n; int max(int a, int b) { if (a > b) return a; return b; } int ABS(int a) { if (a < 0) return a = a * -1; return a; } int main() { int i, j, len, res, cur, res1; while (scanf( %d , &n) != EOF) { for (i = 0; i < n; i++) { scanf( %d , &A[i]); } I[0] = 1; for (i = 1; i < n; i++) { if (A[i] > A[i - 1]) { I[i] = I[i - 1] + 1; } else { I[i] = 1; } } D[n - 1] = 1; for (i = n - 1; i >= 0; i--) { if (A[i] < A[i + 1]) { D[i] = D[i + 1] + 1; } else { D[i] = 1; } } res = 1; for (i = 0; i < n; i++) { if (i == 0) { if (i + 1 < n) res = max(res, D[i + 1] + 1); } else if (i == n - 1) { if (i - 1 >= 0) res = max(res, I[i - 1] + 1); } else { int r = I[i - 1] + D[i + 1]; if (ABS(A[i - 1] - A[i + 1]) > 1 && A[i + 1] > A[i - 1]) { res = max(res, r + 1); } res = max(res, I[i - 1] + 1); res = max(res, D[i + 1] + 1); } } printf( %d n , res); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : HPIO_VREF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HPIO_VREF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter VREF_CNTR = "OFF"
)(
output VREF,
input [6:0] FABRIC_VREF_TUNE
);
// define constants
localparam MODULE_NAME = "HPIO_VREF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam VREF_CNTR_FABRIC_RANGE1 = 1;
localparam VREF_CNTR_FABRIC_RANGE2 = 2;
localparam VREF_CNTR_OFF = 0;
localparam [104:1] VREF_CNTR_REG = VREF_CNTR;
wire [1:0] VREF_CNTR_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire VREF_out = 1'b1;
wire VREF_delay;
wire [6:0] FABRIC_VREF_TUNE_in;
wire [6:0] FABRIC_VREF_TUNE_delay;
assign #(out_delay) VREF = VREF_delay;
// inputs with no timing checks
assign #(in_delay) FABRIC_VREF_TUNE_delay = FABRIC_VREF_TUNE;
assign VREF_delay = VREF_out;
assign FABRIC_VREF_TUNE_in = FABRIC_VREF_TUNE_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((VREF_CNTR_REG != "OFF") &&
(VREF_CNTR_REG != "FABRIC_RANGE1") &&
(VREF_CNTR_REG != "FABRIC_RANGE2"))) begin
$display("Error: [Unisim %s-101] VREF_CNTR attribute is set to %s. Legal values for this attribute are OFF, FABRIC_RANGE1 or FABRIC_RANGE2. Instance: %m", MODULE_NAME, VREF_CNTR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign VREF_CNTR_BIN =
(VREF_CNTR_REG == "OFF") ? VREF_CNTR_OFF :
(VREF_CNTR_REG == "FABRIC_RANGE1") ? VREF_CNTR_FABRIC_RANGE1 :
(VREF_CNTR_REG == "FABRIC_RANGE2") ? VREF_CNTR_FABRIC_RANGE2 :
VREF_CNTR_OFF;
always @ (FABRIC_VREF_TUNE_in) begin
$display("Info: [Unisim %s-1] Fabric Tune Value changed to %b. Instance: %m",MODULE_NAME, FABRIC_VREF_TUNE_in);
end
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n; cin >> n >> m; int flag = 0, j, i; for (i = n + 1; i <= m; i++) { flag = 0; for (j = 2; j * j <= i; j++) { if (i % j == 0) { flag = 1; break; } } if (flag == 0) { break; } } if (i != m) cout << NO ; else cout << YES ; return 0; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
module processing_system7_bfm_v2_0_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr <= 0;
rd_ptr <= 0;
state <= 0;
invalid_rd <= 0;
end else begin
case (state)
0 : begin
state <= 0;
invalid_rd <= 0;
if(req)begin
state <= 1;
invalid_rd <= invalid_rd_req;
end
end
1 : begin
state <= 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] <= 0;
else
wr_ptr <= wr_ptr + 1;
state <= 0;
invalid_rd <= 0;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int h, w; int get(int x, int y) { if (!y) return x; if (x == h) return h + y; if (y == w) return h + w + (h - x); return h + w + h + (w - y); } vector<pair<long long, long long> > get(int h, int w, int x, int a, int b) { vector<pair<long long, long long> > ans; if (a <= 0 && b <= 0) return ans; if (a >= w && b >= w) return ans; if (x >= h || x <= 0) return ans; if (a > 0 && a < w && b > 0 && b < w) return ans; int fl = 0; if (a > b) swap(a, b), fl = 1; if (a <= 0 && b >= w) { ans.push_back(pair<long long, long long>(x, 0)); ans.push_back(pair<long long, long long>(x, w)); } else if (a > 0) ans.push_back(pair<long long, long long>(x, w)); else ans.push_back(pair<long long, long long>(x, 0)); if (fl) reverse(ans.begin(), ans.end()); return ans; } int x[120005], y[120005]; bool vis[120005]; vector<int> e[120005]; void add(int x, int y) { e[x].push_back(y); e[y].push_back(x); } void dfs(int x) { vis[x] = 1; for (int i = 0; i < e[x].size(); i++) if (!vis[e[x][i]]) dfs(e[x][i]); } int main() { int x1, x2, y1, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); swap(y1, y2); x1 *= 2; x2 *= 2; y1 *= 2; y2 *= 2; h = x2 - x1, w = y2 - y1; int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d%d , &x[i], &y[i]); x[i] *= 2; y[i] *= 2; x[i] -= x1; y[i] -= y1; } int fl = 0; for (int i = 0; i < n; i++) if (x[i] < 0 || y[i] < 0 || x[i] > h || y[i] > w) { rotate(x, x + i, x + n); rotate(y, y + i, y + n); fl = 1; break; } if (!fl) return puts( 1 ), 0; x[n] = x[0]; y[n] = y[0]; int cnt = 0; vector<pair<long long, int> > vec; for (int i = 0; i < n; i++) if (x[i] == x[i + 1]) { vector<pair<long long, long long> > tmp = get(h, w, x[i], y[i], y[i + 1]); for (int j = 0; j < tmp.size(); j++) vec.push_back( pair<long long, int>(get(tmp[j].first, tmp[j].second), cnt++)); } else { vector<pair<long long, long long> > tmp = get(w, h, y[i], x[i], x[i + 1]); for (int j = 0; j < tmp.size(); j++) vec.push_back( pair<long long, int>(get(tmp[j].second, tmp[j].first), cnt++)); } if (!vec.size()) { int a = h / 2, b = w / 2; double ang = 0; for (int i = 0; i < n; i++) ang += atan2((x[i] - a) * (y[i + 1] - b) - (y[i] - b) * (x[i + 1] - a), (x[i] - a) * (x[i + 1] - a) + (y[i] - b) * (y[i + 1] - b)); printf( %d , abs(ang) <= 1 ? 0 : 1); return 0; } for (int i = 0; i < vec.size(); i += 2) add(vec[i].second, vec[i + 1].second); sort(vec.begin(), vec.end()); for (int i = 0; i < vec.size(); i++) if (vec[i].second == 0) { rotate(vec.begin(), vec.begin() + i, vec.end()); break; } rotate(vec.begin(), vec.begin() + 1, vec.end()); for (int i = 0; i < vec.size(); i += 2) add(vec[i].second, vec[i + 1].second); int ans = 0; for (int i = 0; i < cnt; i++) if (!vis[i]) dfs(i), ans++; printf( %d , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_TB_V
`define SKY130_FD_SC_HDLL__MUX2I_TB_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2i.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_hdll__mux2i dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_TB_V
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97 #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input ac97_clk,
input ac97_rst_n,
/* Codec interface */
input ac97_sin,
output ac97_sout,
output ac97_sync,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Interrupts */
output crrequest_irq,
output crreply_irq,
output dmar_irq,
output dmaw_irq,
/* DMA */
output [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
output [31:0] wbm_dat_o
);
wire up_stb;
wire up_ack;
wire up_sync;
wire up_sdata;
wire down_ready;
wire down_stb;
wire down_sync;
wire down_sdata;
ac97_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ac97_clk(ac97_clk),
.ac97_rst_n(ac97_rst_n),
.ac97_sin(ac97_sin),
.ac97_sout(ac97_sout),
.ac97_sync(ac97_sync),
.up_stb(up_stb),
.up_ack(up_ack),
.up_sync(up_sync),
.up_data(up_sdata),
.down_ready(down_ready),
.down_stb(down_stb),
.down_sync(down_sync),
.down_data(down_sdata)
);
wire down_en;
wire down_next_frame;
wire down_addr_valid;
wire [19:0] down_addr;
wire down_data_valid;
wire [19:0] down_data;
wire down_pcmleft_valid;
wire [19:0] down_pcmleft;
wire down_pcmright_valid;
wire [19:0] down_pcmright;
ac97_framer framer(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
/* to transceiver */
.down_ready(down_ready),
.down_stb(down_stb),
.down_sync(down_sync),
.down_data(down_sdata),
/* frame data */
.en(down_en),
.next_frame(down_next_frame),
.addr_valid(down_addr_valid),
.addr(down_addr),
.data_valid(down_data_valid),
.data(down_data),
.pcmleft_valid(down_pcmleft_valid),
.pcmleft(down_pcmleft),
.pcmright_valid(down_pcmright_valid),
.pcmright(down_pcmright)
);
wire up_en;
wire up_next_frame;
wire up_frame_valid;
wire up_addr_valid;
wire [19:0] up_addr;
wire up_data_valid;
wire [19:0] up_data;
wire up_pcmleft_valid;
wire [19:0] up_pcmleft;
wire up_pcmright_valid;
wire [19:0] up_pcmright;
ac97_deframer deframer(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.up_stb(up_stb),
.up_ack(up_ack),
.up_sync(up_sync),
.up_data(up_sdata),
.en(up_en),
.next_frame(up_next_frame),
.frame_valid(up_frame_valid),
.addr_valid(up_addr_valid),
.addr(up_addr),
.data_valid(up_data_valid),
.data(up_data),
.pcmleft_valid(up_pcmleft_valid),
.pcmleft(up_pcmleft),
.pcmright_valid(up_pcmright_valid),
.pcmright(up_pcmright)
);
wire dmar_en;
wire [29:0] dmar_addr;
wire [15:0] dmar_remaining;
wire dmar_next;
wire dmaw_en;
wire [29:0] dmaw_addr;
wire [15:0] dmaw_remaining;
wire dmaw_next;
ac97_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.crrequest_irq(crrequest_irq),
.crreply_irq(crreply_irq),
.dmar_irq(dmar_irq),
.dmaw_irq(dmaw_irq),
.down_en(down_en),
.down_next_frame(down_next_frame),
.down_addr_valid(down_addr_valid),
.down_addr(down_addr),
.down_data_valid(down_data_valid),
.down_data(down_data),
.up_en(up_en),
.up_next_frame(up_next_frame),
.up_frame_valid(up_frame_valid),
.up_addr_valid(up_addr_valid),
.up_addr(up_addr),
.up_data_valid(up_data_valid),
.up_data(up_data),
.dmar_en(dmar_en),
.dmar_addr(dmar_addr),
.dmar_remaining(dmar_remaining),
.dmar_next(dmar_next),
.dmaw_en(dmaw_en),
.dmaw_addr(dmaw_addr),
.dmaw_remaining(dmaw_remaining),
.dmaw_next(dmaw_next)
);
ac97_dma dma(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wbm_adr_o(wbm_adr_o),
.wbm_cti_o(wbm_cti_o),
.wbm_we_o(wbm_we_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.down_en(down_en),
.down_next_frame(down_next_frame),
.down_pcmleft_valid(down_pcmleft_valid),
.down_pcmleft(down_pcmleft),
.down_pcmright_valid(down_pcmright_valid),
.down_pcmright(down_pcmright),
.up_en(up_en),
.up_next_frame(up_next_frame),
.up_frame_valid(up_frame_valid),
.up_pcmleft_valid(up_pcmleft_valid),
.up_pcmleft(up_pcmleft),
.up_pcmright_valid(up_pcmright_valid),
.up_pcmright(up_pcmright),
.dmar_en(dmar_en),
.dmar_addr(dmar_addr),
.dmar_remaining(dmar_remaining),
.dmar_next(dmar_next),
.dmaw_en(dmaw_en),
.dmaw_addr(dmaw_addr),
.dmaw_remaining(dmaw_remaining),
.dmaw_next(dmaw_next)
);
endmodule
|
`timescale 1ns/1ps
module SPIFSM #(
parameter SPPRWidth = 4,
parameter SPRWidth = 4,
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// FSM control
input Start_i,
output reg Done_o,
output reg [DataWidth-1:0] Byte0_o,
output reg [DataWidth-1:0] Byte1_o,
// to/from SPI_Master
input SPI_Transmission_i,
output reg SPI_Write_o,
output reg SPI_ReadNext_o,
output reg [DataWidth-1:0] SPI_Data_o,
input [DataWidth-1:0] SPI_Data_i,
input SPI_FIFOFull_i,
input SPI_FIFOEmpty_i,
// to ADT7310
output reg ADT7310CS_n_o,
// parameters
input [31:0] ParamCounterPreset_i
);
// SPI FSM
localparam stIdle = 4'b0000;
localparam stWriteValue = 4'b0001;
localparam stWaitSent = 4'b0010;
localparam stConsume1 = 4'b0011;
localparam stWait = 4'b0100;
localparam stWriteDummy1= 4'b0101;
localparam stWriteDummy2= 4'b0110;
localparam stRead1 = 4'b0111;
localparam stRead2 = 4'b1000;
localparam stRead3 = 4'b1001;
localparam stPause = 4'b1010;
reg [3:0] SPI_FSM_State;
reg [3:0] SPI_FSM_NextState;
wire SPI_FSM_TimerOvfl;
reg SPI_FSM_TimerPreset;
reg SPI_FSM_TimerEnable;
reg SPI_FSM_Wr1;
reg SPI_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_State <= stIdle;
end
else
begin
SPI_FSM_State <= SPI_FSM_NextState;
end
end
always @(SPI_FSM_State, Start_i, SPI_Transmission_i, SPI_FSM_TimerOvfl)
begin // process SPI_FSM_CombProc
SPI_FSM_NextState = SPI_FSM_State;
// control signal default values
ADT7310CS_n_o = 1'b1;
SPI_Data_o = 8'bxxxxxxxx; // most time we don't care which value is set
SPI_Write_o = 1'b0;
SPI_ReadNext_o = 1'b0;
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b0;
SPI_FSM_Wr1 = 1'b0;
SPI_FSM_Wr0 = 1'b0;
Done_o = 1'b1;
// next state and output logic
case (SPI_FSM_State)
stIdle: begin
if (Start_i == 1'b1)
begin
// single-shot measurement mode: write to 8-bit configuration
// register (0x01): send 0x08 0x20 (one shot mode)
SPI_FSM_NextState = stWriteValue;
ADT7310CS_n_o = 1'b0;
SPI_Data_o = 8'h08;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
end
stWriteValue: begin
SPI_FSM_NextState = stWaitSent;
ADT7310CS_n_o = 1'b0;
// send 0x20
SPI_Data_o = 8'h20;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
stWaitSent: begin
// wait until SPI transmission has finished
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
if (SPI_Transmission_i == 1'b0)
begin
SPI_FSM_NextState = stConsume1;
SPI_ReadNext_o = 1'b1; // consume first received value
SPI_FSM_TimerPreset = 1'b1;
end
end
stConsume1: begin
SPI_FSM_NextState = stWait;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_ReadNext_o = 1'b1; // consume second received value
SPI_FSM_TimerEnable = 1'b1; // start timer
end
stWait: begin
// wait for 240ms
ADT7310CS_n_o = 1'b1;
Done_o = 1'b0;
if (SPI_FSM_TimerOvfl == 1'b0)
begin
SPI_FSM_TimerEnable = 1'b1; // timer running
end
else
begin
// timer overflow -> continue: send read command and two dummy bytes
ADT7310CS_n_o = 1'b0;
SPI_FSM_NextState = stWriteDummy1;
SPI_Data_o = 8'h50;
SPI_Write_o = 1'b1;
end
end
stWriteDummy1: begin
SPI_FSM_NextState = stWriteDummy2;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stWriteDummy2: begin
SPI_FSM_NextState = stRead1;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stRead1: begin
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
// wait until SPI transmission has finished
if (SPI_Transmission_i == 1'b0) begin
SPI_FSM_NextState = stRead2;
// consume and ignore first byte
SPI_ReadNext_o = 1'b1;
end
end
stRead2: begin
Done_o = 1'b0;
// consume and store second byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr1 = 1'b1;
SPI_FSM_NextState = stRead3;
end
stRead3: begin
Done_o = 1'b0;
// consume and store third byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr0 = 1'b1;
SPI_FSM_NextState = stPause;
end
stPause: begin
SPI_FSM_NextState = stIdle;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0_o <= 8'd0;
Byte1_o <= 8'd0;
end
else
begin
if (SPI_FSM_Wr0)
begin
Byte0_o <= SPI_Data_i;
end
if (SPI_FSM_Wr1)
begin
Byte1_o <= SPI_Data_i;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [31:0] SPI_FSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_Timer <= 32'd0;
end
else
begin
if (SPI_FSM_TimerPreset)
begin
SPI_FSM_Timer <= ParamCounterPreset_i;
end
else if (SPI_FSM_TimerEnable)
begin
SPI_FSM_Timer <= SPI_FSM_Timer - 1'b1;
end
end
end
assign SPI_FSM_TimerOvfl = (SPI_FSM_Timer == 0) ? 1'b1 : 1'b0;
endmodule // SPIFSM
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n; cin >> n; char s; long long cnt = 0; while (cin >> s) { cnt += s == 8 ; } long long ans = 0; for (long long i = 0; i <= cnt; ++i) { if (min(i, (n - i) / 10) > ans) ans = min(i, (n - i) / 10); } cout << ans; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Gameover.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Gameover (
address,
clock,
q);
input [11:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Gameover.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2400"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Gameover.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2400"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Gameover_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; class fenwickTree { public: int* tree; int size; int prefixSum(int index) { index++; int ret = 0; while (index > 0) { ret += tree[index]; index -= (index & -index); } return ret; } void update(int index, int delta) { index++; while (index <= size) { tree[index] += delta; index += (index & -index); } } int rangeSum(int left, int right) { return prefixSum(right) - prefixSum(left - 1); } fenwickTree(int n) { size = n; tree = new int[size + 1]; memset(tree, 0, sizeof(int) * (size + 1)); } }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; fenwickTree tree(n + 1); int cts[n + 1]; memset(cts, 0, sizeof cts); long long invert = 0; bool ok = false; for (int i = 0; i < n; i++) { int w; cin >> w; cts[w]++; if (cts[w] == 2) ok = true; tree.update(w, 1); invert += tree.rangeSum(w + 1, n); } if (invert & 1 && !ok) cout << NO n ; else cout << YES n ; } } |
#include <bits/stdc++.h> using namespace std; const int N = 500005; int n, m[N], t[N]; struct People { int a, b, c, cnt; } p[N], ran[N]; int read() { int x = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); return x; } bool cmp(People x, People y) { if (x.a != y.a) return x.a > y.a; else return x.c < y.c; } int lowbit(int x) { return x & -x; } void add(int x, int k) { for (; x <= n; x += lowbit(x)) t[x] += k; return; } int sum(int x) { int ret = 0; for (; x; x -= lowbit(x)) ret += t[x]; return ret; } void merge(int l, int r) { if (l == r) return; int mid = (l + r) / 2; merge(l, mid); merge(mid + 1, r); int i = l, j = mid + 1, cur = l; for (; i <= mid && j <= r;) { if (p[i].b > p[j].b) add(p[i].c, 1), ran[cur++] = p[i++]; else p[j].cnt += sum(n) - sum(p[j].c), ran[cur++] = p[j++]; } for (; i <= mid;) add(p[i].c, 1), ran[cur++] = p[i++]; for (; j <= r;) p[j].cnt += sum(n) - sum(p[j].c), ran[cur++] = p[j++]; for (i = l; i <= mid; ++i) add(p[i].c, -1); for (i = l; i <= r; ++i) p[i] = ran[i]; } int main() { n = read(); for (int i = 1; i <= n; ++i) p[i].a = read(); for (int i = 1; i <= n; ++i) p[i].b = read(); for (int i = 1; i <= n; ++i) p[i].c = read(), m[i] = p[i].c; sort(m + 1, m + 1 + n); for (int i = 1; i <= n; ++i) p[i].c = lower_bound(m + 1, m + 1 + n, p[i].c) - m; sort(p + 1, p + 1 + n, cmp); merge(1, n); int ans = 0; for (int i = 1; i <= n; ++i) if (p[i].cnt) ++ans; printf( %d n , ans); return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
module ramb_8_to_n (clkA,
clkB,
weA,
weB,
addrA,
addrB,
diA,
doA,
diB,
doB);
parameter SIZE = 1024;
parameter WIDTH = 8;
localparam WIDTHA = 8;
localparam SIZEA = SIZE;
localparam ADDRWIDTHA = $clog2(SIZEA);
localparam WIDTHB = WIDTH;
localparam SIZEB = SIZEA*8/WIDTHB;
localparam ADDRWIDTHB = $clog2(SIZEB);
input wire clkA;
input wire clkB;
input wire weA, weB;
input wire [ADDRWIDTHA-1:0] addrA;
input wire [ADDRWIDTHB-1:0] addrB;
input wire [WIDTHA-1:0] diA;
input wire [WIDTHB-1:0] diB;
output reg [WIDTHA-1:0] doA;
output reg [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = $clog2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
// For simualtion init with 0
initial begin : INIT_MEM
integer w;
for (w=0; w < maxSIZE; w=w + 1) begin
RAM[w] = 0;
end
end
generate
if (WIDTH == 8) begin
always @(posedge clkB)
begin
if (weB)
RAM[addrB] <= diB;
doB <= RAM[addrB];
end
always @(posedge clkA) begin : portA
if (weA)
RAM[addrA] <= diA;
doA <= RAM[addrA];
end
end
endgenerate
generate
if (WIDTH < 8) begin
always @(posedge clkB)
begin
if (weB)
RAM[addrB] <= diB;
doB <= RAM[addrB];
end
always @(posedge clkA) begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr ;
for (i = 0; i< RATIO; i = i + 1) begin
lsbaddr = i;
if (weA)
RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
doA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
end
end
end
endgenerate
generate
if (WIDTH > 8) begin
always @(posedge clkA)
begin
if (weA)
RAM[addrA] <= diA;
doA <= RAM[addrA];
end
always @(posedge clkB) begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr ;
for (i = 0; i< RATIO; i = i + 1) begin
lsbaddr = i;
if (weB)
RAM[{addrB, lsbaddr}] <= diB[(i+1)*minWIDTH-1 -: minWIDTH];
doB[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
end
end
end
endgenerate
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate inout with id(a,a) inout a; definition.
module id(a,a);
inout a;
endmodule
module top ();
wire b,c;
id i1(b,c);
reg a, error, ena_a,ena_b;
assign c = ena_a ? a : 1'bz;
assign b = ena_b ? a : 1'bz;
initial
begin
error = 0;
ena_a = 1'b0;
ena_b = 1'b0;
#1 ;
ena_a = 1'b1;
#1 ;
a= 0;
#1;
if(b !== 1'b0)
begin
error = 1;
$display("FAILED - b init value not 1'b0 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1'b0)
begin
error = 1;
$display("FAILED - c init value not 1'b0 a=%b,b=%b,c=%b",a,b,c);
end
#1 ;
a= 1;
#1;
if(b !== 1'b1)
begin
error = 1;
$display("FAILED - b init value not 1'b1 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1'b1)
begin
error = 1;
$display("FAILED - c init value not 1'b1 a=%b,b=%b,c=%b",a,b,c);
end
#1 ;
ena_a = 1'b0;
#1 ;
ena_b = 1'b1;
#1 ;
a= 0;
#1;
if(b !== 1'b0)
begin
error = 1;
$display("FAILED - b init value not 1'b0 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1'b0)
begin
error = 1;
$display("FAILED - c init value not 1'b0 a=%b,b=%b,c=%b",a,b,c);
end
#1 ;
a= 1;
#1;
if(b !== 1'b1)
begin
error = 1;
$display("FAILED - b init value not 1'b1 a=%b,b=%b,c=%b",a,b,c);
end
if(c !== 1'b1)
begin
error = 1;
$display("FAILED - c init value not 1'b1 a=%b,b=%b,c=%b",a,b,c);
end
if(error == 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; vector<pair<int, int>> ans; int main() { cin.tie(0); ios::sync_with_stdio(false); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; reverse(a.begin(), a.end()); vector<pair<int, int>> ans; int m = a[0] + 1; vector<int> cnt(m); int l = 0, r = n; int st = 0; int en = m; while (l < r) { if (cnt[en - 1] == a[r - 1]) { --en; --r; continue; } if (a[l] >= en) l++; for (int i = 0; i < a[l] - st; i++) { ans.emplace_back(st, st + i + 1); cnt[st]++; cnt[st + i + 1]++; } en = a[l] + 1; st++; } cout << ans.size() << endl; for (auto p : ans) cout << p.first + 1 << << p.second + 1 << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a = 0, b = 0, c = 0, d = 0, i, e = 0, mine = 0, mn = 0; cin >> n; string s; cin >> s; for (i = 0; i < s.size(); i++) { if (s[i] == z ) a++; if (s[i] == e ) b++; if (s[i] == r ) c++; if (s[i] == o ) d++; if (s[i] == n ) e++; } mn = min(min(d, c), min(a, b)); if (b > mn && d > mn && e > 0) { mine = min(min((b - mn), (d - mn)), e); for (i = 0; i < mine; i++) { cout << 1 << ; } } if (mn > 0) { for (i = 0; i < mn; i++) { cout << 0 << ; } } cout << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_rrp_reg
(
input logic clock,
input logic resetn,
acl_ic_rrp_intf rrp_in,
(* dont_merge, altera_attribute = "-name auto_shift_register_recognition OFF" *) acl_ic_rrp_intf rrp_out
);
always @(posedge clock or negedge resetn)
if( ~resetn ) begin
rrp_out.datavalid <= 1'b0;
rrp_out.id <= 'x;
rrp_out.data <= 'x;
end
else begin
rrp_out.datavalid <= rrp_in.datavalid;
rrp_out.id <= rrp_in.id;
rrp_out.data <= rrp_in.data;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y, z = 0, k, t = 0, e, g; vector<int> zero; vector<int> po; vector<int> ne; cin >> x; g = x; while (x--) { cin >> y; if (y < 0) { ne.push_back(y); k *= y; } if (y > 0) { po.push_back(y); } if (y == 0) { zero.push_back(y); } if (y < 0 || y == 0) t++; } if (t == g) { for (int i = 0; i < 2; i++) { e = ne.back(); po.push_back(e); ne.pop_back(); } } k = ne.size(); if (k % 2 == 0) { e = ne.back(); zero.push_back(e); ne.pop_back(); } cout << ne.size() << ; for (int i = 0; i < ne.size(); i++) cout << ne[i] << ; cout << endl; cout << po.size() << ; for (int i = 0; i < po.size(); i++) cout << po[i] << ; cout << endl; cout << zero.size() << ; for (int i = 0; i < zero.size(); i++) cout << zero[i] << ; cout << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: EasySoft Group
// Engineer: Ushakov M.V. (EvilLord666)
//
// Create Date: 04.10.2016 05:53:55
// Design Name:
// Module Name: clock_divider
// Project Name:
// Target Devices: Zynq-7k
// Tool Versions: Vivado 2016.2
// Description: Module for programmable clock division from 1 till 255
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_divider #
(
parameter clock_division = 2
)
(
input wire reset,
input wire input_clock,
output wire output_clock
);
reg[7:0] counter;
reg output_clock_value;
assign output_clock = clock_division == 1 ? input_clock & reset : output_clock_value;
always @(posedge input_clock)
begin
if(~reset)
begin
counter <= 0;
output_clock_value <= 0;
end
else
begin
if(counter == clock_division - 1)
begin
output_clock_value <= ~output_clock_value;
counter <= 1;
end
else
counter <= counter + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXD = 60 + 5; const int MAXN = 2e3 * 60 + 5; const int mod = 1e9 + 7; inline long long pw(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } inline int get_lb(long long x) { int res = 0; while (x >> res) ++res; return res - 1; } int d; long long a[MAXN]; int b[MAXN]; long long pt[MAXN]; int pcnt = 0, must[MAXN], dp[MAXN][5]; int f[MAXD]; inline int get(long long u) { int pos = lower_bound(pt + 1, pt + pcnt + 1, u) - pt; if (pos > pcnt || pt[pos] != u) return -1; return pos; } inline vector<int> get_dp(long long u) { int id = get(u); if (id != -1) return vector<int>(dp[id], dp[id] + 3); else return vector<int>(3, f[d - get_lb(u)]); } int main(void) { int n; scanf( %d%d , &d, &n); for (int i = 1; i <= n; ++i) { static char t[100]; scanf( %lld%s , &a[i], t + 1); b[i] = t[1] == w || t[1] == y ? 1 : t[1] == g || t[1] == b ? 2 : 3; } f[1] = 1; for (int i = 2; i <= d; ++i) f[i] = 4ll * f[i - 1] * f[i - 1] % mod; pt[++pcnt] = 1; for (int i = 1; i <= n; ++i) { long long u = a[i]; while (u) { pt[++pcnt] = u; u >>= 1; } } sort(pt + 1, pt + pcnt + 1); pcnt = unique(pt + 1, pt + pcnt + 1) - pt - 1; for (int i = 1; i <= n; ++i) must[get(a[i])] = b[i]; for (int i = pcnt; i >= 1; --i) { if (pt[i] >= (1ll << (d - 1))) { if (!must[i]) dp[i][0] = dp[i][1] = dp[i][2] = 1; else dp[i][must[i] - 1] = 1; continue; } long long u = pt[i]; vector<int> ls = get_dp(u << 1); vector<int> rs = get_dp(u << 1 | 1); for (int x = 0; x < 3; ++x) { if (must[i] && x != must[i] - 1) continue; for (int y = 0; y < 3; ++y) if (y != x) for (int z = 0; z < 3; ++z) if (z != x) dp[i][x] = (dp[i][x] + (long long)ls[y] * rs[z]) % mod; } } int ans = 0; for (int i = 0; i < 3; ++i) ans = (ans + dp[1][i]) % mod; ans = ans * pw(2, (1ll << d) - 1 - n) % mod; printf( %d , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_PP_BLACKBOX_V
|
module step_if(clk, rst_, ena_, rdy_, mem_re_, abus, dbus, pc_din, pc_dout, pc_we_, inst);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_re_;
output[7:0] abus;
input[7:0] dbus;
output[7:0] pc_din;
input[7:0] pc_dout;
output pc_we_;
output[7:0] inst;
reg rdy_;
reg mem_re_en;
assign mem_re_ = mem_re_en ? 1'b0 : 1'bZ;
assign abus = mem_re_en ? pc_dout : 8'bZ;
reg[7:0] pc_din;
reg pc_we_en;
assign pc_we_ = pc_we_en ? 1'b0 : 1'bZ;
reg[7:0] inst;
reg[3:0] state;
always @(negedge clk or negedge rst_)
if(!rst_) begin
rdy_ <= 1;
mem_re_en <= 0;
pc_din <= 8'bZ;
pc_we_en <= 0;
inst <= 0;
state <= 0;
end else begin
/*
State 0: ena_=0 state=x000
rdy_=1 mem_re_en=1 pc_din=ZZZZZZZZ pc_we_en=0 state=0001
State 1: ena_=1 state=0001
rdy_=1 mem_re_en=1 pc_din=ZZZZZZZZ pc_we_en=0 state=0010 inst=dbus
State 2: ena_=1 state=0010
rdy_=1 mem_re_en=0 pc_din=pc_dout+1 pc_we_en=0 state=0100
State 3: ena_=1 state=0100
rdy_=1 mem_re_en=0 pc_din=pc_dout+1 pc_we_en=1 state=1000
State 4: ena_=1 state=1000
rdy_=0 mem_re_en=0 pc_din=ZZZZZZZZ pc_we_en=0 state=0000
State 5: ena_=1 state=0000
rdy_=1 mem_re_en=0 pc_din=ZZZZZZZZ pc_we_en=0 state=0000
*/
rdy_ <= ~state[3];
mem_re_en <= ~ena_ | state[0];
pc_din <= (state[1] | state[2]) ? (pc_dout+8'd1) : 8'bZ;
pc_we_en <= state[2];
inst <= state[0] ? dbus : inst;
state <= {state[2:0], ~ena_};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[100010]; vector<pair<long long, long long> > people; long long Free[100010]; int main() { long long ts, tf, t; cin >> ts >> tf >> t; int n; scanf( %d , &n); if (n == 0) { cout << ts << endl; return 0; } for (int i = 1; i <= n; i++) { scanf( %I64d , &a[i]); } people.push_back(make_pair(0, 0)); long long cnt = 1; for (int i = 1; i < n; i++) { if (a[i] != a[i + 1]) { people.push_back(make_pair(a[i], cnt)); cnt = 1; } else cnt++; } people.push_back(make_pair(a[n], cnt)); long long ans, wait; ans = a[1] - 1; wait = ts - (a[1] - 1); if (wait < 0) { wait = 0; ans = ts; } long long time = max(people[1].first, ts); for (int i = 1; i + 1 < people.size(); i++) { if (time + t > tf) break; time = time + people[i].second * t; if (time + t > tf) break; long long come_time = people[i + 1].first - 1; long long new_wait = time - come_time; if (new_wait < 0) { new_wait = 0; come_time = time; } if (new_wait < wait) { wait = new_wait; ans = come_time; } time = max(time, people[i + 1].first); } time = time + people.back().second * t; if (time + t <= tf) { ans = time; wait = 0; } cout << ans << endl; return 0; } |
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ../demo-out/iscachable.v
// {{{
// Project: AutoFPGA, a utility for composing FPGA designs from peripherals
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: ./autofpga ./autofpga -d -o ../demo-out -I ../auto-data bkram.txt buserr.txt clkcounter.txt clock.txt enet.txt flash.txt global.txt gpio.txt gps.txt hdmi.txt icape.txt legalgen.txt mdio.txt pic.txt pwrcount.txt rtcdate.txt rtcgps.txt sdram.txt sdspi.txt spio.txt version.txt wbmouse.txt wboledbw.txt wbpmic.txt wbscopc.txt wbscope.txt wbubus.txt xpander.txt zipmaster.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
`default_nettype none
//
module iscachable(
// {{{
input wire [30-1:0] i_addr,
output reg o_cachable
// }}}
);
always @(*)
begin
o_cachable = 1'b0;
// Bus master: wb
// Bus master: wb_dio
// Bus master: wb_sio
// bkram
if ((i_addr[29:0] & 30'h3e000000) == 30'h1a000000)
o_cachable = 1'b1;
// flash
if ((i_addr[29:0] & 30'h3e000000) == 30'h1c000000)
o_cachable = 1'b1;
// Bus master: rambus
// sdram
if ((i_addr[29:0] & 30'h20000000) == 30'h20000000)
o_cachable = 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 4; vector<int> adj[N]; int deg[N]; int lv[N]; int decr[N]; int vis[N]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d%d , &x, &y); adj[x].push_back(y); adj[y].push_back(x); deg[x]++; deg[y]++; } queue<pair<int, int>> q; bool yes = n > 3; for (int i = 1; i <= n; i++) if (deg[i] == 1) q.push({i, 0}), lv[i] = 1, decr[i] = 3; while (!q.empty()) { auto tmp = q.front(); q.pop(); int u = tmp.first; int p = tmp.second; vis[u] = 1; if (decr[u] < 3) yes = false; for (auto v : adj[u]) { if (vis[v]) continue; if (lv[v] != 0 && lv[v] != lv[u] + 1) { yes = false; } lv[v] = lv[u] + 1; deg[v]--; decr[v]++; if (lv[v] == k + 1 && deg[v] == 0) q.push({v, u}); else if (deg[v] == 1) q.push({v, u}); } } int mx = 0; for (int i = 1; i <= n; i++) mx = max(mx, lv[i]); yes &= (mx == k + 1); puts(yes ? Yes : No ); } |
module DebugIR (
input wire clk,
input wire rst,
input wire ir,
output reg[3:0] mode,
output reg showName,
output reg err,
output wire stateOut,
output reg[1:0] cpuClkMode,
output reg[3:0] numberPressedData,
output reg numberPressed
);
reg[31:0] irRead; // For storing data readed from IR channel
reg[5:0] irDataPos; // Counts readed data bits
//reg err;
reg ir0, ir1, ir2; // Delayed IR signal
always @(posedge clk) begin
if (rst) begin
ir0 <= 1'b0;
ir1 <= 1'b0;
ir2 <= 1'b0;
end
else begin
ir0 <= ir;
ir1 <= ir0;
ir2 <= ir1;
end
end
wire irPosEdge = !ir2 && ir1;
wire irNegEdge = ir2 && !ir1;
wire irChange = irPosEdge || irNegEdge;
reg[10:0] counter1; // 35 us counter
reg[8:0] counter2; // Slow counter
always @(posedge clk) begin
if (rst)
counter1 <= 11'b0;
else if (irChange)
counter1 <= 11'b0;
else if (counter1 == 11'd1750)
counter1 <= 11'b0;
else
counter1 <= counter1 + 11'b1;
end
always @(posedge clk) begin
if (rst)
counter2 <= 9'b0;
else if (irChange)
counter2 <= 9'b0;
else if (counter1 == 11'd1750)
counter2 <= counter2 + 9'b1;
end
wire check9ms = (217 < counter2) && (counter2 < 297); // 257 slow ticks
wire check4ms = (88 < counter2) && (counter2 < 168); // 128 slow ticks
wire high = (6 < counter2) && (counter2 < 26); // 16 slow ticks
wire low = (38 < counter2) && (counter2 < 58); // 48 slow ticks
// Scan codes
parameter CHANNEL_MINUS = 8'hA2,
CHANNEL = 8'h62,
CHANNEL_PLUS = 8'hE2,
PLAY = 8'hC2,
EQ = 8'h90,
N0 = 8'h68,
N1 = 8'h30,
N2 = 8'h18,
N3 = 8'h7A,
N4 = 8'h10,
N5 = 8'h38,
N6 = 8'h5A,
N7 = 8'h42,
N8 = 8'h4A,
N9 = 8'h52;
// State machine
parameter IDLE = 3'b000,
LEADING_9MS = 3'b001,
LEADING_4MS = 3'b010,
DATA_READ = 3'b100;
reg[2:0] state;
reg[2:0] nextState;
always @(posedge clk) begin
if (rst)
state <= IDLE;
else
state <= nextState;
end
always @(*) begin
case (state)
IDLE:
if (ir1)
nextState = LEADING_9MS;
else
nextState = IDLE;
LEADING_9MS:
if (irNegEdge) begin
if (check9ms)
nextState = LEADING_4MS;
else
nextState = IDLE;
end else
nextState = LEADING_9MS;
LEADING_4MS:
if (irPosEdge) begin
if (check4ms)
nextState = DATA_READ;
else
nextState = IDLE;
end else
nextState = LEADING_4MS;
DATA_READ:
if ((irDataPos == 6'd32) && !ir2 && !ir1)
nextState = IDLE;
else if (err)
nextState = IDLE;
else
nextState = DATA_READ;
endcase
end
always @(posedge clk) begin
if (rst) begin
irDataPos <= 6'b0;
irRead <= 32'b0;
err <= 1'b0;
end
else if (state == IDLE) begin
irDataPos <= 6'b0;
irRead <= 32'b0;
err <= 1'b0;
end
else if (state == DATA_READ) begin
if (irNegEdge) begin
if (!high)
err <= 1'b1;
end else if (irPosEdge) begin
if (high)
irRead[0] <= 1'b0;
else if (low)
irRead[0] <= 1'b1;
else
err <= 1'b1;
irRead[31:1] <= irRead[30:0];
irDataPos <= irDataPos + 6'b1;
end
end
end
always @(posedge clk) begin
if (rst) begin
showName <= 1'b0;
mode <= 4'b0;
cpuClkMode <= 2'd0;
numberPressed <= 0;
numberPressedData <= 4'd0;
end else if ((irDataPos == 6'd32) && !ir1 && ir2) begin
case (irRead[15:8])
CHANNEL:
showName <= !showName;
CHANNEL_PLUS:
if (mode < 4'd13)
mode <= mode + 1;
else
mode <= 4'd0;
CHANNEL_MINUS:
if (mode > 4'd0)
mode <= mode - 1;
else
mode <= 4'd13;
PLAY:
cpuClkMode <= cpuClkMode ^ 2'b10;
EQ:
cpuClkMode <= cpuClkMode ^ 2'b01;
N0: begin
numberPressed <= 1;
numberPressedData <= 4'd0;
end
N1: begin
numberPressed <= 1;
numberPressedData <= 4'd1;
end
N2: begin
numberPressed <= 1;
numberPressedData <= 4'd2;
end
N3: begin
numberPressed <= 1;
numberPressedData <= 4'd3;
end
N4: begin
numberPressed <= 1;
numberPressedData <= 4'd4;
end
N5: begin
numberPressed <= 1;
numberPressedData <= 4'd5;
end
N6: begin
numberPressed <= 1;
numberPressedData <= 4'd6;
end
N7: begin
numberPressed <= 1;
numberPressedData <= 4'd7;
end
N8: begin
numberPressed <= 1;
numberPressedData <= 4'd8;
end
N9: begin
numberPressed <= 1;
numberPressedData <= 4'd9;
end
endcase
end
if (numberPressed)
numberPressed <= 0;
end
assign stateOut = (irDataPos == 6'd32) && (!ir2) && (!ir1);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1e5 + 5; const long long int M = 1e9 + 7; queue<pair<long long int, long long int> > pq; vector<long long int> v; map<long long int, long long int> mpp; set<pair<long long int, long long int> > st; long long int a[N], h[N], indx[N][2]; long long int val[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long int n, l; cin >> n; string s; cin >> s; long long int a = 0; long long int b = 0; for (int i = int(0); i <= int(n - 1); i++) { if (s[i] == 8 ) a++; } long long int x = n / 11; if (a < x) cout << a; else cout << x; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { register long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return (f == 1) ? x : -x; } int cnt[10101010], X[10101010]; bool vis[10101010]; long long F[10101010], pw2[1101010]; int tot, p[1010101], a[1010101], lim, mu[10101010]; inline void seive(int n) { for (int i = 2; i <= n; i++) { if (!vis[i]) p[++tot] = i, X[i] = i, mu[i] = -1; for (int j = 1; j <= tot; j++) { if (1ll * p[j] * i > n) break; vis[p[j] * i] = 1, mu[p[j] * i] = -mu[i]; if (i % p[j] == 0) { mu[i * p[j]] = 0; X[i * p[j]] = X[i]; break; } else X[i * p[j]] = X[i] * p[j]; } } } inline void FMTand(long long *F, int lim) { for (int i = 1; i <= tot; i++) { for (int j = lim / p[i]; j; j--) { F[j] = (F[j] + F[j * p[i]]) % 1000000007; } } } inline void FMTor(long long *F, int lim) { for (int i = 1; i <= tot; i++) { for (int j = 1; j * p[i] <= lim; j++) { F[j * p[i]] = (F[j * p[i]] + F[j]) % 1000000007; } } } signed main() { long long n = read(); pw2[0] = 1; for (int i = 1; i <= n; i++) pw2[i] = 1ll * pw2[i - 1] * 2 % 1000000007; for (int i = 1; i <= n; i++) { a[i] = read(); cnt[a[i]]++; lim = max(lim, a[i]); F[a[i]] = cnt[a[i]]; } seive(lim); FMTand(F, lim); long long ONE = pw2[F[1]] - 1, _ = 0; for (int i = 2; i <= lim; i++) { ONE = (1000000007 + ONE + mu[i] * (pw2[F[i]] - 1) % 1000000007) % 1000000007; } for (int i = 1; i <= lim; i++) { F[i] = (1000000007 + (pw2[F[i]] - 1) * (1000000007 - mu[i]) % 1000000007) % 1000000007; } FMTor(F, lim); for (int i = 1; i <= lim; i++) { _ = (_ + 1ll * cnt[i] * (pw2[n] - 1 - ONE - F[X[i]]) % 1000000007) % 1000000007; } cout << (_ % 1000000007 + 1000000007) % 1000000007; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> piles(n); vector<pair<int, int>> cost(n); for (int i = 0; i < n; i++) { int tmp; scanf( %d , &tmp); piles[i] = tmp; int closest = int(sqrt(tmp) + 0.5f); cost[i] = pair<int, int>(abs(tmp - closest * closest), tmp); } sort(cost.begin(), cost.end()); unsigned long long result = 0; for (int i = 0; i < n; i++) { int _cost = cost[i].first; int _number = cost[i].second; if (i < n / 2) { result += _cost; } else { if (_cost == 0) result++; if (_number == 0) result++; } } printf( %llu n , result); return 0; } |
// This tests unalligned write/read access to packed structures
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test;
typedef struct packed {
logic [7:0] high;
logic [7:0] low;
} word_t;
// Declare word* as a VARIABLE
word_t word_se0, word_se1, word_se2, word_se3;
word_t word_sw0, word_sw1, word_sw2, word_sw3;
word_t word_sp0, word_sp1, word_sp2, word_sp3;
word_t word_ep0, word_ep1, word_ep2, word_ep3;
// error counter
bit err = 0;
// access to structure elements
assign word_se1.high = {8+0{1'b1}};
assign word_se1.low = {8+0{1'b0}};
assign word_se2.high = {8+1{1'b1}};
assign word_se2.low = {8+1{1'b0}};
assign word_se3.high = {8-1{1'b1}};
assign word_se3.low = {8-1{1'b0}};
// access to whole structure
assign word_sw1 = {16+0{1'b1}};
assign word_sw2 = {16+1{1'b1}};
assign word_sw3 = {16-1{1'b1}};
// access to parts of structure elements
assign word_ep1.high [3:0] = {4+0{1'b1}};
assign word_ep1.low [3:0] = {4+0{1'b0}};
assign word_ep2.high [3:0] = {4+1{1'b1}};
assign word_ep2.low [3:0] = {4+1{1'b0}};
assign word_ep3.high [3:0] = {4-1{1'b1}};
assign word_ep3.low [3:0] = {4-1{1'b0}};
// access to parts of the whole structure
assign word_sp1 [11:4] = {8+0{1'b1}};
assign word_sp2 [11:4] = {8+1{1'b1}};
assign word_sp3 [11:4] = {8-1{1'b1}};
initial begin
#1;
// access to structure elements
if (word_se0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_se0 = 'b%b", word_se0 ); err=1; end
if (word_se1 !== 16'b11111111_00000000) begin $display("FAILED -- word_se1 = 'b%b", word_se1 ); err=1; end
if (word_se1.high !== 8'b11111111 ) begin $display("FAILED -- word_se1.high = 'b%b", word_se1.high); err=1; end
if (word_se1.low !== 8'b00000000 ) begin $display("FAILED -- word_se1.low = 'b%b", word_se1.low ); err=1; end
if (word_se2 !== 16'b11111111_00000000) begin $display("FAILED -- word_se2 = 'b%b", word_se2 ); err=1; end
if (word_se2.high !== 8'b11111111 ) begin $display("FAILED -- word_se2.high = 'b%b", word_se2.high); err=1; end
if (word_se2.low !== 8'b00000000 ) begin $display("FAILED -- word_se2.low = 'b%b", word_se2.low ); err=1; end
if (word_se3 !== 16'b01111111_00000000) begin $display("FAILED -- word_se3 = 'b%b", word_se3 ); err=1; end
if (word_se3.high !== 8'b01111111 ) begin $display("FAILED -- word_se3.high = 'b%b", word_se3.high); err=1; end
if (word_se3.low !== 8'b00000000 ) begin $display("FAILED -- word_se3.low = 'b%b", word_se3.low ); err=1; end
// access to whole structure
if (word_sw0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_sw0 = 'b%b", word_sw0 ); err=1; end
if (word_sw1 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw1 = 'b%b", word_sw1 ); err=1; end
if (word_sw2 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw2 = 'b%b", word_sw2 ); err=1; end
if (word_sw3 !== 16'b01111111_11111111) begin $display("FAILED -- word_sw3 = 'b%b", word_sw3 ); err=1; end
// access to parts of structure elements
if (word_ep0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_ep0 = 'b%b", word_ep0 ); err=1; end
if (word_ep1 !== 16'bxxxx1111_xxxx0000) begin $display("FAILED -- word_ep1 = 'b%b", word_ep1 ); err=1; end
if (word_ep1.high !== 8'bxxxx1111 ) begin $display("FAILED -- word_ep1.high = 'b%b", word_ep1.high); err=1; end
if (word_ep1.low !== 8'bxxxx0000 ) begin $display("FAILED -- word_ep1.low = 'b%b", word_ep1.low ); err=1; end
if (word_ep2 !== 16'bxxxx1111_xxxx0000) begin $display("FAILED -- word_ep2 = 'b%b", word_ep2 ); err=1; end
if (word_ep2.high !== 8'bxxxx1111 ) begin $display("FAILED -- word_ep2.high = 'b%b", word_ep2.high); err=1; end
if (word_ep2.low !== 8'bxxxx0000 ) begin $display("FAILED -- word_ep2.low = 'b%b", word_ep2.low ); err=1; end
if (word_ep3 !== 16'bxxxx0111_xxxx0000) begin $display("FAILED -- word_ep3 = 'b%b", word_ep3 ); err=1; end
if (word_ep3.high !== 8'bxxxx0111 ) begin $display("FAILED -- word_ep3.high = 'b%b", word_ep3.high); err=1; end
if (word_ep3.low !== 8'bxxxx0000 ) begin $display("FAILED -- word_ep3.low = 'b%b", word_ep3.low ); err=1; end
// access to parts of the whole structure
if (word_sp0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_sp0 = 'b%b", word_sp0 ); err=1; end
if (word_sp1 !== 16'bxxxx1111_1111xxxx) begin $display("FAILED -- word_sp1 = 'b%b", word_sp1 ); err=1; end
if (word_sp2 !== 16'bxxxx1111_1111xxxx) begin $display("FAILED -- word_sp2 = 'b%b", word_sp2 ); err=1; end
if (word_sp3 !== 16'bxxxx0111_1111xxxx) begin $display("FAILED -- word_sp3 = 'b%b", word_sp3 ); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /stack:247474112 ) #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) long long mod = 1e9 + 7; void time() {} const long long N = 3100300; const long long maxn = 1e5 + 5; const long long despacito = 1e9 + 7; long long n, m; long long a[N], p[N], cnt[N], z[N]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; } cin >> m; for (long long i = 1; i <= m; i++) { cin >> p[i]; } for (long long i = 1; i <= n; i++) { cnt[a[i]]++; } for (long long a = 1; a <= N; a++) { if (!cnt[a]) continue; for (long long b = a; b < N; b += a) { if (b / a != a) { z[b] += (long long)(cnt[a] * cnt[b / a]); } else z[b] += (long long)(cnt[a] * (cnt[a] - 1)); } } for (long long i = 1; i <= N; ++i) { z[i] += z[i - 1]; } for (long long i = 1; i <= m; ++i) { long long ans = (long long)(n) * (n - 1) - z[p[i] - 1]; cout << ans << n ; } time(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x[100005], y[100005]; int i, n, d = 0, k = 0, cnt = 0; cin >> n; cin >> x[0] >> y[0]; d = x[0]; k = y[0]; for (i = 1; i <= n; i++) { cin >> x[i] >> y[i]; if (y[i] > y[i - 1]) { k = y[i]; } } cnt = (n - 4) / 2; cout << cnt; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int SG(double x) { return x > -1E-8 ? x < 1E-8 ? 0 : 1 : -1; } int c[1000000]; int main() { int n, m, r, i, j, k, d; long long md; scanf( %d %d %d , &n, &m, &r); for (i = 0; i < (n); i++) { scanf( %d , &c[i]); } if (n % 2 == 0) { puts( 0 ); return 0; } d = (n + 1) / 2; md = (long long)(m / d) * (long long)r; for (i = 0; i < n; i += 2) { if (c[i] < md) md = c[i]; } printf( %I64d n , md); return 0; } |
#include <bits/stdc++.h> using namespace std; char s[105][105]; int sz[105]; vector<int> g[105]; int usd[30]; int ord[30], szo = 0, din[30]; bool dfs(int v) { usd[v] = 1; for (int i = 0; i < g[v].size(); ++i) { int u = g[v][i]; if (usd[u] == 1) return false; else if (!usd[u]) if (!dfs(u)) return false; } usd[v] = 2; ord[szo++] = v; return true; } int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { scanf( %s , s[i]); sz[i] = strlen(s[i]); } for (int i = 1; i < n; ++i) { int j, mn = min(sz[i], sz[i - 1]); for (j = 0; j < mn; ++j) if (s[i][j] != s[i - 1][j]) { g[s[i - 1][j] - a ].push_back(s[i][j] - a ); din[s[i][j] - a ]++; break; } if (j == mn && sz[i] == mn) { cout << Impossible n ; return 0; } } for (int i = 0; i < 26; ++i) if (din[i] == 0) if (!dfs(i)) { cout << Impossible n ; return 0; } if (szo < 26) { cout << Impossible n ; return 0; } for (int i = szo - 1; i >= 0; --i) printf( %c , ord[i] + a ); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2001; const long long INF = 1e15; int DELTA = 2500; int n; long long price[MAXN], Time[MAXN]; long long dp[MAXN][3 * MAXN]; long long rec(int idx, int remTime) { if (remTime >= MAXN) remTime = MAXN - 1; if (idx == n) return remTime >= 0 ? 0 : INF; long long &ans = dp[idx][remTime + DELTA]; if (ans != -1) return ans; ans = INF; ans = min(ans, rec(idx + 1, remTime - 1)); ans = min(ans, price[idx] + rec(idx + 1, remTime + Time[idx])); return ans; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> Time[i] >> price[i]; memset(dp, -1, sizeof(dp)); cout << rec(0, 0) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a[100], b[100], oa = 0, ob = 0, ore = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i] >> b[i]; if (a[i] % 2 == 1) oa++; if (b[i] % 2 == 1) ob++; if (a[i] % 2 == 1 && b[i] % 2 == 1) ore++; } if (oa % 2 == 0 && ob % 2 == 0) cout << 0; else if (oa % 2 == 1 && ob % 2 == 0 || oa % 2 == 0 && ob % 2 == 1 || oa - ore == 0 && ob - ore == 0) cout << -1; else cout << 1; } |
#include <bits/stdc++.h> using namespace std; int t, n, l, r, pos; char in[1000], ans[1000][10]; bool back; int main() { scanf( %d , &t); while (t--) { back = false; scanf( %s , in); n = strlen(in); for (int i = 1; i <= 8; i++) for (int j = 0; j <= 3; j++) ans[i][j] = 0 ; pos = 1; l = r = 0; for (int i = 0; i < n;) { if (in[i] == : ) { if (in[i + 1] == : ) { l = i + 2; i += 2; back = true; pos = 8; } else { l = i + 1; i++; } continue; } while (i + 1 < n && in[i + 1] != : ) i++; r = i; int x = 4 - (r - l + 1); for (int j = r; j >= l; j--) { ans[pos][j - l + x] = in[j]; } if (!back) pos++; else pos--; i++; } if (!back) { for (int i = 1; i <= 8; i++) { if (i != 1) putchar( : ); for (int j = 0; j <= 3; j++) putchar(ans[i][j]); } } else { for (int i = 1; i <= pos; i++) { if (i != 1) putchar( : ); for (int j = 0; j <= 3; j++) putchar(ans[i][j]); } for (int i = 8; i >= pos + 1; i--) { putchar( : ); for (int j = 0; j <= 3; j++) putchar(ans[i][j]); } } puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; int n; cin >> n >> s; int res = 0; long long a = 0, b = 0; for (int i = 0; i < n; i++) { if (s[i] == s[0]) { a++; } else { break; } } for (int i = n - 1; i >= 0; i--) { if (s[i] == s[n - 1]) { b++; } else { break; } } if (s[0] == s[n - 1]) { cout << ((a + 1) * (b + 1)) % 998244353; } else { cout << (a + b + 1) % 998244353; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_hdll__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hdll__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_V |
module fifo # (parameter abits =6, dbits = 321)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full
//output reg ledres
);
wire db_wr, db_rd;
reg dffw1, dffw2, dffr1, dffr2;
reg [dbits-1:0] out;
//initial ledres = 0;
always @ (posedge clock) dffw1 <= wr;
always @ (posedge clock) dffw2 <= dffw1;
assign db_wr = ~dffw1 & dffw2; //monostable multivibrator to detect only one pulse of the button
always @ (posedge clock) dffr1 <= rd;
always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = ~dffr1 & dffr2; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
// ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
//ledres=1;
end
end
always @(*)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[300]; int main() { int n, k, cnt = 0; cin >> n >> k; for (int i = 0; i < 2 * n + 1; i++) cin >> a[i]; for (int i = 1; (i <= 2 * n - 1) && (cnt != k); i += 2) { if (a[i] - 1 > a[i - 1] && a[i] - 1 > a[i + 1]) { a[i]--; cnt++; } } for (int i = 0; i < 2 * n + 1; i++) cout << a[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const double pi = 3.1415926535897932; const double eln = 2.718281828459045; vector<int> a[200005]; int p[200005], b[200005], od[200005]; void second(int m, int dah) { p[m] = dah; b[m] = 1; for (int i = 0; i < a[m].size(); ++i) { if (!b[a[m][i]]) { second(a[m][i], dah + 1); } } } int main() { ios::sync_with_stdio(false); int n, x, y; cin >> n; for (int i = 0; i < n - 1; ++i) { cin >> x >> y; a[x].push_back(y); a[y].push_back(x); } second(1, 1); int maxx = 0; int first = 0, st, hh; for (int i = 0; i < n; ++i) { cin >> x; if (p[x] > maxx) { hh = od[x]; maxx = p[x]; st = 1; for (int j = 0; j < a[x].size(); ++j) { if (!od[a[x][j]]) { od[a[x][j]] = st; } } } else if (p[x] == maxx) { if (od[x] < hh) { cout << No ; return 0; } hh = max(hh, od[x]); st++; for (int j = 0; j < a[x].size(); ++j) { if (!od[a[x][j]]) { od[a[x][j]] = st; } } } else if (p[x] < maxx) { cout << No ; return 0; } } cout << Yes ; return 0; } |
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