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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:28:49 05/24/2015
// Design Name: binary_to_BCD_fourteen_bit
// Module Name: D:/Digilent/Data/Xilinx/Projects/ISE_12_4/Binary_to_BCD_Eight_Bit/binary_to_BCD_fourteen_bit_tb.v
// Project Name: Binary_to_BCD_Eight_Bit
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: binary_to_BCD_fourteen_bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module binary_to_BCD_fourteen_bit_tb;
// Inputs
reg [13:0] in;
// Outputs
wire [3:0] ones;
wire [3:0] tens;
wire [3:0] hundreds;
wire [3:0] thousands;
// Instantiate the Unit Under Test (UUT)
binary_to_BCD_fourteen_bit uut (
.in(in),
.ones(ones),
.tens(tens),
.hundreds(hundreds),
.thousands(thousands)
);
initial begin
// Initialize Inputs
in = 0;
for (in =0;in< 10000;in = in +1) begin
#10
$display(" in = %d thousands = %d hundreds = %d tens = %d ones = %d",in, thousands, hundreds, tens, ones);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__O21AI_PP_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_BLACKBOX_V
`define SKY130_FD_SC_LS__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_BLACKBOX_V
|
`ifndef ROI
ERROR: must set ROI
`endif
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
`ROI
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
/******************************************************************************
*******************************************************************************
CONFIG ROI
*******************************************************************************
******************************************************************************/
/******************************************************************************
Toggle a single data bit to locate a single instance
******************************************************************************/
module roi_brami_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
module roi_brami_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
Toggle one bit per BRAM in the ROI to show pitch between entries
******************************************************************************/
module roi_bramis_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
module roi_bramis_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
/******************************************************************************
Misc ROI
******************************************************************************/
/*
Place everything into first tile
This is invalid since 18/36 share resources
*/
module roi_invalid(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT({256{1'b1}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y41"), .INIT({256{1'b1}}))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT({256{1'b1}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
endmodule
/******************************************************************************
READ_WIDTH
******************************************************************************/
module roi_bram18_width_a(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .READ_WIDTH_A(1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
//"READ_WIDTH_A": [0, 1, 2, 4, 9, 18, 36],
module roi_bram18_width_b(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .READ_WIDTH_A(0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
WRITE_MODE
******************************************************************************/
module roi_bram18_write_mode_a(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("WRITE_FIRST"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
// WRITE_FIRST (default), READ_FIRST, and NO_CHANGE
module roi_bram18_write_mode_b(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("NO_CHANGE"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
RAM_MODE
******************************************************************************/
module roi_bram18_ram_mode_tdp(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("TDP"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/*
ERROR: [DRC REQP-1931] RAMB18E1_WEA_NO_CONNECT_OR_TIED_GND:
roi/r0/ram programming per UG473 requires that for SDP mode the WEA bus must be unconnected
or tied to GND.
Are these routing bits are real bits we need to look at?
> bit_0002031b_002_00
> bit_0002031b_002_04
*/
module roi_bram18_ram_mode_sdp(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("SDP"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
/******************************************************************************
*******************************************************************************
Library
*******************************************************************************
******************************************************************************/
/*
Site RAMB18_X0Y42
Pushed it outside the pblock
lets extend pblock
for i in xrange(0x08): print '.INITP_%02X(INIT),' % i
for i in xrange(0x40): print '.INIT_%02X(INIT),' % i
*/
module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
(* LOC=LOC *)
RAMB18E1 #(
.INITP_00(INIT),
.INITP_01(INIT),
.INITP_02(INIT),
.INITP_03(INIT),
.INITP_04(INIT),
.INITP_05(INIT),
.INITP_06(INIT),
.INITP_07(INIT),
.INIT_00(INIT0),
.INIT_01(INIT),
.INIT_02(INIT),
.INIT_03(INIT),
.INIT_04(INIT),
.INIT_05(INIT),
.INIT_06(INIT),
.INIT_07(INIT),
.INIT_08(INIT),
.INIT_09(INIT),
.INIT_0A(INIT),
.INIT_0B(INIT),
.INIT_0C(INIT),
.INIT_0D(INIT),
.INIT_0E(INIT),
.INIT_0F(INIT),
.INIT_10(INIT),
.INIT_11(INIT),
.INIT_12(INIT),
.INIT_13(INIT),
.INIT_14(INIT),
.INIT_15(INIT),
.INIT_16(INIT),
.INIT_17(INIT),
.INIT_18(INIT),
.INIT_19(INIT),
.INIT_1A(INIT),
.INIT_1B(INIT),
.INIT_1C(INIT),
.INIT_1D(INIT),
.INIT_1E(INIT),
.INIT_1F(INIT),
.INIT_20(INIT),
.INIT_21(INIT),
.INIT_22(INIT),
.INIT_23(INIT),
.INIT_24(INIT),
.INIT_25(INIT),
.INIT_26(INIT),
.INIT_27(INIT),
.INIT_28(INIT),
.INIT_29(INIT),
.INIT_2A(INIT),
.INIT_2B(INIT),
.INIT_2C(INIT),
.INIT_2D(INIT),
.INIT_2E(INIT),
.INIT_2F(INIT),
.INIT_30(INIT),
.INIT_31(INIT),
.INIT_32(INIT),
.INIT_33(INIT),
.INIT_34(INIT),
.INIT_35(INIT),
.INIT_36(INIT),
.INIT_37(INIT),
.INIT_38(INIT),
.INIT_39(INIT),
.INIT_3A(INIT),
.INIT_3B(INIT),
.INIT_3C(INIT),
.INIT_3D(INIT),
.INIT_3E(INIT),
.INIT_3F(INIT),
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RAM_MODE(RAM_MODE),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_ENARDEN_INVERTED = 1'b0;
(* LOC=LOC *)
RAMB36E1 #(
.INITP_00(INIT),
.INITP_01(INIT),
.INITP_02(INIT),
.INITP_03(INIT),
.INITP_04(INIT),
.INITP_05(INIT),
.INITP_06(INIT),
.INITP_07(INIT),
.INITP_08(INIT),
.INITP_09(INIT),
.INITP_0A(INIT),
.INITP_0B(INIT),
.INITP_0C(INIT),
.INITP_0D(INIT),
.INITP_0E(INIT),
.INITP_0F(INIT),
.INIT_00(INIT0),
.INIT_01(INIT),
.INIT_02(INIT),
.INIT_03(INIT),
.INIT_04(INIT),
.INIT_05(INIT),
.INIT_06(INIT),
.INIT_07(INIT),
.INIT_08(INIT),
.INIT_09(INIT),
.INIT_0A(INIT),
.INIT_0B(INIT),
.INIT_0C(INIT),
.INIT_0D(INIT),
.INIT_0E(INIT),
.INIT_0F(INIT),
.INIT_10(INIT),
.INIT_11(INIT),
.INIT_12(INIT),
.INIT_13(INIT),
.INIT_14(INIT),
.INIT_15(INIT),
.INIT_16(INIT),
.INIT_17(INIT),
.INIT_18(INIT),
.INIT_19(INIT),
.INIT_1A(INIT),
.INIT_1B(INIT),
.INIT_1C(INIT),
.INIT_1D(INIT),
.INIT_1E(INIT),
.INIT_1F(INIT),
.INIT_20(INIT),
.INIT_21(INIT),
.INIT_22(INIT),
.INIT_23(INIT),
.INIT_24(INIT),
.INIT_25(INIT),
.INIT_26(INIT),
.INIT_27(INIT),
.INIT_28(INIT),
.INIT_29(INIT),
.INIT_2A(INIT),
.INIT_2B(INIT),
.INIT_2C(INIT),
.INIT_2D(INIT),
.INIT_2E(INIT),
.INIT_2F(INIT),
.INIT_30(INIT),
.INIT_31(INIT),
.INIT_32(INIT),
.INIT_33(INIT),
.INIT_34(INIT),
.INIT_35(INIT),
.INIT_36(INIT),
.INIT_37(INIT),
.INIT_38(INIT),
.INIT_39(INIT),
.INIT_3A(INIT),
.INIT_3B(INIT),
.INIT_3C(INIT),
.INIT_3D(INIT),
.INIT_3E(INIT),
.INIT_3F(INIT),
.INIT_40(INIT),
.INIT_41(INIT),
.INIT_42(INIT),
.INIT_43(INIT),
.INIT_44(INIT),
.INIT_45(INIT),
.INIT_46(INIT),
.INIT_47(INIT),
.INIT_48(INIT),
.INIT_49(INIT),
.INIT_4A(INIT),
.INIT_4B(INIT),
.INIT_4C(INIT),
.INIT_4D(INIT),
.INIT_4E(INIT),
.INIT_4F(INIT),
.INIT_50(INIT),
.INIT_51(INIT),
.INIT_52(INIT),
.INIT_53(INIT),
.INIT_54(INIT),
.INIT_55(INIT),
.INIT_56(INIT),
.INIT_57(INIT),
.INIT_58(INIT),
.INIT_59(INIT),
.INIT_5A(INIT),
.INIT_5B(INIT),
.INIT_5C(INIT),
.INIT_5D(INIT),
.INIT_5E(INIT),
.INIT_5F(INIT),
.INIT_60(INIT),
.INIT_61(INIT),
.INIT_62(INIT),
.INIT_63(INIT),
.INIT_64(INIT),
.INIT_65(INIT),
.INIT_66(INIT),
.INIT_67(INIT),
.INIT_68(INIT),
.INIT_69(INIT),
.INIT_6A(INIT),
.INIT_6B(INIT),
.INIT_6C(INIT),
.INIT_6D(INIT),
.INIT_6E(INIT),
.INIT_6F(INIT),
.INIT_70(INIT),
.INIT_71(INIT),
.INIT_72(INIT),
.INIT_73(INIT),
.INIT_74(INIT),
.INIT_75(INIT),
.INIT_76(INIT),
.INIT_77(INIT),
.INIT_78(INIT),
.INIT_79(INIT),
.INIT_7A(INIT),
.INIT_7B(INIT),
.INIT_7C(INIT),
.INIT_7D(INIT),
.INIT_7E(INIT),
.INIT_7F(INIT),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_2_V
`define SKY130_FD_SC_MS__A32OI_2_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR4BB_PP_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_PP_SYMBOL_V
|
//
// Designed by Qiang Wu
//
// 0: up
// 1: left
// 2: down
// 3: right
`timescale 1ns/1ps
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module out_switch(
input clk,
input reset,
output [239:0] TRIG0,
input [63:0] pb_out_data0,
input [23:0] pb_out_pkt_route0,
input pb_out_wr0,
input pb_out_req0,
output pb_out_ack0,
input [1:0] pb_out_neighbor0,
input pb_out_bop0,
input pb_out_eop0,
output pb_out_rdy0,
input pb_out_bypass0,
input [63:0] pb_out_data1,
input [23:0] pb_out_pkt_route1,
input pb_out_wr1,
input pb_out_req1,
output pb_out_ack1,
input [1:0] pb_out_neighbor1,
input pb_out_bop1,
input pb_out_eop1,
output pb_out_rdy1,
input pb_out_bypass1,
input [63:0] pb_out_data2,
input [23:0] pb_out_pkt_route2,
input pb_out_wr2,
input pb_out_req2,
output pb_out_ack2,
input [1:0] pb_out_neighbor2,
input pb_out_bop2,
input pb_out_eop2,
output pb_out_rdy2,
input pb_out_bypass2,
input [63:0] pb_out_data3,
input [23:0] pb_out_pkt_route3,
input pb_out_wr3,
input pb_out_req3,
output pb_out_ack3,
input [1:0] pb_out_neighbor3,
input pb_out_bop3,
input pb_out_eop3,
output pb_out_rdy3,
input pb_out_bypass3,
//4 bypass packet buffers
input [63:0] pb_out_data4,
input [23:0] pb_out_pkt_route4,
input pb_out_wr4,
input pb_out_req4,
output pb_out_ack4,
input [1:0] pb_out_neighbor4,
input pb_out_bop4,
input pb_out_eop4,
output pb_out_rdy4,
input pb_out_bypass4,
input [63:0] pb_out_data5,
input [23:0] pb_out_pkt_route5,
input pb_out_wr5,
input pb_out_req5,
output pb_out_ack5,
input [1:0] pb_out_neighbor5,
input pb_out_bop5,
input pb_out_eop5,
output pb_out_rdy5,
input pb_out_bypass5,
// input [63:0] pb_out_data6,
// input [23:0] pb_out_pkt_route6,
// input pb_out_wr6,
// input pb_out_req6,
// output pb_out_ack6,
// input [1:0] pb_out_neighbor6,
// input pb_out_bop6,
// input pb_out_eop6,
// output pb_out_rdy6,
// input pb_out_bypass6,
// input [63:0] pb_out_data7,
// input [23:0] pb_out_pkt_route7,
// input pb_out_wr7,
// input pb_out_req7,
// output pb_out_ack7,
// input [1:0] pb_out_neighbor7,
// input pb_out_bop7,
// input pb_out_eop7,
// output pb_out_rdy7,
// input pb_out_bypass7,
output reg [63:0] out_data0,
output reg [23:0] out_pkt_route0,
output reg out_wr0,
output reg out_req0,
input out_ack0,
output reg out_bop0,
output reg out_eop0,
input out_rdy0,
output reg out_bypass0,
output reg [63:0] out_data1,
output reg [23:0] out_pkt_route1,
output reg out_wr1,
output reg out_req1,
input out_ack1,
output reg out_bop1,
output reg out_eop1,
input out_rdy1,
output reg out_bypass1,
output reg [63:0] out_data2,
output reg [23:0] out_pkt_route2,
output reg out_wr2,
output reg out_req2,
input out_ack2,
output reg out_bop2,
output reg out_eop2,
input out_rdy2,
output reg out_bypass2,
output reg [63:0] out_data3,
output reg [23:0] out_pkt_route3,
output reg out_wr3,
output reg out_req3,
input out_ack3,
output reg out_bop3,
output reg out_eop3,
input out_rdy3,
output reg out_bypass3
);
reg [7:0] pb_out_ack;
assign pb_out_ack0 = pb_out_ack[0];
assign pb_out_ack1 = pb_out_ack[1];
assign pb_out_ack2 = pb_out_ack[2];
assign pb_out_ack3 = pb_out_ack[3];
assign pb_out_ack4 = pb_out_ack[4];
assign pb_out_ack5 = pb_out_ack[5];
//assign pb_out_ack6 = pb_out_ack[6];
//assign pb_out_ack7 = pb_out_ack[7];
wire [7:0] pb_out_req;
assign pb_out_req[0] = pb_out_req0;
assign pb_out_req[1] = pb_out_req1;
assign pb_out_req[2] = pb_out_req2;
assign pb_out_req[3] = pb_out_req3;
assign pb_out_req[4] = pb_out_req4;
assign pb_out_req[5] = pb_out_req5;
//assign pb_out_req[6] = pb_out_req6;
//assign pb_out_req[7] = pb_out_req7;
wire [1:0] pb_out_neighbor[7:0];
assign pb_out_neighbor[0] = pb_out_neighbor0;
assign pb_out_neighbor[1] = pb_out_neighbor1;
assign pb_out_neighbor[2] = pb_out_neighbor2;
assign pb_out_neighbor[3] = pb_out_neighbor3;
assign pb_out_neighbor[4] = pb_out_neighbor4;
assign pb_out_neighbor[5] = pb_out_neighbor5;
//assign pb_out_neighbor[6] = pb_out_neighbor6;
//assign pb_out_neighbor[7] = pb_out_neighbor7;
wire pb_out_bypass[7:0];
assign pb_out_bypass[0] = pb_out_bypass0;
assign pb_out_bypass[1] = pb_out_bypass1;
assign pb_out_bypass[2] = pb_out_bypass2;
assign pb_out_bypass[3] = pb_out_bypass3;
assign pb_out_bypass[4] = pb_out_bypass4;
assign pb_out_bypass[5] = pb_out_bypass5;
//assign pb_out_bypass[6] = pb_out_bypass6;
//assign pb_out_bypass[7] = pb_out_bypass7;
wire [63:0] pb_out_data [7:0];
assign pb_out_data[0] = pb_out_data0;
assign pb_out_data[1] = pb_out_data1;
assign pb_out_data[2] = pb_out_data2;
assign pb_out_data[3] = pb_out_data3;
assign pb_out_data[4] = pb_out_data4;
assign pb_out_data[5] = pb_out_data5;
//assign pb_out_data[6] = pb_out_data6;
//assign pb_out_data[7] = pb_out_data7;
wire [23:0] pb_out_pkt_route [7:0];
assign pb_out_pkt_route[0] = pb_out_pkt_route0;
assign pb_out_pkt_route[1] = pb_out_pkt_route1;
assign pb_out_pkt_route[2] = pb_out_pkt_route2;
assign pb_out_pkt_route[3] = pb_out_pkt_route3;
assign pb_out_pkt_route[4] = pb_out_pkt_route4;
assign pb_out_pkt_route[5] = pb_out_pkt_route5;
//assign pb_out_pkt_route[6] = pb_out_pkt_route6;
//assign pb_out_pkt_route[7] = pb_out_pkt_route7;
wire [7:0] pb_out_wr;
assign pb_out_wr[0] = pb_out_wr0;
assign pb_out_wr[1] = pb_out_wr1;
assign pb_out_wr[2] = pb_out_wr2;
assign pb_out_wr[3] = pb_out_wr3;
assign pb_out_wr[4] = pb_out_wr4;
assign pb_out_wr[5] = pb_out_wr5;
//assign pb_out_wr[6] = pb_out_wr6;
//assign pb_out_wr[7] = pb_out_wr7;
wire [7:0] pb_out_bop;
assign pb_out_bop[0] = pb_out_bop0;
assign pb_out_bop[1] = pb_out_bop1;
assign pb_out_bop[2] = pb_out_bop2;
assign pb_out_bop[3] = pb_out_bop3;
assign pb_out_bop[4] = pb_out_bop4;
assign pb_out_bop[5] = pb_out_bop5;
//assign pb_out_bop[6] = pb_out_bop6;
//assign pb_out_bop[7] = pb_out_bop7;
wire [7:0] pb_out_eop;
assign pb_out_eop[0] = pb_out_eop0;
assign pb_out_eop[1] = pb_out_eop1;
assign pb_out_eop[2] = pb_out_eop2;
assign pb_out_eop[3] = pb_out_eop3;
assign pb_out_eop[4] = pb_out_eop4;
assign pb_out_eop[5] = pb_out_eop5;
//assign pb_out_eop[6] = pb_out_eop6;
//assign pb_out_eop[7] = pb_out_eop7;
reg tx_in_progress0;
reg tx_in_progress1;
reg tx_in_progress2;
reg tx_in_progress3;
reg [2:0] curr_buff0;
reg [2:0] curr_buff1;
reg [2:0] curr_buff2;
reg [2:0] curr_buff3;
reg [2:0] curr_buff0_next;
reg [2:0] curr_buff1_next;
reg [2:0] curr_buff2_next;
reg [2:0] curr_buff3_next;
wire [2:0] curr_buff0_plus_1;
wire [2:0] curr_buff1_plus_1;
wire [2:0] curr_buff2_plus_1;
wire [2:0] curr_buff3_plus_1;
assign curr_buff0_plus_1 = (curr_buff0 == 3'b101) ? 0 : curr_buff0 + 1;
assign curr_buff1_plus_1 = (curr_buff1 == 3'b101) ? 0 : curr_buff1 + 1;
assign curr_buff2_plus_1 = (curr_buff2 == 3'b101) ? 0 : curr_buff2 + 1;
assign curr_buff3_plus_1 = (curr_buff3 == 3'b101) ? 0 : curr_buff3 + 1;
wire [1:0] pb_nei0;
wire [1:0] pb_nei1;
wire [1:0] pb_nei2;
wire [1:0] pb_nei3;
assign pb_nei0 = pb_out_neighbor[curr_buff0];
assign pb_nei1 = pb_out_neighbor[curr_buff1];
assign pb_nei2 = pb_out_neighbor[curr_buff2];
assign pb_nei3 = pb_out_neighbor[curr_buff3];
wire pb_bypass0;
wire pb_bypass1;
wire pb_bypass2;
wire pb_bypass3;
assign pb_bypass0 = pb_out_bypass[curr_buff0];
assign pb_bypass1 = pb_out_bypass[curr_buff1];
assign pb_bypass2 = pb_out_bypass[curr_buff2];
assign pb_bypass3 = pb_out_bypass[curr_buff3];
parameter OS_IDLE = 3'b001,
OS_LOOKUP_BUFF = 3'b010,
OS_PORT_REQ = 3'b011,
OS_TX = 3'b100,
OS_CANCEL = 3'b101;
reg [2:0] os_state0;
reg [2:0] os_state_next0;
reg [2:0] os_state1;
reg [2:0] os_state_next1;
reg [2:0] os_state2;
reg [2:0] os_state_next2;
reg [2:0] os_state3;
reg [2:0] os_state_next3;
always @(*)
begin
pb_out_ack = 0;
curr_buff0_next = curr_buff0;
os_state_next0 = os_state0;
case(os_state0)
OS_IDLE: begin
out_bypass0 = 0;
out_req0 = 0;
tx_in_progress0 = 0;
os_state_next0 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req0 = 0;
if(pb_out_req[curr_buff0]) begin
if(pb_nei0 == 2'b00) begin
os_state_next0 = OS_PORT_REQ;
end else begin
curr_buff0_next = curr_buff0_plus_1;
end
end else begin
curr_buff0_next = curr_buff0_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass0 = pb_bypass0;
out_req0 = 1;
if(out_ack0) begin
os_state_next0 = OS_TX;
end
end
OS_TX: begin
out_req0 = 1;
if(pb_out_req[curr_buff0]) begin
tx_in_progress0 = 1;
pb_out_ack[curr_buff0] = 1;
end else begin
tx_in_progress0 = 0;
os_state_next0 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req0 = 0;
if(!out_ack0) begin
pb_out_ack[curr_buff0] = 0;
os_state_next0 = OS_IDLE;
end
end
default: begin
out_bypass0 = 0;
out_req0 = 0;
tx_in_progress0 = 0;
os_state_next0 = OS_IDLE;
end
endcase
curr_buff1_next = curr_buff1;
os_state_next1 = os_state1;
case(os_state1)
OS_IDLE: begin
out_bypass1 = 0;
out_req1 = 0;
tx_in_progress1 = 0;
os_state_next1 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req1 = 0;
if(pb_out_req[curr_buff1]) begin
if(pb_nei1 == 2'b01) begin
os_state_next1 = OS_PORT_REQ;
end else begin
curr_buff1_next = curr_buff1_plus_1;
end
end else begin
curr_buff1_next = curr_buff1_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass1 = pb_bypass1;
out_req1 = 1;
if(out_ack1) begin
os_state_next1 = OS_TX;
end
end
OS_TX: begin
out_req1 = 1;
if(pb_out_req[curr_buff1]) begin
tx_in_progress1 = 1;
pb_out_ack[curr_buff1] = 1;
end else begin
tx_in_progress1 = 0;
os_state_next1 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req1 = 0;
if(!out_ack1) begin
pb_out_ack[curr_buff1] = 0;
os_state_next1 = OS_IDLE;
end
end
default: begin
out_bypass1 = 0;
out_req1 = 0;
tx_in_progress1 = 0;
os_state_next1 = OS_IDLE;
end
endcase
curr_buff2_next = curr_buff2;
os_state_next2 = os_state2;
case(os_state2)
OS_IDLE: begin
out_bypass2 = 0;
out_req2 = 0;
tx_in_progress2 = 0;
os_state_next2 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req2 = 0;
if(pb_out_req[curr_buff2]) begin
if(pb_nei2 == 2'b10) begin
os_state_next2 = OS_PORT_REQ;
end else begin
curr_buff2_next = curr_buff2_plus_1;
end
end else begin
curr_buff2_next = curr_buff2_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass2 = pb_bypass2;
out_req2 = 1;
if(out_ack2) begin
os_state_next2 = OS_TX;
end
end
OS_TX: begin
out_req2 = 1;
if(pb_out_req[curr_buff2]) begin
tx_in_progress2 = 1;
pb_out_ack[curr_buff2] = 1;
end else begin
tx_in_progress2 = 0;
os_state_next2 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req2 = 0;
if(!out_ack2) begin
pb_out_ack[curr_buff2] = 0;
os_state_next2 = OS_IDLE;
end
end
default: begin
out_bypass2 = 0;
out_req2 = 0;
tx_in_progress2 = 0;
os_state_next2 = OS_IDLE;
end
endcase
curr_buff3_next = curr_buff3;
os_state_next3 = os_state3;
case(os_state3)
OS_IDLE: begin
out_bypass3 = 0;
out_req3 = 0;
tx_in_progress3 = 0;
os_state_next3 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req3 = 0;
if(pb_out_req[curr_buff3]) begin
if(pb_nei3 == 2'b11) begin
os_state_next3 = OS_PORT_REQ;
end else begin
curr_buff3_next = curr_buff3_plus_1;
end
end else begin
curr_buff3_next = curr_buff3_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass3 = pb_bypass3;
out_req3 = 1;
if(out_ack3) begin
os_state_next3 = OS_TX;
end
end
OS_TX: begin
out_req3 = 1;
if(pb_out_req[curr_buff3]) begin
tx_in_progress3 = 1;
pb_out_ack[curr_buff3] = 1;
end else begin
tx_in_progress3 = 0;
os_state_next3 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req3 = 0;
if(!out_ack3) begin
pb_out_ack[curr_buff3] = 0;
os_state_next3 = OS_IDLE;
end
end
default: begin
out_bypass3 = 0;
out_req3 = 0;
tx_in_progress3 = 0;
os_state_next3 = OS_IDLE;
end
endcase
end
always @(posedge clk)
begin
if(reset) begin
os_state0 <= 0;
os_state1 <= 0;
os_state2 <= 0;
os_state3 <= 0;
curr_buff0 <= 0;
curr_buff1 <= 0;
curr_buff2 <= 0;
curr_buff3 <= 0;
end else begin
os_state0 <= os_state_next0;
os_state1 <= os_state_next1;
os_state2 <= os_state_next2;
os_state3 <= os_state_next3;
curr_buff0 <= curr_buff0_next;
curr_buff1 <= curr_buff1_next;
curr_buff2 <= curr_buff2_next;
curr_buff3 <= curr_buff3_next;
if(tx_in_progress0) begin
out_data0 <= pb_out_data[curr_buff0];
out_pkt_route0 <= pb_out_pkt_route[curr_buff0];
out_wr0 <= pb_out_wr[curr_buff0];
out_bop0 <= pb_out_bop[curr_buff0];
out_eop0 <= pb_out_eop[curr_buff0];
end
if(tx_in_progress1) begin
out_data1 <= pb_out_data[curr_buff1];
out_pkt_route1 <= pb_out_pkt_route[curr_buff1];
out_wr1 <= pb_out_wr[curr_buff1];
out_bop1 <= pb_out_bop[curr_buff1];
out_eop1 <= pb_out_eop[curr_buff1];
end
if(tx_in_progress2) begin
out_data2 <= pb_out_data[curr_buff2];
out_pkt_route2 <= pb_out_pkt_route[curr_buff2];
out_wr2 <= pb_out_wr[curr_buff2];
out_bop2 <= pb_out_bop[curr_buff2];
out_eop2 <= pb_out_eop[curr_buff2];
end
if(tx_in_progress3) begin
out_data3 <= pb_out_data[curr_buff3];
out_pkt_route3 <= pb_out_pkt_route[curr_buff3];
out_wr3 <= pb_out_wr[curr_buff3];
out_bop3 <= pb_out_bop[curr_buff3];
out_eop3 <= pb_out_eop[curr_buff3];
end
end
end
assign pb_out_rdy0 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b000) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b000) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b000) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b000) ? out_rdy3 : 0 ;
assign pb_out_rdy1 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b001) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b001) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b001) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b001) ? out_rdy3 : 0 ;
assign pb_out_rdy2 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b010) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b010) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b010) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b010) ? out_rdy3 : 0 ;
assign pb_out_rdy3 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b011) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b011) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b011) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b011) ? out_rdy3 : 0 ;
assign pb_out_rdy4 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b100) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b100) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b100) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b100) ? out_rdy3 : 0 ;
assign pb_out_rdy5 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b101) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b101) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b101) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b101) ? out_rdy3 : 0 ;
//assign pb_out_rdy6 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b110) ? out_rdy0 :
// (tx_in_progress1 == 1'b1 && curr_buff1 == 3'b110) ? out_rdy1 :
// (tx_in_progress2 == 1'b1 && curr_buff2 == 3'b110) ? out_rdy2 :
// (tx_in_progress3 == 1'b1 && curr_buff3 == 3'b110) ? out_rdy3 : 0 ;
//assign pb_out_rdy7 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b111) ? out_rdy0 :
// (tx_in_progress1 == 1'b1 && curr_buff1 == 3'b111) ? out_rdy1 :
// (tx_in_progress2 == 1'b1 && curr_buff2 == 3'b111) ? out_rdy2 :
// (tx_in_progress3 == 1'b1 && curr_buff3 == 3'b111) ? out_rdy3 : 0 ;
assign TRIG0[0] = pb_out_wr0;
assign TRIG0[1] = pb_out_req0;
assign TRIG0[2] = pb_out_ack0;
assign TRIG0[4:3] = pb_out_neighbor0;
assign TRIG0[5] = pb_out_bop0;
assign TRIG0[6] = pb_out_eop0;
assign TRIG0[7] = pb_out_rdy0;
assign TRIG0[8] = pb_out_bypass0;
assign TRIG0[10] = pb_out_wr1;
assign TRIG0[11] = pb_out_req1;
assign TRIG0[12] = pb_out_ack1;
assign TRIG0[14:13] = pb_out_neighbor1;
assign TRIG0[15] = pb_out_bop1;
assign TRIG0[16] = pb_out_eop1;
assign TRIG0[17] = pb_out_rdy1;
assign TRIG0[18] = pb_out_bypass1;
assign TRIG0[20] = pb_out_wr2;
assign TRIG0[21] = pb_out_req2;
assign TRIG0[22] = pb_out_ack2;
assign TRIG0[24:23] = pb_out_neighbor2;
assign TRIG0[25] = pb_out_bop2;
assign TRIG0[26] = pb_out_eop2;
assign TRIG0[27] = pb_out_rdy2;
assign TRIG0[28] = pb_out_bypass2;
assign TRIG0[30] = pb_out_wr3;
assign TRIG0[31] = pb_out_req3;
assign TRIG0[32] = pb_out_ack3;
assign TRIG0[34:33] = pb_out_neighbor3;
assign TRIG0[35] = pb_out_bop3;
assign TRIG0[36] = pb_out_eop3;
assign TRIG0[37] = pb_out_rdy3;
assign TRIG0[38] = pb_out_bypass3;
assign TRIG0[40] = pb_out_wr4;
assign TRIG0[41] = pb_out_req4;
assign TRIG0[42] = pb_out_ack4;
assign TRIG0[44:43] = pb_out_neighbor4;
assign TRIG0[45] = pb_out_bop4;
assign TRIG0[46] = pb_out_eop4;
assign TRIG0[47] = pb_out_rdy4;
assign TRIG0[48] = pb_out_bypass4;
assign TRIG0[50] = pb_out_wr5;
assign TRIG0[51] = pb_out_req5;
assign TRIG0[52] = pb_out_ack5;
assign TRIG0[54:53] = pb_out_neighbor5;
assign TRIG0[55] = pb_out_bop5;
assign TRIG0[56] = pb_out_eop5;
assign TRIG0[57] = pb_out_rdy5;
assign TRIG0[58] = pb_out_bypass5;
assign TRIG0[60] = out_wr3;
assign TRIG0[61] = out_req3;
assign TRIG0[62] = out_ack3;
assign TRIG0[63] = out_bop3;
assign TRIG0[64] = out_eop3;
assign TRIG0[65] = out_rdy3;
assign TRIG0[66] = out_bypass3;
assign TRIG0[67] = tx_in_progress0;
assign TRIG0[68] = tx_in_progress1;
assign TRIG0[69] = tx_in_progress2;
assign TRIG0[70] = tx_in_progress3;
assign TRIG0[73:71] = curr_buff3;
assign TRIG0[76:74] = curr_buff0;
assign TRIG0[79:77] = curr_buff2;
assign TRIG0[82:80] = curr_buff1;
assign TRIG0[92:90] = os_state0;
assign TRIG0[95:93] = os_state1;
assign TRIG0[98:96] = os_state2;
assign TRIG0[101:99] = os_state3;
assign TRIG0[173:110] = out_data3;
endmodule
|
// MBT 11/9/2014
// DWP 5/9/2020
//
// 1 read-port, 1 write-port ram with a onehot address scheme
//
// reads are asynchronous
//
`include "bsg_defines.v"
module bsg_mem_1r1w_one_hot #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter safe_els_lp=`BSG_MAX(els_p,1)
)
(input w_clk_i
// Currently unused
, input w_reset_i
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input [width_p-1:0] w_data_i
// one or zero-hot
, input [safe_els_lp-1:0] r_v_i
, output logic [width_p-1:0] r_data_o
);
logic [safe_els_lp-1:0][width_p-1:0] data_r;
wire unused0 = w_reset_i;
for (genvar i = 0; i < els_p; i++)
begin : mem_array
bsg_dff_en
#(.width_p(width_p))
mem_reg
(.clk_i(w_clk_i)
,.en_i(w_v_i[i])
,.data_i(w_data_i)
,.data_o(data_r[i])
);
end
bsg_mux_one_hot
#(.width_p(width_p)
,.els_p(safe_els_lp)
)
one_hot_sel
(.data_i(data_r)
,.sel_one_hot_i(r_v_i)
,.data_o(r_data_o)
);
//synopsys translate_off
initial
begin
if (width_p*els_p >= 64)
$display("## %L: instantiating width_p=%d, els_p=%d (%m)"
,width_p,els_p);
end
always_ff @(negedge w_clk_i)
begin
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(w_v_i) <= 1)
else $error("Invalid write address %b to %m is not onehot (w_reset_i=%b)\n", w_v_i, w_reset_i);
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(r_v_i) <= 1)
else $error("Invalid read address %b to %m is not onehot (w_reset_i=%b)\n", r_v_i, w_reset_i);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_one_hot)
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the 2-bit pipe
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "pipe2.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipe2();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the 2-bit pipe
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] op; // Output signal out
// Declare "reg" signals: inputs to the DUT
reg [1:0] ip; // Input signal - in
reg clk; // Input signal - clock
reg rst; // Input signal - reset
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pp"
*/
pipeline_buffer_2bit pp (
// instance_name(signal name),
// Signal name can be the same as the instance name
ip,op,clk,rst);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clk = 0;
#5 clk = 1;
// Period = 10 ns
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
ip = 2'd0;
rst = 1'd0;
// @t=9,
#9
ip = 2'd1;
rst = 1'd0;
// @t=19,
#10
ip = 2'd0;
rst = 1'd0;
// @t=29,
#10
ip = 2'd2;
rst = 1'd0;
// @t=39,
#10
ip = 2'd1;
rst = 1'd0;
// @t=49,
#10
ip = 2'd3;
rst = 1'd0;
// @t=59,
#10
ip = 2'd0;
rst = 1'd0;
// @t=69,
#10
ip = 2'd1;
rst = 1'd0;
// @t=79,
#10
ip = 2'd0;
rst = 1'd0;
// @t=89,
#10
ip = 2'd1;
rst = 1'd0;
// @t=99,
#10
ip = 2'd0;
rst = 1'd0;
// @t=109,
#10
ip = 2'd3;
rst = 1'd0;
// @t=119,
#10
ip = 2'd0;
rst = 1'd0;
// @t=129,
#10
ip = 2'd1;
rst = 1'd0;
// @t=139,
#10
ip = 2'd0;
rst = 1'd0;
// @t=149,
#10
ip = 2'd1;
rst = 1'd0;
// @t=159,
#10
ip = 2'd2;
rst = 1'd0;
// @t=169,
#10
ip = 2'd1;
rst = 1'd0;
// @t=179,
#10
ip = 2'd0;
rst = 1'd0;
// @t=189,
#10
ip = 2'd2;
rst = 1'd0;
// @t=199,
#10
ip = 2'd0;
rst = 1'd0;
// @t=209,
#10
ip = 2'd3;
rst = 1'd0;
// @t=219,
#10
ip = 2'd3;
rst = 1'd0;
// @t=229,
#10
ip = 2'd1;
rst = 1'd0;
// @t=239,
#10
ip = 2'd2;
rst = 1'd0;
// @t=249,
#10
ip = 2'd1;
rst = 1'd0;
// @t=259,
#10
ip = 2'd0;
rst = 1'd0;
// @t=269,
#10
ip = 2'd1;
rst = 1'd0;
// @t=279,
#10
ip = 2'd2;
rst = 1'd1;
// @t=289,
#10
ip = 2'd1;
rst = 1'd0;
// @t=299,
#10
ip = 2'd0;
rst = 1'd0;
// @t=309,
#10
ip = 2'd2;
rst = 1'd0;
// @t=319,
#10
ip = 2'd1;
rst = 1'd0;
// @t=329,
#10
ip = 2'd0;
rst = 1'd0;
// @t=339,
#10
ip = 2'd2;
rst = 1'd0;
// @t=349,
#10
ip = 2'd0;
rst = 1'd0;
// @t=359,
#10
ip = 2'd3;
rst = 1'd0;
// @t=369,
#10
ip = 2'd1;
rst = 1'd0;
// @t=379,
#10
ip = 2'd2;
rst = 1'd0;
// @t=389,
#10
ip = 2'd1;
rst = 1'd0;
// @t=399,
#10
ip = 2'd0;
rst = 1'd0;
// @t=409,
#10
ip = 2'd1;
rst = 1'd0;
// @t=419,
#10
ip = 2'd2;
rst = 1'd0;
// @t=429,
#10
ip = 2'd1;
rst = 1'd0;
// @t=439,
#10
ip = 2'd3;
rst = 1'd0;
// @t=449,
#10
ip = 2'd1;
rst = 1'd0;
// @t=459,
#10
ip = 2'd0;
rst = 1'd0;
// @t=469,
#10
ip = 2'd2;
rst = 1'd0;
// @t=479,
#10
ip = 2'd0;
rst = 1'd0;
// @t=489,
#10
ip = 2'd0;
rst = 1'd0;
// @t=499,
#10
ip = 2'd0;
rst = 1'd0;
// @t=509,
#10
ip = 2'd0;
rst = 1'd0;
// @t=519,
#10
ip = 2'd2;
rst = 1'd0;
// @t=529,
#10
ip = 2'd1;
rst = 1'd0;
// @t=539,
#10
ip = 2'd0;
rst = 1'd0;
// @t=549,
#10
ip = 2'd1;
rst = 1'd0;
// @t=559,
#10
ip = 2'd3;
rst = 1'd0;
// @t=569,
#10
ip = 2'd1;
rst = 1'd0;
// @t=579,
#10
ip = 2'd1;
rst = 1'd0;
// @t=589,
#10
ip = 2'd0;
rst = 1'd0;
// @t=599,
#10
ip = 2'd1;
rst = 1'd0;
// @t=609,
#10
ip = 2'd0;
rst = 1'd0;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_autostart (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
Require Import List.
Require Import Classical.
Section election_spec.
(** For this section, we hold the set of candidates abstract,
and define ballots and some properties of ballots irrespective
of how candidates are defined.
*)
Variable candidate:Set.
(** Voters cast votes, which consist of a sequence of rank positions.
For each rank position, a voter selects 0 or more candidates.
A properly cast vote will have (1) no more than one candidate selected
at each rank, (2) each candidate selected at most once, and (3) no
candidate selected at a rank position later than a rank position with
zero candidates. However, voters do not always follow the rules;
voters may select more than one candidate at a given rank, may select
the same candidate more than once, or may skip rankings.
The vote tabulation system must handle these cases.
*)
Definition rankSelection := list candidate.
Definition ballot := list rankSelection.
Definition election := list ballot.
Definition contestants := list candidate.
Section ballot_properties.
(** At any given round of a tabulation, some collection of candidates
have been eliminated. The following definitions are all defined
with respect to the candidates that have been eliminated thus far.
The abstract 'eliminated' predicate indicates which candidates are
already eliminated.
*)
Variable eliminated : candidate -> Prop.
(** One condition for a ballot to be exhausted is that it
all the candidates it selects have already been eliminated.
This vacuously covers the case of an empty ballot.
*)
Definition no_viable_candidates (b:ballot) :=
forall rank, In rank b ->
forall candidate, In candidate rank ->
eliminated candidate.
(** From a given ballot, find the first rank selection
(if it exists) which contains at least one
continuing candidate.
*)
Definition overvote (r : rankSelection) :=
exists c1 c2, In c1 r /\ In c2 r /\ c1 <> c2.
Inductive next_ranking : ballot -> rankSelection -> Prop :=
| next_ranking_eliminated : forall b r r',
Forall eliminated r' ->
~overvote r' ->
next_ranking b r ->
next_ranking (r' :: b) r
| next_ranking_valid : forall b r c,
In c r ->
(overvote r \/ ~eliminated c) ->
next_ranking (r :: b) r.
Definition properly_selects r c :=
Forall (eq c) r /\ In c r /\ ~eliminated c.
Definition does_not_select r :=
r = nil \/ (exists c, Forall (eq c) r /\ In c r /\ eliminated c).
Lemma not_overvote_cons :
forall h t,
~overvote (h :: t) ->
Forall (eq h) t /\ ~overvote t.
Proof.
induction t; intros.
- split.
+ constructor.
+ intro. unfold overvote in H0.
destruct H0. destruct H0.
intuition.
-split.
+ constructor.
destruct (classic (h = a)).
* auto.
* exfalso.
apply H.
unfold overvote.
exists h. exists a. intuition.
* unfold overvote in H.
apply IHt.
intro.
apply H.
clear H.
destruct H0.
destruct H.
exists x. exists x0.
simpl in *. intuition.
+ intuition.
apply H; clear H.
unfold overvote in H0.
destruct H0.
destruct H.
destruct H.
destruct H0.
unfold overvote.
exists x. exists x0.
intuition.
Qed.
Lemma not_overvote_all_same :
forall r c,
~overvote r ->
In c r ->
Forall (eq c) r.
Proof.
induction r; intros.
- inversion H0.
- apply not_overvote_cons in H.
intuition. destruct H0. subst.
rewrite Forall_forall. intros. simpl in *.
intuition. assert (In x r) by auto.
eapply IHr in H0; eauto.
rewrite Forall_forall in *.
specialize (H0 x).
specialize (H1 x). intuition.
constructor; intuition.
rewrite Forall_forall in H1. specialize (H1 c).
intuition.
Qed.
Lemma ranking_cases : forall r,
overvote r \/ (exists c, properly_selects r c) \/ does_not_select r.
intros.
destruct r.
- right. right. left. auto.
- destruct (classic (overvote (c :: r))).
+ auto.
+ right. destruct (classic (eliminated c)).
* right. right. exists c. simpl. intuition.
apply not_overvote_all_same; simpl; auto.
* left. exists c. repeat split; auto.
apply not_overvote_all_same; simpl; auto.
simpl; auto.
Qed.
Lemma next_ranking_not_not_selects : forall b r,
next_ranking b r ->
~does_not_select r.
Proof.
intros.
induction H.
- auto.
- intro.
unfold does_not_select in *.
destruct H1. subst. elim H.
destruct H1.
destruct H1.
rewrite Forall_forall in H1.
apply H1 in H. subst. intuition.
unfold overvote in *.
destruct H2. destruct H0. intuition. apply H5. transitivity c; eauto.
symmetry. eauto.
Qed.
Lemma next_ranking_spec : forall b r,
next_ranking b r ->
overvote r \/ (exists c, properly_selects r c).
Proof.
intros.
destruct (ranking_cases r); intuition.
apply next_ranking_not_not_selects in H.
intuition.
Qed.
(** TODO: Do we need a notion of overvote for a ballot any more?
A ballot is an overvote if its next ranking contains
two distinct candidates.
*)
(* Definition overvote (b:ballot) : Prop :=
exists r, next_ranking b r /\
exists c1 c2, In c1 r /\ In c2 r /\ c1 <> c2.*)
(** A ballot is exhausted if it selects no vaiable candidates
or is an overvote
*)
Definition exhausted_ballot (b:ballot) :=
(~ exists r, next_ranking b r ) \/
(exists r, next_ranking b r /\ overvote r).
Ltac inv H := inversion H; subst; clear H.
Lemma next_ranking_unique : forall b r1 r2,
next_ranking b r1 ->
next_ranking b r2 ->
r1= r2.
Proof.
intros.
induction b.
inversion H.
inv H; inv H0; try rewrite Forall_forall in *; firstorder.
Qed.
Lemma exhausted_ballot_next_ranking_iff : forall (b : ballot),
exhausted_ballot b <-> forall r, next_ranking b r -> overvote r.
Proof.
intros.
split; intros.
- unfold exhausted_ballot in H.
intuition. exfalso.
apply H1. exists r. auto.
destruct H1. destruct H. eapply next_ranking_unique in H0; eauto.
subst; auto.
- unfold exhausted_ballot.
destruct (classic (exists r, next_ranking b r)).
destruct H0. right.
exists x. auto.
left. auto.
Qed.
Definition continuing_ballot (b:ballot) :=
~exhausted_ballot b.
(** A ballot selects a particular candidate iff it is a
continuing ballot and its next ranking contains that
candidate.
*)
Definition selected_candidate (b:ballot) (c:candidate) :=
continuing_ballot b /\
exists r, next_ranking b r /\ In c r.
(** If a candidate receives a majority of the first choices, that
candidate shall be declared elected.*)
Inductive first_choices (c : candidate) : election -> nat -> Prop :=
| first_choices_nil : first_choices c nil 0
| first_choices_selected : forall h t n', selected_candidate h c ->
first_choices c t n' ->
first_choices c (h::t) (S n')
| first_choices_not_selected : forall h t n, ~selected_candidate h c ->
first_choices c t n ->
first_choices c (h::t) n.
Lemma sf_first_choices_unique : forall e c n1 n2,
first_choices c e n1 ->
first_choices c e n2 ->
n1 = n2.
Proof.
induction e.
* intros. inversion H. inversion H0. auto.
* intros.
inversion H; clear H; subst;
inversion H0; clear H0; subst; try contradiction.
f_equal; eauto.
eauto.
Qed.
Lemma sf_first_choices_total : forall e c, exists n,
first_choices c e n.
Proof.
induction e.
* intros. exists 0. apply first_choices_nil.
* intros.
destruct (IHe c) as [n ?].
destruct (classic (selected_candidate a c)).
exists (S n). apply first_choices_selected; auto.
exists n. apply first_choices_not_selected; auto.
Qed.
Inductive total_selected : election -> nat -> Prop :=
| total_nil : total_selected nil 0
| total_continuing : forall b e' n, continuing_ballot b ->
total_selected e' n ->
total_selected (b :: e') (S n)
| total_exhausted : forall b e' n, exhausted_ballot b ->
total_selected e' n ->
total_selected (b :: e') (n).
Lemma total_selected_total : forall e,
exists n, total_selected e n.
Proof.
induction e; intros.
- exists 0; constructor.
- destruct IHe.
destruct (classic (exhausted_ballot a)).
+ exists x; constructor; auto.
+ exists (S x). apply total_continuing; auto.
Qed.
Lemma total_selected_unique : forall e v v',
total_selected e v ->
total_selected e v' ->
v= v'.
Proof.
intros.
revert v v' H H0.
induction e; intros.
* inversion H; inversion H0; auto.
* inversion H; inversion H0; subst; auto.
elim H3; auto.
elim H8; auto.
Qed.
Definition majority (e : election) (winner : candidate) :=
forall total_votes winner_votes,
total_selected e total_votes ->
first_choices winner e winner_votes ->
(winner_votes * 2) > total_votes.
(** If no candidate receives a
majority, the candidate who received the fewest first choices shall be
eliminated and each vote cast for that candidate shall be transferred to
the next ranked candidate on that voter's ballot. *)
Definition participates (c:candidate) (e:election) :=
exists b, In b e /\ exists r, In r b /\ In c r.
Definition viable_candidate (e:election) (c:candidate) :=
~eliminated c /\ participates c e.
Definition is_loser (e:election) (loser:candidate) :=
viable_candidate e loser /\
forall c' n m,
viable_candidate e c' ->
first_choices loser e n ->
first_choices c' e m ->
n <= m.
Definition no_majority (e : election) :=
~(exists c, majority e c).
(** Every ballot selects at most one candidate.
*)
Lemma selected_candidate_unique (b:ballot) (c1 c2:candidate) :
selected_candidate b c1 ->
selected_candidate b c2 ->
c1 = c2.
Proof.
unfold selected_candidate.
intros [Hb [r1 [??]]].
intros [_ [r2 [??]]].
assert (r1 = r2) by (apply (next_ranking_unique b); auto).
subst r2.
destruct (classic (c1=c2)); auto.
elim Hb. red. right. firstorder.
Qed.
(**
What to do if a ballot has multiple choices for a rank, but all
have already been eliminated? Shall the ballot be deemed exhausted,
or will we continue to consider later choices?
E.g.,
A
B, C
D
Suppose both B and C were eliminated in earlier rounds, but
A is not eliminated. We should count this ballot as a vote
for A. Suppose, in a subsequent round, A is also eliminated.
Now, should this ballot be considered an overvote and removed;
or should it count as a vote for D? The statue language is
unclear.
However, actual practice seems to be that a ballot is decared an overvote
as soon as the first ranking with more than one selection becomse relevant;
i.e., when all properly-selected candidates above it have been eliminated.
In other words, the ballot is considered to be truncated at the position
of the first ranking with more than one selection.
The formal specification above follows suit, and counts this situation
as an overvote as soon as A is eliminated.
*)
(** Whenever a ballot selects a candidate, that candidate is not eliminated.
*)
Lemma selected_candidate_not_eliminated (b:ballot) :
forall c, selected_candidate b c -> ~eliminated c.
Proof.
induction b.
unfold selected_candidate. intros c [Hc [r [??]]]. inv H.
unfold selected_candidate. intros c [Hc [r [??]]]. inv H.
* apply IHb. split; eauto.
red; intro.
apply Hc.
destruct H.
elim H; eauto.
destruct H as [r' [??]].
right. exists r'. split; auto.
apply next_ranking_eliminated; auto.
* intro Helim.
elim Hc. red.
right. exists r. split; auto.
eapply next_ranking_valid; eauto.
destruct H5; auto.
red. exists c. exists c0. intuition.
subst c0. contradiction.
Qed.
(* The next ranking for a ballot is in the ballot. *)
Lemma next_ranking_in_ballot (b:ballot) :
forall r, next_ranking b r -> In r b.
Proof.
intros r H. induction H; intuition; eauto.
Qed.
End ballot_properties.
Definition update_eliminated (eliminated : candidate -> Prop) (c : candidate) :=
fun cs => eliminated cs \/ c = cs.
Inductive winner :
election -> (candidate -> Prop) -> candidate -> Prop :=
| winner_now : forall election winning_candidate eliminated,
majority eliminated election winning_candidate ->
winner election eliminated winning_candidate
| winner_elimination : forall election winning_candidate eliminated loser,
no_majority eliminated election ->
is_loser eliminated election loser ->
let eliminated' := update_eliminated eliminated loser in
winner election eliminated' winning_candidate ->
winner election eliminated winning_candidate.
End election_spec.
(**
SAN FRANCISCO CHARTER
[Obtained from-- http://www.amlegal.com/library/ca/sfrancisco.shtml on
June 13, 2015.]
ARTICLE XIII: ELECTIONS
SEC. 13.102. INSTANT RUNOFF ELECTIONS.
(a) For the purposes of this section: (1) a candidate shall be deemed
"continuing" if the candidate has not been eliminated; (2) a ballot
shall be deemed "continuing" if it is not exhausted; and (3) a ballot
shall be deemed "exhausted," and not counted in further stages of the
tabulation, if all of the choices have been eliminated or there are no
more choices indicated on the ballot. If a ranked-choice ballot gives
equal rank to two or more candidates, the ballot shall be declared
exhausted when such multiple rankings are reached. If a voter casts a
ranked-choice ballot but skips a rank, the voter's vote shall be
transferred to that voter's next ranked choice.
(b) The Mayor, Sheriff, District Attorney, City Attorney, Treasurer,
Assessor-Recorder, Public Defender, and members of the Board of
Supervisors shall be elected using a ranked-choice, or "instant runoff,"
ballot. The ballot shall allow voters to rank a number of choices in
order of preference equal to the total number of candidates for each
office; provided, however, if the voting system, vote tabulation system
or similar or related equipment used by the City and County cannot
feasibly accommodate choices equal to the total number of candidates
running for each office, then the Director of Elections may limit the
number of choices a voter may rank to no fewer than three. The ballot
shall in no way interfere with a voter's ability to cast a vote for a
write-in candidate.
(c) If a candidate receives a majority of the first choices, that
candidate shall be declared elected. If no candidate receives a
majority, the candidate who received the fewest first choices shall be
eliminated and each vote cast for that candidate shall be transferred to
the next ranked candidate on that voter's ballot. If, after this
transfer of votes, any candidate has a majority of the votes from the
continuing ballots, that candidate shall be declared elected.
(d) If no candidate receives a majority of votes from the continuing
ballots after a candidate has been eliminated and his or her votes have
been transferred to the next-ranked candidate, the continuing candidate
with the fewest votes from the continuing ballots shall be eliminated.
All votes cast for that candidate shall be transferred to the next-
ranked continuing candidate on each voter's ballot. This process of
eliminating candidates and transferring their votes to the next-ranked
continuing candidates shall be repeated until a candidate receives a
majority of the votes from the continuing ballots.
(e) If the total number of votes of the two or more candidates credited
with the lowest number of votes is less than the number of votes
credited to the candidate with the next highest number of votes, those
candidates with the lowest number of votes shall be eliminated
simultaneously and their votes transferred to the next-ranked continuing
candidate on each ballot in a single counting operation.
(f) A tie between two or more candidates shall be resolved in accordance
with State law.
(g) The Department of Elections shall conduct a voter education campaign
to familiarize voters with the ranked-choice or, "instant runoff,"
method of voting.
(h) Any voting system, vote tabulation system, or similar or related
equipment acquired by the City and County shall have the capability to
accommodate this system of ranked-choice, or "instant runoff,"
balloting.
(i) Ranked choice, or "instant runoff," balloting shall be used for the
general municipal election in November 2002 and all subsequent
elections. If the Director of Elections certifies to the Board of
Supervisors and the Mayor no later than July 1, 2002 that the Department
will not be ready to implement ranked-choice balloting in November 2002,
then the City shall begin using ranked-choice, or "instant runoff,"
balloting at the November 2003 general municipal election.
If ranked-choice, or "instant runoff," balloting is not used in November
of 2002, and no candidate for any elective office of the City and
County, except the Board of Education and the Governing Board of the
Community College District, receives a majority of the votes cast at an
election for such office, the two candidates receiving the most votes
shall qualify to have their names placed on the ballot for a runoff
election held on the second Tuesday in December of 2002.
*)
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Thu Jan 29 12:11:50 2015"
module reg_16bit(
clk,
Load,
not_reset,
D,
Q
);
input wire clk;
input wire not_reset;
input wire Load;
input wire [15:0] D;
output wire [15:0] Q;
reg [15:0] Q_ALTERA_SYNTHESIZED;
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[15] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[15] <= D[15];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[14] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[14] <= D[14];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[5] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[5] <= D[5];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[4] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[4] <= D[4];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[3] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[3] <= D[3];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[2] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[2] <= D[2];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[1] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[1] <= D[1];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[0] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[0] <= D[0];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[13] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[13] <= D[13];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[12] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[12] <= D[12];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[11] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[11] <= D[11];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[10] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[10] <= D[10];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[9] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[9] <= D[9];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[8] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[8] <= D[8];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[7] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[7] <= D[7];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[6] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[6] <= D[6];
end
end
assign Q = Q_ALTERA_SYNTHESIZED;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO1P_FUNCTIONAL_PP_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_FUNCTIONAL_PP_V |
module alu(clock, pc, insn, rsData, rtData, saData, immSXData, ALUOp, dataOut, branch_taken, enable_execute, dm_we, dm_access_size, rw_d);
/****************OPCODES******************/
// R-Type FUNC Codes
parameter ADD = 6'b100000; //ADD;
parameter ADDU = 6'b100001; //ADDU;
parameter SUB = 6'b100010; //SUB;
parameter SUBU = 6'b100011; //SUBU;
parameter MULT = 6'b011000; //MULT;
parameter MULTU = 6'b011001; //MULTU;
parameter DIV = 6'b011010; //DIV;
parameter DIVU = 6'b011011; //DIVU;
parameter MFHI = 6'b010000; //MFHI;
parameter MFLO = 6'b010010; //MFLO;
parameter SLT = 6'b101010; //SLT;
parameter SLTU = 6'b101011; //SLTU;
parameter SLL = 6'b000000; //SLL;
parameter SLLV = 6'b000100; //SLLV;
parameter SRL = 6'b000010; //SRL;
parameter SRLV = 6'b000110; //SRLV;
parameter SRA = 6'b000011; //SRA;
parameter SRAV = 6'b000111; //SRAV;
parameter AND = 6'b100100; //AND;
parameter OR = 6'b100101; //OR;
parameter XOR = 6'b100110; //XOR;
parameter NOR = 6'b100111; //NOR
parameter JALR = 6'b001001; //JALR;
parameter JR = 6'b001000; //JR;
// MUL R-TYPE Opcode
parameter MUL_OP = 6'b011100; //MUL OPCODE
parameter MUL_FUNC = 6'b000010; //MUL FUNCTION CODE
// I-Type Opcodes
parameter ADDI = 6'b001000; //ADDI (LI)
parameter ADDIU = 6'b001001; //ADDIU
parameter SLTI = 6'b001010; //SLTI
parameter SLTIU = 6'b001011; //SLTIU
parameter ORI = 6'b001101; //ORI
parameter XORI = 6'b001110; //XORI
parameter LW = 6'b100011; //LW
parameter SW = 6'b101011; //SW
parameter LB = 6'b100000; //LB
parameter LUI = 6'b001111; //LUI
parameter SB = 6'b101000; //SB
parameter LBU = 6'b100100; //LBU
parameter BEQ = 6'b000100; //BEQ
parameter BNE = 6'b000101; //BNE
parameter BGTZ = 6'b000111; //BGTZ
parameter BLEZ = 6'b000110; //BLEZ
// REGIMM Opcodes
parameter BLTZ = 5'b00000; // BLTZ
parameter BGEZ = 5'b00001; // BGEZ
// J-Type Opcodes
parameter J = 6'b000010;
parameter JAL = 6'b000011;
// Other
parameter NOP = 32'h000000;
parameter RTYPE = 6'b000000;
/******************************************/
input clock;
input [31:0] pc, insn, rsData, rtData;
input [4:0] saData;
input [31:0] immSXData;
input [5:0] ALUOp;
input wire enable_execute;
reg [63:0] temp;
reg [31:0] hi;
reg [31:0] lo;
output reg [31:0] dataOut;
output reg branch_taken;
output reg dm_we; // data memory write enable maps to we in memory module
output reg rw_d;
output reg dm_access_size;
always @(ALUOp, rsData, rtData)
begin : EXECUTE
if (enable_execute == 1) begin
branch_taken = 0;
if(insn[31:26] == RTYPE) begin
case (ALUOp)
ADD: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + rtData;
rw_d = 0;
dm_we = 0;
end
ADDU: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + rtData;
rw_d = 0;
dm_we = 0;
end
SUB: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData - rtData;
rw_d = 0;
dm_we = 0;
end
SUBU: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData - rtData;
rw_d = 0;
dm_we = 0;
end
MUL_FUNC: begin
temp = rsData * rtData;
dataOut = temp[31:0];
end
DIV: begin
temp = rsData / rtData;
hi = temp[63:32]; // remainder
lo = temp[31:0]; // quotient
end
DIVU: begin
temp = rsData / rtData;
hi = temp[63:32]; // remainder
lo = temp[31:0]; // quotient
end
MFHI: begin
dataOut = hi;
end
MFLO: begin
dataOut = lo;
end
SLT: begin
if (rsData < rtData) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
SLTU: begin
if (rsData < rtData) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
SLL: begin
dataOut = rtData << saData;
end
SLLV: begin
dataOut = rtData << rsData;
end
SRL: begin
dataOut = rtData >> saData;
end
SRLV: begin
dataOut = rtData >> rsData;
end
SRA: begin
dataOut = rtData >>> saData;
end
SRAV: begin
dataOut = rtData >>> rsData;
end
AND: begin
dataOut = rsData & rtData;
end
OR: begin
dataOut = rsData | rtData;
end
XOR: begin
dataOut = rsData ^ rtData;
end
NOR: begin
dataOut = ~(rsData | rtData);
end
JR: begin
dataOut = rsData;
branch_taken = 1;
end
JALR: begin
dataOut = (pc + 8);
//pc_out_execute = rsData
branch_taken = 1;
end
endcase
end else if (insn[31:26] != 6'b000000 && insn[31:27] != 5'b00001 && insn[31:26] != 6'b000001) begin
case (ALUOp)
ADDI: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + immSXData[15:0];
rw_d = 0;
dm_we = 0;
end
ADDIU: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + immSXData[15:0];
rw_d = 0;
dm_we = 0;
end
SLTI: begin
if (rsData < immSXData[15:0]) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
SLTIU: begin
if (rsData < immSXData[15:0]) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
ORI: begin
dataOut = rsData | immSXData[15:0];
end
XORI: begin
dataOut = rsData ^ immSXData[15:0];
end
LW: begin
// TODO: MEMTYPE
dm_we = 0; //read from memory
dm_access_size = 2'b0_0; // 1 WORD
rw_d = 1;
// rt <= MEM[rs + SX(imm,32)]
// dataOut MEM ADDR of data to load
// dataOut goes to input a of DMEM
// writeback mem contents at MEM[dataOut] to regfile
dataOut = rsData + immSXData[15:0];
end
SW: begin
// TODO: MEMTYPE
dm_we = 1;
dm_access_size = 2'b0_0; // 1 WORD
rw_d = 0;
// MEM[rs + SX(imm)] <= rt
// dataOut has MEM ADDR to store rt
// get rt straight from output of decode
// rt is input d of data memory
// dataOut is input a of data memory
// no writeback, disable regfile we
// store value of rt in MEM[dataOut]
dataOut = rsData + immSXData[15:0];
end
LB: begin
// TODO: MEMTYPE (modify access size)
// First get LW to work, then do this
dataOut = rsData + immSXData[15:0];
end
LUI: begin
// TODO: MEMTYPE
//dataOut = immSXData[15:0] << 16;
dataOut = {immSXData[15:0], 16'd0};
end
SB: begin
// TODO: MEMTYPE (modify access size)
dataOut = rsData + immSXData[15:0];
end
LBU: begin
// TODO: MEMTYPE
dataOut = rsData + immSXData[15:0];
end
BEQ: begin
if (rsData == rtData) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BNE: begin
if (rsData != rtData) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BGTZ: begin
if (rsData > 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BLEZ: begin
if (rsData <= 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
endcase
end else if (insn[31:26] == 6'b000001) begin
// REGIMM
case(ALUOp)
BLTZ: begin
if (rsData < 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BGEZ: begin
if (rsData >= 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
endcase
end else if (insn[31:27] == 5'b00001) begin
// J-Type
case (ALUOp)
J: begin
//
dataOut[31:28] = pc[31:28];
dataOut[27:0] = immSXData[25:0] << 2;
branch_taken = 1;
end
JAL: begin
dataOut = pc + 8;
branch_taken = 1;
end
endcase
end else if (insn == NOP) begin
dataOut = dataOut;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_TB_V
/**
* udp_dff$NR_pp$PKG$sN: Negative edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_nr_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 RESET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 RESET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 RESET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 RESET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 RESET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__udp_dff$NR_pp$PKG$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_addr_gen.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_addr_gen(/*AUTOARG*/
// Outputs
addr_err, rank_adr, stack_adr, bank_adr, ras_adr, cas_adr, addr_parity,
// Inputs
addr_in, config_reg, two_channel_mode, rank1_present, eight_bank_mode
);
input [39:4] addr_in;
input [8:0] config_reg;
input rank1_present;
input eight_bank_mode;
input two_channel_mode;
output addr_parity;
output addr_err;
output rank_adr;
output stack_adr;
output [2:0] bank_adr;
output [14:0] ras_adr;
output [13:0] cas_adr;
//////////////////////////////////////////////////////////////////
// WIRE
//////////////////////////////////////////////////////////////////
wire [14:0] ras_adr_cas12;
wire [14:0] ras_adr_cas11;
//////////////////////////////////////////////////////////////////
// Mux the RAS address
//////////////////////////////////////////////////////////////////
assign ras_adr_cas12[14:0] = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ?
{1'h0,addr_in[33:20]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[32:20]} : addr_in[34:20]) :
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[32:19]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[31:19]} : addr_in[33:19]) :
eight_bank_mode ? (
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[34:21]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[33:21]} : addr_in[35:21]) :
((config_reg[8:5] == 4'he) ?
{1'h0,addr_in[33:20]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[32:20]} : addr_in[34:20]);
assign ras_adr_cas11[14:0] = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ?
{1'h0,addr_in[32:19]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[31:19]} : addr_in[33:19]) :
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[31:18]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[30:18]} : addr_in[32:18]) :
eight_bank_mode ? (
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[33:20]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[32:20]} : addr_in[34:20]) :
((config_reg[8:5] == 4'he) ?
{1'h0,addr_in[32:19]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[31:19]} : addr_in[33:19]);
assign ras_adr[14:0] = (config_reg[4:1] == 4'hc) ? ras_adr_cas12 : ras_adr_cas11;
wire stack_adr_present = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34])) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[32] : addr_in[31]) :
((config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33])) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35])) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]));
wire stack_adr = config_reg[0] ? stack_adr_present : 1'b0;
wire rank_adr_present = two_channel_mode ? (
eight_bank_mode ? (
config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) )) :
config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[32] : addr_in[31]) :
((config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) )) :
eight_bank_mode ? (
config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
((config_reg[4:1] == 4'hc) ? addr_in[37] : addr_in[36]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) )) :
(config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) ));
wire rank_adr = rank1_present ? rank_adr_present : 1'b0;
wire [8:0] upper_addr_no_sd_no_rank = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]})) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {1'h0,addr_in[39:32]} : addr_in[39:31]) :
((config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]})) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
((config_reg[4:1] == 4'hc) ? {5'h0,addr_in[39:36]} : {4'h0,addr_in[39:35]})) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}));
wire [7:0] upper_addr_sd_or_rank = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]})) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {1'h0,addr_in[39:33]} : addr_in[39:32]) :
((config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]})) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
((config_reg[4:1] == 4'hc) ? {5'h0,addr_in[39:37]} : {4'h0,addr_in[39:36]})) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}));
wire [6:0] upper_addr_sd_and_rank = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:35]} : {1'h0,addr_in[39:34]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:37]} : {3'h0,addr_in[39:36]})) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:35]} : {1'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {1'h0,addr_in[39:34]} : addr_in[39:33]) :
((config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]})) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:37]} : {3'h0,addr_in[39:36]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]}) :
((config_reg[4:1] == 4'hc) ? {5'h0,addr_in[39:38]} : {4'h0,addr_in[39:37]})) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:35]} : {1'h0,addr_in[39:34]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:37]} : {3'h0,addr_in[39:36]}));
wire [8:0] upper_addr =
(rank1_present & config_reg[0]) ? {upper_addr_sd_and_rank[6:0],2'b0} :
(rank1_present | config_reg[0]) ? {upper_addr_sd_or_rank[7:0],1'b0} :
upper_addr_no_sd_no_rank[8:0];
wire addr_err = |upper_addr[8:0];
//////////////////////////////////////////////////////////////////
// Mux the CAS address
//////////////////////////////////////////////////////////////////
assign cas_adr[13:0] = two_channel_mode ? (
eight_bank_mode ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]}) :
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[18:17],1'b1,addr_in[16:9],addr_in[5:4]} :
{2'h0,addr_in[17],1'b1,addr_in[16:9],addr_in[5:4]}) :
eight_bank_mode ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]});
assign bank_adr[2:0] = two_channel_mode ? (
eight_bank_mode ? addr_in[9:7] ^ addr_in[20:18] ^ addr_in[30:28] :
config_reg[0] ? { stack_adr, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] } :
rank1_present ? {rank_adr, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] } :
{1'b0, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] }) :
(eight_bank_mode ? addr_in[10:8] ^ addr_in[20:18] ^ addr_in[30:28] :
config_reg[0] ? { stack_adr, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28]} :
rank1_present ? {rank_adr, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28] } :
{1'b0, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28] });
wire addr_parity = two_channel_mode ? ^(addr_in[39:7]) : ^(addr_in[39:8]);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/rtl")
// End:
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Standard functions and combinators.
* Proofs about them require functional extensionality and can be found in [Combinators].
*
* Author: Matthieu Sozeau
* Institution: LRI, CNRS UMR 8623 - UniversitÃcopyright Paris Sud
* 91405 Orsay, France *)
(* $Id$ *)
(** The polymorphic identity function. *)
Definition id {A} := fun x : A => x.
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Open Local Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Implicit Arguments prod_curry [[A] [B] [C]].
Implicit Arguments prod_uncurry [[A] [B] [C]].
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IP ethernet frame receiver (Ethernet frame in, IP frame out, 64 bit datapath)
*/
module ip_eth_rx_64
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_payload_early_termination,
output wire error_invalid_header,
output wire error_invalid_checksum
);
/*
IP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
payload length octets
This module receives an Ethernet frame with header fields in parallel and
payload on an AXI stream interface, decodes and strips the IP header fields,
then produces the header fields in parallel along with the IP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg store_hdr_word_0;
reg store_hdr_word_1;
reg store_hdr_word_2;
reg store_last_word;
reg flush_save;
reg transfer_in_save;
reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [16:0] hdr_sum_high_reg = 17'd0;
reg [16:0] hdr_sum_low_reg = 17'd0;
reg [19:0] hdr_sum_temp;
reg [19:0] hdr_sum_reg = 20'd0, hdr_sum_next;
reg check_hdr_reg = 1'b0, check_hdr_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
reg error_invalid_header_reg = 1'b0, error_invalid_header_next;
reg error_invalid_checksum_reg = 1'b0, error_invalid_checksum_next;
reg [63:0] save_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] save_eth_payload_axis_tkeep_reg = 8'd0;
reg save_eth_payload_axis_tlast_reg = 1'b0;
reg save_eth_payload_axis_tuser_reg = 1'b0;
reg [63:0] shift_eth_payload_axis_tdata;
reg [7:0] shift_eth_payload_axis_tkeep;
reg shift_eth_payload_axis_tvalid;
reg shift_eth_payload_axis_tlast;
reg shift_eth_payload_axis_tuser;
reg shift_eth_payload_s_tready;
reg shift_eth_payload_extra_cycle_reg = 1'b0;
// internal datapath
reg [63:0] m_ip_payload_axis_tdata_int;
reg [7:0] m_ip_payload_axis_tkeep_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
assign error_invalid_header = error_invalid_header_reg;
assign error_invalid_checksum = error_invalid_checksum_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
shift_eth_payload_axis_tdata[31:0] = save_eth_payload_axis_tdata_reg[63:32];
shift_eth_payload_axis_tkeep[3:0] = save_eth_payload_axis_tkeep_reg[7:4];
if (shift_eth_payload_extra_cycle_reg) begin
shift_eth_payload_axis_tdata[63:32] = 32'd0;
shift_eth_payload_axis_tkeep[7:4] = 4'd0;
shift_eth_payload_axis_tvalid = 1'b1;
shift_eth_payload_axis_tlast = save_eth_payload_axis_tlast_reg;
shift_eth_payload_axis_tuser = save_eth_payload_axis_tuser_reg;
shift_eth_payload_s_tready = flush_save;
end else begin
shift_eth_payload_axis_tdata[63:32] = s_eth_payload_axis_tdata[31:0];
shift_eth_payload_axis_tkeep[7:4] = s_eth_payload_axis_tkeep[3:0];
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = (s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_axis_tuser = (s_eth_payload_axis_tuser && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_s_tready = !(s_eth_payload_axis_tlast && s_eth_payload_axis_tvalid && transfer_in_save);
end
end
always @* begin
state_next = STATE_IDLE;
flush_save = 1'b0;
transfer_in_save = 1'b0;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
store_hdr_word_0 = 1'b0;
store_hdr_word_1 = 1'b0;
store_hdr_word_2 = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
hdr_sum_temp = 32'd0;
hdr_sum_next = hdr_sum_reg;
check_hdr_next = check_hdr_reg;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_payload_axis_tdata_int = 64'd0;
m_ip_payload_axis_tkeep_int = 8'd0;
m_ip_payload_axis_tvalid_int = 1'b0;
m_ip_payload_axis_tlast_int = 1'b0;
m_ip_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
hdr_ptr_next = 6'd0;
hdr_sum_next = 32'd0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b1;
store_eth_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
word_count_next = m_ip_length_reg - 5*4;
if (s_eth_payload_axis_tvalid) begin
// word transfer in - store it
hdr_ptr_next = hdr_ptr_reg + 6'd8;
transfer_in_save = 1'b1;
state_next = STATE_READ_HEADER;
case (hdr_ptr_reg)
6'h00: begin
store_hdr_word_0 = 1'b1;
end
6'h08: begin
store_hdr_word_1 = 1'b1;
hdr_sum_next = hdr_sum_high_reg + hdr_sum_low_reg;
end
6'h10: begin
store_hdr_word_2 = 1'b1;
hdr_sum_next = hdr_sum_reg + hdr_sum_high_reg + hdr_sum_low_reg;
// check header checksum on next cycle for improved timing
check_hdr_next = 1'b1;
if (m_ip_version_reg != 4'd4 || m_ip_ihl_reg != 4'd5) begin
error_invalid_header_next = 1'b1;
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end else begin
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
state_next = STATE_READ_PAYLOAD;
end
end
endcase
if (shift_eth_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_hdr_valid_next = 1'b0;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = shift_eth_payload_axis_tdata;
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
store_last_word = 1'b1;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
transfer_in_save = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep & count2keep(word_count_reg);
if (shift_eth_payload_axis_tlast) begin
if (keep2count(shift_eth_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
end
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
m_ip_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
if (shift_eth_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
if (check_hdr_reg) begin
check_hdr_next = 1'b0;
hdr_sum_temp = hdr_sum_reg[15:0] + hdr_sum_reg[19:16] + hdr_sum_low_reg;
if (hdr_sum_temp != 19'h0ffff && hdr_sum_temp != 19'h1fffe) begin
// bad checksum
error_invalid_checksum_next = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b0;
if (shift_eth_payload_axis_tlast && shift_eth_payload_axis_tvalid) begin
// only one payload cycle; return to idle now
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
// drop payload
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end
end else begin
// good checksum; transfer header
m_ip_hdr_valid_next = 1'b1;
end
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = last_word_data_reg;
m_ip_payload_axis_tkeep_int = last_word_keep_reg;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
m_ip_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
if (shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 1'b0;
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
error_invalid_header_reg <= 1'b0;
error_invalid_checksum_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
error_invalid_header_reg <= error_invalid_header_next;
error_invalid_checksum_reg <= error_invalid_checksum_next;
busy_reg <= state_next != STATE_IDLE;
// datapath
if (flush_save) begin
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_eth_payload_axis_tlast_reg <= s_eth_payload_axis_tlast;
shift_eth_payload_extra_cycle_reg <= s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] != 0);
end
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
hdr_sum_reg <= hdr_sum_next;
check_hdr_reg <= check_hdr_next;
if (s_eth_payload_axis_tvalid) begin
hdr_sum_low_reg <= s_eth_payload_axis_tdata[15:0] + s_eth_payload_axis_tdata[31:16];
hdr_sum_high_reg <= s_eth_payload_axis_tdata[47:32] + s_eth_payload_axis_tdata[63:48];
end
// datapath
if (store_eth_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
end
if (store_last_word) begin
last_word_data_reg <= m_ip_payload_axis_tdata_int;
last_word_keep_reg <= m_ip_payload_axis_tkeep_int;
end
if (store_hdr_word_0) begin
{m_ip_version_reg, m_ip_ihl_reg} <= s_eth_payload_axis_tdata[ 7: 0];
{m_ip_dscp_reg, m_ip_ecn_reg} <= s_eth_payload_axis_tdata[15: 8];
m_ip_length_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_length_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_identification_reg[15: 8] <= s_eth_payload_axis_tdata[39:32];
m_ip_identification_reg[ 7: 0] <= s_eth_payload_axis_tdata[47:40];
{m_ip_flags_reg, m_ip_fragment_offset_reg[12:8]} <= s_eth_payload_axis_tdata[55:48];
m_ip_fragment_offset_reg[ 7:0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_1) begin
m_ip_ttl_reg <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_protocol_reg <= s_eth_payload_axis_tdata[15: 8];
m_ip_header_checksum_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_header_checksum_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_source_ip_reg[31:24] <= s_eth_payload_axis_tdata[39:32];
m_ip_source_ip_reg[23:16] <= s_eth_payload_axis_tdata[47:40];
m_ip_source_ip_reg[15: 8] <= s_eth_payload_axis_tdata[55:48];
m_ip_source_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_2) begin
m_ip_dest_ip_reg[31:24] <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_dest_ip_reg[23:16] <= s_eth_payload_axis_tdata[15: 8];
m_ip_dest_ip_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_dest_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
end
if (transfer_in_save) begin
save_eth_payload_axis_tdata_reg <= s_eth_payload_axis_tdata;
save_eth_payload_axis_tkeep_reg <= s_eth_payload_axis_tkeep;
save_eth_payload_axis_tuser_reg <= s_eth_payload_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_ip_payload_axis_tkeep_reg = 8'd0;
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg m_ip_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_ip_payload_axis_tkeep_reg = 8'd0;
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg temp_m_ip_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_ip_payload_int_to_output;
reg store_ip_payload_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tkeep = m_ip_payload_axis_tkeep_reg;
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_ip_payload_int_to_output = 1'b0;
store_ip_payload_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_ip_payload_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_ip_payload_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule
`resetall
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: counter48
*
*/
`default_nettype none
module counter48 #(
parameter DATASIZE = 16 // width of the counter, must be <=48 bits!
) (
input wire clk,
input wire res_n,
input wire increment,
input wire [DATASIZE-1:0] load,
input wire load_enable,
output wire [DATASIZE-1:0] value
);
reg [DATASIZE-1:0] value_reg;
reg load_enable_reg;
assign value = value_reg;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if (!res_n)
begin
value_reg <= {DATASIZE{1'b0}};
load_enable_reg <= 1'b0;
end
else
begin
load_enable_reg <= load_enable;
case ({load_enable_reg,increment})
2'b00:
value_reg <= value_reg;
2'b01:
value_reg <= (value_reg + 1'b1);
2'b10:
value_reg <= {DATASIZE{1'b0}};
2'b11:
value_reg <= {DATASIZE{1'b0}} + 1'b1;
endcase
end
end
endmodule
`default_nettype wire |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_fpext_32ns_64_1
#(parameter
ID = 6,
NUM_STAGE = 1,
din0_WIDTH = 32,
dout_WIDTH = 64
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
//------------------------Instantiation------------------
HLS_accel_ap_fpext_0_no_dsp_32 HLS_accel_ap_fpext_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_2_V
`define SKY130_FD_SC_HS__O31AI_2_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_PP_V |
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// FFT - Decimation in Time
// The produced FFT is scaled down by a factor of N to prevent overflow.
// The Butterfly module that we are using assume that TF_WDTH is the same
// as X_WDTH.
// TF_WDTH must be the same as X_WDTH
module dit
#(
// Length of FFT vector.
parameter N = 16,
// Base two log of N
parameter NLOG2 = 4,
// Number of bits in vector values (double this value for a complex number).
parameter X_WDTH = 8,
// Number of bits in twiddle factor values. (must be equal to X_WDTH at the moment)
parameter TF_WDTH = 8,
// Whether to run in debug mode.
parameter DEBUGMODE = 0
)
(
// The clock signal.
input wire clk,
// Normally set to 1. Set to 0 to reset module.
input wire rst_n,
// Input value.
// Within each complex number the real part is at the low end and the complex
// at the high end.
input wire [2*X_WDTH-1:0] in_x,
// Set to 1 when new data placed in in_x.
input wire in_nd,
// Output value.
output reg [2*X_WDTH-1:0] out_x,
// Set to 1 when new data is placed in out_x.
output reg out_nd,
// Set to 1 when can't keep up with input data.
output reg overflow
);
`define MSG_DEBUG(g) if(DEBUGMODE) $display("DEBUG : %m:", g)
`define MSG_ERROR(g) $display("ERROR : %m:", g)
/******************************/
/* Define global data buffers */
/******************************/
// Input buffer.
reg [X_WDTH*2-1:0] bufferin0[N-1:0];
reg bufferin_full0_A;
reg bufferin_full0_B;
wire bufferin_full0;
assign bufferin_full0 = bufferin_full0_A + bufferin_full0_B;
reg [X_WDTH*2-1:0] bufferin1[N-1:0];
reg bufferin_full1_A;
reg bufferin_full1_B;
wire bufferin_full1;
assign bufferin_full1 = bufferin_full1_A + bufferin_full1_B;
reg bufferin_write_switch;
reg bufferin_read_switch;
wire bufferin_read_full;
wire bufferin_write_full;
assign bufferin_read_full = bufferin_read_switch?bufferin_full1:bufferin_full0;
assign bufferin_write_full = bufferin_write_switch?bufferin_full1:bufferin_full0;
// Working buffers.
reg [X_WDTH*2-1:0] bufferX[N-1:0];
reg [X_WDTH*2-1:0] bufferY[N-1:0];
// Output buffer.
reg [X_WDTH*2-1:0] bufferout[N-1:0];
// Whether the output buffer is full.
// We have two registers since they are drive by different processes.
// 'A' flips back and forth as the buffer is fulled.
// 'B' flips back and forth as the buffer is emptied.
reg bufferout_full_A;
reg bufferout_full_B;
wire bufferout_full;
assign bufferout_full = bufferout_full_A + bufferout_full_B;
// Whether the buffer contains good data. (i.e. not old)
// Data should not be read from a buffer unless the correponding
// updated value is 1.
reg [N-1:0] updatedX;
reg [N-1:0] updatedY;
/*******************************************************/
/* */
/* Define logic for receiving samples and placing in */
/* an input buffer. */
/* */
/*******************************************************/
reg [NLOG2-1:0] bufferin_addr;
initial
begin
bufferin_addr <= {NLOG2{1'b0}};
bufferin_full0_A <= 1'b0;
bufferin_full1_A <= 1'b0;
bufferin_write_switch <= 1'b0;
overflow <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
bufferin_addr <= {NLOG2{1'b0}};
bufferin_full0_A <= 1'b0;
bufferin_full1_A <= 1'b0;
bufferin_write_switch <= 1'b0;
overflow <= 1'b0;
end
else
begin
if (in_nd)
begin
// Check for overflowed data.
if (bufferin_write_full)
overflow <= 1'b1;
if (bufferin_write_switch)
bufferin1[bufferin_addr] <= in_x;
else
bufferin0[bufferin_addr] <= in_x;
bufferin_addr <= bufferin_addr + 1;
if (&bufferin_addr)
begin
bufferin_write_switch <= ~bufferin_write_switch;
if (bufferin_write_switch)
bufferin_full1_A <= ~bufferin_full1_A;
else
bufferin_full0_A <= ~bufferin_full0_A;
end
end
end
end
/*******************************************************/
/* */
/* Define logic for emitting samples from the output */
/* buffer. */
/* */
/*******************************************************/
reg [NLOG2-1:0] bufferout_addr;
initial
begin
bufferout_addr <= {NLOG2{1'b0}};
bufferout_full_B <= 1'b0;
out_nd <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
bufferout_addr <= {NLOG2{1'b0}};
bufferout_full_B <= 1'b0;
out_nd <= 1'b0;
end
else
begin
if (bufferout_full)
begin
out_x <= bufferout[bufferout_addr];
out_nd <= 1'b1;
bufferout_addr <= bufferout_addr + 1;
if (&bufferout_addr)
bufferout_full_B <= ~bufferout_full_B;
end
else
out_nd <= 1'b0;
end
end
/********************************************************/
/* */
/* Define FSM that passes data to the BF module. */
/* */
/********************************************************/
reg [1:0] fsm_state;
/* Define the control FSM states. */
localparam [1:0] FSM_ST_INIT = 0;
localparam [1:0] FSM_ST_IDLE = 1;
localparam [1:0] FSM_ST_CALC = 2;
localparam [1:0] FSM_ST_SEND = 3;
/*
Calculation that determine which positions we should read from and write to
for with the butterfly module.
If we have a series x_n that we want to get the DFT of, X_k we can write X_k in
terms of E_k and O_k where E_k and O_k are the DFTs of the even and odd components
of x_n respectively.
for k<N/2 : X_k = E_k + exp(-2*pi*i*k/N)*O_k
for k>=N/2 : X_k = E_{k-N/2} - exp(-2*pi*{k-N/2}/N)*O_{k-N/2}
We use this relationship to calculate the DFT of x_n in a series of stages. AFter the
final stage the output is X_k. After the second to last stage the output is an
interleaving of E_k and O_k.
At some general stage we have S interleaved series.
So if X_k is the j'th series in a stage and P_n is the n'th output in that stage:
X_k = P_{k*S+j}
E_k is from a stage with 2*S series and it is in the j'th series in the stage
O_k is from a stage with 2*S series and it is in the (S+j)'th series in stage
Let Q_n be the n'th output of the stage before P.
E_k = Q_{k*2*S+j}
O_k = Q_{k*2*S+S+j}
Also let T_n = exp(-2*pi*i*n/M)
M = N*S (total number of items in stage output)
P_{k*S+j} = Q_{2*k*S+j} + T_{k*S} * Q_{k*2*S+S+j}
P_{k*S+j+M/2} = Q_{2*k*S+j} - T_{k*S} * Q_{k*2*S+S+j}
We'll give these addresses names:
out0_addr = k*S+j
out1_addr = k*S+j+M/2
in0_addr = 2*k*S+j
in1_addr = 2*k*S+S+j
Now we assume we know out0_addr and try to get efficient ways to calculate the
other addresses.
out0_addr = k*S+j (j ranges from 0 to S-1, and S is a multiple of two)
If we look at out0_addr in binary the lowest log2(S) bits give the value of j
and the highest log2(N) bits give the value for k.
*/
// Number of series in the stage we are writing to.
reg [NLOG2-1:0] S;
// Contains a 1 for the bits that give j from out0_addr (i.e. which series).
reg [NLOG2-1:0] series_bits;
reg [NLOG2-1:0] out0_addr;
// Functions of the above 3 registers.
wire [NLOG2-1:0] in0_addr;
wire [NLOG2-1:0] in1_addr;
wire [NLOG2-1:0] out1_addr;
wire [NLOG2-2:0] tf_addr;
//To get in0_addr we leave the lowest log2(S) bits alone but we shift the log2(N)
//highest bits to the left (high is to left).
//To get in1_addr we add S to in0_addr.
// out1_addr = out0+addr + M/2
// We simply flip the highest bit from 0 to 1 which adds M/2.
assign out1_addr = {1'b1, out0_addr[NLOG2-2:0]};
// in0_addr = 2*k*S+j
// (out0_addr & series_bits) = j
// (out0_addr & ~series_bits) = k*S
// Since the bits don't overlap we can add them with an OR.
assign in0_addr = (out0_addr & series_bits) | ((out0_addr & ~series_bits)<<1);
assign in1_addr = in0_addr + S;
// (out0_addr & ~series_bits) = k*S
assign tf_addr = out0_addr & ~series_bits;
// Set to 1 when x_nd is set to 1 from the last BF calculation of the FFT.
reg finished;
// Which buffer we are reading from.
// 1 if we are reading from X.
// 0 if we are reading from Y.
reg readbuf_switch;
// We want readbuf_switch delayed by one step to send into the BF module.
// The is because readbuf_switch may have changed since the values being
// sent in were read.
reg readbuf_switch_old;
// Whether it is the first stage.
wire first_stage;
assign first_stage = (S == {1'b1,{NLOG2-1{1'b0}}});
// Whether it is the last stage.
wire last_stage;
assign last_stage = (S == 1);
// Inputs in to the BF module
wire [2*X_WDTH-1:0] in0;
wire [2*X_WDTH-1:0] in1;
assign in0 = first_stage?(bufferin_read_switch?bufferin1[in0_addr]:bufferin0[in0_addr]):(readbuf_switch?bufferX[in0_addr]:bufferY[in0_addr]);
assign in1 = first_stage?(bufferin_read_switch?bufferin1[in1_addr]:bufferin0[in1_addr]):(readbuf_switch?bufferX[in1_addr]:bufferY[in1_addr]);
// Whether the two inputs have been updated.
// Making sure we don't read before we have written.
wire updated0;
wire updated1;
assign updated0 = first_stage?1:(readbuf_switch?updatedX[in0_addr]:updatedY[in0_addr]);
assign updated1 = first_stage?1:(readbuf_switch?updatedX[in1_addr]:updatedY[in1_addr]);
// Set to 1 when we want the twiddle factor module to return some new
// twiddle factors.
reg tf_addr_nd;
// Tells the BF module that we are sending some data.
reg x_nd;
wire [2*TF_WDTH-1:0] tf;
initial
begin
fsm_state <= FSM_ST_INIT;
tf_addr_nd <= 1'b0;
x_nd <= 1'b0;
readbuf_switch <= 1'b0;
bufferin_read_switch <= 1'b0;
bufferin_full0_B <= 1'b0;
bufferin_full1_B <= 1'b0;
end
// Create the FSM machine
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
fsm_state <= FSM_ST_INIT;
tf_addr_nd <= 1'b0;
x_nd <= 1'b0;
readbuf_switch <= 1'b0;
bufferin_read_switch <= 1'b0;
bufferin_full0_B <= 1'b0;
bufferin_full1_B <= 1'b0;
end
else
begin
// Delay for readbuf_switch.
readbuf_switch_old <= readbuf_switch;
// Take note of when new data arrives.
case (fsm_state)
FSM_ST_INIT:
begin
// Starting a new FFT (we may not have received input data
// yet but we can still prepare.
`MSG_DEBUG("FSM_ST_INIT");
out0_addr <= 0;
// For the first stage we write to (the second stage) there
// are N/2 series.
series_bits <= {NLOG2{1'b1}} >> 1;
// There are N/2 series in that stage.
S <= {1'b1,{NLOG2-1{1'b0}}};
// Tell twiddle factor module to calculate the first
// twiddle factor.
tf_addr_nd <= 1'b1;
x_nd <= 1'b0;
finished <= 1'b0;
fsm_state <= FSM_ST_IDLE;
end // case: FSM_ST_INIT
FSM_ST_IDLE:
begin
// Copy the input data into a buffer.
// If no input data is there we wait here until receiving
// input data.
// During the first step in this state the twiddle
// factor module will update the twiddle factor.
// During the last step in this state the BF module is
// sent it's first inputs.
`MSG_DEBUG("FSM_ST_IDLE");
tf_addr_nd <= 1'b0;
if (bufferin_read_full)
begin
fsm_state <= FSM_ST_CALC;
x_nd <= 1'b1;
end
end // case: FSM_ST_IDLE
FSM_ST_CALC:
begin
`MSG_DEBUG("FSM_ST_CALC");
// In this state sections, series_bits, out0_addr and
// readbuf switch are updated so that we know where
// the BF module should read from and write to.
fsm_state <= FSM_ST_SEND;
tf_addr_nd <= 1'b1;
x_nd <= 1'b0;
if (&(out1_addr))
begin
// We finished the last FFT stage. Move onto the next.
`MSG_DEBUG("-------NEXT STAGE---------");
// If we're on the first stage then free up the input buffer
// for more input.
if (first_stage)
begin
`MSG_DEBUG("-Input Buffer No Longer Full-");
if (bufferin_read_switch)
bufferin_full1_B <= ~bufferin_full1_B;
else
bufferin_full0_B <= ~bufferin_full0_B;
bufferin_read_switch <= ~bufferin_read_switch;
end
// One less bit of in0_addr corresponds to which section
// it is in.
series_bits <= series_bits >> 1;
// We have half as many sections as in the last stage.
S <= S >> 1;
out0_addr <= 0;
// We switch which buffers we are reading from and
// writing to.
readbuf_switch <= ~readbuf_switch;
// Mark the buffer we were previously reading from as
// not updated. We will write to it now.
// Moved later so we drive from same process as we set.
/*
if (readbuf_switch)
updatedX <= {N{1'b0}};
else
updatedY <= {N{1'b0}};
*/
end
else
begin
`MSG_DEBUG("-------NEXT POSITION---------");
// Otherwise we still have more sections to do at
// this position.
out0_addr <= out0_addr + 1;
end
end
FSM_ST_SEND:
begin
`MSG_DEBUG("FSM_ST_SEND");
tf_addr_nd <= 1'b0;
// Wait in this state until the data we need to read is ready
// to go.
if (updated0 & updated1)
begin
x_nd <= 1'b1;
// If we have just sent data for the last BF calculation
// of the FFT calculation then go to the INIT state.
if (&(out1_addr) & (S==1))
begin
`MSG_DEBUG("--------FINISHED LAST STAGE---------");
fsm_state <= FSM_ST_INIT;
finished <= 1'b1;
end
else
fsm_state <= FSM_ST_CALC;
end
else
begin
`MSG_DEBUG("Waiting for data to be written.");
end
end
default:
begin
fsm_state <= FSM_ST_INIT;
end
endcase
end
end
/********************************************************/
/* */
/* Define logic that receives data from the BF. */
/* */
/********************************************************/
// Outputs from the BF
// The addresses where the output should be written to.
wire [NLOG2-1:0] out0_addr_z;
wire [NLOG2-1:0] out1_addr_z;
// The real and imag components of the output.
wire [2*X_WDTH-1:0] z;
// Set to 1 when the ZA is output.
// On the step after ZB is output.
wire z_nd;
// Set to 1 for the last ZA of a FFT.
wire finished_z;
// Set to 1 if data is from the last stage.
wire last_stage_z;
// Indicates which buffer the inputs to the BF module were
// read from.
// 1 if read from X.
// 0 if read from Y.
wire readbuf_switch_z;
// Delayed content of readbuf_swith_z;
reg readbuf_switch_z_last;
// Delayed content of out1_addr_z_old since we need to use
// it after it may have changed.
reg [NLOG2-1:0] out1_addr_z_old;
// The address to write the currently received BF output.
wire [NLOG2-1:0] out_addr_z;
assign out_addr_z = (z_nd)?out0_addr_z:out1_addr_z_old;
// A delayed z_nd. Tells us when to expect ZB.
reg z_nd_last;
// For delaying variables. It takes 2 steps to write the output data
// to the buffer at which point we decide whether to write the data
// to bufferout. These registers are needed for that decision.
reg finished_z_old[1:0];
reg last_stage_z_old[0:0];
reg readbuf_switch_z_old[1:0];
initial
begin
bufferout_full_A <= 1'b0;
z_nd_last <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
bufferout_full_A <= 1'b0;
z_nd_last <= 1'b0;
end
else
begin
// Put updated reset here so we drive it from same process.
if ((fsm_state == FSM_ST_CALC) & (&(out1_addr)))
begin
if (readbuf_switch)
updatedX <= {N{1'b0}};
else
updatedY <= {N{1'b0}};
end
// Set all the delays.
readbuf_switch_z_last <= readbuf_switch_z;
finished_z_old[0] <= finished_z;
finished_z_old[1] <= finished_z_old[0];
last_stage_z_old[0] <= last_stage_z;
readbuf_switch_z_old[0] <= readbuf_switch_z;
readbuf_switch_z_old[1] <= readbuf_switch_z_old[0];
out1_addr_z_old <= out1_addr_z;
z_nd_last <= z_nd;
if (finished_z_old[1])
// We have filled the output buffer
bufferout_full_A <= ~bufferout_full_A;
// Write received data to the buffers and set updated flag.
if (z_nd | z_nd_last)
begin
if ((last_stage_z & z_nd)|(last_stage_z_old[0] & ~z_nd))
begin
bufferout[out_addr_z] <= z;
end
else
begin
if ((readbuf_switch_z & z_nd)|(readbuf_switch_z_old[0] & ~z_nd))
begin
bufferY[out_addr_z] <= z;
updatedY[out_addr_z] <= 1'b1;
end
else
begin
bufferX[out_addr_z] <= z;
updatedX[out_addr_z] <= 1'b1;
end
end
end
end
end
/* Instantiate twiddle factor unit. */
twiddlefactors
twiddlefactors_0 (
.clk (clk),
.addr (tf_addr),
.addr_nd (tf_addr_nd),
.tf_out (tf)
);
/* Instantiate the generic butterfly unit. */
butterfly #(
.M_WDTH (3 + 2*NLOG2),
.X_WDTH (X_WDTH)
)
butterfly_0 (
.clk (clk),
.rst_n (rst_n),
.m_in ({readbuf_switch_old, out0_addr, out1_addr, finished, last_stage}),
.w (tf),
.xa (in0),
.xb (in1),
.x_nd (x_nd),
.m_out ({readbuf_switch_z, out0_addr_z, out1_addr_z, finished_z, last_stage_z}),
.y (z),
.y_nd (z_nd)
);
endmodule // dit
|
`timescale 1ns / 1ps
`include "hal/WcaPortDefs.h" //grab register addresses.
// Name: WcaPortWrite.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaPortWrite(
input wire reset,
input wire port_enable, //Enables/Disable port writing.
input wire wr_clk, // Clock input to fifo.
input wire wr_en, //Allows input if specified.
input wire [31:0] wr_in, // Clock data input.
output wire empty, // Active high indicates buffer is empty.
output wire full, // Active high indicates buffer is full.
output wire prog_empty, // Active high indicates buffer is almost empty at or below 160 samples.
output wire prog_full, // Active high indicates buffer is almost full at or above 352 samples.
//Port Controller interface.
inout [31:0] pifData, // 32 bit port interface data bus.
input wire [(NBITS_ADDR+2):0] portCtrl, // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
output wire [1:0] portCmd // Port Command ID
);
parameter ADDR_PORT = 0;
parameter NBITS_ADDR = 2;
parameter TEST_PATTERN = 0;
wire [31:0] dout;
wire isAddr = (ADDR_PORT == portCtrl[NBITS_ADDR+2:3]);
wire rd_en = isAddr & portCtrl[1];
//Request a read of data from the FIFO Slave interface.
assign portCmd = (isAddr) ? ((prog_full & port_enable) ? `PIFCMD_WRITE : `PIFCMD_IDLE) : 2'bz;
//Buffer the data.
FiFo512Core32W32R fifo512 (
.rst(reset), // input rst
.wr_clk(wr_clk), // input wr_clk
.rd_clk(portCtrl[0]), // input rd_clk
.din(wr_in), // input [31 : 0] din
.wr_en(wr_en & port_enable), // input wr_en
.rd_en(rd_en), // input rd_en
.dout(dout), // output [31 : 0] dout
.full(full), // output full
.empty(empty), // output empty
.prog_full(prog_full), // output prog_full threhold at 388 DWORDS
.prog_empty(prog_empty) // output prog_empty threshold at 256 DWORDS
);
generate if( TEST_PATTERN == 1)
begin
//Place data on the buss if reading.
assign pifData = ( rd_en ) ? ctr : 32'bz;
//Writes a sequence of interface out the Port, use for USB Troubleshooting.
reg [31:0] ctr;
always @(posedge portCtrl[0])
begin
if( reset)
ctr <= 32'h0;
else if( rd_en )
ctr <= ctr + 32'h1;
end
end
else
begin
//Place data on the buss if reading.
assign pifData = ( rd_en ) ? dout : 32'bz;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:28:10 07/09/2015
// Design Name:
// Module Name: Graph960x8
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module TOP
( input CLK32,
output [3:0] TMDS_out_P,
output [3:0] TMDS_out_N,
output [12:0] SDRAM_ADDR,
inout [15:0] SDRAM_DATA,
output SDRAM_BA0,
output SDRAM_BA1,
output SDRAM_UDQM,
output SDRAM_LDQM,
output SDRAM_CLK,
output SDRAM_CKE,
output SDRAM_CSn,
output SDRAM_RASn,
output SDRAM_CASn,
output SDRAM_WEn,
output SD_CLK,
output SD_CD_DAT3,
input SD_DAT0,
output SD_DAT1,
output SD_DAT2,
output SD_CMD,
output [7:0] LEDS
);
wire PixelClk;
wire PixelClk2;
wire PixelClk10;
wire SerDesStrobe;
wire [7:0] Red;
wire [7:0] Green;
wire [7:0] Blue;
wire HSync;
wire VSync;
wire VideoEnable;
wire [10:0] GetRow;
wire StartBuffer;
wire [8:0] BufferAddr;
wire [15:0] BufferData;
wire BufferWrite;
wire [23:0] ExtAddr;
wire [15:0] ExtDataWrite;
wire [1:0] ExtDataMask;
wire [15:0] ExtDataRead;
wire ExtOP;
wire ExtReq;
wire ExtReady;
wire [7:0] PalAddr;
wire [31:0] PalData;
wire PalWrite;
wire [5:0] XOffsetData;
wire [9:0] YOffsetData;
wire OffsetWrite;
wire [24:0] Address;
wire [31:0] DataWrite;
wire [31:0] DataRead;
wire [1:0] DataSize;
wire ReadWrite;
wire Request;
wire Ready;
CLOCK CLOCK(CLK32, PixelClk, PixelClk2, PixelClk10, SerDesStrobe);
DVI_OUT DVI_OUT(PixelClk, PixelClk2, PixelClk10, SerDesStrobe, Red, Green, Blue, HSync, VSync, VideoEnable, TMDS_out_P, TMDS_out_N);
VIDEOGEN VIDEOGEN(PixelClk, PixelClk2, Red, Green, Blue, HSync, VSync, VideoEnable,
GetRow, StartBuffer, BufferAddr, BufferData, BufferWrite,
PalAddr, PalData, PalWrite, XOffsetData, YOffsetData, OffsetWrite);
SDRAM SDRAM(.PixelClk2(PixelClk2), .SDRAMCK(SDRAM_CLK), .CMD({SDRAM_CKE,SDRAM_CSn,SDRAM_RASn,SDRAM_CASn,SDRAM_WEn}),
.DQM({SDRAM_UDQM,SDRAM_LDQM}), .BANK({SDRAM_BA1,SDRAM_BA0}), .ADDR(SDRAM_ADDR), .DATA(SDRAM_DATA),
.ExtAddr(ExtAddr), .ExtDataWrite(ExtDataWrite), .ExtDataMask(ExtDataMask), .ExtDataRead(ExtDataRead), .ExtOP(ExtOP),
.ExtReq(ExtReq), .ExtReady(ExtReady),
.GetRow(GetRow), .StartBuffer(StartBuffer), .BufferAddr(BufferAddr), .BufferData(BufferData), .BufferWrite(BufferWrite));
MemoryAdapter MA(PixelClk2, ExtAddr, ExtDataWrite, ExtDataMask, ExtDataRead, ExtOP, ExtReq, ExtReady,
Address, DataWrite, DataRead, DataSize, ReadWrite, Request, Ready);
SD SD(PixelClk2, SD_CLK, SD_CD_DAT3, SD_DAT0, SD_DAT1, SD_DAT2, SD_CMD, LEDS,
Address, DataWrite, DataRead, DataSize, ReadWrite, Request, Ready, PalAddr, PalData, PalWrite);
Test Test(PixelClk2, VSync, XOffsetData, YOffsetData, OffsetWrite);
endmodule
|
`include "core.h"
`default_nettype none
`define MICROCODE_SIZE 32'h10
module microcode_context_store(
input iCLOCK,
input inRESET,
//Select
input [31:0] iSELECT,
//Output
output [31:0] oCODE_SIZE,
input [72:0] oCODE0,
input [72:0] oCODE1
);
wire [73:0] tmp0;
wire [73:0] tmp1;
assign tmp0 = func_microcode(iSELECT<<1);
assign tmp1 = func_microcode((iSELECT<<1) + 32'h1);
assign oCODE_SIZE = `MICROCODE_SIZE;
assign oCODE0 = tmp0[72:0];
assign oCODE1 = tmp1[72:0];
/*
//PC Reserved
movepc srr0, -1
//SPR Reserved
srspr ssr1
//R0, R1 Reserved
move ssr2 r0
move ssr3 r1
//Set SPR
srtisr r0
add r0, 128
srtidr r1
mull r1, 144
add r1, r0
srspw r1
//General Register Store
push ssr2
push ssr3
push r2
push r3
push r4
push r5
push r6
push r7
push r8
push r9
push r10
push r11
push r12
push r13
push r14
push r15
push r16
push r17
push r18
push r19
push r20
push r21
push r22
push r23
push r24
push r25
push r26
push r27
push r28
push r29
push r30
push r31
//Push PC
push srr0
//Push SPR
push srr1
//Push PDTR
srpdtr r0
push r0
*/
function [73:0] func_microcode;
input func_addr;
begin
case(func_addr)
32'd0 : //MOVEPC SSR0, -1
begin
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_PC,
/* Source1 */ 32'hFFFFFFFF,//-1
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
32'd1 :
begin //SRSPR SSR1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SPR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_READ_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
32'd2 :
begin //MOVE SSR2, R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ `LOGICREG_R0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR2,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_BUFFER1,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
32'd3 :
begin //MOVE SSR3, R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ `LOGICREG_R1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR3,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_BUFFER1,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
32'd4 :
begin //SRTISR R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_TISR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd5 :
begin //ADD R0, 128
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0,
/* Source1 */ 32'd128,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
32'd6 :
begin //SRTIDR R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_TIDR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd7 :
begin //MULL R1, 144
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R1,
/* Source1 */ 32'd144,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MULDIV_MULL,
/* Execute Module */ `EXE_SELECT_MUL
};
end
32'd8 :
begin //ADD R1, R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R1,
/* Source1 */ {{27{1'b0}}, `LOGICREG_R0},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
32'd9 :
begin //SRSPW R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R1,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SPR,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_WRITE_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
32'd10 :
begin //PUSH SSR2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_SSR2, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd11 :
begin //PUSH SSR3
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_SSR3, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd12 :
begin //PUSH R2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R2, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd13 :
begin //PUSH R3
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R3, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd14 :
begin //PUSH R4
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R4, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd15 :
begin //PUSH R5
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R5, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd16 :
begin //PUSH R6
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R6, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd17 :
begin //PUSH R7
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R7, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd18 :
begin //PUSH R8
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R8, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd19 :
begin //PUSH R9
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R9, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd20 :
begin //PUSH R10
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R10, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd21 :
begin //PUSH R11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R11, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd22 :
begin //PUSH R12
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R12, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd23 :
begin //PUSH R13
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R13, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd24 :
begin //PUSH R14
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R14, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd25 :
begin //PUSH R15
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R15, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd26 :
begin //PUSH R16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R16, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd27 :
begin //PUSH R17
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R17, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd28 :
begin //PUSH R18
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R18, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd29 :
begin //PUSH R19
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R19, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd30 :
begin //PUSH R20
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R20, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd31 :
begin //PUSH R21
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R21, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd32 :
begin //PUSH R22
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R22, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd33 :
begin //PUSH R23
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R23, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd34 :
begin //PUSH R24
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R24, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd35 :
begin //PUSH R25
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R25, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd36 :
begin //PUSH R26
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R26, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd37 :
begin //PUSH R27
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R27, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd38 :
begin //PUSH R28
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R28, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd39 :
begin //PUSH R29
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R29, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd40 :
begin //PUSH R30
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R30, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd41 :
begin //PUSH R31
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R31, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd42 :
begin //PUSH SSR0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SSR0, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd43 :
begin //PUSH SSR1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SSR1, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd44 :
begin //SRPDTR R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_PDTR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd45 :
begin //PUSH R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
default:
begin
$display("[ERROR] : microcode_context_store.v case Error");
f_decode = {74{1'b1}};
end
endcase
end
endfunction
endmodule
`default_nettype wire
|
/*
This block receives the IO transaction and converts to a 104 bit packet.
*/
`include "elink_constants.v"
module erx_io (/*AUTOARG*/
// Outputs
rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
// Inputs
reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
// Can we do this in a better way?
//parameter [3:0] RX_TAP_DELAY [8:0]=;
//parameter RX_TAP_DELAY = 1;
parameter [5*10:0] RX_TAP_DELAY ={5'd0, //clk
5'd12, //frame
5'd12, //d7
5'd12, //d6
5'd12, //d5
5'd12, //d4
5'd12, //d3
5'd12, //d2
5'd12, //d1
5'd12 //d0
};
//#########################
//# reset, clocks
//#########################
input reset; // reset
input rx_lclk; // fast I/O clock
input rx_lclk_div4; // slow clock
output rx_lclk_pll; // clock output for pll
//##########################
//# elink pins
//##########################
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
//##########################
//# erx logic interface
//##########################
output rx_access;
output rx_burst;
output [PW-1:0] rx_packet;
input rx_wr_wait;
input rx_rd_wait;
//############
//# WIRES
//############
wire [7:0] rxi_data;
wire rxi_frame;
wire rxi_lclk;
wire access_wide;
reg valid_packet;
reg [15:0] rx_word;
wire [15:0] rx_word_i;
//############
//# REGS
//############
reg [7:0] data_even_reg;
reg [7:0] data_odd_reg;
reg rx_frame;
wire rx_frame_i;
reg [111:0] rx_sample;
reg [6:0] rx_pointer;
reg access;
reg burst;
reg [PW-1:0] rx_packet_lclk;
reg rx_access;
reg [PW-1:0] rx_packet;
reg rx_burst;
wire rx_lclk_iddr;
wire [9:0] rxi_delay_in;
wire [9:0] rxi_delay_out;
//#####################
//#CREATE 112 BIT PACKET
//#####################
//write Pointer
always @ (posedge rx_lclk)
if (~rx_frame)
rx_pointer[6:0] <= 7'b0000001; //new frame
else if (rx_pointer[6])
rx_pointer[6:0] <= 7'b0001000; //anticipate burst
else if(rx_frame)
rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
//convert to 112 bit packet
always @ (posedge rx_lclk)
if(rx_frame)
begin
if(rx_pointer[0])
rx_sample[15:0] <= rx_word[15:0];
if(rx_pointer[1])
rx_sample[31:16] <= rx_word[15:0];
if(rx_pointer[2])
rx_sample[47:32] <= rx_word[15:0];
if(rx_pointer[3])
rx_sample[63:48] <= rx_word[15:0];
if(rx_pointer[4])
rx_sample[79:64] <= rx_word[15:0];
if(rx_pointer[5])
rx_sample[95:80] <= rx_word[15:0];
if(rx_pointer[6])
rx_sample[111:96] <= rx_word[15:0];
end // if (rx_frame)
//#####################
//#DATA VALID SIGNAL
//####################
always @ (posedge rx_lclk)
begin
access <= rx_pointer[6];
valid_packet <= access;//data pipeline
end
reg burst_detect;
always @ (posedge rx_lclk)
if(access & rx_frame)
burst_detect <= 1'b1;
else if(~rx_frame)
burst_detect <= 1'b0;
//###################################
//#SAMPLE AND HOLD DATA
//###################################
//(..and shuffle data for 104 bit packet)
always @ (posedge rx_lclk)
if(access)
begin
//pipelin burst (delay by one frame)
burst <= burst_detect;
//access
rx_packet_lclk[0] <= rx_sample[40];
//write
rx_packet_lclk[1] <= rx_sample[41];
//datamode
rx_packet_lclk[3:2] <= rx_sample[43:42];
//ctrlmode
rx_packet_lclk[7:4] <= rx_sample[15:12];
//dstaddr
rx_packet_lclk[39:8] <= {rx_sample[11:8],
rx_sample[23:16],
rx_sample[31:24],
rx_sample[39:32],
rx_sample[47:44]};
//data
rx_packet_lclk[71:40] <= {rx_sample[55:48],
rx_sample[63:56],
rx_sample[71:64],
rx_sample[79:72]};
//srcaddr
rx_packet_lclk[103:72]<= {rx_sample[87:80],
rx_sample[95:88],
rx_sample[103:96],
rx_sample[111:104]
};
end
//###################################
//#SYNCHRONIZE TO SLOW CLK
//###################################
//stretch access pulse to 4 cycles
pulse_stretcher #(.DW(3))
ps0 (
.out(access_wide),
.in(valid_packet),
.clk(rx_lclk),
.reset(reset));
always @ (posedge rx_lclk_div4)
rx_access <= access_wide;
always @ (posedge rx_lclk_div4)
if(access_wide)
begin
rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
rx_burst <= burst;
end
//################################
//# I/O Buffers Instantiation
//################################
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_data[7:0]
(.I (rxi_data_p[7:0]),
.IB (rxi_data_n[7:0]),
.O (rxi_data[7:0]));
IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTD_ELINK))
ibuf_frame
(.I (rxi_frame_p),
.IB (rxi_frame_n),
.O (rxi_frame));
IBUFGDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_lclk (.I (rxi_lclk_p),
.IB (rxi_lclk_n),
.O (rxi_lclk)
);
generate
if(ETYPE==1)
begin
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_wrwait (
.O(rxo_wr_wait_p),
.T(rx_wr_wait),
.I(1'b0)
);
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_rdwait (
.O(rxo_rd_wait_p),
.T(rx_rd_wait),
.I(1'b0)
);
assign rxo_wr_wait_n = 1'b0;
assign rxo_rd_wait_n = 1'b0;
end
else if(ETYPE==0)
begin
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_wrwait (
.O(rxo_wr_wait_p),
.OB(rxo_wr_wait_n),
.I(rx_wr_wait)
);
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_rdwait (.O(rxo_rd_wait_p),
.OB(rxo_rd_wait_n),
.I(rx_rd_wait)
);
end
endgenerate
//###################################
//#RX CLOCK
//###################################
BUFG rxi_lclk_bufg_i(.I(rxi_lclk), .O(rx_lclk_pll)); //for mmcm
BUFIO rx_lclk_bufio_i(.I(rxi_delay_out[9]), .O(rx_lclk_iddr));//for iddr (NOT USED!)
//###################################
//#IDELAY CIRCUIT
//###################################
assign rxi_delay_in[9:0] ={rxi_lclk,rxi_frame,rxi_data[7:0]};
genvar j;
generate for(j=0; j<10; j=j+1)
begin : gen_idelay
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.IDELAY_TYPE("FIXED"),
.IDELAY_VALUE(RX_TAP_DELAY[(j+1)*5-1:j*5]),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA"))
idelay_inst (.CNTVALUEOUT(),
.DATAOUT(rxi_delay_out[j]),
.C(1'b0),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'b0),
.DATAIN(1'b0),
.IDATAIN(rxi_delay_in[j]),
.INC(1'b0),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
end // block: gen_idelay
endgenerate
//#############################
//# IDDR SAMPLERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_iddr
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_data (
.Q1 (rx_word_i[i]),
.Q2 (rx_word_i[i+8]),
.C (rx_lclk),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[i]),
.R (reset),
.S (1'b0)
);
end
endgenerate
//FRAME
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_frame (
.Q1 (rx_frame_i),
.Q2 (),
.C (rx_lclk),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[8]),
.R (reset),
.S (1'b0)
);
always @ ( posedge rx_lclk )
rx_frame <= rx_frame_i;
always @ ( posedge rx_lclk )
rx_word <= rx_word_i;
endmodule // erx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_SYMBOL_V
`define SKY130_FD_SC_MS__A211O_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a211o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A2BB2O_FUNCTIONAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:54:19 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110;
NAND2XLTS U51 ( .A(n33), .B(n87), .Y(n89) );
XOR2X1TS U52 ( .A(n62), .B(in2[11]), .Y(n94) );
NAND2X1TS U53 ( .A(n71), .B(in1[13]), .Y(n87) );
NAND2X1TS U54 ( .A(n74), .B(n36), .Y(n58) );
NAND2BX1TS U55 ( .AN(in2[13]), .B(n59), .Y(n74) );
NAND2X1TS U56 ( .A(n67), .B(n36), .Y(n68) );
CMPR32X2TS U57 ( .A(n100), .B(in1[6]), .C(n99), .CO(n55), .S(res[6]) );
OR2X2TS U58 ( .A(n51), .B(n35), .Y(n34) );
INVX4TS U59 ( .A(n35), .Y(n36) );
NOR2X4TS U60 ( .A(n53), .B(in2[8]), .Y(n57) );
INVX4TS U61 ( .A(add_sub), .Y(n35) );
CLKINVX6TS U62 ( .A(in2[1]), .Y(n44) );
CLKINVX6TS U63 ( .A(in2[3]), .Y(n42) );
CLKINVX6TS U64 ( .A(in2[0]), .Y(n43) );
INVX8TS U65 ( .A(in2[2]), .Y(n41) );
NAND2BX2TS U66 ( .AN(in2[11]), .B(n61), .Y(n67) );
NOR2XLTS U67 ( .A(n61), .B(n35), .Y(n62) );
INVX2TS U68 ( .A(n78), .Y(n77) );
NOR2X4TS U69 ( .A(n67), .B(in2[12]), .Y(n59) );
NOR2X4TS U70 ( .A(n65), .B(in2[10]), .Y(n61) );
AO21X2TS U71 ( .A0(n33), .A1(n70), .B0(n72), .Y(n37) );
NAND2X2TS U72 ( .A(n76), .B(in1[15]), .Y(n78) );
XNOR2X2TS U73 ( .A(n58), .B(in2[14]), .Y(n73) );
NOR2X2TS U74 ( .A(n59), .B(n35), .Y(n60) );
ADDFHX2TS U75 ( .A(n56), .B(in1[7]), .CI(n55), .CO(n97), .S(res[7]) );
OAI31X1TS U76 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(n36), .Y(n106) );
NAND2X2TS U77 ( .A(n83), .B(n82), .Y(n85) );
NOR2X2TS U78 ( .A(n73), .B(in1[14]), .Y(n81) );
NAND2X2TS U79 ( .A(n73), .B(in1[14]), .Y(n82) );
NOR2X2TS U80 ( .A(n39), .B(n86), .Y(n38) );
INVX2TS U81 ( .A(n86), .Y(n33) );
NAND2X2TS U82 ( .A(n69), .B(in1[12]), .Y(n90) );
OR2X2TS U83 ( .A(n69), .B(in1[12]), .Y(n46) );
XNOR2X2TS U84 ( .A(n68), .B(in2[12]), .Y(n69) );
NOR2BX2TS U85 ( .AN(in1[5]), .B(n110), .Y(n99) );
NAND2BXLTS U86 ( .AN(in1[5]), .B(n110), .Y(res[5]) );
XNOR2X2TS U87 ( .A(n50), .B(in2[5]), .Y(n110) );
NAND2BXLTS U88 ( .AN(in1[4]), .B(n109), .Y(res[4]) );
OAI21XLTS U89 ( .A0(in2[1]), .A1(n102), .B0(n101), .Y(res[1]) );
OAI21XLTS U90 ( .A0(in2[2]), .A1(n104), .B0(n103), .Y(res[2]) );
OAI21XLTS U91 ( .A0(in2[3]), .A1(n106), .B0(n105), .Y(res[3]) );
XOR2X1TS U92 ( .A(n108), .B(in2[4]), .Y(n109) );
OR2X1TS U93 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
XNOR2X1TS U94 ( .A(n34), .B(in2[7]), .Y(n56) );
OAI21X1TS U95 ( .A0(n74), .A1(in2[14]), .B0(n36), .Y(n75) );
AO21X2TS U96 ( .A0(n79), .A1(n45), .B0(n77), .Y(res[16]) );
NAND2X2TS U97 ( .A(n45), .B(n78), .Y(n80) );
OR2X2TS U98 ( .A(n76), .B(in1[15]), .Y(n45) );
NOR2X2TS U99 ( .A(n49), .B(n35), .Y(n50) );
AFHCONX4TS U100 ( .A(in1[10]), .B(n95), .CI(n96), .CON(n93), .S(res[10]) );
AOI21X4TS U101 ( .A0(n91), .A1(n38), .B0(n37), .Y(n84) );
XNOR2X1TS U102 ( .A(n79), .B(n80), .Y(res[15]) );
OAI21X4TS U103 ( .A0(n84), .A1(n81), .B0(n82), .Y(n79) );
XNOR2X2TS U104 ( .A(n75), .B(in2[15]), .Y(n76) );
AFHCONX4TS U105 ( .A(in1[8]), .B(n98), .CI(n97), .CON(n63), .S(res[8]) );
AFHCINX4TS U106 ( .CIN(n63), .B(n64), .A(in1[9]), .S(res[9]), .CO(n96) );
NOR2X8TS U107 ( .A(n47), .B(in2[6]), .Y(n51) );
NAND2X4TS U108 ( .A(n47), .B(add_sub), .Y(n48) );
NAND2X8TS U109 ( .A(n49), .B(n40), .Y(n47) );
AFHCINX4TS U110 ( .CIN(n93), .B(n94), .A(in1[11]), .S(res[11]), .CO(n91) );
NOR2X8TS U111 ( .A(n107), .B(in2[4]), .Y(n49) );
XOR2X4TS U112 ( .A(n60), .B(in2[13]), .Y(n71) );
NAND2BX4TS U113 ( .AN(in2[7]), .B(n51), .Y(n53) );
NAND2BX4TS U114 ( .AN(in2[9]), .B(n57), .Y(n65) );
INVX2TS U115 ( .A(in2[5]), .Y(n40) );
NOR2X2TS U116 ( .A(n71), .B(in1[13]), .Y(n86) );
INVX2TS U117 ( .A(n90), .Y(n70) );
INVX2TS U118 ( .A(n46), .Y(n39) );
XNOR2X1TS U119 ( .A(n48), .B(in2[6]), .Y(n100) );
XNOR2X1TS U120 ( .A(n54), .B(in2[8]), .Y(n98) );
NAND2X1TS U121 ( .A(n53), .B(n36), .Y(n54) );
XOR2X1TS U122 ( .A(n52), .B(in2[9]), .Y(n64) );
NOR2X1TS U123 ( .A(n57), .B(n35), .Y(n52) );
XNOR2X1TS U124 ( .A(n92), .B(n91), .Y(res[12]) );
NAND2X1TS U125 ( .A(n46), .B(n90), .Y(n92) );
XOR2X1TS U126 ( .A(n89), .B(n88), .Y(res[13]) );
AOI21X1TS U127 ( .A0(n91), .A1(n46), .B0(n70), .Y(n88) );
XOR2X1TS U128 ( .A(n85), .B(n84), .Y(res[14]) );
INVX2TS U129 ( .A(n81), .Y(n83) );
NAND4X8TS U130 ( .A(n44), .B(n43), .C(n42), .D(n41), .Y(n107) );
INVX2TS U131 ( .A(n87), .Y(n72) );
NAND2X1TS U132 ( .A(n65), .B(n36), .Y(n66) );
XNOR2X1TS U133 ( .A(n66), .B(in2[10]), .Y(n95) );
NAND2X1TS U134 ( .A(in2[0]), .B(n36), .Y(n102) );
AOI21X1TS U135 ( .A0(in2[1]), .A1(n102), .B0(in1[1]), .Y(n101) );
OAI21X1TS U136 ( .A0(in2[1]), .A1(in2[0]), .B0(n36), .Y(n104) );
AOI21X1TS U137 ( .A0(in2[2]), .A1(n104), .B0(in1[2]), .Y(n103) );
AOI21X1TS U138 ( .A0(in2[3]), .A1(n106), .B0(in1[3]), .Y(n105) );
NAND2X1TS U139 ( .A(n107), .B(n36), .Y(n108) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL6_syn.sdf");
endmodule
|
/*
########################################################################
MASTER ENABLE, CLOCKS, CHIP-ID
########################################################################
*/
`include "elink_regmap.v"
module ecfg_elink (/*AUTOARG*/
// Outputs
txwr_gated_access, elink_en, clk_config, e_chipid,
// Inputs
txwr_access, txwr_packet, clk, reset
);
parameter RFAW = 6; // 32 registers for now
parameter PW = 104; // 32 registers for now
parameter ID = 12'h000;
parameter DEFAULT_CHIPID = 12'h808;
/******************************/
/*REGISTER ACCESS */
/******************************/
input txwr_access;
input [PW-1:0] txwr_packet;
/******************************/
/*FILTERED WRITE FOR TX FIFO */
/******************************/
output txwr_gated_access;
/******************************/
/*Clock/reset */
/******************************/
input clk;
input reset; // POR "hard reset"
/******************************/
/*Outputs */
/******************************/
output elink_en; // elink master enable
output [15:0] clk_config; // clock settings (for pll)
output [11:0] e_chipid; // chip-id for Epiphany
/*------------------------CODE BODY---------------------------------------*/
//registers
reg ecfg_reset_reg;
reg [15:0] ecfg_clk_reg;
reg [11:0] ecfg_chipid_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_clk_write;
wire ecfg_chipid_write;
wire ecfg_reset_write;
wire mi_en;
wire [31:0] mi_addr;
wire [31:0] mi_din;
packet2emesh pe2 (
// Outputs
.access_out (),
.write_out (mi_we),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (mi_addr[31:0]),
.data_out (mi_din[31:0]),
.srcaddr_out (),
// Inputs
.packet_in (txwr_packet[PW-1:0])
);
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
assign mi_en = txwr_access &
(mi_addr[31:20]==ID) &
(mi_addr[10:8]==3'h2);
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
assign ecfg_chipid_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CHIPID);
/*****************************/
/*FILTER ACCESS */
/*****************************/
assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
ecfg_clk_write |
ecfg_chipid_write);
//###########################
//# RESET REG
//###########################
always @ (posedge clk)
if(reset)
ecfg_reset_reg <= 1'b0;
else if (ecfg_reset_write)
ecfg_reset_reg <= mi_din[0];
assign elink_en = ~ecfg_reset_reg;
//###########################
//# CCLK/LCLK (PLL)
//###########################
always @ (posedge clk)
if(reset)
ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
else if (ecfg_clk_write)
ecfg_clk_reg[15:0] <= mi_din[15:0];
assign clk_config[15:0] = ecfg_clk_reg[15:0];
//###########################
//# CHIPID
//###########################
always @ (posedge clk)
if(reset)
ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
else if (ecfg_chipid_write)
ecfg_chipid_reg[11:0] <= mi_din[11:0];
assign e_chipid[11:0]=ecfg_chipid_reg[5:2];
endmodule // ecfg_elink
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : pixel panning
// File : pixel_panning.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module realizes pixel panning both in text
// and Graphics mode. THe pixel shifting to the left
// or right is based on pixel panning control signals
// and mode 13 control signals.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module pixel_panning
(
input din,
input clk, // dot clock
input clk_en, // dot clock
input [3:0] pp_ctl, // pixel panning control signals
input mode_13_ctl,
input r_n,
input by_4_syn_cclk,
output dout,
output dout_1
);
reg [8:0] shift_ff;
reg [7:0] mux_ctl; // mux control signals
wire [7:0] int_d;
wire [7:0] mux_ctl_8_f_op;
assign int_d[7] = mux_ctl[7] ? din : shift_ff[8];
assign int_d[6] = mux_ctl[6] ? din : shift_ff[7];
assign int_d[5] = mux_ctl[5] ? din : shift_ff[6];
assign int_d[4] = mux_ctl[4] ? din : shift_ff[5];
assign int_d[3] = mux_ctl[3] ? din : shift_ff[4];
assign int_d[2] = mux_ctl[2] ? din : shift_ff[3];
assign int_d[1] = mux_ctl[1] ? din : shift_ff[2];
assign int_d[0] = mux_ctl[0] ? din : shift_ff[1];
// Inferring 9 flops
always@(posedge clk or negedge r_n) begin
if(~r_n) shift_ff[8:0] <= 8'b0;
else if (clk_en) begin
shift_ff[8] <= din;
shift_ff[7] <= int_d[7];
shift_ff[6] <= int_d[6];
shift_ff[5] <= int_d[5];
shift_ff[4] <= int_d[4];
shift_ff[3] <= int_d[3];
shift_ff[2] <= int_d[2];
shift_ff[1] <= int_d[1];
shift_ff[0] <= int_d[0];
end
end
assign mux_ctl_8_f_op = mode_13_ctl ? 8'b0001_0000 : 8'b0000_0000;
// Realizing mux control signals
always @(pp_ctl or mode_13_ctl or mux_ctl_8_f_op or by_4_syn_cclk) begin
case(pp_ctl) // synopsys parallel_case
4'h0: mux_ctl = (by_4_syn_cclk) ? 8'b0000_1000 : 8'b1000_0000;
4'h1: mux_ctl = 8'b0100_0000;
4'h2: mux_ctl = (mode_13_ctl) ? 8'b0100_0000 : 8'b0010_0000;
4'h3: mux_ctl = 8'b0001_0000;
4'h4: mux_ctl = (mode_13_ctl) ? 8'b0010_0000 : 8'b0000_1000;
4'h5: mux_ctl = 8'b0000_0100;
4'h6: mux_ctl = (mode_13_ctl) ? 8'b0001_0000 : 8'b0000_0010;
4'h7: mux_ctl = 8'b0000_0001;
4'h8: mux_ctl = mux_ctl_8_f_op;
4'h9: mux_ctl = mux_ctl_8_f_op;
4'ha: mux_ctl = mux_ctl_8_f_op;
4'hb: mux_ctl = mux_ctl_8_f_op;
4'hc: mux_ctl = mux_ctl_8_f_op;
4'hd: mux_ctl = mux_ctl_8_f_op;
4'he: mux_ctl = mux_ctl_8_f_op;
4'hf: mux_ctl = mux_ctl_8_f_op;
endcase
end
assign dout = shift_ff[0];
assign dout_1 = int_d[0];
endmodule
|
`timescale 1ns/1ps // reference time = 1ns, precision value = 1ps
`include "commands.vh"
`define H_PERIOD 41.666
`define PERIOD 83.333
`define PERIOD10 833.33
module communication_tb;
initial begin
$dumpfile("communication.vcd");
$dumpvars(0, communication_tb);
# 1100000000 $finish; // 1 100 000 000 ns = 1.1s
end
reg clk=0;
always #`H_PERIOD clk = !clk; // 41.666 ns = a half period of the 12MHz clock
wire transmit;
wire [7:0] tx_byte;
reg received;
reg [7:0] rx_byte;
wire en;
wire [39:0] m;
wire set;
wire error;
reg [39:0] m2=40315426; // value of m to send (for 440 Hz)
initial begin
#`PERIOD10 rx_byte = `BYTE0;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[7:0];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE1;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[15:8];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE2;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[23:16];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE3;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[31:24];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE4;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[39:32];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `SET;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `ENABLE;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = 0; // generate an error
#`PERIOD received = 1;
#`PERIOD received = 0;
end
communication com(.clk(clk), .transmit(transmit), .tx_byte(tx_byte), .received(received), .rx_byte(rx_byte), .en(en), .m(m), .set(set), .error(error));
endmodule
|
// Library - static, Cell - th54w32, View - schematic
// LAST TIME SAVED: May 23 18:09:51 2014
// NETLIST TIME: May 23 18:10:09 2014
`timescale 1ns / 1ns
module th54w32 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th54w32";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net037), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N14 ( .d(net32), .g(c), .s(net037), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net45), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(b), .s(net037), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net45), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N15 ( .d(net32), .g(d), .s(net037), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net45), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net45), .b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(b), .s(net036), .d(net047));
pfet_b P7 ( .b(cds_globals.vdd_), .g(c), .s(net047), .d(net32));
pfet_b P10 ( .b(cds_globals.vdd_), .g(d), .s(net047), .d(net32));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net47));
pfet_b P3 ( .b(cds_globals.vdd_), .g(a), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(d), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// tap_top.v ////
//// ////
//// ////
//// This file is part of the JTAG Test Access Port (TAP) ////
//// ////
//// Author(s): ////
//// Igor Mohor ([email protected]) ////
//// Nathan Yawn ([email protected]) ////
//// ////
//// ////
//// All additional information is avaliable in the jtag.pdf ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Define IDCODE Value
`define IDCODE_VALUE 32'h149511c3
// 0001 version
// 0100100101010001 part number (IQ)
// 00011100001 manufacturer id (flextronics)
// 1 required by standard
// Length of the Instruction register
`define IR_LENGTH 4
// Supported Instructions
`define USER1 4'b0000
`define SAMPLE_PRELOAD 4'b0001
`define IDCODE 4'b0010
`define DEBUG 4'b1000
`define USER2 4'b1001
`define BYPASS 4'b1111
// Top module
module tap_top(
// JTAG pads
tms_pad_i,
tck_pad_i,
trstn_pad_i,
tdi_pad_i,
tdo_pad_o,
tdo_padoe_o,
// TAP states
test_logic_reset_o,
run_test_idle_o,
shift_dr_o,
pause_dr_o,
update_dr_o,
capture_dr_o,
// Select signals for USER1 or USER2 register
user1_select_o,
user2_select_o,
// TDO signal that is connected to TDI of sub-modules.
tdi_o,
// TDI signals from sub-modules
debug_tdo_i, // from debug module
bs_chain_tdo_i, // from Boundary Scan Chain
mbist_tdo_i // from Mbist Chain
);
// JTAG pins
input tms_pad_i; // JTAG test mode select pad
input tck_pad_i; // JTAG test clock pad
input trstn_pad_i; // JTAG test reset pad
input tdi_pad_i; // JTAG test data input pad
output tdo_pad_o; // JTAG test data output pad
output tdo_padoe_o; // Output enable for JTAG test data output pad
// TAP states
output test_logic_reset_o;
output run_test_idle_o;
output shift_dr_o;
output pause_dr_o;
output update_dr_o;
output capture_dr_o;
output sample_preload_select_o;
output user1_select_o;
output user2_select_o;
// TDO signal that is connected to TDI of sub-modules.
output tdi_o;
// TDI signals from sub-modules
input debug_tdo_i; // from debug module
input bs_chain_tdo_i; // from Boundary Scan Chain
input mbist_tdo_i; // from Mbist Chain
// Wires which depend on the state of the TAP FSM
reg test_logic_reset;
reg run_test_idle;
reg select_dr_scan;
reg capture_dr;
reg shift_dr;
reg exit1_dr;
reg pause_dr;
reg exit2_dr;
reg update_dr;
reg select_ir_scan;
reg capture_ir;
reg shift_ir;
reg exit1_ir;
reg pause_ir;
reg exit2_ir;
reg update_ir;
// Wires which depend on the current value in the IR
reg user1_select;
reg sample_preload_select;
reg idcode_select;
reg user1_select;
reg debug_select;
reg bypass_select;
// TDO and enable
reg tdo_pad_o;
reg tdo_padoe_o;
assign tdi_o = tdi_pad_i;
assign test_logic_reset_o = test_logic_reset;
assign run_test_idle_o = run_test_idle;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
assign sample_preload_select_o = sample_preload_select;
assign user1_select_o = user1_select;
assign user2_select_o = user2_select;
/**********************************************************************************
* *
* TAP State Machine: Fully JTAG compliant *
* *
**********************************************************************************/
// Definition of machine state values. We could one-hot encode this, and use 16
// registers, but this uses binary encoding for the minimum of 4 DFF's instead.
`define STATE_test_logic_reset 4'hF
`define STATE_run_test_idle 4'hC
`define STATE_select_dr_scan 4'h7
`define STATE_capture_dr 4'h6
`define STATE_shift_dr 4'h2
`define STATE_exit1_dr 4'h1
`define STATE_pause_dr 4'h3
`define STATE_exit2_dr 4'h0
`define STATE_update_dr 4'h5
`define STATE_select_ir_scan 4'h4
`define STATE_capture_ir 4'hE
`define STATE_shift_ir 4'hA
`define STATE_exit1_ir 4'h9
`define STATE_pause_ir 4'hB
`define STATE_exit2_ir 4'h8
`define STATE_update_ir 4'hD
reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller
reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal
// sequential part of the FSM
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
TAP_state = `STATE_test_logic_reset;
else
TAP_state = next_TAP_state;
end
// Determination of next state; purely combinatorial
always @ (TAP_state or tms_pad_i)
begin
case(TAP_state)
`STATE_test_logic_reset:
begin
if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
else next_TAP_state = `STATE_run_test_idle;
end
`STATE_run_test_idle:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
else next_TAP_state = `STATE_run_test_idle;
end
`STATE_select_dr_scan:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
else next_TAP_state = `STATE_capture_dr;
end
`STATE_capture_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
else next_TAP_state = `STATE_shift_dr;
end
`STATE_shift_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
else next_TAP_state = `STATE_shift_dr;
end
`STATE_exit1_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
else next_TAP_state = `STATE_pause_dr;
end
`STATE_pause_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
else next_TAP_state = `STATE_pause_dr;
end
`STATE_exit2_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
else next_TAP_state = `STATE_shift_dr;
end
`STATE_update_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
else next_TAP_state = `STATE_run_test_idle;
end
`STATE_select_ir_scan:
begin
if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
else next_TAP_state = `STATE_capture_ir;
end
`STATE_capture_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
else next_TAP_state = `STATE_shift_ir;
end
`STATE_shift_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
else next_TAP_state = `STATE_shift_ir;
end
`STATE_exit1_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
else next_TAP_state = `STATE_pause_ir;
end
`STATE_pause_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
else next_TAP_state = `STATE_pause_ir;
end
`STATE_exit2_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
else next_TAP_state = `STATE_shift_ir;
end
`STATE_update_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
else next_TAP_state = `STATE_run_test_idle;
end
default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen
endcase
end
// Outputs of state machine, pure combinatorial
always @ (TAP_state)
begin
// Default everything to 0, keeps the case statement simple
test_logic_reset = 1'b0;
run_test_idle = 1'b0;
select_dr_scan = 1'b0;
capture_dr = 1'b0;
shift_dr = 1'b0;
exit1_dr = 1'b0;
pause_dr = 1'b0;
exit2_dr = 1'b0;
update_dr = 1'b0;
select_ir_scan = 1'b0;
capture_ir = 1'b0;
shift_ir = 1'b0;
exit1_ir = 1'b0;
pause_ir = 1'b0;
exit2_ir = 1'b0;
update_ir = 1'b0;
case(TAP_state)
`STATE_test_logic_reset: test_logic_reset = 1'b1;
`STATE_run_test_idle: run_test_idle = 1'b1;
`STATE_select_dr_scan: select_dr_scan = 1'b1;
`STATE_capture_dr: capture_dr = 1'b1;
`STATE_shift_dr: shift_dr = 1'b1;
`STATE_exit1_dr: exit1_dr = 1'b1;
`STATE_pause_dr: pause_dr = 1'b1;
`STATE_exit2_dr: exit2_dr = 1'b1;
`STATE_update_dr: update_dr = 1'b1;
`STATE_select_ir_scan: select_ir_scan = 1'b1;
`STATE_capture_ir: capture_ir = 1'b1;
`STATE_shift_ir: shift_ir = 1'b1;
`STATE_exit1_ir: exit1_ir = 1'b1;
`STATE_pause_ir: pause_ir = 1'b1;
`STATE_exit2_ir: exit2_ir = 1'b1;
`STATE_update_ir: update_ir = 1'b1;
default: ;
endcase
end
/**********************************************************************************
* *
* End: TAP State Machine *
* *
**********************************************************************************/
/**********************************************************************************
* *
* jtag_ir: JTAG Instruction Register *
* *
**********************************************************************************/
reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg;
wire instruction_tdo;
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
else if (test_logic_reset == 1)
jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
else if(capture_ir)
jtag_ir <= 4'b0101; // This value is fixed for easier fault detection
else if(shift_ir)
jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX
// Updating jtag_ir (Instruction Register)
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
always @ (negedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
else if (test_logic_reset)
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
else if(update_ir)
latched_jtag_ir <= jtag_ir;
end
/**********************************************************************************
* *
* End: jtag_ir *
* *
**********************************************************************************/
/**********************************************************************************
* *
* idcode logic *
* *
**********************************************************************************/
reg [31:0] idcode_reg;
wire idcode_tdo;
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
else if (test_logic_reset)
idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
else if(idcode_select & capture_dr)
idcode_reg <= `IDCODE_VALUE;
else if(idcode_select & shift_dr)
idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};
end
assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX
/**********************************************************************************
* *
* End: idcode logic *
* *
**********************************************************************************/
/**********************************************************************************
* *
* Bypass logic *
* *
**********************************************************************************/
wire bypassed_tdo;
reg bypass_reg; // This is a 1-bit register
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if (trstn_pad_i == 0)
bypass_reg <= 1'b0;
else if (test_logic_reset == 1)
bypass_reg <= 1'b0;
else if (bypass_select & capture_dr)
bypass_reg<= 1'b0;
else if(bypass_select & shift_dr)
bypass_reg<= tdi_pad_i;
end
assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX
/**********************************************************************************
* *
* End: Bypass logic *
* *
**********************************************************************************/
/**********************************************************************************
* *
* Selecting active data register *
* *
**********************************************************************************/
always @ (latched_jtag_ir)
begin
user1_select = 1'b0;
sample_preload_select = 1'b0;
idcode_select = 1'b0;
user1_select = 1'b0;
debug_select = 1'b0;
bypass_select = 1'b0;
case(latched_jtag_ir) /* synthesis parallel_case */
`USER1: user1_select = 1'b1; // External test
`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
`IDCODE: idcode_select = 1'b1; // ID Code
`USER2: user1_select = 1'b1; // Mbist test
`DEBUG: debug_select = 1'b1; // Debug
`BYPASS: bypass_select = 1'b1; // BYPASS
default: bypass_select = 1'b1; // BYPASS
endcase
end
/**********************************************************************************
* *
* Multiplexing TDO data *
* *
**********************************************************************************/
reg tdo_mux_out; // really just a wire
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or
bs_chain_tdo_i)
begin
if(shift_ir)
tdo_mux_out = instruction_tdo;
else
begin
case(latched_jtag_ir) // synthesis parallel_case
`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
`DEBUG: tdo_mux_out = debug_tdo_i; // Debug
`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading
`USER1: tdo_mux_out = bs_chain_tdo_i; // External test
`USER2: tdo_mux_out = mbist_tdo_i; // Mbist test
default: tdo_mux_out = bypassed_tdo; // BYPASS instruction
endcase
end
end
// TDO changes state at negative edge of TCK
always @ (negedge tck_pad_i)
begin
tdo_pad_o = tdo_mux_out;
end
// Tristate control for tdo_pad_o pin
always @ (posedge tck_pad_i)
begin
tdo_padoe_o <= shift_ir | shift_dr;
end
/**********************************************************************************
* *
* End: Multiplexing TDO data *
* *
**********************************************************************************/
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_hwbrk.v
//
// *Module Description:
// Hardware Breakpoint / Watchpoint module
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 57 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mo, 01 Feb 2010) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_din, // Debug register data input
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
eu_mdb_in, // Memory data bus input
eu_mdb_out, // Memory data bus output
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
pc, // Program counter
por // Power on reset
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input [15:0] dbg_din; // Debug register data input
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] eu_mdb_in; // Memory data bus input
input [15:0] eu_mdb_out; // Memory data bus output
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: '10' & '11' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge mclk or posedge por)
if (por) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
addr1_wr_set, addr1_rd_set,
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge mclk or posedge por)
if (por) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge mclk or posedge por)
if (por) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge mclk or posedge por)
if (por) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
reg fe_mb_en_buf;
always @ (posedge mclk or posedge por)
if (por) fe_mb_en_buf <= 1'b0;
else fe_mb_en_buf <= fe_mb_en;
wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
// before being written back. In that case, the read flag should not be set.
// In general, We should here make sure no write access occures during the
// same instruction cycle before setting the read flag.
reg [2:0] d_rd_trig;
always @ (posedge mclk or posedge por)
if (por) d_rd_trig <= 3'h0;
else if (exec_done) d_rd_trig <= 3'h0;
else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr;
wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr;
wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule // omsp_dbg_hwbrk
`include "openMSP430_undefines.v"
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_1_V
`define SKY130_FD_SC_HDLL__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_1_V
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "deepgate_include.v"
module deepgate_top(
// 50MHz clock input
input clk50MHz,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output wire [7:0] led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
//SDRAM interface
output sdram_clk,
output sdram_cle,
output sdram_dqm,
output sdram_cs,
output sdram_we,
output sdram_cas,
output sdram_ras,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq
);
`include "param_include.v"
wire rst = ~rst_n; //becomes active high
wire clk;
//wire pllLock;
wire pllFeedbackClk;
/*
PLL_BASE#(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.0),
.CLKIN_PERIOD ("20"),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_DUTY_CYCLE (0.5),
.CLKOUT0_PHASE (0.0),
.CLK_FEEDBACK ("CLKFBOUT"),
//.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.REF_JITTER (0.1),
.RESET_ON_LOSS_OF_LOCK ("FALSE")
)
PLL_BASE_inst(
.CLKFBOUT (pllFeedbackClk),
.CLKOUT0 (clk),
// .LOCKED (pllLock),
.CLKFBIN (pllFeedbackClk),
.CLKIN (clk50MHz),
.RST (0)
);
*/
assign clk = clk50MHz;
wire [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
wire newTXData;
avr_interface AVR (
.clk (clk),
.rst (rst),
.cclk (cclk),
.spi_miso (spi_miso),
.spi_mosi (spi_mosi),
.spi_sck (spi_sck),
.spi_ss (spi_ss),
.spi_channel (spi_channel),
.tx (avr_rx),
.rx (avr_tx),
.channel (4'd15),
.tx_data (tx_data),
.new_tx_data (newTXData),
.tx_busy (tx_busy),
.tx_block (avr_rx_busy),
.rx_data (rx_data),
.new_rx_data (new_rx_data)
);
wire [31:0] sdramDataTX;
wire [31:0] sdramDataRX;
wire [22:0] sdramAddr;
wire sdramBusy;
wire sdramTXValid;
wire sdramRXValid;
wire sdramRW;
sdram SDRAM (
.clk (clk),
.rst (rst),
// these signals go directly to the IO pins
.sdram_clk (sdram_clk),
.sdram_cle (sdram_cle),
.sdram_cs (sdram_cs),
.sdram_cas (sdram_cas),
.sdram_ras (sdram_ras),
.sdram_we (sdram_we),
.sdram_dqm (sdram_dqm),
.sdram_ba (sdram_ba),
.sdram_a (sdram_a),
.sdram_dq (sdram_dq),
// User interface
.addr (sdramAddr), // address to read/write
.rw (sdramRW), // 1 = write, 0 = read
.data_in (sdramDataTX), // sdram data to write
.data_out (sdramDataRX), // sdram data from read
.busy (sdramBusy), // controller is busy when high
.in_valid (sdramTXValid), // pulse high to initiate a read/write
.out_valid (sdramRXValid) // pulses high when data from read is valid
);
wire procBegin;
wire procComplete;
wire [7:0] networkDataIn;
wire [7:0] networkOut;
wire networkIdle;
wire networkRead;
wire inputRead;
wire [7:0] weightData;
wire [NUM_TILES - 1'b1 : 0] pipelineLock;
wire [NUM_TILES - 1'b1 : 0] weightRAMwrEn;
//neural network
tile_network ANN(
.clk_i (clk),
.en_i (procBegin),
.data_rd_o (inputRead),
.data_rd_i (networkRead),
.data_i (networkDataIn),
.network_idle_o (networkIdle),
.data_o (networkOut),
.proc_complete_o (procComplete),
.weight_wr_i (weightRAMwrEn),
.weight_data_i (weightData),
.pipeline_lock_o (pipelineLock)
);
master_control MCU(
.clk (clk),
.rst (rst),
//AVR SPI
.TXBusy (tx_busy),
.newRXData (new_rx_data),
.RXData (rx_data),
.TXDataBuffer (tx_data),
.newTXData (newTXData),
//MLPNN
.inputRead (inputRead),
.networkIdle (networkIdle),
.procComplete (procComplete),
.networkOut (networkOut),
.networkDataIn (networkDataIn),
.procBegin (procBegin),
.networkRead (networkRead),
.weightRAMwrEn (weightRAMwrEn),
.weightDataOut (weightData),
.pipelineLock (pipelineLock),
.sdramBusy (sdramBusy),
.sdramRXValid (sdramRXValid),
.sdramDataRX (sdramDataRX),
.sdramDataTX (sdramDataTX),
.sdramAddr (sdramAddr),
.sdramTXValid (sdramTXValid),
.sdramRW (sdramRW),
.LED (led)
);
endmodule
|
`default_nettype none
//---------------------------------------------------------------------
//-- --
//-- Company: University of Bonn --
//-- Engineer: John Bieling --
//-- --
//---------------------------------------------------------------------
//-- --
//-- Copyright (C) 2015 John Bieling --
//-- --
//-- This program is free software; you can redistribute it and/or --
//-- modify it under the terms of the GNU General Public License as --
//-- published by the Free Software Foundation; either version 3 of --
//-- the License, or (at your option) any later version. --
//-- --
//-- This program is distributed in the hope that it will be useful, --
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
//-- GNU General Public License for more details. --
//-- --
//-- You should have received a copy of the GNU General Public --
//-- License along with this program; if not, see --
//-- <http://www.gnu.org/licenses>. --
//-- --
//---------------------------------------------------------------------
//-- The module can be configured with these parameters (defaults given in braces):
//--
//-- shift_bitsize(9) : BRAM needs a 9bit-address, but the desired shift could be
//-- much less and thus the logic to generate that address
//-- does not need to handle all 9bits
//--
//-- width(1) : BRAM is 32Bit wide. The width parameter defines how many of them
//-- should be used parallel to allow shifts of larger patterns
module BRAMSHIFT_512 (d, q, shift, CLK);
parameter shift_bitsize = 9;
parameter width = 1;
parameter input_pipe_steps = 0;
parameter output_pipe_steps = 0;
output wire [(width*32)-1:0] q;
input wire [(width*32)-1:0] d;
input wire CLK;
input wire [shift_bitsize-1:0] shift;
reg [shift_bitsize-1:0] a_read;
reg [shift_bitsize-1:0] a_write;
reg [shift_bitsize-1:0] true_shift;
wire [(width*32)-1:0] sigin;
datapipe #(.data_width(width*32),.pipe_steps(input_pipe_steps)) input_pipe (
.data(d),
.piped_data(sigin),
.CLK(CLK));
wire [(width*32)-1:0] sigout;
datapipe #(.data_width(width*32),.pipe_steps(output_pipe_steps)) output_pipe (
.data(sigout),
.piped_data(q),
.CLK(CLK));
always@(posedge CLK)
begin
true_shift <= shift + 2; //compensate internal delays, shift is usually tigged
a_read <= a_read + 1;
a_write <= a_read + true_shift;
end
genvar k;
generate
for (k=0; k < width; k=k+1) begin : BRAMS
RAMB16_S36_S36 #(
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 127
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 128 to 255
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 256 to 383
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 384 to 511
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// The next set of INITP_xx are for the parity bits
// Address 0 to 127
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 128 to 255
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 256 to 383
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 384 to 511
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAMB32_SHIFT (
.DOA(sigout[((k+1)*32)-1:(k*32)]), // Port A 32-bit Data Output
.DOB(), // Port B 32-bit Data Output
.ADDRA({'b0,a_read}), // Port A 9-bit Address Input
.ADDRB({'b0,a_write}), // Port B 9-bit Address Input
.CLKA(CLK), // Port A Clock
.CLKB(CLK), // Port B Clock
.DIA('b0), // Port A 32-bit Data Input
.DIB(sigin[((k+1)*32)-1:(k*32)]), // Port B 32-bit Data Input
.DOPA(), // Port A 4-bit Parity Output
.DOPB(), // Port B 4-bit Parity Output
.DIPA('b0), // Port A 4-bit parity Input
.DIPB('b0), // Port-B 4-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.ENB(1'b1), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.WEB(1'b1) // Port B Write Enable Input
);
end
endgenerate
endmodule
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module UARTSample(
clk_x4,
rst_x,
i_rx,
o_tx,
o_data,
o_tx_error,
o_rx_error);
input clk_x4;
input rst_x;
input i_rx;
output o_tx;
output [7:0] o_data;
output o_tx_error;
output o_rx_error;
wire [7:0] w_out;
wire w_out_valid;
wire w_tx_error;
wire w_rx_error;
wire w_busy;
wire w_busy_posedge;
reg [7:0] r_in;
reg r_in_valid;
reg r_tx_error;
reg r_rx_error;
reg [7:0] r_data;
reg [2:0] r_state;
reg r_busy_d;
localparam S_TX_WAIT = 3'b000;
localparam S_TX_H = 3'b001;
localparam S_TX_E = 3'b011;
localparam S_TX_L = 3'b010;
localparam S_TX_O = 3'b110;
localparam C_H = 8'h48;
localparam C_E = 8'h45;
localparam C_L = 8'h4c;
localparam C_O = 8'h4f;
assign o_tx_error = r_tx_error;
assign o_rx_error = r_rx_error;
assign o_data = r_data;
assign w_in = 8'h00;
assign w_in_valid = 1'b0;
assign w_busy_posedge = !r_busy_d & w_busy;
assign w_busy_negedge = r_busy_d & !w_busy;
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_tx_error <= 1'b0;
end else begin
r_tx_error <= r_tx_error | w_tx_error;
end
end
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_rx_error <= 1'b0;
end else begin
r_rx_error <= r_rx_error | w_rx_error;
end
end
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_data <= 8'h00;
end else begin
if (w_out_valid) begin
r_data <= w_out;
end
end
end
always @ (posedge clk_x4) begin
r_busy_d <= w_busy;
end
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_state <= S_TX_WAIT;
r_in <= 8'h00;
r_in_valid <= 1'b0;
end else begin
case (r_state)
S_TX_WAIT: begin
if ((w_out == 8'h0d) && w_out_valid) begin
r_state <= S_TX_H;
r_in <= C_H;
r_in_valid <= 1'b1;
end
end
S_TX_H: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_E;
r_in <= C_E;
r_in_valid <= 1'b1;
end
end
S_TX_E: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_L;
r_in <= C_L;
r_in_valid <= 1'b1;
end
end
S_TX_L: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_O;
r_in <= C_O;
r_in_valid <= 1'b1;
end
end
S_TX_O: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_WAIT;
r_in <= 8'h00;
end
end
endcase
end
end
UART uart(
.clk_x4 (clk_x4 ),
.rst_x (rst_x ),
.i_rx (i_rx ),
.o_tx (o_tx ),
.i_data (r_in ),
.i_valid (r_in_valid ),
.o_busy (w_busy ),
.o_data (w_out ),
.o_valid (w_out_valid),
.o_tx_error(w_tx_error ),
.o_rx_error(w_rx_error ));
endmodule // UARTSample
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll100M.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll100M (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll100M",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll100M.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll100M.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll100M.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll100M.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll100M.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll100M.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll100M_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll100M_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Feb 14 01:38:42 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
module EggTimer(
input [7:0]SW,
input [2:0]KEY,
input CLOCK_50,
output [6:0]HEX0,
output [6:0]HEX1,
output [6:0]HEX2,
output [6:0]HEX3,
output [9:0]LEDR,
output [7:0]LEDG
);
reg [3:0] counter0 = 0;
reg [3:0] counter1 = 0;
reg [3:0] counter2 = 0;
reg [3:0] counter3 = 0;
reg [9:0] ledr_buf = 10'b0000000000;
reg [0:0] pause = 0; //0 is pause, 1 is continue
reg [0:0] reset_buf = 1;
wire RESET;
wire KEY2 = KEY[2];
//Get clock signal of period=1000ms
ClkDivider(CLOCK_50, CLK);
/*
* PAUSE SIGNAL
*/
TFlipFlop(.t(~KEY2), .clk(CLOCK_50), .q(PAUSE));
TFlipFlop(.t(~KEY[1]), .clk(CLOCK_50), .q(MINUTE));
DFlipFlop(.d(~KEY[0]), .clk(CLOCK_50), .q(RESET));
assign LEDG[0] = RESET;
assign LEDG[1] = ~KEY2;
assign LEDG[2] = pause;
assign LEDG[3] = reset_buf;
always @(posedge CLK or posedge RESET or posedge ~KEY2) begin
if (~KEY2 == 1'b1) begin
pause <= ~PAUSE;
reset_buf <= 0;
end else
if (RESET == 1'b1) begin
reset_buf <= 1;
pause <= 0;
counter0 <= 0;
counter1 <= 0;
counter2 <= 0;
counter3 <= 0;
ledr_buf <= 0;
end else
if (CLK == 1'b1) begin
if (pause == 1'b0) begin
if (reset_buf == 1) begin
if (MINUTE == 1'b0) begin
if (SW[3:0] <= 9) begin
counter0 <= SW[3:0];
end else begin
counter0 <= 9;
end
if (SW[7:4] <= 5) begin
counter1 <= SW[7:4];
end else begin
counter1 <= 5;
end
end
if (MINUTE == 1'b1) begin
if (SW[3:0] <= 9) begin
counter2 <= SW[3:0];
end else begin
counter2 <= 9;
end
if (SW[7:4] <= 5) begin
counter3 <= SW[7:4];
end else begin
counter3 <= 5;
end
end
end
end else if (pause == 1'b1) begin
if (counter0 != 0) begin
counter0 <= counter0 - 1;
end else if (counter1 != 0) begin
counter1 <= counter1 - 1;
counter0 <= 9;
end else if (counter2 != 0) begin
counter2 <= counter2 - 1;
counter1 <= 5;
counter0 <= 9;
end else if (counter3 != 0) begin
counter3 <= counter3 - 1;
counter2 <= 9;
counter1 <= 5;
counter0 <= 9;
end else
if (reset_buf == 0) begin
ledr_buf <= ~ledr_buf;
end
end
end
end
seven_seg(counter0, HEX0);
seven_seg(counter1, HEX1);
seven_seg(counter2, HEX2);
seven_seg(counter3, HEX3);
ledr(ledr_buf, LEDR[9:0]);
endmodule
module ClkDivider(input clkIn, output clkOut);
reg[31: 0] counter;
reg clkReg;
assign clkOut = clkReg;
always @(posedge clkIn) begin
counter <= counter + 1;
if (counter == 25000000) begin
clkReg <= ~clkReg;
counter <= 0;
end
end
endmodule
module seven_seg (
input [3:0] num,
output [6:0] display
);
assign display =
num == 0 ? ~7'b0111111:
num == 1 ? ~7'b0000110:
num == 2 ? ~7'b1011011:
num == 3 ? ~7'b1001111:
num == 4 ? ~7'b1100110:
num == 5 ? ~7'b1101101:
num == 6 ? ~7'b1111101:
num == 7 ? ~7'b0000111:
num == 8 ? ~7'b1111111:
num == 9 ? ~7'b1100111:
7'bxxxxxxx;
endmodule
module ledr(
input [9:0] buffer,
output [9:0] lights
);
assign lights = buffer;
endmodule
module TFlipFlop(
input t, clk,
output reg q
);
always @(posedge t) begin
if (t) q = ~q;
end
endmodule
module DFlipFlop(
input d, clk,
output reg q
);
always @(posedge clk) begin
if (q != d) q = d;
end
endmodule
module Inverter (
input positive,
output negative
);
assign negative = ~positive;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// synchronize flag (signal lasts just one clock cycle) to new clock domain (CLK_B)
module flag_domain_crossing(
input wire CLK_A,
input wire CLK_B,
input wire FLAG_IN_CLK_A,
output wire FLAG_OUT_CLK_B
);
reg FLAG_TOGGLE_CLK_A;
initial FLAG_TOGGLE_CLK_A = 0;
always @(posedge CLK_A)
begin
if (FLAG_IN_CLK_A)
begin
FLAG_TOGGLE_CLK_A <= ~FLAG_TOGGLE_CLK_A;
end
end
(* ASYNC_REG = "TRUE" *) reg flag_out_d_ff_1;
(* ASYNC_REG = "TRUE" *) reg flag_out_d_ff_2;
reg flag_out_d_ff_3;
always @(posedge CLK_B) // first stage
begin
flag_out_d_ff_1 <= FLAG_TOGGLE_CLK_A;
end
always @(posedge CLK_B) // second stage
begin
flag_out_d_ff_2 <= flag_out_d_ff_1;
end
always @(posedge CLK_B)
begin
flag_out_d_ff_3 <= flag_out_d_ff_2;
end
assign FLAG_OUT_CLK_B = (flag_out_d_ff_3 ^ flag_out_d_ff_2); // XOR
endmodule
|
// Verilog wrapper around VHDL Bias Worker
// ssiegel 2012-10-06
module mkBiasWorker4B(
input wciS0_Clk,
input wciS0_MReset_n,
input [2 : 0] wciS0_MCmd,
input wciS0_MAddrSpace,
input [3 : 0] wciS0_MByteEn,
input [31 : 0] wciS0_MAddr,
input [31 : 0] wciS0_MData,
output [1 : 0] wciS0_SResp,
output [31 : 0] wciS0_SData,
output wciS0_SThreadBusy,
output [1 : 0] wciS0_SFlag,
input [1 : 0] wciS0_MFlag,
input [2 : 0] wsiS0_MCmd,
input wsiS0_MReqLast,
input wsiS0_MBurstPrecise,
input [11 : 0] wsiS0_MBurstLength,
input [31 : 0] wsiS0_MData,
input [3 : 0] wsiS0_MByteEn,
input [7 : 0] wsiS0_MReqInfo,
output wsiS0_SThreadBusy,
output wsiS0_SReset_n,
input wsiS0_MReset_n,
output [2 : 0] wsiM0_MCmd,
output wsiM0_MReqLast,
output wsiM0_MBurstPrecise,
output [11 : 0] wsiM0_MBurstLength,
output [31 : 0] wsiM0_MData,
output [3 : 0] wsiM0_MByteEn,
output [7 : 0] wsiM0_MReqInfo,
input wsiM0_SThreadBusy,
output wsiM0_MReset_n,
input wsiM0_SReset_n );
// Instance the VHDL Bias Worker "bias_vhdl"...
bias_vhdl bias_vi(
.ctl_Clk (wciS0_Clk), // in std_logic;
.ctl_MAddr (wciS0_MAddr[4:0]), // in std_logic_vector(4 downto 0);
.ctl_MAddrSpace (wciS0_MAddrSpace), // in std_logic_vector(0 downto 0);
.ctl_MCmd (wciS0_MCmd), // in std_logic_vector(2 downto 0);
.ctl_MData (wciS0_MData), // in std_logic_vector(31 downto 0);
.ctl_MFlag (wciS0_MFlag), // in std_logic_vector(1 downto 0);
.ctl_MReset_n (wciS0_MReset_n), // in std_logic;
.ctl_SData (wciS0_SData), // out std_logic_vector(31 downto 0);
.ctl_SFlag (wciS0_SFlag), // out std_logic_vector(1 downto 0);
.ctl_SResp (wciS0_SResp), // out std_logic_vector(1 downto 0);
.ctl_SThreadBusy (wciS0_SThreadBusy), // out std_logic_vector(0 downto 0);
.in_MBurstLength (wsiS0_MBurstLength), // in std_logic_vector(11 downto 0);
.in_MByteEn (wsiS0_MByteEn), // in std_logic_vector(3 downto 0);
.in_MCmd (wsiS0_MCmd), // in std_logic_vector(2 downto 0);
.in_MData (wsiS0_MData), // in std_logic_vector(31 downto 0);
.in_MBurstPrecise (wsiS0_MBurstPrecise), // in std_logic;
.in_MReqInfo (wsiS0_MReqInfo), // in std_logic_vector(7 downto 0);
.in_MReqLast (wsiS0_MReqLast), // in std_logic;
.in_MReset_n (wsiS0_MReset_n), // in std_logic;
.in_SReset_n (wsiS0_SReset_n), // out std_logic;
.in_SThreadBusy (wsiS0_SThreadBusy), // out std_logic_vector(0 downto 0);
.out_SReset_n (wsiM0_SReset_n), // in std_logic;
.out_SThreadBusy (wsiM0_SThreadBusy), // in std_logic_vector(0 downto 0);
.out_MBurstLength (wsiM0_MBurstLength), // out std_logic_vector(11 downto 0);
.out_MByteEn (wsiM0_MByteEn), // out std_logic_vector(3 downto 0);
.out_MCmd (wsiM0_MCmd), // out std_logic_vector(2 downto 0);
.out_MData (wsiM0_MData), // out std_logic_vector(31 downto 0);
.out_MBurstPrecise (wsiM0_MBurstPrecise), // out std_logic;
.out_MReqInfo (wsiM0_MReqInfo), // out std_logic_vector(7 downto 0);
.out_MReqLast (wsiM0_MReqLast), // out std_logic;
.out_MReset_n (wsiM0_MReset_n) // out std_logic
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
* size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assume (0) else $info("Info message from failing assumption");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4B_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4b (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_BLACKBOX_V
|
`include "bsg_defines.v"
module bsg_mul_booth_4_block_rep #(parameter [31:0] blocks_p=1
,parameter S_above_vec_p=0
,parameter dot_bar_vec_p=0
,parameter B_vec_p=0
,parameter one_vec_p=0
)
( input [4:0][2:0] SDN_i
, input cr_i
, input [blocks_p-1:0][3:0][1:0] y_vec_i
, output cl_o
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
wire [blocks_p:0] ci_local;
genvar i;
for (i = 0; i < blocks_p; i=i+1)
begin: rof
localparam S_above_vec_tmp = (S_above_vec_p >> (i << 2)) & 4'hf;
localparam S_dot_bar_vec_tmp = (dot_bar_vec_p >> (i << 2)) & 4'hf;
localparam B_vec_tmp = (B_vec_p >> (i << 2)) & 4'hf;
localparam one_vec_tmp = (one_vec_p >> (i << 2)) & 4'hf;
bsg_mul_booth_4_block #(
.S_above_vec_p(S_above_vec_tmp)
,.dot_bar_vec_p(S_dot_bar_vec_tmp)
,.B_vec_p(B_vec_tmp)
,.one_vec_p(one_vec_tmp)
)
b4b (.SDN_i(SDN_i), .y_i (y_vec_i[i])
, .cr_i(ci_local[i]), .cl_o(ci_local[i+1]), .c_o (c_o[i]), .s_o (s_o[i]));
end // block: rof
assign ci_local[0] = cr_i;
assign cl_o = ci_local[blocks_p];
endmodule // bsg_mul_booth_4_block_rep
|
`timescale 1 ns / 1 ps
module axi_bram_reader #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
reg int_arready_reg, int_arready_next;
reg int_rvalid_reg, int_rvalid_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_arready_reg <= 1'b0;
int_rvalid_reg <= 1'b0;
end
else
begin
int_arready_reg <= int_arready_next;
int_rvalid_reg <= int_rvalid_next;
end
end
always @*
begin
int_arready_next = int_arready_reg;
int_rvalid_next = int_rvalid_reg;
if(s_axi_arvalid)
begin
int_arready_next = 1'b1;
int_rvalid_next = 1'b1;
end
if(int_arready_reg)
begin
int_arready_next = 1'b0;
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign s_axi_rresp = 2'd0;
assign s_axi_arready = int_arready_reg;
assign s_axi_rdata = bram_porta_rddata;
assign s_axi_rvalid = int_rvalid_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = s_axi_araddr[ADDR_LSB+BRAM_ADDR_WIDTH-1:ADDR_LSB];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_comp_gen_fx_color
(
input clk,
input rstn,
input signed [31:0] dx_fx, // 16.16
input signed [31:0] dy_fx, // 16.16
input [95:0] cmp_i,
output [7:0] curr_i
);
reg signed [57:0] ix;
reg signed [57:0] iy;
reg signed [57:0] ixy;
reg signed [19:0] curr;
assign curr_i = (curr[19]) ? 8'h00 : // Under flow.
(curr[18]) ? 8'hff : // Over flow.
curr[17:10]; // Normal.
wire [17:0] sp_fx;
wire signed [25:0] idx_fx;
wire signed [25:0] idy_fx;
assign sp_fx = flt_fx_8p10(cmp_i[95:64]);
assign idx_fx = flt_fx_16p10(cmp_i[63:32]);
assign idy_fx = flt_fx_16p10(cmp_i[31:0]);
always @(posedge clk) begin
ix <= dx_fx * idx_fx; // 16.16 * 16.10 = 32.26
iy <= dy_fx * idy_fx; // 16.16 * 16.10 = 32.26
ixy <= iy + ix; // 32.26 + 32.26 = 32.26
curr <= ixy[35:16] + {2'b00, sp_fx}; // 10.10 + 10.10 = 10.10
end
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
function [25:0] flt_fx_16p10;
input [31:0] fp_in; // Floating point in IEEE fmt
// 16.10, Color.
reg [7:0] bias_exp; /* Real exponent -127 - 128 */
reg [7:0] bias_exp2; /* Real exponent 2's comp */
reg [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
begin
bias_mant = {25'h0001, fp_in[22:0]};
bias_exp = fp_in[30:23] - 8'd127;
bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[38:13];
flt_fx_16p10 = (fp_in[31]) ? ~fixed_out[25:0] + 26'h1 : fixed_out[25:0];
end
endfunction
function [17:0] flt_fx_8p10;
input [31:0] fp_in; // Floating point in IEEE fmt
// 16.10, Color.
reg [7:0] bias_exp; /* Real exponent -127 - 128 */
reg [7:0] bias_exp2; /* Real exponent 2's comp */
reg [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
begin
bias_mant = {25'h0001, fp_in[22:0]};
bias_exp = fp_in[30:23] - 8'd127;
bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[31:13];
flt_fx_8p10 = (fp_in[31]) ? ~fixed_out[17:0] + 18'h1 : fixed_out[17:0];
end
endfunction
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKINV_BLACKBOX_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_2_V
`define SKY130_FD_SC_LS__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_2_V
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
(** printing [-S-] %\ensuremath{\int}% #∫# *)
Require Export CoRN.ftc.MoreIntegrals.
Require Export CoRN.ftc.CalculusTheorems.
Opaque Min.
Section Indefinite_Integral.
(**
* The Fundamental Theorem of Calculus
Finally we can prove the fundamental theorem of calculus and its most
important corollaries, which are the main tools to formalize most of
real analysis.
** Indefinite Integrals
We define the indefinite integral of a function in a proper interval
in the obvious way; we just need to state a first lemma so that the
continuity proofs become unnecessary.
%\begin{convention}% Let [I : interval], [F : PartIR] be continuous in [I]
and [a] be a point in [I].
%\end{convention}%
*)
Variable I : interval.
Variable F : PartIR.
Hypothesis contF : Continuous I F.
Variable a : IR.
Hypothesis Ha : I a.
Lemma prim_lemma : forall x : IR, I x -> Continuous_I (Min_leEq_Max a x) F.
Proof.
intros.
elim contF; intros incI contI.
Included.
Qed.
Lemma Fprim_strext : forall x y Hx Hy,
Integral (prim_lemma x Hx) [#] Integral (prim_lemma y Hy) -> x [#] y.
Proof.
intros x y Hx Hy H.
elim (Integral_strext' _ _ _ _ _ _ _ _ _ H).
intro; elimtype False.
generalize a0; apply ap_irreflexive_unfolded.
auto.
Qed.
Definition Fprim : PartIR.
apply Build_PartFunct with (pfpfun := fun (x : IR) (Hx : I x) => Integral (prim_lemma x Hx)).
Proof.
apply iprop_wd.
exact Fprim_strext.
Defined.
End Indefinite_Integral.
Arguments Fprim [I F].
Notation "[-S-] F" := (Fprim F) (at level 20).
Section FTC.
(**
** The FTC
We can now prove our main theorem. We begin by remarking that the
primitive function is always continuous.
%\begin{convention}% Assume that [J : interval], [F : PartIR] is
continuous in [J] and [x0] is a point in [J]. Denote by [G] the
indefinite integral of [F] from [x0].
%\end{convention}%
*)
Variable J : interval.
Variable F : PartIR.
Hypothesis contF : Continuous J F.
Variable x0 : IR.
Hypothesis Hx0 : J x0.
(* begin hide *)
Let G := ( [-S-]contF) x0 Hx0.
(* end hide *)
Lemma Continuous_prim : Continuous J G.
Proof.
split.
Included.
intros a b Hab H. split.
Included.
intros e H0.
simpl in |- *; simpl in H.
exists (e[/] _[//] max_one_ap_zero (Norm_Funct (included_imp_Continuous _ _ contF _ _ _ H))).
apply div_resp_pos.
apply pos_max_one.
assumption.
intros x y H1 H2 Hx Hy H3.
cut (included (Compact (Min_leEq_Max y x)) (Compact Hab)).
intro Hinc.
cut (Continuous_I (Min_leEq_Max y x) F). intro H4.
apply leEq_wdl with (AbsIR (Integral H4)).
eapply leEq_transitive.
apply Integral_leEq_norm.
apply leEq_transitive with (Max (Norm_Funct (included_imp_Continuous _ _ contF _ _ _ H)) [1][*]
AbsIR (x[-]y)).
apply mult_resp_leEq_rht.
apply leEq_transitive with (Norm_Funct (included_imp_Continuous _ _ contF _ _ _ H)).
apply leEq_Norm_Funct.
intros.
apply norm_bnd_AbsIR.
apply Hinc; auto.
apply lft_leEq_Max.
apply AbsIR_nonneg.
eapply shift_mult_leEq'.
apply pos_max_one.
apply H3.
apply AbsIR_wd.
rstepl (Integral (prim_lemma J F contF x0 Hx0 y Hy) [+]Integral H4[-]
Integral (prim_lemma J F contF x0 Hx0 y Hy)).
apply cg_minus_wd.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 x y).
apply included_imp_Continuous with J; auto.
apply included3_interval; auto.
apply Integral_wd.
apply Feq_reflexive.
apply (included_trans _ (Compact (Min_leEq_Max x0 y)) J); Included.
apply included_imp_Continuous with J; auto.
Included.
Included.
Qed.
(**
The derivative of [G] is simply [F].
*)
Hypothesis pJ : proper J.
Theorem FTC1 : Derivative J pJ G F.
Proof.
split; Included.
split; Included.
intros; apply Derivative_I_char.
Included.
inversion_clear contF.
Included.
intros.
red in contF.
inversion_clear contF.
elim (contin_prop _ _ _ _ (X2 _ _ _ X) e X0); intros d H3 H4.
exists d.
assumption.
intros x y X3 X4 Hx Hy Hx' H.
simpl in |- *.
rename Hab into Hab'.
set (Hab := less_leEq _ _ _ Hab') in *.
cut (included (Compact (Min_leEq_Max x y)) (Compact Hab)).
intro Hinc.
cut (Continuous_I (Min_leEq_Max x y) F).
2: apply included_imp_Continuous with J; auto.
intro H8.
apply leEq_wdl with (AbsIR (Integral H8[-]
Integral (Continuous_I_const _ _ (Min_leEq_Max x y) (F x Hx')))).
apply leEq_wdl with (AbsIR (Integral (Continuous_I_minus _ _ _ _ _ H8
(Continuous_I_const _ _ _ (F x Hx'))))).
eapply leEq_transitive.
apply Integral_leEq_norm.
apply mult_resp_leEq_rht.
2: apply AbsIR_nonneg.
apply leEq_Norm_Funct.
intros z Hz Hz1.
simpl in |- *.
apply leEq_wdl with (AbsIR (F z (X1 z (X z (Hinc z Hz))) [-]F x Hx')).
2: apply AbsIR_wd; algebra.
apply H4; auto.
eapply leEq_transitive.
2: apply H.
eapply leEq_wdr.
2: apply eq_symmetric_unfolded; apply Abs_Max.
eapply leEq_wdr.
2: apply AbsIR_eq_x; apply shift_leEq_minus.
2: astepl (Min x y); apply Min_leEq_Max.
apply compact_elements with (Min_leEq_Max x y); auto.
apply compact_Min_lft.
apply AbsIR_wd; apply Integral_minus.
apply AbsIR_wd; apply cg_minus_wd.
rstepl (Integral (prim_lemma _ _ contF x0 Hx0 _ Hx) [+]Integral H8[-]
Integral (prim_lemma _ _ contF x0 Hx0 _ Hx)).
apply cg_minus_wd.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 y x).
apply included_imp_Continuous with J; auto.
apply included3_interval; auto.
apply Integral_wd. apply Feq_reflexive.
apply (included_trans _ (Compact (Min_leEq_Max x0 x)) J); try apply included_interval; auto.
apply Integral_const.
Included.
Included.
Qed.
(**
Any other function [G0] with derivative [F] must differ from [G] by a constant.
*)
Variable G0 : PartIR.
Hypothesis derG0 : Derivative J pJ G0 F.
Theorem FTC2 : {c : IR | Feq J (G{-}G0) [-C-]c}.
Proof.
apply FConst_prop with pJ.
apply Derivative_wdr with (F{-}F).
FEQ.
apply Derivative_minus; auto.
apply FTC1.
Qed.
(**
The following is another statement of the Fundamental Theorem of Calculus, also known as Barrow's rule.
*)
(* begin hide *)
Let G0_inc := Derivative_imp_inc _ _ _ _ derG0.
(* end hide *)
End FTC.
Theorem Barrow : forall J F (contF : Continuous J F)
(pJ:proper J) G0 (derG0 : Derivative J pJ G0 F)
a b (H : Continuous_I (Min_leEq_Max a b) F) Ha Hb,
let Ha' := Derivative_imp_inc _ _ _ _ derG0 a Ha in let Hb' := Derivative_imp_inc _ _ _ _ derG0 b Hb in Integral H [=] G0 b Hb'[-]G0 a Ha'.
Proof.
(* begin hide *)
intros J F contF pJ G0 derG0 a b H1 Ha Hb; intros.
pose (x0:=a).
pose (Hx0:=Ha).
set (G := ( [-S-]contF) x0 Hx0).
elim (@FTC2 J F contF x0 Hx0 pJ G0 derG0); intros c Hc.
elim Hc; intros H2 H.
elim H; clear H Hc; intros H3 H0.
(* Allow G0a to be G0 of a.
Allow G0b to be G0 of b. *)
set (G0a := G0 a Ha') in *.
set (G0b := G0 b Hb') in *.
rstepr (G0b[+]c[-] (G0a[+]c)).
(* Allow Ga to be G of a.
Allow Gb to be G of b.*)
set (Ga := G a Ha) in *.
set (Gb := G b Hb) in *.
apply eq_transitive_unfolded with (Gb[-]Ga).
unfold Ga, Gb, G in |- *; simpl in |- *.
cut (forall x y z : IR, z [=] x[+]y -> y [=] z[-]x). intro H5.
apply H5.
apply Integral_plus_Integral with (Min3_leEq_Max3 x0 b a).
apply included_imp_Continuous with J.
auto.
apply included3_interval; auto.
intros; apply eq_symmetric_unfolded.
rstepr (x[+]y[-]x); algebra.
cut (forall x y z : IR, x[-]y [=] z -> x [=] y[+]z); intros.
fold G in H0.
apply cg_minus_wd; unfold Ga, Gb, G0a, G0b in |- *; apply H; auto.
simpl in H0.
apply eq_transitive_unfolded with ((G{-}G0) b (Hb, Hb')).
2: apply H0 with (Hx := (Hb, Hb')).
simpl.
apply cg_minus_wd.
apply Integral_wd.
apply Feq_reflexive.
destruct H1 as [H1 _].
apply H1.
algebra.
auto.
auto.
change c with ([-C-]c a I).
apply eq_transitive_unfolded with ((G{-}G0) a (Ha, Ha')).
2: apply H0 with (Hx := (Ha, Ha')).
simpl.
apply cg_minus_wd.
apply Integral_wd.
apply Feq_reflexive.
destruct H1 as [H1 _].
intros y Hy.
apply H1.
apply (compact_wd _ _ (Min_leEq_Max a b) a).
apply compact_Min_lft.
unfold compact, x0 in Hy.
destruct Hy.
apply leEq_imp_eq.
astepl (Min a a). assumption.
apply Min_id.
stepr(Max a a). assumption.
apply Max_id.
algebra.
auto.
rstepl (y[+] (x[-]y)).
algebra.
Qed.
(* end hide *)
Hint Resolve Continuous_prim: continuous.
Hint Resolve FTC1: derivate.
Section Limit_of_Integral_Seq.
(**
** Corollaries
With these tools in our hand, we can prove several useful results.
%\begin{convention}% From this point onwards:
- [J : interval];
- [f : nat->PartIR] is a sequence of continuous functions (in [J]);
- [F : PartIR] is continuous in [J].
%\end{convention}%
In the first place, if a sequence of continuous functions converges
then the sequence of their primitives also converges, and the limit
commutes with the indefinite integral.
*)
Variable J : interval.
Variable f : nat -> PartIR.
Variable F : PartIR.
Hypothesis contf : forall n : nat, Continuous J (f n).
Hypothesis contF : Continuous J F.
Section Compact.
(**
We need to prove this result first for compact intervals.
%\begin{convention}% Assume that [a, b, x0 : IR] with [(f n)] and [F]
continuous in [[a,b]], $x0\in[a,b]$#x0∈[a,b]#; denote by
[(g n)] and [G] the indefinite integrals respectively of [(f n)] and
[F] with origin [x0].
%\end{convention}%
*)
Variables a b : IR.
Hypothesis Hab : a [<=] b.
Hypothesis contIf : forall n : nat, Continuous_I Hab (f n).
Hypothesis contIF : Continuous_I Hab F.
(* begin show *)
Hypothesis convF : conv_fun_seq' a b Hab f F contIf contIF.
(* end show *)
Variable x0 : IR.
Hypothesis Hx0 : J x0.
Hypothesis Hx0' : Compact Hab x0.
(* begin hide *)
Let g (n : nat) := ( [-S-]contf n) x0 Hx0.
Let G := ( [-S-]contF) x0 Hx0.
(* end hide *)
(* begin show *)
Hypothesis contg : forall n : nat, Continuous_I Hab (g n).
Hypothesis contG : Continuous_I Hab G.
(* end show *)
Lemma fun_lim_seq_integral : conv_fun_seq' a b Hab g G contg contG.
Proof.
assert (H : conv_norm_fun_seq _ _ _ _ _ contIf contIF).
apply conv_fun_seq'_norm; assumption.
intros e H0.
elim (Archimedes (AbsIR (b[-]a) [/] _[//]pos_ap_zero _ _ H0)); intros k Hk.
elim (H k); intros N HN.
exists N; intros.
assert (H2 : included (Compact (Min_leEq_Max x0 x)) (Compact Hab)).
apply included2_compact; auto.
simpl in |- *.
apply leEq_wdl with (AbsIR (Integral (Continuous_I_minus _ _ _ _ _ (prim_lemma _ _ (contf n) x0 Hx0 _
(contin_imp_inc _ _ _ _ (contg n) _ Hx)) (prim_lemma _ _ contF x0 Hx0 _
(contin_imp_inc _ _ _ _ contG _ Hx))))).
2: apply AbsIR_wd; apply Integral_minus.
eapply leEq_transitive.
apply Integral_leEq_norm.
apply leEq_transitive with (one_div_succ k[*]AbsIR (b[-]a)).
apply mult_resp_leEq_both.
apply positive_norm.
apply AbsIR_nonneg.
eapply leEq_transitive.
2: apply (HN n H1).
apply leEq_Norm_Funct; intros.
apply norm_bnd_AbsIR.
apply H2; auto.
apply compact_elements with Hab; auto.
unfold one_div_succ, Snring in |- *.
rstepl (AbsIR (b[-]a) [/] _[//]nring_ap_zero _ _ (sym_not_eq (O_S k))).
apply shift_div_leEq.
apply pos_nring_S.
eapply shift_leEq_mult'.
assumption.
apply less_leEq; eapply leEq_less_trans.
apply Hk.
simpl in |- *.
apply less_plusOne.
Qed.
End Compact.
(**
And now we can generalize it step by step.
*)
Lemma limit_of_integral : conv_fun_seq'_IR J f F contf contF -> forall x y Hxy,
included (Compact Hxy) J -> forall Hf HF,
Cauchy_Lim_prop2 (fun n => integral x y Hxy (f n) (Hf n)) (integral x y Hxy F HF).
Proof.
intros H x y Hxy H0 Hf HF.
assert (Hx : J x). apply H0; apply compact_inc_lft.
assert (Hy : J y). apply H0; apply compact_inc_rht.
set (g := fun n : nat => ( [-S-]contf n) x Hx) in *.
set (G := ( [-S-]contF) x Hx) in *.
set (Hxg := fun n : nat => Hy) in *.
apply Lim_wd with (Part G y Hy).
simpl in |- *; apply Integral_integral.
apply Cauchy_Lim_prop2_wd with (fun n : nat => Part (g n) y (Hxg n)).
2: intro; simpl in |- *; apply Integral_integral.
cut (forall n : nat, Continuous_I Hxy (g n)). intro H1.
cut (Continuous_I Hxy G). intro H2.
apply fun_conv_imp_seq_conv with (contf := H1) (contF := H2).
set (H4 := fun n : nat => included_imp_Continuous _ _ (contf n) _ _ _ H0) in *.
set (H5 := included_imp_Continuous _ _ contF _ _ _ H0) in *.
unfold g, G in |- *.
apply fun_lim_seq_integral with H4 H5.
unfold H4, H5 in |- *.
apply H; auto.
apply compact_inc_lft.
apply compact_inc_rht.
unfold G in |- *; apply included_imp_Continuous with J; Contin.
intro; unfold g in |- *; apply included_imp_Continuous with J; Contin.
Qed.
Lemma limit_of_Integral : conv_fun_seq'_IR J f F contf contF -> forall x y,
included (Compact (Min_leEq_Max x y)) J -> forall Hxy Hf HF,
Cauchy_Lim_prop2 (fun n => Integral (a:=x) (b:=y) (Hab:=Hxy) (F:=f n) (Hf n))
(Integral (Hab:=Hxy) (F:=F) HF).
Proof.
intros convF x y H.
set (x0 := Min x y) in *.
intros.
assert (Hx0 : J x0).
apply H; apply compact_inc_lft.
assert (Hx0' : Compact Hxy x0).
apply compact_inc_lft.
set (g := fun n : nat => ( [-S-]contf n) x0 Hx0) in *.
set (G := ( [-S-]contF) x0 Hx0) in *.
unfold Integral in |- *; fold x0 in |- *.
apply (Cauchy_Lim_minus (fun n : nat => integral _ _ _ _ (Integral_inc2 _ _ _ _ (Hf n)))
(fun n : nat => integral _ _ _ _ (Integral_inc1 _ _ _ _ (Hf n)))); fold x0 in |- *.
apply limit_of_integral with (Hf := fun n : nat => Integral_inc2 _ _ Hxy _ (Hf n)); auto.
apply included_trans with (Compact (Min_leEq_Max x y)); Included.
apply included_compact.
apply compact_inc_lft.
apply compact_Min_rht.
apply limit_of_integral with (Hf := fun n : nat => Integral_inc1 _ _ Hxy _ (Hf n)); auto.
apply included_trans with (Compact (Min_leEq_Max x y)); auto.
apply included_compact.
apply compact_inc_lft.
apply compact_Min_lft.
Qed.
Section General.
(**
Finally, with [x0, g, G] as before,
*)
(* begin show *)
Hypothesis convF : conv_fun_seq'_IR J f F contf contF.
(* end show *)
Variable x0 : IR.
Hypothesis Hx0 : J x0.
(* begin hide *)
Let g (n : nat) := ( [-S-]contf n) x0 Hx0.
Let G := ( [-S-]contF) x0 Hx0.
(* end hide *)
Hypothesis contg : forall n : nat, Continuous J (g n).
Hypothesis contG : Continuous J G.
Lemma fun_lim_seq_integral_IR : conv_fun_seq'_IR J g G contg contG.
Proof.
red in |- *; intros.
unfold g, G in |- *.
cut (J a). intro H.
set (h := fun n : nat => [-C-] (Integral (prim_lemma _ _ (contf n) x0 Hx0 a H))) in *.
set (g' := fun n : nat => h n{+} ( [-S-]contf n) a H) in *.
set (G' := [-C-] (Integral (prim_lemma _ _ contF x0 Hx0 a H)) {+} ( [-S-]contF) a H) in *.
assert (H0 : forall n : nat, Continuous_I Hab (h n)).
intro; unfold h in |- *; Contin.
cut (forall n : nat, Continuous_I Hab (( [-S-]contf n) a H)). intro H1.
assert (H2 : forall n : nat, Continuous_I Hab (g' n)).
intro; unfold g' in |- *; Contin.
cut (Continuous_I Hab (( [-S-]contF) a H)). intro H3.
assert (H4 : Continuous_I Hab G').
unfold G' in |- *; Contin.
apply conv_fun_seq'_wdl with g' H2 (included_imp_Continuous _ _ contG _ _ _ Hinc).
intro; FEQ.
simpl in |- *.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 x a).
apply included_imp_Continuous with J; Contin.
apply conv_fun_seq'_wdr with H2 G' H4.
FEQ.
simpl in |- *.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 x a).
apply included_imp_Continuous with J; Contin.
unfold g', G' in |- *.
apply conv_fun_seq'_wdl with (f := g')
(contf := fun n : nat => Continuous_I_plus _ _ _ _ _ (H0 n) (H1 n)) (contF := H4).
unfold g' in H2.
intro; apply Feq_reflexive; Included.
unfold g', G' in |- *.
apply (fun_Lim_seq_plus' _ _ Hab h (fun n : nat => ( [-S-]contf n) a H) H0 H1 _ _
(Continuous_I_const _ _ _ (Integral (prim_lemma _ _ contF x0 Hx0 a H))) H3).
unfold h in |- *.
apply seq_conv_imp_fun_conv
with (x := fun n : nat => Integral (prim_lemma _ _ (contf n) x0 Hx0 a H)).
apply limit_of_Integral with (Hf := fun n : nat => prim_lemma _ _ (contf n) x0 Hx0 a H); auto.
Included.
apply fun_lim_seq_integral with (fun n : nat => included_imp_Continuous _ _ (contf n) _ _ _ Hinc)
(included_imp_Continuous _ _ contF _ _ _ Hinc).
apply convF; auto.
apply compact_inc_lft.
apply included_imp_Continuous with J; Contin.
intro; apply included_imp_Continuous with J; Contin.
apply Hinc; apply compact_inc_lft.
Qed.
End General.
End Limit_of_Integral_Seq.
Section Limit_of_Derivative_Seq.
(**
Similar results hold for the sequence of derivatives of a converging sequence; this time the proof is easier, as we can do it directly for any kind of interval.
%\begin{convention}% Let [g] be the sequence of derivatives of [f] and [G] be the derivative of [F].
%\end{convention}%
*)
Variable J : interval.
Hypothesis pJ : proper J.
Variables f g : nat -> PartIR.
Variables F G : PartIR.
Hypothesis contf : forall n : nat, Continuous J (f n).
Hypothesis contF : Continuous J F.
Hypothesis convF : conv_fun_seq'_IR J f F contf contF.
Hypothesis contg : forall n : nat, Continuous J (g n).
Hypothesis contG : Continuous J G.
Hypothesis convG : conv_fun_seq'_IR J g G contg contG.
Hypothesis derf : forall n : nat, Derivative J pJ (f n) (g n).
Lemma fun_lim_seq_derivative : Derivative J pJ F G.
Proof.
elim (nonvoid_point _ (proper_nonvoid _ pJ)); intros a Ha.
set (h := fun n : nat => ( [-S-]contg n) a Ha) in *.
set (H := ( [-S-]contG) a Ha) in *.
assert (H0 : Derivative J pJ H G). unfold H in |- *; apply FTC1.
assert (H1 : forall n : nat, Derivative J pJ (h n) (g n)). intro; unfold h in |- *; apply FTC1.
assert (H2 : conv_fun_seq'_IR J _ _ (fun n : nat => Derivative_imp_Continuous _ _ _ _ (H1 n))
(Derivative_imp_Continuous _ _ _ _ H0)).
unfold h, H in |- *. eapply fun_lim_seq_integral_IR with (contf := contg); auto.
cut {c : IR | Feq J (F{-}H) [-C-]c}.
intro H3.
elim H3; clear H3; intros c Hc.
apply Derivative_wdl with (H{+} [-C-]c).
apply Feq_transitive with (H{+} (F{-}H)).
apply Feq_plus.
apply Feq_reflexive; Included.
apply Feq_symmetric; assumption.
clear Hc H2 H1; clearbody H.
FEQ.
apply Derivative_wdr with (G{+} [-C-][0]).
FEQ.
apply Derivative_plus; auto.
apply Derivative_const.
assert (H3 : forall n : nat, {c : IR | Feq J (f n{-}h n) [-C-]c}).
intro; apply FConst_prop with pJ.
apply Derivative_wdr with (g n{-}g n). FEQ. apply Derivative_minus; auto.
assert (contw : forall n : nat, Continuous J (f n{-}h n)). unfold h in |- *; Contin.
assert (contW : Continuous J (F{-}H)). unfold H in |- *; Contin.
apply fun_const_Lim with (fun n : nat => f n{-}h n) contw contW.
auto.
eapply fun_Lim_seq_minus'_IR.
apply convF.
apply H2.
assumption.
Qed.
End Limit_of_Derivative_Seq.
Section Derivative_Series.
(**
As a very important case of this result, we get a rule for deriving series.
*)
Variable J : interval.
Hypothesis pJ : proper J.
Variables f g : nat -> PartIR.
(* begin show *)
Hypothesis convF : fun_series_convergent_IR J f.
Hypothesis convG : fun_series_convergent_IR J g.
(* end show *)
Hypothesis derF : forall n : nat, Derivative J pJ (f n) (g n).
Lemma Derivative_FSeries : Derivative J pJ (FSeries_Sum convF) (FSeries_Sum convG).
Proof.
apply fun_lim_seq_derivative with (f := fun n : nat => FSum0 n f)
(contf := Continuous_Sum0 _ _ (convergent_imp_Continuous _ _ convF))
(contF := Continuous_FSeries_Sum _ _ convF) (g := fun n : nat => FSum0 n g)
(contg := Continuous_Sum0 _ _ (convergent_imp_Continuous _ _ convG))
(contG := Continuous_FSeries_Sum _ _ convG).
3: Deriv.
apply FSeries_conv.
apply FSeries_conv.
Qed.
End Derivative_Series.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_SYMBOL_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPMET1_PP_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapmet1 (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A31OI_FUNCTIONAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_FUNCTIONAL_V |
`include "macro.v"
module if_id_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`INST_ADDR_BUS] if_program_counter,
input wire[`INST_DATA_BUS] if_instruction,
output reg[`INST_ADDR_BUS] id_program_counter,
output reg[`INST_DATA_BUS] id_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
id_program_counter <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
id_instruction <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (stall[1] == `ENABLE && stall[2] == `DISABLE) begin
id_program_counter <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
id_instruction <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (stall[1] == `DISABLE) begin
id_program_counter <= if_program_counter;
id_instruction <= if_instruction;
end
end
endmodule // if_id_buffer
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 09:40:43
// Design Name:
// Module Name: counters_8bit_with_TD_ff
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counters_8bit_with_TD_ff(
input Clk,
input Enable,
input Clear,
output [7:0] Q
);
T_ff_with_D_ff SR0 (.Clk(Clk), .T(Enable), .reset_n(Clear), .Q(Q[0]));
T_ff_with_D_ff SR1 (.Clk(Clk), .T(Enable & Q[0]), .reset_n(Clear), .Q(Q[1]));
T_ff_with_D_ff SR2 (.Clk(Clk), .T(Enable & Q[0] & Q[1]), .reset_n(Clear), .Q(Q[2]));
T_ff_with_D_ff SR3 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2]), .reset_n(Clear), .Q(Q[3]));
T_ff_with_D_ff SR4 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3]), .reset_n(Clear), .Q(Q[4]));
T_ff_with_D_ff SR5 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4]), .reset_n(Clear), .Q(Q[5]));
T_ff_with_D_ff SR6 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5]), .reset_n(Clear), .Q(Q[6]));
T_ff_with_D_ff SR7 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5] & Q[6]), .reset_n(Clear), .Q(Q[7]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_2_V
`define SKY130_FD_SC_LS__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_2_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module decodes video streams from the Terasic CCD cameras. *
* *
******************************************************************************/
module altera_up_video_camera_decoder (
// Inputs
clk,
reset,
PIXEL_DATA,
LINE_VALID,
FRAME_VALID,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 9;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] PIXEL_DATA;
input LINE_VALID;
input FRAME_VALID;
input ready;
// Bidirectional
// Outputs
output reg [DW: 0] data;
output reg startofpacket;
output reg endofpacket;
output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_temps;
// Internal Registers
reg [DW: 0] io_pixel_data;
reg io_line_valid;
reg io_frame_valid;
reg frame_sync;
reg [DW: 0] temp_data;
reg temp_start;
reg temp_end;
reg temp_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
begin
io_pixel_data <= PIXEL_DATA;
io_line_valid <= LINE_VALID;
io_frame_valid <= FRAME_VALID;
end
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (read_temps)
begin
data <= temp_data;
startofpacket <= temp_start;
endofpacket <= temp_end;
valid <= temp_valid;
end
else if (ready)
valid <= 1'b0;
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
frame_sync <= 1'b0;
else if (~io_frame_valid)
frame_sync <= 1'b1;
else if (io_line_valid & io_frame_valid)
frame_sync <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
begin
temp_data <= 'h0;
temp_start <= 1'b0;
temp_end <= 1'b0;
temp_valid <= 1'b0;
end
else if (read_temps)
begin
temp_data <= io_pixel_data;
temp_start <= frame_sync;
temp_end <= ~io_frame_valid;
temp_valid <= io_line_valid & io_frame_valid;
end
else if (~io_frame_valid)
begin
temp_end <= ~io_frame_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign read_temps = (ready | ~valid) &
((io_line_valid & io_frame_valid) |
((temp_start | temp_end) & temp_valid));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
//Date : Wed Jun 13 09:35:49 2018
//Host : WK142 running 64-bit major release (build 9200)
//Command : generate_target PmodESP32.bd
//Design : PmodESP32
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "PmodESP32,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=PmodESP32,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=3,numReposBlks=3,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "PmodESP32.hwdef" *)
module PmodESP32
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_UART_araddr,
AXI_LITE_UART_arready,
AXI_LITE_UART_arvalid,
AXI_LITE_UART_awaddr,
AXI_LITE_UART_awready,
AXI_LITE_UART_awvalid,
AXI_LITE_UART_bready,
AXI_LITE_UART_bresp,
AXI_LITE_UART_bvalid,
AXI_LITE_UART_rdata,
AXI_LITE_UART_rready,
AXI_LITE_UART_rresp,
AXI_LITE_UART_rvalid,
AXI_LITE_UART_wdata,
AXI_LITE_UART_wready,
AXI_LITE_UART_wstrb,
AXI_LITE_UART_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
gpio_interrupt,
s_axi_aclk,
s_axi_aresetn,
uart_interrupt);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_LITE_GPIO, ADDR_WIDTH 9, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN PmodESP32_s_axi_aclk_0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [8:0]AXI_LITE_GPIO_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input [8:0]AXI_LITE_GPIO_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output [1:0]AXI_LITE_GPIO_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output [31:0]AXI_LITE_GPIO_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output [1:0]AXI_LITE_GPIO_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input [31:0]AXI_LITE_GPIO_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input [3:0]AXI_LITE_GPIO_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_LITE_UART, ADDR_WIDTH 4, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN PmodESP32_s_axi_aclk_0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [3:0]AXI_LITE_UART_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input [3:0]AXI_LITE_UART_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output [1:0]AXI_LITE_UART_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output [31:0]AXI_LITE_UART_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output [1:0]AXI_LITE_UART_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input [31:0]AXI_LITE_UART_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input [3:0]AXI_LITE_UART_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_wvalid;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin10_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin10_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin10_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin1_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin1_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin1_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin2_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin2_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin2_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin3_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin3_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin3_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin4_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin4_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin4_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin7_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin7_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin7_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin8_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin8_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin8_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin9_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin9_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin9_t;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 INTR.GPIO_INTERRUPT INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME INTR.GPIO_INTERRUPT, PortWidth 1, SENSITIVITY LEVEL_HIGH" *) output gpio_interrupt;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.S_AXI_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.S_AXI_ACLK, ASSOCIATED_BUSIF AXI_LITE_GPIO:AXI_LITE_UART, ASSOCIATED_RESET s_axi_aresetn, CLK_DOMAIN PmodESP32_s_axi_aclk_0, FREQ_HZ 100000000, PHASE 0.000" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.S_AXI_ARESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.S_AXI_ARESETN, POLARITY ACTIVE_LOW" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 INTR.UART_INTERRUPT INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME INTR.UART_INTERRUPT, PortWidth 1, SENSITIVITY EDGE_RISING" *) output uart_interrupt;
wire [3:0]S_AXI_0_1_ARADDR;
wire S_AXI_0_1_ARREADY;
wire S_AXI_0_1_ARVALID;
wire [3:0]S_AXI_0_1_AWADDR;
wire S_AXI_0_1_AWREADY;
wire S_AXI_0_1_AWVALID;
wire S_AXI_0_1_BREADY;
wire [1:0]S_AXI_0_1_BRESP;
wire S_AXI_0_1_BVALID;
wire [31:0]S_AXI_0_1_RDATA;
wire S_AXI_0_1_RREADY;
wire [1:0]S_AXI_0_1_RRESP;
wire S_AXI_0_1_RVALID;
wire [31:0]S_AXI_0_1_WDATA;
wire S_AXI_0_1_WREADY;
wire [3:0]S_AXI_0_1_WSTRB;
wire S_AXI_0_1_WVALID;
wire [8:0]S_AXI_1_1_ARADDR;
wire S_AXI_1_1_ARREADY;
wire S_AXI_1_1_ARVALID;
wire [8:0]S_AXI_1_1_AWADDR;
wire S_AXI_1_1_AWREADY;
wire S_AXI_1_1_AWVALID;
wire S_AXI_1_1_BREADY;
wire [1:0]S_AXI_1_1_BRESP;
wire S_AXI_1_1_BVALID;
wire [31:0]S_AXI_1_1_RDATA;
wire S_AXI_1_1_RREADY;
wire [1:0]S_AXI_1_1_RRESP;
wire S_AXI_1_1_RVALID;
wire [31:0]S_AXI_1_1_WDATA;
wire S_AXI_1_1_WREADY;
wire [3:0]S_AXI_1_1_WSTRB;
wire S_AXI_1_1_WVALID;
wire [3:0]axi_gpio_0_GPIO2_TRI_I;
wire [3:0]axi_gpio_0_GPIO2_TRI_O;
wire [3:0]axi_gpio_0_GPIO2_TRI_T;
wire [1:0]axi_gpio_0_GPIO_TRI_I;
wire [1:0]axi_gpio_0_GPIO_TRI_O;
wire [1:0]axi_gpio_0_GPIO_TRI_T;
wire axi_gpio_0_ip2intc_irpt;
wire axi_uartlite_0_UART_RxD;
wire axi_uartlite_0_UART_TxD;
wire axi_uartlite_0_interrupt;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire s_axi_aclk_0_1;
wire s_axi_aresetn_0_1;
assign AXI_LITE_GPIO_arready = S_AXI_1_1_ARREADY;
assign AXI_LITE_GPIO_awready = S_AXI_1_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = S_AXI_1_1_BRESP;
assign AXI_LITE_GPIO_bvalid = S_AXI_1_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = S_AXI_1_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = S_AXI_1_1_RRESP;
assign AXI_LITE_GPIO_rvalid = S_AXI_1_1_RVALID;
assign AXI_LITE_GPIO_wready = S_AXI_1_1_WREADY;
assign AXI_LITE_UART_arready = S_AXI_0_1_ARREADY;
assign AXI_LITE_UART_awready = S_AXI_0_1_AWREADY;
assign AXI_LITE_UART_bresp[1:0] = S_AXI_0_1_BRESP;
assign AXI_LITE_UART_bvalid = S_AXI_0_1_BVALID;
assign AXI_LITE_UART_rdata[31:0] = S_AXI_0_1_RDATA;
assign AXI_LITE_UART_rresp[1:0] = S_AXI_0_1_RRESP;
assign AXI_LITE_UART_rvalid = S_AXI_0_1_RVALID;
assign AXI_LITE_UART_wready = S_AXI_0_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_0_1_ARADDR = AXI_LITE_UART_araddr[3:0];
assign S_AXI_0_1_ARVALID = AXI_LITE_UART_arvalid;
assign S_AXI_0_1_AWADDR = AXI_LITE_UART_awaddr[3:0];
assign S_AXI_0_1_AWVALID = AXI_LITE_UART_awvalid;
assign S_AXI_0_1_BREADY = AXI_LITE_UART_bready;
assign S_AXI_0_1_RREADY = AXI_LITE_UART_rready;
assign S_AXI_0_1_WDATA = AXI_LITE_UART_wdata[31:0];
assign S_AXI_0_1_WSTRB = AXI_LITE_UART_wstrb[3:0];
assign S_AXI_0_1_WVALID = AXI_LITE_UART_wvalid;
assign S_AXI_1_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign S_AXI_1_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign S_AXI_1_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign S_AXI_1_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign S_AXI_1_1_BREADY = AXI_LITE_GPIO_bready;
assign S_AXI_1_1_RREADY = AXI_LITE_GPIO_rready;
assign S_AXI_1_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign S_AXI_1_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign S_AXI_1_1_WVALID = AXI_LITE_GPIO_wvalid;
assign gpio_interrupt = axi_gpio_0_ip2intc_irpt;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_0_1 = s_axi_aclk;
assign s_axi_aresetn_0_1 = s_axi_aresetn;
assign uart_interrupt = axi_uartlite_0_interrupt;
PmodESP32_axi_gpio_0_0 axi_gpio_0
(.gpio2_io_i(axi_gpio_0_GPIO2_TRI_I),
.gpio2_io_o(axi_gpio_0_GPIO2_TRI_O),
.gpio2_io_t(axi_gpio_0_GPIO2_TRI_T),
.gpio_io_i(axi_gpio_0_GPIO_TRI_I),
.gpio_io_o(axi_gpio_0_GPIO_TRI_O),
.gpio_io_t(axi_gpio_0_GPIO_TRI_T),
.ip2intc_irpt(axi_gpio_0_ip2intc_irpt),
.s_axi_aclk(s_axi_aclk_0_1),
.s_axi_araddr(S_AXI_1_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_0_1),
.s_axi_arready(S_AXI_1_1_ARREADY),
.s_axi_arvalid(S_AXI_1_1_ARVALID),
.s_axi_awaddr(S_AXI_1_1_AWADDR),
.s_axi_awready(S_AXI_1_1_AWREADY),
.s_axi_awvalid(S_AXI_1_1_AWVALID),
.s_axi_bready(S_AXI_1_1_BREADY),
.s_axi_bresp(S_AXI_1_1_BRESP),
.s_axi_bvalid(S_AXI_1_1_BVALID),
.s_axi_rdata(S_AXI_1_1_RDATA),
.s_axi_rready(S_AXI_1_1_RREADY),
.s_axi_rresp(S_AXI_1_1_RRESP),
.s_axi_rvalid(S_AXI_1_1_RVALID),
.s_axi_wdata(S_AXI_1_1_WDATA),
.s_axi_wready(S_AXI_1_1_WREADY),
.s_axi_wstrb(S_AXI_1_1_WSTRB),
.s_axi_wvalid(S_AXI_1_1_WVALID));
PmodESP32_axi_uartlite_0_0 axi_uartlite_0
(.interrupt(axi_uartlite_0_interrupt),
.rx(axi_uartlite_0_UART_RxD),
.s_axi_aclk(s_axi_aclk_0_1),
.s_axi_araddr(S_AXI_0_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_0_1),
.s_axi_arready(S_AXI_0_1_ARREADY),
.s_axi_arvalid(S_AXI_0_1_ARVALID),
.s_axi_awaddr(S_AXI_0_1_AWADDR),
.s_axi_awready(S_AXI_0_1_AWREADY),
.s_axi_awvalid(S_AXI_0_1_AWVALID),
.s_axi_bready(S_AXI_0_1_BREADY),
.s_axi_bresp(S_AXI_0_1_BRESP),
.s_axi_bvalid(S_AXI_0_1_BVALID),
.s_axi_rdata(S_AXI_0_1_RDATA),
.s_axi_rready(S_AXI_0_1_RREADY),
.s_axi_rresp(S_AXI_0_1_RRESP),
.s_axi_rvalid(S_AXI_0_1_RVALID),
.s_axi_wdata(S_AXI_0_1_WDATA),
.s_axi_wready(S_AXI_0_1_WREADY),
.s_axi_wstrb(S_AXI_0_1_WSTRB),
.s_axi_wvalid(S_AXI_0_1_WVALID),
.tx(axi_uartlite_0_UART_TxD));
PmodESP32_pmod_bridge_0_0 pmod_bridge_0
(.in1_O(axi_uartlite_0_UART_TxD),
.in2_I(axi_uartlite_0_UART_RxD),
.in_bottom_bus_I(axi_gpio_0_GPIO2_TRI_I),
.in_bottom_bus_O(axi_gpio_0_GPIO2_TRI_O),
.in_bottom_bus_T(axi_gpio_0_GPIO2_TRI_T),
.in_top_uart_gpio_bus_I(axi_gpio_0_GPIO_TRI_I),
.in_top_uart_gpio_bus_O(axi_gpio_0_GPIO_TRI_O),
.in_top_uart_gpio_bus_T(axi_gpio_0_GPIO_TRI_T),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
// Gain is assumed to be 0.75dB per bit.
module jt10_adpcmb_gain(
input rst_n,
input clk, // CPU clock
input cen55,
input [ 7:0] tl, // ADPCM Total Level
input signed [15:0] pcm_in,
output reg signed [15:0] pcm_out
);
wire signed [15:0] factor = {8'd0, tl};
wire signed [31:0] pcm_mul = pcm_in * factor; // linear gain
always @(posedge clk) if(cen55)
pcm_out <= pcm_mul[23:8];
endmodule // jt10_adpcm_gain
|
(** * PE: Partial Evaluation *)
(* Chapter written and maintained by Chung-chieh Shan *)
(** The [Equiv] chapter introduced constant folding as an example of a
program transformation and proved that it preserves the meaning of
programs. Constant folding operates on manifest constants such as
[ANum] expressions. For example, it simplifies the command [Y ::=
APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4]. However,
it does not propagate known constants along data flow. For
example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We might naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is like
running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Logic.FunctionalExtensionality.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import Maps.
Require Import Imp.
Require Import Smallstep.
(* ################################################################# *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(* ================================================================= *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if beq_id V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V'
means to reason by cases over [beq_id V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) :=
let H := fresh "Heq" i j in
destruct (beq_idP i j);
[ subst j | ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
- (* [] *) inversion H.
- (* :: *) simpl in H. simpl. compare V V'; auto. Qed.
(** In what follows, we will make heavy use of the [In] property from
the standard library, also defined in [Logic.v]: *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** Besides the various lemmas about [In] that we've already come
across, the following one (taken from the standard library) will
also be useful: *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
(** If a type [A] has an operator [beq] for testing equality of its
elements, we can compute a boolean [inb beq a l] for testing
whether [In a l] holds or not. *)
Fixpoint inb {A : Type} (beq : A -> A -> bool) (a : A) (l : list A) :=
match l with
| [] => false
| a'::l' => beq a a' || inb beq a l'
end.
(** It is easy to relate [inb] to [In] with the [reflect] property: *)
Lemma inbP : forall A : Type, forall beq : A->A->bool,
(forall a1 a2, reflect (a1 = a2) (beq a1 a2)) ->
forall a l, reflect (In a l) (inb beq a l).
Proof.
intros A beq beqP a l.
induction l as [|a' l' IH].
- constructor. intros [].
- simpl. destruct (beqP a a').
+ subst. constructor. left. reflexivity.
+ simpl. destruct IH; constructor.
* right. trivial.
* intros [H1 | H2]; congruence.
Qed.
(* ================================================================= *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
- (* AId *)
remember (pe_lookup pe_st i) as l. destruct l.
+ (* Some *) rewrite H with (n:=n) by apply Heql. reflexivity.
+ (* None *) reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_update (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => t_update (pe_update st pe_st) V n
end.
Example test_pe_update:
pe_update (t_update empty_state Y 1) [(X,3);(Z,2)]
= t_update (t_update (t_update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_update] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_update_correct: forall st pe_st V0,
pe_update st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold t_update.
compare V0 V; auto. rewrite <- beq_id_refl; auto. rewrite false_beq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_update] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_update_consistent: forall st pe_st,
pe_consistent (pe_update st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_update_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_update: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_update st pe_st V.
Proof. intros st pe_st H V. rewrite pe_update_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_update st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_update_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(* ================================================================= *)
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if leb n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_update st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
induction b; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_update st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_update st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0);
try destruct (leb n n0); reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st \\ c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(* ================================================================= *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_update] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if beq_id V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if beq_id V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
- (* [] *) destruct (beq_id V V0); reflexivity.
- (* :: *) simpl. compare V V'.
+ (* equal *) rewrite IHpe_st.
destruct (beq_idP V V0). reflexivity.
rewrite false_beq_id; auto.
+ (* not equal *) simpl. compare V0 V'.
* (* equal *) rewrite false_beq_id; auto.
* (* not equal *) rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if beq_id V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0.
- (* equal *) rewrite <- beq_id_refl; auto.
- (* not equal *) rewrite pe_remove_correct.
repeat rewrite false_beq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_update_update_remove: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update (t_update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality.
intros V0. unfold t_update. rewrite !pe_update_correct.
rewrite pe_remove_correct. destruct (beq_id V V0); reflexivity.
Qed.
Theorem pe_update_update_add: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold t_update. rewrite !pe_update_correct. rewrite pe_add_correct.
destruct (beq_id V V0); reflexivity. Qed.
(* ================================================================= *)
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_app_iff.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l =>
x :: filter (fun y => if beq_id x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
- (* -> *)
intros. inversion H; clear H.
left. assumption.
destruct (beq_idP h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite false_beq_id; auto.
- (* <- *)
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
- (* -> *)
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
- (* <- *)
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
{ (* Proof of assertion *)
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
exfalso. apply Heq. split. assumption. reflexivity. }
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve_by_invert.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_update] only depends on the
[pe_lookup] interpretation of partial states, [pe_update] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_update] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if inb beq_id V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V.
- rewrite <- beq_id_refl. reflexivity.
- rewrite false_beq_id; try congruence. reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof.
intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (inbP _ _ beq_idP V (pe_compare pe_st1 pe_st2)).
- reflexivity.
- apply pe_compare_correct. auto. Qed.
Theorem pe_compare_update: forall pe_st1 pe_st2 st,
pe_update st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_update st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if inb beq_id V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_update st pe_st =
pe_update (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_removes_correct. unfold assigned.
destruct (inbP _ _ beq_idP V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st \\ st1 -> (forall V, st1 V = st2 V) -> c / st \\ st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st \\ assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
- (* [] *) eapply ceval_extensionality. apply E_Skip. reflexivity.
- (* V::ids *)
remember (pe_lookup pe_st V) as lookup. destruct lookup.
+ (* Some *) eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold t_update. compare V V0.
* (* equal *) rewrite <- Heqlookup. rewrite <- beq_id_refl. reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
+ (* None *) eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0.
* (* equal *) rewrite <- Heqlookup.
rewrite <- beq_id_refl.
destruct (inbP _ _ beq_idP V ids); reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
Qed.
(* ================================================================= *)
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '\\' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st \\ c1' / pe_st' ->
c2 / pe_st' \\ c2' / pe_st'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 ->
c2 / pe_st \\ c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '\\' c1' '/' st'" := (pe_com c1 st c1' st').
Hint Constructors pe_com.
Hint Constructors ceval.
(* ================================================================= *)
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] \\ (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
\\ (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve_by_invert.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '\\' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st \\ st' ->
pe_update st' pe_st' = st'' ->
c' / pe_st' / st \\ st''
where "c' '/' pe_st' '/' st '\\' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') ->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve_by_invert);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. reflexivity.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
reflexivity.
- (* PE_Seq *)
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c' / pe_st' / st \\ st'') ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_If *)
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
+ (* E_IfTrue *)
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
+ (* E_IfFalse *)
rewrite -> pe_compare_update.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) apply pe_com_complete. apply H.
- (* <- *) apply pe_com_sound. apply H.
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be, for example,
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking whether [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '\\' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st \\ c1' / pe_st' / SKIP ->
c2 / pe_st' \\ c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 / c'' ->
c2 / pe_st \\ c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st \\ (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
\\ SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '\\' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Hint Constructors pe_com.
(* ================================================================= *)
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve_by_invert);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve_by_invert])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
\\ (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
\\ (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
\\ (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] \\ (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '\\' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st \\ st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st \\ (t_update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st \\ st' # n1 ->
c2 / st' \\ st'' # n2 ->
(c1 ;; c2) / st \\ st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st \\ st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st \\ st' # n1 ->
(WHILE b1 DO c1 END) / st' \\ st'' # n2 ->
(WHILE b1 DO c1 END) / st \\ st'' # S (n1 + n2)
where "c1 '/' st '\\' st' # n" := (ceval_count c1 st st' n).
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st \\ st' -> exists n, c / st \\ st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st \\ st' # n -> c / st \\ st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_update: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_update st pe_st1 = pe_update st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_update_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st \\ st' ->
c'' / pe_update st' pe_st' \\ st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n
where "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n' ->
c' / pe_st' / c'' / st \\ st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_update st pe_st \\ st'' # n) ->
(c' / pe_st' / c'' / st \\ st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve_by_invert);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. apply E'Skip. auto.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
apply E'Skip. auto.
- (* PE_Seq *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption. eassumption.
- (* PE_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_While *) inversion Heval; subst.
+ (* E_WhileEnd *) econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
+ (* E_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_update, <- assign_removes. eassumption.
omega.
- (* PE_WhileFixedLoop *) exfalso.
generalize dependent (S (n1 + n2)). intros n.
clear - H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct, H in H7. inversion H7.
+ (* E'WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
- (* PE_WhileFixed *) generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct in H8. eauto.
+ (* E'WhileLoop *) rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st \\ st'' # n) ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_If *) inversion Heval; subst; inversion H7; subst; clear H7.
+ (* E_IfTrue *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
+ (* E_IfFalse *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
- (* PE_WhileEnd *) apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
- (* PE_WhileLoop *) eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
- (* PE_While *) inversion Heval; subst.
+ (* E_IfTrue *)
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
+ (* E_IfFalse *) apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
* (* c2'' = SKIP *) inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
* (* c2'' = WHILE b1 DO c1 END *) assumption.
- (* PE_WhileFixedEnd *) eapply ceval_count_sound. apply Heval'.
- (* PE_WhileFixedLoop *)
apply loop_never_stops in Heval. inversion Heval.
- (* PE_WhileFixed *)
clear - H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
induction Heval;
inversion Heqc'; subst; clear Heqc'.
+ (* E_WhileEnd *) apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
+ (* E_WhileLoop *)
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' / SKIP ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(exists st', c' / st \\ st' /\ pe_update st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
- (* <- *) intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ################################################################# *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(* ================================================================= *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (t_update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (t_update (t_update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite t_update_same; auto.
Qed.
(* ================================================================= *)
(** ** Partial Evaluation of Basic Blocks and Flowchart Programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_update st pe_st) k = (pe_update st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
induction k as [l | b l1 l2 | i a k];
intros st pe_st H.
- (* Goto *) inversion H; reflexivity.
- (* If *)
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
- (* Assign *)
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_update_update_add; apply IHk; apply H];
solve [rewrite pe_update_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with | (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_update st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_update st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split.
- (* -> *) intros Heval.
remember (pe_update st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ];
intros st pe_st Heqsto; subst sto.
+ (* E_None *) eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
+ (* E_Some *)
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
- (* <- *) intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ];
intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
+ (* E_None *) apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
+ (* E_Some *)
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2017-01-30 19:42:52 -0500 (Mon, 30 Jan 2017) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_1_V
`define SKY130_FD_SC_MS__O311A_1_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_1_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Priority encoder module
*/
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
// power-of-two width
parameter W1 = 2**$clog2(WIDTH);
parameter W2 = W1/2;
generate
if (WIDTH == 1) begin
// one input
assign output_valid = input_unencoded;
assign output_encoded = 0;
end else if (WIDTH == 2) begin
// two inputs - just an OR gate
assign output_valid = |input_unencoded;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = input_unencoded[1];
end else begin
assign output_encoded = ~input_unencoded[0];
end
end else begin
// more than two inputs - split into two parts and recurse
// also pad input to correct power-of-two width
wire [$clog2(W2)-1:0] out1, out2;
wire valid1, valid2;
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst1 (
.input_unencoded(input_unencoded[W2-1:0]),
.output_valid(valid1),
.output_encoded(out1)
);
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst2 (
.input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
.output_valid(valid2),
.output_encoded(out2)
);
// multiplexer to select part
assign output_valid = valid1 | valid2;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
end else begin
assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
end
end
endgenerate
// unencoded output
assign output_unencoded = 1 << output_encoded;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A211OI_BEHAVIORAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_BEHAVIORAL_V |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500009189 : 255;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pci_exp_expect_tasks.v
// Version : 2.4
//--------------------------------------------------------------------------------
`define EXPECT_CPLD_PAYLOAD board.RP.tx_usrapp.expect_cpld_payload
`define EXPECT_MEMWR_PAYLOAD board.RP.tx_usrapp.expect_memwr_payload
`define EXPECT_MEMWR64_PAYLOAD board.RP.tx_usrapp.expect_memwr64_payload
reg [31:0] error_file_ptr;
initial
begin
error_file_ptr = $fopen("error.dat");
if (!error_file_ptr) begin
$write("ERROR: Could not open error.dat.\n");
$finish;
end
end
/************************************************************
Task : TSK_EXPECT_CPLD
Inputs : traffic_class, td, ep, attr, length, payload
Outputs : status 0-Failed 1-Successful
Description : Expecting a TLP from Rx side with matching
traffic_class, td, ep, attr, length and payload
*************************************************************/
task TSK_EXPECT_CPLD;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input [15:0] completer_id;
input [2:0] completion_status;
input bcm;
input [11:0] byte_count;
input [15:0] requester_id;
input [7:0] tag;
input [6:0] address_low;
output expect_status;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] completer_id_;
reg [2:0] completion_status_;
reg bcm_;
reg [11:0] byte_count_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [6:0] address_low_;
integer payload_len;
integer i_;
reg wait_for_next;
begin
wait_for_next = 1'b1; //haven't found any matching tag yet
while(wait_for_next)
begin
@ rcvd_cpld; //wait for a rcvd_cpld event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
bcm_ = frame_store_rx[6] >> 4;
completion_status_= frame_store_rx[6] >> 5;
byte_count_ = (frame_store_rx[6]);
byte_count_ = (byte_count_ << 8) | frame_store_rx[7];
completer_id_ = {frame_store_rx[4], frame_store_rx[5]};
requester_id_= {frame_store_rx[8], frame_store_rx[9]};
tag_= frame_store_rx[10];
address_low_ = frame_store_rx[11];
payload_len = (bcm_) ? byte_count_ : (length << 2);
if (payload_len==0) payload_len = 4096;
$display("[%t] : Received CPLD --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) && (bcm == bcm_) &&
(completion_status == completion_status_) &&
(byte_count == byte_count_) &&
(completer_id == completer_id_) &&
(requester_id == requester_id_) &&
(address_low == address_low_))
begin
// find matching header then compare payload
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
if(`EXPECT_CPLD_PAYLOAD[i_] != frame_store_rx[12 + i_]) //find mismatch
begin
$fdisplay(error_file_ptr, "[%t] : Found payload mismatch in received CPLD - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", `EXPECT_CPLD_PAYLOAD[i_]);
$fdisplay(error_file_ptr, "Received:");
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", frame_store_rx[12+i_]);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
i_ = 5000;
end
//find matching frame
if(i_ == payload_len)
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received CPLD - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t BCM: 0x%h", bcm);
$fdisplay(error_file_ptr, "\t Completion Status: 0x%h", completion_status);
$fdisplay(error_file_ptr, "\t Byte Count: 0x%h", byte_count);
$fdisplay(error_file_ptr, "\t Completer ID: 0x%h", completer_id);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Lower Address: 0x%h", address_low);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t BCM: 0x%h", bcm_);
$fdisplay(error_file_ptr, "\t Completion Status: 0x%h", completion_status_);
$fdisplay(error_file_ptr, "\t Byte Count: 0x%h", byte_count_);
$fdisplay(error_file_ptr, "\t Completer ID: 0x%h", completer_id_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Lower Address: 0x%h", address_low_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end
end
endtask
/************************************************************
Task : TSK_EXPECT_CPL
Inputs : traffic_class, td, ep, attr, length, payload
Outputs : status 0-Failed 1-Successful
Description : Expecting a TLP from Rx side with matching
traffic_class, td, ep, attr and length
*************************************************************/
task TSK_EXPECT_CPL;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [15:0] completer_id;
input [2:0] completion_status;
input bcm;
input [11:0] byte_count;
input [15:0] requester_id;
input [7:0] tag;
input [6:0] address_low;
output expect_status;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [15:0] completer_id_;
reg [2:0] completion_status_;
reg bcm_;
reg [11:0] byte_count_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [6:0] address_low_;
integer i_;
reg wait_for_next;
begin
wait_for_next = 1'b1; //haven't found any matching tag yet
while(wait_for_next)
begin
@ rcvd_cpl; //wait for a rcvd_cpl event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
bcm_ = frame_store_rx[6] >> 4;
completion_status_= frame_store_rx[6] >> 5;
byte_count_ = (frame_store_rx[6]);
byte_count_ = (byte_count_ << 8) | frame_store_rx[7];
completer_id_ = {frame_store_rx[4], frame_store_rx[5]};
requester_id_= {frame_store_rx[8], frame_store_rx[9]};
tag_= frame_store_rx[10];
address_low_ = frame_store_rx[11];
$display("[%t] : Received CPL --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(bcm == bcm_) && (completion_status == completion_status_) &&
(byte_count == byte_count_) &&
(completer_id == completer_id_) &&
(requester_id == requester_id_) &&
(address_low == address_low_))
begin
// header matches
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received CPL - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t BCM: 0x%h", bcm);
$fdisplay(error_file_ptr, "\t Completion Status: 0x%h", completion_status);
$fdisplay(error_file_ptr, "\t Byte Count: 0x%h", byte_count);
$fdisplay(error_file_ptr, "\t Completer ID: 0x%h", completer_id);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Lower Address: 0x%h", address_low);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t BCM: 0x%h", bcm_);
$fdisplay(error_file_ptr, "\t Completion Status: 0x%h", completion_status_);
$fdisplay(error_file_ptr, "\t Byte Count: 0x%h", byte_count_);
$fdisplay(error_file_ptr, "\t Completer ID: 0x%h", completer_id_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Lower Address: 0x%h", address_low_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end
end
endtask
/************************************************************
Task : TSK_EXPECT_MEMRD
Inputs : traffic_class, td, ep, attr, length, last_dw_be,
first_dw_be, address
Outputs : status 0-Failed 1-Successful
Description : Expecting a memory read (32-bit address) TLP
from Rx side with matching header fields
*************************************************************/
task TSK_EXPECT_MEMRD;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input [15:0] requester_id;
input [7:0] tag;
input [3:0] last_dw_be;
input [3:0] first_dw_be;
input [29:0] address;
output expect_status;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [3:0] last_dw_be_;
reg [3:0] first_dw_be_;
reg [29:0] address_;
integer i_;
reg wait_for_next;
begin
wait_for_next = 1'b1; //haven't found any matching tag yet
while(wait_for_next)
begin
@ rcvd_memrd; //wait for a rcvd_memrd event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
last_dw_be_= frame_store_rx[7] >> 4;
first_dw_be_= frame_store_rx[7];
address_[29:6] = {frame_store_rx[8], frame_store_rx[9], frame_store_rx[10]};
address_[5:0] = frame_store_rx[11] >> 2;
$display("[%t] : Received MEMRD --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) && (requester_id == requester_id_) &&
(last_dw_be == last_dw_be_) && (first_dw_be == first_dw_be_) &&
(address == address_))
begin
// header matches
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received MEMRD - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be_);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be_);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end
end
endtask
/************************************************************
Task : TSK_EXPECT_MEMRD64
Inputs : traffic_class, td, ep, attr, length, last_dw_be,
first_dw_be, address
Outputs : status 0-Failed 1-Successful
Description : Expecting a memory read (64-bit address) TLP
from Rx side with matching header fields
*************************************************************/
task TSK_EXPECT_MEMRD64;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input [15:0] requester_id;
input [7:0] tag;
input [3:0] last_dw_be;
input [3:0] first_dw_be;
input [61:0] address;
output expect_status;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [3:0] last_dw_be_;
reg [3:0] first_dw_be_;
reg [61:0] address_;
integer i_;
reg wait_for_next;
begin
wait_for_next = 1'b1; //haven't found any matching tag yet
while(wait_for_next)
begin
@ rcvd_memrd64; //wait for a rcvd_memrd64 event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
last_dw_be_= frame_store_rx[7] >> 4;
first_dw_be_= frame_store_rx[7];
address_[61:6] = {frame_store_rx[8], frame_store_rx[9],
frame_store_rx[10], frame_store_rx[11],
frame_store_rx[12], frame_store_rx[13],
frame_store_rx[14]};
address_[5:0] = frame_store_rx[15] >> 2;
$display("[%t] : Received MEMRD64 --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) && (requester_id == requester_id_) &&
(last_dw_be == last_dw_be_) && (first_dw_be == first_dw_be_) &&
(address == address_))
begin
// header matches
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received MEMRD64 - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be_);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be_);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end
end
endtask
/************************************************************
Task : TSK_EXPECT_MEMWR
Inputs : traffic_class, td, ep, attr, length, last_dw_be,
first_dw_be, address
Outputs : status 0-Failed 1-Successful
Description : Expecting a memory write (32-bit address) TLP
from Rx side with matching header fields and
payload
*************************************************************/
task TSK_EXPECT_MEMWR;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input [15:0] requester_id;
input [7:0] tag;
input [3:0] last_dw_be;
input [3:0] first_dw_be;
input [29:0] address;
output expect_status;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [3:0] last_dw_be_;
reg [3:0] first_dw_be_;
reg [29:0] address_;
integer payload_len;
integer i_;
reg wait_for_next;
reg check_byte;
begin
wait_for_next = 1'b1; //haven't found any matching tag yet
while(wait_for_next)
begin
@ rcvd_memwr; //wait for a rcvd_memwr event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
last_dw_be_= frame_store_rx[7] >> 4;
first_dw_be_= frame_store_rx[7];
address_[29:6] = {frame_store_rx[8], frame_store_rx[9], frame_store_rx[10]};
address_[5:0] = frame_store_rx[11] >> 2;
payload_len = (length << 2);
if (payload_len==0) payload_len = 4096;
$display("[%t] : Received MEMWR --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) && (requester_id == requester_id_) &&
(last_dw_be == last_dw_be_) && (first_dw_be == first_dw_be_) &&
(address == address_))
begin
// find matching header then compare payload
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
begin
check_byte = 1;
if (i_ < 4) // apply first_dw_be
begin
if (first_dw_be[i_])
check_byte = 1;
else
check_byte = 0;
end else if (i_ > (payload_len - 5)) // apply last_dw_be
begin
if (last_dw_be[4 - (payload_len - i_)])
check_byte = 1;
else
check_byte = 0;
end
if(check_byte && `EXPECT_MEMWR_PAYLOAD[i_] != frame_store_rx[12 + i_]) //find mismatch
begin
$fdisplay(error_file_ptr, "[%t] : Found payload mismatch in received MEMWR - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", `EXPECT_MEMWR_PAYLOAD[i_]);
$fdisplay(error_file_ptr, "Received:");
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", frame_store_rx[12+i_]);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
i_ = 5000;
end
end
//find matching frame
if(i_ == payload_len)
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received MEMWR - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be_);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be_);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end
end
endtask
/************************************************************
Task : TSK_EXPECT_MEMWR64
Inputs : traffic_class, td, ep, attr, length, last_dw_be,
first_dw_be, address
Outputs : status 0-Failed 1-Successful
Description : Expecting a memory write (64-bit address) TLP
from Rx side with matching header fields and
payload
*************************************************************/
task TSK_EXPECT_MEMWR64;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input [15:0] requester_id;
input [7:0] tag;
input [3:0] last_dw_be;
input [3:0] first_dw_be;
input [61:0] address;
output expect_status;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [3:0] last_dw_be_;
reg [3:0] first_dw_be_;
reg [61:0] address_;
integer payload_len;
integer i_;
reg wait_for_next;
reg check_byte;
begin
wait_for_next = 1'b1; //haven't found any matching tag yet
while(wait_for_next)
begin
@ rcvd_memwr64; //wait for a rcvd_memwr64 event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
last_dw_be_= frame_store_rx[7] >> 4;
first_dw_be_= frame_store_rx[7];
address_[61:6] = {frame_store_rx[8], frame_store_rx[9],
frame_store_rx[10], frame_store_rx[11],
frame_store_rx[12], frame_store_rx[13],
frame_store_rx[14]};
address_[5:0] = frame_store_rx[15] >> 2;
payload_len = (length << 2);
if (payload_len==0) payload_len = 4096;
$display("[%t] : Received MEMWR64 --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) && (requester_id == requester_id_) &&
(last_dw_be == last_dw_be_) && (first_dw_be == first_dw_be_) &&
(address == address_))
begin
// find matching header then compare payload
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
begin
check_byte = 1;
if (i_ < 4) // apply first_dw_be
begin
if (first_dw_be[i_])
check_byte = 1;
else
check_byte = 0;
end else if (i_ > (payload_len - 5)) // apply last_dw_be
begin
if (last_dw_be[4 - (payload_len - i_)])
check_byte = 1;
else
check_byte = 0;
end
if(check_byte && `EXPECT_MEMWR64_PAYLOAD[i_] != frame_store_rx[16 + i_]) //find mismatch
begin
$fdisplay(error_file_ptr, "[%t] : Found payload mismatch in received MEMWR64 - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", `EXPECT_MEMWR64_PAYLOAD[i_]);
$fdisplay(error_file_ptr, "Received:");
for (i_ = 0; i_ < payload_len; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", frame_store_rx[16+i_]);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
i_ = 5000;
end
end
//find matching frame
if(i_ == payload_len)
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received MEMWR64 - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Last DW byte-enable: 0x%h", last_dw_be_);
$fdisplay(error_file_ptr, "\t First DW byte-enable: 0x%h", first_dw_be_);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end
end
endtask
// Please note that the following io tasks can be only used if the customer has a mechanism for allowing
// the customer design to generate io write or io read tlps received by the dsport rx port.
/************************************************************
Task : TSK_EXPECT_IOWRITE
Inputs : td, ep, requested_id, tag, firstDwBe, address, data
Outputs : status 0-Failed 1-Successful
Description : Expecting a TLP from Rx side with matching
td, ep, requested_id, tag, firstDwBe, address, and 32 bit data
*************************************************************/
task TSK_EXPECT_IOWRITE;
input td;
input ep;
input [15:0] requester_id;
input [7:0] tag;
input [3:0] firstDwBe;
input [31:0] address; // note that low bits [1:0] are not used
input [31:0] data;
output expect_status;
reg [2:0] traffic_class;
reg [1:0] attr;
reg [9:0] length;
reg [3:0] lastDwBe;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [3:0] lastDwBe_;
reg [3:0] firstDwBe_;
reg [31:0] address_; // note that the bottom two bits are not used in comparison
reg [7:0] write_payload[0:3];
reg [3:0] byte_enabled;
integer i_;
reg wait_for_next;
integer j_;
begin
// following assignments are required for io header
traffic_class = 3'b000;
attr = 2'b00;
length = 10'b00_0000_0001;
lastDwBe = 4'b0000;
write_payload[0] = data[31:24];
write_payload[1] = data[23:16];
write_payload[2] = data[15:8];
write_payload[3] = data[7:0];
j_ = 1000;
wait_for_next = 1'b1; //haven't found any matching tag yet
fork
while(wait_for_next)
begin
@ rcvd_iowr; //wait for a rcvd_iowr event
byte_enabled = 4'h0;
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
lastDwBe_ = frame_store_rx[7] >>4;
firstDwBe_ = frame_store_rx[7];
address_ = (frame_store_rx[8]);
address_ = (address_ << 8) | frame_store_rx[9];
address_ = (address_ << 8) | frame_store_rx[10];
address_ = (address_ << 8) | frame_store_rx[11];
$display("[%t] : Received IO WRITE TLP --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) &&
(requester_id == requester_id_) &&
(lastDwBe == lastDwBe_) &&
(firstDwBe == firstDwBe_) &&
(address[31:2] == address_[31:2]))
begin
// find matching header then compare payload
expect_status = 1'b1; //assume that we will succeed
byte_enabled = firstDwBe;
for (i_ = 0; i_ < 4; i_ = i_ + 1)
begin
if (byte_enabled[3] && expect_status)
if (write_payload[i_] != frame_store_rx[12 + i_]) //find mismatch
begin
$fdisplay(error_file_ptr, "[%t] : Found payload mismatch in IO WRITE DATA - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
for (i_ = 0; i_ < 4; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", write_payload[i_]);
$fdisplay(error_file_ptr, "Received:");
for (i_ = 0; i_ < 4; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", frame_store_rx[12+i_]);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
byte_enabled = byte_enabled << 1;
end
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received CPLD - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Last DW Byte Enable: 0x%h", lastDwBe);
$fdisplay(error_file_ptr, "\t 1st DW Byte Enable: 0x%h", firstDwBe);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Last DW Byte Enable: 0x%h", lastDwBe_);
$fdisplay(error_file_ptr, "\t 1st DW Byte Enable: 0x%h", firstDwBe_);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end // while
begin
// time out task function and return 0 if tlp never received and/or tag never matches
while (j_ && wait_for_next)
begin
`TX_TASKS.TSK_TX_CLK_EAT(1);
j_ = j_ - 1;
end
if (wait_for_next)
begin
$display("Failure: TSK_EXPECT_IOWRITE timeout. IO WRITE TLP never received or tag mismatch");
$finish;
end
end
join
end // 1st
endtask
/************************************************************
Task : TSK_EXPECT_IOREAD
Inputs : td, ep, requested_id, tag, firstDwBe, address
Outputs : status 0-Failed 1-Successful
Description : Expecting a TLP from Rx side with matching
td, ep, requested_id, tag, firstDwBe, and address
*************************************************************/
task TSK_EXPECT_IOREAD;
input td;
input ep;
input [15:0] requester_id;
input [7:0] tag;
input [3:0] firstDwBe;
input [31:0] address; // note that low bits [1:0] are not used
output expect_status;
reg [2:0] traffic_class;
reg [1:0] attr;
reg [9:0] length;
reg [3:0] lastDwBe;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [3:0] lastDwBe_;
reg [3:0] firstDwBe_;
reg [31:0] address_; // note that the bottom two bits are not used in comparison
integer i_;
reg wait_for_next;
integer j_;
begin
// following assignments are required for io header
traffic_class = 3'b000;
attr = 2'b00;
length = 10'b00_0000_0001;
lastDwBe = 4'b0000;
j_ = 1000;
wait_for_next = 1'b1; //haven't found any matching tag yet
fork
while(wait_for_next)
begin
@ rcvd_iord; //wait for a rcvd_iord event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
lastDwBe_ = frame_store_rx[7] >>4;
firstDwBe_ = frame_store_rx[7];
address_ = (frame_store_rx[8]);
address_ = (address_ << 8) | frame_store_rx[9];
address_ = (address_ << 8) | frame_store_rx[10];
address_ = (address_ << 8) | frame_store_rx[11];
$display("[%t] : Received IO READ TLP --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) &&
(requester_id == requester_id_) &&
(lastDwBe == lastDwBe_) &&
(firstDwBe == firstDwBe_) &&
(address[31:2] == address_[31:2]))
begin
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received CPLD - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Last DW Byte Enable: 0x%h", lastDwBe);
$fdisplay(error_file_ptr, "\t 1st DW Byte Enable: 0x%h", firstDwBe);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Last DW Byte Enable: 0x%h", lastDwBe_);
$fdisplay(error_file_ptr, "\t 1st DW Byte Enable: 0x%h", firstDwBe_);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end // while
begin
// time out task function and return 0 if tlp never received and/or tag never matches
while (j_ && wait_for_next)
begin
`TX_TASKS.TSK_TX_CLK_EAT(1);
j_ = j_ - 1;
end
if (wait_for_next)
begin
$display("Failure: TSK_EXPECT_IOREAD timeout. IO READ TLP never received or tag mismatch");
$finish;
end
end
join
end //1st
endtask
// Please note that the following task, TSK_EXPECT_TYPE0_CONFIGURATION_WRITE, should not be exported
// to the customer because all the current express cores currently consume all Type 0 configuration
// accesses. This means that this task will always time out since a type 0 config tlp will never
// be received at the rx trn interface. This function is being included for completeness and in case
// a future release of an express core passes type 0 configuration writes through the express core
// and on to the customer rx application.
// Also note that this function has not been tested completely due to the restrictions indicated above.
/************************************************************
Task : TSK_EXPECT_TYPE0_CONFIGURATION_WRITE
Inputs : td, ep, requested_id, tag, firstDwBe, , data
Outputs : status 0-Failed 1-Successful
Description : Expecting a TLP from Rx side with matching
td, ep, requested_id, tag, firstDwBe, , and 32 bit data
*************************************************************/
task TSK_EXPECT_TYPE0_CONFIGURATION_WRITE;
input td;
input ep;
input [15:0] requester_id;
input [7:0] tag;
input [3:0] firstDwBe;
input [7:0] busNumber;
input [4:0] deviceNumber;
input [2:0] functionNumber;
input [3:0] extRegNumber;
input [5:0] registerNumber;
input [31:0] data;
output expect_status;
reg [2:0] traffic_class;
reg [1:0] attr;
reg [9:0] length;
reg [3:0] lastDwBe;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [3:0] lastDwBe_;
reg [3:0] firstDwBe_;
reg [7:0] busNumber_;
reg [4:0] deviceNumber_;
reg [2:0] functionNumber_;
reg [3:0] extRegNumber_;
reg [5:0] registerNumber_;
reg [7:0] write_payload[0:3];
reg [3:0] byte_enabled;
integer i_;
reg wait_for_next;
integer j_;
begin
// following assignments are required for io header
traffic_class = 3'b000;
attr = 2'b00;
length = 10'b00_0000_0001;
lastDwBe = 4'b0000;
write_payload[0] = data[31:24];
write_payload[1] = data[23:16];
write_payload[2] = data[15:8];
write_payload[3] = data[7:0];
j_ = 1000;
wait_for_next = 1'b1; //haven't found any matching tag yet
fork
while(wait_for_next)
begin
@ rcvd_cfgwr0; //wait for a rcvd_cfgwr0 event *** currently this event will never occur
byte_enabled = 4'h0;
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
lastDwBe_ = frame_store_rx[7] >>4;
firstDwBe_ = frame_store_rx[7];
busNumber_ = frame_store_rx[8];
deviceNumber_ = frame_store_rx[9] >> 3;
functionNumber_ = frame_store_rx[9];
extRegNumber_ = frame_store_rx[10];
registerNumber_ = frame_store_rx[11] >> 2;
$display("[%t] : Received TYPE 0 CFG WRITE TLP --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) &&
(requester_id == requester_id_) &&
(lastDwBe == lastDwBe_) &&
(firstDwBe == firstDwBe_) &&
(busNumber == busNumber_) &&
(deviceNumber == deviceNumber_) &&
(functionNumber == functionNumber_) &&
(extRegNumber == extRegNumber_) &&
(registerNumber == registerNumber_))
begin
// find matching header then compare payload
expect_status = 1'b1; //assume that we will succeed
byte_enabled = firstDwBe;
for (i_ = 0; i_ < 4; i_ = i_ + 1)
begin
if (byte_enabled[3] && expect_status)
if (write_payload[i_] != frame_store_rx[12 + i_]) //find mismatch
begin
$fdisplay(error_file_ptr, "[%t] : Found payload mismatch in TYPE 0 WRITE DATA - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
for (i_ = 0; i_ < 4; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", write_payload[i_]);
$fdisplay(error_file_ptr, "Received:");
for (i_ = 0; i_ < 4; i_ = i_ + 1)
$fdisplay(error_file_ptr,"\t %0x", frame_store_rx[12+i_]);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
byte_enabled = byte_enabled << 1;
end
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received CPLD - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Last DW Byte Enable: 0x%h", lastDwBe);
$fdisplay(error_file_ptr, "\t 1st DW Byte Enable: 0x%h", firstDwBe);
$fdisplay(error_file_ptr, "\t Bus Number: 0x%h", busNumber);
$fdisplay(error_file_ptr, "\t Device Number: 0x%h", deviceNumber);
$fdisplay(error_file_ptr, "\t Function Number: 0x%h", functionNumber);
$fdisplay(error_file_ptr, "\t Ext Reg Number: 0x%h", extRegNumber);
$fdisplay(error_file_ptr, "\t Register Number: 0x%h", registerNumber);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Last DW Byte Enable: 0x%h", lastDwBe_);
$fdisplay(error_file_ptr, "\t 1st DW Byte Enable: 0x%h", firstDwBe_);
$fdisplay(error_file_ptr, "\t Bus Number: 0x%h", busNumber_);
$fdisplay(error_file_ptr, "\t Device Number: 0x%h", deviceNumber_);
$fdisplay(error_file_ptr, "\t Function Number: 0x%h", functionNumber_);
$fdisplay(error_file_ptr, "\t Ext Reg Number: 0x%h", extRegNumber_);
$fdisplay(error_file_ptr, "\t Register Number: 0x%h", registerNumber_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end // while
begin
// time out task function and return 0 if tlp never received and/or tag never matches
while (j_ && wait_for_next)
begin
`TX_TASKS.TSK_TX_CLK_EAT(1);
j_ = j_ - 1;
end
if (wait_for_next)
begin
$display("Failure: TSK_EXPECT_TYPE0_CONFIGURATION_WRITE timeout. CFG TYPE 0 WRITE TLP never received");
$finish;
end
end
join
end // 1st
endtask
/************************************************************
Task : TSK_EXPECT_MSG
Inputs : traffic_class, td, ep, attr, length, msg type, msg code
address
Outputs : status 0-Failed 1-Successful
Description : Expecting a message no data TLP
from Rx side with matching header fields
*************************************************************/
task TSK_EXPECT_MSG;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input [15:0] requester_id;
input [7:0] tag;
input [7:0] msg_code;
input [29:0] address;
output expect_status;
reg [2:0] traffic_class_;
reg td_;
reg ep_;
reg [1:0] attr_;
reg [9:0] length_;
reg [15:0] requester_id_;
reg [7:0] tag_;
reg [7:0] msg_code_;
reg [29:0] address_;
integer i_;
reg wait_for_next;
begin
wait_for_next = 1'b1; //haven't found any matching tag yet
while(wait_for_next)
begin
@ rcvd_msg; //wait for a rcvd_memrd event
traffic_class_ = frame_store_rx[1] >> 4;
td_ = frame_store_rx[2] >> 7;
ep_ = frame_store_rx[2] >> 6;
attr_ = frame_store_rx[2] >> 4;
length_ = frame_store_rx[2];
length_ = (length_ << 8) | (frame_store_rx[3]);
requester_id_= {frame_store_rx[4], frame_store_rx[5]};
tag_= frame_store_rx[6];
msg_code_ = frame_store_rx[7];
address_[29:6] = {frame_store_rx[8], frame_store_rx[9], frame_store_rx[10]};
address_[5:0] = frame_store_rx[11] >> 2;
$display("[%t] : Received MSG w/o Data --- Tag 0x%h", $realtime, tag_);
if(tag == tag_) //find matching tag
begin
wait_for_next = 1'b0;
if((traffic_class == traffic_class_) &&
(td === td_) && (ep == ep_) && (attr == attr_) &&
(length == length_) && (requester_id == requester_id_) &&
(msg_code == msg_code_) && (address == address_))
begin
// header matches
expect_status = 1'b1;
end
else // header mismatches, error out
begin
$fdisplay(error_file_ptr, "[%t] : Found header mismatch in received MSG w/o Data - Tag 0x%h: \n", $time, tag_);
$fdisplay(error_file_ptr, "Expected:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(error_file_ptr, "\t TD: %h", td);
$fdisplay(error_file_ptr, "\t EP: %h", ep);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(error_file_ptr, "\t Msg Code: 0x%h", msg_code);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address);
$fdisplay(error_file_ptr, "Received:");
$fdisplay(error_file_ptr, "\t Traffic Class: 0x%h", traffic_class_);
$fdisplay(error_file_ptr, "\t TD: %h", td_);
$fdisplay(error_file_ptr, "\t EP: %h", ep_);
$fdisplay(error_file_ptr, "\t Attributes: 0x%h", attr_);
$fdisplay(error_file_ptr, "\t Length: 0x%h", length_);
$fdisplay(error_file_ptr, "\t Requester ID: 0x%h", requester_id_);
$fdisplay(error_file_ptr, "\t Tag: 0x%h", tag_);
$fdisplay(error_file_ptr, "\t Msg Code: 0x%h", msg_code_);
$fdisplay(error_file_ptr, "\t Address: 0x%h", address_);
$fdisplay(error_file_ptr, "");
expect_status = 1'b0;
end
end
end
end
endtask
|
module TX_control
#( parameter INTER_BYTE_DELAY = 1000000, // ciclos de reloj de espera entre el envio de 2 bytes consecutivos
parameter WAIT_FOR_REGISTER_DELAY = 100 // tiempo de espera para iniciar la transmision luego de registrar el dato a enviar
)(
input clock,
input reset,
input PB, // Push Button
input send16, // Indica si se deben enviar 8 o 16 bits
input [15:0] dataIn16, // Dato que se desea transmitir de 16 bits
output reg [7:0] tx_data, // Datos entregados al driver UART para transmision
output reg tx_start, // Pulso para iniciar transmision por la UART
output reg busy // Indica si hay una transmision en proceso
);
reg [2:0] next_state, state;
reg [15:0] tx_data16;
reg [31:0] hold_state_timer;
//state encoding
localparam IDLE = 3'd0; // Modo espera
localparam REGISTER_DATAIN16 = 3'd1; // Cuando se presiona boton, registrar 16 bits a enviar
localparam SEND_BYTE_0 = 3'd2; // Enviar el primer byte
localparam DELAY_BYTE_0 = 3'd3; // Esperar un tiempo suficiente para que la transmision anterior termine
localparam SEND_BYTE_1 = 3'd4; // Si es necesario, enviar el segundo byte
localparam DELAY_BYTE_1 = 3'd5; // Esperar a que la transmision anterior termine
// combo logic of FSM
always@(*) begin
//default assignments
next_state = state;
busy = 1'b1;
tx_start = 1'b0;
tx_data = tx_data16[7:0];
case (state)
IDLE: begin
busy = 1'b0;
if(PB) begin
next_state=REGISTER_DATAIN16;
end
end
REGISTER_DATAIN16: begin
if(hold_state_timer >= WAIT_FOR_REGISTER_DELAY)
next_state=SEND_BYTE_0;
end
SEND_BYTE_0: begin
next_state = DELAY_BYTE_0;
tx_start = 1'b1;
end
DELAY_BYTE_0: begin
//tx_data = tx_data16[15:8];
if(hold_state_timer >= INTER_BYTE_DELAY) begin
if (send16)
next_state = SEND_BYTE_1;
else
next_state = IDLE;
end
end
SEND_BYTE_1: begin
tx_data = tx_data16[15:8];
next_state = DELAY_BYTE_1;
tx_start = 1'b1;
end
DELAY_BYTE_1: begin
if(hold_state_timer >= INTER_BYTE_DELAY)
next_state = IDLE;
end
endcase
end
//when clock ticks, update the state
always@(posedge clock) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
// registra los datos a enviar
always@ (posedge clock) begin
if(state == REGISTER_DATAIN16)
tx_data16 <= dataIn16;
end
//activa timer para retener un estado por cierto numero de ciclos de reloj
always@(posedge clock) begin
if(state == DELAY_BYTE_0 || state == DELAY_BYTE_1 || state == REGISTER_DATAIN16) begin
hold_state_timer <= hold_state_timer + 1;
end else begin
hold_state_timer <= 0;
end
end
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Parametrizable combinatorial parallel LFSR/CRC
*/
module lfsr #
(
// width of LFSR
parameter LFSR_WIDTH = 31,
// LFSR polynomial
parameter LFSR_POLY = 31'h10000001,
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// LFSR feed forward enable
parameter LFSR_FEED_FORWARD = 0,
// bit-reverse input and output
parameter REVERSE = 0,
// width of data input
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire [DATA_WIDTH-1:0] data_in,
input wire [LFSR_WIDTH-1:0] state_in,
output wire [DATA_WIDTH-1:0] data_out,
output wire [LFSR_WIDTH-1:0] state_out
);
/*
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR
next state computation, shifting DATA_WIDTH bits per pass through the module. Input data
is XORed with LFSR feedback path, tie data_in to zero if this is not required.
Works in two parts: statically computes a set of bit masks, then uses these bit masks to
select bits for XORing to compute the next state.
Ports:
data_in
Data bits to be shifted through the LFSR (DATA_WIDTH bits)
state_in
LFSR/CRC current state input (LFSR_WIDTH bits)
data_out
Data bits shifted out of LFSR (DATA_WIDTH bits)
state_out
LFSR/CRC next state output (LFSR_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
LFSR_FEED_FORWARD
Generate feed forward instead of feed back LFSR. Enable this for PRBS checking and self-
synchronous descrambling.
Fibonacci feed-forward style (example for 64b66b descrambler, 0x8000000001)
DIN (LSB first)
|
| .----. .----. .----. .----. .----. .----.
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--.
| '----' '----' '----' | '----' '----' '----' |
| V |
(+)<---------------------------(+)------------------------------'
|
V
DOUT
Galois feed-forward style
,-------------------+-------------------------+------------+--- DIN (MSB first)
| | | |
| .----. .----. V .----. .----. V .----. V
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |->(+)-> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
DATA_WIDTH
Specify width of input and output data bus. The module will perform one shift per input
data bit, so if the input data bus is not required tie data_in to zero and set DATA_WIDTH
to the required number of shifts per clock cycle.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
CRC16-CCITT Galois 16 16'h1021 16'h1d0f
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] state_val = 0;
reg [DATA_WIDTH-1:0] data_val = 0;
integer i, j, k;
initial begin
// init bit masks
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}};
lfsr_mask_state[i][i] = 1'b1;
lfsr_mask_data[i] = {DATA_WIDTH{1'b0}};
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
output_mask_state[i] = {LFSR_WIDTH{1'b0}};
if (i < LFSR_WIDTH) begin
output_mask_state[i][i] = 1'b1;
end
output_mask_data[i] = {DATA_WIDTH{1'b0}};
end
// simulate shift register
if (LFSR_CONFIG == "FIBONACCI") begin
// Fibonacci configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// add XOR inputs from correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
state_val = lfsr_mask_state[j-1] ^ state_val;
data_val = lfsr_mask_data[j-1] ^ data_val;
end
end
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
end
end else if (LFSR_CONFIG == "GALOIS") begin
// Galois configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
// add XOR inputs at correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
end
end
end
end else begin
$error("Error: unknown configuration setting!");
$finish;
end
// reverse bits if selected
if (REVERSE) begin
// reverse order
for (i = 0; i < LFSR_WIDTH/2; i = i + 1) begin
state_val = lfsr_mask_state[i];
data_val = lfsr_mask_data[i];
lfsr_mask_state[i] = lfsr_mask_state[LFSR_WIDTH-i-1];
lfsr_mask_data[i] = lfsr_mask_data[LFSR_WIDTH-i-1];
lfsr_mask_state[LFSR_WIDTH-i-1] = state_val;
lfsr_mask_data[LFSR_WIDTH-i-1] = data_val;
end
for (i = 0; i < DATA_WIDTH/2; i = i + 1) begin
state_val = output_mask_state[i];
data_val = output_mask_data[i];
output_mask_state[i] = output_mask_state[DATA_WIDTH-i-1];
output_mask_data[i] = output_mask_data[DATA_WIDTH-i-1];
output_mask_state[DATA_WIDTH-i-1] = state_val;
output_mask_data[DATA_WIDTH-i-1] = data_val;
end
// reverse bits
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = lfsr_mask_state[i][LFSR_WIDTH-j-1];
end
lfsr_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
end
lfsr_mask_data[i] = data_val;
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = output_mask_state[i][LFSR_WIDTH-j-1];
end
output_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = output_mask_data[i][DATA_WIDTH-j-1];
end
output_mask_data[i] = data_val;
end
end
// for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]);
// end
end
// synthesis translate_off
`define SIMULATION
// synthesis translate_on
`ifdef SIMULATION
// "AUTO" style is "REDUCTION" for faster simulation
parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else
// "AUTO" style is "LOOP" for better synthesis result
parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif
genvar n;
generate
if (STYLE_INT == "REDUCTION") begin
// use Verilog reduction operator
// fast in iverilog
// significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer)
// slightly smaller than generated code with Quartus
// --> better for simulation
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
end
end else if (STYLE_INT == "LOOP") begin
// use nested loops
// very slow in iverilog
// slightly smaller than generated code with ISE
// same size as generated code with Quartus
// --> better for synthesis
reg [LFSR_WIDTH-1:0] state_out_reg = 0;
reg [DATA_WIDTH-1:0] data_out_reg = 0;
assign state_out = state_out_reg;
assign data_out = data_out_reg;
always @* begin
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (lfsr_mask_state[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (lfsr_mask_data[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ data_in[j];
end
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (output_mask_state[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (output_mask_data[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ data_in[j];
end
end
end
end
end else begin
initial begin
$error("Error: unknown style setting!");
$finish;
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:56:25 03/27/2014
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module addsub(/*AUTOARG*/
// Outputs
data_c,overflow,
// Inputs
data_a, data_b, sign, addsub
);
// input clk;
input [31:0] data_a;
input [31:0] data_b;
//input [31:0] data_c;
input sign;
input addsub;
output overflow;
reg [32:0] temp;
output reg [31:0] data_c;
always @(/*AUTOSENSE*/addsub or data_a or data_b or sign) begin
case ({addsub, sign})
00:
temp <= {data_a[31], data_a} + {data_b[31], data_b};
01:
temp[31:0] <= data_a + data_b;
10:
temp <= {data_b[31], data_b} - {data_a[31], data_a};
11:
temp[31:0] <= data_b - data_a;
default:
data_c <= 32'h00000000;
endcase // case ({add_sub, sign})
data_c <= temp[31:0];
end
assign overflow = temp[32] != temp[31];
endmodule // addsub
|
/* Atari on an FPGA
Masters of Engineering Project
Cornell University, 2007
Daniel Beer
TIA.v
Redesign of the Atari TIA chip. Provides the Atari with video generation,
sound generation and I/O.
*/
`timescale 1ns / 1ps
`include "tia.vh"
module TIA(A, // Address bus input
Din, // Data bus input
Dout, // Data bus output
CS_n, // Active low chip select input
CS, // Chip select input
R_W_n, // Active low read/write input
RDY, // CPU ready output
MASTERCLK, // 3.58 Mhz pixel clock input
CLK2, // 1.19 Mhz bus clock input
idump_in, // Dumped I/O
Ilatch, // Latched I/O
HSYNC, // Video horizontal sync output
HBLANK, // Video horizontal blank output
VSYNC, // Video vertical sync output
VBLANK, // Video vertical sync output
COLOROUT, // Indexed color output
RES_n, // Active low reset input
AUD0, //audio pin 0
AUD1, //audio pin 1
audv0, //audio volume for use with external xformer module
audv1); //audio volume for use with external xformer module
input [5:0] A;
input [7:0] Din;
output [7:0] Dout;
input [2:0] CS_n;
input CS;
input R_W_n;
output RDY;
input MASTERCLK;
input CLK2;
input [1:0] Ilatch;
input [3:0] idump_in;
output HSYNC, HBLANK;
output VSYNC, VBLANK;
output [7:0] COLOROUT;
input RES_n;
output AUD0, AUD1;
output reg [3:0] audv0, audv1;
// Data output register
reg [7:0] Dout;
// Video control signal registers
wire HSYNC;
reg VSYNC, VBLANK;
// Horizontal pixel counter
reg [7:0] hCount;
reg [3:0] hCountReset;
reg clk_30;
reg [7:0] clk_30_count;
wire [3:0] Idump;
// Pixel counter update
always @(posedge MASTERCLK)
begin
// Reset operation
if (~RES_n) begin
hCount <= 8'd0;
hCountReset[3:1] <= 3'd0;
clk_30 <= 0;
clk_30_count <= 0;
latchedInputs <= 2'b11;
end
else begin
if (inputLatchReset)
latchedInputs <= 2'b11;
else
latchedInputs <= latchedInputs & Ilatch;
if (clk_30_count == 57) begin
clk_30 <= ~clk_30;
clk_30_count <= 0;
end else begin
clk_30_count <= clk_30_count + 1;
end
// Increment the count and reset if necessary
if ((hCountReset[3]) ||(hCount == 8'd227))
hCount <= 8'd0;
else
hCount <= hCount + 8'd1;
// Software resets are delayed by three cycles
hCountReset[3:1] <= hCountReset[2:0];
end
end
assign HSYNC = (hCount >= 8'd20) && (hCount < 8'd36);
assign HBLANK = (hCount < 8'd68);
// Screen object registers
// These registers are set by the software and used to generate pixels
reg [7:0] player0Pos, player1Pos, missile0Pos, missile1Pos, ballPos;
reg [4:0] player0Size, player1Size;
reg [7:0] player0Color, player1Color, ballColor, pfColor, bgColor;
reg [3:0] player0Motion, player1Motion, missile0Motion, missile1Motion,
ballMotion;
reg missile0Enable, missile1Enable, ballEnable, R_ballEnable;
reg [1:0] ballSize;
reg [19:0] pfGraphic;
reg [7:0] player0Graphic, player1Graphic;
reg [7:0] R_player0Graphic, R_player1Graphic;
reg pfReflect, player0Reflect, player1Reflect;
reg prioCtrl;
reg pfColorCtrl;
reg [14:0] collisionLatch;
reg missile0Lock, missile1Lock;
reg player0VertDelay, player1VertDelay, ballVertDelay;
reg [3:0] audc0, audc1;
reg [4:0] audf0, audf1;
// Pixel number calculation
wire [7:0] pixelNum;
//audio control
audio audio_ctrl(.AUDC0(audc0),
.AUDC1(audc1),
.AUDF0(audf0),
.AUDF1(audf1),
.CLK_30(clk_30), //30khz clock
.AUD0(AUD0),
.AUD1(AUD1));
assign pixelNum = (hCount >= 8'd68) ? (hCount - 8'd68) : 8'd227;
// Pixel tests. For each pixel and screen object, a test is done based on the
// screen objects register to determine if the screen object should show on that
// pixel. The results of all the tests are fed into logic to pick which displayed
// object has priority and color the pixel the color of that object.
// Playfield pixel test
wire [5:0] pfPixelNum;
wire pfPixelOn, pfLeftPixelVal, pfRightPixelVal;
assign pfPixelNum = pixelNum[7:2];
assign pfLeftPixelVal = pfGraphic[pfPixelNum];
assign pfRightPixelVal = (pfReflect == 1'b0)? pfGraphic[pfPixelNum - 6'd20]:
pfGraphic[6'd39 - pfPixelNum];
assign pfPixelOn = (pfPixelNum < 6'd20)? pfLeftPixelVal : pfRightPixelVal;
// Player 0 sprite pixel test
wire pl0PixelOn;
wire [7:0] pl0Mask, pl0MaskDel;
assign pl0MaskDel = (player0VertDelay)? R_player0Graphic : player0Graphic;
assign pl0Mask = (!player0Reflect)? pl0MaskDel : {pl0MaskDel[0], pl0MaskDel[1],
pl0MaskDel[2], pl0MaskDel[3],
pl0MaskDel[4], pl0MaskDel[5],
pl0MaskDel[6], pl0MaskDel[7]};
objPixelOn player0_test(pixelNum, player0Pos, player0Size[2:0], pl0Mask, pl0PixelOn);
// Player 1 sprite pixel test
wire pl1PixelOn;
wire [7:0] pl1Mask, pl1MaskDel;
assign pl1MaskDel = (player1VertDelay)? R_player1Graphic : player1Graphic;
assign pl1Mask = (!player1Reflect)? pl1MaskDel : {pl1MaskDel[0], pl1MaskDel[1],
pl1MaskDel[2], pl1MaskDel[3],
pl1MaskDel[4], pl1MaskDel[5],
pl1MaskDel[6], pl1MaskDel[7]};
objPixelOn player1_test(pixelNum, player1Pos, player1Size[2:0], pl1Mask, pl1PixelOn);
// Missile 0 pixel test
wire mis0PixelOn, mis0PixelOut;
wire [7:0] mis0ActualPos;
reg [7:0] mis0Mask;
always @(player0Size)
begin
case(player0Size[4:3])
2'd0: mis0Mask <= 8'h01;
2'd1: mis0Mask <= 8'h03;
2'd2: mis0Mask <= 8'h0F;
2'd3: mis0Mask <= 8'hFF;
endcase
end
assign mis0ActualPos = (missile0Lock)? player0Pos : missile0Pos;
objPixelOn missile0_test(pixelNum, mis0ActualPos, player0Size[2:0], mis0Mask, mis0PixelOut);
assign mis0PixelOn = mis0PixelOut && missile0Enable;
// Missile 1 pixel test
wire mis1PixelOn, mis1PixelOut;
wire [7:0] mis1ActualPos;
reg [7:0] mis1Mask;
always @(player1Size)
begin
case(player1Size[4:3])
2'd0: mis1Mask <= 8'h01;
2'd1: mis1Mask <= 8'h03;
2'd2: mis1Mask <= 8'h0F;
2'd3: mis1Mask <= 8'hFF;
endcase
end
assign mis1ActualPos = (missile1Lock)? player1Pos : missile1Pos;
objPixelOn missile1_test(pixelNum, mis1ActualPos, player1Size[2:0], mis1Mask, mis1PixelOut);
assign mis1PixelOn = mis1PixelOut && missile1Enable;
// Ball pixel test
wire ballPixelOut, ballPixelOn, ballEnableDel;
reg [7:0] ballMask;
always @(ballSize)
begin
case(ballSize)
2'd0: ballMask <= 8'h01;
2'd1: ballMask <= 8'h03;
2'd2: ballMask <= 8'h0F;
2'd3: ballMask <= 8'hFF;
endcase
end
objPixelOn ball_test(pixelNum, ballPos, 3'd0, ballMask, ballPixelOut);
assign ballEnableDel = ((ballVertDelay)? R_ballEnable : ballEnable);
assign ballPixelOn = ballPixelOut && ballEnableDel;
// Playfield color selection
// The programmer can select a unique color for the playfield or have it match
// the player's sprites colors
reg [7:0] pfActualColor;
always @(pfColorCtrl, pfColor, player0Color, player1Color, pfPixelNum)
begin
if (pfColorCtrl)
begin
if (pfPixelNum < 6'd20)
pfActualColor <= player0Color;
else
pfActualColor <= player1Color;
end
else
pfActualColor <= pfColor;
end
// Final pixel color selection
reg [7:0] pixelColor;
assign COLOROUT = (HBLANK)? 8'b0 : pixelColor;
// This combinational logic uses a priority encoder like structure to select
// the highest priority screen object and color the pixel.
always @(prioCtrl, pfPixelOn, pl0PixelOn, pl1PixelOn, mis0PixelOn, mis1PixelOn,
ballPixelOn, pfActualColor, player0Color, player1Color, bgColor)
begin
// Show the playfield behind the players
if (!prioCtrl)
begin
if (pl0PixelOn || mis0PixelOn)
pixelColor <= player0Color;
else if (pl1PixelOn || mis1PixelOn)
pixelColor <= player1Color;
else if (pfPixelOn)
pixelColor <= pfActualColor;
else
pixelColor <= bgColor;
end
// Otherwise, show the playfield in front of the players
else begin
if (pfPixelOn)
pixelColor <= pfActualColor;
else if (pl0PixelOn || mis0PixelOn)
pixelColor <= player0Color;
else if (pl1PixelOn || mis1PixelOn)
pixelColor <= player1Color;
else
pixelColor <= bgColor;
end
end
// Collision register and latching update
wire [14:0] collisions;
reg collisionLatchReset;
assign collisions = {pl0PixelOn && pl1PixelOn, mis0PixelOn && mis1PixelOn,
ballPixelOn && pfPixelOn,
mis1PixelOn && pfPixelOn, mis1PixelOn && ballPixelOn,
mis0PixelOn && pfPixelOn, mis0PixelOn && ballPixelOn,
pl1PixelOn && pfPixelOn, pl1PixelOn && ballPixelOn,
pl0PixelOn && pfPixelOn, pl0PixelOn && ballPixelOn,
mis1PixelOn && pl0PixelOn, mis1PixelOn && pl1PixelOn,
mis0PixelOn && pl1PixelOn, mis0PixelOn && pl0PixelOn};
always @(posedge MASTERCLK, posedge collisionLatchReset)
begin
if (collisionLatchReset)
collisionLatch <= 15'b000000000000000;
else
collisionLatch <= collisionLatch | collisions;
end
// WSYNC logic
// When a WSYNC is signalled by the programmer, the CPU ready line is lowered
// until the end of a scanline
reg wSync, wSyncReset;
always @(hCount, wSyncReset)
begin
if (hCount == 8'd0)
wSync <= 1'b0;
else if (wSyncReset && hCount > 8'd2)
wSync <= 1'b1;
end
assign RDY = ~wSync;
// Latched input registers and update
wire [1:0] latchedInputsValue;
reg inputLatchEnabled;
reg inputLatchReset;
reg [1:0] latchedInputs;
/*always_ff @(Ilatch, inputLatchReset)
begin
if (inputLatchReset)
latchedInputs <= 2'b11;
else
latchedInputs <= latchedInputs & Ilatch;
end*/
assign latchedInputsValue = (inputLatchEnabled)? latchedInputs : Ilatch;
// Dumped input registers update
reg inputDumpEnabled;
assign Idump = (inputDumpEnabled)? 4'b0000 : idump_in;
// Software operations
always @(posedge CLK2)
begin
// Reset operation
if (~RES_n) begin
inputLatchReset <= 1'b0;
collisionLatchReset <= 1'b0;
hCountReset[0] <= 1'b0;
wSyncReset <= 1'b0;
Dout <= 8'b00000000;
end
// If the chip is enabled, execute an operation
else if (CS) begin
// Software reset signals
inputLatchReset <= ({R_W_n, A[5:0]} == `VBLANK && Din[6] && !inputLatchEnabled);
collisionLatchReset <= ({R_W_n, A[5:0]} == `CXCLR);
hCountReset[0] <= ({R_W_n, A[5:0]} == `RSYNC);
wSyncReset <= ({R_W_n, A[5:0]} == `WSYNC) && !wSync;
case({R_W_n, A[5:0]})
// Collision latch reads
`CXM0P, `CXM0P_7800: Dout <= {collisionLatch[1:0],6'b000000};
`CXM1P, `CXM1P_7800: Dout <= {collisionLatch[3:2],6'b000000};
`CXP0FB, `CXP0FB_7800: Dout <= {collisionLatch[5:4],6'b000000};
`CXP1FB, `CXP1FB_7800: Dout <= {collisionLatch[7:6],6'b000000};
`CXM0FB, `CXM0FB_7800: Dout <= {collisionLatch[9:8],6'b000000};
`CXM1FB, `CXM1FB_7800: Dout <= {collisionLatch[11:10],6'b000000};
`CXBLPF, `CXBLPF_7800: Dout <= {collisionLatch[12],7'b0000000};
`CXPPMM, `CXPPMM_7800: Dout <= {collisionLatch[14:13],6'b000000};
// I/O reads
`INPT0, `INPT0_7800: Dout <= {Idump[0], 7'b0000000};
`INPT1, `INPT1_7800: Dout <= {Idump[1], 7'b0000000};
`INPT2, `INPT2_7800: Dout <= {Idump[2], 7'b0000000};
`INPT3, `INPT3_7800: Dout <= {Idump[3], 7'b0000000};
`INPT4, `INPT4_7800: Dout <= {latchedInputsValue[0], 7'b0000000};
`INPT5, `INPT5_7800: Dout <= {latchedInputsValue[1], 7'b0000000};
// Video signals
`VSYNC: VSYNC <= Din[1];
`VBLANK: begin
inputLatchEnabled <= Din[6];
inputDumpEnabled <= Din[7];
VBLANK <= Din[1];
end
`WSYNC:;
`RSYNC:;
// Screen object register access
`NUSIZ0: player0Size <= {Din[5:4],Din[2:0]};
`NUSIZ1: player1Size <= {Din[5:4],Din[2:0]};
`COLUP0: player0Color <= Din;
`COLUP1: player1Color <= Din;
`COLUPF: pfColor <= Din;
`COLUBK: bgColor <= Din;
`CTRLPF: begin
pfReflect <= Din[0];
pfColorCtrl <= Din[1];
prioCtrl <= Din[2];
ballSize <= Din[5:4];
end
`REFP0: player0Reflect <= Din[3];
`REFP1: player1Reflect <= Din[3];
`PF0: pfGraphic[3:0] <= Din[7:4];
`PF1: pfGraphic[11:4] <= {Din[0], Din[1], Din[2], Din[3],
Din[4], Din[5], Din[6], Din[7]};
`PF2: pfGraphic[19:12] <= Din[7:0];
`RESP0: player0Pos <= pixelNum;
`RESP1: player1Pos <= pixelNum;
`RESM0: missile0Pos <= pixelNum;
`RESM1: missile1Pos <= pixelNum;
`RESBL: ballPos <= pixelNum;
// Audio controls
`AUDC0: audc0 <= Din[3:0];
`AUDC1: audc1 <= Din[3:0];
`AUDF0: audf0 <= Din[4:0];
`AUDF1: audf1 <= Din[4:0];
`AUDV0: audv0 <= Din[3:0];
`AUDV1: audv1 <= Din[3:0];
// Screen object register access
`GRP0: begin
player0Graphic <= {Din[0], Din[1], Din[2], Din[3],
Din[4], Din[5], Din[6], Din[7]};
R_player1Graphic <= player1Graphic;
end
`GRP1: begin
player1Graphic <= {Din[0], Din[1], Din[2], Din[3],
Din[4], Din[5], Din[6], Din[7]};
R_player0Graphic <= player0Graphic;
R_ballEnable <= ballEnable;
end
`ENAM0: missile0Enable <= Din[1];
`ENAM1: missile1Enable <= Din[1];
`ENABL: ballEnable <= Din[1];
`HMP0: player0Motion <= Din[7:4];
`HMP1: player1Motion <= Din[7:4];
`HMM0: missile0Motion <= Din[7:4];
`HMM1: missile1Motion <= Din[7:4];
`HMBL: ballMotion <= Din[7:4];
`VDELP0: player0VertDelay <= Din[0];
`VDELP1: player1VertDelay <= Din[0];
`VDELBL: ballVertDelay <= Din[0];
`RESMP0: missile0Lock <= Din[1];
`RESMP1: missile1Lock <= Din[1];
// Strobed line that initiates an object move
`HMOVE: begin
player0Pos <= player0Pos - {{4{player0Motion[3]}},
player0Motion[3:0]};
player1Pos <= player1Pos - {{4{player1Motion[3]}},
player1Motion[3:0]};
missile0Pos <= missile0Pos - {{4{missile0Motion[3]}},
missile0Motion[3:0]};
missile1Pos <= missile1Pos - {{4{missile1Motion[3]}},
missile1Motion[3:0]};
ballPos <= ballPos - {{4{ballMotion[3]}},ballMotion[3:0]};
end
// Motion register clear
`HMCLR: begin
player0Motion <= Din[7:4];
player1Motion <= Din[7:4];
missile0Motion <= Din[7:4];
missile1Motion <= Din[7:4];
ballMotion <= Din[7:4];
end
`CXCLR:;
default: Dout <= 8'b00000000;
endcase
end
// If the chip is not enabled, do nothing
else begin
inputLatchReset <= 1'b0;
collisionLatchReset <= 1'b0;
hCountReset[0] <= 1'b0;
wSyncReset <= 1'b0;
Dout <= 8'b00000000;
end
end
endmodule
// objPixelOn module
// Checks the pixel number against a stretched and possibly duplicated version of the
// object.
module objPixelOn(pixelNum, objPos, objSize, objMask, pixelOn);
input [7:0] pixelNum, objPos, objMask;
input [2:0] objSize;
output pixelOn;
wire [7:0] objIndex;
wire [8:0] objByteIndex;
wire objMaskOn, objPosOn;
reg objSizeOn;
reg [2:0] objMaskSel;
assign objIndex = pixelNum - objPos - 8'd1;
assign objByteIndex = 9'b1 << (objIndex[7:3]);
always @(objSize, objByteIndex)
begin
case (objSize)
3'd0: objSizeOn <= (objByteIndex & 9'b00000001) != 0;
3'd1: objSizeOn <= (objByteIndex & 9'b00000101) != 0;
3'd2: objSizeOn <= (objByteIndex & 9'b00010001) != 0;
3'd3: objSizeOn <= (objByteIndex & 9'b00010101) != 0;
3'd4: objSizeOn <= (objByteIndex & 9'b10000001) != 0;
3'd5: objSizeOn <= (objByteIndex & 9'b00000011) != 0;
3'd6: objSizeOn <= (objByteIndex & 9'b10010001) != 0;
3'd7: objSizeOn <= (objByteIndex & 9'b00001111) != 0;
endcase
end
always @(objSize, objIndex)
begin
case (objSize)
3'd5: objMaskSel <= objIndex[3:1];
3'd7: objMaskSel <= objIndex[4:2];
default: objMaskSel <= objIndex[2:0];
endcase
end
assign objMaskOn = objMask[objMaskSel];
assign objPosOn = (pixelNum > objPos) && ({1'b0, pixelNum} <= {1'b0, objPos} + 9'd72);
assign pixelOn = objSizeOn && objMaskOn && objPosOn;
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// This module to implement the datapath of ALU
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_alu_dpath(
//////////////////////////////////////////////////////
// ALU request the datapath
input alu_req_alu,
input alu_req_alu_add ,
input alu_req_alu_sub ,
input alu_req_alu_xor ,
input alu_req_alu_sll ,
input alu_req_alu_srl ,
input alu_req_alu_sra ,
input alu_req_alu_or ,
input alu_req_alu_and ,
input alu_req_alu_slt ,
input alu_req_alu_sltu,
input alu_req_alu_lui ,
input [`E203_XLEN-1:0] alu_req_alu_op1,
input [`E203_XLEN-1:0] alu_req_alu_op2,
output [`E203_XLEN-1:0] alu_req_alu_res,
//////////////////////////////////////////////////////
// BJP request the datapath
input bjp_req_alu,
input [`E203_XLEN-1:0] bjp_req_alu_op1,
input [`E203_XLEN-1:0] bjp_req_alu_op2,
input bjp_req_alu_cmp_eq ,
input bjp_req_alu_cmp_ne ,
input bjp_req_alu_cmp_lt ,
input bjp_req_alu_cmp_gt ,
input bjp_req_alu_cmp_ltu,
input bjp_req_alu_cmp_gtu,
input bjp_req_alu_add,
output bjp_req_alu_cmp_res,
output [`E203_XLEN-1:0] bjp_req_alu_add_res,
//////////////////////////////////////////////////////
// AGU request the datapath
input agu_req_alu,
input [`E203_XLEN-1:0] agu_req_alu_op1,
input [`E203_XLEN-1:0] agu_req_alu_op2,
input agu_req_alu_swap,
input agu_req_alu_add ,
input agu_req_alu_and ,
input agu_req_alu_or ,
input agu_req_alu_xor ,
input agu_req_alu_max ,
input agu_req_alu_min ,
input agu_req_alu_maxu,
input agu_req_alu_minu,
output [`E203_XLEN-1:0] agu_req_alu_res,
input agu_sbf_0_ena,
input [`E203_XLEN-1:0] agu_sbf_0_nxt,
output [`E203_XLEN-1:0] agu_sbf_0_r,
input agu_sbf_1_ena,
input [`E203_XLEN-1:0] agu_sbf_1_nxt,
output [`E203_XLEN-1:0] agu_sbf_1_r,
`ifdef E203_SUPPORT_SHARE_MULDIV //{
//////////////////////////////////////////////////////
// MULDIV request the datapath
input muldiv_req_alu,
input [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op1,
input [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op2,
input muldiv_req_alu_add ,
input muldiv_req_alu_sub ,
output [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_res,
input muldiv_sbf_0_ena,
input [33-1:0] muldiv_sbf_0_nxt,
output [33-1:0] muldiv_sbf_0_r,
input muldiv_sbf_1_ena,
input [33-1:0] muldiv_sbf_1_nxt,
output [33-1:0] muldiv_sbf_1_r,
`endif//E203_SUPPORT_SHARE_MULDIV}
input clk,
input rst_n
);
`ifdef E203_XLEN_IS_32
// This is the correct config since E200 is 32bits core
`else
!!! ERROR: There must be something wrong, our core must be 32bits wide !!!
`endif
wire [`E203_XLEN-1:0] mux_op1;
wire [`E203_XLEN-1:0] mux_op2;
wire [`E203_XLEN-1:0] misc_op1 = mux_op1[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] misc_op2 = mux_op2[`E203_XLEN-1:0];
// Only the regular ALU use shifter
wire [`E203_XLEN-1:0] shifter_op1 = alu_req_alu_op1[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] shifter_op2 = alu_req_alu_op2[`E203_XLEN-1:0];
wire op_max;
wire op_min ;
wire op_maxu;
wire op_minu;
wire op_add;
wire op_sub;
wire op_addsub = op_add | op_sub;
wire op_or;
wire op_xor;
wire op_and;
wire op_sll;
wire op_srl;
wire op_sra;
wire op_slt;
wire op_sltu;
wire op_mvop2;
wire op_cmp_eq ;
wire op_cmp_ne ;
wire op_cmp_lt ;
wire op_cmp_gt ;
wire op_cmp_ltu;
wire op_cmp_gtu;
wire cmp_res;
wire sbf_0_ena;
wire [33-1:0] sbf_0_nxt;
wire [33-1:0] sbf_0_r;
wire sbf_1_ena;
wire [33-1:0] sbf_1_nxt;
wire [33-1:0] sbf_1_r;
//////////////////////////////////////////////////////////////
// Impelment the Left-Shifter
//
// The Left-Shifter will be used to handle the shift op
wire [`E203_XLEN-1:0] shifter_in1;
wire [5-1:0] shifter_in2;
wire [`E203_XLEN-1:0] shifter_res;
wire op_shift = op_sra | op_sll | op_srl;
// Make sure to use logic-gating to gateoff the
assign shifter_in1 = {`E203_XLEN{op_shift}} &
// In order to save area and just use one left-shifter, we
// convert the right-shift op into left-shift operation
(
(op_sra | op_srl) ?
{
shifter_op1[00],shifter_op1[01],shifter_op1[02],shifter_op1[03],
shifter_op1[04],shifter_op1[05],shifter_op1[06],shifter_op1[07],
shifter_op1[08],shifter_op1[09],shifter_op1[10],shifter_op1[11],
shifter_op1[12],shifter_op1[13],shifter_op1[14],shifter_op1[15],
shifter_op1[16],shifter_op1[17],shifter_op1[18],shifter_op1[19],
shifter_op1[20],shifter_op1[21],shifter_op1[22],shifter_op1[23],
shifter_op1[24],shifter_op1[25],shifter_op1[26],shifter_op1[27],
shifter_op1[28],shifter_op1[29],shifter_op1[30],shifter_op1[31]
} : shifter_op1
);
assign shifter_in2 = {5{op_shift}} & shifter_op2[4:0];
assign shifter_res = (shifter_in1 << shifter_in2);
wire [`E203_XLEN-1:0] sll_res = shifter_res;
wire [`E203_XLEN-1:0] srl_res =
{
shifter_res[00],shifter_res[01],shifter_res[02],shifter_res[03],
shifter_res[04],shifter_res[05],shifter_res[06],shifter_res[07],
shifter_res[08],shifter_res[09],shifter_res[10],shifter_res[11],
shifter_res[12],shifter_res[13],shifter_res[14],shifter_res[15],
shifter_res[16],shifter_res[17],shifter_res[18],shifter_res[19],
shifter_res[20],shifter_res[21],shifter_res[22],shifter_res[23],
shifter_res[24],shifter_res[25],shifter_res[26],shifter_res[27],
shifter_res[28],shifter_res[29],shifter_res[30],shifter_res[31]
};
wire [`E203_XLEN-1:0] eff_mask = (~(`E203_XLEN'b0)) >> shifter_in2;
wire [`E203_XLEN-1:0] sra_res =
(srl_res & eff_mask) | ({32{shifter_op1[31]}} & (~eff_mask));
//////////////////////////////////////////////////////////////
// Impelment the Adder
//
// The Adder will be reused to handle the add/sub/compare op
// Only the MULDIV request ALU-adder with 35bits operand with sign extended
// already, all other unit request ALU-adder with 32bits opereand without sign extended
// For non-MULDIV operands
wire op_unsigned = op_sltu | op_cmp_ltu | op_cmp_gtu | op_maxu | op_minu;
wire [`E203_ALU_ADDER_WIDTH-1:0] misc_adder_op1 =
{{`E203_ALU_ADDER_WIDTH-`E203_XLEN{(~op_unsigned) & misc_op1[`E203_XLEN-1]}},misc_op1};
wire [`E203_ALU_ADDER_WIDTH-1:0] misc_adder_op2 =
{{`E203_ALU_ADDER_WIDTH-`E203_XLEN{(~op_unsigned) & misc_op2[`E203_XLEN-1]}},misc_op2};
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_op1 =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_op1 :
`endif//E203_SUPPORT_SHARE_MULDIV}
misc_adder_op1;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_op2 =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_op2 :
`endif//E203_SUPPORT_SHARE_MULDIV}
misc_adder_op2;
wire adder_cin;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_in1;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_in2;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_res;
wire adder_add;
wire adder_sub;
assign adder_add =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_add :
`endif//E203_SUPPORT_SHARE_MULDIV}
op_add;
assign adder_sub =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_sub :
`endif//E203_SUPPORT_SHARE_MULDIV}
(
// The original sub instruction
(op_sub)
// The compare lt or gt instruction
| (op_cmp_lt | op_cmp_gt |
op_cmp_ltu | op_cmp_gtu |
op_max | op_maxu |
op_min | op_minu |
op_slt | op_sltu
));
wire adder_addsub = adder_add | adder_sub;
// Make sure to use logic-gating to gateoff the
assign adder_in1 = {`E203_ALU_ADDER_WIDTH{adder_addsub}} & (adder_op1);
assign adder_in2 = {`E203_ALU_ADDER_WIDTH{adder_addsub}} & (adder_sub ? (~adder_op2) : adder_op2);
assign adder_cin = adder_addsub & adder_sub;
assign adder_res = adder_in1 + adder_in2 + adder_cin;
//////////////////////////////////////////////////////////////
// Impelment the XOR-er
//
// The XOR-er will be reused to handle the XOR and compare op
wire [`E203_XLEN-1:0] xorer_in1;
wire [`E203_XLEN-1:0] xorer_in2;
wire xorer_op =
op_xor
// The compare eq or ne instruction
| (op_cmp_eq | op_cmp_ne);
// Make sure to use logic-gating to gateoff the
assign xorer_in1 = {`E203_XLEN{xorer_op}} & misc_op1;
assign xorer_in2 = {`E203_XLEN{xorer_op}} & misc_op2;
wire [`E203_XLEN-1:0] xorer_res = xorer_in1 ^ xorer_in2;
// The OR and AND is too light-weight, so no need to gate off
wire [`E203_XLEN-1:0] orer_res = misc_op1 | misc_op2;
wire [`E203_XLEN-1:0] ander_res = misc_op1 & misc_op2;
//////////////////////////////////////////////////////////////
// Generate the CMP operation result
// It is Non-Equal if the XOR result have any bit non-zero
wire neq = (|xorer_res);
wire cmp_res_ne = (op_cmp_ne & neq);
// It is Equal if it is not Non-Equal
wire cmp_res_eq = op_cmp_eq & (~neq);
// It is Less-Than if the adder result is negative
wire cmp_res_lt = op_cmp_lt & adder_res[`E203_XLEN];
wire cmp_res_ltu = op_cmp_ltu & adder_res[`E203_XLEN];
// It is Greater-Than if the adder result is postive
wire op1_gt_op2 = (~adder_res[`E203_XLEN]);
wire cmp_res_gt = op_cmp_gt & op1_gt_op2;
wire cmp_res_gtu = op_cmp_gtu & op1_gt_op2;
assign cmp_res = cmp_res_eq
| cmp_res_ne
| cmp_res_lt
| cmp_res_gt
| cmp_res_ltu
| cmp_res_gtu;
//////////////////////////////////////////////////////////////
// Generate the mvop2 result
// Just directly use op2 since the op2 will be the immediate
wire [`E203_XLEN-1:0] mvop2_res = misc_op2;
//////////////////////////////////////////////////////////////
// Generate the SLT and SLTU result
// Just directly use op2 since the op2 will be the immediate
wire op_slttu = (op_slt | op_sltu);
// The SLT and SLTU is reusing the adder to do the comparasion
// It is Less-Than if the adder result is negative
wire slttu_cmp_lt = op_slttu & adder_res[`E203_XLEN];
wire [`E203_XLEN-1:0] slttu_res =
slttu_cmp_lt ?
`E203_XLEN'b1 : `E203_XLEN'b0;
//////////////////////////////////////////////////////////////
// Generate the Max/Min result
wire maxmin_sel_op1 = ((op_max | op_maxu) & op1_gt_op2)
| ((op_min | op_minu) & (~op1_gt_op2));
wire [`E203_XLEN-1:0] maxmin_res = maxmin_sel_op1 ? misc_op1 : misc_op2;
//////////////////////////////////////////////////////////////
// Generate the final result
wire [`E203_XLEN-1:0] alu_dpath_res =
({`E203_XLEN{op_or }} & orer_res )
| ({`E203_XLEN{op_and }} & ander_res)
| ({`E203_XLEN{op_xor }} & xorer_res)
| ({`E203_XLEN{op_addsub }} & adder_res[`E203_XLEN-1:0])
| ({`E203_XLEN{op_srl }} & srl_res)
| ({`E203_XLEN{op_sll }} & sll_res)
| ({`E203_XLEN{op_sra }} & sra_res)
| ({`E203_XLEN{op_mvop2 }} & mvop2_res)
| ({`E203_XLEN{op_slttu }} & slttu_res)
| ({`E203_XLEN{op_max | op_maxu | op_min | op_minu}} & maxmin_res)
;
//////////////////////////////////////////////////////////////
// Implement the SBF: Shared Buffers
sirv_gnrl_dffl #(33) sbf_0_dffl (sbf_0_ena, sbf_0_nxt, sbf_0_r, clk);
sirv_gnrl_dffl #(33) sbf_1_dffl (sbf_1_ena, sbf_1_nxt, sbf_1_r, clk);
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
// The ALU-Datapath Mux for the requestors
localparam DPATH_MUX_WIDTH = ((`E203_XLEN*2)+21);
assign {
mux_op1
,mux_op2
,op_max
,op_min
,op_maxu
,op_minu
,op_add
,op_sub
,op_or
,op_xor
,op_and
,op_sll
,op_srl
,op_sra
,op_slt
,op_sltu
,op_mvop2
,op_cmp_eq
,op_cmp_ne
,op_cmp_lt
,op_cmp_gt
,op_cmp_ltu
,op_cmp_gtu
}
=
({DPATH_MUX_WIDTH{alu_req_alu}} & {
alu_req_alu_op1
,alu_req_alu_op2
,1'b0
,1'b0
,1'b0
,1'b0
,alu_req_alu_add
,alu_req_alu_sub
,alu_req_alu_or
,alu_req_alu_xor
,alu_req_alu_and
,alu_req_alu_sll
,alu_req_alu_srl
,alu_req_alu_sra
,alu_req_alu_slt
,alu_req_alu_sltu
,alu_req_alu_lui// LUI just move-Op2 operation
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
})
| ({DPATH_MUX_WIDTH{bjp_req_alu}} & {
bjp_req_alu_op1
,bjp_req_alu_op2
,1'b0
,1'b0
,1'b0
,1'b0
,bjp_req_alu_add
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,bjp_req_alu_cmp_eq
,bjp_req_alu_cmp_ne
,bjp_req_alu_cmp_lt
,bjp_req_alu_cmp_gt
,bjp_req_alu_cmp_ltu
,bjp_req_alu_cmp_gtu
})
| ({DPATH_MUX_WIDTH{agu_req_alu}} & {
agu_req_alu_op1
,agu_req_alu_op2
,agu_req_alu_max
,agu_req_alu_min
,agu_req_alu_maxu
,agu_req_alu_minu
,agu_req_alu_add
,1'b0
,agu_req_alu_or
,agu_req_alu_xor
,agu_req_alu_and
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,agu_req_alu_swap// SWAP just move-Op2 operation
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
})
;
assign alu_req_alu_res = alu_dpath_res[`E203_XLEN-1:0];
assign agu_req_alu_res = alu_dpath_res[`E203_XLEN-1:0];
assign bjp_req_alu_add_res = alu_dpath_res[`E203_XLEN-1:0];
assign bjp_req_alu_cmp_res = cmp_res;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
assign muldiv_req_alu_res = adder_res;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign sbf_0_ena =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_0_ena :
`endif//E203_SUPPORT_SHARE_MULDIV}
agu_sbf_0_ena;
assign sbf_1_ena =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_1_ena :
`endif//E203_SUPPORT_SHARE_MULDIV}
agu_sbf_1_ena;
assign sbf_0_nxt =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_0_nxt :
`endif//E203_SUPPORT_SHARE_MULDIV}
{1'b0,agu_sbf_0_nxt};
assign sbf_1_nxt =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_1_nxt :
`endif//E203_SUPPORT_SHARE_MULDIV}
{1'b0,agu_sbf_1_nxt};
assign agu_sbf_0_r = sbf_0_r[`E203_XLEN-1:0];
assign agu_sbf_1_r = sbf_1_r[`E203_XLEN-1:0];
`ifdef E203_SUPPORT_SHARE_MULDIV //{
assign muldiv_sbf_0_r = sbf_0_r;
assign muldiv_sbf_1_r = sbf_1_r;
`endif//E203_SUPPORT_SHARE_MULDIV}
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O211A_BEHAVIORAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_BEHAVIORAL_PP_V |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6
// \ \ Application: MIG
// / / Filename: axi4_wrapper.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Sept 16, 2009
// \___\/\___\
//
//Device: Virtex-6, Spartan-6 and 7series
//Design Name: DDR3 SDRAM
//Purpose:
// This module is wrapper for converting the reads and writes to transactions
// that follow the AXI4 protocol.
//
//Reference:
//Revision History:
//*****************************************************************************
module mig_7series_v2_0_axi4_wrapper #(
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
// This is an integer between 1-16
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
parameter CTL_SIG_WIDTH = 2, // Control signal width
parameter WR_STS_WIDTH = 16, // Write port status signal width
parameter RD_STS_WIDTH = 16, // Read port status signal width
parameter EN_UPSIZER = 0, // There is no upsizer code
parameter WDG_TIMER_WIDTH = 9
)
(
input aclk, // AXI input clock
input aresetn, // Active low AXI reset signal
// User interface command port
input cmd_en, // Asserted to indicate a valid command
// and address
input [2:0] cmd, // Write or read command
// 000 - READ with INCR bursts
// 001 - READ with WRAP bursts
// 01x - Reserved
// 100 - WRITE with INCR bursts
// 101 - WRITE with WRAP bursts
input [7:0] blen, // Burst length calculated as blen+1
input [31:0] addr, // Address for the read or the write
// transaction
input [CTL_SIG_WIDTH-1:0] ctl, // control command for read or write
// transaction
input wdog_mask, // Mask the watchdog timeouts
output cmd_ack,// Indicates the command has been accepted
// User interface write ports
input wrdata_vld, // Asserted to indicate a valid write
// data
input [C_AXI_DATA_WIDTH-1:0] wrdata, // Write data
input [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld, // Byte valids for the write data
input wrdata_cmptd,// Last data to be transferred
output reg wrdata_rdy, // Indicates that the write data is
// ready to be accepted
output reg wrdata_sts_vld, // Indicates a write status after
// completion of a write transfer
output [WR_STS_WIDTH-1:0] wrdata_sts, // Status of the write transaction
// User interface read ports
input rddata_rdy, // Data ready to be accepted
output reg rddata_vld, // Indicates a valid read data available
output reg [C_AXI_DATA_WIDTH-1:0] rddata, // Read data
output [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld, // Byte valids for read data
output reg rddata_cmptd, // Indicates last data present and
// valid status
output [RD_STS_WIDTH-1:0] rddata_sts, // Status of the read transaction
// AXI write address channel signals
input axi_wready, // Indicates slave is ready to accept a
// write address
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
output [7:0] axi_wlen, // Write Burst Length
output [2:0] axi_wsize, // Write Burst size
output [1:0] axi_wburst, // Write Burst type
output [1:0] axi_wlock, // Write lock type
output [3:0] axi_wcache, // Write Cache type
output [2:0] axi_wprot, // Write Protection type
output reg axi_wvalid, // Write address valid
// AXI write data channel signals
input axi_wd_wready, // Write data ready
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
output reg [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
output reg [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
output reg axi_wd_last, // Last write transaction
output axi_wd_valid, // Write valid
// AXI write response channel signals
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
input [1:0] axi_wd_bresp, // Write response
input axi_wd_bvalid, // Write reponse valid
output reg axi_wd_bready, // Response ready
// AXI read address channel signals
input axi_rready, // Read address ready
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
output [7:0] axi_rlen, // Read Burst Length
output [2:0] axi_rsize, // Read Burst size
output [1:0] axi_rburst, // Read Burst type
output [1:0] axi_rlock, // Read lock type
output [3:0] axi_rcache, // Read Cache type
output [2:0] axi_rprot, // Read Protection type
output reg axi_rvalid, // Read address valid
// AXI read data channel signals
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
input [1:0] axi_rd_rresp, // Read response
input axi_rd_rvalid, // Read reponse valid
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
input axi_rd_last, // Read last
output reg axi_rd_rready // Read Response ready
);
//*****************************************************************************
// Internal parameter declarations
//*****************************************************************************
parameter [8:0] AXI_WRIDLE = 9'd0,
AXI_WRCTL = 9'd1,
AXI_WRRDY = 9'd2,
AXI_WRDAT = 9'd3,
AXI_WRDAT_WT = 9'd4,
AXI_WRDAT_LST = 9'd5,
AXI_WRDAT_DMY = 9'd6,
AXI_WRRESP_WT = 9'd7,
AXI_WRTO = 9'd8;
parameter [5:0] AXI_RDIDLE = 6'd0,
AXI_RDCTL = 6'd1,
AXI_RDDAT = 6'd2,
AXI_RDDAT_LST = 6'd3,
AXI_RDDAT_WT = 6'd4,
AXI_RDTO = 6'd5;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg wrap_w;
reg [7:0] blen_w;
reg [7:0] blen_w_minus_1;
reg [C_AXI_ADDR_WIDTH-1:0] addr_w;
reg [CTL_SIG_WIDTH-1:0] ctl_w;
reg wrap_r;
reg [7:0] blen_r;
reg [C_AXI_ADDR_WIDTH-1:0] addr_r;
reg [CTL_SIG_WIDTH-1:0] ctl_r;
reg [8:0] wstate;
reg [8:0] next_wstate;
reg wr_cmd_start;
reg [WDG_TIMER_WIDTH-1:0] wr_wdog_cntr;
reg wrdata_vld_r;
reg wrdata_cmptd_r;
reg [7:0] wr_len_cntr;
reg [7:0] rd_len_cntr;
reg [7:0] blen_cntr;
reg [3:0] wr_cntr;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r1;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r2;
reg wrdata_mux_ctrl;
reg [2:0] wrdata_fsm_sts;
reg [3:0] brespid_r;
reg [1:0] bresp_r;
reg [5:0] rstate;
reg [5:0] next_rstate;
reg [WDG_TIMER_WIDTH-1:0] rd_wdog_cntr;
reg rd_cmd_start;
reg rlast;
reg [3:0] rd_cntr;
reg rddata_ppld;
reg [C_AXI_DATA_WIDTH-1:0] rddata_p1;
reg err_resp;
reg [1:0] rddata_fsm_sts;
reg rrid_err;
reg pending_one_trans;
reg axi_wready_l;
wire wr_cmd_timeout;
wire wr_done;
wire wr_last;
wire rd_cmd_timeout;
//*****************************************************************************
// Address and control register logic
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn) begin
wrap_w <= 1'b0;
blen_w <= 8'h0;
blen_w_minus_1 <= 8'h0;
addr_w <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_w <= {CTL_SIG_WIDTH{1'b0}};
end
else if (wstate[AXI_WRIDLE] & next_wstate[AXI_WRIDLE] &
cmd_en & cmd[2]) begin
wrap_w <= cmd[0];
blen_w <= blen;
blen_w_minus_1 <= blen - 8'h01;
addr_w <= addr;
ctl_w <= ctl;
end
end
always @(posedge aclk) begin
if (!aresetn) begin
wrap_r <= 1'b0;
blen_r <= 8'h0;
addr_r <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_r <= {CTL_SIG_WIDTH{1'b0}};
end
else if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDIDLE] &
cmd_en & !cmd[2]) begin
wrap_r <= cmd[0];
blen_r <= blen;
addr_r <= addr;
ctl_r <= ctl;
end
end
assign cmd_ack = (wstate[AXI_WRIDLE] & next_wstate[AXI_WRCTL]) |
(rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL]);
//*****************************************************************************
// Write data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cmd_start <= 1'b0;
else if (cmd_en & cmd[2] & wstate[AXI_WRIDLE])
wr_cmd_start <= 1'b1;
else if (wstate[AXI_WRCTL])
wr_cmd_start <= 1'b0;
always @(posedge aclk)
if (wstate[AXI_WRIDLE] |
(axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT] | wstate[AXI_WRDAT_LST] | wstate[AXI_WRDAT_DMY])) |
(axi_wd_bvalid & wstate[AXI_WRRESP_WT]))
wr_wdog_cntr <= 'h0;
else if (!wstate[AXI_WRTO] & !wdog_mask)
wr_wdog_cntr <= wr_wdog_cntr + 'h1;
always @(posedge aclk)
wrdata_vld_r <= wrdata_vld;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_cmptd_r <= 1'b0;
else if (wrdata_cmptd & wrdata_vld)
wrdata_cmptd_r <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
blen_cntr <= 8'h0;
else if (wrdata_vld & wrdata_rdy)
blen_cntr <= blen_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
pending_one_trans <= 1'b0;
else if (next_wstate[AXI_WRDAT] & wstate[AXI_WRDAT_WT])
pending_one_trans <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & wr_last & !axi_wd_wready)
pending_one_trans <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wr_len_cntr <= 8'h0;
else if ((wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) &
axi_wd_valid & axi_wd_wready)
wr_len_cntr <= wr_len_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wready_l <= 1'b0;
else if (axi_wready)
axi_wready_l <= 1'b1;
assign wr_cmd_timeout = wr_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
assign wr_last = (wr_len_cntr >= blen_w_minus_1);
assign wr_done = (blen_cntr >= blen_w);
//*****************************************************************************
// Write data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
wstate <= 9'h1;
else
wstate <= next_wstate;
end
always @(*) begin
next_wstate = 9'h0;
case (1'b1)
wstate[AXI_WRIDLE]: begin // 9'h001
if (wr_cmd_start)
next_wstate[AXI_WRCTL] = 1'b1;
else
next_wstate[AXI_WRIDLE] = 1'b1;
end
wstate[AXI_WRCTL]: begin // 9'h002
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wvalid)
next_wstate[AXI_WRRDY] = 1'b1;
else
next_wstate[AXI_WRCTL] = 1'b1;
end
wstate[AXI_WRRDY]: begin // 9'h004
if (wrdata_cmptd_r & wrdata_rdy)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (wrdata_vld_r & wrdata_rdy)
next_wstate[AXI_WRDAT] = 1'b1;
else
next_wstate[AXI_WRRDY] = 1'b1;
end
wstate[AXI_WRDAT]: begin // 9'h008
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else if (!axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
wstate[AXI_WRDAT_WT]: begin // 9'h010
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready) begin
if (pending_one_trans & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!pending_one_trans & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
else
next_wstate[AXI_WRDAT_WT] = 1'b1;
end
wstate[AXI_WRDAT_LST]: begin // 9'h020
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_valid & axi_wd_wready)
next_wstate[AXI_WRRESP_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_LST] = 1'b1;
end
wstate[AXI_WRDAT_DMY]: begin // 9'h040
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (wrdata_cmptd_r & wr_last)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!wr_last & !axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_DMY] = 1'b1;
end
wstate[AXI_WRRESP_WT]: begin // 9'h080
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_bvalid &
(EN_UPSIZER == 1 || (EN_UPSIZER == 0 & axi_wready_l)))
next_wstate[AXI_WRIDLE] = 1'b1;
else
next_wstate[AXI_WRRESP_WT] = 1'b1;
end
wstate[AXI_WRTO]: begin // 9'h100
next_wstate[AXI_WRIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Write channel control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cntr <= 4'h0;
else if (wstate[AXI_WRRESP_WT] & next_wstate[AXI_WRIDLE])
wr_cntr <= wr_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_wvalid <= 1'b0;
else if ((wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY] & axi_wready) ||
(axi_wready & !wstate[AXI_WRCTL]))
axi_wvalid <= 1'b0;
else if (wstate[AXI_WRCTL])
axi_wvalid <= 1'b1;
assign awid = wr_cntr;
assign axi_waddr = addr_w;
assign axi_wid = wr_cntr;
assign axi_wlen = blen_w;
assign axi_wburst = {1'b0, wrap_w} + 2'b01;
assign axi_wsize = ctl_w[2:0];
// Not supported and hence assigned zeros
assign axi_wlock = 2'b0;
assign axi_wcache = 4'b0;
assign axi_wprot = 3'b0;
//*****************************************************************************
// Write channel data signals
//*****************************************************************************
always @(posedge aclk) begin
if (wstate[AXI_WRIDLE]) begin
wrdata_r1 <= 'h0;
wrdata_r2 <= 'h0;
end
else if (wrdata_rdy & wrdata_vld & (wstate[AXI_WRDAT] | wstate[AXI_WRRDY] |
wstate[AXI_WRDAT_LST])) begin
wrdata_r1 <= wrdata;
wrdata_r2 <= wrdata_r1;
end
end
always @(posedge aclk)
if (!aresetn)
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT_LST] | (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT]))
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT] |
(wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY]) |
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT]))
wrdata_rdy <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_sts_vld <= 1'b0;
else if (wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b0;
else if ((wstate[AXI_WRRESP_WT] | wstate[AXI_WRTO]) & next_wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_mux_ctrl <= 1'b0;
else if ((wstate[AXI_WRDAT_WT] & (next_wstate[AXI_WRDAT] | next_wstate[AXI_WRDAT_LST])) |
wstate[AXI_WRIDLE])
wrdata_mux_ctrl <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & !pending_one_trans)
wrdata_mux_ctrl <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_wd_last <= 1'b0;
else if (wstate[AXI_WRDAT_LST] & next_wstate[AXI_WRRESP_WT])
axi_wd_last <= 1'b0;
else if ((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY] | wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT_LST])
axi_wd_last <= 1'b1;
generate
begin: data_axi_wr
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_data <= 'h0;
else if (axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) & wrdata_mux_ctrl &
~next_wstate[AXI_WRDAT_LST])
axi_wd_data <= wrdata_r2;
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT_LST]) |
(wstate[AXI_WRDAT_LST] & !next_wstate[AXI_WRRESP_WT]))) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]))
axi_wd_data <= wrdata_r1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(next_wstate[AXI_WRDAT_LST] & (wstate[AXI_WRRDY] | wstate[AXI_WRDAT])) |
((wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT]))) |
(next_wstate[AXI_WRDAT_LST] & !axi_wd_wready &
(wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT])) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]) |
((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY]) & next_wstate[AXI_WRDAT_WT]) |
(wstate[AXI_WRDAT_WT]))
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b1}};
else
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
end
end
endgenerate
assign axi_wd_wid = wr_cntr;
assign axi_wd_valid = wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT];
//*****************************************************************************
// Write response and status signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
axi_wd_bready <= 1'b0;
else if (next_wstate[AXI_WRIDLE] & wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b0;
else if (wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_fsm_sts <= 3'b000;
else begin
if (next_wstate[AXI_WRTO]) begin
if (wstate[AXI_WRDAT])
wrdata_fsm_sts <= 3'b001;
else if (wstate[AXI_WRDAT_WT])
wrdata_fsm_sts <= 3'b010;
else if (wstate[AXI_WRDAT_DMY])
wrdata_fsm_sts <= 3'b011;
else if (wstate[AXI_WRRESP_WT])
wrdata_fsm_sts <= 3'b100;
end
end
always @(posedge aclk)
if (wstate[AXI_WRIDLE]) begin
brespid_r <= 4'h0;
bresp_r <= 2'b00;
end
else if (wstate[AXI_WRRESP_WT] & axi_wd_bvalid) begin
brespid_r <= axi_wd_bid;
bresp_r <= axi_wd_bresp;
end
assign wrdata_sts = {{{WR_STS_WIDTH-8}{1'b0}},wrdata_fsm_sts,brespid_r[3:0],bresp_r};
//*****************************************************************************
// Read data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (rstate[AXI_RDIDLE] | axi_rready | axi_rd_rvalid)
rd_wdog_cntr <= 'h0;
else if (!rstate[AXI_RDTO])
rd_wdog_cntr <= rd_wdog_cntr + 'h1;
always @(posedge aclk)
if (!aresetn)
rd_cmd_start <= 1'b0;
else if (cmd_en & !cmd[2] & rstate[AXI_RDIDLE])
rd_cmd_start <= 1'b1;
else if (rstate[AXI_RDCTL])
rd_cmd_start <= 1'b0;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rlast <= 1'b0;
else if (axi_rd_last & axi_rd_rvalid)
rlast <= 1'b1;
assign rd_cmd_timeout = rd_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
//*****************************************************************************
// Read data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
rstate <= 6'h1;
else
rstate <= next_rstate;
end
always @(*) begin
next_rstate = 6'h0;
case (1'b1)
rstate[AXI_RDIDLE]: begin // 6'h01
if (rd_cmd_start)
next_rstate[AXI_RDCTL] = 1'b1;
else
next_rstate[AXI_RDIDLE] = 1'b1;
end
rstate[AXI_RDCTL]: begin // 6'h02
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (axi_rready & axi_rvalid) begin
if (rddata_rdy)
next_rstate[AXI_RDDAT] = 1'b1;
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
else
next_rstate[AXI_RDCTL] = 1'b1;
end
rstate[AXI_RDDAT]: begin // 6'h04
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDDAT_LST]: begin // 6'h08
if (rddata_cmptd & rddata_vld & rddata_rdy)
next_rstate[AXI_RDIDLE] = 1'b1;
else
next_rstate[AXI_RDDAT_LST] = 1'b1;
end
rstate[AXI_RDDAT_WT]: begin // 6'h10
if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDTO]: begin // 6'h20
next_rstate[AXI_RDIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Read Address control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rd_cntr <= 4'h0;
else if (rstate[AXI_RDDAT_LST] & next_rstate[AXI_RDIDLE])
rd_cntr <= rd_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDDAT])
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL])
axi_rvalid <= 1'b1;
assign axi_rid = rd_cntr;
generate
begin: addr_axi_rd
if (C_AXI_DATA_WIDTH == 256)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:5], 5'b0};
else if (C_AXI_DATA_WIDTH == 128)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:4], 4'b0};
else if (C_AXI_DATA_WIDTH == 64)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:3], 3'b0};
else
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:2], 2'b0};
end
endgenerate
assign axi_rlen = blen_r;
assign axi_rburst = {1'b0, wrap_r} + 2'b01;
assign axi_rsize = ctl_r[2:0];
// Not supported and hence assigned zeros
assign axi_rlock = 2'b0;
assign axi_rcache = 4'b0;
assign axi_rprot = 3'b0;
//*****************************************************************************
// Read channel data signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rddata_vld <= 1'b0;
else if ((rddata_vld & !axi_rd_rvalid & rstate[AXI_RDDAT]) |
(rddata_rdy & rstate[AXI_RDDAT_LST]) |
(rstate[AXI_RDDAT_WT] & next_rstate[AXI_RDDAT] & rddata_ppld) |
(rddata_rdy & axi_rd_rvalid & axi_rd_last) |
rstate[AXI_RDIDLE])
rddata_vld <= 1'b0;
else if ((rstate[AXI_RDDAT] & axi_rd_rvalid & !axi_rd_last) |
((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
rddata_ppld <= 1'b0;
else if (rddata_vld & rddata_rdy)
rddata_ppld <= 1'b0;
else if (!rddata_vld & axi_rd_rvalid & axi_rd_rready & rstate[AXI_RDDAT_WT])
rddata_ppld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_rd_rready <= 1'b0;
else if (rstate[AXI_RDIDLE] |
(rstate[AXI_RDDAT] & next_rstate[AXI_RDDAT_WT]) |
(rstate[AXI_RDDAT_WT] & !next_rstate[AXI_RDDAT] & rddata_ppld) |
(next_rstate[AXI_RDDAT_LST] & (rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT])))
axi_rd_rready <= 1'b0;
else if ((next_rstate[AXI_RDDAT] & (rstate[AXI_RDCTL] | rstate[AXI_RDDAT_WT])) |
(next_rstate[AXI_RDDAT_LST] & rstate[AXI_RDDAT_WT] & rddata_ppld) |
(rstate[AXI_RDDAT_WT] & !rddata_ppld) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last))
axi_rd_rready <= 1'b1;
always @(posedge aclk)
if (axi_rd_rvalid)
rddata_p1 <= axi_rd_data;
generate
begin: data_axi_rd
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
always @(posedge aclk)
if (axi_rd_rvalid & !rddata_ppld)
rddata <= axi_rd_data;
else if (rddata_rdy & rddata_vld & rddata_ppld)
rddata <= rddata_p1;
assign rddata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
end
end
endgenerate
always @(posedge aclk)
if (!aresetn)
rddata_cmptd <= 1'b0;
else if ((next_rstate[AXI_RDIDLE] & rstate[AXI_RDDAT_LST]) |
rstate[AXI_RDIDLE])
rddata_cmptd <= 1'b0;
else if (((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_cmptd <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
err_resp <= 1'b0;
else if (axi_rd_rvalid & axi_rd_rresp[1])
err_resp <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rddata_fsm_sts <= 2'b00;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b01;
else if (rstate[AXI_RDDAT] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b10;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rrid_err <= 1'b0;
else if (axi_rd_rvalid & axi_rd_bid != rd_cntr)
rrid_err <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rd_len_cntr <= 8'h0;
else if (axi_rd_rvalid & axi_rd_rready)
rd_len_cntr <= rd_len_cntr + 8'h01;
assign rddata_sts = {{(RD_STS_WIDTH-12){1'b0}},rd_len_cntr,rddata_fsm_sts,rrid_err,err_resp};
// synthesis translate_off
always @(posedge aclk) begin
if (rd_cmd_timeout)
$display ("ERR: Read timeout occured at time %t", $time);
if (wr_cmd_timeout)
$display ("ERR: Write timeout occured at time %t", $time);
end
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_LS__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_FUNCTIONAL_V |
/* Simple external interrupt controller for MIPSfpga+ system
* managed using AHB-Lite bus
* Copyright(c) 2017 Stanislav Zhelnio
* https://github.com/zhelnio/ahb_lite_eic
*/
`include "mfp_eic_core.vh"
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] HPROT, // ignored
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output reg [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//Interrupt side
input [ `EIC_CHANNELS-1 : 0 ] signal,
//CPU side
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present,
input EIC_IAck,
input [ 7 : 0 ] EIC_IPL,
input [ 5 : 0 ] EIC_IVN,
input [ 17 : 1 ] EIC_ION
);
assign HRESP = 1'b0;
assign HREADY = 1'b1;
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
wire [ 31 : 0 ] write_data;
reg write_enable;
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] ADDR = HADDR [ `EIC_ADDR_WIDTH + 2 : 2 ];
parameter HTRANS_IDLE = 2'b0;
wire NeedRead = HTRANS != HTRANS_IDLE && HSEL;
wire NeedWrite = NeedRead & HWRITE;
assign write_data = HWDATA;
assign read_addr = ADDR;
always @ (posedge HCLK)
if(~HRESETn)
write_enable <= 1'b0;
else begin
if(NeedRead)
HRDATA <= read_data;
if(NeedWrite)
write_addr <= ADDR;
write_enable <= NeedWrite;
end
mfp_eic_core eic_core
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.signal ( signal ),
.read_addr ( read_addr ),
.read_data ( read_data ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present ),
.EIC_IAck ( EIC_IAck ),
.EIC_IPL ( EIC_IPL ),
.EIC_IVN ( EIC_IVN ),
.EIC_ION ( EIC_ION )
);
endmodule
|
module drawEnemy(
input clk,
input wire [9:0] characterPositionX,
input wire [8:0] characterPositionY,
input wire [9:0] drawingPositionX,
input wire [8:0] drawingPositionY,
output reg [2:0] rgb
);
reg [9:0] x;
reg [9:0] y;
initial begin
x = 'd0;
y = 'd0;
end
always @(posedge clk) begin
x <= (drawingPositionX - characterPositionX + 16);
y <= (drawingPositionY - characterPositionY + 16);
if(x==4 && y==1) begin rgb <= 3'b001; end
else if(x==5 && y==1) begin rgb <= 3'b001; end
else if(x==6 && y==1) begin rgb <= 3'b001; end
else if(x==7 && y==1) begin rgb <= 3'b001; end
else if(x==20 && y==1) begin rgb <= 3'b001; end
else if(x==21 && y==1) begin rgb <= 3'b001; end
else if(x==22 && y==1) begin rgb <= 3'b001; end
else if(x==4 && y==2) begin rgb <= 3'b001; end
else if(x==5 && y==2) begin rgb <= 3'b001; end
else if(x==6 && y==2) begin rgb <= 3'b001; end
else if(x==7 && y==2) begin rgb <= 3'b001; end
else if(x==8 && y==2) begin rgb <= 3'b001; end
else if(x==18 && y==2) begin rgb <= 3'b001; end
else if(x==19 && y==2) begin rgb <= 3'b001; end
else if(x==20 && y==2) begin rgb <= 3'b001; end
else if(x==21 && y==2) begin rgb <= 3'b001; end
else if(x==22 && y==2) begin rgb <= 3'b001; end
else if(x==4 && y==3) begin rgb <= 3'b001; end
else if(x==5 && y==3) begin rgb <= 3'b001; end
else if(x==6 && y==3) begin rgb <= 3'b001; end
else if(x==7 && y==3) begin rgb <= 3'b001; end
else if(x==8 && y==3) begin rgb <= 3'b001; end
else if(x==9 && y==3) begin rgb <= 3'b101; end
else if(x==10 && y==3) begin rgb <= 3'b101; end
else if(x==11 && y==3) begin rgb <= 3'b101; end
else if(x==12 && y==3) begin rgb <= 3'b101; end
else if(x==13 && y==3) begin rgb <= 3'b101; end
else if(x==14 && y==3) begin rgb <= 3'b101; end
else if(x==15 && y==3) begin rgb <= 3'b101; end
else if(x==16 && y==3) begin rgb <= 3'b101; end
else if(x==17 && y==3) begin rgb <= 3'b001; end
else if(x==18 && y==3) begin rgb <= 3'b001; end
else if(x==19 && y==3) begin rgb <= 3'b001; end
else if(x==20 && y==3) begin rgb <= 3'b001; end
else if(x==21 && y==3) begin rgb <= 3'b001; end
else if(x==22 && y==3) begin rgb <= 3'b001; end
else if(x==4 && y==4) begin rgb <= 3'b001; end
else if(x==5 && y==4) begin rgb <= 3'b001; end
else if(x==6 && y==4) begin rgb <= 3'b101; end
else if(x==7 && y==4) begin rgb <= 3'b101; end
else if(x==8 && y==4) begin rgb <= 3'b101; end
else if(x==9 && y==4) begin rgb <= 3'b101; end
else if(x==10 && y==4) begin rgb <= 3'b101; end
else if(x==11 && y==4) begin rgb <= 3'b101; end
else if(x==12 && y==4) begin rgb <= 3'b101; end
else if(x==13 && y==4) begin rgb <= 3'b101; end
else if(x==14 && y==4) begin rgb <= 3'b101; end
else if(x==15 && y==4) begin rgb <= 3'b101; end
else if(x==16 && y==4) begin rgb <= 3'b001; end
else if(x==17 && y==4) begin rgb <= 3'b001; end
else if(x==18 && y==4) begin rgb <= 3'b001; end
else if(x==19 && y==4) begin rgb <= 3'b001; end
else if(x==20 && y==4) begin rgb <= 3'b001; end
else if(x==21 && y==4) begin rgb <= 3'b001; end
else if(x==22 && y==4) begin rgb <= 3'b001; end
else if(x==4 && y==5) begin rgb <= 3'b001; end
else if(x==5 && y==5) begin rgb <= 3'b101; end
else if(x==6 && y==5) begin rgb <= 3'b101; end
else if(x==7 && y==5) begin rgb <= 3'b101; end
else if(x==8 && y==5) begin rgb <= 3'b101; end
else if(x==9 && y==5) begin rgb <= 3'b101; end
else if(x==10 && y==5) begin rgb <= 3'b101; end
else if(x==11 && y==5) begin rgb <= 3'b101; end
else if(x==12 && y==5) begin rgb <= 3'b101; end
else if(x==13 && y==5) begin rgb <= 3'b101; end
else if(x==14 && y==5) begin rgb <= 3'b101; end
else if(x==15 && y==5) begin rgb <= 3'b101; end
else if(x==16 && y==5) begin rgb <= 3'b001; end
else if(x==17 && y==5) begin rgb <= 3'b001; end
else if(x==18 && y==5) begin rgb <= 3'b001; end
else if(x==19 && y==5) begin rgb <= 3'b001; end
else if(x==20 && y==5) begin rgb <= 3'b001; end
else if(x==21 && y==5) begin rgb <= 3'b001; end
else if(x==22 && y==5) begin rgb <= 3'b001; end
else if(x==4 && y==6) begin rgb <= 3'b101; end
else if(x==5 && y==6) begin rgb <= 3'b101; end
else if(x==6 && y==6) begin rgb <= 3'b101; end
else if(x==7 && y==6) begin rgb <= 3'b101; end
else if(x==8 && y==6) begin rgb <= 3'b101; end
else if(x==9 && y==6) begin rgb <= 3'b101; end
else if(x==10 && y==6) begin rgb <= 3'b101; end
else if(x==11 && y==6) begin rgb <= 3'b101; end
else if(x==12 && y==6) begin rgb <= 3'b101; end
else if(x==13 && y==6) begin rgb <= 3'b101; end
else if(x==14 && y==6) begin rgb <= 3'b101; end
else if(x==15 && y==6) begin rgb <= 3'b101; end
else if(x==16 && y==6) begin rgb <= 3'b101; end
else if(x==17 && y==6) begin rgb <= 3'b001; end
else if(x==18 && y==6) begin rgb <= 3'b001; end
else if(x==19 && y==6) begin rgb <= 3'b001; end
else if(x==20 && y==6) begin rgb <= 3'b001; end
else if(x==21 && y==6) begin rgb <= 3'b001; end
else if(x==22 && y==6) begin rgb <= 3'b001; end
else if(x==4 && y==7) begin rgb <= 3'b101; end
else if(x==5 && y==7) begin rgb <= 3'b101; end
else if(x==6 && y==7) begin rgb <= 3'b101; end
else if(x==7 && y==7) begin rgb <= 3'b101; end
else if(x==8 && y==7) begin rgb <= 3'b101; end
else if(x==9 && y==7) begin rgb <= 3'b101; end
else if(x==10 && y==7) begin rgb <= 3'b101; end
else if(x==11 && y==7) begin rgb <= 3'b101; end
else if(x==12 && y==7) begin rgb <= 3'b101; end
else if(x==13 && y==7) begin rgb <= 3'b101; end
else if(x==14 && y==7) begin rgb <= 3'b101; end
else if(x==15 && y==7) begin rgb <= 3'b101; end
else if(x==16 && y==7) begin rgb <= 3'b101; end
else if(x==17 && y==7) begin rgb <= 3'b101; end
else if(x==18 && y==7) begin rgb <= 3'b101; end
else if(x==19 && y==7) begin rgb <= 3'b001; end
else if(x==20 && y==7) begin rgb <= 3'b001; end
else if(x==21 && y==7) begin rgb <= 3'b001; end
else if(x==22 && y==7) begin rgb <= 3'b001; end
else if(x==3 && y==8) begin rgb <= 3'b101; end
else if(x==4 && y==8) begin rgb <= 3'b101; end
else if(x==5 && y==8) begin rgb <= 3'b101; end
else if(x==6 && y==8) begin rgb <= 3'b101; end
else if(x==7 && y==8) begin rgb <= 3'b101; end
else if(x==8 && y==8) begin rgb <= 3'b101; end
else if(x==9 && y==8) begin rgb <= 3'b101; end
else if(x==10 && y==8) begin rgb <= 3'b101; end
else if(x==11 && y==8) begin rgb <= 3'b101; end
else if(x==12 && y==8) begin rgb <= 3'b101; end
else if(x==13 && y==8) begin rgb <= 3'b101; end
else if(x==14 && y==8) begin rgb <= 3'b101; end
else if(x==15 && y==8) begin rgb <= 3'b101; end
else if(x==16 && y==8) begin rgb <= 3'b101; end
else if(x==17 && y==8) begin rgb <= 3'b101; end
else if(x==18 && y==8) begin rgb <= 3'b101; end
else if(x==19 && y==8) begin rgb <= 3'b101; end
else if(x==20 && y==8) begin rgb <= 3'b101; end
else if(x==21 && y==8) begin rgb <= 3'b101; end
else if(x==22 && y==8) begin rgb <= 3'b101; end
else if(x==3 && y==9) begin rgb <= 3'b101; end
else if(x==4 && y==9) begin rgb <= 3'b101; end
else if(x==5 && y==9) begin rgb <= 3'b101; end
else if(x==6 && y==9) begin rgb <= 3'b101; end
else if(x==7 && y==9) begin rgb <= 3'b101; end
else if(x==8 && y==9) begin rgb <= 3'b101; end
else if(x==9 && y==9) begin rgb <= 3'b101; end
else if(x==10 && y==9) begin rgb <= 3'b101; end
else if(x==11 && y==9) begin rgb <= 3'b101; end
else if(x==12 && y==9) begin rgb <= 3'b101; end
else if(x==13 && y==9) begin rgb <= 3'b101; end
else if(x==14 && y==9) begin rgb <= 3'b101; end
else if(x==15 && y==9) begin rgb <= 3'b101; end
else if(x==16 && y==9) begin rgb <= 3'b101; end
else if(x==17 && y==9) begin rgb <= 3'b101; end
else if(x==18 && y==9) begin rgb <= 3'b101; end
else if(x==19 && y==9) begin rgb <= 3'b101; end
else if(x==20 && y==9) begin rgb <= 3'b101; end
else if(x==21 && y==9) begin rgb <= 3'b101; end
else if(x==22 && y==9) begin rgb <= 3'b101; end
else if(x==29 && y==9) begin rgb <= 3'b001; end
else if(x==3 && y==10) begin rgb <= 3'b101; end
else if(x==4 && y==10) begin rgb <= 3'b101; end
else if(x==5 && y==10) begin rgb <= 3'b101; end
else if(x==6 && y==10) begin rgb <= 3'b111; end
else if(x==7 && y==10) begin rgb <= 3'b101; end
else if(x==8 && y==10) begin rgb <= 3'b101; end
else if(x==9 && y==10) begin rgb <= 3'b101; end
else if(x==10 && y==10) begin rgb <= 3'b101; end
else if(x==11 && y==10) begin rgb <= 3'b101; end
else if(x==12 && y==10) begin rgb <= 3'b101; end
else if(x==13 && y==10) begin rgb <= 3'b101; end
else if(x==14 && y==10) begin rgb <= 3'b111; end
else if(x==15 && y==10) begin rgb <= 3'b101; end
else if(x==16 && y==10) begin rgb <= 3'b101; end
else if(x==17 && y==10) begin rgb <= 3'b101; end
else if(x==18 && y==10) begin rgb <= 3'b101; end
else if(x==19 && y==10) begin rgb <= 3'b101; end
else if(x==20 && y==10) begin rgb <= 3'b101; end
else if(x==21 && y==10) begin rgb <= 3'b101; end
else if(x==22 && y==10) begin rgb <= 3'b101; end
else if(x==28 && y==10) begin rgb <= 3'b001; end
else if(x==29 && y==10) begin rgb <= 3'b001; end
else if(x==3 && y==11) begin rgb <= 3'b101; end
else if(x==4 && y==11) begin rgb <= 3'b101; end
else if(x==5 && y==11) begin rgb <= 3'b111; end
else if(x==7 && y==11) begin rgb <= 3'b111; end
else if(x==8 && y==11) begin rgb <= 3'b101; end
else if(x==9 && y==11) begin rgb <= 3'b101; end
else if(x==10 && y==11) begin rgb <= 3'b101; end
else if(x==11 && y==11) begin rgb <= 3'b101; end
else if(x==12 && y==11) begin rgb <= 3'b101; end
else if(x==13 && y==11) begin rgb <= 3'b111; end
else if(x==15 && y==11) begin rgb <= 3'b111; end
else if(x==16 && y==11) begin rgb <= 3'b101; end
else if(x==17 && y==11) begin rgb <= 3'b101; end
else if(x==18 && y==11) begin rgb <= 3'b101; end
else if(x==19 && y==11) begin rgb <= 3'b101; end
else if(x==20 && y==11) begin rgb <= 3'b101; end
else if(x==21 && y==11) begin rgb <= 3'b101; end
else if(x==22 && y==11) begin rgb <= 3'b101; end
else if(x==26 && y==11) begin rgb <= 3'b001; end
else if(x==27 && y==11) begin rgb <= 3'b001; end
else if(x==28 && y==11) begin rgb <= 3'b001; end
else if(x==29 && y==11) begin rgb <= 3'b001; end
else if(x==3 && y==12) begin rgb <= 3'b101; end
else if(x==4 && y==12) begin rgb <= 3'b101; end
else if(x==5 && y==12) begin rgb <= 3'b111; end
else if(x==7 && y==12) begin rgb <= 3'b111; end
else if(x==8 && y==12) begin rgb <= 3'b101; end
else if(x==9 && y==12) begin rgb <= 3'b101; end
else if(x==10 && y==12) begin rgb <= 3'b101; end
else if(x==11 && y==12) begin rgb <= 3'b101; end
else if(x==12 && y==12) begin rgb <= 3'b101; end
else if(x==13 && y==12) begin rgb <= 3'b111; end
else if(x==15 && y==12) begin rgb <= 3'b111; end
else if(x==16 && y==12) begin rgb <= 3'b101; end
else if(x==17 && y==12) begin rgb <= 3'b101; end
else if(x==18 && y==12) begin rgb <= 3'b101; end
else if(x==19 && y==12) begin rgb <= 3'b101; end
else if(x==20 && y==12) begin rgb <= 3'b101; end
else if(x==21 && y==12) begin rgb <= 3'b101; end
else if(x==22 && y==12) begin rgb <= 3'b101; end
else if(x==26 && y==12) begin rgb <= 3'b001; end
else if(x==27 && y==12) begin rgb <= 3'b001; end
else if(x==28 && y==12) begin rgb <= 3'b001; end
else if(x==3 && y==13) begin rgb <= 3'b101; end
else if(x==4 && y==13) begin rgb <= 3'b101; end
else if(x==5 && y==13) begin rgb <= 3'b101; end
else if(x==6 && y==13) begin rgb <= 3'b111; end
else if(x==7 && y==13) begin rgb <= 3'b101; end
else if(x==8 && y==13) begin rgb <= 3'b101; end
else if(x==9 && y==13) begin rgb <= 3'b101; end
else if(x==10 && y==13) begin rgb <= 3'b101; end
else if(x==11 && y==13) begin rgb <= 3'b101; end
else if(x==12 && y==13) begin rgb <= 3'b101; end
else if(x==13 && y==13) begin rgb <= 3'b101; end
else if(x==14 && y==13) begin rgb <= 3'b111; end
else if(x==15 && y==13) begin rgb <= 3'b101; end
else if(x==16 && y==13) begin rgb <= 3'b101; end
else if(x==17 && y==13) begin rgb <= 3'b101; end
else if(x==18 && y==13) begin rgb <= 3'b101; end
else if(x==19 && y==13) begin rgb <= 3'b101; end
else if(x==20 && y==13) begin rgb <= 3'b101; end
else if(x==21 && y==13) begin rgb <= 3'b101; end
else if(x==22 && y==13) begin rgb <= 3'b101; end
else if(x==25 && y==13) begin rgb <= 3'b101; end
else if(x==3 && y==14) begin rgb <= 3'b101; end
else if(x==4 && y==14) begin rgb <= 3'b101; end
else if(x==5 && y==14) begin rgb <= 3'b101; end
else if(x==6 && y==14) begin rgb <= 3'b101; end
else if(x==7 && y==14) begin rgb <= 3'b101; end
else if(x==8 && y==14) begin rgb <= 3'b101; end
else if(x==9 && y==14) begin rgb <= 3'b101; end
else if(x==10 && y==14) begin rgb <= 3'b101; end
else if(x==11 && y==14) begin rgb <= 3'b101; end
else if(x==12 && y==14) begin rgb <= 3'b101; end
else if(x==13 && y==14) begin rgb <= 3'b101; end
else if(x==14 && y==14) begin rgb <= 3'b101; end
else if(x==15 && y==14) begin rgb <= 3'b101; end
else if(x==16 && y==14) begin rgb <= 3'b101; end
else if(x==17 && y==14) begin rgb <= 3'b101; end
else if(x==18 && y==14) begin rgb <= 3'b101; end
else if(x==19 && y==14) begin rgb <= 3'b101; end
else if(x==20 && y==14) begin rgb <= 3'b101; end
else if(x==21 && y==14) begin rgb <= 3'b101; end
else if(x==22 && y==14) begin rgb <= 3'b101; end
else if(x==23 && y==14) begin rgb <= 3'b101; end
else if(x==25 && y==14) begin rgb <= 3'b101; end
else if(x==3 && y==15) begin rgb <= 3'b101; end
else if(x==4 && y==15) begin rgb <= 3'b101; end
else if(x==5 && y==15) begin rgb <= 3'b101; end
else if(x==6 && y==15) begin rgb <= 3'b101; end
else if(x==7 && y==15) begin rgb <= 3'b101; end
else if(x==9 && y==15) begin rgb <= 3'b101; end
else if(x==11 && y==15) begin rgb <= 3'b101; end
else if(x==13 && y==15) begin rgb <= 3'b101; end
else if(x==14 && y==15) begin rgb <= 3'b101; end
else if(x==15 && y==15) begin rgb <= 3'b101; end
else if(x==16 && y==15) begin rgb <= 3'b101; end
else if(x==17 && y==15) begin rgb <= 3'b101; end
else if(x==18 && y==15) begin rgb <= 3'b101; end
else if(x==19 && y==15) begin rgb <= 3'b101; end
else if(x==20 && y==15) begin rgb <= 3'b101; end
else if(x==21 && y==15) begin rgb <= 3'b101; end
else if(x==22 && y==15) begin rgb <= 3'b101; end
else if(x==23 && y==15) begin rgb <= 3'b101; end
else if(x==25 && y==15) begin rgb <= 3'b101; end
else if(x==3 && y==16) begin rgb <= 3'b101; end
else if(x==4 && y==16) begin rgb <= 3'b101; end
else if(x==5 && y==16) begin rgb <= 3'b101; end
else if(x==6 && y==16) begin rgb <= 3'b101; end
else if(x==7 && y==16) begin rgb <= 3'b101; end
else if(x==8 && y==16) begin rgb <= 3'b101; end
else if(x==10 && y==16) begin rgb <= 3'b111; end
else if(x==12 && y==16) begin rgb <= 3'b111; end
else if(x==13 && y==16) begin rgb <= 3'b111; end
else if(x==14 && y==16) begin rgb <= 3'b111; end
else if(x==15 && y==16) begin rgb <= 3'b111; end
else if(x==16 && y==16) begin rgb <= 3'b101; end
else if(x==17 && y==16) begin rgb <= 3'b101; end
else if(x==18 && y==16) begin rgb <= 3'b101; end
else if(x==19 && y==16) begin rgb <= 3'b101; end
else if(x==20 && y==16) begin rgb <= 3'b101; end
else if(x==21 && y==16) begin rgb <= 3'b101; end
else if(x==22 && y==16) begin rgb <= 3'b101; end
else if(x==23 && y==16) begin rgb <= 3'b101; end
else if(x==25 && y==16) begin rgb <= 3'b101; end
else if(x==3 && y==17) begin rgb <= 3'b101; end
else if(x==4 && y==17) begin rgb <= 3'b101; end
else if(x==6 && y==17) begin rgb <= 3'b101; end
else if(x==7 && y==17) begin rgb <= 3'b111; end
else if(x==8 && y==17) begin rgb <= 3'b111; end
else if(x==9 && y==17) begin rgb <= 3'b111; end
else if(x==10 && y==17) begin rgb <= 3'b111; end
else if(x==11 && y==17) begin rgb <= 3'b111; end
else if(x==12 && y==17) begin rgb <= 3'b111; end
else if(x==13 && y==17) begin rgb <= 3'b111; end
else if(x==14 && y==17) begin rgb <= 3'b111; end
else if(x==15 && y==17) begin rgb <= 3'b111; end
else if(x==17 && y==17) begin rgb <= 3'b111; end
else if(x==18 && y==17) begin rgb <= 3'b101; end
else if(x==19 && y==17) begin rgb <= 3'b101; end
else if(x==20 && y==17) begin rgb <= 3'b101; end
else if(x==21 && y==17) begin rgb <= 3'b101; end
else if(x==22 && y==17) begin rgb <= 3'b101; end
else if(x==23 && y==17) begin rgb <= 3'b101; end
else if(x==26 && y==17) begin rgb <= 3'b101; end
else if(x==3 && y==18) begin rgb <= 3'b101; end
else if(x==4 && y==18) begin rgb <= 3'b101; end
else if(x==6 && y==18) begin rgb <= 3'b111; end
else if(x==7 && y==18) begin rgb <= 3'b111; end
else if(x==8 && y==18) begin rgb <= 3'b111; end
else if(x==9 && y==18) begin rgb <= 3'b111; end
else if(x==10 && y==18) begin rgb <= 3'b111; end
else if(x==11 && y==18) begin rgb <= 3'b111; end
else if(x==12 && y==18) begin rgb <= 3'b111; end
else if(x==13 && y==18) begin rgb <= 3'b111; end
else if(x==14 && y==18) begin rgb <= 3'b111; end
else if(x==15 && y==18) begin rgb <= 3'b111; end
else if(x==17 && y==18) begin rgb <= 3'b111; end
else if(x==18 && y==18) begin rgb <= 3'b111; end
else if(x==19 && y==18) begin rgb <= 3'b101; end
else if(x==20 && y==18) begin rgb <= 3'b101; end
else if(x==21 && y==18) begin rgb <= 3'b101; end
else if(x==22 && y==18) begin rgb <= 3'b101; end
else if(x==23 && y==18) begin rgb <= 3'b101; end
else if(x==26 && y==18) begin rgb <= 3'b101; end
else if(x==2 && y==19) begin rgb <= 3'b101; end
else if(x==6 && y==19) begin rgb <= 3'b111; end
else if(x==7 && y==19) begin rgb <= 3'b111; end
else if(x==8 && y==19) begin rgb <= 3'b111; end
else if(x==9 && y==19) begin rgb <= 3'b111; end
else if(x==10 && y==19) begin rgb <= 3'b111; end
else if(x==11 && y==19) begin rgb <= 3'b111; end
else if(x==12 && y==19) begin rgb <= 3'b111; end
else if(x==13 && y==19) begin rgb <= 3'b111; end
else if(x==17 && y==19) begin rgb <= 3'b111; end
else if(x==18 && y==19) begin rgb <= 3'b111; end
else if(x==19 && y==19) begin rgb <= 3'b111; end
else if(x==20 && y==19) begin rgb <= 3'b101; end
else if(x==21 && y==19) begin rgb <= 3'b101; end
else if(x==22 && y==19) begin rgb <= 3'b101; end
else if(x==23 && y==19) begin rgb <= 3'b101; end
else if(x==27 && y==19) begin rgb <= 3'b101; end
else if(x==2 && y==20) begin rgb <= 3'b101; end
else if(x==3 && y==20) begin rgb <= 3'b101; end
else if(x==4 && y==20) begin rgb <= 3'b111; end
else if(x==5 && y==20) begin rgb <= 3'b111; end
else if(x==6 && y==20) begin rgb <= 3'b111; end
else if(x==7 && y==20) begin rgb <= 3'b111; end
else if(x==8 && y==20) begin rgb <= 3'b111; end
else if(x==9 && y==20) begin rgb <= 3'b111; end
else if(x==10 && y==20) begin rgb <= 3'b111; end
else if(x==11 && y==20) begin rgb <= 3'b111; end
else if(x==12 && y==20) begin rgb <= 3'b111; end
else if(x==13 && y==20) begin rgb <= 3'b111; end
else if(x==14 && y==20) begin rgb <= 3'b111; end
else if(x==15 && y==20) begin rgb <= 3'b111; end
else if(x==16 && y==20) begin rgb <= 3'b111; end
else if(x==17 && y==20) begin rgb <= 3'b111; end
else if(x==18 && y==20) begin rgb <= 3'b111; end
else if(x==19 && y==20) begin rgb <= 3'b111; end
else if(x==20 && y==20) begin rgb <= 3'b111; end
else if(x==21 && y==20) begin rgb <= 3'b101; end
else if(x==22 && y==20) begin rgb <= 3'b101; end
else if(x==23 && y==20) begin rgb <= 3'b101; end
else if(x==27 && y==20) begin rgb <= 3'b101; end
else if(x==2 && y==21) begin rgb <= 3'b101; end
else if(x==3 && y==21) begin rgb <= 3'b101; end
else if(x==4 && y==21) begin rgb <= 3'b111; end
else if(x==5 && y==21) begin rgb <= 3'b111; end
else if(x==6 && y==21) begin rgb <= 3'b111; end
else if(x==7 && y==21) begin rgb <= 3'b111; end
else if(x==8 && y==21) begin rgb <= 3'b111; end
else if(x==9 && y==21) begin rgb <= 3'b111; end
else if(x==10 && y==21) begin rgb <= 3'b111; end
else if(x==11 && y==21) begin rgb <= 3'b111; end
else if(x==12 && y==21) begin rgb <= 3'b111; end
else if(x==13 && y==21) begin rgb <= 3'b111; end
else if(x==14 && y==21) begin rgb <= 3'b111; end
else if(x==15 && y==21) begin rgb <= 3'b111; end
else if(x==16 && y==21) begin rgb <= 3'b111; end
else if(x==17 && y==21) begin rgb <= 3'b111; end
else if(x==18 && y==21) begin rgb <= 3'b111; end
else if(x==19 && y==21) begin rgb <= 3'b111; end
else if(x==20 && y==21) begin rgb <= 3'b111; end
else if(x==21 && y==21) begin rgb <= 3'b101; end
else if(x==22 && y==21) begin rgb <= 3'b101; end
else if(x==23 && y==21) begin rgb <= 3'b101; end
else if(x==27 && y==21) begin rgb <= 3'b101; end
else if(x==2 && y==22) begin rgb <= 3'b101; end
else if(x==3 && y==22) begin rgb <= 3'b101; end
else if(x==4 && y==22) begin rgb <= 3'b111; end
else if(x==5 && y==22) begin rgb <= 3'b111; end
else if(x==6 && y==22) begin rgb <= 3'b111; end
else if(x==7 && y==22) begin rgb <= 3'b111; end
else if(x==8 && y==22) begin rgb <= 3'b111; end
else if(x==9 && y==22) begin rgb <= 3'b111; end
else if(x==10 && y==22) begin rgb <= 3'b111; end
else if(x==11 && y==22) begin rgb <= 3'b111; end
else if(x==12 && y==22) begin rgb <= 3'b111; end
else if(x==13 && y==22) begin rgb <= 3'b111; end
else if(x==14 && y==22) begin rgb <= 3'b111; end
else if(x==15 && y==22) begin rgb <= 3'b111; end
else if(x==16 && y==22) begin rgb <= 3'b111; end
else if(x==17 && y==22) begin rgb <= 3'b111; end
else if(x==18 && y==22) begin rgb <= 3'b111; end
else if(x==19 && y==22) begin rgb <= 3'b111; end
else if(x==20 && y==22) begin rgb <= 3'b111; end
else if(x==21 && y==22) begin rgb <= 3'b101; end
else if(x==22 && y==22) begin rgb <= 3'b101; end
else if(x==23 && y==22) begin rgb <= 3'b101; end
else if(x==26 && y==22) begin rgb <= 3'b101; end
else if(x==2 && y==23) begin rgb <= 3'b101; end
else if(x==3 && y==23) begin rgb <= 3'b101; end
else if(x==4 && y==23) begin rgb <= 3'b111; end
else if(x==5 && y==23) begin rgb <= 3'b111; end
else if(x==6 && y==23) begin rgb <= 3'b111; end
else if(x==7 && y==23) begin rgb <= 3'b111; end
else if(x==8 && y==23) begin rgb <= 3'b111; end
else if(x==9 && y==23) begin rgb <= 3'b111; end
else if(x==10 && y==23) begin rgb <= 3'b111; end
else if(x==11 && y==23) begin rgb <= 3'b111; end
else if(x==12 && y==23) begin rgb <= 3'b111; end
else if(x==13 && y==23) begin rgb <= 3'b111; end
else if(x==14 && y==23) begin rgb <= 3'b111; end
else if(x==15 && y==23) begin rgb <= 3'b111; end
else if(x==16 && y==23) begin rgb <= 3'b111; end
else if(x==17 && y==23) begin rgb <= 3'b111; end
else if(x==18 && y==23) begin rgb <= 3'b111; end
else if(x==19 && y==23) begin rgb <= 3'b111; end
else if(x==20 && y==23) begin rgb <= 3'b111; end
else if(x==21 && y==23) begin rgb <= 3'b101; end
else if(x==22 && y==23) begin rgb <= 3'b101; end
else if(x==23 && y==23) begin rgb <= 3'b101; end
else if(x==26 && y==23) begin rgb <= 3'b101; end
else if(x==2 && y==24) begin rgb <= 3'b101; end
else if(x==3 && y==24) begin rgb <= 3'b101; end
else if(x==4 && y==24) begin rgb <= 3'b101; end
else if(x==5 && y==24) begin rgb <= 3'b111; end
else if(x==6 && y==24) begin rgb <= 3'b111; end
else if(x==7 && y==24) begin rgb <= 3'b111; end
else if(x==8 && y==24) begin rgb <= 3'b111; end
else if(x==9 && y==24) begin rgb <= 3'b111; end
else if(x==10 && y==24) begin rgb <= 3'b111; end
else if(x==11 && y==24) begin rgb <= 3'b111; end
else if(x==12 && y==24) begin rgb <= 3'b111; end
else if(x==13 && y==24) begin rgb <= 3'b111; end
else if(x==14 && y==24) begin rgb <= 3'b111; end
else if(x==15 && y==24) begin rgb <= 3'b111; end
else if(x==16 && y==24) begin rgb <= 3'b111; end
else if(x==17 && y==24) begin rgb <= 3'b111; end
else if(x==18 && y==24) begin rgb <= 3'b111; end
else if(x==19 && y==24) begin rgb <= 3'b111; end
else if(x==20 && y==24) begin rgb <= 3'b101; end
else if(x==21 && y==24) begin rgb <= 3'b101; end
else if(x==22 && y==24) begin rgb <= 3'b101; end
else if(x==23 && y==24) begin rgb <= 3'b101; end
else if(x==24 && y==24) begin rgb <= 3'b101; end
else if(x==25 && y==24) begin rgb <= 3'b101; end
else if(x==2 && y==25) begin rgb <= 3'b101; end
else if(x==3 && y==25) begin rgb <= 3'b101; end
else if(x==4 && y==25) begin rgb <= 3'b101; end
else if(x==5 && y==25) begin rgb <= 3'b101; end
else if(x==6 && y==25) begin rgb <= 3'b111; end
else if(x==7 && y==25) begin rgb <= 3'b111; end
else if(x==8 && y==25) begin rgb <= 3'b111; end
else if(x==9 && y==25) begin rgb <= 3'b111; end
else if(x==10 && y==25) begin rgb <= 3'b111; end
else if(x==11 && y==25) begin rgb <= 3'b111; end
else if(x==12 && y==25) begin rgb <= 3'b111; end
else if(x==13 && y==25) begin rgb <= 3'b111; end
else if(x==14 && y==25) begin rgb <= 3'b111; end
else if(x==15 && y==25) begin rgb <= 3'b111; end
else if(x==16 && y==25) begin rgb <= 3'b111; end
else if(x==17 && y==25) begin rgb <= 3'b111; end
else if(x==18 && y==25) begin rgb <= 3'b111; end
else if(x==19 && y==25) begin rgb <= 3'b101; end
else if(x==20 && y==25) begin rgb <= 3'b101; end
else if(x==21 && y==25) begin rgb <= 3'b101; end
else if(x==22 && y==25) begin rgb <= 3'b101; end
else if(x==2 && y==26) begin rgb <= 3'b101; end
else if(x==3 && y==26) begin rgb <= 3'b101; end
else if(x==4 && y==26) begin rgb <= 3'b101; end
else if(x==5 && y==26) begin rgb <= 3'b101; end
else if(x==6 && y==26) begin rgb <= 3'b101; end
else if(x==7 && y==26) begin rgb <= 3'b111; end
else if(x==8 && y==26) begin rgb <= 3'b111; end
else if(x==9 && y==26) begin rgb <= 3'b111; end
else if(x==10 && y==26) begin rgb <= 3'b111; end
else if(x==11 && y==26) begin rgb <= 3'b111; end
else if(x==12 && y==26) begin rgb <= 3'b111; end
else if(x==13 && y==26) begin rgb <= 3'b111; end
else if(x==14 && y==26) begin rgb <= 3'b111; end
else if(x==15 && y==26) begin rgb <= 3'b111; end
else if(x==16 && y==26) begin rgb <= 3'b111; end
else if(x==17 && y==26) begin rgb <= 3'b111; end
else if(x==18 && y==26) begin rgb <= 3'b101; end
else if(x==19 && y==26) begin rgb <= 3'b101; end
else if(x==5 && y==27) begin rgb <= 3'b101; end
else if(x==6 && y==27) begin rgb <= 3'b101; end
else if(x==7 && y==27) begin rgb <= 3'b101; end
else if(x==8 && y==27) begin rgb <= 3'b101; end
else if(x==9 && y==27) begin rgb <= 3'b111; end
else if(x==10 && y==27) begin rgb <= 3'b111; end
else if(x==11 && y==27) begin rgb <= 3'b111; end
else if(x==12 && y==27) begin rgb <= 3'b111; end
else if(x==13 && y==27) begin rgb <= 3'b111; end
else if(x==14 && y==27) begin rgb <= 3'b111; end
else if(x==15 && y==27) begin rgb <= 3'b111; end
else if(x==16 && y==27) begin rgb <= 3'b101; end
else if(x==17 && y==27) begin rgb <= 3'b101; end
else if(x==7 && y==28) begin rgb <= 3'b101; end
else if(x==8 && y==28) begin rgb <= 3'b101; end
else if(x==9 && y==28) begin rgb <= 3'b101; end
else if(x==10 && y==28) begin rgb <= 3'b101; end
else if(x==11 && y==28) begin rgb <= 3'b101; end
else if(x==12 && y==28) begin rgb <= 3'b101; end
else if(x==13 && y==28) begin rgb <= 3'b101; end
else if(x==14 && y==28) begin rgb <= 3'b101; end
else if(x==15 && y==28) begin rgb <= 3'b101; end
else begin rgb <= 3'b000; end// Width: 30, Height: 30 From: C:/Users/ITPCC/OneDrive/Documents/CPE223/Gun/pink_beam.png
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen ([email protected]) ////
//// - Tadej Markovic ([email protected]) ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_sync_flops.v,v $
// Revision 1.1 2004/05/21 11:43:25 tadejm
// Added to synchronize RX input to Wishbone clock.
//
//
`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
// vim: ts=4 sw=4 noexpandtab
/*
* SPI bus slave
*
* Copyright (c) 2019 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`ifndef SPI_SLAVE_MOD_V_
`define SPI_SLAVE_MOD_V_
`include "sync_signal_mod.v"
module spi_slave #(
parameter WORDSIZE = 8, /* Size of SPI word. Can be anything from 1 to 32. */
parameter CPOL = 0, /* SPI clock polarity. Can be 0 or 1. */
parameter CPHA = 0, /* SPI clock phase. Can be 0 or 1. */
parameter MSB_FIRST = 1, /* MSB transmit first enable. Can be 0 or 1. */
) (
input clk, /* clock */
input mosi, /* SPI bus MOSI signal */
output miso, /* SPI bus MISO signal */
input sck, /* SPI bus clock signal */
input ss, /* SPI bus slave select signal */
output rx_irq, /* Receive interrupt */
output [WORDSIZE - 1 : 0] rx_data, /* Received data */
input [WORDSIZE - 1 : 0] tx_data, /* Transmit data */
);
/* Synchronized input signals. */
wire mosi_s;
wire sck_rising_s;
wire sck_falling_s;
wire ss_s;
sync_signal sync_mosi(.clk(clk), .in(mosi), .out(mosi_s));
sync_signal sync_sck(.clk(clk), .in(sck), .rising(sck_rising_s), .falling(sck_falling_s));
sync_signal sync_ss(.clk(clk), .in(ss), .out(ss_s));
/* SCK sample and setup edges. */
wire sck_sample_edge;
wire sck_setup_edge;
assign sck_sample_edge = (CPOL ^ CPHA) ? sck_falling_s : sck_rising_s;
assign sck_setup_edge = (CPOL ^ CPHA) ? sck_rising_s : sck_falling_s;
/* Output buffers. */
reg miso_r;
reg rx_irq_r;
reg [WORDSIZE - 1 : 0] rx_data_r;
assign miso = miso_r;
assign rx_irq = rx_irq_r;
assign rx_data = rx_data_r;
/* Receive and transmit shift registers. */
reg [WORDSIZE - 1 : 0] rx_shiftreg;
reg [WORDSIZE - 1 : 0] tx_shiftreg;
reg [5:0] bit_count;
initial begin
bit_count <= 0;
rx_shiftreg <= 0;
tx_shiftreg <= 0;
miso_r <= 0;
rx_irq_r <= 0;
rx_data_r <= 0;
end
always @(posedge clk) begin
/* Check if slave select is not active */
if (ss_s) begin
bit_count <= 0;
rx_shiftreg <= 0;
tx_shiftreg <= 0;
miso_r <= 0;
rx_irq_r <= 0;
/* Check if slave select is active */
end else begin
/* Check if we are at the start of a word. */
if (bit_count == 0) begin
if (CPHA) begin
/* Reload the TX shift register. */
tx_shiftreg <= tx_data;
miso_r <= 0;
end else begin
/* Reload the TX shift register and
* put the first bit onto the bus. */
if (MSB_FIRST) begin
tx_shiftreg <= tx_data << 1;
miso_r <= tx_data[WORDSIZE - 1];
end else begin
tx_shiftreg <= tx_data >> 1;
miso_r <= tx_data[0];
end
end
/* Check if we are at a setup edge of SCK. */
end else if (sck_setup_edge) begin
/* Put the next bit onto the bus. */
if (MSB_FIRST) begin
miso_r <= tx_shiftreg[WORDSIZE - 1];
tx_shiftreg <= tx_shiftreg << 1;
end else begin
miso_r <= tx_shiftreg[0];
tx_shiftreg <= tx_shiftreg >> 1;
end
end
/* Check if we are at a sample edge of SCK. */
if (sck_sample_edge && (bit_count < WORDSIZE)) begin
/* Get the next bit from the bus. */
if (MSB_FIRST) begin
rx_shiftreg <= rx_shiftreg << 1;
rx_shiftreg[0] <= mosi_s;
end else begin
rx_shiftreg <= rx_shiftreg >> 1;
rx_shiftreg[WORDSIZE - 1] <= mosi_s;
end
bit_count <= bit_count + 1;
end
/* If we received a full word, trigger the RX interrupt. */
if (bit_count >= WORDSIZE) begin
bit_count <= 0;
rx_data_r <= rx_shiftreg;
rx_irq_r <= 1;
end else begin
rx_irq_r <= 0;
end
end
end
endmodule
`endif /* SPI_SLAVE_MOD_V_ */
|
`timescale 1ns / 1ps
// Decodes the bit-pairs received by the rx_DS_SE module
// into N-chars and L-chars.
//
// At present, parity is ignored. However, it will eventually
// be covered by this module as well.
// The only way to recover from a parity error is through
// resetting the module.
module rx_DS_char_tb();
reg rxClk, rxReset, dv;
reg [1:0] d;
wire [7:0] q;
wire nchar, lchar;
wire parityError;
rx_DS_char charDecoder(
.rxClk(rxClk),
.rxReset(rxReset),
.d(d),
.dValid(dv),
.q(q),
.nchar(nchar),
.lchar(lchar),
.parityError(parityError)
);
always begin
#10; rxClk = ~rxClk;
end
task bitPair;
input [1:0] pair;
begin
{dv, d} <= {1'b1, pair};
#20;
{dv, d} <= {1'b0, pair};
#20;
end
endtask
task nch;
input oddp;
input [7:0] chr;
begin
bitPair({1'b0, oddp});
bitPair(chr[1:0]);
bitPair(chr[3:2]);
bitPair(chr[5:4]);
bitPair(chr[7:6]);
end
endtask
task lch;
input oddp;
input [1:0] chr;
begin
bitPair({1'b1, oddp});
bitPair(chr);
end
endtask
task null;
input oddp;
begin
lch(oddp, 2'b11);
lch(0, 0);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{rxClk, rxReset, dv, d} <= 0;
#10;
rxReset <= 1;
#20;
rxReset <= 0;
#20;
null(0);
null(0);
nch(1, 8'h41);
lch(0, 2);
null(1);
null(0);
nch(1, 8'h4F);
lch(1, 2);
lch(1, 3); // NULL character with parity error.
lch(1, 0); // This result in parityError being asserted.
null(1);
null(0);
nch(1, 8'h41);
nch(1, 8'h62);
nch(0, 8'h63);
nch(1, 8'h64);
lch(1, 2);
null(1);
null(0);
$display("@I Done.");
$stop;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_excpctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////
`include "sys.h"
`include "lsu.h"
module lsu_excpctl ( /*AUTOARG*/
// Outputs
so, lsu_exu_st_dtlb_perr_g, lsu_ffu_st_dtlb_perr_g,
lsu_defr_trp_taken_g, lsu_tlu_defr_trp_taken_g,
lsu_mmu_defr_trp_taken_g, lsu_st_dtlb_perr_g,
lsu_dmmu_sfsr_trp_wr, lsu_dsfsr_din_g, lsu_tlb_perr_ld_rq_kill_w,
lsu_spu_early_flush_g, lsu_local_early_flush_g,
lsu_tlu_early_flush_w, lsu_tlu_early_flush2_w, lsu_ttype_vld_m2,
lsu_ttype_vld_m2_bf1, lsu_ifu_flush_pipe_w, lsu_exu_flush_pipe_w,
lsu_mmu_flush_pipe_w, lsu_ffu_flush_pipe_w, lsu_tlu_wtchpt_trp_g,
lsu_tlu_dmmu_miss_g, lsu_tlu_misalign_addr_ldst_atm_m,
lsu_tlu_daccess_excptn_g, lsu_tlu_daccess_prot_g,
lsu_tlu_priv_action_g, lsu_ifu_tlb_data_su, lsu_ifu_tlb_data_ue,
lsu_ifu_tlb_tag_ue, lsu_tlu_ttype_m2, lsu_tlu_ttype_vld_m2,
stb_cam_sqsh_msk, stb_cam_hit_bf, stb_cam_hit_bf1,
tte_data_perror_unc, asi_tte_data_perror, asi_tte_tag_perror,
// Inputs
rclk, si, se, grst_l, arst_l, tlb_rd_tte_data_ebit,
tlb_rd_tte_data_pbit, tlb_rd_tte_data_nfobit,
tlb_rd_tte_data_wbit, tlb_cam_hit, tlb_pgnum_b39,
lsu_ldst_va_b39_m, lsu_sun4r_va_m_l, lsu_sun4r_pgsz_b2t0_e,
lsu_sun4v_pgsz_b2t0_e, tlu_early_flush_pipe_w, ifu_lsu_flush_w,
ifu_lsu_nceen, lsu_tlb_asi_data_perr_g, lsu_tlb_asi_tag_perr_g,
stb_state_vld0, stb_state_vld1, stb_state_vld2, stb_state_vld3,
ifu_tlu_thrid_e, tlu_lsu_priv_trap_m, tlu_lsu_pstate_priv,
st_inst_vld_e, ld_inst_vld_e, ifu_lsu_alt_space_e, lsu_ldst_va_m,
hpv_priv_m, hpstate_en_m, stb_cam_hit, dtlb_bypass_m,
lsu_alt_space_m, atomic_m, ldst_dbl_m, fp_ldst_m, lda_internal_m,
sta_internal_m, cam_real_m, data_rd_vld_g, tag_rd_vld_g,
ldst_sz_m, asi_internal_m, rd_only_ltlb_asi_e, wr_only_ltlb_asi_e,
dfill_tlb_asi_e, ifill_tlb_asi_e, nofault_asi_m, as_if_user_asi_m,
atomic_asi_m, phy_use_ec_asi_m, phy_byp_ec_asi_m, quad_asi_m,
binit_quad_asi_m, blk_asi_m, recognized_asi_m, strm_asi_m,
mmu_rd_only_asi_m, rd_only_asi_m, wr_only_asi_m, unimp_asi_m,
lsu_nonalt_nucl_access_m, va_wtchpt_cmp_en_m,
lsu_va_match_b47_b32_m, lsu_va_match_b31_b3_m,
va_wtchpt_msk_match_m, ifu_tlu_inst_vld_m,
exu_tlu_misalign_addr_jmpl_rtn_m, exu_tlu_va_oor_m,
tlu_dsfsr_flt_vld, tlu_lsu_pstate_cle, tlu_lsu_pstate_am,
lsu_excpctl_asi_state_m, lsu_tlu_nonalt_ldst_m,
lsu_squash_va_oor_m, lsu_tlu_xslating_ldst_m, lsu_tlu_ctxt_sel_m,
lsu_tlu_write_op_m, lsu_memref_m, lsu_flsh_inst_m,
tte_data_parity_error, tte_tag_parity_error
);
input rclk;
input si;
input se;
input grst_l;
input arst_l;
output so;
//=================================================================
// input from tlb
// input [`STLB_DATA_NFO:`STLB_DATA_W] tlb_rd_tte_data ; // tte data from tlb
input tlb_rd_tte_data_ebit;
input tlb_rd_tte_data_pbit;
input tlb_rd_tte_data_nfobit;
input tlb_rd_tte_data_wbit;
input tlb_cam_hit;
input tlb_pgnum_b39;
// input tlb_rd_tte_data_locked ; // lock bit from tte
//=================================================================
input lsu_ldst_va_b39_m ;
input lsu_sun4r_va_m_l ;
input [2:0] lsu_sun4r_pgsz_b2t0_e ;
input [2:0] lsu_sun4v_pgsz_b2t0_e ;
input tlu_early_flush_pipe_w;
input ifu_lsu_flush_w;
input [3:0] ifu_lsu_nceen ; // uncorrectible error enable
input lsu_tlb_asi_data_perr_g ;
input lsu_tlb_asi_tag_perr_g ;
input [7:0] stb_state_vld0 ; // valid bits - stb0
input [7:0] stb_state_vld1 ; // valid bits - stb1
input [7:0] stb_state_vld2 ; // valid bits - stb2
input [7:0] stb_state_vld3 ; // valid bits - stb3
input [1:0] ifu_tlu_thrid_e ; // thread-id.
input tlu_lsu_priv_trap_m ; // daccess-excp in tlu
output lsu_exu_st_dtlb_perr_g ;
output lsu_ffu_st_dtlb_perr_g ;
output lsu_defr_trp_taken_g ;
output lsu_tlu_defr_trp_taken_g ;
output lsu_mmu_defr_trp_taken_g ;
output [3:0] lsu_st_dtlb_perr_g ;
output [3:0] lsu_dmmu_sfsr_trp_wr; // sfsr wr based on trap.
output [23:0] lsu_dsfsr_din_g;
output lsu_tlb_perr_ld_rq_kill_w ;
output lsu_spu_early_flush_g;
output lsu_local_early_flush_g; //to lsu
// output lsu_dctl_early_flush_w;
output lsu_tlu_early_flush_w;
output lsu_tlu_early_flush2_w;
output lsu_ttype_vld_m2;
output lsu_ttype_vld_m2_bf1;
// output lsu_stbctl_flush_pipe_w ;
// output lsu_stbrwctl_flush_pipe_w ;
//output lsu_flush_pipe_w;
output lsu_ifu_flush_pipe_w;
output lsu_exu_flush_pipe_w;
output lsu_mmu_flush_pipe_w;
output lsu_ffu_flush_pipe_w;
output lsu_tlu_wtchpt_trp_g ; // watchpt trap has occurred.
output lsu_tlu_dmmu_miss_g;
output lsu_tlu_misalign_addr_ldst_atm_m ; // mem_addr unaligned
// output lsu_tlu_priv_violtn_g;
wire lsu_tlu_priv_violtn_g;
output lsu_tlu_daccess_excptn_g;
output lsu_tlu_daccess_prot_g;
output lsu_tlu_priv_action_g;
// output lsu_tlu_tte_ebit_g;
// output lsu_tlu_spec_access_epage_g;
// output lsu_tlu_uncache_atomic_g;
// output lsu_tlu_illegal_asi_action_g;
// output lsu_tlu_flt_ld_nfo_pg_g;
//output lsu_tlu_asi_rd_unc;
output lsu_ifu_tlb_data_su ; // specific to st ue
output lsu_ifu_tlb_data_ue ; // dtlb data asi rd parity error ; now ld ue
output lsu_ifu_tlb_tag_ue ; // dtlb tag asi rd parity error
output [8:0] lsu_tlu_ttype_m2;
output lsu_tlu_ttype_vld_m2;
output [7:0] stb_cam_sqsh_msk ; // squash spurious hits
output stb_cam_hit_bf; // buffered stb_cam_hit for qctl1.
output stb_cam_hit_bf1; // buffered stb_cam_hit for stb_rwctl, dctl.
input [3:0] tlu_lsu_pstate_priv ;
// input [3:0] tlu_lsu_hpv_priv;
// input [3:0] tlu_lsu_hpstate_en;
input st_inst_vld_e;
input ld_inst_vld_e;
input ifu_lsu_alt_space_e; // alternate space ld/st
//interface between lsu_dctldp
input [7:0] lsu_ldst_va_m;
//interface between lsu_excpctl and lsu_dctl
output tte_data_perror_unc;
//output tte_data_perror_corr;
output asi_tte_data_perror ;
output asi_tte_tag_perror ;
input hpv_priv_m;
input hpstate_en_m;
input stb_cam_hit ;
input dtlb_bypass_m;
input lsu_alt_space_m;
input atomic_m;
// input atomic_g;
input ldst_dbl_m;
input fp_ldst_m;
// input lsu_inst_vld_w;
input lda_internal_m;
input sta_internal_m;
input cam_real_m;
// input va_wtchpt_match;
input data_rd_vld_g;
input tag_rd_vld_g;
input [1:0] ldst_sz_m;
input asi_internal_m;
// input dfill_thread0;
// input dfill_thread1;
// input dfill_thread2;
// input dfill_thread3;
wire ld_inst_vld_unflushed;
wire st_inst_vld_unflushed;
// input flsh_inst_g;
// input unc_err_trap_g;
//asi decode
input rd_only_ltlb_asi_e;
input wr_only_ltlb_asi_e;
input dfill_tlb_asi_e;
input ifill_tlb_asi_e;
input nofault_asi_m;
input as_if_user_asi_m;
input atomic_asi_m;
input phy_use_ec_asi_m;
input phy_byp_ec_asi_m;
// input tlb_byp_asi_m;
input quad_asi_m;
input binit_quad_asi_m;
input blk_asi_m;
// input blk_cmt_asi_m;
input recognized_asi_m;
input strm_asi_m;
input mmu_rd_only_asi_m;
input rd_only_asi_m;
input wr_only_asi_m;
input unimp_asi_m;
input lsu_nonalt_nucl_access_m ;
input va_wtchpt_cmp_en_m; //from dctl
input lsu_va_match_b47_b32_m; //from qdp1
input lsu_va_match_b31_b3_m; //from qdp1
input va_wtchpt_msk_match_m; //from dctldp
input ifu_tlu_inst_vld_m ;
input exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr
input exu_tlu_va_oor_m; // ??? - to be used in sfsr
input [3:0] tlu_dsfsr_flt_vld;
input [3:0] tlu_lsu_pstate_cle ; // current little endian
input [3:0] tlu_lsu_pstate_am ; // address mask
input [7:0] lsu_excpctl_asi_state_m ; // ASI State + imm asi
input lsu_tlu_nonalt_ldst_m ; // non-alternate load or store // FORCE
input lsu_squash_va_oor_m ; // squash va_oor for mem-op. // FORCE
input lsu_tlu_xslating_ldst_m ;// xslating ldst,atomic etc // FORCE
input [2:0] lsu_tlu_ctxt_sel_m; // context selected:0-p,1-s,2-n // FORCE
input lsu_tlu_write_op_m; // FORCE
input lsu_memref_m ;
input lsu_flsh_inst_m ;
input tte_data_parity_error ;
input tte_tag_parity_error ;
wire other_flush_pipe_w ;
wire defr_trp_taken ;
wire defr_trp_taken_m, defr_trp_taken_byp, defr_trp_taken_m_din ;
wire tlb_tte_vld_m, tlb_tte_vld_g ;
wire priv_pg_usr_mode_m, priv_pg_usr_mode_g, priv_pg_usr_mode;
wire nfo_pg_nonnfo_asi_m, nfo_pg_nonnfo_asi_g, nfo_pg_nonnfo_asi;
wire spec_access_epage_m, spec_access_epage_g, spec_access_epage ;
wire nonwr_pg_st_access;
//=========================================================================================
// MISCELLANEOUS
//=========================================================================================
wire clk;
assign clk = rclk;
wire reset;
wire dbb_reset_l;
dffrl_async rstff(.din (grst_l),
.q (dbb_reset_l),
.clk (clk), .se(se), .si(), .so(),
.rst_l (arst_l));
assign reset = ~dbb_reset_l ;
bw_u1_buf_30x UZsize_stb_cam_hit_bf1 (.a(stb_cam_hit), .z(stb_cam_hit_bf1)); //to dctl, stb_rwctl
bw_u1_buf_30x UZsize_stb_cam_hit_bf (.a(stb_cam_hit), .z(stb_cam_hit_bf )); //to qctl1
wire ld_inst_vld_m;
wire st_inst_vld_m;
dff_s #(2) inst_vld_stgm (
.din ({ld_inst_vld_e, st_inst_vld_e}),
.q ({ld_inst_vld_m, st_inst_vld_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) inst_vld_stgg (
.din ({ld_inst_vld_m, st_inst_vld_m}),
.q ({ld_inst_vld_unflushed, st_inst_vld_unflushed}),
.clk (clk),
.se (se), .si (), .so ()
);
wire tlu_priv_trap_g ;
dff_s #(1) tprivtrp_g (
.din (tlu_lsu_priv_trap_m),
.q (tlu_priv_trap_g),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// Thread Staging
//=========================================================================================
wire [1:0] thrid_m, thrid_g ;
dff_s #(2) tid_stgm (
.din (ifu_tlu_thrid_e[1:0]),
.q (thrid_m[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire thread0_m, thread1_m, thread2_m, thread3_m;
assign thread0_m = ~thrid_m[1] & ~thrid_m[0] ;
assign thread1_m = ~thrid_m[1] & thrid_m[0] ;
assign thread2_m = thrid_m[1] & ~thrid_m[0] ;
assign thread3_m = thrid_m[1] & thrid_m[0] ;
wire thread0_g, thread1_g, thread2_g, thread3_g ;
dff_s #(4) tid_stgg (
.din ({thread0_m, thread1_m, thread2_m, thread3_m}),
.q ({thread0_g, thread1_g, thread2_g, thread3_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// INST_VLD_W GENERATION
//=========================================================================================
assign thrid_g[0] = thread1_g | thread3_g ;
assign thrid_g[1] = thread2_g | thread3_g ;
wire flush_w_inst_vld_m ;
wire lsu_inst_vld_w ;
wire lsu_flush_pipe_w;
assign flush_w_inst_vld_m =
ifu_tlu_inst_vld_m &
~(lsu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
dff_s stgw_ivld (
.din (flush_w_inst_vld_m),
.q (lsu_inst_vld_w),
.clk (clk),
.se (se), .si (), .so ()
);
//========================================================================
// Miscellaneous
//========================================================================
// Moved to excpctl from stb_rwctl as excpctl is closer to stb-cam.
mux4ds #(8) stbvld_mx (
.in0 (~stb_state_vld0[7:0]),
.in1 (~stb_state_vld1[7:0]),
.in2 (~stb_state_vld2[7:0]),
.in3 (~stb_state_vld3[7:0]),
.sel0 (thread0_g),
.sel1 (thread1_g),
.sel2 (thread2_g),
.sel3 (thread3_g),
.dout (stb_cam_sqsh_msk[7:0])
);
//========================================================================
// Exception Handling Begin
//========================================================================
//va watch point
wire va_match_g;
wire va_wtchpt_msk_match_g;
wire va_wtchpt_en_m ;
assign va_wtchpt_en_m =
va_wtchpt_cmp_en_m &
(((~asi_internal_m & recognized_asi_m) & lsu_alt_space_m) | ~lsu_alt_space_m) // Bug5226
& (ld_inst_vld_m | st_inst_vld_m) & //bug 3681
~(hpv_priv_m & hpstate_en_m) // ECO 4178
& ~cam_real_m ; // ECO 5470 (TO_2_0)
//bug6480
wire lsu_va_match_m;
wire pstate_am_m ;
assign lsu_va_match_m = ((lsu_va_match_b47_b32_m & lsu_va_match_b31_b3_m) & ~pstate_am_m) |
(lsu_va_match_b31_b3_m & pstate_am_m);
dff_s #(3) stgwtch_g (
.din ({va_wtchpt_en_m,
lsu_va_match_m,
va_wtchpt_msk_match_m}),
.q ({va_wtchpt_en_g,
va_match_g,
va_wtchpt_msk_match_g}),
.clk (clk),
.se (se), .si (), .so ()
);
// These signals will eventually generate exceptions.
wire va_wtchpt_match;
assign va_wtchpt_match =
va_match_g & va_wtchpt_msk_match_g & lsu_inst_vld_w & va_wtchpt_en_g;
assign lsu_tlu_wtchpt_trp_g = va_wtchpt_match ;
// tlb related exceptions/errors
wire tlb_daccess_excptn_e, tlb_daccess_excptn_m ;
wire tlb_daccess_excptn_e_d1;
wire tlb_illgl_pgsz_m ;
assign tlb_daccess_excptn_e =
((rd_only_ltlb_asi_e & st_inst_vld_e) |
(wr_only_ltlb_asi_e & ld_inst_vld_e)) & ifu_lsu_alt_space_e ;
dff_s #(1) tlbex_stgm (
.din ({tlb_daccess_excptn_e}),
.q ({tlb_daccess_excptn_e_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
assign tlb_daccess_excptn_m = tlb_daccess_excptn_e_d1 | tlb_illgl_pgsz_m;
wire pstate_priv_m;
//wire pstate_priv;
mux4ds #(1) pstate_priv_m_mux (
.in0 (tlu_lsu_pstate_priv[0]),
.in1 (tlu_lsu_pstate_priv[1]),
.in2 (tlu_lsu_pstate_priv[2]),
.in3 (tlu_lsu_pstate_priv[3]),
.sel0 (thread0_m),
.sel1 (thread1_m),
.sel2 (thread2_m),
.sel3 (thread3_m),
.dout (pstate_priv_m)
);
//dff #(1) priv_stgg (
// .din (pstate_priv_m),
// .q (pstate_priv),
// .clk (clk),
// .se (se), .si (), .so ()
// );
// privilege violation - priv page accessed in user mode
//timing
//assign priv_pg_usr_mode = // data access exception; TT=h30
// (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~(pstate_priv | hpv_priv) & tlb_rd_tte_data_pbit ;
//SC2 wire hpv_priv_m;
assign priv_pg_usr_mode_m = (ld_inst_vld_m | st_inst_vld_m) & ~(pstate_priv_m | hpv_priv_m);
dff_s #(1) priv_pg_usr_mode_stgg (
.din (priv_pg_usr_mode_m),
.q (priv_pg_usr_mode_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign priv_pg_usr_mode = priv_pg_usr_mode_g & tlb_rd_tte_data_pbit ;
// protection violation - store to a page that does not have write permission
//timing
//assign nonwr_pg_st_access = // data access protection; TT=h33
// st_inst_vld_unflushed &
// ~tlb_rd_tte_data_wbit & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
// //lsu_dtlb_bypass_g) ; // W=1 in bypass mode - In bypass mode this trap will never happen !!!
assign nonwr_pg_st_access = ~tlb_rd_tte_data_wbit & st_inst_vld_unflushed & tlb_tte_vld_g;
wire daccess_prot ;
assign daccess_prot = nonwr_pg_st_access ;
//((~lsu_dtlb_bypass_g & tlb_cam_hit_g) | (tlb_byp_asi_g & lsu_alt_space_g)) ;
// access to a page marked with the nfo with an asi other than nfo asi.
//timing
//assign nfo_pg_nonnfo_asi = // data access exception; TT=h30
// (ld_inst_vld_unflushed | st_inst_vld_unflushed) & // any access
// ((~nofault_asi_g & lsu_alt_space_g) | ~lsu_alt_space_g) // in alternate space or not
// & tlb_rd_tte_data_nfobit ;
assign nfo_pg_nonnfo_asi_m = (ld_inst_vld_m | st_inst_vld_m) &
((~nofault_asi_m & lsu_alt_space_m) | ~lsu_alt_space_m) ;
dff_s #(1) nfo_pg_nonnfo_asi_stgg (
.din (nfo_pg_nonnfo_asi_m),
.q (nfo_pg_nonnfo_asi_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign nfo_pg_nonnfo_asi = nfo_pg_nonnfo_asi_g & tlb_rd_tte_data_nfobit ;
// as_if_usr asi accesses priv page.
//timing
//assign as_if_usr_priv_pg = // data access exception; TT=h30
// (ld_inst_vld_unflushed | st_inst_vld_unflushed) & as_if_user_asi_g & lsu_alt_space_g &
// tlb_rd_tte_data_pbit ;
wire as_if_usr_priv_pg_m, as_if_usr_priv_pg_g, as_if_usr_priv_pg;
assign as_if_usr_priv_pg_m = (ld_inst_vld_m | st_inst_vld_m) & as_if_user_asi_m & lsu_alt_space_m;
dff_s #(1) as_if_usr_priv_pg_stgg (
.din (as_if_usr_priv_pg_m),
.q (as_if_usr_priv_pg_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign as_if_usr_priv_pg = as_if_usr_priv_pg_g & tlb_rd_tte_data_pbit ;
// non-cacheable address - iospace PA[39] = 1
// atomic access to non-cacheable space.
wire atm_access_w_nc, atomic_g;
dff_s #(1) atm_stgg (
.din (atomic_m),
.q (atomic_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign atm_access_w_nc = atomic_g & tlb_pgnum_b39 ; // io space
// atomic inst with unsupported asi.
//timing
//assign atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;
wire atm_access_unsup_asi_m, atm_access_unsup_asi;
assign atm_access_unsup_asi_m = atomic_m & ~atomic_asi_m & lsu_alt_space_m;
dff_s #(1) atm_access_unsup_asi_stgg (
.din (atm_access_unsup_asi_m),
.q (atm_access_unsup_asi),
.clk (clk),
.se (se), .si (), .so ()
);
//timing
//assign tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
wire dmmu_va_oor_m ;
assign tlb_tte_vld_m = ~dtlb_bypass_m & tlb_cam_hit &
~((unimp_asi_m | asi_internal_m | ~recognized_asi_m) &
lsu_alt_space_m) & // Bug 3541,5186
~dmmu_va_oor_m ; // Bug 5070
dff_s #(1) tlb_tte_vld_stgg (
.din (tlb_tte_vld_m),
.q (tlb_tte_vld_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire pg_with_ebit_m, pg_with_ebit_g, pg_with_ebit ;
//timing
//assign pg_with_ebit =
// (tlb_rd_tte_data_ebit & tlb_tte_vld_g) | // tte
// (lsu_dtlb_bypass_g & ~(phy_use_ec_asi_g & lsu_alt_space_g)) | // regular bypass
// (tlb_byp_asi_g & ~phy_use_ec_asi_g & lsu_alt_space_g) ; // phy_byp
assign pg_with_ebit_m =
(dtlb_bypass_m & ~(phy_use_ec_asi_m & lsu_alt_space_m) &
(lsu_ldst_va_b39_m & ~pstate_am_m)) |
// regular bypass // Bug 4296,5050 related.
(dtlb_bypass_m & (phy_byp_ec_asi_m & lsu_alt_space_m)) ; // phy_byp
dff_s #(1) pg_with_ebit_stgg (
.din (pg_with_ebit_m),
.q (pg_with_ebit_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign pg_with_ebit = (tlb_rd_tte_data_ebit & tlb_tte_vld_g) | // tte
pg_with_ebit_g;
//timing
//assign spec_access_epage =
// ((ld_inst_vld_unflushed & nofault_asi_g & lsu_alt_space_g) | // spec load
// flsh_inst_g) & // flush inst
// pg_with_ebit ; // page with side effects
//// tlb_rd_tte_data_ebit ; // page with side effects
assign spec_access_epage_m =
// Bug 5166
((ld_inst_vld_m & ~atomic_m) & nofault_asi_m & lsu_alt_space_m); // spec load
dff_s #(1) spec_access_epage_stgg (
.din (spec_access_epage_m),
.q (spec_access_epage_g),
.clk (clk),
.se (se), .si (), .so ()
);
// remove flsh_inst_g ??
//assign spec_access_epage = (spec_access_epage_g | flsh_inst_g) & pg_with_ebit;
assign spec_access_epage = (spec_access_epage_g) & pg_with_ebit;
wire quad_asi_non_ldstda_m;
// covers regular quad asi AND binit.
assign quad_asi_non_ldstda_m =
quad_asi_m & lsu_alt_space_m &
((~ldst_dbl_m & ld_inst_vld_m) | // only lddbl should use
(fp_ldst_m & (ld_inst_vld_m | st_inst_vld_m))) ; // float should not use
wire true_quad_non_ldda_m ;
// catches case where st or non-ldd uses asi
assign true_quad_non_ldda_m =
(quad_asi_m & ~binit_quad_asi_m) & lsu_alt_space_m &
((~ldst_dbl_m & ld_inst_vld_m) | st_inst_vld_m) ;
wire blk_asi_non_ldstdfa_m ;
assign blk_asi_non_ldstdfa_m = blk_asi_m & lsu_alt_space_m &
~(ldst_dbl_m & fp_ldst_m) & (ld_inst_vld_m | st_inst_vld_m) ;
// trap on illegal asi
wire illegal_asi_trap_m, illegal_asi_trap_g, illegal_asi_trap_m_d1 ;
assign illegal_asi_trap_m =
((ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m & ~recognized_asi_m) |
((ld_inst_vld_m | st_inst_vld_m) & asi_internal_m & fp_ldst_m & lsu_alt_space_m) | // Bug 4382
blk_asi_non_ldstdfa_m |
quad_asi_non_ldstda_m |
true_quad_non_ldda_m ;
dff_s #(1) illegal_asi_trap_stgg (
.din (illegal_asi_trap_m),
.q (illegal_asi_trap_m_d1),
.clk (clk),
.se (se), .si (), .so ()
);
//need lsu_inst_vld_w ??
// assign illegal_asi_trap_g = illegal_asi_trap_m_d1 & lsu_inst_vld_w;
assign illegal_asi_trap_g = illegal_asi_trap_m_d1;
wire wr_to_strm_sync_m ;
//timing
//assign wr_to_strm_sync =
// strm_asi & ((ldst_va_g[7:0] == 8'hA0) | (ldst_va_g[7:0] == 8'h68)) &
// st_inst_vld_unflushed & lsu_alt_space_g ;
assign wr_to_strm_sync_m = // Bug 5742
strm_asi_m & (lsu_ldst_va_m[7:0] == 8'hA0) & st_inst_vld_m & lsu_alt_space_m ;
/*dff #(1) wr_to_strm_sync_stgg (
.din (wr_to_strm_sync_m),
.q (wr_to_strm_sync),
.clk (clk),
.se (se), .si (), .so ()
);*/
// HPV Changes
// Push back into previous stage.
// qualification with hpv_priv and hpstate_en required to ensure hypervisor
// is not trying to access.
//SC2 wire hpv_priv_e;
//SC2 mux4ds #(1) hpv_priv_e_mux (
//SC2 .in0 (tlu_lsu_hpv_priv[0]),
//SC2 .in1 (tlu_lsu_hpv_priv[1]),
//SC2 .in2 (tlu_lsu_hpv_priv[2]),
//SC2 .in3 (tlu_lsu_hpv_priv[3]),
//SC2 .sel0 (thread0_e),
//SC2 .sel1 (thread1_e),
//SC2 .sel2 (thread2_e),
//SC2 .sel3 (thread3_e),
//SC2 .dout (hpv_priv_e)
//SC2);
//SC2 wire hpstate_en_e;
//SC2 mux4ds #(1) hpstate_en_e_mux (
//SC2 .in0 (tlu_lsu_hpstate_en[0]),
//SC2 .in1 (tlu_lsu_hpstate_en[1]),
//SC2 .in2 (tlu_lsu_hpstate_en[2]),
//SC2 .in3 (tlu_lsu_hpstate_en[3]),
//SC2 .sel0 (thread0_e),
//SC2 .sel1 (thread1_e),
//SC2 .sel2 (thread2_e),
//SC2 .sel3 (thread3_e),
//SC2 .dout (hpstate_en_e)
//SC2);
//SC2 wire hpstate_en_m;
//SC2 dff #(2) hpv_stgm (
//SC2 .din ({hpv_priv_e, hpstate_en_e}),
//SC2 .q ({hpv_priv_m, hpstate_en_m}),
//SC2 .clk (clk),
//SC2 .se (se), .si (), .so ()
//SC2 );
//SC2 wire hpv_priv, hpstate_en;
//SC2 dff #(2) hpv_stgg (
//SC2 .din ({hpv_priv_m, hpstate_en_m}),
//SC2 .q ({hpv_priv, hpstate_en}),
//SC2 .clk (clk),
//SC2 .se (se), .si (), .so ()
//SC2 );
/*assign priv_action = (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~lsu_asi_state[7] &
~pstate_priv & ~(hpv_priv & hpstate_en) & lsu_alt_space_g ;*/
// Generate a stage earlier
wire priv_action_m, priv_action;
assign priv_action_m = (ld_inst_vld_m | st_inst_vld_m) &
((~lsu_excpctl_asi_state_m[7] & lsu_alt_space_m) | // alt_space
lsu_nonalt_nucl_access_m) & // non-alt space - nucleus ctxt
~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) ;
/*assign priv_action_m = (ld_inst_vld_m | st_inst_vld_m) & ~lsu_excpctl_asi_state_m[7] &
~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) & lsu_alt_space_m ;*/
dff_s pact_stgg (
.din (priv_action_m),
.q (priv_action),
.clk (clk),
.se (se), .si (), .so ()
);
// Take data_access exception if supervisor uses hypervisor asi
wire hpv_asi_range_m;
wire spv_use_hpv_m ;
//timing
//assign hpv_asi_range =
// ~lsu_asi_state[7] & (
// (~lsu_asi_state[6] & lsu_asi_state[5] & lsu_asi_state[4]) | // 0x3?
// ( lsu_asi_state[6]));
assign hpv_asi_range_m =
~lsu_excpctl_asi_state_m[7] & (
(~lsu_excpctl_asi_state_m[6] & lsu_excpctl_asi_state_m[5] & lsu_excpctl_asi_state_m[4]) | // 0x3?
( lsu_excpctl_asi_state_m[6])); // 0x4?,5?,6?,7?
// Take data_access exception if supervisor uses hypervisor asi
assign spv_use_hpv_m = (ld_inst_vld_m | st_inst_vld_m) &
hpv_asi_range_m &
pstate_priv_m & ~hpv_priv_m & lsu_alt_space_m ;
// EARLY TRAPS
// memory address not aligned
wire qw_align_addr,blk_align_addr ;
wire hw_align_addr,wd_align_addr,dw_align_addr;
assign hw_align_addr = ~lsu_ldst_va_m[0] ; // half-word addr
assign wd_align_addr = ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // word addr
assign dw_align_addr = ~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // dw addr
assign qw_align_addr = ~lsu_ldst_va_m[3] & ~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // qw addr
assign blk_align_addr =
~lsu_ldst_va_m[5] & ~lsu_ldst_va_m[4] & ~lsu_ldst_va_m[3] &
~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // 64B aligned addr for block ld/st
wire hw_size,wd_size,dw_size;
//assign byte_size = ~ldst_sz_m[1] & ~ldst_sz_m[0] ; // byte size
assign hw_size = ~ldst_sz_m[1] & ldst_sz_m[0] ; // half-word size
assign wd_size = ldst_sz_m[1] & ~ldst_sz_m[0] ; // word size
assign dw_size = ldst_sz_m[1] & ldst_sz_m[0] ; // double-word size
wire mem_addr_not_align ;
assign mem_addr_not_align
= (((hw_size & ~hw_align_addr) | // half-word check
(wd_size & ~wd_align_addr) | // word check
(dw_size & ~dw_align_addr) | // double word check
//((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) | // quad word check
(blk_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & ~blk_align_addr)) & // 64B blk ld/st check
//(blk_asi_m & lsu_alt_space_m & blk_asi_m & ~blk_align_addr)) & // 64B blk ld/st check
(ld_inst_vld_m | st_inst_vld_m)) |
// check only for loads
(((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) & ld_inst_vld_m) ; // quad word check
// To be removed !! Now supported for both ld and st thru unimp_asi.
//wire blkst_cmt_daccess_excp_m ;
//assign blkst_cmt_daccess_excp_m =
// (blk_cmt_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & st_inst_vld_m) ;
wire stdf_maddr_not_align, lddf_maddr_not_align ;
assign stdf_maddr_not_align
= st_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr
& ~((blk_asi_m | quad_asi_m) & lsu_alt_space_m);
assign lddf_maddr_not_align
= ld_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr
& ~((blk_asi_m | quad_asi_m) & lsu_alt_space_m);
// internal asi access by ld/st other than ldxa/stxa/lddfa/stdfa.
wire asi_internal_non_xdw ;
assign asi_internal_non_xdw
= (st_inst_vld_m | ld_inst_vld_m) & lsu_alt_space_m & asi_internal_m &
~(dw_size & (~ldst_dbl_m | fp_ldst_m)) ; //bug4149;
// asi related
// rd-only mmu asi requiring va decode.
wire mmu_rd_only_asi_wva_m ;
assign mmu_rd_only_asi_wva_m =
((lsu_excpctl_asi_state_m[7:0]==8'h58) & (
(lsu_ldst_va_m[7:0] == 8'h00) | // dtag_target
(lsu_ldst_va_m[7:0] == 8'h20))) | // dsync_far
((lsu_excpctl_asi_state_m[7:0]==8'h50) &
(lsu_ldst_va_m[7:0] == 8'h00)) ; // itag_target
wire wr_to_rd_only_asi, rd_of_wr_only_asi, unimp_asi_used;
assign wr_to_rd_only_asi =
((mmu_rd_only_asi_wva_m |// mmu with non-unique asi
mmu_rd_only_asi_m | // mmu with unique asi
rd_only_asi_m) // non mmu
& st_inst_vld_m & lsu_alt_space_m) |
wr_to_strm_sync_m ; // Bug 5399
assign rd_of_wr_only_asi = wr_only_asi_m & ld_inst_vld_m & lsu_alt_space_m ;
assign unimp_asi_used = unimp_asi_m & (ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m ;
wire asi_related_trap_m ; // asi_related_trap_g;
assign asi_related_trap_m = wr_to_rd_only_asi | rd_of_wr_only_asi | unimp_asi_used | asi_internal_non_xdw ;
// Illegal page size for tlb fill
wire [2:0] pgszr_m,pgszv_m ;
dff_s #(6) pgsz_stgm (
.din ({lsu_sun4r_pgsz_b2t0_e[2:0],lsu_sun4v_pgsz_b2t0_e[2:0]}),
.q ({pgszr_m[2:0],pgszv_m[2:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [2:0] pgsz_m ;
assign pgsz_m[2:0] = lsu_sun4r_va_m_l ? pgszv_m[2:0] : pgszr_m[2:0] ;
wire illgl_pgsz_m ;
assign illgl_pgsz_m =
(~pgsz_m[2] & pgsz_m[1] & ~pgsz_m[0]) | // 010 ; 512K
( pgsz_m[2] & ~pgsz_m[1] & ~pgsz_m[0]) | // 100 ; 32M
( pgsz_m[2] & pgsz_m[1] & ~pgsz_m[0]) | // 110 ; 2G
( pgsz_m[2] & pgsz_m[1] & pgsz_m[0]) ; // 111 ; 16G
wire ifill_tlb_asi_m,dfill_tlb_asi_m ;
dff_s #(2) idfill_stgm (
.din ({ifill_tlb_asi_e,dfill_tlb_asi_e}),
.q ({ifill_tlb_asi_m,dfill_tlb_asi_m}),
.clk (clk),
.se (se), .si (), .so ()
);
assign tlb_illgl_pgsz_m =
(ifill_tlb_asi_m | dfill_tlb_asi_m) & st_inst_vld_m & lsu_alt_space_m & illgl_pgsz_m ;
wire [8:0] early_ttype_m,early_ttype_g ;
wire early_trap_vld_m, early_trap_vld_g ;
assign early_trap_vld_m =
stdf_maddr_not_align | lddf_maddr_not_align |
mem_addr_not_align ;
wire lsu_tlu_misalign_addr_ldst_atm_m ;
assign lsu_tlu_misalign_addr_ldst_atm_m = early_trap_vld_m ;
// mux select order must be maintained
assign early_ttype_m[8:0] =
stdf_maddr_not_align ? 9'h036 :
lddf_maddr_not_align ? 9'h035 :
mem_addr_not_align ? 9'h034 : 9'hxxx ;
dff_s #(10) etrp_stgg (
.din ({early_ttype_m[8:0],early_trap_vld_m}),
.q ({early_ttype_g[8:0],early_trap_vld_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire daccess_excptn_early_m, daccess_excptn_early_g ;
wire atm_access_w_nc_byp_m,atm_access_w_nc_byp_g ;
assign atm_access_w_nc_byp_m =
atomic_m & dtlb_bypass_m & (lsu_ldst_va_b39_m & ~pstate_am_m) ;
//Bug 5050
dff_s atmbyp_stgg (
.din (atm_access_w_nc_byp_m),
.q (atm_access_w_nc_byp_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign daccess_excptn_early_m =
asi_related_trap_m | tlb_daccess_excptn_m |
spv_use_hpv_m |
atm_access_w_nc_byp_m ; // Bug 4281.
dff_s #(1) dearly_stgg (
.din (daccess_excptn_early_m),
.q (daccess_excptn_early_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire daccess_excptn;
assign daccess_excptn =
(priv_pg_usr_mode | as_if_usr_priv_pg | nfo_pg_nonnfo_asi |
atm_access_w_nc ) & tlb_tte_vld_g |
illegal_asi_trap_g | daccess_excptn_early_g | atm_access_unsup_asi | //bug4622
spec_access_epage ;
wire [3:0] lsu_nceen_d1;
dff_s #(4) nceen_d1_ff (
.din (ifu_lsu_nceen[3:0]),
.q (lsu_nceen_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire nceen_pipe_g ;
assign nceen_pipe_g =
(thread0_g & lsu_nceen_d1[0]) | (thread1_g & lsu_nceen_d1[1]) |
(thread2_g & lsu_nceen_d1[2]) | (thread3_g & lsu_nceen_d1[3]) ;
// correctible dtlb data parity error on cam will cause dmmu miss.
// prefetch will rely on the ld_inst_vld/st_inst_vld not being asserted
// to prevent mmu_miss from being signalled if prefetch does not translate.
// Timing Change : Remove data perror from dmmu_miss ; to be treated as disrupting trap.
wire dmmu_miss_m, dmmu_miss_m_d1;
assign dmmu_miss_m =
~tlb_cam_hit & ~dtlb_bypass_m &
(ld_inst_vld_m | st_inst_vld_m) &
~(lda_internal_m | sta_internal_m | early_trap_vld_m) ;
dff_s #(1) dmmu_miss_stgg (
.din (dmmu_miss_m),
.q (dmmu_miss_m_d1),
.clk (clk),
.se (se), .si (), .so ()
);
//need lsu_inst_vld_w ??
wire dmmu_miss_g;
assign dmmu_miss_g = dmmu_miss_m_d1 & lsu_inst_vld_w;
wire [8:0] dmiss_type ;
wire cam_real_g;
dff_s #(1) cam_real_stgg (
.din (cam_real_m),
.q (cam_real_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign dmiss_type[8:0] = cam_real_g ? 9'h03f : 9'h068 ;
// two wtchpt matches
//assign lsu_tlu_ttype_m2[8:0] =
// early_trap_vld_g ? early_ttype_g[8:0] :
// priv_action ? 9'h037 :
// va_wtchpt_match ? 9'h062 :
// daccess_excptn ? 9'h030 :
// dmmu_miss_g ? dmiss_type[8:0] : // dmmu_miss
// daccess_error ? 9'h032 :
// daccess_prot ? 9'h06c :
// spubyp_trap_active_g ? {3'b000,spubyp_ttype[5:0]} : // should be no other tttype to compare to.
// 9'bx_xxxx_xxxx ;
wire early_trap_vld_sel, priv_action_sel, va_wtchpt_match_sel, daccess_excptn_sel, dmmu_miss_sel,
daccess_prot_sel ;
// Need to maintain this order in selects. Based on priority of traps
assign early_trap_vld_sel = early_trap_vld_g;
assign priv_action_sel = ~early_trap_vld_sel & priv_action;
assign va_wtchpt_match_sel = ~early_trap_vld_sel & ~priv_action_sel & va_wtchpt_match;
assign daccess_excptn_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
daccess_excptn;
assign dmmu_miss_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
~daccess_excptn_sel & dmmu_miss_g;
assign daccess_prot_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
~daccess_excptn_sel & ~dmmu_miss_sel & daccess_prot;
assign lsu_tlu_ttype_m2[8:0] =
({9{early_trap_vld_sel}} & early_ttype_g[8:0]) |
({9{priv_action_sel}} & 9'h037 ) |
({9{va_wtchpt_match_sel}} & 9'h062 ) |
({9{daccess_excptn_sel}} & 9'h030 ) |
({9{dmmu_miss_sel}} & dmiss_type[8:0] ) |
({9{daccess_prot_sel}} & 9'h06c ) ;
assign lsu_tlu_ttype_vld_m2 = dmmu_miss_g | daccess_excptn | daccess_prot |
priv_action | early_trap_vld_g |
va_wtchpt_match ;
assign lsu_ttype_vld_m2 = lsu_tlu_ttype_vld_m2 | defr_trp_taken ; //to stb_rwctl
assign lsu_ttype_vld_m2_bf1 = lsu_ttype_vld_m2; //to dctl, qctl1
wire squash_priority_g ; // Bug 4678
assign squash_priority_g = priv_action | early_trap_vld_g | va_wtchpt_match ;
assign lsu_tlu_dmmu_miss_g = dmmu_miss_g & ~squash_priority_g ;
assign lsu_tlu_priv_violtn_g = (priv_pg_usr_mode | as_if_usr_priv_pg) & tlb_tte_vld_g ;
wire dmmu_va_oor_g ;
assign lsu_tlu_daccess_excptn_g =
(daccess_excptn | dmmu_va_oor_g // Bug 5036
| tlu_priv_trap_g) & ~squash_priority_g ;
// prioritize daccess_excptn higher than daccess_prot. This may
// be a critical path which needs to be resolved -> qual. now
// in mmu.
//assign lsu_tlu_daccess_prot_g = daccess_prot ;
wire daccess_prot_g;
assign daccess_prot_g = daccess_prot &
~(tlu_priv_trap_g | daccess_excptn | squash_priority_g) ;
assign lsu_tlu_daccess_prot_g = daccess_prot & ~squash_priority_g ; // Bug 5336.
assign lsu_tlu_priv_action_g = priv_action ;
//assign lsu_tlu_tte_ebit_g = tlb_rd_tte_data_ebit & tlb_tte_vld_g ;
wire lsu_tlu_tte_ebit_g;
assign lsu_tlu_tte_ebit_g = pg_with_ebit ;
//assign lsu_tlu_spec_access_epage_g = spec_access_epage & tlb_tte_vld_g ; // page with side effects
wire lsu_tlu_spec_access_epage_g ;
assign lsu_tlu_spec_access_epage_g = spec_access_epage ; // page with side effects
wire lsu_tlu_uncache_atomic_g;
assign lsu_tlu_uncache_atomic_g =
(atm_access_w_nc & tlb_tte_vld_g) |
(atm_access_w_nc_byp_g) ;
// Define illegal asi actions
// see sfsr description - excludes cases where 02 and 04 are set for ftype !!!
wire lsu_tlu_flt_ld_nfo_pg_g;
assign lsu_tlu_flt_ld_nfo_pg_g = nfo_pg_nonnfo_asi & tlb_tte_vld_g ;
wire illgl_asi_action_pre_m,illgl_asi_action_pre_g ;
assign illgl_asi_action_pre_m = asi_related_trap_m | tlb_daccess_excptn_m | illegal_asi_trap_m | spv_use_hpv_m ; // bug 4181; //bug3660
dff_s illglasi_g (
.din (illgl_asi_action_pre_m),
.q (illgl_asi_action_pre_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire lsu_tlu_illegal_asi_action_g;
assign lsu_tlu_illegal_asi_action_g =
atm_access_unsup_asi | (illgl_asi_action_pre_g) & // Bug 4825
~(lsu_tlu_spec_access_epage_g | lsu_tlu_uncache_atomic_g) ;
//(illgl_asi_action_pre_g | (atm_access_unsup_asi)) &
//~(lsu_tlu_spec_access_epage_g | lsu_tlu_uncache_atomic_g) ;
//=========================================================================================
// Generate Flush Pipe
//=========================================================================================
assign other_flush_pipe_w =
tlu_early_flush_pipe_w | (lsu_tlu_ttype_vld_m2 & lsu_inst_vld_w) |
defr_trp_taken ; // deferred trap.
assign lsu_ifu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_exu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_mmu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_ffu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ;
//assign lsu_qctl1_flush_pipe_w = lsu_flush_pipe_w ;
//assign lsu_stbctl_flush_pipe_w = lsu_flush_pipe_w ;
//assign lsu_stbrwctl_flush_pipe_w = lsu_flush_pipe_w ;
//=========================================================================================
// Early Traps to SPU
//=========================================================================================
// detect st to ma/strm sync - data-access exception.
//wire st_to_sync_dexcp_m ;
// qual with alt_space not required - spu will do it.
//assign st_to_sync_dexcp_m = // Bug 5704
//strm_asi_m & ((lsu_ldst_va_m[7:0] == 8'ha0) | (lsu_ldst_va_m[7:0] == 8'h68)) & st_inst_vld_m ;
wire early_flush_m ;
assign early_flush_m =
(atomic_m & lsu_alt_space_m) | // Bug 4650 - alt-space atomics should flush.
priv_action_m |
early_trap_vld_m | // mem-addr-not-aligned.
illegal_asi_trap_m | // for fp non use of internal asi.
//st_to_sync_dexcp_m | // Bug 5742
//wr_to_strm_sync_m | // Bug 5890 - redundant - make room.
defr_trp_taken_m_din | // Bug 5890
daccess_excptn_early_m ;
/*asi_related_trap_m | // Bug 2592
spv_use_hpv_m |
wr_to_strm_sync_m;*/
dff_s eflushspu_g (
.din (early_flush_m),
.q (lsu_spu_early_flush_g),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s eflushspu2_g (
.din (early_flush_m),
.q (lsu_local_early_flush_g),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s eflushtlu_g (
.din (early_flush_m),
.q (lsu_tlu_early_flush_w),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s eflushtlu2_g (
.din (early_flush_m),
.q (lsu_tlu_early_flush2_w),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// Parity Error Checking
//=========================================================================================
// DTLB Parity Errors.
// ASI read of Tag/Data :
// - uncorrectible error
// - logging occurs on read.
// - precise trap is taken when ldxa completes if nceen set.
// - if not set then ldxa is allowed to complete.
// CAM Read of Tag/Data :
// - correctible if locked bit not set.
// - takes disrupting trap later.
// - uncorrectible if locked bit set.
// - both are treated as precise traps.
// - if errors not enabled, then load completes as if hit in L1.
// ** TLB error will cause a trap which will preclude concurrent dcache,dtag **
// ** parity errors. **
// cam related tte data parity error - error assumed correctible if locked
// bit is not set. Will cause a dmmu_miss for correction.
// qualify with cam_hit ??
wire tte_data_perror_unc ;
assign lsu_tlb_perr_ld_rq_kill_w =
//tte_data_perror_corr | (tte_data_perror_unc & nceen_pipe_g) ;
(tte_data_perror_unc & nceen_pipe_g) ;
// correctible dtlb errors no longer supported.
/*assign tte_data_perror_corr =
tte_data_parity_error & ~tlb_rd_tte_data_locked & tlb_tte_vld_g &
(ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w ;*/
// caused for both locked and unlocked entries.
assign tte_data_perror_unc =
//tte_data_parity_error & tlb_rd_tte_data_locked & tlb_tte_vld_g &
tte_data_parity_error & tlb_tte_vld_g &
(ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w &
~lsu_flush_pipe_w ;
// Asi rd parity error detection
wire asi_tte_data_perror,asi_tte_tag_perror ;
assign asi_tte_data_perror =
tte_data_parity_error & data_rd_vld_g ;
// For data tte read, both tag and data arrays are read.
// Parity error on asi read of tag should not be reported.
assign asi_tte_tag_perror =
tte_tag_parity_error & tag_rd_vld_g & ~data_rd_vld_g ;
wire st_dtlb_perror ;
assign st_dtlb_perror = tte_data_parity_error & tlb_tte_vld_g &
st_inst_vld_unflushed & lsu_inst_vld_w ;
// ~lsu_flush_pipe_w ;
wire cancel_err_flush ;
assign cancel_err_flush = // Bug 5165
((priv_pg_usr_mode | nfo_pg_nonnfo_asi |
atm_access_w_nc) & tlb_tte_vld_g) | // bug6052/eco6620
spec_access_epage |
nonwr_pg_st_access ;
// Bug 6877
wire squash_err ;
assign squash_err =
// assume always higher priority. BE - share common terms elsewhere.
tlu_early_flush_pipe_w | defr_trp_taken | ifu_lsu_flush_w |
// isolate to daccess_excptn/daccess_prot as per Bug 5165.
(lsu_tlu_ttype_vld_m2 & ~(daccess_excptn_sel | daccess_prot_sel)) |
((daccess_excptn_sel | daccess_prot_sel) & ~cancel_err_flush) ;
wire tlb_data_su_g ;
assign tlb_data_su_g = st_dtlb_perror & ~atomic_g &
~squash_err ;
//~(lsu_flush_pipe_w & ~cancel_err_flush) ; // Bug 6877
wire ld_dtlb_perror ;
assign ld_dtlb_perror = tte_data_parity_error & tlb_tte_vld_g &
ld_inst_vld_unflushed & lsu_inst_vld_w &
~squash_err ;
wire tlb_data_ue_g ;
assign tlb_data_ue_g =
ld_dtlb_perror | // synchronous to pipe - xslate ; ue is for ld now.
lsu_tlb_asi_data_perr_g ; // asychronous to pipe - asi rd
/* Simplify for Bug 5888.
wire st_noatom_dtlb_perr ; // atomics not represented.
assign st_noatom_dtlb_perr = st_dtlb_perror & ~lsu_flush_pipe_w & ~atomic_g ;
wire st_noatom_dtlb_perr_en ;
assign st_noatom_dtlb_perr_en = st_noatom_dtlb_perr & nceen_pipe_g ; */
wire st_noatom_dtlb_perr_en ;
wire st_dtlb_perr_en ;
assign st_noatom_dtlb_perr_en = st_dtlb_perr_en & ~atomic_g ;
// rm corr err. reporting
dff_s #(3) terr_stgd1 (
.din ({tlb_data_su_g,tlb_data_ue_g,lsu_tlb_asi_tag_perr_g}),
//.din ({st_noatom_dtlb_perr,tlb_data_ue_g,lsu_tlb_asi_tag_perr_g}),
.q ({lsu_ifu_tlb_data_su,lsu_ifu_tlb_data_ue,lsu_ifu_tlb_tag_ue}),
.clk (clk),
.se (se), .si (), .so ()
);
// If st dtlb parity error detected, then need to invalidate st in stb.
// Considered unrecoverable for the thread itself.
assign st_dtlb_perr_en = st_dtlb_perror & ~lsu_flush_pipe_w & nceen_pipe_g ;
// Kill will happen for atomics also.
//assign lsu_exu_st_dtlb_perr_g = st_dtlb_perr_en ;
assign lsu_exu_st_dtlb_perr_g = st_noatom_dtlb_perr_en ; // Bug 5888
assign lsu_ffu_st_dtlb_perr_g = st_noatom_dtlb_perr_en ; // Bug 5910/ECO 6529
assign lsu_st_dtlb_perr_g[0] = st_dtlb_perr_en & thread0_g ;
assign lsu_st_dtlb_perr_g[1] = st_dtlb_perr_en & thread1_g ;
assign lsu_st_dtlb_perr_g[2] = st_dtlb_perr_en & thread2_g ;
assign lsu_st_dtlb_perr_g[3] = st_dtlb_perr_en & thread3_g ;
//==========================================================================
// DEFERRED TRAP DUE TO STORE
//==========================================================================
// Cases :
// defr_trp_m=1,ifu_flush_w=0.
// - defr_trp is generated.
// - next inst will not take redundant deferred trap as
// its inst_vld will be annulled by trap flush.
// defr_trp_m=1,ifu_flush_w=1.
// - defr_trp is generated. TLU annuls.
// - Other units see redundant defr_trp flush ORed with ifu_flush_w.
// - next inst will not take redundant deferred trap as
// its inst_vld will be annulled by ifu_flush_w .
// Log Deferred trap. Take on next available inst from thread.
// Inst vld must be qualified with flush.
wire st_defr_trp_en0,st_defr_trp_en1,st_defr_trp_en2,st_defr_trp_en3 ;
wire st_defr_trp0,st_defr_trp1,st_defr_trp2,st_defr_trp3 ;
assign st_defr_trp_en0 = st_noatom_dtlb_perr_en & thread0_g ;
assign st_defr_trp_en1 = st_noatom_dtlb_perr_en & thread1_g ;
assign st_defr_trp_en2 = st_noatom_dtlb_perr_en & thread2_g ;
assign st_defr_trp_en3 = st_noatom_dtlb_perr_en & thread3_g ;
wire stpend_rst0_m,stpend_rst1_m,stpend_rst2_m,stpend_rst3_m;
wire stpend_rst0_w,stpend_rst1_w,stpend_rst2_w,stpend_rst3_w;
wire stpend_rst0,stpend_rst1,stpend_rst2,stpend_rst3;
assign stpend_rst0_m = reset |
((st_defr_trp0 | st_defr_trp_en0) & thread0_m & flush_w_inst_vld_m);
assign stpend_rst1_m = reset |
((st_defr_trp1 | st_defr_trp_en1) & thread1_m & flush_w_inst_vld_m);
assign stpend_rst2_m = reset |
((st_defr_trp2 | st_defr_trp_en2) & thread2_m & flush_w_inst_vld_m);
assign stpend_rst3_m = reset |
((st_defr_trp3 | st_defr_trp_en3) & thread3_m & flush_w_inst_vld_m);
// Postphone reset by a cycle - 4916
dff_s #(4) stpend_d1 (
.din ({stpend_rst3_m,stpend_rst2_m,stpend_rst1_m,stpend_rst0_m}),
.q ({stpend_rst3_w,stpend_rst2_w,stpend_rst1_w,stpend_rst0_w}),
.clk (clk),
.se (se), .si (), .so ()
);
// Prevent reset if inst is flushed by ifu.
assign stpend_rst3 = stpend_rst3_w & ~ifu_lsu_flush_w ;
assign stpend_rst2 = stpend_rst2_w & ~ifu_lsu_flush_w ;
assign stpend_rst1 = stpend_rst1_w & ~ifu_lsu_flush_w ;
assign stpend_rst0 = stpend_rst0_w & ~ifu_lsu_flush_w ;
dffre_s #(1) deftrp_t0 (
.din (st_defr_trp_en0),
.q (st_defr_trp0),
.rst (stpend_rst0),
.en (st_defr_trp_en0),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(1) deftrp_t1 (
.din (st_defr_trp_en1),
.q (st_defr_trp1),
.rst (stpend_rst1),
.en (st_defr_trp_en1),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(1) deftrp_t2 (
.din (st_defr_trp_en2),
.q (st_defr_trp2),
.rst (stpend_rst2),
.en (st_defr_trp_en2),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(1) deftrp_t3 (
.din (st_defr_trp_en3),
.q (st_defr_trp3),
.rst (stpend_rst3),
.en (st_defr_trp_en3),
.clk (clk),
.se (se), .si (), .so ()
);
// Deferred trap can be taken on any instruction.
// Selection is based on next thread available.
//instruction n+2, and the following...
assign defr_trp_taken_m =
//ifu_tlu_inst_vld_m & (
flush_w_inst_vld_m & ( // <= rely of flush by defr-trp to clear
// pended defr-trp
(st_defr_trp0 & thread0_m) |
(st_defr_trp1 & thread1_m) |
(st_defr_trp2 & thread2_m) |
(st_defr_trp3 & thread3_m)) ;
assign defr_trp_taken_byp =
//ifu_tlu_inst_vld_m & (
flush_w_inst_vld_m & (
(st_defr_trp_en0 & thread0_m) |
(st_defr_trp_en1 & thread1_m) |
(st_defr_trp_en2 & thread2_m) |
(st_defr_trp_en3 & thread3_m) );
assign defr_trp_taken_m_din = defr_trp_taken_m | defr_trp_taken_byp;
dff_s #(1) defr_trp_taken_stgg (
.din (defr_trp_taken_m_din),
.q (defr_trp_taken),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_defr_trp_taken_g = defr_trp_taken ;
assign lsu_tlu_defr_trp_taken_g = defr_trp_taken ;
assign lsu_mmu_defr_trp_taken_g = defr_trp_taken ;
//==========================================================================
// DSFSR/SFAR WR
//==========================================================================
wire [3:0] pstate_cle,pstate_am ;
// flop'n use to prevent timing path.
dff_s #(8) cle_stg (
.din ({tlu_lsu_pstate_cle[3:0],tlu_lsu_pstate_am[3:0]}),
.q ({pstate_cle[3:0],pstate_am[3:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
wire pstate_cle_m ;
assign pstate_cle_m =
(thread0_m & pstate_cle[0]) |
(thread1_m & pstate_cle[1]) |
(thread2_m & pstate_cle[2]) |
(thread3_m & pstate_cle[3]);
wire [3:0] dsfsr_asi_sel_m ;
wire prim_asi_sel ;
assign prim_asi_sel =
exu_tlu_misalign_addr_jmpl_rtn_m | (lsu_tlu_nonalt_ldst_m & ~lsu_nonalt_nucl_access_m) ;
assign dsfsr_asi_sel_m[0] = // ASI_PRIMARY
prim_asi_sel & ~pstate_cle_m;
// Does asi_primary_little make sense for jmpl/return ?
assign dsfsr_asi_sel_m[1] = // ASI_PRIMARY_LITTLE
prim_asi_sel & pstate_cle_m;
assign dsfsr_asi_sel_m[2] = // ASI_NUCLEUS
lsu_nonalt_nucl_access_m & ~pstate_cle_m;
assign dsfsr_asi_sel_m[3] = // ASI_NUCLEUS_LITTLE
lsu_nonalt_nucl_access_m & pstate_cle_m;
/*assign dsfsr_asi_sel_m[4] = // assigned asi
~(exu_tlu_misalign_addr_jmpl_rtn_m | lsu_tlu_nonalt_ldst_m);*/
wire [7:0] asi_state_g ;
// flop'n use to prevent timing path.
dff_s #(8) asistate_stgg (
.din (lsu_excpctl_asi_state_m[7:0]),
.q (asi_state_g[7:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire [7:0] dsfsr_asi_g ;
wire [3:0] dsfsr_asi_sel_g ;
/*assign dsfsr_asi_g[7:0] =(dsfsr_asi_sel_g[0] ? 8'h80 : 8'h00) |
(dsfsr_asi_sel_g[1] ? 8'h88 : 8'h00) |
(dsfsr_asi_sel_g[2] ? asi_state_g[7:0] : 8'h00);*/
// Bug 4212 - spec problem
assign dsfsr_asi_g[7:0] =(dsfsr_asi_sel_g[0] ? 8'h80 :
(dsfsr_asi_sel_g[1] ? 8'h88 :
(dsfsr_asi_sel_g[2] ? 8'h04 :
(dsfsr_asi_sel_g[3] ? 8'h0C : asi_state_g[7:0]))));
assign pstate_am_m =
(thread0_m & pstate_am[0]) |
(thread1_m & pstate_am[1]) |
(thread2_m & pstate_am[2]) |
(thread3_m & pstate_am[3]);
assign dmmu_va_oor_m = exu_tlu_va_oor_m & ~pstate_am_m & lsu_memref_m & ~lsu_squash_va_oor_m;
wire [3:0] dsfsr_flt_vld;
dff_s #(4) fltvld_stgd1 (
.din (tlu_dsfsr_flt_vld[3:0]),
.q (dsfsr_flt_vld[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire dsfsr_flt_vld_m ;
assign dsfsr_flt_vld_m =
(thread0_m & dsfsr_flt_vld[0]) |
(thread1_m & dsfsr_flt_vld[1]) |
(thread2_m & dsfsr_flt_vld[2]) |
(thread3_m & dsfsr_flt_vld[3]);
wire ldst_xslate_g,flsh_inst_g,dsfsr_flt_vld_g,dsfsr_wr_op_g ;
wire misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g ;
wire [2:0] dsfsr_ctxt_sel ;
// flop flt_vld and use
dff_s #(14) dsfsr_stgg (
.din ({dsfsr_asi_sel_m[3:0],dmmu_va_oor_m,// memref_m,
lsu_tlu_xslating_ldst_m,lsu_flsh_inst_m,lsu_tlu_ctxt_sel_m[2:0],
dsfsr_flt_vld_m,lsu_tlu_write_op_m,exu_tlu_misalign_addr_jmpl_rtn_m,
lsu_tlu_misalign_addr_ldst_atm_m}),
.q ({dsfsr_asi_sel_g[3:0],dmmu_va_oor_g,ldst_xslate_g,// memref_g,
flsh_inst_g,dsfsr_ctxt_sel[2:0],dsfsr_flt_vld_g, dsfsr_wr_op_g,
misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g}),
.clk (clk),
.se (se), .si (), .so ()
);
// To be set only for data_access_exception traps - only one can be
// reported at any time.
wire [6:0] dsfsr_ftype_g ;
assign dsfsr_ftype_g[6] = 1'b0;
assign dsfsr_ftype_g[5] = dmmu_va_oor_g | lsu_tlu_wtchpt_trp_g;
assign dsfsr_ftype_g[4] = lsu_tlu_flt_ld_nfo_pg_g;
assign dsfsr_ftype_g[3] = lsu_tlu_illegal_asi_action_g
| tlu_priv_trap_g ; // Bug 4799
//assign dsfsr_ftype_g[3] = lsu_tlu_illegal_asi_action_g | tlu_mmu_sync_data_excp_g;
assign dsfsr_ftype_g[2] = (lsu_tlu_uncache_atomic_g & ~atm_access_unsup_asi);
assign dsfsr_ftype_g[1] = lsu_tlu_spec_access_epage_g;
assign dsfsr_ftype_g[0] = lsu_tlu_priv_violtn_g;
wire dsfsr_side_effect_g ;
assign dsfsr_side_effect_g = lsu_tlu_tte_ebit_g & (ldst_xslate_g | flsh_inst_g);
// Fault Type based on Priority Encoding of Traps
wire [6:0] dsfsr_pe_ftype_g ;
wire dsfsr_ftype_zero ;
// Is this needed ? Doesn't it default to zero ?
assign dsfsr_pe_ftype_g[6:0] = dsfsr_ftype_zero ? 7'h00 : dsfsr_ftype_g[6:0];
// set to 11 when the access does not have a translating asi.
wire [1:0] dsfsr_ctxt_g ;
assign dsfsr_ctxt_g[1:0] =
dsfsr_ctxt_sel[0] ? 2'b00 :
dsfsr_ctxt_sel[1] ? 2'b01 :
dsfsr_ctxt_sel[2] ? 2'b10 : 2'b11;
assign lsu_dsfsr_din_g[23:0] =
{dsfsr_asi_g[7:0],
2'b0,
dsfsr_pe_ftype_g[6:0],
dsfsr_side_effect_g,
dsfsr_ctxt_g[1:0],
1'b0, // Bug 3323 - Arch change
//pstate_priv,
dsfsr_wr_op_g, // pipe
dsfsr_flt_vld_g,
1'b1};
// This is going to be a critical path !!!
// Assume that traps in front-end cause instructions to be no`oped
// further down the pipeline. Thus there is no need to qualify writes
// to dsfsr with writes to isfsr
wire dsfsr_trp_wr_g ;
wire dsfsr_trp_wr_pre_m,dsfsr_trp_wr_pre_g ;
assign dsfsr_trp_wr_pre_m =
spv_use_hpv_m | // Bug 3254 ; add new data-access-excp
// spec_access_epage_m | // Bug 3515
priv_action_m |
exu_tlu_misalign_addr_jmpl_rtn_m |
lsu_tlu_misalign_addr_ldst_atm_m ;
dff_s dsfsrtrg_stgg (
.din (dsfsr_trp_wr_pre_m),
.q (dsfsr_trp_wr_pre_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign dsfsr_trp_wr_g =
((lsu_tlu_priv_violtn_g |
lsu_tlu_spec_access_epage_g | // Bug 3515 - uncomment out.
lsu_tlu_uncache_atomic_g | lsu_tlu_illegal_asi_action_g |
lsu_tlu_flt_ld_nfo_pg_g | dmmu_va_oor_g) | // data access exceptions
daccess_prot | // daccess_excptn not excluded.
lsu_tlu_wtchpt_trp_g | // watchpoint trap
dsfsr_trp_wr_pre_g |
tlu_priv_trap_g // scratchpad/queue daccess;Bug 4799
) &
lsu_inst_vld_w & ~(ifu_lsu_flush_w | defr_trp_taken) ; // Bug 4444,5196
assign dsfsr_ftype_zero =
daccess_prot_g | lsu_tlu_priv_action_g | lsu_tlu_wtchpt_trp_g |
misalign_addr_jmpl_rtn_g | misalign_addr_ldst_atm_g;
// terms below can be made common. (grape)
assign lsu_dmmu_sfsr_trp_wr[0] = dsfsr_trp_wr_g & thread0_g;
assign lsu_dmmu_sfsr_trp_wr[1] = dsfsr_trp_wr_g & thread1_g;
assign lsu_dmmu_sfsr_trp_wr[2] = dsfsr_trp_wr_g & thread2_g;
assign lsu_dmmu_sfsr_trp_wr[3] = dsfsr_trp_wr_g & thread3_g;
//==========================================================================
// Exception Handling End
//==========================================================================
endmodule // lsu_dctl1
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// The DLP makes one page read requests from host clock domain. This block has
// to synchronize the requests, pass them on to the arbiter, and mask the
// push enables that come back.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module mc_dlp
#(parameter BYTES = 16)
(
input reset_n,
input mclock,
input hst_clock,
input dlp_req,
input [4:0] dlp_wcnt,
input [27:0] dlp_org,
input dlp_gnt,
input dlp_push,
output reg dlp_mc_done,
output reg dlp_arb_req,
output reg [4:0] dlp_arb_wcnt,
output reg [27:0] dlp_arb_addr,
output reg dlp_ready
);
reg [27:0] capt_org;
reg [4:0] capt_wcnt;
reg dlp_req_toggle;
reg req_sync_1, req_sync_2, req_sync_3;
reg dlp_gnt_toggle;
reg gnt_sync_1, gnt_sync_2, gnt_sync_3;
reg [1:0] request_count;
reg [4:0] dlp_count;
localparam DLP = 3'h1;
// Capture request and control the ready signal
always @ (posedge hst_clock or negedge reset_n) begin
if(!reset_n) begin
dlp_ready <= 1'b1;
dlp_req_toggle <= 1'b0;
gnt_sync_1 <= 1'b0;
gnt_sync_2 <= 1'b0;
gnt_sync_3 <= 1'b0;
end else begin
if(dlp_req==1'b1) begin
dlp_req_toggle <= ~dlp_req_toggle;
capt_org <= dlp_org;
capt_wcnt <= dlp_wcnt;
dlp_ready <= 1'b0;
end // if (dlp_req==1'b1)
// synchronize the gnt toggle from mclock domain
gnt_sync_1 <= dlp_gnt_toggle;
gnt_sync_2 <= gnt_sync_1;
gnt_sync_3 <= gnt_sync_2;
if(gnt_sync_2 ^ gnt_sync_3) dlp_ready <= 1'b1;
end // else: !if(!reset_n)
end // always @ (posedge hst_clock or negedge reset_n)
// Issue requests to the arbiter
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
dlp_arb_req <= 1'b0;
dlp_gnt_toggle <= 1'b0;
req_sync_1 <= 1'b0;
req_sync_2 <= 1'b0;
req_sync_3 <= 1'b0;
dlp_mc_done <= 1'b0;
dlp_arb_addr <= 28'b0;
dlp_arb_req <= 1'b0;
dlp_count <= 5'b0;
end else begin
req_sync_1 <= dlp_req_toggle;
req_sync_2 <= req_sync_1;
req_sync_3 <= req_sync_2;
if(req_sync_2 ^ req_sync_3) begin
dlp_arb_addr <= capt_org;
dlp_arb_req <= 1'b1;
dlp_arb_wcnt <= capt_wcnt;
end // if (req_sync_2==1'b1 && req_sync_3==1'b0)
if(dlp_gnt==1'b1) begin
dlp_arb_req <= 1'b0;
dlp_gnt_toggle <= ~dlp_gnt_toggle;
end // if (dlp_gnt==1'b1)
if (dlp_push && ~dlp_mc_done)
dlp_count <= dlp_count + 5'h1;
else if(dlp_mc_done)
dlp_count <= 5'h0;
if (dlp_push && ~dlp_mc_done) begin
if (BYTES == 4) dlp_mc_done <= &dlp_count; // FIXME.
else if (BYTES == 8) dlp_mc_done <= dlp_count[0]; // FIXME.
else dlp_mc_done <= (dlp_count == dlp_arb_wcnt);
end
else dlp_mc_done <= 1'b0;
end // else: !if(!reset_n)
end // always @ (posedge mclock or negedge reset_n)
endmodule
|
module drv_bus_req(
input clk_sys,
input ready,
input r,
input w,
input in,
input [0:7] a1,
input [0:15] a2,
input [0:15] a3,
input zw,
output reg zg,
input ans_any,
output dw,
output dr,
output din,
output dpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt
);
// registered data input/output
reg ir, iw, iin;
reg [0:7] ia1;
reg [0:15] ia2;
reg [0:15] ia3;
// request trigger
wire req = ready & (r | w | in);
localparam IDLE = 4'd0;
localparam REQ = 4'd1;
reg [0:0] state = IDLE;
always @ (posedge clk_sys) begin
case (state)
IDLE: begin
if (req) begin
ir <= r;
iw <= w;
iin <= in;
ia1 <= a1;
ia2 <= a2;
ia3 <= a3;
zg <= 1;
state <= REQ;
end
end
REQ: begin
if (zw & ans_any) begin
zg <= 0;
state <= IDLE;
end
end
endcase
end
wire zwzg = zw & zg;
assign dw = zwzg ? iw : 1'd0;
assign dr = zwzg ? ir : 1'd0;
assign din = zwzg ? iin : 1'd0;
assign dpn = zwzg ? ia1[3] : 1'd0;
assign dnb = zwzg ? ia1[4:7] : 4'd0;
assign dad = zwzg ? ia2 : 16'd0;
assign ddt = zwzg ? ia3 : 16'd0;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
// Polyphase filter bank for upsampling from 96000.0kHz to 192000.0kHz
// Depth: 16
module rom_firbank_96_192(
input wire clk,
input wire [3:0] addr,
output wire [23:0] data);
reg [23:0] data_ff;
assign data = data_ff;
always @(posedge clk) begin
case(addr)
0: data_ff <= 24'h16B4E1; // 1488097
1: data_ff <= 24'h050C70; // 330864
2: data_ff <= 24'hFD6D3E; // -168642
3: data_ff <= 24'hFEFCB7; // -66377
4: data_ff <= 24'h003573; // 13683
5: data_ff <= 24'h0013DD; // 5085
6: data_ff <= 24'hFFFF42; // -190
7: data_ff <= 24'hFFFFF6; // -10
8: data_ff <= 24'h1C8992; // 1870226
9: data_ff <= 24'h0DAAE0; // 895712
10: data_ff <= 24'hFF750F; // -35569
11: data_ff <= 24'hFDCF4A; // -143542
12: data_ff <= 24'hFFE0FC; // -7940
13: data_ff <= 24'h002F67; // 12135
14: data_ff <= 24'h00036F; // 879
15: data_ff <= 24'hFFFF93; // -109
default: data_ff <= 0;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__FAH_BEHAVIORAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O21AI_BEHAVIORAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_BEHAVIORAL_PP_V |
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: xgmii_mux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module xgmii_mux (
clock,
data0x,
data1x,
data2x,
data3x,
sel,
result);
input clock;
input [65:0] data0x;
input [65:0] data1x;
input [65:0] data2x;
input [65:0] data3x;
input [1:0] sel;
output [65:0] result;
wire [65:0] sub_wire0;
wire [65:0] sub_wire5 = data3x[65:0];
wire [65:0] sub_wire4 = data2x[65:0];
wire [65:0] sub_wire3 = data1x[65:0];
wire [65:0] result = sub_wire0[65:0];
wire [65:0] sub_wire1 = data0x[65:0];
wire [263:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
lpm_mux LPM_MUX_component (
.clock (clock),
.data (sub_wire2),
.sel (sel),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_pipeline = 1,
LPM_MUX_component.lpm_size = 4,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 66,
LPM_MUX_component.lpm_widths = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "66"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data0x 0 0 66 0 INPUT NODEFVAL "data0x[65..0]"
// Retrieval info: USED_PORT: data1x 0 0 66 0 INPUT NODEFVAL "data1x[65..0]"
// Retrieval info: USED_PORT: data2x 0 0 66 0 INPUT NODEFVAL "data2x[65..0]"
// Retrieval info: USED_PORT: data3x 0 0 66 0 INPUT NODEFVAL "data3x[65..0]"
// Retrieval info: USED_PORT: result 0 0 66 0 OUTPUT NODEFVAL "result[65..0]"
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 66 0 data0x 0 0 66 0
// Retrieval info: CONNECT: @data 0 0 66 66 data1x 0 0 66 0
// Retrieval info: CONNECT: @data 0 0 66 132 data2x 0 0 66 0
// Retrieval info: CONNECT: @data 0 0 66 198 data3x 0 0 66 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: CONNECT: result 0 0 66 0 @result 0 0 66 0
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_mux.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_mux_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1N_BEHAVIORAL_V
`define SKY130_FD_SC_LP__ISO1N_BEHAVIORAL_V
/**
* iso1n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1N_BEHAVIORAL_V |
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import PrimInt63 FloatClass.
(** * Definition of the interface for primitive floating-point arithmetic
This interface provides processor operators for the Binary64 format of the
IEEE 754-2008 standard. *)
(** ** Type definition for the co-domain of [compare] *)
Variant float_comparison : Set := FEq | FLt | FGt | FNotComparable.
Register float_comparison as kernel.ind_f_cmp.
Register float_class as kernel.ind_f_class.
(** ** The main type *)
(** [float]: primitive type for Binary64 floating-point numbers. *)
Primitive float := #float64_type.
(** ** Syntax support *)
Module Import PrimFloatNotationsInternalA.
Declare Scope float_scope.
Delimit Scope float_scope with float.
Bind Scope float_scope with float.
End PrimFloatNotationsInternalA.
Declare ML Module "float_syntax_plugin".
(** ** Floating-point operators *)
Primitive classify := #float64_classify.
Primitive abs := #float64_abs.
Primitive sqrt := #float64_sqrt.
Primitive opp := #float64_opp.
Primitive eqb := #float64_eq.
Primitive ltb := #float64_lt.
Primitive leb := #float64_le.
Primitive compare := #float64_compare.
Primitive mul := #float64_mul.
Primitive add := #float64_add.
Primitive sub := #float64_sub.
Primitive div := #float64_div.
Module Import PrimFloatNotationsInternalB.
Notation "- x" := (opp x) : float_scope.
Notation "x =? y" := (eqb x y) (at level 70, no associativity) : float_scope.
Notation "x <? y" := (ltb x y) (at level 70, no associativity) : float_scope.
Notation "x <=? y" := (leb x y) (at level 70, no associativity) : float_scope.
Notation "x ?= y" := (compare x y) (at level 70, no associativity) : float_scope.
Notation "x * y" := (mul x y) : float_scope.
Notation "x + y" := (add x y) : float_scope.
Notation "x - y" := (sub x y) : float_scope.
Notation "x / y" := (div x y) : float_scope.
End PrimFloatNotationsInternalB.
(** ** Conversions *)
(** [of_uint63]: convert a primitive unsigned integer into a float value.
The value is rounded if need be. *)
Primitive of_uint63 := #float64_of_uint63.
(** Specification of [normfr_mantissa]:
- If the input is a float value with an absolute value inside $[0.5, 1.)$#[0.5, 1.)#;
- Then return its mantissa as a primitive integer.
The mantissa will be a 53-bit integer with its most significant bit set to 1;
- Else return zero.
The sign bit is always ignored. *)
Primitive normfr_mantissa := #float64_normfr_mantissa.
(** ** Exponent manipulation functions *)
(** [frshiftexp]: convert a float to fractional part in $[0.5, 1.)$#[0.5, 1.)#
and integer part. *)
Primitive frshiftexp := #float64_frshiftexp.
(** [ldshiftexp]: multiply a float by an integral power of 2. *)
Primitive ldshiftexp := #float64_ldshiftexp.
(** ** Predecesor/Successor functions *)
(** [next_up]: return the next float towards positive infinity. *)
Primitive next_up := #float64_next_up.
(** [next_down]: return the next float towards negative infinity. *)
Primitive next_down := #float64_next_down.
(** ** Special values (needed for pretty-printing) *)
Definition infinity := Eval compute in div (of_uint63 1) (of_uint63 0).
Definition neg_infinity := Eval compute in opp infinity.
Definition nan := Eval compute in div (of_uint63 0) (of_uint63 0).
Register infinity as num.float.infinity.
Register neg_infinity as num.float.neg_infinity.
Register nan as num.float.nan.
(** ** Other special values *)
Definition one := Eval compute in (of_uint63 1).
Definition zero := Eval compute in (of_uint63 0).
Definition neg_zero := Eval compute in (-zero)%float.
Definition two := Eval compute in (of_uint63 2).
(** ** Predicates and helper functions *)
Definition is_nan f := negb (f =? f)%float.
Definition is_zero f := (f =? zero)%float. (* note: 0 =? -0 with floats *)
Definition is_infinity f := (abs f =? infinity)%float.
Definition is_finite (x : float) := negb (is_nan x || is_infinity x).
(** [get_sign]: return [true] for [-] sign, [false] for [+] sign. *)
Definition get_sign f :=
let f := if is_zero f then (one / f)%float else f in
(f <? zero)%float.
Module Export PrimFloatNotations.
Local Open Scope float_scope.
#[deprecated(since="8.13",note="use infix <? instead")]
Notation "x < y" := (x <? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix <=? instead")]
Notation "x <= y" := (x <=? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix =? instead")]
Notation "x == y" := (x =? y) (at level 70, no associativity) : float_scope.
Export PrimFloatNotationsInternalA.
Export PrimFloatNotationsInternalB.
End PrimFloatNotations.
#[deprecated(since="8.14",note="Use of_uint63 instead.")]
Notation of_int63 := of_uint63 (only parsing).
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`include "main_pll.v"
//`include "main_pll_2x.v"
`include "sha-256-functions.v"
`include "sha256_transform.v"
`include "serial.v" // replaces virtual_wire
`include "raw7seg.v"
`timescale 1ns/1ps
module fpgaminer_top (osc_clk, RxD, TxD, anode, segment, disp_switch);
// The LOOP_LOG2 parameter determines how unrolled the SHA-256
// calculations are. For example, a setting of 1 will completely
// unroll the calculations, resulting in 128 rounds and a large, fast
// design.
//
// A setting of 2 will result in 64 rounds, with half the size and
// half the speed. 3 will be 32 rounds, with 1/4th the size and speed.
// And so on.
//
// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
parameter LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
parameter LOOP_LOG2 = 5;
`endif
// No need to adjust these parameters
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
// The nonce will always be larger at the time we discover a valid
// hash. This is its offset from the nonce that gave rise to the valid
// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
// 66 respectively).
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
input osc_clk;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (.CLKIN_IN(osc_clk), .CLK0_OUT(hash_clk));
// main_pll pll_blk (.CLKIN_IN(osc_clk), .CLK2X_OUT(hash_clk));
`else
assign hash_clk = osc_clk;
`endif
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
input RxD;
serial_receive serrx (.clk(hash_clk), .RxD(RxD), .midstate(midstate_vw), .data2(data2_vw));
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
reg serial_send;
wire serial_busy;
output TxD;
serial_transmit sertx (.clk(hash_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
`ifndef SIM
wire reset;
assign reset = 1'b0;
`else
reg reset = 1'b0; // NOTE: Reset is not currently used in the actual FPGA; for simulation only.
`endif
assign cnt_next = reset ? 6'd0 : (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next =
reset ? 32'd0 :
feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
if (!serial_busy) serial_send <= 1;
end // if (is_golden_ticket)
else
serial_send <= 0;
`ifdef SIM
if (!feedback_d1)
$display ("nonce: %8x\nhash2: %64x\n", nonce, hash2);
`endif
end
// die debuggenlichten
input disp_switch;
output [7:0] segment;
output [3:0] anode;
wire [7:0] segment_data;
// inverted signals, so 1111.. to turn it off
assign segment = disp_switch? segment_data : {8{1'b1}};
// raw7seg disp(.clk(hash_clk), .segment(segment_data), .anode(anode), .word({midstate_vw[15:0], data2_vw[15:0]}));
raw7seg disp(.clk(hash_clk), .segment(segment_data), .anode(anode), .word(golden_nonce));
endmodule
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