text
stringlengths 938
1.05M
|
|---|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_128x128a.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_128x128a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrempty,
wrusedw);
input aclr;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [127:0] q;
output rdempty;
output [6:0] rdusedw;
output wrempty;
output [6:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [127:0] sub_wire1;
wire sub_wire2;
wire [6:0] sub_wire3;
wire [6:0] sub_wire4;
wire wrempty = sub_wire0;
wire [127:0] q = sub_wire1[127:0];
wire rdempty = sub_wire2;
wire [6:0] wrusedw = sub_wire3[6:0];
wire [6:0] rdusedw = sub_wire4[6:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrempty (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdusedw (sub_wire4),
.rdfull (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 128,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "128"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "128"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL "rdusedw[6..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL "wrusedw[6..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x128a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x128a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x128a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x128a.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x128a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x128a_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_SYMBOL_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
//Date : Thu May 19 21:55:14 2016
//Host : YINGCAIDONG1779 running 64-bit Service Pack 1 (build 7601)
//Command : generate_target system.bd
//Design : system
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module m00_couplers_imp_1TEAG88
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wid,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [0:0]M_AXI_arid;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [0:0]M_AXI_awid;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [0:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input [0:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output [0:0]M_AXI_wid;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [0:0]S_AXI_arid;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [0:0]S_AXI_awid;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [0:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output [0:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_m00_couplers_ARADDR;
wire [1:0]auto_pc_to_m00_couplers_ARBURST;
wire [3:0]auto_pc_to_m00_couplers_ARCACHE;
wire [0:0]auto_pc_to_m00_couplers_ARID;
wire [3:0]auto_pc_to_m00_couplers_ARLEN;
wire [1:0]auto_pc_to_m00_couplers_ARLOCK;
wire [2:0]auto_pc_to_m00_couplers_ARPROT;
wire [3:0]auto_pc_to_m00_couplers_ARQOS;
wire auto_pc_to_m00_couplers_ARREADY;
wire [2:0]auto_pc_to_m00_couplers_ARSIZE;
wire auto_pc_to_m00_couplers_ARVALID;
wire [31:0]auto_pc_to_m00_couplers_AWADDR;
wire [1:0]auto_pc_to_m00_couplers_AWBURST;
wire [3:0]auto_pc_to_m00_couplers_AWCACHE;
wire [0:0]auto_pc_to_m00_couplers_AWID;
wire [3:0]auto_pc_to_m00_couplers_AWLEN;
wire [1:0]auto_pc_to_m00_couplers_AWLOCK;
wire [2:0]auto_pc_to_m00_couplers_AWPROT;
wire [3:0]auto_pc_to_m00_couplers_AWQOS;
wire auto_pc_to_m00_couplers_AWREADY;
wire [2:0]auto_pc_to_m00_couplers_AWSIZE;
wire auto_pc_to_m00_couplers_AWVALID;
wire [0:0]auto_pc_to_m00_couplers_BID;
wire auto_pc_to_m00_couplers_BREADY;
wire [1:0]auto_pc_to_m00_couplers_BRESP;
wire auto_pc_to_m00_couplers_BVALID;
wire [63:0]auto_pc_to_m00_couplers_RDATA;
wire [0:0]auto_pc_to_m00_couplers_RID;
wire auto_pc_to_m00_couplers_RLAST;
wire auto_pc_to_m00_couplers_RREADY;
wire [1:0]auto_pc_to_m00_couplers_RRESP;
wire auto_pc_to_m00_couplers_RVALID;
wire [63:0]auto_pc_to_m00_couplers_WDATA;
wire [0:0]auto_pc_to_m00_couplers_WID;
wire auto_pc_to_m00_couplers_WLAST;
wire auto_pc_to_m00_couplers_WREADY;
wire [7:0]auto_pc_to_m00_couplers_WSTRB;
wire auto_pc_to_m00_couplers_WVALID;
wire [31:0]m00_couplers_to_auto_pc_ARADDR;
wire [1:0]m00_couplers_to_auto_pc_ARBURST;
wire [3:0]m00_couplers_to_auto_pc_ARCACHE;
wire [0:0]m00_couplers_to_auto_pc_ARID;
wire [7:0]m00_couplers_to_auto_pc_ARLEN;
wire [0:0]m00_couplers_to_auto_pc_ARLOCK;
wire [2:0]m00_couplers_to_auto_pc_ARPROT;
wire [3:0]m00_couplers_to_auto_pc_ARQOS;
wire m00_couplers_to_auto_pc_ARREADY;
wire [3:0]m00_couplers_to_auto_pc_ARREGION;
wire [2:0]m00_couplers_to_auto_pc_ARSIZE;
wire m00_couplers_to_auto_pc_ARVALID;
wire [31:0]m00_couplers_to_auto_pc_AWADDR;
wire [1:0]m00_couplers_to_auto_pc_AWBURST;
wire [3:0]m00_couplers_to_auto_pc_AWCACHE;
wire [0:0]m00_couplers_to_auto_pc_AWID;
wire [7:0]m00_couplers_to_auto_pc_AWLEN;
wire [0:0]m00_couplers_to_auto_pc_AWLOCK;
wire [2:0]m00_couplers_to_auto_pc_AWPROT;
wire [3:0]m00_couplers_to_auto_pc_AWQOS;
wire m00_couplers_to_auto_pc_AWREADY;
wire [3:0]m00_couplers_to_auto_pc_AWREGION;
wire [2:0]m00_couplers_to_auto_pc_AWSIZE;
wire m00_couplers_to_auto_pc_AWVALID;
wire [0:0]m00_couplers_to_auto_pc_BID;
wire m00_couplers_to_auto_pc_BREADY;
wire [1:0]m00_couplers_to_auto_pc_BRESP;
wire m00_couplers_to_auto_pc_BVALID;
wire [63:0]m00_couplers_to_auto_pc_RDATA;
wire [0:0]m00_couplers_to_auto_pc_RID;
wire m00_couplers_to_auto_pc_RLAST;
wire m00_couplers_to_auto_pc_RREADY;
wire [1:0]m00_couplers_to_auto_pc_RRESP;
wire m00_couplers_to_auto_pc_RVALID;
wire [63:0]m00_couplers_to_auto_pc_WDATA;
wire m00_couplers_to_auto_pc_WLAST;
wire m00_couplers_to_auto_pc_WREADY;
wire [7:0]m00_couplers_to_auto_pc_WSTRB;
wire m00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m00_couplers_ARCACHE;
assign M_AXI_arid[0] = auto_pc_to_m00_couplers_ARID;
assign M_AXI_arlen[3:0] = auto_pc_to_m00_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m00_couplers_AWCACHE;
assign M_AXI_awid[0] = auto_pc_to_m00_couplers_AWID;
assign M_AXI_awlen[3:0] = auto_pc_to_m00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_pc_to_m00_couplers_WDATA;
assign M_AXI_wid[0] = auto_pc_to_m00_couplers_WID;
assign M_AXI_wlast = auto_pc_to_m00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_pc_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = m00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[0] = m00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = m00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[63:0] = m00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[0] = m00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = m00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m00_couplers_BID = M_AXI_bid[0];
assign auto_pc_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_pc_to_m00_couplers_RID = M_AXI_rid[0];
assign auto_pc_to_m00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m00_couplers_to_auto_pc_ARID = S_AXI_arid[0];
assign m00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m00_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m00_couplers_to_auto_pc_AWID = S_AXI_awid[0];
assign m00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m00_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m00_couplers_to_auto_pc_WDATA = S_AXI_wdata[63:0];
assign m00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[7:0];
assign m00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
system_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_m00_couplers_ARID),
.m_axi_arlen(auto_pc_to_m00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_m00_couplers_AWID),
.m_axi_awlen(auto_pc_to_m00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_m00_couplers_BID),
.m_axi_bready(auto_pc_to_m00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m00_couplers_RDATA),
.m_axi_rid(auto_pc_to_m00_couplers_RID),
.m_axi_rlast(auto_pc_to_m00_couplers_RLAST),
.m_axi_rready(auto_pc_to_m00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m00_couplers_WDATA),
.m_axi_wid(auto_pc_to_m00_couplers_WID),
.m_axi_wlast(auto_pc_to_m00_couplers_WLAST),
.m_axi_wready(auto_pc_to_m00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m00_couplers_WVALID),
.s_axi_araddr(m00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(m00_couplers_to_auto_pc_ARID),
.s_axi_arlen(m00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m00_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m00_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(m00_couplers_to_auto_pc_AWID),
.s_axi_awlen(m00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m00_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(m00_couplers_to_auto_pc_BID),
.s_axi_bready(m00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m00_couplers_to_auto_pc_RDATA),
.s_axi_rid(m00_couplers_to_auto_pc_RID),
.s_axi_rlast(m00_couplers_to_auto_pc_RLAST),
.s_axi_rready(m00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m00_couplers_to_auto_pc_WLAST),
.s_axi_wready(m00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m00_couplers_to_auto_pc_WVALID));
endmodule
module m00_couplers_imp_WKXF3L
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [4:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [4:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [4:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [4:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [4:0]m00_couplers_to_m00_couplers_ARADDR;
wire m00_couplers_to_m00_couplers_ARREADY;
wire m00_couplers_to_m00_couplers_ARVALID;
wire [4:0]m00_couplers_to_m00_couplers_AWADDR;
wire m00_couplers_to_m00_couplers_AWREADY;
wire m00_couplers_to_m00_couplers_AWVALID;
wire m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[4:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[4:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[4:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready;
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[4:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready;
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready;
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid;
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready;
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid;
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid;
endmodule
module m01_couplers_imp_1ORP4PS
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [9:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [9:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [9:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [9:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input S_AXI_wvalid;
wire [9:0]m01_couplers_to_m01_couplers_ARADDR;
wire m01_couplers_to_m01_couplers_ARREADY;
wire m01_couplers_to_m01_couplers_ARVALID;
wire [9:0]m01_couplers_to_m01_couplers_AWADDR;
wire m01_couplers_to_m01_couplers_AWREADY;
wire m01_couplers_to_m01_couplers_AWVALID;
wire m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire m01_couplers_to_m01_couplers_WREADY;
wire m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[9:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[9:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[9:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready;
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[9:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready;
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready;
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid;
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready;
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid;
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule
module m02_couplers_imp_1VD9O7M
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [4:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [4:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [4:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [4:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [4:0]m02_couplers_to_m02_couplers_ARADDR;
wire m02_couplers_to_m02_couplers_ARREADY;
wire m02_couplers_to_m02_couplers_ARVALID;
wire [4:0]m02_couplers_to_m02_couplers_AWADDR;
wire m02_couplers_to_m02_couplers_AWREADY;
wire m02_couplers_to_m02_couplers_AWVALID;
wire m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire m02_couplers_to_m02_couplers_WREADY;
wire [3:0]m02_couplers_to_m02_couplers_WSTRB;
wire m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[4:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[4:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m02_couplers_to_m02_couplers_WSTRB;
assign M_AXI_wvalid = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[4:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready;
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid;
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[4:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready;
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid;
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready;
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid;
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready;
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid;
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready;
assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid;
endmodule
module s00_couplers_imp_1P403ZT
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
wire GND_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_us_to_s00_couplers_ARADDR;
wire [1:0]auto_us_to_s00_couplers_ARBURST;
wire [3:0]auto_us_to_s00_couplers_ARCACHE;
wire [7:0]auto_us_to_s00_couplers_ARLEN;
wire [0:0]auto_us_to_s00_couplers_ARLOCK;
wire [2:0]auto_us_to_s00_couplers_ARPROT;
wire [3:0]auto_us_to_s00_couplers_ARQOS;
wire auto_us_to_s00_couplers_ARREADY;
wire [2:0]auto_us_to_s00_couplers_ARSIZE;
wire auto_us_to_s00_couplers_ARVALID;
wire [63:0]auto_us_to_s00_couplers_RDATA;
wire auto_us_to_s00_couplers_RLAST;
wire auto_us_to_s00_couplers_RREADY;
wire [1:0]auto_us_to_s00_couplers_RRESP;
wire auto_us_to_s00_couplers_RVALID;
wire [31:0]s00_couplers_to_auto_us_ARADDR;
wire [1:0]s00_couplers_to_auto_us_ARBURST;
wire [3:0]s00_couplers_to_auto_us_ARCACHE;
wire [7:0]s00_couplers_to_auto_us_ARLEN;
wire [2:0]s00_couplers_to_auto_us_ARPROT;
wire s00_couplers_to_auto_us_ARREADY;
wire [2:0]s00_couplers_to_auto_us_ARSIZE;
wire s00_couplers_to_auto_us_ARVALID;
wire [31:0]s00_couplers_to_auto_us_RDATA;
wire s00_couplers_to_auto_us_RLAST;
wire s00_couplers_to_auto_us_RREADY;
wire [1:0]s00_couplers_to_auto_us_RRESP;
wire s00_couplers_to_auto_us_RVALID;
assign M_AXI_araddr[31:0] = auto_us_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_us_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_us_to_s00_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_us_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_us_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_us_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_us_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_us_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_us_to_s00_couplers_ARVALID;
assign M_AXI_rready = auto_us_to_s00_couplers_RREADY;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_us_ARREADY;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_us_RDATA;
assign S_AXI_rlast = s00_couplers_to_auto_us_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_us_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_us_RVALID;
assign auto_us_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_us_to_s00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_us_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_us_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_us_to_s00_couplers_RVALID = M_AXI_rvalid;
assign s00_couplers_to_auto_us_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_us_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_us_RREADY = S_AXI_rready;
GND GND
(.G(GND_1));
system_auto_us_0 auto_us
(.m_axi_araddr(auto_us_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_us_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_us_to_s00_couplers_ARCACHE),
.m_axi_arlen(auto_us_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_us_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_us_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_us_to_s00_couplers_ARQOS),
.m_axi_arready(auto_us_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_us_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_us_to_s00_couplers_ARVALID),
.m_axi_rdata(auto_us_to_s00_couplers_RDATA),
.m_axi_rlast(auto_us_to_s00_couplers_RLAST),
.m_axi_rready(auto_us_to_s00_couplers_RREADY),
.m_axi_rresp(auto_us_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_us_to_s00_couplers_RVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(s00_couplers_to_auto_us_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_us_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_us_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(s00_couplers_to_auto_us_ARLEN),
.s_axi_arlock(GND_1),
.s_axi_arprot(s00_couplers_to_auto_us_ARPROT),
.s_axi_arqos({GND_1,GND_1,GND_1,GND_1}),
.s_axi_arready(s00_couplers_to_auto_us_ARREADY),
.s_axi_arregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_arsize(s00_couplers_to_auto_us_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_us_ARVALID),
.s_axi_rdata(s00_couplers_to_auto_us_RDATA),
.s_axi_rlast(s00_couplers_to_auto_us_RLAST),
.s_axi_rready(s00_couplers_to_auto_us_RREADY),
.s_axi_rresp(s00_couplers_to_auto_us_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_us_RVALID));
endmodule
module s00_couplers_imp_IK3G2O
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
system_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s01_couplers_imp_VQ497S
(M_ACLK,
M_ARESETN,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire GND_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_us_to_s01_couplers_AWADDR;
wire [1:0]auto_us_to_s01_couplers_AWBURST;
wire [3:0]auto_us_to_s01_couplers_AWCACHE;
wire [7:0]auto_us_to_s01_couplers_AWLEN;
wire [0:0]auto_us_to_s01_couplers_AWLOCK;
wire [2:0]auto_us_to_s01_couplers_AWPROT;
wire [3:0]auto_us_to_s01_couplers_AWQOS;
wire auto_us_to_s01_couplers_AWREADY;
wire [2:0]auto_us_to_s01_couplers_AWSIZE;
wire auto_us_to_s01_couplers_AWVALID;
wire auto_us_to_s01_couplers_BREADY;
wire [1:0]auto_us_to_s01_couplers_BRESP;
wire auto_us_to_s01_couplers_BVALID;
wire [63:0]auto_us_to_s01_couplers_WDATA;
wire auto_us_to_s01_couplers_WLAST;
wire auto_us_to_s01_couplers_WREADY;
wire [7:0]auto_us_to_s01_couplers_WSTRB;
wire auto_us_to_s01_couplers_WVALID;
wire [31:0]s01_couplers_to_auto_us_AWADDR;
wire [1:0]s01_couplers_to_auto_us_AWBURST;
wire [3:0]s01_couplers_to_auto_us_AWCACHE;
wire [7:0]s01_couplers_to_auto_us_AWLEN;
wire [2:0]s01_couplers_to_auto_us_AWPROT;
wire s01_couplers_to_auto_us_AWREADY;
wire [2:0]s01_couplers_to_auto_us_AWSIZE;
wire s01_couplers_to_auto_us_AWVALID;
wire s01_couplers_to_auto_us_BREADY;
wire [1:0]s01_couplers_to_auto_us_BRESP;
wire s01_couplers_to_auto_us_BVALID;
wire [31:0]s01_couplers_to_auto_us_WDATA;
wire s01_couplers_to_auto_us_WLAST;
wire s01_couplers_to_auto_us_WREADY;
wire [3:0]s01_couplers_to_auto_us_WSTRB;
wire s01_couplers_to_auto_us_WVALID;
assign M_AXI_awaddr[31:0] = auto_us_to_s01_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_to_s01_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_to_s01_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_us_to_s01_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_us_to_s01_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_to_s01_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_to_s01_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_to_s01_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_to_s01_couplers_AWVALID;
assign M_AXI_bready = auto_us_to_s01_couplers_BREADY;
assign M_AXI_wdata[63:0] = auto_us_to_s01_couplers_WDATA;
assign M_AXI_wlast = auto_us_to_s01_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_to_s01_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_to_s01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_awready = s01_couplers_to_auto_us_AWREADY;
assign S_AXI_bresp[1:0] = s01_couplers_to_auto_us_BRESP;
assign S_AXI_bvalid = s01_couplers_to_auto_us_BVALID;
assign S_AXI_wready = s01_couplers_to_auto_us_WREADY;
assign auto_us_to_s01_couplers_AWREADY = M_AXI_awready;
assign auto_us_to_s01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_to_s01_couplers_BVALID = M_AXI_bvalid;
assign auto_us_to_s01_couplers_WREADY = M_AXI_wready;
assign s01_couplers_to_auto_us_AWADDR = S_AXI_awaddr[31:0];
assign s01_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0];
assign s01_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0];
assign s01_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0];
assign s01_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0];
assign s01_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0];
assign s01_couplers_to_auto_us_AWVALID = S_AXI_awvalid;
assign s01_couplers_to_auto_us_BREADY = S_AXI_bready;
assign s01_couplers_to_auto_us_WDATA = S_AXI_wdata[31:0];
assign s01_couplers_to_auto_us_WLAST = S_AXI_wlast;
assign s01_couplers_to_auto_us_WSTRB = S_AXI_wstrb[3:0];
assign s01_couplers_to_auto_us_WVALID = S_AXI_wvalid;
GND GND
(.G(GND_1));
system_auto_us_1 auto_us
(.m_axi_awaddr(auto_us_to_s01_couplers_AWADDR),
.m_axi_awburst(auto_us_to_s01_couplers_AWBURST),
.m_axi_awcache(auto_us_to_s01_couplers_AWCACHE),
.m_axi_awlen(auto_us_to_s01_couplers_AWLEN),
.m_axi_awlock(auto_us_to_s01_couplers_AWLOCK),
.m_axi_awprot(auto_us_to_s01_couplers_AWPROT),
.m_axi_awqos(auto_us_to_s01_couplers_AWQOS),
.m_axi_awready(auto_us_to_s01_couplers_AWREADY),
.m_axi_awsize(auto_us_to_s01_couplers_AWSIZE),
.m_axi_awvalid(auto_us_to_s01_couplers_AWVALID),
.m_axi_bready(auto_us_to_s01_couplers_BREADY),
.m_axi_bresp(auto_us_to_s01_couplers_BRESP),
.m_axi_bvalid(auto_us_to_s01_couplers_BVALID),
.m_axi_wdata(auto_us_to_s01_couplers_WDATA),
.m_axi_wlast(auto_us_to_s01_couplers_WLAST),
.m_axi_wready(auto_us_to_s01_couplers_WREADY),
.m_axi_wstrb(auto_us_to_s01_couplers_WSTRB),
.m_axi_wvalid(auto_us_to_s01_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_awaddr(s01_couplers_to_auto_us_AWADDR),
.s_axi_awburst(s01_couplers_to_auto_us_AWBURST),
.s_axi_awcache(s01_couplers_to_auto_us_AWCACHE),
.s_axi_awlen(s01_couplers_to_auto_us_AWLEN),
.s_axi_awlock(GND_1),
.s_axi_awprot(s01_couplers_to_auto_us_AWPROT),
.s_axi_awqos({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awready(s01_couplers_to_auto_us_AWREADY),
.s_axi_awregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awsize(s01_couplers_to_auto_us_AWSIZE),
.s_axi_awvalid(s01_couplers_to_auto_us_AWVALID),
.s_axi_bready(s01_couplers_to_auto_us_BREADY),
.s_axi_bresp(s01_couplers_to_auto_us_BRESP),
.s_axi_bvalid(s01_couplers_to_auto_us_BVALID),
.s_axi_wdata(s01_couplers_to_auto_us_WDATA),
.s_axi_wlast(s01_couplers_to_auto_us_WLAST),
.s_axi_wready(s01_couplers_to_auto_us_WREADY),
.s_axi_wstrb(s01_couplers_to_auto_us_WSTRB),
.s_axi_wvalid(s01_couplers_to_auto_us_WVALID));
endmodule
module system
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [31:0]HLS_accel_0_OUTPUT_STREAM_TDATA;
wire [3:0]HLS_accel_0_OUTPUT_STREAM_TKEEP;
wire [0:0]HLS_accel_0_OUTPUT_STREAM_TLAST;
wire HLS_accel_0_OUTPUT_STREAM_TREADY;
wire HLS_accel_0_OUTPUT_STREAM_TVALID;
wire HLS_accel_0_interrupt;
wire VCC_1;
wire [31:0]axi_dma_0_M_AXIS_MM2S_TDATA;
wire [3:0]axi_dma_0_M_AXIS_MM2S_TKEEP;
wire axi_dma_0_M_AXIS_MM2S_TLAST;
wire axi_dma_0_M_AXIS_MM2S_TREADY;
wire axi_dma_0_M_AXIS_MM2S_TVALID;
wire [31:0]axi_dma_0_M_AXI_MM2S_ARADDR;
wire [1:0]axi_dma_0_M_AXI_MM2S_ARBURST;
wire [3:0]axi_dma_0_M_AXI_MM2S_ARCACHE;
wire [7:0]axi_dma_0_M_AXI_MM2S_ARLEN;
wire [2:0]axi_dma_0_M_AXI_MM2S_ARPROT;
wire axi_dma_0_M_AXI_MM2S_ARREADY;
wire [2:0]axi_dma_0_M_AXI_MM2S_ARSIZE;
wire axi_dma_0_M_AXI_MM2S_ARVALID;
wire [31:0]axi_dma_0_M_AXI_MM2S_RDATA;
wire axi_dma_0_M_AXI_MM2S_RLAST;
wire axi_dma_0_M_AXI_MM2S_RREADY;
wire [1:0]axi_dma_0_M_AXI_MM2S_RRESP;
wire axi_dma_0_M_AXI_MM2S_RVALID;
wire [31:0]axi_dma_0_M_AXI_S2MM_AWADDR;
wire [1:0]axi_dma_0_M_AXI_S2MM_AWBURST;
wire [3:0]axi_dma_0_M_AXI_S2MM_AWCACHE;
wire [7:0]axi_dma_0_M_AXI_S2MM_AWLEN;
wire [2:0]axi_dma_0_M_AXI_S2MM_AWPROT;
wire axi_dma_0_M_AXI_S2MM_AWREADY;
wire [2:0]axi_dma_0_M_AXI_S2MM_AWSIZE;
wire axi_dma_0_M_AXI_S2MM_AWVALID;
wire axi_dma_0_M_AXI_S2MM_BREADY;
wire [1:0]axi_dma_0_M_AXI_S2MM_BRESP;
wire axi_dma_0_M_AXI_S2MM_BVALID;
wire [31:0]axi_dma_0_M_AXI_S2MM_WDATA;
wire axi_dma_0_M_AXI_S2MM_WLAST;
wire axi_dma_0_M_AXI_S2MM_WREADY;
wire [3:0]axi_dma_0_M_AXI_S2MM_WSTRB;
wire axi_dma_0_M_AXI_S2MM_WVALID;
wire [31:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [0:0]axi_mem_intercon_M00_AXI_ARID;
wire [3:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [1:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire [3:0]axi_mem_intercon_M00_AXI_ARQOS;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [31:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [0:0]axi_mem_intercon_M00_AXI_AWID;
wire [3:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [1:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire [3:0]axi_mem_intercon_M00_AXI_AWQOS;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire [2:0]axi_mem_intercon_M00_AXI_BID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [63:0]axi_mem_intercon_M00_AXI_RDATA;
wire [2:0]axi_mem_intercon_M00_AXI_RID;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [63:0]axi_mem_intercon_M00_AXI_WDATA;
wire [0:0]axi_mem_intercon_M00_AXI_WID;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [7:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire axi_timer_0_interrupt;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [4:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [4:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_WSTRB;
wire processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [9:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [9:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire processing_system7_0_axi_periph_M01_AXI_WREADY;
wire processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [4:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [4:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire processing_system7_0_axi_periph_M02_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M02_AXI_WSTRB;
wire processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
wire [1:0]xlconcat_0_dout;
GND GND
(.G(GND_1));
system_HLS_accel_0_0 HLS_accel_0
(.INPUT_STREAM_TDATA(axi_dma_0_M_AXIS_MM2S_TDATA),
.INPUT_STREAM_TDEST({GND_1,GND_1,GND_1,GND_1,GND_1}),
.INPUT_STREAM_TID({GND_1,GND_1,GND_1,GND_1,GND_1}),
.INPUT_STREAM_TKEEP(axi_dma_0_M_AXIS_MM2S_TKEEP),
.INPUT_STREAM_TLAST(axi_dma_0_M_AXIS_MM2S_TLAST),
.INPUT_STREAM_TREADY(axi_dma_0_M_AXIS_MM2S_TREADY),
.INPUT_STREAM_TSTRB({VCC_1,VCC_1,VCC_1}),
.INPUT_STREAM_TUSER({GND_1,GND_1,GND_1,GND_1}),
.INPUT_STREAM_TVALID(axi_dma_0_M_AXIS_MM2S_TVALID),
.OUTPUT_STREAM_TDATA(HLS_accel_0_OUTPUT_STREAM_TDATA),
.OUTPUT_STREAM_TKEEP(HLS_accel_0_OUTPUT_STREAM_TKEEP),
.OUTPUT_STREAM_TLAST(HLS_accel_0_OUTPUT_STREAM_TLAST),
.OUTPUT_STREAM_TREADY(HLS_accel_0_OUTPUT_STREAM_TREADY),
.OUTPUT_STREAM_TVALID(HLS_accel_0_OUTPUT_STREAM_TVALID),
.ap_clk(processing_system7_0_FCLK_CLK0),
.ap_rst_n(rst_processing_system7_0_100M_peripheral_aresetn),
.interrupt(HLS_accel_0_interrupt),
.s_axi_CONTROL_BUS_ARADDR(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.s_axi_CONTROL_BUS_ARREADY(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_CONTROL_BUS_ARVALID(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_CONTROL_BUS_AWADDR(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.s_axi_CONTROL_BUS_AWREADY(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_CONTROL_BUS_AWVALID(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_CONTROL_BUS_BREADY(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_CONTROL_BUS_BRESP(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_CONTROL_BUS_BVALID(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_CONTROL_BUS_RDATA(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_CONTROL_BUS_RREADY(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_CONTROL_BUS_RRESP(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_CONTROL_BUS_RVALID(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_CONTROL_BUS_WDATA(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_CONTROL_BUS_WREADY(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_CONTROL_BUS_WSTRB(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.s_axi_CONTROL_BUS_WVALID(processing_system7_0_axi_periph_M00_AXI_WVALID));
VCC VCC
(.P(VCC_1));
system_axi_dma_0_0 axi_dma_0
(.axi_resetn(rst_processing_system7_0_100M_peripheral_aresetn),
.m_axi_mm2s_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_mm2s_araddr(axi_dma_0_M_AXI_MM2S_ARADDR),
.m_axi_mm2s_arburst(axi_dma_0_M_AXI_MM2S_ARBURST),
.m_axi_mm2s_arcache(axi_dma_0_M_AXI_MM2S_ARCACHE),
.m_axi_mm2s_arlen(axi_dma_0_M_AXI_MM2S_ARLEN),
.m_axi_mm2s_arprot(axi_dma_0_M_AXI_MM2S_ARPROT),
.m_axi_mm2s_arready(axi_dma_0_M_AXI_MM2S_ARREADY),
.m_axi_mm2s_arsize(axi_dma_0_M_AXI_MM2S_ARSIZE),
.m_axi_mm2s_arvalid(axi_dma_0_M_AXI_MM2S_ARVALID),
.m_axi_mm2s_rdata(axi_dma_0_M_AXI_MM2S_RDATA),
.m_axi_mm2s_rlast(axi_dma_0_M_AXI_MM2S_RLAST),
.m_axi_mm2s_rready(axi_dma_0_M_AXI_MM2S_RREADY),
.m_axi_mm2s_rresp(axi_dma_0_M_AXI_MM2S_RRESP),
.m_axi_mm2s_rvalid(axi_dma_0_M_AXI_MM2S_RVALID),
.m_axi_s2mm_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_s2mm_awaddr(axi_dma_0_M_AXI_S2MM_AWADDR),
.m_axi_s2mm_awburst(axi_dma_0_M_AXI_S2MM_AWBURST),
.m_axi_s2mm_awcache(axi_dma_0_M_AXI_S2MM_AWCACHE),
.m_axi_s2mm_awlen(axi_dma_0_M_AXI_S2MM_AWLEN),
.m_axi_s2mm_awprot(axi_dma_0_M_AXI_S2MM_AWPROT),
.m_axi_s2mm_awready(axi_dma_0_M_AXI_S2MM_AWREADY),
.m_axi_s2mm_awsize(axi_dma_0_M_AXI_S2MM_AWSIZE),
.m_axi_s2mm_awvalid(axi_dma_0_M_AXI_S2MM_AWVALID),
.m_axi_s2mm_bready(axi_dma_0_M_AXI_S2MM_BREADY),
.m_axi_s2mm_bresp(axi_dma_0_M_AXI_S2MM_BRESP),
.m_axi_s2mm_bvalid(axi_dma_0_M_AXI_S2MM_BVALID),
.m_axi_s2mm_wdata(axi_dma_0_M_AXI_S2MM_WDATA),
.m_axi_s2mm_wlast(axi_dma_0_M_AXI_S2MM_WLAST),
.m_axi_s2mm_wready(axi_dma_0_M_AXI_S2MM_WREADY),
.m_axi_s2mm_wstrb(axi_dma_0_M_AXI_S2MM_WSTRB),
.m_axi_s2mm_wvalid(axi_dma_0_M_AXI_S2MM_WVALID),
.m_axis_mm2s_tdata(axi_dma_0_M_AXIS_MM2S_TDATA),
.m_axis_mm2s_tkeep(axi_dma_0_M_AXIS_MM2S_TKEEP),
.m_axis_mm2s_tlast(axi_dma_0_M_AXIS_MM2S_TLAST),
.m_axis_mm2s_tready(axi_dma_0_M_AXIS_MM2S_TREADY),
.m_axis_mm2s_tvalid(axi_dma_0_M_AXIS_MM2S_TVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.s_axi_lite_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.s_axi_lite_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.s_axi_lite_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.s_axi_lite_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.s_axi_lite_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.s_axi_lite_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.s_axi_lite_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.s_axi_lite_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.s_axi_lite_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.s_axi_lite_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.s_axi_lite_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.s_axi_lite_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.s_axi_lite_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.s_axi_lite_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.s_axi_lite_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.s_axis_s2mm_tdata(HLS_accel_0_OUTPUT_STREAM_TDATA),
.s_axis_s2mm_tkeep(HLS_accel_0_OUTPUT_STREAM_TKEEP),
.s_axis_s2mm_tlast(HLS_accel_0_OUTPUT_STREAM_TLAST),
.s_axis_s2mm_tready(HLS_accel_0_OUTPUT_STREAM_TREADY),
.s_axis_s2mm_tvalid(HLS_accel_0_OUTPUT_STREAM_TVALID));
system_axi_mem_intercon_0 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arid(axi_mem_intercon_M00_AXI_ARID),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arqos(axi_mem_intercon_M00_AXI_ARQOS),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awid(axi_mem_intercon_M00_AXI_AWID),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_mem_intercon_M00_AXI_AWQOS),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bid(axi_mem_intercon_M00_AXI_BID[0]),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rid(axi_mem_intercon_M00_AXI_RID[0]),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wid(axi_mem_intercon_M00_AXI_WID),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(axi_dma_0_M_AXI_MM2S_ARADDR),
.S00_AXI_arburst(axi_dma_0_M_AXI_MM2S_ARBURST),
.S00_AXI_arcache(axi_dma_0_M_AXI_MM2S_ARCACHE),
.S00_AXI_arlen(axi_dma_0_M_AXI_MM2S_ARLEN),
.S00_AXI_arprot(axi_dma_0_M_AXI_MM2S_ARPROT),
.S00_AXI_arready(axi_dma_0_M_AXI_MM2S_ARREADY),
.S00_AXI_arsize(axi_dma_0_M_AXI_MM2S_ARSIZE),
.S00_AXI_arvalid(axi_dma_0_M_AXI_MM2S_ARVALID),
.S00_AXI_rdata(axi_dma_0_M_AXI_MM2S_RDATA),
.S00_AXI_rlast(axi_dma_0_M_AXI_MM2S_RLAST),
.S00_AXI_rready(axi_dma_0_M_AXI_MM2S_RREADY),
.S00_AXI_rresp(axi_dma_0_M_AXI_MM2S_RRESP),
.S00_AXI_rvalid(axi_dma_0_M_AXI_MM2S_RVALID),
.S01_ACLK(processing_system7_0_FCLK_CLK0),
.S01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S01_AXI_awaddr(axi_dma_0_M_AXI_S2MM_AWADDR),
.S01_AXI_awburst(axi_dma_0_M_AXI_S2MM_AWBURST),
.S01_AXI_awcache(axi_dma_0_M_AXI_S2MM_AWCACHE),
.S01_AXI_awlen(axi_dma_0_M_AXI_S2MM_AWLEN),
.S01_AXI_awprot(axi_dma_0_M_AXI_S2MM_AWPROT),
.S01_AXI_awready(axi_dma_0_M_AXI_S2MM_AWREADY),
.S01_AXI_awsize(axi_dma_0_M_AXI_S2MM_AWSIZE),
.S01_AXI_awvalid(axi_dma_0_M_AXI_S2MM_AWVALID),
.S01_AXI_bready(axi_dma_0_M_AXI_S2MM_BREADY),
.S01_AXI_bresp(axi_dma_0_M_AXI_S2MM_BRESP),
.S01_AXI_bvalid(axi_dma_0_M_AXI_S2MM_BVALID),
.S01_AXI_wdata(axi_dma_0_M_AXI_S2MM_WDATA),
.S01_AXI_wlast(axi_dma_0_M_AXI_S2MM_WLAST),
.S01_AXI_wready(axi_dma_0_M_AXI_S2MM_WREADY),
.S01_AXI_wstrb(axi_dma_0_M_AXI_S2MM_WSTRB),
.S01_AXI_wvalid(axi_dma_0_M_AXI_S2MM_WVALID));
system_axi_timer_0_0 axi_timer_0
(.capturetrig0(GND_1),
.capturetrig1(GND_1),
.freeze(GND_1),
.interrupt(axi_timer_0_interrupt),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID));
system_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.IRQ_F2P(xlconcat_0_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_ACP_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_ACP_ARADDR(axi_mem_intercon_M00_AXI_ARADDR),
.S_AXI_ACP_ARBURST(axi_mem_intercon_M00_AXI_ARBURST),
.S_AXI_ACP_ARCACHE(axi_mem_intercon_M00_AXI_ARCACHE),
.S_AXI_ACP_ARID(axi_mem_intercon_M00_AXI_ARID),
.S_AXI_ACP_ARLEN(axi_mem_intercon_M00_AXI_ARLEN),
.S_AXI_ACP_ARLOCK(axi_mem_intercon_M00_AXI_ARLOCK),
.S_AXI_ACP_ARPROT(axi_mem_intercon_M00_AXI_ARPROT),
.S_AXI_ACP_ARQOS(axi_mem_intercon_M00_AXI_ARQOS),
.S_AXI_ACP_ARREADY(axi_mem_intercon_M00_AXI_ARREADY),
.S_AXI_ACP_ARSIZE(axi_mem_intercon_M00_AXI_ARSIZE),
.S_AXI_ACP_ARUSER({GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_ACP_ARVALID(axi_mem_intercon_M00_AXI_ARVALID),
.S_AXI_ACP_AWADDR(axi_mem_intercon_M00_AXI_AWADDR),
.S_AXI_ACP_AWBURST(axi_mem_intercon_M00_AXI_AWBURST),
.S_AXI_ACP_AWCACHE(axi_mem_intercon_M00_AXI_AWCACHE),
.S_AXI_ACP_AWID(axi_mem_intercon_M00_AXI_AWID),
.S_AXI_ACP_AWLEN(axi_mem_intercon_M00_AXI_AWLEN),
.S_AXI_ACP_AWLOCK(axi_mem_intercon_M00_AXI_AWLOCK),
.S_AXI_ACP_AWPROT(axi_mem_intercon_M00_AXI_AWPROT),
.S_AXI_ACP_AWQOS(axi_mem_intercon_M00_AXI_AWQOS),
.S_AXI_ACP_AWREADY(axi_mem_intercon_M00_AXI_AWREADY),
.S_AXI_ACP_AWSIZE(axi_mem_intercon_M00_AXI_AWSIZE),
.S_AXI_ACP_AWUSER({GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_ACP_AWVALID(axi_mem_intercon_M00_AXI_AWVALID),
.S_AXI_ACP_BID(axi_mem_intercon_M00_AXI_BID),
.S_AXI_ACP_BREADY(axi_mem_intercon_M00_AXI_BREADY),
.S_AXI_ACP_BRESP(axi_mem_intercon_M00_AXI_BRESP),
.S_AXI_ACP_BVALID(axi_mem_intercon_M00_AXI_BVALID),
.S_AXI_ACP_RDATA(axi_mem_intercon_M00_AXI_RDATA),
.S_AXI_ACP_RID(axi_mem_intercon_M00_AXI_RID),
.S_AXI_ACP_RLAST(axi_mem_intercon_M00_AXI_RLAST),
.S_AXI_ACP_RREADY(axi_mem_intercon_M00_AXI_RREADY),
.S_AXI_ACP_RRESP(axi_mem_intercon_M00_AXI_RRESP),
.S_AXI_ACP_RVALID(axi_mem_intercon_M00_AXI_RVALID),
.S_AXI_ACP_WDATA(axi_mem_intercon_M00_AXI_WDATA),
.S_AXI_ACP_WID(axi_mem_intercon_M00_AXI_WID),
.S_AXI_ACP_WLAST(axi_mem_intercon_M00_AXI_WLAST),
.S_AXI_ACP_WREADY(axi_mem_intercon_M00_AXI_WREADY),
.S_AXI_ACP_WSTRB(axi_mem_intercon_M00_AXI_WSTRB),
.S_AXI_ACP_WVALID(axi_mem_intercon_M00_AXI_WVALID),
.USB0_VBUS_PWRFAULT(GND_1));
system_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
system_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
system_xlconcat_0_0 xlconcat_0
(.In0(HLS_accel_0_interrupt),
.In1(axi_timer_0_interrupt),
.dout(xlconcat_0_dout));
endmodule
module system_axi_mem_intercon_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wid,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arlen,
S00_AXI_arprot,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_rdata,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S01_ACLK,
S01_ARESETN,
S01_AXI_awaddr,
S01_AXI_awburst,
S01_AXI_awcache,
S01_AXI_awlen,
S01_AXI_awprot,
S01_AXI_awready,
S01_AXI_awsize,
S01_AXI_awvalid,
S01_AXI_bready,
S01_AXI_bresp,
S01_AXI_bvalid,
S01_AXI_wdata,
S01_AXI_wlast,
S01_AXI_wready,
S01_AXI_wstrb,
S01_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [0:0]M00_AXI_arid;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [0:0]M00_AXI_awid;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [0:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input [0:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output [0:0]M00_AXI_wid;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [7:0]S00_AXI_arlen;
input [2:0]S00_AXI_arprot;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
output [31:0]S00_AXI_rdata;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input S01_ACLK;
input [0:0]S01_ARESETN;
input [31:0]S01_AXI_awaddr;
input [1:0]S01_AXI_awburst;
input [3:0]S01_AXI_awcache;
input [7:0]S01_AXI_awlen;
input [2:0]S01_AXI_awprot;
output S01_AXI_awready;
input [2:0]S01_AXI_awsize;
input S01_AXI_awvalid;
input S01_AXI_bready;
output [1:0]S01_AXI_bresp;
output S01_AXI_bvalid;
input [31:0]S01_AXI_wdata;
input S01_AXI_wlast;
output S01_AXI_wready;
input [3:0]S01_AXI_wstrb;
input S01_AXI_wvalid;
wire GND_1;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire S01_ACLK_1;
wire [0:0]S01_ARESETN_1;
wire VCC_1;
wire axi_mem_intercon_ACLK_net;
wire [0:0]axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_to_s01_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s01_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s01_couplers_AWCACHE;
wire [7:0]axi_mem_intercon_to_s01_couplers_AWLEN;
wire [2:0]axi_mem_intercon_to_s01_couplers_AWPROT;
wire axi_mem_intercon_to_s01_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s01_couplers_AWSIZE;
wire axi_mem_intercon_to_s01_couplers_AWVALID;
wire axi_mem_intercon_to_s01_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s01_couplers_BRESP;
wire axi_mem_intercon_to_s01_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s01_couplers_WDATA;
wire axi_mem_intercon_to_s01_couplers_WLAST;
wire axi_mem_intercon_to_s01_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s01_couplers_WSTRB;
wire axi_mem_intercon_to_s01_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARCACHE;
wire [0:0]m00_couplers_to_axi_mem_intercon_ARID;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARQOS;
wire m00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARSIZE;
wire m00_couplers_to_axi_mem_intercon_ARVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWCACHE;
wire [0:0]m00_couplers_to_axi_mem_intercon_AWID;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWQOS;
wire m00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWSIZE;
wire m00_couplers_to_axi_mem_intercon_AWVALID;
wire [0:0]m00_couplers_to_axi_mem_intercon_BID;
wire m00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_BRESP;
wire m00_couplers_to_axi_mem_intercon_BVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_RDATA;
wire [0:0]m00_couplers_to_axi_mem_intercon_RID;
wire m00_couplers_to_axi_mem_intercon_RLAST;
wire m00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_RRESP;
wire m00_couplers_to_axi_mem_intercon_RVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_WDATA;
wire [0:0]m00_couplers_to_axi_mem_intercon_WID;
wire m00_couplers_to_axi_mem_intercon_WLAST;
wire m00_couplers_to_axi_mem_intercon_WREADY;
wire [7:0]m00_couplers_to_axi_mem_intercon_WSTRB;
wire m00_couplers_to_axi_mem_intercon_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [63:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s01_couplers_to_xbar_AWADDR;
wire [1:0]s01_couplers_to_xbar_AWBURST;
wire [3:0]s01_couplers_to_xbar_AWCACHE;
wire [7:0]s01_couplers_to_xbar_AWLEN;
wire [0:0]s01_couplers_to_xbar_AWLOCK;
wire [2:0]s01_couplers_to_xbar_AWPROT;
wire [3:0]s01_couplers_to_xbar_AWQOS;
wire [1:1]s01_couplers_to_xbar_AWREADY;
wire [2:0]s01_couplers_to_xbar_AWSIZE;
wire s01_couplers_to_xbar_AWVALID;
wire s01_couplers_to_xbar_BREADY;
wire [3:2]s01_couplers_to_xbar_BRESP;
wire [1:1]s01_couplers_to_xbar_BVALID;
wire [63:0]s01_couplers_to_xbar_WDATA;
wire s01_couplers_to_xbar_WLAST;
wire [1:1]s01_couplers_to_xbar_WREADY;
wire [7:0]s01_couplers_to_xbar_WSTRB;
wire s01_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [0:0]xbar_to_m00_couplers_ARID;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [0:0]xbar_to_m00_couplers_AWID;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [63:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RID;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [63:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [7:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [1:0]NLW_xbar_s_axi_awready_UNCONNECTED;
wire [3:0]NLW_xbar_s_axi_bresp_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_bvalid_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_wready_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[31:0] = m00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arid[0] = m00_couplers_to_axi_mem_intercon_ARID;
assign M00_AXI_arlen[3:0] = m00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[1:0] = m00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_mem_intercon_ARQOS;
assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awid[0] = m00_couplers_to_axi_mem_intercon_AWID;
assign M00_AXI_awlen[3:0] = m00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[1:0] = m00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_mem_intercon_AWQOS;
assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wid[0] = m00_couplers_to_axi_mem_intercon_WID;
assign M00_AXI_wlast = m00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S01_ACLK_1 = S01_ACLK;
assign S01_ARESETN_1 = S01_ARESETN[0];
assign S01_AXI_awready = axi_mem_intercon_to_s01_couplers_AWREADY;
assign S01_AXI_bresp[1:0] = axi_mem_intercon_to_s01_couplers_BRESP;
assign S01_AXI_bvalid = axi_mem_intercon_to_s01_couplers_BVALID;
assign S01_AXI_wready = axi_mem_intercon_to_s01_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = ACLK;
assign axi_mem_intercon_ARESETN_net = ARESETN[0];
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s01_couplers_AWADDR = S01_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s01_couplers_AWBURST = S01_AXI_awburst[1:0];
assign axi_mem_intercon_to_s01_couplers_AWCACHE = S01_AXI_awcache[3:0];
assign axi_mem_intercon_to_s01_couplers_AWLEN = S01_AXI_awlen[7:0];
assign axi_mem_intercon_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];
assign axi_mem_intercon_to_s01_couplers_AWSIZE = S01_AXI_awsize[2:0];
assign axi_mem_intercon_to_s01_couplers_AWVALID = S01_AXI_awvalid;
assign axi_mem_intercon_to_s01_couplers_BREADY = S01_AXI_bready;
assign axi_mem_intercon_to_s01_couplers_WDATA = S01_AXI_wdata[31:0];
assign axi_mem_intercon_to_s01_couplers_WLAST = S01_AXI_wlast;
assign axi_mem_intercon_to_s01_couplers_WSTRB = S01_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s01_couplers_WVALID = S01_AXI_wvalid;
assign m00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_mem_intercon_BID = M00_AXI_bid[0];
assign m00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[63:0];
assign m00_couplers_to_axi_mem_intercon_RID = M00_AXI_rid[0];
assign m00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
m00_couplers_imp_1TEAG88 m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arid(m00_couplers_to_axi_mem_intercon_ARID),
.M_AXI_arlen(m00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_mem_intercon_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awid(m00_couplers_to_axi_mem_intercon_AWID),
.M_AXI_awlen(m00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_mem_intercon_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bid(m00_couplers_to_axi_mem_intercon_BID),
.M_AXI_bready(m00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rid(m00_couplers_to_axi_mem_intercon_RID),
.M_AXI_rlast(m00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wid(m00_couplers_to_axi_mem_intercon_WID),
.M_AXI_wlast(m00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),
.S_AXI_arid(xbar_to_m00_couplers_ARID),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),
.S_AXI_awid(xbar_to_m00_couplers_AWID),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bid(xbar_to_m00_couplers_BID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rid(xbar_to_m00_couplers_RID),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
s00_couplers_imp_1P403ZT s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID));
s01_couplers_imp_VQ497S s01_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s01_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),
.M_AXI_awlen(s01_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s01_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s01_couplers_to_xbar_AWQOS),
.M_AXI_awready(s01_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),
.M_AXI_bready(s01_couplers_to_xbar_BREADY),
.M_AXI_bresp(s01_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s01_couplers_to_xbar_BVALID),
.M_AXI_wdata(s01_couplers_to_xbar_WDATA),
.M_AXI_wlast(s01_couplers_to_xbar_WLAST),
.M_AXI_wready(s01_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s01_couplers_to_xbar_WVALID),
.S_ACLK(S01_ACLK_1),
.S_ARESETN(S01_ARESETN_1),
.S_AXI_awaddr(axi_mem_intercon_to_s01_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s01_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s01_couplers_AWCACHE),
.S_AXI_awlen(axi_mem_intercon_to_s01_couplers_AWLEN),
.S_AXI_awprot(axi_mem_intercon_to_s01_couplers_AWPROT),
.S_AXI_awready(axi_mem_intercon_to_s01_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s01_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s01_couplers_AWVALID),
.S_AXI_bready(axi_mem_intercon_to_s01_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s01_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s01_couplers_BVALID),
.S_AXI_wdata(axi_mem_intercon_to_s01_couplers_WDATA),
.S_AXI_wlast(axi_mem_intercon_to_s01_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s01_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s01_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s01_couplers_WVALID));
system_xbar_1 xbar
(.aclk(axi_mem_intercon_ACLK_net),
.aresetn(axi_mem_intercon_ARESETN_net),
.m_axi_araddr(xbar_to_m00_couplers_ARADDR),
.m_axi_arburst(xbar_to_m00_couplers_ARBURST),
.m_axi_arcache(xbar_to_m00_couplers_ARCACHE),
.m_axi_arid(xbar_to_m00_couplers_ARID),
.m_axi_arlen(xbar_to_m00_couplers_ARLEN),
.m_axi_arlock(xbar_to_m00_couplers_ARLOCK),
.m_axi_arprot(xbar_to_m00_couplers_ARPROT),
.m_axi_arqos(xbar_to_m00_couplers_ARQOS),
.m_axi_arready(xbar_to_m00_couplers_ARREADY),
.m_axi_arregion(xbar_to_m00_couplers_ARREGION),
.m_axi_arsize(xbar_to_m00_couplers_ARSIZE),
.m_axi_arvalid(xbar_to_m00_couplers_ARVALID),
.m_axi_awaddr(xbar_to_m00_couplers_AWADDR),
.m_axi_awburst(xbar_to_m00_couplers_AWBURST),
.m_axi_awcache(xbar_to_m00_couplers_AWCACHE),
.m_axi_awid(xbar_to_m00_couplers_AWID),
.m_axi_awlen(xbar_to_m00_couplers_AWLEN),
.m_axi_awlock(xbar_to_m00_couplers_AWLOCK),
.m_axi_awprot(xbar_to_m00_couplers_AWPROT),
.m_axi_awqos(xbar_to_m00_couplers_AWQOS),
.m_axi_awready(xbar_to_m00_couplers_AWREADY),
.m_axi_awregion(xbar_to_m00_couplers_AWREGION),
.m_axi_awsize(xbar_to_m00_couplers_AWSIZE),
.m_axi_awvalid(xbar_to_m00_couplers_AWVALID),
.m_axi_bid(xbar_to_m00_couplers_BID),
.m_axi_bready(xbar_to_m00_couplers_BREADY),
.m_axi_bresp(xbar_to_m00_couplers_BRESP),
.m_axi_bvalid(xbar_to_m00_couplers_BVALID),
.m_axi_rdata(xbar_to_m00_couplers_RDATA),
.m_axi_rid(xbar_to_m00_couplers_RID),
.m_axi_rlast(xbar_to_m00_couplers_RLAST),
.m_axi_rready(xbar_to_m00_couplers_RREADY),
.m_axi_rresp(xbar_to_m00_couplers_RRESP),
.m_axi_rvalid(xbar_to_m00_couplers_RVALID),
.m_axi_wdata(xbar_to_m00_couplers_WDATA),
.m_axi_wlast(xbar_to_m00_couplers_WLAST),
.m_axi_wready(xbar_to_m00_couplers_WREADY),
.m_axi_wstrb(xbar_to_m00_couplers_WSTRB),
.m_axi_wvalid(xbar_to_m00_couplers_WVALID),
.s_axi_araddr({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARADDR}),
.s_axi_arburst({GND_1,GND_1,s00_couplers_to_xbar_ARBURST}),
.s_axi_arcache({GND_1,GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARCACHE}),
.s_axi_arid({GND_1,GND_1}),
.s_axi_arlen({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,VCC_1,GND_1,s00_couplers_to_xbar_ARLEN}),
.s_axi_arlock({GND_1,s00_couplers_to_xbar_ARLOCK}),
.s_axi_arprot({GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARPROT}),
.s_axi_arqos({GND_1,GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARQOS}),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arsize({GND_1,GND_1,GND_1,s00_couplers_to_xbar_ARSIZE}),
.s_axi_arvalid({GND_1,s00_couplers_to_xbar_ARVALID}),
.s_axi_awaddr({s01_couplers_to_xbar_AWADDR,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awburst({s01_couplers_to_xbar_AWBURST,GND_1,GND_1}),
.s_axi_awcache({s01_couplers_to_xbar_AWCACHE,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awid({GND_1,GND_1}),
.s_axi_awlen({s01_couplers_to_xbar_AWLEN,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awlock({s01_couplers_to_xbar_AWLOCK,GND_1}),
.s_axi_awprot({s01_couplers_to_xbar_AWPROT,GND_1,GND_1,GND_1}),
.s_axi_awqos({s01_couplers_to_xbar_AWQOS,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awready({s01_couplers_to_xbar_AWREADY,NLW_xbar_s_axi_awready_UNCONNECTED[0]}),
.s_axi_awsize({s01_couplers_to_xbar_AWSIZE,GND_1,GND_1,GND_1}),
.s_axi_awvalid({s01_couplers_to_xbar_AWVALID,GND_1}),
.s_axi_bready({s01_couplers_to_xbar_BREADY,GND_1}),
.s_axi_bresp({s01_couplers_to_xbar_BRESP,NLW_xbar_s_axi_bresp_UNCONNECTED[1:0]}),
.s_axi_bvalid({s01_couplers_to_xbar_BVALID,NLW_xbar_s_axi_bvalid_UNCONNECTED[0]}),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rlast(s00_couplers_to_xbar_RLAST),
.s_axi_rready({GND_1,s00_couplers_to_xbar_RREADY}),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata({s01_couplers_to_xbar_WDATA,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_wlast({s01_couplers_to_xbar_WLAST,VCC_1}),
.s_axi_wready({s01_couplers_to_xbar_WREADY,NLW_xbar_s_axi_wready_UNCONNECTED[0]}),
.s_axi_wstrb({s01_couplers_to_xbar_WSTRB,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1}),
.s_axi_wvalid({s01_couplers_to_xbar_WVALID,GND_1}));
endmodule
module system_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [4:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [4:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [9:0]M01_AXI_araddr;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [9:0]M01_AXI_awaddr;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [4:0]M02_AXI_araddr;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [4:0]M02_AXI_awaddr;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output M02_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [0:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [0:0]M02_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire [4:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [4:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [9:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [9:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [4:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [4:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire xbar_to_m01_couplers_WREADY;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [11:0]NLW_xbar_m_axi_wstrb_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[4:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[4:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN[0];
assign M01_AXI_araddr[9:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[9:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wvalid = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN[0];
assign M02_AXI_araddr[4:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[4:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M02_AXI_wvalid = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready;
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready;
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready;
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready;
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready;
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready;
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready;
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready;
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready;
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN[0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_WKXF3L m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m00_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[4:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[4:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1ORP4PS m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[41:32]),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[41:32]),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_1VD9O7M m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m02_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[68:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[68:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
s00_couplers_imp_IK3G2O s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
system_xbar_0 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m02_couplers_WSTRB,NLW_xbar_m_axi_wstrb_UNCONNECTED[7:4],xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Freeze logic ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generates all freezes and stalls inside RISC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_freeze.v,v $
// Revision 1.8 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.2 2003/12/05 00:09:49 lampret
// No functional change.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2002/07/31 02:04:35 lampret
// MAC now follows software convention (signed multiply instead of unsigned).
//
// Revision 1.5 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.4 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
`define OR1200_NO_FREEZE 3'd0
`define OR1200_FREEZE_BYDC 3'd1
`define OR1200_FREEZE_BYMULTICYCLE 3'd2
`define OR1200_WAIT_LSU_TO_FINISH 3'd3
`define OR1200_WAIT_IC 3'd4
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module or1200_freeze(
// Clock and reset
clk, rst,
// Internal i/f
multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
abort_ex,
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
icpu_ack_i, icpu_err_i
);
//
// I/O
//
input clk;
input rst;
input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
input flushpipe;
input extend_flush;
input lsu_stall;
input if_stall;
input lsu_unstall;
input abort_ex;
input du_stall;
input mac_stall;
output genpc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
output wb_freeze;
input icpu_ack_i;
input icpu_err_i;
//
// Internal wires and regs
//
wire multicycle_freeze;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
reg flushpipe_r;
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;
assign genpc_freeze = du_stall | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze ) | du_stall | mac_stall;
assign ex_freeze = wb_freeze;
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
//
// registered flushpipe
//
always @(posedge clk or posedge rst)
if (rst)
flushpipe_r <= #1 1'b0;
else if (icpu_ack_i | icpu_err_i)
// else if (!if_stall)
flushpipe_r <= #1 flushpipe;
else if (!flushpipe)
flushpipe_r <= #1 1'b0;
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;
//
// Multicycle counter
//
always @(posedge clk or posedge rst)
if (rst)
multicycle_cnt <= #1 2'b00;
else if (|multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 2'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
//
// Abstruct the signal we are interested in
//
//always @(posedge clk or posedge rst)
//$show_signal_value(or1200_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFXBP_PP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_PP_SYMBOL_V
|
// megafunction wizard: %Altera PLL v14.0%
// GENERATION: XML
// master_clock.v
// Generated using ACDS version 14.0 200 at 2018.11.25.19:40:19
`timescale 1 ps / 1 ps
module master_clock (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
master_clock_0002 master_clock_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="14.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="8" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="48" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="5" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="150.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="8" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="145.000000 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="40.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="10" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="40.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="12" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="120.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="8" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="8" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="160.000000 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="1.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="480" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="degrees" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="180.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="192.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="8" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="degrees" />
// Retrieval info: <generic name="gui_phase_shift6" value="5208" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="5208 ps" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="3.065" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="5" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="degrees" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="135.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="180" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : master_clock.vo
// RELATED_FILES: master_clock.v, master_clock_0002.v
|
module q_mul8
(
input CLK,
input RESET_X,
input INPUT_EN,
input [7:0] A_IN,
input [7:0] B_IN,
input [7:0] A_IN_INV,
input [7:0] B_IN_INV,
input A_SEL_INV,
input B_SEL_INV,
output OUTPUT_EN,
output [7:0] C_OUT,
input [31:0] MLC_GAGB,
// MULL ADD1
input [31:0] ML1_GAIN,
input [31:0] ML1_QPARAM,
input [31:0] ML2_GAIN,
input [31:0] ML2_QPARAM,
output [15:0] MIN,
output [15:0] MAX
);
// # vector
// AdBd_qt, AdBd_min, AdBd_max = q_mul_core(a_qt, Adash_min, Adash_max, b_qt, Bdash_min, Bdash_max, debug=debug)
// C_qt_0, C_qt_0_min, C_qt_0_max = q_add(qt_A_bmin, A_bmin_min, A_bmin_max, qt_B_amin, B_amin_min, B_amin_max, debug=debug)
// C_qt, c_min, c_max = q_add(AdBd_qt, AdBd_min, AdBd_max, C_qt_0, C_qt_0_min, C_qt_0_max, debug=debug)
wire [7:0] AdBd_qt;
wire mul_core_en;
wire [7:0] C_qt_0;
wire [7:0] qt_A_bmin;
wire [7:0] qt_B_amin;
wire add_1st_en;
assign qt_A_bmin = A_SEL_INV ? A_IN_INV : A_IN;
assign qt_B_amin = B_SEL_INV ? B_IN_INV : B_IN;
reg [7:0] AdBd_qt_1t;
q_mul_core8 mul_core
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(INPUT_EN),
.A_IN(A_IN),
.B_IN(B_IN),
.OUTPUT_EN(mul_core_en),
.C_OUT(AdBd_qt),
.MLC_GAGB(MLC_GAGB)
);
q_add8 add_1st
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(INPUT_EN),
.A_IN(qt_A_bmin),
.B_IN(qt_B_amin),
.OUTPUT_EN(add_1st_en),
.C_OUT(C_qt_0),
.GAIN(ML1_GAIN),
.Q_PARAM(ML1_QPARAM),
.MIN(),
.MAX()
);
q_add8 add_2nd
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(add_1st_en),
.A_IN(AdBd_qt_1t),
.B_IN(C_qt_0),
.OUTPUT_EN(OUTPUT_EN),
.C_OUT(C_OUT),
.GAIN(ML2_GAIN),
.Q_PARAM(ML2_QPARAM),
.MIN(MIN),
.MAX(MAX)
);
always @ (posedge CLK or negedge RESET_X)begin
if (RESET_X == 0)begin
AdBd_qt_1t <= 8'h00;
end else begin
AdBd_qt_1t <= AdBd_qt;
end
end
endmodule // q_mul8
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:25:14 02/11/2016
// Design Name:
// Module Name: memorycontroller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Asynchronous SRAM controller for byte access
// After outputting a byte to read, the result is available 70ns later.
module MemoryController(
input clk,
input read_a, // Set to 1 to read from RAM
input read_b, // Set to 1 to read from RAM
input write, // Set to 1 to write to RAM
input [21:0] addr, // Address to read / write
input [7:0] din, // Data to write
output reg [7:0] dout_a, // Last read data a
output reg [7:0] dout_b, // Last read data b
output reg busy, // 1 while an operation is in progress
output MemWR, // Write Enable. WRITE when Low.
output [18:0] MemAdr,
inout [7:0] MemDB,
input [13:0] debugaddr,
output [15:0] debugdata
);
reg MemOE;
reg RamWR;
reg sramWR = 1'b1;
reg [7:0] data_to_write;
reg [18:0] MemAdrReg;
wire [7:0] vram_dout;
wire [7:0] ram_dout;
wire [7:0] prgrom_dout;
wire [7:0] chrrom_dout;
wire [7:0] prgram_dout;
wire prgrom_ena = addr[21:18] == 4'b0000;
wire chrrom_ena = addr[21:18] == 4'b1000;
wire vram_ena = addr[21:18] == 4'b1100;
wire ram_ena = addr[21:18] == 4'b1110;
wire prgram_ena = addr[21:18] == 4'b1111;
wire [7:0] memory_dout = prgrom_ena ? prgrom_dout :
chrrom_ena ? chrrom_dout :
vram_ena ? vram_dout :
ram_ena ? ram_dout : prgram_dout;
ram2k vram(clk, vram_ena, RamWR, addr[10:0], data_to_write, vram_dout); // VRAM in BRAM
ram2k ram(clk, ram_ena, RamWR, addr[10:0], data_to_write, ram_dout); // RAM in BRAM
ram8k prg_ram(clk, prgram_ena, RamWR, addr[12:0], data_to_write, prgram_dout); // Cart RAM in BRAM
assign chrrom_dout = MemDB;
assign prgrom_dout = MemDB;
assign MemDB = (!sramWR) ? data_to_write : 8'bz;
assign MemAdr = MemAdrReg;
assign MemWR = sramWR;
reg [1:0] cycles;
reg r_read_a;
always @(posedge clk) begin
// Initiate read or write
if (!busy) begin
if (read_a || read_b || write) begin
if (prgrom_ena) begin
MemAdrReg <= {1'b0, addr[17:0]}; // PRGROM in SRAM
end else if (chrrom_ena) begin
MemAdrReg <= {1'b1, addr[17:0]}; // CHRROM in SRAM
end
RamWR <= write;
sramWR <= !((write == 1) && (prgrom_ena || chrrom_ena));
MemOE <= !(write == 0);
busy <= 1;
data_to_write <= din;
cycles <= 0;
r_read_a <= read_a;
end else begin
MemOE <= 1;
RamWR <= 0;
sramWR <= 1;
busy <= 0;
cycles <= 0;
end
end else begin
if (cycles == 2) begin
// Now we have waited 3x45 = 135ns, latch incoming data on read.
if (!MemOE) begin
if (r_read_a) dout_a <= memory_dout;
else dout_b <= memory_dout;
end
MemOE <= 1; // Deassert Output Enable.
RamWR <= 0; // Deassert Write
sramWR <= 1;
busy <= 0;
cycles <= 0;
end else begin
cycles <= cycles + 1;
end
end
end
endmodule // MemoryController
|
`timescale 1ns / 1ps
/**
Pipelined CPU
*/
module pipeline ( input wire clk,
input wire rst,
output i_read_en,
output [31:0] i_addr,
input [31:0] i_instr_in,
input wb_done_i,
output wire d_read_en,
output wire d_write_en,
output wire [31:0] d_addr,
output wire [31:0] d_write_data,
input wire [31:0] d_data_in );
/* Interconnect wires*/
wire [1:0] pc_source;
wire pc_write;
wire [31:0] jump_addr;
wire [31:0] branch_addr;
wire [31:0] next_i_addr;
wire [31:0] i_fetched; // fetched instrcution from if
wire if_id_write_en; // write enable for IF/ID pipe reg
wire [31:0] wreg_data; // data to write into regfile
wire [4:0] ex_dst_reg;
wire [5:0] ex_opcode;
wire [31:0] ex_reg_data_1; // for jr
wire [4:0] id_rs;
wire [4:0] id_rt;
wire [5:0] id_opcode;
wire ID_EX_wb_reg_write;
wire ID_EX_wb_mem_to_reg;
wire ID_EX_mem_read;
wire ID_EX_mem_write;
wire ID_EX_ex_imm_command;
wire ID_EX_ex_alu_src_b;
wire ID_EX_ex_alu_rslt_src;
wire [1:0] ID_EX_ex_dst_reg_sel;
wire [1:0] ID_EX_ex_alu_op;
wire [31:0] ID_EX_A;
wire [31:0] ID_EX_B;
wire [31:0] ID_EX_sign_extend_offset;
wire [4:0] ID_EX_rt; // target register
wire [4:0] ID_EX_rd; // destination register
wire [4:0] ID_EX_rs; // source register
wire [5:0] ID_EX_opcode;
wire [31:0] EX_MEM_alu_result;
wire [31:0] EX_MEM_B_value;
wire [4:0] EX_MEM_dst_reg;
wire [5:0] EX_MEM_opcode;
wire EX_MEM_mem_read;
wire EX_MEM_mem_write;
wire EX_MEM_wb_reg_write;
wire EX_MEM_wb_mem_to_reg;
wire [4:0] MEM_WB_dst_reg;
wire MEM_WB_reg_write;
wire MEM_WB_mem_to_reg;
wire [31:0] MEM_WB_mem_out;
wire [31:0] MEM_WB_alu_out;
wire id_rt_is_source;
wire hazard_detected;
// forwarding control signals for muxes
wire [1:0] if_rs_forward_control;
wire [1:0] id_rt_forward_control;
wire [1:0] ex_rs_forward_control;
wire [1:0] ex_rt_forward_control;
if_stage ifetch_inst(
.clk ( clk ),
.rst ( rst ),
.pstop_i(pstop),
.if_id_write_en ( if_id_write_en ),
.pc_write ( pc_write ),
.pc_source ( pc_source ),
.i_read_en ( i_read_en ),
.i_addr ( i_addr ),
.i_instr_in ( i_instr_in),
.jump_addr ( jump_addr ),
.branch_addr ( branch_addr ),
.reg_data_1 ( ex_reg_data_1 ),
.IF_ID_instruction ( i_fetched ),
.IF_ID_next_i_addr ( next_i_addr ));
hazard_unit hazard_inst(
.clk ( clk ), // isn't needed for now
.rst ( rst ), // isn't needed for now
.ex_dst_reg ( ex_dst_reg ),
.pstop_o(pstop),
.mem_dst_reg ( EX_MEM_dst_reg ),
.id_rs ( id_rs ),
.id_rt ( id_rt ),
.mem_opcode ( EX_MEM_opcode ),
.ex_opcode ( ex_opcode ),
.id_opcode ( id_opcode ),
.id_rt_is_source ( id_rt_is_source ),
.ex_reg_write ( ID_EX_wb_reg_write ),
.mem_reg_write ( EX_MEM_wb_reg_write ),
.pc_write ( pc_write ),
.if_id_write_en ( if_id_write_en ),
.wb_done_i(wb_done_i),
.hazard_detected_o ( hazard_detected ));
forwarding_unit forwarding_inst(
.ex_mem_reg_write (EX_MEM_wb_reg_write),
.mem_wb_reg_write (MEM_WB_reg_write),
.ex_mem_dst_reg (EX_MEM_dst_reg),
.mem_wb_dst_reg (MEM_WB_dst_reg),
.id_ex_rs (ID_EX_rs),
.id_ex_rt (ID_EX_rt),
.if_id_rs (id_rs),
.if_id_rt (id_rt),
.if_rs_forward_control ( if_rs_forward_control ),
.id_rt_forward_control ( id_rt_forward_control ),
.ex_rs_forward_control ( ex_rs_forward_control ),
.ex_rt_forward_control ( ex_rt_forward_control ));
id_stage idecode_inst(
.clk ( clk ),
.rst ( rst ),
.reg_write ( MEM_WB_reg_write ),
.wreg_addr ( MEM_WB_dst_reg ), // write register number
.wreg_data ( wreg_data ), // data to write into regfile
.instruction ( i_fetched ),
.next_i_addr ( next_i_addr ), // instruction fetched, next instruction address
.pstop_i(pstop),
.rs_fwd_sel ( if_rs_forward_control ), // forwarding control signals
.rt_fwd_sel ( id_rt_forward_control ), // forwarding control signals
.mem_fwd_val ( EX_MEM_alu_result ), // forwarded data values from MEM
.wb_fwd_val ( wreg_data ), // forwarded data values from WB
.hazard ( hazard_detected ),
.id_rs( id_rs ),
.id_rt( id_rt ),
.id_opcode( id_opcode ),
.ID_EX_A ( ID_EX_A ),
.ID_EX_B ( ID_EX_B ),
.ID_EX_rt ( ID_EX_rt ),
.ID_EX_rs ( ID_EX_rs ),
.ID_EX_rd ( ID_EX_rd ),
.ID_EX_opcode ( ID_EX_opcode ),
.ID_EX_sign_extend_offset ( ID_EX_sign_extend_offset ),
.ID_EX_wb_reg_write ( ID_EX_wb_reg_write ),
.ID_EX_wb_mem_to_reg ( ID_EX_wb_mem_to_reg ),
.ID_EX_mem_read ( ID_EX_mem_read ),
.ID_EX_mem_write ( ID_EX_mem_write ),
.ID_EX_ex_imm_command ( ID_EX_ex_imm_command ),
.ID_EX_ex_alu_src_b ( ID_EX_ex_alu_src_b ),
.ID_EX_ex_alu_rslt_src ( ID_EX_ex_alu_rslt_src ),
.ID_EX_ex_dst_reg_sel ( ID_EX_ex_dst_reg_sel ),
.ID_EX_ex_alu_op ( ID_EX_ex_alu_op ),
.branch_addr ( branch_addr ),
.jump_addr ( jump_addr ),
.id_rt_is_source ( id_rt_is_source ),
.if_pc_source ( pc_source ));
ex_stage execute_inst(
.clk ( clk ),
.rst ( rst ),
.wb_reg_write ( ID_EX_wb_reg_write ),
.wb_mem_to_reg ( ID_EX_wb_mem_to_reg ),
.mem_read ( ID_EX_mem_read ),
.pstop_i(pstop),
.mem_write ( ID_EX_mem_write ),
.ex_imm_command ( ID_EX_ex_imm_command ),
.ex_alu_src_b ( ID_EX_ex_alu_src_b ),
.ex_alu_rslt_src ( ID_EX_ex_alu_rslt_src ),
.ex_dst_reg_sel ( ID_EX_ex_dst_reg_sel ),
.ex_alu_op ( ID_EX_ex_alu_op ),
.A ( ID_EX_A ),
.B ( ID_EX_B ),
.sign_extend_offset ( ID_EX_sign_extend_offset ),
.next_i_addr ( next_i_addr ), // execute: PC + 8
.rt ( ID_EX_rt ), // target register
.rd ( ID_EX_rd ), // destination register
.opcode ( ID_EX_opcode ),
.rs_fwd_sel ( ex_rs_forward_control ), // forwarding muxes control
.rt_fwd_sel ( ex_rt_forward_control ), // forwarding muxes control
.mem_fwd_val ( EX_MEM_alu_result ), // forwarding from MEM
.wb_fwd_val ( wreg_data ), // forwarding from WB
.ex_dst_reg ( ex_dst_reg ),
.alu_a_in ( ex_reg_data_1 ),
.ex_opcode ( ex_opcode ),
.EX_MEM_alu_result ( EX_MEM_alu_result ),
.EX_MEM_B_value ( EX_MEM_B_value ),
.EX_MEM_dst_reg ( EX_MEM_dst_reg ),
.EX_MEM_opcode ( EX_MEM_opcode ),
.EX_MEM_mem_read ( EX_MEM_mem_read ),
.EX_MEM_mem_write ( EX_MEM_mem_write ),
.EX_MEM_wb_reg_write ( EX_MEM_wb_reg_write ),
.EX_MEM_wb_mem_to_reg ( EX_MEM_wb_mem_to_reg ));
mem_stage memstage_inst(
.clk ( clk ),
.rst ( rst ),
.mem_read ( EX_MEM_mem_read ),
.mem_write ( EX_MEM_mem_write ),
.alu_result ( EX_MEM_alu_result ),
.B ( EX_MEM_B_value ),
.pstop_i(pstop),
.dst_reg ( EX_MEM_dst_reg ),
.wb_reg_write ( EX_MEM_wb_reg_write ),
.wb_mem_to_reg ( EX_MEM_wb_mem_to_reg ),
.MEM_WB_dst_reg ( MEM_WB_dst_reg ),
.MEM_WB_reg_write ( MEM_WB_reg_write ),
.MEM_WB_mem_to_reg ( MEM_WB_mem_to_reg ),
.MEM_WB_mem_out ( MEM_WB_mem_out ),
.MEM_WB_alu_out ( MEM_WB_alu_out ),
.d_read_en ( d_read_en ),
.d_write_en ( d_write_en ),
.d_addr ( d_addr ),
.d_write_data ( d_write_data ),
.d_data_in ( d_data_in ));
wb_stage wb_inst(
.mem_to_reg ( MEM_WB_mem_to_reg ),
.mem_out ( MEM_WB_mem_out ),
.alu_out ( MEM_WB_alu_out ),
.write_data ( wreg_data ));
endmodule
|
module disp_ctrl (
clk,
reset_,
segments_,
digit_enable_,
addr,
cs,
req,
rnw,
wr_data,
rd_data,
rdy);
input clk;
input reset_;
output [6:0] segments_; // 7-segment display segments (active low)
output [3:0] digit_enable_; // Which digit(s) are being controlled
// This circuit provides software control over the 7-segment displays. Each
// display has two control registers, a mode register and a value register.
// They work as follows:
//
// control:
// [0] When 1, value register is a 7-bit value representing the state
// of each display segment. When 0, value register is interpreted
// as a 4-bit binary coded value (i.e., 4'b1000 displays an '8' on
// on the display).
//
// value:
// [6:0] Binary coded value (or raw segment values) to display depedning
// on control register value.
// Local address bus
input [7:0] addr;
input cs;
input req;
inout rnw;
input [7:0] wr_data;
output [7:0] rd_data;
output rdy;
reg [3:0] digit_display_mode;
reg [6:0] digit_0_value;
reg [6:0] digit_1_value;
reg [6:0] digit_2_value;
reg [6:0] digit_3_value;
reg rdy;
reg [7:0] rd_data;
wire [6:0] segments_;
wire [3:0] digit_enable_;
wire [6:0] digit_0_segments;
wire [6:0] digit_1_segments;
wire [6:0] digit_2_segments;
wire [6:0] digit_3_segments;
wire [6:0] digit_0;
wire [6:0] digit_1;
wire [6:0] digit_2;
wire [6:0] digit_3;
wire wr_enable;
wire rd_enable;
// Software addressable registers
parameter REG_DIGIT_0_MODE = 8'd0;
parameter REG_DIGIT_0_VALUE = 8'd1;
parameter REG_DIGIT_1_MODE = 8'd2;
parameter REG_DIGIT_1_VALUE = 8'd3;
parameter REG_DIGIT_2_MODE = 8'd4;
parameter REG_DIGIT_2_VALUE = 8'd5;
parameter REG_DIGIT_3_MODE = 8'd6;
parameter REG_DIGIT_3_VALUE = 8'd7;
assign wr_enable = cs && !rnw && req;
assign rd_enable = cs && rnw && req;
// Digit 0 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_0_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_0_VALUE)
digit_0_value <= wr_data[6:0];
// Digit 1 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_1_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_1_VALUE)
digit_1_value <= wr_data[6:0];
// Digit 2 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_2_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_2_VALUE)
digit_2_value <= wr_data[6:0];
// Digit 3 display value
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_3_value <= 7'h0;
else if (wr_enable && addr == REG_DIGIT_3_VALUE)
digit_3_value <= wr_data[6:0];
// Write digital display mode.
always@ (posedge clk or negedge reset_)
if (!reset_)
digit_display_mode <= 4'h0;
else if (wr_enable && addr == REG_DIGIT_0_MODE)
digit_display_mode[0] <= wr_data[0];
else if (wr_enable && addr == REG_DIGIT_1_MODE)
digit_display_mode[1] <= wr_data[1];
else if (wr_enable && addr == REG_DIGIT_2_MODE)
digit_display_mode[2] <= wr_data[2];
else if (wr_enable && addr == REG_DIGIT_3_MODE)
digit_display_mode[3] <= wr_data[3];
// Register readback
always@ (posedge clk or negedge reset_)
if (!reset_)
rd_data <= 8'h00;
else if (rd_enable)
rd_data <= (addr == REG_DIGIT_0_VALUE) ? {1'h0, digit_0_value} :
(addr == REG_DIGIT_1_VALUE) ? {1'h0, digit_1_value} :
(addr == REG_DIGIT_2_VALUE) ? {1'h0, digit_2_value} :
(addr == REG_DIGIT_3_VALUE) ? {1'h0, digit_3_value} :
(addr == REG_DIGIT_0_MODE) ? {7'h0, digit_display_mode[0]} :
(addr == REG_DIGIT_1_MODE) ? {7'h0, digit_display_mode[1]} :
(addr == REG_DIGIT_2_MODE) ? {7'h0, digit_display_mode[2]} :
(addr == REG_DIGIT_3_MODE) ? {7'h0, digit_display_mode[3]} :
8'h00;
// Readback ready generation
always@ (posedge clk or negedge reset_)
if (!reset_)
rdy <= 1'b0;
else
rdy <= req;
// Binary coded decimal to 7-segment display coders
bcdcoder digit0_coder (
.segment(digit_0_segments),
.bcd(digit_0_value[3:0])
);
bcdcoder digit1_coder (
.segment(digit_1_segments),
.bcd(digit_1_value[3:0])
);
bcdcoder digit2_coder (
.segment(digit_2_segments),
.bcd(digit_2_value[3:0])
);
bcdcoder digit3_coder (
.segment(digit_3_segments),
.bcd(digit_3_value[3:0])
);
// When display mode is 1, we interpret digit value as raw segment enables;
// otherwise, assume digit value is BCD (display a number between 0..9)
assign digit_0 = digit_display_mode[0] ? digit_0_value[6:0] : digit_0_segments;
assign digit_1 = digit_display_mode[1] ? digit_1_value[6:0] : digit_1_segments;
assign digit_2 = digit_display_mode[2] ? digit_2_value[6:0] : digit_2_segments;
assign digit_3 = digit_display_mode[3] ? digit_3_value[6:0] : digit_3_segments;
// Display driver instantiation
displaydriver displaydriver (
.clk(clk),
.reset_(reset_),
.digit_0(digit_0),
.digit_1(digit_1),
.digit_2(digit_2),
.digit_3(digit_3),
.segment_(segments_),
.digit_enable_(digit_enable_)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_vip_v1_0_3_unused_ports.v
*
* Date : 2012-11
*
* Description : Semantic checks for unused ports.
*
*****************************************************************************/
/* CAN */
assign CAN0_PHY_TX = 0;
assign CAN1_PHY_TX = 0;
always @(CAN0_PHY_RX or CAN1_PHY_RX)
begin
if(CAN0_PHY_RX | CAN1_PHY_RX)
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* ETHERNET */
/* ------------------------------------------- */
assign ENET0_GMII_TX_EN = 0;
assign ENET0_GMII_TX_ER = 0;
assign ENET0_MDIO_MDC = 0;
assign ENET0_MDIO_O = 0; /// confirm
assign ENET0_MDIO_T = 0;
assign ENET0_PTP_DELAY_REQ_RX = 0;
assign ENET0_PTP_DELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_REQ_RX = 0;
assign ENET0_PTP_PDELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_RESP_RX = 0;
assign ENET0_PTP_PDELAY_RESP_TX = 0;
assign ENET0_PTP_SYNC_FRAME_RX = 0;
assign ENET0_PTP_SYNC_FRAME_TX = 0;
assign ENET0_SOF_RX = 0;
assign ENET0_SOF_TX = 0;
assign ENET0_GMII_TXD = 0;
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
begin
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
assign ENET1_GMII_TX_EN = 0;
assign ENET1_GMII_TX_ER = 0;
assign ENET1_MDIO_MDC = 0;
assign ENET1_MDIO_O = 0;/// confirm
assign ENET1_MDIO_T = 0;
assign ENET1_PTP_DELAY_REQ_RX = 0;
assign ENET1_PTP_DELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_REQ_RX = 0;
assign ENET1_PTP_PDELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_RESP_RX = 0;
assign ENET1_PTP_PDELAY_RESP_TX = 0;
assign ENET1_PTP_SYNC_FRAME_RX = 0;
assign ENET1_PTP_SYNC_FRAME_TX = 0;
assign ENET1_SOF_RX = 0;
assign ENET1_SOF_TX = 0;
assign ENET1_GMII_TXD = 0;
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
begin
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* GPIO */
/* ------------------------------------------- */
assign GPIO_O = 0;
assign GPIO_T = 0;
always@(GPIO_I)
begin
if(GPIO_I !== 0)
$display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* I2C */
/* ------------------------------------------- */
assign I2C0_SDA_O = 0;
assign I2C0_SDA_T = 0;
assign I2C0_SCL_O = 0;
assign I2C0_SCL_T = 0;
assign I2C1_SDA_O = 0;
assign I2C1_SDA_T = 0;
assign I2C1_SCL_O = 0;
assign I2C1_SCL_T = 0;
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
begin
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* JTAG */
/* ------------------------------------------- */
assign PJTAG_TD_T = 0;
assign PJTAG_TD_O = 0;
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
begin
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SDIO */
/* ------------------------------------------- */
assign SDIO0_CLK = 0;
assign SDIO0_CMD_O = 0;
assign SDIO0_CMD_T = 0;
assign SDIO0_DATA_O = 0;
assign SDIO0_DATA_T = 0;
assign SDIO0_LED = 0;
assign SDIO0_BUSPOW = 0;
assign SDIO0_BUSVOLT = 0;
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
begin
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
assign SDIO1_CLK = 0;
assign SDIO1_CMD_O = 0;
assign SDIO1_CMD_T = 0;
assign SDIO1_DATA_O = 0;
assign SDIO1_DATA_T = 0;
assign SDIO1_LED = 0;
assign SDIO1_BUSPOW = 0;
assign SDIO1_BUSVOLT = 0;
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
begin
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SPI */
/* ------------------------------------------- */
assign SPI0_SCLK_O = 0;
assign SPI0_SCLK_T = 0;
assign SPI0_MOSI_O = 0;
assign SPI0_MOSI_T = 0;
assign SPI0_MISO_O = 0;
assign SPI0_MISO_T = 0;
assign SPI0_SS_O = 0; /// confirm
assign SPI0_SS1_O = 0;/// confirm
assign SPI0_SS2_O = 0;/// confirm
assign SPI0_SS_T = 0;
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
begin
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
assign SPI1_SCLK_O = 0;
assign SPI1_SCLK_T = 0;
assign SPI1_MOSI_O = 0;
assign SPI1_MOSI_T = 0;
assign SPI1_MISO_O = 0;
assign SPI1_MISO_T = 0;
assign SPI1_SS_O = 0;
assign SPI1_SS1_O = 0;
assign SPI1_SS2_O = 0;
assign SPI1_SS_T = 0;
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
begin
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* UART */
/* ------------------------------------------- */
/// confirm
assign UART0_DTRN = 0;
assign UART0_RTSN = 0;
assign UART0_TX = 0;
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
begin
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
assign UART1_DTRN = 0;
assign UART1_RTSN = 0;
assign UART1_TX = 0;
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
begin
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TTC */
/* ------------------------------------------- */
assign TTC0_WAVE0_OUT = 0;
assign TTC0_WAVE1_OUT = 0;
assign TTC0_WAVE2_OUT = 0;
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
begin
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
assign TTC1_WAVE0_OUT = 0;
assign TTC1_WAVE1_OUT = 0;
assign TTC1_WAVE2_OUT = 0;
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
begin
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* WDT */
/* ------------------------------------------- */
assign WDT_RST_OUT = 0;
always@(WDT_CLK_IN)
begin
if(WDT_CLK_IN)
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TRACE */
/* ------------------------------------------- */
assign TRACE_CTL = 0;
assign TRACE_DATA = 0;
always@(TRACE_CLK)
begin
if(TRACE_CLK)
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* USB */
/* ------------------------------------------- */
assign USB0_PORT_INDCTL = 0;
assign USB0_VBUS_PWRSELECT = 0;
always@(USB0_VBUS_PWRFAULT)
begin
if(USB0_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
assign USB1_PORT_INDCTL = 0;
assign USB1_VBUS_PWRSELECT = 0;
always@(USB1_VBUS_PWRFAULT)
begin
if(USB1_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
always@(SRAM_INTIN)
begin
if(SRAM_INTIN)
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DMA */
/* ------------------------------------------- */
assign DMA0_DATYPE = 0;
assign DMA0_DAVALID = 0;
assign DMA0_DRREADY = 0;
assign DMA0_RSTN = 0;
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
begin
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA1_DATYPE = 0;
assign DMA1_DAVALID = 0;
assign DMA1_DRREADY = 0;
assign DMA1_RSTN = 0;
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
begin
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA2_DATYPE = 0;
assign DMA2_DAVALID = 0;
assign DMA2_DRREADY = 0;
assign DMA2_RSTN = 0;
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
begin
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA3_DATYPE = 0;
assign DMA3_DAVALID = 0;
assign DMA3_DRREADY = 0;
assign DMA3_RSTN = 0;
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
begin
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FTM */
/* ------------------------------------------- */
assign FTMT_F2P_TRIGACK = 0;
assign FTMT_P2F_TRIG = 0;
assign FTMT_P2F_DEBUG = 0;
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
begin
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* EVENT */
/* ------------------------------------------- */
assign EVENT_EVENTO = 0;
assign EVENT_STANDBYWFE = 0;
assign EVENT_STANDBYWFI = 0;
always@(EVENT_EVENTI)
begin
if(EVENT_EVENTI)
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MIO */
/* ------------------------------------------- */
always@(MIO)
begin
if(MIO !== 0)
$display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FCLK_TRIG */
/* ------------------------------------------- */
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
begin
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MISC */
/* ------------------------------------------- */
always@(FPGA_IDLE_N)
begin
if(FPGA_IDLE_N)
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
end
always@(DDR_ARB)
begin
if(DDR_ARB !== 0)
$display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
end
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
begin
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DDR */
/* ------------------------------------------- */
assign DDR_WEB = 0;
always@(DDR_Clk or DDR_CS_n)
begin
if(!DDR_CS_n)
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* IRQ_P2F */
/* ------------------------------------------- */
assign IRQ_P2F_DMAC_ABORT = 0;
assign IRQ_P2F_DMAC0 = 0;
assign IRQ_P2F_DMAC1 = 0;
assign IRQ_P2F_DMAC2 = 0;
assign IRQ_P2F_DMAC3 = 0;
assign IRQ_P2F_DMAC4 = 0;
assign IRQ_P2F_DMAC5 = 0;
assign IRQ_P2F_DMAC6 = 0;
assign IRQ_P2F_DMAC7 = 0;
assign IRQ_P2F_SMC = 0;
assign IRQ_P2F_QSPI = 0;
assign IRQ_P2F_CTI = 0;
assign IRQ_P2F_GPIO = 0;
assign IRQ_P2F_USB0 = 0;
assign IRQ_P2F_ENET0 = 0;
assign IRQ_P2F_ENET_WAKE0 = 0;
assign IRQ_P2F_SDIO0 = 0;
assign IRQ_P2F_I2C0 = 0;
assign IRQ_P2F_SPI0 = 0;
assign IRQ_P2F_UART0 = 0;
assign IRQ_P2F_CAN0 = 0;
assign IRQ_P2F_USB1 = 0;
assign IRQ_P2F_ENET1 = 0;
assign IRQ_P2F_ENET_WAKE1 = 0;
assign IRQ_P2F_SDIO1 = 0;
assign IRQ_P2F_I2C1 = 0;
assign IRQ_P2F_SPI1 = 0;
assign IRQ_P2F_UART1 = 0;
assign IRQ_P2F_CAN1 = 0;
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_stredEe_DSP48_2(
input [8 - 1:0] in0,
input [23 - 1:0] in1,
input [29 - 1:0] in2,
output [30 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in1);
assign b = $unsigned(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_stredEe(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_stredEe_DSP48_2 hls_contrast_stredEe_DSP48_2_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_1_V
`define SKY130_FD_SC_HVL__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_1_V
|
module audio_buffer ( rclk, // read from avalon bus
wclk, // write to audio_effects
reset,
audio_ip,
read, //sample_req from audio_codec
audio_out,
audio_irq
);
input rclk,wclk,reset,read;
input [15:0] audio_ip;
output [15:0] audio_out;
output audio_irq;
reg [15:0] buffer1 [0:99];
reg [15:0] buffer2 [0:99];
reg [6:0] indexr = 7'd0;
reg [6:0] indexr_prev = 7'd0;
reg [6:0] indexw = 7'd0;
reg buf_cnt = 1'b0;
reg start_read;
reg irq;
reg irq_prev;
wire irq_edge;
reg [15:0] audio_out;
assign audio_irq = irq;
always @(posedge rclk)
irq_prev<= audio_irq;
assign irq_edge = audio_irq & (~irq_prev);
always @(posedge rclk) begin
if (reset ) begin
start_read <= 0;
indexr <= 7'd00;
end else if (irq_edge)
indexr_prev <= 0;
else if (indexr_prev < 100) begin
start_read <= 1'd1;
indexr_prev <= indexr;
indexr <= indexr + 1'b1;
end else begin
start_read <= 1'd0;
indexr <= 0;
end
end
always @(posedge rclk) begin
if (start_read) begin // write enable for buffer
if (buf_cnt==0)
buffer1[indexr] <= audio_ip;
else
buffer2[indexr] <= audio_ip;
end
end
always @(posedge wclk) begin
if (reset ) begin
indexw <= 7'd00;
irq <= 0;
end
else if (read) begin
if (indexw == 7'd99) begin
indexw <= 7'd00;
buf_cnt <= buf_cnt + 1'b1;
irq <= 1;
end
else begin
indexw <= indexw + 1'b1;
irq <= 0;
end
if (buf_cnt==0)
audio_out <= buffer2[indexw];
else
audio_out <= buffer1[indexw];
end
end
endmodule
|
/**
* bsg_cache_dma.v
*
* DMA engine.
*
* @author tommy
*
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_cache_dma
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter `BSG_INV_PARAM(sets_p)
,parameter `BSG_INV_PARAM(ways_p)
,parameter dma_data_width_p=data_width_p
,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
,parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
,parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
,parameter data_mask_width_lp=(data_width_p>>3)
,parameter dma_data_mask_width_lp=(dma_data_width_p>>3)
,parameter burst_len_lp=(block_size_in_words_p*data_width_p/dma_data_width_p)
,parameter lg_burst_len_lp=`BSG_SAFE_CLOG2(burst_len_lp)
,parameter burst_size_in_words_lp=(dma_data_width_p/data_width_p)
,parameter lg_burst_size_in_words_lp=`BSG_SAFE_CLOG2(burst_size_in_words_lp)
,parameter data_mem_els_lp=(sets_p*burst_len_lp)
,parameter lg_data_mem_els_lp=`BSG_SAFE_CLOG2(data_mem_els_lp)
,parameter bsg_cache_dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
,parameter debug_p=0
)
(
input clk_i
,input reset_i
,input bsg_cache_dma_cmd_e dma_cmd_i
,input [lg_ways_lp-1:0] dma_way_i
,input [addr_width_p-1:0] dma_addr_i
,output logic done_o
,output logic [data_width_p-1:0] snoop_word_o
,output logic [bsg_cache_dma_pkt_width_lp-1:0] dma_pkt_o
,output logic dma_pkt_v_o
,input dma_pkt_yumi_i
,input [dma_data_width_p-1:0] dma_data_i
,input dma_data_v_i
,output logic dma_data_ready_o
,output logic [dma_data_width_p-1:0] dma_data_o
,output logic dma_data_v_o
,input dma_data_yumi_i
,output logic data_mem_v_o
,output logic data_mem_w_o
,output logic [lg_data_mem_els_lp-1:0] data_mem_addr_o
,output logic [ways_p-1:0][dma_data_mask_width_lp-1:0] data_mem_w_mask_o
,output logic [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_o
,input [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_i
,output logic dma_evict_o // data eviction in progress
);
// localparam
//
localparam counter_width_lp=`BSG_SAFE_CLOG2(burst_len_lp+1);
localparam byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3);
localparam block_offset_width_lp=(block_size_in_words_p > 1) ? byte_offset_width_lp+lg_block_size_in_words_lp : byte_offset_width_lp;
// dma states
//
typedef enum logic [1:0] {
IDLE
,GET_FILL_DATA
,SEND_EVICT_DATA
} dma_state_e;
dma_state_e dma_state_n;
dma_state_e dma_state_r;
// dma counter
//
logic counter_clear;
logic counter_up;
logic [counter_width_lp-1:0] counter_r;
bsg_counter_clear_up #(
.max_val_p(burst_len_lp)
) dma_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(counter_r)
);
wire counter_fill_max = counter_r == (burst_len_lp-1);
wire counter_evict_max = counter_r == burst_len_lp;
// dma packet
//
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_dma_pkt_s dma_pkt;
// in fifo
//
logic in_fifo_v_lo;
logic [dma_data_width_p-1:0] in_fifo_data_lo;
logic in_fifo_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(dma_data_width_p)
,.els_p((burst_len_lp<2) ? 2 : burst_len_lp)
) in_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_data_i)
,.v_i(dma_data_v_i)
,.ready_o(dma_data_ready_o)
,.v_o(in_fifo_v_lo)
,.data_o(in_fifo_data_lo)
,.yumi_i(in_fifo_yumi_li)
);
// out fifo
//
logic out_fifo_v_li;
logic out_fifo_ready_lo;
logic [dma_data_width_p-1:0] out_fifo_data_li;
bsg_two_fifo #(
.width_p(dma_data_width_p)
) out_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(out_fifo_v_li)
,.data_i(out_fifo_data_li)
,.ready_o(out_fifo_ready_lo)
,.v_o(dma_data_v_o)
,.data_o(dma_data_o)
,.yumi_i(dma_data_yumi_i)
);
assign dma_pkt_o = dma_pkt;
logic [ways_p-1:0] dma_way_mask;
bsg_decode #(
.num_out_p(ways_p)
) dma_way_demux (
.i(dma_way_i)
,.o(dma_way_mask)
);
bsg_expand_bitmask #(
.in_width_p(ways_p)
,.expand_p(dma_data_mask_width_lp)
) expand0 (
.i(dma_way_mask)
,.o(data_mem_w_mask_o)
);
if (burst_len_lp == 1) begin
assign data_mem_addr_o = dma_addr_i[block_offset_width_lp+:lg_sets_lp];
end
//else if (burst_len_lp == block_size_in_words_p) begin
// assign data_mem_addr_o = {
// dma_addr_i[block_offset_width_lp+:lg_sets_lp],
// counter_r[0+:lg_burst_len_lp]
// };
//end
else begin
assign data_mem_addr_o = {
dma_addr_i[block_offset_width_lp+:lg_sets_lp],
counter_r[0+:lg_burst_len_lp]
};
end
assign data_mem_data_o = {ways_p{in_fifo_data_lo}};
bsg_mux #(
.width_p(dma_data_width_p)
,.els_p(ways_p)
) write_data_mux (
.data_i(data_mem_data_i)
,.sel_i(dma_way_i)
,.data_o(out_fifo_data_li)
);
always_comb begin
done_o = 1'b0;
dma_pkt_v_o = 1'b0;
dma_pkt.write_not_read = 1'b0;
dma_pkt.addr = {
dma_addr_i[addr_width_p-1:block_offset_width_lp],
{(block_offset_width_lp){1'b0}}
};
data_mem_v_o = 1'b0;
data_mem_w_o = 1'b0;
in_fifo_yumi_li = 1'b0;
dma_state_n = IDLE;
out_fifo_v_li = 1'b0;
counter_clear = 1'b0;
counter_up = 1'b0;
dma_evict_o = 1'b0;
case (dma_state_r)
// wait for dma_cmd from bsg_cache_miss.
// when transitioning from GET_FILL_DATA or SEND_EVICT_DATA state,
// make sure that counter is cleared to zero.
IDLE: begin
counter_clear = 1'b0;
counter_up = 1'b0;
data_mem_v_o = 1'b0;
dma_pkt_v_o = 1'b0;
dma_pkt.write_not_read = 1'b0;
done_o = 1'b0;
dma_state_n = IDLE;
case (dma_cmd_i)
e_dma_send_fill_addr: begin
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b0;
done_o = dma_pkt_yumi_i;
dma_state_n = IDLE;
end
e_dma_send_evict_addr: begin
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b1;
done_o = dma_pkt_yumi_i;
dma_state_n = IDLE;
end
e_dma_get_fill_data: begin
counter_clear = 1'b1;
dma_state_n = GET_FILL_DATA;
end
e_dma_send_evict_data: begin
// we are reading the first word, as we are transitioning out.
// so the counter is incremented to 1.
counter_clear = 1'b1;
counter_up = 1'b1;
data_mem_v_o = 1'b1;
dma_state_n = SEND_EVICT_DATA;
end
e_dma_nop: begin
// nothing happens.
end
default: begin
// this should never happen.
end
endcase
end
// receive the block data from dma_data_i
// and write into data_mem word by word.
GET_FILL_DATA: begin
dma_state_n = counter_fill_max & in_fifo_v_lo
? IDLE
: GET_FILL_DATA;
data_mem_v_o = in_fifo_v_lo;
data_mem_w_o = in_fifo_v_lo;
in_fifo_yumi_li = in_fifo_v_lo;
counter_up = in_fifo_v_lo & ~counter_fill_max;
counter_clear = in_fifo_v_lo & counter_fill_max;
done_o = counter_fill_max & in_fifo_v_lo;
end
// read the requested block from data_mem and send it out over
// dma_data_o word by word.
SEND_EVICT_DATA: begin
// counter_r in this context means the number of words read from
// data_mem so far.
dma_state_n = counter_evict_max & out_fifo_ready_lo
? IDLE
: SEND_EVICT_DATA;
counter_up = out_fifo_ready_lo & ~counter_evict_max;
counter_clear = out_fifo_ready_lo & counter_evict_max;
out_fifo_v_li = 1'b1;
data_mem_v_o = out_fifo_ready_lo & ~counter_evict_max;
done_o = counter_evict_max & out_fifo_ready_lo;
dma_evict_o = 1'b1;
end
default: begin
// this should never happen, but if it does, then go back to IDLE.
dma_state_n = IDLE;
end
endcase
end
// snoop_word register
// As the fill data is coming in, grab the word that matches the block
// offset, so that we don't have to read the data_mem again to return the
// load data.
logic [lg_burst_size_in_words_lp-1:0] snoop_word_offset;
logic snoop_word_we;
logic [data_width_p-1:0] snoop_word_n;
assign snoop_word_offset = dma_addr_i[byte_offset_width_lp+:lg_burst_size_in_words_lp];
if (burst_len_lp == 1) begin
assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo;
end
else if (burst_len_lp == block_size_in_words_p) begin
assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo
& (counter_r[0+:lg_burst_len_lp] == dma_addr_i[byte_offset_width_lp+:lg_burst_len_lp]);
end
else begin
assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo
& (counter_r[0+:lg_burst_len_lp] == dma_addr_i[byte_offset_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp]);
end
bsg_mux #(
.width_p(data_width_p)
,.els_p(burst_size_in_words_lp)
) snoop_mux0 (
.data_i(in_fifo_data_lo)
,.sel_i(snoop_word_offset)
,.data_o(snoop_word_n)
);
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
dma_state_r <= IDLE;
end
else begin
dma_state_r <= dma_state_n;
if (snoop_word_we) begin
snoop_word_o <= snoop_word_n;
end
end
end
// synopsys translate_off
always_ff @ (posedge clk_i) begin
if (debug_p) begin
if (dma_pkt_v_o & dma_pkt_yumi_i) begin
$display("<VCACHE> DMA_PKT we:%0d addr:%8h // %8t",
dma_pkt.write_not_read, dma_pkt.addr, $time);
end
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_dma)
|
/***************************************************************************************************
** fpga_nes/hw/src/cart/cart.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Cartridge emulator for an fpga-based NES emulator. This block provides access to cartridge
* memories (PRG-ROM, CHR-ROM) and emulates mapper functionality in order to play emulation ROMs.
* The intention is that this interface could be re-implemented on top of a hardware NES
* cartridge, where almost all of the work would pass through directly.
***************************************************************************************************/
module cart (
input clk_in, // system clock signal
// Mapper config data.
input [39:0] cfg_in, // cartridge config (from iNES header)
input cfg_upd_in, // pulse signal on cfg_in update
// PRG-ROM interface.
input prg_nce_in, // prg-rom chip enable (active low)
input [14:0] prg_a_in, // prg-rom address
input prg_r_nw_in, // prg-rom read/write select
input [ 7:0] prg_d_in, // prg-rom data in
output [ 7:0] prg_d_out, // prg-rom data out
// CHR-ROM interface.
input [13:0] chr_a_in, // chr-rom address
input chr_r_nw_in, // chr-rom read/write select
input [ 7:0] chr_d_in, // chr-rom data in
output [ 7:0] chr_d_out, // chr-rom data out
output ciram_nce_out, // vram chip enable (active low)
output ciram_a10_out // vram a10 value (controls mirroring)
);
wire prgrom_bram_we;
wire [14:0] prgrom_bram_a;
wire [7:0] prgrom_bram_dout;
// Block ram instance for PRG-ROM memory range (0x8000 - 0xFFFF). Will eventually be
// replaced with SRAM.
single_port_ram_sync #(
.ADDR_WIDTH (15 ),
.DATA_WIDTH (8 ))
prgrom_bram (
.clk (clk_in ),
.we (prgrom_bram_we ),
.addr_a (prgrom_bram_a ),
.din_a (prg_d_in ),
.dout_a (prgrom_bram_dout )
);
assign prgrom_bram_we = (~prg_nce_in) ? ~prg_r_nw_in : 1'b0;
assign prg_d_out = (~prg_nce_in) ? prgrom_bram_dout : 8'h00;
assign prgrom_bram_a = (cfg_in[33]) ? prg_a_in[14:0] : { 1'b0, prg_a_in[13:0] };
wire chrrom_pat_bram_we;
wire [7:0] chrrom_pat_bram_dout;
// Block ram instance for "CHR Pattern Table" memory range (0x0000 - 0x1FFF).
single_port_ram_sync #(
.ADDR_WIDTH (13 ),
.DATA_WIDTH (8 ))
chrrom_pat_bram (
.clk (clk_in ),
.we (chrrom_pat_bram_we ),
.addr_a (chr_a_in[12:0] ),
.din_a (chr_d_in ),
.dout_a (chrrom_pat_bram_dout )
);
assign ciram_nce_out = ~chr_a_in[13];
assign ciram_a10_out = (cfg_in[16]) ? chr_a_in[10] : chr_a_in[11];
assign chrrom_pat_bram_we = (ciram_nce_out) ? ~chr_r_nw_in : 1'b0;
assign chr_d_out = (ciram_nce_out) ? chrrom_pat_bram_dout : 8'h00;
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHa2.
SSCase "n <> 0". simpl. rewrite IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
Case "AMinus".
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Case "AMult".
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| b => b
end.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intro b.
induction b;
try (simpl;
rewrite optimize_0plus_sound;
rewrite optimize_0plus_sound);
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
*)
Fixpoint optimize_my (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum n1) (ANum n2) =>
ANum (n1 + n2)
| AMinus (ANum n1) (ANum n2) =>
ANum (n1 - n2)
| AMult (ANum n1) (ANum n2) =>
ANum (n1 * n2)
| a => a
end.
Theorem optimize_my_sound: forall a,
aeval (optimize_my a) = aeval a.
Proof.
intro a.
induction a;
try reflexivity;
try (destruct a1; destruct a2; reflexivity).
Qed.
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Leibniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
Inductive bevalR: bexp -> bool -> Prop :=
| E_BTrue : bevalR BTrue true
| E_BFalse : bevalR BFalse false
| E_BEq : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 -> aevalR e2 n2 ->
bevalR (BEq e1 e2) (beq_nat n1 n2)
| E_BLe : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 -> aevalR e2 n2 ->
bevalR (BLe e1 e2) (ble_nat n1 n2)
| E_BNot : forall (e: bexp) (b: bool),
bevalR e b -> bevalR (BNot e) (negb b)
| E_BAnd : forall (e1 e2: bexp) (b1 b2: bool),
bevalR e1 b1 -> bevalR e2 b2 -> bevalR (BAnd e1 e2) (b1 && b2).
Theorem beval_iff_bevalR : forall e b,
bevalR e b <-> beval e = b.
Proof.
split.
Case "->".
intro H.
induction H.
reflexivity. reflexivity.
apply aeval_iff_aevalR in H.
apply aeval_iff_aevalR in H0.
subst. reflexivity.
apply aeval_iff_aevalR in H.
apply aeval_iff_aevalR in H0.
subst. reflexivity.
simpl. subst. reflexivity.
simpl. subst. reflexivity.
Case "<-".
generalize dependent b.
induction e.
intros. destruct b. constructor. inversion H.
intros. destruct b. inversion H. constructor.
SCase "EQ".
intros. simpl in H. rewrite <-H. constructor.
apply aeval_iff_aevalR. reflexivity.
apply aeval_iff_aevalR. reflexivity.
SCase "LE".
intros. simpl in H. rewrite <-H. constructor.
apply aeval_iff_aevalR. reflexivity.
apply aeval_iff_aevalR. reflexivity.
SCase "NOT".
intros. simpl in H. rewrite <-H. constructor.
apply IHe. reflexivity.
SCase "AND".
intros. simpl in H. rewrite <-H. constructor.
apply IHe1. reflexivity. apply IHe2. reflexivity.
Qed.
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
intros.
destruct (eq_id_dec x y).
apply ex_falso_quodlibet. apply H. apply e.
reflexivity.
Qed.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
intros.
unfold update.
rewrite eq_id. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
intros.
unfold update.
rewrite neq_id. reflexivity. apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
intros.
unfold update.
rewrite neq_id.
reflexivity.
intro contra. inversion contra.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
intros.
unfold update at 1.
destruct (eq_id_dec x2 x1).
rewrite e. symmetry. apply update_eq.
unfold update.
rewrite neq_id. rewrite neq_id. reflexivity. apply n. apply n.
Qed.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
intros.
unfold update.
destruct (eq_id_dec x1 x2).
rewrite <-H. rewrite e. reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
intros.
unfold update.
destruct (eq_id_dec x1 x3).
rewrite <-e. symmetry. apply neq_id. apply H.
reflexivity.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
apply E_Seq with (update empty_state X 0).
apply E_Ass. reflexivity.
apply E_Seq with (update (update empty_state X 0) Y 1).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
Y ::= ANum 0;;
WHILE BNot (BEq (AId X) (ANum 0)) DO
Y ::= APlus (AId Y) (AId X);;
X ::= AMinus (AId X) (ANum 1)
END.
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
unfold pup_to_n.
apply E_Seq with (update (update empty_state X 2) Y 0).
apply E_Ass. reflexivity.
apply E_WhileLoop with (update (update (update (update empty_state X 2) Y 0) Y 2) X 1).
reflexivity.
apply E_Seq with (update (update (update empty_state X 2) Y 0) Y 2).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
apply E_WhileLoop with (update (update (update (update (update (update empty_state X 2) Y 0) Y 2) X 1) Y 3) X 0).
reflexivity.
apply E_Seq with (update (update (update (update (update empty_state X 2) Y 0) Y 2) X 1) Y 3).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
apply E_WhileEnd.
reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
Theorem XtimesYinZ_spec : forall st n m st',
st X = n ->
st Y = m ->
XtimesYinZ / st || st' ->
st' Z = n * m.
Proof.
intros.
inversion H1. subst.
simpl. apply update_eq.
Qed.
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
induction contra.
inversion Heqloopdef.
inversion Heqloopdef.
inversion Heqloopdef.
inversion Heqloopdef.
inversion Heqloopdef.
inversion Heqloopdef.
rewrite H1 in H. inversion H.
apply IHcontra2. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
| nw_skip : no_whilesR SKIP
| nw_ass : forall x a, no_whilesR (x ::= a)
| nw_seq : forall c1 c2, no_whilesR c1 -> no_whilesR c2 ->
no_whilesR (c1 ;; c2)
| nw_if : forall b c1 c2, no_whilesR c1 -> no_whilesR c2 ->
no_whilesR (IFB b THEN c1 ELSE c2 FI).
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
split.
Case "->".
intro H. induction c. constructor. constructor.
inversion H. apply andb_true_iff in H1. inversion H1.
constructor. apply IHc1. assumption. apply IHc2. assumption.
inversion H. apply andb_true_iff in H1. inversion H1.
constructor. apply IHc1. assumption. apply IHc2. assumption.
inversion H.
Case "<-".
intro H. induction c. constructor. constructor.
inversion H. simpl. apply andb_true_iff. split.
apply IHc1. assumption. apply IHc2. assumption.
inversion H. simpl. apply andb_true_iff. split.
apply IHc1. assumption. apply IHc2. assumption.
inversion H.
Qed.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
Theorem no_whiles_stops : forall c st,
no_whiles c = true -> exists st', c / st || st'.
Proof.
intro c.
com_cases (induction c) Case; intros.
Case "SKIP". exists st. constructor.
Case "::=".
exists (update st i (aeval st a)).
constructor. reflexivity.
Case ";;".
inversion H. apply andb_true_iff in H1. inversion H1.
apply (IHc1 st) in H0. inversion H0.
apply (IHc2 x) in H2. inversion H2.
exists x0.
apply E_Seq with (st':=x). assumption. assumption.
Case "IFB".
inversion H. apply andb_true_iff in H1. inversion H1.
destruct (beval st b) eqn:HB.
apply (IHc1 st) in H0. inversion H0.
exists x. apply E_IfTrue. assumption. assumption.
apply (IHc2 st) in H2. inversion H2.
exists x. apply E_IfFalse. assumption. assumption.
Case "WHILE".
inversion H.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
match prog with
| [] => stack
| SPush n :: prog' => s_execute st (n :: stack) prog'
| SLoad id :: prog' => s_execute st (st id :: stack) prog'
| SPlus :: prog' => match stack with
| b :: a :: stack' =>
s_execute st (a + b :: stack') prog'
| _ => stack
end
| SMinus :: prog' => match stack with
| b :: a :: stack' =>
s_execute st (a - b :: stack') prog'
| _ => stack
end
| SMult :: prog' => match stack with
| b :: a :: stack' =>
s_execute st (a * b :: stack') prog'
| _ => stack
end
end.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
Proof. reflexivity. Qed.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
Proof. reflexivity. Qed.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
match e with
| AId id => [SLoad id]
| ANum n => [SPush n]
| APlus a1 a2 => s_compile a1 ++ s_compile a2 ++ [SPlus]
| AMinus a1 a2 => s_compile a1 ++ s_compile a2 ++ [SMinus]
| AMult a1 a2 => s_compile a1 ++ s_compile a2 ++ [SMult]
end.
(** After you've defined [s_compile], uncomment the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
calculator implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
(* ref: github.com/github/linguist *)
Theorem s_compile_step : forall e st stack (prog : list sinstr),
s_execute st stack (s_compile e ++ prog) =
s_execute st ((aeval st e) :: stack) prog.
Proof.
aexp_cases (induction e) Case; try reflexivity.
Case "APlus".
intros; simpl; rewrite app_ass; rewrite app_ass.
assert (forall prog',
s_execute st stack (s_compile e1 ++ s_compile e2 ++ prog') =
s_execute st (aeval st e1 :: stack) (s_compile e2 ++ prog')).
intro prog'; apply IHe1.
rewrite H; apply IHe2.
Case "AMinus".
intros; simpl; rewrite app_ass; rewrite app_ass.
assert (forall prog',
s_execute st stack (s_compile e1 ++ s_compile e2 ++ prog') =
s_execute st (aeval st e1 :: stack) (s_compile e2 ++ prog')).
intro prog'; apply IHe1.
rewrite H; apply IHe2.
Case "AMult".
intros; simpl; rewrite app_ass; rewrite app_ass.
assert (forall prog',
s_execute st stack (s_compile e1 ++ s_compile e2 ++ prog') =
s_execute st (aeval st e1 :: stack) (s_compile e2 ++ prog')).
intro prog'; apply IHe1.
rewrite H; apply IHe2.
Qed.
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
aexp_cases (induction e) Case; try reflexivity;
simpl; rewrite s_compile_step; rewrite s_compile_step; reflexivity.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;;
Y ::= 1;;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;;
X ::= 1;;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
| E_Break : forall st,
CBreak / st || SBreak / st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || SContinue / (update st x n)
| E_IfTrue : forall st st' sg b c1 c2,
beval st b = true ->
c1 / st || sg / st' ->
(IFB b THEN c1 ELSE c2 FI) / st || sg / st'
| E_IfFalse : forall st st' sg b c1 c2,
beval st b = false ->
c2 / st || sg / st' ->
(IFB b THEN c1 ELSE c2 FI) / st || sg / st'
| E_Seq_Break : forall c1 c2 st st',
c1 / st || SBreak / st' ->
(c1 ;; c2) / st || SBreak / st'
| E_Seq_Continue : forall c1 c2 st st' st'' sg'',
c1 / st || SContinue / st' ->
c2 / st' || sg'' / st'' ->
(c1 ;; c2) / st || sg'' / st''
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || SContinue / st
| E_WhileLoop_Break : forall st st' b c,
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'
| E_WhileLoop_Continue : forall st st' st'' b c,
beval st b = true ->
c / st || SContinue / st' ->
(WHILE b DO c END) / st' || SContinue / st'' ->
(WHILE b DO c END) / st || SContinue / st''
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
| Case_aux c "E_Break"
| Case_aux c "E_Ass"
| Case_aux c "E_IfTrue"
| Case_aux c "E_IfFalse"
| Case_aux c "E_Seq_Break"
| Case_aux c "E_Seq_Continue"
| Case_aux c "E_WhileEnd"
| Case_aux c "E_WhileLoop_Break"
| Case_aux c "E_WhileLoop_Continue"
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK;; c) / st || s / st' ->
st = st'.
Proof.
intros.
inversion H. inversion H5. reflexivity.
inversion H2.
Qed.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
intros.
inversion H; reflexivity.
Qed.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
intros.
constructor. assumption. assumption.
Qed.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
(* ref: github.com/haklabbeograd *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
intros.
(* otherwise, [induction] will throw out infomation! *)
remember (WHILE b DO c END) as loop.
induction H; inversion Heqloop; subst.
rewrite H in H0. inversion H0.
exists st. assumption.
apply IHceval2. reflexivity. assumption.
Qed.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
(* follow the original [ceval_deterministic] *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
intros c st st1 st2 s1 s2 E1 E2.
generalize dependent s2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 s2 E2; inversion E2; subst.
Case "E_Skip". split. reflexivity. reflexivity.
Case "E_Break". split. reflexivity. reflexivity.
Case "E_Ass". split. reflexivity. reflexivity.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H6 in H. inversion H.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H6 in H. inversion H.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_Seq_Break".
apply IHE1. assumption.
apply IHE1 in H1. inversion H1. inversion H0.
Case "E_Seq_Continue".
apply IHE1_1 in H4. inversion H4. inversion H0.
apply IHE1_1 in H1. inversion H1. subst.
apply IHE1_2 in H5. inversion H5. subst.
split. reflexivity. reflexivity.
Case "E_WhileEnd".
split. reflexivity. reflexivity.
rewrite H2 in H. inversion H.
rewrite H2 in H. inversion H.
Case "E_WhileLoop_Break".
rewrite H5 in H. inversion H.
apply IHE1 in H6. inversion H6. split. assumption. reflexivity.
apply IHE1 in H3. inversion H3. inversion H1.
Case "E_WhileLoop_Continue".
rewrite H5 in H. inversion H.
apply IHE1_1 in H6. inversion H6. inversion H1.
apply IHE1_1 in H3. inversion H3. subst.
apply IHE1_2 in H7. inversion H7. subst.
split. reflexivity. reflexivity.
Qed.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
Fixpoint beval' (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => match beval st b1 with
| false => false
| true => beval st b2
end
end.
Lemma beval__beval' :
forall st b,
beval st b = beval' st b.
Proof.
intros. induction b; reflexivity. (* Simple? *)
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
Module ForImp.
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CFor : com -> bexp -> com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "FOR"].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
Notation "'FOR' c1 ;;; b ;;; c2 'DO' c3 'END'" :=
(CFor c1 b c2 c3) (at level 80, right associativity).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
| E_For : forall (c1 : com) b c1 c2 c3 st st' st'',
c1 / st || st' ->
(WHILE b DO c2 ;; c3 END) / st' || st'' ->
(FOR c1 ;;; b ;;; c2 DO c3 END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
(** [] *)
End ForImp.
(* <$Date: 2014-10-25 12:49:06 -0400 (Sat, 25 Oct 2014) $ *)
|
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sdrdrum_arty_tb;
reg clk = 1'b0;
reg eth_clk = 1'b0;
reg rstn = 1'b0;
sdrdrum_arty dut (
.clk_in(clk),
.rstn_in(rstn),
.adc_a_data(1'b0),
.adc_b_data(1'b0),
.adc_c_data(1'b0),
.adc_d_data(1'b0),
// Ethernet
.eth_phy_rxd(4'b0),
.eth_phy_rx_clk(1'b0),
.eth_phy_rx_dv(1'b0),
.eth_phy_rx_er(1'b0),
.eth_phy_tx_clk(eth_clk),
.eth_phy_crs(1'b0),
.eth_phy_col(1'b0),
// IO
.switches(4'b0),
.buttons(4'b0)
);
initial begin
#500 rstn = 1'b1;
end
always begin
#20 eth_clk = ~eth_clk;
end
always begin
#5 clk = ~clk;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter.
module ad_iqcor (
// data interface
clk,
valid,
data_i,
data_q,
valid_out,
data_out,
// control interface
iqcor_enable,
iqcor_coeff_1,
iqcor_coeff_2);
// select i/q if disabled
parameter IQSEL = 0;
// data interface
input clk;
input valid;
input [15:0] data_i;
input [15:0] data_q;
output valid_out;
output [15:0] data_out;
// control interface
input iqcor_enable;
input [15:0] iqcor_coeff_1;
input [15:0] iqcor_coeff_2;
// internal registers
reg p1_valid = 'd0;
reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0;
reg p2_valid = 'd0;
reg p2_sign_i = 'd0;
reg p2_sign_q = 'd0;
reg [14:0] p2_magn_i = 'd0;
reg [14:0] p2_magn_q = 'd0;
reg p3_valid = 'd0;
reg [15:0] p3_data_i = 'd0;
reg [15:0] p3_data_q = 'd0;
reg p4_valid = 'd0;
reg [15:0] p4_data = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire [15:0] p2_data_i_s;
wire [15:0] p2_data_q_s;
wire p3_valid_s;
wire [31:0] p3_magn_i_s;
wire p3_sign_i_s;
wire [31:0] p3_magn_q_s;
wire p3_sign_q_s;
wire [15:0] p3_data_2s_i_p_s;
wire [15:0] p3_data_2s_q_p_s;
wire [15:0] p3_data_2s_i_n_s;
wire [15:0] p3_data_2s_q_n_s;
// apply offsets first
always @(posedge clk) begin
p1_valid <= valid;
p1_data_i <= data_i;
p1_data_q <= data_q;
end
// convert to sign-magnitude
assign p2_data_i_s = ~p1_data_i + 1'b1;
assign p2_data_q_s = ~p1_data_q + 1'b1;
always @(posedge clk) begin
p2_valid <= p1_valid;
p2_sign_i <= p1_data_i[15] ^ iqcor_coeff_1[15];
p2_sign_q <= p1_data_q[15] ^ iqcor_coeff_2[15];
p2_magn_i <= (p1_data_i[15] == 1'b1) ? p2_data_i_s[14:0] : p1_data_i[14:0];
p2_magn_q <= (p1_data_q[15] == 1'b1) ? p2_data_q_s[14:0] : p1_data_q[14:0];
end
// scaling functions - i
mul_u16 #(.DELAY_DATA_WIDTH(2)) i_mul_u16_i (
.clk (clk),
.data_a ({1'b0, p2_magn_i}),
.data_b ({1'b0, iqcor_coeff_1[14:0]}),
.data_p (p3_magn_i_s),
.ddata_in ({p2_valid, p2_sign_i}),
.ddata_out ({p3_valid_s, p3_sign_i_s}));
// scaling functions - q
mul_u16 #(.DELAY_DATA_WIDTH(1)) i_mul_u16_q (
.clk (clk),
.data_a ({1'b0, p2_magn_q}),
.data_b ({1'b0, iqcor_coeff_2[14:0]}),
.data_p (p3_magn_q_s),
.ddata_in (p2_sign_q),
.ddata_out (p3_sign_q_s));
// convert to 2s-complements
assign p3_data_2s_i_p_s = {1'b0, p3_magn_i_s[28:14]};
assign p3_data_2s_q_p_s = {1'b0, p3_magn_q_s[28:14]};
assign p3_data_2s_i_n_s = ~p3_data_2s_i_p_s + 1'b1;
assign p3_data_2s_q_n_s = ~p3_data_2s_q_p_s + 1'b1;
always @(posedge clk) begin
p3_valid <= p3_valid_s;
p3_data_i <= (p3_sign_i_s == 1'b1) ? p3_data_2s_i_n_s : p3_data_2s_i_p_s;
p3_data_q <= (p3_sign_q_s == 1'b1) ? p3_data_2s_q_n_s : p3_data_2s_q_p_s;
end
// corrected output is sum of two
always @(posedge clk) begin
p4_valid <= p3_valid;
p4_data <= p3_data_i + p3_data_q;
end
// output registers
always @(posedge clk) begin
if (iqcor_enable == 1'b1) begin
valid_out <= p4_valid;
data_out <= p4_data;
end else if (IQSEL == 1) begin
valid_out <= valid;
data_out <= data_q;
end else begin
valid_out <= valid;
data_out <= data_i;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module testcache();
reg clk;
reg re, we, we2, we3;
reg [31:0] address, writedata;
wire [31:0] readdatacache,readmissdata;
wire hit, miss, dirty;
// test
memory_system DUT(clk, re, we, we2, we3, address, writedata, readdatacache, hit, miss, dirty);
// generate clock to sequence tests
always begin
clk <= 1;
#5;
clk <= 0;
# 5;
end
// check results
initial begin
/*
re <= 1'b0;
we <= 1'b0;
we2 <=1'b0;
we3 <= 1'b0;
address <= 32'h0;
writedata <= 32'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'h7;
#10;
we <= 1'b0;
#10;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h54;
writedata <= 32'h7;
#10;
we <= 1'b0;
#200;
*/
// Write Miss: Miss generated, gets main memory, write this data to this cache value
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'h12345678;
#10;
we <= 1'b0;
#200;
we2 <= 1'b1;
#5;
we2 <= 1'b0;
#5;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Read Miss: !Hit generated, gets main memory, read out of cache is initialized mainmemory value after writing new cache value
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#200;
we3 <= 1'b1;
#5;
we3 <= 1'b0;
#20;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008011;
writedata <= 32'h87654321;
#10;
we <= 1'b0;
#200;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008010;
writedata <= 32'h01010101;
#10;
we <= 1'b0;
#200;
end
endmodule |
module spi_rx(
clk,
reset_n,
sdi,
sck,
ss_n,
adrs,
data,
rx_valid);
input wire clk, reset_n, sdi, sck, ss_n;
output wire rx_valid;
output wire [7:0] adrs, data;
reg [15:0] shift_reg, rx_buf1, rx_buf2;
reg [3:0] rx_cnt;
reg [2:0] valid_sync;
wire rx_done;
assign rx_done = &rx_cnt;
assign adrs = rx_buf2[15:8];
assign data = rx_buf2[7:0];
assign rx_valid = valid_sync[2];
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
valid_sync <= 0;
rx_buf2 <= 0;
end
else
begin
valid_sync <= {valid_sync[1:0], rx_done};
if(valid_sync[1]) rx_buf2 <= rx_buf1;
else rx_buf2 <= rx_buf2;
end
end
always @(negedge sck, negedge reset_n)
begin
if(!reset_n)
begin
shift_reg <= 0;
rx_buf1 <= 0;
rx_cnt <= 0;
end
else if(!ss_n)
begin
shift_reg <= {shift_reg[13:0], sdi};
rx_cnt <= rx_cnt + 1;
if(rx_done) rx_buf1 <= {shift_reg, sdi};
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:18:58 01/29/2016
// Design Name:
// Module Name: latch_EX_MEM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module latch_EX_MEM
#(
parameter B=32, W=5
)
(
input wire clk,
input wire reset,
inout wire ena,
/* Data signals INPUTS */
//input wire [B-1:0] add_result_in,
input wire [B-1:0] alu_result_in,
input wire [B-1:0] r_data2_in,
input wire [W-1:0] mux_RegDst_in,
//input wire [B-1:0] pc_jump_in,
/* Data signals OUTPUTS */
//output wire [B-1:0]add_result_out,
output wire [B-1:0]alu_result_out,
output wire [B-1:0]r_data2_out,
output wire [W-1:0]mux_RegDst_out,
//output wire [B-1:0] pc_jump_out,
/* Control signals INPUTS*/
//input wire zero_in,
//Write back
input wire wb_RegWrite_in,
input wire wb_MemtoReg_in,
//Memory
//input wire m_Jump_in,
//input wire m_Branch_in,
//input wire m_BranchNot_in,
//input wire m_MemRead_in,
input wire m_MemWrite_in,
//Other
input [5:0] opcode_in,
/* Control signals OUTPUTS */
//output wire zero_out,
//Write back
output wire wb_RegWrite_out,
output wire wb_MemtoReg_out,
//Memory
//output wire m_Jump_out,
//output wire m_Branch_out,
//output wire m_BranchNot_out,
//output wire m_MemRead_out,
output wire m_MemWrite_out,
//Other
output wire [5:0] opcode_out
);
/* Data REGISTERS */
//reg [B-1:0] add_result_reg;
reg [B-1:0] alu_result_reg;
reg [B-1:0] r_data2_reg;
reg [W-1:0] mux_RegDst_reg;
//reg [B-1:0] pc_jump_reg;
/* Control REGISTERS */
//reg zero_reg;
//Write back
reg wb_RegWrite_reg;
reg wb_MemtoReg_reg;
//Memory
//reg m_Jump_reg;
//reg m_Branch_reg;
//reg m_BranchNot_reg;
//reg m_MemRead_reg;
reg m_MemWrite_reg;
//other
reg [5:0] opcode_reg;
always @(posedge clk)
begin
if (reset)
begin
//add_result_reg <= 0;
alu_result_reg <= 0;
r_data2_reg <= 0;
mux_RegDst_reg <= 0;
//pc_jump_reg <= 0;
//zero_reg <= 0;
wb_RegWrite_reg <= 0;
wb_MemtoReg_reg <= 0;
//m_Jump_reg <= 0;
//m_Branch_reg <= 0;
//m_BranchNot_reg <= 0;
//m_MemRead_reg <= 0;
m_MemWrite_reg <= 0;
opcode_reg <= 0;
end
else
if(ena==1'b1)
begin
/* Data signals write to ID_EX register */
//add_result_reg <= add_result_in;
alu_result_reg <= alu_result_in;
r_data2_reg <= r_data2_in;
mux_RegDst_reg <= mux_RegDst_in;
//pc_jump_reg <= pc_jump_in;
/* Control signals write to ID_EX register */
//zero_reg <= zero_in;
//Write back
wb_RegWrite_reg <= wb_RegWrite_in;
wb_MemtoReg_reg <= wb_MemtoReg_in;
//Memory
//m_Jump_reg <= m_Jump_in;
//m_Branch_reg <= m_Branch_in;
//m_BranchNot_reg <= m_BranchNot_in;
//m_MemRead_reg <= m_MemRead_in;
m_MemWrite_reg <= m_MemWrite_in;
//Other
opcode_reg <= opcode_in;
end
end
/* Data signals read from ID_EX register */
//assign add_result_out = add_result_reg;
assign alu_result_out = alu_result_reg;
assign r_data2_out = r_data2_reg;
assign mux_RegDst_out = mux_RegDst_reg;
//assign pc_jump_out = pc_jump_reg;
/* Control signals read from ID_EX register */
//assign zero_out = zero_reg;
//Write back
assign wb_RegWrite_out = wb_RegWrite_reg;
assign wb_MemtoReg_out = wb_MemtoReg_reg;
//Memory
//assign m_Jump_out = m_Jump_reg;
//assign m_Branch_out = m_Branch_reg;
//assign m_BranchNot_out = m_BranchNot_reg;
//assign m_MemRead_out = m_MemRead_reg;
assign m_MemWrite_out = m_MemWrite_reg;
assign opcode_out = opcode_reg;
endmodule
|
// File: RAMConcur_TBV.v
// Generated by MyHDL 0.10
// Date: Wed Jun 27 01:12:16 2018
`timescale 1ns/10ps
module RAMConcur_TBV (
);
// Verilog Only Testbench for `RAMConcur`
reg [3:0] addr = 0;
wire [3:0] dout;
reg clk = 0;
reg [3:0] din = 0;
reg writeE = 0;
reg [3:0] RAMConcur0_0_1_2_memory [0:4-1];
initial begin: INITIALIZE_RAMCONCUR0_0_1_2_MEMORY
integer i;
for(i=0; i<4; i=i+1) begin
RAMConcur0_0_1_2_memory[i] = 0;
end
end
always @(posedge clk) begin: RAMCONCUR_TBV_RAMCONCUR0_0_1_2_WRITEACTION
if (writeE) begin
RAMConcur0_0_1_2_memory[addr] <= din;
end
end
assign dout = RAMConcur0_0_1_2_memory[addr];
initial begin: RAMCONCUR_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: RAMCONCUR_TBV_STIMULES
integer i;
for (i=0; i<1; i=i+1) begin
@(negedge clk);
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case (i)
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case ((-i))
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
$finish;
end
always @(posedge clk) begin: RAMCONCUR_TBV_PRINT_DATA
$write("%h", addr);
$write(" ");
$write("%h", din);
$write(" ");
$write("%h", writeE);
$write(" ");
$write("%h", dout);
$write(" ");
$write("%h", clk);
$write("\n");
end
endmodule
|
(** * Logic: Logic in Coq *)
Require Export MoreProp.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives. *)
(* ########################################################### *)
(** * Conjunction *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** Note that, like the definition of [ev] in a previous
chapter, this definition is parameterized; however, in this case,
the parameters are themselves propositions, rather than numbers. *)
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
Case "left". apply b_0.
Case "right". apply b_3. Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(ev 0) /\ (ev 4).
Proof.
split.
Case "left". apply ev_0.
Case "right". apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** Conversely, the [inversion] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HQ.
Qed.
(* FILL IN HERE *)
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[inversion] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
inversion H as [HP [HQ HR]].
split. split.
apply HP. apply HQ. apply HR.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (even__ev) *)
(** Now we can prove the other direction of the equivalence of [even]
and [ev], which we left hanging in chapter [Prop]. Notice that the
left-hand conjunct here is the statement we are actually interested
in; the right-hand conjunct is needed in order to make the
induction hypothesis strong enough that we can carry out the
reasoning in the inductive step. (To see why this is needed, try
proving the left conjunct by itself and observe where things get
stuck.) *)
Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n)).
Proof.
induction n as [|n'].
Case "n=0". split.
SCase "lift". intro. apply ev_0.
SCase "right". intro. unfold even in H. inversion H.
Case "n=S n'". split. inversion IHn'.
SCase "lift". apply H0.
SCase "right". intro. apply ev_SS. unfold even in H. simpl in H.
inversion IHn'. apply H0. unfold even. apply H.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ###################################################### *)
(** ** Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
inversion H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros. split.
Case "->". intro. apply H.
Case "<-". intro. apply H.
Qed.
(* FILL IN HERE *)
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros. inversion H. inversion H0. split.
Case "->". intro. apply H3. apply H1. apply H5.
Case "<-". intro. apply H2. apply H4. apply H5.
Qed.
(* FILL IN HERE *)
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** Since [P \/ Q] has two constructors, doing [inversion] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. inversion H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros P Q R H. inversion H as [[HLP|HLQ] [HRP|HRR]].
Case "PP". left. apply HLP.
Case "PR". left. apply HLP.
Case "QP". left. apply HRP.
Case "QR". right. split. apply HLQ. apply HRR.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. split. apply or_distributes_over_and_1.
apply or_distributes_over_and_2.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] (advanced) *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
inversion H.
rewrite H0. rewrite H1. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (bool_prop) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros.
destruct b.
Case "b=true". destruct c.
SCase "c=true". inversion H.
SCase "c=false". right. reflexivity.
Case "b=false". destruct c.
SCase "c=true". left. reflexivity.
SCase "c=false". left. reflexivity.
Qed.
(* FILL IN HERE *)
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros.
destruct b.
Case "b=true". destruct c.
SCase "c=true". left. reflexivity.
SCase "c=false". left. reflexivity.
Case "b=false". destruct c.
SCase "c=true". right. reflexivity.
SCase "c=false". inversion H.
Qed.
(* FILL IN HERE *)
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
intros.
destruct b.
Case "b=true". inversion H.
Case "b=false". destruct c.
SCase "c=true". inversion H.
SCase "c=false". split. reflexivity. reflexivity.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
Inductive True : Prop :=I:True.
Inductive True' :Prop :=
TrueP: forall P:Prop , True'.
Theorem test_True' : forall (P:Prop),
P->True'.
Proof. intros. apply TrueP. apply P. Qed.
(* FILL IN HERE *)
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. inversion H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_: unfold ~ in ~~p => (p->False)->False ,apply p,
we can get False->False, this implication correct Obviously.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros.
unfold not. unfold not in H0. intro.
apply H0. apply H. apply H1.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intro.
unfold not. intro. inversion H. apply H1. apply H0.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(*_Proof_: unfold not, then (P/\(P->False))->False,
we get two hypotheses in context: P , P->False
Obviously, the goal correct.
*)
(* FILL IN HERE *)
(** [] *)
Theorem five_not_even :
~ ev 5.
Proof.
(* WORKED IN CLASS *)
unfold not. intros Hev5. inversion Hev5 as [|n Hev3 Heqn].
inversion Hev3 as [|n' Hev1 Heqn']. inversion Hev1. Qed.
(** **** Exercise: 1 star (ev_not_ev_S) *)
(** Theorem [five_not_even] confirms the unsurprising fact that five
is not an even number. Prove this more interesting fact: *)
Theorem ev_not_ev_S : forall n,
ev n -> ~ ev (S n).
Proof.
unfold not. intros n H. induction H. (* not n! *)
Case "ev_0". intro. inversion H.
Case "ev_SS". intro. inversion H0.
apply IHev. apply H2.
Qed.
(* FILL IN HERE *)
(** [] *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
(* FILL IN HERE *)
(** [] *)
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
unfold not.
induction n as [|n'].
Case "n=O". destruct m as [|m'].
SCase "m=O". simpl. intro. apply ex_falso_quodlibet. apply H. reflexivity.
SCase "m=S m'". simpl. intro. reflexivity.
Case "n=S n'". destruct m as [|m'].
SCase "m=O". simpl. intro. reflexivity.
SCase "m=S m'". intro. apply IHn'. intro. apply H. rewrite->H0. reflexivity.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
unfold not.
induction n as [|n'].
Case "n=O". destruct m as [|m'].
SCase "m=O". intro. inversion H.
SCase "m=S m'". intros. rewrite<-H0 in H. inversion H.
Case "n=S n'". destruct m as [|m'].
SCase "m=O". intros. rewrite->H0 in H. inversion H.
SCase "m=S m'". simpl. intros. inversion H0. apply IHn' with (m:=m').
apply H. apply H2.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (ble_nat_false) *)
Theorem ble_nat_false : forall n m,
ble_nat n m = false -> ~(n <= m).
Proof.
unfold not.
induction n as [|n'].
Case "n=O". destruct m as [|m'].
SCase "m=O". intros. inversion H.
SCase "m=S m'". intros. inversion H.
Case "n=S n'". destruct m as [|m'].
SCase "m=O". intros. inversion H0.
SCase "m=S m'". intros. inversion H in H0.
apply IHn' with (m:=m'). apply H2. apply Sn_le_Sm__n_le_m.
apply H0.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
exist a number n , the number (S n) is beautiful.
]]
mean? *)
(*exist a number n , the number (S n) is beautiful FILL IN HERE *)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
intros. unfold not. intro. inversion H0 as [witness]. apply H1.
apply H.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
unfold excluded_middle.
intros H0 X P H1 x.
destruct (H0(P x)) as [HL|HR].
apply HL.
apply ex_falso_quodlibet.
apply H1.
exists x.
apply HR.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
split.
Case "->".
intro.
inversion H as [x].
inversion H0. left. exists x. apply H1.
right. exists x. apply H1.
Case "<-".
intro.
inversion H. inversion H0 as [x]. exists x. left. apply H1.
inversion H0 as [x]. exists x. right. apply H1.
Qed.
(* FILL IN HERE *)
(** [] *)
(* Print dist_exists_or. *)
(* ###################################################### *)
(** * Equality *)
(** Even Coq's equality relation is not built in. It has (roughly)
the following inductive definition. *)
(* (We enclose the definition in a module to avoid confusion with the
standard library equality, which we have used extensively
already.) *)
Module MyEquality.
Inductive eq {X:Type} : X -> X -> Prop :=
refl_equal : forall x, eq x x.
(** Standard infix notation: *)
Notation "x = y" := (eq x y)
(at level 70, no associativity)
: type_scope.
(** The definition of [=] is a bit subtle. The way to think about it
is that, given a set [X], it defines a _family_ of propositions
"[x] is equal to [y]," indexed by pairs of values ([x] and [y])
from [X]. There is just one way of constructing evidence for
members of this family: applying the constructor [refl_equal] to a
type [X] and a value [x : X] yields evidence that [x] is equal to
[x]. *)
(** **** Exercise: 2 stars (leibniz_equality) *)
(** The inductive definitions of equality corresponds to _Leibniz equality_:
what we mean when we say "[x] and [y] are equal" is that every
property on [P] that is true of [x] is also true of [y]. *)
Lemma leibniz_equality : forall (X : Type) (x y: X),
x = y -> forall P : X -> Prop, P x -> P y.
Proof.
intros X x y H P.
destruct H. intro. apply H.
Qed.
(* FILL IN HERE *)
(** [] *)
(** We can use
[refl_equal] to construct evidence that, for example, [2 = 2].
Can we also use it to construct evidence that [1 + 1 = 2]? Yes:
indeed, it is the very same piece of evidence! The reason is that
Coq treats as "the same" any two terms that are _convertible_
according to a simple set of computation rules. These rules,
which are similar to those used by [Eval compute], include
evaluation of function application, inlining of definitions, and
simplification of [match]es.
*)
Lemma four: 2 + 2 = 1 + 3.
Proof.
apply refl_equal.
Qed.
(** The [reflexivity] tactic that we have used to prove equalities up
to now is essentially just short-hand for [apply refl_equal]. *)
End MyEquality.
(* ###################################################### *)
(** * Evidence-carrying booleans. *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and
the type-specific forms, like [beq_nat], that produce [boolean]
values. The former are more convenient to reason about, but
we've relied on the latter to let us use equality tests
in _computations_. While it is straightforward to write lemmas
(e.g. [beq_nat_true] and [beq_nat_false]) that connect the two forms,
using these lemmas quickly gets tedious.
It turns out that we can get the benefits of both forms at once
by using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as with [or].
(In fact, the definition of [sumbool] is almost the same as for [or].
The only difference is that values of [sumbool] are declared to be in
[Set] rather than in [Prop]; this is a technical distinction
that allows us to compute with them.) *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
intros n.
induction n as [|n'].
Case "n = 0".
intros m.
destruct m as [|m'].
SCase "m = 0".
left. reflexivity.
SCase "m = S m'".
right. intros contra. inversion contra.
Case "n = S n'".
intros m.
destruct m as [|m'].
SCase "m = 0".
right. intros contra. inversion contra.
SCase "m = S m'".
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not.
Read computationally, [eq_nat_dec] takes two [nat] values and returns
a [sumbool] constructed with [left] if they are equal and [right]
if they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean].
(Notice that we ended this proof with [Defined] rather than [Qed].
The only difference this makes is that the proof becomes _transparent_,
meaning that its definition is available when Coq tries to do reductions,
which is important for the computational interpretation.)
Here's a simple example illustrating the advantages of the [sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f. intros Hx1.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
Case "k1 = k2".
rewrite <- e.
symmetry. apply Hx1.
Case "k1 <> k2".
reflexivity. Qed.
(** Compare this to the more laborious proof (in MoreCoq.v) for the
version of [override] defined using [beq_nat], where we had to
use the auxiliary lemma [beq_nat_true] to convert a fact about booleans
to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override' (override' f k1 x2) k1 x1) k2 = (override' f k1 x1) k2.
Proof.
intros. unfold override'.
destruct (eq_nat_dec k1 k2).
Case "k1=k2". reflexivity.
Case "k1<>k2". reflexivity.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Inversion, Again (Advanced) *)
(** We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves...
In general, the [inversion] tactic
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context (and, for convenience,
rewrites them in the goal), and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal. *)
(** _Example_: If we invert a hypothesis built with [or], there are two
constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal.
_Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal.
_Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [refl_equal] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(** **** Exercise: 1 star, optional (dist_and_or_eq_implies_and) *)
Lemma dist_and_or_eq_implies_and : forall P Q R,
P /\ (Q \/ R) /\ Q = R -> P/\Q.
Proof.
intros.
inversion H. inversion H1. rewrite<-H3 in H2.
apply conj. apply H0. inversion H2. apply H4. apply H4.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all {X : Type} (P : X -> Prop) : list X -> Prop :=
|all_nil: all P nil
|all_h_t: forall (t:list X) (x:X), all P t-> P x->all P (x::t).
(*FILL IN HERE *)
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
Theorem forallb_all:forall (X:Type) (test:X->bool)(P:X->Prop)(l:list X),
(forall x:X, test x = true<->P x)->( forallb test l=true<-> all P l).
Proof.
intros X test P l. intro H.
split.
Case "->". induction l as [|x l'].
SCase "l=[]". intro. apply all_nil.
SCase "l=x::l'". intro. inversion H0. apply andb_prop in H2.
inversion H2. apply all_h_t. apply IHl'.
apply H3. apply H. apply H1.
Case "<-". induction l as [|x l'].
SCase "l=[]". intro. simpl. reflexivity.
SCase "l=x::l'". intro. inversion H0. simpl. apply andb_true_intro.
split. apply H. apply H4.
apply IHl'. apply H3.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
Inductive in_order_merge{X:Type}:list X->list X->list X->Prop:=
|merge_nil_l: forall l:list X,in_order_merge nil l l
|merge_l_nil: forall l:list X,in_order_merge l nil l
|merge_h1_l1_h2_l2:forall (h1:X)(h2:X)(l1:list X)(l2:list X)(l:list X),
in_order_merge l1 l2 l->in_order_merge (h1::l1) (h2::l2) (h1::h2::l).
Theorem app_ass :forall {X: Type} (l1 l2 l3 : list X),
(l1 ++ l2) ++ l3 = l1 ++ (l2 ++ l3).
Proof.
intros X l1 l2 l3. induction l1 as [| n l1'].
Case "l1 = nil".
reflexivity.
Case "l1 = cons n l1'".
simpl. rewrite -> IHl1'. reflexivity.
Qed.
Theorem app_cons_t : forall (l1 l2: list nat) (a : nat),
l2 ++ (a :: l1) = (l2 ++ [a]) ++ l1.
Proof.
intros l1 l2.
generalize dependent l1.
destruct l2.
Case "l2=[]". intros l1. intros a. simpl. reflexivity.
Case "l2=n::l2". intros l1 a. simpl. rewrite app_ass. reflexivity.
Qed.
Theorem filter_bad : forall (l l2 : list nat) (f : nat -> bool),
l2 <> [] -> ~(filter f l = l2 ++ l).
Proof.
induction l.
Case "l=[]".
intros l2. intros f H2. simpl. unfold not in H2. unfold not.
destruct l2.
SCase "l=2[]". simpl. intros H. apply H2. reflexivity.
SCase "l=n::l2". intros H. inversion H.
Case "l=x::l". intros l2 f H1. simpl. destruct (f x).
SCase "f x = true". simpl. intros H2. destruct l2.
SSCase "l2=[]". simpl in H2. inversion H2. assert (l = [] ++ l). simpl. reflexivity.
rewrite H in H0. apply IHl in H0. apply H0. simpl. apply H1.
SSCase "l2=n::l2". simpl in H2. inversion H2. assert (l2 ++ n :: l = (l2 ++ [n]) ++ l).
apply app_cons_t. rewrite H in H3. apply IHl in H3. apply H3. simpl.
intros H4. destruct l2. inversion H4. inversion H4.
SCase "f x=false". assert (l2 ++ x :: l = (l2 ++ [x]) ++ l).
apply app_cons_t. rewrite H. apply IHl. destruct l2.
SSCase "l2=[]". intros H2. inversion H2.
SSCase "l2=n::l2". intros H2. inversion H2.
Qed.
Theorem filter_theorem: forall (l l1 l2: list nat) (f : nat -> bool),
in_order_merge l1 l2 l ->
filter f l1 = l1 ->
filter f l2 = [] ->
filter f l = l1.
Proof.
intros l l1 l2 f H.
induction H.
Case "merge_nil_l". intros H H2. apply H2.
Case "merge_l_nil". intros H1 H2. apply H1.
Case "merge_h1_l1_h2_l2". intros H1 H2. simpl. simpl in H1. simpl in H2. destruct (f h1).
SCase "f h1 =true". simpl. destruct (f h2).
SSCase "f h2=true". inversion H2.
SSCase "f h2=false". simpl. inversion H1. rewrite H3.
assert (filter f l = l1 -> h1 :: filter f l = h1 :: l1).
intros HX. rewrite HX. reflexivity.
apply H0. apply IHin_order_merge. apply H3. apply H2.
SCase "f h1=false". destruct (f h2).
SSCase "f h2=true". inversion H2.
SSCase "f h2=false". assert (h1 :: l1 = [h1] ++ l1). simpl. reflexivity.
rewrite H0 in H1. apply filter_bad in H1. inversion H1.
intros H3. inversion H3.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(*?????????????*)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
intros.
induction xs as [|h xs'].
Case "xs=[]". simpl. intros. right. apply H.
Case "xs=h:xs'".
inversion H.
SCase "x=h".
left. apply ai_here.
SCase "x<>h".
apply IHxs' in H1.
destruct H1.
left. apply ai_later. apply H1.
right. apply H1.
Qed.
(* FILL IN HERE *)
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
intros.
destruct H as [HL|HR].
Case "HL". induction xs as [|hx xs'].
SCase "xs=[]". inversion HL.
SCase "xs=hx::xs'". inversion HL.
SSCase "x=hx". apply ai_here.
SSCase "x<>hx". apply IHxs' in H0. simpl. apply ai_later. apply H0.
Case "HR". induction xs as [|hx xs'].
SCase "xs=[]". simpl. apply HR.
SCase "xs=hx::xs'". simpl. apply ai_later. apply IHxs'.
Qed.
(* FILL IN HERE *)
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
Inductive disjoint {X:Type}:list X->list X->Prop:=
|nil_disj_nil:forall l:list X, disjoint nil l
|l1_disj_l2:forall (h : X)(l1:list X)(l2:list X),
disjoint l1 l2->~(appears_in h l2)->disjoint (h::l1) l2.
(* FILL IN HERE *)
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
Inductive no_repeats {X:Type}:list X ->Prop:=
|no_reps_l: no_repeats nil
|no_reps_h_t: forall(h:X)(t:list X),~(appears_in h t)->no_repeats t->no_repeats (h::t).
(* FILL IN HERE *)
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
Theorem app_nil_end {X:Type}: forall l : list X,
l ++ [] = l.
Proof.
induction l as [|n l'].
Case "l=nil".
reflexivity.
Case "l=cons n l'".
simpl. rewrite->IHl'.
reflexivity.
Qed.
Theorem disjoint__no_repeats : forall (X:Type)(l1:list X)(l2:list X),
no_repeats(l1++l2)->disjoint l1 l2.
Proof.
intros X.
induction l1 as [|h1 l1'].
Case "". intros. apply nil_disj_nil.
Case "". intros. simpl in H. apply l1_disj_l2.
apply IHl1'. inversion H. apply H3.
inversion H. unfold not. intro. unfold not in H2.
apply H2. apply app_appears_in. right. apply H4.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all (except from your study group partner, if
you have one).
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1,4,1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
|nil_ns: nostutter nil
|a_nil_ns :forall a:nat,nostutter (a::nil)
|b_a_l_ns: forall (a:nat)(b:nat)(l:list nat),~appears_in b [a]->nostutter (a::l)
->nostutter(b::a::l).
(* FILL IN HERE *)
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
Proof.
repeat apply b_a_l_ns; unfold not.
intro; inversion H; inversion H1.
intro; inversion H; inversion H1.
intro; inversion H; inversion H1.
intro; inversion H; inversion H1.
intro; inversion H; inversion H1.
apply a_nil_ns.
Qed.
(* FILL IN HERE *)
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_2: nostutter [].
Proof. apply nil_ns. Qed.
(* FILL IN HERE *)
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_3: nostutter [5].
Proof. apply a_nil_ns. Qed.
(* FILL IN HERE *)
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
Proof. unfold not. intro.
inversion H.
inversion H4.
unfold not in H7.
apply H7.
apply ai_here.
Qed.
(* FILL IN HERE *)
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
intros.
induction l1 as [|h1 l1'].
Case "l1=[]". simpl. reflexivity.
Case "l1=h1::l1'". simpl. rewrite->IHl1'. reflexivity.
Qed.
(* FILL IN HERE *)
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
intros.
induction H.
Case "ai_here". exists nil. exists l. reflexivity.
Case "ai_later". inversion IHappears_in. exists (b::witness).
inversion H0. exists witness0.
inversion H1. reflexivity.
Qed.
(* FILL IN HERE *)
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
|rep_hl: forall (h:X)(l:list X), appears_in h l->repeats (h::l)
|rep_l: forall (h:X)(l:list X),repeats l ->repeats (h::l)
(* FILL IN HERE *)
.
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents an
assignment of items to labels: if there are more items than labels,
at least two items must have the same label. You will almost
certainly need to use the [excluded_middle] hypothesis. *)
Lemma diff_rem : forall (X : Type) (x x0 : X) (l l' : list X),
excluded_middle -> x <> x0 ->
appears_in x0 (l ++ x :: l') ->
appears_in x0 (l ++ l').
Proof.
induction l.
Case "l=[]". intros. simpl. inversion H1.
apply ex_falso_quodlibet. apply H0. auto. apply H3.
Case "l=x1::l". intros. simpl.
assert ((x0 = x1) \/ ~(x0 = x1)).
unfold excluded_middle in H. apply H.
inversion H2. subst. apply ai_here.
apply ai_later. inversion H1; subst.
apply ex_falso_quodlibet. apply H3. auto.
apply IHl. apply H. apply H0. apply H5.
Qed.
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1.
Case "l1=[]". intros. inversion H1.
Case "l1=x::l1". intros.
unfold excluded_middle in H.
assert ((appears_in x l1) \/ ~(appears_in x l1)).
apply H. inversion H2. apply rep_hl. apply H3.
apply rep_l. assert (exists l, exists l', l2 = l ++ (x::l')).
apply appears_in_app_split. apply H0. apply ai_here.
inversion H4. inversion H5. apply (IHl1 (witness ++ witness0)).
unfold excluded_middle. apply H. intros.
assert ((x = x0) \/ ~(x = x0)).
apply H. inversion H8. apply ex_falso_quodlibet.
apply H3. subst. apply H7. assert (appears_in x0 l2). apply H0. apply ai_later.
apply H7. subst. apply (diff_rem X x x0 witness witness0). unfold excluded_middle.
apply H. apply H9. apply H10. subst. rewrite app_length.
rewrite app_length in H1. simpl in H1.
apply Sn_le_Sm__n_le_m. rewrite <- plus_n_Sm in H1. apply H1.
Qed.
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
module eb17_ctrl #(
parameter ZERO = 7'b1_0_01_00_0,
parameter ONE = 7'b1_1_00_11_0,
parameter TWO = 7'b0_1_10_10_1
) (
input t_0_req,
output t_0_ack,
output i_0_req,
input i_0_ack,
output en0, en1, sel,
input clk, reset_n
);
// State machine
reg [6:0] state, state_nxt;
always @(posedge clk or negedge reset_n)
if (~reset_n) state <= ZERO;
else state <= state_nxt;
// state d0 d1 t.ack i.req en0 en1 sel
// ZERO - - 1 0 t.req 0 0 1_0_01_00_0
// ONE + - 1 1 t.req & i.ack t.req & ~i.ack 0 1_1_00_11_0
// TWO + + 0 1 i.ack t.req & i.ack 1 0_1_10_10_1
always @*
casez({state, t_0_req, i_0_ack})
{ZERO, 2'b1?} : state_nxt = ONE;
{ONE, 2'b01} : state_nxt = ZERO;
{ONE, 2'b10} : state_nxt = TWO;
{TWO, 2'b?1} : state_nxt = ONE;
default state_nxt = state;
endcase
assign t_0_ack = state[6];
assign i_0_req = state[5];
assign en0 = (state[4] | t_0_req) & (state[3] | i_0_ack);
assign en1 = (state[2] & t_0_req) & (state[1] ^ i_0_ack);
assign sel = state[0];
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The Reset Ctrl module to implement reset control
//
// ====================================================================
`include "e203_defines.v"
module e203_reset_ctrl #(
parameter MASTER = 1
)(
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The core's clk and rst
output rst_core,
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
// The Top always on clk and rst
output rst_aon
);
wire rst_sync_n;
`ifndef E203_HAS_LOCKSTEP//{
localparam RST_SYNC_LEVEL = `E203_ASYNC_FF_LEVELS;
`endif//}
reg [RST_SYNC_LEVEL-1:0] rst_sync_r;
generate
if(MASTER == 1) begin:master_gen
always @(posedge clk or negedge rst_n)
begin:rst_sync_PROC
if(rst_n == 1'b0)
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {RST_SYNC_LEVEL{1'b0}};
end
else
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {rst_sync_r[RST_SYNC_LEVEL-2:0],1'b1};
end
end
assign rst_sync_n = test_mode ? rst_n : rst_sync_r[`E203_ASYNC_FF_LEVELS-1];
end
else begin:slave_gen
// Just pass through for slave in lockstep mode
always @ *
begin:rst_sync_PROC
rst_sync_r = {RST_SYNC_LEVEL{1'b0}};
end
assign rst_sync_n = rst_n;
end
endgenerate
// The core's clk and rst
assign rst_core = rst_sync_n;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
assign rst_itcm = rst_sync_n;
`endif
`ifdef E203_HAS_DTCM
assign rst_dtcm = rst_sync_n;
`endif
// The Top always on clk and rst
assign rst_aon = rst_sync_n;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_hd__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_hd__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A22OI_PP_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ls__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V |
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
andb b1 (andb b2 b3).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S x => mult n (factorial x)
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H H0.
rewrite H. rewrite H0.
reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H.
rewrite H. simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b. rewrite H. rewrite H. reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b. rewrite H. rewrite H.
rewrite negb_involutive. reflexivity. Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c. destruct b.
simpl. intros H. rewrite H. reflexivity.
simpl. intros H. rewrite H. reflexivity. Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| Zero : bin
| Twice : bin -> bin
| More : bin -> bin.
Fixpoint binc (n : bin) : bin :=
match n with
| Zero => More Zero
| Twice x => More x
| More x => Twice (binc x)
end.
Fixpoint binn (n : bin) : nat :=
match n with
| Zero => O
| Twice x => binn x + binn x
| More x => S (binn x + binn x)
end.
Example test_bin0: binc Zero = More Zero. (* 1: 0001 *)
Proof. simpl. reflexivity. Qed.
Example test_bin1: binc (More Zero) = Twice (More Zero). (* 2: 0010 *)
Proof. simpl. reflexivity. Qed.
Example test_bin2: binc (Twice (More Zero)) = More (More Zero). (* 3: 0011 *)
Proof. simpl. reflexivity. Qed.
Example test_bin3: binc (More (More Zero)) = (* 4: 0100 *)
Twice (Twice (More Zero)).
Proof. simpl. reflexivity. Qed.
Example test_bin4: binc (Twice (Twice (More Zero))) = (* 5: 0101 *)
More (Twice (More Zero)).
Proof. simpl. reflexivity. Qed.
Example test_bin5: binc (More (Twice (More Zero))) = (* 6: 0110 *)
Twice (More (More Zero)).
Proof. simpl. reflexivity. Qed.
Example test_bin6: binc (Twice (More (More Zero))) = (* 7: 0111 *)
More (More (More Zero)).
Proof. simpl. reflexivity. Qed.
Example test_bin7: binc (More (More (More Zero))) = (* 8: 1000 *)
Twice (Twice (Twice (More Zero))).
Proof. simpl. reflexivity. Qed.
Example test_binn1: binn (binc Zero) = S (binn Zero).
Proof. simpl. reflexivity. Qed.
Example test_binn2: binn (binc (More Zero)) = S (binn (More Zero)).
Proof. simpl. reflexivity. Qed.
Example test_binn3: binn (binc (Twice (More Zero))) = S (binn (Twice (More Zero))).
Proof. simpl. reflexivity. Qed.
Example test_binn4: binn (binc (More (More Zero))) = S (binn (More (More Zero))).
Proof. simpl. reflexivity. Qed.
Example test_binn5: binn (binc (Twice (Twice (More Zero)))) =
S (binn (Twice (Twice (More Zero)))).
Proof. simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* Fixpoint nearest_odd (n : nat) : nat := *)
(* match n with *)
(* | O => nearest_odd (S n) *)
(* | S n' => S n' *)
(* end. *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores MC68HC11E based SPI interface ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: simple_spi_top.v,v 1.1.1.1 2002-12-22 16:07:15 rherveille Exp $
//
// $Date: 2002-12-22 16:07:15 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
// Motorola MC68HC11E based SPI interface
//
// Currently only MASTER mode is supported
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module simple_spi_top(
clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o,
inta_o,
sck_o, mosi_o, miso_i
);
//
// Inputs & outputs
//
// 8bit WISHBONE bus slave interface
input clk_i; // clock
input rst_i; // reset (asynchronous active low)
input cyc_i; // cycle
input stb_i; // strobe
input [1:0] adr_i; // address
input we_i; // write enable
input [7:0] dat_i; // data output
output [7:0] dat_o; // data input
output ack_o; // normal bus termination
output inta_o; // interrupt output
// SPI port
output sck_o; // serial clock output
output mosi_o; // MasterOut SlaveIN
input miso_i; // MasterIn SlaveOut
//
// Module body
//
reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming)
wire [7:0] spsr; // Serial Peripheral Status register ('HC11 naming)
reg [7:0] sper; // Serial Peripheral Extension register
reg [7:0] treg; // Transfer register
// fifo signals
wire [7:0] rfdout;
reg wfre, rfwe;
wire rfre, rffull, rfempty;
wire [7:0] wfdin, wfdout;
wire wfwe, wffull, wfempty;
// misc signals
wire tirq; // transfer interrupt (selected number of transfers done)
wire wfov; // write fifo overrun (writing while fifo full)
reg state; // statemachine state
reg ena_mosi; // mosi_o clock-enable
reg [2:0] bcnt;
//
// Wishbone interface
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
// dat_i
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
spcr <= #1 8'h10; // set master bit
sper <= #1 8'h00;
end
else if (wb_wr)
begin
if (adr_i == 2'b00)
spcr <= #1 dat_i | 8'h10; // always set master bit
if (adr_i == 2'b11)
sper <= #1 dat_i;
end
// write fifo
assign wfwe = wb_acc & (adr_i == 2'b10) & ack_o & we_i;
assign wfov = wfwe & wffull;
// dat_o
reg [7:0] dat_o;
always @(posedge clk_i)
case(adr_i) // synopsys full_case parallel_case
2'b00: dat_o <= #1 spcr;
2'b01: dat_o <= #1 spsr;
2'b10: dat_o <= #1 rfdout;
2'b11: dat_o <= #1 sper;
endcase
// read fifo
assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
// ack_o
reg ack_o;
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
ack_o <= #1 1'b0;
else
ack_o <= #1 wb_acc & !ack_o;
// decode Serial Peripheral Control Register
wire spie = spcr[7]; // Interrupt enable bit
wire spe = spcr[6]; // System Enable bit
wire dwom = spcr[5]; // Port D Wired-OR Mode Bit
wire mstr = spcr[4]; // Master Mode Select Bit
wire cpol = spcr[3]; // Clock Polarity Bit
wire cpha = spcr[2]; // Clock Phase Bit
wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits
// decode Serial Peripheral Extension Register
wire [1:0] icnt = sper[7:6]; // interrupt on transfer count
wire [1:0] spre = sper[1:0]; // extended clock rate select
wire [3:0] espr = {spre, spr};
// generate status register
wire wr_spsr = wb_wr & (adr_i == 2'b01);
reg spif;
always @(posedge clk_i)
if (~spe)
spif <= #1 1'b0;
else
spif <= #1 (tirq | spif) & ~(wr_spsr & dat_i[7]);
reg wcol;
always @(posedge clk_i)
if (~spe)
wcol <= #1 1'b0;
else
wcol <= #1 (wfov | wcol) & ~(wr_spsr & dat_i[6]);
assign spsr[7] = spif;
assign spsr[6] = wcol;
assign spsr[5:4] = 2'b00;
assign spsr[3] = wffull;
assign spsr[2] = wfempty;
assign spsr[1] = rffull;
assign spsr[0] = rfempty;
// generate IRQ output (inta_o)
reg inta_o;
always @(posedge clk_i)
inta_o <= #1 spif & spie;
//
// hookup read/write buffer fifo
fifo4 #(8)
rfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( treg ),
.we ( rfwe ),
.dout ( rfdout ),
.re ( rfre ),
.full ( rffull ),
.empty ( rfempty )
),
wfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( dat_i ),
.we ( wfwe ),
.dout ( wfdout ),
.re ( wfre ),
.full ( wffull ),
.empty ( wfempty )
);
//
// generate clk divider
reg [9:0] clkcnt;
always @(posedge clk_i)
if(~spe)
clkcnt <= #1 10'h0;
else if (|clkcnt & state)
clkcnt <= #1 clkcnt - 10'h1;
else
case (espr) // synopsys full_case parallel_case
4'h0: clkcnt <= #1 10'h0; // 2
4'h1: clkcnt <= #1 10'h1; // 4
4'h2: clkcnt <= #1 10'h7; // 16
4'h3: clkcnt <= #1 10'hf; // 32
4'h4: clkcnt <= #1 10'h3f; // 128
4'h5: clkcnt <= #1 10'h7f; // 256
4'h6: clkcnt <= #1 10'h1ff; // 1024
4'h7: clkcnt <= #1 10'h3ff; // 2048
endcase
// generate internal SCK
reg sck;
always @(posedge clk_i)
if (~spe)
sck <= #1 1'b0;
else
sck <= #1 sck ^ ~(|clkcnt);
// generate SCK_O
reg sck_o;
always @(posedge clk_i)
sck_o <= #1 sck ^ cpol;
// generate clock-enable signal
reg ena;
always @(posedge clk_i)
ena <= #1 ~(|clkcnt) & (~sck ^ cpha);
// generate ena_mosi (clock data in)
reg hold_ena;
always @(posedge clk_i or negedge rst_i)
if(~rst_i)
hold_ena <= #1 1'b0;
else
hold_ena <= state & (ena | hold_ena) & ~ena_mosi;
always @(posedge clk_i)
ena_mosi <= #1 ~(|clkcnt) & hold_ena;
// store miso
reg smiso;
always @(posedge clk_i)
if(ena)
smiso <= #1 miso_i;
// transfer statemachine
//reg [2:0] bcnt; // bit count
always @(posedge clk_i)
if (~spe)
begin
state <= #1 1'b0; // idle
bcnt <= #1 3'h0;
treg <= #1 8'h00;
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
end
else
begin
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
if(~state) // idle
begin
bcnt <= #1 3'h7; // set transfer counter
treg <= #1 wfdout; // load transfer register
if (~wfempty)
begin
state <= #1 1'b1; // goto transfer state
wfre <= #1 1'b1;
end
end
if(state & ena_mosi)
begin
treg <= #1 {treg[6:0], smiso}; //miso_i};
bcnt <= #1 bcnt -3'h1;
if (~|bcnt)
begin
state <= #1 1'b0; // goto idle state
rfwe <= #1 1'b1;
end
end
end
assign mosi_o = treg[7];
// count number of transfers (for interrupt generation)
reg [1:0] tcnt; // transfer count
always @(posedge clk_i)
if (~spe)
tcnt <= #1 icnt;
else if (rfwe) // rfwe gets asserted when all bits have been transfered
if (|tcnt)
tcnt <= #1 tcnt - 2'h1;
else
tcnt <= #1 icnt;
assign tirq = ~|tcnt & rfwe;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_4_V
`define SKY130_FD_SC_MS__A2BB2OI_4_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_4_V
|
module BarrelShifterTestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] Rs,Rm,IR;
reg SR29_IN;
wire SR29_OUT;
wire [31:0] Out;
//BarrelShifter(input [31] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
BarrelShifter bs(Rs,Rm,IR,SR29_IN,SR29_OUT,Out);
initial fork
Rs=0;Rm=0;IR=0;SR29_IN=0;
#1 Rs=1;#1 Rm=2;#1 IR[4]=1;#1 SR29_IN=0;
#2 Rs=1;#2 Rm=4; #2 SR29_IN=0;
#3 Rs=1;#3 Rm=8; #3 SR29_IN=0;
#4 Rs=8;#4 Rm=1; #4 SR29_IN=0;
#10 Rs=1;#10 Rm=2;#10 IR[6:5]=1;#10 SR29_IN=0;
#11 Rs=1;#11 Rm=4; #11 SR29_IN=0;
#12 Rs=1;#12 Rm=8; #12 SR29_IN=0;
#13 Rs=8;#13 Rm=1; #13 SR29_IN=0;
#20 Rs=1;#20 Rm=2;#20 IR[6:5]=2;#20 SR29_IN=0;
#21 Rs=1;#21 Rm=4; #21 SR29_IN=0;
#22 Rs=1;#22 Rm=8; #22 SR29_IN=0;
#23 Rs=8;#23 Rm=1; #23 SR29_IN=0;
#24 Rs=8;#24 Rm=32'hF0000001; #24 SR29_IN=0;
#30 Rs=1;#30 Rm=2;#30 IR[6:5]=3;#30 SR29_IN=0;
#31 Rs=1;#31 Rm=4; #31 SR29_IN=0;
#32 Rs=1;#32 Rm=8; #32 SR29_IN=0;
#33 Rs=8;#33 Rm=1; #33 SR29_IN=0;
#34 Rs=8;#34 Rm=32'hF0000001; #34 SR29_IN=0;
#40 IR[11:8]=0;#40 IR[7:0]=0;#40 IR[27:25]=1;#40 IR[4]=0;#40 SR29_IN=0;
#41 IR[11:8]=8;#41 IR[7:0] =1 ; #41 SR29_IN=0;
#50 Rs=0;#50 Rm=0;#50 IR[27:25]=3'b101;#50 SR29_IN=0;
join
initial #sim_time $finish;
initial begin
$dumpfile("BarrelShifterTestBench.vcd");
$dumpvars(0,BarrelShifterTestBench);
$display(" Test Results" );
$monitor("Rs=%8h,Rm=%8h,IR=%8h,Out=%8h,SR29_IN=%1b,SR29_OUT=%1b",Rs,Rm,IR,Out,SR29_IN,SR29_OUT);
end
endmodule
//iverilog BarrelShifter.v BarrelShifterTestBench.v
//reference 1 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIHDDCIF.html |
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: tx_run_length_limiter
*
* Description:
* The idea is to break the counts up into manageable chunks. FPGAs have 6-input LUTs, so a
* reasonable granularity is 5. This means that we check 5 bits + the previous bit in every chunk.
*
* Granularity 1 should be more accurate, but uses more resources.
*
* When there are no bit flips in the input, count_top and count_bottom should be equal.
* Calculating them separately is faster and uses fewer resources.
*/
`default_nettype none
module tx_run_length_limiter #(
parameter LANE_WIDTH =64,
parameter GRANULARITY =4,
parameter RUN_LIMIT =85
)
(
input wire clk,
input wire res_n,
input wire enable,
input wire [LANE_WIDTH-1:0] data_in,
output reg [LANE_WIDTH-1:0] data_out,
output reg rf_bit_flip
);
localparam NUM_CHUNKS = (LANE_WIDTH + GRANULARITY-1)/(GRANULARITY);
localparam REM_BITS = LANE_WIDTH - (GRANULARITY * (LANE_WIDTH/GRANULARITY));
localparam COUNT_BITS = 8;
wire [NUM_CHUNKS-1:0] no_flip;
wire [NUM_CHUNKS-1:0] still_counting_top;
wire [NUM_CHUNKS-1:0] still_counting_bottom;
wire [COUNT_BITS-1:0] count_top;
wire [COUNT_BITS-1:0] count_top_part [NUM_CHUNKS-1:0];
wire [COUNT_BITS-1:0] count_bottom;
wire [COUNT_BITS-1:0] count_bottom_part [NUM_CHUNKS-1:0];
wire bit_flip;
reg [COUNT_BITS-1:0] count_bottom_d1;
reg no_flip_bottom_d1;
reg data_in_bottom_d1;
genvar chunk;
genvar chunkT;
genvar chunkB;
generate
assign no_flip[0] = &( {data_in[GRANULARITY-1:0],data_in_bottom_d1}) ||
&(~{data_in[GRANULARITY-1:0],data_in_bottom_d1});
for(chunk=1; chunk<NUM_CHUNKS-1; chunk=chunk+1) begin : no_flip_gen
assign no_flip[chunk] = &( data_in[(chunk+1)*(GRANULARITY)-1:chunk*(GRANULARITY)-1]) ||
&(~data_in[(chunk+1)*(GRANULARITY)-1:chunk*(GRANULARITY)-1]);
end
assign no_flip[NUM_CHUNKS-1] = &( data_in[LANE_WIDTH-1:(NUM_CHUNKS-1)*(GRANULARITY)-1]) ||
&(~data_in[LANE_WIDTH-1:(NUM_CHUNKS-1)*(GRANULARITY)-1]);
// Start at the top and count until a flip is found
assign still_counting_top[0] = no_flip[0];
assign count_top_part[0] = (no_flip[0] ? GRANULARITY : 0);
for(chunkT=1; chunkT<NUM_CHUNKS; chunkT=chunkT+1) begin : count_top_gen
assign still_counting_top[chunkT] = still_counting_top[chunkT-1] && no_flip[chunkT];
assign count_top_part[chunkT] = (still_counting_top[chunkT] ? GRANULARITY : 0) + count_top_part[chunkT-1];
end
assign count_top = (still_counting_top[NUM_CHUNKS-1] ? LANE_WIDTH : // No flips found
count_top_part[NUM_CHUNKS-2]) + // Take the last value
(no_flip[0] ? (count_bottom_d1 == 0 ? 1 : count_bottom_d1) : 0); // Add the saved count
// Start at the bottom and count until a flip is found
assign still_counting_bottom[0] = no_flip[NUM_CHUNKS-1];
assign count_bottom_part[0] = 0;
for(chunkB=1; chunkB<NUM_CHUNKS; chunkB=chunkB+1) begin : count_bottom_gen
assign still_counting_bottom[chunkB] = still_counting_bottom[chunkB-1] && no_flip[NUM_CHUNKS-1-chunkB];
assign count_bottom_part[chunkB] = (still_counting_bottom[chunkB] ? GRANULARITY : 0) + count_bottom_part[chunkB-1];
end
assign count_bottom = still_counting_bottom[NUM_CHUNKS-1] ? LANE_WIDTH + (count_bottom_d1 == 0 ? 1 : count_bottom_d1) : // No flips found + saved count
count_bottom_part[NUM_CHUNKS-2] + // Take the last value
(no_flip[NUM_CHUNKS-1] ? (REM_BITS ? REM_BITS : GRANULARITY) + 1 : 0); // Add the remainder
endgenerate
assign bit_flip = count_top > (RUN_LIMIT - (GRANULARITY-1) - (REM_BITS ? REM_BITS-1 : GRANULARITY-1));
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
`ifdef RESET_ALL
if(!res_n) begin
data_out <= {DWIDTH {1'b0}};
end else
`endif
begin
if (enable && bit_flip) begin
data_out <= {data_in[LANE_WIDTH-1:1], ~data_in[0]};
end else begin
data_out <= data_in;
end
end
if (!res_n) begin
count_bottom_d1 <= { COUNT_BITS {1'b0}};
no_flip_bottom_d1 <= 1'b0;
data_in_bottom_d1 <= 1'b0;
rf_bit_flip <= 1'b0;
end else begin
count_bottom_d1 <= count_bottom;
no_flip_bottom_d1 <= no_flip[NUM_CHUNKS-1];
data_in_bottom_d1 <= data_in[LANE_WIDTH-1];
if (enable && bit_flip) begin
rf_bit_flip <= bit_flip;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V |
/**************************************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/**************************************************************************************************/
`default_nettype none
`include "define.v"
/***** Sorter Cell *****/
/**************************************************************************************************/
module SCELL(input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [`SORTW-1:0] din1,
input wire [`SORTW-1:0] din2,
input wire full,
output wire [`SORTW-1:0] dout,
output wire enq);
wire cmp1 = (din1 < din2);
function [`SORTW-1:0] mux;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign enq = (!full && valid1 && valid2);
assign deq1 = (enq && cmp1);
assign deq2 = (enq && !cmp1);
assign dout = mux(din2, din1, cmp1);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire [`SORTW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den; // (!im_full && den);
wire im_deq = (req && !im_emp);
always @(posedge CLK) im_req <= (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`SORTW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [3:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`SORTW-1:0] mux;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[31:0], dot[31:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==15)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==14)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {32'b0, dot_t[`DRAMW-1:32]};
2'b11: dot_t <= {32'b0, dot[`DRAMW-1:32]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`SORTW-1:0] din, // data in
output wire [`SORTW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORTW-1:0] mux32;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
/*****************************************/
wire [`SORTW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`SORTW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux32(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 1;
if (ecnt==1 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`SORTW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`SORTW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`SORTW-1:0] d00, d01, d02, d03;
assign {d00, d01, d02, d03} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [31:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [31:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [31:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [31:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [31:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [31:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [31:0] F07_din, F07_dot; wire [1:0] F07_cnt;
INBUF IN04(CLK, RST, full[0], F04_full, F04_enq, d00, F04_din, enq[0], phase, irst);
INBUF IN05(CLK, RST, full[1], F05_full, F05_enq, d01, F05_din, enq[1], phase, irst);
INBUF IN06(CLK, RST, full[2], F06_full, F06_enq, d02, F06_din, enq[2], phase, irst);
INBUF IN07(CLK, RST, full[3], F07_full, F07_enq, d03, F07_din, enq[3], phase, irst);
MRE2 #(1,32) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1,32) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1,32) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1,32) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1,32) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1,32) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1,32) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
SCELL S01(!F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL S02(!F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL S03(!F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`SORTW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [3:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:32]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 15);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire [`SRTP_WAY:0] DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg [`SRTP_WAY:0] DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg [`SRTP_WAY:0] DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg [`SRTP_WAY:0] pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester A for data
reg [`SRTP_WAY:0] pcB; // pipeline regester A for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester A for data
reg [`SRTP_WAY:0] pcC; // pipeline regester A for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester A for data
reg [`SRTP_WAY:0] pcD; // pipeline regester A for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester A for data
reg [`SRTP_WAY:0] pcE; // pipeline regester A for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester A for data
reg [`SRTP_WAY:0] pcF; // pipeline regester A for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester A for data
reg [`SRTP_WAY:0] pcG; // pipeline regester A for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester A for data
reg [`SRTP_WAY:0] pcH; // pipeline regester A for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester A for data
reg [`SRTP_WAY:0] pcI; // pipeline regester A for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/***** dummy logic *****/
/**************************************************************************************************/
module CORE_W(input wire CLK, // clock
input wire RST_in, // reset
output reg initdone, // dram initialize is done
output reg sortdone, // sort is finished
input wire d_busy_in, // DRAM busy
input wire [1:0] d_mode_in, // DRAM mode
input wire din_bit, // DRAM data out
input wire din_en_in, // DRAM data out enable
output reg [3:0] data_out, // DRAM data in
input wire d_w_in, // DRAM write flag
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
output wire ERROR); //
reg RST; always @(posedge CLK) RST <= RST_in;
wire initdone_w; always @(posedge CLK) initdone <= initdone_w;
wire sortdone_w; always @(posedge CLK) sortdone <= sortdone_w;
reg d_busy; always @(posedge CLK) d_busy <= d_busy_in;
reg [1:0] d_mode; always @(posedge CLK) d_mode <= d_mode_in;
reg [`DRAMW-1:0] din; always @(posedge CLK) din <= (RST) ? 0 : {din[`DRAMW-2:0], din_bit};
reg din_en; always @(posedge CLK) din_en <= din_en_in;
wire [1:0] d_req_w; always @(posedge CLK) d_req <= d_req_w;
wire dout_en;
wire [`DRAMW-1:0] dout;
reg [`DRAMW-1:0] dout_r;
always @(posedge CLK) dout_r <= dout;
reg d_w; always @(posedge CLK) d_w <= d_w_in;
always @(posedge CLK) data_out <= {^dout_r[127:0], ^dout_r[128+127:128],
^dout_r[256+127:256], ^dout_r[384+127:384]};
wire [31:0] d_initadr_w, d_blocks_w;
always @(posedge CLK) d_initadr <= d_initadr_w;
always @(posedge CLK) d_blocks <= d_blocks_w;
CORE core(CLK, RST, initdone_w, sortdone_w,
d_busy, dout, d_w, din, din_en, d_req_w, d_initadr_w, d_blocks_w, ERROR);
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
output reg initdone, // dram initialize is done
output reg sortdone, // sort is finished
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
output reg ERROR); // Sorting value ERROR ?
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [256-1:0] mux256;
input [256-1:0] a;
input [256-1:0] b;
input sel;
begin
case (sel)
1'b0: mux256 = a;
1'b1: mux256 = b;
endcase
end
endfunction
function [255:0] mux4in256;
input [255:0] a;
input [255:0] b;
input [255:0] c;
input [255:0] d;
input [3:0] sel;
begin
case (sel)
4'h1: mux4in256 = a;
4'h2: mux4in256 = b;
4'h4: mux4in256 = c;
4'h8: mux4in256 = d;
endcase
end
endfunction
/**********************************************************************************************/
reg idone_a;
reg idone_b;
reg idone_c;
reg idone_d;
wire [`DRAMW-1:0] OB_dot0;
wire [`DRAMW-1:0] OB_dot1;
wire [`DRAMW-1:0] OB_dot2;
wire [`DRAMW-1:0] OB_dot3;
wire OB_req_a;
wire OB_req_b;
wire OB_req_c;
wire OB_req_d;
wire OB_full0;
wire OB_full1;
wire OB_full2;
wire OB_full3;
wire [`PHASE_W] l_phase = `LAST_PHASE;
reg [`DRAMW-1:0] dout_t;
reg [`DRAMW-1:0] dout_tta, dout_ttb;
reg [`DRAMW-1:0] dout_t0_a;
reg [`DRAMW-1:0] dout_t0_b;
reg [`DRAMW-1:0] dout_t0_c;
reg [`DRAMW-1:0] dout_t0_d;
reg doen_t;
reg doen_tta, doen_ttb;
reg doen_t0_a;
reg doen_t0_b;
reg doen_t0_c;
reg doen_t0_d;
reg [`SORT_WAY-1:0] req_tt0_a, req_tt1_a;
reg [`SORT_WAY-1:0] req_tt0_b, req_tt1_b;
reg [`SORT_WAY-1:0] req_tt0_c, req_tt1_c;
reg [`SORT_WAY-1:0] req_tt0_d, req_tt1_d;
reg [`SORT_WAY-1:0] req_ta;
reg [`SORT_WAY-1:0] req_tb;
reg [`SORT_WAY-1:0] req_tc;
reg [`SORT_WAY-1:0] req_td;
reg req_gga, req_ggb, req_ggc, req_ggd;
reg req_ga, req_gb, req_gc, req_gd;
reg [`SORT_WAY-1:0] req_a, req_b, req_c, req_d;
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
reg [31:0] elem; // sorted elements in a phase
reg [31:0] elem_a;
reg [31:0] elem_b;
reg [31:0] elem_c;
reg [31:0] elem_d;
reg [`PHASE_W] phase; //
reg [`PHASE_W] phase_a;
reg [`PHASE_W] phase_b;
reg [`PHASE_W] phase_c;
reg [`PHASE_W] phase_d;
reg last_phase;
reg last_phase_a;
reg last_phase_b;
reg pchange_a;
reg pchange_b;
reg pchange_c;
reg pchange_d;
reg iter_done_a;
reg iter_done_b;
reg iter_done_c;
reg iter_done_d;
reg [31:0] ecnt; // sorted elements in an iteration
reg [31:0] ecnt_a;
reg [31:0] ecnt_b;
reg [31:0] ecnt_c;
reg [31:0] ecnt_d;
reg irst_a;
reg irst_b;
reg irst_c;
reg irst_d;
reg frst_a;
reg frst_b;
reg frst_c;
reg frst_d;
reg pexe_done_a;
reg pexe_done_b;
reg pexe_done_c;
reg pexe_done_d;
reg pexe_done_a_p;
reg pexe_done_b_p;
reg pexe_done_c_p;
reg pexe_done_d_p;
reg RSTa;
always @(posedge CLK) RSTa <= RST_IN;
reg RSTb;
always @(posedge CLK) RSTb <= RST_IN;
reg RSTc;
always @(posedge CLK) RSTc <= RST_IN;
reg RSTd;
always @(posedge CLK) RSTd <= RST_IN;
/**********************************************************************************************/
wire [`SORTW-1:0] d00_0, d01_0, d02_0, d03_0;
wire [`SORTW-1:0] d00_1, d01_1, d02_1, d03_1;
wire [`SORTW-1:0] d00_2, d01_2, d02_2, d03_2;
wire [`SORTW-1:0] d00_3, d01_3, d02_3, d03_3;
wire ib00_req_a, ib01_req_a, ib02_req_a, ib03_req_a;
wire ib00_req_b, ib01_req_b, ib02_req_b, ib03_req_b;
wire ib00_req_c, ib01_req_c, ib02_req_c, ib03_req_c;
wire ib00_req_d, ib01_req_d, ib02_req_d, ib03_req_d;
wire F01_emp0;
wire F01_emp1;
wire F01_emp2;
wire F01_emp3;
wire F01_deq0 = !F01_emp0 && !OB_full0;
wire F01_deq1 = !F01_emp1 && !OB_full1;
wire F01_deq2 = !F01_emp2 && !OB_full2;
wire F01_deq3 = !F01_emp3 && !OB_full3;
wire [`SORTW-1:0] F01_dot0;
wire [`SORTW-1:0] F01_dot1;
wire [`SORTW-1:0] F01_dot2;
wire [`SORTW-1:0] F01_dot3;
wire [`SORTW*`SORT_WAY-1:0] s_din0 = {d00_0, d01_0, d02_0, d03_0};
wire [`SORTW*`SORT_WAY-1:0] s_din1 = {d00_1, d01_1, d02_1, d03_1};
wire [`SORTW*`SORT_WAY-1:0] s_din2 = {d00_2, d01_2, d02_2, d03_2};
wire [`SORTW*`SORT_WAY-1:0] s_din3 = {d00_3, d01_3, d02_3, d03_3};
wire [`SORT_WAY-1:0] enq0;
wire [`SORT_WAY-1:0] enq1;
wire [`SORT_WAY-1:0] enq2;
wire [`SORT_WAY-1:0] enq3;
wire [`SORT_WAY-1:0] s_ful0;
wire [`SORT_WAY-1:0] s_ful1;
wire [`SORT_WAY-1:0] s_ful2;
wire [`SORT_WAY-1:0] s_ful3;
wire [`DRAMW-1:0] stnet_dout;
wire [`SRTP_WAY:0] stnet_douten;
SORTINGNETWORK sortingnetwork(CLK,
RSTa,
{req_td, req_tc, req_tb, req_ta, doen_t},
dout_t,
stnet_dout,
stnet_douten);
INMOD2 im00_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[0], s_ful0[0], d00_0, enq0[0], ib00_req_a);
INMOD2 im01_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[1], s_ful0[1], d01_0, enq0[1], ib01_req_a);
INMOD2 im02_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[2], s_ful0[2], d02_0, enq0[2], ib02_req_a);
INMOD2 im03_0(CLK, RSTa, dout_t0_a, doen_t0_a & req_tt1_a[3], s_ful0[3], d03_0, enq0[3], ib03_req_a);
INMOD2 im00_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[0], s_ful1[0], d00_1, enq1[0], ib00_req_b);
INMOD2 im01_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[1], s_ful1[1], d01_1, enq1[1], ib01_req_b);
INMOD2 im02_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[2], s_ful1[2], d02_1, enq1[2], ib02_req_b);
INMOD2 im03_1(CLK, RSTb, dout_t0_b, doen_t0_b & req_tt1_b[3], s_ful1[3], d03_1, enq1[3], ib03_req_b);
INMOD2 im00_2(CLK, RSTc, dout_t0_c, doen_t0_c & req_tt1_c[0], s_ful2[0], d00_2, enq2[0], ib00_req_c);
INMOD2 im01_2(CLK, RSTc, dout_t0_c, doen_t0_c & req_tt1_c[1], s_ful2[1], d01_2, enq2[1], ib01_req_c);
INMOD2 im02_2(CLK, RSTc, dout_t0_c, doen_t0_c & req_tt1_c[2], s_ful2[2], d02_2, enq2[2], ib02_req_c);
INMOD2 im03_2(CLK, RSTc, dout_t0_c, doen_t0_c & req_tt1_c[3], s_ful2[3], d03_2, enq2[3], ib03_req_c);
INMOD2 im00_3(CLK, RSTd, dout_t0_d, doen_t0_d & req_tt1_d[0], s_ful3[0], d00_3, enq3[0], ib00_req_d);
INMOD2 im01_3(CLK, RSTd, dout_t0_d, doen_t0_d & req_tt1_d[1], s_ful3[1], d01_3, enq3[1], ib01_req_d);
INMOD2 im02_3(CLK, RSTd, dout_t0_d, doen_t0_d & req_tt1_d[2], s_ful3[2], d02_3, enq3[2], ib02_req_d);
INMOD2 im03_3(CLK, RSTd, dout_t0_d, doen_t0_d & req_tt1_d[3], s_ful3[3], d03_3, enq3[3], ib03_req_d);
STREE stree0(CLK, RSTa, irst_a, frst_a, phase_a, s_din0, enq0, s_ful0, F01_deq0, F01_dot0, F01_emp0);
STREE stree1(CLK, RSTb, irst_b, frst_b, phase_b, s_din1, enq1, s_ful1, F01_deq1, F01_dot1, F01_emp1);
STREE stree2(CLK, RSTc, irst_c, frst_c, phase_c, s_din2, enq2, s_ful2, F01_deq2, F01_dot2, F01_emp2);
STREE stree3(CLK, RSTd, irst_d, frst_d, phase_d, s_din3, enq3, s_ful3, F01_deq3, F01_dot3, F01_emp3);
reg OB_deq_ta;
reg OB_deq_tb;
reg OB_deq_tc;
reg OB_deq_td;
wire [3:0] OB_dot_sel ={OB_deq_td, OB_deq_tc, OB_deq_tb, OB_deq_ta};
wire OB_deq0 = idone_a && d_w && OB_deq_ta;
wire OB_deq1 = idone_b && d_w && OB_deq_tb;
wire OB_deq2 = idone_c && d_w && OB_deq_tc;
wire OB_deq3 = idone_d && d_w && OB_deq_td;
OTMOD ob0(CLK, RSTa, F01_deq0, F01_dot0, OB_deq0, OB_dot0, OB_full0, OB_req_a);
OTMOD ob1(CLK, RSTb, F01_deq1, F01_dot1, OB_deq1, OB_dot1, OB_full1, OB_req_b);
OTMOD ob2(CLK, RSTc, F01_deq2, F01_dot2, OB_deq2, OB_dot2, OB_full2, OB_req_c);
OTMOD ob3(CLK, RSTd, F01_deq3, F01_dot3, OB_deq3, OB_dot3, OB_full3, OB_req_d);
/********************************** Error Check ***********************************************/
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
reg [`SORTW-1:0] check_cnt;
always @(posedge CLK) begin
if (RSTa) begin check_cnt<=1; ERROR<=0; end
if (last_phase && F01_deq0) begin
if (check_cnt != F01_dot0) begin
ERROR <= 1;
$write("Error in core.v: %d %d\n", F01_dot0, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt <= check_cnt + 1;
end
end
end else if (`INITTYPE != "xorshift") begin
always @(posedge CLK) begin
ERROR <= 1;
// for simulation
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.v\n");
$finish();
end
end
endgenerate
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
reg [31:0] w_addr; //
reg [31:0] w_addr_a; //
reg [31:0] w_addr_b; //
reg [31:0] w_addr_c; //
reg [31:0] w_addr_d; //
reg [2:0] state; // state
reg [31:0] radr_a, radr_b, radr_c, radr_d;
reg [31:0] radr_a_a, radr_b_a, radr_c_a, radr_d_a;
reg [31:0] radr_a_b, radr_b_b, radr_c_b, radr_d_b;
reg [31:0] radr_a_c, radr_b_c, radr_c_c, radr_d_c;
reg [31:0] radr_a_d, radr_b_d, radr_c_d, radr_d_d;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d;
reg [27:0] cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a;
reg [27:0] cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b;
reg [27:0] cnt_a_c, cnt_b_c, cnt_c_c, cnt_d_c;
reg [27:0] cnt_a_d, cnt_b_d, cnt_c_d, cnt_d_d;
reg c_a, c_b, c_c, c_d;
reg c_a_a, c_b_a, c_c_a, c_d_a;
reg c_a_b, c_b_b, c_c_b, c_d_b;
reg c_a_c, c_b_c, c_c_c, c_d_c;
reg c_a_d, c_b_d, c_c_d, c_d_d;
always @(posedge CLK) begin
if (RSTa || pchange_a || pchange_b || pchange_c || pchange_d) begin
if (RSTa) {initdone, state} <= 0;
if (RSTa) {d_req, d_initadr, d_blocks} <= 0;
if (RSTa) {req_a, req_b, req_c, req_d} <= 0;
if (RSTa) {req_ga, req_gb, req_gc, req_gd} <= 0;
if (RSTa) {req_gga, req_ggb, req_ggc, req_ggd} <= 0;
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, l_phase[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
{cnt_a, cnt_b, cnt_c, cnt_d} <= 0;
{c_a, c_b, c_c, c_d} <= 0;
if ((RSTa || pchange_a) && !pexe_done_a_p) begin
w_addr_a <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*0);
radr_b_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*1);
radr_c_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*2);
radr_d_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*3);
{cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a} <= 0;
{c_a_a, c_b_a, c_c_a, c_d_a} <= 0;
OB_deq_ta <= 0;
end
if ((RSTa || pchange_b) && !pexe_done_b_p) begin
w_addr_b <= mux32(((`SORT_ELM>>3) | (`SORT_ELM>>1)), (`SORT_ELM>>3), phase_b[0]);
radr_a_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | (`SORT_ELM>>3);
radr_b_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>3);
radr_c_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>3);
radr_d_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>3);
{cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b} <= 0;
{c_a_b, c_b_b, c_c_b, c_d_b} <= 0;
OB_deq_tb <= 0;
end
if ((RSTa || pchange_c) && !pexe_done_c_p) begin
w_addr_c <= mux32(((`SORT_ELM>>2) | (`SORT_ELM>>1)), (`SORT_ELM>>2), phase_c[0]);
radr_a_c <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | (`SORT_ELM>>2);
radr_b_c <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2);
radr_c_c <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2);
radr_d_c <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2);
{cnt_a_c, cnt_b_c, cnt_c_c, cnt_d_c} <= 0;
{c_a_c, c_b_c, c_c_c, c_d_c} <= 0;
OB_deq_tc <= 0;
end
if ((RSTa || pchange_d) && !pexe_done_d_p) begin
w_addr_d <= mux32(((`SORT_ELM>>3) | ((`SORT_ELM>>2) | (`SORT_ELM>>1))), ((`SORT_ELM>>3) | (`SORT_ELM>>2)), phase_d[0]);
radr_a_d <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | ((`SORT_ELM>>3) | (`SORT_ELM>>2));
radr_b_d <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | ((`SORT_ELM>>3) | (`SORT_ELM>>2));
radr_c_d <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | ((`SORT_ELM>>3) | (`SORT_ELM>>2));
radr_d_d <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | ((`SORT_ELM>>3) | (`SORT_ELM>>2));
{cnt_a_d, cnt_b_d, cnt_c_d, cnt_d_d} <= 0;
{c_a_d, c_b_d, c_c_d, c_d_d} <= 0;
OB_deq_td <= 0;
end
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= (`SORT_ELM>>4); // 16word/block for VC707, 2word/b for Tokuden
d_initadr <= 0; //
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy) begin
initdone <= 1;
OB_deq_ta <= 0;
OB_deq_tb <= 0;
OB_deq_tc <= 0;
OB_deq_td <= 0;
case (last_phase)
1'b0: begin
if (ib00_req_a && !c_a_a) begin req_a <= 4'h1; req_gga <= 1; end //
else if (ib01_req_a && !c_b_a) begin req_a <= 4'h2; req_gga <= 1; end //
else if (ib02_req_a && !c_c_a) begin req_a <= 4'h4; req_gga <= 1; end //
else if (ib03_req_a && !c_d_a) begin req_a <= 4'h8; req_gga <= 1; end //
if (ib00_req_b && !c_a_b) begin req_b <= 4'h1; req_ggb <= 1; end //
else if (ib01_req_b && !c_b_b) begin req_b <= 4'h2; req_ggb <= 1; end //
else if (ib02_req_b && !c_c_b) begin req_b <= 4'h4; req_ggb <= 1; end //
else if (ib03_req_b && !c_d_b) begin req_b <= 4'h8; req_ggb <= 1; end //
if (ib00_req_c && !c_a_c) begin req_c <= 4'h1; req_ggc <= 1; end //
else if (ib01_req_c && !c_b_c) begin req_c <= 4'h2; req_ggc <= 1; end //
else if (ib02_req_c && !c_c_c) begin req_c <= 4'h4; req_ggc <= 1; end //
else if (ib03_req_c && !c_d_c) begin req_c <= 4'h8; req_ggc <= 1; end //
if (ib00_req_d && !c_a_d) begin req_d <= 4'h1; req_ggd <= 1; end //
else if (ib01_req_d && !c_b_d) begin req_d <= 4'h2; req_ggd <= 1; end //
else if (ib02_req_d && !c_c_d) begin req_d <= 4'h4; req_ggd <= 1; end //
else if (ib03_req_d && !c_d_d) begin req_d <= 4'h8; req_ggd <= 1; end //
state <= 2;
end
1'b1: begin
if (ib00_req_a && !c_a) begin req<=4'h1; state<=3; end //
else if (ib01_req_a && !c_b) begin req<=4'h2; state<=3; end //
else if (ib02_req_a && !c_c) begin req<=4'h4; state<=3; end //
else if (ib03_req_a && !c_d) begin req<=4'h8; state<=3; end //
else if (OB_req_a) begin OB_deq_ta <= 1; state<=4; end // WRITE
end
endcase
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy) begin
if (req_gga) begin req_ga <= 1; {req_b, req_c, req_d} <= 0; state <= 3; end
else if (req_ggb) begin req_gb <= 1; {req_a, req_c, req_d} <= 0; state <= 3; end
else if (req_ggc) begin req_gc <= 1; {req_a, req_b, req_d} <= 0; state <= 3; end
else if (req_ggd) begin req_gd <= 1; {req_a, req_b, req_c} <= 0; state <= 3; end
else if (OB_req_a) begin OB_deq_ta <= 1; state <= 4; end // WRITE
else if (OB_req_b) begin OB_deq_tb <= 1; state <= 5; end // WRITE
else if (OB_req_c) begin OB_deq_tc <= 1; state <= 6; end // WRITE
else if (OB_req_d) begin OB_deq_td <= 1; state <= 7; end // WRITE
else state <= 1;
{req_gga, req_ggb, req_ggc, req_ggd} <= 0;
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin
d_req <= 0;
state <= 1;
{req_ga, req_gb, req_gc, req_gd} <= 0;
end else if (!d_busy) begin
case (last_phase)
1'b0: begin
req_ta <= req_a;
case ({req_gd, req_gc, req_gb, req_ga})
4'b0001: begin
case (req_a)
4'h1: begin
d_initadr <= mux32(radr_a_a, (radr_a_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a_a <= radr_a_a+(`D_RS);
cnt_a_a <= cnt_a_a+1;
c_a_a <= (cnt_a_a>=`WAYP_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b_a, (radr_b_a | (`SORT_ELM>>1)), phase_a[0]);
radr_b_a <= radr_b_a+(`D_RS);
cnt_b_a <= cnt_b_a+1;
c_b_a <= (cnt_b_a>=`WAYP_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c_a, (radr_c_a | (`SORT_ELM>>1)), phase_a[0]);
radr_c_a <= radr_c_a+(`D_RS);
cnt_c_a <= cnt_c_a+1;
c_c_a <= (cnt_c_a>=`WAYP_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d_a, (radr_d_a | (`SORT_ELM>>1)), phase_a[0]);
radr_d_a <= radr_d_a+(`D_RS);
cnt_d_a <= cnt_d_a+1;
c_d_a <= (cnt_d_a>=`WAYP_CN_);
end
endcase
end
4'b0010: begin
case (req_b)
4'h1: begin
d_initadr <= mux32(radr_a_b, (radr_a_b | (`SORT_ELM>>1)), phase_b[0]);
radr_a_b <= radr_a_b+(`D_RS);
cnt_a_b <= cnt_a_b+1;
c_a_b <= (cnt_a_b>=`WAYP_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b_b, (radr_b_b | (`SORT_ELM>>1)), phase_b[0]);
radr_b_b <= radr_b_b+(`D_RS);
cnt_b_b <= cnt_b_b+1;
c_b_b <= (cnt_b_b>=`WAYP_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c_b, (radr_c_b | (`SORT_ELM>>1)), phase_b[0]);
radr_c_b <= radr_c_b+(`D_RS);
cnt_c_b <= cnt_c_b+1;
c_c_b <= (cnt_c_b>=`WAYP_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d_b, (radr_d_b | (`SORT_ELM>>1)), phase_b[0]);
radr_d_b <= radr_d_b+(`D_RS);
cnt_d_b <= cnt_d_b+1;
c_d_b <= (cnt_d_b>=`WAYP_CN_);
end
endcase
end
4'b0100: begin
case (req_c)
4'h1: begin
d_initadr <= mux32(radr_a_c, (radr_a_c | (`SORT_ELM>>1)), phase_c[0]);
radr_a_c <= radr_a_c+(`D_RS);
cnt_a_c <= cnt_a_c+1;
c_a_c <= (cnt_a_c>=`WAYP_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b_c, (radr_b_c | (`SORT_ELM>>1)), phase_c[0]);
radr_b_c <= radr_b_c+(`D_RS);
cnt_b_c <= cnt_b_c+1;
c_b_c <= (cnt_b_c>=`WAYP_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c_c, (radr_c_c | (`SORT_ELM>>1)), phase_c[0]);
radr_c_c <= radr_c_c+(`D_RS);
cnt_c_c <= cnt_c_c+1;
c_c_c <= (cnt_c_c>=`WAYP_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d_c, (radr_d_c | (`SORT_ELM>>1)), phase_c[0]);
radr_d_c <= radr_d_c+(`D_RS);
cnt_d_c <= cnt_d_c+1;
c_d_c <= (cnt_d_c>=`WAYP_CN_);
end
endcase
end
4'b1000: begin
case (req_d)
4'h1: begin
d_initadr <= mux32(radr_a_d, (radr_a_d | (`SORT_ELM>>1)), phase_d[0]);
radr_a_d <= radr_a_d+(`D_RS);
cnt_a_d <= cnt_a_d+1;
c_a_d <= (cnt_a_d>=`WAYP_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b_d, (radr_b_d | (`SORT_ELM>>1)), phase_d[0]);
radr_b_d <= radr_b_d+(`D_RS);
cnt_b_d <= cnt_b_d+1;
c_b_d <= (cnt_b_d>=`WAYP_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c_d, (radr_c_d | (`SORT_ELM>>1)), phase_d[0]);
radr_c_d <= radr_c_d+(`D_RS);
cnt_c_d <= cnt_c_d+1;
c_c_d <= (cnt_c_d>=`WAYP_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d_d, (radr_d_d | (`SORT_ELM>>1)), phase_d[0]);
radr_d_d <= radr_d_d+(`D_RS);
cnt_d_d <= cnt_d_d+1;
c_d_d <= (cnt_d_d>=`WAYP_CN_);
end
endcase
end
endcase
end
1'b1: begin
req_ta <= req;
case (req)
4'h1: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), l_phase[0]);
radr_a <= radr_a+(`D_RS);
cnt_a <= cnt_a+1;
c_a <= (cnt_a>=`WAY_CN_);
end
4'h2: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), l_phase[0]);
radr_b <= radr_b+(`D_RS);
cnt_b <= cnt_b+1;
c_b <= (cnt_b>=`WAY_CN_);
end
4'h4: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), l_phase[0]);
radr_c <= radr_c+(`D_RS);
cnt_c <= cnt_c+1;
c_c <= (cnt_c>=`WAY_CN_);
end
4'h8: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), l_phase[0]);
radr_d <= radr_d+(`D_RS);
cnt_d <= cnt_d+1;
c_d <= (cnt_d>=`WAY_CN_);
end
endcase
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_tb <= req_b;
req_tc <= req_c;
req_td <= req_d;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE;
d_blocks <= `DRAM_WBLOCKS;
case (last_phase)
1'b0: begin
d_initadr <= w_addr_a;
w_addr_a <= w_addr_a + (`D_WS);
end
1'b1: begin
d_initadr <= w_addr;
w_addr <= w_addr + (`D_WS);
end
endcase
end
end
////////////////////////////////////////////////////////////////////////////////////////
5: begin ///// WRITE data to DRAM
if(d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE;
d_blocks <= `DRAM_WBLOCKS;
d_initadr <= w_addr_b;
w_addr_b <= w_addr_b + (`D_WS);
end
end
////////////////////////////////////////////////////////////////////////////////////////
6: begin ///// WRITE data to DRAM
if(d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE;
d_blocks <= `DRAM_WBLOCKS;
d_initadr <= w_addr_c;
w_addr_c <= w_addr_c + (`D_WS);
end
end
////////////////////////////////////////////////////////////////////////////////////////
7: begin ///// WRITE data to DRAM
if(d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE;
d_blocks <= `DRAM_WBLOCKS;
d_initadr <= w_addr_d;
w_addr_d <= w_addr_d + (`D_WS);
end
end
endcase
end
end
/***** WRITE : feed the initial data to be stored to DRAM *****/
/**********************************************************************************************/
reg RST_INI; // reset signal for value initialization module
always @(posedge CLK) RST_INI <= RSTa;
reg [`SORTW-1:0] i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i,i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a;
generate
if (`INITTYPE == "xorshift") begin
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST_INI, d_w, r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST_INI, d_w, r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST_INI, d_w, r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST_INI, d_w, r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST_INI, d_w, r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST_INI, d_w, r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST_INI, d_w, r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST_INI, d_w, r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST_INI, d_w, r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST_INI, d_w, r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST_INI, d_w, r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST_INI, d_w, r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST_INI, d_w, r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST_INI, d_w, r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST_INI, d_w, r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST_INI, d_w, r15);
always @(posedge CLK) begin
i_a <= r00;
i_b <= r01;
i_c <= r02;
i_d <= r03;
i_e <= r04;
i_f <= r05;
i_g <= r06;
i_h <= r07;
i_i <= r08;
i_j <= r09;
i_k <= r10;
i_l <= r11;
i_m <= r12;
i_n <= r13;
i_o <= r14;
i_p <= r15;
end
end else if (`INITTYPE == "reverse") begin
always @(posedge CLK) begin
if (RST_INI) begin
i_a <= `SORT_ELM+16;
i_b <= `SORT_ELM+16-1;
i_c <= `SORT_ELM+16-2;
i_d <= `SORT_ELM+16-3;
i_e <= `SORT_ELM+16-4;
i_f <= `SORT_ELM+16-5;
i_g <= `SORT_ELM+16-6;
i_h <= `SORT_ELM+16-7;
i_i <= `SORT_ELM+16-8;
i_j <= `SORT_ELM+16-9;
i_k <= `SORT_ELM+16-10;
i_l <= `SORT_ELM+16-11;
i_m <= `SORT_ELM+16-12;
i_n <= `SORT_ELM+16-13;
i_o <= `SORT_ELM+16-14;
i_p <= `SORT_ELM+16-15;
end else begin
if (d_w) begin
i_a <= i_a-16;
i_b <= i_b-16;
i_c <= i_c-16;
i_d <= i_d-16;
i_e <= i_e-16;
i_f <= i_f-16;
i_g <= i_g-16;
i_h <= i_h-16;
i_i <= i_i-16;
i_j <= i_j-16;
i_k <= i_k-16;
i_l <= i_l-16;
i_m <= i_m-16;
i_n <= i_n-16;
i_o <= i_o-16;
i_p <= i_p-16;
end
end
end
end else if (`INITTYPE == "sorted") begin
reg ocen;
always @(posedge CLK) begin
if (RST_INI) begin
ocen <= 0;
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
i_e <= 5;
i_f <= 6;
i_g <= 7;
i_h <= 8;
i_i <= 9;
i_j <= 10;
i_k <= 11;
i_l <= 12;
i_m <= 13;
i_n <= 14;
i_o <= 15;
i_p <= 16;
end else begin
if (d_w) begin
ocen <= 1;
i_a <= mux32(i_a, i_a+16, ocen);
i_b <= mux32(i_b, i_b+16, ocen);
i_c <= mux32(i_c, i_c+16, ocen);
i_d <= mux32(i_d, i_d+16, ocen);
i_e <= mux32(i_e, i_e+16, ocen);
i_f <= mux32(i_f, i_f+16, ocen);
i_g <= mux32(i_g, i_g+16, ocen);
i_h <= mux32(i_h, i_h+16, ocen);
i_i <= mux32(i_i, i_i+16, ocen);
i_j <= mux32(i_j, i_j+16, ocen);
i_k <= mux32(i_k, i_k+16, ocen);
i_l <= mux32(i_l, i_l+16, ocen);
i_m <= mux32(i_m, i_m+16, ocen);
i_n <= mux32(i_n, i_n+16, ocen);
i_o <= mux32(i_o, i_o+16, ocen);
i_p <= mux32(i_p, i_p+16, ocen);
end
end
end
end
endgenerate
always @(posedge CLK) idone_a <= initdone;
always @(posedge CLK) idone_b <= initdone;
always @(posedge CLK) idone_c <= initdone;
always @(posedge CLK) idone_d <= initdone;
assign d_din[255: 0] = mux256({i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a},
mux4in256(OB_dot0[255:0], OB_dot1[255:0], OB_dot2[255:0], OB_dot3[255:0], OB_dot_sel),
idone_a);
assign d_din[511:256] = mux256({i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i},
mux4in256(OB_dot0[511:256], OB_dot1[511:256], OB_dot2[511:256], OB_dot3[511:256], OB_dot_sel),
idone_b);
/**********************************************************************************************/
always @(posedge CLK) begin
dout_t <= d_dout;
doen_t <= d_douten;
// Stage 0
////////////////////////////////////
dout_tta <= stnet_dout;
dout_ttb <= stnet_dout;
doen_tta <= stnet_douten[0];
doen_ttb <= stnet_douten[0];
req_tt0_a <= stnet_douten[`SORT_WAY:1];
req_tt0_b <= stnet_douten[`SORT_WAY*2:`SORT_WAY+1];
req_tt0_c <= stnet_douten[`SORT_WAY*3:`SORT_WAY*2+1];
req_tt0_d <= stnet_douten[`SORT_WAY*4:`SORT_WAY*3+1];
// Stage 1
////////////////////////////////////
dout_t0_a <= dout_tta;
dout_t0_b <= dout_tta;
dout_t0_c <= dout_ttb;
dout_t0_d <= dout_ttb;
doen_t0_a <= doen_tta;
doen_t0_b <= doen_tta;
doen_t0_c <= doen_ttb;
doen_t0_d <= doen_ttb;
req_tt1_a <= req_tt0_a;
req_tt1_b <= req_tt0_b;
req_tt1_c <= req_tt0_c;
req_tt1_d <= req_tt0_d;
end
// for last_phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
last_phase <= 0;
end else begin
if (last_phase_a && last_phase_b) last_phase <= 1;
end
end
always @(posedge CLK) begin
if (RSTa) begin
last_phase_a <= 0;
end else begin
if (pexe_done_a && pexe_done_b) last_phase_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
last_phase_b <= 0;
end else begin
if (pexe_done_c && pexe_done_d) last_phase_b <= 1;
end
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
phase <= `LAST_PHASE;
end else begin
if (elem==`SORT_ELM) phase <= phase+1;
end
end
always @(posedge CLK) begin
if (RSTa) begin
phase_a <= 0;
end else begin
if (elem_a==`SRTP_ELM) phase_a <= phase_a+1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
phase_b <= 0;
end else begin
if (elem_b==`SRTP_ELM) phase_b <= phase_b+1;
end
end
always @(posedge CLK) begin
if (RSTc) begin
phase_c <= 0;
end else begin
if (elem_c==`SRTP_ELM) phase_c <= phase_c+1;
end
end
always @(posedge CLK) begin
if (RSTd) begin
phase_d <= 0;
end else begin
if (elem_d==`SRTP_ELM) phase_d <= phase_d+1;
end
end
// for pexe_done
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
pexe_done_a <= 0;
end else begin
if (phase_a==`LAST_PHASE) pexe_done_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
pexe_done_b <= 0;
end else begin
if (phase_b==`LAST_PHASE) pexe_done_b <= 1;
end
end
always @(posedge CLK) begin
if (RSTc) begin
pexe_done_c <= 0;
end else begin
if (phase_c==`LAST_PHASE) pexe_done_c <= 1;
end
end
always @(posedge CLK) begin
if (RSTd) begin
pexe_done_d <= 0;
end else begin
if (phase_d==`LAST_PHASE) pexe_done_d <= 1;
end
end
// for pexe_done_p
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
pexe_done_a_p <= 0;
end else begin
if (phase_a==`LAST_PHASE-1) pexe_done_a_p <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
pexe_done_b_p <= 0;
end else begin
if (phase_b==`LAST_PHASE-1) pexe_done_b_p <= 1;
end
end
always @(posedge CLK) begin
if (RSTc) begin
pexe_done_c_p <= 0;
end else begin
if (phase_c==`LAST_PHASE-1) pexe_done_c_p <= 1;
end
end
always @(posedge CLK) begin
if (RSTd) begin
pexe_done_d_p <= 0;
end else begin
if (phase_d==`LAST_PHASE-1) pexe_done_d_p <= 1;
end
end
// for elem
// ########################################################################### // not deleted
always @(posedge CLK) begin
if (RSTa) begin
elem <= 0;
elem_a <= 0;
end else begin
case (last_phase)
1'b0: begin
case ({OB_deq0, (elem_a==`SRTP_ELM)})
2'b01: elem_a <= 0;
2'b10: elem_a <= elem_a + 16;
endcase
end
1'b1: begin
case ({OB_deq0, (elem==`SORT_ELM)})
2'b01: elem <= 0;
2'b10: elem <= elem + 16;
endcase
end
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_b <= 0;
end else begin
case ({OB_deq1, (elem_b==`SRTP_ELM)})
2'b01: elem_b <= 0;
2'b10: elem_b <= elem_b + 16;
endcase
end
end
always @(posedge CLK) begin
if (RSTc) begin
elem_c <= 0;
end else begin
case ({OB_deq2, (elem_c==`SRTP_ELM)})
2'b01: elem_c <= 0;
2'b10: elem_c <= elem_c + 16;
endcase
end
end
always @(posedge CLK) begin
if (RSTd) begin
elem_d <= 0;
end else begin
case ({OB_deq3, (elem_d==`SRTP_ELM)})
2'b01: elem_d <= 0;
2'b10: elem_d <= elem_d + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done_a <= (ecnt_a==2);
always @(posedge CLK) iter_done_b <= (ecnt_b==2);
always @(posedge CLK) iter_done_c <= (ecnt_c==2);
always @(posedge CLK) iter_done_d <= (ecnt_d==2);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange_a <= (elem_a==`SRTP_ELM);
always @(posedge CLK) pchange_b <= (elem_b==`SRTP_ELM);
always @(posedge CLK) pchange_c <= (elem_c==`SRTP_ELM);
always @(posedge CLK) pchange_d <= (elem_d==`SRTP_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst_a <= mux1(((ecnt_a==2) || pchange_a), (ecnt==2), last_phase);
always @(posedge CLK) irst_b <= (ecnt_b==2) || pchange_b;
always @(posedge CLK) irst_c <= (ecnt_c==2) || pchange_c;
always @(posedge CLK) irst_d <= (ecnt_d==2) || pchange_d;
// for frst
// ###########################################################################
always @(posedge CLK) frst_a <= mux1((RSTa || (ecnt_a==2) || (elem_a==`SRTP_ELM)), (ecnt==2), last_phase);
always @(posedge CLK) frst_b <= RSTb || (ecnt_b==2) || (elem_b==`SRTP_ELM);
always @(posedge CLK) frst_c <= RSTc || (ecnt_c==2) || (elem_c==`SRTP_ELM);
always @(posedge CLK) frst_d <= RSTd || (ecnt_d==2) || (elem_d==`SRTP_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
ecnt <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase * `WAY_LOG));
end else begin
if (ecnt!=0 && F01_deq0 && last_phase) ecnt <= ecnt - 1;
end
end
always @(posedge CLK) begin
if (RSTa || iter_done_a || pchange_a) begin
ecnt_a <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_a * `WAY_LOG));
end else begin
if (ecnt_a!=0 && F01_deq0 && !pexe_done_a) ecnt_a <= ecnt_a - 1;
end
end
always @(posedge CLK) begin
if (RSTb || iter_done_b || pchange_b) begin
ecnt_b <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_b * `WAY_LOG));
end else begin
if (ecnt_b!=0 && F01_deq1 && !pexe_done_b) ecnt_b <= ecnt_b - 1;
end
end
always @(posedge CLK) begin
if (RSTc || iter_done_c || pchange_c) begin
ecnt_c <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_c * `WAY_LOG));
end else begin
if (ecnt_c!=0 && F01_deq2 && !pexe_done_c) ecnt_c <= ecnt_c - 1;
end
end
always @(posedge CLK) begin
if (RSTd || iter_done_d || pchange_d) begin
ecnt_d <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_d * `WAY_LOG));
end else begin
if (ecnt_d!=0 && F01_deq3 && !pexe_done_d) ecnt_d <= ecnt_d - 1;
end
end
// for sortdone
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
sortdone <= 0;
end else begin
if (phase==(`LAST_PHASE+1)) sortdone <= 1;
end
end
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/*
* A musicbox module / template for the DE0-Nano board
* Origin website:http://www.fpga4fun.com/MusicBox1.html
*/
`define COUNTER_SIZE 32
module music_ROM(
input clk,
input [7:0] address,
output reg [7:0] note
);
always @(posedge clk)
case(address)
0, 1: note <= 8'd27; // C C
2: note <= 8'd29; // D
3: note <= 8'd27; // C
4: note <= 8'd32; // F
5: note <= 8'd31; // E
6: note <= 8'd0;
7, 8: note <= 8'd27; // C C
9: note <= 8'd29; // D
10: note <= 8'd27; // C
11: note <= 8'd34; // G
12: note <= 8'd32; // F
13: note <= 8'd0;
14, 15: note <= 8'd27; //C C
16: note <= 8'd39; // C + 12
17: note <= 8'd24; // A
18: note <= 8'd32; // F
19: note <= 8'd31; // E
20: note <= 8'd29; // D
21: note <= 8'd0;
22, 23: note <= 8'd39; // B B
24: note <= 8'd24; // A
25: note <= 8'd32; // F
26: note <= 8'd34; // G
27: note <= 8'd32; // F
default: note <= 8'd0;
endcase
endmodule
module divide_by12(numer, quotient, remain);
input [5:0] numer;
output [2:0] quotient;
output [3:0] remain;
reg [2:0] quotient;
reg [3:0] remain_bit3_bit2;
assign remain = {remain_bit3_bit2, numer[1:0]}; // the first 2 bits are copied through
always @(numer[5:2]) // and just do a divide by "3" on the remaining bits
case(numer[5:2])
0: begin quotient=0; remain_bit3_bit2=0; end
1: begin quotient=0; remain_bit3_bit2=1; end
2: begin quotient=0; remain_bit3_bit2=2; end
3: begin quotient=1; remain_bit3_bit2=0; end
4: begin quotient=1; remain_bit3_bit2=1; end
5: begin quotient=1; remain_bit3_bit2=2; end
6: begin quotient=2; remain_bit3_bit2=0; end
7: begin quotient=2; remain_bit3_bit2=1; end
8: begin quotient=2; remain_bit3_bit2=2; end
9: begin quotient=3; remain_bit3_bit2=0; end
10: begin quotient=3; remain_bit3_bit2=1; end
11: begin quotient=3; remain_bit3_bit2=2; end
12: begin quotient=4; remain_bit3_bit2=0; end
13: begin quotient=4; remain_bit3_bit2=1; end
14: begin quotient=4; remain_bit3_bit2=2; end
15: begin quotient=5; remain_bit3_bit2=0; end
endcase
endmodule
module musicbox(
//////////// CLOCK //////////
input CLOCK_50,
//////////// SPEAKER //////////
output SPEAKER
);
reg clk;
always @(posedge CLOCK_50) clk <= ~clk;
reg [`COUNTER_SIZE-1:0] tone;
always @(posedge clk) tone <= tone+1;
wire [7:0] fullnote;
music_ROM ROM(.clk(clk), .address(tone[27:23]), .note(fullnote));
wire [2:0] octave;
wire [3:0] note;
divide_by12 divby12(.numer(fullnote[5:0]), .quotient(octave), .remain(note));
reg [8:0] clk_50divider;
always @(note)
case(note)
0: clk_50divider = 512-1; // A
1: clk_50divider = 483-1; // A#/Bb
2: clk_50divider = 456-1; // B
3: clk_50divider = 431-1; // C
4: clk_50divider = 406-1; // C#/Db
5: clk_50divider = 384-1; // D
6: clk_50divider = 362-1; // D#/Eb
7: clk_50divider = 342-1; // E
8: clk_50divider = 323-1; // F
9: clk_50divider = 304-1; // F#/Gb
10: clk_50divider = 287-1; // G
11: clk_50divider = 271-1; // G#/Ab
default: clk_50divider = 0; // should never happen
endcase
reg [8:0] counter_note;
always @(posedge clk) if (counter_note == 0) counter_note <= clk_50divider; else counter_note <= counter_note - 1;
reg [7:0] counter_octave;
always @(posedge clk)
if (counter_note == 0)
begin
if (counter_octave == 0)
counter_octave <= (octave == 0 ? 255:octave == 1 ? 127:octave == 2 ? 63:octave == 3 ? 31:octave == 4 ? 15:7);
else
counter_octave <= counter_octave - 1;
end
reg speaker;
assign SPEAKER = speaker;
always @(posedge clk) if (fullnote != 0 && counter_note == 0 && counter_octave == 0) speaker <= ~speaker;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: top_nto1_pll_diff_rx_and_tx.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Example differential input receiver and transmitter for clock and data using PLL
// Serdes factor and number of data lines are set by constants in the code
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module top_nto1_pll_diff_rx_and_tx (
input reset, // reset (active high)
input [5:0] datain_p, datain_n, // lvds data inputs
input clkin_p, clkin_n, // lvds clock input
output [5:0] dataout_p, dataout_n, // lvds data outputs
output clkout_p, clkout_n) ; // lvds clock output
// Parameters for serdes factor and number of IO pins
parameter integer S = 7 ; // Set the serdes factor to 8
parameter integer D = 6 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] txd ; // Data to serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
reg state ;
reg bslip ;
reg [3:0] count ;
wire [6:0] clk_iserdes_data ;
parameter [S-1:0] TX_CLK_GEN = 7'b1100001 ; // Transmit a constant to make a clock
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_pll_s8_diff #(
.S (S),
.CLKIN_PERIOD (6.700),
.PLLD (1),
.PLLX (S),
.BS ("TRUE")) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
inst_clkin (
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (7'b1100001), // default values for 7:1 video applications
.pattern2 (7'b1100011),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_pll_lckd (), // PLL locked - only used if a 2nd BUFPLL is required
.rx_pllout_xs (), // Multiplied PLL clock - only used if a 2nd BUFPLL is required
.rx_bufpll_lckd (rx_bufpll_lckd)) ;
// Data Inputs
assign not_bufpll_lckd = ~rx_bufpll_lckd ;
serdes_1_to_n_data_s8_diff #(
.S (S),
.D (D))
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclk (rx_bufpll_clk_xn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
always @ (posedge rx_bufg_x1) // process received data
begin
txd <= rxd ;
end
// Transmitter Logic - Instantiate serialiser to generate forwarded clock
serdes_n_to_1_s8_diff #(
.S (S),
.D (1))
inst_clkout (
.dataout_p (clkout_p),
.dataout_n (clkout_n),
.txioclk (rx_bufpll_clk_xn),
.txserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.reset (rst),
.datain (TX_CLK_GEN)); // Transmit a constant to make the clock
// Instantiate Outputs and output serialisers for output data lines
serdes_n_to_1_s8_diff #(
.S (S),
.D (D))
inst_dataout (
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.txioclk (rx_bufpll_clk_xn),
.txserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.reset (rst),
.datain (txd));
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_misc_chunk5.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_misc_chunk5(clk ,sel_bypass ,spare_misc_pad ,
spare_misc_paddata ,obsel ,io_tdo_en ,ckd ,vref ,vddo ,io_tdo ,
rst_val_up ,io_tdi ,mode_ctl ,rst_val_dn ,io_trst_l ,bsi ,io_tck ,
clock_dr ,tck ,shift_dr ,trst_l ,hiz_l ,tdi ,update_dr ,rst_io_l ,
por_l ,tdo ,se ,si ,reset_l ,so ,bso ,spare_misc_padoe ,
spare_misc_pad_to_core );
output [2:1] spare_misc_pad_to_core ;
input [2:1] spare_misc_paddata ;
input [5:4] obsel ;
input [2:1] spare_misc_padoe ;
inout [2:1] spare_misc_pad ;
output io_tdi ;
output io_trst_l ;
output io_tck ;
output so ;
output bso ;
input clk ;
input sel_bypass ;
input io_tdo_en ;
input ckd ;
input vref ;
input vddo ;
input io_tdo ;
input rst_val_up ;
input mode_ctl ;
input rst_val_dn ;
input bsi ;
input clock_dr ;
input shift_dr ;
input hiz_l ;
input update_dr ;
input rst_io_l ;
input por_l ;
input se ;
input si ;
input reset_l ;
inout tck ;
inout trst_l ;
inout tdi ;
inout tdo ;
supply0 vss ;
wire bscan_spare1_spare2 ;
wire net133 ;
wire bscan_spare2_spare1 ;
wire net084 ;
bw_io_cmos2_pad tdo_pad (
.oe (io_tdo_en ),
.vddo (vddo ),
.data (io_tdo ),
.to_core (net133 ),
.pad (tdo ),
.por_l (por_l ) );
bw_u1_ckbuf_40x Iclkbuf_5 (
.clk (net084 ),
.rclk (clk ) );
bw_io_hstl_pad spare_misc_pad_2_pad (
.obsel ({obsel } ),
.so (so ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net084 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_spare2_spare1 ),
.bsr_si (bsi ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (bscan_spare1_spare2 ),
.oe (spare_misc_padoe[2] ),
.data (spare_misc_paddata[2] ),
.se (se ),
.to_core (spare_misc_pad_to_core[2] ),
.por_l (por_l ),
.pad (spare_misc_pad[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_hstl_pad spare_misc_pad_1_pad (
.obsel ({obsel } ),
.so (bscan_spare1_spare2 ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net084 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bso ),
.bsr_si (bscan_spare2_spare1 ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (si ),
.oe (spare_misc_padoe[1] ),
.data (spare_misc_paddata[1] ),
.se (se ),
.to_core (spare_misc_pad_to_core[1] ),
.por_l (por_l ),
.pad (spare_misc_pad[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_cmos2_pad_dn tck_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_tck ),
.pad (tck ),
.por_l (por_l ) );
bw_io_cmos2_pad_up tdi_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_tdi ),
.pad (tdi ),
.por_l (por_l ) );
bw_io_cmos2_pad_up trst_l_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_trst_l ),
.pad (trst_l ),
.por_l (por_l ) );
endmodule
|
/* 同步 FIFO 4*128 */
// 一种4bit 128深度的 同步FIFO设计
// @`13
// 2017年6月6日
// 哈尔滨工业大学（威海） EDA课程设计
module fifo(clock, reset, read, write, fifo_in, digitron_out, fifo_empty, fifo_full);
parameter DEPTH = 128; // 128 深
parameter DEPTH_BINARY = 7; // 深度的二进制位数
parameter WIDTH = 4; // 4bit宽
parameter MAX_CONT = 7'b1111111; // 计数器最大值127 [0~127]
// LED 灯的二进制表示
// 根据 《数字系统设计与Verilog DHL (6th Edition)》P153 所提供的7段数码管电路图
/*
—— a
| | f b
—— g
| | e c
—— d
*/
// Len_N = abcdefg
// 使用一个七段数码管基于16进制显示 4bit 数据
parameter
digitron_0 = 7'b1111110,
digitron_1 = 7'b0110000,
digitron_2 = 7'b1101101,
digitron_3 = 7'b0000110,
digitron_4 = 7'b0110011,
digitron_5 = 7'b1011011,
digitron_6 = 7'b1011111,
digitron_7 = 7'b1110000,
digitron_8 = 7'b1111111,
digitron_9 = 7'b1111011,
digitron_a = 7'b1100111,
digitron_b = 7'b0011111,
digitron_c = 7'b1001110,
digitron_d = 7'b0111101,
digitron_e = 7'b0110000,
digitron_f = 7'b1001111;
input clock,reset,read,write; // 时钟，重置，读开关，写开关
input [WIDTH-1:0]fifo_in; // FIFO 数据输入
output [6:0] digitron_out; // 数码管 FIFO 数据输出
output fifo_empty,fifo_full; // 空标志,满标志
reg div; // 驱动信号
reg [23:0] clock_count; // 时钟计数器
reg [6:0] digitron_out; // 数据输出寄存器
reg [WIDTH-1:0]fifo_out; // 数据输出寄存器
reg [WIDTH-1:0]ram[DEPTH-1:0]; // 128深度 8宽度的 RAM 寄存器
reg [DEPTH_BINARY-1:0]read_ptr,write_ptr,counter; // 读指针，写指针，计数器 长度为2^7
wire fifo_empty,fifo_full; // 空标志,满标志
initial
begin
counter = 0;
read_ptr = 0;
write_ptr = 0;
fifo_out = 0;
div = 0;
clock_count = 0;
digitron_out = digitron_0;
end
always@(posedge clock)
begin
if(clock_count == 24'b111111111111111111111111)
begin
div =~ div;
clock_count <= 0;
end
else
begin
clock_count <= clock_count+1;
end
end
assign fifo_empty = (counter == 0); //标志位赋值
assign fifo_full = (counter == DEPTH-1);
always@(posedge div) // 时钟同步驱动
if(reset) // Reset 重置FIFO
begin
read_ptr = 0;
write_ptr = 0;
counter = 0;
fifo_out = 0;
end
else
case({read,write}) // 相应读写开关
2'b00:; //没有读写指令
2'b01: //写指令，数据输入FIFO
begin
if (counter < DEPTH - 1) // 判断是否可写
begin
ram[write_ptr] = fifo_in;
counter = counter + 1;
write_ptr = (write_ptr == DEPTH-1)?0:write_ptr + 1;
end
end
2'b10: //读指令，数据读出FIFO
begin
if (counter > 0) // 判断是否可读
begin
fifo_out = ram[read_ptr];
case(fifo_out)
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
counter = counter - 1;
read_ptr = (read_ptr == DEPTH-1)?0:read_ptr + 1;
end
end
2'b11: //读写指令同时，数据可以直接输出
begin
if(counter == 0)
begin
fifo_out = fifo_in; // 直接输出
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
end
else
begin
ram[write_ptr]=fifo_in;
fifo_out=ram[read_ptr];
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
write_ptr=(write_ptr==DEPTH-1)?0:write_ptr+1;
read_ptr=(read_ptr==DEPTH-1)?0:write_ptr+1;
end
end
endcase
endmodule
// module debouncing(
// BJ_CLK, //采集时钟
// RESET, //系统复位信号 [低电平有效]
// BUTTON_IN, //按键输入信号
// BUTTON_OUT //消抖后的输出信号
// );
// input BJ_CLK;
// input RESET;
// input BUTTON_IN;
// output BUTTON_OUT;
// reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;
// always @(posedge BJ_CLK or negedge RESET)
// begin
// if(~RESET)
// begin
// BUTTON_IN_Q <= 1'b1;
// BUTTON_IN_2Q <= 1'b1;
// BUTTON_IN_3Q <= 1'b1;
// end
// else
// begin
// BUTTON_IN_Q <= BUTTON_IN;
// BUTTON_IN_2Q <= BUTTON_IN_Q;
// BUTTON_IN_3Q <= BUTTON_IN_2Q;
// end
// end
// wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
// endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A221O_PP_SYMBOL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a221o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// updateCRC16.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
input rstCRC;
input CRCEn;
input [7:0] dataIn;
input clk;
input rst;
output [15:0] CRCResult;
output ready;
wire rstCRC;
wire CRCEn;
wire [7:0] dataIn;
wire clk;
wire rst;
reg [15:0] CRCResult;
reg ready;
reg doUpdateCRC;
reg [7:0] data;
reg [3:0] i;
always @(posedge clk)
begin
if (rst == 1'b1 || rstCRC == 1'b1) begin
doUpdateCRC <= 1'b0;
i <= 4'h0;
CRCResult <= 16'hffff;
ready <= 1'b1;
end
else
begin
if (doUpdateCRC == 1'b0)
begin
if (CRCEn == 1'b1) begin
doUpdateCRC <= 1'b1;
data <= dataIn;
ready <= 1'b0;
end
end
else begin
i <= i + 1'b1;
if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
end
else begin
CRCResult <= {1'b0, CRCResult[15:1]};
end
data <= {1'b0, data[7:1]};
if (i == 4'h7)
begin
doUpdateCRC <= 1'b0;
i <= 4'h0;
ready <= 1'b1;
end
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "TRUE" // First word fall-through
)(
input wire wclk,
input wire wrst_n,
input wire winc,
input wire [DSIZE-1:0] wdata,
output wire wfull,
output wire awfull,
input wire rclk,
input wire rrst_n,
input wire rinc,
output wire [DSIZE-1:0] rdata,
output wire rempty,
output wire arempty
);
wire [ASIZE-1:0] waddr, raddr;
wire [ ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
// The module synchronizing the read point
// from read to write domain
sync_r2w
#(ASIZE)
sync_r2w (
.wq2_rptr (wq2_rptr),
.rptr (rptr),
.wclk (wclk),
.wrst_n (wrst_n)
);
// The module synchronizing the write point
// from write to read domain
sync_w2r
#(ASIZE)
sync_w2r (
.rq2_wptr (rq2_wptr),
.wptr (wptr),
.rclk (rclk),
.rrst_n (rrst_n)
);
// The module handling the write requests
wptr_full
#(ASIZE)
wptr_full (
.awfull (awfull),
.wfull (wfull),
.waddr (waddr),
.wptr (wptr),
.wq2_rptr (wq2_rptr),
.winc (winc),
.wclk (wclk),
.wrst_n (wrst_n)
);
// The DC-RAM
fifomem
#(DSIZE, ASIZE, FALLTHROUGH)
fifomem (
.rclken (rinc),
.rclk (rclk),
.rdata (rdata),
.wdata (wdata),
.waddr (waddr),
.raddr (raddr),
.wclken (winc),
.wfull (wfull),
.wclk (wclk)
);
// The module handling read requests
rptr_empty
#(ASIZE)
rptr_empty (
.arempty (arempty),
.rempty (rempty),
.raddr (raddr),
.rptr (rptr),
.rq2_wptr (rq2_wptr),
.rinc (rinc),
.rclk (rclk),
.rrst_n (rrst_n)
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_4_V
`define SKY130_FD_SC_HS__NOR4B_4_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_4_V
|
/*
* File: pippo_id.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
Ò» ID¶ÎÖ÷Òª²Ù×÷£¨Âß¼½á¹¹£©°üÀ¨£º
1£¬Ö¸Áîʶ±ðºÍÒëÂ룺¸ù¾Ýid_instµÄOPCDºÍXOÓòʶ±ðÖ¸ÁîÀàÐÍ£¬Éú³ÉÏàÓ¦µÄuops£¬²¢²úÉú²Ù×÷ÊýÑ¡ÔñµÄ¿ØÖÆÐźţ¨È磬
Ä¿µÄºÍÔ´²Ù×÷ÊýλÖÃÑ¡Ôñ£¬Á¢¼´ÊýÍØÕ¹ÀàÐÍÑ¡Ôñ£©
2£¬¸ù¾ÝÒëÂ루²Ù×÷ÊýµØÖ·ºÍʹÄÜÐźţ©£¬·ÃÎÊRF£¨GPRs£¬SPRs£¬CR£¬MSR£©»ñÈ¡²Ù×÷Êý
GPRsºÍ²¿·ÖSPRsÔÚID¶Î·¢³öÇëÇó£¬EXE¶Î¿ÉÓÃ
[TBD]²¿·ÖSPRs£¬CRºÍMSRµÈ¼Ä´æÆ÷ÔÚEXE¶ÎÍê³É·ÃÎʺ͸üÐÂ
3£¬¸ù¾ÝÖ¸ÁÉú³ÉλÓÚEXE¶ÎÇ°¶ËµÄoperandmux¿ØÖÆÐźţ¬Ñ¡Ôñ²Ù×÷ÊýÀ´Ô´
4£¬Hazard¼ì²âºÍÏàÓ¦ºó¶ËÁ÷Ë®Ïß¿ØÖÆ£²åÈëBubbleºÍת·¢µÈ£¬ÒÔ¼°ÌØÊâÖ¸Áî´¦Àí
a) Êý¾Ý³åÍ»£¬±È½Ïid_instÓëºó¶ËÁ÷Ë®²Ù×÷ÊýÉèÖÃwbmuxת·¢¡£¶ÔÓÚÈý¼¶Á÷Ë®Éè¼Æ£¬½öÐèÖ§³ÖwbÊý¾Ýµ½ALUÊý¾Ý¶Ëת·¢¡£
b) ʶ±ð·ÇÁ÷Ë®µÄ¶àÖÜÆÚÖ¸Á¸ù¾ÝÁ÷Ë®ÏßÉè¼ÆÔÚÊʵ±Ê±ºò·¢³öÏàÓ¦ÇëÇó£½øÐжàÖÜÆÚ¼ÆÊý¡£
c) ʶ±ðPWR¼Ü¹¹ÖÐÐèÒªÁ½´Îд»ØµÄÖ¸Á´øupdateµÄ·Ã´æÖ¸ÁîµÈ£©´¦Àí£Í¨¹ýÍØÕ¹WB¶ÎʵÏÖ¡£
5£¬ÌṩÓëFlexWare²¿¼þµÄ½Ó¿Ú£Ä¿Ç°ÔÝδʵÏÖ
¶þ ×¢ÒâÒÔÏÂÊýÀà´¦ÀíÆ÷¹ÜÀíÖ¸ÁîµÄ´¦Àí£ºÔÚID¶Î½öÉú³Éid_sig_xxx¡£
1£¬ÏÔÐÔͬ²½Ö¸Áî£eieio, sync, isync£º
2£¬rfiºÍrfciÖ¸Á·¢ËÍÖÁexceptÄ£¿é´¦Àí
3£¬scÖ¸Á·¢ËÍÖÁexceptÄ£¿é´¦Àí
Èý ´¦ÀíÆ÷ģʽ¼ì²é£¨Supervisor/PrivillegedºÍUser/Problem State£©
ÒÔÏÂÖ¸ÁîºÍ¼Ä´æÆ÷Ö»ÄÜÔÚsvmģʽÏÂÖ´ÐкͷÃÎÊ
svmÖ¸Ámfmsr/mtmsr, rfi/rfci, wrtee/wrteei, mfdcr/mtdcr
mfspr: for all SPRs except CTR, LR, XER, USPRG0, SPRG4-SPRG7
mtspr: for all SPRs except CTR, LR, XER, USPRG0.
svmÌØÊâ¼Ä´æÆ÷£ºAll SPRs except for the CTR, LR, XER, USPRG0 and read access to SPRG4-SPRG7.
1, SPR numbers having a 1 in the msb of the SPRF firld are privileged
2, On Timer:
- reading from TBL and TBU is not privileged, which are read using mftb inst. rather mfspr.
- TBL/TBU are written using mtspr, which is privileged.
[TBV]ÓÉÈí¼þ±£Ö¤£¬ÔÚuser state¶ÔSPRG4-SPRG7½øÐжÁ·ÃÎÊʱ£¬Ê¹ÓõÄÊÇ104£107µÄsprµØÖ·£»
ËÄ Í¬²½Ö¸Áî´¦Àí
ͬ²½Éæ¼°Á½·½ÃæµÄ´¦Àí
a£©Á÷Ë®ÏߺÍÁ÷Ë®¶ÎÖÐbufferÄÚÈݵĹÜÀí£»
b£©un-coreµÄ¹ÜÀí£¬Èçcache, mmuºÍdcrÍâÉèµÈ¡£ÔÚpippoÖУ¬Ðè×¢ÒâstoreÖ¸ÁîµÄÍê³É£Èç¹ûÔö¼Óstore buffer£»
ͬ²½Ö¸Áî·ÖΪÒÔÏÂÈýÀࣺ
1, context synchronization£º"isync, rfi, rfci, sc";
An instruction or event is context synchronizing if it satisfies the following requirements:
a. All instructions that precede a context synchronizing operation must complete in the
context that existed before the context synchronizing operation.
b. All instructions that follow a context synchronizing operation must complete in the
context that exists after the context synchronizing operation.
2, execution synchronization: "eieio, sync and mtmsr";
Execution synchronization guarantees that the following requirement is met:
All instructions that precede an execution synchronizing operation must complete in
the context that existed before the execution synchronizing operation.
The following requirement need not be met:
All instructions that follow an execution synchronizing operation must complete in
the context that exists after the execution synchronizing operation.
3, storage synchronization: eieio, sync
a. The sync instruction guarantees that all previous storage references complete with respect
to the core before the sync instruction completes (therefore, before any subsequent instru
-ctions begin to execute). The sync instruction is execution synchronizing.
b. The eieio instruction guarantees the order of storage accesses. All storage accesses that
precede eieio complete before any storage accesses that follow the instruction
The core implements both sync and eieio identically.
In the PowerPC Architecture, sync can function across all processors in a multiprocessor
environment; eieio functions only within its executing processor.
×¢ÒâÊÂÏ
1£¬´æ´¢·ÃÎÊ£¨store/mtdcr/cache.mmuÖ¸ÁîµÈ£©µÄÍê³É׼ȷ¶¨Ò壷¢Æð×ÜÏßÇëÇó»òÊÇ×ÜÏßÊÂÎñ½áÊø£¿
2£¬½öcontextͬ²½ÐèÒªÇå¿ÕË¢ÐÂÁ÷Ë®ÏߺÍbuffer£»
[TBV]execution/storage synchronizationÄ¿Ç°¿É×÷Ϊnop´¦Àí£¿
3£¬Ê¹ÓÃmtmsr»áÒý·¢contextת»»£¬ÐèÒª³ÌÐòÔ±ÔÚmtmsrºó²åÈëisyncÖ¸Á
Îå twºÍtwiÖ¸ÁîµÄ´¦Àí
Ä¿Ç°trapͳһ°´Õշǵ÷ÊÔʼþʹÄÜÇé¿ö´¦Àí
Áù ÆäËû
reg_zeroÓÃÓÚ±êʶ(RA|0)µÄÇé¿ö£¶ÔÓڷôæÖ¸ÁîºÍ²¿·ÖÂß¼ÔËËãÖ¸ÁîÐèÒªÌØÊâ´¦Àí
[TBD]reg_zeroͬʱÔÚid¶ÎÓÃÓÚÏàÓ¦¶Ë¿Úrf·ÃÎʶÁʹÄÜ£¬ÒÔ½µµÍ¹¦ºÄ£¬´ýÈ·ÈÏ»á·ñÓ°ÏìʱÐò£»
* Task.I:
[TBD]ͬ²½Ö¸Áî´¦Àí
ͬ²½Ö¸ÁîÔÚid¶Î¸ø³ösig_x£»
ÒþÐÔͬ²½Ö¸ÁîÔÚex/wb¶Î£¬ÔÚÍê³Éд»ØµÄͬʱ£¬Ëͳöex_sig_xÍê³ÉÖ¸ÁîÁ÷±ä»»ÊµÏÖ
Èç¹ûÒþÐÔͬ²½Ö¸ÁîÔÚex/wb½×¶ÎÒý·¢ÖжÏÐÐΪ£ÀýÈçsupervisor״̬¼ì²â£»°´ÕÕÕý³£ÖжϲúÉú´¦Àí£»
[TBV] ÔÚÍⲿÖжÏÇëÇópendingµÄÇé¿öÏ£¬mtmsr¿ªÆô[EE]룬ÖжϱØÐëÔÚmtmsrµÄÏÂÒ»ÌõÖ¸ÁîÖ´ÐÐÇ°´¦Àí
ͬ²½Ö¸ÁîµÄ´¦ÀíÔÚexceptÄ£¿é»òsprsÄ£¿éÖ´ÐУ¿
[TBD]supervisor mode check
id¶Î±êʶÐèÒª½øÐÐģʽ¼ì²éµÄÖ´ÐÐÖ¸ÁîºÍSPR·ÃÎÊÖ¸Ásvm_check
exe¶Î½øÐмì²â£¬³åÍ»Ôò·¢³öÖжÏÇëÇó£»
[TBD]δʵÏÖÖ¸Áî·ÖÀࣺ
a£ºÍ³Ò»Òý·¢exception£¬½»ÓÉÈí¼þ´¦Àí£»¿¼ÂÇÔö¼ÓsprÐÖúÖ¸Áîemulation£»
b£ºÄ³Ð©ÐèÒª×÷Ϊnop¶Ô´ý£¬ÀýÈç²»Å䱸cacheʱµÄcacheÖ¸ÁijЩÒý·¢exception
[TBV]update·Ã´æÖ¸ÁîÁ÷µÄÖ¸ÁîÒÀÀµÇé¿ö£º
ÏÂÒ»ÌõÖ¸ÁîÐèÒªÓõ½ÉÏÌõupdate·Ã´æµÄÁ½¸ö½á¹û£»×ª·¢Âß¼¹¤×÷ÊÇ·ñÕý³££»
[TBD]uopsµÄÉè¼ÆÓÅ»¯
ÍØÕ¹uopsλ¿í£¬±êÃ÷ÿһλµÄÒâÒ壬±ÜÃâid¶ÎÒëÂëÔÙ±àÂ룬ex¶ÎÔÙÒëÂë
execution op²ÉÓÃone-hot±àÂëÊÇ·ñ¼õÉÙÂß¼²ã´Î£¬ÓÅ»¯×ÜÌåʱÐò
½«Ö´Ðе¥Ôª±àÂëÖÁuops
[TBD]²¹³äÍêÉÆflowchart
* Task.II:
* delete OPCODE/XO field of ex_inst, to save area
* microcode»òemulationʵÏÖ¸´ÔÓÖ¸Áî
* check invalid instruction form? to test real chip
* check id_valid before decoding? to save power.
* evaluating coding style, to improve performance and reduce area
* Can pippo implement predecode, and how: OPCD-31 and branch?
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_id(
clk, rst,
id_inst, id_cia, id_snia, id_valid,
ex_inst, ex_cia, ex_snia, ex_valid,
gpr_addr_rda, gpr_addr_rdb, gpr_addr_rdc, gpr_rda_en, gpr_rdb_en, gpr_rdc_en,
ex_imm, ex_sel_a, ex_sel_b,
ex_branch_addrofs, reg_zero, ex_spr_addr,
set_atomic, clear_atomic,
ex_bpu_uops, ex_alu_uops, ex_cr_uops, ex_lsu_uops, ex_reg_uops,
ex_rfwb_uops, ex_gpr_addr_wra, ex_gpr_addr_wrb,
multicycle_cnt, id_freeze, ex_freeze, wb_freeze, flushpipe,
sig_syscall, sig_rfi, sig_rfci, sig_eieio, sig_isync, sig_sync, sig_illegal, sig_emulate,
id_sig_ibuserr, sig_ibuserr
);
input clk;
input rst;
// pipeling registers
input id_valid;
input [31:0] id_inst;
input [29:0] id_cia;
input [29:0] id_snia;
output ex_valid;
output [31:0] ex_inst;
output [29:0] ex_cia;
output [29:0] ex_snia;
// operand signals: gpr read port - assert at current stage
output [`GPR_ADDR_WIDTH-1:0] gpr_addr_rda;
output [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdb;
output [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdc;
output gpr_rda_en;
output gpr_rdb_en;
output gpr_rdc_en;
// operand signals: imm and operandmux control - need pipeling, assert at following stage
output [31:0] ex_imm;
output [`OPSEL_WIDTH-1:0] ex_sel_a;
output [`OPSEL_WIDTH-1:0] ex_sel_b;
// operand signals: address displacement or address - need pipeling, assert at following stage
output [29:0] ex_branch_addrofs;
output reg_zero;
output [`SPR_ADDR_WIDTH-1:0] ex_spr_addr;
// uops signals, need pipeling, assert at following stages
output [`BPUUOPS_WIDTH-1:0] ex_bpu_uops;
output [`ALUUOPS_WIDTH-1:0] ex_alu_uops;
output [`LSUUOPS_WIDTH-1:0] ex_lsu_uops;
output [`CRUOPS_WIDTH-1:0] ex_cr_uops;
output [`REGUOPS_WIDTH-1:0] ex_reg_uops;
// wb signals, need pipeling
// note: write-back enable signals are encoded in rfwb_uops
output [`RFWBUOPS_WIDTH-1:0] ex_rfwb_uops;
output [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wra;
output [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wrb;
// pipeling control signals
input id_freeze;
input ex_freeze;
input wb_freeze;
input flushpipe;
// atomic memory access for lsu
output set_atomic;
output clear_atomic;
// multicycle instruction counter, assert at following stages
output [`MULTICYCLE_WIDTH-1:0] multicycle_cnt;
// exception request signals
output sig_rfi;
output sig_rfci;
output sig_syscall;
output sig_illegal;
output sig_emulate;
// exception requests pipeling from IF stage
input id_sig_ibuserr;
output sig_ibuserr;
// synchronization signals
output sig_eieio;
output sig_isync;
output sig_sync;
//
// Whole decoder
//
reg [`BPUUOPS_WIDTH-1:0] id_bpu_uops;
reg [`ALUUOPS_WIDTH-1:0] id_alu_uops;
reg [`LSUUOPS_WIDTH-1:0] id_lsu_uops;
reg [`CRUOPS_WIDTH-1:0] id_cr_uops;
reg [`REGUOPS_WIDTH-1:0] id_reg_uops;
reg [`GPR_ADDR_WIDTH-1:0] gpr_addr_rda;
reg [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdb;
reg [`GPR_ADDR_WIDTH-1:0] gpr_addr_rdc;
reg gpr_rda_en;
reg gpr_rdb_en;
reg gpr_rdc_en;
reg [`RFWBUOPS_WIDTH-1:0] id_rfwb_uops;
reg [`GPR_ADDR_WIDTH-1:0] id_gpr_addr_wra;
reg [`GPR_ADDR_WIDTH-1:0] id_gpr_addr_wrb;
reg [29:0] id_branch_addrofs;
reg id_reg_zero;
reg reg_zero;
reg [9:0] id_spr_addr;
reg [31:0] id_imm;
reg sel_imm;
reg id_set_atomic;
reg set_atomic;
reg id_clear_atomic;
reg clear_atomic;
reg [`MULTICYCLE_WIDTH-1:0] multicycle;
reg id_sig_illegal;
reg id_sig_emulate;
reg id_sig_syscall;
reg id_sig_eieio;
reg id_sig_isync;
reg id_sig_sync;
reg id_sig_rfi;
reg id_sig_rfci;
always @(id_inst or id_cia or id_snia or id_valid) begin
// EX/WB uops
id_bpu_uops = {2'b00, `BPUOP_NOP}; // {AA, LK, `BPUOP_NOP}
id_alu_uops = {2'b00, `ALUOP_NOP}; // {OE, Rc, `ALUOP_NOP}
id_lsu_uops = {1'b0, `LSUOP_NOP}; // {update, `LSUOP_NOP}
id_reg_uops = `REGOP_NOP;
id_cr_uops = `CROP_NOP;
// gprs access
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_addr_rdc = id_inst[25:21];
gpr_rda_en = 1'b0;
gpr_rdb_en = 1'b0;
gpr_rdc_en = 1'b0;
// wb
id_rfwb_uops = `RFWBOP_NOP;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16]; // b bus for load/store with update inst.'s EA write-back
// imm
sel_imm = 1'b0;
id_imm = 32'd0;
// address operands
id_branch_addrofs = 30'd0;
id_spr_addr = 10'd0;
id_reg_zero = 1'b0;
// atomic memory access
id_set_atomic = 1'b0;
id_clear_atomic = 1'b0;
// multicycle instruction indicator: to extend pipeline stages - for memory access and complex insts
multicycle = `EXTEND_ZERO_CYCLES;
// exception request
id_sig_illegal = 1'b1;
id_sig_emulate = 1'b0;
id_sig_syscall = 1'b0;
id_sig_rfi = 1'b0;
id_sig_rfci = 1'b0;
// synchronization request
id_sig_eieio = 1'b0;
id_sig_isync = 1'b0;
id_sig_sync = 1'b0;
case (id_inst[31:26]) // synopsys parallel_case
//
// I-Form
//
// inst: b[l][a],
// execution: bpu
// flowchart:
// b: (cia+imm) -> PC
// ba: imm -> PC
// bl: (cia+imm) -> PC; (cia+4) -> LR
// bla: imm -> PC; (cia+4) -> LR
`Bx_OPCD: begin
id_bpu_uops = {id_inst[1:0], `BPUOP_BIMM}; // {AA,LK, `BPUOP_BIMM}
id_branch_addrofs = {{6{id_inst[25]}}, id_inst[25:2]};
id_sig_illegal = 1'b0;
end
//
// B-Form
//
// inst: bc[l][a]
// execution: bpu
// flowchart:
// (CTR, BO, BI) -> (c)
// bc: (cia+imm) ->(c) PC
// bca: imm -> (c)PC
// bcl: (cia+imm) -> (c)PC; (cia+4) -> LR
// bcla: imm -> (c)PC; (cia+4) -> LR
`BCx_OPCD: begin
id_bpu_uops = {id_inst[1:0], `BPUOP_BCIMM}; // {AA,LK, `BPUOP_BCIMM}
id_branch_addrofs = {{16{id_inst[15]}}, id_inst[15:2]};
id_sig_illegal = 1'b0;
end
//
// SC-Form
//
// inst: sc
// execution: except
// wb: (MSR) -> (SRR1);
// (PC)->(SRR0);
// EVPR[0:15]||0x0C00 -> PC;
// 0 -> (MSR[WE, EE, PR, DR, IR])
//
`SC_OPCD: begin
id_sig_syscall = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_syscall");
// synopsys translate_on
`endif
end
//
// D-Form
// All D-Form inst. have unique OPCD
//
// addi
`ADDI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_ADD};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// addic
`ADDIC_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_ADDC};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// addic.
`ADDICx_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_ADDC}; // record CR
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// addis
`ADDIS_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_ADDC}; // record CR
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
`ANDIx_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_AND}; // record CR
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {{16{1'b0}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`ANDISx_OPCD: begin
id_alu_uops = {2'b01, `ALUOP_AND}; // record CR
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`ORI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_OR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {{16{1'b0}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`ORIS_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_OR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`XORI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_XOR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {{16{1'b0}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
`XORIS_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_XOR};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_imm = {id_inst[15:0], {16{1'b0}}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: cmpi
// execution: alu
// flowchart:
// (RA) cmp EXTS(IM) -> CR[CRbf]
`CMPI_OPCD: begin
id_cr_uops = `CROP_CMP;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
// inst: cmpli
// execution: alu
// flowchart:
// (RA) cmpl EXTS(IM) -> CR[CRbf]
`CMPLI_OPCD: begin
id_cr_uops = `CROP_CMPL;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: lbz
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {24{0}, mem(EA, 1 Byte)} -> (RT)
`LBZ_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lha
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, EXTS(mem(EA, 2 Byte)) -> (RT)
`LHA_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhz
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {16{0}, mem(EA, 2 Byte)} -> (RT)
`LHZ_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwz
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, mem(EA, 4 Byte) -> (RT)
`LWZ_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: stb
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[7:0] -> mem(EA, 1 Byte)
`STB_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: sth
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[15:0] -> mem(EA, 2 Byte)
`STH_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stw
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[31:0] -> mem(EA, 4 Byte)
`STW_OPCD: begin
id_lsu_uops = {1'b0, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// lbzu
`LBZU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000); // [TBD] invalid form, how to deal at hardware side
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhau
`LHAU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhzu
`LHZU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lwzu
`LWZU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stbu
`STBU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16]; //[TBV] to use write port b
id_sig_illegal = 1'b0;
end
// sthu
`STHU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stwu
`STWU_OPCD: begin
id_lsu_uops = {1'b1, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// mulli
`MULLI_OPCD: begin
id_alu_uops = {2'b00, `ALUOP_MULLI};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// lmw
`LMW_OPCD: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
// stmw
`STMW_OPCD: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
// subfic
// exe: RB - EXTS(IM) -> RT;
`SUBFIC_OPCD: begin
id_alu_uops = {2'b00,`ALUOP_SUBFC};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// twi
// exe:
`TWI_OPCD: begin
id_cr_uops = `CROP_TRAP;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {{16{id_inst[15]}}, id_inst[15:0]};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
//
// XL-Form
// all XL-Form instructions have same OPCD: 19
//
`BCCTRx_OPCD: begin
case (id_inst[10:1]) // synopsys parallel_case
// inst: bcctr[l], XL-Form
// execution: bpu
// flowchart:
// (CTR, BO, BI) -> (c)
// bcctr: (CTR[31:2], 2'b00) -> (c)PC; (c)(CTR)
// bcctrl: (CTR[31:2], 2'b00) -> (c)PC; (c)(CTR); (cia+4) -> LR
`BCCTRx_XO: begin
id_bpu_uops = {1'b0, id_inst[0], `BPUOP_BCCTR}; // {AA,LK, BPUOP}
id_sig_illegal = 1'b0;
end
// inst: bclr[l], XL-Form
// execution: bpu
// flowchart:
// (CTR, BO, BI) -> (c)
// bclr: (LR[31:2], 2'b00) -> (c)PC; (c)(CTR)
// bclrl: (LR[31:2], 2'b00) -> (c)PC; (c)(CTR); (cia+4) -> LR
`BCLRx_XO: begin
id_bpu_uops = {1'b0, id_inst[0], `BPUOP_BCLR}; // {AA,LK, BPUOP}
id_sig_illegal = 1'b0;
end
// inst: crand, XL-form
// execution: alu
// flowchart:
// CR[crb_a] func CR[crb_b] -> CR[crb_d]
`CRAND_XO: begin
id_cr_uops = `CROP_AND;
id_sig_illegal = 1'b0;
end
`CRANDC_XO : begin
id_cr_uops = `CROP_ANDC;
id_sig_illegal = 1'b0;
end
`CREQV_XO : begin
id_cr_uops = `CROP_EQV;
id_sig_illegal = 1'b0;
end
`CRORC_XO : begin
id_cr_uops = `CROP_ORC;
id_sig_illegal = 1'b0;
end
`CRNAND_XO : begin
id_cr_uops = `CROP_NAND;
id_sig_illegal = 1'b0;
end
`CRNOR_XO : begin
id_cr_uops = `CROP_NOR;
id_sig_illegal = 1'b0;
end
`CROR_XO : begin
id_cr_uops = `CROP_OR;
id_sig_illegal = 1'b0;
end
`CRXOR_XO : begin
id_cr_uops = `CROP_XOR;
id_sig_illegal = 1'b0;
end
`MCRF_XO : begin
id_reg_uops = `REGOP_MCRF;
id_sig_illegal = 1'b0;
end
`ISYNC_XO : begin
id_sig_isync = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_isync");
// synopsys translate_on
`endif
end
`RFI_XO : begin
id_sig_rfi = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_rfi");
// synopsys translate_on
`endif
end
`RFCI_XO : begin
id_sig_rfci = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_rfci");
// synopsys translate_on
`endif
end
endcase // XO field of XL-Form
end
//
// OPCD: 31
// including£º
// 1, all XO-form instructions
// 2, all XFX-form instructions
// 3, part of X-form instructions, excluding fpu-related instructions(OPCD-63)
//
`ADDx_OPCD: begin
casex (id_inst[10:1]) // synopsys parallel_case
//
// XO-Form
//
// inst.: add[o][.]
// execution: alu
// flowchart:
// (RA)+(RB) -> (RT);
// (RT)->(Rc)CR[CR0]
// (RT)->(OE)XER[SO, OV]
{1'bx, `ADDx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADD}; // {OE,Rc,`ALUOP_ADD}
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: addc[o][.]
// execution: alu
// flowchart:
// (RA)+(RB) -> (RT);
// (RT)->XER[CA]
// (RT)->(Rc)CR[CR0]
// (RT)->(OE)XER[SO, OV]
{1'bx, `ADDCx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDC};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst: subf[o][.] - alu
// exe: RB - RA -> RT;
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBF};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: neg[o][.] - alu
// exe: Rev(RA) + 1 -> RT;
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `NEGx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_NEG};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: adde[o][.] - alu
// exe: RA + RB + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `ADDEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDE};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// ADDMEx
// Inst: addme[o][.] - alu
// exe: RA + XER[CA] + (-1) -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `ADDMEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b1}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: addze[o][.] - alu
// exe: RA + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `ADDZEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_ADDE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b0}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfc[o][.] - alu
// exe: RB - RA -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFCx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFC};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfe[o][.] - alu
// exe: Rev(RA) + RB + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFE};
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfme[o][.] - alu
// exe: Rev(RA) - 1 + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFMEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b1}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// Inst: subfze[o][.] - alu
// exe: Rev(RA) + XER[CA] -> RT, XER[CA];
// (Rc)CR[CR0], (OE)XER[SO, OV]
{1'bx, `SUBFZEx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_SUBFE};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
id_imm = {32{1'b0}};
sel_imm = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// MULHWx
{1'b0, `MULHWx_XO}: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_MULHW};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// MULLWx - Not Implemented Currently
{1'bx, `MULLWx_XO}: begin
id_alu_uops = {id_inst[10], id_inst[0],`ALUOP_MULHWU};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// MULHWUx - Not Implemented Currently
{1'b0, `MULHWUx_XO}: begin
id_alu_uops = {1'b0, id_inst[0],`ALUOP_MULHW};
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_sig_illegal = 1'b0;
multicycle = `EXTEND_TWO_CYCLES;
end
// DIVWx - Not Implemented Currently
{1'b0, `DIVWx_XO}: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
// DIVWUx - Not Implemented Currently
{1'b0, `DIVWUx_XO}: begin
id_sig_illegal = 1'b0;
id_sig_emulate = 1'b1;
end
//
// XFX-Form
//
// mfspr
`MFSPR_XO: begin
id_reg_uops = `REGOP_MFSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtspr
`MTSPR_XO: begin
id_reg_uops = `REGOP_MTSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// mtcrf
`MTCRF_XO: begin
id_reg_uops = `REGOP_MTCRF;
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// mftb: not-implemented
// mfspr
`MFTB_XO: begin
id_reg_uops = `REGOP_MFSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtdcr/mfdcr: not-implemented
`MFDCR_XO: begin
id_reg_uops = `REGOP_MFSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtdcr/mfdcr: not-implemented
`MTDCR_XO: begin
id_reg_uops = `REGOP_MTSPR;
id_spr_addr = {id_inst[15:11], id_inst[20:16]};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
//
// X-Form
//
// inst: and[.]
// execution: alu
// flowchart:
// (RS) and (RB) -> (RA)
`ANDx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_AND};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: andc[.]
// execution: alu
// flowchart:
// (RS) andc (RB) -> (RA)
`ANDCx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_ANDC};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: nand[.]
// execution: alu
// flowchart:
// (RS) nand (RB) -> (RA)
`NANDx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_NAND};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: or[.]
// execution: alu
// flowchart:
// (RS) or (RB) -> (RA)
`ORx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_OR};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: orc[.]
// execution: alu
// flowchart:
// (RS) orc (RB) -> (RA)
`ORCx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_ORC};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: xor[.]
// execution: alu
// flowchart:
// (RS) xor (RB) -> (RA)
`XORx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_XOR};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: nor[.]
// execution: alu
// flowchart:
// (RS) nor (RB) -> (RA)
`NORx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_NOR};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: eqv[.]
// execution: alu
// flowchart:
// (RS) eqv (RB) -> (RA)
`EQVx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_EQV};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: cntlzw[.]
// execution: alu
// flowchart:
// cntlzw(RS) -> (RA)
`CNTLZWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_CNTLZW};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: extsb[.]
// execution: alu
// flowchart:
// extsb(RS) -> (RA)
`EXTSBx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_EXTSB};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: extsh[.]
// execution: alu
// flowchart:
// extsb(RS) -> (RA)
`EXTSHx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_EXTSH};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: slw[.]
// execution: alu
// flowchart:
// (RS) slw (RB) -> (RA)
`SLWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SLW};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: srw[.]
// execution: alu
// flowchart:
// (RS) srw (RB) -> (RA)
`SRWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SRW};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: sraw[.]
// execution: alu
// flowchart:
// (RS) sraw (RB) -> (RA)
`SRAWx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SRAW};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: srawi[.]
// execution: alu
// flowchart:
// (RS) sraw (SH) -> (RA)
`SRAWIx_XO: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_SRAWI};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: cmp
// execution: alu
// flowchart:
// (RA) cmp (RB) -> CR[CRbf]
`CMP_XO: begin
id_cr_uops = `CROP_CMP;
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst: cmpl
// execution: alu
// flowchart:
// (RA) cmpl (RB) -> CR[CRbf]
`CMPL_XO: begin
id_cr_uops = `CROP_CMPL;
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: lbzx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {24{0}, mem(EA, 1 Byte)} -> (RT)
`LBZX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhax
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {16{sign}, mem(EA, 2 Byte)} -> (RT)
`LHAX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhzx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {16{0}, mem(EA, 2 Byte)} -> (RT)
`LHZX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lhbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {16{0}, mem(EA+1, 1 Byte), mem(EA, 1 Byte)} -> (RT)
`LHBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LHZB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwzx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, mem(EA, 4 Byte) -> (RT)
`LWZX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, {mem(EA+3, 1 Byte), mem(EA+2, 1 Byte), mem(EA+1, 1 Byte), mem(EA, 1 Byte), }-> (RT)
`LWBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LWZB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: lwarx
// execution: lsu
// flowchart:
// 1, (RA|0) + (RB) -> EA;
// 2, mem(EA, 4 Byte) -> (RT)
// 3, reg_atomic set to 1
`LWARX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
id_set_atomic = 1'b1;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSU;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// inst.: stwcx.
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[31:0] -> mem(EA, 4)
`STWCXx_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
id_clear_atomic = 1'b1;
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stbx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[7:0] -> mem(EA, 1)
`STBX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: sthx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[15:0] -> mem(EA, 2)
`STHX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: sthbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {RS[7:0], RS[15:8]} -> mem(EA, 2)
`STHBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STHB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stwx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, RS[31:0] -> mem(EA, 4)
`STWX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// inst.: stwbrx
// execution: lsu
// flowchart:
// 1, (RA|0) + EXTS(D) -> EA;
// 2, {RS[7:0], RS[15:8], RS[23:16], RS[31:24]} -> mem(EA, 4)
`STWBRX_XO: begin
id_lsu_uops = {1'b0, `LSUOP_STWB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_sig_illegal = 1'b0;
end
// lbzux
`LBZUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LBZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhaux
`LHAUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LHA};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lhzux
`LHZUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LHZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// lwzux
`LWZUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_LWZ};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUTWO;
id_gpr_addr_wra = id_inst[25:21];
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stbux
`STBUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_STB};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// sthux
`STHUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_STH};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// stwux
`STWUX_XO: begin
id_lsu_uops = {1'b1, `LSUOP_STW};
id_reg_zero = (id_inst[20:16] == 5'b00000);
gpr_addr_rda = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_addr_rdb = id_inst[15:11];
gpr_rdb_en = 1'b1;
gpr_addr_rdc = id_inst[25:21];
gpr_rdc_en = 1'b1;
id_rfwb_uops = `RFWBOP_LSUEA;
id_gpr_addr_wrb = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// mfcr
`MFCR_XO: begin
id_reg_uops = `REGOP_MFCR;
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mfmsr
`MFMSR_XO: begin
id_reg_uops = `REGOP_MFMSR;
id_rfwb_uops = `RFWBOP_SPRS;
id_gpr_addr_wra = id_inst[25:21];
id_sig_illegal = 1'b0;
end
// mtspr
`MTMSR_XO: begin
id_reg_uops = `REGOP_MTMSR;
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// mcrxr
`MCRXR_XO: begin
id_reg_uops = `REGOP_MCRXR;
id_sig_illegal = 1'b0;
end
// tw
`TW_XO: begin
id_cr_uops = `CROP_TRAP;
gpr_addr_rda = id_inst[20:16];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// sync
`SYNC_XO: begin
id_sig_sync = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_sync");
// synopsys translate_on
`endif
end
// eieio
`EIEIO_XO: begin
id_sig_eieio = 1;
id_sig_illegal = 1'b0;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("Generating sig_eieio");
// synopsys translate_on
`endif
end
//
// inst. below are decoding as X-Form, to affirm[TBD]
//
// wrtee
`WRTEE_XO: begin
id_reg_uops = `REGOP_WRTEE;
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_sig_illegal = 1'b0;
end
// wrteei
`WRTEEI_XO: begin
id_reg_uops = `REGOP_WRTEE;
id_imm = {{16{1'bx}}, id_inst[15], {15{1'bx}}};
sel_imm = 1'b1;
id_sig_illegal = 1'b0;
end
endcase // XO field
end
//
// M-Form
//
// inst: rlwimix[.]
// execution: alu
// flowchart:
`RLWIMIx_OPCD: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_RLWIMI};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[20:16];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: rlwinmx[.]
// execution: alu
// flowchart:
`RLWINMx_OPCD: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_RLWINM};
gpr_addr_rda = id_inst[25:21];
gpr_rda_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// inst: rlwnmx[.]
// execution: alu
// flowchart:
`RLWNMx_OPCD: begin
id_alu_uops = {1'b0, id_inst[0], `ALUOP_RLWNM};
gpr_addr_rda = id_inst[25:21];
gpr_addr_rdb = id_inst[15:11];
gpr_rda_en = 1'b1;
gpr_rdb_en = 1'b1;
id_rfwb_uops = `RFWBOP_ALU;
id_gpr_addr_wra = id_inst[20:16];
id_sig_illegal = 1'b0;
end
// XFL-Form
// inst: mtfsf (Move to FPSCR Fields), Not-Implemented at pippo
// A-Form
// for FPU, currently non implemented
endcase // OPCODE field
end
//
// Forwarding logic
//
// write address pipeling
// [TBV] reset and flush logic
reg [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wra;
reg [`GPR_ADDR_WIDTH-1:0] ex_gpr_addr_wrb;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_gpr_addr_wra <= #1 5'd0;
ex_gpr_addr_wrb <= #1 5'd0;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_gpr_addr_wra <= #1 5'd0;
ex_gpr_addr_wrb <= #1 5'd0;
end
else if (!ex_freeze) begin
ex_gpr_addr_wra <= #1 id_gpr_addr_wra;
ex_gpr_addr_wrb <= #1 id_gpr_addr_wrb;
end
end
// operandmux control signals: sel_a/sel_b
reg [`OPSEL_WIDTH-1:0] id_sel_a;
reg [`OPSEL_WIDTH-1:0] id_sel_b;
always @(gpr_addr_rda or ex_gpr_addr_wra or ex_gpr_addr_wrb or ex_rfwb_uops) begin
if ((gpr_addr_rda == ex_gpr_addr_wra) && ex_rfwb_uops[0])
id_sel_a = `OPSEL_WBFWD;
else if ((gpr_addr_rda == ex_gpr_addr_wrb) && ex_rfwb_uops[1])
id_sel_a = `OPSEL_WBFWD;
else
id_sel_a = `OPSEL_RF;
end
always @(sel_imm or gpr_addr_rdb or ex_gpr_addr_wra or ex_gpr_addr_wrb or ex_rfwb_uops) begin
if (sel_imm)
id_sel_b = `OPSEL_IMM;
else if ((gpr_addr_rdb == ex_gpr_addr_wra) && ex_rfwb_uops[0])
id_sel_b = `OPSEL_WBFWD;
else if ((gpr_addr_rdb == ex_gpr_addr_wrb) && ex_rfwb_uops[1])
id_sel_b = `OPSEL_WBFWD;
else
id_sel_b = `OPSEL_RF;
end
// [TBV] operandmuxÐźţ¨sel_a/sel_b£©µÄ¸´Î»Âß¼ºÍ¶³½áÂß¼
reg [`OPSEL_WIDTH-1:0] ex_sel_a;
reg [`OPSEL_WIDTH-1:0] ex_sel_b;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_sel_a <= #1 `OPSEL_RF;
ex_sel_b <= #1 `OPSEL_RF;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_sel_a <= #1 `OPSEL_RF;
ex_sel_b <= #1 `OPSEL_RF;
end
else if (!ex_freeze) begin
ex_sel_a <= #1 id_sel_a;
ex_sel_b <= #1 id_sel_b;
end
end
//
// Multicycle stall, send at EXE stage
//
reg [`MULTICYCLE_WIDTH-1:0] multicycle_cnt;
always @(posedge clk or posedge rst) begin
if (rst)
multicycle_cnt <= #1 2'b00;
else if (|multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 2'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
end
//
// ID/EX pipelining logic
//
// pipeling of uops
reg [`BPUUOPS_WIDTH-1:0] ex_bpu_uops;
reg [`ALUUOPS_WIDTH-1:0] ex_alu_uops;
reg [`LSUUOPS_WIDTH-1:0] ex_lsu_uops;
reg [`RFWBUOPS_WIDTH-1:0] ex_reg_uops;
reg [`RFWBUOPS_WIDTH-1:0] ex_cr_uops;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_bpu_uops <= #1 {2'b00, `BPUOP_NOP}; // {AA, LK, `BPUOP_NOP}
ex_alu_uops <= #1 {2'b00, `ALUOP_NOP}; // {OE, Rc, `ALUOP_ADD}
ex_lsu_uops <= #1 `LSUOP_NOP;
ex_reg_uops <= #1 `REGOP_NOP;
ex_cr_uops <= #1 `CROP_NOP;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_bpu_uops <= #1 {2'b00, `BPUOP_NOP}; // {AA, LK, `BPUOP_NOP}
ex_alu_uops <= #1 {2'b00, `ALUOP_NOP}; // {OE, Rc, `ALUOP_ADD}
ex_lsu_uops <= #1 `LSUOP_NOP;
ex_reg_uops <= #1 `REGOP_NOP;
ex_cr_uops <= #1 `CROP_NOP;
end
else if (!ex_freeze) begin
ex_bpu_uops <= #1 id_bpu_uops;
ex_alu_uops <= #1 id_alu_uops;
ex_lsu_uops <= #1 id_lsu_uops;
ex_reg_uops <= #1 id_reg_uops;
ex_cr_uops <= #1 id_cr_uops;
end
end
// RFWB_UPOS pipelining
reg [`RFWBUOPS_WIDTH-1:0] ex_rfwb_uops;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_rfwb_uops <= #1 `RFWBOP_NOP;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_rfwb_uops <= #1 `RFWBOP_NOP;
end
else if (!ex_freeze) begin
ex_rfwb_uops <= #1 id_rfwb_uops;
end
end
// pipeling of operands
reg [29:0] ex_branch_addrofs;
//reg [31:0] ex_lsu_addrofs;
reg [9:0] ex_spr_addr;
reg [31:0] ex_imm;
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_branch_addrofs <= #1 30'd0;
// ex_lsu_addrofs <= #1 32'd0;
reg_zero <= #1 1'b0;
ex_spr_addr <= #1 10'd0;
ex_imm <= #1 32'd0;
set_atomic <= 1'b0;
clear_atomic <= 1'b0;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
ex_branch_addrofs <= #1 30'd0;
// ex_lsu_addrofs <= #1 32'd0;
reg_zero <= #1 1'b0;
ex_spr_addr <= #1 10'd0;
ex_imm <= #1 32'd0;
set_atomic <= 1'b0;
clear_atomic <= 1'b0;
end
else if (!ex_freeze) begin
ex_branch_addrofs <= #1 id_branch_addrofs;
// ex_lsu_addrofs <= #1 id_lsu_addrofs;
reg_zero <= #1 id_reg_zero;
ex_spr_addr <= #1 id_spr_addr;
ex_imm <= #1 id_imm;
set_atomic <= id_set_atomic;
clear_atomic <= id_clear_atomic;
end
end
// pipelining of exception requests
reg sig_syscall;
reg sig_eieio;
reg sig_isync;
reg sig_sync;
reg sig_illegal;
reg sig_emulate;
reg sig_rfi;
reg sig_rfci;
reg sig_ibuserr;
always @(posedge clk or posedge rst) begin
if (rst) begin
sig_illegal <= #1 1'b0;
sig_emulate <= #1 1'b0;
sig_syscall <= #1 1'b0;
sig_eieio <= #1 1'b0;
sig_isync <= #1 1'b0;
sig_sync <= #1 1'b0;
sig_ibuserr <= #1 1'b0;
sig_rfi <= #1 1'b0;
sig_rfci <= #1 1'b0;
end
else if (!ex_freeze & id_freeze | flushpipe) begin
sig_illegal <= #1 1'b0;
sig_emulate <= #1 1'b0;
sig_syscall <= #1 1'b0;
sig_eieio <= #1 1'b0;
sig_isync <= #1 1'b0;
sig_sync <= #1 1'b0;
sig_ibuserr <= #1 1'b0;
sig_rfi <= #1 1'b0;
sig_rfci <= #1 1'b0;
end
else if (!ex_freeze) begin
sig_illegal <= #1 id_sig_illegal;
sig_emulate <= #1 id_sig_emulate;
sig_syscall <= #1 id_sig_syscall;
sig_eieio <= #1 id_sig_eieio;
sig_isync <= #1 id_sig_isync;
sig_sync <= #1 id_sig_sync;
sig_ibuserr <= #1 id_sig_ibuserr;
sig_rfi <= #1 id_sig_rfi;
sig_rfci <= #1 id_sig_rfci;
end
end
// Pipelining inst./CIA/NIA
// [TBD] the coding style of pipeling logic: functional and performance verification
reg ex_valid, ex_valid_value;
reg [31:0] ex_inst, ex_inst_value;
reg [29:0] ex_cia, ex_cia_value;
reg [29:0] ex_snia, ex_snia_value;
always @(id_freeze or ex_freeze or flushpipe or
id_valid or id_inst or id_cia or id_snia or
ex_valid or ex_inst or ex_cia or ex_snia) begin
casex ({id_freeze, ex_freeze, flushpipe}) // synopsys parallel_case
3'b000: begin // Normal pipelining.
ex_valid_value = id_valid;
ex_inst_value = id_inst;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
3'bxx1: begin // flushpipe is asserted, insert NOP bubble
ex_valid_value = 1'b0;
ex_inst_value = `pippo_PWR_NOP;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
4'b100: begin // id_freeze is asserted, ex_freeze is disasserted, insert NOP bubble
ex_valid_value = 1'b0;
ex_inst_value = `pippo_PWR_NOP;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
4'b110: begin // id_freeze/ex_freeze is asserted, insert KCS bubble
ex_valid_value = id_valid;
ex_inst_value = id_inst;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
default: begin
ex_valid_value = 1'b0;
ex_inst_value = `pippo_PWR_NOP;
ex_cia_value = id_cia;
ex_snia_value = id_snia;
end
endcase
end
always @(posedge clk or posedge rst) begin
if(rst) begin
ex_valid <= #1 1'b0;
ex_inst <= #1 `pippo_PWR_NOP;
ex_cia <= #1 30'd0;
ex_snia <= #1 30'd0;
end
else begin
ex_valid <= #1 ex_valid_value;
ex_inst <= #1 ex_inst_value;
ex_cia <= #1 ex_cia_value;
ex_snia <= #1 ex_snia_value;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("%t: ex_valid <= %h", $time, ex_valid);
$display("%t: ex_inst <= %h", $time, ex_inst);
$display("%t: ex_cia <= %h", $time, ex_cia);
$display("%t: ex_snia <= %h", $time, ex_snia);
// synopsys translate_on
`endif
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_4_V
`define SKY130_FD_SC_MS__SDFXTP_4_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_4 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_4_V
|
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Projekt : FGLT TU Darmstadt
// Dateiname : spmc_dcf77.v
// Autor : Stefan Klir
// Modul : spmc_dcf77
//
// Beschreibung : DCF77 ist ein Hardwaremodul welches das DCF77 Funksignal
// decodiert und an die software sendet
////////////////////////////////////////////////////////////////////////////////////////////////////////
module dcf77_encoder #(parameter CLOCK_FREQUENCY = 16000000
) (
input wire clk, //Clock
input wire reset, //Reset-Signal
input wire dcf77_non_inverted,
output reg dcf_sec,
output reg [58:0] dcf_outputbits
);
reg [59:0] dcf_bits;
//reg dcf_sec;
reg [30:0] cnt; //variabel
reg [2:0] dcf_edge;
parameter CNT_MAX = (11*CLOCK_FREQUENCY)/10; //1.1 sec //minute finished
parameter CNT_SAMPLE = (15*CLOCK_FREQUENCY)/100; //150 ms // < 150ms = 0; else 1
always@(posedge clk or posedge reset) begin
if(reset) begin
dcf_outputbits <= 60'b0;
dcf_bits <= 60'b0;
dcf_sec <= 1'b0;
cnt <= 0;
dcf_edge <= 3'b0;
end else begin
dcf_edge <= {dcf_edge[1:0], dcf77_non_inverted};
if(cnt < CNT_MAX) cnt <= cnt + 1;
if(dcf_edge[2:1] == 2'b01) begin
if(cnt == CNT_MAX) begin //minute finished, long 0 detected
dcf_sec <= 1'b1;
dcf_outputbits <= dcf_bits[59:1];
dcf_bits <= 0;
end else begin
dcf_sec <= 1'b0;
end
cnt <= 0;
end else dcf_sec <= 1'b0;
if(dcf_edge[2:1] == 2'b10) begin
if(cnt < CNT_SAMPLE) begin
dcf_bits <= {1'b0, dcf_bits[59:1]}; //check if cnt if < 150ms or above 150ms
end
else begin
dcf_bits <= {1'b1, dcf_bits[59:1]};
end
end
end
end
endmodule |
// AJ, Beck, and Ray
// addition testbench
// 5/4/15
`include "adder_subtractor.v"
`include "flag.v"
`include "Implementation/mux2_1.sv"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "addition.v"
module additiontest();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
wire zADD, oADD, cADD, nADD;
// declare an instance of the module
addition addition (busADD, busA, busB, zADD, oADD, cADD, nADD);
// Running the GUI part of simulation
additiontester tester (busADD, busA, busB, zADD, oADD, cADD, nADD);
// file for gtkwave
initial
begin
$dumpfile("additiontest.vcd");
$dumpvars(1, addition);
end
endmodule
module additiontester (busADD, busA, busB, zADD, oADD, cADD, nADD);
input [31:0] busADD;
output reg [31:0] busA, busB;
input zADD, oADD, cADD, nADD;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t zADD \t oADD \t cADD \t nADD \t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t %b \t %b \t %b \t %b", busADD, busA, busB, zADD, oADD, cADD, nADD, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:43:34 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode funcsim
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/mult_17x16_sim_netlist.v
// Design : mult_17x16
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mult_17x16,mult_gen_v12_0_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
(* NotValidForBitStream *)
module mult_17x16
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [16:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [15:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [24:0]P;
wire [16:0]A;
wire [15:0]B;
wire CLK;
wire [24:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "17" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "32" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mult_17x16_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* C_A_TYPE = "1" *) (* C_A_WIDTH = "17" *) (* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *) (* C_B_WIDTH = "16" *) (* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_HAS_CE = "0" *) (* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_LATENCY = "4" *) (* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *) (* C_OPTIMIZE_GOAL = "1" *) (* C_OUT_HIGH = "32" *)
(* C_OUT_LOW = "8" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "kintexu" *) (* ORIG_REF_NAME = "mult_gen_v12_0_12" *)
(* downgradeipidentifiedwarnings = "yes" *)
module mult_17x16_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [16:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [24:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [16:0]A;
wire [15:0]B;
wire CLK;
wire [24:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "17" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "32" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mult_17x16_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA
I7rHN/CieA==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5
Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo
OP1PSFj5jpodG+LwXm4=
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF
/kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3
251QPjQoZCw3A7W9PDc=
`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4
udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S
VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg
y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv
hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw==
`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
QaRubtGbYrmCghuFdQuTgTEtoVYYLcPnD5z0C7mo18fwCG17qy0y8mj8xWiwE6bo49IP1/JXSIw7
rTBwHFOVrmbm926sWNrF1r3IHB83C5cstprQ1om7vnkw9XX87SjkscphhkrHmi08jjzW4qX96m61
/ymclz5TlAocMQJGz/jwscvIMOrrbuH4SkWQOLQnRfx9GIOv5Y7PM+w/wuDSeFXsAXz7Ahq3/qmU
cylNfSufW7/zfN4RZB4u+d28AXsuFe03aSF1dpW+uBK1xtNZccvj9h9NMN0cuwxt8ZUlLJw8l6e2
hqRfTTZl1F4qnnrJu6w8h8uEGrmgnQG1AW0epg==
`pragma protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
XXj6Nc59BeA5Kznlx14IKravf7ohERw7h0fbO7pT7/HsiPDCWh2DlTGpFUcnbNZslPN2RfE0nJNX
WMzLQtaHK4Bm6kxY71OsXEKm7MAIjEdLwOMtJTtlZrbm7chBbSxcW6sjWvI36jk5De3Yct9Ao1py
DpQ9NICUtRTwGG8SAiRkAXRh2Jv3rKvnookQrlVxIkNRSBMSgbwuTbq1ze/KMUZebBWwJNUVIC9r
RV/i9wjYXBOeCCUk+cGDC5uSpwdLXYV9ZxhQUU6C1ufAaK2m4OIUeBqPc2ski2O0qQYQ67c35k50
ynO8H9PTEROPEOn5c37S7feU+36OcOOAsVBTBA==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
CqOwnrr/KIlV/1zLA5B4uphL+fMjPjGg3Cc3G8OUFvB4ffycztPZLCTgreN2xkbKApzkJwXNkjOl
G0VQbILOs2swPmKRbrLSGMq39MwHUuvmEXxqVjRA0Gxfl18q+qzji8l6T2Gw0dnUaEwKO5Giq2qt
FfGAeGxAf8SgWLw+t8iehGqB7WLEFszEh4iVJiz/cjsmFj0AaR7tlNXsv4Ydrw2q9/AsVNaOIyuM
nDsSoVi4bUa+JL40hgy/PENOl4zlrPfjLL331iJ9U2jBGsYk3LGZNygifKx43JrvKv4cTW5D5Xl7
LDS9IifrnHa9kAcc1JaBGcEosKVfmCVegivp0w==
`pragma protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
ULJH61UTceC3Y/6HfRS/V5La9NUGO/HTiKliMg+O0E5aKsfPVb+1g2wZoXSJvrhJRl7cSIjo7WK7
kVSUR/BAgkAj2r84t1doJ8ji+rFW4mF/y5lcQ2c9A5v9MV37fqYBws3+sZvcAcVZc41v2ObVFAXG
248Td2AbEG0WZ2pWs37Cww1ix6rkRK3GKy4gpjQX4+lq9mDPs7XQI8gf/KcyHFZFGFMkSrJnD8mC
5moDcwCDtDKo4cWlqg1MV4ZZoOeT99z++Dw6bT9P8kYd9slHeflHOIa/gF+RHfUSRiHhQM6JQyxQ
AfK+gDoQpkPfVlVp0ALQC1UPUhQ9DIPHOuMX/g==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 337536)
`pragma protect data_block
n4L9wCZ92OjHJwdUcny7E8bxNPElwTziQg+io7Ai02vrA+LMH4bMsMpbMk9FbZTWgl5oSwzajsWI
ps25k/C1DYM2aCYZFUTajQnBubIDMHWD3C5teZziBtur7bcoFJMHVdTZvCNlCaAD2eG8XEFnp0NP
70DoXctq1YVaC7XJhzYvPZ9aNAMfCqZKAO3yDRswvmKTfOrStxb/qEKlrKsYsW1WUZIGl/HgqB+2
mqegKODE5+U+ix95aEcmAkgCr8zr84D9ZXuxNPW/fZpvmUMP1V+refyfphzgBIeKakHmtn8Ml74V
rvJloN2v6ARSU4lWMZVYNV5fYvkmXfAXA4rCxe753Rb1DveuMVl4Mne52b4lGcFJHWayBHYS5OrF
M+rSGSav4VCtmbkaGk0I/nEtAfWtMgPzS0NOJunbhQk/gLw5LhkmcrahYDep3yVa/+CV1nmpOIFG
YtxjddhWd4gZJBdFMvxSAscCwQws2HaoRnLg2C4MaRWqGfC81JJwp97oO+8T0n95s3w0pfMOvvO4
chg5X0ojyqfjwMLiKfUvoEM0VHZeGBIfTn9rtYB6NSHkO8ReQU+EaNiWQwQHr84urjY/XofN0Epz
+yUZtARbmups7J1tq/7zVy5WBT6me8V8wsjZmc0boOotvfObA0kE/pbYXxF3ePxXky4gQSrJVjx6
R2ohvR7uluxqCT+k87U/sQJSZ7B6PUXNvhBUfbPT+Ap89+G2VJE5Mt03Y0rcqaNKIQGWnnyLUP3S
5utvmQuKz+HS/6p2Z1sZgQVW8iE+800anBiLubYZxjV9Kdswh7HJ8hiuOc/z60EwcBU101nmDH09
5V7HzaiOILzfnrsX/0kEwg3wQ0JNfNBytwquw7JfRWs7tJurkYf8ZHm2DKlNjdj0LePK/WqfBM5e
Hn3nrX4ipoh2EMbgG4MGualVftLlOIugx0Mvo32UvGFdf4v+AXmVAM9WAePAKxPE8UMEcTni/e9b
HfS7TzemFI/ZP6D52De28pWUOLOQjW/2shCnQ8GSyYHmhVJzZE1dDKfSLdlWg1ye9T3OiJ+aNWIn
/6ru1C4E5hIJTVOBpUejD4O3VKBOUkwjlVWmTr/68GinylI34VN7F7FiiLAdzaV1/kyT2lN0fH2m
sGu59fDLXiXTClNbpJl9ShXL8V1DRdgGufizJtsbuMDZdD1ZtmDR2sC/7RRHYyjsab5fpK3FSeEg
dY7OgwNsSb/hSBiKYwLtvEuxGeeV13h8DDfH0bL6vXVmKBnoMyy1eR2lpbzKrXHe0dck2YawBCwb
b6r3dSQuNC2M3CEyBx1kyV/eFM1GdW7tVfXCiTDTVQb5oJFN/LlaLFU3BbGVALLkpAdAuY3e+xoa
fscsPu/mbN9NEQQNNzCJLhtRHVtZP/2blezPbZM30Cm3LyXuXJd8G04kJKEfJ+Ytb1drp7jO/Myd
TumO215PA81RTbWPL+StZ3yr6SQxty65nXNjZtyIlO/d4mzh46BjTlprNxUC43SyDUSHssxTxuJY
6FW+NT0BIdVPWCw/rmHnQL3uElmR285a844IIciMsOENHmjIAyXCI2kP5HVXCvKyMIEmndjmNZQl
uiFQ573zNaUSQCNk6YuM5MgULj88eBoVDiN5BG+AHoSJWgr+DlCQmsJi813Xub3J15+AijjsdKnn
o3j4BWJEEJsK+xN1H9hgEcRrzfG7LzSPtdJnvsJo+/SLfYik3Im09/7GW1uoe+iBBTHUSuPlQ62M
8Jdcd+lxZ2+HlS1itP+j7TP7ClL5VvLSlrjmg7wnT7E+vi+vUkFh50e6EUV0jxP80+gwtf7xlr5J
n1I80A2JMFuQE6YkL8vIBtZmqgtwbfIcq7uiwef82yeAC69ijXF19O8sasKeRqK784usNmLC0qgL
NCq7I1mm2mlZ2XDdi6//cNZhoNJJYMDYJRlBNr0i1DBlOko7dDb6W9G6whvJ2s0yArqEZHU5+28C
KdJTPgnuAjyriT7mvqaAdXTboTDb4CFoXTjtqHhrRAmhVvswAXLk0cKzdjoPIyU01bEgxCS7hT+R
E92+oK3NacGLQPE0zgh7/N0+jG53iGLmY7zqnVxDB0DMk78g5gQMLnLoZ3nfiBL+xA9Zyso7iay6
rGfyzZERASWgWXNpC2bZSs/JUcsAdoNsthvT2Pp4s+InOsiq59XnsuhaI/lUYYP3m5eQKo8tUO1r
4e4m5RtwuTYQT6LIdnb0rXQGCYeo5FW0KrGePohiBbn8XBDcz8nkvT/dYTpnMRG9LYZzo+G3Mron
5sovp7TCX77wtyORZH3uxW9k3B18tyh3M6/qHbgFj/ewcxNMty+06jgQ2KqkWy4Rm+vXJg2mm+6R
JfminxjnorcRcGRfqR37fngPVqz6SzQAcvLkgGt6fKi5w5MDE7lKELpxN4RZnALUKU2YGCjCmOUm
B7T2NGmzlCS1x+I2u4YrnQXC9rgMl3WyPb+cvTykgpOdXYripq0j6KbtEC3l4RZWjCnWBEudsSXj
lvTfvPnf3sQ7MZL1GL2+pyiWA3tnrix96BT/eWL/DhquzyHjig4EjaQB0PRbJ6veQ/vmeTd5bwcL
BHXiIcIICfETMTitG1+nhfieAwDky++Qq/FKF0oihnOpuNiAo/u5Af7VhMNgOdGO0MvJey0eiIsS
cmBVhK+/txcWihKX20VgLIu/VTbklV6O62ug50VumRaX1nBqW76U9L2oCgPMfNiKNWSjCAzGuvz/
2LwU0Ql0YoJrVUrjcxgewycfWgGso2Of9cZHDVleIRvTQyBezLFG9a51F3patDUIbeAwsI/d1Opv
J81L6vn4yYPrv0O4bvhMQefgjKM/RjzR/q8hxnhAh2EgGLnrlWvpWRUWQJOBYcXcivcqmfBPB15R
YxvhGD7vRwVaQwQ6aj8hE1znNf+11aGVuEjzUSN5B2f76E4wZEKHrZAKyBG6U3DjdZvnJDKhxgLw
OhD4wY9AMLcNSL0OURK9OEqHZBifiqeJCj3RazQ80TSuGQo+i/vw7qiSMMfWWFCn8sDXw7IWBI7Q
U9+pYOz+kd2FmoQ0gL0DtPdAPKqMlqFVWDqyYeLSbTVwSUKwEGNkO6HMzFbBrUqRc5bwAgnlhMPM
Vyy2ddac5zHYFbVuRmUzn7uesRlRNulKNmak+wvL1hjt18cxU3GRKHjvUj2UVc+KJKj6Orj0orXo
xvHu4XSRbIZqZby9JHHt+mmnqxGYuK94zQzM2cm+Q2+9zP8nJ2yJwczKFUeGQoiuT6n8yFl5VaKR
kgavHzouV9S0w5RR4ZLQT2HpswRVXu5+DuoRvNxI3xZ7qNg9wa0HtoSpZmlTQ9YRr9inSHKiuMFV
GCRkj949oRkYMNj3NW5/nPQOccz2GrrjscbZnfyH62wUHbLJMW/H5+AZrWTLhREERAlsPqy9un7P
+T1AtKtzpu3u2IdeMJQMI4DwggV7t+BZPU5Xfi42ANNowQXofHSrVu/WI45Qeirncx2pfGHpDdbv
OBrZdKfHvE9hkQCL1xwihKr/GigNlxnVjIIjYOA0/lQq8uJ3hpKIvi+fny10pIgP1xRGVgsBrs2w
TVOslL/C2L5KHnafjsBLaRlCccZm2YcA6lsTY99aa2nQa6OSuMA92uy353fDZjUavw5SlDyZONDB
q+xDz2nW7tK9U9tTsNN9NJoU6N/pidzY33fsQFLNKEtydKapJ2//LqjnBKfeh04H2U7f2WdN0yj5
8oHgQEpBw5GvBvzKagPDBBu9Isw0u3uFQ0jve/Y9d1ZYahKeCmcUY7bP5rfhvj7HySQmtGJewnRq
yxAE9FxUmXUWHG/O49ICzGb2sIctnqwJoQOE7PyZw0T+4EB36anjAI8pf7SwAytDEHEQDwtIeNDE
pryLTSRfon3tiAZ+MRgAeJjV+dfZ+fpU5fWIHBkb5xxww+IubWIKlMhfNdTuvNRWQK+zu2sDW+1A
nJ3vyTmGReRzq5HuDIWqH7GmHG2g+mRi/pivvbMt9OKb4/8G8dy74ALbxqK9HvCdxveD7mJkJiQb
XNMLF6zOrIYJv0J2l0gr2rk6TTkLU4LRdSwYDRuvolavWYGf+7hTiutHWpcjB+kZJ6DN8HyiBvGI
w7VkBK4Vpo35n3GebSeYSMTU6V6tUk8Hp6mT1JfcDpjs90vXd/IWQYMjLlDTRoqDuKYt7WXLoKGl
PIpXAyTIwKVvzanLct4/MggvuXQdzpwttRq8mKU5CPyXzXhQr4Dfkh1nJiJtep3LKfvVax4PXrFZ
WMzrEl0SCakCihD7PkTktvWSjtLPb8vcXuveCiUIkq6+3O8uSGhPasbn77SDKzyAGHe1tDS4AVbo
AomLWM+FpIQq53eu70VDp1BuwHN9YGOoxY85+FCX4xidnODJ5cGBArX+NRjdYF/4o4LahCkg5QJN
1KJ2+v+DlX0ZNpDoUW1LHuL0v024FONb0sTUZ5dH2Xt0jWXx0/+nzTIWCOhj3GWKVFwmWGZOa04u
HQz4/XjTZWuYVqtoIJCUWk3G51no/BZ1DkraNMPzN37BZ/93Is0k+mANyg9iOCuntIeLALK3XyJM
8TgsTJ30yErnh9P5gRYdXa3hLW7PO+XrvEtVPLCicxVSftXAkYrmo2psQAnFNvLt01YsdP5YYI6S
Q7sfKM+7CfVj8qgCOeyX6Bd58YF9jIIh0Iya9iwwy04ap5WQs5yLj3nwNsuAGDyZzuiBrmj8YTBQ
TJfLgKYXd+uLneF2wsbXy8nYGnjYiNQcTicr+aV44/CHzba1MJjKEZlfwG71PsA6hrFqMDj+oyol
VSTe3kyjHE3Wy5Cv0bJty0LjqrnB3+usBLISEGHDww66Lf3tNcu7qEATF4gVVCCREHfdxSskDOMB
+mu/AyNDucT01qQPplNlLs7QCmL4hpAnq2Bd3B0lZKgzGkL2HIAmB0v43CN+4d+DjL4p2OjNNMwF
PpztHwSdGF+h4XV5I0GyoUuEh601cgsrd6viYKSrnCnEzrP5Ql1QY7OKBpmAX2bIFJ5wXkz6mV7S
Jk7H5/jSqY97XoJnXsiyuDJ/wxNacFrpXWN0wPcSqBq/CHFFYzqYYJyEMcDnWQSRV2uyo/1JMuJS
R3kkwMC9qHTB7fKzU9u24805y3Fgu8fH6sk5LcsSB2X7GaqlAqgePX0nKDEMFVcNS+IB5v919INs
7WH4+6g0raI2r2qj8HvptLjJ62ckkl4NCdpQiBGGSoFd9gCOlNEMOBVgoFz0DNUi+P+UX7f4EWzA
/bXq1BdSp+QxrbWbDM3WL6n4mXeGM9Rm1IN+mDgQFdHWd9OcxX1J5hSX4LOYBp92YjWz2NsgTT/R
lIiDQVnvmFvgnhlxLgAE99cJP7VhHrxhqaQK/N9YYrlv5znu/KFE/KHZ6JiGuauTtNNEWtZ+7Ce+
26fs6F9t0d1YOULeTs5lGhpElJITmDkFQJc2NOlF944w2hZFV4K6XIcgkC5rhMYpgtdxtQwDiyv7
6fRVtGNSXA0SX3TinKWfK7LWtVyR0Jied0RHYcn0QI04i0kIfWYfGTc3LbVVFSz2z9S3dgr7lW/m
fsArMY5uuQNMtJGfNsZK46l1MbnDZCnT+9Er+qBu1hlqEwUf5VJAYE5pxJiePOezAitPL+9mGCR8
VhREIOFHm3H24fA/6FVr+5st3kM+XNkGXMnslKq3m5QGfJ+xbwxZBcBaso8c8j+0T3QeGx2F7KdJ
C4vh4+zMjWeNiZ0QRNNkV4bIQEsGlicgD1MesgO5qtqjynnGH0oXtKhE8llrF3RwaVgg0MVNicNm
va3b/SdWID4RGs2ZXOH52gmvisRx1AVIJif+N0lxbRt0Yj8/mKrU5VpjLY7HZMn7ZMCDDwEI3U+5
QxQJJNaHXrIPFac5CB0RgrtFKI2DbQq7JTrXlZpHGU32uzSHjuk/sMFCWp2GM2A4bP+s/1BIM4u4
CwBqPJutcNidPi9eUg7sw+n35sjV+dtUXrQ1usHnH61M4qrxRp2KraN7t2KhGwAC6wchr3Ehb6Ss
/TAMYpKpIBx3InnzMyG8JIYe1Rama6sFVQ0/BgJNTlTg/yXeLRc0IgpwQCZLf85wJNwarPR7lZrI
Wrg7P3DqBtGrscHKlUMUM4Tp1Crw/pmEPEzLOBnpCwDzR1mqTY2RonAemKxmRJ0n5Muuo0l8oAZc
zqyc9h/WXoUUy68uDsGddbcUX3u/AivH45ay/3qz0Y1nmnOgpk8Gur5+1r/7/7rU/NpEeGJzwKkd
dqIwiK5qEEvGmchjgp+uiQHBCL4ES/UuUpI8ej56fZUeWheq1oIY+74r9EPlKBRqP/CvqfzqG4ST
0lg4ZMlaLR91ZwB0GM+Ar+JWRiSPujMldz8gVRWa8X9Q07zIWN3tnVR+M59oO+VPAKCPgkAllOe0
ncFc03DW+BNsvzhFfGebPbkomar3YJe5U7dQICqAJ0OVqLRf6+BOtO+9JuJFVlA1HP6rfJqX8gVw
qusWllU0b/0lB6dsabfH89X/rF4NCu25iKNrSoqsiCQMyg0lAZLtMDGqLBtpcALgDcJH6GXPuG7D
7XmoVR43QXPxEqWxKQfS6EcbNEUQMqUmL3PxR3MQw5aaEDdFrv2zl3XqG4Fx5aKCfr4TmP8iB0Ph
WAOIP7yzj21Es2XajxS2xEicKe9lSvOKDWRD1jr5J2ddPiVDXJw+3INlgzBkWXN3sAzTUJx6vbTm
JI//8wxdxT86+EJ9MocKqE9EjJwIdwcbBa3e/v15mrldB35Kt9jjkim/pe7LKsJ1EPkDDbCVaud1
efUvZL9VcnAMO1LddbbOv11U/nvO/DgAN9z0uH3A/N9GudKoqNFJdcpQpHXtRU2R2VT8+Ac6cylK
icI2X3kNYjdH/NDrgrtKi5pQtIdOM+Jk6X4w1KyWKymNT0BKdXtofPg+LPjsKM5JUVX53FbZbzOs
ld2XsKfXjU+YnHCl06FjFytpTnsnGpQjAXLCH6fzqashO0/WI4/35ZuTjq4uF72bkDut7MscZxs3
7reFu50GCs6EBxyZvXldiBDEOeqMnV+KbpMD+0sfuClA41gg522iQYk/bUwQ6RzRt7spC0std2KT
kwy9h+FUvr6Q3TrS7tkmPIZNAew808xqVrpwKOUIR/hsquN8Ddll9XYSH1OLV9Doc63iWHdEuIVS
pBdH72woNSGH6y2NyoJaU+dWnCOGchllgVPGT4FUIXGhBZ1MYBjZlMbTs0hE/x7hN1xNDGdsJZgR
NzLMp5HYzPqDFki+I9eEWTflzdLclfb/pDXvJzZMxImm6CRqMmmNDCTndWDAsUkqpCaS8CnzECl/
vgn61RUN2SFYV4KG268lWKxqKrxS7XeYOtgJgtGb8u2Hl8gD77VHhf9adPwxLWICj9Eab2sOLeK4
vIYjlS/fnKwcs19m+JgI5B0iaKwtVo3XnHBbUmfVBFw50vV/RIcujjo4t+pzD/bPe9GD1+nr+4VB
m7s2EkUP18C5ejSXGtZ/ztkLNniinc/XcHtRVDXa2E5wfad/hmMkyXbJ/cL1CrS55rjXCa1Sq/Gd
fgdhagmg5XxOXgFyhkBYyYQ2P5WjMI/vOxan/ebatOwlBjEjSc3lJXdlOrGGf2SC3+i8O5j5uOFr
7T5g7l4zjD/LuN6C++JJWbFd5mdqQmzxhkikl2WyD1RU5yvDWEMfV1v8cWP2JrjE7w186UJcGbUd
h8EBJucKXbO73dw3VkXqFhLk4U2pQ0ba0WJztkORx0pB1LnMNzg+3poB/d8IOtheF2YYOmaV4BMR
Ro5A02VW2CNReM1l4Zeb0gZxhs+NtSGSn1Zvk67bx4nIwqvy5h86aezkYNQadEgotgFSrPnDVjVX
mqF1xGOUVxwEuAEl/xV1iR2Q2AbJffkxRPy33K/KQGE+jT/ZjQ2NuASnGGCgjwyYsmze4USNbAni
MhMquIKe2ng+uZJ07zPd7Zy5THMvnrrbMchDAKsnF/aMPDshRuYEunu8ZJfHMA0bdk/uJBYLWaku
W5IpBEMl0pfXF7SAxJBupfj0SFaLR5DdMcfqRrjycgv8Nzb5nVu3L9by1awijH18vp9D6PfzpZxw
SBI5Uo/iRUmnxXDShNbdjH7uA9gEYzOgZxag466x+HxR+luUlKz0m2/BoeSa4BLpFFHr+BUMwqDL
rmw7QYH3Kv43iDFVMUA3E/wENfNbpMkX7AP4YFL/RMXTweZUMlJp+OHjmStMHDDEci2WaRO1yYKM
Lmff6sdeXpegf3pDEVoQA8NsI0PxMwgBP7nB/n/gRtMz5qE1ua0f0EOTbQlRtJxl79ActODh7E2v
tCR3AUsIItGcLFdUKvu/zzrpMJgjN+MAZD7C7aSjyZSwsFHRr6fyYy+P6bgAt5FiRgBQYd8i3sU8
p2QX4bE1BL1VhcvcqvebD8fy2J4ifWX98I1WbPTc/BvypeoCNDmrHTt5vev7MdYIfAOR9Qn0UC3t
SS/isCxIYrc0zhpuvnUzMNBtLm1NJkgO0KO6E75boaVg5aQV50BXVjArSvzueN9ATgq7XzzaTuw/
K9nDu0lPNUDdBP0BQuhRnqiuLeiyfYxioQQvaWJZ81CAHV/YI6ONvHXXHLKPlAXqix9eW+bC2g4A
9YMVaqYns6AmdOulWUmxF/MeQ0bSj0z8D45Zt9D0sGplKy4VXGGn2kcBCQdBAB4dyExIkc9EpbGr
iSuY7g0uUCYGbuYZObcA7dvr9r6rpsOMf6pBZiUSZL/GlX9IskaAijnANvXsEy2MT6He90ajsIgV
m9jzeFX6KnGtGca7Uc8s6SjTXkUaIcQunuE9FJ0+CPOJeJTWN7H4UVDmHIxJtAOwVsZzYBYpCM+h
w202uYocJrtx8cQP6Zv5mV7wJbdETaINYTuqH/5YQaIVmBcCeYK0/cH/fkS2PW/o3NJCd8bP5INy
lbqL5BBUu2q5Jw8eS47of1GOxgSfzK0//8/Gsp1Y9hj9k8KvNRxeos+HnHHXfCA4rwz8s7qR1jCB
FbUcBUCiEjDLEGymaZalsWPNHyKDfBzca9/uLTRJeeMVDO883Dxal8uqAct5VBC85HzeLbJlyCsg
nfhhbexHtV5YmcmWPtgZM/+Yw5fjiz4Mb3esG+tBApUCZsHKMmIy+KGi9zhWocTNSAtEElGyzaRN
YqZOR7iYisOxgMANiEL6JeXoEQlwAml7vnf+3fngg4QmFxviCMfLuXnlNSOsUoF1S3c8Qfbm/fz+
wWxGOs61m6P0K/aAXrUjlLv85lZ0EAbkY6lHztuRUdBUFswvydoll6L3Y71tILZkt5lsgFgQAw8F
xbGYhL+ujS08JsxjAU2NWIlLDnKNqH0bHzAycCDC//XcQF1H2Ofq4wPu56hANW8Z9VbS8kGsLkfU
qXEJatI+aIjX7XAUWA0WhmETUA2/ywv+4MYDUlkg4EiGMOfhcZV7aM5aklwCnXLn2ZcSgfG09mGo
hdO8C9XR/R2SkSI0myiik+/4/tf8kJmELVVGPmQAAhJui5Bfp6MUKyprYjm89I6QzfAeRaRzriXk
sgzrjNm84apwFRmp7AWkASDWMkXVwR4en7dCc+KvDCEZZNvUUBMwX9GZsjLd86Yd0LMSSM9J0ipV
qv4DJscJTARqKQC2Y0ddW6IAm7pQvLcNQ60vf8qvRVdxdrCXoVnNwNB5byVBTCzu3PbJHQKJElgz
BCWNRG41quCzZNJWPIzasYZvyka7TyA7S2nmvO/3mM/7KnAsOM4LGfosdArVmP1VyBr6wvcnmMkt
5yMBJyIjBvK7PvXPsaug/T5m4vaiih/OJEY/wnByI7QAfwlnzDfGt/K69cF9/diGpTjewbu2GmwJ
Qq6Yw1TdymzX+mJbBA+oYuYzPBNE2OVj8iSZ03CjL0SbOB9PmGC7oslYCYkYIq6s6A58qoPYLD8N
BEiN/TZe8tLrbAzGLQam1ti1E/AW7VE2Ctcy/UWToy89P1RX+hn5NkLiAOeUPkkK08NEz1hpyNET
1yCEBrXbqKgfH15h7cxbDD4Psw4/DKIzFt9C7k1wTCWoYmateFoNJBq2YvkILJdOhnRE1f8bQb89
3xsH9k4SgYhPNSHP27UweXhD1G0eAoBFVKlraTB6BFkPG99x6VKuLE3j9wp9NZMq3r9kemTN3Jq/
SMglK7RlT93uw0BoVrhaGosSvNcwwCIqoP+D+Y1W5ExxGUSmSwp41DWbrTaPRZSdAg2deq/gNYsf
sLZzxUW0ClkiXGGu5Wx8KDbKiS0d4yslRAtvxKW4vUWVwUrSE2w22OznQZgQc1ymwwf8xA4tuMbn
nGRHnpqNfxID1JHPDeif3AVvKgulBHgYiPPvIDc7rVCqTacPSQKkZi4dkLPn7t8ufefsjnJZ7pI5
KVGVGBd2gBMhVKqAt2NgaqysG1DBLmD3awJOjRCw9zuHoz09IQPhzd8R6msrcSu+ZGlrtFGO41CE
rzOuMrqY1EGZlOOI6gjvtZEFhOrwRgHor+T2OIVR6cj0R87cxDQLLOkWSxXEzHNxp7+AgNvvi4t5
Bp4AI8POupQo9FcWpqvhjUwd2+zuGJzhSVdD6WWYo8VG60+uE7nls6z7KMj8d58faLydREs11SfY
mmT5yjUvVXV44SxK0KZV0YwOa3ELofyHjKz4JoLNDNbZG3MxM0s/9FQhCntGO93e5GB4n6uwaBEH
p0mfs6ODYyU5CMUum/Vy9OwLa/UKnf5nV0NHMK9prVsnww2ABmvq+3EbTBejbx3cizHXGa6Sd9Kh
W4Hisg2Zrd7u+iclSZcxkYecT2qWyd9nfTXSH5H10YO8EuokWyl2rbyBsLVsGRVRAg4mQySREH5F
mWHlWpKZsQjzTW9vaHzLS0TqyF7Jl8NTN9K8dbs4d/SZ9CD7WtzkjkLZTcnGKMhz4EPOTpJOyF6z
ulhvKGKDNduvordNbhvhrxqinmpIFBVuQETGp0d551yxeavvqhVwpPRlGSSwjhXvlaigbyv3i2Ga
FUK7wEZuo+sGjy6s4JspAF/0pdGnLRMXvDEN87ePRHyiPJ9WfpxVSMBeBvIli9tLg/KffMWtwoar
Tgwziy8Kjeok5ZoRAyKGDFwEO3q4/WRADQOaZkffgwjm5kob11uC3Zt9PdFQG+Desro6N4X6Cufs
M/ArnwBGaJUwMPdggK0ct29A7dL2uk0jwaUGAOULvW8gVTeMzFCYiPrVrZIIXgLAQmj79NneA1pG
F+NcSJoz4j5rtVl8ke9MWztob1pHTOFWniKUsn5pyhEp3xzVMHigOxJFmjCmCRaWCqW1Zi12FJYU
yyUpiQ6WalCJ8Lo3ThXmV5R+S8njDZmlbh4eNMBwJzilNU7qTQcKMoDc6fT9sWmBR+3X8+yqbItx
T9mP61WO8PsSmazN2EU8iX8iO5rqsAvbt2vOErBe/3MrgE9NCCOzQ5xxGJdBpydkcDm6zEP77GFq
rqemwwQg+tgwrTY5IkcWV4Y2ZcQW3k/rR+XEqykq2/62hiQCvh+4u7Xlz8vQO9f0lMVyGr0RaADX
VYvcL9asZ7AbgXwq1osa0swW0kVBttRtYNMq0ucme3vXrLUY+qW6JOxfnr6IIlszsf860njWbVSR
N5f19meekh4OEYCd66jzzTdVeX5TNCDrh4uNrCV0igL5HmRnTeVO+W4dg3o+SpR1/ujqBDf4pJyJ
4qqoh4I2MJYIRodlgGoAoZqL/3H1fA4POH+0oGadu6Zm6Ymv2ImoV+syq4YwvYO3I4+thFA+IFR9
QbfZ/unp8Tc+v2abUEQXvsYs6w2TpNfogF1B1YjLCOgazZtd6x9O9TV2r2twcW1DA4vEfmMu3yim
a+yj9qXUvMK1JXVZG12AA/ki9peAOGGr40msIthItNAETtBI81zYj7pznhhtKjk5eX3tevTiyFQ5
wB/Vf1lZjsxOTXfpjy25G3ZE6mc1XpdCiaHAIp6RePk6ePWN5MaCuxA+gV5iWRK+zXJPDQLR0MVY
fEIQzZyZpbgiv3BOZeW3X6eor4bb+RAiNfoVKXVpjuEU6wbKpSSjAQcPSM5Wm6Cz5luabtg5Txhh
rAPhcAOFHq32pHDebOo42U56URSVzvJM6hyctPYatdc6UFeonK9S2mA7p36Dz6nBv60uNpRbbjZn
Yf5HcUoNf9jcIHe5llTNRJ4CDn3Ulqd0GBnSKDC9AsRzZ/167CtRpb80TDVy/TCyLjKs/dql0Ei5
yN2uzTNMT4kApH2mpLEhSCjQpb7DepvIrvA+oxSGzFIXP6fk4xolGSOPzJrPnYFYgqzSQCeK9FcO
s9qHUH1o+QOJfLlQ4FjITVaeBwtnvdJXvSivjJJisiXLjig8LfR+AJVl+UDL4YfEKI0zvQ3fLItV
GrKXIu9GJmKJDH6U0UXmoHzYauC/IfMNkysNzf/m6Bvj7BnzDnUebq/ubYodM0ykfiM34mKFuXQa
9hVjLgyTqWm1t5f0oaCKT0uUkJz820XTshjU/K4pDq3QOlUqtpKSZkg8jcoPlCeIAjrcnnB+Mgvv
rwnqiSsdwevOc1Q71t7q8noLzuZ3lOR8parkGexiUi33f8Ffj5KqF0zmaHG7PJUIpWjwHoOcFmpd
zcZwNi71AGA4Zz6w6YaIh0I9ThqUSRHs4t5IsW0DDH29wiVgUltvSo9o4gxYoHe1usikUPdwDABG
5+DyB4C/vTQdzeogtqYC6mKcebJhnt8EFdWl7MsuboDARMk8W9w6uahUSIcTbCW6a7ZYoKUA/hSE
uQxjhsLDYUVX9WxzHzFGdFOwKmZ/2V7wppuEuziTnb5aF/YrALehCOpOFwQJnmP9i6/gXZ3+OOuq
dQq4lxqypiHF8Pyz8d9iEtOZRCHzUO0azkyfMF/lEnEKdyj/YrMVVka02aUmRsWHnaHTJhLHjU5d
SAv492Ps1PJN8f5xALUNl9r00q++FurjHsd4CrZRAoYvZPIeJJm3+M2+7GO5ICdCwonEI/vz42mm
kyiF9iOra0CCiWTc09yeaVAkxYrCejiAMen11xk2uVuKXzGnWOO6Djr9M8d81V7HeUQWj+Hlc2Ae
FLnUduciqHx7O09epOpu85dYPhvJBDE6eBAByspdEN3JeSwQKyT1UYHCAWEGUF5bCypFtFtm6DYX
+ZyQSi+UF6WYlI3cy3CKdBtrIdcOpmus9f6YCTYcOqNIshFdaoG6BZGpNIqWXm1AIa63HqV82wvI
y+QpZBogXCmUnjOR92GRaxkdWBCuo5SI4XALNTgT88JSshI/HHTZ/cW41CvPCrl3Bg6901MNwRAv
6oIdlAdDn5kwEiSh43VxYtR9ox15McVOqUw6ex6PwJO8GGSpjHtz4IKUHoQm/2T/prvYMHWaYMZ6
fAfUdxQZLuMKFNdceqC+NONy5Rd6THBcse+Nfc46UZWQ6fmABeVBhjEd0QLIfVtoTSRWJdrETT63
8NUjneF8LBq4rHu0oE6v5n2YMKp9ts6A1WPxMMb1fTK16ETDf8q8UClUWQ/PFiQ14XpgFsDahYVL
KlBqjV/58YpPq1OoFv/bMNmS0pPgulM76d33q6lX5TuwKmkhLOkdqa8ex590MPQOis26a+7Keydt
VHp9S1c7efoIfVKpsWFOUzyR3t8XthiULspI1Bud3yj9Kq2KYiN96vVDmoOW6V4MI1BvBKqoKnec
bwrQR3IZit+zeqP4kJjlQDLQeYQKd/2WpQAjdir3OY17tbwKi2nnJbmWmxX61tHvsW2NztIDkc8K
a9ChOXa/VUajR2XJvO5oPVoJIZ8Hplj2SvBSnuzCYrQTbXWY74v2mXyn3RrQMM0WhpLkvNKBl2xF
DDLvDiSC5jEmxUhPxgUCTFTq9B6lrq33OoRckl143jppqxvV2n/dHcncDr+vzCg5Gq87zYIhzdLX
XupPR3kkgenrukS9lEbk2nVcRV1PnM4xgCj72lypQbGyXtgxEdk/chxli3pa5e695u+/s7a9NXhe
p2gDuRUIX78L7DwVQ73ZsfH4VmP9ZgsGSe5M71L8NfwPix2Jx60w54zJyKzgEnQRJEyyJZX0i0yE
3TC3eK6fb0u7oHLDicdGlF7ncPF9GiYDcjgJjH7qjoahdpzRa1kd4Ud73ZqG5dzn+vafI/OM5nHB
L6ZA7N/fwfodVTJqfYMSqRyqFvsG2oWd6QMsNZlzpYb27oxZag+nwU8KQLM8MpTwZQN6bcr8asYO
e0ek02kx5hGj+wBjol5RxzS99e13fnqqgOaUNVvQBBF7ycEfLxjuId8Xcl+TScCLhDT/j1obqhOZ
lLekuHOMWKTsLECzkNOOYmUwvbZObU1tGmJ0QQrsqPrpqQQ/Kx0hibwQgAZzzHwXLrQCuegrdMPi
S95UlTRml6NVo7imB4bqc5o7lGAKTTsm+A1Ub37eouB2+BFjAIv2WVrkIpRpi0DSkzvoxAGIwKpT
832IgDu5eZTHZmHR0bumhnSs9cNjGtCBETWBrtdXtF01rVtYFTuti6o1OI95WsvnwStNrCi5FFFm
1iUimx8m4nv7riMGpsHwP8wC27IWXyq8x59A+BIfeYqfSuQkhRhi6en3gSzWjhDkvPU2wMSScDOs
2BwPEq8s4+751mejl5CXa7fqNuxg3NwMEJWSFE5DVZJmo3orCCJX+39vuY34ORzM9fPx+PYt6WKo
x4ltA4XQc5xk4E30hOLC1N271QNX2Yxcw3zMvE/VJsLhtkOq3T4i1d0k9mVnfDhFbyNfWyfWeFeV
3/6M/wFvVC5G6+Q79GEvWRnjBhrEsJovtZuUjER3ZQSNf4JuUL2aCn4uKf0nXchss/X0SGcYRTvC
r3gGx8p/HGm7yiFftbA2+axIoqezW1+CZFdl/qINwzCzc00KjS8SMcs0drg7A3gkJy+Zc78P2WRb
5uU1cRLOrz84GuckRHz/HM1lkrmyXF/yBkxAGbjyJ9YM7CjpRdB7RaHqlBxRztHKmovgV9qEmxjb
lbZZAx6NCRCNCw+5A1rouQzz9UoF5oOFYt3hV3inlBWrkdYJgry96rVQtVqjhBT0SPsx7xU+s6IH
ScSz+rNdAQdvvFsqRaCuMliSMWbZXMIRzuNx9rPIbIgZhi1dqZg2zv6SoU0PCQ9u1kYdsMg/KS9j
6w6DrtDfRAun8ju5XUt7s2jmjFYpXfuys1WFlFBZAozRuCcdfz4l6SfxBflpfVUlSsTjjC+Nxx2N
m7E+K/0AeoxDwJkif90qZLQuqnxlqfDr42vgFVtHR2x6yHIX3eH9I689YMl8dxCxDaN28hHRVZWH
pefi1SKm0QdczZ2nuUoOi7ygVBgxu8p7Afdp4K9OQEA5fHY3u9T0882/CfYJ6ftbolmJ7oOnwCrf
nZOuT2vLiQkX/vc7NLtEj23+Su0nv/4DjI9ForlQkGjvTmL6YlMrQt45rjWvybD3df6vf6M0a4bo
u9q1/1bQML+q0wOR4F0ZJVREullVbijw2tZQIW77YS7se6xadsN+04Yk8Pg/RPnvoOAA1VCxM62Y
Tv5xXauMwkRb8q78+BNZnANADfH6vKyWCIifftvFqN1x2dxP5behHSy/LkdebT6ur1qxi8zps5xS
+S2dc/MohE+JV52mrSFQUmwL19Stt83Pnwgj3YHKa79CeO90nz083MGfC7h4DzE+HChdPIHkbgLn
Gur6KKTj+rH1zVnucmy63dlZ2SDScgUPVndw5X1gYCP1KbHAmsYVq2ZWJXhBOqguY8kxelxVAnx4
EHgvujhl6yvWYkOVsckakA+fOV8a/Wyhb4Jb/Mt1Q6EihqPLSoIAdgaXQRJj81FjDDyd6BwtNECC
7YWFiSIU2gX8nYZ5iMOh9g0v3LKvfKhwttBgWVQeCgF2n8mBB/tld9TklQ5j8uDInAdr5UFIpUNJ
v/2zChfCzGPet4zwaotQmY3NIQ/31v34dj2q9Mxua1bubaX/LMFak9OWIwY0yB0NvZnBZLlIYBnD
8A3K7Gfm+6uwkAoxUJs8gW8dDeMNofgZJVTd4qrAs70bhxmzzckhvZ8VaRCgdWivfbUSBm7FYofU
Bv+RICNbi7cCBR+NOpJFVhSudSfqEGpK8u19YYWTGyxFC+tghjRJui5RvNtCGJDdXCeZiz6SZv2s
v+useW7mX1k+LYgv1PzCXZ++KjMM2bQUZuDmfKiMjUfOVYjtUgeEVbLKvfOpb6ZKOolXgQzXB5Wo
9CsdFstQHQMFxk73i9lUdBtcyJFCimWM8uYREQ4Eg/gLfhbgtsYbDTvv2WLg90n0fLDARigcp9zJ
EsADobEweLfyy2IDsB0UWpyFkdoV0jeLodPWkGrjAuGDjG96YWVqMKTlEiy3oYlUizE7pFEfDjJ6
wYQfMsDC0VGSL/zF6JMf63JKhBAUNW3w/0WCs5pS8jffrJgpYQrci/F6hiWUV2ytPLpWSex93fX6
DuKCTCvjc690reOLkorciEYuG5XyYU2PyIa6CoTNaKquE1CqztWTPk2e6r0aHP4DF2CjiN7yfix9
pIQgnXz1nH3GmJM61kKSj1eaV/eB7GBgse1mG8xiELeNVHwCLKUhBi3Zdq5HIW1cNsFsiH6AmtqP
z4DbDZT2Qd7wNz9X9ovC63N3eOTnesJBK0epYHMfGjTvk5X/bJZ2Ye0Reev+ygzmt4E/VRPKLPja
/3A8iTleKgbr/+uUz2kTN2aIw1QcmIP92kgnldFTSNbhHjjspeiOGUY2ofyOLTuBNYsUl2Gj105t
Tk5bUbWtMVfCdp1UH1N2CBXKOyA9FeA7TQpzzjlvXbAq6t43IMh0K6oxu3ko6cPtADY3IjGkV247
MPfxlpsSb7WlvNah6m9k62tnXvTlErqdd6wcAHrHDsNvTJX2AKsGyYdN8VbQuqr4Ewe0A/J4R1l8
7VItf4E0MXfcBWqtgGdcsUvzbRqZ4awsI4FZR6E8Ipr790Voys9cHBxiC4U/wNPLmvS/NepFZLlX
j5evY7dt58FcxsozT2IDj+7sAy9L6IfFpdMc9U1qQUS1W4+ETRqVLzKiy0V7ziTEDS5SQJDbQBA2
dmpxnfRo8KOMILb0i7r1xG3kC5M8NsRoSn41sNfZA6g9Hz5DDEDOLYxx0qso47MuA7auDsKgkiEC
mppAJrFZG1DrzD1iLHd7q/iae5Fh5tXYlg6nYaDt2xauVo9/ivAlnxk5Y/ZDkOMOBftD2sTnVaCr
+5QJIs4E3TFyttgwiwMOJERFl62EwyoNK6D5//avIVO9JS3hv1QIM9OCSjiHHuxr3kURB4p1G8AX
TLVgpQxnCGcs56LJKEOpFg1pc7bnL8gzBGA299/78kY0EMazTNF8FPFYitMbPI/E5KzYvojdK3Ry
lFuUokUQcQVxkyu3/N8cdzpQeZtAdkPu/UI18KrN+32DDb+OdG3wEDyFvdZXzqsZW2H7b/sDkZAW
dcFR9BGzDLO/tjDJeS7PjST6GX3R0EpmwceBftBjRQc4dLb/uR0j2uufSTjrpLNdNkyTLjwLxyuB
TAzSsixYz+9mruvH2G/CooVKxY27G7xEtixDPlmZZF3xnQXItne3u4asczFlxeToxtrqm1b1WiMc
aXbCcSKBLd9tk6uv88NeLc3JBdLe+ZHKkwuSyHQ0KtuGhqOLsh7JcB78jjYJSUbmK+3YEf/50UO6
SAVKod4veK3bBWFFY8ThwJeRg1jkQRQludVyKDCgEzAo2dCKABFMFcdj0DHNRv7bEG7kVMgHsifI
9Vbv7UQAbRNuFSxFVgaWEaKYsghqb5iso2twn7QnRQNI8gMIDNOH2gXy69GbCd2ptz1YfEbjbDtF
ji/0rVxmGNBDcQL0eq4rnqtwSrCtgJP7FVW6SVoyl++HDzRumEDufmceGTrQyDfYCGyWNwfXJI29
ZFhTjJkS6yfBPMsQdKHJlbc0GWtb4rdxIBvbvNaZ5WvLiHbjUAZbbYaro7BHTLRYPsw+5hIJiHEr
we/mH78dOwZpk3oj794stTBIqzivv6H6qn0uKFJUfC/MZNeXUmuC1RpNsa41/jfQsbCB5c/QHd6l
TMF5lbPV6n+1zk96DvaR4ixNdDIvNp1Jq5YDi3tnZez/DhpOBujNgaJWmaZ2OtNQSjWerdkoTj5q
6G0k4HfsvHyFcC9v73gXfUgmRkOJGDZm4UZ8F9M4NQ0Sj4YRTok7ISybRdWPrWp/ELR80tROzZf4
lOPfZ4y7und2ScvFU87BMQst2PqBELZX+3uaArUWrIoiusP7tlntOUIep3HiomHm3G++2tRETB5o
vI+KJgF/v3ffZ+q0zjX3h9+ZK/WLAGAlPNS8go/3ZmxcG1TLhR6TRG5i8US6vWxVf24GTEIctPlF
UrIkiM8Zn/JABdcgBjhIboTpdedPkTm+rzw/4XgaJn6k1PUSaBxKaisyLftdmGRtVf8LyZb82Ql4
56sgUX/FD/jRxjh9lJfsBOptGTFcGWpjzYm1M7avvTY0BukCgfxs1j3WxBHRxvU2cLjGmKARSmeb
mZILSNBPz+xBy8p1eViVXDRsVChZLydThd75ZMsyg80xZ/jmB6AATuGNfIPTXMC7VoBGJ9WxXEYf
DJEv5rLOuO1VfCMibczpQx7AjmkvVSvvp9FFQ+KvpbbFcoDnFQEekoq/JDkC+HZawW6sy7jXoTe1
xHVJDx63Eor3hXBSqtJ7pCslQ3ick/T0l3eu8HnqyEf0q50hBm3Z9ciKx/2VD/fcGQ9YQ4BbqF/k
PBa629Shv7RH/zb9MA1McHmltRp/shMPNXBjIzL97zZokEql0hDdNocJPdHO0vHeQQh9Wkqy8jHe
iMJaGjQR5sOWYrl48ApqlarY6PNcfucd0CoUFxmirBbzugbG6HCmc2kgdoPRSRDSzOdJyK/lxr+b
FhB6SRlJTv+Fg7h+slt89Ti3nxQ+9RXBlmOT38g28bgpl/Le1O6bA7WkuA6/B8nbxz/GIZgp9HG0
669woEpeZHnBMkNE1nU+GFRp06o4tJFnnUgYfaZdz7qT7mxr5sfqUh83YQ5NxyV/bJAGe1pkp9+P
ZRIEo4lLOzvLQYWOgSp1a9hfMFJvYzA9QmnzlabWhdhY+tuMqd8i4p7CtyWMJenl1jur3AJxw6dV
7u9dhzjStGQ5h/BF+4IQsSz69PCeXLgLEONNubqq8osTBsASA5xffO9B9oCejlKyTZwif8/Vm5o2
be7P2V5BFFXDPij37TCFFRLUF0PoiYQ33eJWjOPejMAyA9XVWWdETGDcGI2ubnSSpAumVxcWrrCW
NatteSkNXc2F6BJ4CmavBmwT/imSfSxvp3vDRV3Q1f2hSo29ITIrYj46mgldpeliauSxlgUBgtUA
QVC0g/yYE26+/NzU/89enPD4s9wuvgtb+nmEftK66G5tC+BKxMSFUFo57+uJ75lxqgIq0ffjpsr4
/JypexO600rw8Mtw/pAtuFehcYKnXvDvS+glOGoXQESpt/rkd11sezthbZAmQgZhO/jrQKezCy2z
W/Ao83peGv5kSGBddqWcaTHGDpV6ai6l82LYyIdmfcFvCHhN8s7pQBH9+Fe2d4JyJi3Kc89UovOF
h3PrANuvUPWB7httLe7S6qOFv6RLtPHQyUE3Rad0A8QDCsK3KcDlapL6w0pyQRv7GJhxMMFRSb/G
qPbrL7FlE54wr0wb4Nm6tT/9T0vZfFRF59R+hus4pA0SPI9C9/2mcLSA2kFyQcNWWssqYdI8Ip/c
Vw1o3ZUnmWdgMFUuoPXhjaJJC16EaLO+gYqse/kieuC2vkcnv7KViRLwnQkVXWJyJEZkA2V1UNJ1
vCWfMIeiNd8HcpL/6f9y7MxhvXodPBtM1rvU1S6W8yOX7esdNhuBSaEqnN1zqTfEn/W8aj/gb305
u4QBpkZkhViWZ//1Gu29WWlXsV8jMNgOOm2l0NcWj7yLJz/DZsFGT44hQ6CdxemVqn63wL/E4tnE
d54cleJKBQ0RGFtAFxeRRN5bF0xO1EI8r92hov9TPATj0Lx5TX8nJHWfI7UxDbjzRblW4rl7Fc2f
TU5o8HnvTmaadk9W4asBv1btIOf+hc1hxThQyM+mMoErP1UkGvkIEj3NFgvdZI2+RUdomgfl/myS
WA8Vmd8qlfA8cudFtchthupVFseGn6ONo/SZ1n7n/qy/6rvgUX2PBNLgdw/Gi40LE2PrZRFWnaLz
5WT02KlXc7CL5gKPQ/6KpMqQMY0xYa1SZlkUMAUKFY1dU+qw4BRFrYUokyberEjeK5v21tDqEptu
YuneVm2v0UOf17qiAzYhM1Zs7KKKD8X8SGiJh1/7sOezXRbBXm7UsIb0COCbFO0bLEbyrrbjcV56
b6JCnznUyb/lB4YiIuG6IWcRQe9m4vjSYKjvtOsBo8m4y6M5O7z/Uvsfg9gNLd6c+V90iuTmpvnM
qZb7n7ml5nQ5BsOrOLJf7VrvCxz7ZZYcAJ+/9qM0WU2mupg8xrYRErSLGqAlgA9yd562edAPmOC3
6nfEqDdSSCJ3oRwsx/fjxMtLXNpoppwY7lm74LGkPEA5OfRwUTaw5kPqZQ3TRcG11K7n8vQzsDcq
B38ByH/JWgFy+2APRDshzmUJsiDwBdEar27aE+tvKGa/65A+2VOewSKxbkBCB4iO10Fq3AyPti1H
FEy4Z77+EuKQfleZE1kgP3+Qamn62Yjm4bMysOd0+/fh3x4UoQeZcVZhQkfhqhwe/ums37vptSxB
iyfzLCEKBCRdf6yYiH5TrSAjrXfBQ2H15m/fixmtKPdK0tb8pgiIo/MqZPl+G42c8li59j8RiEoy
bLruNCAB4fJLbSNRCHWoJ0hWzcx3M+XdKUshXPUzmw3Q1MjmLhOGCYDpDeHPGNANBOFPHn/XOdno
vK6BgmEnWq04Y7PwwML+FO6pxXYLlDo9fte+Ucs0sgTcaJPkar77JKvx9LcY94/CmN2LpDdXi1RI
d1ai3O/fRvnJLnfDszcyAVgNQ+hh27ro8s69F2udcU6thc9v2qBmublZ63QqY2OmWcp01yNO44Jr
3uA9CmunkHcnSu/2d1R274xjUScY4jP9egXsxY0UwBTqu+Z1tYeshDjS+JSSkC9O4+H4JB3lOf/k
P7Fp0IzwRmIpOUf85ROfYOB7f31bZoNfKdiaOV5dZ3IpkmhBFb8AXE17hHmx65v5XB8MYskxTpbc
+QWezfrnbHjyB8xYnnYxt+Z3+ihHVzT2svoOd/y2LvqnjgRC3ll+5NZbeFp3djOCKwleEIHIhvtU
3T/9GnEZz9nN9amWce2LKBQdZhkCxCFYv80nzfW4SiQ5sjkG9//kfpVbzfNKgsJ70wu9SoY2DXwA
3A/v0o5gVt4EvuCuRQe45H7mqBqziq79IZKTZkgp3+NIaW8vxU3Bgqos5/67ccKTtTy8g/gVS/zz
TcZ2mPbHN28jOH8UYg6MkG73XG3HeQH5RScYk9ubO1pyjAVopJAxLPOMpe1Ger+sCyI19eMOASOF
Irdxyu+hJ2toyqJZXlqTMIQXYAzo/9Peqd53ngZafLIndu01a3xBqWQ+2rU+o5Pi2iZaiOQSKYDy
4tnDUjcK1o3y2f8B1nLT0uTD1d6KIbVhk2aEhM3LbdftkpTUGstMTYEZTlP2/VKp+U/j/DJLDiJP
fXXESEYSFuSjmnvskWr4Dq5Bsvh2EjeQS2gP4wyCKmFYFVKcaDjm5oGesu+t5gZfpUW82AOnpP8X
tTyFWV52rsuCt5H3whH10cCRxakvoue3XIMVmRiNSPOIeD6hX3Jku7my/VlO0D9VHC3rrDkn7Z+B
9gh/aYVRBWAlp+e7soQM50O1XQlO/EED3qKEgELXTPcSFQdxTF9JOvlZKBw6ZDOT+Im7CrrBs821
Yx6RnYauI8g3f043D35XJx26riuM47z0qcgYszMwT8fXcJB6WaVdOSeaNTFRG9/puOqq1114r7Hx
ayofNw+9VwV9s1Vvi90lkPCAI+YCNfETk2rRJZiKyr2oMhMkobMDEmggQeT5rFYn7GDeqkvLQdtz
o4sReTSuG8fyfn09VS1V3hjJd6q4tKgLoxiQEmn/zri1iBVygTyXhXJA9PSgbi13TjLiPozyI+Cc
XdqnFXBz9lFZQQ0eBzmbxJrw4RYvxQHKvFeni6Pu3X7lux2oJgBxvvbwRbxH9I0Pm2bczYhbL0d/
JTXFuaeHa7H/3cAZDKRwS/0bu5waSa+ki1JueO5qkksncLvnedvgXGPlKGkJypW1d9zpkV3FZRGd
WpVSPoi1ls+HXjdagZu9WhdQ2N2BiZA7Ea02yTHDnF6SK4WaE1yAI3wC9wt4PgR/PCJuwdTakW9c
jo/HtZ0FscXsuUKpdZL1ezEuIHhSKi3SLj1+Aw1ouN8lOk90wBNUt/i2yWM5XORV4rBaKBCdZ4rL
nHoUsXz95Nnlrs2/Z5KJhujQVGleZLcYoZZbMoLKQYmc/bs16/u7ASpIdVPZG5WeLFQ4hGqnI2W5
5+LuffagKXqmged2BPBEWw4ckhbGJbPy5834v+atGiYpTNE9Pm6nMY3cDEhfKEPp1hAefKsPOaNB
wsRxPBVRJnUokKIf4WYsQrw4iyz//aR0k33WNdkq9HrPrqpbsGBHReVD/DLPtMhu6bOivFZRc9nn
g6LI8epmNgo5wJ7YdtJMpyVzkWKfwYyBbSe2b6kHUG2YABfqHov/AawcwWxv6D0ZClEfRxgcjHPz
2Ew0mZuZLHLPPh7swwibmv0U86EQnv/S6pFQTLe1//WfZSitZqrI4+q9k9GSuTNzYk/heAMsCg91
J61Fhjo/IDpHQfoMXhzRbOD7z3qbMbYknBGzkKdT+2UAR2rvBk1KyIB1uuexOjDwhrgt3udh21Uo
sC1nTnipLBPxnHI0NKPTB/RaIf5hZSbElmjrYy7Oc3Tci/uxnhd/VGi9gMEG3gCa/7lXPCFc6FzI
47TvK+XG6a1TJdpkovJc27UU602AEGrCPhydbzMwxfBr531HhbSzqC0u6terp/DW7vrwIja6aL5G
zqPxY24GM2TEEs9v138ny3OdnIGqChuEOA8Vy3QFYBH42/0GA3f6piySR0Lrtf40i/2ho+iQnXJ7
um2NbLWPLj6dpDTSp6Nd9bv9RSgo7t6uNDP+41uEhs1ppHgCF7S1kI+rcHoX+HwTB5gp6vjWlSyj
Kr80exkNXMWSeLYaGO2lhn43UVMZl5+3qXmGuYLdFCvfwiixbSG2fCBbcN6kep+kR+ZQw4vvGtKG
SM636vYhKLilNezww7sRxtrXtBQZj4Ou7NuUpbYFJxMZxTv2DmE8ghm9LL8FTfwB8glWDFXEt1Dh
Jzw6qrAtH73P0yu0XOjXYrRfwvfCKi4xP5Mj39r8x8A0myR9NiwjRWKR8tQsvf863AGREzoMmzFW
stlB1uWNRRh2ttSA2ZD548h9d1jbly6ENftNcuZlijhAp0H9DzAl3KYZWE0cEHeWlMX1qhaVDpTp
0fb3Xc8CMPnGgD/Vl4p99Cn2Eq2nJ1Uwi9j8dYB6eQJBXDpUsHFAC0tirq0OciDe97mypZ70CCxm
1w5hBNVD8MIBKrSc4a5j673t45VoxKtl7VG1/OqM9omZueM7Y/0KSnXNS1kRMpv0gsGsa0riEIDS
0YRQFKNp00eK4sYFr5NbZP6hPQLXrClP2TvXAXWUGy/s1zywulIfiaqWppkXkJsRoepmAW2rn0Ef
X36wZyXomN4lnBYKxcF3vRJg+4AHrcaaojSJqvsXWvEKs7Hj+B22nN1+BXo90fmKQQNoJESPZCvk
HGTMjR0mEXmeNHeyk5gwMGF8FP4Mej8ws7+rs6iXQNNclqcJNWr6tqWugt1UkZrjX3U9YMBz3EMn
e38Vt/nF4bws422W0C2wEq4ABxWgOwp5+juB49kA9SOFYzkJSfBXAfaXV5+P8FSKplXNpxh4CzVD
uM2yPgx4f0GDA4Rx7r4vJpAjS83f5mehqU/pwZo06+xc53YKLvquiFm+0Csi8OsbcoBww8tLsKJM
cQxbYChiWHE2v0QAEuBRoIhHUO2PA7SLdNY/jPQ5dRuUaFkaQKQ0YhdTmX3zaf51pcmaYWM8AqFl
rVcaG7FgJ+8iOWvID2n0w17Wc7GPULssz/15ftuSAeFdJAKh8HYVpvIZg0ln1Ce0xxivR9d2wrcc
IpcN8DcQVOeNYrWzcrq9WsNcbzp+a0yLz4OQjqLHyqnqSMeFmWI2r8RnHZGpTdXCl7GVfECor9MU
ZjyYAGyupBNQ6CWfCtrHC/rcNnTNnR3aGefv5rKTHTV6xyLaTJvTAIgnpi9DamJoZ9WSuefUxDrS
+oFg/hABaHXl1A6IDc71KoXakJAf+1qVmvuPdlZNQ8AuhHiJVhFEnCSAjtdxt6mRB1Ymxj7ViNS3
2Ue/kNdpls+r5ps+ohO25JQ/vOf9rewGgSrfMcrD1TGsjjFxsWmP0NOFgwLp6/e0vDPKP8aIkN6F
o4xl7TST/GQJHP8IY/C2Jxu0eWbrmY4YaGnOy3GPIKha/leM3KD4DAJE/CVOOOCKLFs5vuAEStAb
LGtn0vcuPepKuOU/dYJehvfSPHtBuHqAsVUGBBGL6Wd8AP+KUTye87g2EylECn2agywXJgWtLp3s
pntgcBRPKF0nDBhsIn1BrLSrxF+9qBYmbohjHJJG16p2u1wIBThF/aePFJ/befCuVXUQ8rbpkubC
tsFKHorxaeEucx9YyBjwKY0BII6FhVJxAnNHb1/YlG5ABrozQQBzWv4s96m4/Bp0idFnFB3EmxUE
/kyqycH0NrqFkOszBXVSYGqF0+glvJhObXNScrA1884P9OVwoUAzLhbz2nXO0W2NFebijeFQvRrC
xztiTUao8Xjh8aFxJzeWUNbwv/iTeSiAgQGxiTPO/CY1duYbViYMdHGfLaowePFF7OhAmDDBbblq
upxxq1z5j9wkGTM4SUgz1t/7TojxJ99WpA28qMyIlNY/Jd3BPZbFUIw/gp+dwkBM5t9tvQn82knW
QRXQE8d1Kjoh0oaqqevISyQK4O5Y2I85qm2jdVunIqTJu71wgPpOjLZt1J6ndZ4WfBOrLp8piWu5
bk0hAH49vkBVmfDq9q9DShI97vNsAmCPL7ot3cW/Yqp0mOjeLTM2LwZSNKsq1jSkelCW5wPD0LkD
Sp1zuiusQsq/yoEbTZ0YBdkITqdMiR0KgG+OoDxDyVaD/XK4T5NmJlpRXtzLcZj6STD2ALdmMKZa
DHRxgRULLFwwn4KgGBQZfkottAPh0IrDNzSG7mdXq39O4STXV9aXTQcRmCa+ZLyTXYcCeoHNLvKE
navbC5S+xH1+YsHFbm0mhNNvyp0XcC85OrHxST7h3ltxJKiaLjIhEcvW7J9q8CnDI42xHshZULn7
iYf8U1oBJgO0l3tHVtdOXma1sQvpojqkWQGum+cRH9tUwgY9QiI9kl+5dmrKne/2DgOjsLwGzEFJ
1LfkYAQAA6KfvnYMFKr+k+fgy2CHvOfnCSylixuIY3ZQ5MaIbSbjiOmcUzzqjJ+MT3EA0pLbuWAM
MWpF4kV2N6CCzdH+e/YFk/qa/m4rnBsNS4KLBE/BOjNYozI9bMMfDEVxxHf4pX2G6+7z/usa8qBZ
LfwcUSXw/dX+Y/qR/tP8WDLL5pnwAgquNUQSnua/WDU3Mzw6LWIS2wmjlKGdJFND4tHw+9lFk4W/
yR9vgCgr2knVv33KXozjWD8SMlaRCeaVBKtTOXbfSkTXTkDP7ojpmu7V6xrdRAGzs+oik9Fp8RsX
ECmYHyXeCWbkKlCLTf5JAYI6V9patZuUUGscFqn7SEUMfZAygH7IMk7N839tf8LsAfXpavAljgIA
Lq25GQbKyAG3c4LZ904fegA5n/2QEiiCxTP/kPPy+Z+IIOJ2F9p52zj4QDIoK/SAsM00uNF/r8K4
5x5GPgCZiqgcAoPDrwy94FZbFJI+NnCVdIbmNCJudC27txhMFwUdRUpI3rxEzFufRUat4dXInlyA
pXcWPA9GEH8BA0XudbYcomyi+0mIT1k7TJ5kfsxf47igD86luc2wmt3TfAYovOlBVMOd/MzGkKAG
fL3IY936l4J1FIqgt4QmQRS/Wp15u72X0b4IM3rfXgz+hLm16RZedB64ltG3fyO9mZ1DmVHyThVL
LItRhI9grGXyboks/BozhzpZS7Iu4J6WCBF//AOvd8qUys2R3yQQX9aoRoYzV+mLWpi53psH6O2g
I1fSlag4EC+VT+zz2xnhpFWm0oXMfl/8NKR2l+kwDkvdz/n2ggvZxRxaLkd/LNVt6h9SDy1WoBXb
Gqp/R7t/nq16gsvBigJwlms4dmrtdQS1DNNnzRz7voySomCIFUazXpdZZD44lC7Jnih5teZLXPK6
9NMT7r4hLjuI3f7bqKeI7zIHsm9pxcm0KhMAMM7/qyzjQCvwAmvDo2A7k4tx5L4lFyaIjjros6Tv
eiAbJH2d4G+HVcEoQh84iDKsw2s4NiPiZSLNPSzrPzNu/44vylvh5OhIgbKN+E6BDkaCtQJv0uHW
RzXYqe+BA544hC+05NOrMerkQpMM6ERdohgBWwhLKMOj6xw9diy4hZrGaqfv/SLhQjPgSberRGeW
y/sT/SHhygqwrxmCEwygEO/Zb4fEfFJwdcedhHwSQkCB+ZdUYTwTQspXfvGg/F9UD9+KrotNZeT4
QttA80z+XKkWJSPNU7++4wrWw0hmWRmYJZtS1G+t5XkFM8FeovlO6ro/p+amoS9aQ4Tk7jilZTQD
IkoFyI4xQCHKyaZM388b4ASSDrxbVaXwk4bw8H/f5mgs8WOqVtfd+9F/GNFfhIsnVVLF5QxBq60F
jUZDr125cBUVE/z3OT1kogGMTjWJfDhTArHSD6PqdQf7wy594zcTZUfd5q+9aOKSgmhU6+Kmj7SK
eQCAKV7fqj7t9n+IfQ2BmvARuLF6J8cvmSYEKgtDhoto45QOQ9cziVnmleHe8qTLAXxB2HwnVePO
Ixx72E9o10EehZwqat2JM7uG/U2kej3dHauYJbeGbOFfn4MiY3JKaD9hcZfC3p3EWc0Bp1VZCXz6
fd94ZJEit/j03FzEU4nxLCiJxNZlN/M1stBtU1WkTtXDTt0Hy1xa1BONK61Ey8gj/qv7cJf92WsD
1WYNC7j+jTms276HLGQ6u9bbvCuDUluTgQyVXli1D5td634yjGBX65TTzO12WG5hNDYB4zty3BgY
tl0M11Sm1mvatlJJRqCHwUC+iSA87seSUlZrNf+UXvBuLETK2W0Hwtz5IlIJs22qSHQgPxa+JoHA
d/nUj3cIaPyViHuHMbG4nMXy5TmG7Sw8rYNDZdhCrcdXRtd8YBi9pxLr1STScTFEqFRaD2jm5VwU
s86Nf3ANYAa9SH3gbbixRBnwi7XNfrhNPbsQV0ziuATLNz9i9F6gWiksw3yYqo8ZDD9QF5/P6enY
/8EkaM02CHYButDfxS6tDnU6ea7eh8lrGFqG6uhPt5IjObJprTX4f2HIzLMtUp898nDHyPtqTVfW
UNBkNSB7bpRQUG6SP3+G1fQZnBV0nrFx21LQ1gynvf3n4rlSPDdGSGCz3XSSwudMKAEgGVUvIygO
9RIGBrlbqHw0OrXpw7KqlWvKevIRJtb1O1oWSMpjdDnwxceTDmj64Qfbgqjrqh8e6g42axHXP2AT
2vB7Od+uoBg5uef6saBuBfejkZnpALqE8dY7AbID0KUbjiwkmQIylYxujkkyrNBCFVEbntcFeg1w
tC00hEyKxZq2Z72T+T2McG8CoaFZVWCUt2iOPTVgp0d9WFCT1RctEgLcGHz5g6Z7ZzVZmXPz0s5Z
mFZ8Q20+WwE16aH2r9BKUHX+zbcXh/WEfdGtAAN/uGK5TdyDOk7i4UfnUlgV3IV6VdLsenXjNGfO
qeCe2JiYjSdHeRIwxel2y2o5egZ/OgoSrAX4P4aZrM1LZkMjIOWQ/vTm2wHUEZYvleAC2BAJtTzU
suFoBp/JdHIySOeeT1fkZDUKOdUBH+0R3Vvd4Pz9n2pMv8GtNdmj46NQeRQcQSDjsGuQt6BDTGpV
VMJdnkUb5M+oEp/4D9BfhFYksrjmcbWsUvMkCK1vZY0VYjz5nNT4gN9+RTzrvQ92OOM9PAOBZhTi
JcvohjfuWY6TXFdVCbnmFu9Y5fO2Cyx5uXEfJu1/Y65HuJ/3MhHJz6at2Sbkl834l9/hWpVz2vcP
C5pT5GCObX0MPuVEeFvw8cAO6W3E4idHZCsNTpW/pgQvNG6ynGD+vshDuMu62VppC/02gjA3+rQs
1gkxOgKOV3mzlqgTHeP1iTKeB6XYb3Id2WLgpMmLPWBPVIVA00vI25mq9C/RdDB9X+613rtSS0zU
yvfiv5bDBlhHC+ovQkA1Dz0ApSGJSIb0FD1BCwDHnfcvYtDcVuscqkc4jFyDh1H0IGtN/tLFWMKn
dhaghcpSz4riTUfF0rj82LAkXSxttx/vd8Vg+qNISu1d0P5fB6SbLBLQGWBDbxYRi2tPSPU5wxsx
NTmjrsGY9djMrOL+gWmwaujFKpZlEw+Gn8eqA0lnGAvGkEDpT8cdc7ksHbk9CdeHZxUL8mSy++ei
F4tBp1+6lcffbM8BUYuqeyuOutJnCnWxc5HmipWRVNGNekgzNo8ZQD8Uh8F80rxmqAUDf6Czkpu+
ha6VtRLvIZgsiXAvKkVXPImk+aATGbW7YQ70I4qtvh6W/tD9c8758y/i+AJ2X91HkSP7c+poH8sq
t9M0czzkF3rD7kEh86xBs1E/U33l+se4rEKu0WKd9dHUMqrnmb32d0DD/3baF5KMBoqHulUCiyyi
SM8fm1qeqW8OzTXZhS0otUMga79Fz4MY0KhkrIZasPXmNSl9R8U/lqHWi6QbWswXpYxJ6siyebaJ
N33Es8dHBQekrLDta0UHBe39o3i3WbT+Yob50sNpszHjiMMTPHV491EwEa5TaeTVfZINGAlocgq2
uEvIPYAa02Ch9j5Ue0pyHsseFflUDvWZYuNwjOWJFZkTymgvcVaMU7fw17ngARZY+Az9PEsz/nVZ
d5lFd4qL8RhFZ3IvaGYXQJLxXgsnBHrskKnyJr6qhZ/mP7FqNEoGrhKSPn3nsN3oG/V0nnwRbrGU
7oD4kfD4ViKTYpOF3YLRrUwM03VNpd8IRraEv7pe4hVUHaxEtsXndJwxCmCvELlOZGRDuLu5D45C
J22pV1EdZYxFQAhGYffzaXJ/2z4k+98WpcO/Yej/a+uCn3nstLg8PvvjjDJjuvaCbnvF6ya2jCEC
rovXQpC6OsxWV/dvH7nhP/Me/Rg2vAedcbVmmoqkauGNM4BXtc96KU6UCHnUIoAVmC8EQDJVOi83
GVAJMCezkvOd4cb9r5kUTQxPjEzZl3eeHt5Bsg9LuzfhCjUMstQP16UaFNFAmXQ+0+3iobTqObzR
a+AnoRJWzCuUvn+9LoLWDH3op7pNLWTLZpMT/Vpy/enpB27NKcvzRnI9u3S83fAqf2zg0pyGRnj9
k/YcDOnDYW9E79Zc2uNaPrgLimEGFUcyLhN7cobhAg3mXo2CkffaXC1cjuH9HkTt2hDr97mxhE57
vbGyQK3LnIfiSBsXp1yPfJbxcstr3CdpJFebLnfZA1yJG+Z0StHK5K8rhnlpg2eVPP5XsjKxadb0
vCSXozU/uDr/b2NQNcTKEuOfh8/COERgkC/pXbeyEDa2fEehSnBUTel9Z9e8+edNu2bkw3ULRiXW
oIt9Bxek1KNdZla1BPlJVxJevFGXc8jEcamrLv5jNlE+OTrp6O0WTtKwSEFDssloqSXBiC3fFWw6
xGejWw7ZMkSTtw95IGeGRtwUkShdQbjkQyQ0VPOxHWXUUwnOgifl1wbDkOEJ80pw4A8zHuE4Omcf
tfPQ/3d5+v/UnNFw6BLVGpg4YTgJg26/zX6N6tDkI3qilTZSzfC2AFonGBMvmeIX6uVaEEBizev0
ffiKSFjL/eddqYxx4e249xvxGAMswGqcvMObrkRHvRmennzo2i/gCojyNkRFB0ayH0rsH5I/+kxM
8LMeQfPXeveGmTdsoy3x6JeRlgrK6ySrFTP+ZunNYckvLgP4qDT18LPyo8Nj/M88CBQTwLafvE/Y
qHzpZnC7P6rIYwWsqCQxGzfSxGQkbz5RscDqVMFcFXsrSmWefmQdepdesWtT2Ks4hFU/fJBA0Vxc
TznX9F/AyWJbtDELxJbqHCQ1MYa1SLsPolpabh/vMBNhZSyfup864YFMLrIVDnWsI2QqtQT2Mc9y
vzBKSl8yp50nLFGo9Ew+f8fvDi0qcZbdoC+CqL0JZPhN8gIweshVsTEev5i06bHjbTYkkMrqIVJj
YwTQcwJHzYjxGtkPZhurKErdDu3iNmkVsY8ieUF/z43QdJC272zaaHkGp53kSfC8zoWBv0LWKlnn
4R3ytJmr4vx1D2CGX5ceKSD1bdpR9Oew9G8FTRFG08w4RYt23Xkt72UOiDkdXxuBcAF4mFVFCTqw
i20G4LMEJ5WOPY3EJN+GZtCbUJHHAWf1nDAj/tU8jGxadi77mGWr7RUxS8jZ/BGyWUboD68vCg4f
ntDrEtcvbySpGhO71mz75G4lENrFOCAALb0jJSiMgbIMQgIQtDDaTYogZg66pYfp6qttF1BIeiMR
JVW0k4orpui2JloQeAumzdRtGgFLM6Ysebycu3izxccysf8F5d+k1D7bHukm6a3e30XX5518Ig+T
ZnwQXhY04lZ1kaz6PkbY+zZkqOZjxrx7fr9RJZbpr21RSoXqOjOVClQQVdnCFRlo+GIih2V87PfD
DB6S+9YRqAQyzalxgPphTZrKPdTJIZ8ugyWTasb9orGhtpH9fxWym5nU7fD3hhyrOJ3FKsYGTVo0
J/KjHbQ1MCK/ULjcL1XxN7pPcVlii8jSP9OpRcRZfv9xHJ54pNkVceRfKGjHLMGVYvwc1gJqLNEF
nxLWdMnCTNyGcK9lvDWgWCk1OmM3zsgCJl/4szap/1smGTbyCiJRLrZ5m7fAMmGrSMT+93TDSKmu
Se7jFiF1o+hH2DIXr8fNTpXoKdDP7A0zCpq5nnBxP7DUmTcCS4VQTxjPujlReWS6UEXDQ0gujy/H
jbg9C1/fs9hY6WAd1GWiBit4jh7DGqnWeIgsNWXTNsdfujHrtyzXCICEkBrxlFd19zC3JLl2Jooj
s/zYr29boiO9YxgfKLRCHh5/0OE3N3oKEYxZ/uwDjZbdancehP5yn79N2XLPPb1TEG94jZP+6ml/
2zqktBeeGN7R38L/ZNe7Zh0KTd49tEiuzCOo+Jg14MNMxcSwmxJmdiQjADQpM6bkI+qLFxhXdNQv
1xyCJGZ3CuEvvzmg8qCjZtaiHYpFqdF8/dXmU6Iu0RmTRU2m9mdjE0OwAm/UXnRuIzMHmsuw0OS7
FrOF3PihIUy7qGLBi+lWN/e0JP2YjWOW2+zH29LDTKvU5qxw4YccJT/EeyDOliPRIzFaHMFriLNg
HuLa3xacqpl1wdyiIuAnliCPB5npx85s8A9iTp6IlgatFyR2UYpk8NsRlnptQdPuNWrikcIIPKuG
Z0SidQ5tKu5YrRw4/7pNgHhThP0YWEe8pvjUYB595YxOvg8DxJoTAJHq6ykaXXzTT6Yny+3l+Jfu
N+P/Tjp6b5/mBq9zY4skTVNtbsHd6WLT/SYTqfghBhCtnmCrcyaBuuvmV6ymSxCS0St4VK2FpEFu
5HJFSMTObZXkY9ZFHUhu4AB0+RnUejj1yQqqwadYtpYH5c4Gjrbn5sbFVOxW/LQKmt1itA+E7r2L
ogStHoyuQYfC5bofS69sUimETZAZjEBBj4n14Jh38pGwo5M1dpc4utcN8VY+u/nsysfwxwRH88VC
PBbGRc0GIxGVAMN//XxM9BO81Nf5LwsYTgFB3O3c3YQsatwEketVUlAj/wTXcp1U8Ma6BUj9lgW/
79psNC4eukk9kfXdPCBQqXgnXMt6Ms6L6GgPfAh7QIoAQxWJm/91XPxtZDLnNmdSrSrm3j3/FcK8
7DP/pMgBOWsVhf0K31bI4OdcPtGgwQgL692Whp5Uf9/t4S4VGA8bHwzcfNJ2ToUTISJHdchX36eq
8p6uMkvszRyAJqY3Pt/zcefATbBCZAf0/yVxhK9cLRe8dDTdKMlxE248ecbKx8xboQcu+d3mmG8r
yT2r5TyXNoWILAN6VmdTSOIpWc6JrYMBL6Og7XCfM65d4Th4KmQnKt3Kvd6BM1nwIlfOwLhZFQNS
001P/OWUX4U9NdmhzVbf8J34fg71pgKAekIBYXEcUsCJ/QSD+2mevajA2TJYsGA666xVmPOgXhoZ
9zQilpjocnq2GEDWzfHKr9Z5r5yUnTAdWL/Le8GV09dk+iBPNSdKrakT2FkJWesWtOm1iB0IOeFx
oJiL538cIRWvGqo/z0xp9BpLDgJr75byrVqCiyHy1g+Qn/nr3HtEztylz+rXMqlsotnJqjf14GLO
LanV1CYpGUz7oNyUFRj/oWEIEvWtkPyUtQvRP5GqyzY2gkZZ39DSbeiu70yNCvGyEfYA9T/1YYFa
qyvJyQxMKbbaL2chU1OPbbgrzVEuMZ9u7+jukCPHkoaOuZAHvKGci6WgodpORzbkiwBwtgoJYpM2
3fm01ipL30yaZHvGNluxOpk08kj61tWhttoDL2CaAMBl1ekXfG57Hfk/v2eW/MhGLV1xB8Gb6fz7
IEyOaL0C6YiJlKRLo/ArQm9PCld/AeA9F2stfu7xtYiYMAoOQDS27E3IARXh6SQxC/8oqrlXnjNT
iGmDgiIMcdJplMTm6CSV7QrbX9theuHbby/SnHjB0PQldNbnM2XrDmMr8Vj0TPnpSrWbu28qX/CX
3/Z9UKMTkz0b/IRoPVKZSFL8FfiXCMsD0Zt4nO5YXF1SomUBq4o1Q5WFNBsxmSXvRbtDudAO4ahr
4VaY4i7OcZoQYIIH1/lBw7YdTYqGMpE6Huo+scoOYk3ViM6Cu+gFbLeBkUfztp6D4sGBYS4A7P/D
22TZF0XM9DHpqArkIRjHKRJSayzhdwIjla59ePDyc+Ki/PejIiRMC//PHacP38G0pDorPWQH9zDg
Gpo+jKKvxhFtToXmZ2Cn/qAN62GXwYrF82a9wTH//tTbDBUEM/5EXnk2jbrvK/pAC1WWRgFSj6Ud
g1XneqB5xO+T2sKKOm+xbfWTexM3MVRBt/CJ6zIjV5TVPD6rgeWwWkltIDw7Xj/zlcYBNrc/r+CD
DN9qa/bGbXGOYEGl6w81WbYV11V8wehM5iXbdwL2KdMU3+/Iz5z/WdwveWQxTfHjuJUlvhbGd345
zZN1sdeCCW6CMFQeAYjuM6jwZtHyGlGlMHi4Z7qa8LjnpEs7lL1ZpvzD6eKXfNoYX1LVGG1CPZZ+
UTBfkRx5yuSU53ZX0meGlVaNXwSPzZ/61fig1JMegbBw64wHsQUE8jrEPWSzZ8DndXmGBmEKwQmg
s1y7NzOyJNhy2vvfXpPW7vv/2BM+yTGHorl/zeA8GZQ2HC0VBNPhZ7c13fWe/QTM37QGdp7h0nSk
fkY4snBV7phWhpKj1XUv5bIVE1jghvA7yc51V8LtnxaA1ThU7dPI3lcp46J2zFhl0X53p9DhWK6D
hV1KII05hB8z6B9jem4msl3hmqwd7k99lPyUTRNG8xRw4vBUrX6iBoxJchVAXZiRDXqEDk8V8mZh
4Pfrb0g7OP67YJPrb1Ze0KMSdJkQb+miD6oS8l5nYlnNW/+ctZciZQIDyGRV06dkcdNkj2oQ/Ov3
AfKPSCvkeYUPNy/YDSeN/ETyyF+M1X7MYfSgNY9wRHD6hNWRaITGVVgL9LD3lr6F6j2YXFXrsLzv
3wF7HfiUMUXzi67YeOBaac91coFLUoeuRhAqaQl5A4+rhm0wSH8cYBItl6YIBXUxfwGrGAlc7jW0
9FrBTVr/wBR4nW/VXABjOBNc3c8USaK/KcRmnJlvDOziA+/W31/pVR+cr8M1rgiUmWC+6r7vr6DC
MEryZSC8cxKwGQNKpfNlViehSrkgkjiX3R1v2+AZxrQwqshvyxe6NrYWiNMQ6gpSt1a06uCyE+zH
rMBZ2qGE/zS7BYK+tNsrpP0N3MHOdY34tPpYbJJw9w+cO1rh6Fdabhf8GPTRJ3wUVrzTceb6lurV
ZSbeHyaRco7nfAAW3iPFLNwxw3B0/SkPUAIrngA6im75x1qw21mF2cAO7sRv2AjBS2Hc+0LXmlfO
fR1E1hR+cHAyTCwGHW+6Aw84sZylXBDCFhpsGyvof+LNkkomcZh9sD/jNu651OBweuVdECM32i7x
1rAZttTUkd9D91JhBL45lS/7pNS+m9puoROkHQmDKUf4WOiJtdPKacHJ0P7fiL2G5bUKnfuVr02Y
/6gUVNPQ8KprRylP/oPN0D8U1RtNGf9XUAis5TaL5wPY/MNh4ESNL6Fa3TuStFwPQLwPuRdjqm/p
2SLM2V9DvrWKDhxmmhga4/WdGIooxBA6RmDOgH6vHIVAAebgovJGcFVFI8jh1jxKvuH7l0xuy8rr
gok3iQOYFl43tFcwtKmKjYWp03DTW47Gy2+84E/cfyQXpplbSh1JnLZfIeNtB9v80mdPFKsqyUEg
Hm9kcVKYU8X2cBryTsC92w/pHOAwqRouksrZRIFtPSejrSmQSPgUkiiAntkmLbHRZaI/Ss77atti
s+Vgz5+wVpvHt/AL7xpQc99SvgPIUEtLzBZNsbDa25dFkJoBVMVW7X8XUEoEKYGd1YLCZ8UQ+NQy
UIX3SAnY9JD/Hbzuyx7GxeOdMKq12nspplrWEmMeCorfdd4VOn/jImfbBUa4FHt+XK3CLcY5JCz1
4YeSaupo+tbBrgVJwzUUsNGLyFGKRfJOFMYtW8N5XNV3iEcl+Xq/lr1XJaB8Hf+AFkmxS7yusDsU
lVjDgxAFLf7cHeySJL/WX0aHl7njoN9ou/ujJITTHX4kxnGSZr+0q/5Bcq4Ytd/vyPjnYC8+BW/j
Aaeo6Z1EbSnIXGjCtSRCsihR3Wvhc8aoTO854crdlw1Y1oQ7jAk5ty96ZvFwvaBP5DimHDQvs9YR
tC2UQ+FoSFfjC3uw+DiIbKxrnOX76C9Vfkd9g5r0rLHwGRr1xGeh6GQT64XdJoaA96ADNEzSIpTe
zmXdVWwOHq6RE88lcBNbQtiMsLLLd3kf90aosR4MMCvyEfa+ZcxUqy2BCuHr/AMeb2NlgH/oDFo8
fvrBdWBKbp4E/nki3RBZlwsoUW9Dics7gVZiyLAVav3FQNzMyaPJtSGu38375eh8qPckUe27NxCK
2kBwFn1gvaqtVjBqd/xyIkO7emG7oBU2/r+rLdUAfxflsKCbpi4Nv/rHqgmvwZRaAhPiscrwbBi1
FPBt+StlRZbNlyeCEVG0g45G0dINmp+T+olkSyo5MYO6tiT+ESptE/bnPvpArwRpmLwB1OqaHuq0
e2nDUDPhyf4+CRDOCF6KZ/Lj2jlOtqhVAwWADlP1Uw7XKz2epHlJMJIJrzewQuFSW+hntCtp557a
fbOpVa/5OvAPvuWe1R+/53i+/8+Ip7soKPxmxMGZg90rHexG7QkAiVTRis5buyCz6nFFNAsQIhqe
zEoC4l0Qk7bD/h4kQLFo+464hXD6gRXaILa1vOvuqSdIHohWW+gpHNkZDS3gZ6PoARB2hV56Z666
OI33T5cWE9aldM+1mft0j5d1QmTSx2JDqy/0YxXf3+Q/YkBl4j26qmXmFgOWQvG0h9+RHDAkDgUh
PxI2VrJQVAaGsRlNGhiDhsHj1RzliscbKVZKKE7dESMz2aCKYELKuVv0pCU5amZ/1aOwDGS6iSjS
KWmNsZumxvd/sTCLnTduzFHO2zaUrNmyDUhNwEKuEmKBgbFqG7MgDsdK1lwBc/PofPTMHyHP9NmR
k3FGyxlQrwZIbquc34m10NDMBvb9q8qY+FhDWVukkOvvwkAeDDCHpHBx9KVe5evLPLYl7akYev/9
zPFCwlUNnEkeqaBF1mrG9nOr7LClK/JEtG0z83gnTnI46AgXwYQQi2JID4aPrstxj1qY8wgYNXSN
ImSWnVdWRGr0LsYThicGaYYT5T/K7BnTf4C+0apm1rOHLcyve5MkO6sR943My6q53jT56PbBbVA0
kaUEa/H+ZSjgelbT7tttu8DcFve3n3z/Rk4Ev2Qz3ohgetKs2TxzHrYF3GmUuC8O6/EHshSHBqlC
J51DS/zS9mVFnQR8o1AJRurt8O7NATv3VRqBC1q0Ch6wZ8Sn2CiQIP3Qi31jdiDnKHyLiu3egg40
zG0Fa5iBT7K2O7VAiOlJvVrNXgzRAUgjCqm3qxVo8IaFk0nmD7iLZ/wcyL+/EqXC55cdWznvlVJ4
eFiMs4ZtEdt3LIZOdlVK/02idt/7y1gHV/Km5IpSHRAzIJL97wEoPETs9m0t5H0uTsZ5C8YoVgzO
kdgFH615QWPorsfHgDLyAgdngY6yQzbD0p4tqNIXyg6/l1p1BcGuKPT/yTWn2CRZB/vLal/flh5S
Qxjedwpm5dakwrgkHt766zqdYkOetKsTod4vodI7NXtLjBYE28TAu2F9+23Ew8IRaHDePvCn7RP1
V8RErBPr2YAy8TMrTetzo7OScCixDk4L6flNzWcGcf8c5/KTWGUzAgq+LXWeP+m1wcC+3G8vCaS1
R7SpHbC/SFJBHPPQtdbC2f7YsThL79wg01/QAT/kYw+J1GUuwUg7SYljJT2dtTiHTwsYers53oyi
1NKE79sxNEcMoH/r6PPd4/S9PCbSEXWKNHxhOpKnror1mIIm6Bj/s3J0BfkT+e3C8dN1ke2zhWRL
1PmvdjtCS1qPjGoo0wSltTExqfT2vKV8QZ0NSs+Qr9/N7KQ6vGbH8PWRhqZQoPZxwwRg70/u0ZUS
zsEtF2FddO6tQlIpQpcfKsMt5YiH+X2yAlWae8blkXzhZyUrHKtpgg8ztcAS2df0apoJOjUDopfU
9gySHSza/3BKkMQCzpypmn9S3cpS8fP7ilVJJTpV2l/RlR/J805aQgko/1T8DLloOspsHk3w1Ur4
NNrd/UMfhMngfEIMIpD7Q9CHVe/9UqOZlNZaRk6xQ/tycRlx6V8V9eREVKN7ChpXvRM8iDop79qB
ufLADXdaCEHO9+BdYNUFtMQA+69wroa7vD4lDQSjORj7LO9IbDTGxcTp9zM9LLi4hUxmACIaaKGW
SMlqrtRHj/GtqMa6OrkNWOW1xGjMG5c7uQ7qFi0+DQb8SXagSEQHLVVo1WL1/8HUksu0sEHdbsib
XyTp3vrVy20kAmkeGboz2C5mRhv7twE6HU6RYwUXO4k3RVO7VCPH6SSgMPkKn90C0gKLabBI5jwI
YzMA0Djlxzw1/rXPfjI1qBByP08pFOu1L7n7nKpeqCrOgMKmAi+Zqb4EkZ0GgVchTDTFfUEXdFZw
nGvlegJfaZmPxmraxW8Otet91raqT55sLyBXOHpLUBxCqbnBliBX32W2xDda5Gagwr4AnLPWu+xu
GRHBNbO2NHXMEGyVHxkuSw7E95lSTQJRUKhtB1gnvhs/rKXNW48vwB3Z/v40U1i1zB8gv8Se5HTm
CJK4cB8EAjjGhTuRcEgheRoFQ4laK/ecSRrGhFnfsKXHPyC1ONyS64rcp7dMhyMdrT9fD7NmsZiq
qC8SSHXAE/hE8FhuCTf4G+Ffr0PzgpxVtmkmk9KL3ZoMbiAWHd3jn3zNXNIaSm0I/R0Sf6HWKI+q
gMRgCGLAZdIxrmu6mMAyL866iJWs0k9VkoyX5qTfMq8ix0MxKWNCkUZnyqmADWTJU3XW0yv+3/qc
5AuO+nIX5pNgsr4uKj9dOr7RQa7aEFDiUbPSw+jl+wTwb7btjSqNgQgJN52/56EpWaXV4dAbikp1
TvzqJ6x35dT6XUAJGF9Oh36WBi03pFsgLKHn0iD42SLp8YAABsJhaNTF88dL5RspuKhofyFEz5t2
BsQAskEecZf7VJaKummHXxMrWT8WkC8WRg8cKSMrhmvjMtcG77DWbEVsfRf/P8okVIEsCjo9pzne
vQ7obbr/PtXfG+uDfaX9GXgVlMZje/jdFsrS4I4Ay0myih5mcgZkYW3WRShrh7vaXSTuh6Mt1GSB
ZH3YahunSrFNm5D25sqzK6o+kItLBBsAPkHqJF6uzNcgnWKFAkotq+4JZEuyTS3d3IaMCg/QxhCT
1b531A0Bak6uHaVKAbTR9kIF6vMEr8dmxRVqVYsR6BJR42nCdTY2uixNxiJEZZMcGdYWKU6MqTaR
PCQucOlsXPjGE04l9DRZ924GF6KEeDwBSBvUezKts07ikMXKNuxBITEz6ZhNUKLWqAG5cDILs70Q
sxQAd9ipfU5DYNsSUtrUID++cuMjJpkpOi3OpWK+AJNpz/sOeCBw1TREuMJ7PqSFYUYGiiuAxS7w
1TFA+YvdeUUWfqD0PV7wGZPcvtjTlG5Q0Z2rjdYVMpglE8nNHYecJlcyEO257byureXqYz2isIi3
tGiGQs3zfp9BRmEWEX63q1eD9RxTqGJ9TY5iWENkpMUbI/SPI33JinTRNlk7wcwumDNgUp/q60gs
gYSAOOQBsOgwu4/t1AGzah46SWKd3AmW5IPBb81aQmTqlMDDKdmNUm/B4qJKN80Vv5qb24CM+HSD
0tn6hBcgPKGa8BmMlIbLre+CGHhcitFYxPD55UzCE0IqV9oLPLp4ljd2b2OjuYUP8y4uf8iA7wwY
TRFUpJ3drjiUV9oVuPjNxdh+qY3rHe55GkX/tGSIrWNHqvdz6n1VIbhi4E17xo9QhvPMPxSyx6Id
bRLZ31SOSqN4xJtCfCtEnquArFEf47RVsI8xu4xTnHxGisD5MI+pSfXrTkzNQWV2QwuOVy31maM/
Yq/vaaTh2it0RBin4Ky7h4sfTKxsGmpgSSM7iaUgMAzb5zxOMdchOktJcQ2JHKMsKGb6U4OWPg5s
H6vitSV1AWzdvcMu3X/gcgJ6AbVQj9eH5sm9ZWAYAuQVde5lFk6dytVhvMVzu3r8DGW6quCO+KYL
zE3qfLPtHNzTbG2Y+sTn44GVPlsmTK+8D8jD3//wj/+s+jfEkv6O23TONSCEWegvmQFG1cznPD9X
YeTDB469PEUiGqC91Spj4HGUd3dVO109Sb1DQCSvZbJ9spJv4x68ReZByzKEmWfJ97wpRPurEPpy
S22auJ+a6gZOjXz5MxDFy8AkIeH67Nsda7owxBc9acA4MeyfmCrA1TaZZsjyMt0czvYSSrY1msB3
lfo2SQRkpMseugWHf85WX+FbhKhbCACU3UXKCO6IDRn9nYwgh1UFgZCFsW1A9es1WoZ64PvUD/QQ
IhYo+2VvmKfBO7m17lyMsVfLwt/s/2XSyK/HKdGmU0qNaDh9Q+/5iyKuST+BYWL9glp1xXpwtyEy
+75cjLD04fuloTKoN5bWb+QMiBya0vsX03O9r9xKIkogPZxD2eYsDErKdcPO4P0saQ23Ii2RnpEs
UxARHXSlQCf2Qtl/hXJqPKybyz01DBiPULiBN8fi0Xfls6RjBkDOvMoIeVj5PQ4FAwGhoGg9vgNG
Ry9IGiNqUWJcmpX3+I+96j6im32lo1EmcaHL4gpqx4mpGze0ZRGLYpkbeLDthaGeRQjuw77G0AYE
fbxB896ysgHES5rb6KflVma87r4lhKdLVE5isTOulOAnOLZ3HDJixm6jzECFeNY4V61oV3FxNdRQ
0x+dJk/3Psl6m0a9rExZxi++MyYfYV22dmopDBPzhHxww3Y3PmmXWMzhpnS0IpnyGalHh23R6kDY
i17vK1tshybn4flIDIM1bE4Q8iVQeDt9csSSUCRRQTMLiUYglzX/jcUexRUiXfrOu7t8wRqQL+oz
OnxDqvmZw8O14peNOHGrWdhxZCtM0JgZml2Rjk3d9+6hoac5iDcSJ1k/eFCrWDFTACUp62BgDiRT
ztiTdE/zbwcmgEG6kwM3PD6mrYfGooVxkvAfaffiBavC8z55tNnhgh1ZbdGEm1U1if0mGzictwDx
vyYaUaBpMSrdQMW/LQ3daVHEE0MwcHn0yaaaox9jtgljWkTwolt5XRgr9so+DtPo2xTJKjkCXWRU
Ox8/nDJGpDWIztKDZOrX4fQbRzEI/1/7l7gUb/9qdLQTylfsMb9/T5edoSdIlpLQMZ6MUV8mMdHJ
U+tWOo81COcA/zm6RD4H6L+hu+zdlUvrBaWzLx7oVtZNvhJKXbkGAHvfhQucfHvKrvIB36xNpPyG
yYA1cRW06DF0gp/TEi3H9FoUArDurvZ0HUjK97jBiidqchHdEU0xns18m1/ahQQnSeZpzWWzToZk
NwO8bI6+o4UfipvWxN9qSyAgrejKQSQAJMzUtVdv/toDS08FJUMN59xxzKWK2sRvsSAViaSK46SW
Y8RmxoMOxi23kf2thHOI1Gi1SQECDxR7rtFL+Aosczm1W9u9u7K2NtZ0JudDs0G4Dzk8R0dTEghp
WKXLCbbGgcaA5jRY/Ooe/oGkhv6wu3aQOYIf7ckzwvdZ8tIXYHP0x417nwUu07YZcjLuygfpeIji
R3NpzMP4cIUIE+P+HPFanUGajy1DE7ja5wBIcsFCogDKEJm7PRcrBjD/WcSlaLQMugHtYP47kxIP
KgEq3ptnE3yKMQNwtwpL5Qme/gn91sZZOfTCsFyLELacQP6+YaZQcfPn7mFeIjoG9OMvdYcrg2e2
fQWNhuPtWBrWwJLZv2zCgixNxIJsCcrjGJONfBv8P8iVjct/F/BBrHUj+Fp0SSt2l/d4a7GPHlZ/
hDv/DWlEc7lZk6SSEe310o1R+QgKhsF7I1+HlT7k7G4hemqfvamZoAHMdrtIoxKUPxLLljn2KSV0
iHgISEpCftbF7EUOo5drvZNcLBHqEPUBCx1z17ZcI21PW4LZDhjWrEtSuWuEigHAjQGLv/XXhjsw
gTxotVZikucFz2B0uVQ6Ml5fbAfjNJGf+BR6a4Bny+bLtiBKLY71lQnRwj3251n2+uB419aEIMg/
10LPbdY405LVKgSLe1lVMN9zofjKDRewT43PRvw3KUbcqpevjOO6uPmON5cpLk1BdO4hvjfsv0TP
aGYz4v8J76jX7eUh6kgJN3pBuANCZCyVDvscNZG5KaxHt2LC/cRqnkOM+ibZVpAqzTgwK3casLiE
y8agbpF3y0F7+zfXk0MyjvHhX94T0Vm6WsdhkE0Qbl3asVY2meDpyF+ZjYNahDQr0wnuT/VKosIH
EINkTcgmmOqXpfzqUVFvxZQDBbeWQom+laJy4YSpbwtSAzc7WFnpG+88aTOl7EjC3OlcPdBmEd5R
kDE4zwbZFH5VPUhXWthFS3lEmwlTFG94YQqPFfFrb8qjFdsxA8dwR8R8BCDj4myyXJs8zqRSlIic
FzyW7atzWkm3UFkMoGBVei/TeKMSz8lUJt0voiRkSRhVrRaNQBCW64gK43BXERFvJi15ylwkSbb4
pXCQL5SgpntK93Z6qkAxp8yzW0qv4RJA09YVqs+o7OUlXg1cHn3WkoJ9a9cBJ/aetL3us5IOmfhE
wBnnq59qRDxbeSDtTTr9z6Gh4Yc+G/hasniGI14MHShMBLkD7g7wHbw1rUll1N4Pdfbf1mZeFVKc
1/Kjua/RYx9wl9/XDdnlanfHUnVi+jd0dMXh+EuH5unF4vOMq30iK02YnhjBeJgldv7xTCHlHrGP
4PrloOOKEGm+AGNQu3g600+T66xul0v+trzqyPlibCTWF/r7lCqLxKosdYzGiJsHOH+DmiQtCMOm
apXH2T+e+CmoJy0so2eK8MjQYRbnYN5MnMXspE9Q/3PSeO7nX74luD/SgyAw9CqxWqmkbVgs77vR
kc/Bqv7+YaH8TJnsfTJn83qfjt22wvpJyY3fP+D+a8igDVcxkpB29Bx+I/IheO2AOYOXG8kgwaRP
O906UqQ3xwMJMs7eVj/eR1ejx11ukAJvXI7vKVdWqiNmqKtZJtuXrhJ9kJ5iD6FPl5c8YBx0PONg
6jc9oFmTZ/bnFEkHZoXAuyNSnOMMIvSRpULtrwhxAYfaJ0r/3rUubFGXxap3hmJA1Au0bZffNFS1
bYTfT7apNUUnaL0bSbt6TFchN6NbDtXAeQjc8POtuI9+s294OC2SrPopeJSOOrmtCx1te3NhBxEz
13tBjCw4EjjAxgDel4mj2Lhf8mm15nV/6cL6D6H5n+8nkp1E85lmANm6RuXuc/EpkqT/BNFuw6NG
/PjyoKHR7ur1DEhc6DJB7p+6zl/EQMbaAXD8MJBQpgVJI9yd9yi1w0JHnVY5jv7tjxXSXLrV/rNA
P+lnNKJbbMqbbEs9kJ2GNY0T5saTmB1KHkb8mx1ptCNxCv2rA5qeoDv1pN3+MMmFkUND2m0IkHPk
OigYt89N4l/SK3OvrT8opj8X1Lf/mvveBni1ip0xCrxjw6BDe2Kkb7qLwaHXxCz6KTvVvSkfBdXt
FJPmjiBDYQfz1ZA9TvsulHGPRRr5SY7CiUjuK9HTVWYPP5HMoYAcJzqOJMPoZjwE1EZh3CNJAvsZ
mXR/aTfTaXKprPIwI32gh1c8JR1LH7dlKRpLLf0iWlckhY5ZrDv2kc2Y8T+KEjDlzdeMvv/R5U2c
9J2DhPmGTwngitvZSPjPdxFNnjtaMj3dLJTot2PQP3ae3Ji7hkVxhA02XDkJqOmk156pZyfcN5Gw
NlVecFv7j/LscZQYlD3Wojb2QRc6CT3yPb5xaX6bYOO5Bg/Y1CeotwXdwf+jUlH0maV6p0IncY9e
56rt6Lbf7R9oJPwInTkmiEnd4C5VHXpCubsamEoCyWIZ8biFlYR15bjAGYTJVm6Xhu2Dxxg4FYK/
wbGvWfNsIoXSPHFwj4hxYNAzj6izORiknBi4LZ/33EdVprHVLy2MXfMh2XCAtDVeOYnlLIyUNdZa
865pRmOMcN2k0RIbjyxuaF615h3WRSb0DSEkJZQLFXj91qXjihWI0o5v1qQhgPgCu3am2GxmJeAB
39n4GVYlKCe5I9T422oqrNsZUBbQw6SiUE6n1gtRv2aNsG7EQEXH5aqciK28DeGvDWho4vgyqMi8
DuHdGmLj9/WCXthBoVhBG1fsNRhueCSCYPI3zcDRh7unjdAmaqkw+oUw2s7EXfJwXu+vCNgMhn5D
9n1cArpJfhc7EXsIdVsP9Z1Org4eJLNqOzjPO+d40Mu0FP+G3ThaaKa/mga1OkIsPdkmE56S+AfI
Mt9gxxE+GmDDFyiCFLzpEGeIF+GD0NYJqO/EsrthYeEfLYchjP25eY2txIJHjQosWtbMsEAF9+ae
7dUZdZ9LUWubJ2qkXBrJDxAkhTXMB1HOfn16qp9cwiiig1MgcF6My7w2wUwJGS1w1qa07D28VPwZ
fzK3n3ZD1m3wnclTH1AmoflMebOCWxs5jnK2uSwt62CeWrc+MQScJ9QhLQk8XpistgilHbFEN4xL
TwWHDHZMecWo0tDSHrbycFo7aOVdGqLmd+R5ZfpJsQRGmmO6yai+D1QwzwTTphJNFY0suHuLd0Ln
G5FnTdeNNIvg0I/htm1KnX8irmGFBXOUj/5zcjGoOSXu0GAMh+YzaRcEDDinevRU1YyC49wXazN7
wbOMhWaWyZ561A57Z+ffy82delIRStIZWrgDip6A9O25qDjip0jqJ8j4IBvj0v5poNDu/CFg7mvP
jRDjHY5twGQ7vOfQFyQNyvgUwySpJyAnnI7+jZq9ebHUsFE88poYkMS7VFy6wwO+c1i0UTnmhSZK
XHRqCuHV69292H2Du8R/k73pav05G1hLNIHpNObizW8XAx4p44r8JVcjMIa7bZXOWN/1kR8CTiy6
adN8peDJXAsotDomPE+3ulXusKHMypoW/Q8kO8+1L96YqXcRylF6L2zJBKfWhhyV997DFm/202BW
ahFExFzcqZ5Ro4e+ZOmlr7IEbDDzmdag73W9jiefMHrbAZqbHwfAPHqyiy+77sJXci8Nyzhyaxm8
3Mb2arwfXAgo/aYZ/DgTA1md9ihb4YJjFgTiBAKxNLxQCanxBbNVgCNTAUI2RILfKOqHCkhyibKr
Tja5fbnyZde3saq1PxiP5QcEBk4H5bD06rMIp4PXR9kpE/VT4hznbAlehHsW20u3MSATJ6V8rsFV
lDOJMWEwSB28Syu0pH0dDehnJTLg66GBrLzbPNaDrhSue+lIWgv2FyHdkfJGzm/s1XaiELVQFwHm
LQqn2+PD52ig+7DkOUkqOXD395EIYv8DaMxhAsj4S4lWbSQkxW9nt360gJIEpS3eq1M7A1bk5Z5+
8FC9afiTNUDmkSkCcSsdx+52NQuIjIDLTgmTfrsJ3upzFxeNpbrCuQnJOTjeZvFwo3gKX861idV+
9l48klZObZ0mOGbJp4X8Y3PfIqkZwEZjctOsVQI2Hux5zd3j8nMTTMbjRRpE0h6DoKTlb9Kdobh0
q33GmpQitfPFF6zRWN4DK7EweDKYo7txYwIlJHwfDiyQfntOIdYv2IaOYeoZl8sMKQI0UQbwjuxO
Xbytpvlo5/QpEMjtAv4jPqCtNCOWyIWaZWBE/0halrjfKWcwoOcMppNlurf1xXHtxqbMk0zKn1C/
K9VFAIESgdSXq6AB/Mww7mTwayFE1BtjROl96l31bNaHBRvPI81Zcq+A5DOvr16u2N0GOj7mVpFy
s9EosWkUaoTh8uwvmYvhbq1dm0KVKHdK4+boW9Xuc0sQeyjXAczSkwZ5umdw/AAN8nQgZyjE5t5D
DOattGWFh1+ijAYsBOoEUyAxtnsiilTDpq3aZOYOmEsdy2Q8VAo7viD0Kf6ZLCJ/EmJhcZmXI92T
5oqOwSd4LEIQtwqBvYjpHnZxs6h/DMgmgeniL1QQMabSgruaaezVm/Yj/ZpekMHPLBI8LbVLEfl+
6YHb7lEQoW7BK79UJa+gS0aS7XjMJ4QWrf3ACwB4W2NXjuOse64KKrZww7q/s7PCPQS4XFGEyiiC
KYZuxxbBydz44MHe9JZ3sO5i7dHuADs0wk1vwAFr2++BQ+1fHU9LFjf+VWRbQGoEseeq2iSu9SLT
hk7Hscw5B/58qozzR1DDG/unAklVfSXRMxXr/MiDe/BIHIWJU1/RQ55W+0lwrV6458mCQrBO1FsH
1DW9/kFesdJfwfQuav/uimEpIIjmeftMxV4FHyy8tAudhUYsfzy2eSvRmXlp3cegbcTNNx1GsPmT
14L0BZ+E8wjLi0DK99qtm8C+Cv/bhryFxNOvF8FBovnpYIdTE1va5DjVgZRupLa9Z35mTuVHScjI
8ngITnLw046Kx6VNTFZE+sq+/A3e4cPYq5UZVxNQPI2TOTtpeuvmfDWXxrrRs8cv4Mp3O2UuzuQq
/7Ndgdfvshe4rRIPYMaoJhsWbX156myisP6DhbqkN/Xqip/ZBV+EAvFlt18mZAaDRpcjdVGU0l+7
LK++xAHIIV6QMg+V1foiHCJheZD+8rZq0XoqFI+g++vR55V2+XlYNQVOAHENl4RNnGdGdRgQHH2a
ZHkAJnrocZrgSKBaisOxi0wwmgeHCtsyO1mO9mEjOKJrrzAid0vWn+xtrkkn+dVrAiDAMtK99la1
D1TmTDJVkok3wx9A59XQeBTRyunyyqsxunWu6daEXKkoS6XVTv3/BkLG8Jnidpd12NGOVMNz0zPp
YvpNKkwIuYTVXK2vFJu12Xo4crvWnCuLcocG5H/AItiyzpQNrqE7fywjgxvfBzhdmXjowAU6u9Kl
n01QaApfwHGk/eRcxFsldeUISp12dTIVyEcmHZWTIftyTYmyw4YYwtT/ijLFmI6+iN3Rdb5wIL6U
cTXg4r8Ii/ot2SCx2I3YveTK9zJFZKc7WRw7hUZ+B6BGK8NoL+WJUr4gqSai+tU4LLh68+txQd/9
2In2S+ln1gplSUsCoMAJ8uqRBCuuwhMoguKBS0hNGx2ZdaEaL9OjZaW75GXd1ps3Ej+CiYLidius
/2++b5MCKngzFccgYin8n2b3v0R6w3TfnU48NweSRC4refZKUQCLVJBbvw006lD50Jqhdodd1acA
Fp+ZdqDQ331CiANxRgi+n2fkAa/4MzHIUK+LZx7PB62YeaqZpUywB/Zz2p1ACR0IqZvbQQQ6+stE
aqpHHc5KB0cBslB/8u5G82ugBm1L76/LjJN/4gR2Fgtx9NHeBO8P7c42xpkULm7KIAr6QFnZ17ai
aJH8JtdTuq9kRj/gOImbyEKbxUI4wB4iKnn1DlfODVP+MT6AV6uI6C5oR2LqjpzgGftUfES8CQnh
6JMTrYK+R7KrdcnwLrZg0VVk0nMmLB/m+sWicPYx+2VVqo8AQDki1UN44TFovbHe3s6Y4Vl2wFrE
uKmH+N9gYwY6doA5HEhuR+M8NKvuzIDlqfDj93lMaJ3oFc1nEcHTN56Yw5fMyEE6qkrUXfCwOr8t
2hWbVKuw+ypPgrDpi7fPxq6RYzqG62X7yk8nEie2URJr32WOgGAuSicBopFjvSd6qA+1T/IytmYB
iAhaUxSTrOktSafQvEx55RvE/FM2vfzTdX2fR+Gxa3V2c9MPrwyrIEBtqLQPPOsa8iF1SIZzAq5s
mgunuHEoUDGLsEwHEfTBMoVcSVlGVogbOgDRAAg5fDp4wa3sQWshVGEHRC9Wxm6zqWFFI9k+UH8j
MdcYAfyG3V0DCD1y3+E2JMS61H4/nI1R5DKJickHutg936YEE1sXA+etvYlX/qZJKfH50yKta83Q
mtM06ZI5FfKxhLZBZjBOP++kt1hvNzHO/Z6XuNiubTVyVRKmD+3ZDwtvqF2Z0XYPHYxsk4HexfL0
KWTpyDR+vbWMZgdhm7neyANq1qRHZ41X99SVHSiJy9BIJWsvftQIPkfMeNGAirYV0we9Y1eB5pK4
7v4dnUAjFp28HRVwtwYicO7Pxil6zhbv2+gOiQMt/RG/824h37aV4kbfg/D6LPgpIbt9p95aWwH7
121ZsM5VI4xAME97cmmZ72IPRRuRRj/L+t7v3cHbHFSbxd/h/JFRcJ5IoOIvJ/iH+D7ax0FdwEB0
1KxmqiCW1zFqHKBjGuyhwr2efNMM0UxNDnyZNumZgwKjJNJjbWn7tzwsWydqs2TywV/KegoQqd9H
Y/rIiLbwC7Sz0cVnK0GKTYPqFDn9dlr82OWUdiLkMRIn2LqaRRnIsEEGNZ8Pw6XPEqqsoeBKJVa9
hKBm1lGVtukrknnvJOaFI7h/zcNuMjRuTH/0zkr5om3taYwRO5ivhvgn5sv0KcraFrygbPe1yFgw
Vpd1tnbNtxHtmkRE/ClXTktJfDMcUuMV7C6TuRaXpVSz/yrX10hKnLJtKHLvKBayXpnuihR3l84d
iUWmNZaO3S9bq1WwaC1RNqxmMRDzK7gYyqmGyqCgrMFaWSBfjF+bQPTUJt3scEeNSPaxuCMbwfm9
zkMaViBIPBQ3UEfnNE/W/GohIa645FYs7XgCK2nr4AiRy0BuW/0FFr4B1S2dyH6VEhZs0Rbd1Ku/
G9ZWD5fOkA7EfThg9HrVV9Al6oOdgiYO19k30gPA0YBj9P9WjxG10E+XcRl90vBxMm+UjmLTFJdD
DWBiCtrX6uGo2w2pNY8YAGjnTQ18GrBNSWdF4DhQRqy7RLkZJjjsdn0RxReWjoqTRm4QsNYM9KYA
/t9mF0ISuFUPnIUBkoRRIiCO2XeW7NY5eG+7WgZJcJup+1nDP/9oT4QvZKKRt9tSZv3OtDTxJKkW
IEOtVfvGvjj3JKZZio2H0pqkp6weWl2h3dmxA7f+r3fEOvCnZzUwNN1eqzVeeQ1BQbYKlXWCe2vs
ILaxMCnaepepf/mcfDN5HI6Ihu+sawZLwQNURao5Hp5CNQpvoDxy3UW/x8ZfiiOj/TxjbzpvlYY6
fpkOPmZoj7jsyRD/i1x+M8pfAQ6Fpm+zLCCALDA0JT3kq5gb5Ri7cdaXVS6F0/s9nCV7Oj5OebRm
DgSQ/jvJnF5K9GB/SMbV6DZvPCpIVDkxL/ouG4dp1RWmzlswp1HomEKl73GYTD9P6SHAcnj7Jz53
ry2RXlxbdpbkdQxWXg1jyQzllG/CrK1QgPVrzjRpnN6lJ34szUAlpNYX39GkRzbyTpZWeMaD5MuF
ZdHjdf5e50MsCjjy7yFf4hb0lPsl/bnoUPudzbBAbiddAxWVvn7+F9UKQ926QDtRl0aEopAOXuOq
KBlqJOeb1Z40nA1uO+BEfEtXEt/bcvjSK2KJqMchGNt0Sy8zWWMAMCoZX4HK80+QBcJEDEau42FR
bEPsZ8I6YFn5gbkWh7r86GGNC6OC+6wmjsZFTNSQmOZRexQ6DPms3MZhVeDtDEwlnDWbuVZBX29W
aJ1vaRBARFd+u7/oV3OfB9t1eczEt9H/M460r3neyhFFr8otx5rPqzNgm9EC169uHeK/rPxSzB8j
ujfozq6G/bDiYNSJZ558f5Yc1LMydF8UXgNsORABfxWNPq3Xci254PPCFeMzUt8E1XqkfSHBoiKL
me+5EOUqTSunWFKUeFl0974WBILqcN87k75vvDnPJVySXcbhU1cO6BrdH9/Euv+ZYsM+2/MGSm5P
/eiJB1awZIWViW6Uj1atIt5HCA1u1xnJZDN8nlvzbSJXHIp/MWCkLIg/SjsTR+ncERwKHSAclE7h
WQRgVGUUVNhvuVjK+dOz41W7kjeTy0b5i8mf4GU0Ti797JPyMnb+vXlyCpFQ+LrOJLOUHKYKOB2H
iWoASG6ZRMB0QBPlRKw9CW3eFj6uY9NKf99aA7SiF3DQKVndOgK8ELJyNUjqEvVbwsC1cFUp3sW/
zKPRyh4nB2JmCzU2FqUTMCOWKQLHStno+BaspGcvsUuEypsJCRbfvFOSQk7WxIDWM+64yfbe/SAe
zNAPnGlPpfdNR6FkLxIX36QtR/sBfDNK/bZxT0oyWlYLAhCzRcZeGEnWBnCdR4i17qtbn25HGYIo
oCR6RL7kIUyslDFHbDnD1Cb1oEbwcsilcLPLdUeJT0jG+Em3q9XVvSFeeNRF+Q9Xm9vz5S8iu2PT
QdXU9EX/pz4lVs1qZNto3hiUbfxq7N65qixIXzpcBFkzJ9nEG2qRiQyc+XOGiWzFyP+YbANtPv9a
o233Z4vSm1hbytYiFFKAOgN/CGv/D62Csgtg6MqE+CzEBkSSW1FlF1t7FWtNgKwiK9icXbjn21Xt
P4mOiElA4f04xeqI8V8MifopIOU99BO24FADJwDAhS9P2dMvw1qCZMbjiOY6s+cUsoyFUZKHXa2b
f+KRybbjQC20ts1sLxeUpcebvfYnA4nKMS5cMI+rwiufrvhBqq6KdBV60d8NN+Uy870wMXwz4Q7z
vmkOWcpF3Myut3D+aYzluDTUdamTg1TrkP+jJlJ+ziEf2oFKexilLi+7bEZvq8HuAUwjaVSJSxn+
+rEZDnkTWSf5dSQm144FsTpSEJrwv5iypX1m0G3lFw9G7ByErp2k2aoAWbMCBSz1y+IztMPR4Sf8
Y2+QcEM3Qu/YmMtdlsXunfl0lHtIiq5v7nMzf5h7i4EYUf38g25L0zIKq+fZUli/Sr29EYgGQzMD
h81hAUaNn88ulMA49YSmHjRw6LBR5Pt4zTsRRbWYnIN4Giv9vH0+3GAfJciM1NquqWo12em0KRlb
1o9PFuMOXZgbmTPlEUdN3b/LCOt1Lhev7UIa0a6dAIoK8z7Qin4xLCRQJVX+OV79YPkPv82i0Ifu
beSN5Ri3pDpBPbobwGwOAuyuYNq8Ejguhwg8RRAvrVrmYlGqYbHkFR9xU9w7vn2722yBfj9XAc7A
q0ZoEOOHZRMqK1LD32F4x83jzFvDXoE0gIXr1vXDRhZjtPRdlK5N5h2wmbwTaZJ602jcZ8wBJleS
lnN+wX3RYovNCPybC3yCwIx6ccUidV+upWyOQwRm1HTh6ksxYdN+DP1xTYJpIE4lJ9XcqOylV0UU
PzWJ7ETREovg/aFds68rJssgX7XnNtSvK5foS3pPcvnOqRmMMK/tVmD3zUwWi3asTP+6YMRdjEF1
knMLFW/84eu4zJMqz5cMRDqusigSVrfl/S7sbAd0CR3OXT5CRsgr37mJq7TkFukKhRuA8h4WmxlG
BfpZsJKGAyENlMM7f4LLG6Eee2VsXuAxhZGOPZ7GO4HIcPAVkxXOzt5MnodggikWTxCDOeXiwUem
g4RITiK8zGHLJmZjsQb07ztOZl5vAbwoiTI3beT6HI0Dd2V7tSioC7fM404ghLDON5jCPaTqvZS6
BagSf0zM8xA2qrGAO1D258s0pMW6JPuErLwNGZz3CRBgsEbw/Z81SR9+p0KjDTTth/2olIiN3EhV
J6mZcpCh8536QdRy8hsqkfqnV6JXZpwTtEecs/oj9XDZoIgVxyzxuDYcANddR4oG1uWiGW4TN0kr
ebxsTGX1/75jyJWLIvAL8/NYcC11vCbxw69OE4wEyziIzm6RfYVLfpRiimECJHlwfz1l6EIGgU8i
vNPjFKxacePGpBA3Z6/o+M5XWcbZKXI+HgwcEDX3GOpemIF6IdXqwsgu1I/7KUsZf/5gETFKhNAF
OLdI5jmszB8metZYL1LvFd8XSwE25SDxlhZQ7rSpopruAmsxzH4x9f4xxiRTgnEaJW4Hc/7CsPwx
PrNzJIy5jEJQV2syLreBnSnoaFu3Dtrvxq7aEmZQHI9bpofy2fUgVWnKjoXvleWC5hd2srq8Iikz
jblu+ex611VQMeoz0+zGEbZxPp5yc1FJF2v0vbqJ0l51WoLGPWnYr3VnSJFRc/zfNsgxHhjxTjP7
S9CzpxEozfkWO+ynyd8eJcpf7jt1/owXQ+BGNSk9dgK5Ziihi0eeEGDgvQrPOuUA5/zMaEPjp0tz
t5EEPz6SdTx1B9J1Lu4aj5W5oqGhWpC25lwm918bZltkrbW26vG9Pmx33y3Q9MIOVekwoZgy+EaQ
X2UMDFqjTiFMN3HlaXtrijyzeOnBuC40SsGpNoNklXaTrNfBROihDNDy54JeOnmV8uWoQYgxHoX8
e7vSL6V5AnpsGC3D0yyuTNGpg3ISjKsxWuA7WoFcPtkI8y27+Hf1iGp+KzecjhQcOXvB5tJieYpJ
g1XbnovLAL8lvafEPcK/vesg/1Cy/lLUMOgUsqiznmkbDEeetFDsD/PAegwcWOBiM+Jgz2zY58Qs
SOwCABC9hAyFOiE3c5F6A+OMjN/K+/4Sh+LzsTdvYtRlFR2/RzNCK0MpcVSbmFRVcMa+9KPSS9AT
gZR29aWMJmmRe5heuoaNvvAfHy1hZr30stlS5iCO7uxuHOIF2nymyYBRX3aYgP+zDrNvwmICK1sM
BpreWUcY+iijKXKABhq+h0SKG5dc64x6H/gWQCaM0Yu8aUkm68+g4SJrNczuRbFWKJH60BbDkqL0
2gz/f9Wb415NXRP5eNKrxBI/5kZzVh/3U2JedUy1fFzDFIpSKb2MM06jJXhVjqT3KaAz7l/54WY5
8TIeTt5bv9openeQ6NQqw817DXZC6ETiabYwwTAFzRSXNyKmug4PaH5lIjpgdZyKGjVCYfq4DS+R
ScohXHNJy893cuNRQj976Vo00Hf2857xCOWZyh4AaaUtg2SkE/VJodoMSWNT0KCYY92fPq5Ox5Q1
xFFKW1QpRAPXVSpaaeig+Vah0lFw14Z0DASBnpq0lhAhS3v992IJ19BvE2TDrhbOOb2KtLV3IYV8
bI+vkDt339jcEGN6Xgis13KfhnfFHza+aAXcH8ne+Qx0dqvEejjHvf1EHVgMbyscjbXpsJKdf3u5
oFqhWD6uWs/sDkRWqs9gM6NAFRqrYwAjnHdJBAhBh3zuEXsAPXeJ3UJDF49YzONPP98YY+D1AWc3
yYYcIAQZNTlzpeF1MuYuK4W1y3QMYfjeLGC2DgtMVXu+QgiyRKjRbwrLDsqFPv5P4+sIxX5hDIAo
oNxU+pbYOPz448IxNeY39XLqTafK/u+kHkf3NmImIcMEqz6NC1IZPtn7hN66ooxO2euzralWSz54
/kAc7c1IhSb0Hr/lUQEZq+CK4kWzDsSWcAkTpbaiG//oO+BjGM4OzCKsiL4X4RXXajlt/FHPdbt3
yaMjDJxiHubXkn1Pq91S+ADKM0fNcfF8jsb67JKlBS3SugbR3uzSl1YM+rQr3Hh2w5Bcm3+DxtRh
n0PFhV042iQ4mKI1DBVioeCjH249lQmbkEaxAL2SXCjzTh7y/uziF8gk8pogAV1jpdyg1EahoYzv
7GhUNtCVOYuIInQDM1XenYfl2cxBJBG66KQFNEnwSA1C3k6xZeSttsxhaz2C2ecMvCPf5sGA0BXz
3W+J4zkyA/7Td1AT0uidGLSKzYHTchwJmaVuzPMXkKWm7NyCfkeqwzeTzs0pa2iOFHRaL83dyBS3
0W+yGoaFP9CGdtDjFd8wlrO8inEKxT87q7AuMi8E05FeOScOoXKmk7A5+pQyOtVXyp/Isq5o5NUU
J5RVqbGg2QRABbN/mVQtAdNFNGqz85quIETNZ+2R1jNpeuLbhyUhr7JFhccggdIw+jLH/Q3+Yx1w
Qx8uYmekYawiyRzl3uB/eTMxriX190B9PeqfCIXUKhpJU/aakpbi3U6NsSeYHxvNI8TTbJp0Xo3D
jiqpJeFGPeKuN2HAl389CFkxdeyAcD71uAkQOZki9EjErgfMnImUpEjOc05YpcQWDD8BmL9zhQhf
1PHr1Nq3nH0N0DtrDPIhyD1YME7rQxZufsS/9XG1YlayR8+hj1WY0wV3+6RcoPvEGxBtGW8hmim+
uqwRfM3hUrrHBbSVB4BiI2NCrTQeH6H+bPfQMRxRUoqGSIjDuFSfV6pnqAtMsGXFZjFAce9di8de
csNO7zZNg7V7V7NJVifbI622fW6SjfdUfws85n8ASP4kf5qiBL3ZcCbC1J6KHGKhKbFEem0pbd/J
H7FfCd22h79kv8iX/ibJ/ogU47VXuuizGz/yaXv043Sh0sFyw5j3LD1oaPZTNbTyuLKDvM6FRMYl
k6xw2OATKZVJbmB6zM6E0FAP924Da+hdZRRpzkLBpFU4BZzaf47IIR41DfkZgmpvXKE/7oJe+e3J
U89/dRuzBkg/1EwzXtDXAcwSqrdfxXeO/GgjypWUqwBjuqwleb6TZtgppHldQ9jeCfBxRNpIIy2c
+m+W26L1eG+tl42hOO2Ah8Suzbg5ODm6oGQ1DJL0CWKliDPw1h6ezjHN/cyKKcmUFWkK7OTXSxf1
XuBKRznikgo8HiM39W2+6IGTuUS4zzb99zLN0To/85COtmGPrD11sLpgZSy+I91Yx1Mu3sRLx7TS
t4qSWYMDbW8hJp3lPeuRcN9+rhAiUG+mlO4f4RzGGe2u/J0qbOOieQY/Ejy2k2BzhlPteMnLp4Xx
Qe5pYQvXrWFifLxPaxPxB3QG0MMtYWnq9/DUPMhrJkIUe95qPDmyj9kUlA+b0TMZ0OEYgfF9khui
IOUAW6qpWN03yFcM5ZunL23iPsHEVJ51Gkg7q265BdVFMfhAI/nekpQfEOxfNJvL2G8yyrPMTpLj
+QvHLdxo54dfDGWibwCUPzy3+46Uib0JPaxOmY4R230VhgZS59zCGyG6V6mq5W/wPI0e0C/yEoC8
2vTSY+GWOBygl5zgd80nEI1vW/FLtmbkSOPBABKXn/Jw77srL7jS+zfF2T6zMhEDPgfqlLXIaTwl
8w2Ia5ara9yw7pSV7tc6rUYoivI555hOr2yJirXjMbMMOJ5vmPOT0MUfabl76NerOWW4HmTctaFj
bHFEymLvQICAjGI9gYhdXO1FcUawY8EDBZVHgFnCXwW6/Q004BSWtrjdWYLdltIy8qjy7FNo0GWp
SCQPVtKlhkV20rD1yFokWvTzMFXBRPA1RGxSFS3O8CLUGaSQsGaftVesje3OGrSwYsdGRkKCq+Gx
GGAJ4/nrDEWTxYlRJ/zJrFpbnMFyt3wnKoJt4o7tclSulM4J6aWLkUd7DvisRbeWpmL2jb2grTbf
VwLUxXxEykK9Hd3oq40Qmr1kOyBP5uywIFrKS+D/eutaYIHxLm+Cnu1gNhlnQfc5OZ8ZRRM4n0iD
Wxb4J+jGeIFp7y95/2UO6gdtImK+2o1+QQPr7bMJFAx4S9bztKv4/aB80dwFE9nXtDV1t714XC3K
GcOZNmOekvbssAXv2tQNaF00b8b0nd3ugwEkVbtVkm7L59NJi1HCO/w8HYIjHlQSlg146AUy8kST
PD+YnjJ54VJ5wyh5BkbOC7vEjXRMlUmxK/gS480aOk9hB8OFm631tEW/3mnI0hBqobXIj8DDbR7b
ynmzZs5FW2t8Co2E6nIjMzMzY+XzLaWXKjRLg8hSxp7w486x2vrkvh3ZOvltMtaYCe0wTlGLbLKU
SFqGbrOGzVim38TFh8omJXNcJQ126R5DIesrzi9+gNJ3f0Hcw+WaRsNPaNv8HwEbTUHK08Sna8F9
S7irpVB2odJ83X64nXpOyATzlfL4G6NrccwbvoVkSzKzQWuhyM0wJUQyHdu4sdoZcCiaZunfDRjZ
0tSDnlggQxZvjKB4bA7V+CqmH+W80OdoqxPh9FZ6KqweZglrokl3S1kAQali8Tp6Ks/CZ/wvj7L3
slUitBIY/XADwHFaGTs7wk0avj5myl58K8eV+Jp0R80vc4Udgmpgh1MAMHFCg05vZ5IVAfUnREu5
onZnf+zqDWwna7cEgTov0e0WgJBAe9UNT2yXatcX6vxfqRaExKsi2pZ9IlNREe3kqHLWuZRM58JM
67njiHofOyjx1zAzzdPlDbc7CnGy7zcKO9dd0OXK0mEjlX9PW8lCZav/5Y8MI4QNhtfjWfg0MrNo
arpeBR2mDOgXmdl8cvo6/pGGj3E9ElK1DnbsIb7YdpnDWYVq7qPcFzYHVZqQh7CiGwd6ORmanoEl
hU40t+VsK6nsGn8knEt2nFekXEBW3swOxgBSF9KOTUwYwR677cJ6CIeyFZ2HN3RxmErLrjIr6yef
z2iE57rx2PECT+9SrhjmyOi/pXdUl7mxsJYijXszzUX2U0ER92r0uW2DrNoEeyAj6wwVv8VGik/w
KU3WkydrRXENuadT+ZN4EZP6wBVF4EaoPW2XoiWiq+jvTXZfQe1XZ0qi30yLKFbyFG8fUhesk/gz
lGG1itdSMVYt4rMKvMK+cbLX8f12uTStvV9BMgHCuNz5vNH7obt5CPLJyJClggMI+/3IGrCVgA/x
GXELwZbDdgQ+KJUVGhEwCJM9hGo/JcNECXUVXQbkZBeShDCoXcLv+OZ42Ohcu+SGBuNDa9AxDHC5
Am25k8gkTF4mg3OSozfFYG1Iyu9Q+muZFpfYlfQ6WlMta/MvfK5O2L22mPNdPvbhOYHp4ozBc7Ws
fGa7pzuaFOPrQqWHSh1zuYpEwiM3tfcuJlQrXilo1Jv5B4AsECmQhW2L2ZwMm1iP5RBlc/yJlEts
XkSCrbOS4Wk/Ey8Z/iMMqRPe7CDHB40HQDrifWSU9LVx7Mycf2sDlMI69nm4TOtLsXvLVTOfL5WI
GueSkaq2C9JVW2asNHC649F4M9H69J+QIrbF13qdSwYubD9BCIHaSxMK6WL7CwcTAaBn0kKGm4oh
eSH8nkXLIwWnmlmJF1OZpO8uuCy5JJSsG/BwvleiBT3dRV3oW7rES2QY318xUNVExrJktVA9Wg71
D13w+U8uKezCzow0T6tv7mhFn/Cub84ZnigUwNiqawJV/aPl3AEIe6DCe2vrgaJh2HoGmcETEGeK
QyWhiSJz6LX9d6UEYHNf7LCx5W2ZqnIUoR/xw48Xc/XVW72QoASxb0Zn/W2GUc4xNh1eKYR4Nqou
ehoVL9WvBalFrelUo8SUUbwuWe7DYEX9zCjQfYXY5CXOQ8errh8oabSfJChv4NZSJ3t/yIETtNiI
hSgO3h4bt5EDSBmqkzja81qz3A3xa6U1nG4oLUsKSZttsxZz3O4Pu+K8rWQ+Csi3NWMPGAHFC28Y
OLkcpbCBhwuV6pGIzFWWYW2zT3Y898xORY/P/jCj4OrM7Y9vkTbvbGUbzgRf5fv/wtaZH1B7EtFA
j4ouXsFJ3HJfNQsXy3mhmUnZsZBHkIPnlYvZxuqs2mB9xGlZb09eSZ/7cmuwjS/fjhjjV0z2XiEP
DGtEYgXhqQ5PUVCqjYn8k4fMRrM4bO9UFeRIzxRAF8CIyr0Wau4QLK4YL43GwwCjOB4n58DMaDmK
varj1iHjLCYVmP1YgzzriMzfZ+rSvgifrapZO6xSOvLC6mmrxVQidmudk7dKOvpV38dxndbvfNTp
tkIgMNyrsxIPEJYjV7dM5Y4VaiHJ7KzEO7Mi6JTJc/lg2NBPUeL1ReEwHrPt+6t4EssedJUzFGsM
DTmvHnHQIj7ErBlCejNRXAV38gp4Z7Tcexo4J7wXQTwJ6E9Ijse3AYRCRTtv8YJv+Lq3nx0WxKtc
n5btuEyJ/2kbVDA6mM/1BUOocp8nzPe3Je1nLejgsxt/rne5cXWo8Ro950WCX8FKiv0nfvs5vZum
GaP7yXvtews/NTgwpZsrkj4E9atjN0icwT3mvfBljLLj7IgK0JYxlX34cFIWDTDo57DaTUdr1aL/
I9R1gnSARaZCog6VUXUrFwTS+cQWe1hstrFJbx6LojgQGODMuQMkF8otQxcSwL5BcQR4G2OXIHEV
W8oDMnHdUq+FrPuOVK/yOOnt6Fdy62RfmnDc+f9rINXg+WNE3mqVhL/R84w3dTOEPKYQQQ/YWcj2
Mil6yWGiAGyWRB0KV8Q9Slo/YjndmRHolIyLoiUOyf76TAX1O8GhwskXX3yfLr/uf4GqogEfGNc7
+xNJKKqABZ3trDhFD4QNc8W/wH5C5ADlKWxxI33/3ervoWRtOrg8gY74z/TLPJpC2XcUcWd8dRfi
6P5+LQJqv/1suc8xc3s8m21YSUKGybaN87mocDKx9kN+G0N0FUP11IAldf823KPc2IZ48nrWeO1J
KcJ/AWylvbsiZuOnwvbMdM9O7brjmrjDMuy2yP93OtSeIdezyUKK+eRwcBSqOQqEvNxQ3sx39ofA
FDCkqIQqzabjLcmP5VLh1hSClWKXNoFvFGdC69NpQcHrid+FQqrvG4XLHRli2WEalRwwkhoE0Hf0
utUb979074rG3zlT3rIIVSeoR203ad+6tbJwItAqQxIJOy36PVsmJ/+3BdZBMZGAgdZIJ7iRSC77
cE9cg3cAhOpqcYnK8g9URlkM0C78ujvCS5hHv4vafbVh4jPJwq0qzX1IYC2+5E7dUjRLSPFhcqz/
E84dqoxrLYt2t+qh5b7rMVFX+8sffNOq8hG6VxJsJ2pYUZo6kyszl2rk2nYLXz3ZWM5GA3rsaBNy
BTLdRKlZF8BlsThYQo6fbNrCjn65OZp8Uxrfo7LxMqeCpmnvI7sWYrDJ/8LtJILYd6+q2S/2EitW
DK/eIxIvSqLuhISMRZvssXELvVaxouo7W+jav6OWxdHa6DEVXvEmX97UOoCH62n/0Jhtyg2i8qoL
+dKQ9cmqvCNkFknNeloFcSfAuAvjdr7zIB5zczePL3bB2ZSKecn3c+u8oqY6olRMBvb8jLh/ftuZ
YV/ySw0uDfihhoAwsUJZs2/oRiuZIfQLnyUMuaQr3GCaouhZq46vCL43RL3KpttvNUGRAs1g8EWD
6x4YyTHsjAkl4gZ2JMIBzXk53Hm5wCVBMF/0qvgHo44zW1DoJ9cbUGfZHVivx9KP8fQHrSPs6eYR
3Q7Aj8n7DdC3zz5L4wLf+v3fghQmv5ltPp+487orUJiUN7MaB5isnQluC9C50ETBqk6TPLoOIbD0
9Eqr/zejhI+75Yh+A2EYO1clFAHN39emBAuW8P/prmCNtDo0IOh0QfK8JiMzxucUGlPOEtMkIc0i
aFiCBbr4+vuRIPKdD79M0AnlwzZHcyBN9Lhcz5es2FgvzLAlO6PZpySUc4vyc+L7KLx47t2tFKdV
B3vrnOeFBMzzx9rv930Y1D0eOp/aC6Q4BGwMwMlJZNsaxw71Mj2W95OYTwWRUgpShdp7jAHgtUsg
cWqCh9xzB6q5n7VzNmt8ICHWszCrycdtLmQqlJvHTCIK1lYPRSJtJN12uZ0qKkoddLUe9k7KvZaw
yConP/bq1Ii5waMnCmUz3AZ8i6YAT7nb/wE5uCoeokl9ihZxYgTqUMrw7gKBaB3KhqoNxR95ka1e
6i4ao8M3nHURbZFcz4P/D2pFIOAUIap21VgPw1Dbp89KWyZMBbCE4r5otiJyTqpyP/D921pmc15K
zLbKz+GylJhEaoUkBKgqQ/dIZocXne00ZcHlEfPMmZ/A3FrT9jp33uKrIzPbTYFZNGY+mAYzrxIc
Ulj/0es/kZV10P2JZtTBRanMy4ldThfg95Q8l2SK6UMVaSXHld+hf4kkJVDV00jTEgRauVIyRqL1
wrRBOdJiNaotKbs6ZDA+aCG/LuapRyijEm2ePq7E90dWZzC2KzQxNjylVhoLLwSJitXBz/SSlT70
tVqUGPvfs4iHxQBBJ+NB0NJHHd5j7qy2Gpz8hEO+s9xa1hbQqhOk9aADcIUQtIDpMzcXzpv2ncBU
yeMzXO2NQg0j2S2J+cfUY5dflMjo9CAekvnR7R8MmglzMWeT8J7+YoR0M4SSBOjOO+2nePllcrdR
kRmvp169aS5ThVtVBrQZJibLNoUOMA2pHM3yHBzwQW7VG3U9BGuvJ5wdzlcI4BvJIGoWxeTXOE5j
QYIn4eiRuoxMc+BiZvafA/cG5+gUOkdGvi95t0YKzoWmCGndSIE2geDOMJfTJK5d2on/ujGBiDsf
hCGh0bd1UXu5cpZFSAlByyw0D5SM++pnDk6esq7vxNvOoGXxDR9gbzWK2ZIXc2q5yzsGD3vD7ryS
vV+F82O1B8F6SPHwJoDtPafXDHIuWxciKVXi3exD20ZBjuxSNIMIUobfCjWCBCZkTJ7euoaVPZYO
gck8phUUwy1rTo3mOSJypzayTdcUtnDz63RUKg6iC+7iDykN5z18/kkNI80NEFZUibeO4SqMlc1O
Nw1vBtN96olSczTvBCZ0zkQaYdqIdHCpjmR1g00JI7aIK8blD1eoz4ZdvISSLeGIFIIWSuO8ygxR
TzXWSidg+5jz5RoNsXn04PKhyizBJOOYbLEyfivptSwO+tFkqAgHj32WnzQeN7nZgX8IHRu17Na8
RBcHZyDWbHZdbZwg3Z/ziMpGLwxDpYXVdq3DK4+a8eD5KZCAj4/mKaoGSx5/dmywG/L23kV2tgnH
y0ByIVwuXR1nu4a0KLfUVeiZzqkJBMJciWpPNIu8ow7st7to+E8CVpCr/sUZ7YW3VeDv+bGqjL78
mnhWDJHHNcz5V0mAlcBVOOj5jWC6lMDEjgVB866aG4oVP45/4WshMlHxiUNFSXWtdMcWP/a7g7UO
o/Ys2oeToa5KQsLMoLQj3faWZCFELke6jWAR7gyJhUR84L5RWC8thJKuWGlSUUPk9gy1Rt5ynunL
zEih3Q8wTnc9PS+8DP2J137ojAM8oGOu+KweAa4Y6DUktRsY+LVC+8y7fYtqyvdqbOFYss9sT3DG
oR2YDZ+OL4VGTsKksLUwUHnBU+xBjPz/kt/p+T+x5O1njRhSGTsk2CVvsJcDfKW3J46RwUe+aESu
qid2bQDxPJIjMP/U4k+/H5U5h9JnlZxUSz8nFDH34ZLI+s827fphBQvvCwJjWq7y1tFDOVjcc74b
FhRZaApUo0SdykNuiDJGjwQ7QyijDBTx8j4XfYAzu1YhWD31th+p4GrE/UFuBw6bbnH01R8Je4TV
BFWGBJ80WzESHO+YIVbx+J7EqWiNmzkgxyF2MpmcVu0rhTGvRloWp51jcjk8xpoRGvM0FwyPoUzU
mh04szzvokS7HsZv/cyjkgmit88RhWIBMHlaeA8QMena2D32X48MlMj30htZr9gjuLiT0F+kzAjc
BamtJweNoxqbErHDpGsCDyABtlNWpvumu0XdtsiMOL/KWYaT7/gGLLPuxjsh+Ernq6bToeU/TpXX
pAHRlwGhbJLcGU9umbLZdKTtZw0qRa6dvUNMJSM1/0fJpM0Ai5GT2ME/VanZyxh5uKI/Otm7imop
4BYk+xj4n0T3+mdO7q/NODvo2KJiy4p/HNE9749zqrekUQ0My0Gzpz9DfjXidY9yXCBlyMeX579b
AIl2GhoEHG+ALPIlW/6Z7nd/q7s6C3t4CVt6IbmqifwQrRZH5jPgKnJaG7wPvdO+WizpcqA8XtPd
h53SfutQ2zjcqjvZ2lKze/vdLP4/IX0mR5Vh6Pzo0+SFAADqBZha9wPIunLBU0uYi3CcVJYCbkBh
EEit9KRNfLTue88gFNmeT4i7ax3JhJfmods6bh0VczA/RoPGQS4o4MrKcJzd2+OkPoAypqbPrqOD
Ei9G0V3Eotaelop8CTpdbemVsDgOInfieeMqLG6w4aGBUYPFlBlI01d3NtupaweueBveVVO892+i
uw483GTi/nRxEqmMEXbAF0wprW8uEODCpBBbxWdDKqBTk3Wi0CIXlmLadiMA6+Hez0zhwLh71SZD
CoKZasAsTtcwCQaY1u4GuyEhUH+Q3cx83eFVhTTH9GiDh0tnD2L488q8MSvTBH9zMlPHNJDzk9pB
OrAA/1HFVh6JQS5ZVDCnS6q0/0bIBogSmFsHME8eD1vo6UIA62D4kIGgQIY6BTIMKtui27muW7Dx
mUSZ+mulVlJvfy6/NObfwWyU80vyWNk35gJjylvp8OL2g9S9C9OdIRSToPDq5BeiJjx1N0H0m2HI
jIeMSUDap7txNURImURsggoubl3RxsC/wUQ7SzOXQ4dh4tAus9iotTRmN+OmlMjHQHtXV+SCyQ7q
nO6YwgDZdRxn3A+SejlVFPcwiIV3669WSb+BLnFDUY4NaY7hOwLkI52RWyCsVY/2HP8VjCZZy0Ne
jsH5FeKN2ChCtXV5cSF4GX7trYl+Ti9al5X9+D6vUxbq8LR9MnWM4r/MRjOWXFncT53GGABkS2A6
B8Z2qZ2MFx4YQ4JHtfDB/wCpuFvFa8te2DWVfu0KThqJn1n6w4sEHm5jm/UTT9VxLdlVClPCem8o
/BDT6C6m3yjWYDf7JAX5Zz9hWt9NLjbfq2hhDsRGY1DZebmTKAnFzMzPAhap+gyVdiOmkdlrDktI
HKGzETR9bDvhQRsYw4ZqvKeVsnbVGuuc9pi76fMToZo2a1u858iR6GsF1fzu5LdzlUoDy8/7YdhN
pNRn9iaCeNv31guhDKitFsfbzJIUTBp3qhA0VJEPchLjPMbXrED2DEbhhzYYT/W2j4m7hadBd2SZ
8YtBWHYEbMGpg/z3FobyzdylNmtLOQ8r3BRMH7cVJIiu4mSgxMQnJgNO+t021UAyMJ2LryL2udHi
ZskK6qhy28kBU/UqSFvW/zdIHVVI20ACFKohuNp6zyuEBrZ77YXRKC3YIT06sNJ7C3UB1NxqoKCv
Gz7Ux3u2YliXpUWCWD4P2VSqZwyX4ZUhTLMcuR4glQKs9AeNf2qpLUR01jS4O96VoFWs54JF8BCG
hLU48OF0x/IyreEtUDEfhExMun2UY3FAvZOn2CGZyAqSxloUQSDpNMuIfd3uTaxZKmOpFnYwhk30
q/7NF9xsa6u/L5jRU2gobOR226/33kZ4dy8VqkWkYN1p1gR52LX7jYRp43WYVyWXUdLfM7JGFnRm
jGQcQpYMeAtGlPWmtUTvGFg2Y5RdP4s4OKfrLGMXhcOxau5CgpF1nbhlhZDk2uon7hc8mqHnOtDM
++gYPHwyTv8U+Q9d8eO4YoZ1UGNk9Ie5dKZJhxwwJWn1mvnhapMcg1OJrIK+lQDuREomBSGYBEGn
xy0Sw7QXEOpoLqIcu+j5FulNMJKjDy9bLQQdcaPlPJR0/sDxVu/ZVgrg95qI2U5NhAKWBeHn9x/0
F6u8JMeaxO/VRCKOj2xH5erTXdWP6t0rAGGggkKdP2bX0EEFmXZGISEuMAr+KaAKmhU62K6bTV8U
PToEQWAQZJ0Bi7grGrYxbw0ylD0DLC+OBv9/tV9eVNbQIR3G/BtDBAP9VAvKMcGKjtfckViIrKz+
ExnVfX/iwesb38AsBe9z7Uw4yPjZAw+z/uZhaH+oz9x21yjUU3rdltlMDwhB5on5kHB//DYdRn9s
OY1BF/0ti0YGQM83aCqJtNb2pjFTLHO1sD3jnAXMgwY4y1xLWYHRslWifIBRCT/px0TUa5TP2RaT
HzPuA6igfPP6HgMvcsBXS6zdbi3Xrw7VDhE9reX3u8VGgPCzthR8lbYvaj2GNokSwLGkUbHLYPob
ojAhx90944PmBR0ypqLzhfCFs3y1NjXvNX3l4CZsyW/8wunYBhVU807oxJpDM0cUUqJLKI6fqsvO
6Yg6Z2OPuLw5WI52c0f8t2CfqRfNmFv9kzNaviTjS54Ksfa4dJOkdo5Mcr4hRTp6CBMoHZkjbpTY
8+I4HLX0MveQZiRhI1jfZUu/ZvBmoeOZ3D3eU8AzSNCiW+sp3epf1yOeTqxympuZpIgXtMuOXpQd
BUgu/F+WZJh23cNXWbFsSzsDMeu1gxtQAACXeYrkns8IhIEx3jB6PzJoK95veuzDMnlxauQYvCun
qOCIO3xbmf+iDOgOd10hWLFK+lRdAIvlPQI9rBaoLbYQqL++Mce0UpBvsZTLin1HSwMiyBfpWw8X
puTMpf4gVL3vjpjY1tZj4suvpEIVolJZHxQVP/SOo7i9Wmnm4ISKD8xxYbFLUfCHnEpfHJ8bcIuV
ME27Vg0nqoR3eZT8e3wpj4ehaRjT7xs1UGF1HDPDEl8vPuHMGgaE7EGfFZopaYmmovOtFBy/DCYh
/lFehL0iq1dmQ23KYTCci+z3SSbIxSfYmLGWkjJbCeeOi+HKPuR0wF8LnwFj81HJmUCkic1btjVa
mQ/pcVpRPYK+kpv0PpH1QWiEB1pRzcckD5kjvLsEhCkECr4WgKvf74NfrRtHVHxOYQg3lKUY1yud
7I12jyzx0DBll1J1HgJ5oMRva8DQCSkpcD7j8ks0Ffj47OHGyBOknk/dwfHkHAtvEsN5Gv8B0Liw
JHxen5StLA/KBLrPp5Myh3Q0Ky6r05AxEfhlRcDOXZpsqj9lja8Q9xKKWmEj+rciCg288LIrxVGA
d5OoxLn/+go5QdNf3hiGRKGDAmeTDKXZqR7KxipS4EON/45QhQMsfE9vZw0ybZWPk7QToimrBkJ6
W3vHJRZwrVEMvOmvngGy8WCVRzvsfsSiH6GGJf3sBHRC+1lcJz30eJRceC1ARPYBS2UKdIciNLIP
kdBu0eHSkqMqTWaA4PJyQo3r2GloIFAZHowUSLrmYg86a/f2HDxx6aZSJTzWIxFotdqZqbCY+88Z
6JrGBKMJoL1quXh0HAd4sGl47ztOib6TkQnvgON2GbGnAd38rDPeEgPlIkh4jD+U5eDbtMnf+SgF
qF/Nypvp/+exH4w2ZU7dpZvQclSEaIQNUZQ8gXNY1gNlC6TNBK1KO97raTSTn3mCB0IqzTof0it/
iD5qGuGlGqkHyuU4xTzaVoXTcmipPhO5KU+NQc2oHyJ6esmlm8os6/tfhHfReco2jBpYi3f027Xm
2q2LEkqlWDmgf4paSbjGSafuUEO/YOl3f+yjMVKlOqdcOceQboRfBbrALqsGhjnPzX2MacuoMvil
Elgr50dmYyvaX//NVGwCPwkA2P4lch2NFLPZEqnYzidAWm4bVA8sujXVjj3hY2B04eOmPsn8u7wP
7cq41Hp5HAzbl2A2Z1HjBAwuG3wigqLJi/zXBgjQD6BR8naTd30S0zqGv/Spw6JaIlRaLWfhCseh
ZYWr19nopw5G3AQam40jLzK1USe+2LQzo70MA5Kq2PLZX8JKcB+3RVxgKGZ4Z0Vh4WTdpuVyAske
E2rTPpHqaHFgJCNh6N17bDbIxfvDkrGIhkXOJjBUaMv57thuEV9BNIu+JazCtubU4XrD37ZN6Y5l
h+/99kitYHUW1g5d4ToXh8vfgIq3IYXytbN39md3D5K9QXH/JVE7dyksZiJnZDS0YOrQkM5922z1
GIdjxBUhdernbue7PRkWjyHmF7WTaW5XhtSNlrZYA+KdT0zdToBGF9CajtA66qvUye8vuHL5hv+v
3sYNE3UW9mtQdskAyKPIVsw51iwtdRRnlsbGrXlu0F/bqbHUscGrB8+PvdW6JtbnsxnZt4VUW0Pd
LxFR8/o8fayH/54zapweCT690DYxO9Nm6I8pyJf68Qv3M67YIRjAjZJFiD0pEqWIwBPq/xkCu5oy
taRi1YVwEsLXJ3AdHGSD45/r6nPESscEpTVFVY6i9rhsOKF+48kF/97bsFnD8RWqPbumZO7y3467
ONjZte6T0PAMq9gYr0RqXGeCnlMwcVXba9kIWOQU1bfhpKGGFIX9RtV8CTK6f9IeAoC12ebkcVvl
n+IrU3/VcbEauRuLGIbhemgzrf4OWErimf3i19/Izdt0SCQ8aWzYfNI8K/L7KxCiIaEiTjgi7dRF
XIVtHgWv2NtnCVUR99jFlirMKKMrPdpkPY2k15ZldPYKRTNu/eLLuzcb6dhhKrVFrmFcfoI5cxBe
22UyK+1qlIzgRPNaC8K3LedOHG8abVaABvl3dWIw62lc3+AqO8lxYmSgNMmfmV/hCIsw2RkZcaAs
7X7otZ/+Pwf+uQQQ3cOHmYDMtRfAMA5QOejeE+AqTtXBsqjOpWIF8hHLMakTADjGpEaklv0xUcWZ
yyAY3SVnqqIhMRoik/LVufE1n30luUQZ3svaD6JGwTkRX+DpU4Q/4Me6s88lYWKDRl2CSBBFuEVN
OfagvI8gRRB4nwixNnnyyasYLBl4mhHMqZzU6rM5nece6dG1LmBirpESsMHkZ2XU48meWLPB2+Ku
EtzIWh6tkI8tQWZGe07qoMkuseWO4079PlftRwy8/9zNo6BlRkEk1ErNGh5LzW7Xt3v92S494nBX
6J3osUUKsHc9aqaT9PaynEQwoyFBBjKz3SfH0bdLNvYqVNCeFR6CA0k+5P3W2cZ/SndedL58INyP
H6WmVlTvHX5hfbuIA61g200K5QupaAmMow6HUpcVZHJT9uXz0nDF4E6V5aagZewSfJsQCBi+PPrR
i3+F41i44G/8z+cHJnLULVJ1AfhvcWkOMihxsuxBobrXvmcwfLKI0NvsxBbVFj5TX1JxJfLdCiZl
DcBObXfd8iDFv2pMvJ8ZJz+x1NMy+1vlVeOUz8aMrJnJtRPBiJMposxDuZfCQOCa/HvSTL3L/VXF
adeQv+rllKZGgZKfxEQHgoS/p0z23PHopjFAkfJP2I/7jZFwTY6Tuh0+TldW7BJY+iricoi2FNku
YbZfu6W0ZaL/ps8zFqdi3cs6Aw0GRoWqtmjm58yqLiq5xSzx4kSxd7sFB0sStKuQYIgKL+oYSFMB
+v1nGebNHygkpM01fpoQPwt+IE7XfsglwAxPO63EtKm0Fdql5+yjeve8Np8PyrJauCiMe4EIiTH0
vjJRSi/9u451aiGL2gXrqC4hokp9jK8lJVZCNide0xnBpFFle62P2lDFsIi8BNkIrpzyktnOUOQk
jDsZCNCQHBcWus0QIbWFy049HB8lfBw2Fjs+YTKanJioHvMP/phopbx+HfaYL02zYsGhd7lSTFq9
LMpnBtZlVWStjvkVYiaHyB+Tf5s2iwSXrKqGKVBJaS0lIDu5V85O+BixjImu4LjXZciyuc58hUu6
8PebJH/pJ7wnsDKkX8XPIexXe6N3A+XUKf/Qv6NFEvJr9mUcvuRPdvCNqtgt5WNzFCGa92ONwXwV
n2AFjEhVjlNlEGq4DQjLY7DwTW0V2IzTtUxf/LN0xOPMIgRpsl70TCWQNyLhnPMKznMCkLdVrDia
UVUt0TaYsIWBcfqpQTEmhR9KHFf02VavP5hsS+QOCIM1MZPj20g0N90qqAWdNzp/QFa1e40KI/z1
4+R52dFBXri/g8gIrP/gnDwBf4YonYTule6yN8SienAV4uCIKXU9ZtYAlWQGed0Jwdktfmk8QFgl
A83zRi3mIj22fZPkkdDm3yLYlan4jHmgmCOU+Pmwfk31PZNt3N+B20KO8HRLJV5MTXKc8rvUIOke
4SiJXWJUvG57pnQ3bt2Jw8Te9EjwBi7K7Avk/QiMTcM3hTgvMfcfImVfLJv0Kc1Mh2CL2kyuVa2r
GSWW8YyqrYOuvSmuqfS9jag5ogIWyr971lw0Ch2/4iT4KhfQ3P+wB+aGxaAkYoR3GyWKf7IIZrB3
v8FcRpRazp6KAgXmq7BXlYHPqxIC0Q5AVT673sFEQNPFhGpoEghusJXwMAjaC/c2HLKMV4rPjPJ/
P6EOvP+TdSunr80zMcBQZxl83Gzyt7WsAswT3o2NHpOC6kStWEjCb+TCODn+lv48RKR6wWS36jIw
BTj5ZIFOoW8jTlxjCVeZ+D12NLX23NzYF3Ghp04vruGnQKFlZYbAcmW0Woty7xQsKMws0hi0LMMM
bCjzh266vmFjVk/wPMTWGlb/BrFVHOfWuEjU32CdHHlVj55Dr6L6teY/EC3LZwUUDL3VYJsfMoW0
8BMel8WivI1ZZOCUCBdo+DSnlZH2QzL1Mm8hH0+iHC7l8Uz1mw9/iu561YqMvHrwCWlyCJsw8ITz
YoGlnhda6w0kBFnel11pMT1gh8fqMcNalMsvBK5/r7dPmfH5dJVQKNyQ2Clyle/OOWyt7m6+/T9a
nld052xcZEeX0KMiC3umIuSuw/qvJutM3WU5ESVLVo6RCntN8J6oYiAYu5G1ZVJ2VOrXe3VZBpU5
cw1bBJONbcySy5jkt9dLuZFY4MkKpTc9Dj1WLbY6LPEwJQgrD7x3JXEBpezScFrLZQvkj9ca7Lt0
asWJF0t08/TMKMHnDmWT27pOQ9gRmACulwbO+1WFg+ET7i77HWTvFfL89YGy/rIKTaQTajkU5Xz2
f8ZOmZ8w43RQlijlvKuSzZb7IrPtQOCOAzJsqw6Za0ze6GptdpcAYmqYaQQUEV8W64KZQV/fKI1M
m7tvnrB/3p73ROt28CA6MuiVA/NIPBxI9Cxt2pEnZI5m0E9g9WsWO1m29S5AzKGCV4XXeIl/W/sM
tgy5EHHBFG4zo6exF8HxSSHKjKS33NAGxce/8DaH+G/qBJq7ClJS93yfKwk3dJLQGoHb+bNLCb26
A4KXLvOPpWWInbr1j+Vt0fxKzAaiAdrRSxv8I1NJ4tikycFiNKSYHJ6kNFYmsNmQTF889mWN5N25
iuXQjLe11TyPmTdDsNgITTAvuaGSvSK6mU5i4OLj1mIUTxCljdXZC7F+VZMH3RCWi495tg0Iz6Tw
/VBqZQ2BPRZeWyCw1DlqVI4H1Dbc/9AVUj708COp5y0OLIA4OmNonIqVycv09a+L5mYimXIPUQ6B
3jICb0+/0dpxg1rUQLQaOt8vBzfWtB24r88Et/z56XKHgas6UzvSu6gYYWLGIrCYJtwgJDIjR0ad
Wygk6TtALEPZewAia7DAZWJgLz5x/kG8wjPHsUwotplUUkBFyM9OITgV5zITRCCeK5zbGTeBvy2r
axkXf67jnBUyKKZtQ+x9QZedxTmwvxN19bfYhezjd7ntXXMB6jjhr8CMYLtr5A/1wCgf2WTDnzMz
+0qNXbK9lTTrYKR/pE8R8W7i5P6W8l2ToSTvDW2RQf1OZXgpBT7UI20cbwT0vZyGu+S0tkFUAgCc
N+ZnuRLAAmXUTss5WSQWXBldEigSyqbxqc5RrUE8jZeenVItrXfBxn0XxFl5xuC32K0YmwGqh52B
7nb7BlodUGw0ir70PO4KiOThd+OS+wKyjWHPT2ou7uGoAcYCiHnyWEUlUcUh2r5Xc0K+Wlq87KT3
UtArzBo9COs3+MUlTeKYuJBSXgDlX5xEYrd4aft4V2M6dzTQl7I4W7B1oXvnjG/iqPXvP8VZsiHl
4wCV9xL/KYOdOeiimOWQK/Ov0FtYXVfDbvIXpmJZVqWEjPd2rysVSe4n745zWjwhkrrzbMnVmy77
nNJ9iW7aAc5W/ago0xTAMURMvGSsRBxoLRwBCg3egTkErs3oeI9zGpcpkxHR9fxQ2op1BrIDpCoq
34t+82lteZ4B5SS8Eeifo9sj6QxBxBwtoLZ9c+k6IRQub+itr840P8YK+WHWCTtHjOHNg4xr30fn
YgB4zA44UCBSR4PWkXV7hIg/nXbIEDJc8Okva9kGeFc9jOmGxf9JjEzSWdDZpWYYaWp8PpdIGAOQ
zcIaRN53l+BNuNGbpAwqSppzSJ7ffdq2Iewhn1i7LEuswBe9Rl90zeckxN/WzBgYngNsuO2eqTcE
SCW76y8tdwNo1Ex7WPZPCZ8KdDig5wCgJvO6dLstqUvBRN1v5eRDvkwXXPrFjIMbsCmOuu2tRCTg
RafHC3SNS0DweUTH2aXUiNQaTeMEvcOl5B3eknR9wPJk1WoqBW6/GVHg4E5UWyykZFMxInrHnzdx
1szYmBfxCJTQZnZPDeo32PLPNQfeapW6YJzvw/z4QF7w0UEZcxdA7R6hU8hp/ymyp7S7uhhlUKrQ
9gueGaHr+hcCRwKlDunEmPJ0C64pN4Dojq3XOCPRKaAkyTfczn+3fo/5l+g1Qbxz9TTa3mAbAd8J
HNFMkQUdJegx3lKudY0xldAUjDIxew51B7nxs295rAdqEwjwiBgXCbp10cZwsOc9wCRqbdAMUpf+
+ysdbK0DmvmHSpJByZBi8VVsUqyo/BY0vqH84T0PS+7174ID2HxPD13cX/jDL1uJi52DZkHrDlVI
TlvtzPc4QZH95rpFgXK/AebAFfAgpD1bYOKfp73Z4ODNlwj0tOg1PR7KEc6cIDlkD42YMES8qo2g
bvrEB/ihO1BaVcBISRPzWHdas29JY00241CVPnmurMoNBedQIrROw5vDyzKkDfikX6fOdVacZo2w
Smf97zcEPHklcVSLjB94AOTyy3kmGjIgOLvKgbckXDeoM1GsgiQMT7lht5gblt6AKVYRgSSqquGp
5HqT4PbvLiP/2yVj+9L11C58TwqVdl6BZheD7iWhK97nvL4wlnZeRQpmPyXDS4SiZ+I46000c7dK
N6U6gs18/pjTHpjWlXY0bdn3lG7k8/rB242t7zQwWYXfiwnlF9ij2cKgRtcuHOz9/+K1mhuObcSo
7ma/OaqZm27rYW53MBzQG6fcNh1V7bLBcNT1/ZbYBSbWA/SRjO0RZm7+1dqNAWH3mZJW3pe5vKRZ
+Ex7ALHbYLwUIsxLfBTDU3Gv44CkyRneKB8QyF5LONB99kV3urg2UBIN3jL8uTrYyTLNCqJAIh/e
y6J9j86pE3ig/fLfsovu/V1Xnwlv3CSu0BrKOk18yRzk+RG62iM2Sd3b8hzKb9667lKaIbtpfuEJ
rxSM2ug7WT0myqbFDEj9/NzQs8KJ1mtHNbFY535PIj6uDoUUx3JDx426SKsbqW+yFtCKJPTJzbGT
sULfh0t9HCMSl7Gvrvnox459gyQ81Yf+qvMJ5qJoFRRpdDF7SaIsEz1ovJc/AoVE9Flm5xjsmakG
shfJswoZaeXeJeYONN+oDGB3WIRXILsAdbuXcYMkT1Yd2qidnuWitzTsorKuzhDuY4oGVodlRIPz
7tzXmJEEpcZNPb75VQKDhIZXgu61B5bBgnh4nI3GnhvpgqaoAmLO5/ETKmug2ThtSlU+Ns5OeAu3
3Ed97y316gZMnNKNKHvGNqwntiYXBjhjxgoaFAf2mSiRNgJmpWPW8qdqi3UTsHwRXbFhyLkVXEah
Rhszo9f33CYqdt5rleVqEcyjoCjjFPU4409FGMC+DUOQ6XZ2l7uhdbc6kxNW7ilSZkpi9N+SZAF9
zxBmzbrhbRCByA7DuUQACdII4WBu+khG1+3wG/nyxV4nv8IepHsW1nCwFoxuKfn2fEC9NlK7FjPr
U705xAUxrklw2t4D/AF60vsyKb4EtGR99s4cNZaZDJz6AmXU6hFRK0UT/oNeIlsDMoYj/NR+3tOX
lBx+tXDLEGwqwwM7t2ezo9YQChZGPmd99CovTRThPLbUJVPdSKKid1UsEo4QjeA6ocp3EJztLV5W
yMRGnAKeGHbUJtkmBwhbdgF1SpKE2VC0p3sTzhd12kwFsTB7qd/jI3osSsEdnobRTCyUVjWobZg1
1yw0Wn4M/p5uQCrt6O6CwtdruW7SErc9GMx/6M/8bFPZpA1rvKrpnn0M3780eLBNvJX8+M7ehP0F
byo4yRBwNxxLSO3XK8nFCbZeaCZ3gkso3LM70d6UDQYjzjIUYBA6M9yyq/uu7LzAylVL/PsPFCFl
5h+VOeCsVUyYNWUNQcAuE1zBW4S60B+Yyifv++Q1OONqQ3wB5wO2baE/f9geM6YI5Y3NasWkBr8y
8jLYBVLnqjpw9c9NguOhO6hlvxI0BoNOT4sHk9WS1cFoh49feUgXkGA5aCio8NiQdh75wdU98rpH
9ZIAlXbhbOESfhO4o3Tn2ZBlvizO3kvCvTLM7kuTZwNuqYar994UlGXy25fLGfW4fWPWe4MeSx4w
aAugbCDzDLa/WK3nr/affZjnu67kaZoBp2Qs774245jX7rLEbR5fp9mlxf/2zI94MvQYBIfcmvh2
Nj4OiqhV0kR1Oz/T4stwdIg3QVKL4oM4N3zcpkmyur0hKHaRFari8FDz6P7ga73zVEld+8CUqPr0
KrotB7FTRekhIevFgWptF9MGz1lhqcMgMIYeql3HPjvRF7SbCeHVugOESJKhNciq6MkD/22wiToP
EPh1dL3dOD8KyPkGLU3ai7peax8rYG35zXPAv6PF3yA68dZ1UYvL2K7QS3xynIjwX0xF9/BlRQ+0
zCvE7+6WXwh1GIdugVGDQXG1G63PcjMIYR7wR1UEUQhEVySnmL1QnEGL96ZLS7m+LqMr4/ix3h/j
ImOlE02ShCOvIVQt8HhEziwBxQqkXlFD3oy3XbNhc+8nBpzsIkMIRNuNdI6uc8j1JuIBm0LjpR3j
2SsXKoEEs3jb39Aef9KwWm0c6QxqEiPuybyNKTN+xgkQRVMlT4yRoyFjz90AUzeZ7tJV834cN+KP
Cwx5yetxVedIa9JCMZPtkkTWA/IV990M6m0BBRRPl+pUULPYj370qNsupFOO/nhu/3vnGwFPGCRC
IAu46A8g/qKCYiSzu5262dmTxIe8DOVtb64KoailYctKvaYjkS3W5UUsFlvmTNR6RDj1FrnmbdMH
xuxkF2Nbkjove1ZlNlN9sNztsxSwvMtMqJoOv+jVPpH704on/V6qZuyeKTQ3rnTVztsyf5+JqQEL
0BvDnJptbKXlp94B2gKac/sN08seVICfCOncZQq5XAXrZmxYVsB3NXDc84Pa2Ox8KvNDQMMa9/f/
lS+uDsDmySumMUnTxzQs116jj1Vcf+q1OpiA9geHnfnXkBvW32P7/KrIMnZoSNdJ/vhtktrxyD5c
Wax0I8BXb1U5MfIMCJ3UKZAevMrLIsQ4ojCQGk5tVMFSFpT6eKdw/KjTM7QkL5gCeV6jaT57fGH6
/B4Peubv/GaNOR/DXmWTS5lU7uDZX1GMuON6QFZatHVFoIj354mFr8Fslqo1WLtXcbXIE7iP/yJ7
SBoxRPKf9B8XO+JQKZB5aPWJZigkvrhczUG2BkmUne5HZJWpYgDG2s9DTQKZnmcpNXUNytd8HeVN
+wKTA/LjurQBVFVvtI76tFjpCzil/ffcBFfHwgi2inExjUKqT2QqgfHIlIU8sETSpmniSIG7vvdY
JOHBz7t75NBW934ZHnPKmsHOrV5HwJaUHpQwY8fVO/05ZEsXQgMh3ueSKdHHgVbdkoN7PnUkmk7P
UHc2RxJU4zZN2mJWvdOKOoJ7KbUe5x3Uk11dC28vQkF+75d1EwhcX++9u0LCwcvywlZJ2AIPDLGY
Yj12mLbCX+6dSNvqN4gOcQ+XI3jl17i1UsTPOSWG3SA+Jf80K2RhNdGGE/OOiAdyV09HYPxf60xm
lU0Uca5vXd0O6JIZfmFwm7Ii8by8OARnq1jK90xyAE97USjpb7rO31gP0s5526MS6TxyHw4cIuw3
P1r19LyaD2JkM2HnAehgijd8ON6rIT/YDQkLI61Y6kmlwTuOnKy95pK7Z1DQYloJzLuo9bEWLIMG
N/B/DVYi5Pf1W0/k+E4sqqITdEkI5yXu5Hm0LjWqlsP8TtovVkm+wX/fJcE3jCvEKkRC980EItg+
XNws8h0u/fN8/cKkCCVcgvC6hJKEJuBcqJXi4+uEHGut6jLZ3oa/M+jnMQTf0NiHYWQLsUeNbBI1
7iDsZ89ZIQli2I1HUdF0O/0mz9+elHe9qwtDAFz4ATSdFiyWQ1JXPcOZL3EgEo8x9HS59rXt3KD9
FxYwoZvat8N5/pP4q/MBMHauNXZ5o0e9aqZNkebJXWI1TusV4vFB1YzVxDEYpmr2W2R/1SrIGeYK
ppO9XIBpSYDKdJ0PnlWdkYKu5xBnoSeJNhamWAQ5kYlMdhDgI+Awg/DDTRqPiyacpsdF7NbYr4R9
xa+bOeAv1WwDrk8+Z5CwU7UZbYFYJeiMrCHL6Cfe8tVR9mvNRxCbJk6Dv70lJURxBZXfERdyHSim
vh/5LxNCXY3DfYAVjQaua/DDQzZZNsYyS8ThjcquNY/7BO0mD7He0CDvGJfFuIBNKkxnaal4k2Of
oiD2saqor+o4MSUwEK84Y+qEmZB18B5Bdt5LzgYezDk0b5ZfmaiQXDzvrr0ehKSwgrwKjBWS4y4O
hQXwPzbYMvU+hE+VN6TVeABAhDbbS4LOjzcBRuYrVtwm4Gj5cT0FvfAe85cuEkvADx+lGy9V1ltL
bbzGs7SsZv9tqAWVRTehtWmrvLyMz1mo3g357EbjB7KLngkILEc2flkBLB66eWiZnHoBUEQLfUpo
qXammIkwsjFd5pHxMp57NtGveIVR1zkF4bv08etPjql+YeqezxoOWyzbKnt/VW166q6h8Xnl3uKt
q3NbFmO34pMafeWppWEqMNVqjR4KUFvrXI/mW35R8Slsfv/oggl8hGHBHvtnU5iDDy7rPMQmdPsK
RmvLJ14i7osd8IXRXxrEYsYO4gSAI5hdIy6mdKv5/TAGOplskSMBvPMyhYis0zHCpvLdk/dkgBtA
WAE+HE4Zl/AfZzlXqV+vs7rrU+qDUgSuErzeA3NY/83GdiWnyuDFHj/y433BZpQ5DCZQa/bJ8FMn
NzFGf0k3dUvAlsW9AogKiMk7PTeeZWDp62gvPfkbcPefS0tVv1rKOMcNfOwmzvQ90+AbTrJt0kVZ
g9JKWBRqf1osxgoeTRZaxNLoK95wGjYMxj+9OQ06MIF7xubHRqzJdE8ING/MY2eoRRDZ94pAUtUw
yZiyEm8ox+6SeUkx3jsIMwwTBQ7fjcYe75X40ZLuTQzRkf/3Ns9jqG7RrkS97XskaHxcImC5dvqz
7n+C6hiuDCT75ko77ul9C5hb0nxcGDHnW3/LAIjjacYuCYLXTCdMdX5UTNMxTk1boQyszn3cyk5e
9xc0FlvCxUjKBGgGVwzB0YfTtrefzTbeHF0gnahZWbvwg3FyWzY0v57ZXWKYe05mhDWISGh41MUq
Kw8vjWlxkk6t0U44AqrvDEVoGDowhgg4Tn8qf8hwzPudCpWKF0CVbxJfH/GASRPBkcozVriRBQSx
6Kt5mwctXMZ2w01YFySOyxwyKG7wvMRMqt0BUhEa2KahV+2LtflG1TXQVFBxqg8+dABqUv0STtmU
bBPNR/g0/QSDA4R7vlXbzvuWnC/iSNhNe7qGDMfCt0ZL0hYnSSvRs69d/m4ajOwBRu29QREZDn6B
KWpsyNFH3g/kwd3wSHw/nLXkJFO1gmAbQkH0JkYjX1/MM1FVv5blHPO9+L6Na5swPiy6X7r7CVon
lQC6PzdyX4O9fsFEwkC9Z/SqzZpoYGfcMvSjipOsUih2KO+EFqTHkJ5fQmqWoDKP5yYvS3QCj8Ap
5EiSjfK1+eJVSPseBfxAvKAJ6g0JhuSwBu7Ax+jFa5hSqQ2LG58+TQUKYG1J5jnedcS2/bctUZjN
EPWL+mdTtqMyDXtuVRNN+xHOFx3foCjZrx55KG0onC3pd+KuP3xTzjYEsqyYPLTQC/bthwJZjhi2
Xh0Agnyi4Q2teInqYuw9auZsxtD5cCzqof47hMKPr19Q067XZbGhPsmQgz4+eBmehTzwtf+aMFZQ
Za/0wEJfyWPv/YZa0dnSmndgUXXVutoJoSofVvtx6zFTsTKnLfhcEXHBKgSUcai89hy2rwgcD++H
MJvutFFGeV40FxV/N4iUi2wA6ZmIscpATnsYlPUifhFsb8ZYivzz97Mhk6AGasesqe3badF2/sAS
yXXoMXRCkXOk6+OjD+H3unCOQHNvYHQL7yot5n1mvS0t9ujuEj3gqaJkjH9T7GB0c/Yluw3LXyfU
kOEnt0HO39TLPBGIOoIxQPCPd9Q4A72OhSh8+eYEYpc/y/EZChvWZ8WF/KAzdY3j5MmRYi3S766n
S/Yz9t8U2nYmsTVDC8ZX/gu4RQTtUTGSWjwMSAm2DjYYIkDpOY3zEg4aL827aTiJ9obMJNl7F/FQ
R5KWgtSI3v8BVlogXRp3DPHFV1EpJyP8Sf9CH7PETgM8fkA8UW4qD1cteEVxPECPa1uvJgPnlQHK
ffOqiqBCS0XPvX6DeIdaJBb9cRKbhq4Mkg1Trtoj0K/88IFcLZP6zsus6wk1F76IH88TTT01502W
5mcgLOl5INV+MGt/fMU9Wf0y1CneK1u8QsDMMooX6dNOS2QtX0SQ8tfAPkNSoXmRHfuFQxzc2LNx
P5LmOZdlmJ1UBWbmhgjQubEMd8yztXTTsZvV5bLc2/kL9olClzPSbPnYNcdyzdL4bGTtjdC6MZPf
C2tK9/vQqlsJJn9fTQ1bRbiOeqqI2afhloUvk0JR8Z7HzdhF/3v5CFRTUx8MpK8At4+lypAa44z5
kEFhyUuxfKpuIz/1NsQUZAOmNEn6JYtgLm/BqH7zBt/K/EVMP4ZctyRrOLuU69UcMD9zVpl2y5KK
C1f51WqubIyWx6jFuREwRapELvcThns8z6Y8gVISiB6n0nN/MIN5kRSKYaG9w5SsFEfVbLbRmyHK
OkoYYE/RhUWJfb279U5w0dzDQfA+hPzmz4Ez7GYm43fjw3nzlUW8GFZ+/eMMqWuihEu0PdJwXPov
kn5GzJh6cAzWqR3PG3EvKbDhq6yZj/2u1GrT5Z7PRXMJwp3OlwYrSrxjDhaod+ROmkrlAMbePiaj
kL98guinAzuAuNNgx831X9hu2s1qG+x+yf/y61RQuXRjb1nciwKEZoqSdYjylGrYew8dOYP72FUs
O1UZvJMH0T55/bBZJT60+7M9xGdRx1xeHWSEYsEc7bxdVD9WqUDVPaxgMan3AzFyziixnUlsXmw5
pwBapOPG6tiN7aB+9PBCqoAZ8OQtmu5XAKjyAoqyLNbl7KdroFqPeZQkM771uA8uaW/5PBZBy3Jl
etNFeIELiZ1wDBPOZYKfH5sid56vMGQmGbpFxH8bV2krSfxkzNZewIp0YhEXoAbOCZ1PXzSfpB04
VEwViUD6zhjviJ1yGgDK0I9EU++iGLSO8n8bRsWN5GAAIFw3m/sSSw8BO/nwJcCkNIurMiaWhg3C
z3OP5VVEhg66uiNidYViQ1wSAPFFG6FMJ7gzDsBApA1P9eFur91y5emjDaXaeGAA5gqU/gHdfkzI
8iWe5r1uE+CUusQky5ESqz13Nys0yPsSTJ6I18+6oA8fl28mCVenL8fvuRyPzC63mkLQj4zpFUCU
VSFEFDIZX6MSkK6mlQLrFnTNG2/qzCyrG629buGrcC3rnI1T6YEfgXkxX3EBg/erBBorkfjyxHeK
tsOOLWlN0slx4KxQ1jxrtbDBwrVrOtdVsNJp3pD6eWTPmqwrXENYT2NwfjRaAuoGm+2WHVfRuPQG
XQEllCJRrIaX0HJN1BAMmu8Xob2+1ESZV0kM0/ehjf24Z0HnXKssHcaOIfjWsXBOM+KNSACMBp0Q
SC135rLOvuvS4jdXNKTmw2eqArOhDf5hta5/UBz89+wY46CV4VErAPS8MgRNJq8RH6FxV6kANxvU
1T3H8qvJjmtP0s327ISyXCqD0NO3eznKYDtNAhSkJxxzwSyRC+6mF2sDJvNqWpMe6EVs14u4vGyo
6fXCYOyG1+ADizPfCx7rbHKDnOlqV9t1Tv3sc2mPE7fh0793OYateINEXTJyScsd7uFySyC/Z/b2
JknB6YTzVfbfNUnytsTQ0W97zd6Rd7hgKvX0Y7Nu13YpZyY+YKerx6SJPr3vjCEM6IjnCUscAU2M
zdaATw6GhbcCjWL2J5zyaqcgYc0eJhX5WBnH9YlXJshaZQPJlRoGabfRnf4+uzcpeStDOYgCPajN
jVwjMEpGVW79My6Tn2GappKL/eY0PRjpkpTLeE77VHTuy9DsjYRdfWiyzMVI0ovgaEJdAUaUgcyy
/ipAvUc57Y+W5VYnUaX9RaqoYtKgX6mm5yDPRhS4L+s4DvHhREyabcQNcdS3A1ZuovuRWcUUUSjO
b1PM/lgzcgjrv4wPlPLC2ZvnUO8sCSPUG/7+mGohM6EUTnNg5FWhe7LxziZZmsMXwCfek+J+asC4
Vj51cx4cFQp+zde36tNnbFIoOCrCxIa3lpe6j26ukTi81Sh5ba7y2ymHyJPaWKDlCii2HSYmK9vG
wU/24oB992EUaYb8tlJbIRRT52Y06VUS6Z4ZLH6TquKPciMeu9701oTzs4gTZnX2jSXebJRCfYv1
nYg2RXtpWuSEP+sSQxGJktLdvlzoI7PweFy5Rt29sNu2TpgNzWJPwZku4e0Tnly60y7DaxkGlTuc
emKYP5UEmIO1DUbfial8XDGoPznA8Bgm0iGo9aQvZJckzjAHziGdCxznTvEhtOtoiANmuX40YKjJ
gEDV34v28R2XYCjmoyP73Gr+AWM0V+mTr+ptAGHO/DnHVwCS4/K32fHlNZLTRpZBkeIbB5T44qGn
+Dp4xBQ2sYvXYJjWxMeE+y0ZHtWz6a0clBEeT7xt/XoEUFJP6reV+R67rUDHeT48sQuTaiGgDcXO
fBd6Ma76IG0P7yhqB8vnCDAzpnAa3P0TNxqAf4BhpVY6HY54Kv8CbTqX338egoCwoWiWuoTUQ8Hp
uWjzd/C9+/hBAgiTqv92eM8vCEkHEpJVvIHYNU87X5FtaEV8/Yi4jdF6wsMeCbTgGAnIkUMpIp8z
/TJTMcECfJ6bGRaRnh401tzV3rQkZ5dNHwlfTejSjMet0wOX+VjMGl43qaONFQfZ+QSht1+EQ2NO
kjQ8LBaFkPu9/vNK08s9lKylv7SOFDRhRDSBqJusMzSDbBML7ZDCEarG1qnn7BYf13RTNk0Li2qs
hODwd+2gjNiuh8+FPCSDSUneDdTV2EKMNDw41VakWCEsRfnEaXyToYV0+nM2F/w7Q5z9atozphgA
3h8hwwDzpzb4At6ilL9dqjLMc5txUJFserkwaj/nxWH0CCkaI5h1MWbWHP5P65TgrYiburZYiSjf
abtknq6yGvR/CYk1hTVXjqn27SyLCChg/JofHgFaYxeSkktjjnCv4tHMktVyKaVZWz6Swl8Br8Tf
4qXQzwN21w4YcB+rvNWwXiy19wmhkNHeJU/N3P3076+HsMaYHiL7HBNV9D9HUIMhcj/GWAYlZIQT
9j1TbKQVux/RS2DccadmnksexTosuLKTjQDXFOQW7xTTVSCsw93n0lieelYqTOtPTnTmFR6mdlzA
/cX2FvKD5h/ULRnHViY3Jf9DgPL00jyn2G8OadwbreAvAnsACbUHla3LFi9X4AdLPoFdq9TxtJ6q
8ipmB6k+oUAe9E8SLBVkcqB2B95MA3H8kZF+eCv5jbHUlyZm/LLVS3qB4fIetJt4GMm2f7FTDuor
eGB+V7ugDordussQGCZCmTKRGTYguIKnROdslPY5ClqQo2tlNE4TZc3aYyYAfRh1Ik1qvftEttca
y8txh109msTOunRsv77itHgPgV72/IqjqN74I6m7ijhkhITgV6sxoKQayuftcSKJn194Is8cgnrO
EWob2ZHTxu7dlOx6VWbP3ZLIZgJvDcUxJRlqSYMorK3cd6QKetnRukRf+vEvrMDJ0x1LtGvegLEB
0LevxU88+XqaptU2UturRGat+xzOsbRBmfG2iVRGYQxAKsAoCaN1npgx3fePRHqsX7XWSvfopLTU
qCJNMzTX8CTiFmhgLW1Fk60KqMZwwc40pd8GZqcXg4s3i50VopSeDlATvaEYeO3tT3JUVPnAPKFr
mR9bUUXZq0TcvbgRD4KnXJcU92vvZNgIAP8iah9kB+CXuU9TwOJqx40bzSHSO90+yypGDZwOgI2q
eUC1dyoImG3Zb3JMNi7Xah9r7Pu5a9Orw/TDPgOSU4ZQAl6wRhzFSzcbO1QwyEIVPlAc0Nk2G0hi
0Y2Vyx3q38qhXTURt+W2axE5jvHcMmB08XuASoDb7XE4JJ9UGjfTVd0ihpWHctUaXGakbmSrYQyK
X3wtnYF5MFdHlwrTyUYeEXymtywUpbyK9Whsi4r1IRl6dpzomylSvKp4FCw8x0hMQaS07WphFefN
/VvJcXDitDI9TFguqzkh1IFzFPFzrxI3pwfo4Xr+VJbQp+ScwE2J86LN0WI5eSGXArtG7frL4Hfr
py/NiyxlHeKm5QhOj/lROYMZLlK1GKhoxCY//pw8wMSFYNFWAkSr+gDh8Jy878uXbgj7vNOMN6o4
mPu1RjACi1l8gmWpGMupRasz5lS2EKuFkp6zMqbzC7CkrlTiamML4M9Hsdxpykv+9EU4+0pew3IA
RhjVyJN0ZdcBirilkJXuK9w7I4qH75v+dq5IMxCXzRhQrfYI7SXouwLjQkYsf16DT9Cg+bNfzEnM
FpisIUXcWMZTG/ftmww+xaHnLPLboQ+2S1R7oFFfEUIXgXdEPhuz2r5SbtOiI+hiwOD/DzEWMxmb
zjokF7FjSexz7hMGrWNwSyVhP7QHMNZQRTzpELW8TmfNBVh5hTLOpn1tnbh2Cse5Am+duMG6e1jd
J3YUdQtDwevJYIXdZ+MvK4fau3clxpV4rw69QZos9/e7yA8iCsERLsfRr6p/vXpWIh4cojQasLwc
JWVeI5btCHpspp30HfPE56KDBLku/xan7dod7cSpSE9mmXJbX7Bj7gox7n+viqw0ILK09+vF2R1i
hBfIijrMaj226jiz8tCwkYiG26W6nN2B+DP24d8VTpml9iqGAb8E2O7l2xa3YUMNRW9b503S5TaT
mGuYhe5+45kAHczNOy8+CcSellMePJjZSGDSnN4+IHKjuS9w28DLsd/yDcMyKwKYGU45LR+LT7z0
MhYrXo69GlMptr/CldtimnRkv13ZVcJpgTd0tEkNBgQp/pb5OClMfET+NFdqfk46pW4S6oKSxx+v
Sx4EdtdZQpCDLGMudlVkOmCF46diYu/7xCj1xe2uKykjtMrEnW2l5+AlPzH3R+opCuw+A43Wkf1x
BFQIdB/DBf7Sjo/KHgq1YpcZRKxsqMG6Sjy+NxgyqDYRZm83GVHSgzdzNVeDNWO8K16Sebhb4waG
bj72DbAuxke7xxcIgR4hfSV9HNh2Feyafmh5IwZCTAeJ8paa/9y4Aa2nflDqtjuw5N5BkubCu88u
LQWkiu/QdKxcofK8hnMmU4yJEP37c9J+EcCzVYKbBjhnkOnox50CtJVPE7AGMKCE3TtWJDu6oRLV
F8bb+whjhmj9iDrkSgUgiZoxavHIp/viIR0jJLs8jkLRzjbOMT2v+S0SaKB5m2Kl1xONQoxzlNEb
rS6nuEgidenwKP409LsuXJSl/rbEFgyHqaydx807gtu5zA6FcEZzyXdcnkqDCX/bsxZtjKAayy2p
3cTCtAd4s0qh3ztQXoV0R2NDOa7ciI0r/9EpF770TClIAaRQgaTxqR5T4qm2SCc114w9eTyeL0sC
FU+RBLsyB+l6o+ZrcZqd8pG2lXiOIVx9FRgC3jSMg0GnKFS6DncjiREErl8L9Fl09JeYkZVjDWy6
UdR3HsY2TFH46yuny96I7SuqFaYyaJLj+SUuaS9Fe1C9WX/dusbPXuN57CNbDkFw0SCx2Gs1Pvp+
8r8IariH+qjKaUC3V68PzBeNVaDIXuLeXXEg13qmh82Cs4vQ5moreKMpX5HBo64w8T4skHaFT9nM
6/U1w2QFM6XHQmSeeOCGCWwZFUForND1/UKPLuA3MThJgQxo+d4R8ABygMmbhzY3I9KfW2usMRBJ
MawYmvUpqgusQ3zjeeEBwN5zlWlOnpldSsItzq4lM038d35108rRoQQsJqyKDhxVa1HPgGgCgJrw
X7r4vgMQw0Rzf9tdIFbdh2VERapmvyem4JfmT5iB/s0yqrqO+Pr4fVIL5zmEw2BaRAZ2VYlg030m
jpTbmPryRt+qC+v0bnjfo4U5akC+4GYrPL0CZ6tBMS3/WADCm81lZ2qttHtmunlQqoM0EjHufci/
1e+a1+KOaZcvbd1Kkzv4sPDwB6tb/wFMfrrZlyRVnMwxeEmh4fCPFJeK7nG/F3O1Vj/SXVFH3ffb
HOkrb6aNbJU6Fq2Q7JU9npKG88OKZkYsiN1KdnwaC34q+z3MWoroVekRVmlvzJTptVZbLfbyTKrq
/vSPkXCim1qlcqrgPjSJoTCSC+kL/5XhwyiX5bAUlxBDDfVD0N6SwmAhKx9tZycGkUujUm4J+TZ5
FITbaveqBLVaijDu2ap2ee1piPiMAisrwQZr1CzqeHxyTk+PDycE4a+rvR5LO2hf34Xu+XgqUD8/
P3Kc3JjgymRrjnSczx7ytbxOeHdyVzlNGf5lM3xbohW14Yi0vwvBrHvCkNfcc8rqWWltlhHXIrxL
Ds2bF4cAPW7IJBQYzU9EPAuehE489n6lZkRfR2IhGrdCwYssruIOnML7szUA8Xb+YmOU6na4tpot
wSf5xSF0FhO7etzJwp0g45JsLcVS6AtH099NZvYJh0NznIU7c0iePHG+wi7BcT+q9YxSZdQETXp4
Woc346/CIOEqzrD61YYsNrVm3xndpe2nCjuH6eOVGp3dTTkMkdPUE/CQyQ1BtCqoghw3VY2XA42e
vbdPk/98D5/dE3ZGrXuGNEj8ugaNRldg+lQnKGXMfhGct/7ebPiNTiw+S9hKTzDDEkjgjSnYNU1F
mJtg3PyBJJDGrnNHocKZeClvVq6ggMxu6UDKe/xpuIDKiNmwbggFDxxtzF1dEDVRREp7vZ8/ORgW
+AleHHisUSv9d37W6b83LvKd/12he5azlbyrHcz+bqIKEN9652xfstRN6AkpHQdX0F0WOd9hcl/H
75gLgJsoHUOwdH/0SKtGSgHRaBjheTecJEzWHasPBFsALZ5nb25QekV/g8MrKj9Kteuqf3DPIZb4
RbkGEe/zr6FvU5pddKaCh24eR5+6yNXmK8V0N2kVfIKVZWjurnk8vi2+21CfzIi5hqeKGcvT18w2
6wv2KthxXz3v6gbiCaf/+VUZyPLeHft3M3zc1Kl3pFDetccnJzrw6oUCX4Y6zR8cdfIfOr7l+gmm
m9PMA8CSRM4a2wD8uLPRP7VxQgcWkaOu0DI9AHf18CpQYdmJOccyXE1lCQTdSGeGdNW5yjE4C1dJ
Gc9k1DLMeVXaQ1i/WfYivvmx4y3lbzvxXl/ad5pAW70DM/f2FPqPvN6F1vz0u0ogneDXD2LbOpTF
Vo2Wgw0E7hDGNJZ53z2ZG966kOJYkOJ70FMK4I6S1v2SDZUAANdwwd8O5J4rT5kr8yLY+lTzSpU+
8uiKVc5wc1UO1G01k5v7TgGzNJG7NypjLqvMNitbRKrglSd9PdP5bF7eVW3Mjx6/uDgfilE3I+69
tNeObcVL+dWT5QBw7j3hgNZGAVNH9R5J5Kt3Da3OK2brHRcx7tOq1u+4vWh6W6BpIAIwQ4qqy3kh
0xJmpYm+XrliBy6Hjp7ewaAxtzW6HTq8km7Fvzo4Jq45xkTmNQHTdmZ2YEhfDk0oxP2PMKohZK5B
mxK22UiTxT+hMWqcNQgZEqLZ9+1qcJa/S5XFr6hgvWbZCiFh8X4pRX5+pfVl8fqAhgA+Su4OJL2h
hDkE9wj4+IwBMrNrP8FVEW9bEOzVvR6XWHDwbCMqXwWU0VfjV2gujScPA6w5EfETnbwgT4osQsBE
I9ez8SmVhoAG02VfZYu/GECSkZiow27l+m8928g1v850OzF2gPSxCypDef1Dphh/S3H9LlmG14FV
cB8+GMfXpJW5+ZNtFw4lUfKQqIDjCl3MeEZldMeKprriN5u00E0AFKM7U9Njovdys+zFwaqGBDLk
3Oct6z/Vjzbl1+OpC2T3ny7XKhwbbYOboiWzX9bYojiLwRZw1uV9aPIH+SYPhHueR+eOzOOq1fuT
czZ+X30s9H1vDuIsiUaMws8hQHVrFlJUMGRmcVaehHAEBK2CKByHxK5EM2voLx6dXSKV+y0KUJm/
0ozCZEIyf0cQ5se+3IIYCKYHhyALgD5dBNfAGkB3yPSSGQhbzCIE3gvurtv8tbNsjGt/z5bstALu
HFViSP8MEadFqFDR8nmIZUF3w+WH5tdAIKxdrtwyKTWhtG1tGoxJt1r9TaprwHHsDRgAkzi20+7y
UfBRqiTIABlkt4eggIhcjF02fgy1yPY5xVVnGHR/Nkm8VsDbX76RPxveSG6Othm4kpMuMDQaI8Np
Lf0MQQUegW/sWzTF7afB8D1ofyxGtTluXvJCKbktFmVFtH1Tvv43ESAsctLGaDfR9ffiYu72yNh3
Ohishk+9XBmEDQ7s2xccsMcttil01c6RZSvZeaSNf239Mn9R/7Xy2M+I8F5lnkvtAUZkFdZakDSQ
MNosmbocR/4SJN1TxflO6SoOU2ZUPKBwQNdNfi9zNaVxKfOcorBkKZ/+CDoWtXCT6EexfpDRtk4P
j6F9DEKoBSFipkd2t6MZr8XBT5hZcOlBMGjTf0EVa0QE2kZA5byN8xGoq+5bWL7pDEvGaSuiHRKF
09lw9UR4sZV2VaGsuK2yyOAamioECJdrgvrPk36d2dfua4pmACZLVip8qaORuygmecjg0Ey+9wHx
Wv0qQ6s0ijI3+Q/b7wNpQqDAs+E2w0hzKq1yO/DrbmQQYQpbe6coX9KdzTxWupYcspdZlTyclzab
1DK9GZZN3q2ZOz2rMwLyfEazkgoayPu19U2SAr9NwfPmaoGJN91kPWsRF7Dp7raf9hIjHFpRz1MY
4AUUNnl6aeH6a9HhUKlFC2w3bHV/LD9m/wt2wdMYSAy5I1TR2hL+YvAJfE8TtSjHx2lyXOnnBbQf
v8ZlBSdKk5r6I0sCYlYUXpPAby5vDUyvN8jig8Fw/50y40kpQUV1yEMyL+D4PGuV6ghvhlxRy/kK
kdZBe/4JlhDRZJueLjx8RjOX8+EQEmg9HexZl+eLaAwCCqPqDYlw3EYfenSVLCVEXePTuaaaaD+y
emGD1N9WBFfomHdLjY6ENgzo4B0IdITzCsO0xeRVty/4XBdWXIxoPY52RY7viS0aahV8hDfm1jJL
MUsDDCQYCoTiLjt7b9qfsJre3KEm93Shj/At3uG8LhhRJb6keEjMM14fxP21BSbSHfB3zxu2FzHG
pmhc7CBMFBIXFSGSD1ThrBv35zVCGZdOqPEl7TDquNRdkKANjK3sa97Pb3Zp7xDVc5SzJe3UePEq
TBlIz6J/cYSh/P/XAFRSEOVUcuPCgNDAx52uL6zfKvLfZXi1hXLb/RJkNVdY8ETMHv2GyKSxRcNz
axDMK3/rslq+jTwZLQm6+B+zREJ+jwQqLoMKQOHKPTb5OA/pAkkP80C9NMJ724irz+nU7fVhqUGg
Ayl2vxveHS1SCcF1DfEyTk5YEVPp7z/nLiljOXElVv2nLauBLKyReUdx9Hs/itNwcFnBwO4G10S/
3e3sXT1wkRPIPdcZx56CmuXLAhjyFx7mAXRg4i0xxNWQ+fdu2kLAfGcFawx3TjtSXiML01/gE3t3
/snn8YfUTrUxXY+5TcUUiOnRzVHn803n8fqVgN9Yo38h1Ev28NbZGNBfnTzV61O9BL8nIiNhfB4k
9Uz7nvGuep/zvZpCmAQ1DP3Nm5+FB9ttLbupjO8/VBsxF/ZHYcy/6PN6iQ+E75drH2O8CUEC04mv
8BWtMKaZHti22eXvlp/W1akRL5qhDIJ0Hm2lQHCGTFZTZD1qBuhIqGc0TP/lFP0X35lPp12F5KL7
CWGI3tioVomKm975uo7X8gx9SgYtyy8AdNTHHu2hOZRIC+AidOtcS6173ugh5OoZg2A4ERTHUP/I
MS0xKFi9x/JAqdovtL93jFy2+ddrbaalg0pUh85uxIRrl/M9DcnZZdsVWOCkEpZTDOEe3Su2Cw9a
vTK561h2YXwJF2xivnKLfP1RxDpSDlBE+9hbr7mqfr9Xm0kcI6AakJcDP+wH1xVNBIFcSxqIIhFd
IcPe1a3NbDIkxLzxC1dSbbyvKTkNA8mTuOnwBOHt581LhFUORBcVaE8lHKJLmF2tylP/VUzDAzMT
nQxMi0Q6Lb125DTpA7UQkAXJUkWizQeVYlfzvYCVTvt+VoAw2dOI+FSDZRwYwWYc4ExvJ8H8GtaV
1c3TRxuLbUCmxjA9bu+xrb350SQ1aybayXvmwwzCZTAZM+6wwpM6NOWNPoNwKzrZDOoIeCeohDQk
iC7IXoZKEO1D8/VGt70S1pztc4q7+hYrNxsIiCQYGF/c8U6OCQIUIqnPinH9VYrcAbdbkHeMstfU
RHcDfgATw0XV/LePKyGEhzHxhgNxicgpjDTQbSRPXsstEeypx73H6nRkCRxvBvzwhNhUkd/Bdk0R
/qd+uu7jnZxz1xEFFkMbwJjpPHObM5Yv03kiHLlcwNEJqrpIc9yrjkdBmiLA5Y82ZUIyJdXCRGQ4
jaKIoJknZTagwKijTTOkmKQFy7OSttmags7OTxbosbMam1ssNxSjG4brRwwPV9RQpAQUAayXDbZm
cBvOvXRffvAbp2qlhv1q6/tIizeqN/9iFwfEzVNkZCyOUD4Q2tcMgeaYkAhVVpCtk7+VkTziI7n4
4oXh8gNhEB79jISnwW2/isTKwFS/c9phgigeABpzR54E7GKVuPeyp0KrtilVa91bN6ucDokQ39lN
OgJo658plM5O7JCqCddQ0zMkREfxMrtKuJKBi5P2q6ToCBo3eGageauFCFGDHo+PdKuNlFwXQ0t3
VDT0erhQ10ujFjXljVkHztiqQ7WBWxbJqhPxsbsL+7rGQJ9kO1b0UUQevkQr5G0x17PerPDxyfPB
rkbyz4vai0TPUloYnBZzVx+NItZgGAZIzEzb0Zgrx4pNyKjtBaqtmwb0HIMULjDvtomFj3NNTym6
iNr/io85zqvuAKipGM0grZ2piyh4TNalNYDcC8vi7FVkB+m4mPohJLYMXHa/ek/TKI9TV+JEq6xy
ahd4v71w/iCwXRUB7NIOM6mfvjcoKkxfpasmBLupz8/1+4tIM3wRPVPG1nBkCnqYBkPi9bZiTx/P
sYmmpLQa119oH1epkd5KGsLssht2nDH6o7FSUiQmxgKpYDRD851Xgr2KqcfSbqoDkzIFEVZBOzru
zAEyG/fiApculAe+KTN16bnt4NzKGe+McUv1/UAxRMRd/IyP1M5IT4lPt+Wo5OTXsI+Kr43Pfu7X
ptuWn27KN1sT8xSzGTNZBQkYyUPT3E8Y7f+Dz5TNhKRSmLV5H7G7/0ZE71/ilBkEUWBRO5Wc85ND
1cw6mJsMyfENhxQl+QyfMG+A8Sh4kVnVJS6gImyUd0BrKtRNkJ34Lh5nurQnUUawN/LJZl2k5Ww5
65FSw+kvidQQtHffPAVAPotD+P2tJ+FCKE4sXovNfe4MIFonQxfgS4fBfUm0jSmKS6DL5kQoJw2W
xTpJVkZQmpOiy5id7OuN4Dj/y8kcl5cY4D8bIc6ETD7XryWgmWZZymSzfhVxGoEhTd1Mo6ZlPyhV
ntYmkIwVC83IdxdO4MDdW1VYcVqdZUcuKvlRw8k9awYFYBFpsHO071WwbdITCfO3BNyeqQj2CWlx
sQXa1kjC4XK0qQ6O4i8/D6mds7Um3yAUKPKCYUKIl6Cr3O/umvWJCmDmH8ikMr7W/STBZi7ciUd5
HlDK1E7hEwx+3eWEoZyOMQjKU+65EzYf8NrXQZH17Pl5IIBL/lh9zTy0G7c3ThL5BaTpsztgoJau
Suz2yEJV55jDpTecr8yw/5PBeEnKmZ0haAQNVRAVF/5OyuZ1lpiJxxRM1ALW7Pcxvzr24ZVh1dEk
7Tdje/m6M1BHpfq/syd6PHwhDBFIv5cEp4LJ7N7r8NgVUKtcSs44PvZQxKHN4MBG8ETp0Pqom+Vp
jaKB6jq3C2kS0PZtZPAs4svbHfSzkmHf4ym2Re1RUrEfEG2pUoCyzM8Qitrifd+C/gI2JNyAF9m2
beLL/d92qRTO4iAHv5FNGx83fKUlwH/nfS0G0KP2aBxf4xPLdpL3o/i0FamV1fwhD9EDI+pGG4Ep
rRBiZIHPqUTpyLYS8j0LqWX5mTWkUfr1Yokun0zuGxRxCJhx5LLuEAZRwMYCRo5Vb5hnLCZsTGbx
51BsyHHNzaoZLxVVNLQQkIWQqpi8j1npi4jiFRqKUTxx7PFh27fPGNuMbnHcHbxLn3h2AT4SEWs5
lEaAS8ZQUtxWB1Vot4F3V02/4neo5Si40pyG1n2LrwzFYQP8PFwl6ph5qA4iAAio4tbkqbqkJ8NG
87dLFq4zNJLaNTg2jzhwLhX8uQBSFlegUiCAF3+ZuCNpSWG3biAH4zH50jaB/xbOYAuzibTL7K4W
6QtjMP/7zbAM7H2m6tSHnrQ8sL8yIwi2GgEEfWK729Vnnvi5mV8CXiqAQzxmGdDaX1isMfEoLOKD
oBD51f6aMF0Ktv1/HeJaMpN7j5Hg3mohm0P9Gz6QvQBlRzSRCup9NMbQMe/eRtKnx+gVimS+0WzW
bHKSYKw+a3Ji82qByrEx7ralnM9uxR9KFDRSC1qhxLaFPGRZCWXSNx6i9MEeSjFWYi8Cwy8L/KT6
QYMVSMuR+b+JE6seyJrtkn++fZwIhADPhLlk7Tso4fwzwhtIEgJZh05Rf7+5fy+l0CQgnLA///iZ
NSx4aIjzCA4WsaP9nVFp/hZxv+g8sqnS57yl0FEqeeVfKSfKWyqrtpHGAXZLz9xUq0QF1NWrSX1w
yGIaYBvM/9bwAkla+B+639W5tlV8LU10zrsYy+VMCB5RHqxbqZSBc/UVGXxYuwAoLEdrbx2NWIWy
XMAaCiWvb3ZNz5T0ycQ5+xTnfCJ55Kw8NS8j+N2zll+dG8X8PJ7koFOe12I1LW1oRhoSA9Op+Q3Q
ZYTwDkaJplt0WQB7jZIxfVo3aeMccI8gY7VwycKdQfYnJ2eY8ZdOAoAnPUAw3DZ1uSjoswjT336b
zrrz2VdGvDalq/XMqTbmzpy5MH1RuB0XHF3G4Ku2KFlkTU73IEpxEz6k3sOXkTXBkGdhdn0x3G0m
nduiqNcykDL3QfJwSchJq/Mh9thzLJbczDuoJeAD7cHN1mcwGDAgHmI8ZqiLhqcEOCrwyMoKa7UK
KqiprmIQHa+QMr9i5Zrf8Z8LvaVnY3gUoQI/M7oF7OfudWl9xgmlhaCz915YvioZfOPXBl4yi68A
W2J+qtDpHBpL28mSfgCGv6MWSF0vfamJ2y8Qk/RfGP/UnhEzKyEGAEZaX0izP4P7sPGX81D3UUWL
tvYVyug+3BP984jb16gAVErrHLzZ2iseMBMVKMVtTo64krX7xF31wDXVxviVoG3IhdNvlibA7/2H
D1JZ4m4u5oWsnXd5d3jLA0Qb/q2zyB5o6/tYDn/pS6i7S2N/lQu1bcj8GTm0V5BNEjPSOi6yov2R
9Wj223qajBoIAhEra6ep+K+yBip5pKy89WjZirMA8e7d3VjrHAcANCbA6xLAnnC5vxcG/Zmt/76+
SS7fsDqW+mcniXF/jah2CCg9hnjif2YPwVuLzTbqkcF/XaFFUrOzHwKH4pVwhUZOaUBeLfhl23OJ
qjqSGeZ1T1EUNysVPkV+hw0Vle/GYpAYFQhp4QyWtfZ/X/lZj5+MCt3NksGP3eiMKjX9UjLS0r6N
gcLREqN7OUctnMoY5iMcAOdri/knjs3QhcFjwPSHzky9d7pgUrjDew7g9OL+cKWqtocL0VbvmADZ
Kay9An1HmEx09IBPo/OnlbODOgYtl5mibHjiN4N+6hdQNMC2gnBAIq2mjbeySSXIzsYxuI1sXhA9
W1m8yPJ8dfuH1C6VVAqaGTfzrYp8/sSZozcvttZV9pjUaJkz6iVD+VaiS4V5tpHqQQk/SwMvDm2O
ABp7ZdQ6PhjRCtnEPJu/Vh0rlujmoKWsWUywIIoru2Zicpz+uPDM3LLhtxk6o9IPsQfQ2syRV/iP
ljuA7XstBB3mHsNzqqCvaidzPtUKkCzhVxFNwDID1vpzzukaW3Ye6D2hgfoBu13hxFMkl5QAkHKY
hX9bOHBuATOhK0TtdofoLitz/CzTQ4Wlacm54QZKRGmJjcXQj5BNUa5AjQzqKuAtFIfJVLSQx/NX
eWjbssfE4RUYIumLW0bRXziEhYTTsPf+JSNbgM1dMmJT5t7CD/e5GfImX0FPcnkN7PkLBtjNhMVV
16TEHBsXSOquKwadcJNyCpQpuKhWbGrDbP7npACmL1yaL3qZ/dWvxSwmOP89snlx0FDKMlIXKGKa
5ie3LWotD8E2amNY6oTSM4dxidu9S8d4Fah48RrtdaO1YAJ+w/DvLJgJF0fJwGL7pf5BhgLWU/+S
RJI/vey1QpR57xWv80DUtZb/eWnQA0COoA/mp//7j5NzJDC48YmTz+Fxv8hh4yB8S7727CYLABGi
q9znCCg9i4kwHfKzYRs5wNVwocwQwK4P0jYHplrkE0SWknhGlDdgC4deilwaxwIQtgB+nlSs+AKR
yp6Ep6XkTIn/M8+B+DGrpcZ/yhHI6sd59pPDu7Rbyp/xd8A4QDNTq4sRR7u0sk47fjVoCnxrSuwU
qgWiHhfXoUM78iXmmuTthdkBm05q5S3eXciLQ5G6spjzIO16vxCOwrWB37IDk9SgxOaXuT8lC3bk
f/iuNvVGfO/wOOUmwMbIXbP6SzgGurTrEoPaD1zFCZdpit32OrZfpEfHCS3somvmgnvUUqjX+Cq7
QqHd7IggEC1/Juaq6V9dGfg8QOUF4dRCh9+eS6kDE17ojcCuKOTJmqCUFL+gt1Mpg9+/qIUFYFfB
919YC8OT0Mu+u00b27pR+ej4xSL36KczIw9kJTBE7ds4H00vT3+lbWV3JlSEUpHYOnbTh6y/KSoY
JS2M9WH5ZV271pMtR8+Zb3CV3N3WtbWJKd8jhdXkDr1xIw+ArzB0HgP8dNTfYuoq5jP8d11xl4xf
dxUznJTPeMFeIZFyh3v998rEAHdCoVXjwgZBUBp3mu7FrKfU24Y/Wl4sg4rxXIHYY+QDKFX8u/4R
1S2iQjGrmPmvpR/V7nVjbNuYt7JCkCCxh3Zk0ZpTstcXzOu2qpLbs6c3Y6r12PhERB//NCJcuP52
RmrNBXb0+DPcNdtuno/fQNb+rCtAYD1Di5hQUa+dU7884vZKKRzFdoD8Xo3/NwUrYPxeD5C60xs1
0QE39OPDCgXH3zzvZUW/jpc0OKqCgek1HMMyM6TpXoWSPaM11NmZSjOCrusrdVqihHlftjt9DOJL
4OCeUXbKm0K8t/nbg59vjNX8Z0kSrCxO3feff8RgSXpKzzEHdt8tlRj6V5t1LuGKsFn8k1Sw90Cc
EPFyWeBaocUJCAbTTedH/iV3NFNSV2yfqwS0Eu2QvW3qhJGOvyPZ7AkkucfsDnvgmjbfdLHl+wGb
D3qplm+nzajk9WOokVsgMWrId3VMFRrtZlpwIUbaRBC2Rq8419uo6HQa97R3CeVnQ0tAPf+shJvm
Q7xtgnqapBXkEBbDA4RTEs/Et9OerOho4aXA7D3l/6UsF6irCa6/Qtj6p2cQ9Mv8v4SpQXS9jyp0
gSUnBVSwfVWKQ95qTxvwikO1IlUfrEuk18p7PV5fAPPI82dzb7L0RNtUBEazaeiOtzxJG5DhU7G2
B8pPK2/CerlrcGyKR+QmJLnw4Ikn+XJukxKvpz+WUZfIdGl5GMkZ+cw1TItuTZU/OFO4cMptuUJ4
MK3CzGqaVfJmDTCfxHji7tLzhqu/32AfZ6yteiKD88i+tVbnY2op53l4SKKA2kxAl1Bq3W8HSs/u
QMZKPyYgzCs80JG8iL/ZJiLmOMdVekh26kPdy5zI5+FWspHBe0IVlyemCsU0KUxWrkoY5RyMyQ9b
XDAO1XOykSiMQHaAIy/ktnlERePw3MpYzLnvI+FDF/xlOKj2UsecnUR8r3AbovB01v5tKgDnbsEd
G/jLrD/PzVYiRHtdvU663D78PVX4JDGF40T6EfVH8g3PMtl1IlN4T1OXrpWCqCjTJsufBs57SQZN
6zXCsledlcW8ZjwQjrzdVZFrnyQg2oGelc3wR+oHa1iBEs2etm75uYglexuFZ1fgSwyOzZg4AegU
WVJZc9Xlydf3wLkzkuBFRe+mLxYw2gDM38f5PzDRviEivl15O0HMpxrU4n+RoPajLIYACFDWCvUV
oNNS8lsxfZKP249SEMY2GYXe98jpsvNVGJZhpDYqG4pIrhgB3iCtW0NUAGxmrxKz/nDbGWUpAVut
fkxGeLEjOqb4dsHy7snWTvUWbEFVdIjl9YrDj/H0Ev2s8+r5eSW/FGp2by6Ug3p8c205YI9l5SC+
YGJeLk9z23OvM6kmKMJuqIJjh0g//OaEr6wdRshGtyV1CdaQF8SO6m7DCvz4IWuCXKBe6Kn6y/OO
pjZwbDQhn81jpXlFf1fa2lEJQBXZQLg7ITpbuSKleL5aysRVdLwEfBL9inVi0hDOHFPTlE3GcU6a
MC8wCiPJ5JkidWLlF4p+h2lXz3etlm4HKOeY+hUfLrBH49Bvo32vlru/tbrDCed+qhgSNBX1VSpl
gsRYxYPTRWH7S7OIYSIcNEcknPW/9xGCACf2+vH7vGlMXjs9IuowBLVzXWyiuSP5LTvGGcD0Vdlo
ww2NHTmaET4/inRx2pRT3PMRnUjMezCAsgH8mw+LeUPmYZa/6HJx1FxNSkGkDGy7n5FbJ9jExRJS
ciPeoWYWZ8bnTYllGT768FMbflge9/y7JzC3DH9SNxEqpviFuA87rZrv89xKv8AnNptn3YqpSNye
q92eBEWSH0x0yFDVfQrKCMGBq2Qxrx5jsDXVwD+OQH1r/3jFswNIcqSdXscogNEQGf0R4RVP8MzA
HwYnd/1z3HL45kUr9/YMWa4pOQ6EMBM73rzXX3NT+mlZSB0iJkX3aRaHpmK0mTUiBQKXX314ubGh
16iUbksfeZ5HdDOerm3zLswvWPM8qqOwhKvPcFN+ttNuSgaFei7Ojq6ylQN/EusmrQ6+rh66BnDs
JNMkig2/o0da0RI8FFHO5vxHzMSC/jVsK9unZVaVoQr8KzytEX2B1C11XgQt9BI5cUZBDxJFCpLb
F287kiWGCgoX4Mikn3u2wwRNGc6BlYNf66TWPYconXpt+YCOZqTm6fC5M0PA4aAhVLwyvgxtB494
tsIvTQzeR8FAZOWgTW0CRLkyyWCAQJzFVc1raru7vJf418t6x+tlBe6cxJFwmA3G0Q/v9UE2kiBh
t59WZNeR+BbGz3ioT4CD9CZbRWXYKgwIBgv6swFVEbU8GA/jYtZWBnc4YybwsY3wkcZfbqBb4G30
sOOA2yAhZ/qPf1XTfKEGvLiOWcq7dCxa6FMR6ADD02ui+81SJj6AFWpVyIosg1BaFL/po/nZaiBe
i8wZrIWhwbTxEo9jVi5B6lN82IB43ZLEUaUWGzZpn6/ysifhiW1zX+/ZA0ap2UU7i9oshfJTLRMO
bCkAI3TXgWhHYWv2fj1dqLv+DYdNfImCdp+3/sKYFjznsjenaVIo7HjS2a6MF2EHV0s8QYKZHIjS
avUpyXBQoOD1cdIngccyREUsSu3V+JjAtXhA2t84WUdQsqZC1iRxBJKlpBemjGlS1X5cYu3BmOz9
wjSTIBl9Ln8JC5as+oSiGFxJ+z8PQMrGKi5b73FCLNk+dz0oYqcDwVkwnM25BJ9f/vGRm219n8li
yDFyA5OiHrE5Q8buq2C4v2crO9c7f/7iRaGE45ejptBX5dc9vrKsEx8K1ZEyUjgcAqB7DdAYSVNP
gcDlppfBl7cmV0IPxJ0qT7JJRF+CQWhkYlpYSkUAhG5Nsgrn2/gzTc/Bak+BPUcFaClGYE05e7qG
VjaOOXWfKOmCvG0fg10uN29vH8hdNm99syKUEJnCLelKf5ISJ/pGlO/FsdCp8YagvbQQFu+aUVNW
H0IXpsw5/yD1MTppkGS9tZm3SAbwKOd1thraSiOyvEI6S43jtbv1+LZzue/wcgVl30TSpkYKDOZg
KQrIt18TYeYXuuFhpV4T2qYFjYrPM+TS+NLOg4ZnwOZPmDL86qI2B+wd4Gen+6jZE+BjN7nxDVzz
nbL6muj7wAYgXJeM1X23q6eEMeAQrTA7RRPy+E4sCMkL4R6Un8h0RAqcOmpma1tqLIi/Ly/2r45x
XRN7Pmfvug32ZAQ0s+ZQsrtxXK8yfSzn207wd4hbtG34M//qQ9bJ84rmuAYpyiiBM0CAGfxy+koL
skLdEG8asmZtW6jWyE3DkQIBI8S2rMz83+5IyqyNwYFn28sJMAToSsPHtzrHDPJyUfasNZUC1tTA
QQXPbEsh2/q5Y1zwlW1XbCIkzOwT+jzNopAi306DAxwaqdACf38S4KFweZUURfTQO/V3pdldeE5N
twuGLfGgaqObKlA45I9VqpXWPQEla0iNfS/gRAAxMznIL6VzQu3CHMmiZxLQ0pSgTk5ALgxIl3HC
wcPWKGucttPbUQcbUxRZ6sFCjI46dSq7vpgf3n7BQdVDA6yoAfx23epLEkOHuohk7FxzsxJR7AhL
08WO7H92EM1hTbXijE7JAjn9BiYYq6AN5nmh0I6g54n1bF10meov4tuPPu46cDCyDWy5hzhRRrZM
D+Sc74a6bOBIc7Gadk3ujEMxP4kkzRLB4moCpyjdfz7ogPW7mms49mG7/OOcveUDonTZKp2KOL5d
uEgwE8lD5xZ8QlKN6OIBMHM8fpLXVX/F4385GUVL7MEnbkFOd7Ge6XqBgEMF78fE5S0m+r2y0v3Z
SZEuNSUmoBqvae8ib002+vVuuPwFeTJP1yn0heiHPZSSFNNowIMu7vqOM6/h6Pbe4h0yzM8eXNyU
KsqX6yTP4tIledLKBaLJUhVlTLhaNZ0ni4Vr5WR612M6fRLoNk6xMAHfKnRG61FcQFI47kq3iNKO
FUu8EX07q7O8+ZJ9/3vN2TIKnAGb41vd+luXY/pcKs6aRvSFUalSjBFCzuDnLIvqsxqvjkjI40Bk
8K5dOWgXI1DAAYUGQ+yFJkfBSBFoDhYnsQrQ3Z1IzYztnpfGlXaPxe8pHQM4e7nv/QuOasbtZ9gu
jS1EGuQ6e47/BT4w3o0ulpofWkjtdGOr7eJea/fc5ZpFAR2geDOO97awR0Rs5D4teRrJaWzyC8UG
om/3gYvJ3T/GdIL8aTq/Pv2NR4dWZRfu0MOZ9fa++c7Ymwksw987Y5kO7C5Xg09bT4+Pbeyey8vi
ozu+qvqnkR1jrtPDgLgAeujms0TXyskXQJs42RiYiQ6bouPXd5hALB9nIcqe6O3rcP83GY9c8DFt
mGK/Zszi1bugli10h+uVRDJBm3P3z/hw5zPZYrkV1N1rLTOM9YQasQMzaKb+wgoNbGDxv/mXKbF7
lmiS/AECwxAWw3CBqC5/ZYiWVb54gs0SQ689jVm5h/+tSG5BWIOVb/1zGvvWWNU6rn24M199KMN+
9rKzUc5x599yIs8F2jsrYqtMLwzH3ui6Bx/zIkTJzpwGpVzGxbGa5qcuvH16hpXEqft2r+4PY5Nl
ihNU486zDTWNWh5DP1TlRb0yfK8B0rpm6Ch1ALI2GGpO3b+JOU4QEM9Sp7ivvSALMu8zsLTc82du
Vm5ByfEdx5pA9yXqBs89iMVO5dOP2KsMQX0tHTko256nVRnIC5VdhDSWpraRXRjMGbuDz0j673QB
Ddxp3+w0QMTuShZqCBCHC8AnTRtQtKYNVmZDb/n5mVeXol2tEipZTGxd1dIRM1i83pftuVR88W30
xeyrnRkV+PZCbS/bmjBWmsygrmRSzlTiOzr1bqRLdoaGZmQnJVTzz3JF51iRMz7SNOpD/ryMXAPP
FEJcGlUZ70SRvw3F0UNTVCk+Sjktf4DvL4JXtdl7vOa7GjxgsdVqYmUjOTtFpdS2F000RWH/mi2I
BZiG5OyiLK4JRy7iwBdPBF+26vhVLVtTKtxuxKvHdHsAju/Nf8MZdp4Y8gU/5rR6aHl+yVdqcZbh
9WcrycOTSRRgQmFkO9u92BPG5fE575Qc0pqjP5OLm9pt8yZzzZvv3hXNl4vP+b7kWQZ6+ce4w+XQ
IdysgGC7TCpjhtb11+tv65RwFBN+w2XKWUmmD79202gzNdvcu7PJoS00ALmTRRuGnSXZZKiLGjbm
RQKeFrHab/w9bANX4nVk3RYvxM+yFgwF58yZLrFgWVR7fTvWD/LSU87yti6eEuq6HpuX05+2F2mc
UdBStV0W+TE9zkkjmhqWNcJPE06uxg5UaGSTr2JwCBh4nnkC6SRBwlLRfWsqzEPy/Yx2IsEtXViJ
3jy8IGg4L5E3m0ZBOyq2oVWVDrkCYxXdnZKV/UASthchzFwdpJV1mqfKvYdouo/hGbyeOjYp0zxG
Z73SFX4RppUzG+9eYmlSdXOqjR1ZSvTIumOOSqclLYGHNyYbWrN5ZCSC2ORB70dZ7J4Huf8gt80Y
cC71uAXZrxj2dLXcr0/95rNDllwUmpwURWo6cgQito2nSwn4aJVV35U6QtI7J+RKn8RW7JOOEyyO
uE7SJweL3uUBbXq95jxvjVXDBTJCc0DvWxtX7AWfey1njmAnay1h7tOrVAFKlH1lPPiUOyxKC4JO
CqTgS7Ql13rvyoIjosSCVD2lx/qdFtLC5ILC2xq9GjmXSflYYAnARRLyUTMIbhiMwLDg0IWTuLq8
SDxhY9wBMYtAnZtxwN+cv+3N3XRa8RLj28ADKrtKRYf4+tO4zV1dv/TlKuLP3SIbYMPFWE3rB5E/
JHjzGJtsARGswcZqcvJmXKp/BJKxDxVCcfdIYjIisW3Z0v2HHPfoUtPMBl3sUXClY8fRqPa9iJai
Y08gwxyH1muW/WYoW81k1iTYArRyse+0E3IwywhWudg26B5Hnbgw8TsJOK20whNrtZYSSP+fpK4K
h1zmtXe3pOXdb4APvLHbhBXa+LKap1iwFLlP6h8F4bel+8a7lLpFXU0/2RewZMARfmc/g8FLhRP3
y48ljT2PPcSR/VtWefKBQ8sS+baW6F5eI8+uf09oJLNBWDCdiRWM9kK77PW7F/rjg8FPPR0AYdCs
IIWQF0z2m4lOS1tiDzqdXx9RdJ4tSOqWnqFPTYpiyHEDOH9GPg+eu0AqOX+nn2c5o3Bd+UzcMiCr
8SO+Nr40hDGIipyZBjZPrsGO+/+cxQzid7MkYExRKRovU5+BI1qyXXifrZlckUhYwBgmnCtpIcAF
8T8GyHWLHAhfU+uRi616Jo9ILtd30TMH9aUuPrJlJGYo07dnVqSkuo0F3WIrBQluHry4kgXh+BFp
TJtA2W3AYwawttRcXLPJpDERJ/gzCa8jFrdt48E3Kh1iSa9soRc/GioS9u7gWa0/2IZyELCszetb
obnamA3xoIXXB0tcvyiuU6gQNOpwtsEf8kkRyCXMIUO6HdV6kzrHfq2vywufK2uA2Q7ynBoAno/+
L+B8b9iVgAtNwowcLAyt8viNeDE5XkabMvQ+mi8EkQMnYRZXX3B6J+I2l3RKttCjA+CBgCRJavcm
nO7e5YfOXTi+VdlK3m8knrXV6PVQiGj9oTxnVr/2bI5vmhp2buDEtYwhEjKstZp6UPjTa/k212Sv
NnoNumXy091hvBMe7YvIlrHfgY3nZiU6sKXmQT3KDCtJFjrLhhCDxxPIbkAI4rJwZqGuIc4J8lAe
EDnq1Dwoe1SpVOqpzGGNk2sm+vP/suSIEhFrj6GzwoBk9QTdveJOeTirUhigPiKJMMZGWVFqGMly
3dR/GE6/fu6y+q4963nvbjf2h9OB2IBzCNIPSvlDNKBvHXQD4ngpUpDBeiO8ioBosAvjbMMDofj1
kkc9g2qkJkzJ79J5WzPyFqDJgwgN9Jm64/VJ/Dj3QJUA/51ZU6z+bBzwY+EPX5SGXolfJGAcrBqz
3xtkWHqFVvvoDK9KTPaQhJLnv5AR8IiHFe23bWQ4K+B0G3tzvBJAdxy8PApU0WKgLvVfpX03OLCR
MESce5yprv9UEe8/sQ7mOYMIBVW+ohhd+CH6mopQhK6TtW0b9qH4Tya5EAURoDXSCVlBiu+WQ/iL
Ela/axMhg1h7mKcYBSsFND/+SyeTHUyYQpUzUu4tsQP9PxS6CUJgd13MLEvbTWgPihRwfT+keumA
BB4fEO0hBSgKdPrtHvn6/N+w8Rh75a/j+puemaqMcr2J+h2FcUxS+3UNVED0E8ZJNMvDzofMtTLS
Gjvi5JWorhNEdKrWxaRAGWIRotN7onAjKmlE87QcHCrOXIXb5KWZn6iDa6GnzyUly4TVA9aWDJkM
x00DA6Dm0BenktSTKf94f/JyMVvXqTa6mHQlWylSMO8cRkXYIXk7hmRIX8VQXyzLqcCpLXtJ/0gq
aaAkMHEugEeNup8k2gweWJq87hfkZhMzQoP2wa3fcSQVsUQFqw3dKFFJEEJq7y9/ANnNX5VAi1c6
VGH2r/YSHYfCVzLM8zGNejkFMFrf347wOxjiByzLYSs2ubc2d9TRq8R45E+eAnuH1kxHIlqnzi6E
Vz2bY1aVmp+RvOpRgKDoXiYFyI/V31tmYx885i2ExFTpWu56KzOlFVpOx8D4vpOW5xnjXjAoXohq
n/qag6OacYzWkSGh2o8Xc9qIeM4+RXfyMMOTHvxOg6KdryiT2DntBp4+i9ni5/R6NFs2lbXo9F6h
Yt1POZ7XSG0aHp+/5NcS2dUy6kwjyo2vfE1rIr60hzwVtSA6X/giRqaLWSGCBiIG2s0A+PwqG1Eo
GqB581nugVRGl0lNKiD+cdpFNrZk9kIZkTqwFQ5xdkSNRephVCq983rZ3a/wpBVu6CCiF3pvqBuW
cqNDd9Tv1uphaw10n7MavIOY/KpkNz3TxCiZD+q4Lb4SH1gxEqD3aye/GrM+JYQd/ZrXWIFlUfRA
w3OpIa6nwYuEfWVHh85xqXVSN3QFUdD8L0k1RFGBCYWPvofRZPbXDCe9o7OjdaxVGPjw/ys8fHnR
NHYJcr77fdDZaBzzbyYwxzBoNFfM9uuYETcM8FsS9C0pDvMeJj4M7C7Jp+SVQWoUNED3dilEDo5j
We2xj913yjfOgSZerU5HxzUpATh2kbdElwlIW8Zh4xsZzo4a/MHkqtu0XU/vbPSPWbSO6hhIwCJ8
xP5zWELTo0zJV1J9Ox04/FQ+6MBS6hw66CjrT0BDGRSXl7BxgLf6BjgzzZY79uEn8MTvW6RntqjI
+R2RMBkVFLy/HKYpzTO+WiG8whiBcBI0ZcIlM70/lS43jADcJPGdXn9ywvNcT3srZaWviANe0NP4
1YcOoZ3Rt1NFnJDH9ZEtoEGpymlmkM02kikAvf3BOzafXBPyMaKNWjPbDeQ5nWluZ8n8oNbE++jW
lukqJiCla+6KuS2vYo6/A1Ztv7s0PKXIu3IvAazKiETBMqJtscdrN8DqpeuSGzYWxM16zxjCktG0
jCZwMtTcXw8VnbY4KHK/erJ+KVmbHNQbQYJLj89G/ils/t6eV/ZYOT/0Zcx4DARNnSJhUzVH4N5X
n9wrdlbaRZzl7xSRHHnDCS7h41MFBfeNQ0tSrj/jDHwgBvzYysAkTLgMDYqiVeM5hLzEAmdaZfic
iqjZzfGr2qkG+Cn3wcIns2RgfBN2jEWnEGkMJxhlwd9wsF22nOrZRnsAu89bj38B0sXtvBubo/kf
9YSCHfqOmxqnw7ALwwgjvCNUKMoYg5WMoaXJUXqrqg+I1TwAPTtFLNdl1V3cG5o/U3z0KLO+/+QM
bDestV5gsqjh+Lp64hD+0+/vU9X3B2VZhkVgJ4bPxTuQldHjdV7JQCVdw0j8SgS4gJHXf1XGI25p
uKGgBYqkJZo/REOBQ3NeQw/P1egpcSUb64oTaky1uWYaTXYfYzp4Wcw8j+jrJ9E/93bCnE833BUa
ZilxnX43nqq3ugbL9slYCNrNYmt8Za7YWNtUHO93DiJRBVU0S7PXvAOnqXyIX8M4bA7+saRY2MCM
0ZSGQEu7Fj2xmVCHyi8kuAJw91aIvBWyjsgR+gbJlh1++9NKDwUd/vUWq/U0cuBqVx+JGYfMs6Ds
rNKbF2qZ6gytyRMBMBhPVQ09jf0Dtyns5HwgeUZzVTmrm7heeZCVp6S0n9CrKn7MqRtPyT3fuGsa
A/M0uGabRQhIhhMWVI4IKMs5wSeGAWWEItZ3O19XgUp+omvBHpah44+r3oICXByt1t9rQyCwXafe
ul6EgFDyeq5cqFQ/XCQwTZXhtb5d6/4ABJecEhroE99IOOYrxSyMY/+J9GRI+ryW7GojBGKm2nK8
P+I/eTOKlHOlDbxxjB+RJbRxZbh+P128JKKDh4SwX2QHBJ63XEfItMz3bg5ubnnzjpgw2MrhNrkg
xquizWh4xhf6xspfb1nf2tMbodlp3lQlnhCDzg9zTLiTfug31j+OCTvSmH45aWqIsvzlS11AuvbQ
z01uzMxGYsar4yi2KfgZZPMEvvaDSFI6Epw37/kn5sEhsP7OTbCnKcIyVkb65A5tJ6LVgBqnFQsf
UzFQxYMXzfzD9uaKk1pRIjBK1NivUVQXAfX8egmJLstHT4XTJ+OWR7gqbY1wtozuCyNZmz8rC2Rn
jQDZzNZr4sTONSfmJBDbnZmF52G6LjWmE6fmpFg+bPajtq3b8Rr9wtD9VjxvA+OfLtJJi8h+hvRk
6fmanAQRiR12zvcFcXM3e0yjO3dJjUSIQyIy1/FW//mKPxnUTBPqlMon/zWZheVCJ0OnM9NH6Agu
V+fP19q2HzZ4d8Vx5Tea9QBqzYVfqlJepAF3h/SR2GbhwhyM9KWx+Z3a1fabqyoep1v3ltugLb3t
dILHHXriUlvaQ875vx3uztXdODccHCXyYK7oXHkt2opxTYViRdsxhd5LZXTO1x8M6HGWb2iF+Zth
0sw5JxpjlxvkX1sO1xJtwaP68DQMXVpS6R3hVCjeO9Nnbuyo1PhO437nKVG1XCugsMfHp5BHkQeb
WcreNWFCOeF8H6g9LYATyGxnFq9JWJgppK024UCZXAYVHoN1knS3CazJKEZiDaS3Km963BHFcXBq
xjhnrXdJiaLDNVLKCVoEnVecs50IC+15RFViPEhLplvtg7zKpfTRzp23RjVGpVKt/lPof/8V05e1
FDH8CpKZl2q+51oHUhuQQn12VwX2WwWJkqy6m5NaMh8JDFHsRUe3nnkP2zepvCx9yK1sCmH0+0Pq
C9vMUsso+QLUoX7Kb5NuZA93TTa4zqEWybrDyJ+TSBrF0BLXReqdTBMm/EyrlRmzCWUKg4tr73QE
9LQ2tZNC1nixVynb4/AwrhfzpM4TE3IalIGKv/z29eO7zN6KPK8v8Z8vdJZrMDvCbo77q8FqmXeW
S11Tj9bPdOUxy7rvFuikKRy5h3o0ncFb9oa5wcluTPYiVgT3xDFkl2SGGXPSDefDje6bhfKzkCKr
Qi3Wgm861HdJsAMt4gbm5IdxAff32YMOzNEfH40LuYNwqPfjqNOwmSvz0EmvUU3VG+U7MaDfn0t8
JxtmWsldBTQ5m0D8oEkPnzJzclIQIViM2uEBeMF2+oqis54tgdWJ1XIGp15sE/JFhd1XkW/Rc0CH
rabtb7dQkqX9uuOzjZn2imyONbjmDfMTB08WiXn1+UKysc7+D4rONd8WmXY5LdIh+uXfr1jNz/0M
ZeQKwyrTP5NU9fLKZ1i/XgHdTaYnWQvBXfeAbjlses0VY7pN6DSFeyFHPh4f+a4ctpFjMW5K8tmI
ooQYtM86mqM2wKxNNkHpS4W3SRJx5g2hB/ng25NuWbMNd5VpBM5sUdaQjM8uGcKo6wUbHm1+xE4F
OeYJUDPGpYNtm96Qmt07jPP+C142GTnLlISQXgtf91pSA6s6rwPbpgWOwKgK0G61Mcb5r9/xYdWf
BppXevW2fGHzuwOsIrfyh9RzD3G4JMbD4XuG4WsWbtzry1JVRDCxSO6OUunyOJoJnzErY/u+FxzS
E+aHjlyFmthzX8rfO5A+sHMnr5XY6odcOfKu0nsNp02RUbawR15goL+ttnsetGLll2vtYrJdBAY1
oFDPrBqKi4hBj81+rnL9XyhfozQir9PCqZXzrj9bbqbnkJbFantTads/xPw04JOEHZ7MmDzdFd/Z
iwejkdW1RjpfLAULdWx2gnqxTpV+e/BG9AvSqhLb8mx1YP5WALzS8pwKFAC4TYJ17WUd8P/zjJXl
IKxkXhJVDSIoMXzEF1smtaHtgHcrsgZ3wgXbwYa8aHeg1FqluaVymiq72vHNpebTtZQqMLkmzHhy
bYK310pPauULFWwupbr0v1gKeQ9Hu3cspwKm9wdhM0FPTzAhNQec8W0iPu7sBKsnES79BYURFiJB
Z2RP7qdI98VfEYZ1gtdTrt5e4GVyN5r3yBP/kdcLuFe4jKIjeXyJOx2u6MFXZzbMnf8LMT9ujH0M
haH37s6WMO6uIyPUYQFxcQpmALCd5XCpqgHOMdPh61nxl1bOCQ6QXxqBXDp0GNa0CwctWjG08rNW
sqrKfLWExLhzwPQdE0+zz9EwbXa7njBVQpmN/Mdqvxay3DAUsvsokHfr+dGKSRYu35219557TBCj
jX1Acy1bHFl1/uIwBF8c3VgYOVgrAN1YdsABXZRuKBdxCoqDq2N2FK3NmBzLryDGQjZdXx+IZwUr
BS1NllOHaURRO/Rzb6r0nAeRKKau3V4J89hloNKmY4QOpYdG70LeQz5V/yJZHP8jZ4YMpU60Ov4O
tRXz/HRBOSCL1C2MAT2JXDGXf8lIp+R5BADbCHfxxjYNEEUYk488x7NSb2KknllBAUsDgRk2dBbE
35tJPqgHLYXSZAG5HysXbMUrU0jT5owJomQ0sb3125D9bZ0tJ4cz2njGMeiipZRKgUGdll6ArsfI
lBEorBXGLkRNGSClHe1R5kV4dmDCALx6w0FgFjzipOR5ooM5Fmvb8KiLwDggqDxOWkk2TdlkKb9b
U+yJNhHzOJjthpcDfI31HNNJIm0c4Ffko9LvHjDrQjDBABNwWKM1WnQFUzIyS6/sGR6vP/QT7onk
ilHLWT43zWi/TzPNiS5U+zy1+CPape1HfLCqhOoI0IOhv1f4K+oT1R8dajFYsucBooDf8ocaleJG
nDITBBkKh7CHD4KsBZca4YtxLi6V+9KHQUg2TB0z331hBVFq4kf9o4gjnjloTXNwqRukyIWStfLm
7hfGySsHhuyOoUTVJ+V/RFoPhQt3DXzBgnB/AgOLPTi9G2H2Mikb1CBU/cPe1D60fNXG71o+94el
fCny0jw9YUdG2xSWpA/y3gg4lLM/8/TwULMk52ticmTlOl0Bl5RKDSAxPJ/yw11SgI9Y2owiR9oH
0UlJFcMjsDcwXpYLQvU+vQ2kED8jqG3WyfvbsYv+OXfzmNTiX14jdG6+ANg34vyQeDmbLpNDB8G2
u4LKb6PW2l2kkC4OCxC7qTM8CdFzwjc72Fcamz3sVs3dDM38GE+NMmhZq2qZa/KZUf1isDTOgVTb
KRW7RDc2y8Su50PPQZPghNHY+u4fZ3Q/gBeeTLaXoTltOQl+CRc3PWcII7HhuLCqSTXdTxJtJftz
FogoHC503s6peF5QMwxOvZrTpLllKfqknNkI5j2wcscHMe5ptoi9pY7LpMnU3voKr/JAS/ievC+w
NRk+YIPS7S5P6dF8x+yiguaqbOn/8DvOrcR12kW84lijiCrVEZIiCjntg2hEwm1z780ArAUlLOQ+
pkPfDCZggeDG42Uoq1WQu84Y5hkWS0uQEkbqvPMcK1ctTVHbCuFfoXJ+KXR/reQesnKUHZ31Erol
jP5eK7RqWa4hRIoEJpxpBjAdY4zM+iYGG/jUEUgL2p99Clg+VDi2T8Ic8FDZOURaBf1Jx4WbUkoR
CdplUWjdVPcQI4EVDzyRHgpBCUREFRle0vSWa81kHvLZIB8iAmIOjZN+qV+YFHZ+2yxaHGS2pZ6V
yZ2lH3bt2WXIjybbF/+l2aC/3h7Wc7cDJLFRe5Gv+dd55EHLh/e3dAOjcrv3PwQX83ZexQjkPHGb
pXQAJFEIukPQDEdndH35y48WwxCgzT1Wg6kjeKdrRVd37jdSATCvU93/GofMvYjbOgI/Xy2JlPs9
z+GU8bAMz6dVfh/Y96XN7w/xOjXe7wAEIud6R/MIvSQ2MfHCS3shqZJCarlbldi9jJL/autyTdnn
09q0kP+dX5w0fw48iXIEIA7c8Kya4Kf6FFhN/bAqcbwudlXKj+t2s0AYHj44yBWLAxKOH0JxnkfO
W3kwPITDAEtZO61Uhse/JCDdCu5mDfJKBkHFpkhOUE9chmohFrHm39igKLL726C5/mV36Ld1ANrC
ybOJkktUo0hsF5Ds2AgI+HKLbqGJLMlDkBH1IO1Jt6SiQ6GeHxmb7wMTnBobsHI9jQwaKw3HpN8C
/FyKHXGByv6yKCz0Ve5oIu3A5/NQAnOwrjQ7OtXuq1xH5fNeEwxK08w+MrGBathfqyQLHKJZhv/I
xWs3QPIbcJWDK3koUZlnhwhSxuQtsj/5l5HoPacisLG2PVgSvP+49km8Zpl+CO9/R6pdRiyfwnJB
+E19uXbKEcxDL69pLtkxSLB9PYwThcCSui4a7X7n7hGzRqiWe7XZD436CrbzxvJF9uaPVBssbtpW
s5ZUuRj8aF5wetnzDTmWO7hp1BqEx1KR89Hho/jI6XOSlIdYuUJmVnX5W2Cw5G/zCMBazv57bAfr
QZ69pFepqHh8j9OVQtDPTtrQRU/Y0T9pWVUxni956oRcwi7mncBMGHx7+WPhK+R4RNEenOk8Uaow
X+PVlrsjVuIxacShHwH7ZP96Lci6HtJ8qqcGMQW1oYXAm6qJTySVkdJEk3PPaLeqEyUVx5NoMUZB
E9f8L2ClxPUBtZu/c/2rQPrR98sOeRxhBjkcwCpLJHZY4dCT5MXhdJGwur/S0lsc+mzCupxIdhj0
PRUPyDHqV4yXC6h/9VXeFw6bixPbJi5liwhoZ2zfoTQYhdWSgTKUxjgonsP5odHe4MmTjV1N8Six
iEB0DZnw8MPyAp9bjWJ8Mg2gSYacHgTlHEK7dUXikdYK9i70n9UcgpRC9P09Tn9RGQNFvOKKp2S8
wrJ0UkRFNZvGShIZxKUF5S52kGIGiCTaAqsgI5HlC/Cj5bz7HP9WmNexhK2B8fdV4WgGUUI17JKr
fWv78owGGVG6BCk6NI8Lyxx4TF+7SOUa7cofFNx5vv+cIMUkkTA/85PlwiJjp6cVYSYqn1kVGufb
bnDEYEFtzCmcM5uYsPoPOfLjaELX0/aRtaf+y3pRYzjk2i12q4ycfpLq0aCIPSdIXpVkVI2jowBD
YYATQ9plIlBq+Zbx+PHsoZnvCz3Vdk67dKMdWZ8DW39FCoRannjgp3zM8QnsJM8bOnhr0wwhX7gI
HmplDyNG6svu3hDctTeJFgICuH+G+ydsjmS916fnueTPZgWOAnz01J3MjL41GfAmR6J/dfKsm2bA
DcASIY7UHGbIF3xM52Yje72mQs3AZfsa0XUa2WGyw0r714fH+XXyhqo2jwhuXhBTRQEiydGYcsSN
YYfKfEgzTDsAiWS1emebIMSl9hiMrMsy1cJeLXCwUEYqo66q6Vfp59oyUnzegWVrjSpgUyEk781Y
7NpBSsJedNyY9lC0xo4gSiAgQFyJw4fcnsXYSDSXJKvfsbCMZKM7xx823WpVfgqZmxn4vvDZE5XU
rZ5PLGGpTY0+1eRgiGcefpM6onBJ04peVgTRlu2KlMEn63/8wtPsxwOvAcpmVU1CmQaM2ORM6m//
GvCAeZOOCNAOludJtvTe9xN0U7Bj7iJ/MQxLGZAEtEQgEsZF9Djq/8jjCfZE2xtNoUetIwq9Spa9
jMcPZVjDkNHdhRKGJOfy197mLRkTtJx+I7UUmT+gBeveTvW5+HPMFaxJXN1+cy2Vag9t7nvJto3p
XJGSJLNP9ioCel/BBapfdlsUIKX3zZLCfM5sLF9ja5JxfOaIduZE9U1hXSISPp4RgQaRsn845+27
2LdExr5rVxI/otYUdS7XnZjwpfJ89RV71RJADQ9Hnpjt14RjGBBoh3VW7PY5unenawo7+PIK52Vh
xcxgJxi2ymZ1QXSq6lJOqCsW+G8eT7yPjLryLv8qOiPV8PKny4AJTCKgEQ5NzLk17f+O7/afYvXT
Bp1r9RTRFkYXHwszjowYm7QYDLZLKmN/RoDSGAoaSKszQDclaNthfZPgVuCR1rvEe8IkejpbeKrO
v4iQdnNvBjK3ZuSnN+MWbjHfDenFCy1giM6+ChY2TC/L3h1Piw6KIp8k/KxBBTEpjJeGhgISaRZ1
xvMf/XvPW8r5p7BFlF/no8fSdrwwVU4mfSolM56J59Ojc8j20V4vohQuunWvaD2gf4+btZ4f10Yd
nEEd5xPCVqfDiFgWVwBtUShxwRpdH4byE6MmPoPRcWKAYGgryjzJkyhM0ydEehtxVihMeOrXBBxq
efeWPFMfEi7VyFm1TpRTKg95PRZiZQztgHGfAIdrRzVQOwI7cp3++YzqBgXIFpCJq6X5zkjY75Ac
EJaWJ58f5PlVXICJ9p52X+OYSkk6xOn6kQ3RlpFBk4+mxCJn/reVADOjhPHVwE+6KQMtVfD/KDCg
8TdCe3NeutZb8UtEol9JQNDmwl/iW029w2dYLLg7Ohje+Ywi+pnNqXT4pFAyf3+Ouq3isKaBbK7N
sTQq1/OZ4pNK1KhSfzRhEjzV5RKG5ARYyQdiUNUrVQJV6DSnw2fe+mn7eT4t/Y3e6+ZbIQdDWyA6
UoHNhbMFeLi0A81irF9BluQDFECVir9FuYqyLHFzdmecrGi7II4+KGsYo9KyQ3gn5k1+EmFRcVwa
B5yC3U7HPOt5gnW46uBDpdR9AN3cXdvN3GtYDXHTcOUuDgsjjr1hB6qFpW2scJCgDXlRp23tALiL
UcOP6QDMTJ6x0UVlYFOVby1XGrPFKn8w3caVgI67qnnRl8aK1dyrfYZmT+3xdQIQ3b16f16wDiRR
Ijc9JY/9CcLXBi4aH+lzfNCwAAUDonoG6+olI0DxP89BGBlkIyliyzMEBeXMAdCo0sLjFZOesnZG
5j9T2zS0SUAo1JSkPKK5Llp+K4IABk8odUw1msr4zqvFJyaUjV6ow+OLeBqBtQCoSI+svsqo1iuM
SgMUXPFypGXxebuUkdkW/DNhp2C7cJgVVs7FXDh4mkSKuiD6ZBd/4BXboFOxmbsSH2AX2Y7Iy5qk
nBM+zAVKkMuWMrZAZBxqTiGM22EXDJgLIDVIgnsZ0nVQmjggGys2RM3xMrp9BX9dmABbn8m80UCO
Fls3ib4HHSeS84ooPAQ15DXrksi60jtq9UIH87gGrtPz6H/Kc8c9odfesJjGblH3O4v7pVF4kxsj
IpEqtmjw84ydu4AdeQgpa6cc5BM5EqDcvPnqgyOvtEIHIN3fKqkK2owdn3xalpR2a39RUDkuJNN+
+a3QSHG+bzteHxsFwCLhmBk+jl380Eijo3Q0z/YU02cHH/CA+gHhneQlKGFQnikJ1b01ITAhogf1
IeKMtIm74FAzu/UZrNLE6Vuq1pRqbqqyYoCcafTYvhk8eQNpnovUPs1z7wb3QNp1djpoDuPrg5ql
A0OTgddph2oPVV9IqCnLNLc5/BffYtzt+NB2YoF7Nc5gonsla7mr50/w3j7dv8xZzZGFN1mtR5gK
KGC2HMzNbGZ6GYNk9JoTKf7hkPi6yRTsGJU0Ny3kjD8dRxgP8D5LAL575r3KXUmpHH4dSV38umYI
B13sS5XFZlvT/gVN11mAQOTGIoL5LjbOr9bv407CF5DEc+6Qqs39UPXaNadjIXVMlyISLQG7Ji2Y
0bXb46s47sScO/U0xizxqUO+MBrH3Nob1BUBS5pBlXH6XDgqFsWEcTLnLMq9RK8cp+kR+X7+2IkU
Flbkr+IJYW6GgHn9TYwO3+nT4P09U9VPyGx66EKPIoS4BMoubFJoxoU6BS9eTKQoYOzE59RNRxJ8
uamlk6qXOTFPM3Rj9Sq4SJMxdvn0xR7QlyJDNXhb0QfXlbCYGgmXIWixQjfePegIS/lmLKI1WD68
XilvUNckgMi/NyUWzkyfswvGmeF714d4/Nw+KE3ldHCYbXPm5061uYW6tAeR3vXKM6bHqSZBp+2f
AVZZscT+zqlk/mAOfYvnPa2DNh0x33dv0jOd+IZ/rNJ5rQ7erH4DyNDj2hcsCLsAsFsWneGtsTHU
jiQ9/H0MxrHcgJWDCewPtAUbE9Ma4IglOUJmcKAX0FENwjw/pU1k/Tl1G8QSZp4VQ9+h355NJhvT
BC8GVTLG6r4zWDgd36CUBAwKv8XgJo9kAH4KigwsuQaGy++u6Z5HYgG3OuhFjTW7gwHcqsYnoe61
VXsHRXPW4NkPfekh32QgpTShN8ozoy52/ZQ+yEX9d45zHvgEzlSTsmhzKnMzFvL/MxVNy9LwrAid
r1eCdn/Rr1REbdjdtGBEQ6pGYG+W4Aj8GDm7K1u+yOOeFqjqicHVQTSZz81s4UC2UJm3EHCD9OU+
hx03rgqmWhWenTCu+Y/nhzrWJxA8TJbZl16OpGVt8OeS0bwjCutXwsOY3EyrAnnTIkSs8Hw4Ra/z
LWGk5OURAjb2pYopHg6YydKQShbJE6tfveuOWE8HhyOgDjSCv1DdlG06AEeQVptSK6x+3GEHosQr
U6EPFS11+9kAxVJ0czd9uP8rB+BFxYiDL4kK1JVPIdTuTr57PUb+f3wyTq3+b8xRLECf5pdobwbP
teOoJh5eU0I3d04jGk4SOsDoEu0TxWqMbpuVMYDsEAVfnRuORCRwwuI2kDqtUxqOyc2ah/Xt9d+F
Q6wASrtXn53LPKgFGm54dn7uVAX+JnPEa/fO+h6kGl6aQzaFievRmmWb12ZZmLoz5qZ7HRxlilL1
6LwNLZS5P6GhI45DCrIKXFBk7eg4VQMkq9FPEjqtYDaiVUcpFpNNykiQnFzlWw7rXIoNrRU9jPvF
jDn6i7UzpQWLK28LJKLFBkpeq2NHiaYuWRJpX+NmVogymKUAfY5ruj93+G9i4b5ckamO5EXLcz2b
moNH71gaemJ5NAl2lKXhFUKDZWGAPfVR4eBFzsxmWTLhU/t8DyTjYOvvAiTLFAatirs3y5VJgdZl
EhZ670+Jjgw5LoNPVumby6h+lvGorbUjSK2f4SgCHNZ1Ng9cOLi4qw1Dv4wSStE7rMFd9RWMa5uk
+uV1RQFd5OgaTOBps17gvlM7/DTFFaSzDm09Dx+dA8FJMKvimh+DyogdifJaxSTxRWUhNvbcsiy+
OoaV++V3Km7pMgIoaEFusmaa0Rz7kDYVpWAdALTSgqy7CHB5uxTCMCrPh6hv7CaBtr2BLGL56xdg
uxrUzLo+zmoXplO+P/iKmQZkUv0oTN3PE9NmpxjvA3fVpZ0GbYhkPhzDB8dkCV06aPQIKpyMpAXr
1IJ+1MWLqonytrX+orT3zBrVmpGCse+bqjps5llexKmhD5069yNVuO0qNcinLc9IbZWqGsneHfEK
0SXxQolVz1MX2OrV/CdhYKD4qJR/MhedGaRFLNbMsswAsjyr2LtBOlxn6phnUj3aYTqP4yCvKwy8
sJvbvFcctYdOPmHNBeZe9v+AeGTeWcd4YSHincNGAYiEE747TRAPF00MhUDs9q58PR1kRQ/SrN7t
U8PeKDFVM9LLGR5hSIIKHBUb2bgp6pQWOQiT20rTkfoxcZj8Ez0TDWb9Xkm1kitdVsdLIdwzlJ/L
cjhdYs3/MoWSqCUeWNWubHU0/6oxwloowmKQDjRRlOM9s1LY/WZn7KeL82lf6wlv8YncA2vuAhpD
4fBuR/XgV9C8rXeXw9faUfYW73Ohg1enD1x/RpmEjBt6AFxr+rvnp2yBfCBNQaqIBCpRFdFRI6wm
D0A/fDHZt8iKsmAlw4bteTU5PZB49sf4WDinXzdietC7qIv0U5plncKloMyHewZem+u6jjSSXFJb
8XSNx2Q7aFp8Sw/WARE+gEBOtghmbuxg/k1yATFUNyZgR18+wyYxOFocyBKgmGh3XSjMMJdQdf1f
mL5mmrIAn2A19B59U0MtPA28wCotM1gwOKGrlH5Ro6xlVJtzself5UGmKTayAjdqbx7oFRw1nhFe
eeZuFQlXFFViJHYEkrv4lML/I2slfA6Po+VQU3j067YTn9+A+asaO17mOMcRdA5kGoqD8Ydsw4Zg
mH13gpwfeGWKsjCW+dd9u0GFXmVh/UgIT0TCHDQg7y8Rx/nj43TSy2xzjb1dcleeKq+F3F9Z/sRF
peOctKguzJ18d5G3r4y+W/iDKSFI2mKkCzYz6ZERmZBADiCmxNLWNzNskdwZa6pCx8E0GWPFOT+d
Mf1u57CvIPieIcRtIsZb/zls9LokGHnS8KC5b74j5Y6NeEvWFwEeHq6aOw+HVbfreaqBCpRklwwX
tqnw5ZTv3CTGSg+RlNmjaTGIB7fSrMidfumvkwSFQNtQSHyZq2MJ97op2Q5uvApbpx2sJati/huH
/aOlbccZfk05mUAFivEGRm7+xkcIDHlbulqAA36GOAoFfdHVjeP2yoRjA+B8QrM7nqOuk+3sMRYh
ZvqDB8rharDB44VnHi1yCBfglj0CRAnfAm7EfmDxVo4DX1Cdf17YNZdfrg6fbNlLelGwS/BtAgMu
F+jpE+KrogYgTI0+Iq0c52TdeOwDNdV1AmAGafMYZTSdAlk2acZ1IzU681hL2TpOzVjVUaDprWJh
j/jIdhGQWAwmB+5LIcS7gLo+moFdvsAJ20JMqMGhK0X0KmVaXLUtTOohHNoWItcz8bj+D8/PUXp7
qE7Jbgml8uuHvXMgtlQnh6DCQF+FxXjloaRcyvf0nDAeX/9avDHTNyViDUFuE+h7ahiN4w82b4jn
HooBgmsvSV+ScOlYxVo4zsS51OiKdYSQxGv2kW5AR2wPPYs1DQxm/EcHGQRdh63myn4LLXZwIGHu
0fQdLFcTEJpVj/tzxrEP+yqBiu3NgLb8mM5GD1ggHFSPkARU29NkFtlbST7obEnEPeaiCkmGV2gD
poTfs5YilJEe0iCX9PxaIzAfkcRwcDCJrEfNbmBuXTKqMDJThb22k0X7dLfvw12mP8SkSVGlQj+/
PiWYep3dZI+hz4nAmHu2WDiAb2119kCurV1sEUZzioJbOwoxrOYmQ+Vt7c/iz95DFzWQh8Y7H5GK
XCFioSs/HPFbUDf/kMoAouUPPKoVFVxNhfIne/HeiTNSx5f+71Ju8dcizija2e3Jiw5uCsxFwPoE
PCmE83NAOVArYxaPoTs2tvYBQ/efiB8WUdUZUmBYDXkg7MX3sl93iAchVt4Q9qMSdmDTSEcr9RA2
Kj2+DXrQEVvqNtmE+QnBpJ73/vf2B1fAK7BOdCeQ9+k4dhCjX2hvLI73ooM6qOHou/gl5Q0MNiwy
KginxFYRTEnW1Dx0AJLtsN8Ro/JoOAHdbQHA1JvLW73TL2l6uPBHGO+pBwoH6KVPuvWYXed4Llwy
+y7NPZUdcyfR9QkEz4gJCKWFtjt6s4ymoUO55g67t9koG76yHHH232GFHzpDifU/IeAXuEv3xOp4
PiJ4o4ArAV/h7OrMD+dbwWh/BbnumMspfnvy8vIJbaXY7och6rnHv+4rHjceXX9VSiNr0CC4ANjb
nQd9EzY8VZadRkGHQk7rPPQb4cZapn0MbP4tvy0PJATg1UrArjsUwK5LDAPX5ke3/W7ijuQ21IrD
cU3kufNpQOPebvZt0xKbCYVvBnbcUEMMHnhLHzU2zckvp0Z4UmQbeiEoBmJfEK6uBsZvxvxyYFEk
O0x6Li6zne91nHl2VUlXjyZvc3Lq0MWJVB42xeU/4G7Y0/LcT4bdvyObrOD98QiP6+NMj6tFYAHI
8LHSOWcwnVqYQK918L5Rw42MwtzGFfhh7w0YZFgM+AuhW6ywkXLNTN/zis2LfGzwwLQhUa3xfjkx
gRDM/K9g0H990e6Nw269n11XbY1eNsC1XUlknuWcYy6njuZ9+zp3VOZWQnDriNqyqFpdm7M0VFeX
A2LIzYg75jrlaQ/9gZFy3RNRRfj9SGVB75F1sCGEN85Q3EC3HoxRs/brodtKVzKm+VMwLe3LfE+O
+EtUyUj+nO9hzJJ4aC4J9VMmTfD4lN5qw6I8KnK7IY4iCvdasYTBeOnEI9NJa7/+wHlBR9he2nDO
/5hVlE/+l35BqR/fXdZNie+ccdfZjoIHi4tv1hGD8ad9AEcJC8Z2K7sxTHK/Gm6wHB1jhvsDNZaR
8iWHeHhTgMNq/Obs5Hy6tmoCcTOIUxT4Ie919iN33g1C1q7wUzRm1iT50sZF2JG2Vx7p70bg+Ezr
/CxFwt9k3Kk1lzXsrj42Ex9ijRVZ73Xah7Cvg/SI6uanXNPcygO1A+/2JNPt8LM5mlF1CpreItll
Xq3ls6H6uD1eIHue6BXPrSvngvMhJtzrbzFpZG8hp5DuEe8WtlcmajuAeSmDm/Y3+hqmntPeAHxz
j+eEp7EJeWp0JkIF4kv6/H1IpC2bCLrtNPQl1ucuSgtFM2hcemwFk0L2NhgYyHueOvFJbPlozSKZ
A22QlcSbhRzBKbwG37nINZo1FrnX3Cz1P3PbMYsY6wFUJ+Tjepkh+kryvre/Aa0RVx/vTnZ4Zf8G
FqLUiE62RCvrtuIZDLfj/SfaZ42wTUNL3U9YuOxy41VQiLhUO61PoAM+SMuRmKPTt0NvgKDdGHMH
eJzvo2wXBBbphYqsWOCli9IlcVirzJ/t1yoiJR7do+ro+1+bfS9XfWRbmJtLo58Ng2CinP7JrHVC
CYmFVSPBBhB/0DIftVhY+ul0oMnCF6rayjaM729xErqG0weyBc0HKKM3NLCGzSscLbKUwtFKVGk8
jgmrSCmxzpuLyiJ7qgjr/fS7CooosiZaGcv+siR5Vi/JdnruUKfG+l+6wo8hd8slU+kHFI4KYi5Z
6vcV1qjoWP1+APRt3eEnQVBHBtzAl9FoQ933w6wbgJWZ2wPi/bOcR7+yTHwkVcSUruVgJxcixA/l
CtV7GjlH+bkwCTpHoBmuW3iraJcF7QWDtA1TvtDU84V/CG7LdqaYd59Q8pgoagj0N0Tps3u+U4/3
ioWVaiKTqmXiZ0ylSK/KRRxLJ0Y0J1hHb2TZEPnfKENkiDoBDQlQh2iRm2I9RkkqUWY/hb5u2vPc
u3lX68BOFT3qubXX1NskW6UeJ0b8BFvQ9norZwJY8qIBE/+lyw7KHp+ijTt2oJzHwY7iAuCXuueb
lm1B58MWN0LrwRSvWTeA5pl3TGVAOFmC1eWIshxiEvMZN2bruSg6XCsjxJBZqRmwv6jNBc+1TRxD
tDI3X/qgRIpHAv4uMpEUXSIFbEbdtJZJKYFzS0HrEzv6kFXyl8SefAr10UKEpokjfDen+HzDqRy3
fQFCl3nrHO8ho7NvMvFWwfEnMzXIknEbh+dSj3cbsUz1cvOK39gnc8qqK+WBfzO+cUzhtOoHNJvf
9UnD4v7pB3z9tPFeu1tIGKQeC0Ol+mxgeDiAabGC/x5838Y5hfAPcDAyF6jz4ZHBrCRa16cZbRG6
x89+Qf+XccIKJQvDp0etL+4dUyNL+FITNHTiBcrk5oaQtYv44FYeBmVorh8H7kCeMTFLZkuPuu6X
FGt/4/gbkypi1MMLKBiKe8RIRxPbVWz2UJlSso2pXACDcuHpMC89hEZ7AfI1MkM9FhAr4F1DP42v
UJa595wbVbpEOLe/VNMa8pz1bAiK3xMbzdiG/Gj1p7SZITL9LwKY1/Z96CE5cJF38U/eGybh/DEP
pZMJUSXRtI8d9X6h5tDVlo1DaL/fNAVf96UASIFwMTU1o3ecwi+YFkFinP4ITwN4Kjtr+H65bc9R
DTdTSXS72TsRdxLc0g1KWzTpR7ZhYu97iADcwEUCus3oFW5w84XpIq6sSnlSuf6U3JMQEJb+4Gxg
CjEVl1Q+qtGQfFeGVi9EUJdeIeD1af7RFM81WL72Zudi4sfvp1V1adPg9acaBMuqEOM6+hK9Y5EB
PQ9OwfVc8NKB9ctj4ptN3C8cCOPRa2g7guFZbmuMosMHV/RDLIC6igILtx5MlEKL3nXC4axdywEu
sfys0wWR3cFmoCaVTY04ME9XfkwD/b/D8Yq1NqU6Xloa/guIiJwwM3DxQWOU77RI0lYfO5/S8yJk
o/wyX1ZpjjI4pd/qfk1UGZ7WMHh7JJnIXdGN9+0TnTG6UbZdF8bDyeopnrRLoU4WL7cOJZn0wDG2
ioZsLIgpTqHTff6kI7qJRBC2AColEr5Sx+CBL4QwmgOcW+s2S2m14vdVqscOQCoUCJMA1FhlRghL
u5l41gziYPImmHAtnHARcLg1rZRSS1oq/ioISFSbRkSKa1+6MbrSelF4ByKn41E2EuIhsEc2QXMo
DTTvX5u48vwTz6BRQCh+QnV0dxvRx5szB3EfOGDToZYLAr3cBRTJwjP9vIphXuW5sxIXL23C5VBV
8zYvc9fUz2oMxE6Fc+5K2gapTOUlYi4jW0cNsR9n09LOawdv7uzIZskWqSAEae+qoRgV2o9e7t1c
Fe7KTiqoIrA0iaAvFgzPlUvia8bj69kBlWM9U5dx1CnFlXWvbBJh0+669bs2znsdL5fg69ov8ghr
J8mQJJkGa/sU/70sdGeGWImlroQ2IiEbfA8+rbnG61iNDUqhSybLnzcbvF4+4uSsHcn8FjuLg0bN
9C6aMiQashyLXdMBEzGxln6I6dQuL/tC3N7ylrDHdqdOpGqgvsSo4Ji+CjTp5l85wueUWKTw25Wz
eFwqC1oL+89aRTlTRPyqavcakDuvU2OezmNWInq1Uq3yLl4pKMKo/UmZYLHWrOXjhe0M7rOSo1/l
McXbmj3xxdP1UYPI06fKve29QiDcrnYt7LfN7fY9HUt4Q2bYAlHP9m8Xs7kBZP1NY5aUauaFJZfq
2SkcPST0CYpzux+VoaPJ4Pdo0Rb7x7yxCjWs6WeyGNo9zJ3h20jyUZH/Lzsg0PzUzm68xaBwvs7E
fEmxqoAIZf/1i9Qv4tQLxTSWSbKM2zrSZLzJvEY7dzSfj/lyWT8523MNZSY0hKSmbpjRWFwccL27
KqBInDEXSvpdJFsHpQwBXc/wyzPmzduqze2V296Gud1ea6BCGDHiq2NEoC5xUyWqADCWdNbOAqDy
II2oTowO5/VQp8GFJcKb7cZgX5JNX4rujwA3p6dNn7wZ50EMf+WWiuc0oaFhP/ReinKTkL9osTdy
VlmNvjiv7Ufwvx2Eun0FesQao81hmiPoGAQBE+/ACfuuw2xvRLsl7tf42eKfoH9qN6hCWrk3hUEE
VjbTCtCGILl8MeNumEK1cSGlWNEI/EQ7kncNi66MCVqjHmvyQuhdfancrZbUXDPNmmnutGLNhRy9
jKqhUig+qg9MQq0rNRAKHK9tI6z098v60FnYJMOvE78sd8wtiG+SK7dtYoNJHZbldxg0FGZDOxND
RLxYFFepcmA9/flLo6VsIld/fWIMX1/F3bGjScKw3/UEjALqJ7hWlLHXvVLt4cXFXn8hEMdgD+iN
qLZpD2jLMQXaQwNHKlzAXg3uhCBQy/ZA3juAQiDmIIGfOzgT6kNunG2mx6rw63Uwrb16wfQbVIzo
FsQUARR4NVMK+/gNffFduIXtUX6SrTMdyIE9OZyPrlVFNIkJBwiu1GEgdI4X2GMe/rceq+tE0gUw
iKAIezRgxRgLLbUomdAUgQ5mzzgEgNuSZqbgUprcdsZYJOiHBfyk7j00+mc3xVk1exOXt4U0xcfe
+Ua1En+nWQj+K0xswk6OUHKWFYMw1wgq1MYfGUGlDLiALexUtfBwoR3GEbMctGJf19jaJ8EKJkNC
BprP4H7iiX5q6jAjpsYooOJpRW7sDOoATdYaT25fjTzB0bHbr4myIQZ2gxq5xqXD+bQKr/Fdn1nr
guul3GPcjJ+LFE7PSYwbql/LJR5KrJx/wPf9E0/Ft204gKudigwn30PTKqQdBuB5zcZQmsIYxapM
8ZRtSHxP9dDmPwgxCMho9k220FkQ7W3kRN6uaaAyvOG3cxJyfHKjBAOL3DYXXfu7pkm/FNdFSmkX
jPnlhKyePMpkDXaQInYU48RjjRk7g+KGtuvTwuUHR1zAe6a569NGYc0mMHuz6IqE+PIklfz9dRPl
2vvGLl9D4aWZquRQvPGe3F/NUBR/LJfhXBvCSJqofGVJW9/udpX5Pk6257hS32lb/zKqxIIV6jRr
cXtWJyEDvwvhTOC++laTBbWv4+cL4ChFxZfx6Hg+bsxKJXKU9RXOYaOHLmsTkQ9AW5Dx2z+Jra7j
LRxwivAOiI3kq4gp3hNr4YBQLmjnLAJh32PZVl7ZGJgjdRtHzuMZpcy+8zMQGCseeqJ8IyEmQJ0p
Ng3wWDImoCTZuqDVzoMbpWRXgA63pUoOyhmRvGim59QkTm/Z1WMHhew1J1fvDkyPRxXTa3rBQJzh
M86kNLKi2HU4QP97biUeIE8e1k+U5pJoU4YXKN/lQ1jdMZGGGBBEAp6EZmfijnizJcHLyLhINnUz
BMASA0xr+rErd0eKHED/40/AdYWN1GZhZQqpCYcCuwFTR/b3e/evCYD2cBBGWTERwr5q2v6LEXZR
pmu2Eh6Z4X6boUKl5gLr+uBFSTCg5N/And/hcV98Vw1gxfOhs2Jk1wDXZIg0vo2pXKUnkZM7RsWL
6Neg/xO3iAUHQAZMtH0cckcMz66YOBFTWp+DIsgCq/D6gEnMKGChTwNX07SR65jASVpdRDzdsGDe
epdXWOvpcszn56OxZi8aqx7QeatbDiPNRO4XGIOhmncPuCag+xqQ4zjNn9iugO3aIjCT++3lD492
ssme7f7XN4V5a3AhkZs5WKyvjwB9GqNJrELrQ22FRwGVvymBZWnhY94hiK2/aRAA1KDNNV8MXxwm
ld/EHfOE0c+J0fOw/E5jtwLPnViydVzbcbUXbekHk9VFA2ZUriwR3mIcSc+Kvh0g5Mceh7NffYgY
tV2xm/z12P3ew4kbwO/2NpF+TG+TT805D1o7xxYwDELEFhM3tuVougVpQpjzOJ/VI2OvzYnSVGL6
2JDjDNUO9HI4hUz5WcEZU0emTXE/b+O0R5EpLyEj274Tv00z6ObLL20pUr/sb4gQZ6ZZBecpDws7
deQbtFn1Iha+oGUoJbUgttq4DftiPWiHmJP4SPxLhGlYlfU5OSTLZZj69917cWzdjaU6dKKzMQja
UcKZR/LL7pRSKf8mIBBn2p0mL1T9k2GJdJ29ZKaliXGwQ8WU/ZT37Doxp7fvsn4U5VB0v7xqU4+X
hg8gV+TI8VOxMaLgxinOVmXAvjvoDgjjUszh62rQW+esdufW10lli64L+WQd8xRHSdokeeCIjYdb
BOtp3JDAGXojVx6FiqqLi9ZFkqHezojEFDwU+TFr/x5OqoDLvrN/txOZilcqdproxuK05CH2SprW
a4fl/+Bgf6OfZdywX8I2wUYL5qGQYhJyu5nnPcpLp3N7FyEidno7GKe/CtbALMxISJBIi4MWA7Po
nS4LSHLXpHnQR8SRwkvRQ017AzzHbH6pZztOvQNibfUqK7zFi3g7zXo1e3FLoEfMmZMLGXOm7wDt
Gxg06I+CbcHLF9szkENCnBgjB9uFhq1KtAYHiDtcc5vgDbQIDiZVBpICETgkgUyNwIRxSrirU2NI
TCfjcZJGef2fJ2n4gD7PZjCeVgLO9KzasE5WOA5cMWGsnhMXXkY2HA1NSRTUMQLp5//p4mlelByF
8bNGFTrny0TzNeljU9PFTq/YBaOFqw/LQI2ezlpyQKtzBYOAjvQANd9pNbHS787ddD1TVDH/5HhK
u1IK39gOetw0ZcrBWlcyB7IwxxPVULFwYZlONuCCad4TwjWVtM7vqjxc2OGzt8oGaJWay7NzVg+a
nfAJ6xA0gMAAq02nEEjVDVA1PM+pO9taTimqfI+MgtMRjvfSXGwPyiQYtqZVzK/9FO55qoRzfvIl
djOyeEWbKL2bOgoeNhp1W678P5+nm9DfTtDuvR+YV8cotUjB/+Ew+umqKAk/QgM8F25IJVDrc3Sa
n8oF4eiIzboQdGgehRYqyyEnV6ww2oCvbcHIYdkMNG+R5px0N1H9JAhImyLOlFHQh2Mk7Ni0dC6G
BTq+CT3J6WSt2qkTCPHx6UZZ7tHxrqee5IUGQc6ojCFK75y6ytlJ1eDWKTFwdYSoouCfYk1JXbfE
v2UhqCIEkS0b+926BNb4FVvEg5bGWVmJrxAYCvkFnPau1Ehm/Pu2naaDy1dxLWQDh1K4Yy7e0f5W
thwp/UZOJ7WagnGWv1pE3RaZPEIqptH+VOI0M7J5itiFATzcmZ/UGjf4YPR09XLQFhPFAQ/gowdb
0DUccFvjjUjxpAJs4BmTQIfQwoBF8Qb+FSidbQSU1NOlStQ8VoT+zOjR1NxDHBb7K39MToLaFRVg
liuHz7P8IyhfzgqWR1tTdVc1N8HaARRwpXFVyw8z0FOueH38ZnKBsjdJBvocYyEwBgqEWY3RmUCE
/s7vvd2DGWXcYo0PkS9/ZtAOzFq31FyVUSnq5keZ8E/DJSn1gGb/3JfwT2tsFwCP+i6kFNpQ70wW
p/8eUJSPoP9UXt74wo5GXv/OxINzLak1XKgl3aOpT6PqHXFrGuDGWSLE8m2mq6H5E2bRgPPKb7hM
fk+AeUrug+h/FxvMA7J9uOUJEg39xpjM3Ji+kqB94/aMKreMdktUzl13YzCsboAmtj1XPeEiUszl
wWH+/eHjxXb5LC1CMi22nuqNpqN+DwWng6DSVKw0m+5leD1eRHp8+g9jAq92PcPuYy8T5sifL0yA
w5okZqhYuAMv/Vg7p9TWBMmBPDeCbHAJ6aLvBuTqIGDXu2FRTeee3Xpg9m4HF23vjUqOJtNSL0P2
byDkC5A53S+q3Co9FIOHNduMvTzNuWAEbPWA2yBzzX9m5coAETYI58vAgkd0L3pmV8WRQsPZVNmw
C3Yb635hprKRX6R9nhcKc3NoA1ozf3oXuacUGL40NBZ9zuqXOXHeAi5CM8Etk/GmHU8ztURRABJb
k6TthtRUvQNAIAFdaWe8Nq57eLVPhIGsuyfehp7cfEWwvxEdsjn9LCWipCRVeJRzV8i06pHnLeE+
6x8m88pnUYtym7jKWy1iJPdDMrYPOKWLZ/tTnNTO+wSqCwgTHbA1jy2b3uR0XGzZ+cA/wQ10FJHp
S9BR3YyGdOqPzFGG7SmI808yzIVoatrMtoMDrtuXyrEfppo3xKEhzRBzLj1tgirh2Y/S2owooASG
T43WOP6k6sU5moEsodsdZXZDYC3U5Om7vLOIt72O5ZOE3wDuxHIKT7ooPPgUheXFGUNKyqnTCAtl
xXaYdnkG1UGp0dH9YtJlcLNVkcG6YdmkAuwFgrMY+BSXv8IskHNKEglc8tBaaA6cT3SPDnIDWyBg
OG6VeO2kv02Wou3HNJWu/5DkyjmXzduXP0UsCgyzuG58uLHPAObucmHKfv0LatBH1FYr02Tm4bO8
7uBDSeD9sZwIk7L0Y4NUHRgUbLmV1ie5caQlocg6HS/ksz9gDAdsT2TNCwEYjDA0SiwZ7BYzRtE8
rlBePDmvuzyoz3y+f55ndXhdAoFElE+AH96j6x5C8HOPszlt0KvZ5RlKSyiVr2J/xhMKi40vJBc6
O46i6OchEZbbP7dY/tOpAtl/I4cpIEx9XDLNBx5w2lVOwz46nAdzcrM1JDEy3QVK74L/NK8PM+SH
IkpmccNXGY+9BAfW8RovAP0E5tnWH5ntllsTCW1VM9M+S4mh17+5CG1LciJEB32Iladcxt/hPbHm
+5/yBecTZQKMpQYigPNr+69eACFTQjDpSePf+a7yYfAjjBnsTPpfHIGPzucSMb3lrTCcQoVQm9/0
RuRdZH1bwR1pqhvjqgCU5mQckLNx0HIyyQ83APRY6H9eA5xHAOgzwYGwZZtqdkHbU1drLHXedIDf
/aD96CsHHl1STbmUsMPsQsGYAsBKEF746gHDTHOEmjkHyCS1+jY5bFroElSSwLS2B7H+T6eaN8Ok
8UqzUWf/3goiTpOqfDC7pusJrVonAciNzihn/46lbm/jCFpxQjHhs84zvwITagNMOPwo4md8bL/s
sjY2Uz/X/2i6/GG91ZSm4xQRy7Xn0Y2CAK2+ZQmlusIhF38Us+vp/GtCK/4/I6AdyFfBK4x/W8M0
UIWAgCFKJ0mhpIFAd1QiiWRUaZH2IoKWWtdcJcB6Kcx3s4iwc1aCv4O+uDyEsXRRcZ3yhBTt3sBk
T5F1srXQ4wMxK070mJEp31nOIS+3vx4iAPaAzNjoHRph6URsVJ8idxyvG1dkp5Ck+j0duI9YFGV+
oNBEzh79L7/ckd09wpblZCA4Gz0JdkxucO9cfgDeu33wRv1mNMomu+MRA7KheylowVhXjpzMplPH
EQjTdzHZ8ihM+EPOnCrEBIOFRk17LMBx8e3sbHYiQ6406w8j7ryIzLk6MuDekI8MccWMlTW3Dt/y
i5PRV0LFWw9/I7TQSKo0FggoROn1+GhvcZYLr9/49tvn/Ti5E3BzpIJYBxdHxIzIRMxANd8DWKxX
cIKpeBDBCqSy0IYQAnyJfn7gAsBEgSfwTm/jVf/bIO56aNaXcqQyHDBvHk/apQtUUocr8YyZC1AZ
fk0Eh0V3e/FMJ52aQJqPhQc1FYtgik29ZQ6/hFxC07+4BQ80xAZ/ibIy5GAp9JKUiKJpcxNTA2Dj
TmO3TFoeRqIci8/iK4uVXAOA7gkTmdQGf7E2qwHSTO5SNTRmu1e7PRhf56qrv8fr4LafAYcTCNYq
0Cf5GFeXgicGw+h84zNmjpcbagVlHfv1nQb5DO+M//nqRmNBPz61tjdFGQ4B00dku2iIOTIGChbW
N7wX1ss7Shj3qaQkOnCNe3rMdF6B4aGHvIVyNCncUKuxCQjxArIFZNQGTAr9o5ICSHUcEvQGUcAp
pSfVd2oXDxxvCn1WS8S2kaLdE726NvZRlSiQFCPma2kiyQlOTxAv70zN6WxJEGk+rxS/O80J7T2p
4Dc5aCAaGgIwVy0+OKs/87qLCyFaclqSTHWUiuDFxraLpgJspsceONtbLD0aTUPS9TVqdM3Vw7d/
YkJDZDZYOHiJQQSSN4jTafA0P0vcX//+z0H/V/6OmWH9g1lAPK7mg67jEMxIz53jaLjty2LykSLZ
lyrFvOSDB0nuDhtACRpFjmk5/OVCN7HRPpK4VvpbVAhMHzp/81WO1iHEjAgF7OYAEd7SfY7xKgVn
4GhlWbs2pEAv4WG7CjOEyibWiJInN51Om+usHHhfhystXjcQKHhk8QP6hluPSKkuaE7ysSLRSI8P
H6FteIVC+521X610u3y8adKvHfGfJhz9/VzyjuQt3W6rp2UnY/e83xeNkUHG++4ajzDnKYstBkvR
VscAX6RVnuJeYYbzNZFL58avMpy7fe+OC7+dtj+RlfhWSpKKLEjhmTWX11Du6TkDsE1JzcViFVxT
Y5Bkt4d1jRDDTr4ITdnRbO1hmkx310TSEdReLiHFYSO+/qA4mbEfW3VTCElrMb/00khhevavBuw7
GIOJRkQB3jGQXUjH4Vv/uSKnPOgtxkAsxDPh4OwZpZGmLGMBMLJ/VjavxvFRblN8js+SyL80lLwz
jMS8nHTM/Tv5+W3ih0qpLj+Elf/I7oWPJPb+NtYwx/5apr6xM6ehK7RKIYqtlw6tHb438OhlVIJP
V/b7YL51xP75iiz7s3p+wtkW00E39Q4U5ne91hLfMLYBxwXy5gOy5hRaSNWL2MS6Pkpb0KRH3cPy
bACTHFsR9wFe4ubXN35RJjAV0pxq+z8H/S0CL57IbrkIsbFr+u2cbvIJ8RyrJNUpR/u/j2g0GK70
kSXqsEq5/Wn5h+PuFpGVceL1far7dWRCFAeeyceJJFPa2fU4/gfeVRe2ur1HGmiOsqPPUVcBzOoo
OLf2ikErfZiLZWtHfwd5e5FM3eFwxYqJ2GHGxmSDmErkMrFrJr/kdwJd1QlQzwv+sbZBP/6w+19v
Ji5OA0XmpdNVDF4NtwBYPhU7abq7Gn7kRwFEAf32g29GWy/UbpW0fcyI4dFWBn0AFNtyWXRGuxlV
PCub9EEsDHXWORPZg/A9SLJosIvrANUgXdYbnNuB1gl/wJyGGyKJ/Q3oaPk0xhU+soakilavIeLx
D5Q+Qj3viuZyJeI9YfQPc00jBWDaAvu3/NTSuZja5u+//otr1iCfUNFnxgPRydkXHLLSz7kegs64
y34NOE2YHEWUZ/Watvz32pFerZJbQgeUHBsxtSQnHDqnFoz/4EQIslOhij0yMU0fE0mys3QpFHxZ
Ex14CunCmg/anE6SOj/B4Hi6lnxjsgmpHJ2yrhx5742FOz93jtMWPDkoCeQt5mc07uPRpO6vDXrU
VA4r7VrcPkET/Cyuc0rUSXPUhIcmlhx0Bxa0yATk8rRNjhgRemVu2I73xSIc4NNbP4Xvlut2M3Sy
DsEkc98YHtWVpkbZ6C4zr8KYwnYCeBAqM1w7b2qPz7MbiPLVkEST/tfm8vHKWwNoMT+lRiRb0IY7
Kl7LXqQxTb+eQ078qfu8XchXaLmBn6RMZw1al/o8DannaDaffwx8U2TDtyGLLzbMms+8lrcPsj5+
q8NPBcMnq+gocz0rjISkU8o472S9LFvKKmwcaWq3EbY8TX1iCd7xrRognoARiNzmOScUXHWGoP2Z
zSuy1A5K24YHs5vAAMfKdnNQhCev7iU3zUiTLYA1h6usMYCScDBF9cbhhhNF9ZMk6fnJBOHvH9EE
0PZBm97HkJkao0selXUFuVxxPZgvYEY3MhZJm+RQjZRLwvrOlqBDQXpHpKdHoVs+83yMmouqWoYo
yZ2aSV7DZeICM5zJurKWuvcHRJTdgQj8kz/cIix2Z76YtnKrPGa5XkZWHdFS/1TsXoboQ/8+S06q
1wTOyhYJU0Ky9SaKVah28qcjU3Ms9nOfEbcNhv7kTWJGnZPNsEqJYqv34WkCPPyv5eMFsEQk5Kf3
JGyPyVQufgyN61LEk3WzuOQnIUJZ8TsnLRd1jaf9ZyC/m1Lr4dmRFQ5ngnihAECVs2/hBYcUD2el
TITLZgE/CJz9P6uHShkHEbs+uCLM29+osXMZJ+BxlTkENNbJm9BuJQAFV4tdzjVZBkZevEAq1S93
0fOfy98gdf7E+3Pz7pCXAVVTF60MhFttkzO8mUyVnAKN5rpcuaF1o95OlFwN0Ddw9uN4+LoAtGdv
Las3KzKCKx/y6mvG+F1/MiDq5i3bwbG+C+nKo9L8wuYDKBQpgpVitBev9FwQvQ7wNQ2LX88Mh7zc
gafJ6HzyMU2K9SeVZ60mUbXvqwBLweQxvWIBkn3WMdniAwOrP/icYKWU5YwBWOWbcddEc7SkKSNt
BcV5nbafIGr7UIwDmUw3YpBSUVuIThBXhUzunXnEGCJg6aBzdJQyGXPE2X5ogPLrQXt5/LtI7nfZ
q+iTgx+YlJ6Cul5dWnSyt60WKl3hE3E2k3WrxwTjZT4V76q/vRq79rHpUnQc8v8DiaZRNhvJpomM
1PzD03DuPmwqPmeRm4CDYbaRtxNtQw364r3C7768M/6LuYLXSnOgnU2MrOAbot7FiK7XrE5nI5/c
j/qVricYWUBY7ZSuSMlibjAGgbuukrJwuMnGEgnludBwRCuawEfVxVkcm0qQcW18NgAppZbvOOXx
zCIoWBXeYrTZsk0KV2WNB3Gqh68h7n8XRT6+cbMNVTqMpDxRE29YPLaI0YxmOy0fL/vWW8qfixDM
B4bjBChMUWeuVa6L9Drd5B7Y8rwIhMpRXHheNv9nPCnU97kg70NJZ2/YcNOEy7vuV3EECHQtbLAv
obDWm/jgwICIFq/zCBxRxoJst3LQdM0Dm2pOb/Bdi+EeA0797TSn8uM+ESozOUK8ylLYZmaKuvLV
1iULuzSZ6ODWElhruUiUZ8RY0jDTVsPdhH42wfb7p9HORXo9boXID7OllvGi57X+MWDxehe2C+EB
9g8o6fC7cBvAEO00eL08BJW25pvAyPOwfxJbABGnOWdTAPMBYf1gAJCcIzkuDVculxCC1VRJc4F5
6kfSRlTrhjACEqiu8UDePxOllGQYutNhy62tZaCTidY9Y5Ck3wrsob13N6Qdzkgx6KcfEdVvBqz3
HQ+b6RmGwlBOvETJJRuyyroHOmIslbtKqm+Hr+yoYyMTQnLyljPGiCF3kT2vkIvtvm2TL0qeqk/I
yaz3TPcAwdblm1gFOUI/AumSHgrURKxJfBML5Bh/Dw7JXUDU40uh9raRswm8IngoEzs7tCllZEHK
bjBi0Jbjxi55dcg24XTQSyeAR02V7M3noz+GrConu8C3Cz8RfnD5YyZKz4NxkGRg6PYbBd+jp654
b7Bs41JUAfEESs0O/OoM1FV9hT8lVnbpc4eWfnnxjGAhtu2nDu/1mAR/VzxNaYFWWV4cP64nl/0O
e3S2EVQ6phj5zQP3sOMkjVi4npRHoJeGpUqIqDXnqauViShKGWEs2FMQsSjjuOQYbrvQ9XsbxtU8
heZ0xJfnePk80OsS19xQm+OcBMi/w6Fu75oWKTBL2Qer66Lfytg9mxPqSHG8bGyWoFN331UY887E
l7EpJudsL8tBGA/iWdi+Ktb7TcgPv1lP9oWcvxa5llTyEPGZjEnim15xiUJHFTWIYQjy/QZWqRov
x+HbfGXXNEycru+/jP9EVc46rJsjMauQuhnARjHT5u9nqw5oJB6agmbniQb4b6rhuIDffKsrtpgu
Kd+QUBadwfS8dYoCKqNNmDYy6zKg3079pnJ/25ugPEjAmOMtqLmjq7lVpfNn7TeFUIxslF7u5EHP
ln5PkFPUK/mwCaUIdcEPYKaQJOgfYyyGKRH7aTm3BzrW0XPHVGVqoe4M4k6VGVWeRDUvQTVSOZjC
xTX0O3sXky3UyHf+Nxm1ks7C9VptsYNTpPOILZq0LHHPffqVDCniUgz93JL8uONZ0PxiCO4PIpEX
wodWH5cAiesfg6ms7TjmnvA2UgkOd8W5bFJubN0LlyFj9zD7Cmpa2xhx+ru6lOnO0vsK7ici9QRe
lNl3bSm1DRqO8gUuvMDMWFNBtLKPDr2kTXBJh9rrbBnmLrx9rbBbhK8xRm0btopxAAgso35D0dl3
wnXIkkwyEUOjll1iL0z8KhqdAWoB469XRmwl3SwylFo1//Dh/T0WmtlGhyCa3NxbktFpw/P3IVlo
H3VpaOfwnj9HAF7jEe4f4sPVv3jfjx8p8Lw7UZv+lniaGwU56+bHe6L4VMKwT3oNZhDbQpWjGd4I
+W/3dQ1fo+ERkmFYC2dDSWmZmF8WkNO6PIzrUyxCcj/8bEAzCqDPSJ57BZGskLL9RKkyVDaBSZ5X
EkOZenTMi+0dmGTbEsv8GmVBQdWLMQrPa2eswfU5kj/AgHKlmU7QdqopZwioUTMc3DBGY+LMKeHJ
M8wKTs8/uQqrdG+hrLKJHtkbsy2ID02wr+RtW6QiDTkAZewhs5DFAXry0vOC+RyIFHdty54oQzzQ
ryf9o6Mmji89LHlpRXs4702uhaC/at/f4X/y+7bBkhRHguVblgxVeY8fszVNoaeIJeSoXnllTp8v
NNU8iHXxB9fp58bgvp3pse5Y4UIp1Uino8UK7bVjvu3T22AHgHqcJF9cl8dzqs/1Uvbyd+hbGD/x
Sh85ku4PvGISicWCKuV94/z5uziNbRwh8dswJeeZj2SkWLTxm9bI1e6nzu8Pm1D4i/JYTbg3ilDq
+0wThrTJ6nF/dgfxwd0zMbQPS9OYn6Ftibuo/DRCkf0oj6v7yjfjMXNZ10HzBZfTZCU/2MPOeDuy
QMn7tH/8PSWfI6ZnvZzX1jSCEyHvSmrKQL+jTmRnnOxlD1QaKQ7atwXHFeg5Jo5G1GX2YtXTwD68
AZhcoHYInUE/G2uMQ5L3zUtOcmRBEbz2IKVVQeJtf0yRhBbGrkIKIbHPsclD/HNUUT286GGfYes+
6bFyz6yCSYhq7LLm+6LKzPyEcaY4CZTTSuEazugzQj9y1cL2UZ7lAEKxjJ+FuQuwXHcQr4YZhrjA
7IX0PYfENVHRkfUQdesqD0KNY+AFQi+0RHCg3OgerFta6XsDYFeLCO0bFnKg0KgZ+WJ+gYO7zhO/
ChFztzrrZ2QcsT73v69fUQ9x47GiJtrcSIAxJcW7C058BF8VCYsMa9nc1zOgCbr5tNFLjpLjZzjQ
aCD3X3lEjCVmg6pf5XtPDu4sr58oWijuYZQr1hlzHCkk8mJoWdBOeFxsRMvhhqWNBwumfYiTcYRh
zhbbAPN47rIDpUhErsk9zqAEwM0kP5nJkforKmG14WqnhsPQGNmQwjA+gdXTavEIuVv5DwGr5a8j
SmLgEonMzUF4+FGyWE0z0j8pi09SPN+obHZlqqYGc8EiQ5BA05JKQxkaHuPRA/vkIOKPmSPQGA9L
rQRxoLnr0ckwP/+YtDuiG8wZqMjejoNnPHadqY4yqIGwjWEzVlF20gu+N/FEP4XLocXtqt3ySW/7
SU/Akq/v73oO5idjQP2VZGb5jgW5T8xodACAWFHSgbtFsvJAWppVDw0tofkxD6l03yWet3uF9E6Y
nEJh6bTZxwug555ZuSZKSxmVpdB5DELg6zxbckQysMdjyYurzlc4mpp0IpOPLjy7Obfw9srFuG/7
hsWEUktfJ4d+TzTibD5pE5G0bW+W2JPLJEZECOqVOirjm1lgUYoEBZwNAVbrlJJiUjj0/yZuLApB
WU14Vc+BOSpEdSdbrZ17e6EyUfkB6skTdmCcFFO9EAIli2vtZ2LNX50pjhf2VXgATwncEWSgBy61
3i2GVszmWPnSZY+WMRkkJC1/OjUM/nEIOQ094M6zM1/T27SEqUEBI8YS0eKgciMwLDZdoM55g2dW
DW9c7473HLnvBcPCUUsbRl2m1AYmuKZjfnbnz8Q6uUKzhQYij9WfoIW5ajwdoWmkE73TRceHK6+B
I/kPbGEKOuzs+sldc226NtLPAehYy9TmKk/uX22pIQmLCW8YSnBLtm0u9mo9RSEGNn9cIU5ujluU
RAACoTei8+rW9CgKU9eV/z+PowfrFVp0te3TekgM3jUU/2VYOXihRbyoCSDb55y2YQ6T6HWhSq8R
7ZvJzThc50YKGh/feZlwnZKNSEMTMeTLGSUPhexeZEdTAqfhIL31viARhDkWs46ozH0X5uHYSFrA
RuNyDvvEJK/E2jlhwdQJ4nqShWrvR9qvuJ8A2agqqFHeXeAbmeHq+SPe75X64LcOtYfBnAvC5EPj
H4U29okRhXKSljIEsYHtoarSxXKi/UwvNY/olTXNzK7yb9nlEei9zqDhYgHyQEwi1XZtcNpkOubW
7j46bmr1pZxsbPVe6pey8YU+6FLloeE2ZBUiv3/9e6bom/jCM1Y2WNAPIVFAL84LRH52iv8JVrzW
MTG+D6odxhJNe/7ooVpHB2VJIWYSsjc3nM6jhbLb13Phqltuo9l3eF26SfCVJWqjhyt9qFSgrAbw
ayPRvHQsRezpUEkolQdKc8Sw/NGQtG4hQ0ZHd1RmAS+d8VC00dHjq5PEw4OSH+Gp+v0WdAPDYIU1
cwwYduNI6CqCh4oGUC1/w9Upu+4yShQV8KDNuk1rQwhhydBs/n/Fw4RHFt/+Gpa7J5WBdS5Voau8
ihxJ47g1FwWbiNpGmfBRb3TYLgyZmTs6mw90BUg/psVzMYuLRzDouYLCZ9IROvA4Tk0c/OliQZL5
DLr1TSDnkoyBS3frOXRHp/ZFFYoxfaCXhz3iDQI+VbprN0hZ9Go5A32l55BgMKIQLfGOI2BCwogx
2Vk9aYNGOMJFNuEeTJZdbMK/NVOyBBN7wgaXxK5fi9pBjYtewfAh27sU+kLzeG21W1sqoin5s9bv
vvy/0mPZ/fxYvVSqVXORZGhrw1BuKBr8h6ui0BMZx62pScW3bGSXEghzLwHz18Z2wbsTVvGbplsD
VRyUD4z3FKkwO0D/YPcPbAH2Z1Lc1gBBW3R3lkSUIL17s8aITK26tV+jf7VSNUkDbNdZ1AL1TINH
PxnGYS+QRkC8cpdjEpROb32FgNKnoxAILjEVMwegiLLVmZu6I6nAq1aBf0hvTIBNblakGHQ6QDdR
0pE0Laq0LvvIS2mHIubwegCHnIZqoi9Ewj/NKxtAWlY10v4BEWc4gXwol02DGhV4vhwdhMyJ1mFC
CjVwCuWI9jkZZzBBb25UTtskhM0+teQA293a0MG2j2mxVAfYDCFZMe8LQw2g1HAWvSeuMyu5UNdX
ieivL7KTfkYgExHe07LAmOCuRtK+vkmbsu2O06WA/2WqYzvoUmaZX4dnUOVwcedroTEA1uq0MxzO
YBX2fRVJooqwRnIKgbuzOco+OrrP+VxXzM04Uhkjb3qDwBFj7RcHPs7D0txIEzMuZnYnfg/c5WyK
8dUePGmU0A2+ENoKVn4Aj6mxKq4MkwuE+whrlPmadjH2mof9isZNX7AuIq/wG1zRGXvpmE9CNfDB
8pdidj8XJCXx0lLgJkieBsVlxpf81qIREv7ilrhZuMoT5iidQcaKyp0tDScMDtQ1mIFNl+AmP2po
yLuDSYlhOp6wvS/4p5tyuQO+7lw7fp5dZYj9/yWRjz1wan8TWBVaqiGFlakMrJWmyCOvWGDYO13w
dZFlDd+He8n1zp5Db3YRDnjfZ1RjvuC9u0XJa8cfZ/KUXQgHaNcXnXkhz4yT3f4mECqRbZ+LAhkN
9/UnKtKAezBvl/+jV9XlMjBzgZ+nB+ZsmGsCE5c2UGp2u6IHkCrdi24goLA3xF/NDj3vTRj/6GTZ
uFpyPv1TzeoJCCLn+4eYZdI7bOlz+6HyPIc+hJ5YeXcsX0yJ7UNnbCK5PthNxEtD3NHnsGs9WgYM
bYd+g2JQ8aDypuaWYIcLboza82sMa+RnpB28AB/HqPpqjhdKvl8oi0sysq/UvsHwh1W/h8pTMtAS
mCjBJJ+33N7DWh3vlY48558quUlKogGDu63ytS0M9EpFca3HnChcWdbjU0JddM6ohXc2HEPHemlu
JPzG53MGTkoCFfrYe448pebYgBO5L/68IXD9Ml1gSUsyzK3wZa/UwdqzqXFJv2p4M4/yQGTA9uu4
CNOQ6p2BoHoHwApyKuBMirS1ACxnmq8rcB5t0ypyQ7aeGOB0GjQSq3m4WujKPsRK8p61j7vmjNBn
Ej4IiZTr4GXqqvnOyQ682yPHgsC3ZKUuuFsb01SKohMxEQqR3ljATXUC7i/Xxw4giFAJ36pbvCF1
2AqTAaVkTi094zRJ6+HG0s8BCp/8lLcErd1GUsCJfo839dOjFgRFTs3EVWDQZ/MMZCXYso9qWaiv
OvgmuLQdi2+snzJXutik3eSFBvgKDY9LUe9NyTubbeaEertfnzxb1E3du3CVI0qaBOSSvhYXHuqB
N60FDxFr3B7LGUgEHYqrFIfQr3pyiJx3Wp2sSZAV56DYJ9wm89dITKp6CRBnnA9baIrB9Ru9rCoa
8vkXpnrt8cp6h5X1z/heNP5b3CmPhfPatf0SfCCJzgDRCO1AItK/bohHJAM7wRZB82VS0Yh5A8Gl
Wm1M+rYdSgk1pqaD35dYpcE72beYcv2WcyqKj85GocBjp9Cu9ZdUiRYO+U8T4vDngRwN6xfuRehy
G31VUo8MVru/ZKuRbprtRvaRxV/lD8WurgIjEUyl4QJDw2EAjTNafRDjKuQ7thAm13Nk1RanfC74
C9+JcKS/c2as6wLdwbQExmyoCsBxxWe4exGQW+uZX8628JUhAGRdU6BiF8TjE7yKkC3EowPBQOCr
uf4FpPwZFCXKye9FJdYyu6vE5wBE9ukF6wXmfetVV6KgnR8WAtbzVBkmp8T9a6lEnGuaYzGlLwRo
xmU6UMEX//ZxszdP6XbeUAu0FYUDlfrXS41Axw8kNqySVC5+grkgnj2H2ImK+e3XBA5nrq3mjxog
lqG+h1a57QAHZdMwz99fzlMTeSyZ5rn1NyWkbR1J7i95O9iZsR5WunjsEGId7JlmLjoAu89hmTd5
SvTYgEnRbouYpW5iIhoRYdWzUv9+3xH7FESno1hnXnrsPbdPZMmpwPZjznWZFyarEtcT7cm5wxay
rZzduuCmv+CF2TWOPXCsxJxUIoGhjvH9yTHoo680tychqNRZ627wAoIf5RWEFR0MXTYGni/OJJge
kJGLCPmRWzjYt7ZogJQREN0gArcb6s3o17/dN8bFPQqKXs43s31StuoaEwmSIhAyVTbUoDMROJgv
u7KvRRlgq3vVlefZJyHZK0Lk7M+NQ/LXy/KPRiUPG+SoytXqEEniv193Be0cRxvVeTEfszuovFqs
79yYpAT/kHhaQ40rTxZju5TX6Se9/wSTuUkc3q9EaDKkklrWSsTW1VwCt9YaTdoS1fpv6PkHNPD6
VZ+ZJYF8ALNaRNlY8gonjkNY4RumZEQMGpJ1djZnIKMpDJdtswPoI3ftVsmo4rAh47k3AxbwH3sf
3YRkmDdNVllzXC+1/FH2R6x8SbxC4YGuAlpyLlGwo4ut7VzHS+h6ixXFjIbQW+6PgKmZAn6bqpsL
8peWInjmhpFjI5QZDhhotxAzisH6JNXhiUN7cjOHR4+XwmW0cYVN0mRI+OXz+C+Qwh74aEzOon4d
6uQrwTRz1mn5xPz8ksqtNSmWwfg1zcOyseUY7PnVhDfBUY1jmHiIjyt3xYqNruLxwKwHh4NfFjmA
4tpW1j0UpLEXeM4cevZ3iwGxOMvv99QiKbguZOWAVbxNMq30aacfYKiRukCb1V2xnrFKdwSeXQQa
7ZIxoXhVqPYvwBazQKqGnRj3JrU2F59tErp6if/lc6KHdeDia8kwgOeGxBY7OoubAlO0BQXyAqMO
HXQ2cCNcgMexao+RBIbQbHgFL6NXc2OinprlQ9+r0GXsqj/98RGfbBLkc7pI+k+iCXqdG6OFUxSy
2L5iDQhaZRSwuV878QhfeNqs2JP6Waf/RiRItsmSitx1kwC6uyx74o/eSuU1y0q1rX2yy0wwLFIH
R+dzdWgaFq4SCrEe9L6V2SiZaOSnKDfuCooJa1jOpBTtETDnvswKporwMH1kd0GPhRkr/TdkbB1r
0J2IVdYahlHBLRzLVTTYbx8vFlhdTXAEFAyr1IpOwyZvkeJQ/Z/5vufqG1QW/LAJfMGIQ1xR7fCQ
t/DDjQZubod84/ynRyVK2GbrA04dxZbLBd2gEDj2vsu8KOAkM+Yxb9s0tnXicDJVFReaEdLCy1Yk
j2CspmsidDWuvkIqT9g9vmlLmZhivFKaABvKH4gGhm1J35M67Hah5pyOnw54J8QZqSYWY8D7YqmG
fQZC+yBWyA2Ay1hDGIJhoTpSfbEJ4BVXc9PW4Gd50RXZhKA7JCJ4MtUnA6kkZ8LKRXA+Ne8KLyGS
dv87KUwDMGCJ6sMHKWRZvwnzvcvrAtqOBlLvcwqWl4x7zEM3Plz5hVRanUUapkHW12dnwjfVM+XG
MtxLefOqK0ZNPorznEV1cNkpCdxFZW6T/2hFcaJ4CEcRcHS8bztgnSXh55uIgwV11WNba/sCni8U
Hcd5lnmCHgaSoTYjl4Y3CekBsZI7ml7zf6Td737R9+VzMtT5hVEF5Cf8aao4SO/XySL/BX7wKeb4
qJyplRb0OhjGCd4j3Et58fcl2YgJSYhMhJ9U6jAuHQEcHIjyMb0/Hajgd3IXPuuLllvoBcpR7emd
SNjm2jlGGbFQDYSibj8yfSZ6EInetlo4gBPYx4zEC8FNFer4zQQ9ebU25ioa9rvljbsXM6fSl0iU
hnLgkbI70xP0Xj0qT+D4BBeyxe6JUh9tCTk4ZKLOwrwYsYWOsywsPPa9Oc0akkQDQXUtdw+lCLwc
PQkw3dwUmgW/EuDoNIatUEjjLcsUM6Z3iDdjTrQu5jUBDxieob77TmuwZcPtX8MWafE4R4V5qdUD
2D1wI4bF47EglveNdJf+zRCv0Kvael6U8pPhQdzIa2l4ik7Rv5/Tomjivmq49c8Ar6QEZrv1aXRY
rDltaiD8S4/5VznfgGGxKnTh1uzyDhdc/tfzvWbn8ASaKCXLwOq+RUdQG+NmrnQQ7BJHpzUTaBAi
KsvuAU8W4Q4Co9kDfvsf3rypJoTvInflUdvgBdzVcQRNCcIiPrq9GlK/GWtCQXJI2nJlkwL2I13V
/p0SCaIxkwZ8YU4VtnrCl8Z4ElcHyPJnQWDdm4WQbmePtNMTLVWO4OQ+WdBLGABmuFj3eYN1H6fD
tscwVaqfng+SAvXepWN7Nt4ybLnxUD1ppdrQEFTehW3X6rl6ygMYYXnETb18yTJkFdg6/lEoELoU
AHu0ZXm3xC8A7oDHwQGRi4pebZPMDFmwKnXHtvMsgvcaexiqsISWvTuiLzvyJP1Oic+OIYSmxccR
i5cDmYYd42MmBGRlTGiMQcN6U5cAwr3tCK5qvVtIaZ6QBDUMzDpLfELsuKlGizcbl1UFBrfxUzCT
n6NPWpVL/EBXyyih5wybJRXQCtpTYcZxwrzDlRxO6zzLOXG5z+xoWz665cp1oIUX+qc+eK/Cyd1S
nY/KS80nSUZxLoBDszU8jyQqqhXcyP7z76Z3UOo0/f1hoJdjG36k+ojJQdYKeoTtsljVnUSh1ox9
b0jUuZ+YWavWFygNo95Q/ogv4bcj4CiNjseiJv9RGdUP4Yc6dzRH8QKkZX0iYD90AYTX1YQnhlEw
zkqPH0seh5uOXN5JjCjnh/3/RcTR1LxwQubw0wxtoFqNutGZ2nYpbj0NbOYGvZTobA3q+rQBEQjt
nRHRxnDL44xdUBS7VfLTZbV01Q8A+cbpbl7Mm3HEv/sggSn2jMFuXOmseX7+/K9kyfC70G2sz6jn
0/3P36N9HixcGM5SifKg1uWJM1csgBFxuqIE9eCB6r0rTb/s/cAhMPOQb0sZMWHmOl75nZ7TnDkK
xe8mxofRPZpwi3acFE7KlYp9pfMezZwGLD0w7u5Bt1CZuPlrDYn1+36Hwinf2X39WI90QPVzH+0Y
qK21MVKhTUJA+hphGmcyTuQtfiwUYQBCNrROaDhQ9o3OTnUIwDHmYeQqKoClxiEA58T6oQ4FWh20
vN46k9u/tzeNDSBdnpqokXC0YvY2NQQc7wxpHopNzjwLTo8p2IV3X8lw70QfkJkFwjgW1iWtvPEV
ZoZ2FPgGtcXqfkTwugwk3cgRz9Zp74qMArY+CYXWF8xHrYYz0JnUsj1NiC3tzCisboxdskmhf36f
gk+DdcwDK3Aj85G8803abxahJ36Dy5QITS0Jy/4ERJooqT2pR5jeWGO/1fI8MXJYWoh2wg4zCMo6
os8r4TzZH+A3fuKItw4ksAtj7uE6qhZ8x5KazrwhmTe1111nodKQKPEGsqy1yUKahaPGhdrMUOJm
ndtstxlD9B4rbs0I+ber6S0wrD+AYNGT39R8FkVLLscR9oTVmwd+rUalVkeUMjvRQ61vGQTGBYpR
tFZ8gOu3s4zgPJOFoPfgPEUkrE2b6uZCKmmDZJqw4A5elPLDS3xoXDTB4eUoOrcKodNUaT2HqvI0
9X8EbkkgzwFf6UN77eyxf4XZOCW1vv7zaNeMn4Dn/r0++j5P7MQIwEOqC6ZM5hq424QmAevQfl7h
6WJl/zDI/xzcSNiPpHDbVxsdKpNk6nOE1epWRv7CbGytkE5KnvACfo5LMDDQSqeOxWdntjovkoXQ
7ycNDH8Gz7JHHxzZrs/priC81f0lDlpSaaKljZNzDFy9/vYnPUgMcNQHbtRh1xUKw+oUoq8z7lO2
r7N1mpLCxsbWOlLquzlCg4HGwzEhwA1K0qz6sckrx8WVysqiZB6+qQHk6XVG+D0S+ybxGm7+VICu
M2zhtqPvdyOqv33fTEk721tr8G/sej6f5x+jrmnc2YqPcr3IJe08IGh2C36qhuID3QAu0PDx5OzF
1Z3gEeFm2QBbzqeRXjK5D+859GuBNti3sWj/x5N4apviTd4J1it4FNS/HDxboJdHdW54XrkG9isC
exCIlqHtT3ZEUu9xKf5To+75804as63eD1kq3oSLTIwuG+TCC16l77NBmMursZch+KNFuRfAqgNh
LguH6XsB9FVW4aAUhB11EK23cATolIGzihuZKfuFlKlYOGtEAeDNBr/1J6iNsRDdYkr6cf7hVKXn
IFNlpi0Wt0ZUZbuH0cb5+E344nfE47JOIM2E+3FmkbAJ0S/HWMcz0ZEIsHY2m6Lj9YGQkpufGuWZ
7AXb+WCuRQkg5wq4fdWhiaese/4T85gU0vqjIO9FTTsfDwN7QJhwh775NIsmHGE9MYrFQbjQw9AO
RwKSjUqaQk9Wcrq9ul6iMTbYuNGnO7Ibzbr0dW6edtCv0ivHXiEZRaWun5EplmRtYuux3119Gsxh
IXWgyRVXQUmEVXH6VJt0UeKy0bYyICYFG8YyPwE3JXQMcrkrSNmeKIIhoCVAzlYul2YsG/iGNL6N
hXR7r1+W18A6JFc8LjQFc4QNUQx8ZmPXoH8mHBjoYPNRjvQ16+VFpxgxqO9NkkI4G0p817Yjb5Op
gUfRAsYip45HlaMDeHO5MwzKPvmMpKtzp8XFm4qdxVTRDzMgaH+rg1OQvXE5n72rKBEWQ/GICnFL
o6Kjp679CHsWq63GB7/qp9AT52hxrTwrHgBrPKu3ycP3kCtEBEbdbwZF+M60pmBegEsuRzbm6ZLL
SC4lHbCTg+8Ril7LbIAspAPillHhWkWBT6eIkO9M3oSsWUTHQUL9JlZqYjVjrAu+CEsmDUdA0VVW
Y193BtT2TqNFw4ovjAEpBZFyOIDHN6HiOQ10bbCmcCN49KLa/4IEsTDZ4a2L2Cuodrofo6xOpjf7
R+2thRy3UnURO14vjnaPNHbgaiMITU/3AHuEpeZ697ZtHLKV6t3g2xdb8+BhkKjK/vcYukpuPfUe
Zgm6pC7mHX4n1iNbP2SJ3NPIMNyS/vJXqLlmnej2aGr0Ox3HyFx0LB8Mnw4HTLuwgQdu4gl1+1F+
bfbfxMbzZROvcxSOrR1u5Qlld9h51BqczF378pupDDyEEeHez2JrXNRULUJW2rXj4DsHMWPxA8uk
J2fsyj5fHdEjvfcM25SK+x9b+ecSkC3IyA/5O4hDGSJvkYYREbBu2U3GI7tiEgc8OgDG1Tavhyh9
KUM1aR2a7Abim5/JoPpOg7EOKOFVp+4QTYhIGqcKNDuyCpntTBYEOWmLJ9z5kmcm//WnrBUgUQR6
ggEsqUz8M9GvWkkfQ18ODmX9Luo56wjIPskU3FdAO8s36MIWu8U9N/2n+SeusSgomem+4tTc1C/a
uUn3M+prgSVCc+Fh01c6YyG49KK4WJJnVHUozIaztsVWYjoJH61sK4yxa6DD8LnJxkk94BmGX/EX
c9zUTBYE6bl9dYt7vd1+Z73agD4iauSE9U1isRGqmAtUtnqsRhNV6axJiIr7tin/A7cwWoKGOrlo
9AG27/pmjWzfps/qnJBg38+DTVoF2fScl8rpD8B/40IPrfHhUPcEW/C8EwVEnBk2SIjR0VfVSjp/
piZwYJ6eZjzpALyDKmBnf9TuUvTDAvHZs3OJzbtxnqAO5GAnEdXFzqlHgwM1rDtInnZjietJQeJQ
ltNPrPwdlu1Rfge4WhOnXakRz0c7e6qWYc5B9e1eQrkp2MG/JQLgFC0POCe7x2AThpMHNuIynncT
iH7FPQb5QhM+PmTy2Pnim+T6cgwt9YmhCXgXrrkpH7w913H/ycK4xVm12NuXtZCtHRu0J6UICRc8
kuoXTffO3ojr50HwzR4swX57hHhUqIZjD7wXWXpRp5Za/Z9yGisuKOkQBl+dm+IBz9cOwjVUrTzE
xoIhpGt/eiox+W8A1FFrYjky1oag1zLbcDRTIIY/8zxu0+HGgkgIqVLHV+dAIitwT7YcRdWKYT49
gPRJOAf3l4hYYiJlmJ/gkwDsvirnjzXxYKQSgCJBrph8RKSvd1/4FkiNUIZY8CD8Dp/5DepAQcV3
3KaeZc6t5fZ81eznAar6jehu895wyToufE7jwL85HTmqHlDyR6R00s9IOV3vv867njTxhnYl+Vro
kMH5Em0LDlz/upuh7u/LilF1ttpGnpeiSO0sVrjQpILXQhdUt+x3SyqHEdQLtPQeAR4p1VwWHiTM
MWvb+s9zL8e7TWANQYs4KTcec/IiQfA6PdQ8yJ5IqTTzU7CEtWqBwlHf//Y/UhC64i6dYzbf+J5Y
LS5TNgEFqTvZ0xQguOae2nsazT3wnZ6/86+fXBtEY1wT4aGtVtdBUS4BCJXh9OfEAYU+/DpGLH7w
aNMsMQY4u7NvVCu8XkHHTROr4PXe6tTGsttFn+IYS/PpCaRJCMWHaHR1KZ/41zD6nD2A5sH9ZX6i
Aw9I99vZTtIy37pouH0crLtDQGZLxTyQ04QQwbOLowZmjiMBohpMu1T28DD1JtEfQ16pKitPk0tO
ogfjO8rVZ2RNiwjEiMpUUnDuKFhBS1r1SDXuWyev7wUyGfhsHM673knoY3lOAuQaY+KKZgW7CMaE
Wy9jpIzXGNWOJL3y6FVz8Ix0fWwHXxKqhWTSLzT94ueK12wp9RgeAMcUq4/z9PnxfdOibbly9jwj
HgyNq+zWXomlQEpX9iMfAYRBv3tyLbGEQu/W6cNS9PHyFD5H4l5haFBVh0cdZhFLDbyE+bR7DNv3
/0q6pIqV6TGLgOPDIWqlGsHFg9TXmuwOy0J8lQAfbeDNLPH02cnBJoijSijQBONf2VorNxb2IsT+
5toL7uG1zyijaRBqOIj+7J3wKRCPtFGWsOjEMad3vbPYM+MBPUNIoPzaB96mlRLmJ0z2RH7/nOsj
LB1tcGoacrf+s5nZ0Du9mFMZ7ac9/iALatbnJ1hFiv6DCS+RjzsXLFEfq4MHyRwzY2xV9Z7Ssmp/
OXYLqsBnTNPHD7iy93WWmIfVQL3tATxGgJwhFF1Z5uk+hcuB09xlf9knxy/iNnG76P1dXG5fEX21
xQPUnoyvl2Yxt82fMsUQ7q0pjWivrMEdELEgOhe3zo777lTryaa9QD0by1C1hL+BZQSR5pNuQiRA
rE4QuUgP+ngab517H67DZLz3QBYPY1Ax1KpL4JtugcxGI15kI7JJvj4MiWi9twZs1N+QLYoVVM+7
jaW/9NXUxTirinvIaFsFKu6hxcc+O8vvBEvlHvrkqwnKHGAcfs4/nlYHEiY6c+UU28vdtd0XniLM
bsP9b+fxMfla+WMJQ9FxZDOgs8JEEX+/A1o9hQVVYBYBE4gRdDG0AP+rZHh1MfGo6i+ET+j2jv8F
x+Yj2hAWWnEPUJvnU5uDkO3Y8bS43kYN/c/VYRVcUDZ50P6C4CqCQLSMt3ZHTJ7tphghYvpdhdb0
0dIsEfa5Em73095rkigBxPZw6xpL4S0Xbr+ojcrXJofGOLalKJ5xizEXQ/cKljJZeFl89hxC8281
GLOGdasQ16IRc6X3znIcTD2raz7837YCA6BlaVda9hzNnNO7M88SuprxUwx9OzIujnUb72jTRu/I
mnSxDaPC7JSjRyBUQ64I/InodchxZ3IqCtShav0HZL524N3SXOAEBgHaAmORnfdHlVBSCX4xq+4p
tESqGDlZjznRV8S0hz9ZFuU+NO1GubM01aqIoaZvtXnO4FevD4ctcOBQ1Do0wLXB7u2spzmzgJFv
0PiKZGmeHUh92C152j73pE7NUpBM8VlkXeV1oBAgzMjSF/egJkFiF8igfQlekQR1eh0ntiRHpqOI
4QfUMte890Ip27O+cGdYMzzbNJD7FFPCp7t1VsYME+EntC53joZECAz+JRTHTW1RTODU/zh2KFRh
Wd7yKBGR5H+2TFxqeIKY0XPuKRDSDpNCcfEMaNnzYbbN1Z51jcQQP1QS5UFD7DPKr5cl+4cyI+a2
jMZXkGJvzA6JyScU5oh/WZ77GdgX6VsC71SBsd51BX1Gek7euMo50Nb9RuOWroNVrKG8J/OCRS7k
XtSU2WjQHmjslx84bn2jNKKIqYqOIWsgracam08h28cioq+3pmF7oz6zQwx1fmQg3zKUWPCf3oRq
A6DWiLpFj15xK4cf4qgviqXLXf6ZdI5yI7aND5AOsHBa6qmrbqyrpq5vcI9rAsZUVsZxusjznsj6
kzgWiYBF2mgARzh2a1yj6d9Q1hm9Q3NyLbYcf6x51W64pESb8k7ldRU1t7yxgrpDaJHf+/aIRWaA
yH9IIwVP04KUqb6HcnyjTnlq4U+4wMlLUJ2DXW88mIoegzfjpqs3oX/IMH33ZlkOVS0YXDR1Z2eW
IqeIwg+JnbmMayiHOfrn+CQqeG37OXG1CothEUexPTSHLF7SvR7AX5piexlA4PyjLrEYjyQSQ3Bu
8mbNtxmbFUC7Q4MMVvQWgjKlYMmv2kuGh3IjL5WRTqd6FXyk4MfHe23XHSuL7xOFq3No7ws4UZqD
u4KVaOxDz/IyqltcAM7wuYhXsPhiMrn86U6JYTyodlnfkuUDLolkaxWUDr5AamyGtyIQ31YDnDJT
D0zz7uobFZx42CGgLRP3RJa94nbY11/cIlZX69DdYLAAmdq12U3HAIYjbHjC2fLh71W6cmlVxtFO
ILhUxhQOVnjl4ojNUjIoW1VDduit1UwO9vf9h50fdCdw5JaOXaYOLsos/hMm+7OOY8sfNVBC0y3c
p4z/10MYl2pby1AINZmyS5Xdj/Dp4al+4o1QJ8ZKEmY9kmtDIrTHjihPJhkWiPfN0Kv01Zs3QtSS
ck/iASRyeM9HsCKkGqZIPIyamAEKRn+bFfKOzTKoCCpmIIRAVIn8GmEnxEjPWz2voSj7a8P1VcrS
BmSznVEefA+Egg1bHs4wn58NiXlGWx6tk7kRs3EttFXct0z9wQ+eazdzBEO/dVnFazoFfpDJVZng
msrcWtnQFP3wJvSGzQj1m5KX292s3cmbV2orPkaGtXqiiwFOlD3DtrHeliDHfpqSMFnRLpDNB/OC
kKefvliHIG7DucqklzMnqdG6PjTnKHasvvMHrEdwpC91bnGaL3rpsX5UVctvR3Ano5b2eNSYEml5
A3Tyr9Qrc0nsi/EWhbkARlkTW/VDcn09cB6XVAuCmCTBwZgNy3Y78Elh1qyRIsZ+qNNcUeyCH3V+
d3wtFyXL66RN0/j1KVUiOiqcv3EG5RfBOklGwTySc+To0zOwW9jJpjNinH2Q5JzJHSt7YBLU19G0
TvY084ultSOhqt59AhdBYTnxpo2wCpOKd1d1tfOugQG/8WqLPe7dhhjgEgrNdu9ybab1dzqRVuHD
4SFdXE3cf+ipjX8DOH4sisDMs+tMMFGbrxTx4C0XSsCsu+D4KhpilOVydjob4Tm2drh1YHK8lbrf
0QsjHUiX7UiWSulSsTQBpaUzNY/AljPGNZD/3ynqoocIZer3AI+5ON9CnKTNXA8K73sqzGD7XRYw
2T7FKtNEYTBLXd8AsMjp7Nle3UjmOdYIXDnD5I1SUzSCOuMc7B+t1hIkZRYviGvuVIUkpkBhrniu
giIKzbR6wV6UwYzrc6m+obSkwoxZATAlkRT7/dgaI1ns8vIp8dDUVQVfD76AIxs67sjJZdGhl94Y
3Y4t3cEaxvGGHhOg1wCRD7Mdb7p2iyDftc7LPZUckRiX6rLePtxWy3Hqp28KkkKiohY80DVsNOS5
E418vThgFuCeLnkiYfzk5Z5OwCRvw8BDgN2AynLTJlb2AjQhMl2mnlUpIr6fbbmTsKBOiEpXLQAB
qdZBN2I9fGzXX7p00spZpzrqmT1crymqYyg0n/v6knr7x5vtfiW4yzpY6F+pgR6RMgnbNhBcxJY0
ieF1hpKZwK3C+yLiU6lN2CZJnutyGIMDsi3I4Hvnp5qku9n3hmAxE/UwUv7ABrUAa0DYeRYvm7ZS
5OMzZFIf0IWFH9B6s0DeTO0Upbseis8uOord0XbjpMePOqVo/TpVXJkvTlvtqj62QecCB7k4a1FF
meR2I/FQW9zsHBesOFRuvcPtIBSl+vFKsbXHvaZw6wE8Uzs0djeHRfgtPQSnBvSPGgg1N8INO+Pj
89kA6LZIbBhbV+iD0wyr0KqAjRy4LkGKGw0bmzXK8CeyKYlsgaUL++pG03CJ5sUmJpMSnj7xhHGS
IvVzWKyQCpauJ7/j0Z8Qh/xV428tidsOwfDMVTURIcapqADFZT/N/nm/jEqi4i1Q2GEVGSrs4ju9
DPufJV5dTxgSU7UlWvBz0/WIbAvGNQTt296HXnAU8o003KM5QwNcKq0NCKNv6JxPtiO36QuCUPnC
pZPqXEPFD+bYhebuvDRlX+e6oHegN7tgNNfzM4DDynExn0FMLRMSxhcEufKJTaXpf0LyNus/ozk2
cpD2xvHnoYyAuoBCj3mBSftIvFTJ9vu2yQ1zLsH1VYiUj4U+JogqN7vtYAN+99ULD7rDFhKpvAgp
uj8KBds/wwKZ7eZximK0PVoC/fcfsK0ioAc62OTxDFHePNF10ashuUoFzBj6RLIs4TFIKwAyuJjw
Tnr0BLt9J95jHVEbrZJ8vsnVexzNjIzqqqVlobBjQOcipI3lv4O2izdorM9nV1K59tVMi9CA9Ook
SZ3LghakhdgPICsT1Mfdz/IrO3UlriQHJ8JjSinzNCYUkOmddAgkLZf+oMbBbXQnktCU+WIWIrK7
SqzWs6dDjs9Z9asjfEBqKi7neYr5ZOAjEbfRkXhSWPOEzxVoTk2jd47RWst8Ys8/3BYZOyTUy8QO
dlMZuk2xg/sgVUhTVkwCk/sdW77SSNBAys1kV2DX4DIqrm6jQKB4ZMIGDgulyU3guz4u4mPJOROX
aV8zL2xng0EOo6gv48NAEgSVePMFJ9/ziQqIgo/+1IhPSDKAEH3xHpdBv4ZU/r9uSOIq6WvVIb7H
kznpCES1MUy77CQ65PXS3MFT3nAC6NDQwCBLW08HYYCBjIq/L+o4wbFZ4e1BL+Zy3GTvtu+P5++9
zbgkSaEYGgkBwCDCpyKVCLYotnWiBcvk6ogM8oVrjpL+1LPw8cXboWXaOdXJncGWBTZdDYEoYvmR
yt1R4t1vQ2aUrZo9PnTqJC6ckoSZWu4H2AzCwZA4ZWvny+S88xUa/JiQnj7H1/pJm0luuCfwPJtt
Tqcy504vtjJhn/IG4m0JUPhUd4hCd/MxB2lygrZupjXa2WbTdGRPdiWmBUefM1ePhP1WwR/B8p5p
8+JtpsB+gkD3rcL2E5R7Bu5TtUZmEEztLPa1HujvNdRj/M73welPInPH9scuXTtjQoi0TKhRL23O
4SdFRDAGfJ/6Oy9Pi1X/VI5KbwpGh9fWY09sTjeeNYNhO0p3EfbjpZz8n8rAs+8T9pGXAxVlL/M1
si902l+nwu1QkFa3qTOzCpuVbn9syBLOFBO1XDnxWSSK3WTQmNkHpttph38NkF6yrk5Kc7Lc7Zkz
DXXRFq0luvsv9pZuLpGfre4whrPJQagdSrb6Sony9sL55q4mvYEXSXgNTUiArArFTVgWSgQPpCO9
KALk9Y6i06xz/jUlkcG1rJT8SojchlR0zmRMzO1IOFbHz8R1NVASuIBYf5OiRPfarDfDP5RA3zlK
YRcpnNS+1Vk19rCiLxx+Mw08O8QOAJktzi9iw3f9khxbD91uuDn4J2xuzdzH1ENYqdz26uT2cSqv
6e3Em5zLsvnH1rbNEEd5NyQFdw6j2ZqWuH+aDrUJ5hgIalvGrs3fgxSiZCCcpFEBdei3n3XsXvil
4jOcCjiKn7A+zren/8O8Efnb7gxFpurjqUy1ext+2aUWnhiLV/PefYSowRJ0HcpwcFzHp6Ccl9cj
f3sJ/XGg0R6dugym4BNpRh7keVB6GF53teaZpgPHyAyZVaMzaYc/DoEprP8BsXpSTgsHIb99eV17
y3bQt6ep/4yb68auSYInyfaLdfKLuFlhVQqiVWIj2cJUad7+ykUWga/bgkykcOyThiO1pmoO792e
pGrpkL+SOYxvzecestigAeaOc4jwSSEe/Pmq4bl033tj1nVxu6Z9vnRVBDY3IyhoinoTw9783ej3
r1bArwfNJ2DaS7IKl1mSUU2urfpOeokxYRQwtDwfSGQ7v+GCtxQ2G2JdRdC9uil1V97iSZ0VnAMf
ay7ibn1SVqpkxAj+BBgCKMXP0O5Uw4Y/qzoW3hIErifzat2OEjSRMJ/hNsk6bQn+0M33xZOzyfJY
USEiX8Mi+DRCtskUWp85hCQWQ3Me7OaZuXQJvEZWuY7dX1PTEX84NteGCQQpqkG7hYsR8NsuHLxi
6jsBi5uqm3SS/jq7m92qETQzxBOcOi/Jf8H3YjEBPxc458NWL1M7cLYMfdY9a9X305pyMMTp636v
hcQUp9vaPL4LzOUeXV30k0bCSBUD9pCNG7qvwrG0LLTyKK9ucSSQOqYw81c8mFT2FQ5qHmVZ8fgU
QwmVV0sZ0dsAPh4jbKNRGzW5zdVe5cCTRnVLgkGkz5GUYGXW9INAERTINXBxE9NqCVpzCsax03j7
1w/AHpwJ0wL9lNTxzUK1aBqZtp/VgJanYrBFGPIsk7ruqeKY+XOxDKQl1zJ9rFQ65t1bhkqP7bMn
L0aVX441jnWbYAu79MnQ+e0J3JcPyTFj7p8WUHkXRk6FRPx5PZ+bWQIhTZ0hQpWF1e3AYt50kG7P
kqsgz/Gh8Jk+vWAePB3v6b+NN+loyHuVFmyTmyVN5Vu9fS6UmpKgGXP801h/jgR1ZgYnxXdYx9Hg
TE/AkOGf8fA61mv/1AtwSUiOv/1FOqI3LWb2S0BPgDgzgH0kITUl0imGGrNyxunYa8kL90behK+e
RkK9jmS9Pn1J/6S9oRWcEfFQR86zD94FEokMC17X4Z9ez1g8hKPVCNzURutqa8Q4j7BoPY4giTWY
afQLfZbOAldX+4UG1He14z1NZns2svdsJQfQad0grLbl/cgLyxmAxCzUeJTEhXSa1rRJltAl/vNT
xkbNwa5SPw536uTJwMPx1Rf2vCdjIHAeFcObi4MWhVvHHVY+T6Uygg8R4C/2H23ABdi2anGQ6pP7
mRW9TjUoArrDRED2V7tdlJTzQNCSygkiOBYjBYfll1nJrU1FUbCoX3nVsr6i/2W5aGxiVsgAvKxN
0ypVxh6oJX6USOWkmodf4tEpCH0Ku8qbqUkgNV1ht85C1D3H1svoMg7TwR1qjgNm4kWJeqdZB+DI
j2t9zEmns7L19Siq8B3IY1XeLfb8a98xgOdXd4KMK0oHlMFRbloZ60y7Ct6u4t68jDLIh8dB64W9
i7a7icrrE/G3YIVIp4PWZqDhWLnum9L6VUKFtbNCH2gW8dElToMteGYtkLs2nX9CRZPU51fYWZfY
fZHlhtVRi8p4Uz4o+V4/SUCFOLW+zA1og5ZL1kruMpWfxBJ9dkGItiCr0kK6n+0gBDCa+izDEkt/
nc3G54ocNbT8aBcbhWz7Y++KzaKqcmAdrt07XnnLJGvA6pTdHp3Hj3Fm8q+L+QVm7ptlH7T3siDD
mNyIegx6fZ0P9WmUjus/TcuBTsndsqLUhLmxuJoteg/KCVyOhv7OfD39etUgUP1MbAMS0mKnfmC6
cbZhI22KFVikqNKoC+S9HcpWQZUwpzhaIowWNYNnJXZKpbkB92hI5IYzYVHGI8GaTnEbn/ZsmCtx
nHXgN/u4yPyLYDl/QiXBpaA4DNKhc8oZ2/BB2yDk2pBwQgSasQML0vEPryjcM/GLoh+8y7rKbk0Y
mE/uLx0+lT4jKRD4Hy+ju8Ix7+8KbYFCyX5h+ZZ6BHSp0LGGI0LNop8gxZjobYXOy8/8QWmS4XlG
xoM8MdlI/79THNeqRHYhuBS9KOBLTFzFIz6BmRKNnC0j6PLBLhjEy5jLvv6Iai2wLOCNXqLaqP2n
dqHAfdj6+FIDQ6vAFcl2jvVAqdFwAN0CDWewKDK7z6rg/F80FDc1XavwDLeQWMHsITdOtQqDoZ3D
M+wisRN0lMG1+3kGif6a37zAlhgixR45deutfOF3SpFN0OBNxoxltHf0OERmfmkU5Sv5mvFDHPJW
gAUnuNsOPPialC/dSslVgOLcODROTQW3xHnscmhA/BGizCr1E1+2aNRH+SXW9VhHVcqv1xFAV85H
XtMs7AAK95htfURTiVf2lFsgpHGg6j+Xi2e/aZjpLHnfdqew1LEMRDIY86BXTC6wxhrwtYFJEtGy
LGGy5DXJDNMiqVFubJ9kaeUnlo7AbYIxaeOZlo8V4pWMeyNeniP1Tb9hdBiREfFMC525SmJ9hcut
3cstsTpf+v+lZrhbBl+9OAezs5GI+n0W+Sp8jd1OIoN2ThMyAs+FRQPlVkgfX0eSIXbtbm9Bp0iy
3cScCEvGGkhjRYnU0zXBnRhiDRJo847f4gtBY2asJeK4uFubShWOv4TnsGsomhhxRG8hcbTFlC5c
+whDu3R833bGJDo7HsmILU3xYmzQ+v+1vgNhJaTQ7Eg+xQiPBCP2bPY39NNS2Jq57LSaH+Rn5/z/
LnIFEsAC6lJSopXCV0JQ0yy7OBuMCJ1cf7w8zBcQ9qYGRXpa8HscAFxyXfAOZkhrvLQnoY413SMB
OaGpjZ2DOTb2p2KCl3N7XKmtUpCgcJXbsBYN4PAwdRU7CAgjhyNxevSApn7dGAa6NaCJ6kF4YEPj
4SVV+rssT5JD9bmC5W94QZZmbCpDgdG0dQtlBFXp/QhHdYFcnP1JRouvu8ECkNYmC6wm1XvsZiTA
kHQAd+631CDxs+kizUtjdsThpDgIXoXDWMUnlT0BIoG1W5fmmdy7wfx4g88G3srxZsHiTMixhSCg
z6kEOzbC/DymslS6/ai3SYK76nFqB7p5wtTWSCA8lVeMwm3nXmdtRpRe/8OZ0NdDYQOXgFh4Jm3j
yafI6P7r8GSxfujsuhalVzzqLjqqqEmCY/V0WLPSY7Kb9vGR2wEo1+h3ZdIBPUycAOEsMj+i/XDa
tznEVqO4DTnoqs1wEca5b9ynnzoqJ6O0wnA2EFk56uMTocQQp4yd8Hl7AkRwYcTbmMwIr238ddnJ
d7rHdxBEE+7ix0M+/cQoI6Eg9muYPZSNXBzkLZpCvS6XuChxxXzt2itU+j8I0Xwu0kfMT5LuCVix
/qCZ0OnX4MwS2fISw0/R1poUiyogikgTL+0O74Csk0Q/teWICVPcFjK9Lm4dcCBcQecNP/eqgUfb
DuYM/zIiviLcGp0GFkXXlKSn72km0HYX36Nw6HeBsVm0yjlP244Yww6ccGvKT7Bu2dMzjBseaxfa
B0iZZBTenMLKBHx0edYsyGCwsM9X30bOzrQJm7CgL2m0mYId3cYVjA+iKEe9OKMh1eifEKkGonS9
boEI8m+j1KY6RasYZ2QAQw1cbWsCsGQdLUBMYLJppeTN4rg6lyaFx5zN5X5LiZ3eLko0B/9vaKz+
rmD2W+Ll4iSAOmGXBSuluHxhPLsdvLU5GNjBOw/MaJ8AFzPj9MyD1HwPQbtWEg0nhXxAq7hI7P3L
u7OucxFGjR2lQVfX8pGOESES5lWqBANhvkO4pnvlTdRV1ea4v94IWWIX6B7S06seha6WKxh3DgKC
AgoIrZF7BjOFOCKhtGQgVg2F+0wCB8iJgMLCmjqWQLBr38+I1vTnqhY9D3xnqfJNCS7oxmnadQHX
APKROQNN03QNb2bmZr0Gc42COEWegmz+4DGRCqPbT0FIC2K2NFncQv6Wzcwjhk2xEp1vs1yjkSq1
rEwNNmSWqg+DdOdE8kFWCE583NifiHGlr9CIMN1ef8zq5k/urb109VOt5vkaO5Ab62B/lb/k2beL
n2NFSkypApVY4eKgI5xU2rvHKmDCkCZ98fwqDgxo1CMDsXmeXZr+Gf24XrZsFfy3UBflkmh41fjK
t3m3TAxKmpKnYGcBbo2pwp4151FpR5zkM937v34piWd5tKaMhYMAfy3JFD427pQUWo5HSCBfuvhH
AkaPfwlAf45kohFcmQkHmDQbwr9WazqZXqgyJcF/1omu63L6g3gLp1YEC1N0qhM0jJFQLKb7VrUW
+MQKMBTD+xDq1EHTY42WZDmT/LxoJfAvbyfSPmxFx6qPZIZs/STFR8zMKwuMLFxSVc90SvHmsp36
jiuHBb0TknJbv30sNgztbx+lgE756nNiNCFWeTgmQU+A6IdGjToK3a26RfFfJtMDox5Oa+p/zdoU
7sGUWypjYyBHun2LhQntZkZWwxsuewEm3uIBlfMHFryig/73FNfzvMbUUVLvlO77AFOEfNJVcuWw
MNJQwHD9rYGS1nJsHcqa8DeeGF3BdEyey/8+OUOkhCubMDPql2rHyo2IL3LJYyFGe3uxWwF9zG/S
1LNiFrrFznHvlYMmpq5NGox/KKlDSi4lYzodFNJWIAxM29wXK6cmd1D5qRH8ADKIG15dn4LaDug/
9LNv+sK6c9xEVg57GvWxHf4VqUHd28tcw3iMmvJEhu5ywx7U1+wOL2UZ6aMd88yWgP2eL/jYwTxo
q2xmGhOg34zjUzx7sdknsyy98N1jprpSQuBvzJ7MmHTqZjfohE+rSDbxrdNv5eLpwugCq9NIH4b8
3peZkf/A2zdsU7q/DDmGONbsb5F3wxUV7YKuPcYbt5R6Pw4BPHHOnY7pAvSvDD23l5g2uB7h7UWQ
EyfquUuj24w9ZC6BUQmwcNNGf3iFo6wla8iez10o3Ab4sl0z7w5MQD0zw2peLN1bjIisxJk0ihkC
uTUJuJxsXCmrUkVanPVQb0FKeoAcfzmvs5F8Paywo7rkfdngi8Jw1rk15Nt3DxSfkpXd32Y82rrH
0lNTyszJK6RuCCATgxGavYLKGnf8azrFbL667INLijYD6ok2KNIHYhOEdv1uT0EbrDVvfUMmFX8x
pwb4LUgfag3uh7I2HdGMTF6GkGFzzShOIKAZFFl44vwPRvCczOnzyU1gtoIwsJ/ysLb89P+p5hVb
nVnYmo1637ATWU0+NhtzJACDvIA6v9ugEAV5MAAvIm2c0nW/Jn3+rnOqNbrsJbqpVJMD1s0srjI5
sZw7VsW56UME9isSLdX76vlXnjLMew6aSgNVrqgDxIUhhIKKTZ2bj++5lsVvkjzh95n9xUlpPutj
dsFlMvAYv9ecgRj2ihImtMQIqXNuxvE/gN1tn9iIgIba9RrHVYLW9ZHDRpxXRvEqDQ8I4oqTVN1+
96F7WV6lBRqdZlalLfoDFFR2RHNYxatHn0W5JMvjayY0dTsV2eqcEWuJ+bBvSfApLiLRw6fqpn6f
NgbqoGHyx+7pGd0+eSlegUbYPR5ppqdAiTl0kgguEyo7BLMyRu0fR7Xbh65qB4iOWJ/GrwnT4jUS
TPisab6AGiyAJr3nrRvohMeAfWLNydVAy+97+gjnzeuO1NekHDsOO8ymVbM+XqjfPNF5KxF9fyo4
bJPKyjJWsqpI+4hLWxI3pSG2Ca9s+qrkrO3KXuy2LvzkDUJoSGCDof/aNRJ3Cfmlmqvuj2oy5MIX
XVqpiiIpOG89TIHDrKsY6h0aKphQdAHWgzLMKSl70/Z4UcRzXEObIFmbsE4WK5JOllHcGhujrgZA
TmqMky+fCxImzXn0N9h+xoL6xc4m6FMl0ccLAX2tZA4WXTVky8sC6oZAUc+DEQQCn3wvitKMtLj5
eRINYdpT6zxxIvVDtNf1/ioHtIcCaC1+Zy2elQottXeLdvplDJ/V8InBFKA5OPVHvnWhibLNsatU
sdJT6ej4c7JOQx4VIsfJv4Ce+l35Ilp9Ze0vHpu/IzqKOEzs3eNc3veXoqjkdX+CIF1AfF3Ugsjx
RxWYeM0QWhfdWvBZ125jYCmKCYjXh2BNJUgS7HwfKE0gaQyL4Xvcmq4tLA+HvqIbI65iwp109yQT
6QBw5y38ReRSVm7BrQuPuDAHp0QYxIPpue6m9Pc7NnpfvKjhKidjz7MuULV9aZeOMmIobwg4eZGd
1lFUZ9V5kz68fuRddwdgQG1Hq/ctIdp2hARlnCax1oih0GH3LpjKh6XSvC280kjP5t+/LKX+wMVd
viTRqUijCl9e5Vr3C2uhd4gf0Psq0OB7qdXeKLl6PYt0wynuNMS4GquFPXouc8jc33Q4EzMNJy4a
K9ZFD+WQisSugqiHsLoSu3EHnj3JlVNARaBM8VSz6WyFs6W8RRQk0qQwTeouNrmEHmg7orMhjqDc
XPaNa/c5pDM5vQYhIBErIOlxBfxKu1sEI9ua0eaXv1gCWWmJYqqXWS5F76BIiyqQ/MbiCOOe1QPE
MLFvLfK2QJsKpZI3UdE268dmcXc5ESLq6RkINSzalSm6lhuT2jr1ckdK9E/kX6sSNBxC7TodPD74
UfRINFYDdup6eUOlitUMLXkKeuBgvemzEn0cFGbP7pLWJj1dcWBB1cXFVPYyY2vP3KBHmIYPmvnx
GkLk75PX8gfaSK8bfrq0D4DcFr1VKjxYSWD2zvTS1c3pW6ahVpkW9XFeta/Uy1JT+hmkuQggUpQZ
bybIbZAiyoi1IhsosHqSGDyeG9SmhqlLpyFekZTUyi/onUKOsSkJY83NnIpFOI8IVRORYSdeNhkI
iM9IN4rAJBZz+YDpVvOsIpBivBJd2UTCjG3+EEG9clj2Pgs+ge32YUWUS9INAckf/Rs7M1wskrki
wOd9EyCk/hdQ/snbTwzotHjX/j1KlxF3rg5NzmDcvNPCrH4U2iA3SJ3FvzD7AK9Rv0zTpuxP8oMF
1ZvR5LpaSTblcTu8fOuCd+mJNGk7c0vApQdhe3SOzxhxwrxy0XZ/J2Xr4V1tRxwzSQ0ND5Wj3qva
eWD9RdZbz2xHgkyuNGyFRX8/lJ6uTVgWx3Llfg+8ZALy2DT8FYv3T7tQLLaB+WB6IHhjOkDNaa5P
6eMfspOxxrXpgZjQH/x2BUmTP8Q9O1awik1n1ii6CX2z3/MkpP4TKpmgamWc4s0N/dWemECycHQv
GiY2b/tAdUt/tyg8VwzY+p3PaHLMNCUGcTxFmj7Pvyw5E6NV9Esic5/PxjtEu1rUIbVrqViE3eJR
1QsIhfLYv4ce0KQKeWqOoVnLno2SU6zf825BTFR5Fy3xJhU2Hv8moca8GDzaUxiqbaSVEsxLLovc
QLtt4Zk1d1t7biK4hf/m2Ifbw3IDyIfvlJcNzgtrvRidaq+5RWoh8m8sHWLNuEMyOMMJOWNC4O82
kJvCw78ULC/uNVzTJNT4TtfgVg03+fAUyXsbLcIZC53YNG4mjDcNtXEI1UC8IQssvxIsCt2TgE4P
vb0Wl/x/9hp3RUHM3+P7/bC4aeHySCMd4qkdxKOPQ9gmj0meCFxL8Zi+YmCVt7zV3Zy0QIMGcjlT
yd9mQdSkj+L+EgHB65peN5e+iFFQWDxNelDU0WZE6Y9mSaX/TuHFODdqC9ZvO5IEFLVknuOJyuWO
R7BuvKyCCl5XsDvr7URx2jK1jRLrvyvH9pLLZLL/BtFxi5H4htIxlA/lbLxClQQSzrgT4x4v1Ii4
pay9ifyIJiF/A+zXh8pKUpGXtRQ7w+PfCsqcBH06rwv77Gk3Oj0PH6Q2MmdaBvnp/zmlZlG2c8sl
jOWFURZRUGfdRdMhUXMttQvaMQyfqBucjUSRK2CkP0ramSV2dcoSC8/7iQCoxXL7HhXWE1oOrsJ8
pV6DS315L0F5cZtLa/UXDaaMZE4Y0Khj/tplKjTDlTQ/jWcnIBtuCG2yKPOaod9fMfAYfsYqU4vB
uFlAheXw0UqZkWuryV/WqQ8lZXDOamTsdpSQGaRvVvu4LsCeOxz/jCMHIsb74epFikjK8b/eRLbD
cF8lPFFZWjF0kC5sVhGFMzrqqw7PY7zwKgE2ejWhPonKhaTL1He6LalEPfhBDkzB+L0jlICboM+V
PNmBE6LAqSJfMH4hcglSdptkEWHvF2s2IdUW/FkCcubMbiQtkjrxyf+6g53SOpqatbSBza8g4dZP
Q/mIT3VbkQJczV6StlneEB5Mguve9UsHeGJghU8GQ8669KehI7N2aS5uYO89Qkt/Poj872u5/t5F
Cn4SwW2NWZJlv7V1/xNxCmjvhC5LBnqvD163GyzMnyYorKPf2jzJb58giVySco9P+xrfv0vLDrQ2
42R1BKG/RV7ftS3gGLR3IIZikRzTnSQ0giDmwYyUzcDBX7eGcZjvDYhz6AMP5r30Wv3p7EDXy5ro
S+d5yFr5dPXqcFzzLg1ZBInE0jNH3wtveAV5a1dyg/wTpcYUdfPplFJYF0DL7YhNw+K4HXWgyzHG
0RAmod1WS0OJRAgxrNef40MBsGU/U4qXtMZJNVhvhHmKTQfrqA86Cl8Kz50TNWGKwbjiOfh0FxVB
8Kca8i4bY7RYoztU546PpJMECkXHsnsowXdYQw/bJtnrpqfE8a+XpbXrjWoZdTBqhrZunFdZsSSR
UjEagoZSSatqurLpPdZSmpxsasIHvmWEt3NuOthBkBpEtHCFkqE4p5ZRHs3A3O4diWGbzQ7T519R
1Yj1LPLxJVrV6lzlLq7mPeHQhL/XHhmqgKhCK8nUkhoOT5qBV5iLFLWXBEXgYIKlGjDWsoS8X+Ew
CpOlQRjc3FyCWvdQCwKYncw9CWUfwpDGu7H1060BaGclZPL0xsXGl6P2vAOpHDLDW9RPMk7iXjCR
S2veH7x3+2S+uKCjsGblEdln1sUnisDRs8qYq4AXyWsbH4zlJwOdmCv7fDfeWOGL1Rqlcfz9EJMM
sl80uzutxWvg8FNge9fYRa3QEwP3XqOV7eyCInsLPsNUdZB9+V2j0Eg56tPpvrvtOsw+cHE+iE2Z
iV8XN5HWbuk5BhD6msUdMTWmiE2cRUWwLIZ/qejyVPOiigy4oMWs3nahPjnC4JpMBlbja5USSGZa
YQzN3ONwaLTNdlIpDK+MrbFF9pf2hzyBrhxtTxol3JHQfS91dOxHPotDgNo6DG30RvTvdilveFYh
/AGX5scR4bcAs1rX6+HHeZsYeyDDERuilHR9OgLk0Yfmzp+EQeu9W5Q0IaIugGfdkmpyFI+8VwoU
gNO46OzHEicnpTYpA3mxhK+7oAvlitfLM5z1Ppq/QJx4HvaAErabIofebK5SoNbBHF5ewkeEbGQL
wZO7O7RKIi/bTmA9bmaGu/52cRtm/ZRcGqWOQgYFNU7vMsko7hqV5DiMgALAy/JRxZSOGBlP6YC/
SEtjjoev0EAc6LPuCuQ7GtOoEGUHk4x6vEp3KRBb7pl89j0rgxPGRQeJSS6qg0Pd9DvwHbKkAxTD
ZOM5IdbKBIBe8KEbZ8D628MO1cqygymN65Zb2ss73zV+nKdaFxrwdWnBO8cNjaLa3fT9bPQ7s8Tk
awiOn9c39lkKURWaG4CSdeKMXSzW6PBTRR7TqP+n5aAUX0fgci/ZNRp6h/ETp4Nu2YAUk045H/8V
0Y/BxMRQTkBmmTkbtDb/9JeC0RWbrnlZK/Ki9byoKb0m7hnTq+i5u9zyNscM9s1OIJt7gOPUtyTd
oghy8XKTmt980PRlIVmcedi/8FgnlU90FRAVXia4gwE9kQfkRp9MHxqo1eSrhjYW7pZBsW7/f0DJ
p0j6EBrD2K5y51c8IB56QP59imShf/rqQPM5jP68c8Y08mkA2P5gdv4F+WNIoukopT7Na3Hb10bU
d68NnC1racdgdzkZ+j8/YJijNwHQcrlkV4G4CWqMxjudw1rnAcpJOX0n1Y716bRL/BeTuo6t10Rm
ySn82aWJP+Wu32d4qTl/Lzun2lDJCR9P7O0r0eaiZKaMYbZ0gfBqZkDb1OIaJjtYxoBKWugNKFPB
Do4GTvo+vvAoVnQfbtHfyxNLwQMAshvfMkR4IQQ7Fr4suS8u6GlCuuOL6oNk8J7TDjWXguzdCi5Y
TGT1CSPio9a8xOPGLV3kvOe8tO/eQg/eH02UgJ6jChMC7SoNUDJXJoRqja5DGb4eOd3l5IHm9Kyo
QJodSxOf5i5MEkD5nIaFu2iA37xnoE/jT7v1wo7K2nT6+m8wtGUYpb6IF+rLUMtK5SJGiWawGdbj
h6WgX2+r34b1GVnwhBN1HoFvEEc0Meo0Ycq2sO0+0QCEtT+joHgjzmjzDS5Vj27DXjAWoNPt77rt
jEJNYPB+bgF0hwOtdCZh9+xWSzjMjiAhq4JyZjG8BDjLRVrs7Ei10FsikdK80d3iesesTYgsSrb2
essBWuFwrgEFY75DbI+lfvzmyBkTXL6fpEu8ThhmWsI/NnOc92IHtNliHZaFGIjLRHcStdDyxP1a
oPL+7RRedwWgBokgQhlC40/WHxS34q4uBf9+xSEMfBQE0Nyf4LKZr42Nua5dUDKgKIEvA9KFxM48
B4qaDac7AlqNHsWK1tw79T1SsSNpa9Mr7TLZYPGQqAFWgyrTuHHunwtl3Cff0NJ1Iv1SzZ8oJ4MM
TXKE4+gsMR8ivpmVElEc3IC1hTwS8b1WlJjiqRFXdN33h8WcCrATekrV8buBBaJSPv7h0Fnk7SVa
lpNMVb9TZ3YgkfMxZo1M6GcMEQaxxQIY513prfM4pJiFgTRsAMMqIvha0l6gvfiWUFIy12l09uPs
zY+tZN7qzluqJYSQkQdsKMeeHaLXd3d6S7d5RVmeRYj0PivVaTn8dsJmUMQsQETD4A41ELRSTnkz
l2Wt+NaGqwVl3jjRCGOkkWj3F108ig/6laoZJP7i41AJ0uuFf8+31JY4fLBtUzVCJZNw44lreUp7
VNfOuVK8T5QteJ0l80F1h0WTFZB35mQ2khyLPnRX0/dNigo9stFFQPSPzDXTnoYg+cmz/SeoyTbx
j9nui6FAjvbZop/zJW6F0Ef4EWJdDRiy92+bVJuwwCPrhOKBTdnzXp5/q1VaWDOQZ5q+izgty3QG
ooiU8+SZO/60jxcfvAeFLL5XYq4oQWVqq9KQj1uNbdDaE1/iuuXr4XO7ljy3+EIdegZRVX7vFRsT
BEOqvwwwKwDII8kf1W5GtCqfBW/Cksv5JQM47ATOl001s7UNl1MdRSiylsQ7pDi/WSkleUTFwVEY
WUk6XH79SJlupcZ29i5BnLXQosZ12ymFQmOTgH0su0Xs9t/B8bPnWSKVYx50NbCLryUj4N6d9hrA
BNk4M6GVBoKql2mq+v3t6AuLtLH3CUYlb9cVSOo/A64sKkmd6BP7u2NFEsWDdyxx1Yhjru65Y++0
adlOjRlADqEQwX7B5zo4VWHwX2ZRWC+Fv8ZFZnZAkAurt48R/drT/BEU4j8iaS9i4M7H2RYvq5Ml
tNFGk004/JevYXI/8E5Ai3vXbndB+0VqkkQtxWV/IRiseSkNM2lZHIH7syUhMEu/SkGeHZ5pn2Wx
IUQyt31oWBaDYekponl37z4QrvbpW/PXYV6ggyn1nTL6I9QWJCOfzc7aiGpezevBsbU+ipBDB3O3
vI9A5Eo2BR2YDzTjv1QMxQTulULmTTGCAEQSuAc/I6T3B/+jGjpdpeOAmEl5Oj7XMDQu6hUEXNtB
Kiubvn//zLY+Bec9/U53ILzclrd3r6MUANBauFmSWH29nTK5t0wexq0yxROR7+8I/SNvNDiM8BWr
4mtnv0owV0iGA2N5cR6LkpUqHY6OhXNrJOwSiW9ddzfnTsQpOq0O7fuuIs9oKGYD0afW23rC7NO9
VpfWOjG0t45AwFSHxRBtnMzuApyfXe8HffUWXx7f+VJBTHKKWqQ3wrPW7/7yb+qewGXSVC6PXQr5
TilUg1YCfHirEU8rAnld52L/jCboKSUG5OGfQ6hkooN93s94WHn/yt03HHBASlOcLX8MiaWeWNxA
bTRKflUhlj3tuLZaUsJ2JIslj+Rv0Bh6VYKgQmsfzbjVqPUK0B290XhmZXjX+iZrp0TxiOUcgxqk
mix0FLXalHyvlLWVohQiCTNs5wR8cYMXjMiXchJ2zndcyygje9bJE+acog0T86EU/B2QfAbViRnN
eOn7naQYXz6OIsUNEHzUEfA/R2P1Ba+HY6oBJBpEH8WCQ1shhSGB5eioHCtqP28wQ4kWI8xpN+b6
8EBmB8ShzweqiMQ5GMrXau4DD6irLakrs99pTvyxKHS3P84soP+KoBE9O2GLrMxZQ9XlysQS1ZYK
lTwzQ4Fd93gXe6HKZ5oTJbooaGAkYIfOBwdEFvCttQ6jr2yAmDvnlPnCePbOG3txW3HcDesV3aKf
mmrBZvutseRHOzFPctRCA/Rp27UnVSmSCEorybHixHZjmxq/CJ5b/+9m/PsWtoUkUhxh9YiPZvwR
M/nmOLsgIr3+GGZd7qA6ZxNkNVQKLnP5XBNWtAnqVMQHR+DIkXGB288hhUIIkqKLlIE3HmzeNAtl
Q+JUvmGAIdXoPyEBDtcVIUDZjTXwC7HLgudLx6iQJaKWg7uMJkgMfym5oy1ERtxmPchR1CZGms0R
AIeqd39T9kXOUlWMKsYI878vuglMuGBGpikV0prStSp81qYdPePDHKMUtmlKPs78/LLgNxYoLFbg
a5kaD5niI7xKJEgGUht1pkwtYntbZ4YWSDKnTeZD3NdRx4FO5LvktGTuF19LXw1nG1Hbm4Cghekl
dU8p/Wp0KSZhq/E/SonKxDu59RBcRuMQTh0kIgemh9V6KrqdeJz96xEEMDfeSNeU4BC1GH+wxr23
WvEbBHIwJ57dqAuZvsHqCwNIq3WOTJKix3ms4wMzw/5DXfvTHX7fGZTMEyMEXgxGybsId6BZZvwz
G48Ete8IvrN2zFOX/TE2TWvFG0paOIaEmlVbgFBtXSfQr40q7cztA0uLdLe9w0HEV93SJfvzH/WW
Scne8SJExlx/8hQMvE5sjegez/4h1YNn4sSYuApBkPuCwm4qBmgE9W0HGRVA1x4D5bArG3b2rWTw
A5BgCNUla5f8IHCp3quCINGrZI9TozthUvdmTjnKtY8pK6MczGghtIpS+oLvLX2z/uHrusn4Y+pz
5UDetU4I7IoyjlscFMs0mZt3jepxZ6MznkyBFtXkFAKnm+gF/b8harK06bEV8nAnjYzHyc8w8DPI
09WW8RMIQmaljS5k/ZzsUKarmfFWnb63NRZFKdyo5Gcu6RoNwiNqQFUZ3CzSkEfTyGK3D4R1QGh8
2Bv8lXYScB37AM3G4jbOOqB9h56qYInuWeUjywuDYCmWGnLIgqhYLv5YUeYlZYWfTRRVv+TLJKJb
vNelMFtASyGaLWOYGjeN7XPpHNUW/DelNajN3Rn3BsfY2Y+6Rpxd2jihz7fWOo5KzJx4cbWJkE8O
iPaxlq9Fz4CCX5T0LsRKBwktqlnp1ToXMzpuoqrRJX97NnbmiYPAvWOmbrwYOx+r73kS4Op7CBNM
gSRF6N5zU7rgy8rGgO1xuJc2iMpi7t8pDQeX4qY7EMeKkWAretD7xgFgzvpKz2QW1qmJeYkN5WC2
AEjsrXQGl/8XaxKPOH/t2dqnHlsfIdedn/GtuLfHoh2qml8lMvkTlQxIp+tZeU/gx0MGBVP3kscS
SLgT2KMWHHcZrzMkbF0BTiV8G0tqhtSWfwFzTReM7vdEd6dEgWDRYBSJrmTCsvfWD3rzx37R/3Fp
G2TyX4peLRSN+i0PW/0+shC33yC+x5Jk5hY9HPicAkFUV8LJO7ePWW8Zntxbx4f5S8ERpnaiWMGV
LTd23zOaTyn9CjqsjAX4AZrdVof+ULOgiin/3F/PenxeoZycXNSnrUK9RtHhNXsfcDLABv9Ta1a6
9aDtGA7vocXq7XPuVVvSXfg9fvdWfEFUI/JFDE4QFcdX8oFOSQqLkLlzpdyUvquv3f/gibLUBn+S
30Rh7ixC8DE2CP6MGEGtQX/t7v5OEg9Snjajs98D+ky3ZEgDXBLJ+nDTicQXMPAXBtgYo1eAK7gV
63boldUFzcFisnkGhmXYAa0s+lCwk73aZqosDj6pe1GPgRQP3khAARX8j87T3atQ8MhvqQ3TfQTR
kFYfMYDJfgmPxM54bjKj/wPflkd8HmGUDzkW2L+jxwl+/GbXqbaL9crGXv0FPMxViQxjxPsp1L2m
ezLH2DjiaoC8qAo28MklS29nstxj5eZ8FJphDoGXCbffxpKbil/sfu8l+bZ6Dx9Oj4MdhMYAilXL
S2j+rmf5hmtE9ltsM10zPrh070jLtpY5yAwGqxzm/Pg3TeOYTMtbX+fWlcHk1ww84jKH8aRUL5cW
mwa1IOXU7MiySPF7MIe88GPzSy+2n815HtQiSIKhGEdIlI3XoCzGF82welpXG577/yif7i3zHgnk
w98ay2wMxREioqt5JWJ+LrHuzFGJ08Bh0sEOf8aJT4O+phvklguvGQIMFTrpSHeQs+O5BT0+P30s
QrMsjvGL5nvpPfDWwrrqqBRTIb+Us0FU25815cuVqCL1FLB+LBP9c/2+rqAnPjQQTyaUU3xMN9Mc
N6xvCZG9VE2dYfmKVwqqStlP/Ukmgamii9yQ5BRLdEHp/uxkoq7xZqtb34T4aKY12/2VXM1TPODs
I9/4sCbqWvCBIHGYphuqy8/TI+v+x/a6CIK6Xl0psiBmCIlcDHYyRPasZ3jFpbfPn97uTFRmcBnt
0b2EdFfONsz+9V/Wc83XG5qwCIHfkoPirB0urcQE2PS+dpsx5RYFS3H9wXrJtIH0ofQPPaYw+9tg
9yAW/6WDE2s+Faf87UBKVYSqao9O9y9i2CtRxUdDeT5ZuDDAiPHTr30pb80DpSaU33AmXlX9J80g
RXjBbvbNbIksCJ6NZQlAV/2jCI2W95gQb3m0l/YBZek8N2iPWTNEYLrAFu8lMRSKXBuvym2YYF4y
WRVmK2KUbhsoogTN38Zy6MR8TutkZ8hU/uQ3eaubFG2Ge+etA7a+2dfaYoT3DGQ7THRDI1LdzeB9
cPNqegmrcQehTaC+X+3/WhIlj3Ef2/CFH+Gni2OEye1yy7lv+iEsHZdbmTMkvzoKx+0zoLR3af1K
rB/99DybvTd2yvNgO/NaT3ZL6ryqIfe5wLWlOlUSn9plh6iFv5VOYQMqJu8R2dP0g+mHWYurbB2r
KsZVHZsMTbWqcaVKujDXfHvs0hACcqYdP/MZ9bPgVWxVDIREPM8t80TDS8kDtjbqMx+WYjiyDCye
Ua+SHMUzEcA8gmnFum3MJ5FadH68u3jcA4dXgnJDEcih6lgHko7u44AlDkxFkIQpeKSW5C5aO0Nj
bs1R4Fu0Elyacvmp5/81zJznAkYXMlp3/3d5aK9f3govNOIN8PZF0Ubf+3JOUZfZmxkBy4W3yx4w
taD9kSpXIwh5/ir67pOlOTpGe1PYWtC7qU2eYt8l1XF5t+USFnTzY0k/0Rau1a/BOjK0waQu3t92
KhD9fgL43Mi2BZd5TodHiR+NnQMkhN39S6LsVn0M0dfXBY9n/cEwbf2FHRixdkSzY62jvG/dqupe
/FB8p8vWds6xKXHUglqiiQfz05Hxv87E6FYby/hAPAjw72qsIucpCkdMVs3SHe8ULC14wd1fi8Kb
RjwzhfeamKol5k1KDHusyZxmwBSGRhin/Hslf08FMrFrpfdtSC+VSImrqbJP9fUuQWyu1ALr5DIx
EiZ/+wldNcv1VwBBD+Bf1aSy+/hG3souW8DtnL7j/p+1Mi7OyZwit2Dm9Fl4wGZsFKF1jn42WRvc
gM2oMgqiIoQbCLbzo2/BCyf6OSNS0k7okWPWp7ThZDfGBF8kg/INZb5E21f2xYzZ58axaNxKOHDr
YsqQUUv5weMtzkV5MXV3ioKknFKknJ2LImZZe3orHPQKVDnXW6fgQV9WPp42FZpdReXAcKZeIdxw
vKKQbyS9gHCg7TIGFHM1ArR6fKC+EmhILLLKrLu8W51WOrxOP7BXPJPNVMvG83doUOQcTG/oljdR
e0NWllUIVNbYqbbOOeJR3ARvZKtN41AqgDTWIisUIymmJEZheh2EGx++VgAtI5fgX9eRT+608POW
r9ttfd6oafnMsoBIz93wrY15IP/MBESYliwSzMVbl4HK3WWQKCo0nnq93xPFWyEXeC4K87jFOrZ5
QSstRzwuwllqezWJ6FxoEiWFi8bIjt8lAe/dZ2tEso2ChxC0yMMd6A+si2Hmh7sa/UJfG2q/lssa
ELa2//q9p7jQHir1kIT5OtZNiOiOoMbKi8CQo60ig8q3+FpmKL0QR2TiktwIETLlKDTN2BjTog0f
Opl2TrKP4YqW8fCplyD38rZwRw/+5lL+US2zOiiBZ83qJgv6BTFB8siJs/c7Hp9WXPn9d6xlwvh4
vesAhNHBYrjRC4xDlzFbzto2RPzWIyxZ1f1Ztfx76HpfpvOT5gexommyOC03z8J/+U40BuqOS+5/
T1YFkkfNlhhqqU3RLS5Dtk2vh8vNY47EWl8NVfLfmuOqs5/UUzCknIUErF7anCWivB1YFuR13jzO
qhIXz9IzM4GIxDBKG5ETJP5l1DxOqVPuCalB9v9ixjqNtBAvX06nSYTeFPcmVRCEtCzE+q8kCRu6
AnLDrqKnZVfAPIBOMKsN5K5jOr/GCR61WPy0uXsmgS32nzV5VQn65NX1GLaPWZMnUig6VO6KvSiX
kD61NrJcAGQZ37QbGn10NOyldHgDuWjSZxXkCBjrt8VE+EQXvGcWZyubu5e4GXouoVvFZiCE8FNg
uKuFNyFL1YtP6g+eOi+/lZ+jayHgWw6ixSllgJA5fE7oFzagLvBbPh19TOcxT4ndkn+69DEwSSGJ
/Vrp8AsaLTKt3c1m7AJUVDDZfvtrpgNFq118A4MEJLS57AoCVHUQQz5eLT7Khttj2R8PGwlHRNQ3
HDc3f9TbuXTK85ngL7VTppPZyEuZNW1XnNkxmsOTrvG6DO/DOkCN/g4w0uMLdU6IphL6yuhdIA/6
tV4oIn/KvUEWXnQMwQc4e4pGLaz8gCAFgOwgUmxrplyUmntRPbJ1loZw57pHMRBt2cGWuAzcXeCZ
6F4eUXyz83BbC/hF8Cc9AnBsEasjJTChpwjn+Sfq/v5keRXOLmvZkyRrAl+he7URVCvECBn5DPpX
Zu5Hgc0deMzpMMMmtyaZwSTi6PyNVIHqy25VX8KjjckS16Gp/b5Q0DWyBvFyK/H5FrKc9E1LugBQ
NLmZAS+oJL+RVS4ugs5nEK/iT9Ns2WqLhGt1qxIloJrmX9qywLn5qwCKzxd/UMzqM6V3C676A7uV
2Q84HPsxTD7qhamixZDuH3U8tonJ+3mw47Njzkn4F0A/wRLTeSZmubPRqLdudpODGhdTyTtAGCQ8
yJE9IpjJ2mDrJs1uW4s/jTDuaLBFgq6CWZau0h2BB8NJbkWKznQhHAUhmX/dzxrNQrN8JZi5Of43
nBhEJeHqBXTHMPT08CUjfHKCcUqyuZafZH5hQlIboqNbE5Ots73kKiLExphJ5czYNgokjwFunkD0
fx2OnI9pojFSHQQQ5KddcA23jH1qMCoQHMR28wUI+Nl+Hk0V6/mgZM2447XSOnTS9K90PjM0RrCE
aRdIL2mnEPj5dlQAa8P/q+QR0bI2jDwhC7pbgKgg9YK9V00bHlStASHBuKzeFkaejqNZhZNLcOnR
ogZBcYxOmxTbTPl8SkWo0e5cH3cApAeLLdjV8O2awZDFt9QTFsxwYbCh0oF+uNDBilBmmon+aVdE
eWbchr3tUjA6U5UKYtT1PI+OdCyU3G2rxO5n+acfBhbftnrfzFyELocxUxbTb3GVzRRa5eStFpJW
f7quEEqdNZ3UThzhsZl65GO1uvdGMXXM2zIkpn6TMFsLpd+QD+JdQVJM7I34WQWqHVgL7bOp3BR0
1FaKL2hibUOBFjk1KyKlYt7/Yc9pHyKpdMZ/LluHqG2zPBBLgPObWH/+jb1PTZ2yyb4SE4I9gSv8
sF3YdU4E30ZSdxEF8COgnHsXLlKJhI17VPFbGYmmXniHGFoY6hBjbjLMHsKzFNY+/ahJGcxhyBMm
8RRuEGfHVRd4G4khf6nJdzge3prsKUSutwqae3vbqmReZekwxcXOiaeabJNSlXsZsdsHJXCze3qB
kgnI7niN4I2izu8GwvH7zpppyolhEPnvgdjV9T1atIjNoSdqogn5tjtX4kh2odA4UFkg3T5ZCy2y
TZeK7HbNC747JOw8i1OFJTcZ/Z48DyStP82EmBydFcDm2OK28+ABh1xwiBbFjGUTcTxhtaPH97l8
ii+DXczAesS22AMPL6Eq9VTotbaXTIdlFq/eo2oiDO3boI39/u9xDfHG+jXRH8nRPp8E2n2kaa7I
17E9im5uo9S3P15DVaZqBV5vDAX08iqX1Q6xRqLEneK6pkAY+q720SGwDhNVDWwGUZ7T/nFzCQrP
xbagPeA2cGhhjLYqCnJHXc65LzFurxJnHeziHF9qtZvaWqX/yQRetgt1pctrsE8yymmubvPh0X7o
y7ixsjqTivKEeyu2wM0S94+8BGTiMNR2/eu7xEjpkrZqCguwnO8FxTbdnmlgVmrU++t9Ez5DNDA2
/UveCGuv0JX6BNlSqMVw9wa22DwTCqmtTlMid7JMJhxhM3tyr/LhH62xV9u4Pt9/kcT9G9LJGVUk
awhHs++d+PNwKtETv5Go5+ODJnRT+Qhr6cFAV3PKTiBN0KCFloTuHUWBGW5Txt2rX+odXf/KoSd9
0SHe2RRH6hIKvj6+q9XM/u9ESnn8LfI2hU/rhyjNE+2BXesgsLlZU8ucICyUTXi74kOvAZxZOfu1
qBYl7AzjVlWo4uvK1xH2ooNdLqLHBtNSoZduQpgXAQGCdyD09QQKDM94I4N42H/OCVJRVur+Xg82
6rMSjvjG1wVfzcBMk9RTbV1h2tAGJvZpNYn5PU6fPfXBu44hzcK71/Uh4aDQngV09zRdCt0AKqBr
9k+mCqBTmGiicVfI9j/jHBXtzI3Vnr/EIWKIeP38ANLMd5q/+RMHprditdOvlEpcBALD/hrBJ9DN
OinCCfEL504whqrkkYZitWUVVrYwnOC6u88dwQXnWk8QPE6+pckCwhQ4WXBL7N3lGhPc3NoYi07r
XDC86wIbzfqKZi9C8ZX16km9SdXYXJyF+2jrDY+4UrGTr4Dc8pNO9i6trUh8qb7l/RZNcH3N3E5o
5S/t3FvGXYiGFh4RUPt6lAoqEz8IuVsmDYIXNHXKKravnDfBklOfOD0yX6wOAv3NV8tlY9x4udCr
HVDRxtvbieR17MQd5c8L4tjSoKQaOCbUCx8+xXW1teWJz/os6EOQKzOCFMTdnkZOm+magx1Dox7n
Lwjy5UXsJhdDdt7mt1q9+sn3WvCc1SK/H9yHfmA79StTlDiITpEN4O0PE5/sdPvvWDZ2XvVBhWrm
vvsWUELIEDLP+b/sJ2vNwUudQKaInzKrLTuXkh7Rv+0wjpRG11LkVR5NPzVGMvZ7bzndSUURc5sj
PuZTbsbj7LENq7nB02WxWkDvMYiX5tKGTRNhgD/gulP1FPGwFJ61vo714Me8ipCQH8yNa1RWAjFK
Tii4r2LIMzWtmfAfm+49wwCxfaM6kFvkMAC32b6WzDGJuwwj31ylnowWLNId4guFQalzTZaBTLP6
oTXPXtUYbIbYQn1II32nPIpUYS/VSG07aRAqne5YDd9jMvbbgZprrLNjccqApeskPlVlGXNjIdh+
6onB9YWfUroCR1mWDUVdg3jPi12cu3D5vfCSsKpRcSbOUjF/UqsBS8AUUPrvaEgSw7TX570gaHjZ
tGAuv0GUitlGwjEn8T2gshWESbtp+C9x7D7lcnmprS7cWijsGVx2I/GqVE74bTYI3Q0leMYATePd
+CiEGZ+pe7bqfBW1BzkNdXv+4n8O92Y/C9XxSX1fPVCiUvpqZBoNLGQeP6akEFNtWxMJICJUSjqI
6/82+xsKoWELFIc+K8K7Zu+86P7Dfrw/lARrcuVbrSyExGRR3CbZicQEBTur3JgNtq/fFZnUDGn0
1BqGxcmNDZ67Gr/dhKUN3DFLTXcyrsHTxbYbzAr67oLT3dxeYK9VztVTdoLASl7xMKv4Tzgcu6Av
S/Dy4bJCDm0w6cZ64cs/cujIMsB7DQq6e2w3RG2KXTGKCQUdQEzAVidQAz8x+/AJJqwMfxKLj4fa
lemnSj991xi1jV3+aa/W8Uqs4PjK/HxEgdm1IbE0jxVB+u//z29h5Yi/wPZOdp/57LuQrji5tZ6s
5U5ZH/M12ueHSdu3rMnBp2JMgL7N01Nt8lJkvrjnFbpH5V/9DS7wtkZkonqxiCDGyAf/bKC3MfHg
GXwl79t2iPGnjyTxlTMRzf659sHxwkEK3ZZqdIffbRc1q/k9TExFUqt1Sj8DTunI+PorRbDzGCBQ
RPEExVdXBJoL8j7tontz14g9GNuDzlW5zebBkHq4KDzPjhv0tmK/e6K1Q1GxzjbTzByLa/7T+/P2
PHkXVQ1fMLBd6zLMjVNeDYWNAMHMKmi1oZw8BHQGpU6xHWP3At7U0X30DlPnZ1uNJhAom2RBWujm
9cgq+FNkreX479ywCeuO72mdqqQfy9I5HOPJHUPnqq6gIcfFqHylTkIVgF7oFt3zGF0NvaIg2nTR
ZsNmuxMt4pXjcIetiacQ1UsGruBMiCEfWY/3gCyoaKMdc0W7uG/L80EDM3Z5UGYhf7wKOgeVDQmA
op9uGZBAsKGX/LkrzjjPbc5FpiZDJeH0RXhvm1NmXNWsfOyV/KwoB1Z8tv4B4hJzZdLeEWCHiNkv
jQkbG61ZsnFwmK4tJEN4rNNd6bMqVqYmLq5rsbBUUjjW9i6N2UwnYB8sglvgYkR7/7SZTUA+vRak
nR+g3EHvDhlo57KYyY4N0N8VNsjWlJRoD6BAUH295xKMSWTKiGlBIc/Bi9BHR5a2IYm5rN18h34I
iIJNVIyHX1dj/AQfUGqTJwwQBLecDOuVbWnuF3UolbV+DiC8mkL+q0ePsWs7MoE25tzbTHEnfaY/
2tmyZjyvjjHrAFpt6dpaZg0IGfxzYBQDIfufu0g4xwBRhLAS3YVQ0ZCfRWYg63c6A9aHK2uU5UL2
u4brMWz++t9V5mo2uAO6jkKwgNygNSbDDCqR4bCmN/nemYoonj63iLyyt5SbcDDnUq4Hnm4/K5eW
Lz6eX7lYDJWEgIP7urmDuVsqkl7qHn+W36GPWq7nbz+451FJef8xTV8Y8eDvfbMTbZdbVGciI/0/
EjBswDTidq6vVnHHZ93qPctBl9KcPSIsjRM31tfIuj9mt8j+GwreC7ZxKt0HP4K/21ULJBrNuhvx
HNtwGLxIlydV+abTqcKDIytcDO0Lnl17nEHkMG/rKtNy+VlqiSSp5og4TzAOW4hN+2ffd39D1pgX
Y6iIA2AWIE/ZeAx0IukJt0AaLSYiBYGTHbPLHr7h7aZZ7ElWzHaRbhp/LwGAxOQN4d+iDaDdtM4A
k4FnltZOdWOemHakBJ5MxX0umHxWAozXuMXoBlxWOWB0rL4S/2ZYYdpqkF6gH8Ks1L4P0EmhvvlU
we1LFCtWyrGICJ3zVTJ+M7UbKRAxKQLV+wnD3Y1cBJGbbH2Spswug+fl3+kALfhD0AU2grQndirn
WUZQ22cbu3aVcPu6MPDCc2RWqLRSwTOhPqA8nIS18ZkcXZ0YQPooll3NItbFw/jdRWkd+1PqKr6Y
nDdqwqVSxqOargyFRuYIUg19ObpoTeQWB6GvbO23mVQSdYvwx9xrGa0eaNI3ANlMfjmOdExy2z1s
w6wT3zPP9TL6gwupaIJV25JcgDLNs3W7lbjE3Ho4QQpmOxOVSxy8sFAY/HW+UuLXzD9gx7DTEVyY
v/B61PALWOfB1O/aN6OU1uHvkbvPCr/JRVWQ9OhLVcvkwa8hcQWOT4HcRAnFM2ElEoVyXtar15XN
mNB3wfQw7tT3BJdqnFjf0ZpyD/yO+RXv+CbbLegmT+B7FSmy/j533rgfdJcYnyIUkxMvyeM5uyBw
Dx1Phrc4B+C52n6mv1LEU/rOEyQniR1f0ajrb5r9UpjtWMREF53lzZngBzkGkTkJ83UBkvBpxgv2
7DSGx1holg+lsW33Uqvr/kYXIEAco0Gyh4GWodGEdxYA23MMhIky3Yl0smnPgExNNKBmhkQkuF3h
tYIuBd0vxBb5vSJ/pJj/MQXWdoymI3xgLhQMfB8bJDKHa/EZPLa0TQaZj3wi5Xz3rfaXA9zQA3as
hE+gvP5Y1empT2D2CYocFJ2JvgAT9qZN5C+eeKHRIRkk1xVo8eskebOc+K/ktL8mrDYpZkX5mXIs
dDe09vudz8TOSQrHDaWwxyoat8ilQeEcBj/Bpv8YID4v6IjYF9gXW0vszjxvLa9p5M2jAecdNUKy
iOlQJKvIQhDpqOMC6QtMKtWcvU5QMkok0MqudFZf2Cnk8dV8h6UAH3M3L/4xTU21TUrW+FRQxZKG
k+Lk/s6Ec5MFlM52yN+1WcV+sDmroM5shMqIo9Xr1KzSAYUdNUQomcJJPUjsJbP+pgJsTep0zj9i
Gb32FqDE+6aquLNkwrwgbAB1hi8LeH3sfLEDcrT9SPBmCXrl4KlVUDBt2chassWDnqg+8X5rn/G6
J3dq0fWmb8yBEovltcFiiLd78qhyjxGaTT+dr+0XjKqEk7zd/5TyCcWrtW8A+E7IVLfwBseyCML0
eJUchBnCIzHHr4BmDKH7iZqrBf6dvIPmidVgWo1v5EJftAH8hyfENfUv9gmbBHTB+yMG2vb85ITM
fGtq4J3w3WUVAyHyrtovIDYN4w/SF8yQtfNh3nOk1OZ4bJAieegFgN5WztO5T7kr1cpRTtYk4FQ3
4475it8HUeDAlRGLRBq6+jgIJAwwxoX6FQvqo5g6NE91nixvqQzhNZJxHp+byj4Znx8xic/cwNdB
EsKlu1o6hbBHpLRkUHlsj1lFJ5f6v4q0SdXQMB9l2zfIIZlxLIGlfOJWxEgK39WV/Glm1IHU4Xe2
B6J8OxomXKBx1Z1W8VPqbkXrbmeGZWRD5Hffm8SURqk6yvKyFltJX+vl2YrjGvx/t+9yeg96p8U8
k++hJiDrb6wBGHVLd1+l5zFQLa5skrz5fzQlCZNg3vr074D76JnJxeWMkszvHmGtdwc0SP4/EYfU
9x3+S3V3oYGrhkgQLHgl+oPL4W6MKB0X4jjj2Y9P2R7xUYP0Lcu8Nk6EeKKkRopTi/K9CS/N6OEu
0ZwUJoJ8HptzXoFePW86pv36yD0L82GYjc64rcTWsb1k70yUWBpkVgS7AV6aLAXxIv6G6k+JGKIo
dpA33Wx4rCKBZpxYH8xM53l4NxzspQgxtUMMmUWP54ssfQdFQaOJCxwmZ/RAngXJaTrgJWXB1oxR
gGW0yiXsHb6jOLhw3/oVhRns2NT23AtpewiWDyFOU85KVywRYfW8KfL4Z/RfRzmI+s9YDh9hoEq4
hhYn3bw7nX+oe8DAzX+qTE/5acdzQzuy0rnCvW3ZAu69DC1XYzLTq+wzvYax7FOjmw+UWRUXZ9PS
L6vFOSaFEXoD1NEBDXzSTvufBboEkFxg48kgzqJOCw5GGG12vH7/TxZ/ir46FOsUlUXTnp2S7jQQ
NrrmSqL5PpzMJwNONvbayVgPITGRDV76OeZSwMP7dEp3qYXh0nkJlQhcuL7oZyZ24rbAqOOGAwXq
+SiHPzvtZY3X3j/yBNNT68J+g0z3EiFAekrIyEtWPolVF1ApJosOWBHbxEbae+H87X7Q6Uwt3KfB
SXN6339QamDAHdvBsPIZaDsZRvtQZ4URBd93GDvyY4812uCDBOEpBcx3Ly2oYLVMeFX/Vf/ynS2E
6Vsvg2X1mVywKMrXvrLlmrr9QrxTcu91K3Qjpz3pVT7Kn0dnharAMqbR3tWjqC9+hozOGsHC4z1+
KuPA00j+khC3uP+XvPMvII+enr9fzXA0Eh5SHpeDXHDdOqKQeG7PV++wm36hJBos2F7ORTGvlqyS
oAvFiUay2Zx4h+SvbAeUAKQZfuo31+dLltgkmeb8JSytC72z1Ioz4iZ8l9oEOBuFgeNEQ6H+teFu
1gKuOr3+YWV0lBXFOcOBzL+Vyuate+P29CupZ6+3rsTPWnc9GL4U/xeZ3VNA1GEE3LZHGCN0oipE
pDczykLr+ZZEPXEr53ibsgEOyfPSwaXnTOjjy8FKIafioMn0SivOnOaR+9BO0NG/hS/dDMcM7qG/
Z3lVQ2jLPHdsSNfBGKmKKmTAXq0Hta5885ulrkiGGe4T8ut3DqCdKzgs5xb4gmEqLvgml/dHC0SP
5ZF1kNB3rX4LYCXdQY+N18Eagc90OV7abtMF8c1kVizCG6V6W7IAaDLKqT7sI5IFaR+EeD/FGh46
HA0FWhvSx6paayP6dmazeuO0Fu4PN5vVA/L29JdJMif9iBA1Z0CYZJKiqkmBWpO6CslINDFhw363
a9+Sm/FZkMjPQj4zafT3T03r5WtMpdbuZMm0i8Q4ABVrIHlestzSU4TZeJ1QQIMXIx69BYVSbxFU
LN+SGy40Q0R6Pyqnwj9+gcU8N3JRS4BF+aJZbuTEmdrvDaq5N4EdrqITIXrO3TIBa5Zn1ymRgADy
wZKK/Z60viPqNsbg1lRfn5CNsLwGHlfdkQCRXIz1MPaXkP2llNS42Bqr5YA9PMWzmMfE/1D+T0yP
Jhs/7OKrCDL6bCM3qz5jqKCiWjDXZ7XgZPbGKYioiEukQ6nSkMd7QHlRwAVlYkw/0tsMGN0Uazh2
ZuM08ze1xMg1mtTBo3IFqeZNS5qYbUKwBY8p1mMhBv6/+oAZCI7hG6P2FCp5fFpxZj2jEQxjhMLQ
DQkFaG8I/7zP0BZtwOBWMCrGJ+yViBhF3A2UdBRt7ahJJSEhLfcyy72Dqy6JmyS/USH3iMKpPEpz
N6gVKM38iC8n1GPtJlAasiZF5klUKGVNu73Eu/CQkteOXDroATWpCRLfMbtNeXpHTIpvI62SugqP
ZxTpkyqK+3DnUbEL5SoQFtTfOSqMws4G8P63iesTHCBO/Y/Ett7rD5RxzYyavrBUvDJL6MmxxkGY
99KrmI6sgI/PMzrYU5s1MjpadOgL3dOPRY2vpzNGEug8f1rjenc1Jk9ziKIDLpR1ZnpKLcq2mwI3
AWHymw2QXeedBo/Hvdq2dg48vn5afgPhHw5Lct7/cRkx89R7Ou90EVPetBeZOiaiWbJ/M1P5nDVI
YoCEJdmLNKpS/2bdAgqTbKOt1Tri3mmOO1oXvljmnzOgbr56gnbmijc4D3QQSMiz795hxCt0k67o
e46goBA3ylLqCsapHm7ZPlDM2YBXSxWS2iFDN3yPsWYxGApoyitu0WXR0xu0UJSwEJxF5+P4fR6v
c0wdYltDu0/lSvPU++6OpBGoqih3ZgHhroxsMDW1fdeJHT4ldj/ITIkoDzbPI5+/Ay1lA3pMwhLN
OQ8EDFU81/tEyh15v84osCFrdE2cbbyyFwc8cjn9jyvjaDa4T97BMkdTPLL3qtW+FYLDu1qtQAqM
2KYgOKOy8T0yd+ysEa/MUSyuvrYTtO4rg2n1LkcpzJJS2AS+B8KgIJx7pMTxBcbiDHQgyxlRTLKK
KGUSZwBvdWM0VzZN5sVZX3qaS32qTrQSGA6Kv/fSnQ/WNINGVKIMpvBQOtuowKqEEOz42Dntyzc6
5OAtWJIEatHSBfHFuWMI3z9WacgdtaYsuFwzq9AYzC2g5o4RBCNVHCLM0XFHmCGxX+YcQhjUIP1L
FbvjuBp+mcdch8A9r9eKMJVLkZWdfKWxIHG8wVDGjGpk7jJuRDAUhgmllKzF+9Bdb03wR/ADkRHh
59D9zCFlePIhnBJNuZr1rBmMPm4sR3jdg8Tw3fkP3KTUrt4wCvYs4BPDoskaU6YOATBfILL86pb3
+to4rP7/5jHZJ0GWlZHv3TTZiz2WS2dI9dZW7xD+joIX4+TGtR4F3tN8Ik7/E2xRgnELaXQPgFer
0tiL9D/f5BRLORFdYgsgK38mJarokHHAvNc7SgF1Wxl92cmHbcMzFD73hKNPqJF/0bXb/IdNeJBd
n9d8kF33CfGnmGNhekd8kFf1xwqhIFymWjnnuZsfdLixYS7EC70IdPChlYmjGWpJj0VfRknvYpHX
W1PV8SnU0AXVZ7EyMfOfaLsqNy4FW61/17i3lV0E5sw9dNb3skNW7ZE7EXAVrdZl07HoJoi8QzDK
KiFnVc9j0eUdkwUHLQE2bz0njT2UChn21pioqoYa314xT+NyQc7E4qcImcc2C+nHlHf7ZpBxWXId
Y1WLeksfeU1WVpfX4GuZ6+uEgyFw7cyXn0BV/pON3J20mmX6tckxCvEM6pBtKrW9xeZw8RqLGPFK
nJV/1nDQLQ6g5499Oe8d3GnyPPV4b/FcM9syI/2v7TpoZAcvLWI4qPblP4uoGPirQv/aLXBUsrVG
yrQTh4Tr5QeGcEOl1KktPm+3myx8KtjF5KaxM9QZjAcAv/I+pawYpO9/2vPr2hLFQzEn/J/q6kpF
rxgjudFo3ISgmytuS4k05nOxLTPOYhOrDZyuDjifw5aQKXDweQqXhB5OH1LjmtfO4UZ0QmIED6Ls
KAyV86TmD+49pWwhy/emEUG27ZeLUo60jDHlem/J7PLkSSIST3bHfFr1OlbYUDy/VoQJMcdMa+YE
o1PYfhPFpKGSqjdU2JDR+IClgwpSsdvK4G717B8RM8PS6t8Ju1x9LES9YGL8x60vVBlBidclSGFx
kuZrjEmMVK9dqYinmKgVlbHJQVREcU14zbfosmd7ADVAnsXvka3USrqD7KPQHuFbL0ih81JpMelG
mn5o+ff1soZhw5GcIZMzP9UFjW7Kl+4ZW3rbFXYX3mY+udFP5Jo2li6UrQ97y/YEXXYLl/5du5Jc
FPYkHRwXqbiSoXTFy30BZUllOAU7txFWgBXIS6FvwPqqf8uCcKAj2EjC/aA2regYVOx4VBKDG+iN
iPe//krUekhmUKU+F189FwBtB/p7YAQPdG+4snRQBbZlqXvjrRGWnK4lvo00oxFZYmGPHgmYp4Kj
CL4gWa8KrnjDAlduUaCuDlAtcIT6tgApfQ77K3yVVduowNK5KpenJCmdN8I4luIEx0cqlbJ3ssf2
Bmz6eZHnwdvz5F1bDWrxj2OW3QFeE9h9OrpjDiUA2z+xDlyZ52q9zvbSXWJ51LnS8xMIUDALHN4e
/RDlP1soMpdR3T3oNEU5wQP4Boznmn+nBFSD6GLgJPk/AQk0MHkxL/UsG5lV1ItdphbAWKaxNqnt
aodiGyQMhb1v13h4d/XB/7ZkP40l+AY7SWmvHaATo0OQUo/gP2X4chyN3H1nVELDZFhsqf7Zer60
96nh5Arfw5PhmD8RBm97v9ZpkwzrKJIhk5bZrm1OEh/dz1bq0wRmzv5zyATjPF0L73tK40LV94Kz
385UGaxYt/oTaUQUYP8EuSO3JAFxtUytLYmRiuryI7QZ3tEa9zTZmry8WYPJbcQ3GBIeP3FzdPxJ
4WppojsIYTsay2dwAvBl8ip4LShZ+s57lu/pL2KYbjXhZoQiVggPkEnxHeG4xXWguk5qf1/opSig
bA9vaPUlWe6LQElZgTB1ts+7AKZ2CrBDz/awmPR1pzBhicZztkadwXKriA50nrNZgn/Fg+IQBJFD
s+KRWEx/heO8/H/YpnybfgZbRD08QszTFnr+KUO3dLUw9N3k8K2H0tRiTqot9qVdcH5xpTAXarju
D8OI/aYNk7qvHWK+UO5dr6E5VFlOxrWL32VtcICzoJFPffcr1QmsZypM8AKgdvbfoPcs7PIkbbux
GO6E6tFeEqHseqJKw4vXdGPmUZvzNXioTsWkyKkvXAbAwPlGoNpZeG19tQuwszrxWroUjThqfLjM
0lNbbd20YgHai1P54g7nDj1V9CjYDzMSwSGFpIWwL0rhCAIWB9K51N/Ucjh6pQYYPhlff2q98wdu
2ipU+NczgZCquFwIrFjL5P54LjmEyiXklebzmtwA87fHaa9dQ/ik19Jo9taT69UKMxpVaWx+lLkS
ADIu3vJJtYOVdJJCNlLls063mp8uzXJHYQSlrrI8boyxweq/v+dlfAMdf/juSfjQt+TXdF0bzJvP
i9pPEVFB1nGop3rLgyyDs1Z3OD1CC6l1co6vEwJHsMpbd8fsjlwSRP/wn7n0XALoxDsL84zwnJvm
7rFh99OQt335d9WBo/2LCIoDJVHKUSzYY21q7bDKzqulhiKn37taO0p2Jszqkk2sc2YfC3twi/8H
yn9k+GDyufaohb+uMW6p9bQ7byX+7O/7FjdYicW5SInoqnT7TMGBc1oOeVwbD98KddxnE1FZJJ8n
n6CQgeg5NgpGTD0B4WbgZ80AwzYQxz5qFT0amHyJ7dnLI2X6d0MSOze+FFd1K6wMqXSRPqQgxdc3
zeHACpHzrK4WGsyDdYNDd3dVb7RlXaJELdTC8YbJ6ok7KQjjKUr3CDAEFi5vzNjMfdTEXfQ1kbwl
s6RGjMzVlkuN1AJJJ5r1Ls9cur2ENb8faevvDIEY5Ovgt45rwAmUS8vlyBbhAGDIj7iqshg3VaAX
bolNlc7HtWxb07kpYwAeEKklvhosQwx5D20y6BznXjpt/MqdKI34KLq9eDIqLN4HgXU01Mm+/PwU
22AwsKSORnsYIPkPux2gaeAMno/FPOzYQcxtk/OldzBYLdS/tiWLdSo/jusXXwuVC81RxmtmvCbG
pwjv+g3cIhhp6eGMQjIdomsCxY9cTzCG/Nv2Yp4CfLPhUouUnrleTPVLMkAL0AVpg6vN7COqs7Qz
r9vU7skmkWgyw/tuRGC9O/CTRlqpcPPXGVn2pDQZaOnfgceBVG4ugfVuNuJWvDGx8s1x8m3wKFak
mXlWRa8L3GFSuHBHa6FQPVsI9k09OJicykPDtGLgOtBoBck9bNID1TECLsyuaL32SOBM5sxPVSiW
oD5CX7VEUJv5m5n6bGEu4arsexx/mOEhgGoaDCTYa45JVrnDgzm7GwsM8x9Y7443+e6vHmSym8lv
CRrFRtpIyeknAypPCO9teJCPK97Z3mltyQ+4ctIdZ7CGO8OHbDldp+93aCjsZukrXN66rYh1RcLf
Kb8ClXVN0yk+x3Y/VPBJoQR5zPFVmBXAzzwJZIKj3+bEJ8YusUDwnjhaRgAp+QYb27LxAPYRsIpP
Iz0i9JmDonSdh65bTiSomoVqPzOcOOKF3rdwQoMcGVbOqVSMYY6Y0ZRUbBJhBh72fZhOCwQ2ylF0
5Vfei8cTg+k5byr1INEx4pdVxCBaUplOZdQopDX+I6dYepadUgbEc0BjWT771cHYDWYJp5N4j6ed
zVTmfh2x0PS0BTMftcihsIcc0mV+dHYF12Td7nJIaTlxibyTzJ329Xg620SkVPnAN+OnShpo16BV
03PcngBhmPQgoNLcNuMAXVSZy8QI99OrEeJaAw+06R5pcni3DND3Utk8L4bO0N3eDaG/8R7hhejp
XRa8Cg5X+Il0wqZmFkhpohtGiMBhYRwb2uiU/Hj/G01SetuGNsvgbfP4VxN250NipNMc+wQ3mCgm
FGk1d+XoCLWaY5b1cgA7Mn4Mk48TMDmz/e6tB1t+gbnmD7ughtpCKLgCUm0T5fKdsQW395c3Z52+
Q77HLm0piQlfiXrx1yq1eSWQ7vk+9i/EIG0dXadwvveAmMMfExFhcEpdpIKS02Bj8RgXnXQlBzLc
YD/K7BL6QN1ZsuHzs/JO8VAGij0ZZ9lfTKYopoA73qh7Ws40Z7+7uNQ0FbjwvcdGHUGmuqTC8r0c
0+2NHZatj94TqiFTZUhxX4D6FAXoUWQNrLO9CROYPJV+64nJg8ik5AJn2LpnbFPhKfXNd5HQEtSF
xq4IilkC+6o/GeSR2bjHfl151aAKaWxptyFX14s6BkQPBQbx554IetAY/sgc19uSaJT8gacausAk
a+/6Z2PfNbfU2GWL+fJ3zZGwhe6e7rGigFJKOdPxkf11W2xEqgbx7CixgrCombof4M5AgXGJYPmR
TEm0ZdPFvHwiWn4Y4MRIEnaN/gTKrRuH7NW62TCw3UK3/mk/BHpugHtTXZRj27zGIbSA0OaUFq37
0kDV/xYQTD2Y/+CQUSKRt4/NV5udIjghZ8KRnDY48tjuKf5dI51UGBu7mYD6B8jL3I0eY34+KyXf
jtNUxszuPkCXEUC1IFq0rYTShS58/FP9HjXsTYkZ5inPaCe6g/YqzmXsGw42L+9pIqF2IuOe6GxH
aU72b92ItLZhdwjHxV2mHC9RGtKwS+wKaDT6ZWtG0Ch0ICLmvy4upBbvjh9zDHuJxojHpn1+PJZw
Zuad0zc73acsGYE6x0ygCB+yBQIUkfv6ef4H7Lfl/Au/caQhUfndc3yZnmOrWAMLh+CeYl6nNrGh
IrfC7EW5Tqy/Xe/EBdBcF/sQTrmHhQUw+753l4MfJAg7dJaMkB2245RMYV00jgQNuwypg9qBXBXC
44ZmIb4PvDpMrx9DRJsVm6uXFxP1rLoLa8QxC7C9BQL4N+Rj7IQTbJOoCAgaKEhLzYChtEaramdD
jWnVRq7QZfVHTxN2hnYZBSTKrzur4Uh62h3KPuAsJ/oijVRR2KKw+dkwimf+chOivdKkNN+jFiyV
SWRi26+EWF37dYF1LkFcrDFczln91g8V2au0hvxlcR02KWTA/LmpV1rJNFatjs+u2hpKDXsCN9T2
jCLifq9V87cudQTX/wHo1/ntIf2+MWQHDCJYkygKWbSpawI3T2Ke4XQ5UoYt6pnJ8vmovpHQbkur
8El0u2Hy0/rz5tjBhlj1ajH/zcYDmtoppydR9rUXAg1okSVvhGlyWKjfFbXtCC6Ma73dQjEGWWZc
iqDnagPKOa5MW0RG54VD8Tr5OjNWOx+pC0bAFUf2BG7w59gm2DnG9WlMqVmnebU91k2CIHDldNQF
DjnuKyPzqDU1pxLrMvZeM0YujaLLF75sXvClz/hvJLXHGQ+o2T3v6Q+qUysymQmzuj07vlKTQNjz
2Wb0mELXGY4urJCohBK5s1iHP3+vln1oydUsJj3rI7SMmcDkJNx3kX1SZ8+8qAl3FTKEF8q2SA/P
hLq1x13UcH6hVGyo8odIC/lC2lSPFb1EM98m/ZS8p3mLW2fMDDziDnjvLk6XDVI0MX9byJi2K2Xu
hnpZLXJc2Lh+2PRx3VzNx0at5Rxh5ibXfj6ek6AlGkGhzBKxoPqB8JMqpP1grHxQ4FQYIeIpswqS
/4t2ax9MDosDgvproyixBZhwCtG3UKp5AuTNhqsV7XLLX8zb0HuPML9gw39YzuWO9rE/c3wzBkwp
6gdhMPNvQAeSw7K/M2/6EkMJxgEU7ThpgRGlSjbqY2ybHRiMo2mH59c7rkqBZLSaSjwaL07G5Trr
20p8C3BDJKCt6P1bvKb2PGVflLBPaA7SNzou0mHNSIZOLHAry9Jgje50bO/VlQ/rrB9JnOMURQpK
8Am4idtCvoDumNKMFQRXfzjORzhhg0uDqPf9pBji/DNtaBNih+9IF9X1AkVh8dDfSPaMRpjgH2x2
h0FaR43ZLDgt21gccStfXIMUIRUm9hwxi6Xbt4uGGwal7gB5cjCs5uJ1+6cTw9ejU/RVpXcmFVjf
Gx+uS/yRLcDeTP3RDTQMTYe89eubExEGLkk+3mCW91GduERUVzy8CkgVeY3STASf3UQ2wnoefpnX
svkQezSPzKSf+p/RyVvJhVdjseFHhYu1U6eAZphjKx+THsbxhLnv2nmKMb+6AdiVVcYC+ttgQWWS
3jXRdQjxeJ+VswWC2qCyEamWQdl67OqJqsD17VW4i9gTG8YUHVRqs4Xa4ELsWsianxxaOHxJGDUO
3RGJH10A4Z1V0ILL/hQVFnSbMFYKHPug3b/gdrrar/HRBWXnaTbkb6cs5hpE1Efk/nOHqefbjWl5
AvRby9gPmKziFeq27lCsRDjkhW+En3qAOnEFtdJ9o/BOnEPkJVgLdxG5PRB7B+MO4HmJGyfb3Cvz
Aw+pFFu7O4CEgDgfLc2QIwSlB31LIEKauhrwVVdJXcwe38OLgqf6yiT/5wdHlqAUb0leoIFjWjDZ
FUTjVFQ9Ki0Jbs2Ss/tbitCli/Ha057My+rNnZiSoArz7NGLTgwnUQ3fRaZ6kvjyez6p7qNsvm98
/BRYe042svNlZm+12c69PjjmVyNaOblJsvfsLTS+IO2zc0p2CmBWNtIN1XD2CJXUhaPAQrT0IKiD
f042wHHCW75EQUoZA9MyKcDEebd/GMS4oGfm05qOQxWoKkFb7hiGnR8sdm+XZjdVIAqjMnASWb3n
qqERik3AAwfs8dT/aB/NR2+hiOu6lkYfQoNbMWbcYu3DIKArAFC/e8IDrGqeVXPRHa1f96mvJoTn
nKG5eiDSklzQuA9Fsl3netHuLEZQrdMB4y0KCSmTlkONhnrv8S6A1Mevl+7T0ntgmpOoSxukAn64
/PL/cqvnUFJ0WuMrLs/Hn3QIlIx1gDQ9mZM+c1wEAHdIyPpUQt5ncqlnjNBOb5ilmrCeNqAaPmre
pagmNIQJCxP6xkB0UU38eywrEQALgv+n3+WCKQLMj++g76St4HmV2Z2F58Lt0ehpQjuFIWHW0x7+
JyXcy+7fBZxSwjZDUUq9bumMMXTZ5RH1GMSyTZHXj/fMj+2k8mo/SfkZUuwag0PC5F89ki1FHbl2
j4sa2FtWPL1lCkM8BCgma9jfQ3YyEhlajz/TPkEg9RUlgZ5tqvfBRHnn6w34/1a6rfOptZzSTvlH
NTkAnkS3/t2RKJ50bCBeK2RfJaiQ28UaaZ2cR9as1CdUu/8HZ2MIO1gsxQDdEnxFe746WYQK/aCy
5wk2aoXpHAAsKz0Z4vOPlwCG931DdiiMiUwS02k68KdELfUY9EeYKVe7S+5zDU1j46wkh41uNKCE
5goekkwrp7m3pFAf2Rpb47p0MAOlnB0wYwOgMWCe+tuczQCxAo7pT47BLfe6teqGcYhA+XbKSx86
H3BIJ1zWxzIdfHGDJPypEX3Nj/hQgNd+mBvI2O3Vv6+Jmg9mvC9/Bxpo0YLT6GyrPqFMNrYB6+dL
8nRFXG8LToV8Wq+X2RTz3ujrKHciSBIN6xpzCxQ3hfuSjDwzqyF37I0E4Bk/Ju0YTT8RJpKj/M/w
T6SqcwFf1me2qmn7YfKKQUEmePb0JZ/D8csLtu9C1xEJL6bONoKjvTQzBRnrZ7iuGzVVdViFXYje
8KR6poXbjOIO5ipvwHUYSXxDPCrlv4O/kSPZ9CnfDEDMKlpssaK81CzWd+Q+0n6Ynx6u8mO0ontf
JZ+AeqBxi36P9qIzuZ+oiSIL1L8/aKOb705znNPzzvVWZNArpUfYiN9i8MA7zXa9aEYuo4vLG9NI
9ieK9e0uppkAEbSXSOKzBXRI2QzIAZshNk1bzClDHNzPw1eXSuHLw1LQ1Ykjbbjc9P+JEepmKw/Q
6d56GILCjmq8IpYtEJXC9mjBQQe5BMp9hAH1noprWgW1tjpXDru8gdzmwIHvyi1afzNMJ3K6NZUA
mJkVf0O8vlTzSb4sT7xYnqPuJta1D3nYobTUk80s3HqZXtZehe3H9A83VWDSSDWwOBl6hOUoF4tY
JmLGFzEb/8DdhecdRIrV0lgE0Qb8ZrGcabaziay2Cr/Huo/Mkm/YmESXLUY0EPXZRiuyAHDB9VQ3
rqf5Nhymkp/F88Hic0EfazTmqfB5iFD9mRsnEdjEhAvZBbKvEAYK5LhqoEJxr2pM+iduj1L6PMze
rURY1tJ2kU1yXH6bBtQOLNpv/BBV+7xr30OKgrj4jhU3NqkCbdbC5ngJDI7dpKgwXkMGn/idaXLb
6CtOaNxbLCzaZ98oBNQJaHqgQS8MwWzZv2qucuDzw9Vb7/wWSsCvvIJJijK5gzxTGV8yA8MGCpZY
hkuLI0dxpnfmuCbE7OSdSEUuN8C82uQ4VY8jEz+34mo/9tpReuFrx9QzgbgHg/V4BaL6UVVgMdUW
KdqA7nr4uzcy8QGU5J34SbP9Br2p4nAlGf+12nMA4KcQJd5/6rVNPtmQ1nOMIsm4Q8zkUxHMKda+
X6JLxHVzVgek/TBLvQwBuJzEPuFFEhqUesei31Ka43YEIRn/unNF8PhRQbhgHgimYafeZlsHx32E
rLmVgSoNqV1vHzAOm4zOSVyWdd8zwI+bL7KMc7OsYoTA62hRYn1o6uNhn2iqgK0QvjceEAJjPyS+
HtQETNX2bAM3jxYCISzz0tQHvqP5Y4AOIhHAX7VZ+GwOO1NWouxF1BI3ntFbgcHMCSYBnWjxPhWG
nN9el2MWy6fLd7Juv1BynYEhNR3fFvyqLKzJ12kURg2IbndDn68DKBLX7VlfPAwafpf4yxlbJEdE
yf+0qJvgMOgZKMn5fXvEL+XnyOt7Xl+VP3bT+1PAm9btla6Gc3UuQfCcBPucNgPtG5Y5ZvOHdi68
0um5VTvbpWqUetLLebe7e6egwOXIVU94a7Zgy+FaiGVVXp3bOc1vycWn4D3e5FlQetj2hilWtc9q
z1veUQfbcOzKU5DEyvyLzXyRCAeSlkPFeo4IAnOdlco0F23jdsIVTjSvcKGQm8MUyMIGaIT/Po73
3/99lHauCT1eJzd9LCS4VZuYZUgxvBCpMy9sUVDyZRgKgU9SQVE2wUmA65pR17QaBr1F6ZOoVmqD
wqfbe01/g1i+jIm5Ja4EPcoxEbx9/6ob8mwbp6GPdShWdl4mlBsGfTPcJI10u1bPKBSlsAtRHSMR
5JqxoxiWFR5v3X12UOU7a/Vz89i5G65DAUYs0DDBRb9nLgi3h1UP5al48pQPeYI3QOyw78MvBbIN
JWjCwP3+Ag6cxcZTvL395xuiPBoJQ7iDcb7BbOx1CBg0KAZfQaHuZWoZmB5oWLer0U8QdQJKtLRn
/u0fVTDKeM+PBN9rk+faljrsaSH5eherq8AH3TQYWfpSsrZYcWWlMOJxcU4k23x49S8MRP3liksk
1a5JL10clLEJwig9wxKG/QDYuAzH6FufgmjAzxdxBcuT06Zd0GzeLA1Y20Z2J7KTZVxtu2uErbyw
1V+j4yuYaF4MaX56nB4Z9hPSSWKRngzZ4vOChbJcQKtfLzc3Hf1YmiqIdvS4FXYBYrqXy0pn3deE
+ZHQTPcdI3ew5JCc7k70Jt1PHj4OPjNhR04DHfQA0W4x7NPp1+HXOqx5lumgyTs/71BvOG03MQRa
IB+ttbhbzgXy05KHGb5f5uPCZqCK4mZCEaTqEh6qUyHZr8bItGaJ9dKNG8m0kY+yVyhq1W/McA/A
g2nBWI78Rb6XVBtxvxjpoSmpWZDr9gJ2DACotz+1oQpOY+9+lWNTeSpxIrCJ+2zK6hy0v90bZwhB
M3mIbnUygfD2paWyXanBIP+UVx2muNoVbEB9e5ja++rGMlJ0XmbxWzTvp19ONOFwJFhqSCfU99CP
xFstMELQe7zMe+5EgYc85FB8wUOIX/L5vyhsOipK4Hd+62+q/SAit9DRIFFhTEZKbz1iWPUnz9FB
7YuzqJK22peMRPDH++dK8nUCq9tHLe3jYRodwTvwCVUJsZONN+ZieT/bqq0gHodtCh+1rF7stqRU
WooJfJZCn6X66C0bInJDQYVt/mVPKzITQJn26EIvXLIOLNim4ApDKMxkacnsYthau4nJ7DBjma85
ALXdDMw5X3fwFehlxXcnstqT51E3xKgUf0Nft0mgZro1Xo5CRSfOm8QPBYUDqMe1iaWtb6rZ5H7i
izuGbe0z+jQUUuBWOu1JBneuAXH0JGPFVrj9hfk4PbfPQK5wDewCr3dgloG38YrX14Q0d/PJbRqP
v/WsKO8aJe7sZqcrA5CA6duIyDUbYP2ErUxktNHd5TrWdkhizmX9mC9o46Mgrk4ncF+ORx1bJ7Y5
OzHFXnUv8Qa8OVuct4jGHfW+q3Ze91+k+jm6C+ts69sasz+btWB4t8pGtTc2RU5SKyGBTHrly/p/
lkX0DAV9pB/y/748SDgoY5Fdbz2pHpddi/dVgft5YMOtoCZESsV91lldThMwZ5acifh3Qaa/SmrA
DOfgPSZzHQyRsvVCgYPynDJAFKD/EEdJuyiGRumFsEnHTf7Y3xuAAMFaQ0Vt0LXJ7VIvJqpGkhcG
jeXYSrP2DQBBohwmRDh54ytyPoKhXimTvez0j1tRX+Wi5OxvyvFVtj8NWb7q9VoLhQgjjVjNBLpo
JbTWpIXyp2WRq/DH+kQeK6XedK8kS5Zb2p9oLr21Dap82TU+qH/oCZizyyGdpj73OGET3IvAuSBi
C6uwZZc2yzSpseXL9B+PSwfQZBjqkL7ecS11lTqFewV27JIOCNg1alOY6yiVcqRUQqwHnRTVQGuE
pbvpo3X+X8J1Apbcjk6s9ZcmOJ+536RLwrhlowp+5IUlKKAmLE3uNA5FA1JI46xjJUmiyq0j+kGE
dBFU1o0GOFOa47FJJzlqS5BtdMcXMiStLp3ub0zry3XizwemHd5h+UhucpLYQVJNMOarIQSUUWWZ
2PbWtX2sVsfu4CAn07JEAc/WsVY7OqmIppETxeGFyyPz1rhY0u6B9OARekgcpTGUlQH75BNkD5dW
FxovkFP+HDuNDwvc21e7bPmD+Cpow+3cYHIT55EBfuD2CCcSRPSU2R8iNncAf/4sdP7yMoS9ebxQ
NE8CnR2J5LE6qUcEsvvCpKkznvsoCcd4iEr17RM/S0Y/07NZt8WVvw5H746b8M2YVBcxL+tWze0E
dtStJ+yHYy1xB+Y9n2ZXBn+6Bvf+HtZr85Oe//DKg9fSmlvaxDivlP0ix9XWhGx3QszOYr+72EZj
eKJrBAMC7Nk86MQvIPB7LZyjxzkExCVGneXJFdVdW3nVXr82umxUxevDQgYotSdUX+ufP8fCnq9a
0iPhbuqwjG7cBE1M6C4R/gXVMww1rnaB0CN58ZFRjL8uF6U8lZaP47stBekXe2e8a1X0+YameMVz
KtoUCUnkfMMXYHeQVcNJs+2TtF3NOBBxeFEKld+fkTG6add889tvoFjDXu0BG8l9ciVjNq7HaK/x
G2v4cUqAq3gyOgw5TKgXV8UxG+cwTSilkI9ENI2SnqtNKJlgmLl1E1QZz9seDZYC1CNBVbf4q1D4
WEmVZNoBmbyZJ2ihwMb89o6C+k6VTrvQDxa4Sq+oHJ5HkwwXRP4gGjXJN6iGfKKPKAGbJb5v4zON
2c6hCEXPWpwi+ISkBdT0mbPy9VGckxM8T/CKkAdQMf9yamAvq0bNEieg8v2ZxSphBac+BHcSx+6z
YjXq0gMC52DSQNFVdryLNVEeiGg6SbMVwupjy7WHnlU/AzmZSb9phnQ03TMPTu/36d3oe+J8HuI6
Duyj4TRypz4RGW86l3D/T10Yfi8RtDdczxUbIOqZ+zPSwXLlry5wvVR3ouP8OoHuPwHeeWqA7G1K
t4MmBjXYiIW29C6VgmFVkzC68W/z3Dr2hv4C0dz/26ywoNQoVzYwz8gQde9X2QjQpX/jcq8zuDoN
TXzIrFxXefj1x8XMtAByRh1rfBdEsM4Z6ol0pDDELYRhMMydST0NxQ3xyEpSCFU571mWU4Yk3ECd
DFZ4rBMlm+qEl2kUsoZnIFGII/Js/td2g83aupTHyXC3JderADfL5sZOAx50xqvSAlOftBNUvEsc
5pLMnG3yuXipiaT2Gr6UBQUB3xCa6vn0xzJJsR/vIyeJDmx7p53O+cusLerLTaeCNdVchsLh/6Yj
x+SwWzBPuzJwYeLTZbzO4UpdpUmGghQs1IIUx3nqdeOX17QXLI7J77Q8EJKuLA/220J9NYjp58SM
5QEDJN2V81jN88JpUexNNnLWQ9gMRgSXsze5IvNq893LUpF9Kasd8mZvIz42GAepYmE4CV6mlEyM
xkuyNsL9jNz98Hr0Leqa9sKCsnoj1fFjZWCWEfwLfQLphECzR+S1p0177EZBEQKgUkrjPGO98y0P
Eg69rhgFy4iaAV0tHwpI0jLdggGXsAisoAXk/YhI0EPsMiI8mNybBTW5js7ndt7LAq994JYnXwut
OQntEfS/BMnlFaoAVD/xfFzQTzgtOOEAQ5EuzFCh0l2MVUjv2TTShrcpx1JUXqV3VRrf7XzIX/L2
SkN8tInDQ0osovlplP82k32jPPIjQkdZqdE7FhC35s9Pu3+FeaaeVaXU/P/6pq3tYalk1VBi4qdN
zvecwbOxQE1ka+DG36pCauwhukGjOAVbX36WTQt9nFkXeTsO4OG0cxTFm8gQlfTximxsX6NchfTw
GlT8MkVXajWt0UaaHdWvGB+catVGa8BWMLqweXoIS7PSwPSnWEaN9WxGvqOt/YiXuz4XJ1+m2oE2
unJXlhgiF0XKiS5CyUpKIXUdcXboyanaoke8Wxsl7TxLOcq9z0Q/hk2cAFOlWZq8W1a24IpxQ+vM
mrRkAdvZrcQRbJjxvAveXplShKcQPKpWLGthVt774g9kQdO6EQYQuL9e85qp371dmrh4U9N+Q8lq
0xMxYquS/OAPUfyOm6RHSAa389xD0xOvpCTQAgRvmSlyPBtmyM/pR1Ay4KQ97XHKyWTHcEER4ua4
0HmLkecRGnhspEEx9u8oRQgT0BAc4a4JaFBOhVnXLRQv40KA5mBoFMqAcashdudK9YSUq0hDI8Hp
jFOTrvgaF9XpX5EFIgWN1avpNz4jmg8lJoHm/e0Yte+ye1kzKt39Jp5r1tAaLxo7pK18tbvk3v33
91XRsjEv1RxZ/fMPnmeppd+5tWAbgblT7qJy38sz7DFkTp1K0MbzeZKcFX8tf/qg/wbT22V40QmK
7e7JGUAcEKG7UJ0ndaNWtZvX8EiuTqP4J6cPRvMppzARqigMX9m3/JAIGTHq38+jODG08XgqtBJs
b2fIg1OPb/ee8IJwWgJKZ1VQdtQI8MsgRJAqMOCCblVOYzk2m7ErA87QS75kgeXvpD+Mx8iePr+e
0vKaMmJk1EMg2UrekZNIrTwgtqt9IholL4dURglRq3CqBLgdJySGjXmhC0iV1zRmMnm/Vwxc3tBX
MYOqhkdqjWHzU+vyxzZ68bwI6ymBVJEMAj3YftMSSOZX8JB9sPk2Hbq0bUYj88f0kGDdEbOs0l0j
gshLJ7auw9b2sPm97RbdUgaoEQOnfkKXz5h4Rjt+Dh0yNTb2vc6fy/2OLwk8XMjMUsUOW5T2LbhL
phLoMHyzeblxCVkql76eiK1+qBSJZaaDEyA1/FlLI3cKYbs7/GLpear+wBjTBvWOpIGzNLC+p0IL
SRYSNFGcOK+4f/IsTV8IW8gPuEWp+4MR1CG4Yzey5SOMtZI8qpPrSeVwW98v9o85YRqr1Yme8AHk
mbSd7qlt8Fb0DzG7ycbJP2zctMJWaIjdVVjOTGeP+MY7Q+wjzWitWHDjaKVXYOtBneDr4A098NBs
Zg2OwFa+uQwwMYdVqjzN1ijb5UDlmtSngJggux/GVGLJl/Nnsml98hrQ9Vz3iwlanqwByBg8ghIS
UySeNQJMCJPu13OiZoNfz+Z4JPpN+kpeTFpivaLdcekYkfKi0mPr3q2NJJ/tY3yjfcwjIM/BAIZm
3ypo8a0c8Gmv8IyyLqWHbier29TLS/HSpMUSUHr+hIA+uwmFjqQsehD2WWz8W8aro8+xA88vHL6x
LsLiD93sEL3tO9EZrHOvg6AkzeLVSdGYLeoe6poHsMFlv0ZJojucxZhPfLnpc/po1W1+dZpWetxq
e80UWR22c78a5aXQ/uQzNVSdlYyEatXTr56jj+SGI7RUOZVjRbd8Wkwute0cOxEnTVQaSPZ4zXiW
72RAgr6/Jry5n1GaLlDNSk9iHukCernjbFHzWV+ORF1apXtQWNS/9JmYWB5JI2oSN2+2fkemq67X
K24JxiXnN7ociuNoRWitQe+R6JTX51h86H3+2bKpqZCMYoD0PywF7dSFtVXuxk1DoysIf20kpFpZ
r5wsPpo62rXHglY8LA3sSSlkYX6vfBu9GiNFIByH8qmahnsky9W4GfTmJE30wU0tqMER8dtoJ1jA
zb0GkCiKPhg6yTTMhMeXkE4d/m3Ihx/aQADDr2mvjqJpReZAjZCXytpEt9HAiNFTEt/ghpw6ZO+V
nWmO8GTlPxcoqdxaSEpXzzEDakhB4r9pRslAqZA97MNcq/zU108sDoBF4FoEQwWARHZta/vW3Nj2
mDC8RJOw4Y2LU3dwkYASDhkcQKj73V9QMO+TZEfcqm+pfWbDfksbdlKCJCP2i/llQWp4VGO12wAD
w4514wuKCNaE6qQPMedxOPdt3kAe8fdIifPdgP9bGwlZLMVe/E6Q2hNBsX6k0OVX1anVKRHzLktG
LjLPWyR1Smbdvo9H6zkauq+YIMtQYhNUGpcww9HqPET/1GqwhkAGpUVJpQl1aHk6jW6JrOa0GG98
Ozd8SUDGfYAKuoV3SKWuIsfjbrtL6Iaeg69SAfStKwahSevp9PSNdvaleEmBXZZ0E6C7U533xuvr
40rmzqvwJqEfKN1Mm4m/fFJSqKwnGz0SrRnMKVrhQ1TaNbiZwn/npaF205nuxOtg1tQ7GnJUrC7V
Sq25eMwZ9K+w0d3CAZtLn+sNrSCtDx+O8Rd72fYmZiHQsNy5tjfmqO7CNZ2LODlBdq1zARsalGaD
WGJvMLHynPaWJbl2VNyTU2/yZTikuiBME9D+JUkZvarN50/nVcMq4pVOZeG7/a0ZW4cI8dos+A7y
s3giVOTwukaAA7XrOI6fO8/aw1iGQLDZd4/6IROd7C6oP+UGOJu37AiMw9BzPXpre+lFv2vdSZZW
z9lOMl2AuAMJ585QvEbW8THB+vZ4foCPoyQgerKhpqYS3MhgoDVeTMBwxOVMuJVVTpDcHWeLlDiv
4KIViB5qDKgRrAnERK9WPZboVVcTT4Eymb4rGhPs4IKhYO1SEbpxf+PJ83GdZMtp30yBhqh8qSsf
xILZPXg5SsmHb7NRfO4nZm2suKn8laCtPiz9iZpu+/fpjOcqNxcVG4ffH+h9dRxSBmokvQG6yRmi
yJlXftxDT7rD/D93OmHIt1MIz3sqnVTM3egfsrBZdQFWvE9Qx68V2sKPfVpmXyC45lnGLw/JYwU7
BM1vFUKadJ8oME61yHOJyASq9zeqKv38LmQdaJLV1b4KmyWmzqKATrFscV3JFU9/dXq5nt7F/QEX
EezA/kPNqfTf5oYv7Ubarmvobg0hcvVN58Y4T8bwC15jqKqXry2IaWqcyJBhVZw9E86qtJJm/sk8
CKw7R+ql2HT66Xt1AV3ELuEQ9gZHPEEytm9DZrMCneq6Aed1sC84lJZYzNhHom1K4mQOEhVFE2bj
Aee7Zk8zCBJGTSE7l+XeX7OJ4XUmUkmt/hVsunywxap8IyIjrPhWThavaTStY9nWwE2/cpNSLTOH
aRuDBWwcNW3w20TlJmHnjzdMEHmv6J2Utx7XIT92SU855Rdf1BQixHenZbxVarl0gjMmqY6dqgpQ
V74ekZ4j713E59qY2P7mWxjFrvct3xy7vNbYyyZCo4dzRgM1QlFWPuCOv9o8Fs0ttBjH5Ku2Ep1X
Fwbby+2EdjwbnCit9EynEOHowCA3y/SqUaC5DuphML0gMuI472EeaMszJ7rGL9uHxEj5Aamab4P/
FgTQdjR8IA4ZiK1N9KpCC1rFlQFX/OJW/cCxo8Fgkyo8z297wH3iv/oez9F6HYDlysZWe6sAfEXa
YeZ45M6ZNmH0+nNyWJWFXbZpAwnT92xiMSZzN2Tn8wm4/PdWbeHhwYn257AvmaV75XE54aU4mxQF
mj/soV2VN817b9F4m/y8Ji6WEsofY58rmzKZ33MIZc8FfbFzW5st8R1PW9P1ge6VGCuAu3NULrs6
mIkzGRhiDrJNLV6CxtLrKPMPSid9BQxsNmvoJtxPoK9HpfneOk3ujPVMIsfBiYlKM75FyvjbJz3D
s+yC4ZH4hmxoUkggpvFreI9XIYpGqLedhqxdnuQRZkF3pyCcMOrVthBfJKuMJACfot3rNTR6ksXb
L5MHvdn7QvsdjuudMtPqIOSqzyegO++Zgmlqgm83wjJaPfJ6JcAGpo/p/Ly3lS6GLmNkAt0Ld8Cf
eSg4+b/Vd4sZ8mx+LOVNiUjN4eA1j1yRC8ZB6+DoalKyLAt4UCAEuzQRQACXETtsyMfOcgc+q1dC
VDyjowDglz3HWkfTxpB63L2Awq8wjgilB8jEpi9MNmNptQwiKr8XD92czn+it1MlMhd1c37e/mhZ
d8I5IoRS1E198TRla7COeC7MzkmJaEOgLrHKWKg7FVrQEKGgurInRZzI2ioVBVfLQeUN6kKxQ/RO
YBPzdLHCDFT/3kDnTMXyXMZ5sRSLMDAf8GwgKMAPQe2pppfoNv7y8vnM17a5atS8vuFQ3Et1piyZ
0bqM/2wtD0mzW0Y7CQ7byFYqFugscsFQqKeU21QwLduvvn8AsWWH96UEr3Dvdon7Z/hFO7dyH7cH
2IT6NbAjHC+JEQQKuaEStJUY+2QX+r4z9r/jYPXCDLDwbctVnx/hdTeMmK+bkDdzvmet2Vpgz4an
g+ggkrZKcbyO24vgXtAPONdjnRDSXTaEGksnjx+Kl/HzdaeDS0TBeak8P9WG3eTy+6xYyRQAZeia
n8Hbe0uT/DIylJHpkPcn6JWbtU82mEJfX43TuNXhHGDypYgYtf8VTXR6Tg2k1MylJVY/HAc1w7Hj
os3okLi0/WZamjlrMZ29vvsnuiqshBaG+c2zMSF/yU0EXj07s8RTvhv9rcnpogK9G9YBDNCDxnKh
+A3nUwvy78odFn+iG+07a5etW8leTB9xdmwESAld4zxPKpjxY/JOyvopZtgzBzLdyQgiHuB3mUqd
gD7B6RlUoh+DttANJJ1r3zAh+fmrlEUpLhgCLsJXgZgggm5x4uSY9g6OPG/q0fEUQiUaRnwrSzpQ
Qr4adoRDCILT+vw2rubY1FM7ADS8/gyfTiPiyU/p5SUaBK62/GmA1aYC1B+YpR3eVRBcNTIDrcCy
Z400vdmdwH3MiSPEVY6A1+Xw4CjpjowP4C5XmtQcOsEYCvfhBk4tEq5VuiGmZXIWnMkXTJR9wm/f
TKbnOwFRFXtZWD0MrAHhqiNH6q/qgQRFosZ5ocz/l+pOrMeWU7AOxae5s/X4KU6DQP0vcdd16sF1
ggSSrOBDIK7VG1/4PDvRXkH+uvEWjhRv+huUm1c318Zrk7MfNXQgVlIcTODU1jjOvHjBmxtKGehh
oODPVWvcDJ4DS9BypefFTJFUkjFjrFDc9bniP58LuKCiI7bqpeFcErTxvY7g17kBYwQUjnYAG2cO
/V2/dU0GcHlQG1ToF0lDBIRsmf4a13ypbXZlQfWx15Rr1K9mj3Ad5hQ1d8LawGYdubDcPANgFlK/
0ojgiFBghrt871QVhXwEJh22ZFIv4EUB6JrNKx66cp1mR5OBrLc2fW5EivhNYx1JyApjRIWbmXET
pw1G8cQpKfE1TPEPQ+uEVGsi+LUp7H/8SAqjtzdL1vR19fQ7eNrwxk4tWmNL32HNHGo6p1+3VEAr
yaXqEY7Kkwf48JPOrZDgKHwrv+MK4/9ntrEScC/T/w6e0KV3bcl9BV7M5jE62JVfpIUEkJeskBvd
Up+yLux0vexXXxZjmWKJ0ahsWXm/wFU2Lvdp42B1eWdAsb0mEwdqM3pA7reeA+aX1TwelBz8HQTd
BUaxp2duFyH+uFK3yKlPYXCIDBJjSznGaK/LuH09EAWKPZcRINag3E+R03DFOKRQrmSAHuSLxqDA
BIQihBsIogPpHnV/leiO6T4OVyg0XUpVHM4a7LfLZSwscTIfYDlXWqH2dgqKP/qwBcVcHp2ZbjJ7
KTaH42yhvqKAFRDtfxw/1F7qJGqChEGrHAozWwuE6nFhkTLCzcckW2MKyVT2kX77RkZb3b/vSWyo
AZPvdajMlhqhayyhbG8ZB5NJ97nPZlrgkNfQavnkfS9vT8lW73tZly+e2CO4Z6EQ0sm4yjyTx3rw
E6EI9upzYHBiGNlCDlszVWooR/FpFO5Zqr9KWVKhTQpsI674nNUdg0W2VwDP63uytoDQtTBS8pA7
KPQle1HVymQsOI25B70jQFhV7ayvPnItJwfXpnAa1VC7pR0QaTrKzWKM7yVCuQPoio4xrbsguzK3
S4dKhHJOhZoxMcsmst+mwaEYOcB/m6vV15H4CdVc5i6Ml8c3pvdGEbgSxGro368pVuvOf4RZhs+Y
6Gx3H62e662eN0xSFJO3bFIm4W970KGY/1JbzTI9X75sJVKpDePhGpGn4Sbiz85m7GG2fdL5C4Gt
UANXEtG8Ya8p40y2ZecLDDxvoD3e933JRtZ1DyQNEsAS3aZ7t/gC4RdPJXO+6qzw2J/qPghT+3zb
42xli1OaFOe+puJrmeTbYpDvbayTsc+yot2ZbCv8QnGBenKWt1fvK24dVQVK7a+WCFD+7TjnC6hb
P+biMSBaVbem8QXbS/ojnLUVgor8XNgtCR6+S7zxCh0J5ns23Z8hUgHmU0xEFwyIe+AoJ9+kTxwF
hLXw5F1YZAWJH3nH8wgeYd4Ft3wFIUrL43JpDU5vuft4X48RkdEPJoxK2fU94Zjy4LoLggtnQsIQ
CwPzJ76gBn5mO4DEBK9W+7PrpoalVvsAdsHJ5dZN6ffIvrV6JiDlMbxu5HhlC1twryTRVjBhHJ3Z
c/z7G61E/AS13HbtX+cP69iBgEnH2zX6QLO8XBSKSwmVSAT/2dolpJs1Wdv+6jB0ToQHz/yL5uwk
BSv28XhcMpjXbxT1PbCPM8XCIS+IpOMsBLoSm+CAyJv0yPGKx01tJyvZCWfvi954ZAWnMpigcUZN
D+Y6nyYa4jcQtP2530zcRXzodYX64yjiCr1B5d3BA485D1uvcjpcpNGKMtVJyJlwRGuE2OHOCf2j
T0hSHrci1U59G23QEh7HC8vtvlv/qTEwZ7yaexemPNqG0+xMAHNf+1qC9MSZKgD6+vwCRdUH87g/
D+YUZZjZnlbnyNlGhSPnozr4vZdraTyvaNH25ZlNNV3oUOKUf7BrzapiE5R7FuWSpZ6Vl6wcIndn
bQ79PFVy6at6Pklj35ZUx+GkCukk9vkzw76shsAn0rALuQJ9vwJEyZPe8B4I5WA5r56t995JDR3i
07JXfTntM8SVQ2IS5fFIFVFjmZPTZH8O8MMh6VZqidxyqptUKL+o8apQBzp5gUSLMpfkB7rV6mXm
Jiro/SB9AM+d9T6a9c8UKYQM1L+L6OUuyDlSo+QiNtVHYQZz5KCh9Rff9RcwOxpzi3rtc1jcYVTx
uYO0ctrSZdgShcvfxlDQgWwsjRrAQn46qFe76ka7RyM+imo3KNKSI4V5NdPCq1SFYfMRWFQid1Vv
vrRalc8vQrO2Gs/KktFJnZRe3Q5jGR+ReAVuSQR7t0MFBhhsJEaXYl1qOFfKBjlwtx1Nu5bolfYz
HW/v4N9Kc5h75lCxH+FWnSWPvWJrQU4mOmgktpxA70Y+FkAaCQcOgeXvM2Vv3TvaZIFuZXe80DEA
d6Y/kY4sPUjcxVsPRb0a2LdMdRQjxg92hOzF1Lu4UDvlNlkZcTbDGnRweVBKjymLmaL0PesdNQ1F
WiadvNI464tEEBPHaJRGn8AnroJrR0LSOFqXVrwdlEpsL4gKlMGCKQIYZehXUPgIBUJ3py6PxrhQ
aQmGw14j5NBb78MPYTyUQlcpai58/xdRvhTfFfZ54UpIhmlCKchcq/qbYurT7zP6HPYOwF3tJl0P
cZagMUIuxpj+XgmcdlF5Hf6yqeo/q18HRlUDXIXaYZ5XimqwjyGzOJIV1L0PedHFWCVaB0UZok5C
ZUvket5qdwkSR2dWIuNZMsC+vLRUaroHdSvYrq4lqpYauPZ/GpZEDdYySiftNDyu/lKkkEmxj2S4
L3rtiMMRcww7vCOOz5eVoG+8Y6rsyWR+A+ZQer7DvUl8voRiTadx9yBk82gjqo2U8ExHE7b5O4Vo
k7Bdr3JGzpLahz5ScBUee8T4H7tr7zIVPUtzgFVRqmko86p4MGhqgG9DYZ+mMGSyy4mKxjfiPe2a
RYssJzxbyFS+m+PWTjdimgZFOp78vgFTmrbbfuPMBiaepGAeu7TCygXlU3kMSLdRNCUnwyej1NxL
Ey9pkrSJw5YjAOZftmJFFdKu9MZTfbhizSyY/AMgZRAzK8y17J1h2KzN9TbMV1pzWzKdkpzR+9TL
hZRn7uDXM20Cp497Nzmn030DhLRVHn7zpmrMvueRlca/WFP8hju0fl0IX2VHFDK7QpGomxqM1Bcy
eBwxunf9855/NalvqXIS3b6rt3pxLCgKVT3j9kZTTIh7DuTQJZ9HPLe8spjTge+vQpawNW1RGJzT
5JQSrP4r5FT0x2QFgWYoXVdq8Z24UW58Opesl2l/Kp/TJgC+C+bQDJvL9nQ97Z+ZRw7QjaD1Ca2U
THz95Dem/gvNumWMFxZFCpMc6ywHVscDmlohRSsfz9YNpuQ+yEtdPHyPQ1qre3k3texk73v9YYRz
N8r7e2ZaJNOu2U4AeSp/uLKddCVGuuPz2VV5+1TET15PZy7VLboxjQMKpmm+/IIERdv8l6b9+nWp
3jtUTSwauIiGVA0czdaYpiinzCyD6+PsHLvGj5mvmYDxNoer4FMVOGhSY9DlpzsLEI32+eoozV18
jpd4zqGqrNtIJd+DKgLnwTa6QUe6en49iUIKy9nTj0SrWyCE71Fyv0IJ61oRCB1EVHWnwzbpRL9P
2y0zUVzRSjgArJvrAPYIOQYiAQSAX07g7uvPskdNNY3XiqOYNYCdJ+ODmnXF8MzOYglQ0QiOSibL
C/y+ogfjTx+8Q4Vq1TLgBhLnuy6k/qGXGyVP/xXRMhgg2FnT1w1pmjve2BXFhSMf4xB5mCEsVgv6
lEfUCldWSXZMUEACsdD4hO+iFp95ux6sMNCmS2NSYAzFk271L/MyF8bd4gLfjLLx1hQZYQwAW1of
5Jie5TEs9IBZFG6IalpyGg2vK/q6MvbckxmfmwdGXEJz5joaXUyeICs1uU4gmD7Yv2DZFs7LPYJ1
VYK0v1xTUMtH+OkTIGDiILOEr+TXE2L4nT75qtcfzYEVBuEhZodTBLFVJNCWVTXRPpvgMzrTe5HS
vI6s0lwhv1ppW01IuLzjU896SHgYv0w2W94NKvUbrf33noYTuwaTO2gVU5S9w0ARArvFgLYUz0Hn
ud4znhGxJkWS6QrdGp1cObrXiwq77VxzEL63mOrWmSAuoSOz1gS6IQ4SiYkGJVkNEuTcNWV5YDg/
P3OscB3MBgOkgYackyFovFzPWhplTG/DoNGUI118VqbHhiCaY49gHzNHC23Ij366q/6HMHkc0Dh/
Ou51H82ZREvmQxZathnH3kCc1Fm5rIn8UxiGHtmVgDqsvEF6aSf326gsVOSQvQM1QRcPXR4DA9Jg
FvbMIIRDGDSBJkBYC31De27ctEHspMLTWtaStuD19E2BkiuxnriXXQKbG5Yj/TIOQLft4UrqxkZW
ljCyLt91HMzX/kTX6Wu13xWJebXHXsEgvoaavkeLt33tVtU2/yK7Qg14xHTIIvJ3g5FoAYk4qsFG
bTcSqC9ykKQn2icuV81tCLIC7VdpKpufG0Psn8kM5dUSc1aTGM4TztN1GLWqI+RK0xniaSdBaf6J
RMFESsyzE5HVxEA1/Css3VKPPaZyIce1ZefpictqTqo6LizJDSI7n63SLrmJ2B+FSdC2gqbWipTF
zXE+pT3v18dRN1SM8bo0CTRZSbOQ4mRyxx9oEYA1Z49eRo4UBOFr6K5wpP9/HlgVj2WjsUz3ctWY
z/AbIWnf60/sq2/8zDZwM0pcxOoDDLLX36EWz2GG1MDs8Z0Mh+4hWX/JEd5phkx+VEhzDq513xiQ
YR1LhDnGhhWnca3pxa/SlFx2MQft/jWCXWaDxT8EqO1GcruxdcMXDs+1UnLXejfi4OtTGiyrb6EC
ke/bbbLncQlrmWLHAauiQj3/orsXgHNuhJU9nY3HB3+rnGyP3G7r34llVNt5rv4khZXl6DjBf3db
ZPwRZKZnwb9pPDVMnlbwnJe9B6fzQsmfvGOYYD8+7ziFUHRDsvJVLhSlThQ7pX4dh6Z9TGSzgHQR
FdKzHxYUtZlRpE3BqrPP6zI4uUjsZUTM8ynLtICVTUgNTZTLT6Anvk6tbZa9Mpy3JtVfmHYgL2oJ
ld/oF70RO7wmw2hsS2Me3i4do0upCuFYVh+4Y6EwDUjs4CNCA57NqDVbtUrCri7t8IauI9RZk0V2
qXXRr1aD7pOTfM0G2ECSFRUrUqqm25OA3xLpaBbUXPMyBhzqp8F1b1IbylFP4SXwyaAQNBrxhK5J
96FbCyrAdOnqb8hAIOBXQg7RB3d3rzqasj+iUG0jHJ50a0VxdRzY3jV9jwxyOa4ig2stGoJITRoD
eBZmKSYQeIr5krPXC/cV9EoCMKp/9bHXT5Wm8KmdDW3w0nsN+f5vZjLJI6FYtXRhHEKJbTYd2reX
dPkDzl9wK7nWt0aaZHSk0andOwFVa8GsRAOZYcj2+duHzYNjcXdT1U9QNYb1+DiM8efT4ci2T/QJ
E+sILER74XUGjTQ2OebVy+3xRPJi0eNraEj9K2TbSwa5RY05XNuEST4Ep7SRurZK60Rfvv0oc6Ib
LQvqmnWU86cC6RuuXnzR5iPf9vYB6s97LoZRmFfIyEwf4DbnDknzUjnzNBo+rD34Hwhx3/wGcAWI
EoAOX1AyO5yOQyKOIQjVpYtFkgnv52l9i5KeyKudqkxFINBaBbrV/ajEDIDDRpm32CSpBbk+4j2D
/vleD63qo3gWAWeWR1RGo+Tt5WcVbZaDGpq402eHARL2jk1lNuP8BeqE1e0OwKTTb29MG/xsu711
dNbZOmwZZlxNIVixIet8PT6xuTDNcIAYaP+RJfUtDEoQ9PQUHWY+7sipX3/oLC0mD1Y+b3GA6WFr
kDSZkVEVY5KnmipM7ZFqilUoSgOQojOf+g58eJQdf6SP0aCVCC2PyZUC6TC+Dw/yWeACSaUAzmTq
o8ykqytNZyzJHQAMV4G+mBKCSirv21Cwpi8xK9hMtFYDjN43kMMzg7tv3fI3Em7GbQBo/IHh4igY
SwBIiOMNHabJ3g2rXlgi8SIsmZcsar+HRC2Gy8vl+Wf8W+ONWbWtzUUQUuOKR9oduyhC4e38XvAn
8Mxx+Sb/gj+Q4CIpJqWgmOJd6TBKULm366cHd5E7MqNgOcTSfYyfHRqG7PFxqaHli8adfB81PAC6
GuRZYiE+mI8qj8zBgF3TmWZAscOXbXr+LGugR7H/apYK40/gEqQc7P57g9e3Beb5Fl1lfr8ZTtP5
Pd7ifqIClfTksqXvuuczsd+ByK70vjEO4F6vmmaWeJiZ4YH+KAoBJjrxkm0IP9fCFciHTK7TEtXz
RulQAHg/tR0dGUkEPyaC+vmF8Fm5E5Z5uGHj66i/0oldkWkRifiIP3LZdPSDq9EOwBVD/we2Ubdb
OPqqW6Tk09ZEMoL9RzwAkE3wkgVPHH04YiJhZWamnt4cYXZT9YRSOIQx8VNlZolCYB1COvttzUQP
Ujj2EN9AVAdCpN2OGcj4uutMKuJQ7bSK/NIE81lQU+85veMaQLAIJw6mF8zswZtioQ767jhOWAvW
LJb0lxQgZ9c9NztjdACnsUIJoH2ybY8dEvK+5HQtpflQrGkjNVFW2ktfWcKCyDPwlFXOSnRfWwRi
8rIve1/OeEEo4nUPuk6dstjkEJ90uJKG2sFx4xjKmQFqf7I62U9HDHNO7529kSjm5pIJzoLoGvOw
rHEXTcoeCfo30T4lBXzNNOILHA00JZvOWRYKwFWBWK9Lbt+1eXyTRBrb0BHHvCAx7e5XJKA2zIPJ
Ov4oulf/af47t4tfViiTWTG2zzIgVn8/KZ8K1R0u9p14NbgXpt9E53KbQXGPfhSAeXFI4EzhuZ1C
0N30U2wkO3AMQShLWk3+cS+lyx/+dfWYhCUTzKZRUCPHzmVmWkGREA19Pyxy3S8xTmktKM/gmIh1
ZjN5/GHmEM6UOzRwVWFTfC5pFcB/BefcbSOseDv6eCJ6EBHewLjbQlcc9Q3Vb31vYNyBTSPhtPM3
HJOBgRaFCRv3cFMY/qzfj++fmTE9uPu9cOHFMYDlwCwa3TIsnxUAD+6se7+XaDmEpqORs4shLkV6
vNm9LYoprdT0AJBG+LY8JsOmsvQDWvGfWZETSdqg1tUOJnlpbGBlULW52KdwyxPGQev0//B1dW5X
g0EL5rEpxFeTWm7kq928YBzjU9RQoRrHbIue5teh6sSi/3C+2em3PoIMkdAjoFgbj5zH8euVln/I
GVt8afA9djA8W4xFrcU+oSWBOae6sq+1fZKeNFfN9XTOVsRrCKj8nNFGtmRhpT5AkKc9EYusyiTW
BKHkSALtyPr9JTHMRiOpPc/tq9YfxxmtEmxUzONhPBqTGEuAMC9dzgkopGawN23nCc42p5se3HKA
ph7wDu11qBOe6urJEvXk3Hg2Pn6xz/qk5IA9eFpHg1qOO/3kn/3+G3oROAeMMCSfWQzLuQLOnHHo
Fmm0HJMjFqTU06E3nQCUpGlFuOh+LhxLFk7V2v64RbQ76PFfSxdRDzeoYM7XhW6fgLWnjIybACvi
PQHhhpC5AOlhfgtc3FjdcBCooAWouO4FlutKaGjDjNiQ/jj1UfQyoZQElkKhUsxIdTo9vObtYrsJ
mDzY+z3XNEyyvfXqCEOD1H/vwMozA42bAiiT1jlqEhhlLHB3p3TCPf3sx4R9hT2qhnD1rbsjVvBL
yiTj1c/0qDUSM8vCBRKdIgBmixm4tbdKcoYADdnqXRoAVd9/5LoGtEnspq7SebkwlkeMHrZYwH+a
3VmVYtZIrh0oIUIdNE0xqoXvhOhA8JAL8/l3zq9kFZpOt4Zbqys+pfbycud3waIiW6Gi1WgsRlSC
Nl0Bpl61op2QiAeV5n0llw7/02L49ydVh/iZUtgrQda7o/bGdmlIhl9h6Y8ZrhqOvUMsigY+9Lth
fzj5zvJj6YVzWYqEHvEEYdB1QHk1wwtYDTmz/UiTnZ4719uSvD57EpyLte6oTRueq7TxtjhWh52q
l+n7c1n+FX5xPYn/k1YPeHi/5UPhiTEPalLptcezSOpYP24NGrzvWJ4XiB3z6tZwEcrZKf1tDE3i
uZ70P2PusWyLFjdPJ5wYCOk7JTtyDo0F11S9hqweh7F7D4mDIm90tN5vjAMCGUDS5E93k5Sbqdvl
KQWLDIAj5i+vcEjosKnEDmaVDXRNRfnUqeltkzldgmEU+koeHigrO0awKY9y6CeYezzVd+RXUJzp
MY/JVwt1CYyN1lZLwzKMWFV8qP+VFJD9eoSpPOT4PCbHawsKLW4q24R2foZhDj4BF47POvJUAqp1
HISxt1OIANxMuNZI98+aPPBd5dGfFoItw2B4HljR/GxFkM0u4HNk7BSFGOlnHbX7f/sEdSFDcU+i
IBnYruLKSKjsPTr0H58zt0cMP045SNbt8E0XqYnAdkkrsPyDwfWt2sL6zDHXoTL8rg8TGiJ9Rn4/
nzqz3pEtIK6VB0D8xlT626o6lvFZgLetqmpbDCM2xKlWCQk/j9zANe5zxbelaU5+Sbj9TJ32qwl5
zFyceYJZiFPm0mxRXrECK+Wn683lpzqA/j4LPidS0pFkv4/aUlpUOr4/0VK2nEpqr5hDTyOvMq2T
YjRGNKB9NWd/s9r8hlBptLSQBCkpbTUVbcmZdYMp9zvbln7u+cin2WBGZl05mc50At5JRTDinB4O
aTyq2WPFxexR5d+sOS1sTun5o7KJF04KfDIV2IK+ohCahFkq+q+OVKAOzS0zBgQ2tMjEf+sGiHSd
LYmdiM2HsltaLzI4mN7uDJcDxbiGqH55fRcsxzUxjUmCwwm41ETW+Sg+PSu/pG2ftktAqhZQSC3I
D3YXHrqXCoOCbXPTzmZGzgRQsvtfyx+F1p2XqScS4C+wuPfhBkk5kJFxp67E6URLwEZUN9cFUwZ8
Ugo7YkTQ6Y9ijjyKXEIB8MNQKas85DGkfjIuL+9NIekKBoLZ9/XC9JIq55p7FXmhBhHMHAXPuCjC
2J3aPoWpD3wOthuB3h8iYs2zL1TyWlwM9YfGbV++9v/0hnepyGqqMz8NMmdxBsDSM9sopgzUqjkm
h3gaKrSE//koLPDC0mGmP0tKZbmH5s0nxn8tNABzWbNezAq2yzZg8cpK1yy333Vr6s8MIhwUXBw6
0/rPpUFOfRKo5uYqME8B5torbX/AEesEFa72Uh603tGV36xVrjT7TIxXUmAtZi/ZkSYW4LFLjaJn
qbHX2BTunqtAYCSsjIbqD0BfDrkEaW7zNGUXcbL70l3CJptE0I5nDdfOrG12RVChVsxSsdtTQiCB
Axq6jF8U832MdBmJZK+2TJYyhHcYkhUK0vyU1vqxVugaEub7TbqkFT33cPkpi2HZCSlsNtFvHu0j
pZ5+LnPz6brsE6cvzIJgEO9MO8HXD7OGKyoFZgr/HsVK/j+2f+NKBuNOOmvNqqmHs3tFOt0Qis8U
MuDg3zuBnBCWLkxpb4YoC3wlHYJrtw7ycGr+uet7tOBrnXGFzak152AfdI5h/bT8mpsftiEfBTiy
/XGRxXcH5s/g2f6hrNgEzJffSjAR0k2NcB+MbgfUV4pzpLA1hR6f+rL+blOg8kRzgaCB/+Z380B1
lbMpbbBeSZBZbjRLrTVCDOq7A/OQms1wRcN+p8cm5qw89xn/oqR4fEIuHnhrRE69mWlJSBOKwkeu
igAAGFZ8LntXw4eYBZcJWeD0i8QDeQf1Z9bj6CLuZv64/aOsOGcewa60fuWiUZdlq1bDkAFnsvz8
KnUFKmxH2b91ULVjIl/yDewgIMAy6IjYp6y5j//XpJwkBPd2t7vypDnrr2YTLZAJewzPAfjDbGEv
cvtE+bZ+apaw/FZIuix4G4Dgs6AIaw/fuh4kB/bmcAG6YwMo/VzFHNZdL0MIhIu1bcQlAhG1Q6Am
v6Zvx0dIGlw751dsVn68WUad+xFGQFm+D+HzbduZd7e1165UKLhZTsMtAx8roJ/xLUw/G978yj2h
Y2tS2uoRc45talDdOSnriVwTkn1+Uz4px1tpdBxSW+wt71KXNC5qqSwxWCDJw5HFiRj2+7XL7ZnD
WODAK88pLf5Ip7y9TdLVwWf4XKr7rp3OyhOqsl39txCnyl+jEjvgDW0wy2sxjCKgEzM75DrqT5J/
XjE6BeBNxoC3pBryCbgBk2+nuo75xG4/i15IlZDOwZsnOPRlUtmCy6lG2ne68HRo5gZ+GRWRbEmj
+8YVCAw0LbSwHgTHZFZ9dTH09R/z0vDzLliZ2lMrcaWF0dA3zTHK9iaiOGAbtP1uu4e9RWB2mbrx
UdlW3pYD1CYpTSriSCfNC9vBjfZxhhd1+YX8S5SQ/0cxZ81DKQA7PtnSPGzCd6/Z4ygYVOVxPI/z
40qEcyv23lG5U90O7tI1vGsSARne+Bf3CC01thEvY8YyCt/uLpbq2FbkDaCrV5mGMt56gqlXcq+m
nFGcMXuK6IHJcQEobRnEw1eN9AuXCHgZCouUXmN4Bo7EF0PxNgVxZqjGNUlzAE4zszjGtr+5F4ts
9f4BHX/8Yru/Xw1M7RWAbn0uUEG8OtdmEKJCeA3XLDw7y2vgQv5zEdCB+ettJ3RVQr3h5W3Qf329
zEOqv5amGw3A5BTT92zTV96gg+XKIWXsVVhNgtcUS3FD1QiQLIWpDXIEByDiPiyL2/fBm3JegUQA
8zupuc7qTilQMdr2geO5G1DEuiMDdLK4dEpU7EflHGV79ZkOl9n70GoSeW52ztI5c4BBm0A+PU7o
nR+IbCiYxgg20v1COg7UIfY4GxGFZylVRHK019B8jtuD6Hw0OQGa4+S/3+ZiNf1v6byaXJl4W9yo
ZndlplbV/2DmKvnWV+kqAfLYvi5Ejx0qI47PTGRPy9KCZPymmNRfQ5L70J6y2JJjw6uJWHd1aHud
PrkBabEHjbfYPj19pnc7yWJBU2jwPRyl12B+oBOyDxoVcZtx/qL1To/oqopr/vpP0NBgPRO4yOh7
upXRxFKeOmuk2v2j23Ok8TBeemKtd021QcjpVsskYMgTgtwktLEqKgRD0skVypiG9UasMNODqFye
Au807BopYlCyMmW/FCdcOIFs1Tj8EMGif7sF6aJa6rZEkWiGHMelQUFKTO53lNt/M/wbu8XdBEuq
KRMd+OKx1zPl6tCtoeOw2NNCecXIIZ6gRdNPKKzCgKHIzcRAWkHhiJQX5BSejmTCuQNQNJZElUWk
r9ABLwFHH0hZURFDFsULfoO89gAOoVVvHmCsQyu6Ufcgs7LO7Ps7kFuRO8oFzBbiDKX0mG8FLRwy
c5jXxOFnfI2OcWxHhrBS4o0hJseIogRck6IJy5fLX+zkuB4KYhW7cWHuQRyFuWzD0k+rKz0T4GSZ
Sz5S2K+O7Qf9LsZ6dXbkC0fN/9oUwczCbr82/EmWvymhAL0TovmvwqplAGhsPLc002tiiYAAZfvW
RULNvfOpDPjo/MQ1OyOgXZplJZ6ZqQFDGcUXnFmn6mLzdIAeQL5KB/to2hMBSGtZmTSFmsWkgao6
rN0nGAPTlv7+4EoD6Gr9ZKqbq4rGaRQYhszLcsJvp8MiqzL8Y+SQ6x8LfoMgCPxi6SJR34nB5qiQ
j4M7bbMyLgxCSD/M2fKnTiQTKzo+PShxUo2gd7jloEHCySE6oL6mwcjZ6mFhIf84pZ0wjwR0BbEJ
4mohT2ni+7GoZOS7j+9eDqdLxhCvmfbrb6aMKb+GUsAJbt5gvaN/znMRMKMavlBjYlmZSS8roPEO
4x44FK74Lg6Bvp8OZhFtgeKKvlC6jKDksbS5rzSRUoxT6rOB8Yiu8nHxSANEfqWHB0qXUckg0FsR
bqxGKX5Bto2B7kyTOZ0EoyUIjxeFOrxl6VjLf9nkWG6bTzKSRzqxYZXoayo6Iyb02HtanxkuLVcR
q/DU74kEVsSRQMrTJmN6PVUL6HhWq6GLngp2XPc4WS3M3hRdtCRGe9fxGlbqQn1KN+P5PY2PDJra
WytarTpK3RwlKWqSlXQGDdvzktR/sYABYoPuXrJjU8rbJFYh6fd8QFJqjYgGEycLiFTibhMR7eL9
qtO5TwhcVBc+0jsl8zxu7728JGerNSEjQ9PLHgSJLAEJ60B4zp00JFAoFcvzMR4GlOVeVAf5+/r+
oCqeh9RRTx3wfFPKPloMQVUQosTxIP5C0bw9mFM9U9fPyM1SMKO4h05cPlsVdDiwoAA43GqCITCj
0SHQkX5q/c9c40dHBg/dGENiQtgiH7f/Er9L804Z2+SOGOmWAsKB70G0Fm3PA4mXyW7/9yqE3AAx
pvYXNLK1eDbF3Mz+DGEXNiFyvPD4YxXV2rLY0TTb9HLuKaTYmQchozxVw+yEGFXs1zC21+2uKdPR
feFFFrDT5BCVmq/mycR6KYAhz2AYlyg/K3Nq88cWizuGQ3oomp7Uu7XxLpewz+JJrXC5MsBioexk
/J6CaKYEoIGc2kmr7hEAwSUw37OUJxHjX5Q37iBZQR1NWbpwxto3jjxXbf3C2G/8qq36kigg1fwc
oPDYOlIIvBWUE0mwChs3zLZ9sFLi8CerWwMWyJ1SnEQp9ySO5/UGUvWhMEkf0QHyz98y/c0H8cEO
xf/aYi1+BsSox8cAgiOscFJBwCpF/Equ3vMYhTcYy0ns3tBkZPnjlDZCdpfuwTAJt+xreOgiS1aE
mOOxDPB8bEIS8K22E5ButOJlW5KTceRCdQooVz7Xb1RA22ZPo5Gl1eqRyX89D6Z8pKdaWP1cHutT
Wd59qSa3P2fBe7lnOoO1j9oDCd3qw/b49QoShPe7PpSyRMRpYQK0roqsHe+L/Cgzre3YQRXH22nM
5PY3vTOrWOy0ywpoC3gpiunjBjJn8FbxE4YerRCKzwOaqQ6BGLkkRp6u9/S1jGbhRszY6/sIbnqh
OJKiSLxkdDMClDJRmw2DGPPuavXDm+rrWPs81bCyZdvf2ILtiWnFOVpev2xI8vAe80xh65rb/NIs
rQtUS/9g+zz/T74zQZasJtUBlTZBhxb5HGZiDSoT+CeNYEby6WcRfGBRp+kzwVtL/7FX8x72rc5Z
oelw5dz5tGa1MZiUJ0WHg6cN/0EpXE3gVX9qwHYdfVeEB7iWfF3/kRMnNqxnCb/N+BNbrPYro7Jj
jJ4Y3saVi7xXqBOSp4D+L2WbRSMGfyXE0gxRc2DFmqUtzEju8vO6b65uaHoHgAdw9MnG47X5nkCx
rXPI+2v1TMz3+cOqkQu12bMxCOYodotZOhZWmm2TFGH7rQRcE7EnuyUmZhHJJEzAt8lnmyzS4z6P
VC1fgFA1QCuv/ZXnVNkoh5hKrxHNzT0iGHt7oLCt+40WSZPdRKYbSmqdYr2/crbJJZvwwosjzPwL
H8wz8M6zuljlRQIiG95gGMMjRvnbpGFeMF5Hd7FQ0YFbioNC71jvVYl30i46vClSm8zA9Y3TCENl
/K3lFPnz4SdeweohkNbY0IoRk4ccYup1w/Pvu0NW7Rbu7x/IuFEFpzItGFrbS1wD/dRWtr/XNLw8
YtwH4yS4V4cdnHdBwtEoEqYBgOjCggG0Da8o3z8dDC1ojc4lyqNGqp5YFLMJfBrwHQW0qOdJul0C
1oV8O9DxLLpNJS2KF8htGYU06gCs3VFbilOLWNBztaiORl+0bL7P3sjJstp3EUO6vFdUjYcVPvl3
r5j45WB8qAbMfNZYdCcaZxqlsjZYA5iu/rr6XeNcLG2YiS3NIRdy8Dnbh3AgBgaO6Rm0HaIJIVR9
j3sNDqLIvFmcFij/rpRFDmNreTB7Toe62W4P7wHmObFN13lLj7KH4oapL0F5D72Waq1n8o1xbufy
04MNwqrCZ1Cf7WvopqosPbmn8b30gjihRlspIbmIvel40BorZ6LkHnVAuGksCp22Mul+AyXqji6k
bjYBRfOo7OblTtxmeFmKfDACObn55E0+fGWi7KZUyXH69RFttDm9gSh2zGyRna6YSMI3XMZ9o756
elzao0IY9KMBDFUWFXffYK2snOjmpe7C9lyQgsqbpJO37RAkHqqf3lRvaHudPwh2pv2IRqPObfl+
UoVg8UhvQYXeXySC1KthChBzpWj1/Z8ka31ZtJoE080/7n+vmpDgovnG+VgFGAbqFjMPgNdFk24y
fLXFiaw4aHFZhaKIKWkCZxTm5JZBaeYbA7EGTsBxF99EqKL/jTzUcIpL6qd6ao9epD8/oiLSf2YZ
givZ+GfAqVMZWmjuwnCbmPkpbAkMopHkiXj7WtRDUnaBFt0298L/2JW+MT7LBe00dP4cv40qwdwi
eEYgzJPklUbrOjYqjT3941paZsGxg+Y3WnnwOBnaLryF3glpNKnacBWykESZWyOhGuT4yD4ccpkG
5/YX1XW2ZsAYPq+uvzfPjZ/rQ4EyIUGU6eojSKVH8y+K8YeA9PUPsfWyGdzjPCTtvsYPMu+ZDFUT
7N0DrG7iHJ2lH/7rV5lMFoqd8b2JuTCEh2Ro5rhV5jvlbZ3TF/IllNxBt5RLQSB2ttjafTy8WChy
EEXR/i0njuS9tq27aAtuZoEDPf7v46ZTX7Ho4UpvAi+B9pKRwb5pKzw3bO5Z9hjLqg5/PAzBbMKG
kwX/DPFLZOLE5XVGpmcwb6BDr8gBbFkqRUBTcP4nDzEQpOoPrXiVwU4QsUC3O6PSw8AbjiCMAi7J
+0dXM/0Q9UV+66c0oaveyXX1Tvp2VRiPkEG9UWXiEqf7ZIfjN+zIEvv7UWUlzgaiS/hCsKsSBe0+
MH8Ox0hRCjg+ljNQHxp/x+hMFqm5UCVstNqjXn2Xp3HPwotSXC0cccGqu4rtlICrwlbzxCDdceau
oZxFXZPc4YnmXCjDGHASjvp6Pgbag89oeHJLUFKyyK60aO8FJ3Bn1++PUOO3Bk9ZWEXEq5vp14DP
UwQrALe6o/n0hEjES2I5U+lfL4GJ0uzDJVoi/hZj7IP0nn9nTR+GrZ9W+DLt6ywFm2n14QyVLfqB
/Bp1u43Zyt0htJetqC+RoXTagJdPvQrMvcJavo3W855ZFSTf/pXf+Sev5O0l9J8jlNnopjn2hX1Y
47ORfu/OAMvwurmDsZGeKN9FNIShbNvJLotP+n3k5+sKtoNQAGnO14yhDGbmDLfxTNf9hBPpfhtC
Onou26vFLaDgwsxbrn/y52ykbc/tEk212ASoHn+D4LHAVoraxYtsaN/7iAH4kTuH9uXbTBVKCP0m
NJkNF5WyPwEn/0qfqDOxRDcWpu1AA0dLR2RykUbeqHdXKxNBjDXZ3LS16Uoy6c95PhEipxpFdht2
UrnSpn8apahauDeE8/F/+wOi+MAahaK1XuW/dBvIyBikbiC6AGC6I9oVNXZX9XhonCHXfArwPQzb
zgYs95eUzIb5Ko4bHFTHdCACeEkKtkXoT1payo5gffseUQGm4zT5OeMLQWcJyLUzg4cJFlUq+MOh
b/PM12SRK4srVHBRUG1c2lF+h06sHBY/Mjsm6ssDH0F/YWQukPP+FsshFUj9tfKXgyccOjWlo7Qf
MFCpya2iCnfgG2dgVmJOagZ34FUlpBeVGLdFXHiMHGqPitUQFvtuLYnsbwOX50jVFQ/hjwerEL4X
K9dnNixf0ngXLQiMolznWvcg4MlUIKtR+VO6kwtdNJKYhJ+tKTnFDPfQKeQhTqQpIACE9tBl+/Bk
NjcU1GoqKMlAgAQzmwmhcQ2Hhzq3FxlSnj2fy4gpWMF1aKGf47UANkGQN/5RonXx5bnXNuOdpsZG
5GmGPwl97coLCopZXe7iCkJ+onsJKS9XoWBSR76Ogf26j8nNXKayJQxmu5g+3tp3NVIL9yUoy2rU
F0/GIhXKdewIkrFgTfxDKpl6b7gHYG4DWXxSaFQx0hY5zFRGAGQ3ZOfXOdvc9RlUxdTNvUemeB1c
FEtdpIw+lJ4NkXc60Q5GTA7gNjAlg+kCfIa8fUm4jwOV2KTjhYqyMq8EohEtoRvB7VoW0XsEThhA
HTiZJzbUySScOVtqXm0O/0KauPyX5qwPyARYW1c+V3fkd3YjFZ2qwkJVWkzFocTrrBEy1DzlU6Mx
7L2XQ26cdHlf49dO1Jd1Ad+59z/aC3fgQ5Dncey29lZEXQp//SkAfvQr44dEZiPbGCxexFPRT/kC
XO9Oif/n85ZnI94Ktu670/DjD1hUqwNkR4QkyPCvgPCmsnRlRlC/9cZ5DyHkrhVReSOsvogGOLpk
7os8Fp2EcX9xZAOeKlBmX70G3bqEyakjWeNP8ViZtrPLKFXtLPBCNSEJMCmgNVJ089KKrlUrUmNM
pNYjbpEY7tP114YOCq2dPOEqNZBH0Y+w8UHxWUPVRoU8PO7AQEu4m5++0RvG+wH5vp4cAVaj4lch
Xms32Bnq1l0nQfhQSpkQ7B3C6xeH4wiLXkvlWzzfl4C3JaZE3fabWQRyfRbYDm8QAjbuYbc8QoO6
yd8oBpN5DAUz409VsW+JqQwR9IdvqPwd05/QopPuUaA1nbTjsubD1856y58pCEFyayXSuIisosHt
PTU4PBiRr0JqTZrlPrr8ZayL3y+B5rvrLdHOej6QlxUO2NIla9cNV0OtW6Gn7ltIpCzTu5dQTMur
HwwXWUDtuvupMstTaiz02yCc0xrLkWNhevpCbxpbxwKkxGKgpxAEUwyxgKeptdR6c8CHqTMCqQMi
3GPDKwXx8sPDW2jxZp8v+GU9vsDn4h3MrCu+gPlihYeIU4u3VhiugOr1VI+RgT0gHnYMrPtcr8a8
OQ3C+vNeiXhYyMKkCAxqfU4tVoDZaSiF4Ln6Cn2cFIqRjzqTYJ8udJ31ye6wrKNHkQRUq4iejeG6
OBkGgbEstjqqcytQ4Sr6QB8OxJsNYWZxTGk7YrH4atFa89l0BRLNzj3tE6fn7ts7EqsaQBtEYzGK
j7fv51wRhXcysUOw+Fx42U0Uez9rGQQqLg8sBa5mDPI06F1viVkgkGAa5zqLXW0fzFVrjCsB2E51
YE9vvOCJ4ZCJt+pcse9XO/pD+6PTe3xlcWDbzcOgC1YuUx5Mj9fK1oluC5Hs9uiSv/bej1Nxr84T
SIbFZYfBjiOf7KGiy5U4st+1R8CyAK4QxDRnfDC/vE2XJoYheU+HbyLMILq2lBQVe9MxWg/AfW9B
n1jYqsJc4Auek21f1SPPYQbbxId+bSju+t/NVE3VT5UrqgT4tyf4mHJxuiEViqr6zqmc6OYJkEIt
jyNHI7DcEqlyMjYrhSooTxpM9DEHUz6PCjCrl0nMZRYUyxaQzLKuxPj0hOMjSwmiR2/Yq3kp2oFt
jFzPVpHJSBHILSeUlowX0l6NW10XX7LcUYtwmZ8BxNRotC9GUu9UC6XfWKZzuQtFUDf9zlMEJwMT
uecTLMQtC3Kc9M0lCuH08YtjlrvJrIxU1l0MP4FaLCmC9DQmMajti1bRr5CmayrVZt1ZRYMSygOd
iDOxcc9p63QgalhvhF3HfCWiM6MjbsNuSDvlZEFXZGjov7DDThbKyJ0OV7VO4GDFqCONSot2B04l
7xFOeZbCk33p0VgW2HHsGc3QzDNB2MDm2b3zZXnoqbef7RpFo3Bc71Qu98qjVGAO9NWmQdn8gh7U
r2bEp3qJ7/vOLvWcYmNcnlP8wejTCBJNZP2RqPl0FL8PKhgQTB7kZxcqsTTCtft8+ObcbSJJ3odN
Fxdi/AiykG3GX7LhvKEUiIXfDuYye3CO2i2T7Q1pcmTYEs7c7cjJu7Ej9yL6g6jQJxrC3/qQGvQ+
ZjoqXw0Fg04bqNthcnKumyNQIspZSp805VotuuhLEp3l3PTT4uCupxUB/CTtyWpDIUNP33iUL2wZ
VoQbI6LvfPpSEBxVvpe3wkxdErpIglaoZRiQJACMZmgR7rYurf+GQWdSENZozzhAL7LH9xqVAXZN
SRUOyWy/V3FNueZu8aFk5bkgMiyZEfGSLFIUw6eeumNbtPbx0TOLBV7PP+gJIbHRA5VCHZ6csqwa
cRETMZo0naacoaUp2Y/jOw8ZolglAN7SJlUdnW+B2KbIOPfk+TLinCL9LVjyViz/Y0UAgFmVNj/+
O2Rlh9AzWO4MQQ0TK8Ky1VdIAm87T62yigwRRUCBNwf17Apu+AKnQPxjyvk0YpHBl7KH1uPjC5rp
H8BqnzKltoxZZ+7PPQw7XBlMQ02h8vCpM+t9K987lw3FsNPE5J+Y90F7tueL2vLw3gEE1DFgW81y
+EIwIvRMqZVZ6v+bZptJWWu1d4eBpTI5jEOY6Y0SmrTfLneUzhlh67ZD3grVMnOcL/3b7xdHvbnk
FwgO56Jr5nAKDjDcyhskAoR22V4dmh1rDAPzUcYGej6994mER+STzSBA5/N6DkeUIJT6n2UNVmV2
+4HL8Jz9BTCKrRQGQJ2qF3jEmfURt4QeMrRNHt58lKFzXOLtQRRvQ8vYaTQhMV8W15iYb7xZ0t9x
ZdxLP7vSdu0aLMOtkfTMOH56NabtJuHUPnwD9/pf5uBtURweEqtfv9OU3NlbRefWUUEeGpKi5no/
7AQ1GJj33XyFZZmB7van5ofILPSd9CY2QqRn3EQXTQab2h/nDUt0yQdn3Bmb7EVooOgtMXYeUnRL
CsWJlIwieelojGXA7pOnhPxvqX8nN446rHcza+pTqB/VBnjsev2Pov/hjywMf9qEo3OCs30Iu820
GqexgcbRAZoPshpPfafISzFaIf+wHOTZ1xKHubncrLmpLtWBrs1JcHp/jhYDvl5StGbnXFBRCCOZ
eusTuSrpeQ8gICIxd1LcAO5GTYyVKehHZ9kJLpH72YNkANbI3mKfje9XXwuwPKvMeLln+rbN9OPK
HFFVcFXhnjGRe6YjrqWm1VxOMvxgrZE4gjvqS/edDNNa6JIpRPISLmEo0kYbiVJSKlxRCgWw5Ow+
Omg7xzCYXnEvkLhL8oQSsTjte1czHQ1k1zkQdL+ErU5PZC/Lb9cqj7byDLRWg92+cY4VJzslJG6N
4Ztc+rIkBhQhjkWK0ZCS8e2lKB46AYiDnJRabJVyG/BOFcMUuCfkpWy5maXz8GIMx4riuwfn9Es7
vD94hqw8A8DLsPH5GZB/ycfHDXs8siYcp1kMFHsy76Ym71RVC97lpb/5yq2OgsyAYxbAruNPLlMO
WR1ya4C0Jig4h27NURZitk4Sg8K3gl1E/mSl5KEykBoueHkYmyCDQPvh19RNO90LIkrM1IBk5hae
frGvH0U9Ap+EAJ0ZxhHnUKT+F6dr1WXPT8NVHDd2kgdk/r65m5Meg29C8XqvwyJYiN4bB2j6rAJ5
Jnn97auegzNU4zPEBn8ndXkmbHWUWEPAUNzMfQWBAsgJFrQXeFZAghz9UrHGwEp518xj564km5+x
791raXGJ15b5feZq1NvhPvcsSCmp0m7fwvbjTgagC6IOri6ZC5cDOV8UXSm+DbOYEdCltvIRlxnD
NRtJJnB1Gc9eKqceCG83TiVjCistOkx4EnyKACWaYa8uc1jEh8Zl84YqAzU091aeS09AW1LOp5GM
aLOL3L+aBTOv50PqWFRQbfunEKsqF1rSsCVXmc1qW0MWHdYR4xYnZea0S+ws4QIYBAzkvTp7B6EK
EKtYE5/BFJ4z8lNxVL2ll6JIJg9x7nlnlXpgkHD1oaIY+LaxpKisgwkQqmIhDdAnfP8IwYlyct81
Njk2Rxmqt3ajUyk23HFiehf/R/aVbNH1npMYAyFu+MK4klBf1nCjOaFJ1I1cgfF4tLTiMG6dH0EO
JEA9rrNzt4VP8Mbf2b80rI1hMSVVjS1LitTa54/gmhwnWGAwDpv41jAmKH0VXyTHXzzGjZNbB1GM
6MSxxXrarULkatBKwhihYBwgi3BmauqRM5SEH8l6/D6e8NqmMIo9AOUV30G2K8anudCsJGEQVgOV
4DmADBFBVaQzlvoXEtH1gptt4K33drl5T6DXSKn805q7ltf93mPJ+KMkfXn5r8vVI6WL81US+kCJ
56GlzkIP77FbkAfgkrp5jL1sEKpkyf+TJJPyzFEmuxKdtvnpo7q4sw+oOOv9KVnKyprZCt+MaF9X
vU7342PMlHPMsEW7b+AmrRWNrBaLmzn9fGQewQw17r1oZnknGDrSjw6s1p1vNtMvwO0ctUkzckh2
zPFCZPRF0x46iEp7XJ+h/CoOUh42//a0j7hPF/gAey7e7MjioBXMFmjeVR9rcLNm1nsAzF85Vu3w
XgWH0haXB5QQiEg5zdHvZAc5ZWNz0yHNauDIzHvzhCXsvltHX6bYEN0Zn9Ptr7HChekCu+yW77x9
doiUtULl05lJzksZUBRZp0o5nk9GV+qTmqndHYyzvrchrvvmbc5nWLHWZ3/TD2pMSP5y/HPpFHS3
7cysSW4DQJK8VyaLeXvDEqpkgoEwigAXIxQgMJpBcBjsOoRSGdlsix3nSlNCgTIX/m+8bgejZM+D
ORd1YCmTuuTdn+ok5xbhhONQL5EGijrphUh06CynqNrJrBi4YMUD+J9ys95kWdGJZy3LkLDCgZJo
OvqzbhMaPWEgaSoghbAHFLoiCFzfNFB1zEcwrfUNkzZBWAT6C0otqTCZjhLrHN16Y8pOsC/t8Mzj
05ERy1SouDgT1o1Je45XBf5OLj6nRbyJIqXeRt+UeKGBah7DBmIzvLMFuN3mrH18ZYmy+GcsttGF
GuQwUjY5l8tHZ5m3/I9S8kS70pTrJQcKrqez6Fu5NIpn/DVb7wIEDc0mHKQI+eawm+SA3gRWniQk
r7jjWqe/YzNsVhMygmRS0icCiIdurz1emksTvV1VDmmnMIkpYlRM3gHrK6N7Z3vbj7NKPktylxcy
mfoZu0EeUFGek2b7DPd4ZhRrzo0EtVtQmRGWU2Cc3mxtRjDLfE8RNr4jj2YwvjCj+2NGmzx7l77P
JRnx/vFunTmFEpC1n+wapB3A55FXnRtGMRq/ULYiyzejcNAmyQppjGX3OEP5pjCU5oZYpHRvMEDO
vuN0+ErkNSHpYRhvPOazp7NDaD9vlVKpcHhS+iZpERj2qIMdL2Os6eTQUwWbXqrZLSGJExvx1xwc
2VgW/mONGf5JngA9VYd9UJZricu2KuQiZM4yXCjjGb/KICcz0tPxz4oyGqNDZYQ1MRUCmk/5fhDP
gANKbTgmNDvgkQ48hICQQVSH7ANdgwEgbauzoqNpxSm0qAyrpY8KsKs5SgdKNuzT5Zr6L5klIi+S
Ko3ZtI6C/kJwT3lS115n0Hznrov4TGCWFFev3gKNgiNDHVxLi2AOweKP0N87UdVY+fTLtsWRXl3n
3DNSc0GjUcN1ws4tcWbZkidUptPWlNUKHzfJfUzX1sOlM0oyXEyzy9XOlySz+Vz8sNJEAArhruvl
6PxDGCcwHQXDUzeDNtfm/uM2/nf83d2xJBBgD0SFGzE3oWQTIa/JgnCyWwsq8ON03pzKctCUN3qT
orsNzFjzyBRGKFi50TUlckboyPHrVAiM3jPM6jdaf+Fz6ZlQx9i7j5OafPSgYAutX7YFhV6YJbTT
Xhb1yxtUUZMzmKVl+pg0kjuziK1P91CQ4uYYjkAg9MpJ5MZV+QX/HcqG+As/6ifpvqb28tm4Fg/A
+WxVuA1g/DHNrZrjaIwkrxZCVMhcdueoEZF0aoFP+I9W4pRYn4w+yKM8x849Mn16hyo5OnJzUHaP
MiUQ3oTqm/GcVl5I1VEnNS9HT5GxnKx0c5EW7WO/leCWenHdIZNKhsR9lBWSAo3+2R6hP1EWAt1e
mJ7lHHPHnC15lq1gXDqEpsuFhSUodF7zS0lP2DMlsPu7aBYQRtXjUJe6oEecwHyq1FtGrvhsdQaQ
G+/uqyTygZJpyLbBNMyOxA5g8AlilmAnfZMzZ05mBXJ7C0FvVy9Pa2V2GGSuoyyAHQnHQWvoOkiY
IllajAffaenOMLKfQCZHuPBXNDFPAR4df/Kvw0i3BwcVs7zGv1o95sGwquCORCdnYN7JEGgE8xko
wcUO4PagHv+/fOoxMMhtI1qxQypKcyKWyZj9Dkyar5PeMdvZX5OyOoLpLcgp5eIMJIMJ+gAL1ciq
Vas7ShEUR5+/c25+aJM30nMUyYmIoxpyZPMRZHVSNKQndv2KSuvhlp6rnsw5CnjUkWTfRYa+8brG
qKDNkoJbYonEGm7wnHX8CRG6wuGsi0ZFyRu6ILd+DdB7WrPdAnQ+z3XDOZ8/mQtEcfEUzCvA0l4u
TLtLd3zXuvYvgzAVD1+wFdFPAvzngHp+CD6i95YRuRoUafvlEBc6uaQp6KgqNIq03Qpf4g2TiDlm
Yc2tDkx1ylxGRYDGIMH1JphnZnXMEt/JR0FXp0o613Yb78V9W1cu+NhQSlDYyTbdFxEQYZWhtFdW
I+/FqNNgqDwSeqOTfM8OlQrSJ2E3tJRsOp8azXIbDB2vJTTarBTzFMxRoxn7bFFArmQlQ7ZpCACz
xzM3fZgwMAjpd2y4DgaUYd0nD/tpkQV1amB/gkXkdgXOSp4SHO1FDee5kdNvNUHNfLM3jh0cp5N1
wYb5Uju8U7nj408qWgMUsPBAW1JW9gE4s3DkQ8oW72HT2rlccJ2FFaO2vu5SNj9E/qOgUb43GvCs
/n1XXuDakYfCBr0T7dzK7kZ0hUJPXvH2T0+9J4bn8SQmhUuGrqlvb8kBIeNA9MEYOGaoXOdTX1jU
MyvUt8P67O/3OEOHAu+YOauXz5BS0pou4YKBcZxtE1oG8vqF+WD7l3sGqlW9HDJ13xbw/hUwkah6
np4gDUXDNY7GgtipZFn3THY0KpR8nBeA/awSy5dGq3nRcpcKRW/XLkDLJFzDJI7cKVEL36ZVS+CS
shNv8sTTWzJcoHw4J5aq8+Io+64kXGzg9c4/n4JbdO+b/fw2WOasQO+U2ePOUbNzrGAHfwEbRCSr
DGigWZfEh1X8DEkJXSur3aZEWHKiN4jQgm5sfq/4hJFuL7v6t+DXQwEMPW5Em0bDlPMIIYyC7um6
yFPFjmJMZCcSS4HS4g6TSnPYrBCEpI1PaSyRfMf8FaIKSLxRjY7Szmi6LJ89DgZ5bxeXxYPhuJbX
opl7i7eeQ1BFPXyCVlQQyjCeff4gy97ez4oyuZEHKNV0VjQ+qIqM9sy3GgtUP3nFjDDrcufezA1f
A1Iho3akO1FjwSXvotzL0wZwntad+GZDJy05uiInRTI2XWiHnYV7eT6fnZvPrSDkTRPj05b+NetB
CvuKzVZAnid/H5gBSrAgJD1zaf01hp17B2RefE77CaLi9gMEeYjmVjB+yqlTC3DcbDxGcmB78n2D
VHxxuAPXscFaOb8QmryMn8f4GcZ5uw3OAv7rSxDd4SYdx8Zf+JCbKKnKWc70f53uatOoZyD15oyE
Xl7Dl+OibGPjPiIIXiMCIPGVBiG7alSH3dIPWULmOryHl3iFsjUb2up7tDCKGb7XH01BCXHpWO8a
aV5pqrv6/mJe+AWy3wkU06nJF5wjM+FYcE6DNoR5hDLctNhI+e24xlIvapwaAWiNHpwRGw9njweO
bEgK0Nf4v8X3V5amhzbDLZ1muCLBRWZGwR4KrtNCedpFcONhz28ygeOi6WF1v5yMatb16vebgyTC
fYAWkEjsgjBVoO0fo2nAhcPVs67FXXPMAfQVmdIRrLVZclq88QgnwaBbLvJpFjnuakq+Zu+9qTLD
WrsZKbtQ/uk9eahOdreG98JqtDnon5Cdqlsjr4Ek9TeYrdGTjuqik/0Pw77pMAmGTQkTDuoO0s9y
8ETc/zZu2M6baBdH7vxDEM6s7VhGytKcm++5z2RKl9ijGxYVnwKFY8TObjYtmzNG7lbtxTv7Wo9h
nbuxCANHB9ajI2CWDJL+G2Lf7diGpN426dkC2J3jcUiakObEP0L7H+JrXcWS7G0AjkqdY3ZJ80ii
YrB/fMUH1KXexTqYlMSnAuZ+S0O/H4vwgucEh8YajMMez0Frz9bmVfsuIZY+6BNLYB/GfkL60mnr
f6EYs4KT+sh2ONy77vqO+cS2KSDKq9NeltlUNSm8eBBr18NYj73lC3jGIOUQGQs2V32N60SytElc
2xOvq5bz8qXjdjYnqS+iGei6U9/9Hfe/oUxXA96ylewKdyCr7eLzwn13ptN/6V/rCOmMy1KcU8ji
NFpIrLeMrFxkQTGldokDqZPArAE2cQNTNdZTViDg3tUqNWnyT9DtNNFh/+IRxR8QmogVGDf8helR
sJkRiST0vGdA2JykWQwUHpE4E97SelTQ2znr3PTSvIRoYHdfZa7JtrnNHTPU94jBBoeG/Hjkt3sL
kOMj+swxTFYh7YOcX/xfyvSqE+/jC7UmoB0cBoMd7QVQkrNK5NdVWX0wLwsDaFJz6N/2DugbZQRu
U3agwu+3uYUwI60JDoepO980sXPqI1gYj4B9qkUIGdU6y4wg2LI84vco3D1S/sMbU3YAafnpq0QF
SZW+YdrCMMeROhvT0VAvlNzv/brxLRawYhaWPEHEPclW+SDsc6KDo+UQIFEVJd/dekVcJyosplhs
qkFllHl22knoZW40q2Ry9lAYQUhN+1AA8ZC1H8gr8SQ+yvkNkpc/rSm4BBW7m2A1AhqmyV+Yq03i
Aa0ZteAiyyx2krzqat8nwG+CMwenbJE2Wdh61CLqSJPvSeBwliJ8H4P6C2g9ro4PM04HVtkvbfTE
f8GQ3tERaZKU0rerRBAQXUgdAHViAM/ACnMWPoHlSaE8meC6t+Z0ODM2i7u3IJmJiI0QTnaq75SB
P3Le/zlvVKdbyDLZg2S4CcNelN5oAa616cHJvLFUwvqHfrKkLbAyplHI3d+NtaR7XIV80FkK3+RL
xZAK97zoT6UPWLHQxv+zpALhI+PQb97YTSmq3BpFHTockpeoiZBfW06Epa6LjATgi+g75smX1Alt
j1HXgFaOTRpccmeuO1IN1e/iZ492c1JNdeBy2NlL/tYulTSEDJEUSB7AZXDluB03xY7dVPrz4izE
Eja/Ql4xN7pWMXef6MZDG74rc1bj0NM+7GT6l+ATs3cUNTUgnxyBStYTF1S8PM2fxaG1sbLbmtWe
Ab46dzN2Am6joyrOpEHkMKc0ZFCVBDhGHWP20+XIDG8tCqJtoO5Z3Kwfz3xh1RQepatVFDv9H084
78tSSXBokh10ZlS6Pqm/DBhoiBZtYMZRuSTVmOZy5ibbOg7zcGhKl1lgMRsTxmij+IBpn/4dPUmd
//JUvPKEP62Cyl7Mgl8QOTiXCv4xaIltfrVzplgJyism4cxImHNNUnVGze2oIRfQ2m5nPTLpkRtp
HVSjO4XsZSIGo21+csq9afzm8WYZnXHlUT4rk7BBPHOISqvZLUjc/Bvy8IMzvzkWGZFf9xjcraSn
Ap2+FwxVTzRDYR10njEIiiYpj5ud8eE9sEN7CnXMX+pAdv4py3RcqzOdJp+EfBIds0g69w5djKO5
ZdP3/P91HDBduYQBrhOu7PfFzewxbFQ7E08bDvFHIDYT3Y+O4vc6fS67EmADrJ6IvtkdGbwCA0GV
PAUqn58CkFGYlxWy3Eac1IYORC95DIYhjAzXhBYYs5pc+z0uOp8o4jlYGJ6SlIJSCLyUNGsqH1fr
sm81CJpOFRdYMgGs6qqeDRvRC8GBuAq9SK3S6P793KQiGOOsQuVXSUYPPNIVxF1TnjgD7miKPEUu
uGZh8iKLTtqJS/PbzM5/ooAXRJMYfGK21mzODClO+yCJUONm43pQFzKoCJs4Rz0dBwUvh2JcPoRc
2p2eAJecVSuQkvdQI5mZjPZ4tcoaz4TXv8G4Msr0FwtMs8KAs1uM8g5UxHmJTvjBqXPxK+Tq+RCL
rxFeOmZsrP8scnxvmDdvMczDw/S2HlrB8peFlBHy2+Y1e9wVmgUuHzymPMktLvA8H/BNBmM77oD4
6KkY5NZ0IXL3KAKwv7J8s+5oB1YRAJMEzLoUSwD4B5j0bAMEvmLo/i6hBUp7Sk7/nK4Rzu/wpYKG
qWqXPaDf2pIxK51i6SX900VdAKXvxldAnjmGWYkN7XqUPTusDI9mobeuEHWB3BuO8fqa6odeBgI9
fn2JHMaOka8MtzzQGJTx0ufRmkIPKODEEG1bEbDYXJKYzBR/ZPnqRXLJXb2mCZK+RywG5iyohix3
ialNiIxNTxzNV52FPh7YK1vZO0D0mNHqifcQw+CEN1OeaGIzUP/Ocm9lhv/qxpAvSd1BFeLoSvJ0
ztfYiINmFV0bHVhs1xyAiqtK7NEcbdckbe7mIBkpZGUp6wByVdJw2ZQNLB0cdYPBXyAf/vfuDwIY
GaoN3TrqfNl2koYOLav4Eh35vgD0zC4zmwQ32UvSVrukD9qUo5V7Q8wDNazIffbKOuo9CgJYCWkl
avzbrtVBWGtnE5pUSUcfxsWoGtLLZpJXXe3Vjls7X6Q75+xrTeywt3tbID2tRA07bc5DllmbGDUm
wnh8nhByS9uOcklw8Ey62V6rLsZAYmZDVMStN4P7Yxs0ZSbiEqRzl+FeBU6GJXeLMQ34YI8bjz37
K/4DNogkQMG+uQmsTZUekds2zPlSfB7dojA+U1HtFK5f9AwiBlYIxK6HQB8P5lzHNsGOWpA/Dh7C
oqsyqBGzwouK7WyLwnaENuQoatg2OJCFR6XX/9HErUSE4P9aG/SHq92GIAgfePDt2u2+7ubAl8d2
hjvlhjQFoTjQ2cKiHr6UnJNc8HNkGO6K4gFwMenfd8ZTOukZnGjOK+wsRrNGBSWqSFItWatK0SK6
lin9kriepWD9lU2/gz9ELo9y3Uwjf5ROLbk+QnSIxqVXI7XdKzrasvtqQBoMXflOfVFmLTxj9pIh
fzEBsN5fElTBQ7VtYWGGjEaIZTJmxrcaRa3sflJi1gDWEcpmQFl3QRRqg39qyt1ltEx24Vr/2yeo
Xfsn+5ghJJEoMYk7seP1zbyzTzEyKcA6YVCE7baQvpLB802/xX5l/540HxVMxWd4uWmmF7o16Mp3
2XgGbsehol5+570Nui9/sXsAYItitjpzbJHW7SXI37uPNxnk30EJ9DR/yq0Xupe+/Kkn7BiBgpDg
+uPHvihvyfYoDXmQb826enaOEsASJGMf+BmqkB5ka/PmiP15X8f6ZGxbGC1v3yHDjMT/GL4L+Rif
pELlMSc2klbr7+cyoVlm0iD7RJLHY+5wJfpCZkSZ2nlHxvLyShQWmY9O/deYIH9cSApCZpZcMsyK
fyF18BoLzezFNZpCuCry/o3AHITe4ZN3qbzJHbUQ+OVO2pB3fkOkXlxblCMlEdNasx+MMXl3tOq7
gka46Ppo45RzbaXu/KaIOQqha1NOBBDJ/y1f51E4qYYn0uNlKkkivSmMmy4WzKMe4125OVz9SezH
isC+mUcx7ZvlOBD5PjT9GWjIYJnIJ9n/FP+Ve5m4sX1l0MOJWh4wOEKj94ONhSo84W/gSz0Sxtfj
JCaEpaAEO29VLjUoMJknF4Q7l5KDxPJnWsNGxz0YJI+Zqr7MxkkobRmQwtu254ieCwd8tSFdPQJh
EfJMzitdlqy1Yv7hKc/sZszvgDCb5ZGTcCRdA6aDArvFOylMJzq3D2EvfkdmM6Hdcju8tlAY/YPS
7ZTk+CGJjmtFFrX9hFPlMiTVv1Mqfju6VfaIxx9XFvXn16PLGcv4Y6+9kxbmHUo5JMrgYHJOm/4q
skEaGUaqbxRomXek671QT/jOa5qMddMt/imsATkAPjIy734OpZ9SDCJH8xWNV6ROfTwevd6aqvcV
BsxU2ErB+HbeBGVuXKnWJzjiCbdd3vcnI2vzslDAYqwTllaXHJ79aS7lsZzSQQhTcVjBfuPEbg3j
/8y2/QIS/USG6V9VXnOCCyH6lndSU1g15+e6u25kGZ2GxrNEOaVBq6e38Wjvt9jMowV0oZjrZug4
Vqn7rnnln6ZU/a5O9ZzlXh3FAiuwpHQp5m85ll1G6xtj/lHduqmZxRa138c59/EO/iNs4Xv3QXuH
C8oqcdSivKoDDI4Iw8K3Urv2kjvicerAg3J6tTMxzSY8BTgT8R+cRxQ7RHqWPYuFJV6uA4Bkum7f
5OxZV+TO4ImhRz3U396BzBD2sUEyndyHS6KT3phJ3JIq757e+L3DPgUvOk1cZFCO5zoUTy1EoNLX
Ys/lU2lOFI6OXob7lf3Jd3CXPUji85dmFDdmMI6CWC54nAEqhIhJ5HIcFotEjJ/Pl/TkOxtGDzBV
uAQ9t6qavikpd5rpQBXaRoazUabBgPeNRDEHjRes81iMzlPlBSfFwFY2h6RmZdY4GYQKYMak9CHH
Su3H7hJJZRBNUp9RWbW0NSdy0iVy4Ah14bdpbH7DxljMHFrqaFKP/n7yucaCMqGwDo5+WcjRTOIQ
79yCvn4zRJ8pdMYcB2tbqbtCFYtfIoW6ezDtY2eSimjht6SiiL8/1+F+eXYPbC5sUqfrphc1UyPc
wDssC8pOI6uGIbZK5lkb/qQWr41VI6FueQiG651LADm13lIL9cjYpIQoYiX9nzvfdjt+J3LBzhsd
t+T+5fYluRIIvNZIFlE+Na3h39BErxomNpY8MjkbjQbJcCzteMh9YiWXPy2f5GC09qhB0N53PtCk
yTTZaHdijwnMQfy1Ago31/iqWRH0YBGJylZ8NNjJJQu+Mt59slhqjBBUdcmyPQTEOP7oNyPRf5aZ
IIXPsFFvy8g9HdtVRr1ue65bAJBrWeIlJnfFfv7oXjXXafV2Rma2aT28glhzMVSvUyYut7K9X0LD
+qt4LAWRWcX/NpPqA9iCeOezBeAysGsWY0jHBWT7rWE/UzV0fQLcS454IYGlRNrYGoKKnHhHS6Ih
BjPQNu5BS9kvEzj5xCk+/dLWKJOGJbHGzctAfuDkImPVrgkv82cBJZ3C+xggtfnkzj2iDrQDxw18
u9D5JhkwwpDXblSJDNGq0Ix3XkcDf6b8Q667Kl/pLg/tiGRCShoWQOriZf7VyWCtJJ9C6yxtPPIC
EweB3MMVohlU7wA/zguSwnOyRbGlLcVKUfqXCoKcHgFSi1QE9DAC91Lk8kAUh94kltluM5aoaYf+
omV1o0CKZbr8aAhvBGbnuvcmCmZcvb7BHbEt7HmRgAo/pxun1gk2IzMtVYJyx4zfOEIDN3lNJbuv
Lp947tnF6RDUaIWp4E7xwAeSY6F0jGsbNMkgNo6U4/wTIRjRNPR6TXE9RkPJZT59TbaR66mxpu7q
ATxVrXY7lGKh0GDcyrRrqplHsUoJr/vVB4qrMenx2g8Nxc64kFaYWG8XjbOTK92aUNNBMesX5rWy
B7ZhmnIyEFq842kivOuKTjMc/0yHmdMSwb1s75UML1BVw/wq/g8IdwOHNna7NShcELI+520qK/my
hzvnB1OchpsoTGCGf2ZwGlK828tvvnKKKOD/o0JpMRKyTVV/Phe57cj1K0g5VewPF6LDs+j2I2ju
ZSy95pJ6KvtPFTqBghi26IEW+G+5983BBM/KfREGxCr7K/vqbdtjxjvmIkgQMPf3bd/o/r9nPVhU
vt519GxsQay/nUj10bEmSDcASGXtyVk+oKvIPxF2J5ZmtVEQmMEk2BgdIqVbv363EjpOtUMmSqAn
cRDDN5PFx3hum1NqY880yzYzGamgguEiQoyIBqYk6ota4j+q98OGE7Em1+ziQ8wMmcYcDalOKxX+
2ymvVf9ucw9QciUTQEyRXqdvvBnGUdEeqDG4LhK8D3rI0YRxutGr+CpitNe2K1mhRx9SmMgOsN6Z
geijgXyPj6MDmOZBBik1I/ni2wxXKODAp/jPGNs+JvbEQx5YBpblg7tjc6RP0Z0C83oLNdd7JUW1
m2lQ9FHQkhGpbS/5YK94FcEDznR3Kvq7Iu9Jrw5lPAY9aJbEwMEtztPBh/+CCkWutuluAF3s2oMF
e7vzcB3HaklEQuWW+Y0C1XJXT0/+HNcTZ2Fcspgtcshhvtk9BWOd0KR0OjMpv0iTP6m44IQ1/Jhh
iXM1ysB1U064lvgLBYtAXQllw9Fp/tyEspJgmZqpAZRWLutJOfK5yyhWeegQehE5+CoKhMLWhdob
nsRLZgJfXIRviTVBWVvZxBnHcSHhN/YAY3x74jVRoLL47RIup26qWEXLNuWg9r0dTB5uY8pSyK5T
RKZqVGu+3STPHpeF4ACrwCE8F7wilQApr4dSU3wj27Pt45XUTdFQBGkF1nL4YSNIlTy7rM2K6YSR
lksP1URxrmv3SO/ME5tprj1JxBDcdrPkAVgHOcT73safMLrVOAlIJBOtPYV+PL672RvSjenIvYCS
PhVqA0kzAiDs5t3/GuUJnpdKEpSSIYYZpsgzwsv8K/QRh491rcJbX1j+LBf4DUGsNgYAvpgkV7wJ
zh27eaBeFWhI+aj909FQ9p65LWBEiaftwHnyadpMyg7WGZLHJVMAKWD+NsjepDN321YVx8LRd4vd
MAmElbHq4oN3rrrYtREeAw8h+vFVKeoxY0n9xHmj347ynMHSvvmik875aBKo2JfCZ7wKcplX4EFH
L/UkozlRswcAtkIbo+kzwfmrRKSnD4nOPA8UTrNrKpea+U9r5hp89sZf8qh8XXaIKNGyMQHqXauP
61Fvp5j4RlgmWs7IV5VrzSJDr3VKuIbcbllyJC+yXTvmmcUAe8EL32jBi6Pv6vs09EgdLuwtgHG5
rg67qTanx4XvCyZ7SY2CzwtM8cUkICv2g0ODu49PXOFvuKmBpMoYiqGDT6v0jW7pQHEPMXVc0Tis
sVxUtVOC/a/QKLndhMqbMrHo2Vi+gY0+Z0txSNM1+jpFH23IWtqOpw/GEzFgh42oyPJt6IZYNBQx
YpokMuNI6caxKybscLQ7qIsO/D/Zg9laDqXBtThHfiuj8f30zZhb7uZ5fb8vcSiGNviahSN/Ku74
CYVYqYBTEx6fgSVOod7Z48l/CykHUqMhPS27LsU2F1k8YyYSg83n5yY6K1rUj0Cute6tZgI0PoOW
q/dzACZd1qNbIXpNmWmDLkka8B1TUknPupjY+95l3MLkOLenARaKPcY2Ri5E9flgZOyT/W65Z+/r
JT0Y0NpXhWWkVqKqW33wYKZxuOMZpL3LmmAqfyDsy14y6W5DhSxIjZQJn0LPVmOKpGP7A3aBILxY
z7W5Iq7SkGRxa3piZvi9+Q6Or1xC49aMfU2tk+J9VkXKnI3n290orWTCU5neYQRSA49Kvh/UdWRf
2Td/K7E+H+AodS81wF9fQR/n2M2XNhi24MOut+mAeUjmLRG2iTkqycYk0hK4rKszw4wXRdHPLot1
hJnJkHjNGwwpIThueUq3tZOWmeBGtrzTwwvU1MvxgaJbVx+7bNAJcE31c4/ZV7jfTejkrIXrEefy
TsePxlCp99Jg5yVI011suqwzmQni8+DI8mIzhAvIEEbAgoR4zLjG/VO/bVk1uts8q3vmqD8cHno8
ZbCkDO0A/1OouHs0Q8XNvMhcXtovlJ23A7XydHtii0qS5OMwCHyOSYDzsJeOtpetbaf0XCIGOomQ
aVADoCCZ+YHW3Sjcm8HaZpqbzd996pZkVA/jmRFEbLRL4+9U9h/CTFLzncfhvfDmJ5+bE9zUHi6T
ID2smsNQDpaxr9rzNnNjYw9xrn3knH83lN7ugpHMBjjVciTWHNP17Y18yE7He/wbyX/0Bcb7vv27
CCj54rtqpaDB36siF4qZPpceEzOnZMJsDW8u5lJQ0qO94eJu8EIZ9aGsz+jOj7Y9DgjS+an0qX/O
o3yw01SgbGITgcrFKcSytbF0mz4lKEUTprh17LwZ4A9zLG8Uty56X7M3BXL+LFs0+TQNVIUdcD6P
u0dyHAB/7TApzqJ7WYZK5PG0cN3cb4EplYAoGft8uUEFBybjZULJUgEDG3KyCOhnFtow8FiWz6A8
GIXRqit3GNWyIa2qCAhP1K3WtL295r0ym26ZK+I7G/Am8AMKB5N+YJmgf9hHA6r4vXuKN2R9TPr4
Iev2uFs08QnhV7ySx+vSll4zFgX2FTVm3DY/Geh1V3vGKnPyP723q2sN3DrEfLT1QNpT9AfGyfi7
ZpNh1qHaBdvdj5QRBjBpdudnC1fgu36lAcbznz/3ZRJWdFUO2HaE36yyMIDsQHWPyh5NpqeOPy8E
o/mzOgsQJZgVZjWGRdWo0FA/T27i6iZUhI94RyY40jPMtRQIex3XGZEs/CTgwNCx5VbhqMcBl8JI
MAtcgnz0ZMwkq31FAuyzCyUJGLRNm6910tc2TNcVKnbHtde6IxM2WDJKg+7TwKV4DdBoNbEc6HDg
776aDXsLRq5n0Ellbiq2RUMWqiGK4fj7PS0doyTgyDoVLbnWhusZ8HGtT3mGlNNhpjmNL7VRDhBM
kSjr2dByfYb9t+8LuD7cbvMgKP2QM7hVvS/5nL/H8oydXZ0YMG+G/kifNetEZL3wg0FmDpWP93++
10pXJTI/wp8683QNcnPkHPzdAl5ruhTuG+X5rGfaIP9DA9iwX9HhEI+bn0fWT6pF5Qe9SwtRt3/C
WyalGU1VUFwaXr8FUlglGH44JmnjgULE7/BiQaJjFUtnxpFvQopJ7NZv1zAFKZhWxpyQGKoHNFRF
Glj81PRFBL1i65KZ0pVn9GWheWBljuYU5V9nnIKlqofU++PgWrAOE02a1IwuI9VUFwNMbgVwpxWP
CTX38WEBA/O1qJik5hTgEFnvsm6J76jvJuSYT+1JqEvLqxn3vLZ3XscPRATTBKNGuGmK4Bf8rkvD
58MgXFVbbXOt06sMN94DlHkYYMdkcp5Ng2renmQnrII46C+VWM85OoDPe8L2yzUtT0F9o8lJDH+/
8895UwJZwHsNMrIpiX1iSnZr16BIPr6JavOFDcKMgG+yY6Awb7RcqKrd1wE2/xNxw1TyCRBrz81Q
9P3gDE74xCr4KpaTG3mGIW9nLRGu8OPdMKtWIQwfIdMBrC8IOqWRxUjpLVg5/nYc5vQyl/CESPm/
TAWjr9UYjmEh7j9RdK7sMoGj0ewxQF+HFQqQRHKM3FblNSXnqEvNltxi5+orxcJPI8e8yQHHnghQ
XV7AjgS9iC78Ul0Pi7YnqsbLFUPQUViiBAa+c4UC6xQYeNCddtF/QecyHXlCUDXIj/J/IG2s+Vhm
+hDX1j2qwW4urOLgHmynq3gYzfwJLpZ3i2+IWE4UEfM586VPEzooKNybrohPe+7dLsHoybwe+quT
AUNI4aOeYNPAeqYITYSWg9JNJlR+l6YIUeZG0Rc630q3ziwUDgGEtUz1sE1aNnafZuTCpKTdkBIZ
GC97bkZcza8zNtK+m4fv4/yY0qmXn/GH4Bjs+DC3QkPYWIEp1qvFRedqkIEg8OgWYgbtWtx0kvm2
XeTu1p+Zrg2JofspfDERdhpxVdcrLG5K8K06RnoOKt1LhVSzPShwiTWFoGETOOD9VTviq8NX4noH
sxuf972rnyGZ+iLMMNhqzhB1Ey5M07co9qn6M6E68KABkvIAGXzHz96mYEWg+l1uuppCJpNG8+yq
tSP87IZALjIqCiXoRCo9cflRqrNgzPeiF0hCabXDkpinJij77UePHbfVNfAqcYbP7HJFXEwaOxqT
ii8d5MmYp1P8UoKP6HcSDsQZrGq2lxSeBDIaqd335710o7H6U/pXpA32CQTy/2ldFqo2u1G1NT3Z
/J5GSKIeWkrfBc/aqu4ubOZ0CkRKh+Qt81aWjGolAy+/9BKRaq79qI+BS2j3iJPVlxFL+X736ajB
P2h4aGR9+T0huiriqBrY4XKtEmWRp6dKCr4pVPGy/wtPxBaloDYM6/z9xr48tGZF4b37GjKoU5Rk
JJ2KU0lQujlkRsFvx0GaRTFA41raBN2PycrSKwv0lCESK5rqLFqgUSKpnawP5ByVzl7FJ/n2iw2i
u1QrphPGSNBXnO0IQSg66WcEiaFeTAnqlogce+jeoC2HhEZ8p5blgx4v0mPRAiImWf5JkQF9oSY9
bPomeubGrq4Kx5LhhHjgAhQTCicUNi3R0uK3MUgNsgOo6SdcswJbDVEhm1RdMM/eDGp4b96xa+Uq
aKSBrYV9EU7xYNSY1V65sGqF08LqQUb1djtj0QEp9cD5nE8Jl9hp4KD0kkZbXh93/BrAdGMk1/Ih
2AkaFrCHpKlKECCn0hKPEgDw+Ba1Ny4W+zMRtZXgqEOjoG4WpuvPqKy4ZApOtRPcDoFl9OE4pnAw
5VUo6JNhnSpR9C0efg7NEV74aWTIbt2zmEQBiW1jzENBaXKR1O+qbpnEb189pX035vukk5rt0NgW
PFAHR2tGFaj9r2QS1PHUxDDLJUoPIvzNc8/J6HM2gRSrzSYEOxifitVLvBXtWl3+ATFp9Gua9Xnf
vYvTSErluBjUgwbWiDMShNJ1KdSPHj7EBW5CWxHv9g5Se1/Ymz0aOmlcoHobYSfFY3xYFdceIwlZ
9rTywhuz8Sdb6YvIqGqH4nv3vZuKGS96Y+cSX0A52DRz15vTfZy7RiJd/TpJHkS9XIa+zTRR/swC
bkad/SaSshfMxWTo3QHjl8DbLyFLifluiuC+W/hsSK2kdckfR6A1Z3QtStwgUxJyGAVbuTXSptxs
x8iYZGPV1tEtS9FZ+VqIEU7/CEzcaTw9zDPIdzKoEwmwulZuuvbNis1KAW/ZrebarnusFKqm4pX5
LI9xmogTyUAjXkKdbs9rp0M0RSKiR46oDp1H5KlvjMAvdVu6GluAqohIKTMSuKxNJ/1dCG6R+Jx9
QTPIpB2sKPw6CdX6vfpjf2E9gT1oPwVxFqMac7ZYlCoj46bdQgIM/Wk9+dZbiZmILFXQFYKug2uX
W5m7Ev6SyqvInKPCwlUnA+/JS+Ey2p4l3elDlTNjakaQnl3PA5sDg8mr/HHmApR1p372uxGbZDr+
UBwmKMYbwmCrcWJiZptzHJYGfdutFLpmwLkwqJc/fGsOV4m6XVWcvgqBb1hvdp0KdYu8p0ox75k5
zDHdJivtAh0elPksVoznb8mUU1McMcecyWirGA/VSGmI4l0CYWzW1psuxU8ER6dynOx5wr2zBrDZ
ghhXCUdWNOZs9j5hsj66NiEWlyvfQcQLH+Z40OU0Ln7fvfkPH+WO+m4X+doj22MW6k9eFLLUmnhh
49i+85SP2j/JhuJzToMRU9r3uGFzErW2PyyQyBXxGn8p4nEfvK0zZ3VgRuQyors8wF196SysziDr
yS+gSBFrToDwu9HIXlqh72HW+AebdDnjN/df7IhRzmUmUzp5/8fNcdDLgZq6Zj6/IC75ybiT+F38
rqtXGfuak+O9f7DU3W9RJmybeOSphVOqB5SskXuCQSFTqw2wFqo02Zcl2g7ZagBiUkOGAJwOxh5X
j+gKlhrji57NLGEaw6uMtklWsQBbWIgcG18xYyU2UqoFQLVuIDr3f6UhfkYGqNBObgk+idCBEsyi
xGZuLPGVSL8HUQuqflcpqVKq5LHqQE/mhOnq0iO48+h02hTJdy/ZMBx93NX/hE3wBGrTm+okSk83
RXE7GwW+dp2CuTNid+wi0dpQ6yQzx5TSF6MWJOIe9d3xX75HgN2KlEkVvKtP3WjSCN9egLMK5alY
RtuM9td1fYXOvwMT2TYQDGnK8HgE6CYZ7ZjdvpYadywqXUfrILcDyxMGDCtNgY4txz/eswk2HR9B
YCbAQw3GDXf+lSlzfOSYTGEhJpLCRETGA4e1mcsnUhO7cDyJ0DuY7pY0FASV1D++zCZUXYMN+eWq
JV67jr0ZJ6oW4nNjt1uW5KTxDEZyne7f9YM+TQA3Wig2jWcMywKutf/NhcK/4cjpwm7QhjNUkEBJ
UXs+zWKMh1uUmV4BWA732frWEZRIgE81DmIg/djTsbwGGWniYd0rKIk5ZcZ3b8q4miob3ZX/ZTgN
7Lbrz+aqGKqvaUgzPqj8+mTaPnLeuWeuWDUM07uQZUhRIgG1Mc5p1YTMzclsCJfriHC/oU6N3hhi
oO0H42KeyoafWfJCKN4ogz1aHro/7BPgEuI4+6cnb5X7YpiyugGNbalrTqUTPuD+NkNPGUlOwBCh
yMCKkhUdtWU3mP15dyNS8UrmA51ecj5lwe8HB595X20OpzRRYt/kqOIvd9zb76en1tN7XjK2+YyF
qpE+aY0ITn9Qq+eNL309m7kqEbvcf9ZE2xDpTlSB1/xbaVHpuA3UDyhSpXXgi4m7BC9rVhzhLpZl
RYPD4WYXTDXeJO6XiZuDfby3tJy2mvR5nccfDXj8ennwMUMJIulRSsoxnicdvVEWclhuL3ARatF4
nb4WpQjktMDQqwDeRlAOYE/OGAGmR7Fkn8jcyb3xLVhU7PHO+niPxUGOgWzlzyRri/rroeqAocpr
Mc6shku92zs/F1yfM7iCNzECOXv5a7JLXeLJElselegI1im9QJkift5i/G+U5KcYXDtJimHpC5Ik
OomOt8R2nDZ99LM7iFs/pqWwYbdZDtMMXqSBQJTPpL13gho0bGvm+EPVNPts4rP91EYGYvo/FjqX
qZdKoDkYoUeZ5q4TNx/lY4QQwOuaLYpoO/MR8dK7PA21ZQRTKCnm8gyzTxbLKGpToSE5sHYCfHKI
+qA/elFqwbN8l7Ry6M+/SPvqUJ3f44GVWexlI+uJydsO9u5UcV3XoRdOMDcfJHAO9mysDBr5+vmD
+jjuURDItDnQiT5EGeWNUI8Xo9G5R/n8ZCT2aOH7rHb/d0e88Grx9rZ4z7TjvGIPFDBWs4SA/M9z
hgy2YzIoqiTTlmGyv0WOkAB20FlWpvSYa4bsJFdGSnUrObFueULE1ueAq2qmUJsTZhcz8Jg7FUyl
nBL3Swidirpnx3jbljsJxAChcLy7FvcbM4cAart2XsxFyCQYbdMZBmeeIbwMfU6VzpfDHMPIITeq
XZL2T4mQUVpkF3YpCUzu0w62wZ0yQNBiCSqlcFZLq0LqEuPjTGRFrnWBZDebHeffTOvEWj9Ieh8q
r4rKik1DTAt5LnKQqFWmBqwPmZ7VLcQ6AsYk71C2qIunUCfeTO4iFpQ2tnqjUqfeLrIFFD9LAl60
4dm3UUSq4yCuzxOtj5SFEoLrWWBTBF9exxOBbD+wcZF6Zf2ly1LYLxL5WIlKUHkyZ/TYtDwE5mlf
8t4zLgRaq1lqaTsJDRsaqzcWQQ9QaL3W4/qHXEq5NfDR0oNuacMCWRkLZs2t1AwAYxfpJO7IlT23
1l9aJv1LvMz7UGnWyj+cxuGMMqPKbw9U5j55BnhL8aWoazaYdlAIK/su+1Sz9fYq5dHCq7DDpFqY
ykb9XULx1P2BTN89d1xZ41Alu1mVBN+ZPI1zk8oUpSipZAbYh3cmZgNGwr1S4y0d3I+Hqz30nSwY
OeL6uvxoFYiKDB8oAcyUWEepe40y/fkC5Z2ttVqk4VSoVqmE4r9I6NR8JZ/mQZYsnzab6LvppSOK
yf4WzVhNQQLI3H5md7bKHl5gsPfboN2pHfd2V4G5NWum5Ix9ePc3LD5pbtYLkOI9FPTY4F3pm5BM
il6gyABI8UIKY45QlrKBbH0NP2OMVH4QHWc873bXTk/AmKpC/SChCZtD7yvOHMx2EWMqcYbDLEky
4H1sfPKnZUrAUd8Aq3LRgrbCT4UX+ltzyLuBWIqUm7RXBBM6t0BG5feHbsgDkK1Um+PpIcUHS8Ca
4XQCBmgYMs7lyBswhtJE5hlji12xhteKo16RCp2tx6eZGGV7nzJ9+3m+SwLVcQqiLEGm+CENpbl8
uLVjqKFANA5EzgsOG6HZwcM0QCWTA8Sj4dmepZXIKDN019VcJMIZ76XvC7Vxe4t2GH2VcK83NzH8
vpKfMyubnNwEGEPzuAfpj6lEGCtLgg4EzZrNd3LIeYoQ1qgme+e7pIP2echZbv8sIAoyHvuGlIQ3
gQUYZDE5cpJvIup7MFNpfn7ufAQrhMuZbZtBrewkf0IOFlG4uHOYhocuPlBzZYnkO0XT6A+xw6C1
gjbMTG8B3lQKXqmzdG3A6uuSbFhO9YZjMBqD0jrIToZppCQ6UIAQsTsr8Vm7tBRIKODRKcyq8ldp
5nN9pj8UtvqXmqiXtyvLyYTaofRj0um93o2+Ue+iMAef+j+iSpY1/HFONboKRvPgHk4ovBpfHKym
Vzq4sFfkqqsrzwPnFwDMutc5qzy87Baw7oC5iNONXW+orKdHxRwO1Jd/WBHyEsX79LCz6gsyAKVy
dPbQwW510+kdZIJSV6jlbB5oL2Kd/9KQz2HMxL45Uggxn9y3conB9mWddiHwfNolwCXxHS3VGQvK
dey7x9T9BCvD7m2e7a4OdqT6iqoA402ihdISfDZh3Gc6m4mWT20GpzpmU4/PSR2BKqyjDBZBZ8Aa
AxcnpA1x6gOIhZlLB6GITUxL9rKZWM5A41hAzlijBCvNGZxxfYNzjWaYI25cU0Bb6W0IgH64aO2a
vS7HOWczlkmvofGgeu3Hro/D62hyjmj5EkBEvhmHgx+G8wernwinVHpfQbUYpXhSPeBSaaZlaiXB
fPx15jjRF2ewjFe/yjB+1FpgwR1G9RRD+jMJIp65Odz4htjFNx4H5x4DDWlHa1RuTdA5+VL/5iUN
ToGLjWXFi8DMYOy6Ru6oL8SqZ6vTMSk9WIRJuHybkwPkYsZ/Sid8Yc4vGsU4wmsZh7f/mnqGq3V6
2MrvmxIgRnKWpPbW65Jou+ArBBnHw6xH7HW2gRxhqUAQ+TRt7DqtYHk6iLX6SasHx40MHqXgDNnm
FUEqH2zX5hEoooZNOYl0qWKfoOdafgq+MACqdVKMDQd8QRXomMOm8DCy50X6rAtn4//pOk3qYuuU
k9f5qE5J9Y/JEyWrS+QxRm+37zllYXGWWFJJ8MsQ4XjVgM0APk3yzcSwpnfLk1PGzd8Lqh/2g6U7
zePs8wuXYjJxYE3uLZx5W9CLMngPIyIhAiqRiUtcUs1WGwtd74dwS48/nCs8cWJvrJoxzUnlCzJ3
p2aPwZx27oTakFbC3PFmgTPL7awVzp6S11k/T9APUZN7sLCoBN8l3W8lopdWnqtaU9L5LMCK8mXZ
MdkHHs66/RkM8i3N1A7RJbVDOXPk21jcKZT/mBtk3fu9cGrBXYO+11cUB2lz3F5LaUIiPDO+amhX
jYQ6Eoe4o9OY6ihN3MNvERMc1Bk13HRVYT0N11/iJHhEGP5yA1zzOF/BIITDT+Quwp2/Tq8ihMoh
fDWo/63B7/OB9rJoZpAQGDsdgGHT1B/P4E9woGJO/dFLJPrwq3IdTXbyACjyu7UKZBxwPpPoergt
2M+JkU8YRYo8g+b/I0BC5NJJYcGOIHOPci/DfqWTRxKrgbOzOLsAWe8wvvr2xPr0zUp7o02YD6jY
BLVdIgp4e5stjF+JCrJeb36gDqh4acVViidMFPqkjV6/teCtMwN1onIeX9vNmIs9WutiDkFBF3Hy
yzSl7v+rvGzDjOptJbZM6KEv1Kk13QlJxvle14doNy2mdBQV7JAhsHlQ7WmsmTJ2bley6sA9ctVg
9R6gWP7E6kyyrOI9KtLLjjE13oD/5pKSWUWvK94rJXrG1vZUZjZGStCnxXslovZPc+Q4tBooc3QL
RPO2/cY4AlASCIG3VKi9djwTwbC8WRoakIqOiSnwu4/41VA4HAlDmUcnP6TXQYiOZJj2xHMHSz3b
hZKWNCORwnHu+JUY4WfdiJ7GcfYig/rJ7+CMHOKFLi0YrJuqje3Ve59Oi5IsrlLky+zyDxCmS9DZ
qZdbpEeYTihv8pHDWqGCdgpSu67MiVij9gQuj/jfhZ9TDFVeMIb6me+TX1dOEcd19iOjrNrjm/Jw
H/S1LhoDhYKVoM5OLYapocKq1/AHDmiNCv+KUX/tvrFQ9TRhorz8tfxZMjRWLTTXQaPT1uQLa9pM
W5BcJhs+6+1PgcFHT/yCPbKs69XbGrXtBMU9nMiDCD7Z9exvRAAY1XLn0teyjfRTqRYmR9wEgsy4
g9lTxNW1IWQBxCHYRyDhC5aKLNvAdYr5ofnAbcFZOE3e5CGruhJ9P/nQZLVUX9h44F2mQadVvQNh
UQCcq2wvlHm0PZf4HcpB72KyY0IER+2BINmrN2ivDeEoDvIbWP2J+Pr3swP35Pgy0qOzT5ow8BVD
xHYuqR5hfluoyugy2NGE5AydNu1ons2i8nU+1GQUJNdS5WLgw7yvUMs8j9ifOWL4JHJDIeOVqLjY
gIIRJ1NUiOzUB7nNAPPrgClG63p+afuKFp9Sb8mJzBnLgQIJgzD++Xcx35FFvcDJXr+C2PAV3+lu
YaTzLarB5m6G7pMD+7niNJB7rviFpPZyC8mmlAgFWhneN5L0pwv+2Xu7YiqeGbyJEmiISuFRAfFt
Q/MHdOIWSsdeg3/5RZTaalp6IQl0ZUGzEF9liba+rtL6nIAOjVpyPRaRYwywarmh2HEyOx0hslgx
ru933euPRkWTQOAfZ4x3luSwyHCsTMlbVofhttgK6i+3w9tXv/JfiW7WhKi87jgcIhfb9s7jN9bj
d/IQbfo4QyJnH/7B1/CEkN/7NOmkRw59F1kxu8F0xzWYedvd982Q7obwAi37n5sW185n3F5boaRI
Uhm08ahE+7a07qDO917yUh8vm61CZ1/GiJbz6gUQ5/z7SjcG1gUGhi3fYOZ+pgHDR4R4jJlbQPjI
xN9EWZS7hqpHSXr8BOikeZeUW+blPCXNzss16qga1NijPqQXwXH69q94w3jKymVUw3TXHsrbyZgM
YhzSz6sjVLpyXSxLyjVH8Wap4M2HQGM3ZArv+MqtsxXVFJXf1QhMePG0hAggj1Pce2CrXgkvEUTZ
SJFrtn7Il7zFDiKDcJIKNYrLuhjugrUe9PYZjWIkN3YEpNZjns9fj5ploh6OuGausXGPBQXOz7D5
NSQuequliLF64+nTlfptgQfWXIoQSj39nmHBQHQTov/pnLLKnC2GDx5wcxVEgFUYtYjLVuX7GEnJ
tzTTMKWLz+8VfByY1xB6b9R9unvzT1VVn8B9MLVlMtdOxeaS+Ga1M4cwmKZ+YNZBNKxB+3M+DQ2W
QlQKIng72GdE2fY66X6RE/l9PS1Xv6XGYmDwSZXP4NlxcKuRQ6UHovMnUhxosVkuF+7MmufP0s/m
JnrgFqMPqeQmP/32taJxrEgpdPMfSKwrTDGC6eWOaWbQAwnYn/3BngI8ixQwveRPohyIZK96ZO9i
8wvTC4lzcZQtnelSvf2dLsa/YzubQUAxyVA69Rs4DIbiS8HwIF1cP4tAfGUVeF/kbuAaBMLS/hFf
+J9iFqEpI+srBmvze9hh11Q2MK2xJwyQ6gvunYlzQL1s/FPYI/T8wQIVMIdC+qfon05TlMcsFLIV
GIQJOC/DHWHjr81uB6gMOv0dtyBgABjCv3KNhrAj+seteaVlsrrzIvxjcoZUHdYXFuPcy7was7sz
J3vuYS8lUGn9wCnyqBiOuRvMPWxdtCxfGDBnJs8IlBjlt2AoUQR73M8fX0yM8IBqtF4EJjL0d9DG
cLMC4UgdQfE/1Alpw16li621S1HZ87lYaw/0wFKZGmTal920OYCZybuCbWmUQ85R+IFxoKSI5Lwq
l5pTZV3cQGimAz7KGyGexdz05DYkpcJZmmcuqwjmVuXWlSZ/SrfRVOLEDswrgbO2ruzo7SGbnnWr
0Av9jmovPgpV+8kbR4uyZBSImHiCz7uzJfoS0hqMIt3WETytswY67bxTH90rM5qPM1e3D9hecFQr
+uz4l+7KHuJyOrzsX6oTho2gCBZpJC2Rziu5C/QBEYTt976gHhz/KGPR7zBVIX6iL6Z0IidgvdBV
Wen3qnnvOYomDJRoF7LmCD7QW7gzBpX4QKVxuDP58wLDryxsNqE4D2lnc+dSh79tlL5fjGridBHd
vRmR/HiE0lqYQaRs9rcJONtVauyBAv5vj9yowznFVCYzlUvsZ77cha+pSISTtb0ni0CkLfKxIBDz
mTHUnAOuchqnRBHV9uMvOCCvMpjffcQ7wS7ElKlDLnXyzJeYsaxBkqmv+dGvP0fw0mT/3uYJeeQT
ep8cIP72ZiybYgx37Fhb1cCakA85hwlS6rY1I8VAjsj8Zg6XIFF4xTGY3rLkkW2mByIbnojidLBA
PCZIfsnGaob5SSgIzlbFbjJSdfaUI1C5/wuNjzWfvZlu9OCMD0Pyb+osdP17k5nMl56BpgTSFQx0
pYVoVKZouzzqloVJbDEE+tAtK42KsNYKfpg2lFuvhRVdaqk+3VbWKL+r9byU96E6dsoIEKcCkpUh
6rlHLv9hPNiEIdh7tAZLN+foVZAakEQMUJHwJMBrhGwOwO5AB42loi+OHIhP6uWE2NmSE/XJMhJy
WzrO973AIgxaxbutbciNICYGcRgrTTi40+YcZgBSZslQw1Dx+XJZTOgop9QfmZVhWBhb74Y0jSXz
zoQoEKvd0XOegCB0xLzK2TcKi7k1foLbj9ONx7JrRBETwdsPZT/9zBF21TVhIW1Tn0oQX3/GvypE
8dhNUF06kY78Vbto/8KWOoFf+9O6vgElWbyRwbhWha76pO8JzAuf7a1cBiEox+ayB4eMIQAgRM68
VQoaPUgDS3JiaXwWL47MnZGRyAL1KGAx0w+IKe8/aQEKuFBYAv0BpLvpCbCizC/294Qt0JD1YGOU
iQZrUCL4StBmMucYoH6BnhuOVVze4rItRwMpmuoDsVjfOE26ZTtPXPZht8Df+1jlT9sVEIAKTbTb
64gmnF6LkvGLVsJD6FeHUOAZDk1CxTgpSDiAHERx2CP9x5QQZRR/p3l7fTRz6QUWunxr4W/wXP25
8zbkWSXAy6rr8D0KKhmMKD0PhQ0dVLrXeevAkk/N0aV/xd0ecFTKtKvnfwndmQSgYLmmmfBGZTYp
VvZQMqVCaXBtwP2s+RYf0e0J2CKtQfCZ1/+gGEjzPnLexweh7XC40bCN9qr5H/wQKXxRCYQtiezu
JMAbv2zTp0KmOCB0Nm8jpAfVkVvxV+4JIySTlv9g+itlkDjuQT1qks6xuBbAVWVkxYNXDeIZsdXf
H1Eqn/tCawvDEAJ+2KHvLfPU9YZorPzkSRzYuT+v3LKLBnvBQXha4+O5+IGC8r2oa5syMH69NDSZ
0BlukKM69rHJwc+Vl1r2mT3efccwD3b1eu+0ru0Ll5q1985QiP6r8YfMmcnegpXkP8n1ys5cwZRj
2OENwkMGeGPF42+8Pfm3f6oIexKfeR+UFJI/VQvoPv+cbd3e82DefMpyuM4Nt8TIouphA69PXwH5
uANFRO/cwSXKlktFPzSwmP8Nnhvy336m4fRF/daYv9x19ss3b29/Ll0g7Jwx5dei0i8P7RUNaLC5
x1xkwOdi2hOZRIDbamy50yiPsT9am/KtDFmzbhilpbzHorsQZxtZcet28Xprf28iJe9ECFrMkeLZ
bmwMqVt1cLNB3PtzeTx1PtxIg3E+Lc6bBJSc8aBaYAorFIpqq8cH3W3y3zB43oF6AtZt5AZNWqmq
L6HPMQr9vyZuh0x1EttuTMJIEbBkV6j+FYwwXo2/rS/SFTJn8mJ415gt/hVz0R7XurIugG4e1NJ+
3/hAoDyEPNeeODYdbXoN1R7r6X6RiWUe8lzAl/xt3Ccg/aHKTpfD6fRbPnY2LoLFVX005crKlJtv
QunYitdsKH5Zhi23OnzyRa3E2CrlxOgK+SI3jNl/TLuKb4p3zVZQAhnVz4YVBN43M17GEXMwM3Ip
ywYQxyYgms7UcT6K7yHmx28NhBUzBMN2i0KMSehMme1ITGLyaQgHZl9wOUlhy4+6nCj4RRF4KNVA
6gF1mDNQgU10obAsUwlkX1OINCMCTBk8/SyhoqUGopqE9QaGL71vTDHMKWiDqGD3Yn+RXAs2ppWI
sqj15ApYu3rAn5ib9C2QzOWUpuGTvzRMjyDzYJ0C4IfWiXkw5X1YZzAwvEejAkjo3HOjbeM8I6og
80se912Mba+aNjhdnHcUz1yVjLala11k8qEIoMVDOri+ZCN/JvMZtZi27FyhaiDokYa4R28kdT7p
Yg3xs6sK83zObpFjph6pptuMAdhqvJpTfigNZKOxzAYRzX9A1Dw/Ipn3GE4JpLkpcrsI5zix5V48
5+EJwv5dNOTAeYsUpHjJFWKi5Qrk5BEHssMA+YmhBwWBGvP3C/crVgM2WXd1EgJNdHeODXhGq6+4
CuEUHMEON4F57E3OfyxqmhPdtlWlvAq3ivPtBunnXhJtoIKi9xqJGcsY1aBQMKyzELTyIHbEJaMY
qAxxcF16JI5MNgVks0xHy+6e7fY0ud2mD5hadmSE5IC/+vffRmkxUewRDHOgHUZ2lTLJK+dhlk1m
F8DBZ4YDasPT3h3Dhk2PV35EsiFfr7rFkX1YAt6wqaMFFbfVz3FXNzv22nGixx0gSfxtTO1DTsee
FgSfladWg26Y/qHeSStaA512NK/pAdEWE5rP8QyCsoVMOHYDF8oDY2+tLZNvH/ZA/1ALGq5pACqm
+seXxj/MCiQGj6SIqJ2SaQ2p7uCVFSAnjc5Z/aXTIMlxRWWhT1UWnp6GpCKzRprPT2iaPxnY9VM0
43DzpFQQN7n+NLXho3SO3oZEVvvKhNTywSVPX/Z51oz3B1kW6aZVLiO96K4IJ8V/FO4JJzgIMbhR
m1jf5aJTxOawLUR0eaU83cj+OuSdQRdHNHn1F9yxpnfNXFBiNTtXUjrtgFytLwT9YSO3jrh6hhmJ
J5io6PGVRLf2iHrwDY7+qfMzpsD2gC89y90e6WX9DOpUuMMZLd28HRT+wXF9aR9DhWXo7K+xQ2Eo
kafQypV33oL33FqXTR2T6akyD6yYYTKOShMFF4gQRhDyVMTGmRrUGX2NoYi37jfRPVaMeqvTI33E
vWyj+vDknTyhZhWmFdYeAD13WKG7dOJKIdMwwa58dlCPg0rMpobF1bGo87R2E6UjWk/dc/WsYv4U
8G6v1kFCzVJSVHC/y8uiGuprmeMl00zg9qk0e2Kytj/Quy7uFwgb85q/as0q++ot/qsGPOtbV1BF
LYvHac4wlORs7nzaAblRrCZ5yIwzLCYbUcjY9NCK6Kp4hvT9RJNesnELMnsktaexv48t1QwTiA/r
kWqSGpkeejLn5VdTk306224gD5FPIArG+mVRn1Y+xKC1MNnzHf3G/ecWbU05pVadp6Ro4na6GPTh
fUuAvlKl7lm/QWGwTcPMvl47oyw0vZtlBfbmHXASIiHfnIgkRuFgOlWKjw0wAUlbGUny03cU0vqq
zb+iOYGKhnqv3FmnxP+o7YnTNKgHHHGxRvslngQ5jXvA9sgxVhWEqYZ0PDo7xNI1g7o6yy+EPQE7
9Ue0DBB9BXItbqe8/AWO+pEHlBSFTJ7FuCLQos1/kMhhQ69dwQCOutoGFHH0Ry3F+rVqelFM+PaP
O1lFR8VO0KG3cz9mF+4QC+8MutSQ+rtLCoOi0H1/QMgox2WkdhRtgYGBP/1jRWg0VlrSwsLzOsDJ
ZETLY84NeFPKNKHpZBwUD4uqeFJnmUGl/A2Eo9wNzYExYIDJVWp2fOsy29fRgy3R0evZE6D2r7RN
tiDci1FMe5/yk0N3kMWjjiAqYPKhgW+ZhAQXNKxSXorbVw38r2ztiN1LPb6BMA05KRh+Jq2P3O25
9WNZ8fGjgccfpCbxdPkaeb4rMx5h2ctJuKAtBxh2EZL6FsfbOlnTrVuL8BXcLs617wnewreqvEVJ
Y7BFCib1PhhZwykxOMsivv7INGpIdmBpnUqUigrkgt6mYQYCHrlZmFyHldwTh52lBk5QYFZcI1pA
Agx2HZdj+z8P2jez0uD6Vawq7rquG3e/BsRiCfkMH4CeaJFCtbWc3pQWAtsYYb6Tpvl7gqH7+G5j
Qr0i0SGCuu6Xmqf5HOVppPrujIvGGXA/RiGro87sMm/d5tTvfz/4SDzxXZuvOyZoccuveJXRJ357
anzEaVmuwYFPO1trGW2YKXmmdkQPqOOJTWJH7m5suqY4TSFaQKtmqQN8yKEc1KOkfSMfXwTWPTCs
zbAuCpMsqD4qfcYctnUY4jvLm0ulwx+FCyhbVZjr8py66jdLzd6OpgMPjAnhWR6sNfDgI3AZNzEt
Eatm06dEOYHO8k+e2Z20lWuf0WB6NHMY6Pb4nJxEBZKhe4DIZBEwGpyHu5tJEEbCzWSzzh988nef
hv/1+cMGqmGY6s8qTYuVlXgyeFrK6RoEhy+Fk6ooh/sSE1TyPvSMumSbUhYmbiKASksYPnKrmY7q
GK4IJ/6VfljrgEW2088SGg5+ML5B0Xt5wy4oT+poiCPQ9uCpIfnx9DOGl6bIIMQJvMGiTK1b0UxE
jB/XssBq0eMW3pDXiXfzry6IXPXeFsXuqGf7tZxDm2jRFu5jvvtfVqtboJP1RitEpmKipnmbi+xv
1DUxsaKxV4CRLa3O29F1WksfCkawqSW4uSRbAjEobJhj6BQTmjGgkswacx2bb426Onx1GdI/7fpr
Y0CTYLA9IJrABUroXE/pC18Rs1nBHJ84mD9Pqcxcp+kBH4WJ48kZl/vudPVLO3actPxh6q/i0t+h
seNblVoCJU/EMRxb14Au9es3cl1mCW36nGcvJ8Eos7i2ApPALcIxlfCiBWlDYhNiEjzuCoIRjtju
npo9sgmEXKNC+tIbgeM8riiyy5kSobIlTunNyY+1D2q/GAjKyXaXSYl4BqRgfXYufC59pannrLCq
cu9mTIl8Kv22MUsIIXfU9ESmvtx6360pziY5675nTN+E+OZYPKSmKTDh509lVolYB7YLyX0UGuTy
zKHeonl0EdzbhyHAUX9jseobtEuTIcrWt3qsKmzXzyDMa/PdFXtlhrSmcr2XYICZr4M15ZnRETYk
2E937A1h6gPdwYRlfDhZFVHHyDHXbtpkng+2ZXsfqxET/kFLoXxD+ygkA3WmY+AuC3jdcDF8cD7C
w+wH9/mgZ65CVZTcoiko1TAcpk6rCktRNNvCS9qKi0FYhy/2xo3tznQ33C2ivXX2EnQLgTPqeGYG
UTEYbILGsbULKltoxU9Crq7f3IlpqKVn3n0k/wINqQWFu5YXPaS2EAz2AnfBoFqvndouA/qrpN1m
n9Yjz4dNnwPTwLmRO35o+47k/FE3Q8wfHWBDxD2UHZFvHn8mf+nTGJwKf1hFQ4ExMXFYjNY+tSMx
lGBgW6qqtbHf2mV69mSINGQM5t3piq0fvxLJAwzRXj3b5nFicatlI5dfQsel5YEpdPYD5mWEiFfF
plzEsGnxRkxsEHY9CXZy9tw2vAQtJzUi32tKysFyAJucWAedKmxisG6yIDWf2iTFTZLMsY0gPrC5
PSmzPNQUNfAs3q7pZFYExVcDvyLRHbhK9dRieiDsUgo/8DAZDByX8JW7U4xCMKC+ucUHn+iOoSZt
EP8H+U8iu6ROIibinUmcCuU1jnCVCivuPSPqed7tKSYXVOHnJnDhaJp3Zq94vpxvalTIC8INyR1w
wij0nzDlyzEEx/TRdWf16YPhKKdJbnPRIY4qDHBeaHxF86WvOampOjhdvoIG2Ye3QwTHjVdCGbQu
7S2ORbWgQyCpV5kfsu5EkYyXa2iP3EAguGBlG/LiF1LkG20v6jqacojRrH8g9xEJOLFbzijvYwd9
7388mLrSrbCavWjbm8VbDq7P7HccOSIgfe8om5CT1K/SB4N3KFDhwaZnK6Y1CkVE5+Albd0ZfCNh
5vD9EXcxoOm71kk0v76bZOBRkeOP2SFtxAS93ssrI2FPSCzatq7qhdVj/wj0YqFEypXDMQwJ4QPN
/ZahhyKSREDx31qvKNgxhTUKAxZK08/S9G761hK7VowZVkgS6JjmSihhRHIt5/bigMBwgucwyqCL
3mRxUk2YGOJSNtjurfJYhw8C3M0z2xyJAu943YsyYu/GjGqR4lGue6+ArkYKByPIlBfec9qghAb6
lBN3cSATaU9fTr6BAPToWkxyc0h5jWsAAf50Sil6fKGyeVAKtA2MPGZQNM07xVHMxaAzePGCSy8I
97aE7BIMJOgZ9DGxyMNtOPBGrqeqEzE+rBnOmYjFVvO/B0nBuU4ZzguY45P3R87qNR3jVcvmWktm
Ulp6nKgkyCcCljzAeCq/b7OM/0hAmqdxLa9Yi6dqwPlxa+1uIhsK//okzvonb5WAsfH5WZbnpwzy
GmxM1Ma3o+kmiTVCHe8RznQmROjfJwv9NhuKKWW6cnL8XLoIVFck/uVOVbeMpEwfiRITWynTDe2C
SFJzuqkKGn2CCEwBwVMk1BrNE+9FJBYl8uZWsZVtMszo/iU56hquUq9iV/cWKAgUUKxdHmFmCkjW
BbdI0t1DmlUhtsDDQlMrQh5h9AJQa0UUK0J43qIHKOUTEHtbM/8EBhRI1Cp0NcNd5kOgBJwi9vr3
Juz7XnGd2ReoaPLbl9psVEcol8mwNwnv+XWCU99khHGC1Kst8Hw2lRUdtH1trTslFr0hlpW4+1Nk
2qDYGTgFm4Gk88BPRxhy6rarVPiRQh4DyLnremDpVeFOjgJ4itdIdIwy3xXsWTTY8Av674f+vd0j
B3FAqdn2KkXqKyPOD+4mSWMrOiIMNuHXEZZGO/W21Q9NQuSF5h/gffwtkuw3w8Kl6xoYTWcQ3a+R
BoZyCp3OcQCeiHdojBEVjGBeR1pDDRjAf0vNjYDwJgBHCFSheO45O712k+FkFcIEK4naf56d0Sz4
TDjcxpIgfc+iIRLezFFPrBmAZqEiNU7pDIXczO2pp+kXlAWtgpmIt1e3CFq3gFHr3DpdSnMfc7OP
6OeWif2h/slQijBmyPux4nxsGz3YSAFJsJiYBLTiGOwvRt3V7J56BYc3F2X3TdXEHG6XVsbo436m
4sFeBehKrzDKTEINcmFVqCrl9wgGGNRVVWmv78tdnIeXB508LnJg+Yy8AAC2zYqaKh7KDBWSfeFN
fGX0QHijS9ISngLZo9wdNksDwrb76VZ3V6/GzLtWFHZQohiLI2IOq5nG3ewlXc42LO2mLDMNTatn
B2tIJNw7mSDWByBh8O8Xg0i3dltNc2p0zwOdZ/rP/snVFxDgE+uBxbcdtNMJNITmyGoh2T4OgOfb
75sp7VWClR+qGNc71c+H4qXHBeJYzHww0aWBShTrs9WC5EK3VRwbU4CnaXlUvNHRduPrdYLS8N7N
I4sn170Nzf57wSn+wc33/D7h3+VD4kXWvTAc7HA9CzwrmNUYoOFDFLgseDXAX0jwQ1UCvWqXXojc
3jDB8iRNXlrPFNQAp/JebfRmbf/WJPVjOS+gDKS6qC3UE9cc0zKVjjjkomb+kKU8vGeHG6wcjJTC
jQXLWzFYDA0JsYyKzaXbNtJ6PxcPOLwlIlexFMyHzkqWE17pZsL/Tp8gkbh3CwRdMmw0IDARHhCK
OKq7cvBjSEvNA0JN/Nnk+Q3ujx0gyMieEuaEQifNq8c1C3I6nBQ4WB7Elw2LD7LhWgyzOHPzCc8H
7899bc27p5Mche8QCHNOM26hVkKpxZUni08n8VD5DlFI1R3qw1OE4VpT1hd2jYoHxnhqlK+t7jNn
yb9peOSb6hb22By4j82KFjGYoxxQz9GWC5C1+MnydF4qMIkLcX/ykb+xpCRZ69hH4B2KW3orbbMK
HPveTcFOAUxrtllz9Jwd3dTxGMvVFJ+qIazAn/nZeaR3zCfqtngu5wIHBQxyDV3wZIfl1MJWR04s
thOT7dzKlkLO0ST/yDXcigCU+Q3YwuhzFDL6o84oSyu9cJiDGOayBdh5iGDKQo/wezSShG2fBxXD
UfLcxKUC1b0rbkdjsKValwE2SrLqsj6Yj9zXyZ1FV9kYaQO/UD8evMD4/a3o7HMH1Dt+UoLhLf4/
PJ8U4aHwGeNgM6vBxwInsDQ44eppzR4AmxzaHSdt1gWu3aoxuY33MS+Pi4Fx4FqbBbv6XOl+2/QB
8hxIzzOLETiDqiYyIcDtBa4uophl014sFgkNDCgJDfhiu/NICuCqfLdka5HCkegBNqjXyY3M3Cgu
xXS5znU64hhy2DJelSPsbETClBJzCecJfYWjzl0Eg9TNtrIE2+g/NoXPOLm1PcfUKHkLvuofljMH
4djys+IbXbWErADGp98pF3yGu27v3w2ZFeWTDxhmoiWIljGJg8oQ+Rp1v0x0ao2hVgsH2rAkGCqz
G4IH3K6c8pvtC0qncDVCqS5KhLLYO9tIRmhbniCH8uHqTtOyHAEWphvtaArC7M17XO5r3WGcWhdS
QEz69n+Rkj6vO5l0Wj5xmR+SEG8Pd4vENpT7cnN5TePtK2aiTH0xBTfqCkdMV0IVU03Eprbw5oj8
ByAkobIjBfHI7DkFXnr7Sh007PhFeulSqYpa+OkyBt6to5HkJww2yu5hSjMsiDS9I1xPN7ik9oIr
DvvAiw+sW2EXYEmdeLuf48rzItPan9C2VJbznZgskrHBsNWt0oj32SsZJSSVYRu116oIPkFOXNss
He8KFNkLUNxmSknfdMtg8Ntrqe4oKZ+VV1EH+DfRHQOs/EVM58xEu4e7i3ZhAuDgjKOlzjQupM+q
IPkPHK/5irtlXTYQl4spkdqJXvwW0crdTzxV66Gl5WJXEhXI+yUwHni53VhOnY7Z68mW9gWkM6D/
FDFTSzA16Rcq9xsRVz3we9/bmOjNj4psVQNDnq63uXH6KA2yYkkyA2Dc9NaEWLJoCF3jYDqnhg/5
d3iIL0TJuvfhgr7wp2jUaJyrDh/oIlU65UQWDs18mIC3ymzXvTMd0GQMx64c3YjivCSJt1aUq0+E
7sqqas+gV4088Tv19sAcLMaeAdOl2m1UL0HJesJbAp7JYRh7aEUwtEwc2doq3DgbTJUhaBCEVhaq
4pewel45LyE3Pt1AoCT5d6el7tCj/EsVHPP8LN9fs3O5GoeciuH4U1gpKMB4xjBXObwpHcmQzOmu
dqZN1gUnGvMgLKLidK5v6+nzX9ruFiAZTpqfhT8Q7nJPf2JQOvpd3oGvm3dMVNOXzwnSUR/qPKYG
sFZfJLPnUbpoiG3wJ9z2dkf9Fh37HTSHISKR4hl4fhlc4UXiJOh5R/qvdYkbB1BNgQy33fFV2FFR
99/Zc6S3MZ3BNiGtxmxLZNY5tzRZMJyqpQtZ5mYI5YJyxoG9ju0jIJBhTW5uqW8j7MjQ9fhWVPeL
1x8WykB6C4ovsLIKhIIDPVzteJDixgHO12UKImWJcJUWruix1GudBnV3vnXKMlnj46zDgsz6aR/8
rX2Z7FK9IqEWoL8audNOwZfUkarLqKbPQDEkrCfGDubi6XSslxW8Qdu/XOy1qFhht4NLh6g+fn9F
9OO6KabJyQudgTTrOJSyg121ATcMyTVrh0e+92QyDKiT9c+lXO53l36C2t2te2v8TvSbdI4uCE08
PrWj3+DThnhm3qaCcqzyQ0RYlKzu81oU+D2BOwYjjyMZj/dygF/xzdNEGJuwwplvk5DXoZkH6+DH
lNWQvDo+lUgChbmKjZCfbOJfgAt7MHsz8rDstDnrjlbHAby+4gy7Kia8Q83QKuYtUFyBDflpP/Bi
ZGDiyx1Wh9Piagb5E6k1JT2s7rGe33AAlC3FBbbnkJN45mROU0zMmsTo2PcoLeiOhGQauodOnH+i
87MYns6cBn/bugdrVzFRvU75pIjL61ULl09mvyzIjA2Y8jqH8/HlirdmNiHFb9A4oxtMAk6ej20C
OSUeHbeMADtS2F0H7XX56WaQbiwwVpvZilnxc034nQ3SA4fm2Sz6+859e5813IFbmSzfCGd9UxyK
TF3x715bnCRkGwp8TR5iRzBHn9vhP+xjfi9vCRrDXGeUbeAwjVtYOurUP+vhZwvl+h7zz2l/Ctmc
Ccrry/bC/wqptP1NfuS1F0y87ODEppYLgUw3hSiId0oxypSDeQ8hrb+j4wTdDA4u/b9Cljh+F970
OK02GhE1pBjN8cHLgJ+nZ38+yHICgaae4aLzgVfiHt7iTR5PSqQFBrOdeYN0bEVL8CR1Z7+MrEvS
4muTbBuzG7NF82eFpqisPUoM4zlhd3TdYJ8TzxFjS9iWi3q+IlD/fR46z868dJHbjDf2jwDN9I8x
Qj0vvS2v7UE5uy/hGNoPQxkXx05OHBJOzvcLV0O0fBLRXVoqesxK3SxxuLrC8AhJVSkAoRnepCHe
28JhdpcJjKMS9GSA7qDHy2/IDKsTeyj42RudLeWTu5S3VvRqD2Zq8oZrlK5O3jp2zYTl/IsH8Vpf
25/Ig2O2iW4wK1R2SZ9n4SjGV0NiSqrEONjv0zVcFpWCuNl3l1ZLzGwolPsW1lo+GnABoaffqJoL
8EM6CvIkyrLaRSRGlO6KXtvgguROUH/cU/SxvPwUdECo9GnfmGi2RFi/1YfCf2AGXV2tc3K5N7UQ
G1Pf13m3JSARQ8siEaEIS1qv81GJBEQtXQyfZwYZjQHg6145hWpvCB5nJAFvYM5CyJEjiGV+a3WM
MI8D5ncSqTOVVhVjd5FqHBEBMfQpNyWc6BSD9pGKRu3VFTQNczzIydZmuewxER/m6E2C2A4awWNx
QgTrAHdSHTD9GVuBswhqUu1d+5uabvEfTj23Hl3lrW5NlesydnRrYLJrJ+VjZwXCU5eTw+29gG87
zlLeyf1OCv3qoYdmTEabaVhTGZaD0KIPpXQCdFIGG6l078P7OLgB5cN10hL6OnSLoFfonlEXMaaQ
yp57ZrULilWOiN3of0LxHAG5H0D9vbhKNz+NzNkzAeN6zoPwQyhHXcyNZrwOityjQ9iT7nLGquFJ
d2m5990UUlH8S104r+nfOAn7L9DWS0vb/7D5vVTPFu2KG+l/PgKCiGMuJiaiS4OtgljtbqBA39aT
7Q7xem7ncETaATfsJ67Dc4GdVVlEJINPbUVM5/zSQYIJygo9iMBTmexKY8a+CKAvunUjzF6HsH+C
q3EvfGvNllCsrJ6jCRQgx9pcmQKz+vAWCLtYe2JnI3u+haZnDUbs/4/KJJyiGMAbYZy6twFuL3XC
2Z1r+H4k7FKPmaIkVHZAlMqehlDlHp6Qbi6yFbc//18pb+/t9eXZVPWxNm+FBS1XqqrLri179cUu
WwDKVQ+BU10jm9UKBUHE857TVxOm6d1YQFDx5C33UB8W82NEfUpbpHEYOer3tJF3EozuTk0G7o61
JbdN4QHFhWK4UHrQUbcUblasZBqYUEKqe/lrUmxQi/KEqv/gC11diIW1Ow+3YbpSASmnOzRdwZRl
GvhqUpzMaGr5Qqy4TBE+jMRo3uIUhXd7kvlMP4hZ6Dul2Axavz7afvHso+u7aq1bb+q7Cae+PFrC
9dMZyX4Aa6ymX5Gpo4wQzpiAFBKr0uS+bWTKkdqRqWR7HgVzqHA0yjmRrMUnyZ7HivkXd0iPDwYN
1zZNy4aKN/MjmwVYC+9i7v9TEnM8nlWyVzdCXlGQDG/4vOU7xvTliFN0wvxgaqFv1+CjMfhl6hsk
brIpK1VZmMEp6tbb05Jsqb8YXXI5A3kYpXShnV7D5o8PuZlMEI637lSEOcZX9J3j9hIgp0FxMdXT
6Yq1RY+BknkxNNdmcKJjU3EB0nFei3HC9qi96uP8IPxS5ZqD+DUxId4Jb0cEOE3Mhu3UXVA94oj5
WGFIF/GFJHfwFpqeREfeZIzZ8Ob11ctmYcP7ovLIgcDHZqkemiwv56AB3jDbNUR7oSZHKXgi4Dpc
CBFvsNKqip6jZp5eyxf/tofGYOpG+roKVTPAaWGv78rEZicfeEj6XYKotKbp51ZR0psJMweX+pPk
x89l0s8+TUFmMXix0TMWMF01ljGXLgra2aHGJMwuLQatPXIJyeIyg9cPW5S6gSHayM+DIuot3QHt
90PJ5WIZSMgZ+lVfAvcGrqdlBWZVoei7GDCHV4106R5/h5ZNyiqvC0pAzwIyUrkSUTr3U57hZol8
oweiX9/yFAfNX/8EU3pi0H4MH6KxJWwSh2+nJBgkhWmtcUo29vAW+wmtl6ytn0K39dM3LJXAjDnI
bgxFIvb11NWO+CUzBBiSMkAmkiORp9SSatZs0VuqPfyFbZb+A8nkaudA8q5S8fTRB8xmdts6vCOC
32SbKjky43fsDaReuRFMDdtZ7lVfmIKPi64TQ4FLZIaVtTh0ExAZztkU14+qkiHeqZANEoSCIANp
X7AxNMffdl8oYNardAZOPxwOwhZKjD5NUYL3nkjGZQMgJ9iRPHVoJg3t89qNhM6//N5HfmbZoQ0K
1qZyK/uDWPZFOUbBVFpSfJY6I7pJRxiMK4GSzMYAKA1FkkXr9Me5k0+7rCwJdECpI8lZKSyL5gQy
DV7+rPLyfvfZcW/aiMQRsF9DDMlvsk2z2YEzDv9Ytkwie2cYzgDdbhMmQYpQooxjJJLb2j3NwjrO
Kdloud152ka71WN8tcQFByyqqVURwS7ywScnZQYseFwdvIkmhYKXnaWEXx+YGqZQ2Wa1+6XraaVb
bxE3c1iunkeyGnEcwmE9CJYBAUDv3sTzQysejQnp7X8dAaSD0oaP6AWOKLyL+mPRjzV3cD8vXfQw
K4xmaTAEyuzztbRLqVkzL4JSUt2UK2Ooi7p09gz557IYhBMEoPEH0vk6fbigB2YOsWLbBulTyPM1
Ykg0McR2lOKPt57n/GvODKYdgPVxuGvVozMYhzMHvPcL98BIUBFXjN2TqBwRCGEIQPk/R6T86gxU
Is6/dlMNnr6QMvF18qSNvrT9WdzO+80TcgH8LZv0AmfiV7OATJPxvSV+iiS5FSKG+JZzpZ+4asCw
VuCMv3pm+WFp3s3qPvofBOhe8CnrHAfTiy2nUGdSJKFRkQr8P5vlGVRkg7QAq7CWCwg61UGzl5PR
n6aDepGT94nKSg96TTC4cy+wVQoaBuFXILgFcrUVqwL0IyvI+IWSnnnKE3t1k2KSO+jT7GNKhnHt
sc2Fhn4WhOwZjft3cYHICFMZprdFx4fAz2RbHEhie54EAd7Nc2f7TAZQdhC7lm4Ms18dBD3jG4Yx
chTT9AlyltjaO31GJyyynVRKTuRgmEJpBA/Tw7ojlYFMHxG5qnGwm5d9PdRgiEyhV7tA/9zlTntO
xezxixOQZ5lvXwj6Np32GDFinmh4mToOCbIxHU68NcjUfbihtmGNSTh+T7aXS7qv+ddDAUof4rpi
Rj0gu7j8SJ1TCk29XRRpGXHC9XdJ+fxtmB//jfObpsQZsGkCHHQs6rZHq91ZHaR88Sw0tvtYvt5y
zOezo4Goro6vP1tX3UYt0MW0pC/cKmao42RTTav3oPprt3evX/De5U80unNuE9S63ZWWCrXjB+bU
NILRYHJQd2pocDhraKj2BQ3qHdRSsjTV4XerQe+gk3v8wgFo28iSss4AncOxs8td1E0aOW2rogp6
Aq9EZPuDX02oneh9VIuvmymewOpGaUC+IrrqsKGWuEKiF7nlkPrGBgZYL2qLGZmjO9H/evMsDKc2
axj97EVx+VGF6eT5FGk/E74rYv9vAC/4Pzr/Ftz2tdEVLSnJSdhfiGFtw0jF4wXBpyEFZFIyOqcQ
QksF2km/bHHROgGYTOULQZ76OGDc2jqpMTFrhnsJrqFewZesfPVTIsC+MvPzDBjTAvPBQiw5BFcP
d3zv/98C9B8oyvHFHtmwVt2c2zE+z6DR+cpYEfhYw9JnZhIccbtrc4CWSYYeXuT8pxO4PZmWmPy6
Xz5szeB99A8DTKgW4+HwbOQkCicq3sm3hqh5xopie+TVdOGcFn3PPcljfhcwvLRHN/xxcWTh5XZ9
uEEbIrxAeoZ7NENmL6jGWA2hYC+prEEgMDRMLwKYXK8JisFdrxsyHhOFqppPQ6d8VTX+AbjL7dBV
/pTJJh9boMCmD6WZshHKL97WLHbN/Yet4Y8fGpqXHQ1wl2uMO8+Fpol3NTIPHP7FP9//0KgeJAMJ
5ZteRdyAmEk5KT39yhWgsj7YbdZll7MIoxjUrAoMzvKNZUdiQvTZstJSOk45icXlW0waLfa+SuaZ
1OloRRm4BG3ltCsfpIDYZlMS2eDQ5hO/H/EA0Mi8pa18t3WlEIZCq8ReCPT3sXMb/jQ7BvQz7j98
GQxMXpkZAxx94Iu+fyuQCVDojcx8s8iCmE76p1JwsGxSlpsYd1c7jcaZxHx694sN9meO8dhpEFFh
83sKW69ZzhioZ41YwHvvnirN7r3/pIK8XaD9cQbh2RugifvvIOvznRdpRQiL5qeL8k7VHsawerNX
UyZnumUOLG6GfZY44qTO+p3pV36gFaUUol3NtmxVBTMeTYPq5PEvbOuWE+EuzwEWHkMZCEO4lG14
2aDd7VutECPPU0ojzCi6gZPa0TYgelt6X0TgoGoVPyDA5qx6ktBTR2X6j3AMF3aH59pnqlwnRPGO
Z7w2CSgUhQ7jOm3q0pzylMvR6tO1z2w55KaWbZ0f2xNy4nTt5W0OcPAvcnxz0QZ42bbxBpeT2JYK
kY5zaDLld/Z949FoGIEzLvgMlBl21USmw+Bo5wWwlWc01wQ3wN+13jp1I3cEoKdLrOiTzeCwLCm4
HlutldSxvF5cT4dM59l9LPg7e+/HFJUKHHL16G+2kmDeLyDZTZqlpJ1i9CAnDVNkrs/YyWpzQu6B
tpD+PB5fgQH06bgup/yslWiMy+XXMr7wUZXpUIUmX4xAKoK7dTSp090QWbQPnr8cofBwvKIXPcDn
2XOSy3+EBwY2lX7lrXYsoJhuVrkR3rwLBTurYD5K60ZGU7dINJpY+sbh7SSDT342Bk/YbIOi2QsW
lvnw5xWyZMHAD0CVH+EI8I8y/80ONrdMdJ4Y5r7UfJf67E41eX727wi2gwHlz9uQNkmLm7VfgSfT
XPY6jwAu8rR+LYKDnlc5AVFz6U792K81HQAO9hHx1tj0y1H/DQLCjDTpFE6AWiJV/xG8P6FUIfkk
3yRQ4NfbRKF/STepnxwHxQGSmMIgHMK2n81qDdMBTrYnbRy2wNguQqXJSI9QZZ5VMl6RtGLs+fG7
6wqzwaGEfXpSDqB5F3VMLO7zIE7qQ8rJ0ow31ewMPPNQ+Z+AtRalRzcIWvxv1fa95QDGnWgQcN0i
pYVVZ9aFhPXdh+vc71V6wfHpKeri+GsMIE6UhA2N30AHUFOhsOFPctC7xZS2Wt5A0OzZxPz3vGGS
voerEepa34hc64coCbwo9aAUGy8njfqbEb541BHL3uQF/hi9mhBGHhcFHiOrCl/vJ5H5HMQZhx1I
RXIPT+QOyhu8UOiAPUqyc6Ji8dv6odS87AkdAxYoD001NeN6oqWeuHqN70bRNZpJlo2PM1IVHKUg
HvVwLZSYuRl7Er6Lp0GIniN444cE1iRsYz6Ba59R8zGeWgDLjIR9h1OAdL1ykJPl8yL7PdEtw23a
05N9svtnM7EBZf+dqM/URJSCdQFu+qFru2QLTSfgJzNdM1TvY0UgV6BYD6HITh3KRZz+ONvsJti+
25iXQuZ3x/NbTqQ1dsFeaLDrN7qyvrRhgrjU+9xm+42zN+cpQRDACkYCm/LRvyTKgTloUvsNDIid
H09NI9XpyCzOgBiPefbVDCYJ+veqLJjl2IgAvfDv8CN7xMwNO2S61cJB30+RsOk55ImLv2KIZlX8
afBBiOXfGPLW9szpBpFXnGjnExnfzY785zmldSz8zb4ZVGUVvJVfhwP3duVa3RhpOnjRXrsVwRo6
ScrkNmiiBHswtskZqJ8VZJyXAixlEQeUJGIQ4nIxU/rs0I+z9xvAMLRgjDxPR9p2r8fjQk7LT/t3
QNIy0QLzc9PjvrlU9gaRNWosKmgy5tKClVqHI37yGEc5xUnoiwdhM2AsaynUmDpheviJSv+EkJb+
uQKggmtDZlAUB5VhkQ7mTJgLx6Dx4nrMh25Hj9s1JWevAbSrcuaKqJlWP0UYL8feutks6wBUIqqk
Bxk7LhQNh+10z4MnaXiqJ89fjLZWgnQHMhQea4/Jf54szT6TgVXtUkRzfq9CivTBoxuCwB1cv5PC
iP2j1RKbKQ/+7zvkC6pN20BsSf3ndc2xYaeOV3F5jODnjsRLmCroxeCUeZSmAhPDBPVIhBIrCpFs
kSUsLKhVammF6/qMFXShGB9s4c+ByalxZxCOj7xbLSvkjRH1DKsFP1JuQklkHMW99MfIO4FLA3gC
d17e4ZE4ngyD/07OQPVGS1cazzfP21olZocZMW+aICGOWirmV50e2s3TaXucKAbxJvYniezXE9Im
7h1AI+T+2APkOTC7jaL2nl9Znqts3kU3ypoJ3IGtVtjW9QuI/Ad+wAasUg4vw3Yu2AbUvRgFXCyR
LTDU7N7uVeTKGOnww/3D3SJnptPhRRGvNAMvrN7coF/THeyKxZXFB9w8WQz93VmksCXbKLegoVXk
wh5CczDCCB2H1yb2Y+9+qejC/ru1bW/1Az8NVn8z5jyX9+k5Z/uXMEkvmkdJ6DGLC+aa2ILxmMwY
n0sGTn+/MPDslJDUO61zrXjbsaiZLqiNdMGIbqYWDAe8gz+iIQr7xab9dYZAopcrwlsJH3VLdvaR
dDIiIfa5MweJiL37Se7A3PbmpqMw9jgNwwf+SLZZPyZTIb8FDW5FcO++g6hR9j3xrxQS0k7+8Jrl
7FLokASXfpcjB3tqFgQpz5DJJb3u6D5Nx4NyPOabBxkGFNa2kYm6pxgBbfcwc2VyNL0A1Pkidcc+
nXHgZAk0LXgydyElgEzOUtOz5kWM8MVGkAwTlfDvohzhMuWkuROyuvTnuy+lbkfrq/02/MmNIxmL
g9SqmWBpSelcvy/A6Zl7qhFMwTEs4nkWts4qIj4rfJySR4Kfyn6txUCov48La5P1mnkN3hMTvS8s
Y1WqMhmcM8dN3i3x5m/9gZbWln5fEWc5Ym/r24K0jx9O4xs9CXx3hnl7DwLo3L2Y7B+PApkTsEUX
VHxYuyZnT/7ojNoLvv4J75geBlx6dYf44jqRu6A2VFfA28Qi5EfuAj6jW2PN3nIT+sjwM6t1EKFG
vyqRDBYLYVt/aLJaXbs1Pb84Srmmzc09iwx7lIfqVr1luAmRF5YO14AbEWcX3hPuvP+J27LPUnjA
Jk5Ijnz1Kn9kRYCNXZrvswZynBTpSe1m5k+yTlCdpwEUePajZZtg5o1rY3FYvHt2YQKbojcxRsCo
BrF114U5ApBJOdZtWsCb6ujzxpBGsGLYLsILFtx9Uh2IPVHml9SMQwc7pxbR1dUq7TV0SJcSIjpV
o1+CnXEh/I3je2wSF7HuQd1RX81R2sQzwczCmjDsWMhBGHTg0rUUk8g6dD7ILsd5iOhig9g7JhNX
31pGCVfDxrllOocka4lICu908gNAomHrAtU6V1/tyLajY+dcH448ItMvkOs0M+7zNsCgRIrT93CI
wwSwq03yNqDstCMzFnxpqDwqVy2FwUKJtazWW9+75ZEnssjA8JaRQmYN18Ze97uHm2zto9JbnaV+
sk71/TtuStY2TABBtGXESfqk+99ubIDm4F2UU+88Z9qGw78wPmn3W9E9XF7ryeqExLfyK9Ws4Lfz
iyg3S/tahjX4w0W/mtT8eGEzS0/KWXBm30JpY3tjCpfl1qmEW842iMaVkt5Q5hkH9bIytzUterWp
B+OWms1NbKHBczQdJcGj4/sfIA1mDgXk0dnjyouQQoBHL8O6qMmVxupD59pJPjI/edgKpZIM29Us
6gjw0mFs1OJJ+ab1zJDg95OfHjZ2s4jb9xNAdORa/8pUryLf4ulujIPkw4icmCIcH1mkahJefdzg
JbNTRnStS0/v42FbjofLPUYb8zhg4bznkgJAnFjIyqvvE1eQz8+wmfVlSpJU5e7CFJbvPZGzZAXh
4bAtY8KnUYiFNUVEtabuYyCgri3ujzY4ruyDyCfG0hM63KfqlXE4Lryeq/p4t1WD2YIlCVqHBp63
QQYP9e+IJy9YW9oYjHtlO4KHhyPtw8i6Atwqn8F3CgjQx08lnJG+cBtgSwIfeEbfuSUCFRi9QxQl
gr6+DdAsiIRvLgMfIRHnRopem6doa006XiPP8fP20oXEhHtkxk3PrH4N1w4KLiwXyTiPksifQ3CW
ZlKpXE+2RmhABOwAlqDIES7MQas4B9e0DTc2BcrLtWxwXr/zG8600CgGq2gZV5JmEdzj8ACe137C
A91H4QcZIhd+Jq6me/kUIhrOGh7iRPypI+bsAFv/n8fOle94JIdjOQWrWGk19ia8Tgxwq7nWzBuZ
mxoFpS5rTyXFdi55+OpkqRhE4jbKsLxZnk8hAP3z495Eyoad32vUzNwfwKJQnH0E46c5bA5W5kEB
MomA1yO9i+Au+//W1ooxk4jf/sWb/BWpiKjFBOxn2JRd2tiujK/LdhhrGMfzh8ECuwx98ILhHHKV
2IwuW+o7UOazprAKphW0Zz7hKfS4RuLpjFNYcj2yrQ7JhsAgwcqhdsAP1i9O4FZXH7YkaSEPOgOO
+FxYGe4RJeGMghrW/Z/w7drDfjri331HqiM5PM/Zxjq/mTMx0rt6Vm0sUoDGt2E4b30rjecDF464
UV249RoAeCrG2kctSKMxw4alLoq01nr0wBAfWuoLG6Fcs2bskr5wf3s05Ld3mJf2eV93I9T91Z/b
CaGfX1GKeTyfeXCrXDN6kbAGpo0aQRNQSTRh1C4RoHhcqSJIjdX48BNXgxAIuB8XiGuHHs6/+yjh
CAEoyqYDoFowNjvGZE1an1Kv1oxEykqATH7X3OcTKZNf0/O4GC15CaRu+83pFjp/FRGE5dJzqgHv
oMF/pQq3rDyriyVnLaEW4b8tu1QPoXgQzLZv4Akdqph5sWCDQOeeodNaKSvTwePJMYoJxKtVPkpM
VezLehGB3SUXVWlng0Ou8cmhSruA2CATEWgAs4kmUIFYZMkolNcWhFGKG8L+m81mYKHQF57vuuuv
U40lcraD0gEvO/EJWSMu2jXO09ISsxZswbPsEUP4Glmt4aP0Gxi1TGrGziikC2rfopfBSRecG/VB
C4yvuMfiUOFjsLqfcgCRTnfyU78e39HDX4wSZJblmslH0lTSOBN9LgTrmAgMb+O/FC3DSwk1buJP
S6s6Lw1m2ncPeXPylzg76tA0HzpMr7Sf0TaUA/+o2KYRIRV5QOj522dEFAlSyorGq4oLQ9xamSIA
WpaYcp9OTndUvnyRgBSQ9liVy6FXBKxwMb3AoH14qgqm7nBKiIbUfZD/7hiAGMX7BsL2lGxu08Im
2af3n5rwp9tnn4hF6hSeOBvpAJgBZbsWZdkvIMcU9gaeXYOFwz0Fmx+60YWi2xwweW0zsr892ogJ
m+M2b6MeDPPmuB6OR5sIKZ2hr7+89EthIbo1qa+dhx8NmETFTTUGDcTQooQHR3Z2krdQS57ajxnA
zGKpWqxMzdYRLz42iT04cxaUcGH8ArJ49es7vnPlSUl5XF+ACP3NLEwWUIGBoFJIPZJcRl9FqaBz
xTAoTYmQ4m5teBKYVP9K69bFB+4h/diUWtdkPqh+p9Khb8gmPxCKKBO9Ye98n9Bns8VhjiDThEdX
zU08I1Rdj5bbaM5HwfA3lwKbMkHSybaWrDii2JrtY13H3UvnnPM2IOnYoYg5rOGi2WZw5MtxBmE5
Z2kpeU2TrJWEmZFHzd766c3kpJiDDGuZmnUUtp66oZxbL2RoXu2n5Zyp3Ghat3uhxATHots0Rmoz
ZcWr5DjI/kGapfHq5ECBceVFWnPZAJRNDWtURNUOR+X87uIjKv2+JU5rt80dnqxrgyNc+SbMSMbt
uiUAnHhJKONWsjf6a969sFoKgVRsfk9dWyJkr2uT/Mg7CyHeYaquvRFQTYJp8tezXVROJJbP3+iS
GPebfgc8Z0gg4GhNeG0Qi0/Xr1MGWEwQn0Zu0H7daljTfhwthGKKs8EeFnBx03ETBSVV+CbcVZFc
zaE9xAwXSzKB/LTzPi4hFBUWanVgLSd4foGv79skIH7K8Kfp+WALSIukqhBp4dLm7wVnHz6yOPlQ
i9UxzWEMaT8nxDUP8u6X9Ya1X0jChM8kQMaDov57G8KAWoCA72QnTM5IFpQ1rF3wjf7u78s9JnYz
/RMFqfwDsBzvvx96RvzNEa7RfepSA2qjG7lTUTXOvivFMnMrXPzZOvATApHX247e/213ooPKjE9m
DhR5wvSqdw1ENWRurnTk0MlSbzkBevM9jy1p1nG//KNny5bF8QAmGWXiQbXNil7T5KMwreeRprg/
nmr26SiFeKhhQpfoia56IrzD8WpYTF1JGVXbI//B3KCeEL8VUsmwSjzBS5VNV3vvHpFEacFHoNvs
JQJ93c6Cx/MPiK+1ndPx87DS5CHjyunK1AtkeVES8OgnnZX/dtJa2+ilrPWjBXDKkvgUsX/UHihV
UFdGTUh9tl8HuhQ5fVRGbqv//Jok0RyXmcE7+FTA36I51esp0063d9d/NSLmqAFD7lfUP3A/3tcH
XH5XBMAjACI0C/GdBNBsmseq/2r6Cuc8DFYBcm3hfu4GFQwtISyDfWl4TKrQCiUECZZOuoCCE4HI
VW7udOvWT2FvFY/u/97b8BOpCb8v2m3Wn1hk29jrrk8FqquMfTY37fa4w0uElOm1hasP9UxM5HPe
eyCbJkbB8vsC8EnUcJf+5Y8+RlaSaazopsAoqKp0YvtSYPje8/lBn94kgY3Oqn2Jdwdzyr1rGNvn
EOmXVq42jf/pzBsSwlzdKhXJp2liGLnvuMeSkZJRzwX4JEnqRyE87pj9h5FO0tSe4Rpjth+rxVzH
N8eVOmTJ/cSd/cSYltWsUsS5IFeqQHH8meFFGMAUtv1ZpgxAo9f0gAwT+MMh74xxQzD5sHBqtW/8
I27o0/mdLFMitFFZE2zLWnUmYMiUxUTtwjynWvDQwR0lPSXgCg0lQprMLNrlk+j1Faoi/2Bbe5c2
KL/8b7SDbb0rqkgxr5EZmTYMBdYJoTKMEvxMkopXRqy0AG2Z4CtgPf1EvUSs20oN9VgtJkbCEX4W
s03YyHs3wQKCEyJlh9jgCnG/QhINmaYzyjw5t8ny66us8L0m8ep/snJxaEHugZCWBPsDW7nVUw+v
Bx88ZgMdRbJ5F+KvoCqTFUqvwZq3aR6qvZGPyEsHfyYK7+iabJxU6TIQ6CVnka/9n1IQYHhlKb2o
8993+owPinfJRn7J3SMc19hp7gFpdOD7XZ3g5PHDgulRhMAxlFxIMIHp/mBoN21H5ctpscfZ/KQH
4wqBDg+aRFrv3lvq6kxmxl/m+kxcjnyCadJfvKwL/R7hLvvHZplBqogmeRu7IEtTzhedqbUm2X8P
x2/Snjj0pRZDiNnEb3Ya4HsUkjlkBJ0hCkHAiZhDc6xv8lmESpRNi91QalD2cuJ5nWdkLpUuw3kQ
biwdnq803mkGCJbJUwJl6utu8VNQXhGqwiyY5ubCkylmLbMaLsvtiSzhx5lSBr5VKV6+4Cs8bqkS
yVEsQz91jKYtBwF4rQsLFmllyA1Jmf4DQBxo/H958Zt1mpg6R1pDsWj7qt9Ws5ku9pCSU/5GkJeB
IwKcf++Wj+O8A35WqRM4P45MK4wfj7EifCdt6PIxVZtqCSKDK23VamuVXl5J5hGf800gWXaS57Mk
yRiMVSHGt2RB41ZhSr9ojk8+/YgIOeuS54iSq1Vg4Tm8M798VcUx0QMfMxhJ6mcHeBU3C7kYgkJv
0sNDnE8qNu3e0lwjET9Dtk9syYLOx04OeKMVhAdGmINbOk23UgKvLL7tZMOd0FPGCNVlbuKWYcbQ
M7HMO4/+Wk6O1zwmV6O1q1UEqf+2zx8vlDDczg2YjXdh+aq/R+xgGucQ9mZ3pPl1wlFjTv8V/sO2
nSx1R4E9l+ZBOxgq85Ee1Ye8B661JVBWQew37dPZH0B9Df4X1O/glC3AsjCh6ry7TH2NDaj+aRL5
OUsclUE8Yo35EXreWkbhWAKOzyFC8Fnk5tpg9mWqbScVUSJTjDMltYRGOsOeYH6NSAWj7RTJ4wHe
quEH6eWt9Lh1yIpQ7ADdWhHLfqBLMlFYlSsww0sjz7B9cH7G/hrAI/vnCTdspWzIaBrdHuitjR0i
h7ofFXsK7Wgbl/iC1kMy/hWZAPBUbRS41T8PyW15Ahk7QDy6BmRLB1JqEa514cxwNkGK9jbI0pXB
xMccyydgBZ42JEfoTXv0WZvdZDeAAIOuJXyoyxMsFgmQ5umIzX116QiR5GsTVTe4G4UCQE01ZXwn
CjVX/QUwZ9V1wfAhtRBviim8b32qXduLLJc78cTQ9ltMiGzlf1IbUjzHtJaB7XfFjCe5VVytob0q
BWiVSeO9O/ztS9EmL57rzcl1dBndNi+eZbizjkJYj8Ws0np/tRdoc2q+B0BXwJJqUqpnvBfy3MKa
uFOoEPxDIo+qNJTfQYIcDU/Yo4UqTGaq8ST1tv6HsGsSg+MyeQWvetl5h7BbsmAYPGY5GRBUH6Ia
qH7Bz0bnrwyevrQAgB0bJzkt7u5hnSu2hr0rTmSl4qmZd5MSYo08/cd9CFjXVcis4Ajys3xN7/QZ
C3U4Z4BLZGkMMN80lvOrJN8qmkWbAjPypgj+LaBh3c2ROlkguyMVXlqSsDNjimTVrrYi6KKR/IMm
hUyrvHYKzfLrCw2Tuc7Q2LiULyngw0V/okxOkiYpoYUIZd7Kf07tgMUgFCldflQgMN8q5ahEGvh7
ZGxXFqFjufR55Hq7wTZI6gGlN7Mybnu5WqnUIy1cDe9051PZ8KiVmux5gZRY2WMFZdlW8vuCrRHd
VDwD8xTZ55ue7waRvz7Eg6REjZpw4ONqGK3x81hYBws5C1zu+wi27COOn+B/1tGeXpgcEzrzWuil
1JjOFGlQ03lf7RlYI/gMcN89rQOeufUViVc4VWv9s9zX5q+XmUnoVFXo5NdKTBSPFiMWfZ/Yn/Vb
brvFjcJPi1W8oOKMapm6tmuAob11J/MgdOPYaGBiMJs9EpkjO/gZHB2iLxKXd885WJ2p3j67kekV
0jELrfXsUhH4jT/O0sDHKXT95hi4vz05UixNiC0U+4WqcW+srWjpR8y0LdI5vzo3f9Tb5g4eFrxG
eIodanlNdI5Qw688jCzUWdIJXd6WNVRn0HsIVC+59cDbZ5CLUTCwJrM4pdNwnAbMVDAZcmRqtWCU
SOCYB7JS51TNrRthB8nB++VXCMXAQ+k46FO4AITbcpm5eBd2z5Ze3pVgfrFbBTWGOUCsweZ3/MM2
SZS7OLQJ6l6w0oxnqKgMuTE02aMt3LUNmL9TJImP+ixL3rGgaegldV1Dt8tWpRQ0NEQUKLdUx6Os
9vS2Ah/abTYidaonY/DXjorH/XYJY4foUZ8qDkaRoq+Tgmj99XSyhp10no2BnRyTUNBlI5y6YB0W
v97t8uVKrA4WicuOENNQKitJjKE55djWBFIDfLO4PnHujGiqT2+E7SXSUrCgRHe+6kyMueQvan76
fcvO5nyvuzDOjzU9GWMkDEyAZNau52bxJMMi4x7meuLS/virzROUFEqHSXFRJObnS2e3NYokpG3H
u/GwkKt/xA970CbpN0OrcUO8adL2WIvMiqc0AZryx5NPwM1c1DVh/4U6CR9hARBVyB3mUUeeJj3/
uszHBd0IBO+7HhoMnzHkhjkQqbijEDrKUEbWvIuci3OiHcKtvDhN+aGkHDJstkSWhFHaisYASqgq
yQIVw0O6H7X+G+N7BVVQBkGPnNSfi8775YEs+HbXJEJw8jqKeIaNmJTjry0GY2eAmAuyu5M0vPN3
D3r4fiDqV0ti8G3amSgq5Vm2+oHp11p9We+uVr5off4CbQOh9nSIyvsKYM2j7eYLIUi3iz5bhzwx
8OukKpbcgPOWljGKlm0w/9+eMJneyreVjif7+JqXL8TDVNrYzLGEuSqLKyqwhzscd5Nuuq+hE/5w
HJ1BLrFqZTGwG60iTDqgIaHDJqr753CObNHfIad0Mptj5zyZTYyfTQRIePFYYyk28IknHvtu15ZE
0Qa7WR5mnJ/r8ZhEFPnth/5fuX8n9O47ymLaeZw2LJYtY/md3RysCtRyC2xRAHmEr8ydhSLsl5Wh
MnHBBW1T/aNa35c+hK5NP0vvpOLvjqj51ko1qDENl1OJ/oq5o0WrG7Tv6SRfOgKbSi/0Qmlmy8yU
+m2MVigsf25vwLfPw3lrJiFZktR4dVNF5uHw42+ywkZzdYtG1XNuQZDpT/Ch5d9nkeeRPLi5lDRN
XAsq7zv3ioqVR1ifgIDKvhkf+xTdKx0m+us6Jir5jioVZe9EYaeW5t9x3ZoK/P5PHOgs0oBSg0dl
cUIH1yuElzQUPIeu1qaGTUpdAhsLT94pMhoyH8JYmzcr2hUSH88ahWokuOBCmj8yj9Y3+Brg6vZd
sX3um8rvxrkJBgpq/cSkgAapwwUeopoJ7arOzK2CKBQb+VxDak79jBTW/KdgoF8ozAPZ+ZnFvI+c
S29EzD2YFv6HpLQX+EMwiD59c6T3nXWMsKfFpEeAwRrtD3GPIS1wNMunWHocR3us1xXLkcNhT0wg
OTX8Hfgk0VbAZmj9dFCAE+WUeldAuQjAqHRb1TWJZMkDKgdb7COBi52WMzWm9VJngcQNEZmiwCbo
vTqklvu88JzN3gOdPXSRHOHtGEK8XsNX2Plx4GpPLoE9SKLV/dnGv4lWHQVXZ/yyTcdDkYsjhSMH
peRhn+BnFcdqjU3mkdUL5LY7MlFnFSYmbEJJvXYs70Lm8Rv5oMNHDguzzVeGxQVN/P/f37w08JIJ
twdmQj48yqkHStUw8D5GwCCF64qtF5z32JmaAbmaOtuDBW41jlh4ApbFABEZE/HifGD27Z9a3DGy
HRk/1fJBSBTylJZarfHoMoQL8naPyi4f0SHrFJR5gNRsk0X4LZ4D9WK40tw1/extjLZTzU3Hg5ZS
AtwilDVzWr0WjQpGf7p5ja01MdOXKnthqdapkQX9GzmwRZv5gK5bbrFOilWzueRt9vs3wkm0sNva
dp2D/c+APcLg7bK7DvdvH0w2MqfxP6FScbjnLrjNxXgbZ+vrZRGmMdmuR0tRJ1KnsVplDg0nAomy
8yfSYhmMfLiZ/givjEG90UYvo+vshUTz7VIyyv0YKHFjh8yUW7B1zeXRMdc7jPPHPAQ/CWNCbsPG
5mSPIIBExQ7Eiz4sieIaemqYNiIkNdmk4ivLTa8+vs01IIwgG5icE3nfa12ic1qDmjsU38BzWb4x
vdQ+dtvc3EFzg82slxvey2iYaxN8DZJbkmPsvNKh0+LE4dhcJ5EoC/UXENQ4mhmdqjMNtzX5foWi
wBeW/nRnCR2aBYDSCKc9/Yli0DsArxgsu6hnECwSurH5Z0grmdVBU1LaQf/BQm6Y9fgV+d+R1I/F
LGS4HwJxaODKVFXkkINakZmoKJr0F/ffm/GGXmzHcjBBqhFwDsAJb4ZpkVAR1sAhxPDG7LtM6Kib
bdLIiknRocVvOsm4FCRhKSvxwLItPxOqkGsbn5bEYGreNDbqBeII6mIZrxZT5D9sq9WEVKVQHOmI
POJsSJsLGxss/QJPxDSzU2hKO/oJmyWA4SghvUzYlurPgvBTQKbXsVm8zsAOgnnUL3kC81iYJ/Pc
S3EHzukAyyc6zGZbu5WckMnCeJzmIq7YR5NDAGac/vLyBVLL9xefZ0gKzeBl+3uQ/8FuQJvwIVOF
ZADFJxadgSGc7kArdTvBOImVsqIU+SIuSdWIs8dUF/SaS2aDWQ7QuEhh2/4Q/epo6YXnTLOPI4eL
YBkQlNLwmIZWwXojBRvC46TGzeiSe2kvajAbIUaOOJuRmDLJ+FGQkAo97nkRiHRjBTaPekwqKAgp
w5ey8p+MKzo+3J/wwr5lIhvgo+kZUSVmvLsUrAYW3S7t4djGf+xnWL1e8LXACHHcTQMad2Y1HUlx
hu9uI0clePnJ/QlWYgwIVoqdM4orkOxaaNlhEvV/c/hsdKPHNppx3+2kzbhDecrec51JvQsribUx
GmvCFMsNCClV87ntZdOkpERMDnqigRA5/EIRNX8ucLSLdraWP/Spm4OgdBvLtNHRxh1VqOzFHlCM
1jl9O/1lRVv8TrbIZFf9aoogrBUaatKEyDImIdDo0s9DeadUWAK6ADZFZnUD/6KpaIydvkykDfa8
niILt8ZAZbinbnRZF5hof5/j8CBH3SX4uMYoUcsZIAjTFGm0zuVDQjsT5gk3yqA8oIuYx0xjT5KV
vIAaWk/dtn9SFnqpfJFOFbRZNN3HlkwmztNSm01diJna28wgNEOhgeCuoxgTWLSVGfO3KM8x1NCG
nDcr9EZdrlyAi51l/LldoDg26p7B+EOgrv+0XImHAhqo4PC2PxAMgYhVLDBZR7scHo+3SWJyZv7n
My33O2MySPSRPoyYNH8m6AWMszwJkMbueOoLZIBVUKjon0IbLckqSeExG+Vm+gxhV2hln51I3hx8
Gc4iB0Jf1FKPmdlcwodisW9K+fJiBzg4KsHgfRU4APBeGiOP6rWAGw0fchySMe7rItioNIkV16VF
KRYrFmbC2SMOEozc3cPXLJEq/cm1R3SqRU1W1BJRhLpxuqiEETqPLNFtpwQH4xlGHqMAA7nM7TLB
kjTLrsqMjM0hkA6/pvMbdebTZiTerqTdDHoJX9Tdmwaw0Ws+hY6PLLL4NV0AvyKTMoe9msQ4tHvp
WuGqw5iAQK+M3HW/62syzw/nOTTpfnJ5C/ybCILx0PqwEy42sqU1g1RUl2lcHSr5yq3H6bvtd0nC
eScpBZqmwmuyhz7B1CYLmcZWL9biXA/no3MxO+x3BFKJvWfx6rAPw9W6dk0cfkfyC+/PmzeCRH6g
PB3e6CMXi0rUO5AYDgnfUIFkZ+acfr7GNa8GnBw461j75mERz99cOhBrC6NFvTBrqqm2WyauTdy/
0I7jl0ymI+lkN2e8ft0VNUqzAuTcKv6Is6372nbKHLGHmV3UAIihyZiKiMKo1R+oPiQFQKnNlKZp
iIAVbS7LrGDYBV71XNtUYvLZ26W7WAE8dP3LdCA2khDMcAMCmMZhc3fKOh/6AfZoJodyLpWHM0tD
r74qnC8ObD68UzG/qmbxAGTc0FYAmQVi6dXKwVwJKaGxE1uyqEMt4AW2/8odbKMPeVCsf0bDFWDn
i8PuHnFLckuRI3yOUtLRpZZFsLKe/UX1kQG0xLg6MhPuq4BC7mU4H2HMr4z8X5zswzhdH/Xqjp4Q
NeoUK853KrBjyitEDz5HLNDoTEh+BB6rKveImg+9YfOcYYAOfZSGnZYlj3N4pE+l+zWf2QW+p0d2
jNCMr8bo/9U+ETgvOXo/i82jg4sn1Vsj4aZNR67wIkqVW47OuXB25c1OGNdtfRX1d+uOXtGNnbo6
Gy1qlfh25OUG+c9XbAt48lq0Iu3/ocU822VJCCNKpzfkOzliNxaiJfscRccSqeAxXLcj8ufxyfZW
fw6iN6b2+x5H/4/nEFPpfYMx7XsS0gHWOMG88tNzA3u4vl35ljxxt8KoQfS/hJ5QSXriqpTFKDYq
OpUmjYN5SLWSUXMjNJCG7Gv8cbakaqbRaAorVwcKvWIZwyPQ7KBI/wZv0gONCtipyxl2TK2a83JQ
ASJXlACRt7d2u98mSF6RsAhjNLATEvx6ZCn40HjfWOHS37fETyKXL37T3x17zol7O2hDOm0mpcNR
TMDONqlC+Foj/wSl4q+WO15bF0boNkXh6GPFoOPOBTPdzKMYs+3Te3V/uv7UASXKrzZM/wuR0vR3
7b9zJf+vZE6/nIRpnN43IJc19LW+RYKn6oAKO6ZvMFTXKpzYmufN8lGy6jfB8rSLnPDxziacaUu0
duFHHi5krIKOmJKkVKbnDvIlv3WUIy0k/kygxwa9bFpxMZCiqKPmph0lcNVTxMmcApst98c0htHQ
Ow9e9uJl27mXXbp9N//QtUJZDc4nDlKrs9PZN7CURWtytnkeshKi230JJlPmcLvNIYR23Jeo2L8x
ekfvAsTgqWRldJ5mVrhYnxlxsk//NiYvkJTKvkisUf4eXPxSor+g4SaXHTjU8g5lhm2T63kwp+RB
i6v4KRw3MZNwwiuHBBSEe9EVC6cGRoxQO3fc7tMghiYGof5dZvn0HGc4PMAxY4/VlDrkC4q0XvNy
lVOxwtNnGwlfGmrSQLP4ds/8/YGfadCR5JRyE0Q5nEG+r6DZs03YZAUgseKyZ8BKGzzuIgfab/by
TuYQ1Bv7slVETKwao9TZW+rshuZCUvcPh1KiYv03JrKBNShss9a/gx6EsrmZvPXu2y7esSq0v4px
muGb5CpwtEt1SM7ZBshekeOb1Iv2JPis8+WXKO70WAxycy0C3YNyyRs/YLm76eSVFMufkpsSSC1P
azjysvEHX8SJFAZ4hspi5miRNvFvy3Z9Av6j8xjzsjWnEhYMcWIrfISey7Q1c/JkWLlXhvPv3eAj
nYmOqPdSvePwNRwFzuJujcHHbg1Ev5xu/4jWT6x7HOC5U/0s+GNHqeCC0OoZ/4psKk3V/DbF5oGZ
PtozhpndfsZiP5nRYAHQN+mW4fBHTsDgKWc/qd0ZfjogJgIBhfsV+D4sXMVQyM7gWctN6xS3mter
wQomga4qCs4KcsYglAwBMt+DAxnltz7fxAm9RYdTqItDy3FmwtLSCb4Go/SErdUUBuDY/+BfZUge
wP790vYdPJ9edzQGHHrGo/TA1U9O2Utgm90z3XTYHhCk3FsaVQZBSdjdqW1D+DyTVLNcZnYzcAX9
mGOpJhfNx8VRmmJj0Ykls15LOtf2ecMzZjq/PXg2Rg9/EUDVpAsNj5+FOolytzvtnoAIU3mXn5HB
HOFC8EFFY9h1XW9/S/F1G+UgCUggJNPienpMmnFC/wrejQ4WoUYkCGsEbb2M3G82BPCfd8FFEuTW
Ok0O0/CucVllf3ud3FwAxYoFiYEF/AncwlLGU2ym503wTEPbqdwROwDPJ32m7InFCh2UsRuP0v3c
eF65o2z88eYYSY/2ewvBnSuy5+PPYqRl3qslJbKiwO7fOMMdmaetpbfblFzmv9yv2PgKqqS+MtED
BCcnefmF/Wia6YXtPsU7t8yPHGUtBBrSQE+xPMljihoCy4jLjdptNRrcfBi+0E6WKAFDHIbTIyZR
ptCLofvTkW9hURAa2djTk6jZ0uKcCXbkzr6W7c07Em+q7V6Q7oulknx5r7on4wyTmKDtNIb+9LRZ
p1ctNZVVUjiPJrcmG/VvtkX2KEijAv1d93no1SS7/pfOcayv4Kxx39zJQhUAhQBmSDFxXVcsh0oD
XH26SEW7YK6ZnTuOnd7ILDVHV6BmKY4rstMEzclbB/Zy1AAVHlPJlpVO9xOyNTCTuxoJ0hNq4Ymh
vm/O7UFB0cfub0fhHPv7RC8LWM9g9aFaDdXAg1dqAx4lzsS2NmZ5VZz29hpsrjfwg8RjatlLRrrS
J/TtA7+YdzDPloB1UBWkzyb1JTAbyt0I5QQaXWsC/2HnWluFqdUlwG59NS4Gc+iEWV5cuG27BIAY
kjKD60mzc7pToROh764ztPVVnnHc2gQnFFr1ATXJJjw7kl616RBSudGdQQEx2i2KXWB4on1gEoTx
gLeh1iVI81B8Fz6IXyNTDDKrCOMRwbQPQfNZja/sCvwPb83A5zcf9eciB61l9CNlr4RJ1lkd5/Oz
oxJJfru2oxQK6IBKE7mwwLCn/eP712V+66N5z+OHVlToqFwUCL0tjqK7TSTYJIWqfrt7QBsEf6mc
6NLQWbLsZtz+ATdmMaLgGN/mgVHARIcwDKo3QZc29cxK4u5PZbrA/vLwmXMAJBRp6ZFHGDiyVGdJ
t5oI/ionw6BtL1hFzHPDVzFktEDKrAVuVTCJBbpWJa4DbVUVqTrdi2NbJrX4zJj4e9gJaADPGu/h
rtAk/fuhDV8+m4oEbH8waDdazpSCAariu0mDuFaojOYn8O4hR6Kez2TJQQyj6W3hTn7PxrGG4cCg
IWKuMVO25M8qmxzfY6xEQeQ0KNnGAdazsAbhL9oiA3LHVmurbFHNpQZy6mYhqS7AjMRSvjLDL1GE
HNrzV0KDm9nhV2LNu3ILp5UVz7FxbUvzLsiSiujNn5yozAsNJ0/tKqDORSVXWtfOadxAJAYADwNU
Q4fRSI0dYFeLw0CwAma5Ab+xhHBGSs/dy901ysz32F3FrVQ/ysf6Cc9sUFLJIu0zIe4o/28XBnjA
gi0Fimvz8yzU6YDUIy8KClUpP4xs+Q8Cb7YSFenHwZyiTwUcz4iXkkB+G1iHXZBgz9z8Hj/KkbNA
Fnu6i/g5rbKf1inOrcP5rGwQF+lANhvuuUC6zTRt90pg5T9EX1sr21vWoQo+MejFBJjQT23XSiUn
j3JMLVVkx3mUbQUQkdepA/hcqhlDzQbr5XnG+nZiRp5ZOFFirC7ybnqKakGI2i/01N7WR0tjwAjx
xAfd2opkwhzYtVhnt4NmK97DkHa9hPdRB0/Y87q3I9rviFkiAR76fmCz3cGZVYtiez6pUvmvAiiM
M+pzvvrCTmNaapV/lwYCLUkdXpgET0RCFuhZOpE/lRcjs3JnlFTB+fjAlIiQso4W2AYij4AWWsJg
8n4YvlF55UuhUHkt1Vc7wKRCjUbwJxoSWUYYEHq6zmkBjXgfVF7mmyJKBv5dHm4o9qaBNuaJq9Hh
Dv+mph4Yj2AfAAGl33D7MID7o609iwPYPT4fIoaVGH4DiCKPK4nNsubv+9HEFm1AnMZ5n61bZO1k
EdegLRqVG/HDxOZo8Y77o+uveJD9Fohxt/Jstn23TS5fZWWWCWlTywd62upukPaxuFsZyQRh9dBF
wc7qVI/5whXMHppMn4FTGxfdqTxV9RNPyoQ1ybOJGj2kkC5Kutj05nSTnka7Mvpq6WQ0qRcBdZ0e
oxYTYHNOmmXJ6Q4y4k51zqYDeJYzDoHdvJrRLld2dQ2vmGrhVm1EgTlSVISi8DPIxjiCHbQGShCQ
offof/A3g182l1MMERwDV0ZQafo/GfdF2FrDr6MHXzYOIMgYUKCaErSQ7RiwvHbFuLj+L/BEBUHN
UE5ODkmZ/Cd+jqKlRAfsAHNoKkGbvcFp/fVhk98L25dHpzaKoFkb/DF7CMaFBZu4e5Dkx0HbVD9j
t/fSvNi5bOOjgyuehxukbMyjAdTzIhZhurEte6tCuvmbwkD7eqk4+Cn1SA0HAfyvmDKA/PnUhDp1
6R8iaIHkk3cGL7wxoxbHnz3WRfylOQHq6IrPBU6bH8qLCyrMAEcoZCAIpQaTj3+MdhdOxTiR3uoG
Cd0VmsF38+To9vSjrzqI/LqKwR9zTbJzsT/S7KHnWDAT7cMUhWayAXHegPoC7YlrcllEaixBt5iB
JR1oS3nbEw3sKSFkGRAwHyw4dW9wCrWXVlQeedx47e5/ZWvZvgo392mgpKbmeF7QPy9XmXjEDllQ
g/fB4R5VnO0aPjox8ecZczi0wzd93usVwi/xQsfUq1KvM09MVH+mQZL3Lfzxg7gNzWJ+cZaPebgX
aZiBWjyI8aqne/YTtsMKk9ZzDu8ymguCeK9Dwg2oBCR2rth9wHANYEj9OCUHF0g6LE4H8FYMk5Qu
JTqXLjEDj7qP3taVUGtAjT2AEVSYEGDfDFIxGzCA2mr1QF6Md8/xiYkztk0VzpxkouxaXzaF5EQI
ZTR7WuLlYAf79tCF0+SQXJEBf4y0SGxkh8Y3b8B/YbrqHZgQLJkoCaqg5j2Vvi9OPauULUSkcTo9
Ukkjp+XoQw3qoYWE3wUsKOhc4VZQ2dNHDy1sVR+BnBsAdoNUhETAXF38zZD6TtOKaMlmxv5HtOxC
IHmFihOOkfNJ788uO6VadLAylqtfOKEmFoTDELRPghI01/ceD/kqIkDCpg7ADxTQTejfgCEhhU4P
JT+Tiz5N4j4MmX1jP22fQrrZoLjC582R8tTr4FvN0UqS/1SukKWEYMdTYUWIN9biW516dIPDQG2r
+j6abe2UM4dOGmRMlQNlSr6cE5dBPEu9YVo6q/gXrR91zLTbNMxWBRLb/UsWi9zRfVqaAOT5ex+M
XUYqa9uHCb+mW+Lm41PKyYYEsADy7CkF+pRlzNS+ZyhcwQmlXp+RiaGzzPjLnhDEaa9+nEU/VBRc
odweOFwU5yi86Usg68NT1E/ZuHdwgGfrFCqWGZYrl6yX7ym139f59OMc8om23Gw7IhiO3VypI+wK
YMNG1XvE1i+dglwMZoksUsostNpOwzefCWxdyvksYIalS0zdapiyBcIkzAeP6WUQ7RS9pXVP5q89
+R7mJHTIAKHS7hDcr5GbRf6Dl6nKPXCy98Cictlu3MguJYoukv4gCkaFB8xsF2CaaXvq1zco4pLF
q1RWnRRCYAtX0FQb7sY2jCc67O2OG/ku1lEqeSeCY7Kq7vZI2EvxRTnl8OgxF/AXRV62c0vkOR0w
KRIM+OjukC4fEXTIBfz1qVOP8ycNAH3SUzFymk9IIWZQN9LbaLS+S5a+GYSdpfml3BcoqpJt4tuh
cjY/shluKhgQdS++NPxbWTqtILK4hhLhVYXSwJOESlsc46JlIxMsvW0nWL3VR5hp7aTk5i2cVVnJ
4JcQa1tM0HoqxPGvsmtz2iiMgxSB+Hee64mzAlyIOD+6E1/cdwljhSimEXPsIBWMIISya1gZ0zkk
mHLhLHXQvz98R84sKZdSpAHHzVFfAaqo1ZYQksMqcjL2gPnjKEPdM7jvJHblCTuwDYm5ZfyKBZW/
FEhtTqTv9COIU4vu9NOnUbyEAxxFC5Ia92BAWUZ4JAeL3pgJ/xYHjSV/vpw4IJap5Zs9ZSOaasQ0
iJuSYGzwcRpFynA6zYZv2Dx9eHOBJiroewHZ5xgWaQVqHmjxqYqzxpGmwy6vtrMTIbQlUdxYJazp
pj5XMQaTHF5KvgW3PS7ZDRSoc4krhnyAiK4liUYY5tA5vneuYwCrlfMf7ozlphPiEi/0zw/ygIBn
sW9er0pDdkHfSR3hIVBFKGNtUoqjGbtzgYyAV3eSmJkqQr5WWMkMkaGRbYT/2uTVPfPFpm9Ok9Vs
G06BiTBiTB6RRvZdU3WQtEADfegTqaEhbQaDQJMz78IZVnC7ZttSikVvo+tuQr0qVxXH8RvQqwxP
B3tNJTPmmoAAPlZy9Bx1Xpg7dIouPamEUrCGe0SBejhNCHlO6yLhgWP+LQlQTKUrvuglRDcrF5B9
emwZ0YVxjjHWl/Hbmf7cWQgCOufPOEqd9ylAxVdwp4yDDVUJ0Mzc1T/pSZ6Ntj20T9x/4eJ28i6Z
GYyDTFWZ5VAhmpcfor/5cA0gV/LLD3wvuWxkihJEBL6yRLEXtwfLVLa/v8JZga4MkvPDprqLZO1V
tU5+l0yGvfZQrimODk+A41sSLJJkW4y2I7vljm5eh9y5gZLj3Izy19+0absDQGJ82IRb+y8tpJFE
tfWFz8YIsIfXv4U5ibWZAfiAD+vwjLQv1o+eAYsafrbn0ggsngVFCxokmjP9w5l5R0lkroFw7MBg
M3mbEMGxrVNzgVgfHC2ybwrO6l/US4kp6sqX3j0dU17TdrhgXv0+dmctUOFUORF2i6E6fvcOf54m
9mwaSfpBmfjZD6GSOoHJfGd4V42bID5JROMuJhNsEcQ/2sZTO6wbQqse91zS3zmCNW6fPV+qzF/3
RYaW3GZtucWIlToDUyRNt6wCqhd1h9IvybHNyZBxyB0R42Z0Hds/ZlukG5pC25y1chEKtbvc2+52
+JFhHMaeDTe9GrhoYk0HL1Zw1WmrBZjmjuFrncA+HtyHT+Wy+NYiSCfsXiW0+IAtGhajoWCx0zbt
fjchHFtcvDkfnzNuq1Tm3tEi/37pza+zBu2hfJJAGF72u9vbJriFV8uNW6bJdbcvgsY/F/a8y5E2
/kqMebq1EV1xiWta85WDqnWjqcjgY1IvTF0od52oTrciWv4kN0bJPyt1RAHKRL1//IjN1k8ped4Q
3eQKbjvD1dhJ2Hcr0Ro17iYr0U6SUnepjAUyf706rGfmZ2ZKVVRmyztt0r4VAnjtltZRz8xGepvk
yrwDPlV8x3O40fFqEWP54OTdr4AIgRmpNTQmcZDeBSOu1cor3qZy8C/MnsinUTxV2t5vl3FSHJvf
prHosMfznBnDKqlQOeG7OQe1C3wEyRVUmodPjTCiG7W8L7HLm71oqgX5rrU7fAm/lIAKWqrTuVzI
ki+xIiOeSM/u+JuwQOIlq+dWYqX2HysNR/6gU1df1JR09BuIwsqqjJBtGDo60Ud/G+yPM3t+oDp5
kTK1e/jded89XU8t6T3+Z3XtVaoqzcj42ZuIIyU48QFiKJhwEM2znG9rH4RfY/Evrp/NCxHcW7Wh
BXxOFawXu7VQWLSZ/zxMTnQXiAvL5O31pqh2Z7sxmIIVCznHgfUptA+7NwniLzBG7rhbXp4Pt08J
pa+b0DN0NHC/X1mqxXVQC4QEtmdKcrCfweu/OkJFfbJ5BDFi/12I3A+TTSHguoOkOApo2I4UcMqf
sYeptHtDY8UHNnZiK1N7UWb2yo1+nx/spmjz3TGVKuGDVb/WMeuuj0SzoAGdCb/k/hlJvczJc5ln
RPvnL4pSkxQ5+0ilHt97DYmvWcUSW8GJxkqT2Bvc3NORBrJk0cpoPFM9n+h7mR8DSBbRg8qQK9On
q9yvgRdQsCsionxBswtD0uA2Vv1RVrBhI7LeLGc0anVr5eRptCnx3H7Anb5vtrolp/8FtM4ZNIz5
yYziOnW3OzL1G4wTLvBii6QXkKzWH2W0ln013dJbDiObB7OyX1PqdyybBPlz26C/NM7YUcyJl385
+iDHaaKI03UUsXsAQQB2Ef7T7p5yO72cbkoPP7kf503+gWhw2iDwPz7Ul9nsTg5JpjRlRx2WVFST
P6+4a88DkuIt2yEEceXWrunlnDVpV2muBxaossHZNYpafiaT89d2pzizDa7AZHlpIQWllia3XrF7
QFfZEywcCqjZiolrUsqppQFDlL+L5ktoh2QCsrw7YlwCE/4alTqOq5guySfmw4H8HMlzuRXCRhjB
bqoVBqcPgBNk7IvdCIXTLiiQYWwYOUQgiwSbIvbuFwHGp1GG/fc/TuhUdZiHY687Y9G6HYY2oZiz
vMcuplUNO7T/hUAiPupthy+8i6J5VINx+pqL0xQTCr3873oe2jkMC3Chb3R8l+125N6cHf+q/cIw
Sa+LzNNfu0ZAYDrRIclgn+HME3FWodtPPdKo1BjtD/66vdlCe7olPUfNUZGR2WnuPC5SVxVmnspm
gQ0K6Tc0wl9g3skNmqF6PSEr/NYoGKUNF0mF70LcDBihQk3pDfohsOvV7/WjU7ZWpY4t8PN2k/6T
8buv8vzU7C6BiZcvzEYtc0tcJYv7BkglOTAODC/YeL7bgDtsUIjXLgRcfIuwalVHseGA1SiP0JU7
Ykce1zA2Gnp/z4Rmtv2enemGFMpsp0+dSX2Rp44OUpJLn2eEl9SggjUlMkNZoRGaRK22N5yJyMsW
tPNCx7sGoatFB/4btU9ua+DcLsZ4EiMRMe4FPgoh/x1OYhcm+p3PCdkzrEHamMWcFq5NDDRaL5b8
h/aQIPPgmVCqCaRe88JL1dhuzUvIQY/KsybdL4i36wVuSnffaubD84BkZRVrB0lyK3Yk1mY09jnG
Uzf06WLzTdBwTt9gEhTEwA6M918fyRWgEDHnnQbKcyCblmqn21k53O8lwK7jU0tby4ECMBQWOPvy
yx7isHnkfPKnyLxlVqpQkHguCoi+NugVvLYYGJO316Kem2HyyambjMvOc7WlUtxLhx7Vi+hlGl6Z
H/qLu2s/kPm5cmmEIr6Lgndbd8rs2oOIXG8np8vVpvNd8XUncJkL5yMGIzKmdrCkAz5I4kX1AMKK
GA78i9tZBunaJnz4xGklldgjPR0BXr/2oyXXFBsPskMozZiYVJRkX7VbgA21DIUeQOctNO5bGZmL
UGls+bCG47qByc420Lgu7fc4tFIQfCGmuA2wzII6v9570Co5a64oA7FYMvrkzlaQRBZ2dwysDgcI
q1HxhchHNsD8l73Y1clHJmg3ck5t9d3L3OpPtChHCk3vIB4qjxA64Cj2T7BHov07b0WFOI2ODJC3
IUU36UmFuc01gm01BGCr8KG2GPm8P0f3oyQbu6/ChLu1oavNkiCXDGYDoP3wNE0L+kovI0TaRYny
obPiEjNwZd0Z1+3Q2Aqvvbla9OUmk7xT9gFGLZYeDWSVWdMbJu2luS/R9L4Z/Z9SUmHk9N2iTdF8
aRpabZ2yAUfFI67QIwSVBZOh6CNoWEC2HCWQ77iZI9wA5U8QNwvnZabXvs7VQxKefqWvKZw7Mwoh
2qd2AdnPqEEemHOT5OmCjrTKbjjKrdcWE1KOV1og51gM5QB/0tYWzH988bb+sIpP0MCRvRKh7cDA
BfOcbw+r9PjXvZK8DeP2OKp1kPvkWOUxttgcasNpF33WWZv81dIjNfWSQQw+cq5vaHsa3URKhivG
FCYTWx1XKNEJU2/h9lSSU/tfiJk5NIoUn7dJ4DrNcYYhS7roQpRrRbMadumOIEFzrwP0PkBnxShJ
mU65d+GslbEVZVhQbQA3WaOlDZa26jgeImPKOp9J1WVsrPMbvvAnhY+wT2g1wkciJedRtbN1D6x/
9590aAf10Rb+GdTqSdwqxBQ7KoRf0X0Fo697BjdGKCIRYyLNrDZ0xMGCz39h72jPMG6ZlTS1KdUw
e/IKzWmL1ITN9zZSwDIoFQ/7522U9OUrfOmyHAZPN9UbCCzGxDgWZe4GuHOqpSIcLwPgV3aHEFe7
AQSht7C3psnIep1PJ+HuY4gpPpxYZqZv5KI540A+DLjrgHrdkmZ4GDt3WIHRA5O+OXnpof90tEWQ
yKB0waU0Amo6RSg4v4D+3x4XhRV0aSfsMSGHQW/68ks8S4yG8rdpb4juPmUTRjMz4rWQPK1mIq6Q
Het0wr0mlrysPsre9L1US/A5hYVkg1vHx9fxdflK6x2ADT8fPKjvAI/3ccNxQKvzcdA/boj0bOPs
Kix1uuVGUqv4fB+8TVZdTX2snM39nsaSUzYL2RgXkLuD1fEOPPnF1rVBsF8P42yuv9RQAnfxKAvL
R4DwYNxMv7ta9y0Kz/XTEoxE66LiCGVY9779i4lKKEY7togqPnw9lfM1Bq54nTrVabkvAq7GPgdZ
3RI7H6l6DHX4Grq9WJi/K9d9BptgSi+2Xi+g5LnquWq2X1F1q2ttCHssgPD7JevclMgokh4lVSUy
MPHI2ma86CA9sbBNz1+lzqRvXoSHQQFdfjXjyvTKm2UwCbVr4/vOOVvuPucLIIpS+nnk3ZpNoDr5
sXGoKYcMme8z7hkSbqVrTy9wE6WXoqbKPAObNG+YbUSwUwjdQCo2Brpd46wvPdAr/wqIw6bW3/IF
ZEnZnZcFP/UZKBghCfG5kHdEugqaqAo1+eSX9mvxFlUXCKkkLTXLQkjYuNiLStHyqJ4vzWnOGcbB
KdSdTw4AN6fyGkcyBmCc8bpQVdqCaW9VXrab+grFPx1noMFfDHM/9q9o/wOXe75goyq1Es9VBW5P
lfY/q6luOPChTcq/wdMdM3V8tRJTlV3fzpeUpTS+5Zn1aqQRGD9+ducukROPFqrSzF2VCyF1joaF
UIgXPPiGsO+CbqkeDwacQ5Q20+vX8/hczrBVj4+BMf28jdtZslXPk1yfVYp+BLPtg+OTTg3QoRgl
FeDkw+uEd76vriZNCjEDt5/UwS9STbIj6MIL/OT7KPuVIl5xMHlEGqbXQ4UdenNbfe4I26ofFOuP
SO4nBXRfLkAU0H0bUx8VoyHMVLsTuGoIDbttIMbez5xzh0+e2GFwEN/hGme+y/zKdqMFj6PrSuqr
enAnSWbrePQmvhhdkD2gI9wNSCH3bHsXRwAh4b9AJ5zTUT7IyQWjBE3+3cxG2VWkPYbbk46RfKN/
k7p9Qld8J9L/qji0sJk4GUbHarT4a/PdzvNJ5gaJA3UkVr/hVX4shHoqbLo2xdykGkXhsStTPGSB
JnDCoRpeP4w4Mmpk4UQu2rmf8mPfY/UOqhLzSxk1XMQsylQcbie8eULEtA4+70CiNgRFXjc4YTwW
BfvBPnv1pkPGFBSHSrDDPqIgcg6lvIEpoffvRHxmwDtewjXgjJ9Fg9QoQwDfPUDQlrcJlym2ZGlo
Ex8BH01xXLH96miiMd79JG5FpiyKZVSjScm4YoBesuL395MsfvAIcype8uGsEhUOJ9Jrqfzd3f3f
q+cy0gkz+arDIFgQNbgGmL1WJZYlMLQGjU9Y1iLA7A09CbJa3bCnRijYU+JFubfcCM4RU1f/CW7X
BtWMWG1urh0n4Bnbily8l3VnQYtQyA98lEpO8WLG066b0AwjPXVIAXxn1z7MQHEjI2tmsQ+PE5YX
OiIaPBq7pqCI/jWPkezXAFgpxUVlJ+ZecDSKb1+qJnEsHZy7MZnuboXb9KkrEx/D2j2YHVD2gEhQ
Q8KsslBLiH31Nwt5d3txBZ5JYFPRCps8gKSiGqTH/PhWwYj5sMQWJDTQNpR0p+MxASKhZHfspeYU
7UJkZi3yIAkGnnUxTWrDYWiu79g7sXzrTf6CsFLR0ybCrA1qQV38q6KBVxcJg3EKr+nfioV/EpYZ
vqdZbuLyxrfOAa1yeOTgiWHv3t4GPiXIQ3uYLmW7z2fr3utoslSPBhtNKaIuzjaHyiBR4NQ6dihr
Kc3zN9TqW6SxYWYMeWi7wbsd9Qjm23E3khPbkbXL2tzxe1BA2cymUPAnyG4NtG1/fIEeI1+9OBPF
Ph0tXYn6wt95qj49xKQiiJizPNo+Eh5dHjvjnybm5M+BbkT9bPyefeHZSxDKJ9LVwNF8VvDLifj/
IAwQrRfJOS68ia/9Zl4upYxUigwt5DYf0OjdgirbgekesN9moxin/5W9HpvG10/8eI03qdPMHoq6
1CfHfy9ScoYA8TI4cmY1IaI0iDuIziGMy18AL/la4XB7ReVpDdc9Xt4LmFNbTAOzffft9+PiRdD7
8XUArdJMytFZd4K0ymM059rxhGtotg4vTkODt79JkEGNbqIUc9M9P+bx4bgX5NkmZTxumya6tWE7
UPK2LK5dx8C5B8g0pAkfYkYaGpbnQicaGa9t7PPTSMkjxQNRZpmgXeyhgVWfrlMXa33VOQ0VzrL4
8CuZiSRkmxtf3DPSzP2BjprwUu0dendyALgzW3+D1VLtDWBIgUmwmozgSSxoE9x2+nV2nPKNsYPi
7H+i5SQ00+8uMKStV/uCM0M65ls5MLYWeRUzJe1N2EZaXzMtPwPR05Wd4dZ4fdmI0mIINDaiwjb5
CMNt+uzYVD8zBlrAx3/EDnuKVDWbH2eeLFCJdnKkVoh/+DeX+DR/smZv/w4pgblgu6NB6SUcAK5w
vK9eWKGkPos+Az9ghYKSbzShgb283Z7fKs7ExEeldQUwtwFXQNWzpnN7oAba1Z7HqqmiHo9n5Yw4
4nDuc1kLEqbxoyoJ4odL2gtIxpnXIOQ0hwZkM5GXvpgoNKHgmb+kRWvXqqarrZ+sAV/jG42PXo1Z
LMhPlGrxPmDEstvzbuEtADQu5xa0jJOQt3wRUAIO/OMaRnvaUygtuLF3MWxgMBsGSOXt0oWWxil+
OSzV/SHn1DfJ8xubqyScHSmsbwTcE+2UWB8kc8oc1i0cBwzYLix4DR0sNGCeyiJ9ktRR0oRpYyf2
2tQ8PHxmUCW6Q4DUSADX7qE64gm/ArkUE80wy++dCYGA7G3ZqY6PjKFBuZZv9oFBZy1I7bYXWIaz
S+caL5zQvKJmHkfsj7r+h4x4TOMY5BIPVFcnJ/ZmdwRG4l9xegW7MWp3T053sjf6X5hOze1T7yz/
hxfsJWjVl0KgHCQL/6rPpQJAU3gjX/T1nYEIkB1Xt+wHbe2KTRyIK2un5iPYj22JCbiwZljqq+N7
Wi0/FJr/Jtok/W+zRf90n2TJX7JTfYyDLoL+ygN2KznydIEiFgbCBcJsDnXbqUA0zD4kjCpfzZLE
TmIIokYw4olYq9RnW+XNaIjN9sw/HsMX9hcE+WXR0DCpFDdW9Lci1NouGiKI+FQcvnkHMQF1+iD8
IVFm2q92eRsOnNK33nBtX4xR6RgtGwyWxCR47tqxGDp1svKjtuLsqoQKxCUQTBMLQyirOCx9OAGC
KW+wskToCBmjiVQgJsYr325Ojwzp9Ftsu8cVqH86w4opQkWC1QC2DDnyP31uLVZo1ybrhKL0XfV3
njPTjO8zOIhUvqVBbDJ6eQkc41oPHmOzfYka85hTa3YwFOrcrVGAaxysR+IuPvfTyESLsrBypKIW
WEqVaiTTY+UirAURUUvHD7Yn6ej7aFcTkDa+/FBZnwZiA+REkQC9GrEqPE0riyuY6VZ7aPxfiEHR
qcC3wPACltFU3Xy4ZIy0kAC7jojjORjsv49Elh8x1XwtFJh06NUibJhSTenbMOGGc4LgvyohdMf0
h6H5dfoMO82WudYjtvz/YENVAURGoPGXws4PhRqGJhhkTB6r3e8NBSG48zbhDM6xDSPc7NxXw3xF
X3KI2jKYY9cOpLBl0Q3Wwfq+t3QNIHG3+mJe64q9jsh0cWz07mwMX3cwLH81ARMbD5vOQJ5olDYO
lKqxPH0SBmvwxBYNfiKw2KxWNvsw8m2en13BNGYULfEQeub4uxClzJCsZkbuuzTrZ8ghdmHr1C/H
fytJkfZCcRAYWtCvQtw0hJISm4XUlUYi68EGwU12HMZ2pD9Ggdr6n7fxiAmm1NskaSuDVDN4jlTm
q+R1MblNfYEhNfSallvW2UKeUKqd9hjJLC4XmMijXKX5aVeOSlw8bQBrpU+CkejAjWsvtgyqhSND
6RgxTnQdvF/VQ0MsdLPpi9R2IHeLpuL1qbiZWCLQKD5lpd4cidJCaV6l16Vy1E9qjnXLxcBL+qx8
2scFjDuFW+62+gXyThM86Qa9YEjjNqA8mekQ1bbbMLKrox89gaCyQrchvz4SRTBbuYNsSSWcEwke
Tz2EDQYwVUJXU+3W3/f6827DuP7qB0bH084z/JJOg5QVUMVniU13uD2CpA+zbx1UM/cPuHIjPMOs
p1tKVz52htEcK5ySKun8csLLI1a/63lbdPqegvRGY9hWHYYVI3Sihc3ih7cqdLL3fyep2Fa92646
sgjBDYHz3x//oFsaNdMVIBFVkw7SHkuTuUm2vepGqRiV+KpQnY4Nos70Phg4L3DIEVVrqf3ZzwU4
1SEwYNSXBtOC+QNcyZTFdMSF5hUxS9ctRli6n8w1F2/9y6HuBvfQn/ef586dnqKR0MNt7BD2gAO7
2nGv5KUEMpjwI4yuvPDkQYEBMptTq3MHdMpihs73fDbXdLJXM2UFPKgdlRdDiHKKuOE4pc3Ur86I
4DTHitXMF0f/IN3btkaleBr+6pvoVOFWUVBhA5I6xeUBxHSqCkuuBbneh8i/umYSEp4/THo9xR1w
6j2S0tPLpw6gpt4Ekd79wd0lAwYiKSYqa+amXWjmWjhanc+hC4dDYF+lf3y4OZ4K3+b7XKIMyNbH
GE2wUYVsIiwVeQ8JPSzhIqjkoCKQ97dTxQI1/57lsmgfNc05eXnc/h7jZzSFubXiIplUEB1P56mm
Iokp1YEu6OiwhVOMHaT2NXBViVASP6amKS/iH8c1oUvnxPvBUEpXhzMmznK0rbW+thekKUeVPMs9
fwb7F3pSjr4ZY5AQbrLsQ6EpC//FOUViSY9ehc+obIHjPxZ0TgVeRnFbh19klbCt6OluEZNAkKBZ
kxDyq8fczFAj8yZjcfZ60YCvAJpdWXuWszBGqjlrXewAQeaKxcP0ZB/5tRyGUFqJ7JQdPO4ZfK8K
glpcNPYbpV2/os8gNXP7ItCf5DvXLOQOKpOdptpNKQ1wI8oyKMy5MvRaefJXFZtqQ7Jmbkp3sWY+
Ts9ojet6U6oYil58RI7FD69RkqIySDVdRATMraqpLrdfLQ8Awh7wfL6E1AvTc7DffJgPiVNNhR8b
SQZHauhBrbTvEDcQh9CJufRsmpwJgAaVKV1rG3FsGJy8QxrC16kM5oIvoPX5qXpDjIcLh0PmcTH9
P7Hc9xtROA1hNAmm4kfEPJfw8WBpMMBsETB26duIJ542Fx1b8EMVzacV3FRJrmynFfVnGPzWyOuP
wCNHwDO7lFqvq9SNAqmqzK/1dEwPo8H+nS7oK7QbaiR2tE2IkLW4/WInxOhGCn3ARq7pxMLZ+WiA
SoMD6i7ww8LxSTGX3twyBHV13ygb7uW8ANrrSobW0k4qF7Ba7/JS24BVzsYu1vZ6j6vKBGyyXqEC
HxRYQmkbChif7IlC0+GiO1XSvnAXrEsjYJJjBz8tYZP8HZcZmVBcEnH9/+Qh+TqMIAiOH6fUy+rE
yhh9au2r+FU9oJBbOW26p+oraTmjk2YamR0pjL5CuclseHr2GBhnpbVSvhDnpjqGSEaZIMFCt9dX
3SYRjOwY6JLqfk8YzLoJGoPVs4TuAkKtWzqB+AKQEL7ZcXyPhMoidDabB/ZWWnEPMHym2JfwGOPD
nlWx/bhofDpOE6sBJSWt75u3u5IJuu1l+tbBVgxCu8DmKWSdkQrDVOKi5j8fKNjXVkXBkg3BhESN
CLhciPQGQTS24CFngwqSMTrUa4indaXpyEmiTDhR20heua7TrSbYqUAXiZk8Z8zVIVigxQCjxWp2
+iHlLY3YiMUxtH16wYTY4s59dNUO5+BD1P02GvMAOA+/pRcIQLFnSNQLBumCRXW/JEMb0LDZI/TK
vD3spfYd5TgkR0xmcjnn/FWae1mKgJiwcoXe13JScsfZsq5fDpT6Z8/Kz/NEr4wIYd+DRe1xyEX6
cBMB4FxpEzM2gfjroZTcQ2BbP2YDMwc9nWr0GdynFnoS66NC0R1qpZOAczjAdZdT+jZP5m+wPq4P
O9oB/B9k3fYBko/oGEQ8gBzmLVD0TBL9evDgs4rfBkl+72L567PCOqDgxjiUG86wUL3zlStNKU4D
Lu1lHBUYvO7JdidzGwmlUH6cQDQm4uWPJd+VB+jX7TCTQuvhrmN8k7czJN5pPpwLWiMzKmKCrKix
pleyiwGIJ9vf0gbWTDtPreDmn8TUfaF0Hslv4ntCrZpNRdVB+dZ+t4rsxfOMAR5mEZxkBICDzYDm
Lee4mSsw9wq3iU9HFGJ8HSxjt36iYCbMTvuuWWncJcXFupY0of1S1G30oefw+KZepaZY+pFEG1U7
VUgGoJKWvNa4rStn0laSSpnGEG9ighH/3SWt9Kv2UoTiEXb4CoZnHtEUZo+96cYw+1UnsBOfZafv
vPJzih08Rt8V5Xcd98py+iTG2+tBMPUqMCU58DA72NzLrsZS7HCGGm58/jQ8q7o8vF7HFX/7QBi9
X6uLpVBzJqo2a2E4gfesdhz02QaHirkZh9OmHAdT5EAwJoE+FbswIciJ0cQ7FNmR3z+t2quvMdB5
Cq2G4iOozhqzamuV3pPiyXqA8dVrhL+hm3BeSf2TNoP2/JUu6Q6ENZUIBFeH9IlwdHC8mSwiLeAG
Vvt5MZ894VUnuzIqhz8HLF3XpU7sCgrF9zXmzfeOAJA3TwkooDM+CJSQDuxco4Reo4uqCba3fRx7
SY3L4haj4EPFz8AsuMjN/Cqm0xc+8jfZYq2HEJ4paOSN5tiiZeBq03Qc/34dsO7RVUTF7NACNxj4
5l4hTMKx0I8+40jK+3m40etJzVsP8XvVxTrZmkDj7RF+Zn9CztGHw4E0z2gGbwCN7lxZsp6ajgVX
l3K5ZhnIkrHJWs0u/wWIaC8+RVG5A82K53lPo02lNcUnzt/f21mnmC1atMkgMKUrkujpgAa+UA/V
0sBgIEZLhSwVp8WHkZdTjz14gbanns6opbNBOU5vf5u/MSyBUmC+T8hZ+WM/ZPvZvFH775gFBcuo
7JYJd4TkeaUo6bz6CQyD0iRoztafsJJE0pT0/e5UpOa/dkLuMcFFmGS143pMv7hOD7J+PpN56Tq/
m4w1IF1c4ZayhpAEFziUXcSCqPjsU00CMsDUDDDUhmal3izYWacQBBeTESwVVeBl2vB53ULrjnqT
x79ZMWZJiq4+xAczZf8diQJZGnZ3QhvWI5q4X2M6dGkzuxmdaw006r6C2LFHcx7akCLU4rXOIvec
7AISUCqv1XDw3P5EVbgtwEGtnIQ6/Jq+gGBljniFVNuhpSGjlVj9fdyezqa0fbQIb/zQFoGOyuce
Z89Jbo4kXNf6Wi5/Z5oAZulx9Z0FSoz+CdEFnb3fGDbGYVRKrhXXuwMmYuoGJflddHxcvfNq6u5e
xjSiEZzFkRgzGOFyjI2DIa1sVDMLd2nSPiPYJovi4nGzyrdJJ9v5im+HV80rBs8zycQPyQQztm3v
bgDBjn9SPAJgqndcqhbLTZF0OCrrvuiaWhJLc1EF4etTRGcVw5WAPQNkLpspyEzazehZkeaTGE18
d4D6Rt8iowIZRnDT09QMYfXBYbpDiz/ObcInpg3iEYhnBlrBIf8l84df7nwpo0yGb2u4FDPn9qO6
z1jOM9tENWWG5Id7uqgbsqExwgQtmXqPOlLR2HdZbDsi4X466pOGOBxOW3iSkJU+tNcY1hJeC3fc
VD6HxRTlG4ZftVfQZUD7180emES4snONueto4VpNgFPVSjRBmQKNtWPLDg3Zl3FkTdUGX3rXnQ1D
d3SLB11e1CHetuyd4CWlA7mM90IOAd9893hw6NQMGcrd/eJdqvetvcx82I/86rU9mW+hoIUbwEit
0G0Eb8WiIyuzqt8muZ0F1LYqtvdyYDYRezbZN+U5B0vR01/T55heTOXRAdJAh+qyQ8MAEhXV241h
w7+xxezViBqZYx6O8WUg5Y3Q68UvmQjJvk22oJpWyQsKG/ale+Zo+6Bzav2VN3z5hyUdvdbiNSC3
lIohJaifybHBCXjKa1Koil3aRmnF0XJ/Q0sNqZKL8L8SPUDOoKIPy/nigZEQEPbVoazvpwB04qMY
CBEEQ0fnE9bz2dbqu3i1u93MB9Yc/RMf6mbv87fNnOfyKGc1HIObU6VVBqCEuRUI+ofgv5wEwi+Q
mF8Sw5IJvyJs2UsqbwsVsBzvf0lGff7cYA4urt2Qv52mnmAtKaWI/DtjojxuwoyaTBQDKL+1pbbl
cOsoRiA5fKuJYrekVR8wxBjzJi72KVDyvojeSm6e5j9VxThZTrD4QJAbrp5ttZ75x6jVBps4F8uu
W5CksH3F4bVQcMrGi66DpHcOLGWVJZXOJ2GlA90o9XvCb87d5IBE8OkwRqJjuNCD8NaQFqN0yLHx
7GEkRXbELgbqa/5PY1viPotpP8ePrUQp48l5pomq5+yIyZhDnVsmOKIYOCSD7LtbOIUrLmhVNpPu
Suzzz5/5jVEQDK2dweMq4Hfi5QN7Ap5hiP8XPqgDTWSqzJD9rF8nNYoI4UMaIacA4qgr2AS4G2+w
1OvtTUG/eNBFUMNbnX8qUWon0qFnlgHLS7NqNTwN2ZOUpzW+ZgMEFwmvrbVd4bliuxleWVrxqICZ
eHTMcpTkHh1Smz9smQ1IXnR0K4H6lfVPmiRc8F2VYopnlJyL7XuxPnOXEnT9+GyngqXk7fwhUpZ3
1RV1VHhLAI/zyx60+E4onLcBf3gWarjAzEmhuuchD31mPuxxi4e3pqGS+bDTvoqcjx/9VwTyHTjN
dnmDjCdHV1ciqJTLlGUiVUltdp2YeM9p9O2zdb+1nGlpiBNgd/DJ7NSHET3p09rpgSNYln9N6ohn
Et6axWdchILXBaAFCTooZk/Yt+mK3mJ0w8I8IRq/Y1J0PcSc+J1Juu56M23b1zWzoyH/NC4DF3/A
2rjXqv8lNoaafFQGpI01geb0NMFaMDf2/1AUJVGJvhyYFyBjWdSwXnLSCtHPYsED++K+aQWrlYTr
USTS1MgrrGjC1/zfLOuOmA11YiRnDV6x2D1+OzTRI5uJzTOUId2cMcMQWiaeNDmhCGAq9QMoDMp8
FoIpcf4PTiJPyoUzsWOZWKRSwE2uniDz30yP5zxk9u1SDSgMSAycl2H1g4p1VQlpSNnQ65gw9ZH8
9yLHulmHmzmR/+v3Vo0bRRqogNvPM0nyy8xxwojk22A8eVNRx0X3oDDNxXTJiJ+GgpiGOlNjb5Ss
tCT+3lOz+3npU583d7pTozXHoogQjAdja4X2bW8xYTYktFVk4rsFcejUWV/wz4iwSwsqFVdtl1CG
/LEF5SdpYN4QOqP+Rnm/2iCAOpAjlsuhKvQQFE2sZUvqC2aWVF5yeyFmGexNOb0zmgBTTfi0zMn9
oSuk9pL3VN8Ezma3MJrF0dWxH+DbyZ+Pk+gth2+AGOyrNgVhlMOHelp8mtM49f0ZrcAboS0taBpb
rFt9qWDRLcJ2OMILP7SMJvJ8QgquePlvPM3CvBkkA4tNoLjHgHEdBoOWYGRH+X7ggHbiPXpZGNt5
uwBgZTJECyZEeqXJlHNFBF+wP57mQ4al/hRuquuYaLQ19sb/lKHrOMqN0H8LjYrkC82TfxWKCpS2
I9wVzbDm9fXd/I1roYdkZJF/hefDKP2NdYDnO7Oy3OAAGZcQ0kpct/HMOWH17ThgnZ57b3N1V+2l
tvAt/82s742saw0nnM8vUryXoDbLKqSWGtTzqYgmYph9amO+3++zKfLsLL+0K/eeNKUBunAbScYx
j3kMblMo/OuizJiH3V/43CFtshHtjeng8HmYdNTa/ju8GqKsrJOqJhVRL1ECtTBSXEcUnmJy4vKC
S9tXOOoM5u1Yi/9ZZe2kLgl+K3lKYk1Lwmjc7xj2mqYw23yIxYIdPw54QHeorFvI/3vxjn1Uazm3
2mOLR96yygWKwUkFtxYZ2/2fVP8U6REzab6C60nstxyZgUyhiCOSPoEPiRbjJGxNSXqiCE/9xQRm
TIuLx1gZhthvUFIC9AjGFc8Zs/jnaKTMi8phrKHAdNJnAEkQH2XhV3yKCDGnWaa9eaMfxHk3Ij/j
lyAJFyoxVdko24m4qFf1MgnLXK3hkG1ZldK1H//lChSjiLZkDwbmN4TNTQ8nLTf9jOMPtUINLP2i
LHtVBNSflLbZTN7Saja30HFZhB8e9lKTOmBLeFxrZ/kALp7+07ypqgR7tfR25Ai/jN+XVKQFZTCJ
WJIWwis1oreTa0jz8keWKCPm5E43fnqEVmUh94jnITJhsKiF6LLQn18UtlcnnsmF6HqsMEhh2AEc
uaZCZ6NaSfjjWzARwKMHE7afXh0mDjxsyqBDwoO9oZz2LN2TT2q553rV/nev3KM+vK7FWHCv99l/
KicFbk6Rd1bCUrKbmuqPHVCmpxsv9CgU/KIN+DsWRir2PZ5Uh+TjMrF2162VVMnVzbHkwJe9oubm
W/njumX/q6CR67OnpEvw6Or8TpmJtQQQUlQTBbFgvGbmTFrEXnwPjLDT1KCnHuW0v2/Gd3+l8PXy
fKml5BEQfjRTWr0ijndLMIQAK2BYAxSsj5OmQhxHa7e0TwgwuuuGrsthOV2k8fQqFIpsRDl2fTff
qOeR7M+YWq/UHlR7LyBJow2yz0nKoUJgVXJ6XYZ7kHsE8Opl84dpZKXEDa8F08507QJdc51eMvVD
jQ0FXklIeVHPRSNeKIP3t+PpFsvp45hM/AASHdFSP44QNEmhf1gsDtGkfY1Nqy4jOrBZZ1T596pT
sY8669ULsO1V8ZZVPgkqxZr2oR++dIBboS7tnjC8gwQhGT3VbqHxt9O+4hlBkqCKqVEGgU1epo6X
kBn81pbYDde9W/dgZ8vBF0GywCkEQTsIPNzpvLzje7OTa2ogO81T8ngKmKZkR3CvuPboxcTfbU37
ohvDClZChGFEe7UgaQAkBn4D5jvAlaguBIOe15yU9SVuZ9bYkiERDh405xIi3txm4yQL0wlg2zsK
h04l1WC3p/bX/EC6qscGPpo+kniJuAdswvB10cVxTn+NSmVhMaIpHNIoUPoOxVEgaXasxuRBkOBq
2x6EOnWFaKpYAdHEq0QZzdC5dMxzDpyAuZ/UuGtLKB3lodgNXIHW1h3YyF+yo6CFlUS6P4y5UIKr
rCcWNQSUyCkBP2qZ4X//8Wf0CGVJEn9+nBgZGiTyGcMHa6PtM8iPRA07+2PP1nAGgf+aE/ZyMo+l
6xbOaGaIieUQpVb7z6kMeADYPA72LcBtS2bgL5CKr7w8x9G6s939m5ssNvF34aZJqecAktuW7HWv
b97s/Uxg3mq8rbOv711Smv5K1mbkHIs7zrpJRJpL0NKQRYR9iRavkOHi7YBlWPpdQa77IlRm9yTb
v8ROCv6HAuKDRqw6B/IvJaFRelqY9R/wZx7WHEKObcgBrsvbq79Vlk9vMnxv6uHGMXW7c11O3CnE
DlqxpohPyT73v8WoWCfMBQ+qXDVbTwDoZWqs34I5MQOuZu4KtXSWdkDhkh+VagWOx7r1ALZeyvgs
z0+zCr7Be7QXq04FQOHI+ufRzaIucYAchSpad8sU7pQG8JkMpTBbllxUgpEUElB/G4PK1HCFnqG7
upWXQUAlYLYSx24MoTG0BIIXOnyStTInIkQRJ0l7UZQzJlDNxHOIpjVGX0slw0oNI3zhPMn1bWZr
RrV4osdTzVsI2zfbzhilXqOERgr/xeEKvovqnbQD8xwcTKJ1Qe0lQ/GafAzVHLsbfdKUkerQAjp9
XWitVhZCQmKGoYxviuKhPoN3PWj30v137XRoUIjO6yz3snSOecoqOjQT/yEjkUpCgMmGMP8gUkcU
x6GKSJO2B+iYMgU9kJ0cY7ASdWniTDoyZdPNYCXC88CSStkwmBOsj2uE5k1ULV7Mb0avX8MMTJ4Q
QhBM6acFhcx2Jrp9ETg3gf88Q5/QPxAKKwloXU22LaLd92NiqxQHrEKBBkZ/LabVP12vAWjS4Y0G
qHZsoYg6S2K5VD1yPC+tgrbTGuE6scINPVHy24obIo0ab6eVofTBsjbzo0rpzGW0wI9B/DnWu/Vu
0Mu75xd/EMkzCsPLh3u4n5N60KKk8f5XT9yhkTAEumQCBIchPHClytyMTNjkuyvteZP6YTzgLuMc
OJWvGiUcBebpf1w/+Y25TgslVHalVV17RLVT8Ks62uzgcagRNCyTBCvh1FCzEauyE34WJ12VlNQ5
eEnPADSXFXAPYHFdJ/fLespTUROKRp5U2aXjsVXr0r/pnCJ2c0qKzYWEELE9/yoRtUC9Ep+dPCcf
KWyBc1BxP41+VA13BaKwwN4oeNHjUPZsEqggbCM0JARVOVBIFVEZvce25+grBwIBCtkX9iyIOL/O
sTwdivHqdN6fcxGAbOAoNLrY4uaYSlSveuY/RX3+HS9E0R7Q76o3i9GT+Gd2PYPaWHPXKG8SluTD
tRvt97rEcNt3fFkJDjR3haeygIuEYC9gBzUCh1vPRifqGzJnq9pBZA+RRKkAv3jbBWYRfVO/Qfno
65aN81Hv7ADidcsC9ZD4pmQHeeDGp5phHHbn8CK8PsYaoEMuBTkMwe2HWafeuH8mCmmy0oNL9Iyw
yYgbvHBE2R92CEmNZ8/NY2VlnK7usXgRh7SmruYWcnF+F1hqRzed3nEx8T58OKcQA9EH7lRfiSOi
SvvPFxqHyUXP5nSibipYUtMO64I+DufqbgpTRoi6Dv9gZVmQlHZL7p4fdu2zBbQI//8moMLmMXXq
yBzjh+GqtcBvK7YxVjdqXqs+Z60FWMrH2hV7g67Z3s492Ua3aslGIgPr+ugZxzHZkIQ1T4hyjVLU
36xUspikOPj2cvdloHO3fwfI283knKWG3hC1tea5CyG9JoumXNX12f0NCMzqKgY4Tcg0bk6IgiLR
6DvN+zyAjf28cwd9zUJ4SRHCyETp1EzTJq4KPBYu7SbOCIiSIKUqXzKIlmt/MIUc3u/tEKVJI3+U
K0bGAuJcp5gAqMqsFGwF0qP6R1wwM/LySaph/LPfYMV6rZYqu1okxAh1nkk8g5HN1CbbEio4yBeK
u9l+vHgoVTb7rV8nuCqy7iZTEb1oJXMBnDnwvrMxVKHhQ+hkZL6icKTUYksecBReD3ZRm5JvUTwB
L+VnbXfn5zxZyavGgeEc9zj0W3vfbEPS8RkNwCsCpkVWV3rYlZqCCLt4ySJdP1/2l389KaVRBYvt
YDiu0sJlrlPYJIqD0M0oukoe4ss6+Alv6KwMiDPzTsJ3o0ghE6xn0H5mNiCdPSRaogAq0H6rXAru
Bf6DxCQTVvQKPqm9rXoJC2hLymx4WPwBwdkSPSD9rBDamvGnR/2EpLee4wK7FFk0khQgfmy8oOj0
4TUG3vT6+wgRA2+ZaiabHsYpCXSGjUvDZNbFng/Vqla5n0DIameBGBabUclh0xKCOvw5XvETe8PR
N/B1AhKw52n7Fg+2SI14KJYJKd0kFdnmMB2zeqqrYYlc2OnJ0ChQdasqU63xaPLRCppfMQysaFrq
7sXrNe2LV59wAUwDMtaZJmOIXY4xty2SRrI34cjSz3kK2ST+qjCPoGnBWPuM13poyOw2aIGqW0v8
iULb3KYWcEmwwE3lsBFKJFFjXdnZ5188qg4yg2Tz19PuLvWHtFklyftI70UxQP4TlnQt9ip3cgYb
weGl/TdB3z+fzwo3Glh7z4x6zPrC1Bbvf934kjbIYVXME0PXk8Eut0ywsZi7f1ZcsXxYVhIpMMEx
OnO84Vpnql7zcpZzzi8Kz+Sf+U2Vuu7FJwBPb/dAQczVbuitaMosrkw1T/0mVr3jwjmuOIv0DRc6
ytMCDXVDb0fiDrEMOlqDiDXM50h9sG5RM735cMiR5VNUWPVckuYexGIxjIxhLZxtA2hRM0Fl59aJ
/lp7RB235dkLKTaN7L8UWd7c8+ke7EOyL6rBQO+xwispLZaFVLUtxkULZR6Q9xuO0lKMhxdGXiye
iW0yHDPJHVz6XN6wDGreGwKvtN6xdYzDwgguluTFkH/OF31TLbqq0L91DNebW2JkUyhs8irpv5mp
lfUEIFTEWbJr/KdDUpWcsfomoRhbbi0a+LKJmXabPyq8oHR9TdL62l54It+ueRx8i3URbfTrFTvH
ConrR0l98HKJL76DgdyNT7dKRrZXkR3vYSfJrKlt++Bq2lbIemryICf6bt3N0NVuDNrAzRXUgMJ7
d+CYSnXqJa8dFGoAZe+F1tUhbHN4qq6BjX3OZB7IFyCYSD/rc3wgPQuNZs4QL6cf1UGyV16XqQYS
6XBPyGCXYt8M8aCSxRLTOJsidGT5pH+nQToSBw40/r0yWKQY7AsaSoZTTwmX9QF4l/bNXTQfjkzX
n4UZVpzRYtg5V0XwPjo0IFfXa/Cl1gmIOM57bvikUnrrWCQEGXa5Va8lCq/lQ79PKlcUiFe2xjL0
3sQnDyYf5iLt1uLTEFOrRQ3xzad8aTfCuVABD+Bdzjrl5HqBQYRD8QeX90FDyXhGyNulMTTIvBw8
HbRSyV13Qg6myfP7aoPzRNjMBZDqc1iMff6oJi9dMlq7NUbWGAcYAlMoSKfT3YOHvFJpMrb6AdrQ
7JZBVDNiSRKgOPy0a3ZPvDZKT9dLoedfg8z2mTGxWiVBLrzsEjVL3Pkp7dkyXjIsGSiaVQOe0flp
kZQhIcfVQKiS7hlh/PqYsA/bCsfvgPgpsjHlR37XksqtAgtqm0YlscOp+hsEPr9R8+QdT0dcft4X
joiTgJSCLU95rXd2ICjSiJ8JmmCWOP9NPWVOsUDJCfhTdZ8GItq7tYXbB+cjyHUR076ZGdWFL9Wp
wDrWVeGWX63jXps2YU0kJ26ht7h/gFvpmaZACYvEEUhGZW1pXJLsmHfIyuwhwk2jIxai/PEf1NHF
7DcioTzCLqG7YNausfmYbzLrc85kaUw9LPoDLOQP6g2U5NI515A2gEBDdB4uCeX8pDmHKS+qqbYT
0TLtl26v9CNM97OVGFROFQ+sl6ozT7qwctJJPLEBXrsG5wa8z6iYMqYIhRCsdutXNfrvdt9Mm8jx
3xGotPTtmuu8RXZnRr59UeKx/FzbsJ3fEU9R/celC1wn2D4nWaaCI7Q3rJYqnPxVnCt6WyksyVhh
GZBrtaBuWMNIzyuaNhawkgfmwVcNWp8nXYavb3ostqkozf98keJGjstdKTgT4cJMYLcswLmYzzfK
AekHO2NbLBA5OmsPZw6tQ8JJkyp8RO8r2hZOPErhCX1bQXw/2gWOe/ZIg7gSnyQdR57UIZv6RO+E
3fRTIQoKL1rgm6FYRv5dvgAmUsIjNlGAYNC0jo4AVVGjmPkCaO5UO6yYC+wCPBACL9aA+ARujmFG
ijrybt1tNkwPdCzMapRFr/LFH8N/Dnax+t6fcHH/BZeGzCBW6scit3Z3jjTWY0OLQfBWY85/F30c
Q88u5OpMjpqVIIgUDL6W+Khbn2lpccke63VPFlHcTsCpGIrwhUEIwhisL3qYsrNLXAB6TqwzEO/2
r8DKMYlUMYnywla3K084+vXQXZvLL42DqEZfztLMyDtS0TMamVGDPWGfKEQSingpZ0XL4EwixXcl
JJcjnJ5lJfIjbfV/haZuaBwcckJh8puwxVl+5AAy5Fyzx46+Xg0E7Yv+n/BG8wOn/vmh5UKYM3UX
uYP5yCRc87POO0HGmgkMHnPAczqBRyA+vE0VvyS0zUA+R+2o2Y4Zy2+PHP5f+t8NAGxVE5m4VDY7
CKjzgA6M330lGWeRyet14o+WjJAFnMb3sE0TZgVZyZ9yDj6qHsbB3Ycs03jzx7ZMi4jxXCJoSqDB
4OXva01jdaZV1SZOhI32cUzFjR2YOTPt0RSOvkfFAutrc/22RDbHlXCcJOoipF5TqmfjciP/XVu9
Y1twPz4dg0nLV2JZXGr2jahFj6Ruwwi5T+atr9OUqyt1g4i9p/gJqibhekzodYBhi48a6vQ7v4oU
NyIw2efNPd5r/K1PFLRA8W87bRAESBl0p3NA1exel6Kw4xp9VXPS2xr07d5hHU6EdHCevPzGMZqZ
V1hltFxE647nRntMqo282NO+xcF12Su+1Lk3LipfyUJ/DvLrJFeBxR+mIjvaOu1YI2ktSpaFQGs8
WiHaOPwEqjrvFiMSRRR56yCTeDu7BssRG+Zj+l3DiTnviNiNhGP6TbPRAKYE01BX9nf5As8Be1Tc
Z5pQhw0mYRi5327QIERUsvxKi/yAxxGzchLqX89RppMUwstbhseXpTlhqkNtOpTkrXHSJ3WxcF1V
F1LeAXXzwBsha8m3mbJd8q2L49fhNsfmVYVhVEW6UZbM9S7CXpA+/UPTYP27aKHCcqcmOVNrgzHj
qRH83tyVG+VeXYfnax4pw9W6xlr2yoJSj7ARpuWJj3WXS1AehbzQoqlElGQscbXLBT2uB+l+LBaC
S892S7RT7jjJzVMW9P/F9QAJIsuCc9pgmpnO8pl6nBq4AQciIogxzHcwTg2vBglILSj5yNaYlnRx
9lWVE8hTeokhpOHScubDGCgWGmO6bI2UWpuAO3PIhSuAn+1muf1g7zzih/QyCFv88nf7aXjGGYjO
FvpCl6t3jgyZNUqK9DzRujN02aAwC1qDAdLVLjyN2xptH95xTwtCQJL/PC407tGYRwRKIM3SzYlO
z569xqSIoCJ5m1NNp5xkuNS1hB+j+924ec1kKDx7gvv7LrRowuqkJDAD8nlzNBlY3y3w0a6f6oZs
ukEbzOyWwSgUE7gYBcWunp7/b8RfIYoqwiqAAwn6QDcOdONiQbFIAZImir6ChlMjOQ1LHybv2sv6
vdYzSmO9Djo2ToFlexcjEigjNDkGWfRUA8YcDZJlEHxKNsplqphaVJiMwAgDrPJtdiRLSs8V/2m2
QJ7DjHP9/bOBK9lFapqYJbSveRiOM84Xo/Zu27wUU14OyH1RV4LeHJ7gfQANP5VNO7TXbs5J7hm2
zorsafiLVhFD6jInrw8dlh7uj3JXlIpqXYanxRP2GcAdIpER/e+3xT7SzEYCP1ZUv2+jNLfKu5Dg
SDC+p2kwyARrPyenRlrr1fb2FSUcMRUV1q4K7DIScabGaSflY/MbIiKPN7cMxPxprihGU3Ot+oYI
lc1ZPIgzlkxUUFDJ0vjPyW2yUYbmnkP4sO7Ut/MYZq+yWWoiVCTEAubV2jDBLuA0TQN5FTGISnjh
Mjo+rLE98DPH9sTXaxarjLsLjkXQ7lfArFSX/5VlOB8RFGoy+i/fhnkTrEu5doatUAWN9QPZkoCM
Hp3yQAi+ThbY9JOpYOgPA3uBQY3sk/t1qLhEEJuLlji8fmM8dU8Ca0Jx5BqoOlh+iVhmsaz85rHU
rzwOBdB+Rw3qcAzRWtoZCV+NVmBWbtSUjBd7UxUjs2FHmuzpbFsUm90+bCgUykxsRhi4++0+Omy5
f7tNA7q8SK9hKNMCUmCzX54ewNd9ZQEGeWvta5lKL4YFXK5eEai+oXo0YUQgoFaNhUKCXbCWlM7l
Yx665St0/2T0sL6UeIKbn8rPut11QMzScrRfWmNPr9UgW6PxkjeLSHLL0Bk1h69lARZZ4vW4cqzf
5OaGlGruxJ/IotR2EQhTrSyQwFkX6o2dUdwVsFIYZQMJ+Kx53ipFgYay9MKNso10furA8aGP5CS4
XQig5GU6Gimit2jb9kYttWOhTDy+bU/MKVQccIzDH+0s0IeAOjRGLPM7THYfjozIZxGdjPEl3iC8
H3C8p6cI6tsYq+/hnoy+F4Bxvf9dp+tJtJ3NNoJI+C9FgwQ3agMheq8GF7fCfHEq1mKJa5STeqxE
1la0B7IGkeWn218x1Jbij85TPubYe3KuPrcLdPrW2cm+7oJNb12v6aX71PkibEbfCrwiBTlUJOHZ
egsxATewNfjb4ZwwwxUk59jMLNsN6zzv0nkkSZkMGk7Hc/Njzt1Oox5iOFnLXBMiicq+vKXhnK3a
QyJRzhnlMV27iqukh5DDr/Y2yU/wGJI+ZBrxhhpl7zrbAfPRNGWzVfqMd/04ytEzNM0TYdprydWC
FCMyq692vfq9PCK4H39E2qiKGOI7Atwedw+/mgXv+MpyQ0tpfHJ11jxTPSg0eYWj/kieBqliRHFf
5HdX+uKu6/WASLKrThwa5KdVI398413xgQhh8mQJN8qWibu351u3+AwIFGhkNm3mBZS+ljPibO7r
FzP6ltM0wZiMaxj39oSnLuf6qIyThRZI3BrEwq/08m4DjyUNMzavJmQsJ6OKxKIXccOTljONbe6b
4ejLmZhuZbDS9WRn+Tk6+d5OmEhE2OQdlavDcldbXWneIOimS4vnmbuDK43OJxubv5o+lTTCikVn
OUBvqpBRupD3TSE0oco27WEnNceMDbfE4TzlW895LWJYujIoH/VqcNZwNI7ghbyF4G6dwV/on0Bw
ZwWAdnRwxl22S5u+5wH0W3eNuetUPBCfYR+4bsJbVtPcGY553lBuiW/hwhzpbijbaNU110y7xW45
3rTvgQjfpjJTQfybZwRDGVasCcT69zCFaINP03Esz1FtUG++7zzZ043w2SlEIfpmNM9d9aMLPhCY
YbMgwACYhhfXqXfwZF7UWiEEU3opyCKAaEwSHvNv7TB21Mt7GHI8cMfAa5PU9DHpnpSuF0VXSQo9
QzulumjVTO6nzNNTwWRN4qQwSZV9ML76C4BBb5tm0p7COLjtopki/n3tLjoylcIqOkhIWEmY/Xub
pXV37a/CazCPNxdVpdOxht7BTIiFiRDFbPiBvdFoCZe8zDL/1IMy3W3UCSmlWtxUQZr6FKLQ4eIa
eDyu8YZ6/czIqjN4+LNldSvlWRM5wxYdiVlOqk54Yc0Nli7aRD7tk4BEoQWJKy/83T9mt38aVgmM
4o+QVvE9KzrHDZNmGyQ1VgXSV1aKLInCgQkVTw6NdGkudbJOQJTOGILqoOhNlSOaq1shPMEKI+8j
XRWxCq0FqWGAzV3SUrtM0HBzga8KD29ULYp5VmM1Cv4BfdsI2o7Nzg/0OIyhEVEHvdIqqKSjVFsk
aMcD+PTDAm5eQXr9Oi9eWkuEoUz1Wn50EV7Mi6FVXhmdt2u3ZClvElbc3KFyZ/ZX+RWSWHZkEzYu
IJceaNWiQ5Ecnyp/hg9iS7PWvjJHmoj02hCtZgVCEloPpK8Sfk3XqRrKqpZdhH86Uv1/jeahTZyy
oiWxfBeZxoAygHvwFpobpSrq4pNnIxwlQNBzUvYvtX9S71vT71P3HcdmSKumSaFjmhnnfQt3JSAx
ya8x/Gi/5IWpSIJsryvUCq2SX1vJMhAik6QoJOvIyCm43Xx8SwgFvSoJ/PFDPG2AHJt6mNniBK4s
e29mBJotNZi2SYtCsUm3mO5RiCMieBG2H3CKLgqz6CYf31JYo0PqwzqcBDRlZNnZJY0fFXz8qOCd
M7tE2ojYwiSQ+xzUXIL/9K1JI4gfSe3g1SrovQvdoShwAR0A8yaqql3nzYOfF/qOZZbTP99tAWRh
D3bYT3wKGQtZarl2zFGZEeFDMF8pQosPcLGba2a035iwaxA70svZzmmPtx4gD6Kwt5gBpmqiTXmS
XinThKTBIITwPuB94cArkA0KUzwTVLJNOLI5Qohbu6I+hc9eeaa92bvfQUK2xKFf9QlhsJZJrwe+
NI4y+G2hz3QP4wJX90bVysgdtAqnwKA81LpdrF3scnqD8orr5+NgFJv4mtFOqe7CBzJPPgTsuVcm
0y0KvvZXGz4GLmJXC/jZaZgl/LPDVlM/2O7GtzbTiDv/14g1srJtpyUujWpZrBkb5kANwYpm6PRN
E+uuCHluR6QD8Ud0yrbRdAdnIVkWsmS1Z9cD8XZuTfmZN+oDLK0L25QlcrlydQwwrbwDtMr33QFc
1Zxu5jXyCS7eWl6qP6ctRXlZdZFKe4OrfdV+5d62F0yW90y569a0jujTdLFHyLGyS6UPlwqLsBVa
CoCUsgZZzkeVcq1GPGSktTWu0xeVVQQYCE3FJc39jG9XoNOIsAnh7rh6aVAlAq5YV04/WOQbNf24
6HWcw2po6TwFHxw11UO3meXwe4vVS4rotANE9iKhOD6DxS64PrFm7VvflXKPcjEopxXjqwtxwv4b
VyEBbXg/Iny17AsIYqY6o8yifvmX98uo84hIOMYMjZBIW/ESaUbULc6ODq+YqAvC+qYklnR3d0lP
7uGdargcTCbDUm5o8HvmXj8uQJBzK2FSGrlpJUYFNGBJ5jOxzvh72vht4YSiQNJoyiag50S0rt9L
PCkz+uVpvzZrH9lb1kELNLkHndiSLVG0qosr8DptP4MqfnYoLhmeo9cbeuhYZO5wnJPFggWCzfop
umYx1+BPqWppo7fSVanF1IlB6+u20hg/AmnRwTZmogtprvX22Xa8n+/r9GF9ifwRazQdQGszEdUE
+IY9S8gQ7PTyOxUMn9xBrmGFEWWhTGBV3Cgqyf85n0NufaA6Ymf5ONmjToPys/NK2ESx70ejNQ6E
qCraf7QV17DdAZyKfVSe0ZlGJ1RF/yQXN3NFvak9I1lZR7HR5eBpAS5O+mAqAM3GxCixy/uKqUfo
okFUStzOwFrJSR2BaxRnbmOp33ZZPvHiRhxCZew+ThkDsd6FlPpca8e6QULfNp0ymQcsKAnv9UeT
re0llIl///1kEeSSp5RVmQMwHVGgiWo7wlCkl8U8AqxzamkAz8b64a+xjz5nkm4Z00+KjeerbXDY
tACiBzvK8Vrba6K6RngicUgUqybgMB7waXdJO+BmzMJG84JYdNeOU08CiTnVSdG/rdsWPLYLe6d0
/EL132lZPMZm2OhsGXv23hjoes3pVaXVKdBNFef6lxh97Yw/pZ477MnH7Ehm2qm5f0zXtHHgAXXL
udE5+iVLAf007kQ3tR3NRhtg2oY4eevb8AxblRheyXtiNrjyK+C9P5+1eJe5etrylH1vA/YbISle
t4Be8r8wLfUd2LpWyhT2y5FKCCIK7Rg/w9uSfkuiaSo4uTKA58v8TPiKUcdsuTyoO/9odE+N8eN+
4xNyrVD71uWWigtANHDfiqzZLz6N9fwW5rA8WBGmgbTjXZG3R9rC2wsHzRawEf9+dM2BYyL0CMs0
VVcaJjfp5J/qVROl0IVW2QUYgj7hKvRl4GbXdlPXuEW65EJ7AqAcaeiNoLlgf2cr/gvFM81IHyDI
7xdLOINQzwbNvL2DGBgSMPB62VPT2iI2wxkSvlUL3NAHbd6qJ69whGJq7oV/67I5wIry5kJRFaH2
1zIBeATLMqcr0jYeKVJOykJT5wUJNn7w+/FQvkxk6ctt1cxJlKmYpKVBW3JEjK8U+koTjqEageRL
TLxorlcdZypXc8YsQ7W292vV7bQcP4wfZgIjko+eDjtfLszFI+YgS03CzjHjJhamAJMkufNDvWAi
q+xqQI3gFbP+d7osqdTK9eYdMUduWJ2K7gi2kXMC/6AgAyhTBoSAbkO+14e+dpfxlvnlyMDPU9Kj
FolhfTfHPb2pa1ZNO4eTMUceG3E0E6cthv+bWLtXlNyk4XQaXytXvjn3liaWoCWlc1LYvyjvKWHb
/DBIOgGOJnrG3xV/zWgDK58IOtq4yOqnqFRBcqR05uFOBYOWJ+1cfykf3zuIGaRLr+zJ+ewgo6o9
bpB5Z3r2NCqO4bB5WU/a5FE3g0Rqs90a5QWKI4LNvqTxWCq1RyHhWDb3pHEORZdUSWAMifPYiT3Y
SWK3gIgmCfQbKE1FtQ8UtTPhjTQwf8hxpkHryy+k3bwO1xJ9KPPGKWzJzTDX/3fxqYVVjubgtPoO
tll4Iucm6favdOyyIvZdqmmFlxTmlmkGINWOwP+h8g2sD7sJI1Ns4mPluKu9fQ/x9gI1SwSwiTwZ
NzU6MIeIR1ZJIbVKsk5o7JBOBNexDXUBakXVR7cXFDZv8uzSz6rulAMnVTa1zrDUzzBaeL3XU7FH
rEGs8cRVsuOvwL8O3Nyx3ZDrftp69lKpvmnyigFQyHLvgAvW8GA1XisV1/7fyuUPjRKeBjLQA7d2
hqKGU2Q9Lq4f5HdqTn0hWAdye4ykmUV6D0T8E2KcSDI8yUifoPg/dSCuM1BFKabFolDyEBcHAiTf
H9m0Yl/7s+cEEUkEvfPgYDRHA6Hc11ZsSmWMMg9UtGK0j9jm17aYdeFDP6GRPT5c4MkDI5ahUwID
GTrlPnPmvMrWH7rcfOkKAPl5I/74gi251J3vnL84NoqTjRdCwVmLRgv+rlZU7OPaKOY9/5aYhYeb
wfMzNYKPfBtw3mDobjOgAu5FOOmagRou+bJ/MAzwz5gqr9TjAjVhn5NXrBFCwSIg7B2eynNeb61s
m17XYv4qwvIixQED5ihr93ShxRwcp+JftCqPXHbhJJ8wUmrDci8UwdZb+le4bYjQ86gF+lBba6B+
D4WWab7PsDNwKzaJoAj6o4vNGU2JrIMh+ZpDC68sNL402aMzSXUIzpJdsgusVBpRwcw9Yj1VPnfM
HKFPPPSZvF7+b9EnqRU8VeGCPc7fTvdFCPPJOQ+iFEJi723vCytHvPWcodCQ3B7awZmsfNSmzENm
dZF+8ZtV+/M903rkDRk3j309077/8dls50bUQH7zNtT7DKgIzUnt4GmAEuqSNYJdZ787hbTjWZhq
qFMVWtBbS8DOU8q1/vCP1hrzQurLkc0qOo4+PWCYYpSXfhaVcYs1d3tLC0erjIAU5WiFa/8TRDgE
ygmJ0QAQLkHgHUQeJFBSneNdE94huMvVUC9fRAOmBM0cPKHfExM9pmz9iLa4Aq/poCT6afG6VRIF
FqXkXVNUiqCa+Saaf4pOyXCOTBZfxYdkqCGZBerZO9LfWPXSGEyDbExldfziarkxDcpdn6Np+Pgn
QBcO4dMVimBXorrmvsB2lQjJvYib57fflzEEAzi7C7CFl9FQs9d+TZdaLcEbs3FqTGUDYPnq+pDd
s4WojiMDTl42AsEbYkoPYf5j6YLdv3MGUczhecZTVfsMlZEyHnBArAGiFTtg53Df4I+Q7KAVWuU3
xx1eBE8BFEAKhY7Ul0OQK3oBCc6h+Xb32ifgEc0sQcClsTXfZeOTqfFF4TbXj7mm3Vtc0j99VZnH
bNVVMJSx5HGeA4M/WTIRESHAaIiTH2oHX2TccS/XrKOLPwMAdn3jSQJrG+rjNYuwX8RaWcYMARuN
ELnJItQAlcTbPr5QUP29Mt5OOrQUMWK5wFjSDi014u5nFa+HTqeSsd8auA5DED1shxA/LpmtgM/q
ODOw35vmKzZkO+ynMjCsSVZl6fEGJndM/X+Clt293xjBIKRallQs2Tiq99vj6aDupUeQ2mBQTaYQ
ILECv6YDYYoByjy1wc4MgYVVQ6CAAO+5ctz91w9TbX8pfca1XEDc8iAEbL9oYxkhJFvUo3OkD/z2
CRy0308PK6j40F6kbopCWGm29NBYWkef5Ohnbamz4bilJmIU0o3yLalSzjOlxwuGbblCMpISTae+
utd/go8aARB96PQpWwQDoPAo8223e9fResFT76Jefk7XX2s1kB8MJWgA46uyn9jZu4ET9whykEuJ
4qqQNzK7fBtesf+tWjJGm3muUIJdLNRFbSiMTw0fS8kBl6EX5bWzq+EaGLf3tahAyDVoTDZVXHuz
3/tlVapiEe/P2TsdU5NOiiPbs2SAm+kiKDObw8V9Rk9S3E/jcgasJZ+Cua8u8yrjfg6HRCTiyzHX
B9mZR+zZjnzhmmYxpVAxHbyIIMW0BTMJ3hyaIjJsSu3jcbrPJp4p2/NVUvxZT7IJpVD/h6X40tM0
H14wpwcc9t9KYbg/pAattWn9yvZdp+n0ZEPaOisfAwvQFCo8BZ2m9qNYzmjzQXZlHTisrWxHPkE+
iZGtNlr+MRARg0Rf869KxV1AoCXq+DPOTGPF+kTaS2GHrMTRTmVin12jVsL9HdtUMxVRU1Le8Mso
+9ekbMrLMH6j3UbsDNW4/XmqDCScEzjJiHkmBLJagWUUND/jZa20Ei1cXRaI/VN4CanQHATUv6Ug
Kv5Cx1KNbUZNpHbLFipPJE9yxWyThrDLCZFL2sEu1lW4JDc6PTUnJvQTBDWsk3lnCNylSPrHdO5/
p+lt7fPhrZGegb63fzkVzgBqVUvs5xCyrYrZZDStY+Ojj5sPeOfOZZiQEZV16Amzg9LDYlj7oCRB
2C7d8Znk/4foiqikKN6xr6Dr+VcHk1E8bAl4y1FKpBlOjmNQLLDwhA7jmr+al1bEZDAr0GTF1Jmj
Reea5oLszqNDSI4FItAgV8kGXif8DAQg9VAPHWRPknszaa+Mawmq1JoWwOYW4vF2YutjxVWs97m3
3gLZWU9dUrOJrkZhcWy2XomlE6rkJayXBuO/DRuohjDd3sXR1IuixoXG5sC0i9Tl9rSmuQths61n
4erefh2f6ytBKdIiGYBmY73vpYForivRPVCnbIcbmoS2Fera1mFZQmRVWXr5j2UYmsf7gSBdZm49
CR0H43R4MT6D6zlX7xcs9wsmPpf0mm+nW+9hbvEVvhusSqxrIuxTIyehUo7k0Vos/ESfzuz1xBcs
wk5z0isy/1T7KdIdOxEan433iD5fCokaD08eLTCaFBdopocpub8uAr9nX1HcKItcvYFPrACCT0LI
O6B/rXPW2bovARKkvO5vrM03eT4JICJDDY+DypxlO/fsj6QDYahmi5d3zf02SJ9usQyYRZeXU07e
VnHxnjfcYm2ZIVNbiyFFOF/SZLJT2/rS0wEmkUh8J85jbwfTaKVcqXpEBjLXyF/L3H4xWSHRu+JJ
DDim0DLQKikulCbz/i2Q8WOwUgh3GLZAmW+EMkqIgqogurR5GeRtvWgJrS1Ghzj1rOcSf0TTkoYx
i/Klc7byGQTkTe2Zoi9O4T6yZ5UnXjRKhhPG0z0MsO3wLJEd9l31KYhTmPoPkjLmEVTk37dWhDki
dED1N55OR3CEsP44oib65avpJR0msGB0I4ByIETEDwpQf9av33YnNqLGYKzG6ixKMshc326zeVP+
Xi9tJ80/R75HAzZVtt334a8tOhxS2jjk8TynXgQYHZe5QOu+rhNwe/qdKIBIysdT8zmm16erIrq6
h1051Bq3MXdSehUH8GBtXesxmIzagsrlQ8EUNck59vfzzkHohLEEPoF5t5tX8rE+HvSDT7BC0hcY
DgHABvUZ+TpIsJAe4xjV088DKzHJiE4bsNsSDvvdJAoy929hqnUCIzBMDetzrSSueHfoF9NwyCxx
UKDcNOr9CvNMsTIpwDp7Lhypcij3KLa8Lg12FeKS/DIDHHEACa+AQLHkIhMvH9rWFwIdA9Q28VM+
C0zz/N5OBb2rsJGCLsQy4x+23xGSrL+Fm/C01k8q/pv+7JqFZ6nWPH+scspQkLNQaJ24phGcDNSm
LAxdgKaSGny2vZrypYLe8EHj0o45VWQzZsPuVWOQmcLLdfOy8uk64PbvmnFAHJLfFyO2GxBHzlLo
oC1hz3dyr2tiAoMlFw7UFI7LV7Uxi/NHzU+ZCVtJafdFw9Uj7JHXBT1hehepeZhfIbOxUnv6niNM
o3G3WfMUtScIa5bhAejGHK7265ogg+MxjoCQIwYQqXNmmrUEfkTp0iI2Wevd7iaT2XPxQcYISZ9+
uMyCfZVxV67aYMgBB4kNzxY6IHXRXRDprsOcvl+vapn2CY3ox4xGUiAP2YoGuoHzt8JzJQLqBoGA
3tBPrrL1PgSdRZCjYZwKz3nlgjllGhHl4gi+e57imDI+Z9xQJeDcT3jxK+43sd1igpWh97se0+ll
FCnKG0av8FGMj2kwJgLOxKar8QQgrfCrVDGQw8djiNAIbGTcpsDts1MV4UiqhGxSaxvkxnd7qdYc
5brmou3i2tFreyZjokI1ewtFwQcRiu4HX60Voe2f+AysNehK/SKS3lljUrH7IA//un0FB6hTlKpO
rOlX9EDa1OrKaAye84El3CyjcTxy9ENZZ/41s6hbPLjrqSELpqG+abScTDcpwfXMtTFTrcV4hHRC
oZzqQ4tz4R0rm83aDBTPHaVY3s2Ys8A4hBHk8IVtDoOs8IKnGia1escTl5PNsLocnAb+V4fZuicj
i5EKa2WOYihzMNefs+yHGQVcb/9x2g192OYGj+uc6mXf5h3lKp16XDybi9PN1xFbuY3L81Sg2jgW
voUSqEAnAfwwKvKdauQUTLhnOpSFj/RU8HigAc0LduX7gR2x50IAq+pJjCadrzBSdeslN7bDOjJB
UHc25Em36kkeexY39DPdMUlnjxCnEI8YQX1v6/sTa4mCoWVUGdi0JuasLSb3iuxDkhPGGo5RrlVx
9M9gOeWVa4JaX9BneBG98RpfvlK/lQDhnjwlZ3TEYnqBk45FVvv1Lso1LHAJnE1Cet78038uQ6xT
Nzo5KKk5uer4IsfcxNaKvCPmLijPFPPPkaCrkIHU+2hHhKN61niYZZNPeIIdaDifVRmWRRWDbfIR
5q+n53zzDYd8FhybQp70RrPCDOXPcftwTxx8MSKBZG+CEp8vpqyXgDlkUSzs9MiTGiSw+SBd/PHo
QpCz4t4BC1msK2eDFjU2pg78aGCfc+9CDbTLGNjbW3HpYp5LTg26FgEvcy9RTkC03ZEpGeneq/F8
TpaWrI85SUmTixxEpuQEKoh8hUxJTpa+e6jIVfsIpVilgsfaINNp6V1OLEGw5bJwmLQ4rOaBrrh9
TWiHSDWUT2pcqbtdI85WrhOpV92XOaN9flaLCg+PhG+xTSRYK88NJY6Ca71MxzjmfJVWQODsjaJI
wKnrzzm48vNfVHi5jWCBcv8KZ8Ovyo8GLoqrNN+wyfIVQ00o9ArJ1HYyeFfZG4uyoFrEZNDYhRhV
2alIuo40VcuMyDk1YEHhxjlOCIqo3DvImcKzWIFbbHLw/tqshsoZR0jMS8GLSYc7k0uS45+Zgyyx
FM1Vi0DIYOuA/+xalAopAr4KcsIMua8YqPyCk30YizEdN0W+mD7eP2CtMQxHVp8xly55wxHrPfSV
REDP5GTYELZmVE7GSTt1tDStRM4uMYz+v5AKCPE2omhkv73y4zqBPlcFq2IUWkQBLPtRsKBw4u+S
slorIrehCci6gjMKsos3G4PAzmon8dVAt8BjtwksPKhvKjshR7uFGyKI6mcvrC3xvndHhbtGfGsA
1sGlH7ZiY/JcNxq4SS9jW1MW/SpIx7TE1r++bpsACp7Zy10LkyASaEXhQ75tih96SLMsj5SOA/RF
4CYs0V0ilFDOwB3sGuVFQcGd0cxqUaxH6iGJL2El/VF05Hm0SSVsRvbgQN5UdNHtKxvEwI1axdkS
NF7FLGku4zspIKq7jU2uatzy6mdXW1RQzqxeKXgd85fvfaPZseMzCc828/r4rCPTi7MeNC5V2Z1z
owT2RVipPJ4x98PWamaCVew8KFdd1HK4kC1HN594FaDvhlOYcfhxmvfFwpvElV0axoD4jDOilWbj
974qU7IleDjfSFNZQcBDKDfrmKXeov+vJl7v6rF7EDV/1fD/+e3AscGw3noDh4fetPm7bKOMz5ZD
CFKhLnzCMGW0ApeonbejbhjSLf2/qfUKXdk+ojjiGZ2TmDc1lKjA0ZRbVO+8JLkBb2aB97cX9i7o
cQHQhnug36Ceu9HHcJ+7IQhdwIGzhM+QdpFg/0abLe1TjNfqH11nqp4TkiMHvbgjJEpcotek2BzE
mAs9VII4CmrEyCZilA+Mh7skvy0DwEI2Pvz7l7zujWQrdAjfNBUyP/pY4CA4rVHQOMrM5MSeSllV
UWl18b81tgSXMFC6RJExuzSaf3QPLe6AOkY3wy09q84TkLib7qX7fYJ75XwNglbqJrm7wgxpvoM5
00W2lj0nDzV1DPf59VVnA9izki/DZ9nduzuBULIFhOd4rOY8KA1kuyS6jmWpI4b+UsmgXuQEWaNd
YWF4WFyV686uufjYbvK5fNJ7nryxLhDliV7YJt5JPIuqWpiqpKVQAs9k0LlfkJbg2ZUw5R2htu43
s+Chj/oRENlKx99lbdBL76MBe3AhkbKB6kUmMe8RT22mi8IhARABHLvH82eJXXZtJKn+AMhef+6Q
40FKmgEDCxhWWzOCTWvrcXoo4aqA2+Wv5OdW56ctWJyAjWrP0y2HYu7O79PuYnhltX21H/UGKzNw
MLM0Pjuor18IpMIgK75Vi6RY/jWYVXEjMPUCKhOqmG3ZBTFegBpQK8q1C9a77OkpK5tb50sIqfpg
DxHj8TT+TqCEWXxAtJb2NS9RzDmuLzPN9S4cLm6vnQp11pOOBLTnM1TwAGv8CCCjnutt+EXiGqEv
KGmLdp9BGngew/VNbDvNnLwhaveUZnLxxOExjA2U8KWHPJrtCGwzjgyJygM3LI0LDmnQ1F/oCbwJ
YVY2iasI+XvqrRbjyJif8ga91tmVRnaMIp8v38Sk/nM0qXzPm5n3Xzh9Vtmu2SZkBwcWDAoq1j2N
Iveqbib1U51CwvGkcLIALRhOrwK4fmkjBrbB/ZZwuJm76b5cTLqBsEGP2xFYDUK7KT60RV8q18l7
sq9t8ZV20s+wg21XeKobiol0Lwl3Ll0/1i48MeY0t73h3/0qB5k/jbPYzWXkfMMjILD0gQ/nd9DT
nPWRQurhGJ3Wr+nP3Vspeeb1lD3pIqVhDab4XhAQZV1HR5GNhE9Vm6WjBWIadQ8SoKbGAawjF2X1
+6fbPGgWxJabab4g5DKe3X+1ChPwqn7uvxEEgT2U3VV50VgEPm9ATnrVVilqTX6czbOc1Ag6o25i
UjFftT4cK+0v0mdz2ZxjSlXuzOvF4MUoo3qA+0n/VW+Xhie7Fm7Skn281zRiDiwW1ArJeyZKscNR
VnI7cI9wMTSERXar79Ztstt4U+LdCmDsl2bHjS/cVBOCu1DaCZlmc4fXD8wFaQNCu8nFU0ie1DqN
Hm2ffJClLNZq/ckn6nhIlJ2M94uUICa+nVV9jBs9f4KuodM9TqIUMePBLFilLMq6w034l3uUAyMw
oM625HFC6YsU/bpYlc3ZbJRVHXJHMxygs8gGBQg05coy8yGLM630CbYbFYjx5CVR/ehgzDeO8Bwe
bBdJP4mhZTDQZInbgIp4g0F9MXXhZi6Z5Rq0C6PmhFSkgal+4l+7Izrp1wVtGcLZ4PbyjgAd4iFz
XH/79KhR7SfDmOFsWtbY0/ckhJDWGvwRTfSKDIi1YpoKX4rN5x5dK1D3mI7cTIMGWowKXukBUbZy
WuBNOd6hIrbFfvCs9tJ5GcJVgNcZs1HiZCq1Jio+IrdlpOKMhX/i/G/YpmbSwEaFkBZJYWrfsI4T
wpV2QmFaSxKGfNe4QDkR9OVxNaDWBSInHFB9dfn4OPG5NkkusQJJebjJatA1d4npmXu9SQ4WWmBn
Mk4fM/Hxkrb8F3djxRJ5SWHAwoLm/F62B2z7UikueXUKE079C01uRg4hGdCbgRp3Duka3AlyBoIO
soKd6wPa8N8PJsuHkf/vryF21pf47IgfCVqKNSAHeUMltR1ObTv46YrLYt0qNP2rV1cSVa1XgkYO
qR+E5/nTD9sai38QZmde+kij5Vb77bZgXcBusfMOTponnELeJzpWh0D7nN3Z6IOAW5Ncz2yPkwn5
VgKI4MsUN4H5OxpZxSBPnjEwk8mu7qvpPd9qXuirC3tF4GH6+3MGuOgsyn0cs0kiE3lPKdOgtMgL
Be+3DiiomCRsn/xDOCkqW22UEO27TZA5fUliNPftWCxjIybiUocPb4ATFgzqnIttzu/WHrOtDY8h
suGVAxCMPL1DDIQjKqzMJiBSPs6CFor/lYhuXa26RY69kWJUar7cTN/c+JzwC1Q3lOGWv9/GvMTa
M8J86FHD41CbrST3v25zjW0ePOOGToaxwZTvRFyDYC1TqQu5cL5UhsCrzSPqz9ysExUJy3aL+v2D
7ufm4sAsVPnsyK/ke2R40QCHXlS9nSkNNb6xojMP4B/GTzZGOMjYN1OeLdScsD7ngYtL/i/gD/Zl
aLdSd8/gBvk9fkhdOV+FpWrsUEdpBfwII0amip593nM2sDjq2fcdoLXfnTxwqg9CG/tzYF8diPqQ
DDkJSYi50O4klqy7PX5fYbNajpMWKVRymbeoQqFxR3R0O1Dnf++I6YTRQ370iQM+n685S7AM/YSP
kfYR7jVwzKpIMXzqESJCV1+fqkPGofHo/kM9Vp+fLdiY4Q+XR4iYC/IHxg2TwUManf/ZadTx+BBC
0XlN0gisYV/rgexTgP8ygcHOhX7/52VXfw4Wk7jB2WntMVSwoHucNXeg8jW7wifiRpNy8tg/QwCf
eyMbMsrtEEZd6BQCx+jzPIIVlg7dxiBhqK0FrDU4IWtCitaTjmXztSw91UY6ch9d3i0pdelmhYBS
g5ztwej0ealBrAnfBDUrnXeaN1ik676PW9iLCQJe0BPL4a68S4f46JfHv64ONw6tm2m4YlT8Mg6Y
bdClkfZisg6yLNbTkMGLvODQqNoqT5LJbvSvHtpVYpuoRSoWljZJ8gAlLjgwpQdPAjO7om/vT72q
lrOTf33YVsoDQIFXEdPOcfjJX0rCTTvfuCc3wmLDFs/vFEvWxhvBTpiwe+GWK4C36LmM+WArgB3D
wfx1363fA10tgMwU40OQi/sivY2ozMIALzRbOmmHVPqRTdN2QWDFLxMkHPWfPUMSt4UoM6Kqevkn
L7UMnOF+nBUhCenhgvGhbsXNZVJ6KW3uhUrq/CyO94KHDXmwpEil1iiVUkluy8fUd1SBNo6uHjbO
mxHMqUyIHNe+d9rumQG+tpKVleud6iC/CJVcY6/rzztKkGti+ZOv/j3kyrq6JhARfwF+gzSro78G
fe3AgOy1zXx+UVoA8Uq3OSh6eZwwjIY0ttjMQNF03u8HS9jc/0Dfte7uFALDUJNhHEiKOJiQ/Syd
wTNVL5rEEwMT5NkH52QsYqXOhm3BYXVPIS1Z26hhS9TsIHACY20Uqb53lIJdSpDuk556kHakeNVa
WfaV0k3pjjWnH4bnlM1EtGIiYO5veDFocsV9kJf03feGTk0JrS6E4n20MAU2SoWMtamcyPiOqb0h
X4+jmll9+Z6xV27XnzMatOOwvntPFnzjZihMPNw8Laa7qG9Y3/S139zltIGHYZPSbJJE2xre3COt
V1cvnfbIcHB7bkaG/vPg2L0ibbubZH+1WVSiuKjWXi1KwNZWuLqVFWnEQW7G6x955Zc+3uscCSzC
ZM2ipd0FuHKDUmAeW+PqpU1Pa3Su7a600pjlA85MDL47HBuZN9K+KHApVzB17ntOCQhh0q8dkdft
zW2ES+Jbst4k513zpnmk/12IQwCYecWluteh9c0BWg+hDYDY0E1v6xxqPJ2A0okMdoULeJFmTFvs
QkyThpVY/tCvNWo4+9K0ZZ7ATBz/csw5oXloTesVHwkR18mTUuZt+xwRS0HQSft5cUUcENZzNwiR
5FF3blSeTr7nTpysFXGo0tM73V3/V8jeYNdu027TUFlCU0B+NgiuPY/Ze7MBlTVAv/FhXbg+oW2G
WE3ncXgLU0YOxQ7JtYOWHuFkbwStdk9fGV7iC42qyYN9k0sPnR1T43cFRzCVLON2j7GhEVz/FLxR
FRGEdeOfGM8USIP4XneJ4TYbzcoOoQMTDpztfWWoaSfywKvBI+xM2aYr2CVdIcVQ+MoM5sA84nzQ
kfVNRZ2qeXNEfXQkBoipFBbRvxOwDsEbtRFZhirycpnUdWpcrlJ4tZcgC0NiTpMiVAE7UxtYKIZS
NJBUhU6vWjwo953h7UegpA1mWz1g2S+xE35sePgZhNypdy+RWCQR1fBSbyd46lVuzu9qMRSU9air
khy6Pmymyqu7JSYQo0YfS7TJH2eg6jcvdGQewzx1bgIhi0HnziZzZmEFRT2mK/pA6pbTT0uAKq/C
fimx28ROd3CqfjI6YNq6XRgJgz+xi3wT9Rm8po+Z8nzYWB23QRliLvtmlku3binGjJ3lFDVsMzCw
i1k9FTHyQTXsb99jMxwnnMHMwQIH4jOPmWdTahjhPcoZhysI3Js8bQ9ZqX58zWh5yRnqvHwlBe3v
mkgtXY3mwSHPfwNUPbAz1/ZhGO/4ZGlyO+8gj+xD/+3t65uSUQy9V3Ezx9m6+O0jfSMZ5qKQhCxC
TnUxc9QLB/wqO/XfB9dJlnXOYG9EP4nsdokF2t29xCcczNJrKv/QBom6lcvX5213hcQc9q471C5d
iLi8kE6bt+gRa7DReVkIAzTih1eLCoAjy1Vrgdua9O3hgWsE6AAKphMIiQeUiFc387xvPXcPpOyO
+fbmHAkOFLEkvd/nPa0rBwtkIV/roSdB+9LmRnzS1jB/oG8ZFmr8spOWJ9u0jiOL8L/09DAG0mcf
LpeZ6MQQOKoB/PUlNu1BJZXhmtKj8xDjRGdz7Tro+ZY2hsQ+EPZz9s7BXSQa0PnfQvJFNRGJsnm/
KcV8+V9N2aQJSq8H9wiMW3UMunpYqXPIjRbkbzLGUboIXZgvgEBzqrGuFjcKt6p18IWUi3AlGDbk
P9TJNQmVeXrrQQJfzRhwmw7Wl3uY0FMiLgpo7IrPNwhzOjyTpYzuMFOgHZhTo4fbbFPC9uatXrev
h4Bug+8ZeRtoL2LtnRjCuAttKGpazqLkmkRBLE6zlP7VQYx1qea2qvoThCPajs04Fgt4GNf5YFG2
C1rgQNNCm+IwwoyibeqMauLvYTnv3N63ur62cS+ubtR+D+14bytYgPsPlBG1srE1xXbe2feOG3/Z
iCEU782XmAd4+jnqSMpyZzaBeRHHH+l+KKxb/s54EkA3EzvlwfjwjEnf8GtxZYmZHaFQXEbp2BO+
Fj6QFaVGlaveD7WL25UleU/wrFrb6e8W9lkxmCj+9HeX//OY4jPGwrLjs70xwvZjBn4lAl6joJWg
3kRPP3BtmUhw/U/z7FT44MXfJV8Q++Yb1LZamIvklhL2dcLtBOkClF7kpZJlA8cuIqE1YwicOMwX
SsLUcvRXrk36EHLV/t+S56kIBCusRVbfuWQSf2C2xnfVcY0I4U0Z1B3QgaVnGiZDl8d/pF5nG8qY
zdLh2PqSaf8gW0kyk8CgZKnrlK3JKf04/XplvUznsBX4oBN890E/RVvQViPWcUvx2lKQMd1Iypz7
ASKriaVTww9qQpWmk3jBvk89L2dLp3/ez9L0nOJ2VjCsWLvblJuohcmj8jDT9agixx2CUbaFFYQJ
l0FhqTMFCrWfbkeA6aE8tBEqs3NvHHJLa+a/KuA2E2mcLGIHsZKb3Liu6cXAnds5RzJyWCdb7pS8
D1Hu/oyXo8oSeD4wYJP9cbpVlhLIYD70TvlUKykM6YM0r5NlHoPit/bwX67w+VZ+pwNKEorI68ly
vbRnhK0GLDdUWOTG/w2AhcMqyzSJz+d1UFmLF4DMLgmzy2aFrr7Gq6l4AknlCb1fLaDXg6j+WBMd
qFeobD1TRBU6KDj91J9v/B5wx86WNw3siZGvC4YXsKdAo+SIUHlSmn9jFMRLctjVavyv3dDWs21X
LBqUCNbMl/sYAPKuMRX2viB2RZLX6+JqvI/pFanRj+V+nRbWlyuj/aBdnV47P6TxhwiabJmbEe0b
RY66MM0hCCEaWFwh7BW2RijaUssqpsFIC5AGAXEqQr8tmtr1PhBhYPAUg14ZAWs7upo4yRvEqZAp
9z/yyKOtx7FJYRze4iskuKhED4z4sTCdDHCDvnm59T6Q/z8KKurTLwIDTaH3xQma4yQ8IH00Wk1n
uHwa0zkIx5nrassK6jM0phJi/MQ4Ns1bpDtikFU83YYGDAHCYRE9LQKvm3ai9cfxl+Ad/hM1VW2n
Ot4Z+l963Zswv4ZiBLTR/uXcfcEMr0qZrBcH0nTN22ZzAg7LnHRwxsWc16eb/09sRw4Ml1C+U+s9
kJrxWWHWY61n/WzTBr28DipV8LOyiAXipaPU7WSaRx7yGHTZeUtjuMJwjLZJ7XP6ngOJOaapn716
auZGbow/fkIhIfSTBVTshPUik/a+1zNDxusAPugJR0g+/zle2p8e6guSWeJp4AMhPpOyIh6pUT4G
4FngJnLmK89x7nhh24bzg+UFIoeQtEOMAZ0jT7gEmBWSM9BWlAjgqtP0xNHj3ccXdEg7wbYJoFJ3
QOA3BDX2RUkN6edaa2u2jibkCg+gqQ/9uuKy+Qa9+H7CR8ZSsDR+EHvTeOwYjx+6RMaO6lcdNEnf
D8kLmux9cUEP+qKwWz6inFoNza3c5DbXJ8b4u+nFIM5R1t7uPz8FgxU3mTGaqUpF/lhlbIzc4zUZ
j7reVpIs5dXQH5gMBUvQPqMLwkIIIaB+oi2v0ngvaNy9XuNTZKWO1MpJDnFGyGROlPiL2zKDOXKR
yM0NuhQgYpZLOOEyk7r31i+cc5xgsoQRWrd0vLPwoB6Tj5J7i93Zm1mBhZwQNx1wkQwkvEOqroOl
Mkwo1q7ymT10ZQO5O5sIsdIUiF7S0ghTG2L758hxflQwB3pJjFxm3rL96n/OtypSROldKx0OuCej
ebFjbRpgYrOEkAXiBbRPQYXX9Cs1/JOfFXP4XeuWyP43S1Z15d9YvkZsUyjNM+mw7SRan04i6BDt
S6V1RfKt9meRYAppxDd4aNrTf4BO9KOigZjTg2vde0jdaUBqABhYDP9NMWrepsUrjWQjT1Y8/qls
7I2YfNK/rZ3gaSa8PuOgSdAPOHrFRAfnf+yiBP3bIOl+Ak/jlqSsfll5DMoHj1xqY1kknSCgaC4D
bsJxDv5QABPPtMmTDC5gLpDQ3isN2D34vIjzDc+sVJ3KAKdA3xmAcMsES3R9uenHOCgsx6NNrQDT
d2+W9aBlxpDbzo0bLvixal+M6xtK07Clwt09NUo/8M7LU0s7Q8ZJOzqxejeWmv9F1ayd0jAGktXe
Z65rhQsuQkxJFJzwJSADwKC3Z8E5COx4oNGmgGMZ8Hf9yrequUek7yx37qUG8uW5enEKYtPLDGKF
e/ifVqeEXVwhtosdTyInFt4m7ZGO+9b1YDlPzqfDMAvdqp58N/LU3fJUfSTVeYFWnHwqqr6vWvoR
qQSay/DaMVZVwMtAhakjrSO/FUexCSwwn6dlpQUlLRnbPDcd5bCTTr+xOfJ4dfGvz4bvj+v66Zyj
wbPKFkT75GrwUkIqEhP7bA6gEhQtuujzuPW5DnLAJgysXaKv/1Pu6ODyO+xw4qUB8bwHOLmHvgmu
IhOfM/VpV6t46PpKysafGRF0Oyfql7Ban2VT9Yb0mTFTXGA+OQ7NpfhmgcG91t9FclkfTPUBUpdd
3yGxlcDyXF5qKH9OyNEF665rA+C88/BDo83XWNCuAoJ/v4t49D0e8Q2P0aCMUVEEvepKY0zFmDMo
+d4PduMRTUZfCKbdwjPm4C/gFDOuKylEB+DIaYDW6CDSVKionAl45b+/qWqyvICXR2T/UgT6xE6+
W5aJTn1mXieeJ4ts/4QMjqGl4XGizWiwLpPMgRV8BRZefaSjW7XMKQSk2l4hRQafBTS0tK4+Zzby
kbYSerPWnZ3tGkdSitHMxqPEcxj9ZMoUlKzjy++WsyXqP0tOs0eBYIpZ9P6JjDfy7ZQE6BWDt4VL
DWbM7mzb4YpaORa0e6kHhiuvFt9A40zJrwqEGaZxawfNGNBX2c+fQLDw0sBdb3as0s5Cv1NsyU7R
Rkxe5YmrG+El0T5BRLkx1vzRceCifEDYVbgJ9PRaVj48zJzPTdpmaUVPXAvput/Wi6TIRRFK5tdi
LiwhZCfD5oer1YsTZjpDn7Q3YwPOHchW3LTw62yvav47PO/UqrISM0I7P8DB9S9k68dJrW+ZtiND
kf2kGG2FqQRATIR+a2ADBmRJcHeSpSNUp0e3Ae4TL82JnmNZZsk9rnD0pgHJJy7j1V+AehykJFo+
U6mFUb2MFsL/nTx0i6+tM02uHtvNfPLfXPfzrPJ2skXII3v7hLgyAbuHfoIH9iwlEbFUZP06punH
F1kER8o/YFUIHgSlMNQgour5jN9iD36gUH/o0lQPLJMKHJVj2RUaBqkUNDycXsJTFL5E749AOTQM
yLEknnVWWA3kDO5JgvT9d8tZSb4hfzFXXc95sVsWEBnPTq/7ogqHSN1za9kVy0+r/LR0dbdC7jUu
udqxmS8QpE1Cq7IEG+vMsE37/yWSoQ3YFhs4Mp9jLsfOwV8bDGVeA6WLZ0UCeiuO7DFB7VZoN7ov
5WHZjoSQpqiUkb5XC5nRRPZPVMIuTZvIIr1CRCnKuwuiX84srCbUitqeNvUEnvr5O8exuwtSpXGT
GxqpANnc+9B8LC7eWYAVcj9yexVzMNslAMb2a+rkS0tg4xlUOri84OlWD1NSnreemNQOcS+g/UZA
TfxUWejBtoXB3PcSqsAX4UhqtjlnXfafRRDxbbWCxVljUT/R2hLu9XSMU3wm2DQ9EnHr7BlrbxKZ
TPONcx3dUeRq8u22U4z1670fs4krsg1ODiOqYNvqoQUaJQ3Zf4BIrm9edKl3JW8Mf0ZqLzr1egAL
D/S6RtHdFt+XP83op34jcsiLJzay9h2jvZDxVCYOZPc+AQcQGzepE3ah0BcfEhdmlBY25x3RAI12
QZhrfjDKtvhoNtAk08AfQvmrxQYKMFc/YIZ54qVvqDpVWeByNl0oIOwYHKRAsVKzJDZM4aoakfWb
62mmUWaT0yrjqoB9w4X1E83GxGp9UTt4IQ8JTQsubo8Q56LQA7I5uSLMZ+PXUS6j7hEuG9EXqzu0
siaGkCWMF9/DzHm4mxTTV1f7B6Ehq+O1ORXr8/bN8QZbPpTU9xOge5ofSBpO15pD9rfvo4fhM3nS
a6QgVSqDCBTW5HK1HxPyQmQM8CDNn2TnkxfkGP66Bmsd+IT9c6QbE13Mew0oVhvbW2lfvEWFExd+
N23jKXulMLCso0Bwmz0sU4mXNKs/KubrdCTW7mO6fqe9BSyo2W3MtcAj/VOa2tYT+NtxlFIUITp+
0BHRAfPmjgPp9DyAcuyWzJeZns6hBxJECUR9eSG2gx0t+YMEd8j454124JDCpWUYGM1QdliMdWIj
8j4L9Dea+328N67IQynLtNOc2rK+jZAbFWZVon7TneL2ZEtFwV8zgTRKorosPryD8q/w8cBHn/zH
rlEzXrk3EzIVuyz9Fy7R3Mt2SC4P97ghBaFp8wuEmQ2bHNnYqbI3ZGF2jOm6W+Spy5EPTqWdX8Wv
LYXmbaXeA5bb13y6AQVjzmIcdx1hSpEh42iOv7zQDzQ0JtW143gxP4/5vXIWuA54K7K+bUGuuNUD
AfFW80YHQf3uTGrRbSQaEv1wiMJ6+Ubn50wdlz6DRv/EkVErZqFuAx+dfABC1Ddz0Wvp1y5ZRSXM
cF1GwedqG4UliRfuwCeyz1LRo5N/ZHA0GSbX6ysX7A1PF38RIAauK+8Xkbr/b54N88HtDxyXts1y
XlYkk3mgbipl3N5f+JFYrO+8TRsiGVPytTBwlhTveb5EXt++0q3v5dF62YlbWuvQnm2kJUePpN6A
5SsuZmmstCqZCLerucjpx0JMJ8niNxWIn4m+hEVpf/g5cGkFwdeq3VG9aqvl2dBKs8hvME6a3xIs
KtHcmRWGUPCp5BNI3/ywp628G8t8ge9RUAIYFJeS3HDj7T7ybfgr/gYmc+fEHqFm8vajKM15iAoO
rC3qRlqTJVXVD1Je2meIMnR0YmJMFqU54hqUKm/QOIflJXrq54Jt3I0xy0c0miIbQgZT55wFBq+S
nVrPD6W+DVaZtLCMLUUA00wXNPqVtMec/TQltgw5OPI6GEJt/fWHnmOIJS2dcgB4/rlq51tS15Sj
KWN5qySINp+b31dIiskZzIqHoImyfi/3H/Ck9Gb2qi5+p0BhHJFOWbf4HZVNX1PlmOSRp1hiEU+V
HLRCTSkP+4+m24rvaygKyxTkUAMB9OaBZ8xp7GNbOe+jrxYJNuSBmHyXCWkW5o7y7Y9Hiz/MFGmM
uJoTjOZ0n/S6/EOZsZ5NSfJdp/yOvsgw0HT11TDbIahvvmEwRLxVFxrak2tv3gQbqtkHmQqiOEyW
S3Klp+jSi4wyLYGUOqxYvmdJnHmz47rzLdpMjztO2PLrDJxdub/qRfBjbzPi3uEvuYe7CtEjNl7/
MebTfuua6wZnm05qeq7Y5LK/oLBMiC3X1boypn9m1Bi2H4RE5tg+h4wHE76vl+y5ZQHGJSdVG0i7
217kwQumZlyuccAvv/wgbbWaYwwmtcXZBLN4Wnj/yQp4jxIjdlMqMQW4KTh7VSElJ3v/R5rCS3EL
/99YXBCMmwvhN4GziPbpfwgW3DEqGUfTdABznxuceWe24D355xQKFYnEwISGvR3n159+055i8KgZ
wsO/15ECRjhDmDxVrHHytjsOpWfexIm9+lAD5x2I6FUeCV4exu7T7KEfF4iv6PUX/gyNFfxMKm88
4FgLN5zXsE+mynDnd7nqPhTYRLYnraTzFJK5x67nj+kuT/FVk1A8+vSMc1Gg2/MYsEvGWo3SJvgI
KN4fBh63cj/LJ2wInTePIUMojlDbgSlDnhgkVrP2Wyom3Z2t21aR7an03KROB/QqTSuendQ4k8cw
WUfkvP5N1wYREhcs1xOnMHW2E3HPTxBq8w79U0kDl2D1fdHgcvCj/ZyBdRmT56s7yBn3Wyp5e1jZ
9d7feCQyoFDPXviy5vNFFxVnwHM/ILyHsyITB00N1GtFK9o1EZpC424wLQnA3CFQee80sZyLLJto
PcNYvSFW/aMWdBNZJTE1rEu9aM0T9heFxhKQzhSzowC/xTUbVTFZcZmhLV9tMaBCD3X3coF3Panq
k82jAG1bg7r3bmlAGB0QZAQONufstbp6P1fsoFh0nny8VsIOheRqeTlP/Cr7gafKvntpbhlFvJYm
otAdSi/DVwjOMd44imslRtIZBbzHRDOQZQVz6+QaQ9J1hGOCCzYfhZTtks7dibXraT4Bm2OCKFiG
6Z0Ga2Bida4NMX8F9XfHicIwzdhMQia939lodtX+zSxwRbsFlCvIJSXsEo9g86YnOUjy5OTmMzKt
mwliRNc6bsBgPoDREq+7VQrUBA4UbDbAs5kgxo/twXo37uDFsRf3lGiWOI7/AohyChT4IVBvVTDk
cCBEVED/pB1bp5XbRO4bqlL6UPTdDBpuZVyfYsBGGh4XpEv+kWBbCpFN9uOFyqLlwdvPr29SqiTH
YLbxPNqKU/YZQ4KFG5ebDa+FLXsVSfr3br+K0KxI08OWg4qqpsdgvbUmy5lX/UNOdgnSZe/+7Mso
mPF+GOZPGdAm2R1Z+Ia3ZtxdRGiW3aCo0U4RPy0qOiKuPbhDPzcnk+Cv+IThtUjqIBIB12/JHY3t
atfbUa7RuzDUUKDVArzzl51VGGs7z4CllVRC2MC0x2O8Ke/+8zvxl1HPjtVPndn/ws0KmZi4YQ3w
ziucsmFLoSfTfb2F83VkgqJEUYCYJZVYfe+n+EQgKqvsQnow1IUhQUrL36+AzJgtEM/NSZ1Hseoj
3BoOVeVoEvKV5Vt+nEuXjZE7AD6jKegWcWZezgkrT7b8je04ZIxZljAF8Ghx7qQjq5t86dWb04ON
v1+MxhpI0WnDixNgWsYhRxp5EYzR3HfrQMBtf7GQx4GutnZ1BaoxX+Q6KOd2cs8GeFAzc6gOYOQd
jVqrqIt6qc1uCtXgKndq4o0fRmT7OfR7/a4yy+o1y7jIKw9mwkMHnk7fVCcb9sFTL9bMlK+3WPEY
o19ZxVxiarJaTus1FJFwTgXxiiId4tXjDNew0URICIeF4gWbAg5WkxYB1TOze+q+2h2pTeu1Fzjw
IL5wlnE19t1sro/AZKK5ifmugS/0LDXeJuHvCeMNxseZXRqUlghGy0HHpcK+EiyDD1RJRNDa2qGr
Gc15+pmNSkaCcajQB9VUizpoNFeNJJ4rTdnEAFFgIi/doZFMlTT1HYb6kAp0JYPmZY7lhLHgxoRG
MEduiMuv5iRKYWgLP44dGlRXTdnHXGQxTqPJQ97iXdFzzB7EuXuXNdj7UcGutcGlEvw7HHq4GC4g
s71iARs0sZ1CocsGjq3qtsmV/Mxc92vkCOQMJRwYoMD4IozzZGDgkp64rVjU6sAk49k5WNGKE5J9
Zm57PemxGkocuJS9plfkA89CldYtZ205u06FSrcyq92W8bVzvnU30xSXaQYRfJ0SOjY0YtLYHgUx
YsdSz9ZIkFMDGB8+F3leF4WqgAn8W6BSfVxVtR9X4fIWZBBfXMY0SrS01OTzg3574qPDsRRL12m7
+2nvShcPCKyZZ2NFg/LgGHPXmnyr4PXRA/xtMz8ChduoaWWrZ3hzgW/JQrVBLkWrzGailiaj5H4G
ye0pI8FJDpqwvjMQ8q6neNJEsxzH1rPg3OCr3B5KAeYdJ7FcIWu36zQBadgARiPgV4sGo8b1ynXn
+DNrzRTnVSvyRPdPsj0RcALnToC8z5Na4nym0XCSIn/a2fgpEcBB16bkX2rBGyODIUVu+jaQsAbO
E55PO1rRhqKb+rHnqbZlWE2n8GSTHcpygagOPRcEYJqw7+WSonjBDycmcxlKvHAbKBikd3wMxWZ7
k/lKaY6zkI0j+Kgy0APKL0UkSfUsMNaLZJi90nxnXn0tpLy21eraIW2+pVU92frMqRU6Y+P9Vc6j
twdFwHCCOnaaiqg4e8yD5fdP9hZreOqnS3XpwSRJv5RzziJLH2njCPUikVQQBQxJAfRCg9DwOc5v
0b9ise43fo2L6665sbidTdbQLLxsrhDVQRl3HZJCs5Bmu0ZP6SBu2trc0XmwTYWeqyHzT8JFWJ9x
6hpikD+u6F0bvAABwiBhVeCNjFNTS+3PBxrmZDlhwohQDZbXuSEq7tCaJYyGUue3iU3LFQDBs4Rn
9x4NlC2Vdd64mweBlwsw3Pou/HBXjWUiYunHRoa3JF7OLT2133XGUTsg4iF8mEsUkJcXLaAxp/P1
HE/VFPzbMNLQu5b/2Zn/MlX4lTeMCM6/mhJUUQoMR1qlh012umq5xn82MzXiJFHE5cKC0wVPuFdT
5WT7hKiEsLpejM4jpqY5AYTutg/Vx3DvZJhdZrDtR4cXBDkzXi07U/9SxAK+az/21tuIMT0cJA2a
IX/30MfH6sIaMw0ZyrWkX13t6Mh8h1k4nyz8qxHJB+vZR1kCYgHUCdE7wgPmqrtbG5rGchGtFcvc
AIO17Qy8sIvdoBrFYhUgMrenostEv0K8P6DaUimQ6yL+SHD5Hi4JddqGv2pWCruOR6NEMVsqXuEB
BNFobxBZkv4Ycdof6PmL+xOOXYARIhpb7ICbMdRU115LIOvGApB6JpdZtxSVu4cKmCqhqK+RqLuB
IyPUY5xjhZ/VJOjXXLN4R1H7UpRK9RyNyHSFJOAzfIvGAP++HKcJ+RRa9Zwum3SvdgjLsgIrmZjT
hlde/xqvCHTt4BvbKTjGlpHmfX81yfO4TSkOuH0lYNfw6N1DwvX7yz9o/ACNp2SmmaSQ5ZxCH1tB
LtKZ6AevUUQ16VsnSt1CWGpo0TikjDy5jiSq1yzeAdoH0hBpnessjQmcCpwtVJTD+QmaEQTcDXUP
HIjb4hpZRtrsz/CWQ8Oboh31i+c224FZ+V0GksHL+lpzQXcIHBNXt2X28B8MWMWgsLr54tgCUU/K
Yqx5WTu326BhNLrWlvSz/71MEtRKHzGkulCpFE5brhTRINE1anof0X+Pnpzvw2GBKMNF0fseSx76
SkXWvLxmNp/bxbiDZ8D7Wl/Sy9Vt37dSu3/oPghHOhjZo0GurUYjVxPPFmMeNkHmAwKqE+EmDw+R
lyIXolNPwXCH5/2LIoxgaHgFmzMUgK8/bYD8Wws0MTU1N9j8vboYQR+uHw+ZBfT+NLf5mddAyQCX
7l5ZPcFvL0VYPAZYKugd7peUT6zIgDh6mSLwenWq6L93iw74IAip2JD4GOdsv50dFeAzy0bGZkd/
pRsiwnDpSyVkGig31ilOMyIl6cB4blijRD1BdEWY9Zu5xIbVIp94H30XH+22YjL0OyMzR0+7G0b+
K4c/ziC5TFlvC8j4YGsJ8sZ/cAIjkEstF9L7sqFwSLX+eSaX2d0LV8VPXp8RVOd8lloZcs1LCUqM
7JHnVQb5aksnjolwztjPoX+99L/EwzNJxSZ9sLt949xxi1DIw1mIi2GqzNaoVpb+L+HR2xVl4MD/
zeQaFFHYd+UuwXi2Wy6e5X4XaaPci4S9Qh/7FvKMZrN1ORr+h0TNyS/DRhYOaStW1FNV4B6BJo0R
pbQPf8cRW5g/1UYvGESO9QLRRr2oC+Ap/JvDahpsWwmqqTuDy+OKRFvCdcEM5PdJrR4AFNVFgsct
MolEUECdbgM85u/Qc6zuDSoTZ6wn54V5pcyEtc0zZkSV6W8mvn1VvswGkVh8Me8jTzO24mofFyy+
p/hcWIG92CpaywlmdPTfIhLxYza2QvSOVnz6OXqnOJR2y+AK7fSXfLGhJro1B8qJcfJCYoTK2JpD
73z6li/8AI6uvxpFN5gChLQu4Anm6/eBaTkwsTF+GcW9ag8qc9Ri0aHOO0BtlHnIEoGNNWK2AsMb
A0FtfCGSaz2siEQ2ny5tFatMo6XNvmpSK+euRkVOR79c1T5bVrVd4HEPuiazIAdonxhG72/JxVPv
J4STxw6WNt+v3fzXhY+1/BQzuUY44GPW9LvWShHOs8TRhAcG1ULtyjrxlCm6zwV86fRN6SPNK/eJ
SwmZWKkHCxNSPAQmrpSnDQbHnf0UH3tphYcdQs1n6iUMiUM4CeOky0QShQGCtQ8UXOvI0buwOMPC
ykhXI9IMHvs5ASIy5AIAU1l9qnE/Yzou0Dv9MFkyShfHvbDgjFzScqM7luMw47BXtqg6BhfK0k8Y
Q9Zroq/LR0mK0fNonWa/+swYFiXclv6wAuHu7gyhpWYWtaXqqGeo++eJ96jDTjSwTYGyn7TapAMP
SDdwlniX0k6V5XGVPYKDIWHL2dwYJ8bVWYHVNXn6TuZAxoRfwisjOWyK3DwQUpOOe83qhpsNcNqE
oGjvBnlHlsy4HyeT5val53DfYdDTK5EF+rH3z7f/7+WohyfnK/Cl0CFU67zsT3CbpR4maGxHO7ic
wGFWIPsY41+u9sbrV7vf5Bcok3Yrs3kfJIOms/5JHZZGzlLY8GnG2iwSQMjwqgR3PcQ8L2AIcuGW
wBZizFhDsgu9vJbEQjHxYWxYcvPm4oO/vp+KWBd6+e3ubW7SWe4dHbc05sdopYrVgIUr4VaCxg1F
vn+RQLfxhGJIyD2Y50QmAC1c1maxF76scln2KIMmLyQs7ABMWfsyJ3TWMPuYBwfuGqXCNylC3vvn
3sua+HUKQNZCC2MoRtMUYhb0urrBTjI+ypJleHyzK11avSGzaBfTrf/Nrmq2mZ8XPZ0dvdlWNDlB
c4xiTicjG8cKx4UCpQ6c+M/3XNVHv9dBy0FjKvEi1Guyj1O00lBJvqSRA964MvQrfxk5a7yuNR9o
+vxRGlr9DBgGk12eMJ3uHEcLXYu5PwgLQ6wiZuRRWVjQqngL5fMUjhy0XozLKu120l8uGfilj5SE
7BN+P/2enNXg1zQCIxNN0G7pJj6XHR3jTPswcHl5acoBTMyxYtjWNi65SadAVuQKm83wRsUia3h0
C8LZjbWjp+LQloPZy+Zb1hVFcbm9zMx2gFvf8uaQ2K8I2FKDtSZ+uk10S11VwFghbobRfUVCEQgu
+dGWft4ry8cHs+3oQbhZgWVWDtjkKbuWkpaTdpnZ3V9xlmudUMXzu+mOR9n8lJSuhDcBNYZWQbFS
G7qppMmSamUBQR9t21H2xmGt2PzVR8ezdk8ie4e3ByzxpWDAuxdvX3/FAuJ1WdiHTwRTrqsQ2KGp
eW8P302KNx8O7AbRZv/ird/7FIRzgjzquwkkC8NA3fAIVlSYc+4oG13YDk3brJcKZ9YfByRL2jK2
41yu+uiMz8igyog9sxBXIiSIUIU7zzQHRxrEDUCoDe4Pu6cVPR8lC4nsvhZvx0p86WvSyHUNFHeY
Tq1Px4jIZYyEzoQkDW2kWp4NMczln+K93Y/gpCJyxRvvBpmvzRXr8AtO6Z8wM5kNyJ83PWT4lNMj
st7NlyZ6MucLcYOLD4BFVKwNEX0Bw7gfj9jyokGz+Opt7xGsoW2UcYxO8funj+DCaYflY9zBVQZx
irD4x+xc+ROmOABN53X1o3BVERYA77lObiL7FGpmjRxK+0oCFKAP2boFjoXv9dAkjzB+nO8VHJJS
Orq6tbS6pfh9Dw5uDXlNCDvPk+j6UhPMTkgho6w3zA1aC0xFbNbtOEaKKsM/0hT+XfGTw2Cgnac4
hZpKWAN+EXiq6XqIQYoveuvJ+V0VzAMBMAMfextvK32DCLu2eiMZV/s2PQ/tv64ekrCUTSUMf4nF
UUw4VOZ0C3crlQ/8WjCLtBjgVlmc5kUKziou7du4tOaGRa1DQ3m1QCLbJnXUXIu+trWd2c9Uy9Xw
iJsg5O5imX3aOz2FJuqdO8dp0fN+w+wWA5sU/KQOPUqvAIm85f4X9xSZzcjqZao5ZRTyM1nCbhmA
ynG8UFFuKTaMVCnEdEJOI28aQN67wtD41U9sze363UUcluJd1mQ6gG2pm4qbNsg1FyZOA/qzsnog
JJvXguvM54dk8LHgLbTaEKcrpaJSYE39SrwVZna+q5y7/qeyqr8LBuWsMnxDXSo7m0CMzoxMjon8
j0NrpiUcTSHzOUrlNHCt6WeFlcF866MT+xVuGF16nsX9JNxklWJ8vPx1XmFFSkSmLlQRaMtsX4nK
a8a+8nXTpXnjPuotbYHH/jyOUxlsRp/0vsXtxQi+aBH1U6oZhwhGYZDvcpe7mCknnRg/kkpTKFoV
NT52HbHO0hNOIlsE/YjXohEAM6MGxA9x1WUuU/cZbcfuM2NM7L6UlJmDD2xKNW09SM1jY0ldk3wX
8DtXQe/hu09F1YSu0AU3Zp/SRYADxc8P2hnCQW9zvVtjM/abHTpd9PIoLwWQ/sblZt6JLWgP09SO
ONSH9JVOWYJoegsMukTcP8Zw0fDP7UdF3s+ip5HY6AImv8ronbiokzIX3r8nXZlKkjVUP2cNEOPj
ZPdGmVLS93qq6yB53m/jtWFYPI3CtDll5Et4J2T0aRwXCkeXBO4tO6yvGSu0Aeou8CQJUgbEw5gX
0uEhk9uY+Hn0fu2kVAKXur25KQQ+UZy5mwhltgSWBQcttY70trIcJohVOhC2VB2p+JfoNrjpp/b/
ty4i/XcstvER4pDXxKeljytqDPMiRymzHF0/wbZTkbsVBZkI6QGiPj309OWl8qB9jkqrHyD5OB0k
FBIGuTHF70gOvgFC7e0SeWF2QdNDOoSfIwJvAZzXVPyl04h9IZrISAzQ2apa7jlbA+9zr/AfHQj7
KsIlrnSu1Nm7rfmIiPhEUGo/T8Ihqpm0bZ3B6VHnLyKNhsMnj3cUWCHvbi3h2D83z4jLgrgakvXZ
n+coQPmEK9w2VIgHk6gZX3cp3CNEwDQazRpYTy19V2Le8LbYBTVCFQrUEMN6Wsyq9/FF72iHuMHD
Bo7Dv2giXu9890g5kyoCnBxiz317Kv14GoPEDb3/7xceUnuFgAM4EHjoDuVaz+tSv6jjn3IzsXLO
0ftGJEhuz8a8RQtU0dJKPu7Hl0VjUrwZGha8aIFzZbgfq2dbA1Pe3uZDpSTlDbkOLt7RHElG9Ebr
Uqvq1wDWtacUEsTAqq2g0ygIZC33iQHfyGK8WU72ddI+T6bOMaJeEm61JVSTbXrBF3WvEGa1lqjQ
ovbvG6K83C7Tz9UdMKqWYrcb3VqlVJeg+fP0pbzbMZvI/VETy2UQwuI9vzezv+3pxJCwRwclvZg6
zWNlVuywCheno/e0AecfofKWLzPTHUNh13WfCHfJmsLQBKnLm1IhitPKapN+gaEkVstwMgJ4kMbg
0cJMUGgnjWC+ExgPx3+fVjZyg9Szxh5qTv4JyEn4Z4DuDIFmBgVLIn7pwo8pYJq8/nlDi+MrQzSu
mEI1knffJ0jtBoXkUI1G8qabr0iVsHx51lxY6ECf2X/eagkcg1mPuHGd4hjIW3HW8oSqoTx2LeUr
SHbJb1bbenQSdSBsMxfn+JfqDpUalUVWr/icTizu4wtCvzj70cUOs48DVfkDAp3hWjQbqvUyiiCO
9QC7JlRcQW54E2eXbtAV7SZooFLKc5GNEgZSqhdBLd6/MhKm/C4kEHvzN9M5bxH1vlxXmKnE/0zK
UfLcTNW5BfByu8dl9GcEEEJ4ZxkY0romSfQmLiWWQN17f3ockid4lufqjjAaTB5H6j8zIRygiQt/
GLXwD1wHsfkCgFMmCaEXOCKsRJl+dDrRBLBfKF5ed0enT9XMnF17hGCHOwgCzr5mKDJ8DGF6QuHD
5SFuZd7EpE1Cq4MnaF9qcP7dx/A6BfCjyqkTH5dx2/HrZ/f8EM/yNaPF4idqvcqH7Rc8DeshsqGs
DDg0w8utl9OthnOo/9FOrhjq7j7H5Mu4HlBwZC/EHH6AFjmVTndMwMOYPUjZ+Y/6wilo97rqHldK
1+58z/amRAE8pajrv+3ylebqYUHlHeP0I9mL0whQ/JXyuz1NmmdHkmWNcwl5+Ugho4qf1nebdnYQ
JKl+dKyUJsJF0MjrDB/2xPDXr3/eBGlYkPv6XBS6ca9ghAf5jqzHOBXW474NSGet8AnFmgXTBFCH
raL2lu/UrMBxLkUqyNyVz4Oe01g5frR8+R9UYmzzJOm6kytsmdysCvTyyvi+PLbQxVzJVBHBjm7s
pjZDbPt3oN0tjnMWADInUwC9KuXMzCbCFZ4xBKVnEi/pZRI4O+9edlmNJP6nRPnJTvaKxeZx5Bvq
g/Neg8DVjA+4WDQKsl2YO4Bzi/CX9O0AnfcYIL4dEB+XD/G+X01m0TNUAF92HyRTZwejMZDhrPOf
D8w5XWTy0IDJCPkMq4e/m/plvB9BK8LQkP+h1aB8of/p5aDRvfYNCBD/mk7RptYXUfot+qYQzIp8
P5QZrw/VGJseAELdxfQ0A8M2sBV2bU7qhOvFYxBfreYybhaSIdluvzmVE4vJuhWMbZU6AkNDuov+
j2ESD1CozCNzoJ/QbBvBj/lWV/5OAOBjBnENTUWzuKh8DKbstVAPJjaLvjLlrzYdhLgVarobP8ms
j9Ye77Jb/wSMbGwoRGGtv4N0akBiiOSg8cMbD4UWE0GLuFPOTBg90f/06J9mG+dvqpm4bv+RJj6x
bfutgkxFzhv44/UmLmwl+yDFMOVZ5EWlG1uEtOVCEe7YJ9/FX6A4aifdPd2f/FFhhMMTold6b56V
Uw5hwHHLIGZLZmipMu30xnrzPd2+UgrAFIzSsC+czXw42TI88oZ+7t3LjikW4Hw3YVOuV1KvQbuG
2K06Ed2UD4zCj/Ll7KJu9HhAzTGbUiw1UyCbJmR2m+ykV4ffqVgd1bm+FCklvegEQHkA1cgoS4h2
lm5QNkOh3htGeuxW/BuD3BFsHyXDCGd0YjyL5STcf9zDPAqIEeXYv/rv3XFheisTWZEqw4fPWNmB
FkWgGVPfwVTzYhEZYW3AWO1gKKm9/zzbbZONrJXdUQuwvSaajWlAqVQc+Gt2jr+TmEiiT+vTZ2c/
aAPlan+ALhpJDgCu/1pT1+g/8FZ3RvX5EHoXxoiG9u9pNDokhZOXgzBwzhze6B/zn7X6cq/LAHcd
uJpaSQ1rovIfeLFqzuk5bCNSI0syi3KpVKrmnc8Cf29PoNUNely87Ad716pTsaUIC/zRV6vON+NJ
HFdIpPRrgYyqtR8UC0RIc9owmWKkOVrc851FhLbd/yuRMe3K+CfFAuGw62Rj7b44y2wSkD8tS4v/
GDYIrL3TxOmWCWKuDARwhld392sLpztNjeOr/f0//2sMOvOECVzYBMRpcciQhBK5ddsLwMjWSiDg
x7pVxhlWQTws7bMenwmwgGSoi/E8VO+egq+GPYYGktvv+SldPCA3+Bk7UZTW7ZyCIJvg2GnSUuy+
Iwie2QiBIypEDDgbVpo2BKXGgtKQlCwKBqLiBtmpGO3PA5Ll/zBDbL2ow3KTBvEBX1YXfN6clfnQ
kpB4DH0XgK3lsQZJEl/hnap1l+6ZKAlH5gVnJxVdGTWazjRsXuRnQaYbn6xeeas7MEYIa5xfxh++
sReoy4/gRwBnV4LCOIJnJlfFfuH52CKXRYNvbFKjnjaBedeV9LSfBHyiQnPQNddP78k/LLdvq+Fv
qpU/uOnM7ivXR+T2NUWcBxzerQHEEu6wpSdCv0RPBsgoSnfroKw+q/Ca8jnem9JdNPRQaCPhbRjb
dEGYpwfWo7l4nFlidSN+eIHAQFWcCtv/+7kroTAij0DAMQ1iLzNObfhXPkfk696LsPXR3AeA2tt6
Nw1rTmNfk4gnimMus5dAE2w36CfUnMQntzL0Gs9p+oESCQx8pXiuu2a1TcKPX581VKD9RSRfPXp5
o/n08eR58rV1Hz5LmNExRxms9UEoj6wQllSTsLyr9h2fWKnoJK/j+kC6uz2tVlxVvn0JrDv0Za5N
ARSVa8Gr29XwE93n7HgKE12Gm3rsD8eLS0WtPl1qSOdHAtK16NBBCtFjx7XFul3FaQ/cZQyo5AhF
35r6oYdnnFcmJ0WPOuskIughTNWTWGbGKJXJkvr9NCC2V2SvgPUSgSGsBTjBZbOV8egkLuhYaloJ
QyEBwKoSTKODh8vH/spshDmOFhUbshj1xOR6JEk1zDBJ1XsxyNaR67Ld6iJ2pw+DWt4bCtoVcUeq
WmrZQr5NqucxGbDz/rJKJVDjZ0COshCnnZHCWyk3WutT5o3lK//N4OB68VFBvMNzhnT+T3kzsCVC
bATrHPHsk+6FXQnFppEMrZo47dEH/iYW/jwOdcZl689CSJkDtRg1+I5/FDpS3ENACDvLAdFQQ5LT
OlR0uB87s95RJ5V955aHFGm7vEjQHAk2Yx4xwVi1vAHtLPYDyPeza4siLego8MWV1TIDveIyI2HX
SKR8bDvIvBHFd1Famh6RP3tzWNSA1XmlqB0OhlwFISPCisgct5E3s9kxv22yuOX3GmF+tHT2KgJq
Qa2Vxy5A580xfl6uL3iXM29mho4DK1dYnqxHF/dU5+YDeNeTAV/c8KKzXhr1Hf/cvnzGPhznekA0
p93RVaxdDD15m/Pr0wYRE1tjVHxZo9usaMMntPKjevTqBmyFI2U+/DG2alT8BKtN0Tp7hEDnPpld
SI5z0yd2XAQJhct9trFd4c6wz2ogEu+Pt8MZEqFLP+jNXjVQ4+im0+I0lM8bybRYxMlwfRdmKa1O
10ggTE+PGvOlY0tlKAoILVJ2vKzNiV1F5uozsOe0KJcImK2N3fnXdUAzMt9GFS2tC3jPGpv/Jbgh
2F5rooxMu9bLoSJUyyJ1AgPE8xiYVchGYbj1G7I18rLAEkuhx7ceJjpAzKTeqq/3QuC/pYQAnSIC
qk2q3+bIftr7ter7yPVNP8Rour9qYDoTYh0sgT0EzhfpKSyn33DCfg9/kwt0Zjj4nqrlhVNlQ5lX
FYyRUsmHUDYIwLK+L+MIKovBOJb7ccC28TkpZbzuTB9NViP2+WLBK/nFynlGik373qdhk7Wq4n5u
qO/wUAU9g1GzRkc6oQ5Jz71rDBiTbd4gKpXRWLbjcEPuhogIJ3MbSEbicDpsnd2b1r7kK/3yLQfi
vhpFU3A1cVL8U6jHWLHMuVL9l+0WoLWBMjWUEvx8fNt3VJqga0hyaNzTLHbIyouT0KXzhPqR72d/
r5rXZaRgeKXukMAPf/tbLN7RNLeUKocMPMYQa9UATZ08kKytA5VPrgzu7fTxtsSXAgBY4BTk3jzO
ZIkCog1TRSvuyTzhkTfHTvZK0SrplguECghoyOhTe1YlnzImNCyu2tT4gnrp0vgaT8AJRylDBlsy
yNI52GlFReUYRWTRZNABZuc9i/gT6FQ5UJkXIKrFMSukNs3YKqoOr2ut6Ga0rscXyTuUpoZGqrIN
DvDRUQ7MXgZ28ld96uK2KUGgHaQTbDQwEOwXDU84lM1IRzWC1WChHir1HR0i603H97NvIXJ48cRO
3LUs6G2CnjbQhAZJ4Dl8CyQWq6njmgAkHZv9l5mLF7Nvo8nNbyPSW/QDLQOzkXYBQZwqyY0FcNRX
709BN5vnXS/Ed17j4UL0eBoNcxFMBul04XtltflqiAQ7VwPc9kzCU/moGYCUBaQe97D8HN3lHZof
mtz9IdLeyZF1DvBMGjvTNyP6Xzc34Vx4nJUlro9T1hxHotCCWpfAUmRN42HUGeKJkk3F4Lq0FQRA
UkehmBp7qSbWQnk4qIH6P1aS6xbFoY70QpI0sU44xOENT03D/rmakxvHYyG+f55M5Z2c3gGV90Ms
6UIOOA0ZLu94bLWZxEQXnPI7aW7ATGaTmnXQA5OQP9oUAXXstaoXBHipFiLSe572xjoMMvC3sBdJ
Cs3eGi7+SXsaWZhrV9oSn90R9XSXf8sXrvA1OJCl5OL73wak15sAg1RBOHVXopI9KEMIb/vIYxft
DQY8j//j6fIRbH3KHwbhR8TITLkVzJ0aZw4WoQv2vEyR940IOFNy5q77m6t+raf1JbY/1d3dSbqt
cRLdH0/1KwACRRV4DOlYl17b5nnMkObWOf6JtdjFlwaad0qhR5qdS/PJKBeL8V8WhSSZjfMNOe4O
h16TZy8bHPM9cRhfBLFXHxFYU358Zf8g0wRUdF4xGYXR4TLipOaCggb4aoTOM2I7Cp/CUA4rkkxY
rC/DbdkbOwXIJ/Kxr0+Cc2RH6mSNHIAcMFpB26JeW0mYEbpktwXdvt/kmWmM6nshDSMZW20/GryE
/Vh0283NWA9+eAHzNTnD2hLqV71bQgeU0p+U1YgxPMK8HNOHpgJ+zLcWB0abip/ctv50+VYKmfFS
Xm1zU7Ing5QIAvMsTyYcJDtfYo9LOZrmuaREU/zSnnpKQMTHRPn3JYOXeQVOwGDw9R/9R2z/q1hC
bwOinUuX5sBd8m5V6B7YJNTFV6YCIHBjeJmfHmE9EGsnAHu46mTqyTOUmMTl/0I6nnH78OJjAAtP
SDWRUfZ69N0hSBGwqRrFMpdF+jRJlJ91aoQsEjKPl5aJXfeWKo0vhE7RQvwmC6Uois8Y0pIeD9F+
A0gO0hOlkURWv34eWrQJauvRk2mwsEmHetNv1/6GPP6VIq8x87jaO2dAP353KA1Add+LJsDJfwTc
d7vAGiR5GOxwl1YVZyJd78P3PQmUEPBbimQJLLBjAwmydsIVoosEAKfiawGhR/EAryW6nc+X8e7C
P0PP6WC4TWBCW80GAZDB8m39K3FpCWHFRpYNX8/P3Coz6BLlS+7+U+Pjtq8Xn5pmN2PSfM94+ett
yL/CLJ/JhW0z7Fhlr5O1mnUNRTiLzOa5hAoJbSc2Orv0ndpjjL1gx9jksTIHLEmzykcYvBI/ybkZ
zcCUCbeuLg/eVeiCYR3mOTOJYmhlaTAEmFDNqbVqRNs9Bm+v3Zia0BnLaAhPjJRiS5D/2nFsDd1V
fU7Z7EEuVUHX4t4s3sMOJauVtCEvzB/ckT1F2TlrzZv1FRdKSnYjOukF56RoOhy9iPzbdEug+nQY
hGeMIO/XsEFzvtVu9sSj3HO6XGYty5HUkf3/ITKJq8ofO1B6chcO7KDn4U4QOYEv1wGqNtEoblXh
EvOqoTVt+rtBCFZsX5JFPgV6C4c2o2IJ3TL4aGyqSnMllk4DR84T2TwoHNLp26T8fTPJivCcBfRb
8Ziu1dzmbK/gH/xl4Xth6is4ayo6tq6p3cXqAPyFGPvdvujOrlqnfRB7+8Zwur2SsMJ06LT2RQzf
ev0MjULNNzbDSJaRswPTpZOOi8au+HDFD1XiWsgOcDTgvGf3LEz/pdA+CJG0aOipxdFYheT1x/1K
F5J09NwTKTukzZ/lGUMJrCw1Jw4NhMbAd+sK1k6PVwryhakdrwT0K0V92oIUi05Q/rodeOVS/7+a
KzfmOMeVtaLne8BLn2WnujKXY5FlbpaWXPDFmJAWyhFy4lfbWk8UqXdKFC7si2MHQo+QDQKfXnwA
FqzCIu6t0nl3Rz3GD9RK8Ex/BlRokUAtkSHCOy+ngUV4DTftJnY6jyyryjURIKjU+Nvff21P7+LB
/KuZVbm/NHKikCOu+vvC9JyMYqydXG7U7yRacPOHLXFWjK39oU2Rc58F613LcpvZRdKRbqZ9JSts
gyeJyd9MJFLOUqGZby+LEUjsgMD2ycKnjuGcjF5jlw5fJ/BQQn+juwVoeEalYPulnxYGtn47X7uW
xoZDiaYoBpTuydyESN7MidNBYdmyrYaK/G5YyHUboVqTJHXK1oWU2qAniDTmsWYyaMavRmV/qCwK
CWxuI44E7JGcgvi3CMZ41nllszfo8Z0/bH/Ddq2S7sfiN99uoOhIjpA/9IgC8fioa6wc8CTNjAjk
BkjYtUKzo5hfnxec/6A9mcueJxZlpEHlqja6u8xX8CM2FQWMSaV/xn07MfAWapPVwGXEZWVcD8Cx
i8/VDTXMGw4pwRBkJjfHyfv9vMXA8oGdQSxui3yaPX3+eGWk5kwFwOyT7wdEjT35Tv0QAQkd7Ytn
/gOGn4faawN45Cup0J+N/5LlkRODD1B35q+kev4iHMVIqwnSdwu8DYbFbFZglORF26KoBcyzr6Am
zb3sO0gQ/2pQBeEirhXJxnvJlb/pPjmQ0GBwqc5ySBn/U0uo1FjN5cylRGBR/tGkGqU8neIqIdda
d/fCf6ziXKJvefLxk2VSLgopofoJrEotKVl4Zr7MaJsoYHcGBQAU512vuEHqIip14S9XOwQ1DJfE
+a5Q/oeWKP608GzUq2+/M1n+x1SDHoaH/7U1XhzIlJGGP5m70YpvI5lDNma4Ed8KikXAzcehbQ2l
uOWGVJNp1ANjBqxyq4WvE+gjvuf6s3OA6rq2qW7xIpyMKNLJBJ7eMWY7MmGY4ifM1yzbp2zycmzY
mkEmUQ07HiYktpMUCRcLgnAHNn9Goe24xI0eaSISMRMHPs7BgLrF1s5nsCycnogKabXseNLmVUUg
r0uw3+s3UjCWoZP3a/adZrsWCba2ShpMjbtGcZ0V5/zF9V5eedy5MGjiwiI5ckmyp5f/fQdrGAyN
Qm4Ho+aC5HZndoEO/j2yo553Ei8Rri8SetBzW8q6nSeGWuuLVwUwNb4ryIsLGFE08gGToaeNUQhl
wOT6XgYvMzmp2HcJPfj5UYr0dyTKPOuSKQ134K4cpjOazcf/b2Vtp5Zbk9sR+WRHKJoeODBoiJyg
lpCXGRkd5Ueg+adeVFFD4TK3iGJtjOE0pTUaDqGYqsg3JqLBRxbNaUDw3OIxgLu2m3xjPq6XMgN/
0/2asOAXbKTa50o36SWnjTOd34PQ8lc6K11b53eR4DJ6PqakTnj71Ta+1Rh0BPCpmgFDuGbfC4Ne
R5GRFVdVzJgHRNfEqMNV4UNk6O3uqUHIStCybGkAJGxBx6JjSQfjktC9pg3ylXHXwDaJQvtZisH7
HWYPDAhrHyJULNCtd3djkCV9cTQTCiKDUJKrFl8t3miVl52KPBDSxbSSkiFOw+zUAnBk1VAXtL6B
OfZrdQMwg0M7ECntoFy9HOEwjviuNEkDbc9gGac62IL85mpW4pEPHqS4W4SjOkvhSjxOi8BM/ng7
3YP6gypIUvzlGCXdyS0+zXRwvUdVvIZrK0fAZbrm95nKrXbVbMmlMoVP+oemOZDspu71QsC+dRA4
+Klr1pW6A0yX6lQgEVCGnp8dDMOJ9baYbMKQ21vr6ho42wO0a11fhhWJ72rKiiETo31o8NwSbP2W
1wCwz1npy+d+uT+eMNxMQkVa6ofmJynblaYa96F7WS/F/+V5ZovTZ/MB14NYKN3wptv9swG17p38
fnfh4XcmMNwdgULr8TqhFswnn9Brk1aZ+OKP+NIl1cOxrDdB5ScwRt48r1G03OsktX47xhhVEIYZ
1myo+7s9w55g0h77dOLEQBcj5IgXmMSvdv10XFhAGiZ1sxhx8197vY/WGhcKldIEUIhJQppyhmvI
FpnR2j/yE/SL68NrOlzk3BDjJstHn/u1f15sIv0wOa6coGEfQAhfaL7yv1+A9V5hRGWymA1YdQPd
gpvc4K3O5r2E3wNpi1B3C4YepkGsgtmKPez5AtGU087LDZFrY8GrLP1plhRuI6j1KL5QscaFo/ao
zLzNmJsDw6FgfS5ARWLVlSJMTHQp/LxAxRu8jJrrx9Qfg6XuvEqFA2ZNHfhdXnBY9Tv0J7ottYzR
iKONLz+Zkl1cUxCAbc1XgRDuLRfT3Y2C2LySjsgHopJFAHRgetkj2jNhQIlnGgImJ3NeDvmfx4mT
Gqe1D9d+EwStJLDZA+4FdiMvWvweNhPE9+YwX1G9U7zQiCo8L06Xub/1ZBHsED2tkIGreZ7VJq6k
7C7EostWpH27TvrG18NNYdwH+VG68dO/jh+HsOI092pHpos9Kmp48PqhTe31Ql6JGxm/rewr8B7b
y2KakxYzDfa3jPQjW3RxCsmH3i/0Do6Icu57V4XgG2yq4ek3h5UGvZIUuPNiet9OnRIG7vbAY0Hr
ZvkqV3qglzGxd41le5Vdjw9FEIokN0kvtimaPt3aMiaCGP1itAN+Z3eo/Dn3KU5zWE+kdoV8Pu8X
awZUluQ/qaShphWRDRWZl9JxcU4K7mnfcAfdX50mwlB5gKI4GW056dZVJTqJ45ENWy+uKui3mvPI
kHASDFCfqy8JZywUUOdgrLeellx9/qj2i2yLI05wnPaMieIGndX36VOuQbFLmE2dcwPiDpxpd9Hu
M8auWkYRZG30P4y1Rb0caz1woZW/n2cne1Afvbgd76zoTq87IWZeXuAp5DwK/GgBRYCdIMBw+sYn
uqy06G3tdNB0jWe5ZDlnvLChUP+MVrZTqYV5+QPuKpNMXYADnflLEaejndv1Ad/6ZqPPePlH2bsJ
/qsEkNueFi+gPWIR7bJbG4NV7Yn+OrXY7wtCiSdpnj/IW19qLsyCUW8mRiIC/wHfGL8SAVto4U3A
1CmUC8AmgfywbcxPnfNSnpXbAreo9LZhpHVszXX7+wJ4FBE13jwEpbmxRvMXi6UgQF7NRUntiG5i
KWP967h3m4CdTpVGii3Fr+k9651nVg85GfUeWI/oeaoAw+JpOZS9AN7MpUzM+WV0US3yZpX3Kedr
DWqyWYEO9d44EAC6ZXFCkpjrnI+ToDBYN3hUyPqoV2M8Bnqj7y8/qQvHiSlybbRwwih+HCN3T0QM
YX6CfWCDVVqxoFVDF/k985Zzir6tu2eQ9dB3mDjvsHY+IBydzdTcWgO33uyswFufz38og7v3SOXe
E8r5FqLuBfu3azpyYnzjms+lAJhe6NDk/HWRgAEhvIh3AV0ICfnetdUP1dX92d+2h3uoRsrUmGbJ
UOvErLut/dVtBEs9fKq1loFuex825z3cqXYHrOFOBp+Nf0tGKQCn2TmCMiBwR3EqrAHGAzNVhlbB
tZ0kU7tRKuy1QmkMKaPE0FQqcu8cLSZYrwVcxyt/ZiAP5nuyuUvoAPYu6U0am8wCPqpMWjmrVkyA
RmYhqAbXTJiJSfpPS0/0Nhawpw+R7E+HtmS1MldyzdPFMltqICdd/CRiKuQS3pnBarZC8CjNYCDk
O65mEMQmFZJ3xty+leW7ZRO8fNju6u4iQmYccQkP6MSqJkBhWmjyCeJZNX59e2CwcMhKm0mgOLh0
yukSyD+6Mn3GGc/aPZ9Dvr6DCtNsSl1ItgHHqUbCo5xdI0iqyVhcg2LAS7s/Ddoy0BK0dww7GPoe
br5jPoId8bXhYbfakhltVADxNN7AfQtXBJ7g9/wkmIVvESjX0DDWRPfNYgZdSnVPcS7iZ8IeMQT9
sUyLiDFNap/T/auzudOoxEkJq9PMp8Dov/cgv6AXmQ4t759SyOChKFgIgYLSJRvfz+5BlcoZOb4a
Vo2i0f1CpONIxHznodAAiN+GHGTkxHpdxloY7Np73Jua4X8o4smZ3BbBnVx5zK3d5Kv/PaPTPck8
TrJ1kupEEPU842AkKqEVbjnit4TYYG00+uQL4ZDyFv3Nbb3/yA33nN5D7in79BnQNTcoi5UCfX13
8XloxZKvnO96TeWiY2R0ZI0U5lz22dbfCXYsYcZy1KtXsyp/vHpSpiNG3NOWbHrU9SsZLXVac06Q
sCywNEuUE+PVuSAugutM3Crd0FbL7aKOSNjHuTAitQJJhPx5q4tPnMyHUe2fbpGZX0cd6vh3U4Id
zSSE13paaR5iowX6T3rLnL6nE7O/qttVH5Y4y7CaLJ0HZ4DhUdFJ1CK4QQpr00BVYEibt2eC6zpn
feqrF9KHCTtaN6UwkZy523s9cftaashmtqmbu2skEXuz+5i7YpvfEIl6G4fLjiGASbE0dQ8QfkUS
hdHaMIbojMFNICeBTTWKAgPARY5CAc1FaevMp4ALRl1Be5t+yIR2gThZ9YlpnDfTh8JJW+jodfs2
S7t8KPoGrcPynkqjqqa6Cfs8t9zXyP6zRF7Of2V6oXfaYgvPvNVFBtFHVI4kbL1hB+KjAyOJDTV8
uR5qmjM6uQseRjvIVzRI5gOoEPvXSCSWg68gfLfF6Py8XVYOTiWsCSYCYQaa0krvS6rDFP80F7Pl
QCasc2waLDv4rRLiXcuX13uLGwVzoYehPOGVK/ZOrFlwmSY6yCoDXwvrUINWomwoV4V3zwRb2UMm
0pD0QSpjyvTqSTrf1JgnWMcsrj2xxwjCERnKMzRieaaYbI5GwHh6TkZQVSpdEqnWn60uCGW+jiIn
rpfHQYRjJQ6LFKGK2/jaxIbkm6ty8TFi5Ocv56MgPZDOJuV8X2JI4nkOheE9f6SyPiO56C1iByFB
+vanfD/F1Xoan9ncjWgRnueH6Xc5SQkx7sDwjWv1/AfAIFvGXd3hJ4CI0gG1El0hZnPeOv6nEVqX
pEk2GVtNYXCxXt9+uE/jb4n/gBPk4gBDxeHJsl8dxJFXckZeyWlkqpY3O9BvBoqJvPDeKQkg5rxW
EGsHjiAcoaWLpumhJTqPZTgA2FQHjHrJ6387qZZ13JYvyygrYYID7//hZaVYxAqswVIA3/+01GPw
BAB4VRUzfdZBQUp804xKtHkq+rReqJvLrb+qbbPfhZVDuRUZbyCHJT+UPQSs4pvB88MirGa+kffa
6Fyn+r6A0pMoxdhZ6F+q09TTBtPXmCq4n4xscFbQN64zK+ZgRdl+QZ17/XdmyjrP9rm9QLF2kmp0
zZArBwHAD0Tsk/p1MxUHSP9eZHkLheSBX7f057q6rE7NBPUadzPRmWYBXkTJzqCLAKU2ZDsKHEZd
kRtJWpMac7EfUjWiYVFuSGj2SHB7xpS3EqulVDp4i1MmkswyOTc6mWctebT9AeQ1AelDc8vOovh9
9mR273o44A0etzsZCPbJqpjVOVQfJ2jzaqCz/I6lohnw3KrkWHMhe52dmGYwmWQpx2muDv4/XYFy
NROUnfE40hQPllAgrirICVjmKRl0bvRygI9jyUHSTQlRJlMEuCQcO5MNs+CD9O9GKo4QVfSu8Lky
RABotTSeew0W9T9XV+xQNITZ6YDwlrdzSJHYlint3Yl95rOrws0Wkw544Ke+wMSV6DrciQyUJYqB
Xrlived8k3nEcpoEIWpcWT+EoOskvBaZDDDOQPgJHCmn/XxTJH2KwAj1Rc3uvmxhj6bfeuPSXUqI
wlOWMBJqmoWA3EVpKf5fzfVcBp13knVa7FeWwS2QtmjxbNWAnuzmsBp8G98RtaavmsTjvWVqt3Md
igwhW3dtQo6Q9l661vWlZbvyziHxkd2/94D1R/A5Dtj5I+Ecz01XVnec0Nfk4z2kPpB0N7zLo82Z
54sha1fPyy0sVXO2BJ6YTsbrvIoKyADhVIroZfSY+7MPwFDXFZHefRMoWpPX8OP+uIXxzYQ2zmJD
hiQ0Zuw23L/tLlHfIdrlbNtJPVTSjMFJzwuJ/g+sMxi9w5hz80yhlY6RzanQ1lKzejgQ+59x8SY8
2exYLDNszJC7tu29S/HtfLHfyL5DAFpzsyg5dzwT1IfTfxh5SiJH6wDwQDKWYYStpLUaehcJsuX+
XnVBg0fQgPsAJlO9niT7TUjZXyRqcgP5l0bx15YfIG5s5T8jor22Xy3/cW6rnENVkrHmPGp6WDLX
mWRDwjccbZf6GtSKHGBRAjjy40TbckgzxzOXzMI9B9j9ZE6CP4EG7+reytPgCIxo5nYP4I3Yoe8N
wIhTz+xeZj19FD8ZKdJGrKNPbedopizAZiZ2gjsiaQGIf7E7NN3mpWYuTIEUBr3Ijjw0nb7Br0FN
hEHwB6UGzf/rcjO0g5Kh8S+Ya+AlfKYLN272nMpXRbFTzvbOtPAjE6WMhx51T4K0vqajPvRM00EO
ay925jcZqFQ+jFmx6tcyK16VnGH01bHM/4mvGwcZQoirLmEHkxW6Y4iEyL86P4DcD/B2YErfMsuk
fn0sQ0xEg7kt5IZid4MhVLj8Iy6gBOycTqaKeg1adbUs1VQyR/pKwArdAvc3OESfoXYM3t2oeTRP
IDIgFbGZZgdmDMPoSDBhhDBIEVklHkiH8EVov9yztNe1Gg3hUxljBkT3oc0XFMTyi+njrEN5Q0A5
SqS5t84oqNA3qSh/eArb+ggSYCbXKMT+OuOIf5J5uV1ldkSg8eAhtADHi3X3yoaN0jn/SspIkI1L
Xqqq5lMi6oZP302W1K37+w9s+GKNUT9vmxs2kdwPdszM/NA3bbfuGlG/fyc2S/j12JcfH65FjH9I
4NDvHBcLGcttEy4vBUEcv6D5HAPgUlxAlj8BSLqun2hOvTKP5kY6if91TaR5PyEYQGUkJrdJ9M/b
ZRYzrOKRp37LP5ayb6svJY75n1YyFwVxOSwy7J+t+ISiuOIwD9OWbBxCmkYZ8KUGXZvLhRSPV4gN
yQFT7TFUb9HL+R83IQCWhtlvqMnb0txOhHMWC03nmGgH0Cy9R/I4ocW8Nz/p+ckQS/NqFrzknV9p
qUEcFnGw/8WRo2apRb7Y/LULGrlt3vNB/GahjUMGwIGUpFWnCHa1v6ro3vtDLtC3wgwaidjdV3hN
20yI9SrACYyb7SFErQr7694qrwaP6vPYC9eYWW3C9x/mBOrRPVcQ0GDQtrCTkxH+LpXNwdUxZEln
FehP+fLhEZfFNytkFlnTOBAUEIQt2Dl+0GveIj9em+lVp+KGAPI3z9BHOmGfJE5W/OcDbJSWbznw
yDpPYN9zeDX5VPAzHHAV5bW0p6hoH9mF2DM8v6Ztbt7x3x/lT6M8OmnpPTBTaytvRKXwEaQROzDO
FqimjfFmJ3GBaMfrjXDAcquTOH+jYJ9JjQQ7SvY/ZqoMSkEjzJCK/Wmtlc4zYYXF1Rdv9ewE/0rT
BKWY60VDXS4TzMCDBn51hNqzzzxAsC12Cr5MVr+69mI29tu4VJJ607JO3zi/oDFki4vbKDKdcDO5
1O6mHS6MYdmbCcgp/0CN5LSVbhj8s9sbBlVcbYUvc4ocOdF1yEOwEIyjEXi60zaTdVSIcDCSSmmD
Whl+kDKH7gTq8NEQb+BQyaR/fBCifzCmkjppFULkgOQ9/gzHophcehgtoVP9cYgNSe0VRhjylSMG
4CHGsCx/GTi8nXrEaHchP2OpmHKN1b3sXclkz4h67bPeK9XbySVjb2pcSR3WrAXKl/yJFrDU3x1/
hPVWXmTv3uDm0Kz8++rJpLvNkRxqjMLVv7eHCwpb7DMu8tZR02uBxvYpLWKbaNsCaD05b/umu7hQ
ohJ8XPN/6PXqLPURYBKS8J0hCoSc9QrkJC18+aiNkW30jNgzo6I2NEYEr4qXBfhfg84dBeftOmPE
AQdNJC+clgmupU6kbUiZ2gAIV6CGvGFnOH+39KMvsNJT+eb50xzjYnEC3YPlEmUYFnAobKjXMDBn
Q3ePvJ9R9lPAS5U+wTepVtn+yrs/1IbjEUV0326RsvHcImXS21FPAmV5ttWddgHqEuHEtfT/RF/D
jmfimbnaq4hgL2vPLUAy7J8jgthK/VkRoQvMtV1sJNph3VzlOy9YYLIZG44DkMBHVoWjIad6yEeV
t3fzqj+x9dJaAtbY/3pREEklFQik/kqyNARuaJl+7jXaoJbfx9yKDb8GNqQDgluNb0bHIcIv6m+0
d/1+W/MkHNBgixGShqfQs6HrtUFWQUr2Ylqb/vzTcBqhu6/DBitaCm57XX6AsEhWeEk6AwazaS29
4rM4yPZJD4niBNtC5o6ovyHUe8hjZF8o10u5+BLR7iFS41+1rSmzi+MyAIEyOniiJgDuZEi+2muY
ThNFomqdW2fCAFaG6dpsN71mulBo9c169tmDL0dYL8toq+xc03TaLgGzaxqXbgU857iLGdHa2iT8
zhUKSR6VL/42dN7ysgpe2ky8aL4WSP8DONrOBGBhLbUyLClwMw3GSQ1SeAJMwMcWHdswAsFUquad
wUq7KiZxNb7AEhjNg4H80dnHllmVb5zh1/gTkdwuJ6CeL8LYREct2Flv1UaSXCvvm7CRAi7mt8lP
MPKiXGJtea9AqC7wPFIp0FHevQ8QpAqtxkqTNXAYxCI9nccr0F0+Jli1IXjRv7mBwQrONmZWfDAU
frTnOdnRhN1MPGiBw9l9VToihuflfwvT2YS1gfhsmv5h9QC8fYeYoNYbKnh0vCWywkFW1Sg8AEvy
dOAZqDar9sKtBiG6BNYkeKKQdUZZpRkJUm6LCRLO3FNkzGTRWrAhGiw4IykieehcnpXpZC4K364q
YyVaxHRpAz7AmOUgeNtw5OYRHSQ8o31/DydAUB6CKB9jHsY6BFo3NfjLTQu03mPJnBHnxXejt2c/
ga64qLc0FO+6tHlofIqTZgT1+ntxgfC+a0wH8NJM/R/eTKWUeSXuCycHbtwJ04b3f5hH72BE5StG
vBWAQXzPQda9YIzjUvnyn5DhOrRL5vAbNyZrSUiKQgDJcmtAHqKYaBRrNmzeBK84b/qNys2cUT+Y
mfoQjy9oeHmqxdPMrXGHwVorgLPEiNagYZIXpYh/CIMcDZs1a/rJW4IM538b8vCwiVlqIigZYM5t
wWuJyvljjyduiBWj5AE0vKHls60fIVdi0DRJlNElsCDRgoPmtn72K+c4QZ4JZEQ9uml3grXttrg/
z+/mImPvfnVznacNCA3NXxK5gl/T5o4B/LY+tgC9XKDU/GBqMghdVRzlmT8HFNy3Mpi2/Lx9Tsur
2H9KeUu+z08C7J/bQQXUtURCvUutj36od5GjK5glYrvjwkD8Q41VEV3f82pL60xvINtHy7aoLEzV
BF2VP7mJqYUSNGuBhiFK5CShh3v1Hxzd+2l8Btva0gho6Ifgk3AXB2eJAP4TURtOJPO5XcjjSAQO
s+uUh6cnBxwpGYKnBVTJLLc7nMuOgbW/ZbJ61NAhKEBO7Pkw1n+8ZPchWqy78OEV2zf1MPc/D/O/
fbOD6TTLEcuXdrEbjiSD76oQsTuXRiD+cVfDWBB2EAzOq8z9g9imF3L+4dlMJ7Iydj5oiQgHSQbo
oOZi2hh3Ag1zJ84cpikdx+USxEA6c5hdQyic3HXVd2HpVUlj3Jk/vC/apF+PLA8982eymvPR2cTO
dL229LZdUrfOtu4fIrea1wt/eZuRVDgB/JuSC5FhVkmXSNFMAlwngkeEbHRpCIeAcmfrn0uQ+XVY
bciJMmxk62yttbCn+HedHadKuZ41PU5yU3N4oRlLogaFsC/MHriC7e6P00JPbR2gSiAbN0rucy4h
yoGG9SXBIuykuc0+SjSG6sca2HE2IeQjglvMNORFz25aDsWraSv3gVGK3TvHNwNWPFg5eq4uoCvj
WHeVAVhB03txIJQkXTF1NAa4nHrIHi7vx3wOd0ypP7sgGyTBmGkPxc/b7eZKSlPuWmZEYBWMAlYm
IQ4XjqixWjuhHIzrW7xfnWMLqbzow2BowXNMAqS1Ggc18c7jYDi5SLG/XbghXoVdzTlF2foOeu0i
F+3+vJ0MbxsycQzTC0rX1hs74s8w8RPvPVxTTLZ6hjZiz5XAzZRHVge6HYHLdhWsPBsUpf5nNjMz
a9REmyzpoC8QV2J803UrqHYwlaIio2TNTnX3qnGb0J5CrSBmNPzeDTjjntJQZwrNQOV8JIdX3xXG
mQcdvwMw7OEF8j9Ju6P4+ZWVYziX3A5waEHrNEUOElCadWZ3qsWrelWU5LJPXWvfZ3KX5bFYU0B7
IsBG1o0fYJ8dd6b2ScIbV2gzKK0XLgth8QOpgev8QrB03Z6fRMVOwsKNtXVzRKNIqw9hZkAJVCBJ
A4YoYs8KKhLQdFc0XDFJAwa0U2bbmwqNw/rAOQb5ca4oFrS6p6vAsxkC/eC1f9eq0Hl30qFCrBXM
a6PCSLmEUaPs9z2G/FOGYTAXShzd+utcyTSrmY7w+ru10Uz7xSpNkCXY2C06FXMz7k9KvXwcxig4
uqqcgp6g80TzWn9O5ud8Qxm5jBa67dANTqaCetQi40HDNXkoXAjmRoaODgST+p3SgFCGaUXm/XRF
Rtb3wwIzS6aRjgce/3tzFvTji7U9FC4E/oxkTbNEn3CtKFadNljC0B4MUdZaqjtp6wavV197upV8
iQ76JMr0MJjXeHNERXYrtOCPfLGkujEAgVcPgu5Z/4ZUfxp/HU8CWnQGCCpGPnvBjQvJaqX0O8pa
6A7HeT2QSzLxEKWthB9b8tQNc7HlJQQMna63uYPzkT4QO82VmCweAEzhWpBw+eQ0EXBLdxj7mMGl
qINkTyu/TzC7Qj3PHa6MHpUkHzEEd5omUCKqApHMT6KfI2Yfj5SwSDXorRvYkMQJCQy+wVfHnFIo
WgiK/3iYPwQcbMlub2CBRCcM239CN1dJLirhrKbfgG4OkRMX+trdseY7+4lYrgVrCwpV7Kb9jukk
w76vI5t9NJydWO1H5fk24Z25kq0D9ohPKt1mpdAWecTv7BMnqBBzWiGSMsFdR1oBn6qCloe0rv44
nDI4iPBWxk/NmpVdnKGgtX/cIePEh28xmZuNJW9BMRvgiOORhkuxitqCmNN4DdZ0aG4J8JtPA7te
/sv2x+rsYmd8o0lfsNJMcW47unziwsvnNSxmHOGp21lOyxsYgpZblLO4HtbQ/YRjoCYow6HSVut5
tMYtNkLXkSwaV8Qeymxbfn8Q3WmXLIh6cvCjU2aawX2M0mzedKWIXbgPxIL+i1gI/9w/zlvsKgv0
4qimP9RL8OZiba1pUKtB01HNYIHq5ob3Dnq0ITUM198LghMTuTIh/epQ8M0OpBteopAbT99tItjq
kv9jeJezwEpQCHbGd8OfqTIwYhAq2v+/4biG9a2IGz3ZfmgKld4Oltv6SrcWAFvqnfSpazNvrrqK
soXy0F+0MI0HJPOmVHIGPjh+qs3nxN3kAeF/vt2alVkwNclE/zPjkUdV2kLFPS/UAS6Md1NV8txR
B5KJgrKGw4H+FsVIa5NNiLdrNloNoQoBt61TBIaoxBATthmIp/xoizOQRQE4UmvP9tAo+kBI8+Cb
vZdgCsv6v7TKnQLmwgaLrGZ7fz2R2plwSunftr9nzjBGPwssDQKIXkf4TfC3XNb/yydLMK+ZKV1e
78fGdhmkH7MsGo/+B70DbrrFFBqaqoV23YBspinGgUUORf+ccPHnq7cdvl7LUlL6q6VXdEz7QHny
T3UqCUkzjFrlHheUhvpQPm+yy8zsr+gE0nCwGR3HsKuUxD++MCb2zNbXgbQcuw6SzJJN9HqkTrA8
lCxk5zKg0M6g8CrvI/0V+xsAOmVpLKcivIg88RwSek9+IrNLcNR/qZnqQ8MDgf6GDzpVzsknjx1E
cXXw7iN0TyTuA9wnhx9eZzlL63QJq6wrg9AAC2ggkKrLmAyQxMrgTppfnLU2X/BC0ltF62FTbfTq
UShgcWy4J7TLgi5h45J4Qk5obRKO7xoAId7sqvPVufDrdaKwgc0cvqqFPZOrRlxTGxpC7OjQOFyJ
x4Yh00+mX2hptz39CTEQdvj8YifTkUmzQqJx7XF6Tf6JRHaA74AQ2QS8FYdv4XGLAMBvvLYkL5Sg
zYz3102BQRw22aX6Ijgc7kW8Xdj04lmyy0D/+mneW5ntZCCYWYeLNfYXie442UGGiQle5Mr0XN6H
WWGwpp/XEdiEPX1pPILyDMy1yOiYUzIJ0Gg2/PCJbTsVasWoQ3cTr4Tm1yuAIy07DT6bh1YPdkF8
2f6aq7z/MDXREpIXtHvY096N9X+N8jYzM5mv1Gzbmq89H9QKF4N8LePq7QmJblc3nSoKZnKdcLU+
mYCgBgu0LIuy2L55zA9tlLJTM/UX2Drvx4kT0VDXb50o2r0o+xIIDn+dS4AMxi5M4IZR+MMKlG1z
9eTmLrdBJyjmgRUN370WMSIYKoIsZFr1wGCctFA2csq0tuoLtQygAjfZNJvm7oBhVnvnkkJk2tGv
YXxHEKCy9wTimNz9Vx2xMQrHolHhTn96BJyjI/ghlOyWDjfGiPBRNV9gNKShSHfzPWQNuk7cV+ky
oeCz1mygjsFr3NebZh1shE2IvyaTPOejiu0DummzBvFCevY68tku0WJYQHr3uWTKPrtaCoIHkp4V
dkLP3hXmKi+dMr4mF4upcuWfYoaY50wTquLjxQzvaD9dB1PWRC7BpYIoVvDTSp7rf7EgnHdUE14I
lVg2XkJvNXDgPzskR0BF4VgGdCivrj8leqJC9G7Yl25Ge8Ylfx/W3inNmIHejg67z6lYA6iIOvjR
LL6n/40PdOXF0vBB9R1PFcHT4gEDKon072oiqSb5eaVl6tlscgeroQ8yh71p0VrVM3IeEyfvv2Ag
fYiUQpNSuyK82feDIl1Yiqhy3eFCWR/cOEnJ/FEvOHD1FfHxHKGga6Ka8oXhXokeZzJBDPd/6j0j
lSiqkV1ok1bNi4588TA2yiEwA01qBPiKZdd650jsAQzQK1VIFtvjrlRncrD0fohHnhyDDJJfY+JD
qY2VgOs8/JBaoXJGFAGZ3yvfqjxmcFOEtd/PubP26iC9i0DXze280x/IadgnaXmTwqEQ+m0v1gsV
Xf/kr7GJBC0OlVSUjwIP3ZW3AcJEPPs9aXlU8q4Yl62Wa2TJ5YHbKE91sXZaYThZ5rDYNjnqKVmB
am5rN5o7vQGxRec1Fn0uZGMk1bXC0zULHLyQ2kboliZv+9Ao10XjOpmE5QgbmeKXxFvKcYHM5gVt
9lBtl1XBfwBQk92YIWEtNKx5xFkvwKZKqqeqAGpxqDzxwuRjrwzI7AE/h2nR790ej2lkE8f5IiwD
SHpYFODKSr3LnkDfo8T6eAphXXyLdqAGQeVNeRQDX45YevZsdedKI9gZOMjh8eqFDSyDsNte5Hpe
sHz5UmBoQ3WhKUHGYHGINRQBnGMHq6bYE+c5SMvs+2pOt+SXzhQ9ZVB1JbU/j4o4QaQMhCWt9/v0
2AnC2EeDHaWzx3StpS+DWqk2RP9ZxD95ANLVc3S/8msJe8QkgoruDDKqHlL3TK/au/x7ziopcB1I
sRvdXdTZLuZqbAtJk1bDajflQWexXZkTHFklkZChAML0Icszw5ML1XXQREnwSS21gW3OU7T2JCwN
WfjG02Kqbc+LQrZMfwvNOsHAYoip6nwGMhtMMzTXZuHNYfUeOPNd9v7Xpzb4eJ74svaRexaLjOYS
egOHv8GO8orkRdK3SMuyI3CjEu9b7P6rt4pc2KDr4BCxAoM9X/uqBu7CHQ1mRZutSlv/5oUnpkW9
jTfIdVsyNYasM2CCtfnpG4KaBqz06xvJJkRCItK2y/yzir15zZkbQ9x3hK0w+G8r/RGc3o3xmBWO
CW0YM0X2tbm4f6amgYjnlzahDGgVqbd1AH4pzDqpkGhTg6RoLVZsgE1Czm5tWYOqL69Np3HVoR6a
mdmfHnX52ZupHI70XXrAAgImOiMPWXd+1lmlPN0r3AfeByOQuxcGA3U1eOj9wk5/xOPMZ1vVEvP8
AK+Uxb0HlE2NT/KFGYS+Hc7QVOMQNjy9pvmqsD5tR9/GW8apNDej2+XHH02HUqJyce1DHRkjL/XZ
9YCbMtVR0nWLvdYnjCEfZuAqn9waxi+FzOdvHyESWOPq+yVKUE2SwvYHOs4dwFWhF4ajqOQPazKq
NvhiH/gWV2m9evR4F62xaTh5tDUdm6SHpgsSAz5hqGI1zdELfQPZjKrVbE/48p6ckg8ON7z+bU1U
QN/8duo0ZYSgOiy3MXD8Mk3/h76Swmr51MH49l/jRZSroIHJKnK/ul4Hrq6fPa4ZGlgD/AohVAV6
KkeCANhXG1E9mGFex6IBUcWuKPMfIFNB1A0gX6IFr45O9ROUydu5Sdn8f8EAs4blwse7GHdFs4iM
K/PhAZFGAzEWcegG5dRTASY9UrFOPidvBD/P7fgc86z6JLS/beQEVB1vpRThr3kDoibkkZgGLOIU
r+zt0jK5yMD8JmIMZ3utw7+I7QD3X2F0SEgmUtpB53stlmTEcBaZ4mda28/VUPJwczxkI8hJB636
eE7jrq+CosYBP7CHESxpOzd23abGuqnTAm2ze6IAvRuwnqRnJCQN5pelYGDFfb68gbdi/1Dm6NvP
IZXLUlaD/x3oASAY0YlMM1wT9pxx+wjkhu245M+sO66tXDgDUA4mI1q4Ta1nH/q0BTxdcmZHddL6
MtMDPPp5wS9YqLxV8A14cQJAYq2kyRvk/HfgPKhbEz/ZeYWyQ+15Ei5rBQopY1PW5ohudYgR3HGi
1bJixG1cuE24gSNHwk7UE4fTu3aYSqDxa6utV9nkxPqAKitWh1ZyogxrtgkclVwE8781UK1fKCuc
VoSID+zXdxtNbWyf51hy21L+bSnmUO6Dc2N4VNpFvWx2kfKcDO+nwIzmNLQVnkZPVq3aFLlrItcd
5HQc/7ThwFnkEJmzCGFcJIxZzv8x9lXYuiN5xSmZzWCl2XUx9sazBkxNLVNpujmC1k84DOfyubZE
SvuaD3x9TNn6lOBsXTJh6LsrUYlfjQa7Q49GE1A3v0FHgNpPRXGp26XPMxGE1IEXUqtAY/PriEdz
X5SggqXkY7WVXiCOen4YdZPGbipDgXxOVl8073r/MldrNly0lMOMFpO/iDbEH8ErdF4baVL8UPUQ
8b251BbJ64Xl4rgv8U1DekyslNcWT1bI8CZcgiCKMEKAFpDkbJNRoAr5s0ubcThm8HyPEtzbHJhD
qAs2cuLDgvn6YrlAhCeGwC1aT9XfzmEwYEP2s5gSlbfjwXvCr8oVxjkX2I3tza9EmbSoix2UQy/8
SWoaIT5Skqiu32Dy3A8SzIPoaTFxd3sueH6mZYtrduLa2lo5Rp2VlQk/pmQZqf9pCqCF/9UZ5cJ5
iyEABvp8+3gjUxPYlFe+MEbKtCgG4tyPZzUPk4FOzRdY7STYZPfgiDWa/7ULO4M5mtckmmI+CtS1
bUA3vDjmKsc+gz8zVOETnmXiqyeZkkIDppgRO4yDGEtgBoVM9RZyB7SYmvE4ifwn6/30G/+YhCD3
GbCuPoCo6cjPCCK5btK1VaKdp3t1FqqqDCnSOQ0myOwimaVmSzyhaxhWNnsDqDM8W1XUQIEXonwk
u4ilJevBfsjK+Ru3CI8azExMe+mWah2VXwbCaCwBn4SB+zTpcV4n3PeGxpmdk8zMh9R5ltKkxqvq
2hflkdSEG9HicyCMfyA3uFrcfYlDD4/CoQrqX09kI6VA8Dx6U6lSyKsRYtw+1q8zkRiY3NGhwMYc
2mMY8R3JY6U5z4ypl3zE74k8KH3eSmJTNhhtHw4E8Fv3TOffihfNs00J8rNcmYKgvuWZDY2Qp3Mz
wXGkIarf3qzZIURyqRMUVR1/vXDB1AD/GnW8bF3SWgAwdokvVJVTTxlaAZElZfBUEKftY7VxYvRF
k8E15nnhTvtyy7G9jPWfY7QqO9Emk6+tBgbHdHT9Kc1cva1ppmMjiEqOe3fbDD59hDEjFgQhh+Dn
LFzLSiQVSvBIV3XYmA8I1/acZILgrNAoIH2aR8JH5U/8vTcAudGXrx5yz+Y2tYEun1FOWTbn6qEd
saxCop7INcXVRQDX5I/Y9ySE7WSsAdlow5heaLduspthwHChQSkfpDvGOLsczJ/tbvJI+lcED2ji
fhroUW1Szu84eNGvk82MOZmL47FiSpk6F7EUKY6SWNgDLjcZhpWxfkyoxj7QVPa33uhGUaM1DLaW
fP3pky3DBk28hXjLAy1s2mpGHBjtlW+Bv+60qQ+UFNdO0HoWuUEA5O37FnESQ4JRDZwQojRjh4Oj
6UazgBj1s569sIiP6xo96USg9+n0mNwHIIlYRQvG0I0diQaJltBZxhHyMoqL8qD4jzYFNvDnOl3L
STODIu866bnx6KZDFsnNUGyrd7fYTxYvckfppt6xlAkWYA5OAzxUSCCQT424JoZCDtBdiox8BcCU
pv9jL4i0QpmML62EkLNPEF9wbg8VCBltvlD5XT1lrHC242VxOHs0f9ndMBC4NhPzuejl+e/9+gOJ
3EqEqgWVjpk1pgvutW/ZGR6GNeRGEQ7/yc8+8Jj8Sq7rst+ao5Rtwk0VUNjCQDws0tDTkilH/xeg
ErXYS3oDOq6AQqtKFO+NMZKFnehGSS/pJa8NJOJNxTUuCtvfbtONvDZEfh+FNDFiga9XUyWjr2CC
lkf4o9FLHnfWgTL8RYkaj3S+Ce4Dd1oSlBDQpLDZPDC3hmyCEUQKAaZd5enfIiunyVBULPQCdoOw
7U8ZWa4j9QUIFy5mOggI783ctTOGx+86SGCQPmkMgXl+41mVcRhAi17bXb61h6ztrL7Rlle+G4sd
00MURR9I4ab9cavjH+8N4o+cFgvSn59fJRD6UrgHl/6zxSuO5yaFMGTJP5YPI31CefzXhRKD9E9a
P8lZg4iZRjItklhSoJ5u8lKsX8N7TlxKdgoPN76b7/cGWpsTcZOT6fKhEoRS3eS3yW5i29fmkDqn
26lsZsXmScyJz2BkCnDb3akD4TO7qQQod++45WjT+1MLxXDQGckdWyt2nI+X1Tf3M/h85dMSnDSU
jrGrsaRrhaANd0sDkxfB0wdbESp+Vj0uBTfprHtKFdnoYCSvbJYBLEIeGpDKcrDhgKnqxz2wPMfK
67awGLmIEsvv+i2z2rSiideXWWKHQUcvksTD4YkhJ6L37HZW6QKNXPtkETSPU+n44OeN2QiKL/YV
av3vunbB8e6Z7CRZfXDQOJMG6TxSTHgHSfhICpxnlQn5ZmHTD4QwypQIHrXuMhOFJosHj4Dy7R7J
r+vcOlQFt0VOAESsp8m/3WUR+5tj4E4q8fntsuF/eoAs8OKdFvM17KlV5viEzEzmiZYnWMJFAvw9
/IUc5wlKivNGhJe7W76Vnd0eDLsKx6awv2ymb1lAkF8jEyf5+6ZWzqstHS0hmItdQbM4mkr4sJ+1
0ul52GeDJgNRxbNL356CshQuQjndQr34K24dJNtnKMZWUnAwKUQ1EPWgL6gGOavv4gNoP0dP7pKN
KmrOSNpc5jcNZu+wYqVVZ6nfSgwqzpxC6GjgLcDetvdeAQxfHXOA2B7zscG6FVgBtQxNMp0plXEM
Gu9G6wAnB7SvgnMc+VXX64tFgQzvPILk7ZsrBeaLwDXxbMaSvyjKEfejQ7k5FV/khfZ53WGxC4Ga
9fNt5aLfcxn/oTodT4QCQphyNLrg/U7Cl4vsdi1P0gMNKPLLw7BnJhgtFAyLgV8oElybisI435tz
FhRGzaw6jfkpXRcW/hdj+GezMbduNuh/sPoWredtKH0p7nPtWFgncV0W7RVstMjuh8k8Ey3IVJSt
uZVYTiccSHVLwzqckfl/S9R1wdVH7qReEGz5T3G+SA4Xfap+OMDz00oUPcH4vDOpvquctOvFNk2z
u0z9S5E/FahumV6hl2NpM5EjCrqDapAqmkkmtry7xGA8qlLQJy9fYPzbnyldSWQn++ljarnRTfNi
XgnWk0b5rnA6OY42oIWSU7mZFpDoK6LYnlADaI4358vKZsAM8EF3+WgCvHAXBi6udLnSq0xoG9zv
dt2j0XwfPAyPMCvO/gQCA3Mo/dTIZYU+8nj019idvsK8bnx14YSjjHY2TFiblDw1/M+3f66RBRoO
LaCzoDvwJgjtgrJNwtFna2VZFnrnl6YWogEstEqiCxJnwFr4yiiZAmzEWslIT5Lob4w6KkMh2MPf
QN/zSA72z3QF62cfrFl2ln0JMkNpU0BUzt+zDwAj5c+fSxe+AgjH0d5T9D7OJlExaE4dPaOlK97h
8aayzqJkxKA38+vMUjEDYbjLHKLLVnCYSe9kEewZOqZzZtBH4hNWCjeJ+6qhUbIWXlZZpnSDhoCy
PJZqwExC22fpyKSe1czQmr3DjnsoHOD9wCmnWWzGMjvw0gjUJSvlOdTBhDY7Ub5fPW4fGzDg466m
JcSMVvIUmGw0OEehnmXtStlltM4elaId4/9I11vJ8xizxNVQQW9V1OqswKprUzl05OyJ34fb6rhG
iOWu1/w4FwdPIXVJJwyJMfWQC4PKJko0DS5avyxqKSSxEBVOVsQwvtlFwPH9TbchG2DaYryhKtXG
NQHXdBoltRZa4bxqezvWtR8Dg3SAR2i4D7+TFrCGY915v2cjLP8VQ+S9e5S2tu4AOR+oz8KDxV22
xDVC9sKfpCT3JGvngKhPU/eHC6uEwxa5W5PHxAoTHXpgBXWQG4QCvrrYee1Hiv7kcp1bz7v9tOif
DCEFeeJj2pV1gYrKegpg/nBSFi65TVhPdlnLtQBDDdhAZSnCKZ6a2bO/4vAuI4mk/fON1ls57+5J
HLkOl8S2gt1i0dOW82vbig9yOBxG4oKyAmbCLLG4hoX/SMpoPTtyJf/8Oj3322OQnBs5RpjYpz/B
zNjRqOwnmCGxAppiee5fx3sG/lDL9ncYKqUivzdrhb0SLYjMGZVa83rC3O0YRLJpBvw9aj1F4D6J
qgE4xw5W0SCQXf16xQ0RunJzDNO7cnIKfzwrHOwTF9B/7ynWXGaLDg7eRLFEHMUXTEIOaWnnDlYH
gzRUMNW4cJVCiMZbAlHmkAqE13joVIJAk36kxLS3jwWS+znx4zGaCdl52VT/tYxJ4OnrakCebf7H
pQ2K9pKL52jAGpDnRyMTpMEQcBhGXrHJfOynVlrjG4iOmb/AIvmt7+2YIDOpHBFfjTp4M0Czhhap
5vDnMrkCR+baAXLTkCIRSTUlmADudaPt3FnMyP4k5GREE7Uwl20IaxQ8VUvw7sdLlq0GvFN84kNx
Z70Ja2XZtG+h/eQzjSBjefi/baQUDIpwuIuxiT/zO1aoVQtvGVUfhJzpDYa35cLQIsinkSYrWZnf
3DLNDL/v9YvfhDBKxTJ2yGyWzLz85e4n+W8kQBDmlSkQdmcwMaEuv3jHQkW2kV/Bh0vmGxw5QEe7
Bu43zTBMuXl102Ib4/lSlB1AxfDcU1SENcVLC4ApEMWzrTrNeHAgVPYle/sPUyOrOkMiwbNlpJkp
r9UHfpg0RyJ2pj1WDFchI7fUDAW/8tQrSZ4g3HGlhLDtBSwGCovDyjiPYUAA0crP0rxZc81c4ncd
w8Ui4uxKsROGrXZ3Wmmeomu8TEKDRH5cf8BW2hN/VuzUdroWEk5MD2SKbJI4Ku/vJgq8I1kxMaNa
lZSIjlUUIMThy8nNPHA8fSWA7zA11MdxZNpVv61RpzaRMm6AYmGW9cNBq8/3yBa+KQ9856HOj9Cr
6xugMlxTgQr6IB0nlVtOBwuce0zgZHuDyyRGS1mSSYDD8oEnjtQsaMhvoyvwvctyr964QR1JZUBJ
gz0jTuKOSSeA2P55Y2j9pIt7JzXcI4zs58nIl8O9QBM91URVT/s7sPPswhAovFQchbVzCyP+/Tj0
3dBFP6zjvO5aqb7S/VrTHGjfrqY3qqAYikRXVkpiMPZcc8t5z4ttljEgjFkvxe+SBkT7BJ0Seb7k
5RJ09ekQYwi1pOus/uMf1MctGi1Cl0Sf3WuzoMhYuQmjUW7J8jtkGqwVTEWbFtXImW0QpxFNFotD
+Bb3Y1G2Za3VegGzFb6sZ82W9pQjpV6lYUfywJ2TwMHJbgbs6ocu4aNsmAxjhcyYAKVjf2Y94p2J
40BLCW2+r+muLIfl8K4LQiUCqHiPKj+vm/w1tW37y9L13QSpaeWZa9TCO6BAm1ORgXXhpQfIEm4x
MS5g9Chl+k9EHZhEtw8Fj5UM0NYqEvwN+GIO7Z2B3zdruQFdjwX8pmoaqAPUs2iip2z7+O/TEvWn
8UZzcX/n829M4qykyqAEBBf9r/0WMlBqCfRQdFP5jhXaOiRQojQ2DNvmrtN2ZnUjChr6Opsk6blT
+hp3lYWcclGPPuSsJEBMBRx6rQqIj7Qn1n7OZQX4uphsYcWIQR5XkqXbSBGlkIRWWTYLOlbxe26+
4YQeImRbFMxTdyMxsz4a+I8uye2CLngDGSHI0D0lVQ0sUfHn6LCFme7aWLXfH3C/As/VXhAuiW/q
muAlBEVoYbSB7CoBoONrmElxYw25sS1B1KXqmBnfx89AEkoU+qIsKgFuK7Yu2LA5iomjs+iY060a
SKEFKPjO/XkxRDmJQ5nUY5BFxPG0PaUvfmExcxD5z5nM5Kwez0p70nRaG03j7Kh0FSw9bomi5KGu
cQ0kg7sK0UhZJSR6R3frDneMp15BuaBxNvSTd0Ql2P4vMD6PyHqN34vl0foI57OgKRqgsi8rRpvT
nAselq6vb2RbEd++C2RQ029nJeLawvrh72K5cB8l1v907dytpgY3SLSIjmPOpPeD9gcBhjOiZi8T
eIytWSko9guCYHoH6cUOw450xX7W6E03RUa1aHCObGqlRq3X3lxzx2w5VFE4sCt1vyF6fpA/XcPG
ZYBU20II9If35J1andKQCA8QbVWS8nyDHb6lb6nHASdke6Z7v3gszIm2EFLkbGfwJgiPzNTMxrMB
YaHraun5o4U2cwdmrHOTgYAW0KfddtmWpZdCoWjwyC5j5eUMDYoNe3wyTyttgUsftQw9mQqvtkt8
V/CgXSB8rDrQTJAYX6D7XgrKXLwzkl99Oc7gi7huevHeqKrYV1PP1h6uknk6oLCWgNIU5mu7DbGC
MORqU7/HZIVmvzq7R5PcgoJ3t/VSkOPOiiSLxJs9VfIlP0+CIdQKkSe55lJhh9f38QbmwK/1qsVQ
lxu6xxOxj1H+VCObqImdkrbXIZjlo/Xg3iCHcv9Lw09K9sLwBsHvRPwmUqvUFiK+4wVfOi9kb/vF
uNCsxve+fpEzFELf3osxQj8s2eVB6352N16rnsjDluO7C+64xoOnQGk3TJLYQd3m4uWvGwpLmZIa
46MI00gFmhm7UhhKTNR7qvtkTrHCTcrDla4jc/QB83RQwqsPafpUuI/nkoKKxufd3aQBjPhju9qE
xEB8dKqJmH3HNWoZBgASsrMZEM0aEBfdSSxCPVx3uqoq1G7BzzHorSrzP8Ixv4Y+/BJC8SlVUPv1
WXoVAje0CStsFQgBtLFZ7hcHQfgYhlxzFgJnFJV47rhfh97jFDxqbJQ+c/jJ++RSCipag7/F/212
2Y4BboDM05mMIIGjJTFnvVrOHVgDXRFG9Xosj3LYz+Pzy4ibzuRFxTASLw7lSDU9rhKRdxl8lsHD
8Mepug8jCnUrFQ+w6rmG+jAZ5ISJHrP/9xrsOUp+tVnq3UMuxdZcZRIOMXNkNtIJkTfqH1HRy9K3
1IdDjymQF8Qn2swJsisMy8KnxAzm4zF6AtPKpuqipmsuO06dj3o7S+WLjZGRVxmrkMGbjA8ZFvK8
MC9RzlBzzj3tdRXwnagbAe/sZvJHs7AyYiFxWCbetiFURkZtYDt+5QjKNOAdMMsHeEWDSGA7xlVY
LMfXHpYB3Ic/bbokorjx3xSX5DkgGBUWmPBmh5H7k12SGNtBRUH+U/vpQePmWs89Z14yVd7wAmAs
75OV5RFnaftTH+J7/0UPsY8aujDGqsY2mz1uZdiwEXrE4nlR2PvV20+/p7PgGogqDSkbMLUXqsiz
UF8VvVAHQ2O6iwCNfL6XLEiP/O8PpFbHhjnP/Q7j27g7ZQ+BoQcaTS23YCAr7kMLtciDaW7c4DWO
UmHa28dnUe4x1qfsPblvxl7k+q4C6ew7TJaRiJsqkj5gOUKiipt1jIijsCMuNJt670f2WSEA6xvr
i6jdIDuDhbsWoBXE4+keKgs9GZeW7IzceLQq57uC3oirAvd2ArX+svKhrpzrOUGHiOHcjZQ7sZPl
R2I3XlDutOSrCOILP81f2pVkjYBa4DhEuVal321bdcu9I48tN1gu47aGq3jTz/zBbtvqCK/SRAkm
rC8l3UMOLtor8msyk9dYon3YFf+FFkxhSgpMNnk/Y9dXAOCwEock/JBh2ji6UhRdwoReqghYv25M
P4pw++kDARDLELSTm4Ro0yDQEu7LXDxvg+8+BsACVcGnj3y/Ncd3LMWabSX3+kTtsMskwg7YPmG3
RwS9Zm7HPelU0+6PRCRupvQ5HFf2WNfFITagGWTYSPhjYWDVmfskPGGkRveCxsU/dH0WxPQzLBAv
ax7Ji23bZZsB62zMRMZk2Bauod8aJI1m9/VrrhN53VJxmOt/TnWqIuk26nJxQXNU8rb9E6ypit+A
UKpyffzHUwyT8zbrys1aCr6tlRsHMPR8htLYD2545qXRanRFqWxbe+xJsc1Ggru0MNs26bx9tj8Y
bTYX5nzBIQO+wGjH7MmkuxuhWKPn25ZfVJVaxjkHX4sKH7HXk5lr6xZwHh5gjChsz+4++C4rrlSe
4xz5qrsiiiXZ8nMlxbwzWkzYvPwqpvOPS116SdDRTunQslFcmH9WSsIR82yJO9mbbJMtdnCxWoKb
jLIj8RvnbiSEx0ELZoGCw3fBb1ALrPJPZtQaZ7+4mkwnC+yfxN5WTkWum5gY9Aiv/mHBrRWBPEg1
g2xAs7RNTakZkFiadDLjELWBg4QgagkidXKQPhmTFflnvCn1etbS+GU/zcCBgS7UgxHhMq9DUZFJ
VLLLmK8i/JLshNgbQ+xHd3Qqa++nTs1Wmw+4gOIulJIiZ+6M/XZjHjP/kxliumROzPqRW0Fr3hWX
4EnytA/XxveNzxEJlJAmO226R5mUSHxL2bW2dAngWfvzSgsOjCovL7lLBg7DAlogI1oF5wzCf3wS
QeSmaJ13OIhLb8QfpDQpuJ+47y94+lMOEMGgdeaRa3aot/SU3Xe0oWKHCPY8loYBm1+KsMoyr+Es
EolOGphrYI+0RFdRABhCxo9ZjMMbuE2VZQt5oU8WtZOxxMTt+Bo1PQPKMYab8fdBc13e7XLYTSYk
Q/j8iiOVvcRkwLIVErxd+EBk/S2lYxaolHL5bKZUCa+pPMTLbskElTxcYVb55VMFZW4ouXXZG8Es
/KvDB96xmKQt+HWJlb8GgKsHWrCvqtiuLtySkiCwX++iTkmQ9eVpCiZCpdNe42yZkyIaqnRDpaLR
N3GOd0JWWRxzTBuKZ+LbMtrOnKVHDOZubhBhqkQpqbipHZeJvQUwWjdyw7hDmr+T93kd8BQNvdrl
u6mMkbh1nJmTg/22mBwfX6kI7PdnF3zR6R3Dh9cJmHqGa2RK5eO1rgj7cgyvjsOV/KRzz+TaF8m5
QaiQmz/39tRyE6gvA6/6P7alXqGLyI3t+H1ImyjyZqp3CvCLIkpRUUs71ZbELY6DzNv959nX/gH+
bEBolYRm75eb7C0Q0OQiHi/zxNwFEdEJzWAWv5lFmQzdgijsdghxTn/NArV1FZ+zTK4ouo7CaMMk
xV+ZuQBNdUApupzZQCLv3L8dRy63TRMhEzr7ExhB87aBqjIP7QZjXZTBUgJIohYz30V5kPCQPGCD
VmCtiNXNA5vfIiKh4vQaKe+Imb0CR9NqoHfgFS5h71FPHzsLjbaReCO0WeFzwMM09PEuO2txOdcd
piP5e2WH8pJpI5OskuUED99ZtZwE08RkoWTTW6sHLVSnK69ptPIHXurfqUKuQIY6r9cHx+1CA2tv
rYMyOlfBX9T/voB4b5ZXmt9IMYvyOYR4KsEmJ9TFZHY46ZfF30tSkpqGPVDWPT9QlKnO/JniUzMo
8n2Hwu8mv1usYb9na5BHBMbiel1yBBmTgWJMaRqsp8CQOwaVZZa12j35vzfFqDi8f/veOmTaqN6M
w7pcagUFkCNb9P+RhiE/xRIJypyOAA/Iuc1C5TZTO/am2nsdNsSR3Je/2CtXY6imREdYsmPJ0r6m
kk8ywijhhzVjfBfdJeIERz3ixC1CEHEH6dBu8sXWAR0+iQpkriyHD+FEdpdLMyTD10Fjza6p+iJ0
sTbXk0Oj9MUCG86gVK0UlWT7ft7QDVHzXQmltr2ObBTTd5aL9Y/3Unfdvl7OzdJDJszYHdmCk5g8
FPOcNltOmWjvkWNQSwHLK3yJDESuSCccBNTmpnIyNPGVC3bkZZjdaP0Z+qpCR0aaASxuI4LtyCI5
HPcW+tRQJQw/mbGd3R8k31shUeNHnGd24xC+s6iflTT/29pQB4/8JeMPuyJLFW/d9HQZoWhl+Yd5
YmbdK78wHxAAttjmVwhgvCIyMP1f3uyu+cR3Z0KfbYhf/Yabbc3+HdoSF+kVT+mIjRHS0sAqiQlP
2m3jpQC4vdw9u29tLfYI0nw4xyne+imagiumBKR/mJ44jW35cYXavFt81hI6cSnaxuts9btQoJwG
PFPAn5u2ZeJCSh2ZCk+zgEzW9/fiZf6SBve/w8UCRWgOy/eq2PZqhQO9WuXQrspH6o4W3eiEa3yj
taOSwx03OVCGZnEvr32Cr+wCJcFS6ao0MZsnX/GzDWf5MP4VyItrnfaN1E8P2wuJSzZmI2To63Z0
IVSgNF3qV0g+mRvlveU4fj9hLIatERz0K3TuNgaA+nH0Y0h7gC/3bj7s796pvylgPiSyUTfjYlFq
JwMp3THTqEoQu+RKk9YkVKQsjeFDGF3CUsVIIO82tln5oYjGV2qGN9snt28HQDPoPF7c2QwyrymJ
dia++PTSKxVm/FqFHU19BguoueauBtQj4aa1cCed+uCl6M0yoVDojKPSCW20PjvztyoAriBumgHL
9OF85vDUEnsPFMixA8/UPt+ocqlGQZhNJUBWYfKTRBHCXeYJ592s1cfBG6PU8esCTU5L/w7/abAa
6OCxrHUMGSTRozU+Lc58J6goFdeU2kjcuAZklh89O81Fr57B2hhvqm8cRpbZ2GUS8g3s9ep2fody
EYJD5gL1jV02OANqPVhp3XDIcV41JFAc3nosF2gdHUeSDiKOHSEU2jVAjoeYmX0bfDWDkGBBeiMN
nSnDWhTrkB3h0/7msxrJh4f62IRORyDMYitIsai30qAiqX4vjZH6jcht2RWmCy15VNkSdsMGLt4c
/xHOpjtgRDwqekCdVT2bZGI4WIlYatEAfExtzibN4u4navGYzqgD13EdiZcUfS/aWk2Y9NJ/Ov0I
addTX5apKa6kvZ3y2CkzeC3L9RdEOE0GtRtmPrsTkf5OFooupKuYUQtikW4FZA/nTLLmVtwKfAmY
Ku7aGHlY5+1WGVRWXzNjOtCpCi2jcgFbfpwIncoISm4LjXV9/2WQM+tGQu8eKGzEQhrqDfIByor4
BWDPK5L6nqaQwrPpt5l8/KegzJrbxV7QWFT2cC59GDkepVbn5McEbGd64114matJpOCdweikmLHZ
uCnYOWhuyOeSF2kQqtKyu1p1T7TDZ6kTIZmqgM2aNsoKdJB7xGr7y4Vstzs/Wn6hm4BlF7C0C0pC
rUXdRUOC8F1PHVPOMez2F5+hju4htyymU63Fu3wo1smdUzpyGC3LLK2FppKbTG+FY+28CIw5iefQ
Tt3CQXJH5evhCZKX1JAQkph7uu7RbYPgORQJwwao8k/0zAUc9afJ4bC38lNvdKkHGZ/6XF8sNAYg
G9PBTTAY/OsMq0bIs4sbL8mA18+1jBjKGz8+Bg9kY07vVX7/e6XMmlY65XlKfOY070C7S3HgG7zs
3MCE2lnBiexmClPK5GawVtD7nOJe6j6k+39muP98L9GNlld7vW7MO6HZOTdEgpuKk4t/5zGhVBsN
0wOs+yd4CX5QdjXseJ/cqLAqQ45GKK3bgNNFOE79wARDRPwC+PCSW8kTOA0WiBfkfQLZxaEorMDK
+l8VJj6ZzTFDmasw6rcGd7evrfJfXh3tRvvI6xZ+7BAg96jlpA+ZPHVFh42p4/QZ9ik2yNBXX/UJ
nnHncJIqQZwM+wEf8+l58/DE1+YYU37U/did1ykCrqzQv3DI2tFnWW6k3LPiEG6X14VInW5aVVey
4ZjrVqn10g1E2P2AA1pvuNsWRpgJYt4S7VExjlCwJI+a6LSkXINx7Bpnq3QWLjd4FxIC3xgk4HgK
7+Q24jOdVNRcufqQfE2883sL3iB4KPufoeuUGSeAJRSSioriBD++nq3XDOE+a4zGk6+6XLhznLXR
RrvS4aGmVZZdPwAi7iz6luOrGqN91XQwgf9c/HNm6sAsi1nnulnXNQmfTgS9cK+wGliddR94BgIK
4a88E6R6D+30y0Y00s2WNZGgsX3Qs4R2wcZnxXAW89Hwzb2FBqIDgdt1eRbPDbHnvTaQeCtUiNzU
7i/2HfSJ6XRQBuvz0b0/fE8xh1LwcrDDVKFQ1OQKamoGy/1Qc5QddG0AizxQoQN26Tx/tIaVIg3H
Hbrm4XeWcM8rwB+wG0YXRH1Ml7qQaiwVUjMVgwvhOBHoUnl0HN4+UEIXapjhkSgM/dwo6eWzVD3V
8bvmz/tIlpRFzcFrDVt0KIkPYqifEw87f/BHFkCzK9P3MmTeQGRtTk3nVwyVNemKGGlgwrNSdSXV
JG9vzSNxlp/RqToRjpywGMF/F4WXhoAZRTJkYm48uL4XqGCRV8t7urvJjAlVsYCYITJgnt+Mm/8/
rGlZ9kQ8ER/y2wZ+ar2ZzI4grKCuwS9Ws/5h8S+Webnon06XHkRfGBN/LG8FV2JSQJsahxoeEWny
1E1ioBvB9KLLgXQDH+ffpHhyRCOzRDSYmbj8LdS/nUG02bNQ8XoCySwz6QLFOw091uVaiaEVjo5J
397fX8/gmsQwr20TokREwfO8DlNP55Blmf7b0qDjKbYh8EozggCCxC3eTyKp77Dv9hRl6BO8JgOg
PkRdXLckwYzOh8cQ/e0sL0vDWVgrKif+mnKO1hS6yRnHN2CsWejOtg5cYwVtpa3gyHXPRIff1rm0
DDGj/KwYx8hTZO6nNT6jVWeHrdVAGNFB8rvK9rOS29YrPqXeh28hN6i9QsrjrA4jYlL3I5Pkd+DQ
KNu/UqoO9kO0mcMc3CzNDo9qlD0L8bTTICbjnPgmLYNGphBsFskyOiHKu0Y5d7BFZdmzwcPoe/2K
6r9gOk4djtYsli3kIijZKTJU2tqiK//9rT4JQ6wap059kHgeJpDvk5DijBJiapcbSLoXS2ZozXzN
TsZpnafigbIhqMvtMXc3n9IUEFPaywK/Etbm+95uWfitmKPckT3hvK4nkilBaoMkGymp+dRgn6cj
n51u+juP8MExJJjoPIeN34snsT5m8cXkrdXZsTfaSoMDglQxCtvLMeMxSgo4xysj6omses8usNeP
UdF0DUexEO3L4UKEKCNaYeT1DBKEtDTjs62enOrdznUSa9fiShzFs916hmMUhb9YxSFkzGLYLOTh
vmVPZAyXtJAK4xpQ4tPt+gnOyLmyBXBvb+f3I59yT2NSOq5JBVonx2L2LP0yWJHXAwWTTdikbkGX
4dcT4FQSie//q22LYRhfrsJyp41TFLuyGmG/vlWQtiDnbGLHh7VA1hIaUVvWiBz5dKyaNJehdWpu
hPNNe3UihJQxSJfjbhGWzPbcR6nyj+TwG4Epj6o3aasxpA+RFyFzNobI/ZGx9q/Q6xw1EyptlqhS
rlGbJCDDILBjeBAzFH0tEKg/XEBJf0IkaVOlD3JsrsWExJUzqYY8jb/EqUaMobJStlWnKFGoTgbH
g4Lplm4IM7Tis9Q/E/X5Z1iVJu2wtMXVibDoP62wjFIzfy/j8WA5yMLxSGAqEumuqM62d99OPfTV
ZZm0maQrcS9vewSHy2jz3NkQ8dzlaXOrJN2z1i72xoWr4yzN/yZtWlKmLUeACR5jc2ENXo7EPgin
QIjjB9qiWGgSgpGY3A8qidQKsRrPE+aNlAbNkQkfIuM7FQv4qEwRjfojOlIXfdUzWChw3mGUWOWu
8JdxmQlUWfDGPrXPX3UGXnIE6NFuxYydAJsnhGVQsa08M8agM4x4K7FQSiCzxEqNRVJqWOw9SBb8
9XmUmhJiSnWUI4jiQ8uo6EqaomohIJywcVROqrORV+KQnCsCvtpxhqLTxaNkP65+NC4+lxaQt36H
3xqITprGdjGEt96e3ivQeIv36hwDyvXhz3cicUHze6yjxFlmv1Yi3H2ak4585w2WOjP3A55wJWEa
/9AgfmFTuhNIPuyDSJGkFe2YqcVFBi9zdmaTj2lUrkmgEIzdLGdDjBV5bqh9wTlhGp55T+uxxKGM
e59X6WI1JDXUY1bdpmOW14ePE4Zhhfttxq5URDLr7n0gaLoYx6SKySBLlXVpi3RyPxw8RZrreMCA
5OSDja7WjKNfTjvjtWuEVSDHG8AC+KfLNubcYXANyFQ53YzgYuqCcbl99iBKGhOtevGWLmv168xq
6sWKUSFuyPX9MYJdq1wqGJzMAnxiNR6m7ZT1DSF0AaOyLtI4UoO2tnHHGFyQ7DgoWpNJ1u3kVXIB
Srd+KjpupoAoZWu3LCaLPg7Np2OX7vsyGWFIHK2AUE9af8rrEsZmYUKSU4IFJfPAa8n7j3jmEKtk
W+ZWrtc1hbwrPiADJeFN19B7mphkMJFs1tVRSjuoHopAollM3c6dZADgZgxc+YIZhNCTxDmBcKiG
ZfhXvQToYeI55xsW5HKCP+aJ8VrLBL76cyYTHH3cdvl3c8AfOJdbXPAbrzPoAcxvp6DEi++Kr153
S1aerS8gEnEzeClS9Yz/lB4Xd3q3HmCAwZ3JejgLcQinyoKzbzhJGQ10bPpVxQ3eIDU4mZTakD91
Leew8kPfq8pFjUVig4VhPWyvUuKYHcI82MzmtXzA+4oTwACGXNcA1BI7SVSvZtvSBK2ypCwHhLeN
Jo+yo478J2KkLj2ttVUGLjK9LHIXQ3zGzipNg+/TaqQnsILgBurMxtOgTf8W8KSw65UigsPC8RUB
Up9RwNKIrioqZc05Rpe0VqfxsHO7n3UajJjKagi46O4W8C/3P8XHJINK5qxvVT/UQ39IQOvsuSGI
XQtNv10fwUhylRChRerDYECGqfA7YE4yTNf55GTh/A3lYkvuf740aWDHa7CJ0jylcyeFba4t01Pq
wq3Cnx9QQAMLSS0Sm98vuHUyirWUj3d/idPqN/CKesD/fYd+w1pJqDbZ++Wt7B5pJSbEwVKJs5zs
umFFoQMwDcWVtVzRilVRFX5Nqa/FeNt0QTBzqp+MNblWXn4NXFh5BO4SAo5ZnX/3V0ikVwnIabj9
F1W3If1Kk6Uz8xIxJ257bcaJ72XQtFbDv/xV5wAc0mcuDMNk/hDWrA5FxQYc8c62ikF/WM0lCDHY
MvTh5236heKGO282mJRDZ2/9Jx07eODJfwa9aRgoWKHW8aour6vud6hkAfcv7AhACF70GZzKbohg
EhspMgnTd0YCIPoAv99mIADKQP7kdD7XtEwxNG4Y89ZgMv9u6ibW+AQR4qfN+rdA4/y7KGFee1qj
gJdc+fE5m6j2hdLmicVCssdl8XpR24DH/SmxEoLGpfMU3CALRpLbIQ0uHgiSDnlPbaQkEobtIyIq
DdWL7EiISFR7OvwsvquRYV6qnV3Ak1JmSnpnxsHZfQGLze/CLW1jOEb+WOM8bBupHfYI+w5PANsG
Zg+HQo2j/Fcq+GydBYcpJzFDYhFIfjMI12xrV5XAce0cYCrU0LdRAIJFHFv4bHubI0W2uHb7wJeQ
QHQIuU4MUQL6qEtwxTT3UEhIXgeImt1Qp7o8LZUMnEL3VFqTN5F7R12JS9sipJEm4KQLW/5RRviE
8NZSx+3NJiuXnFpHtAQS54vHUDnFYFupSD1cB1R7rYHazXyz0b+/bk3Dqw2n2g60m1HT4KDS/Ta5
FDLtjoboiHS4YGHntFzSbVPwJW8MOu2k/cHsHIBOPKIaQhDk1kH/ecWQqvjbayWkFa14KHSTY2eX
UvaEUPhPTJ3PNJQaYLY0+1XoiWJsiJbb7e+9nf7aSxPbietegF9Jpji8VsbXcb91ADozS1D1N/pV
D173JXGH60TBHZNE5YDhJNcPm9qzBcMkPzmlFlCCnmE5ofoVeST4NHWcxMWdqYLMpodXwwvPTP+C
nxYAwb9ItNAS3xeMcwOMOUi+4gSal21/IkZ55yuhNjfE313Z1tXsEqHCmH1n3wdUAN7BtXB7r2/y
roSFagHGyxDD8GIM7Ct2c8L8XvhFxyfZ/uqn86/zFFfuQM1cb/KNm/sNbl4qNZG7hIp+cEuASj8H
JC94Kyeq3lggFIgtTf2meUUZozT2A8lYLcGR1xJj4/K1Zln5+8Khtp86UwEvrYb/fbNm0vI5c52C
Pv1XR179QBobt11hdIDc4IcYQkh8q6/TB1PVMyCkERbNt5Y+w3sC6EuUl0bONFj68tzXEsQ/hNGx
7W5amVDOG9c6gFphbhVZ7X/nHetBy6Qow3n+oNCAM6nDqeZHYY4Jr7zOIWaY1xx27iP+WvzZa5p+
mLP5dEPeM6TjR9kdmZfdw83rW0fqcwYQrv0kIQmgF83HwRHCEXqOY8h+MgX6SIWqnPKrJF4wkF3O
tAAztJRaGaEaJBz41025X0D01Vqx1dZNmmWJeYI6BGNIJkjyjOGj2DzTjesrV89iusa8N4QGHfL7
8DshDzUsGPL/93wDXWc/OtcSPVNw6CiAnz7OcUPdK1IrQoAIatBnhCfb2Y46t/Tjcmu7ZgfpReXI
/qRTbKTUrcWdpgSPDdr6XAgFEvmaA+pokyXLMq1YW62njIEfT+gFwaDIpI0/KKqe51y1e1YuB6cx
9GH4DaYco80TISdPay3CwQ0DtbNaFGAi5xbUWV8H0U2jAJm6jhc0gT+diTnJa/1/nwe5+pyS/203
seIlYfg0wHN0FCS1plkXYTjOkH0PPJnowGcD5RnhpnCLwxBtVSflozfw0aoWDITaoNBLUpf/BMxG
yqPdGguI6/pPW/eXGg8Nfslc7VznG8d9KDC6pX4XtFTjJt7uHX8Q7SIY2jKYIOGH8taI2jqc3QN+
h7MibHjNHy/6YkkYNJquqEgAo+nxCHbf9ECt1i6+UbVevfxfu4/3ARAz1pVlfUASPc6Hm+TiwFe6
cxHGtQHPKBjuCWkkcaHuTydlZXkQ17oSbU4R9y62iK2teCSyLr2Ts1uzVB928QDldNZCy8Prbc3F
wNnjGwWAaYkHfyRFOTJ6yDM2aPouM1/d7TOyfc0wgE9LfCiWzHOFI8kzZMMpd8W2B/i+TgcOGtTF
eiqoo/qpI2dL03hL/j8F2QlFJFOLbCibvwIx6MhiN972Kjna3MRYZKfqWxnqab4+yG1Dnj/jdji4
lpSDddUjV7XoV6ImloldZo3f0kZVcwf4MXl3PrAICOF35F0Hx3/C+9UGbn+LjfdlMfvyeFlbt++D
mq9b5/c2M6QcrCpf1fhQ3c/DOByYcBOGtG1PSLDbQntFwaVfVndBqUNlELIZNIjs2C+BA1NFOR+T
amWArgNBuEVVZm7WFDvXJ6XSF9cUnajKVAwpYvMFX6XYD1ZWRCLue5vzAOLg28GvHE0iRbtJW03E
CO8Cdki9LgaINiXku50pBH6DVTiDR9IBHezNwabLjuLCxa72wsj+clufPQLAr15TMSokBreR/y//
2rF+ZUH82g+kVd6Gxd4dhCR6HXze1YSD3dZELprqKZN4Un13AIfDBklDx+MpFmFb3aSBXOHPEZLI
PQHHQF2MiTJ1bZKduGy8M1CrXyGdNvhMQ2D0fdbPRb/BXGtoO7v9l2mVRc9O3IwBGZcR8/H2JJ8d
XaGsxhQcIPpGgiPAJnQZiuYLgaqHYCz8/buyntlJbKnxBJSfDhZhf6gvwy1UC/i4uuyzJgq6RuMG
Xn/IU40uDIUMBkr28ORxRlfuV0f1+TFl169gHjq1TqCnEVSdtCzDM0GJvfrA4qquaRk6nS3KmPvQ
/EjZ8U3go5Lz/iKeDhwGSBaRyZbpVCukRucr0JRllkV8ji5f8NlsqckgFBusWxyFZvXV+vjssVdj
laLlCCJeyoBmH5NgN+QArywm2Fpc9xehR+dQyfpanzWNgs86C9h5MBE5Vn0ft8ZuuHVEzr8T7g/0
txHa5IMjN2dm/+hDuY/DL+chAonsMdM6JW/MtWgqFZlkojh1gys4G3VANPZEzUUyeCOhXpAQ3+8K
ILau+NFbmrQwIF2NDPL3FEEDyKgdMWw8vHBdatX6OcxOTqQrtluA+9QXRFg4Bss7tf2N5HDfvuW7
o+UUphFEhiHPR3q76RTci6j1Czo9htiXOD8eNu0YotwOTvIUOALk6x6KfonxNc/ys1ePUE5x2jPB
Gxph+v9kfBLYOMM54TEqJU/nt7d2N8ELdgUKbS7nZLTxpwVriVhX1pdFxW7Kcq02qceuwvDo22MO
vsVAsFW0bI9sKZqgFF0YQGO6P58q97sQEGdRKy5FEN1OF5/jRfqzmUCHlTBg3masI7t073vpNDCJ
ZNnsevyEWGpyFNPYs9Zjr/t/HZAHzfMg+qF+K928zjvpPMv/R8OQ61Wwqhv05Sv9VprKlrIMxsDA
uvKRwy+z91FKg0vh5e6ZahbkfkLV69fRV4DsSapq+bj1i4CPICBiMCGa153tUtJjfYQvIgwOObLW
GFnSkvYlGPPrcWoxcVAzNURVdJN1JXOVhQhBsix3Pbuig4I0kfWBUgbuk5u7hiU6kqiJC7RWM5mn
hzOn9uc7QkVcr0yguMri3H6RpDO8NnkhQDbbAW+pbtY4eH4R9/vUAl8pz6ZGTiif/uYig3mDh87e
UdtXhgZIzh31+UwAlKFv1PzjJF67WsfxZprru0I20orGT4inCyDkNmu7sVoIeosV4F0sDi/HUHfF
t3KpAXEoEnB1ooIctSIu9nZZfMX6moCpARSbEaRmjPqksC0Layn6VEvADrCP85ZWVgMlS/y17McQ
ZSk5UuzUD+Vf6wQoraLgJ9yiHTP+UjZ0Hr5hWUZd9nitPNY/ev0ulgy/J+SPx6QGUTLVjeYykgjt
+ALXGyypdal1Y1cqGqv9RBd3KwCED6C/3YL+tGjIES8sQuxrLLOuETZX/5+T8UJKt74RDtBbjnyF
bs4EMPL9F+6tsKnMcVbRATlMd7Z0wCT+TPDRQWcJO+ztlBU7tHKDWjtFUMpO5fCday2rx+elxoXf
Jl/AlJcGxOGhosOxjJJ8D+t+Ub13MdDBH8nfN0E8Hu0ZBh7hq3Jkbv2JGvBLa0julAQ3CJEynJvN
WuG4aT0gQ7PzZLcY11USnBK7Bs0fnckjVUlY5BkrPyR16A3FDwEzKVs+9oD8w7c2XM5nOT7Zmvm3
qYAJkqH3wK1iGCh84g0ww/K335XG2mx06JWDqIYZTVvWBZnxqhPWx8WB3O421sQuAn/9CV+hCRtx
obPy3bIkjUYsI6UO+JYfvenRqP5Tn/6MltHHJeFdT/duHD8ZgDuqTFJPCP9KrGdhokImbtxZI4TR
snTUZce7wcpxBTvLzA9mxo9bTIIpIYYGWi2IS6TDeHdkyhhboBP+ReQMYOlZBk760JtRCOEzoSx9
2VZsR+nRujQBxnladao+w7fCWKO8Eg7Gk54JXjW4uy1J5rX3EcD4phavlOA3XJmlUYUJZ0snCJQo
BGQtY6NFC2Qu9T/SHd0M19Fm3dcGS3YQnExB4egnAxFGnOkiyxzhiZgBud+A+a/TEnkm2wmwngwb
+JZzVs7xUvhhcA85hU+73Po2C6i+kzBLUZ5Dm8rjs1mZtOO+rSjSXbe2NDPkqb4OfrT2SaVnWHzo
ML+Xjxmbst0XU/zmrz3BWlLq7E8vGl28A/+3knNnAPZekFZ9lVxORAfESHZuWijMI8iYaXwO8RQD
5JC7r8JBf5s8/A93IVYwLhjr3nbD/yWyKnMvuZh4n5bxqyaJV+hnVTL97GVjN8NJ9VbU0XopCkFN
c4Nfgp97XCFrUg6QOPg3b/ytXZP2XUQbFcYso6d2e++yvHeTz5W4cDhs7mDGWUO7m/VE/oGYQGef
uuIdN7jiba3XKsB7WhvShqZoMWJ4b6TymUshDevGDrw1tbgYMzZtC2wghSGgbzoq08mvb/3U4kYu
7YUDSqC+/5aGMbfe5aopjinzoOtbrjXkZV55vdH6G3T1b+JjpRjClo7Veh9098V0KyGALYtGrkqV
czodjaMP75eXzIdKfHmRMMr2WHat3DjucE/hkeKLMGFjJ1cquAGtJ8x+EbXNlM3J6xPs+vjgTpAc
BQ1/QeXMyCexolzTERkjQajZiQuxaiiCW5wC4SHX148G2+uPy9kq982HKCnX0VgTQkvQQhu19V1W
A1tuF4MNGdmgon0DGC+3N+e0K3+i6CzHjZbKMwzdVr9XFTkwIExaDXqWyicto7dWL7iItw2qcBWJ
066Ao2Q1cmSgp3M8+GOZiuLsUenWTMHicZ9gkBNoks+h8LCRZG4Y981rtGB9WVcush/Ob/t8SXbj
Yi4fTf5XMkQIQeRoNUAj7yR6f26QugtiCDWrR/snDk+/2iRYJMP6mp+kKt2q9xdbcIBqdMnbHvKy
fhsiNcNIB4G7iGQDzUqmQJlHTTI202n3x37jD+bZ59FLIX1DXkSJp5tumUHrjod41IzAkyA1SYni
y3ThDKgL26t+tlXk7m74LzVcCX29O+Wsgnl2HfCWj2FAr7nIV9akwqNf2kRo/YYLi3eqV+q8L9Lk
Yt36JV0YgSTUkGuadjUyh8hf2tTX8aXvbwRFcRMd/dkDktypKQhdgBs+IVihK/NB54dSjJt643aD
70YDkkNt0RT/QmzXiOiEBHgMEarv7oxDr3SFXrIoWaEfaacsYZbE9KUJH8QSHr1xRvBgb2SKVW+l
XLrsqHNeDnAz1aOif7QaFhFrR2YMYI1F8RAjr88nJrrrY9XPQ6XCXrf7eg3ltGiWbwYvV9WfgcCD
E3l81UgoW8kOGnp1ZQ0fzLH0srf84uVTSolcnKmjcN0z+XLrFyWWckv1erQYsa/QvcEvifi716eb
sQOIU6WT//OkrHBsvyR6hKb5BSn2rGiyfechvAge8tS1bl/Z3aBAY6x39qRK+sEQcUOvTiAjaAuB
wp8VTCxI4KjSnAUxlx0GPyPlImqrOcUCFrTVmrk+d0HwJRCKFFV19tgHKdp8vBPql9QGSwIAS4XB
SIavE7ZggmkPLpqHUUvuM5Q7iWlyVySHdIRORUojFmRKCkKXBQRFBI0bPfXGNn3WZClUOnkemSjv
MuM9LXN0tO1l8kKGKdnond53s3MHxEyCOzWKo82x+vHeEx/6hkJ63QubELOi1ydprMEeB2xCWKML
kNIdU+CEp2XD1/YPjJ+T//lqvglGCLR4NIHiYCyQN3Vh1vEjA2gzFiFTuwfl9JYL2DQm3OZWYwwJ
4CkBOLymcwxJBtXqka4LBMRcEdOOCEeokOGPM1z9TEIIAdrcJVroN48k9MspcljhL7lmRMx8sB9I
B4UmVAfL7+ejccBotSzxfmspia9rKaod1jwCniWhx/xaSWz5xSAZIS6JZY2Q4c7SavKaVe9V/TXD
QWoQgUSlqPQFAWqCGofBBVYavTsWcecr/ZSfkcgBf5QYWFBJJhzqjRTrqWHUKdvtO+Fb6JJfbCUn
HknwEMSqxSEMq6FFalUuu3otu7bzNxfVjws4B7IIJcDPjrE084VlQSoU9u1bGB4meHw59B6NQeDA
cK9eTXN+T33Jyw7sFrNQc1IXPHTdHNs//6e5v+9VBKlx9hMAZV87ug+V+Ea4OYegxHZZ+tiXVVr+
B7dJB5+cggc4mMl35wAaoC+0fliorsBxiE7gdjrY8f/lqP6uEMuJvTRKuSArzFb1AX4yAFMCTjJR
8XKvoue7rvUFGMzT4fhQPx7Rs6qcMusvcehmkRRuV/j97jFLJJmifUgoxGSzXWdcZ5Zmd4fZx/YQ
2DRzbgGtq9mMLjsh8oFwCdFsddOffwJ7AfwirDAQqRm7ci1Dxo5LvJRxt7MWTnjDl/znKfCZLbcN
3K44GuZaSKPW6L/8/Zj5c9ise1EFmEei5LvBw32SsKT9Wg3pA7s9WEcRdlkuus22zt/VVWIcVSSW
fqovym9McxCM7s861XQeEwLf7C8SzL2xGQyNJ+RRmOq7xd06+KWU0jqgXNLgcaHdAXPvPw9G/Itn
Sryrx4xZQb7ApiBKbRno/wwvEpjn1PSz89cDhIZF2ddNlRy4jetP5inMGdXC0iX+y29monyOR78a
SH1FGphKyjiec9XXmP4ZRFCkfhnfvHQBcNrIkhGgLNFFjTTPWAOWdWXUxs+AkjcM7ts1wozxm4Nn
COvVv909HOj5/4127dXFSnHChALICm5kayeeHFdsKb6DiwNdkA39uVPBX/8wY9nKIBgUwhgLkoUa
NdyrgrHEC2H7d4Pzq2F0u/yc0sNvO7j4vKh10OuXaHEP/Sa6+nHcRo5zeY93v6YxMpfKPwSYZT8a
rRgKqvd4z815QgfYDTzlmm5xq2CFsBa6mlUVoBleYuKgyLVXqKw7u1KoPfHHqYwptlEdgdvey7sH
Eh+exnl2FUPXbdgvSNy2PgrhzSYeIVR5jdUQ5P+dHOPYP4UwofcYExw68Rnf9H/75JQUWM3L9meV
++nkLThteBramKpKMT9SQExKCy7OLYAKEs9Hh37ssaNhT8o2RFGqGth1KZFhxf0s19i6IG8QglZT
MpjNhTy34YLngTxRbKUXsX8YLvcUZCaOz0QA3F9K757kXzD4rmjJrNisECzusJ+U2+QIIhSu+Pua
uTVQcJu+dRGBevHph74Ad0JBif+TGLoN8H0SIHm/3d2ryY7L+oJovAv9w4qxrwQVvr3IKvVhaZmF
RlojHJMe94BbPmNe8iHbEB+vngMH7sTL7wuYFoqRYQd5xIuf/wzzwD314MUz9r4USUqWHND/9B+6
+Xnr9D5G7YWi0L503KwuwqbBfeGX5o/NVIfoItKIp6eLLrMKUHru+u+1k/bAe+Lvh+GzX40qzODv
BR6Ehe/BmaF6AHa8kRKVNqYW4gMnnWjUkOUqn7NGqTq4eUOk8Mh4bZIf4VbJBJ3raVJh6pQR0h1f
6sq0NumEFjKryy00LqlUgCdgCULFcj45YbBpRWPbh5/geQkiJ/VSrvzjBcL1id8v3t+DLFjc8pK9
oQiOeZzcjJp8rQvdg47JURHZ2cur58fImOu4zvaGRXkN6ZVR6nRP0fgrvUiFnOP97fOF7DtkJvp2
2hDpvC4FpZsryWGCz8U2YfR5MWuIMaSGdGQ/w50r90BRb2D9yknlVTJ8wzusHYdrcYA6MNuIx4j0
K7Xp/V94hKHV3ffRiSeMW1FNmYqpN+7oJPeMCOz8zKgPiGGrT4gAgEBssM4L4eEUSlelRPQcgVc+
IYba7k2k1cdCWHfJHKoIzhS4Ex8zrxlqvzFR50TDVfXfHUneuYT/sWEPjH9v5CS1mcJR49HKFjpo
LgxUNslNZ7Qi5i8vLfcY+8c6HWiEjPrQ/jkk6RxFRIH1WniivgMvEYQXyrsYa0kwO1jOc7DsEM/U
LtpvpZJwOGk/LGreqxSG/Aa9219iFLKyQh9gleIAe2qkGLQYzwqSdow0/o9pCwsqPQMaEdkKt38A
wgGo/XP5vcJK2ntZz92QaTG0aP7q5mjS4+hSiX1UUImkBngYgNIRHGtFD5yCf9q8SpMtn+WZBk85
1pPtSppZTBqx1ZhjJ6sPckHQ1qpznNI0b36xtLp4DsDUBg7Uoe7aMrA4/wnc0Mum3iF0FZyfs/g+
/NmDxr12G5abZpnGOklalGjGkiiwOlKUoqxSlUVwuuYY/een/RH44yrOOVMTmlcEKVsYrNBMYbQE
JjKJFrtZBiFKVs045aEmfq6iNbD+TdyCaNuCfQpwA8NKZMc6zOrzn3PXmQ2kq4kmtRqDQ5Bj8dDT
lAVJIJOViu12knzPMzU/bUbCHpdR9Kwq6t3c2FlNYULOukJ6nrsgwmTVnIzU7SJGM5DM7wQv65Xx
C1l6BGEQwZWWI+SKasdpOfb4LID//A8RBpM9T2N6bI48tghm0eFbHZFpP5pFS2oW+TnRXnvT8kK4
EH1f3J5IiFI44aB5fhrRc7/QL6lwHrPSDRsGLr3rhIgoYplDIY+eNYsRgfbciEERwpEtxn9612G4
Mo4aC4vXwCTOr95nvk+Cjq5nmbxb2+Fd2gCoX3Dg9EhAmZWaPVahKkyxVA6Hr73bZKmxkgDyMcVt
SYg9VZp3/T9z2xNQVTyTC24lZv9NKR7HVXqi7gcM/rtJBzNGhEBIhpdiKSpqYQra6NXMFaIy9ZXH
jvBOUZisxo46JLEmBeGBR+lhiXy843lrqP7/+Fx9dF33xoYudP5u4YuW7pfsX70RMgzRmMX6ZdFc
pmyPV5n8KEZuV+KTFhsGXHGxftb7Xl6GCMVwl/S5dBuPzSgzfKyN1eWHp0oaWk+mzXpnCSljC2Fs
pdWk7qrl/WH3bbp4Cb+2syY3F0UWDL2PTZEpTB3I6XcOAHPe0Q9dbDwK2pSZsOST/XZzhklCOcNF
wBI+TE/P1sp9Jo4jmpwtinY2TuGZG+hUg+WStOUFPt6UYsktxmUZIk2ZUpWT0vQTD97YKtMVBIPh
D0/oyr6wSIurD/0XlASUKg7J0PdUl0BpAOEjtw4CWQb/b8Ty2A4CKAd3qEZnxC/IEacOomMOc/en
LpaLs7Msl0kD49zytIYL6jtMRtJPJtgvVRvAb2ZFK2qtO2VqrdJmyH0GZpGLQRd0aZg7nKDS4Zam
2yE/k08RtT5ljAT60W9aK937eQBZcAVjwVrdUeBTqiqjbUln8/Ol9xZMkO3qVEQuZ7rGPFu7Zu6d
eJzmaKwDvjOAiVInWBmrVDYP7mwlPYlk5xOjk6FuBb5wPOcWz/GArSJNV1HKgJ5BBZ4kJ4LU+q8+
EGC1ztryjnRtfvUpSN6hovzOwLiiGCYVxeq6w/UgvxQu+DzSo9MQNYBZ4jlc5z1U5/SR4BKGW8Nf
+/fxcU3S2wUFmy5XIRzv5JuWgTXDuiJjzBIpl12+OzXy2Qxdg2smmmVECpGWh5TYKGr/9HjXCalz
OuxE1RXtuqrjHbyHcw97iN3TvV68bjEEjRUJEmbB+3hpINZjiLSWmzGXUv5wy3r3w0Rz25Jfgsgx
igGIpxlqQ4cJVVTVXQl/P+ffhv1gjD9vHu8oO+CpoDJt+uImgm1AcxWJ7mm+Klpv5hLzC2HDZaJ1
RBzZk+/+0b0fFZai6MoxUvw6n/Wc3O9xiMnx87umKro/wrU36UfZ3xqgFiQqhYLhaPQvEgh7uMl/
OcQ5saj47XIUZu440y5uGoIVwyqZcL8me49s14KAQxjtCUEVqszYBg5PFGRPiZNOcDZ1FHKUbLXw
4t5i6gyg79IhahY5vPRDYv0p+WN+8UgOBewzavIQeZ0MJN4bSPcwWWdaHjpVdJHCVQNKlkg+K4Q0
gduywLlUaHJkRa3VjAlXfrq01+DRmI4H+IqOOzSLF2Ld/00aX51nNiTzjrsOYX08q3SPQp0CJxmF
0PNrx+la/AR+5S+QPExE5ED1myHxxNDDKF8dJT18Ia/H8BeXyAydhdAXpJrBMRjsW5t3RXqfeyn9
ax3z9ijnWB/le/eyDKBjQS+hequWQ2Rz45d+WRPbcVMgORYov0ZFyGDqbEWS74xgslV5Kmt/UBYx
m8uxJBOSsGgQwKO2/eQ5O79CMWecuaeKW4QMfba086sCQvlmeW+fYeXxnaP9/wpzIqoHLyxeOJsk
MDJF+5LLD+l3Ghrm31+7q4YGkBk53A3lyvF4nCuqVod+AgHXU9zyb/YbuHXvqvfozcJH7tSHUs/Z
mYPYHS7EesFpQpU9AUY4hQ8VPGLlk0yPzfslogpXPutMiFC1/Z63faYNfgEKSu06kiVvjHu/kawW
INQflqR73ztoAOQymlWTg3z4181I+G+yKiAtTXgvtSaxIjH8NRETdPqv04ja7BFZKRPwtDDNvhwn
rMLuD+eyK4mqqUjtu/yYaiypQiDlLoF0aPldYN1Sefmxn8nqCHJg/+jSg+pnVozl/5MqHv75aXhD
8aMXZcTlL6s6p3eZvZUTp4+v9u4fr/+n30wh8yBdtpcK9omp9POMuP8PY+M1PEAIsY7fTRZ2JH05
VTJNfXnGHS73XMuWZaTKSTTWGaeChOwDCde8EWOBuyHcZZb2kp/RBId4xtunuzAaZ1i/OpXb/14b
mtzuL5SddpEA2V2zogrU0RPCHorJmPPNK+j9cuhZYJb4oqp8+E1yd7teV5X3Om8FaRAoK9IKEKcG
+vHt1pRJLZ55Wr7VeFvL+YTM98P+OQc0MLxXhkvIT6lXSypNI8MgNRddYHeePbkmANoULC9TBdRE
NGEc49OVTCfvl8b/kUmkVlJ7KhSQK61iX5XX5Emdsyuy2FiMj60e3FEurSlnRiKpGWFt8ln6J0Hp
KCPIxFPKLM8JDTCqFtTyS0E4pl30lkVzVf8pSEXjVqdMUFgQfHRhB8NvMywSbBKBcCSauXULD5VL
UHQzcCD3lq4l93YA0nRmpcIQkFJsZRWSIXqG/rm+FZry3fr20JaTjVkNoerkDpN/zpdhcBEQavCR
wcFDhi926YSzUsfynMclKEZzXLGEDB7yfwDl8bGnFDpR2L0/OiHbj2bprPylEcMpwJ0rTHP/TE++
xHAtPaY7OOMJhRh3cN8KfMT85uG3/WDy/ha32WSxJKyalMHPA+OMPslj6NNFm675d2Bsy7x29OmK
2ME5qgWH/Y5JPbIaPVPyJq6XO1Rx7OETvpA+0rG9jlFUvXP8Yth1aR8OKuVdMX9KtmQ6utVJa3KL
waolhk1zog7klb/1b0lKucMdznJVJBSypx2rVO1+3yQG6CqvzUpd0cdL/n/Rd3SPUbwzUMv4XSQB
+dLd9FwCejGNhqNv3euwPN6Qn2U7JsNHqmM9qZxFFra5qRNZSqerkFDfrngKU+Au+xevrgoQqgcF
yJEKYi+USJf5fORmyOBIa0JFGz+4UQ4fkJXMncZ1lpBI2QXpXdv641WRK+9CenA5qz6/NbccB7Bm
Juz9y4w/lhC3RrODliFCLzpxr2XXy9qu7mYomvHxY318L+BjalQZFFCrLVLhOY7RUa0yE0BiQf4d
mIlc0c9xfStgCIznIdIOjgtcaGpFRTBRVWrhSb5B4I3c6AekWmlFCnvyK5eI1v1zntk93wdIKdyD
7545Zo/rSFechHE5ejyUx9ctbedBbqF/Fd7HobglMq39g22cLb5f8QOcw4uUbNLeIX3YsAizoYWX
QqkiGryB/wa1p5MwPbGRahcgJ9CzSdU6uT83eIWgp5xzv224yNCRRk7oycPsABwYnzZEhq6FpB/x
4lKGYSfHq39MH2RcgdeTMg6cJnTokhVOSaiaezxQ2xjYqkzrO3bn4zSz8Vl51Mz4ZdV+qjAbvcL0
JiMX5ym7KGiM//K714k0+61NXpzMaz/H0TMcb7mB6RVLcZB6V6YCVqg9sswiP22w4DRvlsGhmTXV
tF9UwiHSdshofyQaaPMmaLeCKA0D7YHgNeUV4UW87M6ZX1XV7EoODBxQuZWhGQQ85w5Y9JYxjgkR
14Kf+4aVRs3Frnj1dzRIgH2gaZ4slIZz2JOBGPn5RrYopYtbawWFGvZelnF/SufEVedTcxXh5dgK
xirccGeh0Z8gRQyE+mpvwIRWwQE9ey2HW2wY+IK1zKtUOOvO7hpO0IC2wSOXS4E4k70vG4PJarq6
GV/i+bDVkrz/MhlaAB34w8I4xklRWnLRYpEgremhFwdUpqji0IR8W+W9jMItTVorLygwyz547fV1
Jy2p6Zfp26/mCYdIq8dfbJwVcMOi9YniK+xtoSybLaZg4x597BrEIw7u+0Rl5WFYoRBssi9qlAgZ
brvXcF1SUjYq5e0ggKy7tGRQ7arRqr9dYC7eCbRljfABFl9UJSPxZWiko1ORFAimDA5n/5xnldeV
AwEBzGspqeedLG5C/K5OjsKP+aSGGxTlzjy6ES9iZ8zZpcJ8nl3qw+AH9YucXB17WYrX2Un1GVSR
TR1jUsEY0y1guT/KUo8tOKddkmoAwVCXj+LGCQkcPYqYN7rYbO6vR2Ayl7mcsYLvg8S2gbQ4C34/
tSpB7Bx+mZav5ZaebF2ON7IOauqCBh19i///khdJRL6Re2Re2irzoGVFxGpisvxHZ75efXU9Pp6c
AMefivg0R2Foy2B68IiDpewSemuFpTVCPl97J6sVScc+TFC6pgwVcC05GE5UbQLsydPfMCLf3sWe
F4KbZS+7zTrzC7ZAPiKM8SDz4Fo6DQQRIIXRLAD3WAhz2S5xZOVbYa0HqRpjjfH1bjRpIcMBSf8R
1CQ/eMF3YwidS5Cw4c0ByA72rmSEIipspuI7mqthjABL/EVFc9pEJcSSYWr/EqN1+KdMihePdCT3
vyD+mM3joAUHmT3M32DN5yVXCFGscpzcQVfw+62n1Ze1tcBTMuNoQHwFrmPb5mjP6cwRfyiOIFi1
rMFzr4lNMJMe+T9DRxPNtgVeWlA7rBBAImuFq1e71ZthzkMdCTc+Y5nAX6TlBJ8ioAEhNuWig8ar
fv5Jh4ZqzRfav2+gTmqQ+6rCPo1JSY+QFe0ul1iCNzNT4nofcQaNTV8TP0SKZGDLNT7mX/NS9SQ1
QzR2XgFleu1CPAmQOCkj7ZyxfZz0K6VWoezLPpKbJGYlGm3EB1VtRPN9u2izlUCERRAzYc4tqZzV
bZjXJSmtpcR62qQd5WstUZOalyGv7zScNNIMPZZyw15bitvVPl2/Hhzi4wdxkR7IMORbCBhSK4xs
OEjCzSc5u+NMKHiE8YnNCddev+At8sbevS3VGYHc3faaOpSg1MqHsYD0cFhOFkAnSIEzu6LdjbjU
fgi//kkwSe77Vg/rCSYk6MmePS3blzpevmTZkrPk4FNOq5R3o8bUxvp5Y5++lO7LPDhXZHNkmQ5A
GpdmW4JlPcmGIamZqMa8uEEORxSOZyRFDg+6+wSgtMOD5NroCNdDN54VSmMt/gS0sAIMugJlJZUF
/+yKo7kpCz/VeroGgqsrKVXOR0f9dv+d4uTLkWHcNqZAt8+Rej7R5DTGdchGcrmB9nPb4bloph99
xkm+nbKfkh2A/M+FOA0uF5R9NO5raEmQAmMoHnDcQSngj6Yrh5bDWAQUzxLKfInWVU6I+qBXgzSj
Sgnhf6qn7eZS1Oiujw4MZKGZ7K5zWDq28+tLHRMSMKStJZNLvFOqLWv5FvviERiTI7zWJFsD0xSx
hmBAsHEG9+MA+QukGJF8ViQgBj84rAmXpcs8zoTLmhX29N2NBkKUxKIeb6nzhRqgKhsZwTYORzMK
+3icsKysrfsWfdDJ6taRhn1VHI9OU7VLhk7HwhU8GOYiKSplq1aB2LD3YKl6yxs6nbAUSmwQYYwx
y3176zWYR9lSGbjVMRP8LyyuAoHjMZqD4sdrhOOvGq2t3MUa3IJDKtdiEoEpKU3r4cAtbWrlJM0m
urrl64jGRlagbcTS8Wqjvyd5LQP2ulpYXJ0xlbmyaykbTnlzGH7Q1gbsO4O04YeI0dpCEMm+S0d6
0dWYmOBGdTBVB8U15jS0ns11UfW4tSTJ9FZX4bYh3gyHI2le67Fov4/xM2pPu1PO//AbbVZF0a71
Bm0nLJ62k+2n5pe+0dLjoesIi2JMWHbGthVh90QLYO7X3yhcki729hL6HvwRyFPLPjNvxwfPZkR1
mIhloCOi4R4CZvYJesBvWqtpDZz6NPiAGSK9LSxyLbEnye+zSSg7EUz70VaPCbiTCsCwbViBLqZ9
zcnGokXxws0VExdcI8eC5TeWoCjhF6xRQXjFhUoDoKr8NvN792vH8/rh0oYkiITrnz2iDFq5LYlV
Xgh8SqzQChuQ/kFT6qnNiy2QGGbaecycY4m7UqS+xzW5p2EDXerWytltXMocYsdMCDwwu8+I+INr
275t03EE2XJqDc3xMVdLemXZUV/+8cFsskyKiU68KWUxEcHPOUG9AJgZDv5xi+ombF9aCyQuY97v
6r7QKBtx6XZyJvqakiFzykloaIodwKE/MGNsUGBFhI2p8ThIGlQeqwHN+GgoUDrJ/K44XXVsKFMn
kNnsKmkPGKnlmVWAAUZo6H860xITGzpV/1D/296olLuNJsiKZ0RBuW7imScmOZOwW3JP2sVQlokZ
ZoHxaUfqoKhZzS8eWm/PXQBKX/+X9QPfpxUuiIuq12NBdbb0ZGvJNqF+8yt3sv7org3Tf7MXGWmt
X5HUlUtQ4Qruqs08wCCCeqRrTnMIw0HZHeFaSSc6GiQUGcLDc3eDmbuJDTIRIITJoAx5is/2lBcX
7jNANFw5TO2bx/vXFpqrG/9Dj/om6DcTb0PuHQFqazFGzQzNUI9h122YSrYgNs+LyfNICJv8C0DY
UefPO95Evybe6QnltCiH8EFsH/lTAYX2Ad3jg9VgUusmTOIpdFos+TTcgoF2o64TbloBx/R3N+Hw
N3z0vZGkr1NnDFqfQEDqITf/XwYihoYo0HA59vNh02iJ9T5usns7fRUlR+wc4PyQSIkiLy96dnDr
k6OiElBE7CeRdXVZI82UeINSwl+xP9FXIO8yJPjdO6bQsvOg1cdLMmEXWiEbBeQDD/bLlcUEAJCN
7rkvptxnrtHgHwrkKQQp/5em7o/zzVeoEKEl6CTwjIWV9LJQirKvxqZmsByZk1FiBL049Mb4VV4a
MZTuBpeN0OB6qq3uPOb0a+Q/bcw6riYb+tqgpnIfnHLvOwzEdgqT9sQvfS5KMoM8eubN+v2g6cLN
R1x7VHuJxROaXbHHxwaGwH3VmpDljnLd8JiWDIeDKZFqXPzA5vZHDk/vovzbGUmjZKrFB4D2f8mH
SIK1C1vH2+Jg3ur+HQQuHgUk+SbV3F8TSluK/7Bv16C6GC20+iWaKcBjBsGOVIMUegKxw+9oR3wo
cWD+zz6O4hLM9Qx1nVzLDa90ugKpKVxaorNhE2cMwoIQQz46Pi6tLT5lZqSTYicBQxU6mYbtZy3n
wpsapTKfm4qM1dj8RpaDvgIFwTpqc6efZ2WytSEL4B+0DdbDuTRlGD+jmtmg72wfL0TXrDDxRrOZ
JcMea5AwV14Ey+4OMGUBnRk5aZo0M5sABkYguW4FjWXKCRZ2sOChld0tBn/CwyhHB+e/8Q2m4F7S
fQSosbYvCQeWxK9JLB1bC1+pKQXlp0TRuVZycy/yhAsPsSoFdeTAkbXKhkFVHGm2ARf1GTwE0GoU
1xe/XFx1wfFG41tO+BtoXtWmR0K1BGo6Jx+2pF7JvldLMQjO/fuJZnVQ0wtrGxyWqJdMiR8MEoLd
FQXF62EKEONMNMOckRNSM5OAQWQFoPLcL/IUOpgaMLyf4jA1YL+hdi6doVjMZhL9AnJ9ESOs1l14
SQQ3RoWeIcNypjiE4fhyqI8rq351fJ5gwvWeCV/Krl+WDeFepNk2qdi1yZ9gbs1M6dTq6uAV2zy4
crBDQHJtzyLutpJLmQ4nSwjHcV4QkaLjryTUyibbj/MxVQ0ngdcLKJjgMY/GmkDt9x2ZE3Tze4vE
kXjIveoO2ifVhCWYpzZe07+vavJUgm2BKQ+RzMfNi1l/g/HFyV5Uc//8oSjfUyhOG/aSsu2081yu
7+UBuo0EXfW3O/Txx8T1eISart465zV5ysx94T7QFtlN0ucNOW7BtXzw/sPmHvRythkBjiSgRmyY
dHwH9BWm0xuwN1bXuG1LeOYq9wGc/tPXP72QX0x2udBiNU7/ETQ6sUMiyRxqLtDelOIAJeMCTgz9
LdzFL7Pkq/VriW2xSkCi/6LlDvbkzy/F8gbTJYzkO4X8feKOdi6Amr/y9gQwNJc6989Ss++JCkM1
MYLfoEgD9BWc3dUEpZc2ijKrYSxNWOAnxkeh8fxhkl2gTAx+oAXrtgpccbIGt/2IQX77dq/loIxN
fcCdzABKq6jLH8pgFWpC1hJoGWNzTiHG/OdyafPkrYjx9bdgH6rQwo0riyIFtRaZBa1moUCXcWA3
ISfGgpuj/HEZQD51POeyeB4vCoUOetcwvFeKQlSCVkVe0uc8HJAxCHZMidIa2Kecffrct53Fak2S
7khm+QIA78tYx8ZzqOi4Olm0c2AeD8sBjbqhF1I+ZlqzFInNe3hnOXa9WTdome8JqRuUBuBYZr2j
rUWp0E7DtTjH1SGni77/Lga+dM1k4XKxMMIJyFZpsEg5WbbaZntI//mSNR7RQ2gyMt6Z3TkoCDvO
6mG/mfDfCdQIc/B82Lpik4JmLMusVdSbU+zxXJv4GKe1s91ztwl+/x8/zyfsZGQj0hjikqFLZTFi
BJ5+MXs57deHdJ33Nqbao7x2CQaA0u4p/ebDurr7zTG5t4zCIRcjgvjMZGZujcJxTqD/h8zrSh87
Plq/fOxceDR5NYmG5Ow0unOXCsG/bKAcKo1A8+R7mko8WsNmSE/FHncRAzr5AfMM3ffUAVZzY99W
IHZyEuHCLs9JngBbSopX62u+/hsAM+ms12gd7L9wvPzCW2Dlqvi2Zeuj+L8eBOgOtrJtMLLjAYto
ENVncwp5TJnfLS7/0dvuT1VjXqdeBCB2hjD07PF1rxzzGAC8FIABRoTS2aSxD1W+o4oi2YnHcxht
L3QIo7I8jrLK8o5rY5P9SX6eG98qv3H5Fro1PQJU5SbIcI2h5sCrAv4sAiSgj/DOVtNtfjbvpN5y
+lyKVrb8Fwl7MZcV//QOe39RDVDi7cQnq9OoavOOsL0c5wg+KUE8vkj8YrQtjqEzifyWNIXCla4l
VkuZMKBTgvnIRylsHndLKD/Gre/stBDq3OfoR5Fs7AocMntbESnKbmmeLg8XgcAjbcYw+gxq1gBH
4I1L/xaEvHWJ710sPQmghm+64Wiyb4OAW/tPP0kSnE22Fb1Cz1WIkukCqAhAWKieHZifsZNNjh9x
D33meytRgUZcBCgmpNqDjqjlG9NEEkRHVg2f0SF0IPX86VFFiGdW0eC9K08/7T7HX6TD7ZZaFQOG
lRu2s8EDBhfjnIgULlVnq7840zhkqBO0TmyBNHp1b837QdTsIfMo0/JVBDZUAUOj6lA08POBEmi8
bmc1L4Xy4VTTE7EF3ReOuxi+BkRwmlpY3MhcgWk2asuIEfttEBox+Y3I1n06b4Hsid8ERxDHlxQC
0t0ycjVBztZRk7XqJZdIclYtRIq7FfuWmLwFmInzINgoAQS1llRLGXP4WnrAAcB3gK78rmw7Tmf+
d83SWmoHzJ0tDLW7lb7xZDnHETjEpB+2YYmGYaY/P9d72aT0DP+63iy+R3OOJU5u0UMcBKZJe1ei
RlcRAJGgi9g0uCtD2nGVSayiINMyb4oV2Vo9KD6+bJtPeFXhUntcNjp/bGHMo+gJHikkbmny8aIN
jRvy2+MrWYqNFXoyiu0mWSyuI3O0YnULTFxw+qoeVAhS88vXqyEw3l1IxQq8BY9iJZGT3KjEMXMj
7HL3WWfWkxI+HiZcyUNcc/bd4WYmhLgrnRrG552MFRl/mc2REknZJKbRt7DW++Yl6CC5VspaylKv
pUn5xmCIUO2JOFeSAG7IW2PABMNKPiLhn4MTbYiIw0rcXR9BCQRmOtK0BMLBUZKZKcTPyWsyaoK3
rcc+HIXoMsCk05RiLvAhkLm26C/plvQvz7FYCHP1YKRoClZaDkNh6iFaRkpNMSC9tjD+rRr0R+B9
IHqgYoWexKu3MY8h60udZtt1y5W/0tT2o4/HsfSCR/pXZImz/5m2oklN0CP5Q2LFGUVxqM5eXK3S
iWjtwGTVCe6Ogty8x8wCdtNFSgIkHNLhut7diHQSB67AnGmJg7w7EkrCY0cMeJvHnLc6IZz+ySWX
ZcDb1XXt9yOQh9Bx7qCQkyXPCglmgyh4HV1NvVtkCAnF6M+xBcqNiZWJ1FH6XqoypvKhUODB5Eb4
uVrMjbc6dAuEMyEkeUfLTPSxGxtwxs2HJttUAakqf/Qr+CpJTKp6z3xxXopSUfj3c8WLnJ+14fP2
ewgbdHLKBUSPeFkk15gvj6anvbiqLIFk/EZZCnl8lVwuaG0TGzmOr4m6ptLH5NRYSJWN6vft0sPE
ihcOUk1fi/Nk7cmppaAto3dFKinv0wVHXbdWEzxuK7KVsQZiErRa5t1k6CCNWxA8xfbaWGwwFRHA
rfJ9DwUbg44ERzhH0krZ9Z5GAJ+8fQFacmcfW8lWrsqPCD7o40Y1DRbSqTKrOfB0/PyRFln8h0i2
yQmGB5v9Xyoau6N3OqGRhsNtqxjQa/pxpctfok8Y9KV5LymycsUgRj7kR3sGevIh+HeoMz9ljtjI
lROD2hMx9pgvj4ac9Q+VFFyFgMEyhi9ETNS8X8eQLvaw0df+ufF5scOu8Qoky6cRxMeDUOs79adP
bbeDXdxdQ0QxibyTEOewFPKwdARq3E1Ftu7F7ZRJI9xql3E9lUFwVzK1nsEEnXwPajB39On5GHfN
llhhpCJqnRT+b9k1Rc2oxTiLRZoBKglEopbCpWmvg4LyNcU7yMq98smgqdgIXrAD1TcuJywFtvMc
IiDyEoplPu8zxpMeqn4Qwdl9YKREBkGmaIZkyEjSgrS276gF71OFOOnbgKaaX0ddT+wXdEH7bqT/
32a6t/9a7TOtexHGQFxu4XCtZ4iueksYywHBj7tm+Qhi1zz+dTC0uduLspS3oAWCjQymzA5TLpoi
D5zgEh1/hcZGO3HPHcgNtOd6W9o9WY5Gpt4+Ers3670vgT4yQtVuGpDHFhiG8CHbInKUkN+FPsUp
sUjsn9ysIzCA/nYjTppv577/aZy77yoK10ymg06qGHykQdJGyeYmb4qv40amPKVVJc0TwuUOLIf6
MllztGGEH2V+7kT8Tjb1JGG3VASZMZiOcgl3/qJ0DJC7BlreSV2RgFeGunx/bClfFQnCU4fLifub
nIeEeJSH7hGPkznHnXSMfmT6EYTYfKso8IyT08Gj/9wvDwLZRZM1gtM9J2jONx0cC3zIhGqxuCKn
Aw2KUZYMi+bzUX17z1+USYAh+GWR9MVfBjhcYx8TdvbPS8Qw6Xn4g5V/TmEVIDuxumpG5GziIt9l
0VmG/uWYOkHtvi66wm7i6dxGhdsROvj9qSBxxQQSuw9bNLMc+mC7idjPHoMyvcbcPBLUlSOGE1lL
8m1VgATVMUpwJ9Mjgt3mXlDk0z+NseRxX9hMMXf+UNNfaydLII6IYGIiZWDRog9I510Fun2IMNAn
3hg2ia6AmI2plUr5flJEscvR/CoAKs3X7NPu2tCBtBah74E4O/yip0s9GtbBa7IyzPUu6qTpt0pg
+Gk7t11zVEjsPcXa2ZnZbilhgF6J0Lx8K41qBpbGQcciB2Ogh63rixJCfJVIquKXfsUMK5gBWnq3
cxZW8PEgacTauGg8O3I4E54KVuhGfnnyMGCfS5QGgoKo6LLwxXrf7SUia7y0sACRsBJtVEQ44iEO
FDpxXLHQyuBzXH/EfDpdtacGDIGWEUc8p/5c0cbzMj8MdaBQjJ7xfgm27hRg6dh1Ld6eE+P2s7uv
b7InKoWl5oZmJE677dtQFRATM2j7AFLqclKR/wHefvdtP6dMFv3um3zQ3I1Xd1RGQOTtpDIMh2s0
8xEaO4PRl3KzkZJubyM2+bYf7R7NtrPFqQtx74LwYNWc4HFVdJ3duKd5MW/YRydu3DC41v9LkdPp
UT7ZlxNHLxZLVwJ/sCrxK7A9MpVWZ72Ng2Mq0LkqFDYYjie3OARImkTWbL8Gv7Ot+GuZasFafZBQ
JxyOj8b5otER+XlBhzkKD8o8D4JdRsgzRH8VTrXpWRiKgBQNjylb7+EDPQDtcY4p825odm8ICXG3
I4iwvoJbJfhQCiatZtGFacIQUPCnGHc5/H4wkT5944K7ghWKLQGrQ90rwHMfBN5hiCxaC5EwSbXf
PClbfefxszSJZo4A4MYBQY8iocGpeMSrkQy+DnP04zTIwjv+mbMHyWEpkWogOmyqwDehXDRjeUvk
c8XelWF+bjpJfC035Q3pWo5LBo7qw+LZPF4CTEEvT/gaySrwMvUNkG+MoQlqEcNZ2GnF42Vi8qLq
8lD9WYAj3pJ9YLrsls0G2FX9B2MoHWn2ZUKJih7eEO8TqLZl/8fVWVFt5YVtsd3mR5RY03XNwOw1
mmKNZeLCo9mjhSPpLXQEYTRY/kxvyiCccPYHoQcMAib65Nf1zx0XASPyJegBx7jpsEuYYAIudR7H
d9Yj0J5n6sy3XWCijm5VlzMyxoKYo47xMMn7solIFdhnHYGqrkEOHvK+1nNNrNOArsg4bmUQnhc7
kCij16jHqJPUaFd+S2TiQGN/tO4fU9QM468bx7/bzUq4fuHe1v/rf2bvZDTLmgt2Y61LRt7S1Fjn
Hx35YSdK5h+RDSCGUmKozeVuSkgU1g8G8e2Oxb052Zhga+LaaQ5fTZYxw+pK0yQB5nLpVwckZ427
dVJOSOu3ntRy98+jR5SmYfy8NOpM5HVhyhnD0lvtRdqtUXJB2WXKsIj9rNQTQijsSr1HSBs6LdjB
8nIe2AOHkZs7QHNe6S4SBYjT2vFfNDnucr9VuKjPl1irCH9Tb351CvfOCNSWlKa+Ao7I1JydsKPr
mui7FY5wkr52sJCu3x9QIdzfIqPGf3aPzpPjwM8HDKzZjpYYn4h6jnBHgqVE/fMBrMjhWYtZHSey
lUomFdmaJSsZ7e7kqo0IY5UAV680i/ju4GZjSi1NtWK1p0ixd0br/9TdiJsDMb89OPNAuoqfIVIw
FZD/s/2/kbmnfwOBK4fGgk8WqfHF80Ml7TxHjgKYaNblSvOxw1vE8Joo45qO9IgY92aMR+vYC0so
wmEvxLuyq5V8cRgM430qln9469+stL5PTVkgPYmqzRbEcZhHjm+jDu+keLneD1J67OMstmAGP6lr
YbX5Ozr1I91uRux8gGvCS+lHbStpDSpFRAmXZMMvySNuuI5W2oRxVnEqNEOowwmfwrpL10wi7F4S
Q6UwwKd2vkLV7Y6oahsv3aiFBI3YtEz83HabejiZlVQWrAk0JQEHJfMQ4knv1ySxqVHNJwJ+szEa
uFFYp4Y8YoEL0hs3oWcp6k6F6SOJEDx62cA/grOXTMJT7Uo0Ncq3DvppYc+/maR4RyJ7rgB5zgYS
RN3JJEAYgCAuKeE4ZoTUmtTHf3ENW0+pyuxwbEa6x/V/+J5z3ICHPJwSNgih1+CIMvnal4HE77XK
1xK2L+gYT6bzMbEiQ05jtoMF4mxAzxCkWqD4tbg1n+qVrtJVZVlr0I/l7NlFPyfJjBSn6C6EnRfq
Efi+siccesITQAwimMRFY62t8iPo5jjHZft1/5kUr6et2Fwoof3DoOgwK9oKM1FqsHpa8cjwnftg
L6g8s0d3rg9aMX2oXBuQOiu6Ns0hlQFT/BngTgEL/I9pxek7CoxgxeMhZNnM50CQcMhlktlIrZTG
qpSJ7fjtwyeVjTtXsint3p3eYq5O/hGtMCi7Hxd2KPk9ioOvZfx6Wp3gL/0e7BFlddpk8lz/MxwA
ZmAQCPmI1yXA8/5KM/dATcvV5OSLEiitT7GXuSQvkzspubhLhxo3QWUaczXGwRfoZzAjon+NsWa6
BlopxuFpmBm9ygqTWMkY+FEhyUkTttoQ0vCkIFTh5OwNOif5Guhkv58II+g2C0v7thCR0dazHqFz
uLkQVmhG5SmPa4/JcKdQ4V76Fu2v2hwjP5ZYCAI4NEKNjk4z1/QQ+1JFsCJoquHTsSmMGnQoFNmA
vvyoR/jRpXzAPRo8i90nXz/9tZeeSKH4rJ0OicgQME/p6apm4L4a8p/oxs5QdvbBAq11rOYWzDb8
jvBkPEGHh3sLGohZMsn11jS3DmR3LcqOlmGxQ2ai7EQsSfAAqEV3dDiX83/FPKdYW7KJWQ2T/uXA
SLfO8Srupjr0CRYw+dlr3WYBqEQB+JO1EpplBDjK2zFHaaqHgN1Z224woxfaE1YpgEncZXp9Pl2L
d+KzUVq+LPaKJfk5k3DgQlidNSqFUjMXjj3yAcxKzOhtlbyg3dp7QZoIGU/f/OAZEz2qXsArl3y5
skOtqDgwRhskRQICrmxXy/Eeh0iS1y9TkBnPf6kMhnGV0lGen4Pq3Ght+aUXVkjw7gNFIvG2vkG9
/hZUYhFCX9x9NFI1FF/b4ytgk2e6MSyV7HDsuGZ3uTt1KuwQz5gUebFtI9ud9GJayDAFdsQAUsjy
gEHcnh7qGsMR9EuX7P4NJFkjkoDhoV19pliVUtujdCO9yVGK+AXIT4gmN/H6BexuVODgZ3tS66lK
xn2Gn7osleDP3+V7jRc/3hxGyLyLe6+SKInTRbgXHaLMuxKBvRv6Sx6+MhjwEY+M8LkUe2UFDcvF
UVNswNDiUMXfy8zLmrZcS68KYrvSkKvNO+fPGW89BwTXaRpODlKTgrWpuc/ekw7tJAbnKKuYxuEr
UauKrrCKjdL1R+V+NVhNwHZX/xAOz4Kiq0jwSKKpsEyP0+weQEKGlS/O8G20KDlJyYN+2X6muwR9
QCC2K3JAbt6ikWZaRndiv7eBK8uJ9aa06lsKSdxB06U/dJy/7diG+Sug09BO9LwI4VIieLT1KINW
48BeTJsYAwwfxzs7AQaqEfZ3BED/V0NxJHc5E3gzVk2EqEmD0E35j0cQn9YQFdft7m0r4RQBd6Ie
d+84wsJZNzMsAjRAFT8bIwCytQ/LzoZ8mb6W913dOOidYyuR9NX/iInJfUmopygMazU1qnJzaObL
fPe33iam7Ms3U0BbdVEJtlc0lD5F+67pucaa84VexdpXRjQZlcidVaYzUBlVzlEm0gZRwJjquhQ1
wz1Rd5SsmOUF7jTs1sPhIGBaL5BUxKmGO99u2p/0azfz60dD2uJ4I7cYBxXHSsASuD0+A0p60bBA
6zuMloWfV5dRw6r1KRhvBKdLjjduSsmbXm8xNv+eEZuNcLIIa2Acs8hOCUm2mPrf+YRAdLmlZKsp
xU6T0PSDowxEIVHv1LTD26DrlVj12DZGpRsx9Uc9afYBIuW//P9twwx3npqEDbbsP9+tAevzfMgu
UL5iibjMS5japEfCvnV2BKFUF13ONXcAlAyNL9h9rE0rM7AsTPCJE+Euj2MF+l64jPJ/uBtANg9S
JJ+jnlxkppHCF/ESw4m/W87fOsZXiJOL8E+RrKu1+7YH2k4BKTBdGn1Va0VUmsibbSpAGzDjxoBj
DHHkuZ/jkibGhoj9atE6QvFo6GVFXcpEjxx+/bwffSmLqIDusxjhw2stjWmlPJ6e8ZDTcXP6qB3a
Hk1Kqda9VoFiQ50xkz2hQfIrq1N+tEmtGZcNVT19LtV6bV824jbtlr34IFLIDBKH0SmOkJYeZeMc
8p03azoqw29WoKDPLicKgL/T+gNVGULVFzKnSTo1LnJN2m4wIRuBYvDb2tUujFnqNvQMkLOmPwaO
2Z0Fb6egTPinH/ZTmwkVCAPAwaL1do7CdY9llUFN1gvzhhvfVLQriVXTA1hJbZIkArNs7/XvB6uo
1xQuXtBKLOaLj6YSbbi9KSmfAJiKjLCaa6w/m99QjzR91p9zBcNyJJ3xkkifHNDy8SNcgbIo7BNt
06zg1mgbrz5ClP37YRgivFljzO9c2wZLF3ZGKD5Z4ga3NIxnrEvDMpJX8cnwYS53w7A5NjgINgKY
l8Wszj0GEuVprOgeRteHWAcY+hp+ZSZp4LeCeE7fjPfHQSmmNN2fggfaWjQFYRrO0AaaPYJwuotQ
f+AnXUqUyR87wut0jmZ7NpaIQusdM9Xieu1T+9CfkkG19s7Xpcw2npAfS52UNuXKKonI5fOrFANU
4leTG7QUzR4/rE0s+2UoceQAd+F7LEjpjmllhvXDwi5BmIGXAIhBkXj8xE6br4gNIobsjBfEeqKV
4S5GSn6aSaIFHaMgZWCbb76RnV11gkpV5UtrO5qI9mHArXCzZTbJ3JXM6CM6I5EGjL3sp82aDVhz
M8Pw4ELjCkoDRXMWUJK/Lh2nJ+QlETIRwsnW+/3S3+8Li5A817J0p5jru3AD6oLG++qlNVYss/9M
vVZvsxRSkOFyTPUrDyxcFno/c4nb9RHLCeQ0/suNomHytB6WBIaJCZ/+pYhyI8rGZw56m2218QUa
yEG8GiL0qT8pPdjotpNHvJOWxTV6qy8uLbpV9vbygx2lID5/XbxjYlXhY7vY0oOthpdndMFVvUVg
8GId3x9Y+b4POHnnvGeyj6KeANlZxCUuHGIzOy6f6a7hwnNxLoy2Yl60ryabkbwB0oQDYMrgMllO
X+v7DuxK8qVC8ce7ua2L46sc/2un16I/GmkG0SIdUza6a/DqWump6+NEM8zlF4yMSFSO7xj4SIKf
ptCAcPQ+IE/MXxvUNZQAiv9YjS4166pvaGgJR9Z/DWEHevvMyqbHWijYPH/r1C/yXPS3NJvAuhrJ
A3/3SutHk7c1bJisnSvO87/2agOy8rOBXFt6SJoQ5+HJE4QpRipOVB69qoNjD2TpazFJcBimMx9M
XFzGwC5Sv5iSHpyhtb8AJr1Sz0jCQoPj1UWb1cqnZgU6NrlKfucc85FBudot2bb1Jc+xp/dKOl3E
ynBuGJqNaNtpQHWFHNQy2rZ0XvDXZAz1HfwxTXNoHQEOSObN+2YTBBcZm9T2GQ4sBhBTYaAWP+ll
xu2T2o5KXbSXuuEalXVdizbF6ZG90Ps10Aei5fVmD8mZQLHMl+Wy22idWBWTlZgNSC5TgAlsTPMK
PBP3jKcdWunIi639M7I402rk/+qn3lQK0WSV0V48xrPzk1dN7Njcx50bL8eYYJb2KMuYuvEWokCy
IDrEFYcyKTfVjOoVhl3tnYG248PhDDrE31jOHmpD28eZZT7EchvkQgc1usX729XaKe6w0JP5L3vq
Ta84ncMTVO1rV1lUjdpbRJLhC5VQPYXBtgK3Jy+OZwgJTrO4eh6ViD+35efkwDfod5rVG6mBMuyX
HQG0ObJlD39mJhsK4bkjVSi4CHP6OzBjH+XvNh3k6S9ZF3Z+ns3FLDjx5Rmv2syJeoBDGh7tjNGD
9ee+bwXPTmwJzutf4h7rD/li2BKyg4xjKHweJ/JfcsFUkGquS0f/A84dPJEeSzjPwoybhMtdmjYc
Jk/DMlToh0GctIkdo0GVT2xynRuolgNDgu2l1hM4fppxa30rkiJkMgTn9LiSQkQk2E1rtO/Tm+/3
2H5OV6j1FFC0frwv14bAGFr5fpiKsrwUxf8jpyqEJ2qgQ/WkQBaEIJKqfq0SRsBrkiHvyhnwCVrE
nYWyX2jjTt+wpDGtigcF7TAUpEBSI0CYxtlHWI70Yt7Vv0IErPpjpozizEe60U0DSfkxdF1MBSqd
UTsEPqAxUs3LN+zJ6XlrER1zJdfpXg0wxNvWe+vEc46PPkx2LGOVDxrh55qY4Y7scNbJumHw8k+h
9IAWhgkyyP0ODyQ7XeO1+BRxM3hBawDl3cOSupbqtYYD1B0winH4WTZOl05XNsFIGKy+j3A8OOcb
ooqp328UHN2lAVQm4cfd8wi4m6WJyTLsCwj2Q8ZBtXQcgihmmHhC/cMZWB6/Ga+YR8vRX4X3N7mH
kba6LHwBzX+onc0jzSD7deQD/YEukp31Y+4TgWLJ7EGt4Qk+C1VGf73FW9HBjj52notg6Z/VRYs+
oTpiS7+htXq4KbsKTofixkcKWjYX5LxZIvQqSe08QtQMYit/eHix1CqtXC6kh6qIhG2mw2SjqH3U
vFeO9UP8v2UNTsxPReVNEUU8QG89sN0OrK7nC+pwbuEXiDdHvfO6ybaTqYH05eZyQ1BA3zUNZNWP
o5DNBY2hBvIgEjitgzFFmWjgGRy4EO0KxMSdbQzGhkFkdH4/Myl1E1k5FWrT06tnMPScKq7w67Tw
lfGtUc+VOkoJjoVpdWqHUeoi8u0t1+sXigV4+Z61fKm8tRheq7U7Wfe57r5TqA1sE57RKiUa+SuA
sXwPPESMRjqxa1E8QS/k+OFwEe7aOIKfHcgbtuqUjrAWgcnlBa3FTTquPALCwob1IbFjcTfq2EHW
5dWm25Y/WitvR4Y4/XYV9oTiDCDCX0mSgKT1UAbCmaaRenXWuPpNxMBMnLikSmOCpzWChWo5LNhY
ooY9SQD/u4SWA1DsfNDEHAqtrJoUfIv0ONxZIqMsxuv+poWSak6GzoGM2FjdkkVn63mczqjUftVa
TMJ0fl8IH6yQNqloqCBNW1DtJvPLSEj+c5pK0C1McfjBYHIHRKgIlRDB/o/F8M1BKLH52hg30xaT
QlkrqCM2+hQaX5dadnorweC35kgoUSTg6slOpLv3L43uY9Msy/rxgIM7pBqY47nuFR21+5Ph6nZF
aWxbXn/weWdecB+6I+qnH65VoswPELK+MmEjW665Hd40FjiJI0cLdQHdVjLxUW4yhVMMK+BsysT/
BcEgPnz3mTdIzlvV/uR1zH9yB5r7obJFEBIZo8/kcJIFL2LBeKcNAGxXWG4C8H6ywiT2zoh8nlgw
8uNe2TIZiST2JDPGUX8J0tLuNktr4mNJOBfEZ5SwNm6XoVC+iQVkXzVV5Mn9mn89s74zFE0U9ImQ
EBlkXcw2iR/1BRj1HNDf7UNteW4nnJNC4uqAqmGChyNTU3UsNtZl+FOjelb8P8xHVS4c6yZbXH2i
c0tA0Fy1fi+vRcJmrGsgMHMlsvdNhZESU/JItTU8LzYOKFkFNu0AIYxPKEz9YIopbaK6V+JLCuAf
3NlBRKw12BQy3eoZOXsy0hsxbrazihDWdCh9z0xdpljRyVhzI7Rm9kJq8/dTSVZj9VAqXi7sHS0O
ty/a68NPZigeqTme3GAxg1jfANjbdTfa0GNq0bgZDj1VijvRo3KHV84a/kJuTrQGWBX1GrH13VrA
JVJoDmO6dsMNUVXSsUXbG0EL+jzeZ82HRm9yTI3jLYsCF0FvysM1dK/spcVTWCWO72DXyCldIIoE
lBYOaaCVKBd7ia/OUd6p/kTZWY94fNgzsLj7Xzc6/YTKz20dDxSIkTKlDnQ1NXWx3dzIDzVWlasa
f28T9I+e4sOk1ZgJ9KOU8L9PsByg8MEQPchjXfcTuJsDXgz7fwjWZCHf6AF/uV6krrk7aMJ/2Ma2
Uy9W4FXwQyPm66yxY2xiX5EKP3oJir38QTx/X9vohpxM9rC5mZR+JoQt3RrQSGSTZPdhf1z7soHx
nDX0U+MLu+VyE19ZhIeGOXuGc3Pj0gRTjNMmEHxp8tobt6/EvtoA4Y2T0I1QR4mfRqDC5NeqElTH
F+bB1YAgbiXmYXMkj1aeyVe6vI9denfspJpBYZXSAKvgHgAo51kNkPhqctLjuYDuVIKVmQkQU+vM
sjz5z6Z+/L/J6OGAayfmBu2/onwHlemE2oDiVpO8s/LBnWNFXWMDwTn4y16G6G7UTAAJl8SEcQ7U
OghBrLsoiZP6DJhLnAnJSOkrOp1Yoa926ajfeFTy+AtpX56gCCXx8WAeSIFrazKmARFvEaTIOeqp
fOSo8x+kw4V5Muiaw7buOqLrxL/u2jK707w5FHZGkEOMerLelNuF1CRrDTLUcrOh0CYO39V6w0U9
N3eXev+VoXgqfP9ztrH6axc39Pgl7AJK+LjIclboxD1mkLswEudqgXF9am0NJTvkTYh4DZDDq2B4
OeFBwlyVR/aX54/DsXyul1q8zkOakp/v4+D7bbrba7sCS/8bxn/IjiNyDXE1XB22B0xwNKyzy4aB
5jcvQYKPzri5n8M1m092aug5B98jGx+GOsJl/A/viABKMYa0mxf6/Gv+1t5crQ8XlVZn9vktTjei
pFJET/fWPFHMxOteEkIVqVhOY4hs+mUQcO+JqbzzFlZaEhx1mYouN/nGhaqc0xs+opTVZ+7NKqEn
GV+8I+JGsyj1ayiEiQ2NIQgZXXXh+jNwM2FzpKjLexcWGZd4NyxBGP6QtugLsv/o+S4aUrfrQ2/c
m6L9hVvmvsm1MFfVGaKWC5Gdf6CugYSHjQvKCfaq4kEWK4xRYIK+AGTLFHBR8iFzqLUG4lNL6J5+
oJ7srvUZ1itEj3mx/2eiQ8qARabIZDfSQdxxokohjvUKDW8OAj5phwjetjEwS9x6BnuvoGt9R4M1
GBlsSyMGic8IWelOogVnTvjl5c6c6xVOgrV9lym41InkKUiGLXrSMytx479/cKGl69CDgPWkPMTZ
lug772tcrnpgMzZE9Boov4gyGA3V1p19jRhWeVvNTb6m+LsBZt4/B2rkfy+EJ/sgsPI/Ws4mIxSF
b0k2LiD5Xp7A5YYYf9s5HgHtfIf/1k9t6n8qExVwo04qfeTec/u9jzFp8aBJHVdmXFscD3JElAV2
GlFgvVtUFPmbY7BzsoEd10ztz6uqd+143pGL3KXYEBgUUdAIIWQlmWFUPAeGvAC7ClHebi3DMSXW
g+SdTOr+4kZe+hfyjhJEsYfn2X7yddqMapyGG9bGWggkvsZc9y2ZUW6OHiyBdUKmqlJZ9DX/ZoVZ
lUBN5emZy8VjzpShuDGW+8x6WidOV1pP1CjrCT1ro8SsL+wmGVTz0/UdTjE86o+90VnwF0DgercF
wLArvzg0qNgdqplUQTVSYMj1zficK1Ev1iUprKkZWMQ7JGk6btTybS6d5PUQ3RnaEmql+OBZOpBU
71w+5MF4eGqNCOCpTjuFk/kQtyjcK9ZOmmG6Y3UDqCFbrCYmDdFzXrL2fR1qIR53oDhdCgjAAUPf
jnzwiNREPTxJJ7ia37W0HgSMujPb0NAwwdPlhi/F+MJ3vGcwiCA7aptQJNw+zYgxVxJEJbf6iXPT
U/ViXY8FG9f5i3rswDnXFqjN+lVl8nFyir5ckxPMzu80ytN5muMDQmnIaGtlR3Nk7Wls4zMZtDQI
I50yQUK5VGuY6GXpFRpblAS1fg8yvNvmC12yZthjSBgs5wUSiBLnfy3bOcsOJkCP4mh5xqcWBaI/
O97ZJV3p/X9CIFNKoe4FtSNIbnd5pNDGzmC2eol0d7kESFzgOvPtFejgNgWVntXY8eXjbKeYa6qY
ZHhgAZni+YUZ5N0g/93rpt5VnXverFHVb6UA9bV1g3alLqxsPS/kDSH+QCg5tbBl1RYDVu5Q28a4
YaT2Iq+eBqiTI2pWktTpwOPc8x+JoEMaZ1Gu4DoX/UuBTSPmld31HLXEt9IoDriQ6vEGOmyQBmjx
rs6whPRA9YNA6wkCdQvu3tUdZlJq/+Wg00Clh/kGweb0fYf4hAagG5INj3hGYi/FLJxRiNQNcMo2
7vhW91b1LLe3/1h6GXQv5sZJtB59fhBUHM+kIViIiFfrFUh2LtbL6Ax60TfVF4ZKPaeK1AhyMSCZ
fqUeDPhfFH4OYfpmMsBXIsRv7javeajBhcnZAlKOLR0RTftM6z0u1T0ov7JHRUmAHxQO1MgMFreo
29KEV2Ta1KHFtyV25c10creXVkjyv3SjsP/pG8qwZUfEFRspg9eaooBctjasOPrie526gePnfIYB
QsjNHeonuBaAPz9Sm4JbCt7qMaI39ghCJ9sB4QX/9wicmgqRvsdeQdTzN/HOut9Jh9334fEcc9kk
GKh9g1WgE0r1mzVLyKM1lAI+gotzdAXnO6NtPAA32sMc4KKnpwUacBIKeTEEfa6egh9zzJyTArS4
rmy5EoOgALVeqcFEZdffvCQitjvcoKetOyfcgJpJ99a3B02ddIC7nxTNUmCCVYNfRa9xH6dtdVs7
bk+xsvXRzTo+0ToD40Nyl4BhTlZ7X9T024eaEOKP++IvSsfSAEV0DY0wZvdYXxKD1XefrGKEEwWu
YjnZjyc525CqaB3GOhSRWMRq1xzE5QgvSB5QWsXE98zt7/3cqcT0DDmD0kTFVmxEXZ813zTcaabI
M+IOaFlOM6rkcK+DmDSFYas6TqeJHYkNbWZkqbL3MyeiCQYv6AW66Va7AgvJMk7TZliJlGIycmif
Vo1bOe++Pfl2Zpc9oB0X1lcchb9DjzR3q6YLVefDQcOCJDfaps2OP6wV1W6MavuMjBX86q76Rw0o
SF2x0rBYgwV058YXg60LCZWFJDK+aFnkS3qkeA1figQ8YQqRgYnZjq26iA0O7HXJTMDtTbyQtbIZ
S1KtT7566do67awin464BqScR0sq41HeC4CsHxJD4+rx9zXH9MYRm2MZKjbjGxa5jn9QkdwwexwN
cH6Yh1VfO/uk76+ZbraR29bed3BY+ONtKQBIh5pg3HS+P2Py3uDWda45pZUpILhlcltHsEgnSjZg
hKGEF31y5hmSpZcEaUgAK9NEmTC1czl8BVDsmYo1Tp70N6gmuoGFl0JNMidWJP0wZ40rX7ciNOWS
8WWUVNd0T3ZwxJXMQ2lvZacLIZTmSLOg2J6+MgRE0UlT+3A2n6Lnx3K15x5L+Ne4fVAfbHiJatGa
tZLOb9mVcRrAahMu0TZLuiKFIdYTK1YaK7rbYJWT5TLEqQrD/zK/alIAYGJGKwbKD4gs/pmRS1ak
bY0BrNpOr0dvaOTOLGfiM2Yjn+9c96eKMP9tOHSoXAwUREnVjDxoRI9PiiqRdt6/4mKVUKPIM0QV
j5jBbdkIZWMwC3VwDJWT2rva4AN/hvRX6LC1Pe64Ws7FUExeGgbjBWmS8rj1Tu556Ss2k4JS3Owh
0P7KodRFzCAe+sB7acmtwZ+zRHShMLOiTZsdjedUOEyJ/yJFiTuOVe3R2LWZrmNBA914Az172Rq2
zbtVh6vnK8JaZQM5hwckpyIzdlrYTc/AN9BB8uPVYJJcpkqeVwmifroRrfL6OfSKZNbsnLwAmRWv
KW3y+Nj1sy88pUtRjrWNt35FaG/YqHP1XCrUWzy8YAXosSW5yplZkXhbqMGfJX8+kldzbZmZMulC
YqiedvnKpjj0OQMk3tmY+l9I2SCjTcPJ1Py+WW1+PxTYeJr2fzabTMsjElJPdvHXBNQ/w4klQKpx
Qss/Qh684Jj18hEq1RGuzq4PQRbGgDCKaJq8p/Aeno0Z+cYxkMjtQgpP9sTkfJAElCbFIjXxNy3M
5CM1BDjqrOlSEfWCnF8b/JkoSuWdwL9HLfz4zm+eyM/Usme5DqTgUGkN7v8U4/c6yb3Apyb6dRfw
J6oC8A+7/koAtI+yIAVWgOuU5fqejU8C86FYtTpW1oRgltU63t7swkBZSNVOukMIj3Jior4tE++c
e6a3OzGlbgEorf0dI6YE6QUIugEzffWNzFTs5E81laS2zpcF9qaZMw8uduQvcqkM9ExUPmZmi+cE
VqL2WhEoSmojI70K+wEHnzLUu63ioGV8lutkY4kJzyzhfpTh6mF6MQfRRIMUx88ZHAzyAQ5swdhn
poxFjeXBkf9GxWFXHptKa/dLMCqFvyE3wareXSuS8YgldDrniG02zju//EHEjYbJdy3ekkZBFekp
kHLXg4pltYlV1G+bnBqw8QmFXu+P60BqZ6MVDjQCCDHcIqnDghdqTGkFG0AnC15lGe3EvicVl5f2
CJ2U9oGJ1gMtx5ThEWmA7If6oj2ElwKWjTISRsZinn26HWu0TEcqlX75EHUP7u03Vvhlf5f68Azr
/ETlk9iPOCp31Xr5GizLIC2wb8//q/7y9MXVv8xuQ98UJhvCFPEHg6zx1eksfRCiiFHOLk/AQBSu
1tt8ma88WT3JkwWK/uv0rwkIBmtkPNo8NEjNKBX95qcuLMIBZHEnFPbebouPkTJh538xJIepvY02
z3WSYZmaRLQVu61wmSOvEsd9u2Rm4AHbHkRCBCpYNkrZ69naM24WF4rKimcXfKPM+DxrPA24i192
0a6Ou2cxvMWsXtmPvK5a3MGVmhee/gipshU2Q2+xM/9VmXJEd1r8c+fBM0DOuYGxANrrM5dsrmtD
YEllMbmZMqqYU/j5TtOY+95HDxIhXxPrFszDq0ga9tV1jsk1FQ3kOPi3JJcJTWeSIIoFUpdbsAHq
CcMdkBMF19FUPVDbA5/N7UiJ1SVjdWR1dapv1IL4vzoRQ9A24Yrd2xL0W55U0HltlkwVq3jyQlLL
udMSd5x/IwS+uIqUvIlzEfY80+KlhMQtr7O145c0ekuU7pUyROF0zN27sIBhug16ObOx+IZkRJpV
8ILLHE2+5IKIN1HwDkeTBlx3zFUwjX7QNuKAAsDFg+zt3m7PsyLkwilxjNp2rOgLpKvMRYoC4+fU
Ofjbw5kKpem2l0YX11lIB2vZWyQrfDVDGCDmgbDIxQWVjcTnTTDdmxt8Gr8jDaBamRjeGCzKVGzN
ThAjqj7QkLc/w85Cttm+I4qSt23egv9ondbCb5TVTJ7J4hH/mLGlMIWT5aVrk0H0PCjY5PWZH+J0
PaPRK2WxFjEFRl+0WNBSAeA0eVrzcdfGKd7vD3e5Q+osKmPRDRPvaDoEYS3SHdyFuE6is4HA53lu
QdQlvPtkSc1kWF/uwvDxmOvJG0dJXP+HAVD5taxtAvaWfT5QmVmCiGTZzJ1iKI+iL4dpZY/9gkdr
iTdujHubF9pGKE14TzlMGXYbRF1yPlt8Z94airo/s3xB4bcPESpBw1y2joJFANGJX6Yipw97co3b
wjYirBmtGe0IhNI/OEWuWfqWKRYpE9ZUC6OhaJuEfUiXCEKFDCB6ZK0YhyabHvcjMf+6I/+iWKlK
E3HYSZvcv2R5tg5iCLYOazBo3Cx0RYH4oYvXf0ExZ5q//5YTBNui4aP7fzromO/VEy+wsRBEHMcM
QcfUNjT0D3pwd2FNpLrCRo8KVQUNfzFs7kTdbbWD+EW7nYTqk/nfXyMnKjB0Hea5l/qU8XVnE7eV
K3j8NksRNHKgh9habj7UjQFHGjce045QSaDIUVCIqB8Z/K1T3ffhZ8gddWY2xG852dLJXaQEsJRK
Tt0zaGjMb2HyrWUhux0hfWro4pn8AxaoQ03MUjP7/wpaI0N/duBTGn00XFeBn0D5+aX9QkzyxLpO
jR801dUlNhC9wQSHIRscvwRZyozkr1R4D68G1pV2IGynXeyVQ0d3kNDlNsiubuGYeNIW4rERimq8
SD/0jOEzUGOm5A7DLaJcZalFM0UITYQWXhJNemm0ou7zitMiRckLbdnoXn5A+LN9RsMm79Y2g4dq
wJjpT7moeXt2a84tH0eZMpq0hEm7zOAIRhU9TaU/nXx1E7qEnrPzNot0sPEA+wdNrZjtg1kgZGh/
ukQ7O9HfvtLFaqfEO3RXXYVVttbYKf5mS+TZCtgs05AUfofvpz9H56VkXQ0jHS+dWjm/vgCqKOk5
wRgp7FdvDBDRU0Co6FhvrR8qcvHzQI+flvHsyzCEZcLB2M3mQGD4h5rB1pkW2OXYptlgUFkA90x1
NEF7fQ9HWDgK0YdpdFUD02n1xa5EjB0/yZUZSd+I/Gmi6SWglsYoxQbG3DiEyrcTTPykqwf6kCmF
QE8IPXiCyxnkSx0VbL8LrmBfAyCFTnUuyfZRLj29PxiTuMF7/2Yk9hCy+fdJGdAPyyEtdlBGxxD2
mPMud6pUi/DLvXzzsX/ZiaZKIGVQTqOTZ51jgxWnMa57P17mQDuj8iiEH2HafsRvPYeDOeX53jpC
+k1AKvb7HewCZVVNLzle3RIMgOs736eqWPQhKK5CVwru6Vm+Mh7jMNL8LvapuOchXmnXlD2gUdaC
T6xG7p8rLE3RIptnviGTOQn3cST2ewT4b6rpXPymvdHVjRqBe4BREqFJXo2vob8rdUelCEFY6V4Q
mV1LbmgyM5UhVTSe2rIpjp9BXzl+b0wIIzWvz4Cf6VdbmhdHWtl9vBmQdN/nGBZVOOOk42qMIWjo
2lKXYn1i7i8T5RF1Q3Pp7lv/FbtBgCD2GqSQ//SVzJMQvba8BxM3TCg5y77DrAqjQEkhArXH+62P
/cA1Bbj1nkyLMK4lYB8OIjlStJ5ofo4MkqrED61pfGvZq4cE4qrMpvOtniQXadEy9NtJK6UUoT2O
IdMKMX+ZfMNVigJiK/AZzuCZXNu4WrHLDQT0Hhda5byHCw+cfJMQRWOo7McMuB1D+XR+ixmeYhQ6
xmJdJEj6cZmhS2tOAsx2Wv+lycsQPzMIUzqIxs1xicAPKMh4UZFaFTKsaN/Fnh+/Ooki3lYkv4B5
wOIzPsclVH5Tq5MFkdagaob0zCCltkWNM543A5R+j1iITDf6uHIRhfy0XEk7EQnMTB88YheImvaF
yXFqSRkAA1TGo1Je/QUr6wT9zvWYihWkaulZ50zMKml8B1iDfeWt9XwjRIjmxyPBhikxg9gqt4Lj
QD7HoS/5wZZZrstgUXsAa6NvRFNa5AFxXdixuHySjKvr+R3c07CuLtnDJbu1G5VcX3eR8pF4PxUW
O1fYOSPhZbFI1flHSrSt5tXo97juc8bIAd9zDXOuUeDq+OZChqn9PqGYOHs3h0w6CMt3pz5FkgF1
25Z1gR4vRw+0t8ONi+vhNvW6BLv14MytFWNn5W1bVPjxCdMrprjKKJdUcmYa46AT52LujL4uCgp4
ruEDmmD994Rz6jpAHyjlJUpGMbAe6+qnccx5om3D0RjwWVzcu8VauyXVEu6WaizYYDC6SHqci6Dg
hsU7+Nrgij4Px8PFbfCFJwq1w6Y6sp39VFSxvzPWWa8CorGJ0S5elFPYKnr8nT4MG90wSYqTWyCN
I7N1rnIdAYDXxknWuGjqi+HdPBSfH7Ftr8Ji7+sKyjJb6PIcvpEWthAN8kax+dM7sqMKSx+6C4QH
1jgLbPmkBPgJcPxMleSCgjCUePCLZHrt6oxmCBAWSE4jNfosFP2Lc9Sb6LMZRbFDLccYyweoVb/c
Eww8Efnc+QSkdedJ+662KjKLr3eMoSdC0HTB+MKVr7RIuan5FsCchyCYJB+ILC+YoIwUlsKk1rGl
aO0ipLXK/ZjXRqCgBFAQ7d0SFCIKWA8AXKlnHSkIu864njZzYzKcJ7hzEECK2zrQABBdfL77na8G
cjh73Ui/T1e05RJeAP3noIl8Ca34mkeaAnDaFHnSiM3DIzAFsnSYvh5yukpSIQKlX4mKFspyZntL
89Qe8fdWO0yer2X6xPFVto2DLCks6nkfq4UpMO+DbMignb4utqQBe/nVOGIONiSpnWpLRDUtva1H
Oq99In2wIjAng2ODv20THO7ckU0YTE5DndwVoJ90VSAgx7+sKg5+INhZdsMnuiAQN+VTfMV2tFMD
3BBcVnTZWHyGJcAKBAnYBQWTy3AZkfNERjBdtt47kUys7GEmKY+4dtrQoY3twISATQBP2xE2h0y+
oePC5+La7usyEFqwb9DUpsboJyZuF1u/smlfsNx7Wpd7ZNZNiCi7AaMWZiACqb170VQM9DC27A36
BEOqNRyu36tuf8RJec/KR7jOHGaTSpTrxrx+7xKWDSfjD3XE97LPV+rjNwMitL+Akn7gvfbDYsFg
dLelzYaHksj85DfU3hUnJydodF0DXk5Q00Xd8w36IfZwdv3qGqxoQjhfiLoAVYvyXmEKLtAU5D4u
y1BD6KnHfuHQBrONJOJ2jfbycEV99YUnEa0+0auDd9Aiq+14WRqK3wguDmhcQx24L1zseS/y3HZW
R9A9J8LXfDVQH04eD4k08TS1k/XAn4l+i2tuUPp4NXoIcPRZPHg46JjiJwXp6R7G+PJVsqx8IVIr
nXNWNFsuEDVJ7pFZYJ4HkNy4KNdBGXeQdCSDt2T+b8Dw8uJfe6B+kCMJ0a5vlz6sEpxcNv2jmSAt
UVj/qBiW9o6ez42lkt4JYHjG1p5qv2CahqS5TWIH1CI6rJejiLuJ5K0k5ywXri2RE6JtjdvFzbyE
Q24a1yQzzD2pYVMwCFbfQwPP6ZinabQbbsWw1i27vC9RhH1gir6UrH80oKKlFEwkOLgeyq+tQ6nZ
lZ4fNN46Lj+WOWwi9BtwRjijXlKxAR0Qsxwu9uvDCU5UiyG15TEbSCdj4AUp5Y/D8XeEe75mqK6P
XnhKGjGFsTSHJtPEq1IKJrOIjq3lj0C9XIKd3IlJt2V3eDgozdPPZ+FUzEwSr4P+VU9G3pH8RWjW
mpfokwuAoe+Iqrne7+zAItdPPahcIXtCehgEJxE/j4EJVMU/lwUKsHinRwi/4hcv+BBtQLJgeFus
NP6xCJSej+Lw31wDOmIhzq/7HUl3V7uL50hOYQnbPf1YJpYQgEI4PdLlkfabyZ/JpgFHckWsm9LL
QLUamSArdJUHZmG+s99MUSsY0JOfMfsLSV95BCFkdPfJ6M9JTt0bdqabqxygdPiAN2BoRj6+W2be
zdIgXFkkCdzG+uiCdDKeiI0942hZHKSwiHHd/25HcBr/z0cG7aOpqxDjxJm2SfMhX3NQzTJyg5ZI
munZZtPa7NX3y59PnzcUOYG+GdauyU31cy4vyfDQErcDjotIrh16A5c0sxXyVItKCdaoBUGt+Xmb
A761TJNmcugK2UoThoAeJD8nxWt0KQuhj+DWKIHxDtejprH0/ycvCoMN4OxKJWYukyNtfgSU1m1F
mzY8W+Rjw8oeMeMJywnPeXxKSIcVGXGuy+35rtRA/giNTxmjY8MudmY03ze/jRiPNedP7U3LsPmw
OB9zl6eYghSrqvr+6FEzhCOYbd+hd76lXLRveUkFGgzGJ1SB5I+swg5mjkH481SoxmhHQT/gTW41
am/2tHedqs60aFMPPBltYlaHNRUKkVHTmc5TjOKM9b+9H3KzRTcT9y9xFA9pCC8TwpOb8zy2UEBa
yCaUiMO3j1KS3m3FM3DAdbaLUAviQjD9z3dZqWRVxAZkE5O32VYdZi5J6DWAmNvsLvNVXSFeOq96
w/Wqtiv1U3KEyPGdRS08wugehra59uLbeUTrUVexlqU3hTKQ5Uyr8/FOZklBOob7D9h0dTTvWQba
0UXnmw+YDNoFoV3c9lka653O50koH3YeZvk3wvQwUGRL2UUmrdIWWy63QlzaBV1Ra5gHvCFVufOH
+Vu8jlpIIPstqhv9VYhMYYqAyu2RWfmRnubDs/PezSMRSrT7imo/vBnrWDtPYGkSltHa8AxzUmk4
h/PMsV36+NJlqrCrFOcqq/Isg1JUFBvha/EHfThLBzg70r8GSagXF+yv2VA47tBGF9KGCAgPP7+M
hNwbabikp54gXsO5NVyjY5ARkvEuuJ8zOKK16k0LITW0T7chyUeEturDrV8Zr12kikNPIEsGBNy7
g+7iuV5j4WCedv58ZzqsH3UpG1CxlLvGFQcNUBgW5a1uoPeN7ji4oZHU25z8U8aiUaje1u9hhFZL
umItcBMBiL7uayRG6zSAGXpYAPEN62k58FKd3UhGor+kM8oZ3t/dvTSpl5TMxZ7yfjzrRUOsa1Y1
NuLPnU0GqDfXhixjXnEAwdH+F4MU2gGJuVox26a52U5kjJ4l5atm9tLvJLsvdgKxEzBDvCO42LZP
EpR2r3uT9yi7B/4CSb/72/pJjojJU3TiQRwVebjNvDj2+fN2e+/RkhTPPggo3wHz1TBIP/WqD9aq
NzML3iIFWY0fIBoC7AQohSu2OzTNMX7iUxWBJ8f/3n+B0TnGISI5w5pzBAONzIw+nRKCdou1Hjky
1OjJoa2Fry2gI2f8BHnTp3XnEtKTOvNP2wpXhY/im4+B7+suGusHTJx5+STaqBD7sfQ0DvOMxXVm
ytPb1uD7mBeW3MJo+AB4TWEBcxgOu0nHxvRKOLEHEY9EOjXb5f3Lotr/+57RYa/e004Lk5HVyqOz
xftnKhUvj3VmLQ2AvBJ/k0hWqWUJMaXq5+d0UX42MkMhB84y3e3MmMqzaPOOOJwixqOo26fxwddy
mtYoXX2gzTwuZGc4pFe/R+mYwVzpWe2kv4A64Elv0/NtD/RE2Cw3XotwkKInizyvrH10zALZ0hzO
dx+AbRmYelYUcg/RhKMZcgSFubmPIy/Xj467gZfB6e6KvrdClphXCjQFM9i7Vzf/xouc4RAHMiCj
QVixRurMF5cLcFzVqflA5tYP1OjrBU7fJ88tnBjITB6KkivfkCLb4lIBbY/QAiTg92lpVo8he/Tt
7uNs6zAA66GFLigHMMmZNrNhLSqnL7Dk+pbThyTR6FolNIQV8DNLc5Th5j0XNYVSTfDjwOil+dXj
yk4nZJjuDF5I+qA/ZP1cbFVEgfUGXPcVHXJisHsEuSUwVWCe6GDNxSJFVYk8wpNY/2+biP/d7Kaz
UcsQpfoaOURJw7vv29+j+N0VS92hsWnsa6ug3VPAZyurX8b7rkLCce0ANbMrBFdKLBGD9oJPOX0Q
rigqufGR3HFt3a5RbxuJSWlwb1viaerG+CkA6kccCOtRKgervJ52rDfGubqydR0MV7biBS09AYm9
feF64v8u2K91yP5ColH1JVSsE1GKHVhoLlC0x/Rak5JYcsODIDLWFmJbo0vTyAldoJHkT4HPSLMH
kPYop0NbMBncVGCAGZKDoK5ODMHwOaRe1WdCYft81WAcvEtfMQZzQMOFaAWSDsNIibFdnTpv7Rwc
HbB3KR0Xm3aFnN9broUEpOGkD7Y5DeXKpOl+1cTHs9/kGT96NKFHeYpLsbUScThXQvqvIT4dJZse
R8L8JWxz6wJaX1LxCM3gyp+0zwkAmdxCWqkpktElVFLYGdhv9v37Tks9ZgFfF8FApSqNkxarXJRs
/x1AbtvgznODbrzFoCVmPxQIUEZUpuiT31tIByzst2VmDBS82Xhvimr0G1P4rKPiCfz2rz1Qs+nU
8TNiNzCkIrdlShj2JBvxFhVZu+uftWW3qE5DpBAwyILPCG5TNDnK5ZMWz8GmRkREVSKX11HolGKl
23IPoZ7fmSlBzk/6EVkQMJBLLBdGc/ymZdJ+1i61IzqsGBMRC6iOJwUFlM4cLwfH6O397xGybOMd
I3d0raofmLUz3V8p7+pxaHeA5ClWTw2I6WAyRT3SrTx/zBWEMcJYEHNUPfkbCsMpkWZhzVdhUiWq
HN6DsElh04M3r8uv5X89+AvJ17hjVcKvk4vO4syViGxIaXJcvcpylUdV0xU9wSzfkccia0tUQAST
5qsQuswjc7pKloBva70EhrUfSoOVNkMIGEm6FWdt0ja3WWhvA2ucmx8/iMO8atKbMMj+C5V+eIDl
V4LIra4W6JKHyz9zyw7Sed11Ovk0CSsHHsnw0h5Cy+KcT2Yv/t3edlp5js3ysWv99ZxZE5ssLpbq
vN4HSHS8aG8axjNz5UZ+Gb38Zp4/Tl78J0xQFATmZoWZEy7Bd/KU28CfOJft5w7Z8hYb/9JPURPY
uNmtCOB8ATUSPDuxMpcbjOAQGXNem9qqLBloHQ057OFLuc2eZG8hm4PnmJmtbOX1D73idjLbJjqR
xx1nOf/1MJRFGFeSsYoxXUsuvRhF++zNse+VsaYDBtlGoSrtdEjU1KE9AqF0GKpKkmaIJDppwL48
lohFakdOUV2yXd3jIZMUzXRVQ9wQebpgEWu6ZS5CIEhKAxO6PciqDFLJOJeXY5j2I/iZZGfnTP8/
Ytz03fQ/AZJrSkWw0lNLuSsQ/xpAptQ855zmcQnk1+fwbmPwLNNZl0XUYK/eMmpLTJC3HYPWp0Zr
c8SP/tMY78jZWMnVsOblO1sY3AbPX+bJevh1ZQckEqWJMo1wNCIFYXUTHxFT2w+bqcIxi/ecU2qX
pFkf2eM9k9OLQ/3vRroiIGl2n5IxiAwu/wCTzrprb9GFhNdyJLb0n4B2QmuAqt4GLSRBRl1xtAOu
zx2MgZrsK34vDDbJK3wLqzl0aUVZE+n70qYTmg18G8DVOECThionIF6L78Y/6iv/Jc4/ghrNAkwz
Hz63D2pJ+ZFhgoL/Xim5vY6j9JEKFI3ViNbh23jGaIMdVWECnXULjUlmK7Ohyu0oIQbrpjP9W8e+
EWGIEbGwqOjEW8y+hGUwkRAodE6E9xrHhO9pKfF1EMOE8udteXv7PLqixa5PJ9ONyBQEHTyAEhQZ
cARmfsa+Lp5IdVoquF2nMpYHvKydXVj+/iq5nGJqvTI94xU3RL9+KXIRRRvqlxkyrI3CZgue/nzR
mSGtxLsCpYnX1Li8L01mxv2XTQkv9vp8Ziv0xoAQHUZbGmblks7ARqbsqkBHOvaZcnoEFKuyBsIo
GlzTZVI4KXv32SqCXKi2ER/Xob5rfaMIRigr0iMNmmovy2gK1T2brw5RvYfnM3Q13D5qronAbwoH
dOQeEl0C05BJZmxIjNsEhMg23bwN8Q2rseloLJv16ToNfUAWn4I4HDsqg8JgDmC1wvbdIii4hgg8
jhWffvuNi6ttg1sHwXFk/WItQUkbwB9HUvpklrNhjTZt2MfaabrRNOIBP6aOlA8Vy9kmHc9BwAkt
OrXyxQ604yy3RfHVMdXTBh4mr5ZPe9+iAbopLnliCpMecY1JaSKQRFxDXhKqwIVJZRu/PtERdpPQ
BKnpyz5glzyCiPMfWGky0iP/EwFJ0HhtbICxuXx0h/YmoOZWrTCn94vyZ9h/WQCLjk3VB3pnZIlT
hjeQYUAO4MqCQoonbcTQpMX14cX8/bdqAdLcoP/u1RDI4JXcF0lodmZJYFcdKdNSXzPRJW+6WzFb
jd8iN9xFqoG3uZ03bh+XBY5UEFPvqxn6ykugv++f3qugqgFb5QXDJreZ9Zj71O5qOz7cyTOnSvto
umoYgyhS4Irb9wqlEMOAxGyT7i6BG9feNi9bJ2OaYX8NSgvFOj8E4XKUW9N40jV23GbGt6tryEWd
gZqM85GjP1IPyrElbIdNp89hMfI8jgBzI+n5DpYeds0UVsuZWvDrWNS+F4ZgEsRRk4S0C+mBAaNx
2OJ93EnhfC17GR/hfXwhV+q8nQvrdL+kAlU3qQrEO9Gf7NTK4/mvJZkzTu6ccc1ir3/z8zsAw9yn
7iJe4sa580/BKZuPsMrV/EAJKDjmnRvoebrINniN3JWD41UYeexjeS+yJXwJiqtDMbYfhCK7Pfef
8qNWLb2E+b05UTkh5XYNn37aQKrJ5rDi0oAJWwk+jFtn9dJIXZiFi/Vyn6tgJ2QMmz0WoHYoKmhd
/y6xlfuf+MGsr4yEIXgzOfeG/a04cEgr/CDTTK1cy8CmH8Wfx+DuZsfsvjt4VNgZkNJUgsfvlDpq
h6/jRRIChQq20Eyt6hbAzDcf15tDCVf55T5V/rwKDH7GEDonaocN0rVaKZRsIc316MCKkZbGFaZR
Nr289Y/MYzpt+KhDWTMQe36VehhHEd7xWFOYxnIgwmp04g7kF321PQuPxrHCVUk/a7vwoyz1kLvO
LPLNm2lolMlqdwAqGQd0lIh6Xwt1M+9f1q/8k+mqYdrGu/XDj4d2jiiVXekjCPTpzHlqMrUNfp+n
Z4gHc+Scl+BZDsowyWFVhIQl3kSUITcHX13cHccmv4OtnmDIDH27BaRljPPRB0MA4Pmo+GFI3H8+
N+lxoqOWiFPWwTwhu2T20xqk2t6rulMwLkNXxAobdaZxtCJQN2LLDyTTkrRfsyFQO3Osk8ak5BSQ
q0tTN974zrwRWFyuR6EJmsBFCf/OJ0w1tCavwefssIpwSmxVsTCuJJ0BFgUx7v+SKoChomeIlONr
ag7VXLLPD+Us7DV5sTkaJouxmyhaGEnuxUuyOaaGiuLHQuSyXKyGLGqv7k0eEfF2O0LryD3wNH8J
YFLkwN2BthoqL2MYvydwkG69AQu76cS46nIoX+cfn7mkUvrOt9kgXQoIejwFKwV9vIDNBgRjU+i9
60JPjkJycNQ/wi6glTaGTNddw3x4Bv2qSMkfzkeDzkWdWJEfvmbhtFcsTDtNrKk5t5gpyUgLj0Kd
TVG2LHflBsSSnv3rQnzjjoifnkzV2GtkglREYLUpieaDh0E/NBUpO3zMz9I3AS6Hc8Baqsm7GYQW
QkDnO2vR6Q/Rc/vR85CMVLC+UEgsjUcuWz/Px7lqcudKYCI3EaxvaMARXedls5bUco+whJru9Onl
Uq6lN74RloPtkU968H7/xMslnrznIuAEiaaPa6C2POuXZkNBC1jTV+fb2QGHl3tzJTqXg0OqiV/B
rer5JjCVgb4bclvn3BoHubECdQ5zY1QzJM+hJsCNL+p8AKMfs/PCt7YV67vmb4tlehXDch5/TvMu
51vtOnDX22KByiojKifBDBlfcZPUfXmYZzPWw5hdq7FHUToO4y4bSP+3o0MtNIH98Fhg0BlL5EFn
r22W6J06yxqvQjy6OFJqOnWqLoHJ9DKevdTQA43skkkr/V/xt4XdJ2Ijlo+RKIaIGJIxajVr1m6J
pYAh83YWneDI/ox4ECuYwcsrKbaVvNIrYD9xn1fmlkkLfUVHPddOblYqb3hdTVqcHzTuv96BkQvp
8Uir8ai6+qJ+Qy+Hb+hyJ3MGnaC/1Zd87ExMfB0FlsxN2US6uWf5RANhXmei1w3v69UI9DrtD65W
6g478lOXslWBBPKdDXsyde4DleMI1e+G/2gdxdszRzFr0llSAvubICrgOvKGqoIN5thAxGktRFF1
sNppO425C/+wv+dJVmvQMIzi8qcXZ28fMxo4SN+t7fC00hM/tzWyDhFajFgzjFdu+Snnghu7vBHl
wIoae7QkXUAzrF1VxfxA0Q7ycvbQHSuFLI7LSOVzw+k6jCgIcgoNPt73GEAfXa3sQy3uHHlBpd6A
w61I2PNauAWvhXZCRhOZuhg1mumgXeNvsomlf0S+bKjTIYhFEcIZF0OPLTLM8zbf2DdYKBCSavP/
Dts1iJubXKVPrEtb0vOdCR/x8quBKH2atv+kdoNjvMlGsWykgNmqvggRvVu69goIyduuL3HuMPvK
ClzYbPl5GGmTlzo3ahV+pU6keSxrUgsEfqGenVSn1UbXFouwRPvFPxVg/NHyhzZ2N/5TrgGd/DS3
sjnUpTIvBaR0Dcu4FmQhLifaWVtCBd08SAh+2nglftIuwUhcc4leqJfGhPY1cdEHEqJwsx49HuQe
t5J2tQHY+cGoav4APmqm3DOg3qGMzvlVdY1NuTV/AVwtVUA2snBcfl6O6Lv/RJX903cAK1fg7+9z
9YgzLTM9sxDOKSDnHKe+RyjUewoGaIsCCjmNjL8xQyIjyzIZdfHwdKzIms4G4q/c3e54coPmDDs+
TpmFT5CPMR5zhSZbaEzDVo1anbK4JvPxY2lLE8ZCbtxB+vULXUS7iDqpDTiiFhbOA5Hpqyjy4gXO
jUntmB8LtZr/Iu2v/noU/VvOib+C6ylSEBrsNGwDNMHELSDzJaGNR7wMwYNE9uJX0tFR4Ujf6EGi
Hkenu1NYgctdg1lfsK3hecYBCHB+CZhtmMbZ1KfbfI4ToPAGDfq8qcr34U+1/wv6RST4k/51KlX0
pMavG1enQgaF0p2Vb0clUVPWr95GyudTsyhsGYt9++O+xmCbPx70GvcjZ7UOQ0SDOM3RfHLbmyjm
45hMfIvFqIl4hERzoYIGpCb60GM0jnjoY/KJovDKHCwmI7e1EEVdRezxrT5Vb6TfDCInSPwdpAI0
DCbrZMT0idb2P+lnLHd2N2clJGsacykf1Ol7rQ5A1v8wYIcItmLsXI79bE2Lx6t813gVgoo0ZHaG
1aaiWpOW3WDEGEO50uOkjM1p1vIIms/vxC7B/MvIOCM/uB58A4kNlsrsRgpGFJaRk3YyTXLT+gXe
mbweNPHmUhGdklYSr7hCJPszoIvfNEITgzV7vPRqPu3IHVd+BXNmCBjsPiqgKuJG4xMcP6Xs6lNw
C7rrBR8s47YEMRg+ZUCyKHnd3ByrcffsIjwa/Y4ljYEE3oqKWLRlU5yTUojviwML6GCit3WXBXuL
bkSM3e0wnJ4xRwigtYSuCbjRSt6/8RCQQNGWrLbp0Kzz8URQNKx50qyrXunnEaOnqkDNIb26Y5EL
hfsZhz0e36AJAGGXTFbyfqRqMmy/qXlc/OrS5tRwAiaqQaDF4Dd+tRrMIaCy+KdClSbonkAYmEd8
KHC4ujzq+t12ngpC1jC+CQimh3UVkli087YOBGGy3L15gl9MXCAIhmF1I8Fnxyry98uYKbckSjQx
qaFDmuGwA0hX+hRNODs8zyIx56MZYx7DXNNa5vTx7AcpllS51wIyRrWYDAa2D2FkPxdPAtVVRSSh
UQv6WmfPa3cZJo3bdmQg3xQAuuy1ytwG9GVZpSfevhJ0JrgDQOeaqKv2oCYapsN35bjnAryyfTvK
SbnQdElsQf2NBoD6yhs+gmUJN5pp687LeV9EJq772uf+IcoxyMtVtnwAVtcH+nliXEFQa+pv/a6Q
+qWrEuyEZZwy1l67YiH3XbsShvvrSp6d8YfjEJ60kzHljaaZ5BLPD69BBcHTf4VDz1ez9qTUOqtf
u0CURGREHYONSS63nN8ayCydOoaG7xd7HXcdAC9E4gS8CwUlkRYbX24UILLw8/0v5FS1v1T2REwR
kv39CactHoAL6cq2XM07S9ksk4xz0Uov8aB+UAuDhqJx0AvkGdenHn5HxRWRg3ew6ibthqkCQNN/
X+TeqJ5C8O988HxiKw4Mp7ggX+edYFGuWEIbJMsQoJC8IyqkKpmw5COH5eCezEI6GQ1IfbbzQ7Za
l37KDgb/IddWpBpXGl6Q5i5ZgUuaXLORUB7ASE78IfgoOi60U4/9mDhm5rYSNl8K3w6JRPMr4x2y
CqnitahCxlyvVosy/isdbsxjyqEa4bL9d9rp4pV0pjKxYY0v4fWj9Hi2nL/eaQWWJwo9NzbLOmtc
2bhFmHAnFNyn0u7RhP/oFDJ00U+6xr5sbRWVu4hI3tcoLpcttfG+YIaMlWuENaMVPzsjhKh12QqQ
6Far1R9mrqNhQjcFGoG2Y+zgv15TBmWrvYe99lsktoAVzNfjWw+1MT2LZXbQiHUtsIUn4jYWjfIT
8T350HoY1TIyxJ61hnJHMElRYrYw7oRVR0alTqTikFZUdPvmTK7y4jvuC/xRLEqGm3GdjfsgC6Jo
0m9RdI7JTnNCYMX/5/C7mA4AsIxpWb+AuqnAFG9TdTIWnzDW1PyLO6XYcGvX9keGvhue8htYpolq
WL7110BC79hv4Z0xr0NAzJVu/EcgtWjjYaAJo6JXRSXASdcxJep+wFLZa9pQrLkpe7zw5P3vbudl
veJ1F17vLtEHhRkVpyWmq1rhKFxQMeutsfnuwfMs8aOERCMG63idd5qEHY2n3Au5ubZRDvWuMsAU
5K/EIg3ZNUtYzB8zMAww54O6dg7n/Yyl2iCtC6VH3JuZRr2013xinPP2G952sOX8+ejYQzsq0yH9
VlrvbYEfr4dCiLzkmcY4R2cvcVsJy1k+6XfAX3XocWsXFkvvN6YgLQkLRbhftJyba6lw351/r1D/
yy2QRIafHJehW3jpPb5SHf2enRZsU3q1TZ/9NsDGaBBY9uHFyHDDkuM+Qmc51xj+zzLVuxcm2mkC
QZYm7KI3G7I9uhUSr9K2NNbMByFnwVywujTDvRhMWcXYX9ZEef9u+JJD2RIs5QZNn4y/3tPGV+ib
8NPwxGDW6Hfl1y1Os3aGSdKS7UrtsCD2Qqw0wXeSYylDZ2/tj9d7S0iBUOwo7YQure5mUd/2Du+a
soGQTShktZVdeHn8GkjgFZAoJE5bqhduR1XZRF7xZ8KRGpVOHEg4ydez9PmZvf/rEuY5N4PeS3no
rqIm9baYrmA8oxzQpuVSuWt2MTDgLURtlp0zrw4V2QbR1Lb0Gq1TbXT9uNxmVNxh1y3dROGx9aa+
FUIbv9cSL4JbJHDZbHQ9hZh8KGnYRbsECup1z+zoZG0pnm59soeW9OGpsj6vYRSxm1+JYAduqmqt
AGOlBOqOlcYT8oTmHVwS8JI9S9XTcSOlNXVyf5ydrBqrZxGAG4Ju1fdPRmUFOlG/oo5xfn3pg2Ih
Obn+YOtWIOGeuZHQ6iC7q6uYsOyUH83ZlW1A8eRNU9UEtNrzJewr7BArJImfS6SIis1APpNZM4F5
dnZvE1U+08mZKiBvwJMR9nXrM/ATYEinXnmSTbhVKA2yk5M7PJphL4fJI04bCebDfkGuTSGPsM+b
WblvvyU6uhMPs4etc6dwKdEa3vqE3ZcgRcoagcBe7X5fs+mXsKNql0wcZ4e9dsN3zWlKTmbwxNQF
z40PmstXnJky/7wb1CNG3DOGmN3WaI3pg/MDWtxb/cqTeag8gexPxsw19LBr+HBprr8A3nNZ2Prg
szCuS4AnwgkXGUUepEiciuWKLhtWq43UIGkRLmCWrmnndSbHGoMYOl9mUVqDcHa3mtqm6rPzc9pm
NDZvD54VZWWbQoKcIRb/T2wJ/uKF+VN6H+7SPRdCiHCAhBO0cw9hhDLwAC9ivmL4i3WrmxH/MUNu
e8o1r7spS/W2P7bHSvPOo6mO3mkVZN97hZb9Jq8lUV1peZEPBucjqAxacbAXOqfDwrqZlvx+Le3k
P953hJptxgwyfhiSjzd03kQbAOu2TcfgRuyUtd9LJVacgr4GiWbW2ENnBwjEdyy7UXa0t+OlcwOg
kXRA5o5W/rEFw3Ao2+O7WZ5bPA1jVKph6HpUyvii92m0HRRUElT8fBOL8RLwzYxRC4bZelxMri6B
AoBIPvnd95+6mIEM8eSEu4VygNWkqBkg4F7bi7KStDIdioeE5x8k6b3bvnu9OXvNF7jO85E+qvcC
eDwXfZRx0JNl0oG2LdA6ocE78XR6Xa4+/oTMMKlQxX20gdL4ayi5h/fs3aAI6ZAWQPtr9s6jfjIq
1Lr5Upn6yvX+jqke1bvTGYNXJI+8tqGz8wtyMF/9s6/MEglCmHUWP8RJ1jP5b6ugQiNB0/UfJUgt
66GWfgEbvrS4RPSV9vFqwPEJIaqKnGSMtyDNdi8OjRf5HhgHCYWuZ5gr0nJPKCcZ5EVD/u/Tu8nz
nBjhCgOCj1kw/LHmJcga0phaxDIYi1bVeBr4/oMVGhryEj3owVJf26vqJ/mJ9tru6pFGvuWQM14h
0iMjRCX9luv4CpT3MLZSepanzZGcZBtMPLOfGpBsOba216zhx6EhQK9EyUgDSPQlrJErksmEem9f
MRRlJ93AI/AC+py5ynPpl8VFct4HI24sljIldGcqGkby2HPq2W/crBuT/5rSCXAqZdNu3VhNryxK
+noAuIJJSWuV0mMBJd3Qx1Nj4p6GZzydGBy1Gduy5Lahw/tuGfsCdWGuuBDjOBrjFxSZDbwojLKh
Q8DRo42IYDSYyY5/+QIkAV9qSVVn8d0dQXnHnsn38z0JsevsHFvW0GV+3dETgVv/3dznJvliJr2h
YT5VGaH5oIROXhE9fFRoWXABpue718PT2qTy4pVYrHQlenTGovDBWlMvo26yVKMI45o4ic9tWVKU
P0ycJ3UN1ELz9XDJGb5260Eug0XHeiaMVnpLIh08pjnUKTXQiGF/wQGC40UHzhKYHExseu3r4dgl
d8EH+7OWoEpzhfvwt1BDJSBj9B0lkzn1vuDNVb5fX+j8DD/pJTAEPrioE4OXn9BaubW5KourtEbj
wcwybBGRKgSKtJWOHxPnv/VXa6t6qPgcnNhWZRvbDNJD25aLCGHPWI3GmpXVxXiZub5JIXYL4oF/
bT8YF89qHw9187LJ1NRil5LrdKm8tKScQv6vQwGD/q9w8I0hbsZ10xyhoHnK2Fwu9yQpDfThQOt6
A4ZjH2kvy0dP5TWDDXPsirsuwhsPrLeRmcNxhG2/l/lZSEXHJ7A3fbw7lBYSMdMM3cwY0rXTk0mR
kbmoNRevbNEf6lVCUSpddT/Kjylds3MbEBeCJRY94fSWXHx3miR7ftEBs6x/ba1q3hFsXofc4PWX
ZvpDmBpSouuPOpHl0vkKevojWveOQ/xboyP04mxCX6Iqav318+llpbHtZvoEZYfRRfdsIgVvojcr
fu5ISWwyswGwGv5wHibI7q73lc9sJlRiYX598N2TKj0pLfVdicw3AwZiZAdnF+fsjKfeOFWHamB5
y17GrSqS1P3nbDlHA5qNSfADfjESyJq7eYyExCIywLQWrvp01GIgPwyJF9lMzSqS2yhajpZV1js6
Svod7PN3tP6y319kJ0J1VYOJcn+ksjgiLlectiEWFQvb1WSL22FOsvucxdRatWMR49fEH1YioLjx
oquOWoePbxvuexNlgK9JLEo4eOVonTjnOPRbC9+pDqO3xcBtIZaUP3HThnZyh5uOUfr2I2C5NcCQ
da1hqj+cHIgTeg4pnrtieX6QTm5mfuDQUNo9+rho/9ZkdDPwnEYK9fipP4cfVrowdpGbeqji1dnF
fydr3d9hUJVjt1vINl01jupSFiqIf4BGOL/GSKhKVUbXOGLKFs6Od1bXHO+tjddC5tSsui9tSrUL
zi8RbeDbRKtJJHlWCda/HyYXt+F0YiVujRUI7r1qpCgy8Wlw+Gt4hgujs2lv0eNXbxjS7DPiWx7q
Yu2J+ya6I3fX8/0jBPO0jcy7mRxl/hLQ5njVGhzDNFJ/c2tkJ75iw/iwa9/PVsNAgwfuk/fbIypt
1Mucm6Byfo8W6Od3ZOLYiw16CldGMLU/oZdvsuNYDE2cngH7SVPwB1L4qsa6QHPpGCvqBjlB9+ev
2kNtevSOFsovMkKy7dBa+QGLuUAsOTXMD+34IC0DBhElszG9vQvJru62NwTf9ZlTPfdN6T9bL7t/
BdrSNjbTz2yty63iDTo4sH0YMXpVuxf/BNupUW4Gn2mTNJ3EV77fvNWFArTywE+Un9KCtUQtNqDr
TqT8lFAA67/blNIoU2gGRKxDyQU4U7VHOpPpt3YrCGRCSBfh4hC3a/f3o5akrAKZgErYBeDjUwtm
Tl5F/BPBCIS6h+mhVFTWdpDAyRdMxfOrv3XFPptuJAbMezqiSOF3eLAgymrwrjyUhxm5IVeftFHy
eLUxoo2xKMjUyXWd9KJb2I0DD8LetrKp4GgBqqYYaceF9RR9GbiyxaSUK2Xv+hWJNGczQsOvllZn
VgfO7rTMIgHPkRPtML86r7YjUl0eHyl//xMcpssAz94AVkdHgcbrxHcm468Wt5vMBVZVCgCm/pqL
M5FnEmMF/fIZehlOlFp+LMLm1Qvvt1n9GVKuMFuAgR0S8YPiiA1jkjclHkI+VkfYtyLF22UrTpGU
BLMt0XXw81mztX+yYTeOgA7BEfH0upFUSYHgbVjABROsdiLnbAPeLYZ0BiXU7UfuRhinXmdctOLA
3mDcVNLq25SHxkrjvhxihQHgVyV0+JvFS1lDTnE6xEuBkDrSvIh+yKAWVNiP5Ir3yXRwRfnUAqY7
Y5Bq1lmfk7n0XRAawrhkSWh2sxTWTTCCuaUNVBn08iEmA0iX+TUTXAC+LlZcSo9fFMSZZb2DF3ZT
GMI3INnqubtI7MwvBMtdPaQvpV3kUOHX8cpMqpuO2g8afdEwff9P3ncmMWMA5NHCAGCOxRo5Wp90
6HSN03d0uBSB6nhjOO0FPlX8f/3L4HHXhwFlgG4URLadf4RaO+OuxJL/gorWWczJwWF3G8JFEB8K
BOGJdJTDfLH3fV5D+FDADv8XKsbHmLfyFQZyBob6zA+AxYOD8nuhhFJ1Oc7X7eNInmTO6CZvQKMh
FI9QIlEb3J7yPWzI9lahKWJremcyOrMbWN9bGMVcbY1chlBpEolexDfRSSM0DKvXqzGG2Nc7cf8C
hZuqS83jFCqTRMhwTJeAyaVqhtUcWovOFuFGZcxe/Z7TrueLsGie5LUn3LHIJ5sqOekeh9XLz6ty
cIOIXzgBUrCo+GSn/VxefXxXQrgr+i7kkI/jE3i59N4S78d/jCbdQIRpTfPIqUNimCVSkoDMdYIU
cSCT25ZlyDDfm3UjbaV4PtHeobz2ovJZfsW3u8NI/z/fZIfd/IGBrBf0UVcmL0vkP0MaDXVoSkzz
PhiKHI5ng/OKehEv5Od20had4ejO0832lcfqKsegtMEciYTp9UHyoCJ3dvgppB74fY8WGjTX3n1l
K3l3levTIRn+yBDzYMVkiJXWlDexJd8skyYNxcB7dvklzeMXehTTkUBEFSTlsvgttWOnmL323KVd
bEFfp76CssEMzQXZ6BhfzeKti5v1rUrtFOpOjceoLPL4fMFnNvgNvDZTE//r5mqM0A6Ehf42lqBF
wQanE7LOULja8s3MJ4cCZeS9C3b9cxkHaRW9FCRj1L6XW0wrreu1C1YK9R2Y3exhzhv9+e4oBOcL
1GjH4VXNurAU6RXXRklapsLmA5PKhqp9miu3Odv4WrPLFrL6PB3LluiEOCw6lS1Xhh89Y41bUIn4
sXKrWAgDUbmEBNbuXRKW2Tu9K2K4j1CoKv/Qbe1AH9/0FiGsiSRuTrkYVCugLCluFSmRyOJx27Br
VAB0vO+a5VIO7ftZ77e+6qTcbTyCSVaJiwkPh43bODCI06+H+iD4B8ASWs4JCQ/GNbCJpWQarXBZ
FDyoflSjFusrLhizaf3QG66tcaPWZeAbyq7sW3EYdePkyHmF1jJ1y813I/BTo+hV6gWY1fnjGDVk
RgSddgiFD1Wvkt0OYZ0dOhoWfFH5RfzcwiyLqT0GDayYLBA21BjzTLCn8pVFhr1k1c9/HEiCQAq8
9pWL4uR+sxtzIowZ5pAQqxwlC3RvSfzWXyjuYO5f7biblHaeHcVBzhKp2oDmA1oFmOeVD/1P6CJu
OsPc4f3VZA/6UnnawWD7M6wP+ZME7BRi4moe8N3RukSKmtHq5az7z2kdrBc+E1CSJgeqi+CueGaw
l3owYRRNinqusoZDDr0KTwKaSA6e6oK/QjsF/W77i3g0uPRO+opB8yub1Wk6Rm6K8opuJlO6WUxh
BPnci5beLV/tHUdHWvSQs15Cp5nrkuqHB0oRtqr9B3gCzWPGeIoFNNZWxjRGxV+23e7oFegK6xE8
PXoherFP9Uxm90RY9/0lq9uAoofP2dKxvgZ6mqC0Z08bH21L9UP2V+lExfwwxDXcBxAOgNrpXOdU
Wyuh/RFpXfhkYuPFOIZPTfMKUmvTs15gfnXSxp0No6y9yDxXSjWD/PNAxDNDMvFOC8+yCkIrSJBe
1xNmnN1pG8Zww7yeikADd36t0y0yAEw5AKqAA34kq1BpTnZzG5BFAj3H9BRtUKAYInKGnc9w4a3N
U1++L082MnxH/A0vERU8FEFZe+h9VPzwR97VQf6/w8ZDoxcVbG4XM7MzlrcUPDFeKjPJ5MjR0gXU
cU/mqpTy6CWWmY4mu+XwUgwv7I7vApXkqcffqNK+6tQjTBlxWftnm6kEbx/SdoYZICag9GplaAkG
MzIpaWcAyH2Rh2/btsXq8YwBap6c2Xmg+KEam7gDrpSJ1JvfWHpk5qgPF7mrIo1Mrt9xOuYNX1Yn
HftknJRuV4ewrEGqdv6fRZfgl7tcEG7bIP8jtr9Saw+ZnHHhBbw9BIEhodtfSMCoaa1Tex83Mv0c
hu1F6FPBcls4QCElEz/evcFfA0NmJa5MiPYt+RE8PO8NDjMmWfCoQeayj7BpS4Odk6tTVJ8jVW0w
cW9x5yNjnYQ/UFoofqZ+UsKu10x8yoImNlQYj3lloFa+C94NAG7O3oqNgS8aMYbxu7hHReUjE4s2
Tdke/5xeflZI9YwOk8DcWd77YJ8pVF+qa+BAu+h4hZaR/0lOtoMiABo2cgkrV/VmnXhNBzHcsBIK
vqPDaeNqmeJLLf6maBNm7b6skHyZYQQM01ZhcKbDcm9wG34RRbcObgneVPZ4w3rEEEIUX3dY446l
cZmJzEbC4pYoD3qudyr6uBufArfE5FHIez9dt4B44mtluKY1z7PC4fKtuWDbbN4XR7QKs1Qf7tUP
mhLtXZj6L5As8QD4UX2PbGyM0RnAta4cgwvyifhgmMd8fOY261MxiI8YAOzSJ9tRy9dTKv6t/7lg
Nl1VmMMTjetBcrK3jZzHYxQJyHdKtclTOwH+/xktABM/WfNUnx9p4e60Sk2WVrq2r3UQ5gXGduH2
7PDtx3mu+GwEjJAIetwhwYfp3aNyidxuSYd64qf+Nl8LM9+mez28MYCfawECb4YDQRKENWRJgU8X
+4qQrr/3nj66zAQuSKft7CCDPzMU7dzaqgB6txs4kDMw5KjC7DvlGbsR9cPer4ZIRQwrkGnfP3Y+
+DWmSvZpXZIoz0XbRavRmG/SR7lLSBa/Mtr9P+y1UdsozFhIpDfDqLq1eNN9derH2hPXWr4lCXOS
n8uYbfySX5NkZ6iGNHcxKjP0uzp/Kto04qWda7CLAkmDlgQxA8pqDZRazeTFaqCjJt+uw3pVFQo/
LoBlW0wCeuyniELNJ3Iwx8+uyIe3id6rshdeidJ76ZgfODj699lIU9g9Lm+MnaTFaM635q0tLvBz
ksvxLcLmKrZ7pUVkLxf8Xdi0Lr2UK6QZG5tnJt0E9WQgsGXLTM6IkW2s5STfkDhQ6odKfMady0Q7
/XDgFMztMS6CTz7ubsfPjjIUovIlK4u2RvX/EeoFfpO86QK09P7W8w5NH1Eg/v8UFHxg7qwQ0gYT
I5QqMHgll4vvAs1qUMstnDNZsUMTqRswoFszsM5FHUP7lFIY6UBMiFq3s0Yya8Jj+X5JuFl6uqZ+
HV0hOSYlS9iaeXk0BF2LmIno2DxjeK1IXXZeTe+dF3DCELWpSYgpMHRwzEL9QlhQeP7vssXXGH7+
ddVWVAhzEyp1LYYPkwChb/MwnCqRAkspPH6/FcZeKaiR2pJgB9YB9oH4+Lf2roSH0TlEs9+woivL
OtsqRzvZDA4AEPZP0GxI3+P++88QE3/DMz+UehxR+/wUTG/EFZBBK6ca4Ub/XdC+2/cUY+0kPByO
/XsrtCn9cRsLY5v6eJ/NuiYB/3F1tBipC9MX5lnXbLPPMUUw2NHrAJd1eBWWRfYuMMDl272RhcnA
s43d9SO+QRqlQsf5FJnJdZQ5sHGYnYKdU3rNpByf8hwJ7xLXiZU88pNnGSMlcjuYoTUTDYYsDvEG
uNCsufkBZIPdljrvoJOq3z0E4ops3VqyR8mUq/Z7Yb1RV+zjLF/SIPRp3lIZjGaRF0jYCYjg1r/8
EIWs0kkh3HNJDuc/wuT/w8mNiowDGpIzLNVAFaX4pyAi5ICWfWLO0DddTX17oDLySjx+/Zl+F8vL
AQqYd+hyzwlI2bkLi8v2MCiDJS8dZBrdddXM7tiHDqX5g647nR6oEjTVaSjPS6PfkmCU9YIjRJlt
H7B7wWFfTNwH+HOSKbiWWuCZHICvsnDm8lnY24WDXuhwhz2w29+JTEpEoSvpgdZ4BPSc7gss0sG9
9fcJhnEKAipIm7rGytp36N9tyLm6oqlyjcrZThaX0pREowQn+7idkzyrHVPbAgH3EDVHC1UGPYld
fTWsb7zr8MZKkPiEGjNe1DS5pCHhg7io2y5e+ijML73ab6vVrymSX/7lFlGSihedVIB/VeMtasfo
G7uTJ4JKygkh1pA2pXszoT8uLY33MJ7DXuDNHeifFAct3GK2SJpsMTpMrqx/DYhJhQm440FFV5TB
S17tb8ciMnd/wxhksFQSYVOaDg8Dcxzgx8lzuyY0IgkQo253rNgLtrLhKSZ+uEHIdwyAaALDqQhc
Dynj9bhgGhkbqMrI4AHcBcwckNfNYS1DbhOzaoqFB2HCPs4th+opndbV23o/4zV5TQApVjth4TQe
DqVbPQYPsmvqnjz5ZhgR53JLoNj10idagK21bR5awDyELItqlITzpw4/BWhO0rR5h0njHwgisnj4
3u1KrE5oxnHQtAD4238A01smmpUvS8YLMCreV8+AxwZbYEbBja8nwXz4aw/4WpgKWzxiW4+3XzPp
MsvyuCOgbL2bf0KGYFLF6x72pOEqhH1zA8yeya3dxcXJ2tS9SE0klHq4zPPLMs8PHrYW+FvSU+F3
Ed8sUEm8ys8/cUFBrPUCa+zIfFz1CJqGsrE/46/w3cpN/oBlPHxWgTCzw0DcGbackVvqYIGtxPqt
/O1TvoKKjMulZw5HlpIKGzuMR4TLlfgMkoofn76C1r/uvMkqXUaO1iupOoOqUs2GGJKwp/vmaMea
1lS14mAkQhtimeBd084PBO67T8A7R0+tuqrUHpfhHlBNPyIG08POcspEo8bmkg4hcBPNYotOehBN
jTiqWHnmPdPRV7aTqCc1AmlM4M3Fvi+DZ6Xwy6KMpVzdP03vFJWHHwBx5u82x7R3K0lsixH+ah72
sDTUXaxpbivEEaqBRHZtb8KhrsTAFwWYvEqzdrWqtB5VZPRR2fBQdK8jAIsWUg9K+Xb4qTo9IgY2
Jl6vJpbDUlOQezRMnEL3I71uMdSOyzjNiTUlY0JMiIu7LhbvR4gRhy9GMq3RBSK7jutCSU7g6vsi
jOtbNwxolrTh90Dy+dHkNH/jIi+cmE5lZbAiel7z42PTc+J28xz/rjonQ+Z1sa+zWJf3wRFm1V/D
Lgsk0gatiuTLfVhuCCUGe+OT3khMUPi7lWDEfQ++VlyYLgC3Z0ILgJLb8TFk4xbyFj+kYO5CqRhl
cdffAtGDxhJNffN/309X9csqAhkVnUwakB5/Tb+9sXF32HlNou9z0zm0dou2FVACxqj6orswEDyf
OgrxfwSc28wvqzQPPbd9IZRzMkkDeatqz2+PBX7wPhf8vRDa4e8Wmx5wZg1eTSsV1KjxA5EYMULm
dPBbknKr7l582PkJzZUmXmNdzhdpQIED5sIm61IPOSd3Fe65L9NXWP4+jcg10U7dT1A7f8H8U8oL
RVUpeLePmb/IVbi917wHxGGUdoPsEzgMI51J1pSSCaFc+BsPJhFyDYwpGbmZRlRuAFxsfuhQAIhW
8EiMFKFKQxYChAM/oBobc3OtO7MKMyfEfFzoM2eRzEaocHQFdVhcgJZ//WOT4c/OzO0wQVFqs3jo
jjM8Xk2ugx8AcWz6i+KLyVjALP8W8o8MV3UvpNBlGJK4u60zU68sVpCtR+DRaTSO0FrpM6EzqY5P
plYAPqtu/IBoZGBxlTwPPjPEMuVb0DOnjiwN14bY/bDH1NzGpIQUPXx38yzGlWcc8PqiSuAHgP55
4OKYBD5PRNwvyBCWAvCzWw1NE/PY/5s8AxOphV8DuAhwm43SnAtu+gYQqgsHk7kNpHCtHtd7GkTS
bnG36MUSiOd9trIbX/ddFVDHClHAxttdRGb9ogMfvHZG5kguef/JJS4uzRs7yEUVfktCs3SbreKC
dE7NbwZaoQ9EjS+seVFOW+d/FNPi7XtSOJATe0FoL05/IaT7dMrD6KrQ6bmGluGjdKiqbzCYwh+g
e+/CEMVE9fVsyt1s0AEG7Y7l5AIJwQ+AytI8nMJaOJXxeBA61goXqm4EV9FMdibivfgmjdgjl6Qo
EMednr0qv8fXFIRPPxKxzDwwgGr5ExzZ/X9DnOKtB1MZ55gOLXUedbu+E3SW26TES1SahMr7C5yU
H6eXuaCOdHeJDnzz4MDRIOEvJ/52wDNVBP0JE2hhH6dgtDXVUc1qveltYYuEWN2WjbOdEJ3Po33y
cQlkEJAHsSVjBk9MwcT/CCq5kwIsLbDTD73wr0yL0jND9uZEOSeVHSrKaTBoVGtcqZPgeUWiNTgu
nNmQD3wr5bPgM6S6wMqw0zJHuFpSQu0yvMN04ER7l1yODmiz45Ya7jcx1GLOiBGYXAGtvfd5eMym
8vpdZDclFbjC4jeSh1V7VYOa13WfKimHtZXQzA87iChChwW6QcQejPF6AjP76dCv9YFa/4SfW+Kc
i8yVz42tAI90dfqYsTXes4OkEm+YyV/tdfj6CCsXSkI/EuvP56up2y0NalU+poybmHVEZHRMu2ik
dTGqIWZZ6UL3MVg9HghK1F9HTDxt5Jow+57vWEOsnzNiw6MzUAapnKThxmf6MA6ZWyAgNdxf5pP9
6gf5IXzZQu3RUQU0MwT/oar24vaoh70lElYCUCGfsTSHPmxWR3dIOKcs7EkR7MjtTCx6NHWkxSNt
fWWy6zSY+b/P9/DBcvqBe5S0Wz2pMyDgrMrkxjKv8i7GI0+4lpVIRpKA13xHp8USCzdVpRi+SOhM
nKuzl7kLZ4gAtlXtQn3HI8WFBqYKP5RIehaN9JPcFslk7AR7zrXsWYVkXUAi2SGYQ6rbxBjW0bSE
kw5SvyfYAhRCkSzQn8cNy6XlmMFGjJNYfDaI9iY5rJxCFszpI+Vxy1uGEvsPtN4Kb8P1DaW8gmYn
SN/S/XFwOCpTZMaswOEtFbNTMA0uorZHE2VQS7vw78JHnYK14rKLfOy77UspxzxdgBTop7C2fsP4
nijeK4hWoBTeo5WewRzryj6AMlCwKgg3Esj7dm3jeiOmmLpLO/qAJ8DGGrTrAS8RaSgyX3qE5pAt
04WPPfQdhU3geEpzwBsbbMJeooXT8QkByTVzRhgvgO8gb3/1Y57xf1bAO18lrGI5F/NEmFKHK+lP
UyG1YWeT1QzrrNC1YpD/Qn9+89hDLoArDK8OKiFDhflA2ko5oQDhKgTuQbVCV0nbBZWLX0Jus1o1
xjV0buY9uZ8Lrkvb768mwxdjW2x/5MPllgC7/0dc5ohBQpEcGwjA6bltzNnd1SCmdSyW0NAzZC0+
bF1cbTcLVPQr//Zg8MFRkymnU5T6PW7Iwk/E8RSkT4ZhOfsqHysLaZUy6y9SotiUZ3+VDf04+2P1
v43Fq1YPglCjoZomcBd8OXq2MUsJiAQYr7/hw0Z2FiVYqX3Hi0sgLmcyYb1tDyNxgRizCBbm+rBT
VjlVteQZceNTspHXLh6Ve8H6NpW6+0osYqESIojnBAE20Vb93wSab6LSh8fV57ylX4WrFO3w+szF
5C04HBxjXrQL4wGvc8xFSgrIBDLM+dnh0IAbEh+5yHiswv7xveIpZMPpXpd6VJk5bKLnfRi/jQMJ
N46KfqZ0LcV6mzgzjhlNzp0VS5AbMuYpIFMk3oPE3npGFs5+ILNtP8nlL2IguW95/GoheaY0DyXX
eqOOg+PLTsgAyZRaMWrpvLE8mqg5AsTPKcOOLK3ib8FV+jxCgLbRstTQ6smBufxXYJTn/vZS1qSf
veTC/MtTF3WgwMHwcLyFMU6ksDiRqFlfngCT8PBX44hnGxYYhKtux7VZtvEdcvuJnGWgBc4RGT/M
cP15JX3K7xInyqBixGi6+5iixrxJrrI99maEjk2jbpsfdaXBpygQ8X7B5sap/qAc6evTpVSVqTGI
Va+KAteIPjCTMs9/JGRITU/20GX//iFxrH4Lbb4T0DXtR61uWit4Ao0fgIxvifNJLkKX/D4j8ddF
8yjjUxiTmAR+L5/Lh45rFgjmX2z+voU83p6cZRK4ofGMfpGjqEcD69tTJjnAyF3GAM0w/E3kh4kV
8EAgVP4mLY6rRFZnakXyuj4RkJkGqUU3vJoPu/rXDKzNrsoSh8Qs4mFRc3Mm0rqHIRP7knfwjd2u
ajpqGOuyubV4GWfZMhwMQgNWP0fX+plqU8LMICGPLAVP6kuiAKGssYzxZXdkSLcp7K9rIDfYyreY
ALFHCRMi7D9PLiXiF3eZkdBOFwpkM5o1SYqNG6SZI60u8Z7ylPhp2Km1fndZfq1wWZhDr1CU62it
njObP2PH9htCGDKzQdDTJx0W70dRbdPETb5LppzwfCM7Z8pzkgU71gn3kU4n034RtRiEcG7nHINQ
992K4Zf54oKTHUevgCODD4l4epM+pzWyLBOnBBNtH+W28cmH7bwWjRcnH6awwqw+YczLM2iuic2P
+GFe9bjlKYcEW466CoowC+RllRixxJTSyrgdGn6FgzIZnJdM7DjIV6aLy76UAOdZu90c0YIQMykQ
4RATYUPTrZtWKP8gNEAIKh2d0OcKVeMF5qbac9J+96RkIH/BZLTvQV0A/NgXr+MwM5JJCTogSPr4
Lno48Kqhi7s6V+Sj5O3YwItV62UXhWeFOqgZ/yA5pQJ2dm66kxWuPlgPXVDPAMPsNBE6v/VOgufY
log3RvZo2FCn8dHZVu0x80qdAi8ut8IeBhKvhGdy822pfICohNyVAknNPZv1oELwn/Y2Ox0rsQX+
S4Mm3xhMQCIThgpWjf/oLEg9WPoVRRFA4MmT32QxhOowj0aZlHkwlM/LE0Y0L6Z1X+lJa7JxBEXb
GFgOCc8ZQ3oIkoYFQHgl2DeUWmLDTLpStjLD/IVMFuf2WYv9x9uujlAU3D5tqZxdnALTtzRrFUtf
ugVh3BhwIEHtN820v+yc2kssEmmotq42OygAjGddnJl14Q5rMw8cJcrXLcJjCl83mSHCLk3lf8vm
ONTXiv3/kSQFz/vyy6+Fowy2nwwqc4IFf1mCt7xpA7PMF1N9D0vEhJPT+AehRBre6iApu27wpjNf
Wx1jsb3Kkhy7u2RAWPbFs6kqxRb/B6Fkix/uBR/b9j1bUc8qtz7bWUrEGaK8njm5j6MHo29Ggm9d
/TDRrH5/LkgA25k2zIEqmJs/Kaf8y4xpFzZZt3X4FxyyeH4JgxGqagZ6JVzkcoEW1a7cwYNtuJzD
xyb33W1iaqkDclBwv5/EJEQuxxNxmuNepc6t2hnFXr4WHiCn5aZNR1bTNUTKVAg2JhNPf4seDNf5
4FcRa+2O/oj9g7UMexCx7hUEFHgmGCI3LdCHn9AayFn0elCjnEni17HiYHdJ/0B7wS9K021AlAj+
xMfyc0s8Djh1dynC4N+LrNHwXHVkZNW9PC0ch0LuVf/OF0I2PfupHYZXbG0zWM3j7/45sgPLmZ4k
RvosR3ld9EnnYr6T3UEI/5PB4WD9aCtzyN0rIZz8oBdXjyvzAbrVY/2cD5wy8w00qkjEUEv3Ilqj
8v41Y5Qum11OtipYhTUQsQGb626DQiy43ZZk03X+S94R+qraW27f7CtUF4v03ZX/Nycga9tPtBHF
hvW1eiI2WVc52O0MtGsAylDxVYGs5aBgkBJOBJkZKGBpUYD8v0gsQjT6uZG87syAiUqIa4AM+xmW
bTn4R4Qee1dMAU0eTNmDNDVS3BgLaYkteL5VKFSUxjhq1xRAFGkz4NLd2Lf1LaAGyRAEBHgSpWWu
mNYWMi2Z+rEXQcp3LfbP87Oalvum76LGWQBhGmFX2dq/EkxewaKzHS694hLdpl+s+bm8zbgZShIi
CKYs2e7c/Xu6zlXOwSzTB0NW6GgKRejIB2Lq21p2GoQOOUAG3JlKpgOqFxuIxBE+WkqCKQ2kneNK
ddYLJ2aVTG0HQCI72P369fn9NsuDbGQ4l5lBTuH76mGFSabj+ztw50nukrx6yMIAUff3ozduHlHT
63kULHirCiMnGC6JZjt+AgAgk4ouijK52Nwi0O3UwlJRV/7MeK95/mTuNORliCOvv45DIHrepODw
Tj0nYOruD6O2dDXTUJQAvZT+D76+M5aw0i3P2J+hrc/ztEYrhk0GMzmxkm7S8K6/UNHekj4pFl0w
x5VEvmXV8OgF+x6OvSNfKTl+FhX/AY2bg26Ds8qewYnIOuu2zRsGeB0KlAGX9f8TVzmGq/groMoW
4Z7rIyXFSkuK1ZkdZn6kge1cziIxN6BjRFfOjgavBWGthqQbGlKDslGgiyQVWkwRwTdr9vNI/30M
vTM34gN5FcCeOELLwCQ/ieHRLo4NeBnqNGirvpknJbi4SxgKIaNFwaR3mOSqZwdoDUFo6rv3SS+T
uGuNRvJ4gHOLQ8PseHwePl1oBJiphvWg9sypq9zRSZ6Y3ksNS8osXu6byFpeSQslK1oEhoYjKELo
QB7CyhPTrFO1Uxqp0UoEG8mHDzhNspaZIKL2qpxHMsFkLRDzBEF2xQXsNo/GM83M2LkjO+T9zQgM
1hyVkn53mF7HW6cmqVqyMPKM4w8bLj5gl4jW5M2hFvhgYbfkFfH2feLBpRWxMeCN52a4gsUE9824
05UXrLBbHQdUM25nYfXSEXjJ0zzsHfc51TqMfwISPGqnbEAXhuQcBJKBP1Bxg6fODIA/nSVIaUT6
c2dczScq/y98uKWdqSNGkVPKl3k+44n3dsgeux88IWYCWLtGHaOmSN5ofHGmOV+jwFkKk0mmGiE6
6SE+ipEFZQ1qLi0Mv67fAWUZJK5eoSrahipkUMHsxTEpu/Ye04aM91Dswp8+xfLortIg72sHF9Mh
Rh18c6Cp6z4eU9xVqqSxs8bl2gGLoUTjcTccCo6gDDvvXTXl/Kg025saiCDI9v87T3mOL66abRDU
5rDSM+5GEAfD/RVT63GfVZyc4mUflSzDHPaF37bTk4kt0Q175+gI9t/FW2zboh4jau0UyiV1pbZZ
QesozC4WSER8ApZnhKn/WQi9uZ/inpXTmRZtZsTCnmH9GyYxP/90mksplpLjn1ciTIIKb7xxt/Ux
Mp1FvZvnOWF+1i+/lFqtclyoKznI8xCsihOdO3NjqyIr+3OFKfibZXF9KmfWK59oKSj/AsIgbxvD
FJbeiIqNGwT3EaLjA1ueqrPdgdQ8eIsLXHko7zLkOhjOxodnZa3Pea+51bni4SnOAMucRsUoPnF9
i0A4Os7w4H9P618r9hIyP6BejYxa60hBqmsRtuUrKEGfCL6xsVSQ+wypBw/eDp9lInIiYWxfVn9p
Gl7qDXTAxXeyk/pi7JyXLfIF/U4Qnqwsj53gtBC9ptbZdbKAOHw7uK3fgUYFzd24+mt1Oy9k5U3n
NF1fNV6qBO7oZPXoA4uNQEmLDa31TnXyquD8z8J/hDmH9B3pSJYS4z27T5/zh90945/szWeVhbQl
rF2VWSj+sSsIpQaNgwSpJM9QAeyAsjKz1LnxZkRNYgHjKYxAN5/dSgJQVpc8rTV90nb/QywEiuYB
JXAxen2cNMkOBYAjvIPDS1j7mGs4gJJqne0CgRvoDPqqc9Yc/0qE6mdBRKtjv7dpBhFr0dWRMSuf
BebzdnXoYbIE+4dCUOkiPfZpBu/DU2E+n3BiyZKkl6Y3fqH91lDuaVl9RZRO/whuoA5TQiL8No8B
gXFc6babFMOJXpoQmvrCS62xtD/Ahfj0GhXslF1+zIR/XD+Y3ryZs3XtqtwtPzKYWObL5m18OScg
0eI0H4jb+0iJbcNWSRhu7K/x6OFqedqhAlVnStfDRsa0/IiwqDFHuUIijFKvUG2IVMVyNZwl+kAw
iIKw3WJIniNe08NsH+mT9ubjCAnz4+idWyngrFh840k+6q7JKPyVatQIQgpRMs04Mz3Brkik/IT0
PCHio0+3NxiWbIM+3Umn9nnbLpVI8g80eIn9Ydi/sG+wons0hytDWcoqUxUz6adMNKlizavIeZXP
o7ZEjfroVodCfP2PtP86fxMyhALARZuqjZeGG+clntKdVnjHXuVV6LV4PbUe4tg2oKkTcNkiEI0H
tlr30wAIMSnXmJi1TPTe9lUyb0b8vY7P4qQY4bBiO/4NWIXDRbHWcrsN8pexDlNySYoxbuHvMjXt
U8sefkcEHyU4dcx8BDU192alk9SOMTe5QRFQdV8P/Gyo3Ps5KgTHbUt8TyzJ/YZmkeu/i+hhwime
vuAcXdgqA3lLMLOV7yEa1CVn0jilBTA6szA1k/i+Dkg4b1CBKZob6JnZxF7fv53ZFGmxAh1FTjnt
yKEqj25CHshVPdMNZes9IoUnKT24hqUWt9sXx+6adEd1EGE7yJlkv7Pj4dJV0JzRXflwt6ncbaa0
q5L896+XsgoKy0kioS/5rqT7TKtU76cl9W/tC2imidP8GEbHW34rO+nfDcvDcpTOyvEipdajUENI
TKgcf+5McTyuWYAHMRC//PV4M+gR/MW5JEr+HHVlQ8JNTXXAd1NF7TWXuYEvMdlmINRC6DFasr0J
CBC81rJllG9qa27U7MUnJ5QaJTiJEJ8TIa/EbSuqLXzNw02mvYSXvUZaZbV0SE/8e605ctdaSdXB
5CYve7V3ZQy9u5ToUYZz266fFDNrjiXiKUMJqef3RXPQgaqL3eBsYiT0ERz1RJhmIl2Jt4Vr+LkJ
rKkVRPuwqjkvSphLqTW/fd2iMLO4VDH+jM0FRXWALfY2NB/IzxySp4VdDFZpK2QAGfdtx/7sFX5A
h/huQN86o0OoVP7hGJMQg2YpnixUo+oR7CwxAS0H2yqDjet7iDprjA/CLWuuEMMTrJL+VBq4yjj2
+0nM8KQTAMc6kptGaFrr3bNVtCEB+VvpAgIYe1ppkXfhnYR0xSnOz6bb+7COoiE4NaeXtcOpbtVW
tNq5nsktiqBJltPjgbYpiBX7EhOn3ZXJv0RbqFkTJh2DgvHvFbtpYh7tGZtAf0esprdQ9vTAR41G
K4bhzO41VDQd2aEi+6zrxIwaQ834e6Jkxd21GVFrROBVMAmPqaf1F5W5XtJTGc0jKuP6QqthSkd9
10x+/oMq+RGfPCytSUoOrnYlq0XdACDb341Cn60oxw+zNsnR+bAu0zxj3tEVwfmFhIGgiaSAnSJ/
PMf8KMEAT1TZTEKJSF3fWlL1y8Lk+g9IpRmmJ7KUX9YW6TCZH6aqqGIy+LBlU8BjXX8vYd9EKu8R
UuqsZw8wV9qeXTeGpKi8Yzir0Iomau+H/C0ex0J7DxTNmNuouRnErkhPOe2zExQTMBqQq7HVtSTn
uyLuzewN6MZ3uJTq/vCI07bbIOBsdbvNjMgR8GJdoGHn6KZq8DnlaqjytgXOX8WgbWk0/wiLNH3w
OJJLx12lS7Z6WVXZoZsVce5bTXNtTH+Z4FI/xsBexokoxq9qTxoSQcqFd5H8yvo/kPfA68uDbC1S
9ZkgeEux6HGNCt2iaFRmx71/tEb1WxWgzSHnprEWgow7yVd0/OOWTBxI1rMprx4LMBsbjLdD/41O
9vPx8nOIpiwEewUQQQi8HVhmMMjSrOgwGU7hIiOpnREYdjB46U42hDSdX5/TNJTwlSFQGE871cLt
BKmFGBJ38RsYaMhG8h62fc2BlZG7llHQRSAMFuUH2e1P6lo4l5l03sk80w2tRs7tf67BQBNxMHpG
A1DC/aONhru2nPsEqU8Npqu9NjVyOQnxVdntLQC8Q21lGtTYs40NfIFHoR7L1hyBCykOUem1T+Qw
BaPqwHW7LWJfrwHxfgearQATgMqkiTLZpZdHOJ14psvIYYc5AMZwnWIyQBI4y8PBCCX5Zzn4aurW
GDxeX4o3tJNlq9nRw+GB0Sh4rP4Q1FL1+mhl+spniBcOOETzFkTQ4TBJHgtLbLrgdFv02AwhdFr7
Ss10w+TdXjJQU8ygTdqyIB1ESl8MtHpiDyYNdciPt+Jm0uw8Lw/KTo0Jw2hPTU+NYTE38tJd7Vzi
GzWKDec6+6zhrA+vX1TTQfxyL29E9TARuefrlykM4pUxfIlgyNMRzquXvj1H7DFJBJiyDZC9MwDt
n+4R23BTr5R9p9WYbGkq6SpzWeg5LjixfB887RxYHPI4OGFBsqXbIUSqY6aw20GOXHUlEGGcUl3t
HIvyjDsaobcCT67xZVgBivx1psT1fEXMX20+1bxoSzf1j3daetOcnjRbVmSOEah2V2t8UpX8pVM6
lSwpR9GucszMNDgFhrSdeIAjbTVS3tFuze/qzb3Gp3uwpy0jUlEnJeo5KNRc7Sb4qP4N2NPq9bBD
i7OBGxgYBr7jOxCSVcLu0JfnPGl96tCLtMHYnsPveZ6lK0A0VyoNfLN0xo1HWpkFVkQYKNX9wbxo
262+gd5r3yQceKP7Tdm+3D6yoD04l7ih0HiEivHOUv1FvxPGqNT95XwaNzSdUVgyt5/S1109tojB
O8l9fdPJs+PHUrG/VZZ9s4aCdj7uKCLNvTTLSIX4u2LEkYqYLYzFXSw2DCIN2d5ReRRoQ4KjwoxR
RLfhF6FwTLbuDJrbcZKSj5he8Zpb2MZaYUUKVtlvOKB3cwl1qStG+gpFod6EiqKnxummcmmMKW//
CcuWYPsDzcTb0Hx/MTXMWXUNOY7xivrHFXzJvb5h8agGrVQ1p5CiKSHOOAMc5bana0O0YgQKAnub
bB/9iP16kBvDvZgz5YIBJZ25N77vt+5W3+oVUeFAHSt163xGXrV31OWZHSKMOzV5Z5S4EUgMcxKI
fMzVm+RoAIoE/bRmMPEfJvGZP7dcPZyJ/MuuP9dJzYIKh7yKdeVzkkO0Z097ACUf+sx/Tk3qJbPi
9ogdKWw77/X7Wtmyj9BWqb3sNEWFt3L8BGQhN8iR131sJPQtVy4h6KTUYZcR6KSMJN2KbyWKPp54
SSE0n1Pc89oR+s11OMcpUNiEr1o2E4Y7Nqn8rkOii8mrO3RAIooG12AgIRI7qsDuIDvZlgWYBlSY
avqD5ikuht0fgV6PjzMyzrP13shDPRqckWYGyeJycMroJ4e2pCETye8fMDc6jViWKF6VM06lsh/S
e8vqBsFdDg0VwDJ2TfUQUaovXIr2RPBbA7Qbl14AKynKphXiuCJ6jV9GakcaCpfnOJ15d/w4jvbe
GGh4PHBaPlc7J4GQswmLvN8Mz6JKcHe8ViW3d1+xfhcyqsGFPyIaT1zzOrY0Mat1hSAqB3zegY87
YIRIstgQ5ZS0wJ2ATUqk4rx64z0I3Jo4F2GrdE97B8RkclkDbLxvFiOjx19pB/7kMotq8Wu/cmSH
oyo6PsA2Zc7PEDQ44EFQpMstIX2vPzVVx5hZZfAd0gAwf5iEEFssDkWkBWhXW0vboJxD/E/I7XCr
gPdsbgeo2X9moa0WCoe1Z/wZVVUspu25DQaibyTwGmDLwlwH5nB4ryVD5Y0gQ2F2nTMv78hPBXy+
DDBAEGriSNqSJPBltKoa77o4ebBGODDvWlcdz7/64b6YXKuANAMLKVCJ67dMPTSzS6TTHa35Xoi2
UfoBz4h8SEoGIhKoVIpMPGL4suWdAArbfpFU8ZgLknFNmf8cGX2OnAyb01n8RQF7SxPlqhZcqfAH
ZLUjo9NoVo3CddK/fmncWBgRrQzBzaS7YFulThJ/0ehctUChYICb6cvLDs20IeD1ngKBXcCeJ8/E
V8/CiN5lLYq02U+UkatHN2UAKqhvy/0JB9K6rX+ebjsqfCj+mWiyf7SbvJTqdkt+xvTzaJnv0Nyf
zo5uq/bMSdb2D5kA9UEBtAoM8pY/ANKcN2Fjf7kO7kLbHwV0IgjQ+RwgAKSknes9SfuwFAdmbRvK
yavApGesyq42b7fJ0bnCVo9jJ0u6XZqxH8qVi78EpJ3F70LcuH2NAma5mnFevYCt+5PQbsuqmCj5
vVV3cnH3irXHKB9jBpfkTzV41s/bSC4K7uHiV/NZS/p2jx8ouiNyC7cBwx01UUjROxl2aovBiMa3
BQtSWzukhvNx8VXG6aK39TUj30o/VeviT+Au+tb920pDQb0vuaueq114daT6U2TjZ8NUsAwEdTfA
X30YP9hw8gPj+GOK5qgQpFV8hQLZuwpj7WqYCYs8CfLbRSNJE6LhY5GmrzIvNbcuTXkj8RGoF0k+
rwubXNiX6abPe5MfazMv1O4e9yk/dOqdT75gyMGfABuu88zwkPp5KdJ3kNaVRJJ6ORaHbeS7eEZl
I3lgBDGgoKLkI1qaesyYFDCURk/nNCYT7cqIi0V1DAykyE7HcYyvH5vLHlng1cLcHCD6W95LMOsx
cOAuWH88w0TFn44SVbHXpQfKZ5PNkTW4Y3sgPzs2rSV0jXGZdIr5LIIcY5DTYS/J5h+LkEMyMTbk
Dgh/xOzhmeGzUMQRaU55GwEogBWocroxnpvp0v63XfuW0T8DYgcxL9UqGwvIpn/2q+f7tsFkgvIY
KAMCKWtqbfDVHFzucHv1ONZgJ146monPjzHZ2XsqDCNGcD71XJ5Bco9K00EnyB7U4ZimijAVMjRO
dQKh7lCb1RFmCshoThPzxkV+OkkiFV8PUCcx7OjGj8+D+jKG+MFlRBE6qWgh2Ibgv+lWt+lVBClY
FZtRQrh2LIKG+xelG6np9SfDeSyMRPeWkSbhTIiiLvTKbREkbM5MVf0G1sXTgltfl/+LbN9XkC6O
nlQ7VvZBC9q3GvuZqf4sfw95X0KUvZ2jykkcvshIPpBlQt4gddNUxxZkkRFAGSU1pJzUFRpxcmqO
PgcYHrohnNxtIFlLPUgGGCQn01vvQyRXBpEr9+u51QEku5JhaFTHtGOFwwbcHww+oaw6H7VRKMFB
ajMy3B/RdJJp+xtBvNyy0mgzeh+mhlfOacZ+tVwMfWFYEzImSms/OCED+YKwy8zL8RnS1OCQ0Gja
q9/O4vaPvdaHwSm1MWctlhKbLmSVI+AHBl9jA4z81w5wXFt7kyAKMXmQ+PsX+TGaXm4RPnZEAtYm
CWasIBcVGwm9lyTRkgST4BaPSGM/B07FaqOjCcqpJ464IA49CZjCza5uUgzVx+ZBR+gES+UJWEzP
YargBVwed+nNhJopoKULlChETFMDD7EFqWmSA1MrY+S2oqt/PpXb5Itar9/YTG0sC4E2+vNezmvA
3lQjV4iW4Wiq7NDcjkPO33qD1/3Ghpfl1IX+vbLkSkCH3dBYoC4MaVwcMDF/3HXhk/snhDPsOPug
SppXJBO7Q54XRFTsuslDIhrgbfI6Q6Vffgn6J08ys75fUpIq4xOgchjJafe2qFfVXEprbGQZdk/x
7hZNUKDoU4Iv/9OHyUHEKKNiXW4wc2+gehWQ6XJC4ucodqyPEYBdUtZD4+1kabDkge0y1ypqiQfe
994MS9u87YGyHCnVkbZK+HRabdWj1mfg6mRXCOXH/U5LU5RhGuWR1LdbdSuK+6IgiFqv3sdHd3QV
2cQjCTDuIDdEvxg0CHAVWsMtGC3HOc1qVLft1dFxFXJ09DdZUCYRor+8X8XnwBLEncGqBd7qIh6s
qa83gfOqpXdl/vonXYPJhxvHv0yM1O8K4RHWflQ4TqmIuxGg90dA4e0hzQgbOlG36DFIhyMYzmMQ
eCovYa+M4p9vCmPhqBQ8pxC+8XTglkKlNiaxVfJx7JMSXBG2iVEAmzZ5Q8P9la/FdK8ahhV4Rrsn
1J+yRYwKxMlq8votL/xqcPCZxNSvBLKHFzZVaP+1ac5buY2hkD1uM5dLZNE3VriV4gxMtIaSVd9J
YoLQXYuEHTqmrhDGJLRz8tA51Xth0lR1MIp2YZw9keCeuWbKSc28XFDMtZSfAz/xDbgCxnkAnCmk
wfmtFVZooAWrV57ZlcrhOFeNc+bXeD3mpAQlXUl2rhEXEeSP/1r/td7bs2jAqeJOQD92gYONJIiY
+pBXPou0nmUsSzofS0To1xC1QYHKkOj3ROewV1MmpRwP8e1/GCDfIkVUaoZvicw/OB2ZB2wpvJmO
w/9GPvGSchRaYxbYsEANiawvIX9Z+pTtrl9sFwig5wN8XT5gJ/TnlsA1X+Lyel1Cs9v1Wka7Ude+
YCEKmZcICrfSw/i1JHw2ke1XtLc8SyG1S9t55EAiPLkezx4Kd4TPmSQFrACCXYuhoR/YVZ/X7Tlf
Qj6hdsWGSm7yrqWVBkLbH8ZCVI+woI6oBPw4q4OAa0iz0RKvoaza+Fhva39tUz/RmXrB2l0VtkYp
21W8FArrRGZPovLWqkSv+XhqxASxNPQK4VE1TnjDrUdtH9Jyqp22E3xeaqgHw7WLXvd+4sX9Cia1
gK0cdplW3ENXO7wWR/HguBurzMXTdXCVfMnZGdoBvG34Jlsjurap0dkXWNaD37FASh7spwjIgcjH
cgYoIX+ubEawEEC0ULQNtx5m2urUSqtiLdvtRqz5BOZPTpZNmmB+dtpGzQ19GLhs6TUIDmo70ZrW
abEWpysQ3qJaeFzYGxEnFJFl2ePcpKxu1TkbmvM/7dQE/Ri63JFYlISaKjwKiTxHVMsn9yZHcSb+
8njqnZLeNTnAsywFYmeWr/3thd4TPnhywBy1S84eDo7zw86nLxS4ayFKalC/k9tqTpLHR3OZFEWY
EfQpeR4sL8Ina6SnNNt3tM3f/kDBxxpbW04iLADuy+LpuMB/h1XAoBlkYS2I3m4/EQj1W4YENmxm
Jm3FyhtU4svLZAVYht/M/Sl+I5IS4AyMqpeTQiuRXscRwgxhezd0vrk8rpD6JrTE2HfnnXARie8+
gn6sneWT38yUkhkWj2F43lAWg2p5TXEV1FsFr4ngWDeE+7o/snFfhqk7fOtVvnQaFvCYqtE3EMEE
b8toaQTomotWs73kZOig0mXtW1X4MAz5wv5l41TCkggPRn82t5TjkvGayWv93cn+c479sKFBIWr7
uO7rb9Ot+NW5IRaoU2jGTkOm1r9PLxuWQQd6TymxudzYUy/00Z/ghHZq8LecseNI/o40zfF5cADi
6qkhezgodGhkgyVCNV03gcGTxNUxoShefFhNy9QLdCSLbc8Hqv+HaTDFDQr1SvSFhFkMFfZXpnag
tivFVThvak8c0IAdh6QhTZxjQibJQvazAtgjQCNuAtdlfEjxoMSdza+IpoBPw4R1HEoElxlKNEzx
FqoqEubXfin6tta/o3J0ucAiZMMf7DrtgBGue44BR8b2qiHsqjkvPUVeuJJgpR3vzVs9gawxm4q/
LRjJ9tpNqa9yI34YhV0qDpXji5Z6GQTMPwQpPr+TCllYU7IYl8x/z597ZJRTQ18Qv5L1aeGalPHZ
B6038afHr3x4CknwzYpsrY3JwKN+JYYMYo0Dd1XdzP7QcXh0+aK3nPD2fLgXOsLueOFBj5v+IgHe
p/B7iuOe0a1PFvGufi+0KWo+cILG387RON57Xissc1mYFrRU0rBux05ljcT/nHQzlbYIqgSgO9Ty
ZtnwovzW9s3JKeMIV6ES7oCSSXryLLQHiuyCtcxl2uu+WO/I1iOQ1D+lkZ9J8gFeKGdkgmt45WhX
B5uztlvJpL2K+HSd9jakQoz7H2lS6aZpAmYpMasVTvU89Cld38paeIxjsJ+ennmFxjBGJ1LVziwB
H1P0bMWyW+JaBv/V9qyApjuwc2XJnrhj1LnJOaXaG0XfRcMMyyYTOZxMbSjvGtWy99wFRcoK2XU1
Yglkj25NJZuUaVJubYnK/p9UQZ0/cAi86crLn5i32SLay+ucEjv28ZsVXM3Jx5jxlLP7T09QJIba
37unhO8Bo6PaZbqvrRjLyPrtmFmjK0CElhIFOc5Vi9B2kgaKRjfjmk+qq/Mj4Y1+9uR0Ng3kp76d
OAdGhH719ABZjQ82bE+tyyw4nCii2p8pFSQ6CYx+s6AK3K+XgNLh6thbLUFEwX2mn0Trg9QJ79f/
Yo9nW9zZMqC559h+Xcc3JgEL753liocI+0QGF7KUE0+6V9VjSqcq7zREExw1d/8vDWIAQdAzx9uy
k5GOzoy5MVRgFuyyd8xr8+zDQzDbL3AIoLsaDwNWjcx+alz2XILJflzMWl14Du2vJij7BP8yTfGe
3WA9Bnuq82OmL5dnV6wM3UCehxkpyW5i66Yq4ds9HEEMafuzINtKfzUhejstNqAEGtTmelvmozFr
oyrJsp8jpUUOeCCOobzya7FTf4KiC0G4Cs1w0m/0AypoThVFJjh8cfdDGpQJfH93K+7RUg8JiwPz
IANrBUVP6snYWw/DLoLBe0cS3PFHzey3vTW36dT2MhVXlu85ROmLFSqNI9dOOJZWVYSq5RvuOPCx
W9/tsWxuzKZlDoi3JycvanG99s8VKD7EvU4oDQObE7Ln19pJui7KrrIPYYo3gYJ3AIRYSn6xNus2
LAi2WQrxF8pGr62mY6667JAiT5XJLreuPWDwnXU6vPC/B1fhdIJ4Htb6jg8TOfQWtRQQcXeBUCLL
YDNacfE3KrI3be8GwfU8BN/oZAVbPBGhx7BP/q84Ostkmjqn4jkqFmxpflXfi9qrpuFGDXnohN/Y
bwo+oRXw8ve8vaiaspTr9yIAuFdVnA6qbSZwkyQ+F1isbSB1sUsAPjVjlvlRCpClCFcu5BxFtS5Q
ZeFHIVS1JAJVL9mXjNQYyDWGSU/M9oXsuaN9sW4omUi1292Z01nIbrVXzlkaUg/VYhIVzghBLg5S
F1AVcGDm8CN8N9FRbtho5uIqZ/ppbpWrBrW67f5yIKMZvU1JzZ1T6vIoTjRFuAA0FZ8XthP3xaf+
TrBFdplnXZoaw+b7894HM0+fZMw7qsuSy9msjPKasnLcAl4lC2jK16vItr5xw1LAIDQqfagasW0V
uIEq6iD8xv9v6FC8qgxlNIiq3IAVROL8aAkGAwW6t9RxYL7yJoLG/P2ZkZPHXg00HszSfiHve01O
mAKbii3NcFShCn5dhK3z/LxtXo1KbtXU9ZTwi76Aob7UBxBLo01MbONZzxdLi6IhLeZDyUfd8ktg
fioCP4nWIdcvqZt/407MDmbGbPpWAR7MrxLS/f7ItPyUD0GSjv4PxENIUydLUg0hC7Erkp8457tG
Dn8zbXYRc2QVVOKrYaBQDXwz0qdT1X4yv/j1fy9Ob6+d3dzkr9jgqPUXswg/Ol8w/oedTtoa53y+
rJBm862uhaxhjEOf/yKBfYIZ09Aongh8+jidqOwl5/mxTG5Ay0+5rpmTazEXfYzmYwdIrmgdvJXt
L9H3scpjgINr5eEydUac3SusH7wnuZRtQwr8mN1dgPgOpTFPfCWhX4L4pqAU+N/P4fs+bYtl9OQ2
EqiJsVmqhjnJl/iWfZNVtKnflfm/D0uludsNzD5k4nbYTrWQHAkgNsKMAmO2qHVsPMZkRo9GUban
H6/k8VoFEWKHEIg9Xa+FkpSrF0MwPj6rZpLKs7gq185rBXzNE9WEu3XJWdIgQSUAuytVzt4hsxVa
n4E4Pm+RDEV3CgCkTeByRjSu43q5r/aelOuFy5Pc8GRfqt+hRIDAM2rr0dkpTM7wG1jP29P7niwG
2a/bLBBuDNcKjGxsPOzkBoWv1mpruXU90tjmq7Gc3w5hiMtBJ4dOkH42VOOcMnkMVsOf9/tBMf3/
yO8SnSX6bW3j9Tzm4vjFtHjtzndZjMsbQydVkr8r+UdOGq7jx/90RfWb1tXORLqaI1YqgvMGp4M9
DhsDAcTgs6RnXbLz98DX4kf/62UjXgZmaV2Sj6X8+d3wboxY2VTuBPdveKfN5AVULuwJDJjpv9V1
6XzodsIx/uBzFPEoe+t60KEA8pwHz2F08LtWWyvkKHQxVE2q8mYi1Q+2lDAfj5JTcC3YYxTOhJHA
c7HXP+boOkNWK/Rbx6xfDgwbl4dr8qDrQo7qBPmhbCE9QLRP0MS1SEpXkS9oc+w8YsEWkZPW7YOo
0SQ1kl7CI7nS2RjQPKeR86GCP9bPKuJl0iuXvsPu1SrPz1atwb3hGkLMmeMAcR93eBxzYvfLPuJY
bHdfIw/hqVx2G/QCSnu7M0wg/wwigukejxa3ash1bfmtMwxx7uCI2LOCg7Wq//6QLwLvapoGHysE
QVBE2lMNUDDefQ2hfAoW9W/QdTTO/tSc9j/8l4TKooFJE9GpggbmMUSnyZOOWWg/MHFRLU/8eWhE
LcJp4ZV8h2cXzIHq5dnJTUfkSGd58Gfjrw/VJp71GhteDDh01tBcV6UsgD59nJjyGUrG6iH3Vuir
/GsNXDa/mTijCEA1YQ3dZ4O2lAABQI/j7v6cgStsm+2D4iqDVR7pK7725m+BORsVx9QpCjyuKIOv
ZWCVcGxFMP4A+X4OSsgIYrFUUn4MwLmywYodzz6XCbS8b8/4EpqBxFdS0q+JiHGVbhKHCISGZHmQ
N6pruWJjWzwBOWuZxBrdAkrlehbcleyCiQ9OGaSYfYbuHHGlzYGe4+9Js693u+XFFR4rvH9q405d
HjXT6gB5iix4tm6w9g+0ZxY9uSes+Dlcv78Z8mAOqRzOo4+Dsw6fYhJh9pryQETwNMO+H6c+8NQB
BPG1KPz1yc0S1sAdTLoGVXc4FUGrVjFZBl54PuRyE+rWRIAmg3CwayxHV/xEfpmO64XMq/yxmjkt
wNK0+UeNQeDvxo0C3PPe1zqDLG64i/lNoCk67uJZ8++msVNuM51fyauK5hV5TxOefAdRN3GckaMQ
NyAQikY63iI4BWw2i3n3+LyJXFKynOtVd8SZa0nRYi2yF8CEXagPx0Cd8Xe56GeImJ0LDAbec3C7
sbmus8ZbVVCfV4i9104rbJp8pZr6Gt41ivPLv3MEp4Tdemag+T5/w9OJrIBQBFGV8R3Mezib8YVg
4N9j/hWJ5vwu7JM+Cy+pr0slhebTTQB6/sShaQFr/tjOkT9Zuq/zo/T1JDHEqdfJJnA/mPBGbxkJ
rQkGxQMIYBYFDEWc7wUPQYcWopEVnw6xdyWGKa7i/FyimT9pUAF4PWkbqskyv2mz9EMABS7YfLtW
umFBODaUPQETGzFkEeYCMtLaW5dPq+iv8lCLsMw5bL5RNX7sK8eVLdAxrVxzrjd4mtwHaG9NCTI4
LhZlQpq4aFtz2bIAe9Uy3+j9K8gvQSGDu4UFDFNrNZeUnNhi8X5/qLeDyo9L+KaC/191y62ze93v
CpGlWdufgSrbVG7Aa+Df9OtBhy+zq6lPvtf3ylH0vzqmtWqGZ7f88IsrSTD4gewvW31WUkIr7Aft
PeaMak0IVBLPz3aZ5HJ19czifFGMBwhIGdhdjxtv0au41A9z9LTtNLBbhaTzg5mqnX4QLbOuZ4WO
BBY91WrJHb/tLzYPtOfbNMfFhKBEvuVUhYNt10NwlXd0ITf7evawhj8QF3Kl9dd0iKKH64NUroUJ
ZiUlnlWwPl0XNtWB6WU1afzN3TBCDkMuabuTgCyTmaMNQmIWhNEr6ufcA15LPmftCy7gcmRDlevL
bkdyDfjfhFm9N+7qmIOfOjlGqMyK6bhpaVulEGVOa+mDJsEo8dcpRIIKNkxA8ddRLT+vSS0FSG6w
zqs5Je7RFNRRONV/yNbRDfxufUjEP7/OFJYTQEV2HBV4NDJa+9IVQgV62VniUijaWSvU1gCMzHHT
XwgVQWMjQgN0h/5nMycYox3S+gq2DLqo9sg6iv7hpDSXIUrsTUifiCpuS+jMfPoNpUCtaTZDo04x
Az4QYZ4B5z/6Fkyp5H3zxJwNzuR5j101tIuBrYT1qtWvuYLLnDEvEBFIMOzhuQ+KQtm4vxa4Gwvc
2jQgUmqvW1xwpOXAeyclM2zU90RKvFTf7CNaeRgcd5rZtjEXtE1iCJKoQaFJry50lyOYJFzsEoe2
BWFXj2eyCrDRwMM99zIChNihnD27J2IyyoFhSoqi4IqsNj9nQYRdz779StfTCuBsHEkSaXvAcwbr
yXo2sU4gMwBsaz2ZDrITCEFnbkyq9je0EjkcxTV0FIrHjO4UTl4i1aFIVAIiUDyw392RhPpMyzx9
mNhburJpdojbo+K0sDVCYWxgR5x8znwuxRnbsvU9Eo4Xfh1PI5KAc1BGH2U2nT4OL9ig9kNsGvhL
F2Z9eFKhif26g1S45y6AvDeeJJHGTD8pnsEx1OrTTElJrJu2TOiXrcztFtcPO9JsweCzGtZiXn5j
DRIC3/hXXIo2d6lny/2dOgjDe+fCcBaqKCcheXwTiA+eKyujgIxoIe1pEDXfhft4p5c+js1TcMW+
m/4asYX0vV1AUtKe3bdLPnZVNLbmatAr0QPQ9sPgW5AWZlyC/SW+GVuvSFhmiJcBuXZqmkuYfl+/
+1YyNRrGIjWJIgEPTOwSEF3etHjUcu9Q45UtpiIBQdwqpD/EzGLRs7DsfcbyKn3vv42bM93n+BPO
8KdU+jeUNMmPYPO3lYJvjw5vDjKIf07/qKlrwOtOw4u8TlwWuxCTg3OoPMaFBIT/UOEsIxgLhNiP
fg7lRBiucefk9/GK8RT/EuzyavmIR0J05CIcGS44U9ahspY5TX5NlnZ0F0vz9eazpTwCvFT7rVjm
PXvk+PQkhPITzsHcL9I6yLWA6KHImBCGrTkhDW/AcJ7A7JjvZx0zJplEPmRg7LBGXWHQKNZQI8zv
P2eVG1lB2bVm9KeSxpMd0KT0b+GEvDf0e3/0dsK7CiRJ8P2LIMxSIlan7xdNMd4J7WvToUhKUSir
Qpv7Qy0hORpU6ohUY6y8fFehuEw5s0U7r7dcMjQYofrnLfrYq5HTe1ew/o+WSsT68rYNpkmFc5T7
/Rgo4icDdKU2HCnX1KuBZdR7TSrqNFX2U35rO4ulywfGIkNDKb4MsuyRWB+/QnmFKf8A620XLnwG
W3jcqOpfrPgEpZygiPlOCCcFvLobrleraiQX3ef2tQd/qN56cBd3w6E9Ak178Kkd+PQF2szwWtDM
UY1rjnFGJsWYBsJOFmwTw54bGJ0EOCSa8QHyxUQEq77pnPk13ZdoMsswt8aLk/ewIKHzyx7Q9mAr
AAkLXJDYMY7Zsnwg947X/X7wCC4Jv86L9bzwSdPDBFij2Ej0znA/vtfFiK1z47fq8/rmCB4POdQ2
uFmkjPlTcWAq8AQgFGB0+sDFFPMabHguf2XnmaZdAw2c7UvAWIigwCArtytkdg4bYY9qVUYxw62w
7nHIBaWFDL2hFrSoQfPumLkboL+xnKl1YA3ccAYNifqS4D8wahvRiN+Y+Neort0AisXezFpgsG53
3D8I6VWsJcS49BrvNI6/kP7h3R9+uJtOCacVPI/jfQXATU8o7bO0F7qXBFZDS+z6ubs3ri7+SnNP
vPOnloS1GQO4bAQVbEEk8vJ/iZTQvg/brPTkjvi6YnmxGn5fxgV5r7eQfz/MmOZi1d47R7Qw1Ypw
txsEbEwXezOY3NG1Wmww8VNhivy0zI3rfIWCOxCo5ni546ToHG5wfvE85Le9LS2vVea3fLcXeIhv
pl6uq2y54qzaiGd9HvARvPb9odCapSlNaD8sDG5LAdPQxMq1ycxZkJikguG4OgLtuR9iMfNwoUmw
ONtUvOivuRKCbidZmXRzjK2/2wLbYGhHA/cDDnaEthZQ6MK8belGJP9D+fx5E1doPeBcuf3ha389
CJjOjZ39ykRTQuj6Kmhy+qU63A9ZOCFmIxeZR22hX26nayy8DsdbY2RFR0VYhu6o4uqT5zJbDcsW
pl1RjtkEuzs1dEthVmxy+9wEmfa3WrAvGHkIBJzIhATqRZ/j0+TQxBojPoicZDSoig8W8rdhpbtb
tMPY0W1VjfQNGHospJwv0M16IompqAcVfvx5A0WBKyW3/X5hxzGVBEDhh0W6xm4rUFjFeCVIOP+A
cqbl62olfdLTIsds7dq3oCIluwcHSmgbEgMOn+YD3nVVQoouIOMmgU/rSohIrN3jJsH0tICjg5dr
yheKJZQtrcs+ihNgmxwl7ITGdXr0+V0VocdysXkcPX+MTTAJjbbE/z6FaIyi60lFWifSZW2zVMpD
Pn01HRKmdCL5sU17F5o6WvRquTUrgQr2HpOr/RS9Hm5xyFulJk8Xn1C7IeSVB8w06NSDgHmADvsO
whlYy4LS0FXvs0QdaFvRFpbig+P+mcSsP619S5/a0qot+FrfzNKFrEiAox3bMQiiEXTWySzhWKzJ
6WJim5bhjIpStXeJkasJ+mkr1QhT+lG0ncrPYDujc6eUNzYWvP+0iO81qoQxOXYF8cg/9/QvVD+b
ZI4cgYhCI2DNuEF3wW+biwEEukPFmD5hWISW/ZMrFwWliec/SfgnAHvmlZ4fUa54khB2HUoYX5zD
BqNcjl9t5IIHBcvNJ2AcNZGr6SPmsoth5GpCmnbIdqLVxrezUfHqq1hSQ96LKl+Zx/LL4E8UbAv/
WNkdV4YupvP9mb0RD0tG2UJK8wIOhohJ1O6Kzn69NOFnYT4rJTWffR00/1DyQ886PhmW0q8Epqq6
2JXlgk8+EmOca0o4HDv5CFegxoHGdM7DN9AfLAWqRBmQ9qKmQK392B8mrl5r5RkxyPzlesjHEyYH
wM2DtWVtvVk6neCLbAP+mgUe37f9ofk3e3foj/Xd/Gc6dJ56uD1bjpj4xnRcXEHlHQiXNe3qzCKY
hmeiZHQBfeh8Hd69WDD3fQ30btITGQF04JR/CHQF9lhwt+2x9YrlbKg0w/Ju3n7kKWYO+9dvz77e
gJVF7AZTbaji2pX+Vv5Vpm6ypi/48NlpuMbMa0UetC4ymxbrR1fTJF/YuUHLsb8CBEo1XViHxQNm
i9ZV4kZ7TLgY8za219QAEdlM8RhAR2esO3PD6SvvFUc08zQQEIwCx6sf2eHTVHhih8fFqTOx2/Ns
RLVdz/7CPpHexAy/ylsknyC5G1jrLO2kQTwZHXvo8PTwKLGeEMKF6sG2FVYnt83s5bxHPDGWvjuo
Fr3R0OcIlo5w0AoJljit3vjH2o2gddCe2HvFBzwNGFKGx0wXcHcQA4wme2ADRMZVE1HCCPWg9+WJ
p6EKbSg/KTRn7O2gReXh6N2sS4kRH8zEolsn1Spvk+Iueitt5mjZS5N8bqO57Q2lVj7RL7D9Jjc8
y5iExqfMhz9so584yeS57z2x72Lh9g61/10MsmSwNJLpPKqM2xuWpKoGRBBTQociJYgzkrnQd/04
rN8OBhR3iPhmv2RWZCJdELAwU0uH75x5Ip/oNfsEXq+UHpcpnntsD+xLe5ygFww+nSjzTWmiU8X/
7xJku+W/WIRDcf9vHVKygIECZ2nY4qePWwAqBU9vrQsLZ0whj1SZiJmf0YRrAWtxWMZdoVyks5LH
rILGPN6t7SKuYj6LsZKuNOFbb09SlVGu9F54ZoQ4e0TMtiXtTm3BzQzxuZKlqWcJ4N65W+FQgkge
G3Bu+ODTE77JwRQvW+Th5WjpcCr3o3jsAXll9egQ9s3XXzB/bxRLufxn5TsZ8Kqx16u7pZn7j6Cq
WkIVeLX0wmCSprYO3y3LHYmqtfpnJDzoZR96eWJhuM9jXQs5chzCEJZi2g0w6q6DksbofzH6pmDR
NY/5C/+nLBXqlfudjjHjzGP8dy5jVxwRQqIAXQFF55PQiTunQf1XtJttLkEuMe2p+ju5DzPzHjaf
u/cEenKnY9c+u/2DTUI0JDkkc2/dgfmog51NQARgB4rdsYSxpEJbIl7u4etLXQevW8eF2wgJGlGG
v4qNHVDGMeFM3SKYHwS3RWkgYhU0CydlX/PnzGSHiXldeBxfjN4y3um79gFtqssLcwS2XgKhA+Vy
87dsqconxlFcg/EUvHlMQvuj9KKWbOy4u+73MAjC8gxK0+ET7zs2puJiLjzq9jGs+37PY1pVfpJo
2v7hp89VufyankF4C8mCJN3WfH3Iu+qGVKbBudyI1L7sjDzAn0GfIVFdNHZZZtPnaPfWJZBwyIc6
kr5yWXNTqjD5rch2z88Qkvp7Ai2JeILOABYEwuQ6R1ZXkufo8iRRSpliaCCnDMfJbcBbpOolthNT
8sb3j5x//cjlC4KLlOJ146epI92mFeyifEsG3T8X9pB5Szlb7kMF3g4HnRd1WFTuptkrPLuoWwbm
gMdR8hbBVbYbRfOB/AR719AlTzf1dzC9slsNF030I+XyYnuidX49/VQDTslqiBxKszVqHl6aN+ZB
PNOqkNq8mcG+5Anc/Qb4kjj3AY2gXazskTaZ58D/AGGT1f7HhczZq3/0ul0JZAjKAlmB3wVRHub4
UTAOLs1CHoXf5K0hUHkrkCioQc93mBwDBMpejH32yAysc7d49fl0V5qaZrtXjetnzN++kvi8Aa+2
dtgTD4Rzykw2OtXL8+DUcGejHPAFTiu9/CkP0yFd/jXq/gcvEAo8PLxb8UIwNOTckOxZgXHH7u4h
YDbkBrnfWZCI5OpVgCmHj/0LiuSb8eN+YNhdcOBFyr9WGgsMn5ReUcKE9+LU7OxqBj09JYHKyqi0
qysheT2UC1Ad37tSExdiTJbcYn3snCpNNi3wRKUZpOyLTQ88GmKmbUbFJS2a9yF6dQKBWkAAp/fS
J5MBZu9LenSWGHod1VUuRN4LUJ27b9JDuOhW4s/LydUogpaTtQ2alM2+tvXOUf+IwaGme80k90sT
ac3Up2g7gzJyT1gkEyuLZWhK/aIFZnU0SsIa9/3JAgjvhjH3eidcrQaW3rUDYi+aBhSuO0omef+n
BD4/tRGSUxc4UAXvvWjJ548jk91v28FMmt0f9a3HBOE0+9tTfQ9A1greD87BXlS950JDhnWzMkSj
3SKHACTdt5E/E+4KKIm1HuiUxq9g6hkWTv7pu5tmM67sfq43BaZC849wUisRVMQvdCJTJKlEmc1t
h4uxZkmihjXZ8OQA8yqUnVQ5zoh1lFo44eXYVjm4wjOj4+mSOYyek0g1WJS9VJsRUCh4oIqYkPNp
fqIbl+ghP/mYAdur5G3crXBElFC14W5UpK1rJM97uapER+CTE8qu9GxajvBAzqvHjQJ4EPd3ADfh
nK9ncdA0Hs9RYXZb14bkjvAJWtE0ylFmA8tX33nqbV/vTKzJ+WVh3gpHoUtV6hMyy/U+cZ/qJTbc
2GnYXcZX+vz5qJI/498I4+ZoZZHHIdPJXj9kJrFITurMSrnFBtOJhrgYACzsaZI7YtoT2EfeZST2
wlWO9loBP0vAdpFrgJAMiSzw/0NpZ9+8fR+4GSSugja2HRaiA3jFc4Vp6rX+0eRpocm75GCGS2y/
s2n+yiL7SMmx99UVBvDlAlFRaciImGS7X1cdhx1fXCaf0Wfjzfa/aC141Mp/NKBTmD9j/wyy05AE
5ZRlLjbIIGEYcNmwhJCYczybI2lOShjrs3bsd3DPBlqMTfxQXJW7UhFnI+MPq61wUSvyoyUDJ7uL
LJGctvmE/w7vSz6f1w0jRv7bfhVT9I3M1XBU6LaOHr0v7Jo2XLSU9SfV+nngZtgWPU4Nv2nfX1r+
i7h+eQETjZu4VCQLa4yzzoAPRlwxKR1Bx6H46KdjyIKYvvhW1eoL36LNJScWBlqBfe3XOQVfWxYD
PsrgYsFXcrFb9CKMNh7OIlvCNO2sunL6uWWScIlyH6CTk/MM+dA5MQnZcBpuk//rDnX5MqmXTp7m
AdC+mQ6J15sKf30jmEluZq9f0omvG4usowL+hnCNpTUjfhpJibz00mTPSI+6c8cJLTgptSygUvX9
B6QkyHBBDNVRB8bwQQ0roZ//EvCSPvL5JD1VlWpT3nubmsaG1Y8NtafmwEMmln1eRgxGnP97c/8Q
U0/BuDEJz7FaShjX5sa7TU0OcphLvmCQiIOmi2RF4EsWseHw18Y4gk8dBAST84D/BAY2Dw4bgFq4
l9o673ogy8ltz51jVVNerHcWW2cJiqSqzKQRYp6V5WyP/LP0j2c/XhhmguY8jax7uLuqqzzPo2j4
QwA5bDpmqOrC2iXcFfcDbFF1hh2F37V2cQOyFOutBCTbPHEZx/2dyqvXx/0JFT4iGZrdOwrTgeN9
JGXxwKEQiwRFbvyMplsmIvGewdoNviD32p6bJpy2uJXELmS2So+6AYgD6jlkni5PwsPSOTGE7JV8
rJ6h4hAA4Yn+02jDJhCCAtX9kEnm9wj9g58IFNV1vcE11/RgLHifEGAa0SGS3jY11hdgtkKgZAUG
JSmQVhoE3db+d8OGXw0WwBiWNlw57yLTFmFlr6m1MaYZ+bx0Ca6vCillGLZDpUwjSyXMm0M2QN9V
ulNhw2yp47EFIIk1sUdnxeARegdpdDSrWdWvKfr972NAyCNEyS95NA0SMFWY8dzHhHC6vGR0a1nd
MMrVYr6rdCFT4MuFGQpCDTKsYMHl+TnbRNZnSwvXEVNirJW/lbIsWyHt8QFfT57wfI8MGQ6HyZwq
J3pEwPbK+sRIuULBTvW4O06sB161ZwsSYTnUPDJc9HQ5ghiiAovz2qrrnJo6LsGTDsxKsVCUswIJ
e6iSXPxg0Hsf/5zpIVo41K4oHYeu+qLIdzgelQJWkQQ0BqzhWARJT1WcadBjVQ1jZo1BhTwT6K9V
QIV/kI0ahHLIVgrsaN/4Ew3ENDrVwgXD1dj7SKzDalj9SLtjOGjGWkS7V9FBK+CfJyEqleIItkEN
7XZS9H3wsdS0oM2tzlaH761ASss/Wv+Q7tu5ymOmuG0SVbgi2YjaX0gbjLOnVRkTOnGdt2TUE3cU
7k7uigilkOeZw+Pai8auiVdqtVPP7vQ2eXYobLxltapSWeiayrR6Y7Awt+pAtISg+J7RkF1pNkR4
o9suQug+gzGJi8tW+ZPJLGAe0IIOwqiVVPObs11Ar6DpUs2kQ4i3E+uLLGyvohLwZfMANM9ocH1c
UhFN0EwJxS/Ry63FLPBnP2XyqdRyjZRVZwTAOO8drnQiEysDjej4HM6ScTNZNW+jK7epCDBKm5dY
b2sQTV4l3sK+YFs4NfdgAZDrONAFvYQCW5bxQFdyqt4+2yfcwsdq+/AOSkeiyLs+fTOKVXHpUj6+
QeYALAyhLQvtIDEEUkdL3YbR1GR27pwPZBqcEfVBjdqEtMwfACXYtuKhQ5uMGziYlKEyssj7nQwI
wsMQLRfsDfgJrMROH8OG63NLIahsKbNflXFyh9cbnC2y1dSsLTiR3FbLF/A6tw6iUwMt2YftwVZ9
3vpsJcHTi+1xWm8urkgQ/6VcgpQFPkf4kYJ64ckECNDhvJV/KeQf5NSCZ7UymCAWG+fLP8e3aWkp
/dojuJEnmYriW0xXtD/Yy3NKdqaPiap8xsOniA9/b8sNCKg1IAirQD+TfwszWNI6mKeaPGavqxdm
Kj5pDobu3Jmtcl++MFurTSvP8h7JgRwLSAE40YKo6H3qp1u9ySdPk7jsMA2sCssi8rbM8Jb3/lzA
K67phCcEdWQsFiF8X9RSKWWmcb5MZ8K3DC8YK9H8Pxm5vXyuZSKKE60OieGPAPz1zADS8cwwTbzk
LLqvppYTMaIpGZCyBdR0iROXqrePpuMj0mk10Oq21J9FwqgYQI/CutcHaNRtY3AxMGL7RhfpVGKd
CKdf9hOm7hKq4/xtPCgrghew5aE7Bhgl0szGX40DzyZDkzVjA/2SlAy15qlz8fJ8Jpvrjmd+Rlfc
T2n8PVN315hdDjFX/l5PwKnVM1te8cbsHaK5BBdi/OWFwelv1q+YzKmYh9kx5+eSalE4juedrfII
xpMjIsNFmxZAqF8+gghb6DCgqSW9VXPYkA0LNNsK2slXnyc2D/YafhWFCYCoafcDednpOEDmPNIt
p3cLK69lyc0SGjYqGYCymSe9AxV7+SWREq7wa8NO1vnMIIwOVRs/UJ5CY+K6PlpMg0OvhBB9r6jW
mmZiocYM6xyDXi1ySz3+qjz+oiJAbD1xNxF+ccMEPSShCdl90Xz3dxMnr+Upon6DVDfgzxO5n9xM
7tFm9hjfNA+Gu7NqRL0DHabEUf3C02idVKyKGCN3wS5MD3EB++X3rbUh0EhoWIy6SxC+unhXSU7S
pv/aoJ6fNYEY+HdETDYd38qYg7dufLL9iUpNEEL6Dzq/8QHGwNT0aDuip1n4C41A5KuczWhlJf4r
HkMxn6hhdarafvMK8Bh44Vo6fMTzC1Fu0cz0wIl+F5eESFS5tlKGKkWuiqPSnJzSTHIQ5wpUFH7M
RL6YwGc0+oq69Vtv093tCsQV4kmxKLDPFlEIuHJUbhh25XbCAzx9YWLB14bklDIWKcIvxmml+vOY
tWV4nZWGrYKEgXOetnmnqM4plHAUEPWJKec7/meAPDnw44Kew/QXeKUg3lpLKcNrKDknD5TId8dx
NAHS0OZDlB/qeXQOwvPhWhsQ3YTYl5Ezpv4Zfsam9DjO2sjXuL40Y2ZLNs1UoOCk5f/8Az5GoDbc
Tx9kqc4NcUUce30DdTZYD1NsmxImH9dfRU0eEbmypTfwaf4PmmT+xx8AGuJ2/GGQehzdvRfwiodR
K9+Scwy+yxUUmPcmb8bhN1N5Vd7ks0OGrNYKM0UJp3ABikMZwhVaMqjrdevgeXPChSPqtZQBL37F
WXydr+h1DcTmhj9gLiK8+KR0MgfYpyYXifYNBikdRqxXZIjagf4KWGTOrSetvZ5c3/D2i7VocZFs
IkikV+6HqQe+8DQ/bH/BTQxcuPL8AQSYGCOtnWwZK9XDPfImS8twacbM/wgqhyvdaw/PLZla9ng2
YJMUMIX5CNVnfC6OHrZauJyHmvDHIVYquS2iISme2RnnKhGCrWITvJa7WpuGvWfTwUm/bjWVAcv+
hOcbfjNulZcQkqcP/0adfocxOM+qlrg/f00vfdfztKZDnY/nj0dAQT7QlCju2ht1tv6RzeAfuLM8
RFJew7eLYCw/Vfu2NEJ2FI/AgwfgkDNga1/EV45EEI6HQw6rnk0nm2rZMjbkrCKnGu6dQp/ZqXZx
xyj9uqvU4qBupftMMm8rryLzm5IydPQ95CQWZnRRrqioW/hSl8eHoevdGYHK2yl3pe2x40YimS+1
A7cps+oRiCPWCPM+E/XV6sicyxi2Bj/iAu63jPgi06pfgUYT3yCIZqZGWehNzMen5HMqKJ8UumzU
B/50umP4+LyfJ2R1jJcGMfyjQ+BQw2T4PVx4MxC8kM9FHKkmRaUg3gfhGHGTTSt8jZes5QtruwEm
I3qveP8g3gJm/zfuhK42wzoL4D17BokS5FM+JH6wF/SjTg1Jz/c8+8FLuh6uiz/c0jTbYtNKLa0a
H8uPOIOo2uANsIYL8dwgshpArnQ9Fy0Su7BoNoFeD5KjG0cTni7eINB6B54OXG2af/p01AmI2RDO
iGwjt4HzEvQ6mUYfD35Upr6C98bbNDmIe5wQry9wU+hBktXz0m1XWuK/O4AYsjirlSeuezhBXvte
+GN9CDf6OYbZIqn9oGRNl3DQ0eGD2D+JNDaj5hTZtyKrZDRMhBR/G68DsXg/K2ADDPai06InwZyl
MRZX7Dq/+i3IdxuKCnHzpp2nGPcZJ+it1AVWzM+IfpUWPAKyb6B6hV14IyPAFbhg94Ub7Al1sZHt
hC0hDjWtRUjAzL6w3JEC54pLMW6u9Nw9ACPEN3DENcZD1Q35f/gQfwtl41ebAQ/zpsn8k7p1ZugI
Bxgt/aQ8WbZCdA8boKkwkIb5NoUu3kvdbVDzL8swWMsgzw93W6dmdk2RgR5xkVFcdU59sKmkaq5i
MWm8hgfa+f0iZNCp4Q+R+IG7s4spef9QhWQMBm2FVnTELbpBKqKG4RMa2XWqHNcoy/Q1k+ddoGy2
ez+GpXwd/TAmfZWc4u5SSNcwNQ1bpOLFIOwIBawweKd6yeoLMuQLksUy5bctT29CTW/JLdBLFTHP
hyCbek+Gsv/9YS7RvhKvZYsVpd8iX0VByqAvv0ojSfxehQq4fmEPvq3BD43bQlY54D8vb+qKTuSj
ynfSBwszrqwNI7pAo1FMweqcgTKdjJmw1KH9aa8aWcHR8ilnKIJ1BcGE04ejC7KuHRXPaNkzCxoS
T5s+umfHclG3RLAfPFDn9OdJ7U500nG8NoN5AbLgqkQwEGCylnzJXYNizTbQeNc/0Wc6JPfbfVq+
o10LhuJEOmf8ak25I9HPnkjDAC70iJnyzJqYLUjXHjBknSkIwG6eeOyX3AhXDlFG2tyBIyVp5+dw
huPS073I53WxHRK5yk8iSBLu4cVLn+nNkRffaLtGTY+EULc2TmAJvRWttVKA2PX2xPSBUIP7Hvzt
oLpD3JMKjSWgZ8jqp1Wfd4R+ZRt9sobItjTalw8YywBa5w2H0qIFS+bDLAH4wbKivP4BJRUtUhLS
3nmpQ0jEW+TbzgLtNHXgBiQFYr9lTUb+kf83CuON2R+vfsxHslIXNEXWR9eN4LMlo/SUAOGeji3r
ekKxGA9GtKBOm1waScaWAjoU7v7RlOka3+UmbfYLJWWhoQ9SjEqrQR5Ps16OwdK8u77irS4aFzv+
yyX+GgnqEpgAEYGdPAflQ29H/JVOl8dllX/D1HEldDUlkDk5EOPqhpXG2BReFfuolcLKKRPtBObx
rv37JJXpwCEieuFR7PdWQUV/zY4Mc2h0rIRHNPAJnIEMhbfV7/0QagyZUyS7GNQkPHgMcI0aozHU
rfOhDsFWukmGogpwmn6oJEZPq6hksL0kiiRQTBVNQ/xfHrGgSmcm5/9zGfNgdRfigUP4ednBTQKC
8yPw2zbo/4N9nM8C1IQAIYLO+8/y/KgpU//3lwz+Y9SeujKPj9da1x5AkCw4DxXjk/nOwp8oH1Za
a+XZmTj8SdEvvxuQ7xkbEGZ281n0/agkHnMOLSobRMwa+HkcCjBIM4yincI9/+gFdVH5EOXF2vQT
S7G0LSPZ3Vvcin2rKhy/M1p1taBbTBFrF+Ryq9mev+9GO5DriYVAaAhL/NrIj/vgWpHmafXBM4kn
yNqCIh6aNJ3Aqpq0RPKHLyUMoa3U28lKgN9AeCUBCB3GPrAqw3rnAlrUpesD2eXQyYLWiyGdvvIo
2HKmR3A6a7cj3RXN5tkNjwq492zh+PCZ5CRcYgl4X3DHgrjkHUrtRt4gguKCRpICXSSPJHbLAWKd
KXB/NkPFkoJbJj94jZDtXeTxKD9B5NvJMnLWyyqcYoLQGOioSPiLiTZdyW1yf6MjoKYIkpEKQy7V
pVdO8SCZhjpnlQA35w+0+9pdxLidv9JjTyiG9psbWHtkbSkADEvs9S8VQhh6IWR8/n4B29pjuTkj
3btRJPgyZ88g7umDC2bWSgBOAs6MWCbPQ8ooI2HzFzYPueXmh9NxA26CYzkl0vsyCx6j9dQeYw7l
qIbN2AHYkMAonF4YhtKqIuFctw182/kqN77fd7HTWHOOjQlsXhckhPaM6TdrNxw/yQc9OZ68zz8j
lPTAx6ZwcqYBfD2SC0hF8v2kJtY6cwSwjRk6FU7g3TllmT4Ymlec5DaawQGo7UNNwEgV/fszGaV7
ZzNSZK4Jw7CUAXGgcflZkKjZvZiGc8/aM56G4J+OdrGceAnC29JG1byfVXp7Qzawh1MqdS52lBA+
d968KFJdAA0Qf+ZKzMzmb9PUyH77014MDxMhs3UZRcQD7huTfeyZbMdtsZRSIEAehiFFZPKdsjZ0
ArKS7XdGRXSIeItACC4mC+2ZPJCy7AYMoSdC4WlAJj+VNRQAgixPXnyV3SSzIlOGqdWjl+whjmmu
rK6MgMLNDNLKb1JxB95daNqxpJ3wBQizXUA+3wEYyJM3lRxbN9M7HnpVUaPjgFCimEx5HpY45dy6
7jy7/SiTHOc43aFhxxHjzuRJCxUXFjMizFezSsh24iQ0J7K2WHY+kJBkT5c4/CJwq/JgVnRCpLs5
PI+s/Ceq4M1sk5xDidsOh9joUI7He+UVj5NxUa/3M6gplEZUCNq6+ivbxTJykBwx29vHfqPxEB5k
eS7TzEZ2w0I3MpHJPr0jxjQyAZonBdHqUf3F50AIUTJts4Wp3kvJtGN8NVOWSJNI12CcLP7Ov8LZ
PwThIvRAoWZIlrT4lAcAOz8kAri+POywdytJdh0ugcgtFtqFNhKzIwsTkTedV7DPhp+XB9FjFrpS
wprCGrOGMGhlrYLRmD+J8OqW9gkmIJ+L9csKXIz+uZPaX0HdNjBSaroKFB44BIBXcFzRLFQs6ai/
t3T9HzoJbxcfzXef3vviifexdg+JD6ZXkH0dvy5o5Oqj4S1W4YYoTPEnMmOZ/QtqgnRU0kp9OMGC
74nonG3ap867DTxraqyn94xvSWlr50adCbwFhvClHD1TlA/Hr6f1heHdZ32tZWfoORWKLlE9mpoH
PN5jsUKMeiPDdnQs/FMThLZzthBj5h4XOzrGYCfGla+0YjZnOPpByvsyCNgCoFqB1HMlaJwENUGs
mon5gz2exY5bzbhUHSdrzGx1WguMIGVKxTGuEtZ7ZWJ/xDlEETDK4dbPUYjMka6U5qbiXsPfmOS+
pkq+ug85cVdHMYxRty/ADySHi7zC9MMpAjg+cnpELpl8ziodCIwtvCMQbNZ0Tbtvw7jM+jiJFMJA
jvk7IburoI25wDRRHHtTNEMGpwPP5ptdGFHjcqMDzHdDEqsyIeWPq3MTQi1t8v7RfGS4G3Pgy3JI
SyWtRkBsGnwqOwVkZ7ZyEkKOHmYBWoe5zetDjRSnTGoEz3J7EroFCUmXuTfBDQinqShqE8tVQsqQ
UZucWvRWxak1KC98o3pXgY4l5J9qNJF7dmOa8zcs2tj04/nDe7wov+GRAkNbWcKHeM6/4rz1nMos
VyJv3lvVRCil4qWEg3Eu/QWQnfIhD+LC7e7emzdGxRDKb2RO5ZqouDSg471ape3PERYJ4hmKY7D4
D8uu9/uu5BP1CkMqI4nmjGkSdlAtCsO/sZlSaWxZTM1DiblTvLvRah/7NhOSNOA+izqB62eb5nqA
Gi+3tGlz8lLAwzaW3nwugAW0npHe0hw5zxtfxVpERtHqHUbXEqckKFJKRdcs+aKeyHBYu8G0psV8
C/S8qBolxc/gGICWuBllTVfJBHkiLFO2IuB7xDWkZbCSYZqgWx7DXYsBVqUSeCkSB1/ZBVcx1cFJ
2j1la1jqECE26KvXBc/sR3/Hn7F1xOHsUjrzf8ZNJBt7tsTPjXDDSRU/prKU0L8dhI1oWWc1jiBC
mz6+MrxoHP6Yj8d9rAgPxPAad+Wy1faG/31KN0anXf9LFi2AzwE6pkzJ0ElsYrIOo2joYRvvP0c6
hB61azcr+3p5OBWS1CGs9sV1W759BmG9JO0gwtyJWn0YMKijJlDjkRCog0G7w76fSzPthqYmgSJD
6a6iNRwL7IdCKksgL0unR7hRJ3oOG6vI6Sr1OT6Qv6aGtTE+7he9cIXk4udAynXUm2+ujgCpaK1j
3jcg0JUJas+tYYBGT/fFbjtDzh85qvhmCOAEz42wGyJAJfsQMtjFgcndQ5br49SLwx4zjKuU06eR
hW32Q/SAE/3L7sCUhZJPdE1dvgpvy2Tv5wm1MVjPwh896KjZYcDYfil6zxuAFFCc1Uoo31XRCAB/
ov9zOU49q9AR7OPDxbrbPqVMr59/erAoUvi/k8UDzfDkPxyBsv1JDN2avmy/IFZP8Kb8gUYJ8g9V
Q99h13CM7GN0yEf0UEYnWpdKHjrOXZ/5EZHa/lPsTvs8la0xqf+xfG7N8eByr39E90mCZDOxs/ie
9iMceXMDVJsYbOn8UtqirNIUXkJGKtNiLT/kjqKRFA4JOF70Q0CUWcO7mJz/jmj1KS8PpcFhWc7f
sqBVQWEFaPj0E5buaizBzGOFpR7Tk0J5Qg2YcBVY7F2g+iatamACtIx+jXhFn594f1Jm0hqWed9P
fRNpiR0XBPTSPuE19EWkcyYjcR2k1Z4zJxFeHZATgVKraIcIHq8zGB555DXr06bUesSdJUcmMDaz
4V8LhefLNFF9iMjbZ21Gk+EdzWd7G+bmmCOoBn+/3aA+AFy5ZnmixfzOC1oOL6AUDUA+junPZ/HP
S2Yn6uDySQ9Q12g0bZOLDZGF3j6OvKyEDFgkSS+ePnfc0mGAaz8UZ0Ctzfa7xooZ5+zKezdL1jtv
RsU4CHeUdEvxMN8OJwqOJYkVe2AJnMxo4cYXCNvRI3Ww2hDCyvQJIeOC44NCTMGLBjac/9QE9EB0
nCAl56M10EbzX4N9PopOqJSAokt9iwbMxhlFgLQ55yk6LHC/xV3dcGJAWkzl9jlqA+ADX05cWTVF
EsLxaIESbogj4eJt+5KGFMVjR3o+yYSW1l2J1AEFs2qQnqX1ycSWfxvzCNs9WjGrB3CXOHMGb8w7
qfhyAlvvvIJiOFzntgmkV0n2IX0TrhzeaOvhGbd989i4i0pr9U9WlPSxqNGqqufthTXPlcTgsYsE
UMf5gGvikqhh5vqg5zZgBGc7rzRPsSub9ggsWy9/cFE9GrO8XVef3Tca0Fv+kGWJVVGsm7qElHIC
F0KepD6YlPMpu7ldhx2F1B1oDzr6Q69T8w8QgRA092DSe4zcln1cePLK4dvBzh51ZHZgcg+cGrw+
cpiEq1VROhR4tpR8PnUpHrYRtptI40lwSKx3vJAguPGYYeK8odVMDAwmK6ohe2vRpjsSZ3+IdxTy
LMMBnDiXEaYi+uXE7Y6XFhYgahZX14gV9Bj3cO/JYfH1GvjmYVVO1AWtXm47lzrzu2i6NEPzKukF
skOAVmVI3CjRvbl0gnuJI7xPmQHNNgXxiX7fWtofTl6tbxB9I27yKLJxI/TTNTdY1S3dlrQtXXj5
crgDB/KiD3KEvImurUkmMOQgaHDsVSwWmZOzs71fZj9VdKXk5xurgG2DmrGkuRQOLgQP7MH/ucAt
SR+D/+Fxmlke7PUqX+ZYldYtNcamkRJMHSwAHNLUHnjuH37OoTIm+7mZe6nTm/yM7hBNjjOXxNrk
eLPy1tQnhazuO7t22LlN1M/NOQUNuHNHF+L0uYYnULFrWdOcyRkzolyovmY1AU0fQWiLBjMGxD2x
c0QKVtsIm77gU4UuEalH9y439Rb36217FV81YK6G/HuEgJVBPfUAPElpsuFrpe4U74nKf8Vk+6ms
NbHWzCYqzAxMbO3CZ78KrRpZhgQL3biyDGTIwMF3YrNYE7his3FalMUNV9zFAML/1BEaOo94p9Hp
lpcEjJJktUrXM+LwRWmsSbpBVU2xv+woWteGfyWtJ1gkOKdMY2PNJscQNfF075VBbrf7pnQryS9v
Rkm+dKDG3sPyWAK7hyvfZ/nEzzF6WF2d7dHnXjQbUAcqQY574d17gThIpAf6aHhfT6jJRbSGuqAE
cRplJZpt6ffM2EEF0ULGURPxYzpI9sxEHrHVvf3S560ZfscLDA0+2DTJu+D6WuX19BXnaK8uuNCd
/6nGEfBaMdGQLw/k6BpuUgu0aN0OktqiqroAh848OxHvOIoj2ueLB8ilxP049LzSo4rptTHaQK35
odI8vpZDBQRqTJ1IYjr1HmwYlDIDwsT9L9KJ0ZQIhplydhWunI0RuyedMFeyDRdF73SfdfMycgxo
mVo88CLwLJiHwj7JWdEH/IEPRHliQv6Zt/B7oUkG5QutvfFzV4A4rr+7sAbBfK6kMjJsYzkxDujh
L3hiqavNOzQ4PvXDNLXWmy1XcfAkeORR4RRGzsdony2FMdLpSJIfo8og1gadbwmYrH2BWkTlfN+6
7KPHr38lqkVXwjbs9hUCP9xUNpTl+E9WvjdVfgKLf4LoC4SJYru3G3p8f7CQuv5ERchrVg4Rr+jE
eNulAx2NCaq8bGy6bUa2KEa8PTF7hjMtJOLjnelT8dyZR/WC9O+mK3affihP1WRngnsuRrmjoTbR
/faKOZKRo4jhHm9kjSky7jS+IDYEIYXZTu42kmQKTvr/CO1dKwBZzkorrh9JAF75zSyyaYhLL8lG
6EiymTH32IJid9POEzxH8mPrMcq738C47XiAbBDbyDj3hQDpkzrcoMx4hlKkzfwUMMXDvqP8XCM/
Nsuc1TULHVjDlqeVRCXZPqOmyCJHsFVcdx/7KdlSa4Pu0r1BDqv6T15e83VCM4RcF0cw+4guLp/+
0Bwhxkc7SQOYjFN3WEfCLpz/1ECNyI7JVSnyS+ngNp7/R1DBH0ekfKr01QFXNNqo9dsUPxoFfmUs
xrm2XV7RxrjXPFPRKJ/S3yl1QMRdiLIZ1i6WnLhCchjEsunbGSy6ZJDfKzA3WMmNM4wudQrjT4Ki
QRWQOKOGyB0smXEaZ4RwVkJHqO1kjxmgwmME1rSc4eUkZKSqUBHzvJIA9lybBEr+tAKkYCNP6bcR
KijNaJw2ir1SX9Kpcb3GuhTFXZQ1wmCrsFZSFbfpDsZ7Nl2+QUU2GcFmCBSvnTO7RufdfJ6jW2s3
dN9XNarHc2Fverw4UuwQS0c4v4e5pTCjWwjuDuaS2I1JVp08ubk8AkiZmFT+/aUaqhvEf/twuac7
q23bSFUy1p7bPG1jgyKN9kJbswaSde65wKmcdnEON+3ahblcCol51RaOKPnImzGRYeXE6C+78bFe
fMpzAT1wNWM5Soc7eut6PTEYi8qDTpFgH54xWWzTaGETR99SqDOtEgoXwigUMq73ihP1HeMG37+t
8Ek80GrPwPnmP8IHH6JNIG9yyz/rHbs2yHMAJUXpVbdTkz5acJRxWxAmLRl6WdWizRLa8sXPswBJ
WpTDDexkx6W5UcEFC05b0WW5mWiQiCswMBDgLK9lQG/dvoHNw7to+HmVjrJdo+KSNppLjUYAEUc1
hOTWnsSblIaTca3MkJlqYJF0BANM+bWSd8DiHvWuwwdYZQJwPHM9bRgE5Y/brl2ewX0VKf8i0J6T
6sTj0uU3kJiR6HVgVuiC4q8V8qw0dyvrdGawdTcK+i1NfaPz3VI+j0NbK0c1R6YhVQ3BmqeBAzh1
fRcoT+cnH36eY1BS5tdic/5vk15ayycU4EZpS/s+imVfAVF1mbGJ9GMKAWr7NM8nSG4UfHb2OKFb
UeRVafx6tnWQW9na8rHlQM/3KR9ptygP2XfYveoTkG3nvU7NyOrZT1lpPN4JldMlBo8C8WKFmS5j
ow3pfvgYLZ5KwJwbpKNPdT6BcBIAkTqpP/73hI2cvHq7dRu9bc0ESIdST8Dicsowi/h2qhgPyy9I
PXgFcka2P6qpB7xITq8PQJeukHvrijPFF7mrkTnKn04aPH32EgJu6dKZTpaXdV+n8z7PV7aFhH6G
shxmdeLjIVmcseNNnFH1BAYPKXplm3Q1FiS6Ys5USEOeqYZiPnDzP2yaJvsSAf7JdvhmgHV9fv8y
DoWWFHF4V7er3huWWIEy+Ptlh3bEAakP5Xke09D0lVHb/rhCi9T7qZ55E1tYE2RhIkLcBG/TmSXi
EY5t3m0BJ3DwOoUZ8+/+JvuPB+uCO2yopI8rLcl9Q6V6p0Em59tC/a5Bga+NipFit6r7YKomunNZ
+DG05x/x4pMJOkFgALQ+NfJOZHj+k9L/OnSmQYeqVrAZAWTGGKQz1goh4NtDHP2RsaJebxL62SyR
q0J//VBOp7b0Uv5Jo7J5yIe2M73lQcCG08YbrveLegE4+YFxCKPjqA03i5N+TsZ9bDseeI6Jucpd
GlRNg9wh3s2ozcJcm3Xc6bR1k8/t2ODiV3dVnfTQH08GVdw1iz9+YRboRo/tncsF1SSg/SzSVnF+
rjXzgCZ/Tf6d8OAiaTZC0EvyW/CWuG5qKjbNDN75xTurYwO+3dlm36Q1YPnyGEQlyPaK1zVKXD/A
EUIBeNpPRHOhbFAOSkksLFyAnJleTr8UysuRNoQv0cWgEa97inJMvvZhPhNRTDSe3Af0QWtZYSj9
xPpRkc1JGXw6SDVKmm9rTcYyoHK/OScKBKKt6noJtRuqLgKxL2ihNWL7It3GRIbJbayl4KW2iZ79
CBTrj2GJypMyZwYp4duBLQCv9cQFf7SoUKxZEwEkdAhiglyjAUyIy0XfwGzOk8HFXnvNL4sWwkqU
dyt4EqjzWwbxF0uAAQZhYbgwxYTgnd9vyp11iZWc5QQqHiL0Huq5eva+NV/6afQCH4mAWVO+QyQp
mIu4UmMPlpSd7683p77jUr5gAW0LK37I6rU80+ugtRO4c/ifZ3+QBXgVW7fwI5R4xf5ZCPo8dTtS
p4QlleSx3q1iytWRxbCJPwkakzt9ItA5QdEP15gfE3hgYsH++hqT36Js/b7PPiGOcMH7YZKYmevf
+ZD8CaK58HrsUx5zA9NEzkg0WlJrHAX2w144SfvvZCdVKGPEYYHAmBV8nj8zwXnxgrODoYc6dMRt
3oArOVXqVHD8M7+MkN6Irvdnhao3tMfxmmr+nRIOnQu65iV3ntXjQSat2Wj+7WWn3BT22+ej1WQH
x/DOnpSP0fyZtCsvkkE1QE8NDOJhnRFOZnQPtH3mYc/3h23Lz/baCz+LAjHrYgnCIIOmfYS5NacF
Xq9oAINgEW71fuIbYDay1wt6hyRyyqoiaQr9IWay97pYoNOzKRnUD8XWrEssLIdv48qwUud3O2+G
W+QWAAyRo4Qcjz+PNYdHiSAkLHiLleAo5rTPMOi+DY2jwv5MwavKu+aRiNxLrCNgCYY8uoXW8ze3
2chCTI3SmmYytE8f2Vmstm2JWbncxeB0vHcMMT31FTHN6nI5A3sW6pUrDs2QBjCLavLGcvXRhThj
/UxNypk5RR0+MbLUt9+/InJ1J3KNw1UdrPTRZvEov0nFqgRbjXbOOXDAAP2q5Pl46DM8x15gKOMJ
95+EJWAnZfuk4KlmdnN4QUvMacUQAY6Csa7dSh1eqFrJnrEcEGnArHeqVkfd4/F//U1MfneGwEMi
aUBLnWZ+Xr8yFHkUIXurbfMHjHHM1ORXDMiUHOSDS8rVubI3T0cW9jJv9lZMQDeBItAf77lXqxVH
uqDigqcKen1cNZ2iYbWYO8YONhIktXzGYsVCXGjiTckfta3LxRVZGKbmLktg+Qr4qw7zRHN2+Gzv
8NfQK3Veu6LziRAn2VvD1H/gFisDogGQDVKrKZn7Ui6e77gms9G0AYY21CcupVzg2q3ZnEIvD7ST
xD05WNEB+s1wZLY/dfsdzyBIq7MppjX7knaToJ1w5aUovmpktp5xM8XiJeFuqYwmQDcYqpWwZNtA
cCQIEkPxBxgkVa2OniHVTZ/Dem+MWLNjnWRHtAZdxhzlwWHGZJwzFwgbXmfcjS2z0Y0QYZ0Ozb2z
Vzyr7FtPOdCvWuUJMf8jGvT4+xGVcIUBY4gQeNC78Vbz/mkB9WMOF2OjoB66yzeU26Y3/G2/v8Nd
kXDXmvmAECYyH7NGWC67DWjGc1d+7jV0N9Vi+/1QsoYgv2ykk9cX1yWpdzX66UJCZbGvIlg7sIdN
sv2jv7D4KO/cajJjZ1KdKgj+PvKiop1aOlGd6T8tEDAOutR3bgAq24VSRPQ8TQKCix4P2Jv3Gg3E
DRZW7dE0zPJz6tddTBu3BOIbjGLTWKhTkWmSAHRDjIsopxkSMn8f84n6s6NomVhnxl5vfXnSHE09
fuEaD+HEe5ZtEj1pT4zSBL9+/t+xCNasUO0jAaz6ddL8rZwufkGVoC84Kx6f3qU877kY3NjtsSQO
sAtaOKJzt385XHIqYvFOUDxIMfr6+tHKMMTk9G207Jhw1ULVvoqaHgAsowi+G1p3FdT3FdLJ3tMM
LkIiy68FiQ8IuRIhP1mcdjPjLjn24nk6qWLUnX9/c1LrUezz1cRyA0xSeIYdbgCKEb0XOKjaeBw9
VVIRiURK8FW26nI86WxDytcGRH4a3MawtTpMzsFGJea6CcEqMUSfB/qBWGQFLuY1vgyeqiwy8ysv
mnMhYlSN+bmJ9gC7YccnhESMYJy9vg5hksxEaocxxZdgSiNPDy6GZIlubsbbsR1qZXdm92FH4vRU
2nBuCvUW98bkiW0PAqx+lZ3SWyham0CdKH5gZ/F9ZEoiz9gfvaMG4ZeYdOcHUyAmHP9XhGPR99sO
2KtbYeoJ2ZvxD2IDwRMMMLbMUxHkAEJOMjKNOw1mN67N/nZuDXFGoUzbKwH6YENDvTNL0SjkrKzY
xeg1wCfCFLNns2y+7s09WjQYjTkh/LxsU8ak80nkZUG6vGc3ibiuOATkxIq8dCyMC+zjhIc7UVmx
UFVOBk/fVZ5iTtsbojmNVzqo9lensCRogFU6N0Q4U57nrHqnFGQi2ip+rppynkmWTjvJcZafP2Kk
41ZiAVgsggaVv9ZgzS2xGRck8FJmaJ/2ukCYWEXTZ4h0i8nwaobIch9DIxKCG2odxZXI81dJivNv
P7j6EhL6mT++qJyRmFgMC0wxZ2+DcCFZvEkLIxgqe1DTIwWwFQpsBkNLcIqtib3X76+KQFguYNZi
ENYPKCnmaB2fyyx3GYiKVknQE6bo5mYGxWK7d3e2rHRVysM2SMcXUhJdEambg7hjpaeuQya0UGgE
iPU96crR64Uk8+bAzVVbdOUtIPmxuzH1qi6zcJnP+8Xrcg/3k5baz1W1G635uaI0RVGSWpoybSUY
N/+wlPQ73ej867RiHkGedvUIscPb9OQhBgMDd1dU8zFJwpFuH1ZD9RtrTq88W1JJ2ZEBkqZSXS40
n+dQREep3xWykuL4IcJ4gN4bXYWiqufE6fHmgNV2niqErkZzsKZ3X7SYu3JNhsUZo6sbFjGjn8VX
ZMRE0eDCeHl/PHmKtyW8N6z0jB7yjB6DzX6bjQ5p29CzQNtibKsyUNZkVCLzFLJOD9Q5govT2oUA
V/gXnF+HOPCuoCJ7mRysOx3988ncCxP3V7Vmgh9JElluhbWCfDYnwSLOWvr38MqN03me4ROmLQ3T
1P40o+r0UM6Yq3VYR7toRm2aEJoINGay9o4Vk0+WQYMrlHV4ohhT9iGyrqcC2mr6PRGr0DZVcMVi
75ZLhGvqhOWybWblD0P4dN/c4WsFmg4hQRC6L6AP5LDD/xNzg3dFcHwsqtx0ZfuA5UPwTHe+um7w
Dx5iXETkxgy388RpkbwcOkoa44mcoMzxYkZDbjLh9tdfJ2lVrocPhttMegYuO1DF1ArWxHEsS+ZT
gIq9zMO4xDtdBw1lTtd+eCFW3ebmndTeE8w51b0P3725G2UorWM5CuiSAhQlC5aj6nz3YbUHBcKw
RKWs3w9IAyADF9XmP2M3jw28DA72XSldEsXyibQZVaBbs4D/mB2RxqIrcnWm3lKXFA+1imwPcj9f
kQX8qQEo5BwUU+ey9g1jnx6TIeSqVgXlrX0ECeoNoQlTGQsOaJNu8Q5hET9YYaycUjFNSBItnioy
Gayh7/cLQKUYWw1qLk/FWzr1LJVKMzNqNC8Gu/JE4IBtPGpX+DpivlmcsjziKABDIbofPmkZXvSY
0j4Kj7xbeyKNRHH5SI5onwtEIjznbFGM3HhljqEQbXYB6GT5DKrwZmXkzUl/FXynjIsJRQtfGnyW
5DFw4TVE2AHT7FLe1FIALX+GhhrneuJisAbny6O4zTZGDWvg0AZo++HuMSEu5BL5MG6t4czzUDut
gD/iPyQjqwXLBUjsxGklwvk8TF2BS7LfwFNYdi/Xi38OW5MMJF3uQQaDhJWGAWNBIPgLzZg9meAm
KgbmT3v3nk3wobWqgiU1Oa1s4+1y5wVXKHoEro3GXzTKMxE7Hc+X0i7il41EmIknjIhCSpwY1529
aNX0KLZDnIQCG7QIsqAoAgXGS4CeB/mQehBtKzvGz+DGPB9mDRODY8wtKGMaFGYESlTYZhmecy90
h/TY/vU35e5uT0h5wWgw+nyDjjl1sx5x132TC1HUzGOjXyjrVkiuIIMnfD5ARCOWR4Ii8BN/dXNy
APmGLG3x6jWW+M5NSHLRxo63vFLlehPeBMDMWHp1ECtpN60um9AyTpuEkPJ505njfiBWDZ8VzRoj
pB/QXHuvNjlLNRFDqAxGx4j/speKJnfAXbIrkKw/kEQMSwyfEL8EOtErJa0/+x8SeDlfp28xqgHs
5fud2T65Dz7xLcN1K4eBTIZIWXvh2NcgsGpliQossyfpfe40KMLhKpSUUD5F9w3daDueI9wMyOfY
LIPhGBiB24Uldi0jrfEk/6cvhsYuu5+UhpRob7SjfLx4L1OtmuOfLmW+PaGt0s7JJNmmGNzlpTsT
ioVcxMBebG6l7U/9g3JCPypS+St19hIl3yU6vJzVpSzQSq9Y3cuKwS649I44oOUYC1QOsgmYR5/s
ZvD9zl7PdHvA+tl7BltDORTt2I47vRj/47ikc9sfnL+RmDD5/LteeW1ECN+zjE0Kcc9Rr+YMyaZr
/W1hxChkIcU+Ln6qRu00QCHg8vda79S52agdMKS3pCPydKu5Sb8vT4HHmXc8qmXwXkM+NvWY9Bpy
Dy8/32HGEe4sy7alv+3F2I6eUSoXq9kNQBndZh2v15kOhE5c2OZZJ27mISamSqUSUYFJzu+B7v7t
50LX1N+IVxV6xpYuJpBAV9b3QxWki7FsJr98h44cas7fQ5iPzOogsYGmxBnQyL7NBfMoRe2VlX9q
uLDxafMhGdHGVRTf1xTMgf4MX+fIYqtQoxI672sjiM9fCdAs08buFE8Jthv+qDmTkjD10v5FaemN
sepZg3d8q6iMY0IQaSfMxKPn3o6mPria5h4+5eUDfuoyv0smvUibh8+ABDaVHAhIsOpzAldi96/x
ZDl7daDHmHf4iXUbOs8MbOqCUKdRdxxQHvavNbRKPneLaSUcvg2pxk9qqmDtZaOPasIgldWtSPpf
nkx7OuX0MP8BrEfb8nFuRXpM6krBSqp96lBSzn66ep7K9BLRVqvS7Vs6FtUi7m3dJTcqt4cyaz57
Rrs37tivMqpIsQX83XOS7YbEPwxBexm/vop6NapAr/FiZao7FBRTe81RuxHKroiR9g85dHt8PmWa
qqCJddVqX0cnuAnv5eXcz4vW7RpkWZ7Du51QTWCE2G1FkjbFy2CEQPL3YTYJ8z72rx013tRKEHgi
m1eLpj1dmithNQpalDLyw0+KaPU/5+kVsJZ1aCeiaETjRTJ5GdfJ2XpBt2yTsebifDUQBITiC4mT
717bc3juPiWC9xxChXIAOkDj9sMs4uxczSC5HO/ciqX9GIVBQeK97g0yvw8JTop/La6HsbvhKm6s
tjyo/tqpg7bhY8Vx+SXCPCpYVdHdJppUSMSn1dPqosuqcaAm9YCIMFvzuA9Yo54hzkGhq1pIs784
9StRvRtOuaQrU+rXG+aoIefBXZKbhJktGRSkyaS4zvUmfZlohhLaABNQI9TM2SBF0decoKOEsxUB
nMc+11fcsqS0c/0rOV/2lLt5fzr1D4IwlkWie/gsd51WtrBaFFgaKBO66VuBQVj8nVcF94bJPIYf
VfvVmSZgb3kWDTHPsbQezEWc1H3L6g8MrLvyYsdALuxJ2XoMmxzKsHiG8ppqN0BiYKx5foL6aUz1
Hz7BNgIEga7tZ1XBDOSZmcr447qejZnlZtKz02YsCaJrfl7ZxglcJ9bJlflbz2B4MBzGH/s23M+Y
IICmzFSEL9JoAuFoc8VrrmdSizP2lr2cIir4WPJOgfv40q4zQr4u2HYd7wymbsVdlKg5spuLrXJ6
hr6zoEVtBzZDkBbkQPnkLGT4TT9KDKgRndSMtkIV4If8UjqEYROx+PTLjEy26Lt1kBS62CMQzdS7
jdVd/s9EnCwn9suJMhd1AJ3U57DQObjUQDd2w6t9LEvghDw78LQsVEIcktOhlK7zSIP8nDQpCOLC
KdE9+GvPDXi46Opgn5G6nVYkMgBPVXNBEq+SYGosaE/G0jwcHASuLu+9UjX6B/sFe/C8x07dpE6z
kE1TRfxMo2fuYiuYv1uMWV2C0vLUvkDFv0XOKLxLIWHf7qVqZ7T7T4NVNpmGXl9oyLcVcjMgvkcG
AFLcpxGUeo03crphcE3U4V6jfeQME74AfAsQBqNJBKEs3JFA5KUinMkFs/vK1RCmun3lk4kI01t3
tRjqfWPSenFKYOxfL7aZr8YfQEQwRWL59WHp8+cfOImm6E6pYKKs0iTY7fRa9WGKGGnTL050wTRg
UHRlUlnzpNAG0QpJ6buYjbfdWH/iaIrBWt6gwQ9IfWQTXM7YxVi2nPYQU0a42b5LN6nkR6BQELAA
4kAzKMxzsaOnIDuiVc/Be1rhx0HNAEOtUxXBTuYwsT7QJzQGABTSd4gR3JnC7rEJgc0SlcRe6CeU
lSK5FrNA6Wd1nw6HBUEB/0z9EI77fmw/ncM/1VLTeMpujZkxPS6Taeq0DybgfSoebXPwC54ulKfb
dj3c8rzE2BHBsDBxwUuDGWO4nucfCY9yFck5p3KwebaA6roi0l/c5U0w/7x2QB3liTE+7iAvBwAK
ICBLEVF2GBG0HGdxoJKg5XxPkn9KpV7L6S5jRtPUqwkkkpM3NclXzDbNyj3VuAwqAQYlkQbZu1Z7
aZco1DQtj9jKJxw5BEbabRO5QD5afziMpJzBRt7P/Y5Ayd0V2nJN0R90xvfH1+W9nYBeqRrzbOU+
+HxPuru/OGSV9PScDn+KC9GmngXRO4QzFFuRXqRcVO1Bz+V2YBcIzJiMgX97BBUcUQtnOTl2MRhO
7PQuqiHsFcL+2qvTQ1TY4cGY0qJA1bGfk+xV116yG3MSK+B1L8DB7HmSnJeRZBk/BsoPHe6KjWbb
U2SKOGagnYE47Fh3/7pmry8OLjhvCkxIC/rMvKzt6YoLxSeDPZJrqMYlgbuOWGkRt4d68yoLVJtn
Xf5fsXswBgAbZXo9XE3oZJbgewqjwMIWNmjpWJneHmWfIUg3grtyyyjDUVfjJY2tD4CKpIHjuAcQ
44S3ZXR/diVuOsohKsmOHmMFtcBVB5240bw99dpmFKPQmTD0rgmyO9fUaQsC9buvvE2LMleLn5tr
4Q1XbXcP7FdKpodFXksciw/C9lcjBX32PUnq0amKtU5Kub4ZcaE42l9O7GK6UGLdGkNwYCieymI/
t1LJ5PtZ2txB3ityKMGl70merietCWmXD7R7sOjw8k6vMM5LW65yu96Clemw53uA98GHXFbVEiCc
fWTKPAGbKS9iTEUM/jmAKJk1QCAini7Ox7sBoMUERJnyG62yiXzW1/bUlBwPeQSjjxGOu1NwPMOi
v00cZmoFKmzf2yS1kFRt+sWJzXwPiEWv9nGVqxB+qIdtBlSx4K3PxZx4Or0zylIO3pclJ9IzqXkt
BHGlAB73X5qF1vhw4Tu4Zkfu8kyzgCBFMc/T4iNXwnege856O0k3b82KfbAmck/fjLGnhoHEqqPj
iOJ3w77pWVWLuuBcwf29x5CQS7tYtZK9pjdHp8sc7rvhOzsDwtJfTuVpLimPU2t6DipBu2m3e+u2
oahL0Q5ap2elsTXjbav0l40QAsUoYbg8yA3hVXKrDItKwdXWtlyLRxA3XShiqBMyvL47H+EH7Tmy
Uqh+rjZTUJ6V+jh/lrbrhMkOEFnNMSUquRxIt0bnqGGykNfk8ynGOibjeMBIAbni+CnxZB4bAQgz
bQ7a8TMN6xx1VlxIWcrEU1ufYoTVFZdOITVhtioyf9j98tXMHSwJkfTxASFiLcvaaX9Ktbi9Rfx5
MN8SR20jdh+qraPUBhRmKGRTHzjVUDPVAQpNPZYb7a4Pz0yscASkq6E3riyA5zt7yHoiV8zgNeZ9
+cBeqqQv8+lJIp5coe17JDiia+H3McIhXrsdcNiYtCjyJgjs2jeHIV7q6ZbAHZEMSkEnZUf8YoOx
7bF9Ri2hBhFQLNVZ+wqaN8Z+0m7lgdq17PGgNEpyAfJsck2Mkoi3TuhOPPNjErJ6Wiq7qVOMVVMM
Y0OSnwtwdilhSfU6WyXhjelqftNeypxLdWVjgxKvKE9Wsg2D+zXIAwM9kLi302VSvbB2tSHV8BU+
fgrcjsNGAN7ECmgipwF/zKjqgKOj93rNN29QZ0pZkrNReB4ytmTK7DsfsDb0vCtpFN6sZgoGnoLf
5rxNPFYAv9Tiu5mNp6DefQ0HRQupIo4HmILygssic9z0rMu8CN5AmOWGQkjERydtMxUy2xeTgBZW
r5ez49arS30BcgPMQ42SeLudbF5n4O19ai9qke6AlE/d0ldUD583674yJ/KRdHRLn0W5fHFAQMDj
0qj6T5GezxJk1LTBJDOnaftkdgM3O9P8aNdBcqSJMM5TG6yjgXKlFtflgS4b3xSBJoX6bIA3uRqW
KeoFyuvphnCIGwu0BFej1hMHV+5HCywM5rwtMMYJ0XpTABW+ybUHveeR2y4uRcBhhrDth68LgKDH
p07FEUUzPbpXnOz2qF9R5awuZ6XDtDdvSdcm9+nhN77ZtdRdy/RBbRa1TyeapLeNhhvCw8g0Ccco
lFiTWFH9bybQgfTG7tIAVidHP48pQXD/1Z/rvoKIc6ZuJc+eMEZTGuRxhZdGJLintgfgWdJ4SfEr
dy134tNjM/nTYMTVVSVdWfoRxbGk4xi6Dxh3jGVnHHuPjpQ0IICIQfEyx2EXKDAZ4P2pA3K8cjEH
5Xh0giayRSNtIHhuVihRHbhqdKznzEgPNDd+ds0WmsP/NQhE1yar5z/JF36QC0+yLSM6pG1eHNqs
pcKtUO0sJnL6DNrtoB8QL8znzKz0qvWXfQNeJ5wN440C1kz9X5QIGebSQgi/Wckt40rYu16WCkBV
RwIjpckkDLtq4nPjOB0wJX0zSEGiOuD+SwzuaE1cB6P/1zIkNnwdrx0xPX3NQHwQ9pIOsiNSgbcq
lzYM1jUNvPc7qeKe07BVewtizev+sW8RTQPmaB74mkGjFI1gS1OBUL2k2pUFQbwDsBvfieGnq3DQ
d/nNnJ43mzaapXRrGS+o0hAp5IYRczLj9PYJnWCKyLH7ZJ2I4XnyxMkorlxMLvbfQ48TF/ooUTj7
EwewnbBKEYR1wga03eH2dMgSF5TbVPtM9+ioUGqRut+LE7pOVUr6PhvzHd5UDFS2ACKlPe6TrnM1
a9B4JhEzAZX5p2+NDjxhtBMaUFoHk2nBzFE5o24AYTXQMolgQnikP6xB6or6vj7WzopxEzJceflF
SxKy/+o5AEDrGyrWuRVfoi/GcXGfZh35sPVNMTnfu18mKxYLzuxmMlVD8rkXobjISgm3T1+xYJdS
AeuhIeCErkLAIxMV4RqRqpDH2zUW0VpLWFtIdWvCNLfIcLlPyKIhVrdD0mnRUy6+GBTOPyLil2vH
WMmizzUOUjkUt2/NW9xEKFS47kO61T+pn1zPDPtNQTuhlkyn9sB0v0dAdB6GAm/QjTrIPKxop4p5
eIg/eNfsxk3rbE47qNnb3yPQGjrxQJbynoIDLzI9+LluRb7aa9ZO82MQ8wTOlfvJSOWpOROsy82a
XXceXFGrwWEwBV2QpTgXMUZg8E9aFAEpLNnCfqf/v4DKDKzlqilUIJKtPJV7bDcGYjoyej1abjhG
it720cbLGR8U5GkWtO5wKvyBdXU1uFWJllgNdBTIJAo2swON4ICCtS+egAPH/KazoWYuMDWdg1TX
rSaGckMW5XeQKTio4VvQrWibSTznKUJyLKZW1Kczarf1/UjrB28WSL6KsSs9aYW0Fyja6dlFegvv
K7NeUA5w0unlORnssp0KDkV0Ypq+vDzmzxNS7ZggZ8QnH8CHvFL55ByuXifsSR1yBsGnkqRoUz5R
LZNOy4ggYlE77c0RTDhRYthN/uRoidpj8sLCnv0LwaVAtqOWuLHroQlmSHqsttUCO1ID8xBv9i/u
ek6gvGmsDS8z4rrWaBlAgaE2/33HODOQSs2PAfdVXt+CVaeI7ThX2Nb480uAhOrW373bakKrrwLl
Bn5QTGmZ5hEDDzgbgNjB0t/lMIrvUSnzApPi8FRKQBzROlvVDDSEtED4eKNM6y5HeVjdVR/+v3gE
PXAMKCJVzIbouVzmN9hWy4s7LflUhuuIeA5qYd7PTfl9IMOCuxFBXz/jVdsoCssRnNq4U0rwSi2M
G9TTThMt7qEIFyGKjKoa2g8WTSBeCYHfCZkHiEDUnzPp9RrW/CBhx9Bjh1FS+Hyz/rOrkZ6PPXCC
OgYx+UjNK64mXz4YwPCB7+JjB69OcRnoxfRdcbr/PAAVChBFAvXxb2ff2N7AnKSu9WnuZnMc0uDd
oq3JsLTKG679gmPuVZRuf8rzYTwOXWrUSnO5p+0TBRfLCJ6AqPHgy7vcI7+4sTaL7+3p/sdzqWx4
/54wnYetQqnkLExweKJvDTVE6NQgvBJKIsSm6PmqNbe+/oDxT0S1wspvsXZ029ckZ57RCEvdCqHD
6WBFJD25o9O+hRHyy7INWXaYCscBGpSrTIPizAiIy7eskM45ZEn0mj3iukEKn3rKjeZ40dae/3RB
WsVhy5kt5gRCmT6z6Ws21aO4Ka2wg4NwhVSa0oXYfEMGv6oquG0lAxp/7sRO5Qt2pjDFvFDQ4Nbr
K71C31GE31QKI+3JuZASBAgOIrughV7HL+bM9lBs3wrYIlhEVUPfdnbihAw56z4zffABfC8WE610
nzsQIpSYZX7qL0ycYDGNyisRya88ClwfCFiEt6fVyMrmNUlZEQIVFsChYeFenX27laG6Be2cfNnN
eK64ISjfuTRElCRbkolmH/jP0Sq2V0xfFeb5pABPXdlaVMkPw8VvSgarajsoT9sz45ZUcPyBiz0I
8Tdrq1/tqSUtWTEIQ6qS6ityMfJ2uk1yhl2ufv7jMb0zjNAZKT1EwtO49xfEUYMXpQhhBqFkO6k6
KSWoy5tXWj+8ZMMIchQVidOGpHxq8VcWLLmC6IAgt1WaouZV11DgMQFpVxjO59oR7ZYhiyWufmtR
pZk19CDuzyimL7kJ1FwJd2jyqLcT1wDw/vWqxbxHIHSoflN806Ze3c0lxy1TNSpM8EGW7Jt1kh0Y
VX+cpR94CeW1+/RVJhWxgFCfp6Al0UkEC53PuDHlQjZzVBnVbXv4xnjL6m4w2dAwI3OM3hJTarhf
vdBYTRIkmqkn+gtW/1ydbECNWL2/BAymSVCCsKD+OibEWsfYU8N+foJ6DpKVGk6Q38xKVbu7Avoc
yyEsbHh0RWuq2i3Nn964gR8YJpkzHpAa9CHapcJJAKk3B4LPGUvg83de2aWnlnm4I46wsaA+RoxG
cRzvm+k9l93nkCrfgW2Pe3Kqbpz64NqeXbxcT7X3xjQDtq5WjkZoOyWdKV4k5NXtxsQl7O4tL+bt
67c81a+V6bAWAtu4jvgqmtllc0wLulLdtCYF0gA0hspdZASOTXhVxfkSRrP6eclF7rWB05XEO1NB
hT2P8cXgXNdxonTKzljMQNzhDYnBG3/BjNzwu0OUnagCzq5WmVE/ArS1qsyPxINgaJ51PxxMirOR
FIADEAeSSDAG7Ts/YhQh7HAzotW4QfKjeGia9eSHccd6/d2b5kaPbrW6sHSGBoMHXJgxynDRq7ks
hQ0ilTHa7+V/NLHZBuO/GEVcQGMg6HgXhoChRgmVcPPcYUWPpTbhRSTsXsTMo3txBq6dd+802QZG
kw0f3USF1t9avcSMyCs2w+lE1Z86d3mMT24FdZQqohO/wNCU2l94FpwAqZjYlWzsowBmHTMbniWt
DZXwrlAqp90/jZ8C6YlynJUxPwGdDZaE/NavjseE6DCrmXdobGijQIBBFOKKx0lKzkFa1tgmEvaO
JfC0UDaWWjHmMIv9bbjwDnfJNu0MDrSJ+MrcadbpJpk0ptbHMJ7E8wd+xtbfF1vOoFk3x7Lye32h
G/2Kb3FIUnnA6fV0UdC0QmpcMjn2tothHMOCh7aAh5imMY0NVfapNpwj8uixNmnbghXn/vKqFo9r
fjblJVMSqWnbnK7cHthFnQxWNnGSDvw4IWVaCRYSI9eoBA8TnYFyZaLw4xn4rYl0rETYm2YA1P9D
wYQ8onumBNAJs0k6+gcCsiOQU2zjW0GlV0QLtmL21as3WSvyueE2+NP4o6K7G+rtb6R0vVOuL63g
DwANnto0eXikMJnlpT1ijRcsKTomZVJz9GrSulrfvldfYcgX88sCl/alcFgjCJqO+PeSc+cICOYj
U0sKZSjG2uMIzmvXmyEjBej0Y1qoqfkpNasILNR0fTFFUi315OOGaxtpf4KKRSQr5mPVHWDC2K46
wsr6gKb/dgn14WalEKb+v9v6TkVVPpf7J7NheZ2WiPxlGOcYocW1FqyW+IAHihLMuV9a1Qh9oSgv
xiDcG0ykM95Ku+oJqEfVPKMipdb+PbpVZFOainViySe6SYNcvksPJmuSV2oQmuq7c9YEA83eUD56
4ea2+pJtqGUa6tnHke05IoyNMz99Xqr7y2sQGkhJAftrrPwxasdfuEglaBWHReMTcfVQ27MkEXBV
PmFzfHzwg9Ey206Vm/RK/8VrU18pC+Z3zVd6aek1vURFQczj39cIaG0EEMYUrBjkkOQ+6bPBN6Sg
v0g5Sa6WFA981TlBa/A1ktbgfywsQ5grgITcF2tRBPhIoFKAwOItZFtLTomZbumCKtfGQSbw4Z7k
eFqrzJOeXxemmyM70TLOPBaSQJw4APIW287yJiYsPxig0NLwpgZxHbWO6cikqKAxCN+SurPMF0fD
3dFztimZRjqgMRS3psLiL4Q2b5FOG5d52dhKKnEiK0uQY2uRUN4AsbCus8Fu039C+Cq+r8tCtS8G
lmiVL1wtdYB+OP1coKGQ5B5K57OCVBOWb0nhj6ShxmryoBKsJeOiwzZj2V8xBUuzzp7o96DZcaob
6RwASl9A8TurtVb+zY+/YARpFJkPNhUGXeuD747G0tLeTQoN9LStccc4YAavUC1NnYum1fJ23gRw
iKy2SXXZ9YdSrT+hj+1QhPGZqwehwO1U40mx7b2O6sQvoU23GXdTsKY025tyDKNnn+OXFkXthOGn
mx1OfPpD9lj/ND4Tv3Y57q2caHW6NQixQvj8uYSN43t+RKLGsaGlYrIHQmAKYlTkhUV18z3q5BDp
5UMvhy3C3sseseqlX6s6q8sePDr4k48m04MsNFCt82tDFMJNjD52Qn8lzsoTwOqouAMpSViHtHiS
sopOMGscW0ifmY3UBt89PrH0L72f1oZD/DgQwWtTfq8tn101MkA/jTDhM5Y4bf6x/OEy7gNUeCe8
IP9paVSVuYy/D7EeAzmWHNyVddMlG4GO0JiMcOyC8nc0zRTP+VmEuCNS1pL8PLlUVpXIuMepjTBG
Y+0EZYhQeBvx27fX2KsqtnUQZ7js3rtTm+bMeL6414E8F6k11nA7OfRO1YnN6fgyiZPrSqqaPd1H
r26AFHzKRLpt91RZBiyAtovBRvoHTg+EvjVNvUOGGGLAejJMwO1sbhcstaP4H3TtzXVB6FTkfCw2
m/p9SgMPlxbiw2zFYUR9KuauQY/OidSwH/70n6JNo7/Sxpe3BA89PNxCGbigX2wPDxmadWXPcooV
V5nkNc28sZfTmzeRk2C7fKvDxeSYr1fFSMheIFR1KL2KwkQIrzdfSSZ3w6EOGsLR33VquNO6pxj+
K51M2O18U2Z/n3Y5YnyIFz3VjuVRJ4KvgaQhl21ELgvC9O/VIoK/l6z74xMNCqlP8J4qz/NTbIFN
rx1ohbwsXdi5Zz23fWOle/mWq3tMTSrSFgmGUhDhcJb8+gg8UqHSg7QBTzz1YmatKGa7FR4C6Ey7
GsHa3J8nW4v+t8oDNYVt/aMjSrv0iiBEzYlU0hQKbuThE++ZeZzLfuATiznRb5tS4morXXL2U7PI
vE+lxbVRKOpujv0IIvC11sGadtxDztBy0+qUAM884CcjeBWoz+CC6B528F5eOJuENj9zFDo4IfAk
jpTeU6/BPu1gcf8bqidGj34qDdnng4KxmTPW395geUjZan9D7fZ5yfgX8bqRYCpQkf2IJhPCfH/s
XyfUsRpAxAw3CDsBNJWDLncsuGdfhbtwxi6k/W4j2Pv5lnePcvbtau2NqhzSCaRrsgvscJee+w8j
0f1a5+sgCpiBjPhFmDLdJZG2GHER1gYlnyPybVg6zN5FkKlVzS8gA6CYfa2/dle7WaZkOo5tsXk+
hIwByAlFNDlr3MSoouipdH9GafCwRcHX6ExM23o71sUZvF75rFnqFT1lypiDOP8RjU6ieqiBhxE3
1PFAZ3WyWBG0eTL/QkKlR4WQTVC8Js5bKrlf3Dn8htzNYZYg2HMe8JE7/jsK7RolLphW8ff2Q9Px
vZBDG1fdXCVQ0psMwclZd4wTFfr76b239ZdeY0WHAsINhrKrSKEwzD50X9/qLylouysoiIYkZpnM
faAYXr5FEAgkZuyTlYmfPdyZe1/lcV9AOF95g9n7x0qBlRiFyEwcCh9KEzl51xElOZvsnSya75O4
wZSKeRZtorP8UBA4LJvXHK2QsLic98dLSknD2TQbZIW7PnfiPNlbrcQgVuuJzdrYlzAr+ccw/jPL
wscVQIfFz+nNvnf7JDS34E2Fqcfqu7InAIXt1OzpmHiudNm80Q2m+Z4ONIQj0kd8+c54nDs73ds8
13WtodvNGpuzPP6MFRL3dpquDZ3tQBakS7g4TojxBUFqp0JN7LMCx87Qxxk/SKbErNx4YqEEmlAd
NxF4AZ3tgbGyEE90xkbyywIyxzValj1uKA2RMhfJsBU6yvqG4XMBhxWtcFIGCdw7U6+LjrcDF3+b
2LR4XoZF8IGuZofJHx0KiFdf2RUKCHpKpasWBeJAp86oGpkVqd7LywniOBC90sMV1OgDJhFuxeHs
DKvHkYPT/DBdmIxbmVM4RYgCT8cfJdTuiuEt9bQiXHDFiCP8Z7wBmllWXQPF7uKgJLh6KDsHosCv
D7q8yH4kH2b7k3BbxWrcp7T1r6tLCZj2iLYgjefjIHhZSlsUKMeR4FqwqM0rMqxRLUpMzL9Tk6Rj
zuQyny85vH+9UUHhjScXVwFr7/tLPXFKmjfelMG24nqbhzpM/RAw9cnoYGqVfKCo5NpevBN6DkTm
3BNivucnKNN6auTOcw61PmubSGQ2Ggi6jF3vEo1HLuaQ4q5g7i1lnqRS592lADch7rbtW8MyKU/j
gsV/LQySnmogr4OwhA4bezToN5XYV55Dpqc1d3nSbV75OwrSMkvPj0LWkxfgwKJmXMKLJNqsdxSB
+8mhO8HYoJk8mTKuBtikHwRQeTP6jpZERr8RY8Jhy+kAkEI47ZxeRatulcKfSkysatuSsLvq0DtB
0ACSYddGjq25ISis6xNtYwrOS2eglD2mDNHS9sNuXTdQvHB43t5zmDaRGlEWSyesYLOcHszAE9zv
+mRBzYrpji+eQoC/vwz3acg9sJAsJ2ljcynYttHwBW/0rlGkhxe+42JqWrEfBvaoqgTzBahr9PUU
3jDTozHnY2IzumiKyo/gWOzTy6PPgqGIqv7i0b/7vXNmrpk8IXGWyZs8qpPZ0Da844NazaGbhS7d
IvDMIUeFHExdSpUmHIa74t6QvrxuA1Bw5f5bxqDTKqymncsIYNgn+DGuAFWgmeOIo1qNwlK3v4Te
uyEa+eX9k+IBvvAHR0Iunv4W6z3tJrgnaDj6Gs+1jwAKKItdhp9xhx7HuvmJIcZ6/63zogkZ7ZZu
Uqs1eMrscCibI4bHm+ztnUybkWpRGBY58Js8UQ1mdg0j+OOAUrnXVxdmwlLtcNRPchGw3qN9cZVJ
rPhuQ39keLn0StuhrYPstrdsudBFC+4qFx/I8mBV65v7wezxIiCdQ+HCBayJstDd44cnHFZYH/03
xCMDzc2hDfZkEUXAxVEo5I2EB6sfaTwmaVVVgFzq/Vg30djFb9DXQMcLZc2PURgycL/ZIOw877yL
v+qREiHq0psjX13pkIswcvp39MbJVKeHOs8oNOkMdCPn0KWmJ1lnaVyxdw8liMbkic+xtsdnZMIq
tBl+wjtW0KXI0SSRnKlHL8Vr5n/l8pY9uLBUghPpYtLcuWaq7hVb4JUP4q9DG3QoNuvDFFYGJg3E
0BzcM2pq/EJ84/yeT9dnjTeuhgSjx0/tk41xao/SxKmucSJMrXw2h7aiNkyuSp0ThcZemrJ+Lj47
SAmng27rXmbIHs9BhGG9DagH+pF0pX48kPFL0E6NXv/nodHTwm5okEowyI8t7PYFw9Zf4nvMWBhQ
Elbh+O2WaDAMs0syUAyZih8NoD9Z6IMwQ1Vy48dzZ0gm7F11MlxmIxKixmbo9QNyDF5CDTtyRDtC
mjJTSn9RPxMXe7CH9KjQ2KdlZytDR6S7FInsqjgdnHRhMHAVN/tDnAWuaiHnknV4zbXfRJbx8ii6
E9Y92tNnZI+MHs9/eX6CPM7zOS2b0PZnIOMO3JQXZDdrh7/xmR579BgIGI1t8TU4C73NmVVLsMwQ
tkC0u+12a72BgmPAg/kaZ2i+5KkOW+JDDaT6Y8Ej6gVS3qNG5x609eM3V1Pwyb4bcuiC6KoMw1ZY
JqZbxoRCqKxGSXVPG1B3G/qNYyV6jNImODuvteKg3dhV/hpREnrEduKznj+TEqnmBj+aKVZ32ggl
9ZSH/7nKXxqaY9OGtw2L/MlO+l2d8ordFZrl9yXD7u3HptaOhITp9uvxr/LZo4LOogZp6vFE1k3e
Bt4eG9XqgA7Qr0hrCc5QXinUBe3Qxd1yFeB3KAmgfDG1+DYj6E4lEsnpRoVKNsnXJHzPlL1csb9O
cjMpkCHyiRhlNc1dBl7u0O7Fuzi1xpA96pKecUXa2/Q0fWxTugutyfeshiadsCG0o19C3hcNISQX
6ZZMg+/V8b2+fIFfznVtaELIWsuIsxJ6r7zq3TC8WUpXWJNbPpuj+2So/qDwmYgz+vUgWLpSm38Z
CD2FcKUkffcePvYYcTT1s28GQyXh48hm5QXukxb+imyn6/YftOj3z2K78pn0q0rax9QeKB43+peL
kfM/gyHThpj1hks0mPSgAMIa1FzBJpaIk3rMnj5+McyPIvVeLCVf+o3wDHhZzGpyvJVpsdhgBTWJ
XIdTsf9YJihGocmA5WGSRcQBHk+ISJe4HIVLj4KPbCCo0JD11tTqZO5KS9Y6RY2/tz400A73EJNl
v77L7a7OrtWuDaWkCkmME3YLkSX+vb+Fvylds/kO31/dHQiWOROVP363LvIRJpNcj1heaBV3yc2k
rFMI1Ic7F53pooog6YSTqrbY65D77rAdH0mE4p+HBywURsXC/EHbG51rTeJR3zaf7J+NZUV46jY+
4qC6Q29zgQdAw3/9/timjlp0JpzlCxkdM1ERZh0cWlx4pjnV00F+kd7tR/yztn3Zyu7n7oBqDnvo
Sb02bOQ0UX10q9sKw4wY+attltCRNHTFii6yYlKCWA5yEugJK7HAOc/Iboo2HNs6g75OmZgcI69p
h04hkvl7dBV+1VnPzAxL7LSoEdj8dAAk1newarxG6PUG3DY5mOttikOSe3lMG5OJUjc+UfL8npeO
85We8GOkjdsqX6eFdQGFxJDadftHJtT3LdF/53M/W92CN6LPbfoJit1zG3W/5jUuQvVw389TxQx4
Usrq04bade0vUVnIumGEazikZmERKrf39WZ2R197CSDfR4ERWeAj
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/25/2016 07:00:27 PM
// Design Name:
// Module Name: testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module testbench;
//
// Model the free running clock on the Basys 3 bpard
//
reg clk;
initial begin
clk <= 1'b0;
forever
#5 clk <= ~clk;
end
//
// Model the reset as the center button on the Basys 3 board
//
reg reset;
initial begin
reset <= 1'b0;
#13 reset <= 1'b1;
#57 reset <= 1'b0;
end
//
// Models of LEDs and Swotches on the Basys 3 board
//
reg [7:0] switches_reg =0;
wire [7:0] switches;
wire [7:0] leds;
assign switches = switches_reg;
basic dut(/*AUTOARG*/
// Inouts
.SWITCHES(switches),
.LEDS(leds),
// Inputs
.CLK_IN(clk),
.RESET_IN(reset)
) ;
//
// Test Case Tools
//
reg test_passed = 0;
reg test_failed = 0;
integer i;
//
// If test fails, alert user and terminate simulation
//
always @(posedge test_failed) begin
$display("Test Failed @ %d" % $time);
#10 $finish;
end
//
// If test passes, alert user and terminate simulation
//
always @(posedge test_passed) begin
$display("TEST PASSED @ %d", $time);
#10 $finish;
end
//
// Time out issues, if our test does not complete in time, fail it
//
initial begin
#100_000;
$display("TEST CASE TIMED OUT ");
test_failed <= 1;
end
//
// Run our test case!
//
initial begin
//
// Wait for reset to finish before starting test case
//
@(posedge reset);
repeat (10) @(posedge clk);
for (i=0; i<8; i=i+1) begin
switches_reg[i] <= (1 << i); //Flip switch up
@(posedge leds[i]); //Wait for corresponding LED to light up
end
repeat (10) @(posedge clk);
switches_reg <= 8'hFF;
repeat (10) @(posedge clk);
for (i=0; i<8; i=i+1) begin
switches_reg[i] <= (0 << i); //Flip switch down
@(negedge leds[i]); //Wait for corresponding LED to turn off
end
test_passed <= 1;
end
endmodule
|
`timescale 1ns / 1ps
module MultiState(
input clk,
input rst,
input [5:0] op,
output [2:0] state
);
reg [2:0] tmp;
assign state = tmp;
always@(posedge clk) begin
if (rst == 0) begin
tmp = 3'B000;
end else begin
case (tmp)
3'B000: tmp = 3'B001;
3'B001: begin
if (op[5:3] == 3'B111) begin // j, jal, jr, halt
tmp = 3'B000;
end else begin // others
tmp = 3'B010;
end
end
3'B010: begin
if (op[5:2] == 4'B1101) begin // beq, bltz
tmp = 3'B000;
end else if (op[5:2] == 4'B1100) begin // sw, lw
tmp = 3'B100;
end else begin // others
tmp = 3'B011;
end
end
3'B011: tmp = 3'B000;
3'B100: begin
if (op[0] == 1) begin // lw
tmp = 3'B011;
end else begin
tmp = 3'B000;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_HS__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 14:56:48
// Design Name:
// Module Name: sandbox
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sandbox
(
output wire [127:0] OLED_S0,
output wire [127:0] OLED_S1,
output wire [127:0] OLED_S2,
output wire [127:0] OLED_S3,
input wire GCLK,
output wire [7:0] LD,
input wire [7:0] SW,
output wire [7:0] JA,
input wire [7:0] JB,
input wire BTNC,
input wire BTND,
input wire BTNL,
input wire BTNR,
input wire BTNU
);
wire MISO;
wire MOSI;
wire SS;
wire SCLK;
reg SS_REG = 1'b0;
reg SCLK_REG = 1'b0;
assign JA[2] = SS_REG;
assign JA[3] = SCLK_REG;
always @(posedge GCLK) begin
SS_REG <= SS;
SCLK_REG <= SCLK;
end
//assign JA[3] = SCLK;
SPI #(.m(15), .Tbit(100)) spi
(
// External interfaces
.str0(OLED_S0),
.str1(OLED_S1),
.str2(OLED_S2),
.str3(OLED_S3),
.GCLK(GCLK),
.RST(BTND),
.SW(SW),
// Transmission start switch
.st(BTNC),
// SPI Master bus
//.MASTER_MISO(MISO),
//.MASTER_MOSI(MOSI),
.MASTER_SS(SS),
.MASTER_SCLK(SCLK),
.MASTER_MISO(JB[0]),
.MASTER_MOSI(JA[1]),
//.MASTER_SS(JA[2]),
//.MASTER_SCLK(JA[3]),
// SPI Slave bus
//.SLAVE_MISO(MISO),
//.SLAVE_MOSI(MOSI),
.SLAVE_SS(SS),
.SLAVE_SCLK(SCLK),
.SLAVE_MOSI(JB[1]),
.SLAVE_MISO(JA[0])
//.SLAVE_SS(JB[2])
//.SLAVE_SCLK(JB[3])
);
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / 7SERIES OUT FIFO
// /__/ /\ Filename : OUT_FIFO.v
// \ \ / \
// \__\/\__ \
//
// Date: Comment:
// 15MAR2010 Initial UNI/UNP/SIM version from yml
// 03JUN2010 yml update
// 10JUN2010 yml update
// 29JUN2010 enable encrypted rtl
// 10AUG2010 yml, rtl update
// 28SEP2010 minor clean up
// add width checks
// 28OCT2010 rtl update
// 05NOV2010 update defaults
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP, make default
// 21SEP2011 625537 period checks on RDCLK, WRCLK
// 16FEB2012 645871 add conditions to RDEN -> Q delays
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OUT_FIFO (
ALMOSTEMPTY,
ALMOSTFULL,
EMPTY,
FULL,
Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
Q9,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
RDCLK,
RDEN,
RESET,
WRCLK,
WREN
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
parameter ARRAY_MODE = "ARRAY_MODE_8_X_4";
parameter OUTPUT_DISABLE = "FALSE";
parameter SYNCHRONOUS_MODE = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam out_delay = 10;
`endif
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
localparam MODULE_NAME = "OUT_FIFO";
output ALMOSTEMPTY;
output ALMOSTFULL;
output EMPTY;
output FULL;
output [3:0] Q0;
output [3:0] Q1;
output [3:0] Q2;
output [3:0] Q3;
output [3:0] Q4;
output [3:0] Q7;
output [3:0] Q8;
output [3:0] Q9;
output [7:0] Q5;
output [7:0] Q6;
input RDCLK;
input RDEN;
input RESET;
input WRCLK;
input WREN;
input [7:0] D0;
input [7:0] D1;
input [7:0] D2;
input [7:0] D3;
input [7:0] D4;
input [7:0] D5;
input [7:0] D6;
input [7:0] D7;
input [7:0] D8;
input [7:0] D9;
reg [0:0] ARRAY_MODE_BINARY;
reg [0:0] OUTPUT_DISABLE_BINARY;
reg [0:0] SLOW_RD_CLK_BINARY;
reg [0:0] SLOW_WR_CLK_BINARY;
reg [0:0] SYNCHRONOUS_MODE_BINARY;
reg [3:0] SPARE_BINARY;
reg [7:0] ALMOST_EMPTY_VALUE_BINARY;
reg [7:0] ALMOST_FULL_VALUE_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (ALMOST_EMPTY_VALUE)
1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE);
#1 $finish;
end
endcase
case (ALMOST_FULL_VALUE)
1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE);
#1 $finish;
end
endcase
case (ARRAY_MODE)
"ARRAY_MODE_8_X_4" : ARRAY_MODE_BINARY <= 1'b1;
"ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_8_X_4 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE);
#1 $finish;
end
endcase
case (OUTPUT_DISABLE)
"FALSE" : OUTPUT_DISABLE_BINARY <= 1'b0;
"TRUE" : OUTPUT_DISABLE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_DISABLE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, OUTPUT_DISABLE);
#1 $finish;
end
endcase
SLOW_RD_CLK_BINARY <= 1'b0;
SLOW_WR_CLK_BINARY <= 1'b0;
SPARE_BINARY <= 4'b0;
case (SYNCHRONOUS_MODE)
"FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE);
#1 $finish;
end
endcase
end
wire [3:0] delay_Q0;
wire [3:0] delay_Q1;
wire [3:0] delay_Q2;
wire [3:0] delay_Q3;
wire [3:0] delay_Q4;
wire [3:0] delay_Q7;
wire [3:0] delay_Q8;
wire [3:0] delay_Q9;
wire [7:0] delay_Q5;
wire [7:0] delay_Q6;
wire delay_ALMOSTEMPTY;
wire delay_ALMOSTFULL;
wire delay_EMPTY;
wire delay_FULL;
wire [3:0] delay_SCANOUT;
wire [7:0] delay_D0;
wire [7:0] delay_D1;
wire [7:0] delay_D2;
wire [7:0] delay_D3;
wire [7:0] delay_D4;
wire [7:0] delay_D5;
wire [7:0] delay_D6;
wire [7:0] delay_D7;
wire [7:0] delay_D8;
wire [7:0] delay_D9;
wire delay_RDCLK;
wire delay_RDEN;
wire delay_RESET;
wire delay_SCANENB = 1'b1;
wire delay_TESTMODEB = 1'b1;
wire delay_TESTREADDISB = 1'b1;
wire delay_TESTWRITEDISB = 1'b1;
wire [3:0] delay_SCANIN = 4'hf;
wire delay_WRCLK;
wire delay_WREN;
wire delay_GSR;
assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY;
assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL;
assign #(out_delay) EMPTY = delay_EMPTY;
assign #(out_delay) FULL = delay_FULL;
assign #(out_delay) Q0 = delay_Q0;
assign #(out_delay) Q1 = delay_Q1;
assign #(out_delay) Q2 = delay_Q2;
assign #(out_delay) Q3 = delay_Q3;
assign #(out_delay) Q4 = delay_Q4;
assign #(out_delay) Q5 = delay_Q5;
assign #(out_delay) Q6 = delay_Q6;
assign #(out_delay) Q7 = delay_Q7;
assign #(out_delay) Q8 = delay_Q8;
assign #(out_delay) Q9 = delay_Q9;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_RDCLK = RDCLK;
assign #(INCLK_DELAY) delay_WRCLK = WRCLK;
assign #(in_delay) delay_D0 = D0;
assign #(in_delay) delay_D1 = D1;
assign #(in_delay) delay_D2 = D2;
assign #(in_delay) delay_D3 = D3;
assign #(in_delay) delay_D4 = D4;
assign #(in_delay) delay_D5 = D5;
assign #(in_delay) delay_D6 = D6;
assign #(in_delay) delay_D7 = D7;
assign #(in_delay) delay_D8 = D8;
assign #(in_delay) delay_D9 = D9;
assign #(in_delay) delay_RDEN = RDEN;
`endif
assign #(in_delay) delay_RESET = RESET;
`ifndef XIL_TIMING
assign #(in_delay) delay_WREN = WREN;
`endif
assign delay_GSR = GSR;
SIP_OUT_FIFO OUT_FIFO_INST (
.ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY),
.ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY),
.ARRAY_MODE (ARRAY_MODE_BINARY),
.OUTPUT_DISABLE (OUTPUT_DISABLE_BINARY),
.SLOW_RD_CLK (SLOW_RD_CLK_BINARY),
.SLOW_WR_CLK (SLOW_WR_CLK_BINARY),
.SPARE (SPARE_BINARY),
.SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY),
.ALMOSTEMPTY (delay_ALMOSTEMPTY),
.ALMOSTFULL (delay_ALMOSTFULL),
.EMPTY (delay_EMPTY),
.FULL (delay_FULL),
.Q0 (delay_Q0),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.Q9 (delay_Q9),
.SCANOUT (delay_SCANOUT),
.D0 (delay_D0),
.D1 (delay_D1),
.D2 (delay_D2),
.D3 (delay_D3),
.D4 (delay_D4),
.D5 (delay_D5),
.D6 (delay_D6),
.D7 (delay_D7),
.D8 (delay_D8),
.D9 (delay_D9),
.RDCLK (delay_RDCLK),
.RDEN (delay_RDEN),
.RESET (delay_RESET),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.TESTMODEB (delay_TESTMODEB),
.TESTREADDISB (delay_TESTREADDISB),
.TESTWRITEDISB (delay_TESTWRITEDISB),
.WRCLK (delay_WRCLK),
.WREN (delay_WREN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge RESET, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge RESET, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10);
( RDCLK *> EMPTY) = (10:10:10, 10:10:10);
( RDCLK *> Q0) = (10:10:10, 10:10:10);
( RDCLK *> Q1) = (10:10:10, 10:10:10);
( RDCLK *> Q2) = (10:10:10, 10:10:10);
( RDCLK *> Q3) = (10:10:10, 10:10:10);
( RDCLK *> Q4) = (10:10:10, 10:10:10);
( RDCLK *> Q5) = (10:10:10, 10:10:10);
( RDCLK *> Q6) = (10:10:10, 10:10:10);
( RDCLK *> Q7) = (10:10:10, 10:10:10);
( RDCLK *> Q8) = (10:10:10, 10:10:10);
( RDCLK *> Q9) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q0) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q1) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q2) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q3) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q4) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q5) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q6) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q7) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q8) = (10:10:10, 10:10:10);
if (OUTPUT_DISABLE_BINARY) ( RDEN *> Q9) = (10:10:10, 10:10:10);
( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10);
( WRCLK *> FULL) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // OUT_FIFO
`endcelldefine
|
`include "definitions.vh"
module uart_loader
(
input clk,
input calib_done,
input disabled,
output reg started,
output reg done,
output [7:0] progress,
input rx,
output reg mem_cmd_en,
output [2:0] mem_cmd_instr,
output [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error
);
// Our interface with RAM is write-only, so always give the
// write command (000)
assign mem_cmd_instr = 3'b000;
// We always want to write 256-byte blocks to RAM, so always
// use a burst length of 64 32-bit chunks
assign mem_cmd_bl = 6'b111111;
// We also always want to write 32-bit chunks, so don't mask
// any bytes
assign mem_wr_mask = 4'b0000;
// Initialize registers
initial begin
started = 0;
done = 0;
mem_cmd_en = 0;
mem_wr_en = 0;
end
// A reader for individual bytes of data off of the serial
// interface. Use a higher baud rate so we get better throughput.
// Data transfer takes ((2^19)/BAUD) = 4.55 seconds at 115200 baud
wire busy;
wire [7:0] uart_data;
uart uart_
(
.clk(clk),
.rst(1'b0),
.rx(rx),
.busy(busy),
.data(uart_data)
);
// State machine logic to load data
reg [2:0] state = 0;
reg [7:0] cur_line = 0;
reg [7:0] cur_byte = 0;
reg busy_prev = 0;
assign progress = cur_line;
always @ (posedge clk) begin
busy_prev <= busy;
mem_cmd_en <= 0;
mem_wr_en <= 0;
case (state)
// Wait for calibration to complete
0: begin
if (calib_done) begin
state <= 1;
end
end
// Receive 256 bytes, load them into the RAM fifo
1: begin
// If we just received a byte
if (!busy && busy_prev && !disabled) begin
started <= 1;
cur_byte <= cur_byte + 1;
mem_wr_data <= { mem_wr_data[23:0], uart_data };
// If we just filled up a word, send it
// to the write fifo
if (2'b11 == cur_byte[1:0]) begin
mem_wr_en <= 1;
end
// If we just filled up a row, send a write command
if (255 == cur_byte) begin
state <= 2;
end
end
end
// Send a write command for the line
2: begin
if (mem_cmd_en) begin
if (255 == cur_line) begin
state <= 3;
end else begin
cur_line <= cur_line + 1;
state <= 1;
end
end else begin
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, cur_line, 8'b0 };
mem_cmd_en <= 1;
end
end
// Send the done signal and do nothing
3: begin
done <= 1;
end
endcase
end
endmodule
|
// pr_region_default_mm_bridge_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module pr_region_default_mm_bridge_0 #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [3:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [3:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (DATA_WIDTH),
.SYMBOL_WIDTH (SYMBOL_WIDTH),
.HDL_ADDR_WIDTH (HDL_ADDR_WIDTH),
.BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
.PIPELINE_COMMAND (PIPELINE_COMMAND),
.PIPELINE_RESPONSE (PIPELINE_RESPONSE)
) mm_bridge_0 (
.clk (clk), // input, width = 1, clk.clk
.reset (reset), // input, width = 1, reset.reset
.s0_waitrequest (s0_waitrequest), // output, width = 1, s0.waitrequest
.s0_readdata (s0_readdata), // output, width = DATA_WIDTH, .readdata
.s0_readdatavalid (s0_readdatavalid), // output, width = 1, .readdatavalid
.s0_burstcount (s0_burstcount), // input, width = BURSTCOUNT_WIDTH, .burstcount
.s0_writedata (s0_writedata), // input, width = DATA_WIDTH, .writedata
.s0_address (s0_address), // input, width = HDL_ADDR_WIDTH, .address
.s0_write (s0_write), // input, width = 1, .write
.s0_read (s0_read), // input, width = 1, .read
.s0_byteenable (s0_byteenable), // input, width = 4, .byteenable
.s0_debugaccess (s0_debugaccess), // input, width = 1, .debugaccess
.m0_waitrequest (m0_waitrequest), // input, width = 1, m0.waitrequest
.m0_readdata (m0_readdata), // input, width = DATA_WIDTH, .readdata
.m0_readdatavalid (m0_readdatavalid), // input, width = 1, .readdatavalid
.m0_burstcount (m0_burstcount), // output, width = BURSTCOUNT_WIDTH, .burstcount
.m0_writedata (m0_writedata), // output, width = DATA_WIDTH, .writedata
.m0_address (m0_address), // output, width = HDL_ADDR_WIDTH, .address
.m0_write (m0_write), // output, width = 1, .write
.m0_read (m0_read), // output, width = 1, .read
.m0_byteenable (m0_byteenable), // output, width = 4, .byteenable
.m0_debugaccess (m0_debugaccess), // output, width = 1, .debugaccess
.s0_response (), // (terminated),
.m0_response (2'b00) // (terminated),
);
endmodule
|
// lab3_mm_interconnect_0.v
// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.04.26.23:17:39
`timescale 1 ps / 1 ps
module lab3_mm_interconnect_0 (
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire master_0_clk_reset_reset_bridge_in_reset_reset, // master_0_clk_reset_reset_bridge_in_reset.reset
input wire vga_led_0_reset_sink_reset_bridge_in_reset_reset, // vga_led_0_reset_sink_reset_bridge_in_reset.reset
input wire [31:0] master_0_master_address, // master_0_master.address
output wire master_0_master_waitrequest, // .waitrequest
input wire [3:0] master_0_master_byteenable, // .byteenable
input wire master_0_master_read, // .read
output wire [31:0] master_0_master_readdata, // .readdata
output wire master_0_master_readdatavalid, // .readdatavalid
input wire master_0_master_write, // .write
input wire [31:0] master_0_master_writedata, // .writedata
output wire [0:0] audio_emulator_0_avalon_slave_0_address, // audio_emulator_0_avalon_slave_0.address
output wire audio_emulator_0_avalon_slave_0_write, // .write
output wire [15:0] audio_emulator_0_avalon_slave_0_writedata, // .writedata
output wire audio_emulator_0_avalon_slave_0_chipselect, // .chipselect
output wire [3:0] vga_led_0_avalon_slave_0_address, // vga_led_0_avalon_slave_0.address
output wire vga_led_0_avalon_slave_0_write, // .write
output wire [15:0] vga_led_0_avalon_slave_0_writedata, // .writedata
output wire vga_led_0_avalon_slave_0_chipselect // .chipselect
);
wire master_0_master_translator_avalon_universal_master_0_waitrequest; // master_0_master_translator_avalon_universal_master_0_agent:av_waitrequest -> master_0_master_translator:uav_waitrequest
wire [2:0] master_0_master_translator_avalon_universal_master_0_burstcount; // master_0_master_translator:uav_burstcount -> master_0_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] master_0_master_translator_avalon_universal_master_0_writedata; // master_0_master_translator:uav_writedata -> master_0_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] master_0_master_translator_avalon_universal_master_0_address; // master_0_master_translator:uav_address -> master_0_master_translator_avalon_universal_master_0_agent:av_address
wire master_0_master_translator_avalon_universal_master_0_lock; // master_0_master_translator:uav_lock -> master_0_master_translator_avalon_universal_master_0_agent:av_lock
wire master_0_master_translator_avalon_universal_master_0_write; // master_0_master_translator:uav_write -> master_0_master_translator_avalon_universal_master_0_agent:av_write
wire master_0_master_translator_avalon_universal_master_0_read; // master_0_master_translator:uav_read -> master_0_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] master_0_master_translator_avalon_universal_master_0_readdata; // master_0_master_translator_avalon_universal_master_0_agent:av_readdata -> master_0_master_translator:uav_readdata
wire master_0_master_translator_avalon_universal_master_0_debugaccess; // master_0_master_translator:uav_debugaccess -> master_0_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] master_0_master_translator_avalon_universal_master_0_byteenable; // master_0_master_translator:uav_byteenable -> master_0_master_translator_avalon_universal_master_0_agent:av_byteenable
wire master_0_master_translator_avalon_universal_master_0_readdatavalid; // master_0_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> master_0_master_translator:uav_readdatavalid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // vga_led_0_avalon_slave_0_translator:uav_waitrequest -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> vga_led_0_avalon_slave_0_translator:uav_burstcount
wire [15:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> vga_led_0_avalon_slave_0_translator:uav_writedata
wire [31:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> vga_led_0_avalon_slave_0_translator:uav_address
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> vga_led_0_avalon_slave_0_translator:uav_write
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> vga_led_0_avalon_slave_0_translator:uav_lock
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> vga_led_0_avalon_slave_0_translator:uav_read
wire [15:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // vga_led_0_avalon_slave_0_translator:uav_readdata -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // vga_led_0_avalon_slave_0_translator:uav_readdatavalid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> vga_led_0_avalon_slave_0_translator:uav_debugaccess
wire [1:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> vga_led_0_avalon_slave_0_translator:uav_byteenable
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [17:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [17:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // audio_emulator_0_avalon_slave_0_translator:uav_waitrequest -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> audio_emulator_0_avalon_slave_0_translator:uav_burstcount
wire [15:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> audio_emulator_0_avalon_slave_0_translator:uav_writedata
wire [31:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> audio_emulator_0_avalon_slave_0_translator:uav_address
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> audio_emulator_0_avalon_slave_0_translator:uav_write
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> audio_emulator_0_avalon_slave_0_translator:uav_lock
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> audio_emulator_0_avalon_slave_0_translator:uav_read
wire [15:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // audio_emulator_0_avalon_slave_0_translator:uav_readdata -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // audio_emulator_0_avalon_slave_0_translator:uav_readdatavalid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> audio_emulator_0_avalon_slave_0_translator:uav_debugaccess
wire [1:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> audio_emulator_0_avalon_slave_0_translator:uav_byteenable
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [17:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [17:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> addr_router:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> addr_router:sink_valid
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> addr_router:sink_startofpacket
wire [122:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> addr_router:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // addr_router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> addr_router_001:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> addr_router_001:sink_valid
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> addr_router_001:sink_startofpacket
wire [122:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> addr_router_001:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // addr_router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // master_0_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire master_0_master_translator_avalon_universal_master_0_agent_cp_valid; // master_0_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // master_0_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [122:0] master_0_master_translator_avalon_universal_master_0_agent_cp_data; // master_0_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire master_0_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> master_0_master_translator_avalon_universal_master_0_agent:cp_ready
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [104:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [104:0] audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [122:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [2:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [122:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [2:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [122:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [2:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [122:0] limiter_rsp_src_data; // limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire [2:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [122:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [2:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [122:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [2:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [122:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [2:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [122:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire [2:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire limiter_001_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> limiter_001:rsp_src_ready
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> limiter_002:cmd_sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> limiter_002:cmd_sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> limiter_002:cmd_sink_startofpacket
wire [122:0] addr_router_002_src_data; // addr_router_002:src_data -> limiter_002:cmd_sink_data
wire [2:0] addr_router_002_src_channel; // addr_router_002:src_channel -> limiter_002:cmd_sink_channel
wire addr_router_002_src_ready; // limiter_002:cmd_sink_ready -> addr_router_002:src_ready
wire limiter_002_cmd_src_endofpacket; // limiter_002:cmd_src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire limiter_002_cmd_src_startofpacket; // limiter_002:cmd_src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [122:0] limiter_002_cmd_src_data; // limiter_002:cmd_src_data -> cmd_xbar_demux_002:sink_data
wire [2:0] limiter_002_cmd_src_channel; // limiter_002:cmd_src_channel -> cmd_xbar_demux_002:sink_channel
wire limiter_002_cmd_src_ready; // cmd_xbar_demux_002:sink_ready -> limiter_002:cmd_src_ready
wire rsp_xbar_mux_002_src_endofpacket; // rsp_xbar_mux_002:src_endofpacket -> limiter_002:rsp_sink_endofpacket
wire rsp_xbar_mux_002_src_valid; // rsp_xbar_mux_002:src_valid -> limiter_002:rsp_sink_valid
wire rsp_xbar_mux_002_src_startofpacket; // rsp_xbar_mux_002:src_startofpacket -> limiter_002:rsp_sink_startofpacket
wire [122:0] rsp_xbar_mux_002_src_data; // rsp_xbar_mux_002:src_data -> limiter_002:rsp_sink_data
wire [2:0] rsp_xbar_mux_002_src_channel; // rsp_xbar_mux_002:src_channel -> limiter_002:rsp_sink_channel
wire rsp_xbar_mux_002_src_ready; // limiter_002:rsp_sink_ready -> rsp_xbar_mux_002:src_ready
wire limiter_002_rsp_src_endofpacket; // limiter_002:rsp_src_endofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_002_rsp_src_valid; // limiter_002:rsp_src_valid -> master_0_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_002_rsp_src_startofpacket; // limiter_002:rsp_src_startofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [122:0] limiter_002_rsp_src_data; // limiter_002:rsp_src_data -> master_0_master_translator_avalon_universal_master_0_agent:rp_data
wire [2:0] limiter_002_rsp_src_channel; // limiter_002:rsp_src_channel -> master_0_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_002_rsp_src_ready; // master_0_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_002:rsp_src_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] burst_adapter_source0_data; // burst_adapter:source0_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [2:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire burst_adapter_001_source0_endofpacket; // burst_adapter_001:source0_endofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_001_source0_valid; // burst_adapter_001:source0_valid -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_001_source0_startofpacket; // burst_adapter_001:source0_startofpacket -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] burst_adapter_001_source0_data; // burst_adapter_001:source0_data -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_001_source0_ready; // audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
wire [2:0] burst_adapter_001_source0_channel; // burst_adapter_001:source0_channel -> audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [122:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [2:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [122:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [2:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [122:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [2:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [122:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [2:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux:sink2_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux:sink2_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux:sink2_startofpacket
wire [122:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux:sink2_data
wire [2:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux:sink2_channel
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux:sink2_ready -> cmd_xbar_demux_002:src0_ready
wire cmd_xbar_demux_002_src1_endofpacket; // cmd_xbar_demux_002:src1_endofpacket -> cmd_xbar_mux_001:sink2_endofpacket
wire cmd_xbar_demux_002_src1_valid; // cmd_xbar_demux_002:src1_valid -> cmd_xbar_mux_001:sink2_valid
wire cmd_xbar_demux_002_src1_startofpacket; // cmd_xbar_demux_002:src1_startofpacket -> cmd_xbar_mux_001:sink2_startofpacket
wire [122:0] cmd_xbar_demux_002_src1_data; // cmd_xbar_demux_002:src1_data -> cmd_xbar_mux_001:sink2_data
wire [2:0] cmd_xbar_demux_002_src1_channel; // cmd_xbar_demux_002:src1_channel -> cmd_xbar_mux_001:sink2_channel
wire cmd_xbar_demux_002_src1_ready; // cmd_xbar_mux_001:sink2_ready -> cmd_xbar_demux_002:src1_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [2:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [2:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_src2_endofpacket; // rsp_xbar_demux:src2_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
wire rsp_xbar_demux_src2_valid; // rsp_xbar_demux:src2_valid -> rsp_xbar_mux_002:sink0_valid
wire rsp_xbar_demux_src2_startofpacket; // rsp_xbar_demux:src2_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src2_data; // rsp_xbar_demux:src2_data -> rsp_xbar_mux_002:sink0_data
wire [2:0] rsp_xbar_demux_src2_channel; // rsp_xbar_demux:src2_channel -> rsp_xbar_mux_002:sink0_channel
wire rsp_xbar_demux_src2_ready; // rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux:src2_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [122:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [2:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [122:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [2:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_001_src2_endofpacket; // rsp_xbar_demux_001:src2_endofpacket -> rsp_xbar_mux_002:sink1_endofpacket
wire rsp_xbar_demux_001_src2_valid; // rsp_xbar_demux_001:src2_valid -> rsp_xbar_mux_002:sink1_valid
wire rsp_xbar_demux_001_src2_startofpacket; // rsp_xbar_demux_001:src2_startofpacket -> rsp_xbar_mux_002:sink1_startofpacket
wire [122:0] rsp_xbar_demux_001_src2_data; // rsp_xbar_demux_001:src2_data -> rsp_xbar_mux_002:sink1_data
wire [2:0] rsp_xbar_demux_001_src2_channel; // rsp_xbar_demux_001:src2_channel -> rsp_xbar_mux_002:sink1_channel
wire rsp_xbar_demux_001_src2_ready; // rsp_xbar_mux_002:sink1_ready -> rsp_xbar_demux_001:src2_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> width_adapter:in_endofpacket
wire id_router_src_valid; // id_router:src_valid -> width_adapter:in_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> width_adapter:in_startofpacket
wire [104:0] id_router_src_data; // id_router:src_data -> width_adapter:in_data
wire [2:0] id_router_src_channel; // id_router:src_channel -> width_adapter:in_channel
wire id_router_src_ready; // width_adapter:in_ready -> id_router:src_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> rsp_xbar_demux:sink_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [122:0] width_adapter_src_data; // width_adapter:out_data -> rsp_xbar_demux:sink_data
wire width_adapter_src_ready; // rsp_xbar_demux:sink_ready -> width_adapter:out_ready
wire [2:0] width_adapter_src_channel; // width_adapter:out_channel -> rsp_xbar_demux:sink_channel
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_001:in_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
wire [104:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_001:in_data
wire [2:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_001:in_channel
wire id_router_001_src_ready; // width_adapter_001:in_ready -> id_router_001:src_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [122:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
wire width_adapter_001_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
wire [2:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> width_adapter_002:in_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> width_adapter_002:in_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> width_adapter_002:in_startofpacket
wire [122:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> width_adapter_002:in_data
wire [2:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> width_adapter_002:in_channel
wire cmd_xbar_mux_src_ready; // width_adapter_002:in_ready -> cmd_xbar_mux:src_ready
wire width_adapter_002_src_endofpacket; // width_adapter_002:out_endofpacket -> burst_adapter:sink0_endofpacket
wire width_adapter_002_src_valid; // width_adapter_002:out_valid -> burst_adapter:sink0_valid
wire width_adapter_002_src_startofpacket; // width_adapter_002:out_startofpacket -> burst_adapter:sink0_startofpacket
wire [104:0] width_adapter_002_src_data; // width_adapter_002:out_data -> burst_adapter:sink0_data
wire width_adapter_002_src_ready; // burst_adapter:sink0_ready -> width_adapter_002:out_ready
wire [2:0] width_adapter_002_src_channel; // width_adapter_002:out_channel -> burst_adapter:sink0_channel
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter_003:in_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter_003:in_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter_003:in_startofpacket
wire [122:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter_003:in_data
wire [2:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter_003:in_channel
wire cmd_xbar_mux_001_src_ready; // width_adapter_003:in_ready -> cmd_xbar_mux_001:src_ready
wire width_adapter_003_src_endofpacket; // width_adapter_003:out_endofpacket -> burst_adapter_001:sink0_endofpacket
wire width_adapter_003_src_valid; // width_adapter_003:out_valid -> burst_adapter_001:sink0_valid
wire width_adapter_003_src_startofpacket; // width_adapter_003:out_startofpacket -> burst_adapter_001:sink0_startofpacket
wire [104:0] width_adapter_003_src_data; // width_adapter_003:out_data -> burst_adapter_001:sink0_data
wire width_adapter_003_src_ready; // burst_adapter_001:sink0_ready -> width_adapter_003:out_ready
wire [2:0] width_adapter_003_src_channel; // width_adapter_003:out_channel -> burst_adapter_001:sink0_channel
wire [2:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [2:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire [2:0] limiter_002_cmd_valid_data; // limiter_002:cmd_src_valid -> cmd_xbar_demux_002:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) master_0_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (master_0_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (master_0_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (master_0_master_translator_avalon_universal_master_0_read), // .read
.uav_write (master_0_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (master_0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (master_0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (master_0_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (master_0_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (master_0_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (master_0_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (master_0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (master_0_master_address), // avalon_anti_master_0.address
.av_waitrequest (master_0_master_waitrequest), // .waitrequest
.av_byteenable (master_0_master_byteenable), // .byteenable
.av_read (master_0_master_read), // .read
.av_readdata (master_0_master_readdata), // .readdata
.av_readdatavalid (master_0_master_readdatavalid), // .readdatavalid
.av_write (master_0_master_write), // .write
.av_writedata (master_0_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) vga_led_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (vga_led_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (vga_led_0_avalon_slave_0_write), // .write
.av_writedata (vga_led_0_avalon_slave_0_writedata), // .writedata
.av_chipselect (vga_led_0_avalon_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_readdata (16'b1101111010101101), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) audio_emulator_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (audio_emulator_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (audio_emulator_0_avalon_slave_0_write), // .write
.av_writedata (audio_emulator_0_avalon_slave_0_writedata), // .writedata
.av_chipselect (audio_emulator_0_avalon_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_readdata (16'b1101111010101101), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (95),
.PKT_CACHE_H (117),
.PKT_CACHE_L (114),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_PROTECTION_H (113),
.PKT_PROTECTION_L (111),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_RESPONSE_STATUS_L (118),
.PKT_RESPONSE_STATUS_H (119),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_THREAD_ID_H (110),
.PKT_THREAD_ID_L (99),
.PKT_QOS_L (96),
.PKT_QOS_H (96),
.PKT_ORI_BURST_SIZE_L (120),
.PKT_ORI_BURST_SIZE_H (122),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.ID (0)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (limiter_rsp_src_data), // .data
.write_rp_channel (limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (limiter_001_rsp_src_valid), // read_rp.valid
.read_rp_data (limiter_001_rsp_src_data), // .data
.read_rp_channel (limiter_001_rsp_src_channel), // .channel
.read_rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (limiter_001_rsp_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (8'b00000000), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (113),
.PKT_PROTECTION_L (111),
.PKT_BEGIN_BURST (95),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_THREAD_ID_H (110),
.PKT_THREAD_ID_L (99),
.PKT_CACHE_H (117),
.PKT_CACHE_L (114),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.PKT_QOS_H (96),
.PKT_QOS_L (96),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_RESPONSE_STATUS_H (119),
.PKT_RESPONSE_STATUS_L (118),
.PKT_ORI_BURST_SIZE_L (120),
.PKT_ORI_BURST_SIZE_H (122),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (127),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) master_0_master_translator_avalon_universal_master_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (master_0_master_translator_avalon_universal_master_0_address), // av.address
.av_write (master_0_master_translator_avalon_universal_master_0_write), // .write
.av_read (master_0_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (master_0_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (master_0_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (master_0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (master_0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (master_0_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (master_0_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (master_0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (master_0_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (master_0_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (master_0_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (master_0_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_002_rsp_src_valid), // rp.valid
.rp_data (limiter_002_rsp_src_data), // .data
.rp_channel (limiter_002_rsp_src_channel), // .channel
.rp_startofpacket (limiter_002_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_002_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_002_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (77),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (3),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (77),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (3),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_001_source0_ready), // cp.ready
.cp_valid (burst_adapter_001_source0_valid), // .valid
.cp_data (burst_adapter_001_source0_data), // .data
.cp_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_001_source0_channel), // .channel
.rf_sink_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
lab3_mm_interconnect_0_addr_router addr_router (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_addr_router addr_router_001 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_addr_router addr_router_002 (
.sink_ready (master_0_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (master_0_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (master_0_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_id_router id_router (
.sink_ready (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_id_router id_router_001 (
.sink_ready (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (audio_emulator_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_002_src_valid), // .valid
.cmd_sink_data (addr_router_002_src_data), // .data
.cmd_sink_channel (addr_router_002_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_002_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_002_cmd_src_data), // .data
.cmd_src_channel (limiter_002_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_002_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_002_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_002_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_002_rsp_src_valid), // .valid
.rsp_src_data (limiter_002_rsp_src_data), // .data
.rsp_src_channel (limiter_002_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_002_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_002_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_002_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (77),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_BURST_TYPE_H (74),
.PKT_BURST_TYPE_L (73),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (69),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (width_adapter_002_src_valid), // sink0.valid
.sink0_data (width_adapter_002_src_data), // .data
.sink0_channel (width_adapter_002_src_channel), // .channel
.sink0_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_002_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_002_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (77),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_BURST_TYPE_H (74),
.PKT_BURST_TYPE_L (73),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (63),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (69),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter_001 (
.clk (clk_0_clk_clk), // cr0.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (width_adapter_003_src_valid), // sink0.valid
.sink0_data (width_adapter_003_src_data), // .data
.sink0_channel (width_adapter_003_src_channel), // .channel
.sink0_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_003_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_003_src_ready), // .ready
.source0_valid (burst_adapter_001_source0_valid), // source0.valid
.source0_data (burst_adapter_001_source0_data), // .data
.source0_channel (burst_adapter_001_source0_channel), // .channel
.source0_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_001_source0_ready) // .ready
);
lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_002_cmd_src_ready), // sink.ready
.sink_channel (limiter_002_cmd_src_channel), // .channel
.sink_data (limiter_002_cmd_src_data), // .data
.sink_startofpacket (limiter_002_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_002_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_002_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_002_src1_valid), // .valid
.src1_data (cmd_xbar_demux_002_src1_data), // .data
.src1_channel (cmd_xbar_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_002_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_xbar_demux_002_src0_valid), // .valid
.sink2_channel (cmd_xbar_demux_002_src0_channel), // .channel
.sink2_data (cmd_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (cmd_xbar_demux_002_src1_ready), // sink2.ready
.sink2_valid (cmd_xbar_demux_002_src1_valid), // .valid
.sink2_channel (cmd_xbar_demux_002_src1_channel), // .channel
.sink2_data (cmd_xbar_demux_002_src1_data), // .data
.sink2_startofpacket (cmd_xbar_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_xbar_demux_002_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (width_adapter_src_ready), // sink.ready
.sink_channel (width_adapter_src_channel), // .channel
.sink_data (width_adapter_src_data), // .data
.sink_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_xbar_demux_src2_ready), // src2.ready
.src2_valid (rsp_xbar_demux_src2_valid), // .valid
.src2_data (rsp_xbar_demux_src2_data), // .data
.src2_channel (rsp_xbar_demux_src2_channel), // .channel
.src2_startofpacket (rsp_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_xbar_demux_src2_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (width_adapter_001_src_ready), // sink.ready
.sink_channel (width_adapter_001_src_channel), // .channel
.sink_data (width_adapter_001_src_data), // .data
.sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_xbar_demux_001_src2_valid), // .valid
.src2_data (rsp_xbar_demux_001_src2_data), // .data
.src2_channel (rsp_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_xbar_demux_001_src2_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_002_src_ready), // src.ready
.src_valid (rsp_xbar_mux_002_src_valid), // .valid
.src_data (rsp_xbar_mux_002_src_data), // .data
.src_channel (rsp_xbar_mux_002_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src2_valid), // .valid
.sink0_channel (rsp_xbar_demux_src2_channel), // .channel
.sink0_data (rsp_xbar_demux_src2_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src2_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src2_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src2_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src2_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src2_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (62),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (69),
.IN_PKT_BURSTWRAP_L (63),
.IN_PKT_BURST_SIZE_H (72),
.IN_PKT_BURST_SIZE_L (70),
.IN_PKT_RESPONSE_STATUS_H (101),
.IN_PKT_RESPONSE_STATUS_L (100),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (74),
.IN_PKT_BURST_TYPE_L (73),
.IN_PKT_ORI_BURST_SIZE_L (102),
.IN_PKT_ORI_BURST_SIZE_H (104),
.IN_ST_DATA_W (105),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (80),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (90),
.OUT_PKT_BURST_SIZE_L (88),
.OUT_PKT_RESPONSE_STATUS_H (119),
.OUT_PKT_RESPONSE_STATUS_L (118),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (92),
.OUT_PKT_BURST_TYPE_L (91),
.OUT_PKT_ORI_BURST_SIZE_L (120),
.OUT_PKT_ORI_BURST_SIZE_H (122),
.OUT_ST_DATA_W (123),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1)
) width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (id_router_src_valid), // sink.valid
.in_channel (id_router_src_channel), // .channel
.in_startofpacket (id_router_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_src_endofpacket), // .endofpacket
.in_ready (id_router_src_ready), // .ready
.in_data (id_router_src_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (62),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (69),
.IN_PKT_BURSTWRAP_L (63),
.IN_PKT_BURST_SIZE_H (72),
.IN_PKT_BURST_SIZE_L (70),
.IN_PKT_RESPONSE_STATUS_H (101),
.IN_PKT_RESPONSE_STATUS_L (100),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (74),
.IN_PKT_BURST_TYPE_L (73),
.IN_PKT_ORI_BURST_SIZE_L (102),
.IN_PKT_ORI_BURST_SIZE_H (104),
.IN_ST_DATA_W (105),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (80),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (90),
.OUT_PKT_BURST_SIZE_L (88),
.OUT_PKT_RESPONSE_STATUS_H (119),
.OUT_PKT_RESPONSE_STATUS_L (118),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (92),
.OUT_PKT_BURST_TYPE_L (91),
.OUT_PKT_ORI_BURST_SIZE_L (120),
.OUT_PKT_ORI_BURST_SIZE_H (122),
.OUT_ST_DATA_W (123),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1)
) width_adapter_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (id_router_001_src_valid), // sink.valid
.in_channel (id_router_001_src_channel), // .channel
.in_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.in_ready (id_router_001_src_ready), // .ready
.in_data (id_router_001_src_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (80),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (87),
.IN_PKT_BURSTWRAP_L (81),
.IN_PKT_BURST_SIZE_H (90),
.IN_PKT_BURST_SIZE_L (88),
.IN_PKT_RESPONSE_STATUS_H (119),
.IN_PKT_RESPONSE_STATUS_L (118),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (92),
.IN_PKT_BURST_TYPE_L (91),
.IN_PKT_ORI_BURST_SIZE_L (120),
.IN_PKT_ORI_BURST_SIZE_H (122),
.IN_ST_DATA_W (123),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (62),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (72),
.OUT_PKT_BURST_SIZE_L (70),
.OUT_PKT_RESPONSE_STATUS_H (101),
.OUT_PKT_RESPONSE_STATUS_L (100),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (74),
.OUT_PKT_BURST_TYPE_L (73),
.OUT_PKT_ORI_BURST_SIZE_L (102),
.OUT_PKT_ORI_BURST_SIZE_H (104),
.OUT_ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0)
) width_adapter_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_src_ready), // .ready
.in_data (cmd_xbar_mux_src_data), // .data
.out_endofpacket (width_adapter_002_src_endofpacket), // src.endofpacket
.out_data (width_adapter_002_src_data), // .data
.out_channel (width_adapter_002_src_channel), // .channel
.out_valid (width_adapter_002_src_valid), // .valid
.out_ready (width_adapter_002_src_ready), // .ready
.out_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (80),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (87),
.IN_PKT_BURSTWRAP_L (81),
.IN_PKT_BURST_SIZE_H (90),
.IN_PKT_BURST_SIZE_L (88),
.IN_PKT_RESPONSE_STATUS_H (119),
.IN_PKT_RESPONSE_STATUS_L (118),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (92),
.IN_PKT_BURST_TYPE_L (91),
.IN_PKT_ORI_BURST_SIZE_L (120),
.IN_PKT_ORI_BURST_SIZE_H (122),
.IN_ST_DATA_W (123),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (62),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (72),
.OUT_PKT_BURST_SIZE_L (70),
.OUT_PKT_RESPONSE_STATUS_H (101),
.OUT_PKT_RESPONSE_STATUS_L (100),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (74),
.OUT_PKT_BURST_TYPE_L (73),
.OUT_PKT_ORI_BURST_SIZE_L (102),
.OUT_PKT_ORI_BURST_SIZE_H (104),
.OUT_ST_DATA_W (105),
.ST_CHANNEL_W (3),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0)
) width_adapter_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_001_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_001_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_001_src_ready), // .ready
.in_data (cmd_xbar_mux_001_src_data), // .data
.out_endofpacket (width_adapter_003_src_endofpacket), // src.endofpacket
.out_data (width_adapter_003_src_data), // .data
.out_channel (width_adapter_003_src_channel), // .channel
.out_valid (width_adapter_003_src_valid), // .valid
.out_ready (width_adapter_003_src_ready), // .ready
.out_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_retdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_retdp(/*AUTOARG*/
// Outputs
retdp_data_c7_buf, retdp_ecc_c7_buf, so,
// Inputs
scdata_sctag_decc_c6, rclk, si, se
);
output [127:0] retdp_data_c7_buf;
output [ 27:0] retdp_ecc_c7_buf;
output so;
input [155:0] scdata_sctag_decc_c6;
input rclk;
input si, se;
// Output of the L2$ data array.
wire [127:0] retdp_data_c6;
wire [ 27:0] retdp_ecc_c6;
assign {retdp_data_c6[31:0], retdp_ecc_c6[6:0]} = scdata_sctag_decc_c6[38:0];
assign {retdp_data_c6[63:32], retdp_ecc_c6[13:7]} = scdata_sctag_decc_c6[77:39];
assign {retdp_data_c6[95:64], retdp_ecc_c6[20:14]} = scdata_sctag_decc_c6[116:78];
assign {retdp_data_c6[127:96], retdp_ecc_c6[27:21]} = scdata_sctag_decc_c6[155:117];
// arrange these flops in 16 rows and 10 columns
// row0 ->{ data[2:0],ecc[6:0]}
// row1 ->{ data[12:3]}
// row2 ->{ data[22:13]}
// row3 ->{ data[31:23]}
// and so 0n. Buffer the outputs of each
// bit with a 40x buffer/inverter.
dff_s #(128) ff_data_rtn_c7
(.q (retdp_data_c7_buf[127:0]),
.din (retdp_data_c6[127:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(28) ff_ecc_rtn_c7
(.q (retdp_ecc_c7_buf[27:0]),
.din (retdp_ecc_c6[27:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:40:25 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_1_sim_netlist.v
// Design : zqynq_lab_1_design_processing_system7_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "2" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "zqynq_lab_1_design_processing_system7_0_1.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [1:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [1:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_processing_system7_0_1,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input [1:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [1:0]IRQ_F2P;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "2" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "zqynq_lab_1_design_processing_system7_0_1.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(IRQ_F2P),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module Tx8b10b_tb ();
reg clk; // System clock
reg rst; // Reset; synchronous and active high
reg en; // Enable bit
reg [7:0] dataIn; // Data to transmit
reg writeStrobe; // Write data to transmit FIFO
wire dataPresent; // FIFO has data still in it
wire halfFull; // FIFO halfway full
wire full; // FIFO is completely full. Don't write to it.
wire tx; // Transmit bit
integer i;
integer dcOffset;
always #1 clk = ~clk;
initial begin
dcOffset = 1'b0;
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
dataIn = 'd0;
writeStrobe = 1'b0;
@(posedge clk)
@(posedge clk)
rst = 1'b0;
for (i=0; i<50000; i=i+1) begin
wait(~full);
@(posedge clk) dataIn <= $random(); writeStrobe = 1'b1;
@(posedge clk) writeStrobe = 1'b0;
@(posedge clk);
end
$stop(2);
end
always @(posedge clk) begin
dcOffset <= dcOffset + $signed({tx, 1'b1});
end
Tx8b10b #(
.FILL_WORD_RD0(10'b0011111010), // Send when no data present & RD=-1
.FILL_WORD_RD1(10'b1100000101), // Send when no data present & RD=1
.FILL_WORD_FLIP(1'b1), // Flip status of Running Disparity when using fill word
.LOG2_DEPTH(4) // log2(depth of FIFO buffer). Must be an integer.
)
uut (
.clk(clk), // System clock
.rst(rst), // Reset, synchronous and active high
.en(en), // Enable strobe for transmitting
.dataIn(dataIn), // [7:0] Data to transmit
.writeStrobe(writeStrobe), // Write data to transmit FIFO
.dataPresent(dataPresent), // FIFO has data still in it
.halfFull(halfFull), // FIFO halfway full
.full(full), // FIFO is completely full. Don't write to it.
.tx(tx) // Transmit bit
);
endmodule
|
/*
134bit pkt format transform MAC core need 8bit pkt format
*/
// ****************************************************************************
// Copyright : NUDT.
// ============================================================================
// FILE NAME : SGMII_TX.v
// CREATE DATE : 2013-12-03
// AUTHOR : ZengQiang
// AUTHOR'S EMAIL : [email protected]
// AUTHOR'S TEL :
// ============================================================================
// RELEASE HISTORY -------------------------------------------------------
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-12-03 ZengQiang Original Verison
// ============================================================================
// KEYWORDS : N/A
// ----------------------------------------------------------------------------
// PURPOSE : 134bit pkt format transform MAC core need 8bit pkt format
// ----------------------------------------------------------------------------
// ============================================================================
// REUSE ISSUES
// Reset Strategy : Async clear,active high
// Clock Domains : ff_rx_clk
// Critical TiminG : N/A
// Instantiations : N/A
// Synthesizable : N/A
// Others : N/A
// ****************************************************************************
module SGMII_TX(
clk,
reset,
ff_tx_clk,
ff_tx_data,//
ff_tx_sop,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_wren,
ff_tx_crc_fwd,//CRC ADD
tx_ff_uflow,
ff_tx_rdy,//core ready
ff_tx_septy,
ff_tx_a_full,
ff_tx_a_empty,
pkt_send_add,
data_in_wrreq,
data_in,
data_in_almostfull,
data_in_valid_wrreq,
data_in_valid );
input clk;
input reset;
input ff_tx_clk;
output [31:0] ff_tx_data;
output [1:0] ff_tx_mod;
output ff_tx_sop;
output ff_tx_eop;
output ff_tx_err;
output ff_tx_wren;
output ff_tx_crc_fwd;
input tx_ff_uflow;
input ff_tx_rdy;
input ff_tx_septy;
input ff_tx_a_full;
input ff_tx_a_empty;
output pkt_send_add;
input data_in_wrreq;
input [133:0] data_in;
output data_in_almostfull;
input data_in_valid_wrreq;
input data_in_valid;
reg [31:0] ff_tx_data;
reg [1:0] ff_tx_mod;
reg ff_tx_sop;
reg ff_tx_eop;
reg ff_tx_err;
reg ff_tx_wren;
reg ff_tx_crc_fwd;
reg pkt_send_add;
reg [133:0] data_in_q_r;
reg [2:0] current_state;
parameter idle_s = 3'b000,
transmit_byte0_s = 3'b001,
transmit_byte1_s = 3'b010,
transmit_byte2_s = 3'b011,
transmit_byte3_s = 3'b100,
discard_s = 3'b101;
always@(posedge ff_tx_clk or negedge reset)
if(!reset) begin
ff_tx_data <= 32'b0;
ff_tx_mod <= 2'b0;
ff_tx_sop <= 1'b0;
ff_tx_eop <= 1'b0;
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b0;
ff_tx_crc_fwd <= 1'b1;
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
data_in_q_r <= 134'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
ff_tx_crc_fwd <= 1'b1;
ff_tx_wren <= 1'b0;
ff_tx_sop <= 1'b0;
ff_tx_eop <= 1'b0;
ff_tx_mod <= 2'b0;
if(ff_tx_rdy == 1'b1) begin
if(!data_in_valid_empty) begin//0:has pkt 1:no pkt
data_in_rdreq <= 1'b1;
data_in_valid_rdreq <= 1'b1;
if(data_in_valid_q == 1'b1) begin//pkt valid
pkt_send_add <= 1'b1;
data_in_q_r <= data_in_q;
ff_tx_sop <= 1'b1;
ff_tx_data <= data_in_q[127:96];
ff_tx_wren <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin//pkt error
pkt_send_add <= 1'b0;
current_state <= discard_s;
end
end
else begin
current_state <= idle_s;
end
end
else begin
current_state <= idle_s;
end
end
transmit_byte0_s: begin
data_in_rdreq <= 1'b0;
if(ff_tx_rdy == 1'b0) begin//MAC core don't ready need wait
current_state <= transmit_byte0_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[127:96];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin//pkt tail
if(data_in_q_r[131:130] == 2'b11)begin
ff_tx_eop <= 1'b1;
ff_tx_mod <= data_in_q_r[129:128];
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else
current_state <= transmit_byte1_s;
end
else begin
current_state <= transmit_byte1_s;
end
end
end
transmit_byte1_s: begin
ff_tx_sop <= 1'b0;
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte1_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[95:64];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:130] == 2'b10)begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else
current_state <= transmit_byte2_s;
end
else begin
current_state <= transmit_byte2_s;
end
end
end
transmit_byte2_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte2_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[63:32];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:130] == 2'b01)begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else
current_state <= transmit_byte3_s;
end
else begin
current_state <= transmit_byte3_s;
end
end
end
transmit_byte3_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte3_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[31:0];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
data_in_q_r <= data_in_q;
current_state <= transmit_byte0_s;
end
end
end
discard_s: begin
data_in_valid_rdreq <= 1'b0;
if(data_in_q[133:132]==2'b10) begin
data_in_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
current_state <= discard_s;
end
end
endcase
end
reg data_in_rdreq;
wire [7:0] data_in_usedw;
assign data_in_almostfull = data_in_usedw[7];
wire [133:0] data_in_q;
asyn_256_134 asyn_256_134(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_wrreq),
.data(data_in),
.rdclk(ff_tx_clk),
.rdreq(data_in_rdreq),
.q(data_in_q),
.wrusedw(data_in_usedw)
);
reg data_in_valid_rdreq;
wire data_in_valid_q;
wire data_in_valid_empty;
asyn_64_1 asyn_64_1(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_valid_wrreq),
.data(data_in_valid),
.rdclk(ff_tx_clk),
.rdreq(data_in_valid_rdreq),
.q(data_in_valid_q),
.rdempty(data_in_valid_empty)
);
endmodule |
Require Import Coq.Sets.Ensembles.
Require Import List.
From OakIFC Require Import
Lattice
Parameters
GenericMap
ModelSemUtils
RuntimeModelPS
State
Events.
Import ListNotations.
Arguments Ensembles.In {U}.
Arguments Ensembles.Add {U}.
Arguments Ensembles.Subtract {U}.
Arguments Ensembles.Singleton {U}.
From RecordUpdate Require Import RecordSet.
Import RecordSetNotations.
Local Open Scope map_scope.
Local Open Scope ev_notation.
(*
This is a copy of EvAugSemantics for partially-secret labels.
This version uses RuntimeModelPS in place of RuntimeModel.
*)
(*
The top-level security condition compares traces involving both states (as
in "state" in RuntimeModelPS.v) and events. This file augments the semantics
in RuntimeModelPS.v with rules that also produce labeled Events (in Events.v)
that represent values that are inputs/outputs to/from nodes. It also builds
traces that are sequences of pairs of states and events. In the future,
events will also represent downgrades of values. These events are abstract
objects that are used in the specification of the security condition.
The "input" event during the read is the one that is really strictly needed.
The model of a node does not contain any state corresponding to values.
So a purely state-based security condition would not say anything about values
that are read by a node.
I considered whether traces can be JUST sequences of events
rather than sequences of state/event pairs. I think the answer is no
because then it might be possible to leak information via
the handles a node has. (Even though the call of a node does not contain
informtion because the choice of call is always essentially non-deterministic,
so the call is a piece of state that probably does not matter at the moment)
When downgrades events are added, a trace might need to be
list (state * (Ensemble event)) (Ensembles are sets)
rather than
list (state * event)
since individual calls might produce more than one event. For example,
when a read call does a declassification it would produce an input event
and a downgrade event.
*)
Definition trace := list (state * event_l).
(* This is used for state/event pairs in EvAug.
* The type is slightly awkward now post refactor *)
Definition head_st (t: trace) :=
match t with
| nil => None
| (s', _)::_ => Some s'
end.
Inductive step_node_ev (id: node_id): call -> state -> state -> event_l -> Prop :=
| SWriteChanEv s nlbl han msg s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (WriteChannel han msg) s s' ->
step_node_ev id (WriteChannel han msg) s s' (nlbl ---> msg)
(* The notations used for events on this last line and others
is in Events.v *)
| SReadChanEv s nlbl han chan msg s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (ReadChannel han) s s' ->
msg_is_head chan msg ->
step_node_ev id (ReadChannel han) s s' (nlbl <--- msg)
| SCreateChanEv s nlbl clbl s':
(* It seems clear that no event is needed since nodes only observe
* contents of channels indirectly via reads *)
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (CreateChannel clbl) s s' ->
step_node_ev id (CreateChannel clbl) s s' (nlbl --- )
| SCreateNodeEv s nlbl new_lbl h s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (CreateNode new_lbl h) s s' ->
step_node_ev id (CreateNode new_lbl h) s s' ( -- nlbl -- )
| SWaitOnChannelsEv s hs nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (WaitOnChannels hs) s s' ->
step_node_ev id (WaitOnChannels hs) s s' (nlbl ---)
| SChannelCloseEv s han nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (ChannelClose han) s s' ->
step_node_ev id (ChannelClose han) s s' (nlbl ---)
| SNodeLabelReadEv s nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id NodeLabelRead s s' ->
step_node_ev id NodeLabelRead s s' (nlbl <--L nlbl)
| SChannelLabelReadEv s han nlbl clbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
(s.(chans) .[?han]).(lbl) = clbl ->
step_node id (ChannelLabelRead han) s s' ->
step_node_ev id (ChannelLabelRead han) s s' (nlbl <--L clbl)
| SInternalEv s nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id Internal s s' ->
step_node_ev id Internal s s' (nlbl ---).
Inductive step_system_ev: state -> state -> event_l -> Prop :=
| SytsemEvSkip s ell: step_system_ev s s (ell ---)
| SystemEvStepNode id n c c' s s' e:
(s.(nodes).[?id]).(obj) = Some n ->
n.(ncall) = c ->
step_node_ev id c s s' e ->
let s'' := (s_set_call s' id c') in
(* Here c' is an arbitrary command. The next ABI call
that the node makes after the one executed here is an arbitrary one
of that node's choosing *)
step_system_ev s s'' e.
(* TODO
Theorem that proves that step_system_ev is sound/complete for step_system.
(* should be trivial ? *)
The reason why there is more than one state transition relation is that the
'events' are just an abstract concept meant to state the security theorems,
so it seemed useful to keep them separate from the main specification of
behavior.
Alternatively, we could just decide that actually including events in the
main specification of behavior is just fine, and then we just replace
step_sytem with step_system_ev.
*)
Inductive step_system_ev_t: trace -> trace -> Prop :=
| StepTrace t s s' e:
head_st t = Some s ->
step_system_ev s s' e ->
step_system_ev_t t ((s', e) :: t).
Inductive step_system_ev_multi: trace -> trace -> Prop :=
| multi_system_ev_refl t t':
step_system_ev_t t t' ->
step_system_ev_multi t t'
| multi_system_ev_tran t1 t2 t3:
step_system_ev_t t2 t3 ->
step_system_ev_multi t1 t2 ->
step_system_ev_multi t1 t3.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_BLACKBOX_V
`define SKY130_FD_SC_HD__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ted Campbell.
//With MULTI_CLK defined shows bug, without it is hidden
`define MULTI_CLK
//bug634
module t (
input i_clk_wr,
input i_clk_rd
);
wire wr$wen;
wire [7:0] wr$addr;
wire [7:0] wr$wdata;
wire [7:0] wr$rdata;
wire rd$wen;
wire [7:0] rd$addr;
wire [7:0] rd$wdata;
wire [7:0] rd$rdata;
wire clk_wr;
wire clk_rd;
`ifdef MULTI_CLK
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_rd;
`else
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_wr;
`endif
FooWr u_wr (
.i_clk ( clk_wr ),
.o_wen ( wr$wen ),
.o_addr ( wr$addr ),
.o_wdata ( wr$wdata ),
.i_rdata ( wr$rdata )
);
FooRd u_rd (
.i_clk ( clk_rd ),
.o_wen ( rd$wen ),
.o_addr ( rd$addr ),
.o_wdata ( rd$wdata ),
.i_rdata ( rd$rdata )
);
FooMem u_mem (
.iv_clk ( {clk_wr, clk_rd } ),
.iv_wen ( {wr$wen, rd$wen } ),
.iv_addr ( {wr$addr, rd$addr } ),
.iv_wdata ( {wr$wdata,rd$wdata} ),
.ov_rdata ( {wr$rdata,rd$rdata} )
);
endmodule
// Memory Writer
module FooWr(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd50 )
cnt <= cnt + 8'd1;
// Write addr in (10,30) if even
assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
assign o_addr = cnt;
assign o_wdata = cnt;
endmodule
// Memory Reader
module FooRd(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
reg [7:0] addr_r;
reg en_r;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd200 )
cnt <= cnt + 8'd1;
// Read data
assign o_wen = 0;
assign o_addr = cnt - 8'd100;
// Track issued read
always @( posedge i_clk )
begin
addr_r <= o_addr;
en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
end
// Display to console 100 cycles after writer
always @( negedge i_clk )
if ( en_r ) begin
`ifdef TEST_VERBOSE
$display( "MEM[%x] == %x", addr_r, i_rdata );
`endif
if (addr_r != i_rdata) $stop;
end
endmodule
// Multi-port memory abstraction
module FooMem(
input [2 -1:0] iv_clk,
input [2 -1:0] iv_wen,
input [2*8-1:0] iv_addr,
input [2*8-1:0] iv_wdata,
output [2*8-1:0] ov_rdata
);
FooMemImpl u_impl (
.a_clk ( iv_clk [0*1+:1] ),
.a_wen ( iv_wen [0*1+:1] ),
.a_addr ( iv_addr [0*8+:8] ),
.a_wdata ( iv_wdata[0*8+:8] ),
.a_rdata ( ov_rdata[0*8+:8] ),
.b_clk ( iv_clk [1*1+:1] ),
.b_wen ( iv_wen [1*1+:1] ),
.b_addr ( iv_addr [1*8+:8] ),
.b_wdata ( iv_wdata[1*8+:8] ),
.b_rdata ( ov_rdata[1*8+:8] )
);
endmodule
// Dual-Port L1 Memory Implementation
module FooMemImpl(
input a_clk,
input a_wen,
input [7:0] a_addr,
input [7:0] a_wdata,
output [7:0] a_rdata,
input b_clk,
input b_wen,
input [7:0] b_addr,
input [7:0] b_wdata,
output [7:0] b_rdata
);
/* verilator lint_off MULTIDRIVEN */
reg [7:0] mem[0:255];
/* verilator lint_on MULTIDRIVEN */
always @( posedge a_clk )
if ( a_wen )
mem[a_addr] <= a_wdata;
always @( posedge b_clk )
if ( b_wen )
mem[b_addr] <= b_wdata;
always @( posedge a_clk )
a_rdata <= mem[a_addr];
always @( posedge b_clk )
b_rdata <= mem[b_addr];
endmodule
|
`timescale 1ns / 1ps
module MAC #(
parameter N = 5,
parameter PIPE = 3,
parameter WIDTH = 16,
parameter M_WIDTH = 2*WIDTH+N-1
)(
input clk,
input sof,
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
output reg [M_WIDTH-1:0] C,
output reg valid
);
reg state;
reg [7:0] n,p;
wire [2*WIDTH-1:0] O;
parameter
IDLE = 1'b0,
MAC = 1'b1;
initial begin
n <= N;
p <= PIPE;
C <= 0;
valid <= 1'b0;
state <= IDLE;
end
always@(posedge clk) begin
case(state)
IDLE: begin
p <= PIPE;
n <= N;
C <= 0;
valid <= 1'b0;
if(sof) begin
if(p > 1)
p <= p-1;
else begin// if ((p == 1) || (p ==0))
p <= 0;
state <= MAC;
end
end
end
MAC: begin
C <= C + O;
n <= n-1;
valid <= 1'b0;
if(n == 1) begin
valid <= 1'b1;
if(!sof)
state <= IDLE;
else begin
n <= N;
//C <= 0;
end
end
if(n == N)
C <= O;
end
endcase
end
MULT mult_16W (
.clk (clk), // input clk
.a (A), // input [15 : 0] a
.b (B), // input [15 : 0] b
.p (O) // output [31 : 0] p
);
endmodule
|
`timescale 1ns / 1ps
/*
* Copyright 2015 Forest Crossman
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
module pwm_demo(
input CLK_100MHz,
input [2:0] ADDRESS,
input [7:0] DATA,
input SW1,
output [7:0] PWM,
output reg [7:0] LED
);
wire [2:0] address;
wire [7:0] data;
wire latch;
assign address = ADDRESS;
assign data = DATA;
assign latch = ~SW1;
reg [7:0] period [0:256-1];
pwm_generator pwm0(.clk(CLK_100MHz), .period(period[0]), .pin(PWM[0]));
pwm_generator pwm1(.clk(CLK_100MHz), .period(period[1]), .pin(PWM[1]));
pwm_generator pwm2(.clk(CLK_100MHz), .period(period[2]), .pin(PWM[2]));
pwm_generator pwm3(.clk(CLK_100MHz), .period(period[3]), .pin(PWM[3]));
pwm_generator pwm4(.clk(CLK_100MHz), .period(period[4]), .pin(PWM[4]));
pwm_generator pwm5(.clk(CLK_100MHz), .period(period[5]), .pin(PWM[5]));
pwm_generator pwm6(.clk(CLK_100MHz), .period(period[6]), .pin(PWM[6]));
pwm_generator pwm7(.clk(CLK_100MHz), .period(period[7]), .pin(PWM[7]));
always @(posedge CLK_100MHz) begin
if (latch) begin
LED <= address;
period[address] <= data;
end
end
endmodule
module pwm_generator(
input clk,
input [7:0] period,
output pin
);
reg [7:0] counter;
reg pin_out;
assign pin = pin_out;
always @(posedge clk) begin
if (counter < period)
counter <= counter + 1;
else begin
counter <= 0;
case (pin)
1'b0: pin_out <= 1;
1'b1: pin_out <= 0;
default: pin_out <= 0;
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_BEHAVIORAL_PP_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_BEHAVIORAL_PP_V |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`define FMT_TXENGUPR32_WR32 7'b10_00000
`define FMT_TXENGUPR32_RD32 7'b00_00000
`define FMT_TXENGUPR32_WR64 7'b11_00000
`define FMT_TXENGUPR32_RD64 7'b01_00000
`define S_TXENGUPR32_MAIN_IDLE 6'b00_0001
`define S_TXENGUPR32_MAIN_RD 6'b00_0010
`define S_TXENGUPR32_MAIN_WR 6'b00_0100
`define S_TXENGUPR32_MAIN_WAIT_0 6'b00_1000
`define S_TXENGUPR32_MAIN_WAIT_1 6'b01_0000
`define S_TXENGUPR32_MAIN_WAIT_2 6'b10_0000
`define S_TXENGUPR32_CAP_RD_WR 4'b0001
`define S_TXENGUPR32_CAP_WR_RD 4'b0010
`define S_TXENGUPR32_CAP_CAP 4'b0100
`define S_TXENGUPR32_CAP_REL 4'b1000
`include "trellis.vh"
`timescale 1ns/1ns
module tx_multiplexer_32
#(
parameter C_PCI_DATA_WIDTH = 9'd32,
parameter C_NUM_CHNL = 4'd12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "XILINX"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY
);
`include "functions.vh"
// Local parameters
localparam C_DATA_DELAY = 6'd1; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rMainState=`S_TXENGUPR32_MAIN_IDLE, _rMainState=`S_TXENGUPR32_MAIN_IDLE;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountStart=0, _rCountStart=0;
reg rCount32=0, _rCount32=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR32_CAP_RD_WR, _rCapState=`S_TXENGUPR32_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [C_DATA_DELAY-1:0] rAddr64=0, _rAddr64=0;
reg [(C_DATA_DELAY*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rLenEQ1=0, _rLenEQ1=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR32_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = (rCapAddr[61:30] != 0);
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR32_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = ((wRdAck)<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_WR_RD);
end
`S_TXENGUPR32_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_RD_WR);
end
`S_TXENGUPR32_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG;
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR32_CAP_REL;
end
`S_TXENGUPR32_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & rMainState[0]) // S_TXENGUPR32_MAIN_IDLE
_rCapState = (`S_TXENGUPR32_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR32_CAP_RD_WR
end
default : begin
_rCapState = `S_TXENGUPR32_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR32_MAIN_IDLE : _rMainState);
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCount32 <= #1 _rCount32;
rWrDataRen <= #1 _rWrDataRen;
end
always @ (*) begin
_rMainState = rMainState;
_rCount = rCount;
_rCountDone = rCountDone;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCount32 = rCount32;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
case (rMainState)
`S_TXENGUPR32_MAIN_IDLE : begin
_rCount = rCapLen;
_rCountDone = (rCapLen == 10'd1);
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCount32 = (rCapAddr[61:30] == 0);
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR32_CAP_REL
_rCountStart = (TXR_META_READY & rCapState[3]);
if (TXR_META_READY & rCapState[3]) // S_TXENGUPR32_CAP_REL
_rMainState = (`S_TXENGUPR32_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR32_MAIN_WR;
end
`S_TXENGUPR32_MAIN_RD : begin
_rMainState = (`S_TXENGUPR32_MAIN_WAIT_1<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_2
end
`S_TXENGUPR32_MAIN_WR : begin
_rCount = rCount - 1'd1;
_rCountDone = (rCount == 2'd2);
if (rCountDone) begin
_rWrDataRen = 0;
_rMainState = (`S_TXENGUPR32_MAIN_WAIT_0<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_1
end
end
`S_TXENGUPR32_MAIN_WAIT_0 : begin
_rMainState = `S_TXENGUPR32_MAIN_WAIT_1;
end
`S_TXENGUPR32_MAIN_WAIT_1 : begin
_rMainState = `S_TXENGUPR32_MAIN_WAIT_2;
end
`S_TXENGUPR32_MAIN_WAIT_2 : begin
_rMainState = `S_TXENGUPR32_MAIN_IDLE;
end
default : begin
_rMainState = `S_TXENGUPR32_MAIN_IDLE;
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rCountChnl[3:0];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rLen <= #1 _rLen;
rLenEQ1 <= #1 _rLenEQ1;
rValid <= #1 _rValid;
end
always @ (*) begin
_rWnR = ((rWnR<<1) | rCapIsWr);
_rChnl = ((rChnl<<4) | rCountChnl);
_rTag = ((rTag<<8) | (8'd0 | rCountTag));
_rAddr = ((rAddr<<62) | rCapAddr);
_rAddr64 = ((rAddr64<<1) | rCapAddr64);
_rLen = ((rLen<<10) | rCapLen);
_rLenEQ1 = ((rLenEQ1<<1) | (rCapLen == 10'd1));
_rValid = ((rValid<<1) | (rMainState[2] | rMainState[1])); // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
_rDone = rDone<<1 | rCountDone;
_rStart = rStart<<1 | rCountStart;
end
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCapAddr,2'b00};
assign TXR_META_LENGTH = rCapLen;
assign TXR_META_LDWBE = rCapLen == 10'd1 ? 0 : 4'b1111;
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4B_PP_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRTP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtp (
RESET_B,
D ,
GATE ,
Q
);
input RESET_B;
input D ;
input GATE ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__CLKINVLP_BEHAVIORAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_BEHAVIORAL_V |
module one0_handler (oh1,control,literal);
input [13:0] oh1;
output reg [15:0] literal;
output reg [25:0] control;
always begin
case (oh1[13:9])
5'b110xx: begin assign control = {8'b01100000,oh1[10:8],14'b000101};
assign literal={oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7:0]}; end //brz
5'b111xx: begin assign control = {8'b01100000,oh1[10:8],14'b000101};
assign literal={oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7],oh1[7:0]}; end //brn
5'b100xx: begin assign control = {5'b00000,oh1[10:8],17'b00000000101000010};
assign literal={4'b0000,oh1[7:0]}; end
5'b101xx: begin assign control = {8'b01100000,oh1[10:8],14'b00010110100000};
assign literal={4'b0000,oh1[7:0]}; end
5'b01100: begin assign control = {8'b01100000,oh1[10:8],14'b00010010000001};
assign literal={3'b000,oh1[8:0]}; end
5'b01101: begin assign control = {11'b01100000000,oh1[10:8],11'b11010000001};
assign literal={3'b000,oh1[8:0]}; end
5'b00010: begin assign control = {5'b00000,oh1[10:8],14'b00000000000110};
assign literal={3'b000,oh1[8:0]}; end
endcase
end
endmodule |
//issue stage: if the instruction is a store, store in the head
//execute: if the instruction is a load, check if there's store in the store queue that has address match, if yes forwarding
//store will complete in the same stage as the load and other instructions to make the ROB design easier
//if a load and a store in the same time, load goes first, head store goes in next cycle
//retire: set the store queue entry ready bit using ROB# to match
module store_queue(
input clk, rst,
input issue, mem_wen,
input mem_ren, //this is a load, don't release a store at this cycle, since d-mem is single port
input [31:0] rs_data, //used to calculating load/store address
input [31:0] rt_data, //data for store
//from the load-store station
input [15:0] immed,
input [3:0] rob_in,
input [5:0] p_rd_in,
input stall_hazard,
//from ROB, for retire stage, set the ready bit in
input retire_ST,
input [3:0] retire_rob,
input recover,
input [3:0] rec_rob,
output sq_full,
//////////////these five signals go to the arbiter,
output reg isLS,
output [31:0] load_result,
output reg [5:0] ls_p_rd,
output reg [3:0] ls_rob,
output reg ls_RegDest
//this signal is the write enable signal for store queue, it indicates the complete of the store instruction
);
///////////////***************************store queue logic********************************//////////////////////
reg [3:0] head, tail;
reg [1:0] head_addr;
reg [2:0] counter;
wire read, write;
wire head_retired;
//issue head store to data memory when the head is ready, and no load executed
assign read = !stall_hazard && !recover && head_retired && !mem_ren;
//get instruction from the reservation station if it is a store and it is issued
assign write = issue && mem_wen && !stall_hazard && !recover && !sq_full;
//counter recording full or empty status
always @(posedge clk or negedge rst) begin
if (!rst)
counter <= 3'b000;
else if (write && read)
counter <= counter;
else if (write)
counter <= counter + 1;
else if (read)
counter <= counter - 1;
end
assign sq_full = (counter == 3'b100);
//increase head when read, increase tail when write
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'b0001;
head_addr <= 2'b00;
tail <= 4'b0001;
end
else begin
if (write) begin
tail <= {tail[2:0], tail[3]};
end
if (read) begin
head <= {head[2:0], head[3]};
head_addr <= head_addr + 1;
end
end
end
reg [31:0] value_queue [0:3];
reg [15:0] addr_queue [0:3];
reg [3:0] rob_queue [0:3];
reg [2:0] control_queue [0:3]; //[0]:valid, [1]:mem_wen [2]: ready
//reg [1:0] priority_queue [0:3]; //recoding priority, deciding which store is the youngest
////////////////////////memory address generator
wire [31:0] address_in;
assign address_in = rs_data + {{16{immed[15]}}, immed};
/////////////////combinational logic, comparators////////////////////////////
wire [3:0] rt_rob_match_array, rec_rob_match_array, addr_match_array;
genvar i;
generate for(i = 0; i < 4; i = i + 1) begin : combinational
//for retire stage, set the ready bit
assign rt_rob_match_array[i] = (rob_queue[i] == retire_rob) && retire_ST && control_queue[i][0] && control_queue[i][1];
//for recovery, flush the entry if rob number matches, and recover is high
assign rec_rob_match_array[i] = (rob_queue[i] == rec_rob) && recover && control_queue[i][0] && control_queue[i][1];
//for incoming load instruction, address match when valid, mem_ren is 1,
assign addr_match_array[i] = (addr_queue[i] == address_in[15:0]) && control_queue[i][0] && control_queue[i][1] && mem_ren;
end
endgenerate
////////////////////////sequential logic/////////////////////////////////////////
genvar j;
generate for (j = 0; j < 4; j = j + 1) begin : sequential
always @(posedge clk or negedge rst) begin
if (!rst) begin
value_queue[j] <= 0;
addr_queue[j] <= 0;
rob_queue[j] <= 0;
control_queue[j] <= 0;
end
else if (write && tail[j]) begin //this is the tail, match cannot happen on tail,
value_queue[j] <= rt_data;
addr_queue[j] <= address_in[15:0]; //the memory will only use 16 bit memory address
rob_queue[j] <= rob_in;
control_queue[j] <= {1'b0, mem_wen, 1'b1};
end else begin
if (rt_rob_match_array[j]) begin //set ready bit
control_queue[j][2] <= 1'b1;
end
if (rec_rob_match_array[j]) begin //flush this entry
control_queue[j][1] <= 1'b0; //only need to flush mem_wen, thus it cannot write to D-Mem, and cannot
end //match with incoming load, retired rob
if (read && head[j]) begin
control_queue[j][0] <= 1'b0; //set to invalid
end
end
end
end
endgenerate
assign head_retired = control_queue[head_addr][2] && control_queue[head_addr][0];
///////////////***************************end of store queue logic********************************//////////////////////
//////////////////////////////////////////data memory and load forwarding logic/////////////////////////
//////////////signals from store queue (load instruction will also use this address) to the memory
wire [31:0] store_data;
wire [15:0] mem_addr; //can be store addr or load addr
wire mem_wen_out;
wire mem_ren_out;
wire [31:0] load_data_from_mem;
wire [31:0] fwd_data_int;
wire isFwd;
assign store_data = value_queue[head_addr];
assign mem_addr = mem_ren_out ? address_in : addr_queue[head_addr];
assign mem_wen_out = (& control_queue[head_addr]) && !mem_ren;
assign mem_ren_out = mem_ren && issue;
////////////this may lead to errors if one stores to same address twice within 4 stores
assign fwd_data_int = addr_match_array[0] ? value_queue[0] :
addr_match_array[1] ? value_queue[1] :
addr_match_array[2] ? value_queue[2] :
addr_match_array[3] ? value_queue[3] : 32'h00000000;
assign isFwd = |addr_match_array; //if any of the entry matches, forwarding the data to load
/////////////////////////////data memory, data available at next clock edge////////////////////
data_mem i_data_mem(.clk(clk), .en(mem_ren_out), .we(mem_wen_out), .wdata(store_data), .addr(mem_addr[13:0]), .rdata(load_data_from_mem));
reg isFwd_reg;
reg [31:0] fwd_data_reg;
//////delay forwarding data by 1 cycle, because the load data from another path(memory) has 1 cycle delay
always @(posedge clk or negedge rst) begin
if (!rst) begin
fwd_data_reg <= 0;
isFwd_reg <= 0;
isLS <= 0;
ls_p_rd <= 0;
ls_rob <= 0;
ls_RegDest <= 0;
end
else begin
fwd_data_reg <= fwd_data_int;
isFwd_reg <= isFwd;
isLS <= mem_ren_out | write;
ls_p_rd <= p_rd_in;
ls_rob <= rob_in;
ls_RegDest <= mem_ren && issue;
end
end
assign load_result = isFwd_reg ? fwd_data_reg : load_data_from_mem;
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC
*/
module eth_mac_1g #
(
parameter DATA_WIDTH = 8,
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* GMII interface
*/
input wire [DATA_WIDTH-1:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [DATA_WIDTH-1:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_start_packet,
output wire tx_error_underflow,
output wire rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
axis_gmii_rx #(
.DATA_WIDTH(DATA_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_gmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.clk_enable(rx_clk_enable),
.mii_select(rx_mii_select),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_gmii_tx #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_gmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.clk_enable(tx_clk_enable),
.mii_select(tx_mii_select),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
endmodule
|
/*
* PS2 Wishbone 8042 compatible keyboard controller
*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
* adapted from the opencores keyboard controller from John Clayton
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/100ps
`define TOTAL_BITS 11
`define RELEASE_CODE 16'hF0
`define LEFT_SHIFT 16'h12
`define RIGHT_SHIFT 16'h59
module ps2_keyb (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
output reg [7:0] wb_dat_o, // scancode
output reg wb_tgc_o, // intr
input wb_tgc_i, // inta
// PS2 PAD signals
inout ps2_clk_,
inout ps2_data_
);
// Parameter declarations
// The timer value can be up to (2^bits) inclusive.
parameter TIMER_60USEC_VALUE_PP = 1920; // Number of sys_clks for 60usec.
parameter TIMER_60USEC_BITS_PP = 11; // Number of bits needed for timer
parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
parameter TRAP_SHIFT_KEYS_PP = 0; // Default: No shift key trap.
// State encodings, provided as parameters
// for flexibility to the one instantiating the module.
// In general, the default values need not be changed.
// State "m1_rx_clk_l" has been chosen on purpose. Since the input
// synchronizing flip-flops initially contain zero, it takes one clk
// for them to update to reflect the actual (idle = high) status of
// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
// allows the state machine to transition to m1_rx_clk_h when the true
// values of the input signals become present at the outputs of the
// synchronizing flip-flops. This initial transition is harmless, and it
// eliminates the need for a "reset" pulse before the interface can operate.
parameter m1_rx_clk_h = 1;
parameter m1_rx_clk_l = 0;
parameter m1_rx_falling_edge_marker = 13;
parameter m1_rx_rising_edge_marker = 14;
parameter m1_tx_force_clk_l = 3;
parameter m1_tx_first_wait_clk_h = 10;
parameter m1_tx_first_wait_clk_l = 11;
parameter m1_tx_reset_timer = 12;
parameter m1_tx_wait_clk_h = 2;
parameter m1_tx_clk_h = 4;
parameter m1_tx_clk_l = 5;
parameter m1_tx_wait_keyboard_ack = 6;
parameter m1_tx_done_recovery = 7;
parameter m1_tx_error_no_keyboard_ack = 8;
parameter m1_tx_rising_edge_marker = 9;
// Nets and registers
wire rx_output_event;
wire rx_output_strobe;
wire rx_shifting_done;
wire tx_shifting_done;
wire timer_60usec_done;
wire timer_5usec_done;
wire released;
wire [6:0] xt_code;
reg [3:0] bit_count;
reg [3:0] m1_state;
reg [3:0] m1_next_state;
reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
reg ps2_clk_s; // Synchronous version of this input
reg ps2_data_s; // Synchronous version of this input
reg enable_timer_60usec;
reg enable_timer_5usec;
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
reg [`TOTAL_BITS-1:0] q;
reg hold_released; // Holds prior value, cleared at rx_output_strobe
// Module instantiation
translate_8042 tr0 (
.at_code (q[7:1]),
.xt_code (xt_code)
);
// Continuous assignments
// This signal is high for one clock at the end of the timer count.
assign rx_shifting_done = (bit_count == `TOTAL_BITS);
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
assign rx_output_event = (rx_shifting_done
&& ~released
);
assign rx_output_strobe = (rx_shifting_done
&& ~released
&& ( (TRAP_SHIFT_KEYS_PP == 0)
|| ( (q[8:1] != `RIGHT_SHIFT)
&&(q[8:1] != `LEFT_SHIFT)
)
)
);
assign ps2_clk_ = ps2_clk_hi_z ? 1'bZ : 1'b0;
assign ps2_data_ = ps2_data_hi_z ? 1'bZ : 1'b0;
assign timer_60usec_done =
(timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
// Create the signals which indicate special scan codes received.
// These are the "unlatched versions."
//assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
// Behaviour
// intr
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0
: ((rx_output_strobe & !wb_tgc_i) ? 1'b1
: (wb_tgc_o ? !wb_tgc_i : 1'b0));
// This is the shift register
always @(posedge wb_clk_i)
if (wb_rst_i) q <= 0;
// else if (((m1_state == m1_rx_clk_h) && ~ps2_clk_s)
else if ( (m1_state == m1_rx_falling_edge_marker)
||(m1_state == m1_tx_rising_edge_marker) )
q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
// This is the 60usec timer counter
always @(posedge wb_clk_i)
if (~enable_timer_60usec) timer_60usec_count <= 0;
else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
// This is the 5usec timer counter
always @(posedge wb_clk_i)
if (~enable_timer_5usec) timer_5usec_count <= 0;
else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
// Input "synchronizing" logic -- synchronizes the inputs to the state
// machine clock, thus avoiding errors related to
// spurious state machine transitions.
//
// Since the initial state of registers is zero, and the idle state
// of the ps2_clk and ps2_data lines is "1" (due to pullups), the
// "sense" of the ps2_clk_s signal is inverted from the true signal.
// This allows the state machine to "come up" in the correct
always @(posedge wb_clk_i)
begin
ps2_clk_s <= ps2_clk_;
ps2_data_s <= ps2_data_;
end
// State transition logic
always @(m1_state
or q
or tx_shifting_done
or ps2_clk_s
or ps2_data_s
or timer_60usec_done
or timer_5usec_done
)
begin : m1_state_logic
// Output signals default to this value,
// unless changed in a state condition.
ps2_clk_hi_z <= 1;
ps2_data_hi_z <= 1;
enable_timer_60usec <= 0;
enable_timer_5usec <= 0;
case (m1_state)
m1_rx_clk_h :
begin
enable_timer_60usec <= 1;
if (~ps2_clk_s)
m1_next_state <= m1_rx_falling_edge_marker;
else m1_next_state <= m1_rx_clk_h;
end
m1_rx_falling_edge_marker :
begin
enable_timer_60usec <= 0;
m1_next_state <= m1_rx_clk_l;
end
m1_rx_rising_edge_marker :
begin
enable_timer_60usec <= 0;
m1_next_state <= m1_rx_clk_h;
end
m1_rx_clk_l :
begin
enable_timer_60usec <= 1;
if (ps2_clk_s)
m1_next_state <= m1_rx_rising_edge_marker;
else m1_next_state <= m1_rx_clk_l;
end
m1_tx_reset_timer :
begin
enable_timer_60usec <= 0;
m1_next_state <= m1_tx_force_clk_l;
end
m1_tx_force_clk_l :
begin
enable_timer_60usec <= 1;
ps2_clk_hi_z <= 0; // Force the ps2_clk line low.
if (timer_60usec_done)
m1_next_state <= m1_tx_first_wait_clk_h;
else m1_next_state <= m1_tx_force_clk_l;
end
m1_tx_first_wait_clk_h :
begin
enable_timer_5usec <= 1;
ps2_data_hi_z <= 0; // Start bit.
if (~ps2_clk_s && timer_5usec_done)
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end
// This state must be included because the device might possibly
// delay for up to 10 milliseconds before beginning its clock pulses.
// During that waiting time, we cannot drive the data (q[0]) because it
// is possibly 1, which would cause the keyboard to abort its receive
// and the expected clocks would then never be generated.
m1_tx_first_wait_clk_l :
begin
ps2_data_hi_z <= 0;
if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
else m1_next_state <= m1_tx_first_wait_clk_l;
end
m1_tx_wait_clk_h :
begin
enable_timer_5usec <= 1;
ps2_data_hi_z <= q[0];
if (ps2_clk_s && timer_5usec_done)
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end
m1_tx_rising_edge_marker :
begin
ps2_data_hi_z <= q[0];
m1_next_state <= m1_tx_clk_h;
end
m1_tx_clk_h :
begin
ps2_data_hi_z <= q[0];
if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
else m1_next_state <= m1_tx_clk_h;
end
m1_tx_clk_l :
begin
ps2_data_hi_z <= q[0];
if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
else m1_next_state <= m1_tx_clk_l;
end
m1_tx_wait_keyboard_ack :
begin
if (~ps2_clk_s && ps2_data_s)
m1_next_state <= m1_tx_error_no_keyboard_ack;
else if (~ps2_clk_s && ~ps2_data_s)
m1_next_state <= m1_tx_done_recovery;
else m1_next_state <= m1_tx_wait_keyboard_ack;
end
m1_tx_done_recovery :
begin
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
else m1_next_state <= m1_tx_done_recovery;
end
m1_tx_error_no_keyboard_ack :
begin
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
else m1_next_state <= m1_tx_error_no_keyboard_ack;
end
default : m1_next_state <= m1_rx_clk_h;
endcase
end
// State register
always @(posedge wb_clk_i)
begin : m1_state_register
if (wb_rst_i) m1_state <= m1_rx_clk_h;
else m1_state <= m1_next_state;
end
// wb_dat_o - scancode
always @(posedge wb_clk_i)
if (wb_rst_i) wb_dat_o <= 8'b0;
else wb_dat_o <=
(rx_output_strobe && q[8:1]) ? (q[8] ? q[8:1]
: {hold_released,xt_code})
: wb_dat_o;
// This is the bit counter
always @(posedge wb_clk_i)
begin
if (wb_rst_i
|| rx_shifting_done
|| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
) bit_count <= 0; // normal reset
else if (timer_60usec_done
&& (m1_state == m1_rx_clk_h)
&& (ps2_clk_s)
) bit_count <= 0; // rx watchdog timer reset
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
||(m1_state == m1_tx_rising_edge_marker) // increment for tx
)
bit_count <= bit_count + 1;
end
// Store the special scan code status bits
// Not the final output, but an intermediate storage place,
// until the entire set of output data can be assembled.
always @(posedge wb_clk_i)
if (wb_rst_i || rx_output_event) hold_released <= 0;
else if (rx_shifting_done && released) hold_released <= 1;
endmodule
module translate_8042 (
input [6:0] at_code,
output reg [6:0] xt_code
);
// Behaviour
always @(at_code)
case (at_code)
7'h00: xt_code <= 7'h7f;
7'h01: xt_code <= 7'h43;
7'h02: xt_code <= 7'h41;
7'h03: xt_code <= 7'h3f;
7'h04: xt_code <= 7'h3d;
7'h05: xt_code <= 7'h3b;
7'h06: xt_code <= 7'h3c;
7'h07: xt_code <= 7'h58;
7'h08: xt_code <= 7'h64;
7'h09: xt_code <= 7'h44;
7'h0a: xt_code <= 7'h42;
7'h0b: xt_code <= 7'h40;
7'h0c: xt_code <= 7'h3e;
7'h0d: xt_code <= 7'h0f;
7'h0e: xt_code <= 7'h29;
7'h0f: xt_code <= 7'h59;
7'h10: xt_code <= 7'h65;
7'h11: xt_code <= 7'h38;
7'h12: xt_code <= 7'h2a;
7'h13: xt_code <= 7'h70;
7'h14: xt_code <= 7'h1d;
7'h15: xt_code <= 7'h10;
7'h16: xt_code <= 7'h02;
7'h17: xt_code <= 7'h5a;
7'h18: xt_code <= 7'h66;
7'h19: xt_code <= 7'h71;
7'h1a: xt_code <= 7'h2c;
7'h1b: xt_code <= 7'h1f;
7'h1c: xt_code <= 7'h1e;
7'h1d: xt_code <= 7'h11;
7'h1e: xt_code <= 7'h03;
7'h1f: xt_code <= 7'h5b;
7'h20: xt_code <= 7'h67;
7'h21: xt_code <= 7'h2e;
7'h22: xt_code <= 7'h2d;
7'h23: xt_code <= 7'h20;
7'h24: xt_code <= 7'h12;
7'h25: xt_code <= 7'h05;
7'h26: xt_code <= 7'h04;
7'h27: xt_code <= 7'h5c;
7'h28: xt_code <= 7'h68;
7'h29: xt_code <= 7'h39;
7'h2a: xt_code <= 7'h2f;
7'h2b: xt_code <= 7'h21;
7'h2c: xt_code <= 7'h14;
7'h2d: xt_code <= 7'h13;
7'h2e: xt_code <= 7'h06;
7'h2f: xt_code <= 7'h5d;
7'h30: xt_code <= 7'h69;
7'h31: xt_code <= 7'h31;
7'h32: xt_code <= 7'h30;
7'h33: xt_code <= 7'h23;
7'h34: xt_code <= 7'h22;
7'h35: xt_code <= 7'h15;
7'h36: xt_code <= 7'h07;
7'h37: xt_code <= 7'h5e;
7'h38: xt_code <= 7'h6a;
7'h39: xt_code <= 7'h72;
7'h3a: xt_code <= 7'h32;
7'h3b: xt_code <= 7'h24;
7'h3c: xt_code <= 7'h16;
7'h3d: xt_code <= 7'h08;
7'h3e: xt_code <= 7'h09;
7'h3f: xt_code <= 7'h5f;
7'h40: xt_code <= 7'h6b;
7'h41: xt_code <= 7'h33;
7'h42: xt_code <= 7'h25;
7'h43: xt_code <= 7'h17;
7'h44: xt_code <= 7'h18;
7'h45: xt_code <= 7'h0b;
7'h46: xt_code <= 7'h0a;
7'h47: xt_code <= 7'h60;
7'h48: xt_code <= 7'h6c;
7'h49: xt_code <= 7'h34;
7'h4a: xt_code <= 7'h35;
7'h4b: xt_code <= 7'h26;
7'h4c: xt_code <= 7'h27;
7'h4d: xt_code <= 7'h19;
7'h4e: xt_code <= 7'h0c;
7'h4f: xt_code <= 7'h61;
7'h50: xt_code <= 7'h6d;
7'h51: xt_code <= 7'h73;
7'h52: xt_code <= 7'h28;
7'h53: xt_code <= 7'h74;
7'h54: xt_code <= 7'h1a;
7'h55: xt_code <= 7'h0d;
7'h56: xt_code <= 7'h62;
7'h57: xt_code <= 7'h6e;
7'h58: xt_code <= 7'h3a;
7'h59: xt_code <= 7'h36;
7'h5a: xt_code <= 7'h1c;
7'h5b: xt_code <= 7'h1b;
7'h5c: xt_code <= 7'h75;
7'h5d: xt_code <= 7'h2b;
7'h5e: xt_code <= 7'h63;
7'h5f: xt_code <= 7'h76;
7'h60: xt_code <= 7'h55;
7'h61: xt_code <= 7'h56;
7'h62: xt_code <= 7'h77;
7'h63: xt_code <= 7'h78;
7'h64: xt_code <= 7'h79;
7'h65: xt_code <= 7'h7a;
7'h66: xt_code <= 7'h0e;
7'h67: xt_code <= 7'h7b;
7'h68: xt_code <= 7'h7c;
7'h69: xt_code <= 7'h4f;
7'h6a: xt_code <= 7'h7d;
7'h6b: xt_code <= 7'h4b;
7'h6c: xt_code <= 7'h47;
7'h6d: xt_code <= 7'h7e;
7'h6e: xt_code <= 7'h7f;
7'h6f: xt_code <= 7'h6f;
7'h70: xt_code <= 7'h52;
7'h71: xt_code <= 7'h53;
7'h72: xt_code <= 7'h50;
7'h73: xt_code <= 7'h4c;
7'h74: xt_code <= 7'h4d;
7'h75: xt_code <= 7'h48;
7'h76: xt_code <= 7'h01;
7'h77: xt_code <= 7'h45;
7'h78: xt_code <= 7'h57;
7'h79: xt_code <= 7'h4e;
7'h7a: xt_code <= 7'h51;
7'h7b: xt_code <= 7'h4a;
7'h7c: xt_code <= 7'h37;
7'h7d: xt_code <= 7'h49;
7'h7e: xt_code <= 7'h46;
7'h7f: xt_code <= 7'h54;
endcase
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 11:08:00 09/12/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: Key_Command_Controller
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Key Command Controller
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Key_Command_Controller
(
// Key Input Signals
input KEY_CLEAR,
input KEY_ADD,
input KEY_SUB,
// Command Signals
input CMD_DONE,
output reg CMD_CLEAR,
output reg CMD_COMPUTE,
output reg CMD_OPERATION,
// System Signals
input CLK,
input RESET
);
//
// BCD Binary Encoder State Machine
//
reg [3:0] State;
localparam [3:0]
S0 = 4'b0001,
S1 = 4'b0010,
S2 = 4'b0100,
S3 = 4'b1000;
reg [1:0] key_reg;
always @(posedge CLK, posedge RESET)
begin
if (RESET)
begin
key_reg <= 2'h0;
CMD_CLEAR <= 1'b0;
CMD_COMPUTE <= 1'b0;
CMD_OPERATION <= 1'b0;
State <= S0;
end
else
begin
case (State)
S0 :
begin
// Capture Keys
key_reg <= { KEY_SUB, KEY_ADD };
// Wait for a Key Input
if (KEY_CLEAR)
State <= S2;
else if (KEY_ADD | KEY_SUB)
State <= S1;
end
S1 :
begin
// Set the operation
case (key_reg)
2'b01 : CMD_OPERATION <= 1'b0; // Add
2'b10 : CMD_OPERATION <= 1'b1; // Sub
default : CMD_OPERATION <= 1'b0; // Invalid
endcase
// Only start computation for a valid key input
if (^key_reg)
CMD_COMPUTE <= 1'b1;
// If valid wait for command to finish, otherwise abort.
if (^key_reg)
State <= S3;
else
State <= S0;
end
S2 :
begin
// Set the Clear Command
CMD_CLEAR <= 1'b1;
State <= S3;
end
S3 :
begin
// Clear the Command signals
CMD_CLEAR <= 1'b0;
CMD_COMPUTE <= 1'b0;
// Wait for Command to finish
if (CMD_DONE)
State <= S0;
end
endcase
end
end
endmodule
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* as1: st assigns X to 3 *)
(* as2: st assigns X to a value less than or equal to the value it assigns to Y *)
(* as3: st assigns X to 3 or the value it assigns to Y *)
(* as4: st assigns Z to the a value beneath the square root of X
and above its predecessor *)
(* as5: for any st, st implies true *)
(* as6: st is not constructible *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(* 1: forall endstates of c, X = 5*)
(* 2: c adds 5 to X in all its endstates *)
(* 3: if x <= y in st, y <= x in st' where c / st || st' *)
(* 4: c doesn't terminate *)
(* 5: c assigns Y to real_fact X *)
(* 6: forall endstates of c, z >= floor (sqrt m) and z <= ceil (sqrt m) *)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Axiom functional_extensionality : forall A B (f g : A -> B), (forall x, f x = g x) -> f = g.
Lemma update_overwrite : forall st i a1 a2,
update (update st i a1) i a2 = update st i a2.
Proof. intros. apply functional_extensionality. intros.
unfold update. destruct (eq_id_dec i x); auto. Qed.
Lemma update_same_id : forall st i, update st i (st i) = st.
Proof. intros. apply functional_extensionality. intros.
unfold update. destruct (eq_id_dec i x); subst; auto. Qed.
Theorem hoare_asgn_fwd :
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros m a P. split; inversion H0; inversion H; subst.
rewrite update_overwrite. rewrite update_same_id. assumption.
rewrite update_overwrite. rewrite update_same_id. rewrite update_eq.
reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}
*)
(* This rule was proposed by Nick Giannarakis and Zoe Paraskevopoulou. *)
Theorem hoare_asgn_fwd_exists :
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}.
Proof.
intros. intro. intros. inversion H; subst.
exists (st X). rewrite update_overwrite. rewrite update_same_id.
rewrite update_eq. split; auto. Qed.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{ P' }} c {{ Q }} ->
P ->> P' ->
{{ P }} c {{ Q }}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] and
[hoare_consequence_pre] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
(* FILL IN HERE *) admit.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ####################################################### *)
(** * Hoare Logic: So Far *)
(**
Idea: create a _domain specific logic_ for reasoning about properties of Imp programs.
- This hides the low-level details of the semantics of the program
- Leads to a compositional reasoning process
The basic structure is given by _Hoare triples_ of the form:
{{P}} c {{Q}}
]]
- [P] and [Q] are predicates about the state of the Imp program
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
*)
(** ** Hoare Logic Rules (so far) *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
(* FILL IN HERE *) Admitted.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, prove formally that your rule is precise enough
to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. intro. intros. inversion H. Qed.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** *** *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(**
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
*)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
*)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(**
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** *** *)
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall st st' b c,
ceval st c st' ->
beval st' b = true ->
ceval st (REPEAT c UNTIL b END) st'
| E_RepeatLoop : forall st st' st'' b c,
ceval st c st' ->
beval st' b = false ->
ceval st' (REPEAT c UNTIL b END) st'' ->
ceval st (REPEAT c UNTIL b END) st''
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_RepeatEnd" | Case_aux c "E_RepeatLoop"
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof. constructor; try eapply E_Seq; try constructor; auto. Qed.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
Theorem ceval_deterministic : forall st c st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof. intros. generalize dependent st2.
ceval_cases (induction H) Case; intros st2 H';
inversion H'; subst; auto.
Case "E_Seq".
assert (st' = st'0). apply IHceval1. apply H4.
apply IHceval2. rewrite H1. apply H6.
Case "E_IfTrue". rewrite H6 in H. inversion H.
Case "E_IfFalse". rewrite H6 in H. inversion H.
Case "E_WhileEnd". rewrite H2 in H. inversion H.
Case "E_WhileLoop".
rewrite H6 in H. inversion H.
assert (st' = st'0). apply IHceval1. apply H6.
subst. apply IHceval2. apply H8.
Case "E_RepeatEnd".
assert (st' = st'0). apply IHceval. apply H3. subst.
rewrite H5 in H0. inversion H0.
Case "E_RepeatLoop".
assert (st' = st2).
apply IHceval1. apply H5.
subst. rewrite H0 in H7. inversion H7.
assert (st' = st'0).
apply IHceval1. apply H4.
subst. apply IHceval2. apply H8.
Qed.
Theorem hoare_repeat :
forall (P : Assertion) (c : com) (b : bexp),
{{ P }} c {{ P }} ->
{{ P }} REPEAT c UNTIL b END {{ fun st => P st /\ bassn b st }}.
Proof. intros P c b H st st' Hc Hp.
remember (REPEAT c UNTIL b END).
ceval_cases (induction Hc) Case; inversion Heqc0; subst; clear Heqc0.
Case "E_RepeatEnd". split; auto. eapply H. apply Hc. apply Hp.
Case "E_RepeatLoop". apply IHHc2; auto. eapply H. apply Hc1. apply Hp.
Qed.
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
fun st => forall n, (HAVOC X) / st || update st X n -> Q (update st X n).
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof. intros Q X st st' He Hp. inversion He; subst. apply Hp. apply He. Qed.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Complete List of Hoare Logic Rules *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(* $Date: 2014-02-27 16:56:35 -0500 (Thu, 27 Feb 2014) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DECAPHETAP_FUNCTIONAL_PP_V
/**
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decaphetap (
VPWR,
VGND,
VPB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_FUNCTIONAL_PP_V |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id: Logic.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
Set Implicit Arguments.
Require Import Notations.
(** * Propositional connectives *)
(** [True] is the always true proposition *)
Inductive True : Prop :=
I : True.
(** [False] is the always false proposition *)
Inductive False : Prop :=.
(** [not A], written [~A], is the negation of [A] *)
Definition not (A:Prop) := A -> False.
Notation "~ x" := (not x) : type_scope.
Hint Unfold not: core.
(** [and A B], written [A /\ B], is the conjunction of [A] and [B]
[conj p q] is a proof of [A /\ B] as soon as
[p] is a proof of [A] and [q] a proof of [B]
[proj1] and [proj2] are first and second projections of a conjunction *)
Inductive and (A B:Prop) : Prop :=
conj : A -> B -> A /\ B
where "A /\ B" := (and A B) : type_scope.
Section Conjunction.
Variables A B : Prop.
Theorem proj1 : A /\ B -> A.
Proof.
destruct 1; trivial.
Qed.
Theorem proj2 : A /\ B -> B.
Proof.
destruct 1; trivial.
Qed.
End Conjunction.
(** [or A B], written [A \/ B], is the disjunction of [A] and [B] *)
Inductive or (A B:Prop) : Prop :=
| or_introl : A -> A \/ B
| or_intror : B -> A \/ B
where "A \/ B" := (or A B) : type_scope.
(** [iff A B], written [A <-> B], expresses the equivalence of [A] and [B] *)
Definition iff (A B:Prop) := (A -> B) /\ (B -> A).
Notation "A <-> B" := (iff A B) : type_scope.
Section Equivalence.
Theorem iff_refl : forall A:Prop, A <-> A.
Proof.
split; auto.
Qed.
Theorem iff_trans : forall A B C:Prop, (A <-> B) -> (B <-> C) -> (A <-> C).
Proof.
intros A B C [H1 H2] [H3 H4]; split; auto.
Qed.
Theorem iff_sym : forall A B:Prop, (A <-> B) -> (B <-> A).
Proof.
intros A B [H1 H2]; split; auto.
Qed.
End Equivalence.
Hint Unfold iff: extcore.
(** Some equivalences *)
Theorem neg_false : forall A : Prop, ~ A <-> (A <-> False).
Proof.
intro A; unfold not; split.
intro H; split; [exact H | intro H1; elim H1].
intros [H _]; exact H.
Qed.
Theorem and_cancel_l : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((A /\ B <-> A /\ C) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem and_cancel_r : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((B /\ A <-> C /\ A) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem and_comm : forall A B : Prop, A /\ B <-> B /\ A.
Proof.
intros; tauto.
Qed.
Theorem and_assoc : forall A B C : Prop, (A /\ B) /\ C <-> A /\ B /\ C.
Proof.
intros; tauto.
Qed.
Theorem or_cancel_l : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((A \/ B <-> A \/ C) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem or_cancel_r : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((B \/ A <-> C \/ A) <-> (B <-> C)).
Proof.
intros; tauto.
Qed.
Theorem or_comm : forall A B : Prop, (A \/ B) <-> (B \/ A).
Proof.
intros; tauto.
Qed.
Theorem or_assoc : forall A B C : Prop, (A \/ B) \/ C <-> A \/ B \/ C.
Proof.
intros; tauto.
Qed.
(** Backward direction of the equivalences above does not need assumptions *)
Theorem and_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A /\ B <-> A /\ C).
Proof.
intros; tauto.
Qed.
Theorem and_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B /\ A <-> C /\ A).
Proof.
intros; tauto.
Qed.
Theorem or_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A \/ B <-> A \/ C).
Proof.
intros; tauto.
Qed.
Theorem or_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B \/ A <-> C \/ A).
Proof.
intros; tauto.
Qed.
Lemma iff_and : forall A B : Prop, (A <-> B) -> (A -> B) /\ (B -> A).
Proof.
intros A B []; split; trivial.
Qed.
Lemma iff_to_and : forall A B : Prop, (A <-> B) <-> (A -> B) /\ (B -> A).
Proof.
intros; tauto.
Qed.
(** [(IF_then_else P Q R)], written [IF P then Q else R] denotes
either [P] and [Q], or [~P] and [Q] *)
Definition IF_then_else (P Q R:Prop) := P /\ Q \/ ~ P /\ R.
Notation "'IF' c1 'then' c2 'else' c3" := (IF_then_else c1 c2 c3)
(at level 200, right associativity) : type_scope.
(** * First-order quantifiers *)
(** [ex P], or simply [exists x, P x], or also [exists x:A, P x],
expresses the existence of an [x] of some type [A] in [Set] which
satisfies the predicate [P]. This is existential quantification.
[ex2 P Q], or simply [exists2 x, P x & Q x], or also
[exists2 x:A, P x & Q x], expresses the existence of an [x] of
type [A] which satisfies both predicates [P] and [Q].
Universal quantification is primitively written [forall x:A, Q]. By
symmetry with existential quantification, the construction [all P]
is provided too.
*)
(** Remark: [exists x, Q] denotes [ex (fun x => Q)] so that [exists x,
P x] is in fact equivalent to [ex (fun x => P x)] which may be not
convertible to [ex P] if [P] is not itself an abstraction *)
Inductive ex (A:Type) (P:A -> Prop) : Prop :=
ex_intro : forall x:A, P x -> ex (A:=A) P.
Inductive ex2 (A:Type) (P Q:A -> Prop) : Prop :=
ex_intro2 : forall x:A, P x -> Q x -> ex2 (A:=A) P Q.
Definition all (A:Type) (P:A -> Prop) := forall x:A, P x.
(* Rule order is important to give printing priority to fully typed exists *)
Notation "'exists' x , p" := (ex (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : t , p" := (ex (fun x:t => p))
(at level 200, x ident, right associativity,
format "'[' 'exists' '/ ' x : t , '/ ' p ']'")
: type_scope.
Notation "'exists2' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x ident, p at level 200, right associativity) : type_scope.
Notation "'exists2' x : t , p & q" := (ex2 (fun x:t => p) (fun x:t => q))
(at level 200, x ident, t at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' x : t , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
(** Derived rules for universal quantification *)
Section universal_quantification.
Variable A : Type.
Variable P : A -> Prop.
Theorem inst : forall x:A, all (fun x => P x) -> P x.
Proof.
unfold all in |- *; auto.
Qed.
Theorem gen : forall (B:Prop) (f:forall y:A, B -> P y), B -> all P.
Proof.
red in |- *; auto.
Qed.
End universal_quantification.
(** * Equality *)
(** [eq x y], or simply [x=y] expresses the equality of [x] and
[y]. Both [x] and [y] must belong to the same type [A].
The definition is inductive and states the reflexivity of the equality.
The others properties (symmetry, transitivity, replacement of
equals by equals) are proved below. The type of [x] and [y] can be
made explicit using the notation [x = y :> A]. This is Leibniz equality
as it expresses that [x] and [y] are equal iff every property on
[A] which is true of [x] is also true of [y] *)
Inductive eq (A:Type) (x:A) : A -> Prop :=
eq_refl : x = x :>A
where "x = y :> A" := (@eq A x y) : type_scope.
Notation "x = y" := (x = y :>_) : type_scope.
Notation "x <> y :> T" := (~ x = y :>T) : type_scope.
Notation "x <> y" := (x <> y :>_) : type_scope.
Implicit Arguments eq [ [A] ].
Implicit Arguments eq_ind [A].
Implicit Arguments eq_rec [A].
Implicit Arguments eq_rect [A].
Hint Resolve I conj or_introl or_intror eq_refl: core.
Hint Resolve ex_intro ex_intro2: core.
Section Logic_lemmas.
Theorem absurd : forall A C:Prop, A -> ~ A -> C.
Proof.
unfold not in |- *; intros A C h1 h2.
destruct (h2 h1).
Qed.
Section equality.
Variables A B : Type.
Variable f : A -> B.
Variables x y z : A.
Theorem eq_sym : x = y -> y = x.
Proof.
destruct 1; trivial.
Defined.
Opaque eq_sym.
Theorem eq_trans : x = y -> y = z -> x = z.
Proof.
destruct 2; trivial.
Defined.
Opaque eq_trans.
Theorem f_equal : x = y -> f x = f y.
Proof.
destruct 1; trivial.
Defined.
Opaque f_equal.
Theorem not_eq_sym : x <> y -> y <> x.
Proof.
red in |- *; intros h1 h2; apply h1; destruct h2; trivial.
Qed.
End equality.
Definition eq_ind_r :
forall (A:Type) (x:A) (P:A -> Prop), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rec_r :
forall (A:Type) (x:A) (P:A -> Set), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rect_r :
forall (A:Type) (x:A) (P:A -> Type), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
End Logic_lemmas.
Theorem f_equal2 :
forall (A1 A2 B:Type) (f:A1 -> A2 -> B) (x1 y1:A1)
(x2 y2:A2), x1 = y1 -> x2 = y2 -> f x1 x2 = f y1 y2.
Proof.
destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal3 :
forall (A1 A2 A3 B:Type) (f:A1 -> A2 -> A3 -> B) (x1 y1:A1)
(x2 y2:A2) (x3 y3:A3),
x1 = y1 -> x2 = y2 -> x3 = y3 -> f x1 x2 x3 = f y1 y2 y3.
Proof.
destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal4 :
forall (A1 A2 A3 A4 B:Type) (f:A1 -> A2 -> A3 -> A4 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4),
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal5 :
forall (A1 A2 A3 A4 A5 B:Type) (f:A1 -> A2 -> A3 -> A4 -> A5 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4) (x5 y5:A5),
x1 = y1 ->
x2 = y2 ->
x3 = y3 -> x4 = y4 -> x5 = y5 -> f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
(* Aliases *)
Notation sym_eq := eq_sym (only parsing).
Notation trans_eq := eq_trans (only parsing).
Notation sym_not_eq := not_eq_sym (only parsing).
Notation refl_equal := eq_refl (only parsing).
Notation sym_equal := eq_sym (only parsing).
Notation trans_equal := eq_trans (only parsing).
Notation sym_not_equal := not_eq_sym (only parsing).
Hint Immediate eq_sym not_eq_sym: core.
(** Basic definitions about relations and properties *)
Definition subrelation (A B : Type) (R R' : A->B->Prop) :=
forall x y, R x y -> R' x y.
Definition unique (A : Type) (P : A->Prop) (x:A) :=
P x /\ forall (x':A), P x' -> x=x'.
Definition uniqueness (A:Type) (P:A->Prop) := forall x y, P x -> P y -> x = y.
(** Unique existence *)
Notation "'exists' ! x , P" := (ex (unique (fun x => P)))
(at level 200, x ident, right associativity,
format "'[' 'exists' ! '/ ' x , '/ ' P ']'") : type_scope.
Notation "'exists' ! x : A , P" :=
(ex (unique (fun x:A => P)))
(at level 200, x ident, right associativity,
format "'[' 'exists' ! '/ ' x : A , '/ ' P ']'") : type_scope.
Lemma unique_existence : forall (A:Type) (P:A->Prop),
((exists x, P x) /\ uniqueness P) <-> (exists! x, P x).
Proof.
intros A P; split.
intros ((x,Hx),Huni); exists x; red; auto.
intros (x,(Hx,Huni)); split.
exists x; assumption.
intros x' x'' Hx' Hx''; transitivity x.
symmetry; auto.
auto.
Qed.
(** * Being inhabited *)
(** The predicate [inhabited] can be used in different contexts. If [A] is
thought as a type, [inhabited A] states that [A] is inhabited. If [A] is
thought as a computationally relevant proposition, then
[inhabited A] weakens [A] so as to hide its computational meaning.
The so-weakened proof remains computationally relevant but only in
a propositional context.
*)
Inductive inhabited (A:Type) : Prop := inhabits : A -> inhabited A.
Hint Resolve inhabits: core.
Lemma exists_inhabited : forall (A:Type) (P:A->Prop),
(exists x, P x) -> inhabited A.
Proof.
destruct 1; auto.
Qed.
(** Declaration of stepl and stepr for eq and iff *)
Lemma eq_stepl : forall (A : Type) (x y z : A), x = y -> x = z -> z = y.
Proof.
intros A x y z H1 H2. rewrite <- H2; exact H1.
Qed.
Declare Left Step eq_stepl.
Declare Right Step eq_trans.
Lemma iff_stepl : forall A B C : Prop, (A <-> B) -> (A <-> C) -> (C <-> B).
Proof.
intros; tauto.
Qed.
Declare Left Step iff_stepl.
Declare Right Step iff_trans.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR4BB_PP_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_PP_BLACKBOX_V
|
//--------------------------------------------------------------------------------
//-- Filename: BAR1_WRAPPER.v
//--
//-- Description: BAR1_WRAPPER Module
//--
//-- The module is a simple warpper to BAR1 module. it provides write
//-- control and byte enable access on BAR1.
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BAR1_WRAPPER#(
parameter INTERFACE_TYPE = 4'b0010,
parameter FPGA_FAMILY = 8'h14
)
(
clk, // I
rst_n, // I
en,
cfg_cap_max_lnk_width, // I [5:0]
cfg_neg_max_lnk_width, // I [5:0]
cfg_cap_max_lnk_speed, // I [3:0]
cfg_neg_max_lnk_speed, // I [3:0]
cfg_cap_max_payload_size, // I [2:0]
cfg_prg_max_payload_size, // I [2:0]
cfg_max_rd_req_size, // I [2:0]
a_i, // I [6:0]
wr_en_i, // I
wr_be_i, // I [7:0]
wr_busy_o, // O
rd_d_o, // O [31:0]
rd_be_i, // I [3:0]
wr_d_i, // I [31:0]
init_rst_o, // O
mrd_start_o, // O
mrd_done_i, // O
mrd_addr_o, // O [31:0]
mrd_len_o, // O [31:0]
mrd_tlp_tc_o, // O [2:0]
mrd_64b_en_o, // O
mrd_phant_func_dis1_o, // O
mrd_up_addr_o, // O [7:0]
mrd_size_o, // O [31:0]
mrd_relaxed_order_o, // O
mrd_nosnoop_o, // O
mrd_wrr_cnt_o, // O [7:0]
mrd_done_clr, // O
mwr_start_o, // O
mwr_done_i, // I
mwr_addr_o, // O [31:0]
mwr_len_o, // O [31:0]
mwr_tlp_tc_o, // O [2:0]
mwr_64b_en_o, // O
mwr_phant_func_dis1_o, // O
mwr_up_addr_o, // O [7:0]
mwr_size_o, // O [31:0]
mwr_relaxed_order_o, // O
mwr_nosnoop_o, // O
mwr_wrr_cnt_o, // O [7:0]
mwr_done_clr,
cpl_ur_found_i, // I [7:0]
cpl_ur_tag_i, // I [7:0]
cpld_found_i, // I [31:0]
cpld_data_size_i, // I [31:0]
cpld_malformed_i, // I
cpl_streaming_o, // O
rd_metering_o, // O
cfg_interrupt_di, // O
cfg_interrupt_do, // I
cfg_interrupt_mmenable, // I
cfg_interrupt_msienable, // I
cfg_interrupt_legacyclr, // O
`ifdef PCIE2_0
pl_directed_link_change,
pl_ltssm_state,
pl_directed_link_width,
pl_directed_link_speed,
pl_directed_link_auton,
pl_upstream_preemph_src,
pl_sel_link_width,
pl_sel_link_rate,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_initial_link_width,
pl_link_upcfg_capable,
pl_lane_reversal_mode,
pl_width_change_err_i,
pl_speed_change_err_i,
clr_pl_width_change_err,
clr_pl_speed_change_err,
clear_directed_speed_change_i,
`endif
trn_rnp_ok_n_o,
trn_tstr_n_o
);
parameter BAR1_WR_RST = 5'b00001;
parameter BAR1_WR_WAIT = 5'b00010;
parameter BAR1_WR_READ = 5'b00100;
parameter BAR1_WR_WRITE= 5'b01000;
parameter BAR1_WR_DONE = 5'b10000;
input clk;
input rst_n;
input en;
input [5:0] cfg_cap_max_lnk_width;
input [5:0] cfg_neg_max_lnk_width;
input [3:0] cfg_cap_max_lnk_speed;
input [3:0] cfg_neg_max_lnk_speed;
input [2:0] cfg_cap_max_payload_size;
input [2:0] cfg_prg_max_payload_size;
input [2:0] cfg_max_rd_req_size;
// read port
//
input [6:0] a_i;
input [3:0] rd_be_i;
output [31:0] rd_d_o;
// write port
//
input wr_en_i;
input [7:0] wr_be_i;
input [31:0] wr_d_i;
output wr_busy_o;
// CSR bits
output init_rst_o;
output mrd_start_o;
input mrd_done_i;
output [31:0] mrd_addr_o;
output [15:0] mrd_len_o;
output [2:0] mrd_tlp_tc_o;
output mrd_64b_en_o;
output mrd_phant_func_dis1_o;
output [7:0] mrd_up_addr_o;
output [31:0] mrd_size_o;
output mrd_relaxed_order_o;
output mrd_nosnoop_o;
output [7:0] mrd_wrr_cnt_o;
output mrd_done_clr;
output mwr_start_o;
input mwr_done_i;
output [31:0] mwr_addr_o;
output [15:0] mwr_len_o;
output [2:0] mwr_tlp_tc_o;
output mwr_64b_en_o;
output mwr_phant_func_dis1_o;
output [7:0] mwr_up_addr_o;
output [31:0] mwr_size_o;
output mwr_relaxed_order_o;
output mwr_nosnoop_o;
output [7:0] mwr_wrr_cnt_o;
output mwr_done_clr;
input [7:0] cpl_ur_found_i;
input [7:0] cpl_ur_tag_i;
input [31:0] cpld_found_i;
input [31:0] cpld_data_size_i;
input cpld_malformed_i;
output cpl_streaming_o;
output rd_metering_o;
output trn_rnp_ok_n_o;
output trn_tstr_n_o;
output [7:0] cfg_interrupt_di;
input [7:0] cfg_interrupt_do;
input [2:0] cfg_interrupt_mmenable;
input cfg_interrupt_msienable;
output cfg_interrupt_legacyclr;
`ifdef PCIE2_0
output [1:0] pl_directed_link_change;
input [5:0] pl_ltssm_state;
output [1:0] pl_directed_link_width;
output pl_directed_link_speed;
output pl_directed_link_auton;
output pl_upstream_preemph_src;
input [1:0] pl_sel_link_width;
input pl_sel_link_rate;
input pl_link_gen2_capable;
input pl_link_partner_gen2_supported;
input [2:0] pl_initial_link_width;
input pl_link_upcfg_capable;
input [1:0] pl_lane_reversal_mode;
input pl_width_change_err_i;
input pl_speed_change_err_i;
output clr_pl_width_change_err;
output lr_pl_speed_change_err;
input clear_directed_speed_change_i;
`endif
wire [31:0] bar1_rd_data;
reg [6:0] addr_q;
reg [3:0] wr_be_q;
reg [31:0] wr_d_q;
reg wr_busy_o;
reg bar1_wr_en;
reg [31:0] pre_wr_data;
reg [31:0] bar1_wr_data;
reg [4:0] bar1_wr_state;
// BAR1 write control state machine
//
always @ ( posedge clk ) begin
if( !rst_n ) begin
bar1_wr_en <= 1'b0;
wr_busy_o <= 1'b0;
addr_q <= 7'b0;
wr_be_q <= 4'b0;
wr_d_q <= 32'b0;
pre_wr_data <= 32'b0;
bar1_wr_data <= 32'b0;
bar1_wr_state <= BAR1_WR_RST;
end
else begin
case ( bar1_wr_state )
BAR1_WR_RST: begin
bar1_wr_en <= 1'b0;
wr_busy_o <= 1'b0;
addr_q <= a_i;
if( wr_en_i ) begin
wr_be_q <= wr_be_i[3:0];
wr_d_q <= wr_d_i;
wr_busy_o <= 1'b1;
bar1_wr_state <= BAR1_WR_WAIT;
end
end
BAR1_WR_WAIT: begin
bar1_wr_state <= BAR1_WR_READ;
end
BAR1_WR_READ: begin
pre_wr_data <= bar1_rd_data;
bar1_wr_state <= BAR1_WR_WRITE;
end
BAR1_WR_WRITE: begin
bar1_wr_en <= 1'b1;
bar1_wr_data <= { { wr_be_q[3] ? wr_d_q[31:24] : pre_wr_data[31:24] } ,
{ wr_be_q[2] ? wr_d_q[23:16] : pre_wr_data[23:16] } ,
{ wr_be_q[1] ? wr_d_q[15:8] : pre_wr_data[15:8] } ,
{ wr_be_q[0] ? wr_d_q[7:0] : pre_wr_data[7:0] }
};
bar1_wr_state <= BAR1_WR_DONE;
end
BAR1_WR_DONE: begin
wr_busy_o <= 1'b0;
bar1_wr_state <= BAR1_WR_RST;
end
default: bar1_wr_state <= BAR1_WR_RST;
endcase
end
end
/*
* BAR1 Read Controller
*/
/* Handle Read byte enables */
assign rd_d_o = {{rd_be_i[0] ? bar1_rd_data[07:00] : 8'h0},
{rd_be_i[1] ? bar1_rd_data[15:08] : 8'h0},
{rd_be_i[2] ? bar1_rd_data[23:16] : 8'h0},
{rd_be_i[3] ? bar1_rd_data[31:24] : 8'h0}};
BAR1# (
.INTERFACE_TYPE(INTERFACE_TYPE),
.FPGA_FAMILY(FPGA_FAMILY)
) bar1(
.clk(clk), // I
.rst_n(rst_n), // I
.en(en),
.cfg_cap_max_lnk_width(cfg_cap_max_lnk_width), // I [5:0]
.cfg_neg_max_lnk_width(cfg_neg_max_lnk_width), // I [5:0]
.cfg_cap_max_lnk_speed(cfg_cap_max_lnk_speed),
.cfg_neg_max_lnk_speed(cfg_neg_max_lnk_speed),
.cfg_cap_max_payload_size(cfg_cap_max_payload_size), // I [2:0]
.cfg_prg_max_payload_size(cfg_prg_max_payload_size), // I [2:0]
.cfg_max_rd_req_size(cfg_max_rd_req_size), // I [2:0]
.a_i(addr_q), // I [8:0]
.wr_en_i(bar1_wr_en), // I
.rd_d_o(bar1_rd_data), // O [31:0]
.wr_d_i(bar1_wr_data), // I [31:0]
.init_rst_o(init_rst_o), // O
.mrd_start_o(mrd_start_o), // O
.mrd_done_i(mrd_done_i), // I
.mrd_addr_o(mrd_addr_o), // O [31:0]
.mrd_len_o(mrd_len_o), // O [31:0]
.mrd_tlp_tc_o(mrd_tlp_tc_o), // O [2:0]
.mrd_64b_en_o(mrd_64b_en_o), // O
.mrd_phant_func_dis1_o(mrd_phant_func_dis1_o), // O
.mrd_up_addr_o(mrd_up_addr_o), // O [7:0]
.mrd_size_o(mrd_size_o), // O [31:0]
.mrd_relaxed_order_o(mrd_relaxed_order_o), // O
.mrd_nosnoop_o(mrd_nosnoop_o), // O
.mrd_wrr_cnt_o(mrd_wrr_cnt_o), // O [7:0]
.mrd_done_clr(mrd_done_clr), // O
.mwr_start_o(mwr_start_o), // O
.mwr_done_i(mwr_done_i), // I
.mwr_addr_o(mwr_addr_o), // O [31:0]
.mwr_len_o(mwr_len_o), // O [31:0]
.mwr_tlp_tc_o(mwr_tlp_tc_o), // O [2:0]
.mwr_64b_en_o(mwr_64b_en_o), // O
.mwr_phant_func_dis1_o(mwr_phant_func_dis1_o), // O
.mwr_up_addr_o(mwr_up_addr_o), // O [7:0]
.mwr_size_o(mwr_size_o), // O [31:0]
.mwr_relaxed_order_o(mwr_relaxed_order_o), // O
.mwr_nosnoop_o(mwr_nosnoop_o), // O
.mwr_wrr_cnt_o(mwr_wrr_cnt_o), // O [7:0]
.mwr_done_clr(mwr_done_clr),
.cpl_ur_found_i(cpl_ur_found_i), // I [7:0]
.cpl_ur_tag_i(cpl_ur_tag_i), // I [7:0]
.cpld_found_i(cpld_found_i), // I [31:0]
.cpld_data_size_i(cpld_data_size_i), // I [31:0]
.cpld_malformed_i(cpld_malformed_i), // I
.cpl_streaming_o(cpl_streaming_o), // O
.rd_metering_o(rd_metering_o), // O
.cfg_interrupt_di(cfg_interrupt_di), // O
.cfg_interrupt_do(cfg_interrupt_do), // I
.cfg_interrupt_mmenable(cfg_interrupt_mmenable), // I
.cfg_interrupt_msienable(cfg_interrupt_msienable), // I
.cfg_interrupt_legacyclr(cfg_interrupt_legacyclr), // O
`ifdef PCIE2_0
.pl_directed_link_change(pl_directed_link_change),
.pl_ltssm_state(pl_ltssm_state),
.pl_directed_link_width(pl_directed_link_width),
.pl_directed_link_speed(pl_directed_link_speed),
.pl_directed_link_auton(pl_directed_link_auton),
.pl_upstream_preemph_src(pl_upstream_preemph_src),
.pl_sel_link_width(pl_sel_link_width),
.pl_sel_link_rate(pl_sel_link_rate),
.pl_link_gen2_capable(pl_link_gen2_capable),
.pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
.pl_initial_link_width(pl_initial_link_width),
.pl_link_upcfg_capable(pl_link_upcfg_capable),
.pl_lane_reversal_mode(pl_lane_reversal_mode),
.pl_width_change_err_i(pl_width_change_err_i),
.pl_speed_change_err_i(pl_speed_change_err_i),
.clr_pl_width_change_err(clr_pl_width_change_err),
.clr_pl_speed_change_err(clr_pl_speed_change_err),
.clear_directed_speed_change_i(clear_directed_speed_change_i),
`endif
.trn_rnp_ok_n_o(trn_rnp_ok_n_o),
.trn_tstr_n_o(trn_tstr_n_o)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Block_Mat_exit1573_p (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
height,
width,
min,
max,
min_out_din,
min_out_full_n,
min_out_write,
img0_rows_V_out_din,
img0_rows_V_out_full_n,
img0_rows_V_out_write,
img0_cols_V_out_din,
img0_cols_V_out_full_n,
img0_cols_V_out_write,
img2_rows_V_out_din,
img2_rows_V_out_full_n,
img2_rows_V_out_write,
img2_cols_V_out_din,
img2_cols_V_out_full_n,
img2_cols_V_out_write,
img3_rows_V_out_din,
img3_rows_V_out_full_n,
img3_rows_V_out_write,
img3_cols_V_out_din,
img3_cols_V_out_full_n,
img3_cols_V_out_write,
p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n,
p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n,
p_rows_assign_cast_out_out_write,
tmp_3_cast_out_out_din,
tmp_3_cast_out_out_full_n,
tmp_3_cast_out_out_write,
max_out_din,
max_out_full_n,
max_out_write
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [15:0] height;
input [15:0] width;
input [7:0] min;
input [7:0] max;
output [7:0] min_out_din;
input min_out_full_n;
output min_out_write;
output [15:0] img0_rows_V_out_din;
input img0_rows_V_out_full_n;
output img0_rows_V_out_write;
output [15:0] img0_cols_V_out_din;
input img0_cols_V_out_full_n;
output img0_cols_V_out_write;
output [15:0] img2_rows_V_out_din;
input img2_rows_V_out_full_n;
output img2_rows_V_out_write;
output [15:0] img2_cols_V_out_din;
input img2_cols_V_out_full_n;
output img2_cols_V_out_write;
output [15:0] img3_rows_V_out_din;
input img3_rows_V_out_full_n;
output img3_rows_V_out_write;
output [15:0] img3_cols_V_out_din;
input img3_cols_V_out_full_n;
output img3_cols_V_out_write;
output [11:0] p_cols_assign_cast_out_out_din;
input p_cols_assign_cast_out_out_full_n;
output p_cols_assign_cast_out_out_write;
output [11:0] p_rows_assign_cast_out_out_din;
input p_rows_assign_cast_out_out_full_n;
output p_rows_assign_cast_out_out_write;
output [7:0] tmp_3_cast_out_out_din;
input tmp_3_cast_out_out_full_n;
output tmp_3_cast_out_out_write;
output [7:0] max_out_din;
input max_out_full_n;
output max_out_write;
reg ap_done;
reg ap_idle;
reg start_write;
reg min_out_write;
reg img0_rows_V_out_write;
reg img0_cols_V_out_write;
reg img2_rows_V_out_write;
reg img2_cols_V_out_write;
reg img3_rows_V_out_write;
reg img3_cols_V_out_write;
reg p_cols_assign_cast_out_out_write;
reg p_rows_assign_cast_out_out_write;
reg tmp_3_cast_out_out_write;
reg max_out_write;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg min_out_blk_n;
reg img0_rows_V_out_blk_n;
reg img0_cols_V_out_blk_n;
reg img2_rows_V_out_blk_n;
reg img2_cols_V_out_blk_n;
reg img3_rows_V_out_blk_n;
reg img3_cols_V_out_blk_n;
reg p_cols_assign_cast_out_out_blk_n;
reg p_rows_assign_cast_out_out_blk_n;
reg tmp_3_cast_out_out_blk_n;
reg max_out_blk_n;
reg ap_block_state1;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_cols_V_out_blk_n = img0_cols_V_out_full_n;
end else begin
img0_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_cols_V_out_write = 1'b1;
end else begin
img0_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_rows_V_out_blk_n = img0_rows_V_out_full_n;
end else begin
img0_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_rows_V_out_write = 1'b1;
end else begin
img0_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_cols_V_out_blk_n = img2_cols_V_out_full_n;
end else begin
img2_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_cols_V_out_write = 1'b1;
end else begin
img2_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_rows_V_out_blk_n = img2_rows_V_out_full_n;
end else begin
img2_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_rows_V_out_write = 1'b1;
end else begin
img2_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_cols_V_out_blk_n = img3_cols_V_out_full_n;
end else begin
img3_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_cols_V_out_write = 1'b1;
end else begin
img3_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_rows_V_out_blk_n = img3_rows_V_out_full_n;
end else begin
img3_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_rows_V_out_write = 1'b1;
end else begin
img3_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
max_out_blk_n = max_out_full_n;
end else begin
max_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
max_out_write = 1'b1;
end else begin
max_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
min_out_blk_n = min_out_full_n;
end else begin
min_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
min_out_write = 1'b1;
end else begin
min_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_cols_assign_cast_out_out_blk_n = p_cols_assign_cast_out_out_full_n;
end else begin
p_cols_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_out_out_write = 1'b1;
end else begin
p_cols_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_rows_assign_cast_out_out_blk_n = p_rows_assign_cast_out_out_full_n;
end else begin
p_rows_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_out_out_write = 1'b1;
end else begin
p_rows_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
tmp_3_cast_out_out_blk_n = tmp_3_cast_out_out_full_n;
end else begin
tmp_3_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
tmp_3_cast_out_out_write = 1'b1;
end else begin
tmp_3_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @ (*) begin
ap_block_state1 = ((max_out_full_n == 1'b0) | (tmp_3_cast_out_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (min_out_full_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_ready = internal_ap_ready;
assign img0_cols_V_out_din = width;
assign img0_rows_V_out_din = height;
assign img2_cols_V_out_din = width;
assign img2_rows_V_out_din = height;
assign img3_cols_V_out_din = width;
assign img3_rows_V_out_din = height;
assign max_out_din = max;
assign min_out_din = min;
assign p_cols_assign_cast_out_out_din = width[11:0];
assign p_rows_assign_cast_out_out_din = height[11:0];
assign start_out = real_start;
assign tmp_3_cast_out_out_din = min;
endmodule //Block_Mat_exit1573_p
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A21OI_PP_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_PP_SYMBOL_V
|
/*
File: earb.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response),
arbitrates between the active channels, and forwards the result on to
the transmit channel.
The arbitration order is (fixed, highest to lowest)
1) read responses
2) read requests
3) writes
*/
module e_tx_arbiter (/*AUTOARG*/
// Outputs
emwr_rd_en, emrq_rd_en, emrr_rd_en, e_tx_access, e_tx_write,
e_tx_datamode, e_tx_ctrlmode, e_tx_dstaddr, e_tx_srcaddr,
e_tx_data,
// Inputs
clk, reset, emwr_rd_data, emwr_empty, emrq_rd_data, emrq_empty,
emrr_rd_data, emrr_empty, e_tx_rd_wait, e_tx_wr_wait, e_tx_ack
);
// tx clock
input clk;
input reset;
// from write request FIFO (slave)
input [102:0] emwr_rd_data;
output emwr_rd_en;
input emwr_empty;
// from read request fifo (slave port)
input [102:0] emrq_rd_data;
output emrq_rd_en;
input emrq_empty;
// from read response FIFO (master port)
input [102:0] emrr_rd_data;
output emrr_rd_en;
input emrr_empty;
// eMesh master port, to TX
output e_tx_access;
output e_tx_write;
output [1:0] e_tx_datamode;
output [3:0] e_tx_ctrlmode;
output [31:0] e_tx_dstaddr;
output [31:0] e_tx_srcaddr;
output [31:0] e_tx_data;
input e_tx_rd_wait;
input e_tx_wr_wait;
// Ack from TX protocol module
input e_tx_ack;
// Control bits inputs (none)
//############
//# Arbitrate & forward
//############
reg ready;
reg [102:0] fifo_data;
// priority-based ready signals
wire rr_ready = ~emrr_empty & ~emm_tx_wr_wait;
wire rq_ready = ~emrq_empty & ~emm_tx_rd_wait & ~rr_ready;
wire wr_ready = ~emwr_empty & ~emm_tx_wr_wait & ~rr_ready & ~rq_ready;
// FIFO read enables, when we're idle or done with the current datum
wire emrr_rd_en = rr_ready & (~ready | emtx_ack);
wire emrq_rd_en = rq_ready & (~ready | emtx_ack);
wire emwr_rd_en = wr_ready & (~ready | emtx_ack);
always @ (posedge clk) begin
if( reset ) begin
ready <= 1'b0;
fifo_data <= 'd0;
end else begin
if( emrr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrr_rd_data;
end else if( emrq_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrq_rd_data;
end else if( emwr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emwr_rd_data;
end else if( emtx_ack ) begin
ready <= 1'b0;
end
end // else: !if( reset )
end // always @ (posedge clock)
//#############################
//# Break-out the emesh signals
//#############################
assign e_tx_access = ready;
assign e_tx_write = fifo_data[102];
assign e_tx_datamode = fifo_data[101:100];
assign e_tx_ctrlmode = fifo_data[99:96];
assign e_tx_dstaddr = fifo_data[95:64];
assign e_tx_srcaddr = fifo_data[63:32];
assign e_tx_data = fifo_data[31:0];
endmodule // e_tx_arbiter
|
module gcd_mem3 (
clk,
req_msg,
req_rdy,
req_val,
reset,
resp_msg,
resp_rdy,
resp_val,
mem_out0,
mem_out1,
mem_out2);
input clk;
input [31:0] req_msg;
output req_rdy;
input req_val;
input reset;
output [15:0] resp_msg;
input resp_rdy;
output resp_val;
output [6:0] mem_out0;
output [6:0] mem_out1;
output [6:0] mem_out2;
wire [6:0] data;
// mem0/rd_out -> r1* -> r2* -> r3* -> mem1/wd_in
DFF_X1 r10 (.D(mem_out0[0]),
.CK(clk),
.Q(l1[0]));
DFF_X1 r11 (.D(mem_out0[1]),
.CK(clk),
.Q(l1[1]));
DFF_X1 r12 (.D(mem_out0[2]),
.CK(clk),
.Q(l1[2]));
DFF_X1 r13 (.D(mem_out0[3]),
.CK(clk),
.Q(l1[3]));
DFF_X1 r14 (.D(mem_out0[4]),
.CK(clk),
.Q(l1[4]));
DFF_X1 r15 (.D(mem_out0[5]),
.CK(clk),
.Q(l1[5]));
DFF_X1 r16 (.D(mem_out0[6]),
.CK(clk),
.Q(l1[6]));
DFF_X1 r20 (.D(l1[0]),
.CK(clk),
.Q(l2[0]));
DFF_X1 r21 (.D(l1[1]),
.CK(clk),
.Q(l2[1]));
DFF_X1 r22 (.D(l1[2]),
.CK(clk),
.Q(l2[2]));
DFF_X1 r23 (.D(l1[3]),
.CK(clk),
.Q(l2[3]));
DFF_X1 r24 (.D(l1[4]),
.CK(clk),
.Q(l2[4]));
DFF_X1 r25 (.D(l1[5]),
.CK(clk),
.Q(l2[5]));
DFF_X1 r26 (.D(l1[6]),
.CK(clk),
.Q(l2[6]));
DFF_X1 r30 (.D(l2[0]),
.CK(clk),
.Q(l3[0]));
DFF_X1 r31 (.D(l2[1]),
.CK(clk),
.Q(l3[1]));
DFF_X1 r32 (.D(l2[2]),
.CK(clk),
.Q(l3[2]));
DFF_X1 r33 (.D(l2[3]),
.CK(clk),
.Q(l3[3]));
DFF_X1 r34 (.D(l2[4]),
.CK(clk),
.Q(l3[4]));
DFF_X1 r35 (.D(l2[5]),
.CK(clk),
.Q(l3[5]));
DFF_X1 r36 (.D(l2[6]),
.CK(clk),
.Q(l3[6]));
fakeram45_64x7 mem0 (.clk(clk),
.rd_out(mem_out0),
.we_in(_006_),
.ce_in(_007_),
.addr_in({ _008_,
_009_,
_010_,
_011_,
_012_,
_013_ }),
.wd_in({ _014_,
_015_,
_016_,
_017_,
_018_,
_019_,
_020_ }),
.w_mask_in({ _021_,
_076_,
_077_,
_078_,
_079_,
_080_,
_081_ }));
fakeram45_64x7 mem1 (.clk(clk),
.rd_out(mem_out1),
.we_in(_090_),
.ce_in(_091_),
.addr_in({ _092_,
_093_,
_094_,
_095_,
_096_,
_097_ }),
.wd_in(l3[6:0]),
.w_mask_in({ _105_,
_106_,
_107_,
_054_,
_055_,
_056_,
_003_ }));
fakeram45_64x7 mem2 (.clk(clk),
.rd_out(mem_out2),
.we_in(_012_),
.ce_in(_013_),
.addr_in({ _014_,
_015_,
_016_,
_017_,
_018_,
_019_ }),
.wd_in({ _020_,
_021_,
_076_,
_077_,
_078_,
_079_,
_080_ }),
.w_mask_in({ _081_,
_082_,
_083_,
_084_,
_085_,
_086_,
_087_ }));
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Fri Jul 8 09:01:52 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode funcsim {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/pcie_recv_fifo_sim_netlist.v}
// Design : pcie_recv_fifo
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "pcie_recv_fifo,fifo_generator_v13_0_1,{}" *) (* core_generation_info = "pcie_recv_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=128,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=128,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=511,C_PROG_FULL_THRESH_NEGATE_VAL=510,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v13_0_1,Vivado 2015.4" *)
(* NotValidForBitStream *)
module pcie_recv_fifo
(clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input srst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [127:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [127:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "128" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "128" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "0" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "0" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "1" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *)
(* C_PRELOAD_REGS = "1" *)
(* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "511" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "510" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "512" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "1" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
pcie_recv_fifo_fifo_generator_v13_0_1 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(srst),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module pcie_recv_fifo_blk_mem_gen_generic_cstr
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r
(.D(D[71:0]),
.clk(clk),
.din(din[71:0]),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.D(D[127:72]),
.clk(clk),
.din(din[127:72]),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pcie_recv_fifo_blk_mem_gen_prim_width
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [71:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [71:0]din;
wire [71:0]D;
wire clk;
wire [71:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [55:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [55:0]din;
wire [55:0]D;
wire clk;
wire [55:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module pcie_recv_fifo_blk_mem_gen_prim_wrapper
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [71:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [71:0]din;
wire [71:0]D;
wire clk;
wire [71:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
(.ADDRARDADDR({1'b1,\gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gcc0.gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({din[70:63],din[61:54],din[52:45],din[43:36]}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({din[71],din[62],din[53],din[44]}),
.DOADO({D[34:27],D[25:18],D[16:9],D[7:0]}),
.DOBDO({D[70:63],D[61:54],D[52:45],D[43:36]}),
.DOPADOP({D[35],D[26],D[17],D[8]}),
.DOPBDOP({D[71],D[62],D[53],D[44]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(ram_full_fb_i_reg),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(srst),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [55:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [55:0]din;
wire [55:0]D;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92 ;
wire clk;
wire [55:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram
(.ADDRARDADDR({1'b1,\gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gcc0.gc0.count_d1_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,din[55:49],1'b0,din[48:42],1'b0,din[41:35],1'b0,din[34:28]}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21 ,D[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29 ,D[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ,D[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ,D[6:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ,D[55:49],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61 ,D[48:42],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69 ,D[41:35],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77 ,D[34:28]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(ram_full_fb_i_reg),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(srst),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module pcie_recv_fifo_blk_mem_gen_top
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_generic_cstr \valid.cstr
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1" *)
module pcie_recv_fifo_blk_mem_gen_v8_3_1
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_v8_3_1_synth inst_blk_mem_gen
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1_synth" *)
module pcie_recv_fifo_blk_mem_gen_v8_3_1_synth
(D,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din);
output [127:0]D;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
wire [127:0]D;
wire clk;
wire [127:0]din;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.D(D),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "compare" *)
module pcie_recv_fifo_compare
(ram_full_i,
v1_reg,
\gc0.count_d1_reg[8] ,
E,
srst,
comp1,
wr_en,
p_1_out);
output ram_full_i;
input [3:0]v1_reg;
input [0:0]\gc0.count_d1_reg[8] ;
input [0:0]E;
input srst;
input comp1;
input wr_en;
input p_1_out;
wire [0:0]E;
wire comp0;
wire comp1;
wire [0:0]\gc0.count_d1_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire p_1_out;
wire ram_full_i;
wire srst;
wire [3:0]v1_reg;
wire wr_en;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'h0707070703000000))
ram_full_i_i_1
(.I0(comp0),
.I1(E),
.I2(srst),
.I3(comp1),
.I4(wr_en),
.I5(p_1_out),
.O(ram_full_i));
endmodule
(* ORIG_REF_NAME = "compare" *)
module pcie_recv_fifo_compare_0
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module pcie_recv_fifo_compare_1
(ram_empty_fb_i,
v1_reg_0,
\gc0.count_d1_reg[8] ,
p_2_out,
srst,
E,
ram_full_fb_i_reg,
comp1);
output ram_empty_fb_i;
input [3:0]v1_reg_0;
input \gc0.count_d1_reg[8] ;
input p_2_out;
input srst;
input [0:0]E;
input ram_full_fb_i_reg;
input comp1;
wire [0:0]E;
wire comp0;
wire comp1;
wire \gc0.count_d1_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire p_2_out;
wire ram_empty_fb_i;
wire ram_full_fb_i_reg;
wire srst;
wire [3:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFFFAF2F2FAFAF2F2))
ram_empty_fb_i_i_1
(.I0(p_2_out),
.I1(comp0),
.I2(srst),
.I3(E),
.I4(ram_full_fb_i_reg),
.I5(comp1),
.O(ram_empty_fb_i));
endmodule
(* ORIG_REF_NAME = "compare" *)
module pcie_recv_fifo_compare_2
(comp1,
\gcc0.gc0.count_d1_reg[6] ,
v1_reg);
output comp1;
input [3:0]\gcc0.gc0.count_d1_reg[6] ;
input [0:0]v1_reg;
wire comp1;
wire [3:0]\gcc0.gc0.count_d1_reg[6] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [0:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(\gcc0.gc0.count_d1_reg[6] ));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg}));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module pcie_recv_fifo_fifo_generator_ramfifo
(empty,
full,
dout,
clk,
srst,
din,
rd_en,
wr_en);
output empty;
output full;
output [127:0]dout;
input clk;
input srst;
input [127:0]din;
input rd_en;
input wr_en;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire [4:0]\grss.rsts/c1/v1_reg ;
wire [3:0]\grss.rsts/c2/v1_reg ;
wire [4:0]\gwss.wsts/c1/v1_reg ;
wire [8:0]p_0_out;
wire [8:0]p_10_out;
wire [8:0]p_11_out;
wire p_16_out;
wire p_5_out;
wire p_6_out;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire srst;
wire tmp_ram_rd_en;
wire wr_en;
pcie_recv_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_0_out),
.E(p_6_out),
.Q(rd_pntr_plus1),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[6] (\grss.rsts/c2/v1_reg ),
.\gcc0.gc0.count_d1_reg[8] (p_10_out[8]),
.\gcc0.gc0.count_reg[8] (p_11_out),
.\goreg_bm.dout_i_reg[127] (p_5_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.ram_full_i_reg(\grss.rsts/c1/v1_reg [4]),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(\gwss.wsts/c1/v1_reg ),
.v1_reg_0(\grss.rsts/c1/v1_reg [3:0]));
pcie_recv_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_10_out),
.E(p_6_out),
.Q(p_11_out),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[7] (p_0_out[7:0]),
.\gc0.count_d1_reg[8] (\grss.rsts/c1/v1_reg [4]),
.\gc0.count_reg[7] (rd_pntr_plus1),
.\gcc0.gc0.count_reg[0] (p_16_out),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.ram_empty_fb_i_reg_0(\grss.rsts/c2/v1_reg ),
.srst(srst),
.v1_reg(\grss.rsts/c1/v1_reg [3:0]),
.v1_reg_0(\gwss.wsts/c1/v1_reg ),
.wr_en(wr_en));
pcie_recv_fifo_memory \gntv_or_sync_fifo.mem
(.E(p_5_out),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (p_0_out),
.\gcc0.gc0.count_d1_reg[8] (p_10_out),
.ram_full_fb_i_reg(p_16_out),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module pcie_recv_fifo_fifo_generator_top
(empty,
full,
dout,
clk,
srst,
din,
rd_en,
wr_en);
output empty;
output full;
output [127:0]dout;
input clk;
input srst;
input [127:0]din;
input rd_en;
input wr_en;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
pcie_recv_fifo_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "128" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "128" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "0" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "1" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "511" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "510" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "512" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "1" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *) (* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "9" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *)
(* ORIG_REF_NAME = "fifo_generator_v13_0_1" *)
module pcie_recv_fifo_fifo_generator_v13_0_1
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [127:0]din;
input wr_en;
input rd_en;
input [8:0]prog_empty_thresh;
input [8:0]prog_empty_thresh_assert;
input [8:0]prog_empty_thresh_negate;
input [8:0]prog_full_thresh;
input [8:0]prog_full_thresh_assert;
input [8:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [127:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [8:0]prog_empty_thresh;
wire [8:0]prog_empty_thresh_assert;
wire [8:0]prog_empty_thresh_negate;
wire [8:0]prog_full_thresh;
wire [8:0]prog_full_thresh_assert;
wire [8:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
pcie_recv_fifo_fifo_generator_v13_0_1_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.srst(srst),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_0_1_synth" *)
module pcie_recv_fifo_fifo_generator_v13_0_1_synth
(dout,
empty,
full,
clk,
srst,
din,
s_aclk,
rd_en,
wr_en,
s_aresetn);
output [127:0]dout;
output empty;
output full;
input clk;
input srst;
input [127:0]din;
input s_aclk;
input rd_en;
input wr_en;
input s_aresetn;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire empty;
wire full;
wire rd_en;
wire s_aclk;
wire s_aresetn;
wire srst;
wire wr_en;
pcie_recv_fifo_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
pcie_recv_fifo_reset_blk_ramfifo \reset_gen_cc.rstblk_cc
(.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule
(* ORIG_REF_NAME = "memory" *)
module pcie_recv_fifo_memory
(dout,
clk,
tmp_ram_rd_en,
ram_full_fb_i_reg,
srst,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[8] ,
din,
E);
output [127:0]dout;
input clk;
input tmp_ram_rd_en;
input [0:0]ram_full_fb_i_reg;
input srst;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_d1_reg[8] ;
input [127:0]din;
input [0:0]E;
wire [0:0]E;
wire clk;
wire [127:0]din;
wire [127:0]dout;
wire [127:0]doutb;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_d1_reg[8] ;
wire [0:0]ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
pcie_recv_fifo_blk_mem_gen_v8_3_1 \gbm.gbmg.gbmga.ngecc.bmg
(.D(doutb),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[0]
(.C(clk),
.CE(E),
.D(doutb[0]),
.Q(dout[0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[100]
(.C(clk),
.CE(E),
.D(doutb[100]),
.Q(dout[100]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[101]
(.C(clk),
.CE(E),
.D(doutb[101]),
.Q(dout[101]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[102]
(.C(clk),
.CE(E),
.D(doutb[102]),
.Q(dout[102]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[103]
(.C(clk),
.CE(E),
.D(doutb[103]),
.Q(dout[103]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[104]
(.C(clk),
.CE(E),
.D(doutb[104]),
.Q(dout[104]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[105]
(.C(clk),
.CE(E),
.D(doutb[105]),
.Q(dout[105]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[106]
(.C(clk),
.CE(E),
.D(doutb[106]),
.Q(dout[106]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[107]
(.C(clk),
.CE(E),
.D(doutb[107]),
.Q(dout[107]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[108]
(.C(clk),
.CE(E),
.D(doutb[108]),
.Q(dout[108]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[109]
(.C(clk),
.CE(E),
.D(doutb[109]),
.Q(dout[109]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[10]
(.C(clk),
.CE(E),
.D(doutb[10]),
.Q(dout[10]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[110]
(.C(clk),
.CE(E),
.D(doutb[110]),
.Q(dout[110]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[111]
(.C(clk),
.CE(E),
.D(doutb[111]),
.Q(dout[111]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[112]
(.C(clk),
.CE(E),
.D(doutb[112]),
.Q(dout[112]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[113]
(.C(clk),
.CE(E),
.D(doutb[113]),
.Q(dout[113]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[114]
(.C(clk),
.CE(E),
.D(doutb[114]),
.Q(dout[114]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[115]
(.C(clk),
.CE(E),
.D(doutb[115]),
.Q(dout[115]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[116]
(.C(clk),
.CE(E),
.D(doutb[116]),
.Q(dout[116]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[117]
(.C(clk),
.CE(E),
.D(doutb[117]),
.Q(dout[117]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[118]
(.C(clk),
.CE(E),
.D(doutb[118]),
.Q(dout[118]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[119]
(.C(clk),
.CE(E),
.D(doutb[119]),
.Q(dout[119]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[11]
(.C(clk),
.CE(E),
.D(doutb[11]),
.Q(dout[11]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[120]
(.C(clk),
.CE(E),
.D(doutb[120]),
.Q(dout[120]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[121]
(.C(clk),
.CE(E),
.D(doutb[121]),
.Q(dout[121]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[122]
(.C(clk),
.CE(E),
.D(doutb[122]),
.Q(dout[122]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[123]
(.C(clk),
.CE(E),
.D(doutb[123]),
.Q(dout[123]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[124]
(.C(clk),
.CE(E),
.D(doutb[124]),
.Q(dout[124]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[125]
(.C(clk),
.CE(E),
.D(doutb[125]),
.Q(dout[125]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[126]
(.C(clk),
.CE(E),
.D(doutb[126]),
.Q(dout[126]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[127]
(.C(clk),
.CE(E),
.D(doutb[127]),
.Q(dout[127]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[12]
(.C(clk),
.CE(E),
.D(doutb[12]),
.Q(dout[12]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[13]
(.C(clk),
.CE(E),
.D(doutb[13]),
.Q(dout[13]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[14]
(.C(clk),
.CE(E),
.D(doutb[14]),
.Q(dout[14]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[15]
(.C(clk),
.CE(E),
.D(doutb[15]),
.Q(dout[15]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[16]
(.C(clk),
.CE(E),
.D(doutb[16]),
.Q(dout[16]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[17]
(.C(clk),
.CE(E),
.D(doutb[17]),
.Q(dout[17]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[18]
(.C(clk),
.CE(E),
.D(doutb[18]),
.Q(dout[18]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[19]
(.C(clk),
.CE(E),
.D(doutb[19]),
.Q(dout[19]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[1]
(.C(clk),
.CE(E),
.D(doutb[1]),
.Q(dout[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[20]
(.C(clk),
.CE(E),
.D(doutb[20]),
.Q(dout[20]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[21]
(.C(clk),
.CE(E),
.D(doutb[21]),
.Q(dout[21]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[22]
(.C(clk),
.CE(E),
.D(doutb[22]),
.Q(dout[22]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[23]
(.C(clk),
.CE(E),
.D(doutb[23]),
.Q(dout[23]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[24]
(.C(clk),
.CE(E),
.D(doutb[24]),
.Q(dout[24]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[25]
(.C(clk),
.CE(E),
.D(doutb[25]),
.Q(dout[25]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[26]
(.C(clk),
.CE(E),
.D(doutb[26]),
.Q(dout[26]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[27]
(.C(clk),
.CE(E),
.D(doutb[27]),
.Q(dout[27]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[28]
(.C(clk),
.CE(E),
.D(doutb[28]),
.Q(dout[28]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[29]
(.C(clk),
.CE(E),
.D(doutb[29]),
.Q(dout[29]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[2]
(.C(clk),
.CE(E),
.D(doutb[2]),
.Q(dout[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[30]
(.C(clk),
.CE(E),
.D(doutb[30]),
.Q(dout[30]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[31]
(.C(clk),
.CE(E),
.D(doutb[31]),
.Q(dout[31]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[32]
(.C(clk),
.CE(E),
.D(doutb[32]),
.Q(dout[32]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[33]
(.C(clk),
.CE(E),
.D(doutb[33]),
.Q(dout[33]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[34]
(.C(clk),
.CE(E),
.D(doutb[34]),
.Q(dout[34]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[35]
(.C(clk),
.CE(E),
.D(doutb[35]),
.Q(dout[35]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[36]
(.C(clk),
.CE(E),
.D(doutb[36]),
.Q(dout[36]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[37]
(.C(clk),
.CE(E),
.D(doutb[37]),
.Q(dout[37]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[38]
(.C(clk),
.CE(E),
.D(doutb[38]),
.Q(dout[38]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[39]
(.C(clk),
.CE(E),
.D(doutb[39]),
.Q(dout[39]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[3]
(.C(clk),
.CE(E),
.D(doutb[3]),
.Q(dout[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[40]
(.C(clk),
.CE(E),
.D(doutb[40]),
.Q(dout[40]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[41]
(.C(clk),
.CE(E),
.D(doutb[41]),
.Q(dout[41]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[42]
(.C(clk),
.CE(E),
.D(doutb[42]),
.Q(dout[42]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[43]
(.C(clk),
.CE(E),
.D(doutb[43]),
.Q(dout[43]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[44]
(.C(clk),
.CE(E),
.D(doutb[44]),
.Q(dout[44]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[45]
(.C(clk),
.CE(E),
.D(doutb[45]),
.Q(dout[45]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[46]
(.C(clk),
.CE(E),
.D(doutb[46]),
.Q(dout[46]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[47]
(.C(clk),
.CE(E),
.D(doutb[47]),
.Q(dout[47]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[48]
(.C(clk),
.CE(E),
.D(doutb[48]),
.Q(dout[48]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[49]
(.C(clk),
.CE(E),
.D(doutb[49]),
.Q(dout[49]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[4]
(.C(clk),
.CE(E),
.D(doutb[4]),
.Q(dout[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[50]
(.C(clk),
.CE(E),
.D(doutb[50]),
.Q(dout[50]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[51]
(.C(clk),
.CE(E),
.D(doutb[51]),
.Q(dout[51]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[52]
(.C(clk),
.CE(E),
.D(doutb[52]),
.Q(dout[52]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[53]
(.C(clk),
.CE(E),
.D(doutb[53]),
.Q(dout[53]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[54]
(.C(clk),
.CE(E),
.D(doutb[54]),
.Q(dout[54]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[55]
(.C(clk),
.CE(E),
.D(doutb[55]),
.Q(dout[55]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[56]
(.C(clk),
.CE(E),
.D(doutb[56]),
.Q(dout[56]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[57]
(.C(clk),
.CE(E),
.D(doutb[57]),
.Q(dout[57]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[58]
(.C(clk),
.CE(E),
.D(doutb[58]),
.Q(dout[58]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[59]
(.C(clk),
.CE(E),
.D(doutb[59]),
.Q(dout[59]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[5]
(.C(clk),
.CE(E),
.D(doutb[5]),
.Q(dout[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[60]
(.C(clk),
.CE(E),
.D(doutb[60]),
.Q(dout[60]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[61]
(.C(clk),
.CE(E),
.D(doutb[61]),
.Q(dout[61]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[62]
(.C(clk),
.CE(E),
.D(doutb[62]),
.Q(dout[62]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[63]
(.C(clk),
.CE(E),
.D(doutb[63]),
.Q(dout[63]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[64]
(.C(clk),
.CE(E),
.D(doutb[64]),
.Q(dout[64]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[65]
(.C(clk),
.CE(E),
.D(doutb[65]),
.Q(dout[65]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[66]
(.C(clk),
.CE(E),
.D(doutb[66]),
.Q(dout[66]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[67]
(.C(clk),
.CE(E),
.D(doutb[67]),
.Q(dout[67]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[68]
(.C(clk),
.CE(E),
.D(doutb[68]),
.Q(dout[68]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[69]
(.C(clk),
.CE(E),
.D(doutb[69]),
.Q(dout[69]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[6]
(.C(clk),
.CE(E),
.D(doutb[6]),
.Q(dout[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[70]
(.C(clk),
.CE(E),
.D(doutb[70]),
.Q(dout[70]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[71]
(.C(clk),
.CE(E),
.D(doutb[71]),
.Q(dout[71]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[72]
(.C(clk),
.CE(E),
.D(doutb[72]),
.Q(dout[72]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[73]
(.C(clk),
.CE(E),
.D(doutb[73]),
.Q(dout[73]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[74]
(.C(clk),
.CE(E),
.D(doutb[74]),
.Q(dout[74]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[75]
(.C(clk),
.CE(E),
.D(doutb[75]),
.Q(dout[75]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[76]
(.C(clk),
.CE(E),
.D(doutb[76]),
.Q(dout[76]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[77]
(.C(clk),
.CE(E),
.D(doutb[77]),
.Q(dout[77]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[78]
(.C(clk),
.CE(E),
.D(doutb[78]),
.Q(dout[78]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[79]
(.C(clk),
.CE(E),
.D(doutb[79]),
.Q(dout[79]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[7]
(.C(clk),
.CE(E),
.D(doutb[7]),
.Q(dout[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[80]
(.C(clk),
.CE(E),
.D(doutb[80]),
.Q(dout[80]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[81]
(.C(clk),
.CE(E),
.D(doutb[81]),
.Q(dout[81]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[82]
(.C(clk),
.CE(E),
.D(doutb[82]),
.Q(dout[82]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[83]
(.C(clk),
.CE(E),
.D(doutb[83]),
.Q(dout[83]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[84]
(.C(clk),
.CE(E),
.D(doutb[84]),
.Q(dout[84]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[85]
(.C(clk),
.CE(E),
.D(doutb[85]),
.Q(dout[85]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[86]
(.C(clk),
.CE(E),
.D(doutb[86]),
.Q(dout[86]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[87]
(.C(clk),
.CE(E),
.D(doutb[87]),
.Q(dout[87]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[88]
(.C(clk),
.CE(E),
.D(doutb[88]),
.Q(dout[88]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[89]
(.C(clk),
.CE(E),
.D(doutb[89]),
.Q(dout[89]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[8]
(.C(clk),
.CE(E),
.D(doutb[8]),
.Q(dout[8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[90]
(.C(clk),
.CE(E),
.D(doutb[90]),
.Q(dout[90]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[91]
(.C(clk),
.CE(E),
.D(doutb[91]),
.Q(dout[91]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[92]
(.C(clk),
.CE(E),
.D(doutb[92]),
.Q(dout[92]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[93]
(.C(clk),
.CE(E),
.D(doutb[93]),
.Q(dout[93]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[94]
(.C(clk),
.CE(E),
.D(doutb[94]),
.Q(dout[94]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[95]
(.C(clk),
.CE(E),
.D(doutb[95]),
.Q(dout[95]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[96]
(.C(clk),
.CE(E),
.D(doutb[96]),
.Q(dout[96]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[97]
(.C(clk),
.CE(E),
.D(doutb[97]),
.Q(dout[97]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[98]
(.C(clk),
.CE(E),
.D(doutb[98]),
.Q(dout[98]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[99]
(.C(clk),
.CE(E),
.D(doutb[99]),
.Q(dout[99]),
.R(srst));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[9]
(.C(clk),
.CE(E),
.D(doutb[9]),
.Q(dout[9]),
.R(srst));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module pcie_recv_fifo_rd_bin_cntr
(Q,
ram_full_i_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg_0,
v1_reg,
ram_empty_fb_i_reg,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_reg[8] ,
srst,
E,
clk);
output [7:0]Q;
output [0:0]ram_full_i_reg;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [0:0]v1_reg_0;
output [4:0]v1_reg;
output ram_empty_fb_i_reg;
input [0:0]\gcc0.gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_reg[8] ;
input srst;
input [0:0]E;
input clk;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [7:0]Q;
wire clk;
wire \gc0.count[8]_i_2_n_0 ;
wire [0:0]\gcc0.gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_reg[8] ;
wire [8:0]plusOp;
wire ram_empty_fb_i_reg;
wire [0:0]ram_full_i_reg;
wire [8:8]rd_pntr_plus1;
wire srst;
wire [4:0]v1_reg;
wire [0:0]v1_reg_0;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp[5]));
LUT2 #(
.INIT(4'h9))
\gc0.count[6]_i_1
(.I0(\gc0.count[8]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD2))
\gc0.count[7]_i_1
(.I0(Q[6]),
.I1(\gc0.count[8]_i_2_n_0 ),
.I2(Q[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hDF20))
\gc0.count[8]_i_1
(.I0(Q[7]),
.I1(\gc0.count[8]_i_2_n_0 ),
.I2(Q[6]),
.I3(rd_pntr_plus1),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gc0.count[8]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[8]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.D(rd_pntr_plus1),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.Q(Q[0]),
.S(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.D(plusOp[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.D(plusOp[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.D(plusOp[8]),
.Q(rd_pntr_plus1),
.R(srst));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I1(\gcc0.gc0.count_reg[8] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I3(\gcc0.gc0.count_reg[8] [1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I1(\gcc0.gc0.count_reg[8] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I3(\gcc0.gc0.count_reg[8] [3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I1(\gcc0.gc0.count_reg[8] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I3(\gcc0.gc0.count_reg[8] [5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I1(\gcc0.gc0.count_reg[8] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I3(\gcc0.gc0.count_reg[8] [7]),
.O(v1_reg[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.I1(\gcc0.gc0.count_d1_reg[8] ),
.O(ram_full_i_reg));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__0
(.I0(rd_pntr_plus1),
.I1(\gcc0.gc0.count_d1_reg[8] ),
.O(v1_reg_0));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.I1(\gcc0.gc0.count_reg[8] [8]),
.O(v1_reg[4]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.I1(\gcc0.gc0.count_d1_reg[8] ),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module pcie_recv_fifo_rd_fwft
(empty,
tmp_ram_rd_en,
E,
\goreg_bm.dout_i_reg[127] ,
clk,
p_2_out,
rd_en,
srst);
output empty;
output tmp_ram_rd_en;
output [0:0]E;
output [0:0]\goreg_bm.dout_i_reg[127] ;
input clk;
input p_2_out;
input rd_en;
input srst;
wire [0:0]E;
wire clk;
wire [0:0]curr_fwft_state;
wire empty;
wire empty_fwft_fb;
wire empty_fwft_fb_reg_n_0;
wire [0:0]\goreg_bm.dout_i_reg[127] ;
wire \gpregsm1.curr_fwft_state[0]_i_1_n_0 ;
wire \gpregsm1.curr_fwft_state[1]_i_1_n_0 ;
wire \gpregsm1.curr_fwft_state_reg_n_0_[1] ;
wire p_2_out;
wire rd_en;
wire srst;
wire tmp_ram_rd_en;
LUT5 #(
.INIT(32'hFFFF4555))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1
(.I0(p_2_out),
.I1(rd_en),
.I2(curr_fwft_state),
.I3(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.I4(srst),
.O(tmp_ram_rd_en));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
empty_fwft_fb_reg
(.C(clk),
.CE(1'b1),
.D(empty_fwft_fb),
.Q(empty_fwft_fb_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFAF0FFF8))
empty_fwft_i_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(srst),
.I3(empty_fwft_fb_reg_n_0),
.I4(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.O(empty_fwft_fb));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(clk),
.CE(1'b1),
.D(empty_fwft_fb),
.Q(empty),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0B0F))
\gc0.count_d1[8]_i_1
(.I0(rd_en),
.I1(curr_fwft_state),
.I2(p_2_out),
.I3(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.O(E));
LUT3 #(
.INIT(8'hD0))
\goreg_bm.dout_i[127]_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.O(\goreg_bm.dout_i_reg[127] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h00F2))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.I3(srst),
.O(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00002F0F))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state),
.I1(rd_en),
.I2(p_2_out),
.I3(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.I4(srst),
.O(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(clk),
.CE(1'b1),
.D(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ),
.Q(curr_fwft_state),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(clk),
.CE(1'b1),
.D(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ),
.Q(\gpregsm1.curr_fwft_state_reg_n_0_[1] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module pcie_recv_fifo_rd_logic
(empty,
E,
tmp_ram_rd_en,
\goreg_bm.dout_i_reg[127] ,
Q,
ram_full_i_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg,
v1_reg_0,
\gcc0.gc0.count_d1_reg[6] ,
clk,
srst,
ram_full_fb_i_reg,
rd_en,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_reg[8] );
output empty;
output [0:0]E;
output tmp_ram_rd_en;
output [0:0]\goreg_bm.dout_i_reg[127] ;
output [7:0]Q;
output [0:0]ram_full_i_reg;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [4:0]v1_reg;
input [3:0]v1_reg_0;
input [3:0]\gcc0.gc0.count_d1_reg[6] ;
input clk;
input srst;
input ram_full_fb_i_reg;
input rd_en;
input [0:0]\gcc0.gc0.count_d1_reg[8] ;
input [8:0]\gcc0.gc0.count_reg[8] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [4:4]\c2/v1_reg ;
wire clk;
wire empty;
wire [3:0]\gcc0.gc0.count_d1_reg[6] ;
wire [0:0]\gcc0.gc0.count_d1_reg[8] ;
wire [8:0]\gcc0.gc0.count_reg[8] ;
wire [0:0]\goreg_bm.dout_i_reg[127] ;
wire p_2_out;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_i_reg;
wire rd_en;
wire rpntr_n_24;
wire srst;
wire tmp_ram_rd_en;
wire [4:0]v1_reg;
wire [3:0]v1_reg_0;
pcie_recv_fifo_rd_fwft \gr1.rfwft
(.E(E),
.clk(clk),
.empty(empty),
.\goreg_bm.dout_i_reg[127] (\goreg_bm.dout_i_reg[127] ),
.p_2_out(p_2_out),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
pcie_recv_fifo_rd_status_flags_ss \grss.rsts
(.E(E),
.clk(clk),
.\gc0.count_d1_reg[8] (rpntr_n_24),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.p_2_out(p_2_out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.v1_reg(\c2/v1_reg ),
.v1_reg_0(v1_reg_0));
pcie_recv_fifo_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ),
.E(E),
.Q(Q),
.clk(clk),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_reg[8] (\gcc0.gc0.count_reg[8] ),
.ram_empty_fb_i_reg(rpntr_n_24),
.ram_full_i_reg(ram_full_i_reg),
.srst(srst),
.v1_reg(v1_reg),
.v1_reg_0(\c2/v1_reg ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_ss" *)
module pcie_recv_fifo_rd_status_flags_ss
(p_2_out,
v1_reg_0,
\gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[6] ,
v1_reg,
clk,
srst,
E,
ram_full_fb_i_reg);
output p_2_out;
input [3:0]v1_reg_0;
input \gc0.count_d1_reg[8] ;
input [3:0]\gcc0.gc0.count_d1_reg[6] ;
input [0:0]v1_reg;
input clk;
input srst;
input [0:0]E;
input ram_full_fb_i_reg;
wire [0:0]E;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[8] ;
wire [3:0]\gcc0.gc0.count_d1_reg[6] ;
wire p_2_out;
wire ram_empty_fb_i;
wire ram_full_fb_i_reg;
wire srst;
wire [0:0]v1_reg;
wire [3:0]v1_reg_0;
pcie_recv_fifo_compare_1 c1
(.E(E),
.comp1(comp1),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.p_2_out(p_2_out),
.ram_empty_fb_i(ram_empty_fb_i),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.v1_reg_0(v1_reg_0));
pcie_recv_fifo_compare_2 c2
(.comp1(comp1),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.v1_reg(v1_reg));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_empty_fb_i),
.Q(p_2_out),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module pcie_recv_fifo_reset_blk_ramfifo
(s_aclk,
s_aresetn);
input s_aclk;
input s_aresetn;
wire inverted_reset;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(inverted_reset),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(inverted_reset),
.Q(rst_d3));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(inverted_reset));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module pcie_recv_fifo_wr_bin_cntr
(Q,
v1_reg_0,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg,
ram_empty_fb_i_reg,
\gc0.count_d1_reg[7] ,
\gc0.count_reg[7] ,
srst,
E,
clk);
output [8:0]Q;
output [3:0]v1_reg_0;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [3:0]v1_reg;
output [3:0]ram_empty_fb_i_reg;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gc0.count_reg[7] ;
input srst;
input [0:0]E;
input clk;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [8:0]Q;
wire clk;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gc0.count_reg[7] ;
wire \gcc0.gc0.count[8]_i_2_n_0 ;
wire [8:0]plusOp__0;
wire [3:0]ram_empty_fb_i_reg;
wire srst;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp__0[5]));
LUT2 #(
.INIT(4'h9))
\gcc0.gc0.count[6]_i_1
(.I0(\gcc0.gc0.count[8]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hD2))
\gcc0.gc0.count[7]_i_1
(.I0(Q[6]),
.I1(\gcc0.gc0.count[8]_i_2_n_0 ),
.I2(Q[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hDF20))
\gcc0.gc0.count[8]_i_1
(.I0(Q[7]),
.I1(\gcc0.gc0.count[8]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gcc0.gc0.count[8]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gcc0.gc0.count[8]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.Q(Q[0]),
.S(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp__0[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(plusOp__0[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(plusOp__0[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(plusOp__0[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(plusOp__0[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(E),
.D(plusOp__0[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(E),
.D(plusOp__0[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(E),
.D(plusOp__0[8]),
.Q(Q[8]),
.R(srst));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I1(\gc0.count_d1_reg[7] [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I3(\gc0.count_d1_reg[7] [0]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I1(\gc0.count_d1_reg[7] [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I3(\gc0.count_d1_reg[7] [0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]),
.I1(\gc0.count_reg[7] [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]),
.I3(\gc0.count_reg[7] [1]),
.O(ram_empty_fb_i_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I1(\gc0.count_d1_reg[7] [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I3(\gc0.count_d1_reg[7] [2]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I1(\gc0.count_d1_reg[7] [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I3(\gc0.count_d1_reg[7] [2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]),
.I1(\gc0.count_reg[7] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]),
.I3(\gc0.count_reg[7] [3]),
.O(ram_empty_fb_i_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I1(\gc0.count_d1_reg[7] [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I3(\gc0.count_d1_reg[7] [4]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I1(\gc0.count_d1_reg[7] [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I3(\gc0.count_d1_reg[7] [4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]),
.I1(\gc0.count_reg[7] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]),
.I3(\gc0.count_reg[7] [5]),
.O(ram_empty_fb_i_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I1(\gc0.count_d1_reg[7] [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I3(\gc0.count_d1_reg[7] [6]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I1(\gc0.count_d1_reg[7] [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I3(\gc0.count_d1_reg[7] [6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]),
.I1(\gc0.count_reg[7] [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]),
.I3(\gc0.count_reg[7] [7]),
.O(ram_empty_fb_i_reg[3]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module pcie_recv_fifo_wr_logic
(full,
\gcc0.gc0.count_reg[0] ,
ram_empty_fb_i_reg,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,
v1_reg,
ram_empty_fb_i_reg_0,
\gc0.count_d1_reg[8] ,
v1_reg_0,
clk,
E,
srst,
wr_en,
\gc0.count_d1_reg[7] ,
\gc0.count_reg[7] );
output full;
output [0:0]\gcc0.gc0.count_reg[0] ;
output ram_empty_fb_i_reg;
output [8:0]Q;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
output [3:0]v1_reg;
output [3:0]ram_empty_fb_i_reg_0;
input [0:0]\gc0.count_d1_reg[8] ;
input [4:0]v1_reg_0;
input clk;
input [0:0]E;
input srst;
input wr_en;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gc0.count_reg[7] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;
wire [0:0]E;
wire [8:0]Q;
wire [3:0]\c0/v1_reg ;
wire clk;
wire full;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [0:0]\gc0.count_d1_reg[8] ;
wire [7:0]\gc0.count_reg[7] ;
wire [0:0]\gcc0.gc0.count_reg[0] ;
wire ram_empty_fb_i_reg;
wire [3:0]ram_empty_fb_i_reg_0;
wire srst;
wire [3:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
pcie_recv_fifo_wr_status_flags_ss \gwss.wsts
(.E(E),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gcc0.gc0.count_reg[0] (\gcc0.gc0.count_reg[0] ),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.srst(srst),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(v1_reg_0),
.wr_en(wr_en));
pcie_recv_fifo_wr_bin_cntr wpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ),
.E(\gcc0.gc0.count_reg[0] ),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gc0.count_reg[7] (\gc0.count_reg[7] ),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg_0),
.srst(srst),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_ss" *)
module pcie_recv_fifo_wr_status_flags_ss
(full,
\gcc0.gc0.count_reg[0] ,
ram_empty_fb_i_reg,
v1_reg,
\gc0.count_d1_reg[8] ,
v1_reg_0,
clk,
E,
srst,
wr_en);
output full;
output [0:0]\gcc0.gc0.count_reg[0] ;
output ram_empty_fb_i_reg;
input [3:0]v1_reg;
input [0:0]\gc0.count_d1_reg[8] ;
input [4:0]v1_reg_0;
input clk;
input [0:0]E;
input srst;
input wr_en;
wire [0:0]E;
wire clk;
wire comp1;
wire full;
wire [0:0]\gc0.count_d1_reg[8] ;
wire [0:0]\gcc0.gc0.count_reg[0] ;
wire p_1_out;
wire ram_empty_fb_i_reg;
wire ram_full_i;
wire srst;
wire [3:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2
(.I0(wr_en),
.I1(p_1_out),
.O(\gcc0.gc0.count_reg[0] ));
pcie_recv_fifo_compare c0
(.E(E),
.comp1(comp1),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.p_1_out(p_1_out),
.ram_full_i(ram_full_i),
.srst(srst),
.v1_reg(v1_reg),
.wr_en(wr_en));
pcie_recv_fifo_compare_0 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT2 #(
.INIT(4'hB))
ram_empty_fb_i_i_2
(.I0(p_1_out),
.I1(wr_en),
.O(ram_empty_fb_i_reg));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_i),
.Q(p_1_out),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_i),
.Q(full),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac_rx(
input sys_clk,
input sys_rst,
input rx_rst,
output [31:0] wbm_adr_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
output reg [31:0] wbm_dat_o,
input rx_valid,
input [29:0] rx_adr,
output rx_resetcount,
output rx_incrcount,
output rx_endframe,
output fifo_full,
input phy_rx_clk,
input [3:0] phy_rx_data,
input phy_dv,
input phy_rx_er
);
reg rx_resetcount_r;
reg rx_endframe_r;
assign rx_resetcount = rx_resetcount_r;
assign rx_endframe = rx_endframe_r;
reg bus_stb;
assign wbm_cyc_o = bus_stb;
assign wbm_stb_o = bus_stb;
wire fifo_empty;
reg fifo_ack;
wire fifo_eof;
wire [7:0] fifo_data;
minimac_rxfifo rxfifo(
.sys_clk(sys_clk),
.rx_rst(rx_rst),
.phy_rx_clk(phy_rx_clk),
.phy_rx_data(phy_rx_data),
.phy_dv(phy_dv),
.phy_rx_er(phy_rx_er),
.empty(fifo_empty),
.ack(fifo_ack),
.eof(fifo_eof),
.data(fifo_data),
.fifo_full(fifo_full)
);
reg start_of_frame;
reg end_of_frame;
reg in_frame;
always @(posedge sys_clk) begin
if(sys_rst|rx_rst)
in_frame <= 1'b0;
else begin
if(start_of_frame)
in_frame <= 1'b1;
if(end_of_frame)
in_frame <= 1'b0;
end
end
reg loadbyte_en;
reg [1:0] loadbyte_counter;
always @(posedge sys_clk) begin
if(sys_rst|rx_rst)
loadbyte_counter <= 1'b0;
else begin
if(start_of_frame)
loadbyte_counter <= 1'b0;
else if(loadbyte_en)
loadbyte_counter <= loadbyte_counter + 2'd1;
if(loadbyte_en) begin
case(loadbyte_counter)
2'd0: wbm_dat_o[31:24] <= fifo_data;
2'd1: wbm_dat_o[23:16] <= fifo_data;
2'd2: wbm_dat_o[15: 8] <= fifo_data;
2'd3: wbm_dat_o[ 7: 0] <= fifo_data;
endcase
end
end
end
wire full_word = &loadbyte_counter;
wire empty_word = loadbyte_counter == 2'd0;
parameter MTU = 11'd1530;
reg [10:0] maxcount;
always @(posedge sys_clk) begin
if(sys_rst|rx_rst)
maxcount <= MTU;
else begin
if(start_of_frame)
maxcount <= MTU;
else if(loadbyte_en)
maxcount <= maxcount - 11'd1;
end
end
wire still_place = |maxcount;
assign rx_incrcount = loadbyte_en;
reg next_wb_adr;
reg [29:0] adr;
always @(posedge sys_clk) begin
if(sys_rst)
adr <= 30'd0;
else begin
if(start_of_frame)
adr <= rx_adr;
if(next_wb_adr)
adr <= adr + 30'd1;
end
end
assign wbm_adr_o = {adr, 2'd0};
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter LOADBYTE = 3'd1;
parameter WBSTROBE = 3'd2;
parameter SENDLAST = 3'd3;
parameter NOMORE = 3'd3;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
fifo_ack = 1'b0;
rx_resetcount_r = 1'b0;
rx_endframe_r = 1'b0;
start_of_frame = 1'b0;
end_of_frame = 1'b0;
loadbyte_en = 1'b0;
bus_stb = 1'b0;
next_wb_adr = 1'b0;
case(state)
IDLE: begin
if(~fifo_empty & rx_valid) begin
if(fifo_eof) begin
fifo_ack = 1'b1;
if(in_frame) begin
if(fifo_data[0])
rx_resetcount_r = 1'b1;
else begin
if(empty_word)
rx_endframe_r = 1'b1;
else
next_state = SENDLAST;
end
end_of_frame = 1'b1;
end
end else begin
if(~in_frame)
start_of_frame = 1'b1;
next_state = LOADBYTE;
end
end
end
LOADBYTE: begin
loadbyte_en = 1'b1;
fifo_ack = 1'b1;
if(full_word & rx_valid)
next_state = WBSTROBE;
else
next_state = IDLE;
end
WBSTROBE: begin
bus_stb = 1'b1;
if(wbm_ack_i) begin
if(still_place)
next_state = IDLE;
else
next_state = NOMORE;
next_wb_adr = 1'b1;
end
end
SENDLAST: begin
bus_stb = 1'b1;
if(wbm_ack_i) begin
rx_endframe_r = 1'b1;
next_state = IDLE;
end
end
NOMORE: begin
fifo_ack = 1'b1;
if(~fifo_empty & rx_valid) begin
if(fifo_eof) begin
rx_resetcount_r = 1'b1;
end_of_frame = 1'b1;
next_state = IDLE;
end
end
end
endcase
end
endmodule
|
/* verilator lint_off WIDTH */
module emesh_monitor(/*AUTOARG*/
// Inputs
clk, reset, itrace, etime, emesh_access, emesh_write,
emesh_datamode, emesh_ctrlmode, emesh_dstaddr, emesh_data,
emesh_srcaddr, emesh_wait
);
parameter AW = 32;
parameter DW = 32;
parameter NAME = "cpu";
//BASIC INTERFACE
input clk;
input reset;
input itrace;
input [31:0] etime;
//MESH TRANSCTION
input emesh_access;
input emesh_write;
input [1:0] emesh_datamode;
input [3:0] emesh_ctrlmode;
input [AW-1:0] emesh_dstaddr;
input [DW-1:0] emesh_data;
input [AW-1:0] emesh_srcaddr;
input emesh_wait;
//core name for trace
reg [63:0] name=NAME;
reg [31:0] ftrace;
initial
begin
ftrace = $fopen({NAME,".trace"}, "w");
end
always @ (posedge clk)
if(itrace & ~reset & emesh_access & ~emesh_wait)
begin
//$fwrite(ftrace, "TIME=%h\n",etime[31:0]);
$fwrite(ftrace, "%h_%h_%h_%h\n",emesh_srcaddr[AW-1:0], emesh_data[DW-1:0],emesh_dstaddr[DW-1:0],{emesh_ctrlmode[3:0],emesh_datamode[1:0],emesh_write,emesh_access});
end
endmodule // emesh_monitor
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:36:02 05/06/2014
// Design Name:
// Module Name: MIO_BUS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MIO_BUS(
//cpu_read_write
//wb_input
dat_i,
adr_i,
we_i,
stb_i,
//wb_output
dat_o,
ack_o,
clk,
rst,
BTN,
SW,
//vga_rdn,
//ps2_ready,
//mem_w,
//key,
//Cpu_data2bus, // Data from CPU
//adr_i,
//vga_addr,
//ram_data_out,
//vram_out,
led_out,
counter_out,
counter0_out,
counter1_out,
counter2_out,
//CPU_wait,
//Cpu_data4bus, // Data write to CPU
//ram_data_in, // From CPU write to Memory
//ram_addr, // Memory Address signals
//vram_data_in, // From CPU write to Vram Memory
//vram_addr, // Vram Address signals
//data_ram_we,
//vram_we,
GPIOffffff00_we,
GPIOfffffe00_we,
counter_we,
//ps2_rd,
Peripheral_in
);
//cpu_read_write
//wb interface
input wire [31:0] dat_i;
input wire [31:0] adr_i;
input wire we_i;
input wire stb_i;
output reg [31:0] dat_o = 0;
output ack_o;
//input wire clk, rst, ps2_ready, mem_w, vga_rdn;
input wire clk, rst;
input wire counter0_out, counter1_out, counter2_out;
input wire [ 3: 0] BTN;
//input wire [ 7: 0] SW, led_out, key;
input wire [ 7: 0] SW, led_out;
//input wire [10: 0] vram_out;
//input wire [12: 0] vga_addr;
//input wire [31: 0] Cpu_data2bus, ram_data_out, adr_i, counter_out;
input wire [31: 0] counter_out;
//output wire [12: 0] vram_addr;
//output wire CPU_wait, vram_we;
//output reg data_ram_we, GPIOfffffe00_we, GPIOffffff00_we, counter_we, ps2_rd;
output reg GPIOfffffe00_we, GPIOffffff00_we, counter_we;
//output reg [31: 0] Cpu_data4bus, ram_data_in, Peripheral_in;
output reg [31: 0] Peripheral_in;
//output reg [11: 0] ram_addr;
//output reg [10: 0] vram_data_in;
wire counter_over;
reg [31: 0] Cpu_data2bus, Cpu_data4bus;
wire wea;
//reg vram_write,vram;
//reg ready;
//reg [12: 0] cpu_vram_addr;
//assign CPU_wait = vram ? vga_rdn && ready : 1'b1; // ~vram &&
//always@(posedge clk or posedge rst)
// if( rst )
// ready <= 1;
// else
// ready <= vga_rdn;
//assign vram_we = vga_rdn && vram_write; //CPU_wait &
//assign vram_addr = ~vga_rdn? vga_addr : cpu_vram_addr;
assign ack_o = stb_i;
//wire MIO_wr;
//assign MIO_wr = stb_i && ack_o;
assign wea = stb_i & ack_o & we_i;
always @(posedge clk) begin
if(stb_i & ack_o) begin
if(we_i) begin //write
Cpu_data2bus <= dat_i;
end
else begin //read
dat_o <= Cpu_data4bus;
end
end
end
//RAM & IO decode signals:
always @* begin
//vram = 0;
//data_ram_we = 0;
//vram_write = 0;
counter_we = 0;
GPIOffffff00_we = 0;
GPIOfffffe00_we = 0;
//ps2_rd = 0;
//ram_addr = 12'h0;
//cpu_vram_addr = 13'h0;
//ram_data_in = 32'h0;
//vram_data_in = 31'h0;
Peripheral_in = 32'h0;
Cpu_data4bus = 32'h0;
casex(adr_i[31:8])
//24'h0000xx: begin // data_ram (00000000 - 0000ffff(00000ffc), actually lower 4KB RAM)
// data_ram_we = mem_w;
// ram_addr = adr_i[13:2];
// ram_data_in = Cpu_data2bus;
// Cpu_data4bus = ram_data_out;
//end
//24'h000cxx: begin // Vram (000c0000 - 000cffff(000012c0), actually lower 4800 * 11bit VRAM)
// vram_write = mem_w;
// vram = 1;
// cpu_vram_addr = adr_i[14:2];
// vram_data_in = Cpu_data2bus[31:0];
// Cpu_data4bus = vga_rdn? {21'h0, vram_out[10:0]} : 32'hx;
//end
//24'hffffdx: begin // PS2 (ffffd000 ~ ffffdfff)
// ps2_rd = ~mem_w;
// Peripheral_in = Cpu_data2bus; //write NU
// Cpu_data4bus = {23'h0, ps2_ready, key}; //read from PS2;
//end
24'hfffffe: begin // 7 Segement LEDs (fffffe00 - fffffeff, 4 7-seg display)
GPIOfffffe00_we = wea;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = counter_out; //read from Counter
end
24'hffffff: begin // LED (ffffff00-ffffffff0,8 LEDs & counter, ffffff04-fffffff4)
if( adr_i[2] ) begin //ffffff04 for addr of counter
counter_we = wea;
Peripheral_in = Cpu_data2bus; //write Counter Value
Cpu_data4bus = counter_out; //read from Counter;
end
else begin // ffffff00
GPIOffffff00_we = wea;
Peripheral_in = Cpu_data2bus; //write Counter set & Initialization and light LED
Cpu_data4bus = {counter0_out, counter1_out, counter2_out, 9'h000, led_out, BTN, SW};
end
end
endcase
end // always end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O41AI_PP_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
wire GCLK_b ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK_b , m0n, CLK );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:13:07 03/02/2015
// Design Name:
// Module Name: drivePositioner
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module driveControl(
input clk,
input rst,
input [15:0] SPICommandWord,
input SPIFIFOEmpty,
input sector_pulse,
input [5:0] sectorNumIn,
input [8:0] cylNumIn,
input sectorNumInReady,
input cylNumInReady,
input headNumIn,
input headNumInReady,
input drive_ready,
input beginWriteNow,
input SPIProgFull,
output reg FIFOReadEnable,
output reg inhibit_read,
output reg writeData,
output reg writeGate,
output reg drive_command,
output drive_clock
);
reg [3:0] cnc_state;
reg [15:0] SPICommandWordLocal;
reg [3:0] curSPIBit;
reg [15:0] driveCommandWord;
reg [4:0] driveCommandWordCount;
reg driveCommandInProgress;
reg [3:0] clockDivider;
reg drive_clock_FallingEdgeJustHappened;
reg [3:0] writeDataPipeline;
reg [8:0] SPIWriteWordCounter;
reg [5:0] desiredSector;
reg [15:0] compensatedWriteDataToDrive;
reg [3:0] compensatedWriteDataToDriveCount;
reg [3:0] return_state;
parameter [3:0]
CNC_INIT = 4'b0000, //Initialize the drive
CNC_IDLE = 4'b0001, //Wait here until we recieve an instruction
CNC_DECODE = 4'b0010, //Instruction Decode
CNC_SEEK_CMD_SETUP = 4'b0011, //Prepare the command to move the drive
CNC_CMD_SECTORWAIT = 4'b0100, //Wait for the sector pulse
CNC_CMD_EXECUTE = 4'b0101, //Issue the command to seek
CNC_SEEK_WAIT = 4'b0110, //Wait for drive ready
CNC_WRITE_SETUP = 4'b0111, //Gather the sector requested from the drive and prep the write queue
CNC_WRITE_SYNC = 4'b1000, //Wait for the FIFO to fill enough, then wait for our sector number to come up
CNC_WRITE_EXECUTE = 4'b1001; //Execute the write bits
assign drive_clock = clockDivider[3];
always @(posedge clk) begin
if(rst) begin
clockDivider <= 0;
drive_clock_FallingEdgeJustHappened <= 0;
end else begin
clockDivider <= clockDivider + 1;
if(clockDivider == 0) begin
drive_clock_FallingEdgeJustHappened <= 1;
end else begin
drive_clock_FallingEdgeJustHappened <= 0;
end
end
end
always @(posedge clk) begin
if(rst) begin
cnc_state <= CNC_INIT;
return_state <= CNC_IDLE;
FIFOReadEnable <= 0;
SPICommandWordLocal <= 16'b0;
driveCommandWord <= 16'b0;
driveCommandWordCount <= 5'b0;
driveCommandInProgress <= 0;
writeData <= 0;
compensatedWriteDataToDriveCount <= 4'b0;
compensatedWriteDataToDrive <= 16'b1111111111111111;
writeDataPipeline <= 4'b0;
desiredSector <= 6'b0;
SPIWriteWordCounter <= 8'b0;
curSPIBit <= 4'b0;
writeGate <= 0;
drive_command <= 0;
inhibit_read <= 0;
end else begin
FIFOReadEnable <= 0;
case (cnc_state)
CNC_INIT:
begin
if(drive_ready) begin
driveCommandWord[3] <= 1; //Drive Reset
driveCommandWord[1] <= 0; //Get Status
driveCommandWord[0] <= 1; //Sync Bit
return_state <= CNC_IDLE;
cnc_state <= CNC_CMD_SECTORWAIT;
end
end
CNC_IDLE:
begin
if(~SPIFIFOEmpty) begin
SPICommandWordLocal <= SPICommandWord;
cnc_state <= CNC_DECODE;
FIFOReadEnable <= 1;
end
end
CNC_DECODE:
begin
//NOTE Pipeline this if necessary
cnc_state <= CNC_IDLE;
case (SPICommandWordLocal[15:13])
3'b001:
begin
cnc_state <= CNC_SEEK_CMD_SETUP;
end
3'b010:
begin
cnc_state <= CNC_WRITE_SETUP;
end
endcase
end
CNC_SEEK_CMD_SETUP:
begin
inhibit_read <= 1;
return_state <= CNC_SEEK_WAIT;
cnc_state <= CNC_CMD_SECTORWAIT;//Let's assume we will need to seek
driveCommandWord[4] <= SPICommandWordLocal[10];//Pack the head number
driveCommandWord[3] <= 0; //Drive Reset
driveCommandWord[1] <= 0; //Get Status
driveCommandWord[0] <= 1; //Sync Bit
driveCommandWord[2] <= SPICommandWordLocal[9]; //travel direction
driveCommandWord[15:7] <= SPICommandWordLocal[8:0];//Track delta
end
CNC_CMD_SECTORWAIT:
begin
if(sector_pulse) begin
cnc_state <= CNC_CMD_EXECUTE;
end
end
CNC_CMD_EXECUTE:
begin
if(~sector_pulse | driveCommandInProgress) begin
driveCommandInProgress <= 1;
if(drive_clock_FallingEdgeJustHappened) begin
if(driveCommandWordCount < 16) begin //Setup the command word so the drive sees it on the next rising edge of the drive clock
driveCommandWordCount <= driveCommandWordCount + 1;
drive_command <= driveCommandWord[0];
driveCommandWord <= {1'b0, driveCommandWord[15:1]};
end else begin
drive_command <= 0;
driveCommandWordCount <= 5'b0;
driveCommandWord <= 16'b0;
driveCommandInProgress <= 0;
cnc_state <= return_state; //We've shifted out the word, wait for the drive
end
end
end
end
CNC_SEEK_WAIT:
begin
if(drive_ready & sector_pulse) begin
cnc_state <= CNC_IDLE;
inhibit_read <= 0;
end
end
CNC_WRITE_SETUP: //Gather the sector requested from the drive and prep the write queue
begin
if(~SPIFIFOEmpty) begin
desiredSector <= SPICommandWord[5:0];
FIFOReadEnable <= 1;
cnc_state <= CNC_WRITE_SYNC;
end
end
CNC_WRITE_SYNC: //Wait for the FIFO to fill enough, then wait for our sector number to come up
begin //What an ugly combinatorial path... Some of this can be pipelined if it's necessary
if(SPIProgFull) begin //Fist off, make sure we have a full set of data to write
if(sectorNumInReady) begin //If the sector number from the header decoder is valid now
if(desiredSector == sectorNumIn) begin //If we've found the winning number
if(beginWriteNow) begin //Showtime!
inhibit_read <= 1;
cnc_state <= CNC_WRITE_EXECUTE;
end
end
end
end
end
//TODO This needs to be simulated
//TODO Also, CRC is probably failing at some point
CNC_WRITE_EXECUTE: //Execute the write bits
begin
//What should this module do?
//133 times, read in word from FIFO
//16 times inside that, process each bit in the word
//16 times inside that, shift out the current bit with whatever compensation it requires
//writeGate <= 1; //TODO Testing to ensure no writes occure
if(curSPIBit == 15) begin
FIFOReadEnable <= 1;//We are going to be reading from the FIFO next clock
end
compensatedWriteDataToDriveCount <= compensatedWriteDataToDriveCount + 1;
writeData <= compensatedWriteDataToDrive[15];
if(compensatedWriteDataToDriveCount == 0) begin
SPIWriteWordCounter <= SPIWriteWordCounter + 1;
writeDataPipeline <= {writeDataPipeline[2:0], SPICommandWord[curSPIBit]};
curSPIBit <= curSPIBit + 1;
casez (writeDataPipeline)//Bits [3] and [2] were previously written, bit [1] is the current bit to write and bit [0] is the next bit
//The [1] bit is expanded to the full 65MHz clock time via compensatedWriteDataToDrive to simplify writing and accomplish peak shifting (see RL02 Theory Of Operation)
4'b0000:
if(SPICommandWord[curSPIBit]) begin //If our next bit is a one
compensatedWriteDataToDrive <= 16'b0000111111111110;//0111 (becomes 10) with Write Early
end else begin
compensatedWriteDataToDrive <= 16'b0000111111111111;//0111 (becomes 10)
end
4'b0001:
compensatedWriteDataToDrive <= 16'b0000111111111111;//0111 (becomes 10) (NOTE: This is a data pattern requiring shifting, but we accomplish it via the 0000 and 1000 conditionals because you can't go back in time (not even you DEC)
4'bz010:
compensatedWriteDataToDrive <= 16'b1111111100001111;//1101 (becomes 01)
4'bz011:
compensatedWriteDataToDrive <= 16'b1111111110000111;//1101 (becomes 01) with Write Late
4'bz10z:
compensatedWriteDataToDrive <= 16'b1111111111111111;//1111 (becomes 00)
4'bz110:
compensatedWriteDataToDrive <= 16'b1111111000011111;//1101 (becomes 01) with Write Early
4'bz111:
compensatedWriteDataToDrive <= 16'b1111111100001111;//1101 (becomes 01)
4'b1000:
if(SPICommandWord[curSPIBit]) begin //If our next bit is a one
compensatedWriteDataToDrive <= 16'b1000011111111110;//0111 (becomes 10) with Write Late and Write Early
end else begin
compensatedWriteDataToDrive <= 16'b1000011111111111;//0111 (becomes 10) with Write Late
end
4'b1001:
compensatedWriteDataToDrive <= 16'b0000111111111111;//0111 (becomes 10)
endcase
end else begin
compensatedWriteDataToDrive <= compensatedWriteDataToDrive<<1;
end
if(SPIWriteWordCounter > 133) begin
SPIWriteWordCounter <= 8'b0;
FIFOReadEnable <= 0;
curSPIBit <= 4'b0;
writeGate <= 0;
compensatedWriteDataToDrive <= 16'b1111111111111111;
inhibit_read <= 0;
cnc_state <= CNC_IDLE;
end
end
default:
cnc_state <= CNC_IDLE;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_TB_V
`define SKY130_FD_SC_MS__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// data format (offset binary or 2's complement only)
`timescale 1ps/1ps
module ad_datafmt #(
// data bus width
parameter DATA_WIDTH = 16,
parameter DISABLE = 0) (
// data path
input clk,
input valid,
input [(DATA_WIDTH-1):0] data,
output valid_out,
output [15:0] data_out,
// control signals
input dfmt_enable,
input dfmt_type,
input dfmt_se);
// internal registers
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
// internal signals
wire type_s;
wire [15:0] data_out_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type;
generate
if (DATA_WIDTH < 16) begin
wire signext_s;
wire sign_s;
assign signext_s = dfmt_enable & dfmt_se;
assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
end
endgenerate
assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)];
assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0];
always @(posedge clk) begin
valid_int <= valid;
data_int <= data_out_s[15:0];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : gtx_tx_sync_rate_v6.v
// Version : 2.3
// Module TX_SYNC
`timescale 1ns / 1ps
module GTX_TX_SYNC_RATE_V6
#(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg ENPMAPHASEALIGN = 1'b0,
output reg PMASETPHASE = 1'b0,
output reg SYNC_DONE = 1'b0,
output reg OUT_DIV_RESET = 1'b0,
output reg PCS_RESET = 1'b0,
output reg USER_PHYSTATUS = 1'b0,
output reg TXALIGNDISABLE = 1'b0,
output reg DELAYALIGNRESET = 1'b0,
input USER_CLK,
input RESET,
input RATE,
input RATEDONE,
input GT_PHYSTATUS,
input RESETDONE
);
reg ENPMAPHASEALIGN_c;
reg PMASETPHASE_c;
reg SYNC_DONE_c;
reg OUT_DIV_RESET_c;
reg PCS_RESET_c;
reg USER_PHYSTATUS_c;
reg DELAYALIGNRESET_c;
reg TXALIGNDISABLE_c;
reg [7:0] waitcounter2;
reg [7:0] nextwaitcounter2;
reg [7:0] waitcounter;
reg [7:0] nextwaitcounter;
reg [24:0] state;
reg [24:0] nextstate;
reg ratedone_r, ratedone_r2;
wire ratedone_pulse_i;
reg gt_phystatus_q;
localparam IDLE = 25'b0000000000000000000000001;
localparam PHASEALIGN = 25'b0000000000000000000000010;
localparam RATECHANGE_DIVRESET = 25'b0000000000000000000000100;
localparam RATECHANGE_DIVRESET_POST = 25'b0000000000000000000001000;
localparam RATECHANGE_ENPMADISABLE = 25'b0000000000000000000010000;
localparam RATECHANGE_ENPMADISABLE_POST = 25'b0000000000000000000100000;
localparam RATECHANGE_PMARESET = 25'b0000000000000000001000000;
localparam RATECHANGE_IDLE = 25'b0000000000000000010000000;
localparam RATECHANGE_PCSRESET = 25'b0000000000000000100000000;
localparam RATECHANGE_PCSRESET_POST = 25'b0000000000000001000000000;
localparam RATECHANGE_ASSERTPHY = 25'b0000000000000010000000000;
localparam RESET_STATE = 25'b0000000000000100000000000;
localparam WAIT_PHYSTATUS = 25'b0000000000010000000000000;
localparam RATECHANGE_PMARESET_POST = 25'b0000000000100000000000000;
localparam RATECHANGE_DISABLEPHASE = 25'b0000000001000000000000000;
localparam DELAYALIGNRST = 25'b0000000010000000000000000;
localparam SETENPMAPHASEALIGN = 25'b0000000100000000000000000;
localparam TXALIGNDISABLEDEASSERT = 25'b0000001000000000000000000;
localparam RATECHANGE_TXDLYALIGNDISABLE = 25'b0000010000000000000000000;
localparam GTXTEST_PULSE_1 = 25'b0000100000000000000000000;
localparam RATECHANGE_DISABLE_TXALIGNDISABLE = 25'b0001000000000000000000000;
localparam BEFORE_GTXTEST_PULSE1_1024CLKS = 25'b0010000000000000000000000;
localparam BETWEEN_GTXTEST_PULSES = 25'b0100000000000000000000000;
localparam GTXTEST_PULSE_2 = 25'b1000000000000000000000000;
localparam SYNC_IDX = C_SIMULATION ? 0 : 2;
localparam PMARESET_IDX = C_SIMULATION ? 0: 7;
always @(posedge USER_CLK) begin
if(RESET) begin
state <= #(TCQ) RESET_STATE;
waitcounter2 <= #(TCQ) 1'b0;
waitcounter <= #(TCQ) 1'b0;
USER_PHYSTATUS <= #(TCQ) GT_PHYSTATUS;
SYNC_DONE <= #(TCQ) 1'b0;
ENPMAPHASEALIGN <= #(TCQ) 1'b1;
PMASETPHASE <= #(TCQ) 1'b0;
OUT_DIV_RESET <= #(TCQ) 1'b0;
PCS_RESET <= #(TCQ) 1'b0;
DELAYALIGNRESET <= #(TCQ) 1'b0;
TXALIGNDISABLE <= #(TCQ) 1'b1;
end else begin
state <= #(TCQ) nextstate;
waitcounter2 <= #(TCQ) nextwaitcounter2;
waitcounter <= #(TCQ) nextwaitcounter;
USER_PHYSTATUS <= #(TCQ) USER_PHYSTATUS_c;
SYNC_DONE <= #(TCQ) SYNC_DONE_c;
ENPMAPHASEALIGN <= #(TCQ) ENPMAPHASEALIGN_c;
PMASETPHASE <= #(TCQ) PMASETPHASE_c;
OUT_DIV_RESET <= #(TCQ) OUT_DIV_RESET_c;
PCS_RESET <= #(TCQ) PCS_RESET_c;
DELAYALIGNRESET <= #(TCQ) DELAYALIGNRESET_c;
TXALIGNDISABLE <= #(TCQ) TXALIGNDISABLE_c;
end
end
always @(*) begin
// DEFAULT CONDITIONS
DELAYALIGNRESET_c=0;
SYNC_DONE_c=0;
ENPMAPHASEALIGN_c=1;
PMASETPHASE_c=0;
OUT_DIV_RESET_c=0;
PCS_RESET_c=0;
TXALIGNDISABLE_c=0;
nextstate=state;
USER_PHYSTATUS_c=GT_PHYSTATUS;
nextwaitcounter=waitcounter+1'b1;
nextwaitcounter2= (waitcounter ==8'hff)? waitcounter2 + 1'b1 : waitcounter2 ;
case(state)
// START IN RESET
RESET_STATE : begin
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
nextstate=BEFORE_GTXTEST_PULSE1_1024CLKS;
nextwaitcounter=0;
nextwaitcounter2=0;
end
// Have to hold for 1024 clocks before asserting GTXTEST[1]
BEFORE_GTXTEST_PULSE1_1024CLKS : begin
OUT_DIV_RESET_c=0;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter2[1]) begin
nextstate=GTXTEST_PULSE_1;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// Assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366
GTXTEST_PULSE_1: begin
OUT_DIV_RESET_c=1;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=BETWEEN_GTXTEST_PULSES;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// De-assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366
BETWEEN_GTXTEST_PULSES: begin
OUT_DIV_RESET_c=0;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=GTXTEST_PULSE_2;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// Assert GTXTEST[1] for 256 clocks a second time. Figure 3-9 UG366
GTXTEST_PULSE_2: begin
OUT_DIV_RESET_c=1;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=DELAYALIGNRST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT TXDLYALIGNRESET FOR 16 CLOCK CYCLES
DELAYALIGNRST : begin
DELAYALIGNRESET_c=1;
ENPMAPHASEALIGN_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[4]) begin
nextstate=SETENPMAPHASEALIGN;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT ENPMAPHASEALIGN FOR 32 CLOCK CYCLES
SETENPMAPHASEALIGN : begin
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=PHASEALIGN;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT PMASETPHASE OUT OF RESET for 32K CYCLES
PHASEALIGN : begin
PMASETPHASE_c=1;
TXALIGNDISABLE_c=1;
if(waitcounter2[PMARESET_IDX]) begin
nextstate=TXALIGNDISABLEDEASSERT;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// KEEP TXALIGNDISABLE ASSERTED for 64 CYCLES
TXALIGNDISABLEDEASSERT : begin
TXALIGNDISABLE_c=1;
if(waitcounter[6]) begin
nextwaitcounter=0;
nextstate=IDLE;
nextwaitcounter2=0;
end
end
// NOW IN IDLE, ASSERT SYNC DONE, WAIT FOR RATECHANGE
IDLE : begin
SYNC_DONE_c=1;
if(ratedone_pulse_i) begin
USER_PHYSTATUS_c=0;
nextstate=WAIT_PHYSTATUS;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR PHYSTATUS
WAIT_PHYSTATUS : begin
USER_PHYSTATUS_c=0;
if(gt_phystatus_q) begin
nextstate=RATECHANGE_IDLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT 64 CYCLES BEFORE WE START THE RATE CHANGE
RATECHANGE_IDLE : begin
USER_PHYSTATUS_c=0;
if(waitcounter[6]) begin
nextstate=RATECHANGE_TXDLYALIGNDISABLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT TXALIGNDISABLE FOR 32 CYCLES
RATECHANGE_TXDLYALIGNDISABLE : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_DIVRESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT DIV RESET FOR 16 CLOCK CYCLES
RATECHANGE_DIVRESET : begin
OUT_DIV_RESET_c=1;
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[4]) begin
nextstate=RATECHANGE_DIVRESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR 32 CLOCK CYCLES BEFORE NEXT STEP
RATECHANGE_DIVRESET_POST : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PMARESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT PMA RESET FOR 32K CYCLES
RATECHANGE_PMARESET : begin
PMASETPHASE_c=1;
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter2[PMARESET_IDX]) begin
nextstate=RATECHANGE_PMARESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR 32 CYCLES BEFORE DISABLING TXALIGNDISABLE
RATECHANGE_PMARESET_POST : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_DISABLE_TXALIGNDISABLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// DISABLE TXALIGNDISABLE FOR 32 CYCLES
RATECHANGE_DISABLE_TXALIGNDISABLE : begin
USER_PHYSTATUS_c=0;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PCSRESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// NOW ASSERT PCS RESET FOR 32 CYCLES
RATECHANGE_PCSRESET : begin
PCS_RESET_c=1;
USER_PHYSTATUS_c=0;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PCSRESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR RESETDONE BEFORE ASSERTING PHY_STATUS_OUT
RATECHANGE_PCSRESET_POST : begin
USER_PHYSTATUS_c=0;
if(RESETDONE) begin
nextstate=RATECHANGE_ASSERTPHY;
end
end
// ASSERT PHYSTATUSOUT MEANING RATECHANGE IS DONE AND GO BACK TO IDLE
RATECHANGE_ASSERTPHY : begin
USER_PHYSTATUS_c=1;
nextstate=IDLE;
end
endcase
end
// Generate Ratechange Pulse
always @(posedge USER_CLK) begin
if (RESET) begin
ratedone_r <= #(TCQ) 1'b0;
ratedone_r2 <= #(TCQ) 1'b0;
gt_phystatus_q <= #(TCQ) 1'b0;
end else begin
ratedone_r <= #(TCQ) RATE;
ratedone_r2 <= #(TCQ) ratedone_r;
gt_phystatus_q <= #(TCQ) GT_PHYSTATUS;
end
end
assign ratedone_pulse_i = (ratedone_r != ratedone_r2);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module CvtColor (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_dout,
p_src_rows_V_empty_n,
p_src_rows_V_read,
p_src_cols_V_dout,
p_src_cols_V_empty_n,
p_src_cols_V_read,
p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write
);
parameter ap_ST_fsm_state1 = 4'd1;
parameter ap_ST_fsm_state2 = 4'd2;
parameter ap_ST_fsm_pp0_stage0 = 4'd4;
parameter ap_ST_fsm_state9 = 4'd8;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] p_src_rows_V_dout;
input p_src_rows_V_empty_n;
output p_src_rows_V_read;
input [15:0] p_src_cols_V_dout;
input p_src_cols_V_empty_n;
output p_src_cols_V_read;
input [7:0] p_src_data_stream_0_V_dout;
input p_src_data_stream_0_V_empty_n;
output p_src_data_stream_0_V_read;
input [7:0] p_src_data_stream_1_V_dout;
input p_src_data_stream_1_V_empty_n;
output p_src_data_stream_1_V_read;
input [7:0] p_src_data_stream_2_V_dout;
input p_src_data_stream_2_V_empty_n;
output p_src_data_stream_2_V_read;
output [7:0] p_dst_data_stream_0_V_din;
input p_dst_data_stream_0_V_full_n;
output p_dst_data_stream_0_V_write;
output [7:0] p_dst_data_stream_1_V_din;
input p_dst_data_stream_1_V_full_n;
output p_dst_data_stream_1_V_write;
output [7:0] p_dst_data_stream_2_V_din;
input p_dst_data_stream_2_V_full_n;
output p_dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_rows_V_read;
reg p_src_cols_V_read;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg p_src_rows_V_blk_n;
reg p_src_cols_V_blk_n;
reg p_src_data_stream_0_V_blk_n;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
wire ap_block_pp0_stage0;
reg [0:0] tmp_35_i_reg_775;
reg p_src_data_stream_1_V_blk_n;
reg p_src_data_stream_2_V_blk_n;
reg p_dst_data_stream_0_V_blk_n;
reg ap_enable_reg_pp0_iter5;
reg [0:0] ap_reg_pp0_iter4_tmp_35_i_reg_775;
reg p_dst_data_stream_1_V_blk_n;
reg p_dst_data_stream_2_V_blk_n;
reg [10:0] j_i_reg_174;
reg [15:0] p_src_cols_V_read_reg_756;
reg ap_block_state1;
reg [15:0] p_src_rows_V_read_reg_761;
wire [0:0] tmp_i_fu_189_p2;
wire ap_CS_fsm_state2;
wire [10:0] i_fu_194_p2;
reg [10:0] i_reg_770;
wire [0:0] tmp_35_i_fu_204_p2;
wire ap_block_state3_pp0_stage0_iter0;
reg ap_block_state4_pp0_stage0_iter1;
wire ap_block_state5_pp0_stage0_iter2;
wire ap_block_state6_pp0_stage0_iter3;
wire ap_block_state7_pp0_stage0_iter4;
reg ap_block_state8_pp0_stage0_iter5;
reg ap_block_pp0_stage0_11001;
reg [0:0] ap_reg_pp0_iter1_tmp_35_i_reg_775;
reg [0:0] ap_reg_pp0_iter2_tmp_35_i_reg_775;
reg [0:0] ap_reg_pp0_iter3_tmp_35_i_reg_775;
wire [10:0] j_fu_209_p2;
reg ap_enable_reg_pp0_iter0;
reg [7:0] tmp_39_reg_784;
wire [7:0] i_op_assign_fu_215_p2;
reg signed [7:0] i_op_assign_reg_789;
reg signed [7:0] ap_reg_pp0_iter2_i_op_assign_reg_789;
wire [7:0] i_op_assign_2_fu_221_p2;
reg signed [7:0] i_op_assign_2_reg_795;
wire signed [31:0] grp_fu_713_p3;
reg signed [31:0] r_V_reg_801;
reg ap_enable_reg_pp0_iter2;
reg [0:0] signbit_reg_806;
reg [0:0] ap_reg_pp0_iter3_signbit_reg_806;
reg [7:0] p_Val2_2_reg_813;
reg [0:0] tmp_reg_818;
reg [1:0] tmp_3_reg_823;
wire signed [31:0] grp_fu_725_p3;
reg signed [31:0] tmp2_reg_829;
wire signed [31:0] grp_fu_733_p3;
reg signed [31:0] r_V_5_reg_834;
reg [0:0] signbit_3_reg_839;
reg [0:0] ap_reg_pp0_iter3_signbit_3_reg_839;
reg [7:0] p_Val2_30_reg_846;
reg [0:0] tmp_33_reg_851;
reg [1:0] tmp_7_reg_856;
wire [7:0] p_Val2_3_fu_324_p2;
reg [7:0] p_Val2_3_reg_862;
wire [0:0] p_38_i_i_i1_i_fu_367_p2;
reg [0:0] p_38_i_i_i1_i_reg_868;
wire [0:0] p_39_demorgan_i_i_i2_s_fu_373_p2;
reg [0:0] p_39_demorgan_i_i_i2_s_reg_874;
wire signed [31:0] grp_fu_745_p3;
reg signed [31:0] r_V_4_reg_880;
reg ap_enable_reg_pp0_iter3;
reg [0:0] signbit_2_reg_885;
reg [0:0] ap_reg_pp0_iter4_signbit_2_reg_885;
reg [7:0] p_Val2_7_reg_892;
reg [0:0] tmp_29_reg_897;
reg [1:0] tmp_5_reg_902;
wire [7:0] p_Val2_31_fu_420_p2;
reg [7:0] p_Val2_31_reg_908;
wire [0:0] p_38_i_i_i21_i_fu_463_p2;
reg [0:0] p_38_i_i_i21_i_reg_914;
wire [0:0] p_39_demorgan_i_i_i_fu_469_p2;
reg [0:0] p_39_demorgan_i_i_i_reg_920;
wire [7:0] p_Val2_33_fu_524_p3;
reg [7:0] p_Val2_33_reg_926;
wire [7:0] p_Val2_8_fu_542_p2;
reg [7:0] p_Val2_8_reg_931;
wire [0:0] p_38_i_i_i_i_fu_585_p2;
reg [0:0] p_38_i_i_i_i_reg_937;
wire [0:0] p_39_demorgan_i_i_i_i_fu_591_p2;
reg [0:0] p_39_demorgan_i_i_i_i_reg_943;
wire [7:0] p_Val2_s_fu_646_p3;
reg [7:0] p_Val2_s_reg_949;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state3;
reg ap_enable_reg_pp0_iter4;
reg [10:0] i_i_reg_163;
wire ap_CS_fsm_state9;
reg ap_block_pp0_stage0_01001;
wire [15:0] i_cast_i_cast_fu_185_p1;
wire [15:0] j_cast_i_cast_fu_200_p1;
wire [29:0] tmp_i1_fu_230_p3;
wire [7:0] tmp_16_i_i_i_fu_314_p1;
wire [0:0] tmp_27_fu_329_p3;
wire [0:0] tmp_26_fu_317_p3;
wire [0:0] tmp_17_i_i_i_fu_337_p2;
wire [0:0] carry_fu_343_p2;
wire [0:0] Range1_all_ones_fu_349_p2;
wire [0:0] Range1_all_zeros_fu_354_p2;
wire [0:0] deleted_zeros_fu_359_p3;
wire [7:0] tmp_16_i_i12_i_fu_410_p1;
wire [0:0] tmp_35_fu_425_p3;
wire [0:0] tmp_34_fu_413_p3;
wire [0:0] tmp_17_i_i16_i_fu_433_p2;
wire [0:0] carry_2_fu_439_p2;
wire [0:0] Range1_all_ones_2_fu_445_p2;
wire [0:0] Range1_all_zeros_2_fu_450_p2;
wire [0:0] deleted_zeros_2_fu_455_p3;
wire [0:0] tmp_18_i_i_i_fu_474_p2;
wire [0:0] signbit_not_i_i_fu_484_p2;
wire [0:0] neg_src_not_i_i3_i_fu_489_p2;
wire [0:0] p_39_demorgan_i_not_i_fu_499_p2;
wire [0:0] brmerge_i_i_not_i_i4_fu_494_p2;
wire [0:0] neg_src_9_fu_479_p2;
wire [0:0] brmerge_i_i6_i_fu_504_p2;
wire [7:0] p_mux_i_i7_i_fu_510_p3;
wire [7:0] p_i_i8_i_fu_517_p3;
wire [7:0] tmp_13_i_i_i_fu_532_p1;
wire [0:0] tmp_31_fu_547_p3;
wire [0:0] tmp_30_fu_535_p3;
wire [0:0] tmp_14_i_i_i_fu_555_p2;
wire [0:0] carry_1_fu_561_p2;
wire [0:0] Range1_all_ones_1_fu_567_p2;
wire [0:0] Range1_all_zeros_1_fu_572_p2;
wire [0:0] deleted_zeros_1_fu_577_p3;
wire [0:0] tmp_18_i_i22_i_fu_596_p2;
wire [0:0] signbit_not_i25_i_fu_606_p2;
wire [0:0] neg_src_not_i_i26_i_fu_611_p2;
wire [0:0] p_39_demorgan_i_not_i_3_fu_621_p2;
wire [0:0] brmerge_i_i_not_i_i2_fu_616_p2;
wire [0:0] neg_src_fu_601_p2;
wire [0:0] brmerge_i_i29_i_fu_626_p2;
wire [7:0] p_mux_i_i30_i_fu_632_p3;
wire [7:0] p_i_i31_i_fu_639_p3;
wire [0:0] tmp_15_i_i_i_fu_654_p2;
wire [0:0] signbit_not_i_fu_664_p2;
wire [0:0] neg_src_not_i_i_i_fu_669_p2;
wire [0:0] p_39_demorgan_i_not_i_2_fu_679_p2;
wire [0:0] brmerge_i_i_not_i_i_s_fu_674_p2;
wire [0:0] neg_src_10_fu_659_p2;
wire [0:0] brmerge_i_i_i_fu_684_p2;
wire [7:0] p_mux_i_i_i_fu_690_p3;
wire [7:0] p_i_i_i_fu_697_p3;
wire [23:0] grp_fu_713_p1;
wire [29:0] grp_fu_713_p2;
wire [31:0] tmp_22_cast_i_fu_237_p1;
wire signed [21:0] grp_fu_725_p1;
wire [29:0] grp_fu_725_p2;
wire [23:0] grp_fu_733_p1;
wire [29:0] grp_fu_733_p2;
wire signed [22:0] grp_fu_745_p1;
reg [3:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
end
hls_contrast_streg8j #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 24 ),
.din2_WIDTH( 30 ),
.dout_WIDTH( 32 ))
hls_contrast_streg8j_U60(
.din0(i_op_assign_reg_789),
.din1(grp_fu_713_p1),
.din2(grp_fu_713_p2),
.dout(grp_fu_713_p3)
);
hls_contrast_strehbi #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 22 ),
.din2_WIDTH( 30 ),
.dout_WIDTH( 32 ))
hls_contrast_strehbi_U61(
.din0(i_op_assign_2_reg_795),
.din1(grp_fu_725_p1),
.din2(grp_fu_725_p2),
.dout(grp_fu_725_p3)
);
hls_contrast_streg8j #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 24 ),
.din2_WIDTH( 30 ),
.dout_WIDTH( 32 ))
hls_contrast_streg8j_U62(
.din0(i_op_assign_2_reg_795),
.din1(grp_fu_733_p1),
.din2(grp_fu_733_p2),
.dout(grp_fu_733_p3)
);
hls_contrast_streibs #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 23 ),
.din2_WIDTH( 32 ),
.dout_WIDTH( 32 ))
hls_contrast_streibs_U63(
.din0(ap_reg_pp0_iter2_i_op_assign_reg_789),
.din1(grp_fu_745_p1),
.din2(tmp2_reg_829),
.dout(grp_fu_745_p3)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((tmp_i_fu_189_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state3)) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state3);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end else if (((tmp_i_fu_189_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state9)) begin
i_i_reg_163 <= i_reg_770;
end else if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
i_i_reg_163 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((tmp_35_i_fu_204_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
j_i_reg_174 <= j_fu_209_p2;
end else if (((tmp_i_fu_189_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
j_i_reg_174 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
ap_reg_pp0_iter1_tmp_35_i_reg_775 <= tmp_35_i_reg_775;
tmp_35_i_reg_775 <= tmp_35_i_fu_204_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b0 == ap_block_pp0_stage0_11001)) begin
ap_reg_pp0_iter2_i_op_assign_reg_789 <= i_op_assign_reg_789;
ap_reg_pp0_iter2_tmp_35_i_reg_775 <= ap_reg_pp0_iter1_tmp_35_i_reg_775;
ap_reg_pp0_iter3_signbit_3_reg_839 <= signbit_3_reg_839;
ap_reg_pp0_iter3_signbit_reg_806 <= signbit_reg_806;
ap_reg_pp0_iter3_tmp_35_i_reg_775 <= ap_reg_pp0_iter2_tmp_35_i_reg_775;
ap_reg_pp0_iter4_signbit_2_reg_885 <= signbit_2_reg_885;
ap_reg_pp0_iter4_tmp_35_i_reg_775 <= ap_reg_pp0_iter3_tmp_35_i_reg_775;
end
end
always @ (posedge ap_clk) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
i_op_assign_2_reg_795 <= i_op_assign_2_fu_221_p2;
i_op_assign_reg_789 <= i_op_assign_fu_215_p2;
tmp_39_reg_784 <= p_src_data_stream_0_V_dout;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
i_reg_770 <= i_fu_194_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter2_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_38_i_i_i1_i_reg_868 <= p_38_i_i_i1_i_fu_367_p2;
p_38_i_i_i21_i_reg_914 <= p_38_i_i_i21_i_fu_463_p2;
p_39_demorgan_i_i_i2_s_reg_874 <= p_39_demorgan_i_i_i2_s_fu_373_p2;
p_39_demorgan_i_i_i_reg_920 <= p_39_demorgan_i_i_i_fu_469_p2;
p_Val2_31_reg_908 <= p_Val2_31_fu_420_p2;
p_Val2_3_reg_862 <= p_Val2_3_fu_324_p2;
p_Val2_7_reg_892 <= {{grp_fu_745_p3[29:22]}};
signbit_2_reg_885 <= grp_fu_745_p3[32'd31];
tmp_29_reg_897 <= grp_fu_745_p3[32'd21];
tmp_5_reg_902 <= {{grp_fu_745_p3[31:30]}};
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter3_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_38_i_i_i_i_reg_937 <= p_38_i_i_i_i_fu_585_p2;
p_39_demorgan_i_i_i_i_reg_943 <= p_39_demorgan_i_i_i_i_fu_591_p2;
p_Val2_33_reg_926 <= p_Val2_33_fu_524_p3;
p_Val2_8_reg_931 <= p_Val2_8_fu_542_p2;
p_Val2_s_reg_949 <= p_Val2_s_fu_646_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter1_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_Val2_2_reg_813 <= {{grp_fu_713_p3[29:22]}};
p_Val2_30_reg_846 <= {{grp_fu_733_p3[29:22]}};
signbit_3_reg_839 <= grp_fu_733_p3[32'd31];
signbit_reg_806 <= grp_fu_713_p3[32'd31];
tmp_33_reg_851 <= grp_fu_733_p3[32'd21];
tmp_3_reg_823 <= {{grp_fu_713_p3[31:30]}};
tmp_7_reg_856 <= {{grp_fu_733_p3[31:30]}};
tmp_reg_818 <= grp_fu_713_p3[32'd21];
end
end
always @ (posedge ap_clk) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read_reg_756 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_761 <= p_src_rows_V_dout;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter2_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter3 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
r_V_4_reg_880 <= grp_fu_745_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter1_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
r_V_5_reg_834 <= grp_fu_733_p3;
r_V_reg_801 <= grp_fu_713_p3;
tmp2_reg_829 <= grp_fu_725_p3;
end
end
always @ (*) begin
if ((tmp_35_i_fu_204_p2 == 1'd0)) begin
ap_condition_pp0_exit_iter0_state3 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin
p_dst_data_stream_0_V_blk_n = p_dst_data_stream_0_V_full_n;
end else begin
p_dst_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_0_V_write = 1'b1;
end else begin
p_dst_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin
p_dst_data_stream_1_V_blk_n = p_dst_data_stream_1_V_full_n;
end else begin
p_dst_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_1_V_write = 1'b1;
end else begin
p_dst_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter5 == 1'b1))) begin
p_dst_data_stream_2_V_blk_n = p_dst_data_stream_2_V_full_n;
end else begin
p_dst_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter5 == 1'b1) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_dst_data_stream_2_V_write = 1'b1;
end else begin
p_dst_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_blk_n = p_src_cols_V_empty_n;
end else begin
p_src_cols_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_cols_V_read = 1'b1;
end else begin
p_src_cols_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_0_V_blk_n = p_src_data_stream_0_V_empty_n;
end else begin
p_src_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_0_V_read = 1'b1;
end else begin
p_src_data_stream_0_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_1_V_blk_n = p_src_data_stream_1_V_empty_n;
end else begin
p_src_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_1_V_read = 1'b1;
end else begin
p_src_data_stream_1_V_read = 1'b0;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
p_src_data_stream_2_V_blk_n = p_src_data_stream_2_V_empty_n;
end else begin
p_src_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((tmp_35_i_reg_775 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b0 == ap_block_pp0_stage0_11001))) begin
p_src_data_stream_2_V_read = 1'b1;
end else begin
p_src_data_stream_2_V_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_blk_n = p_src_rows_V_empty_n;
end else begin
p_src_rows_V_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_src_rows_V_read = 1'b1;
end else begin
p_src_rows_V_read = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_i_fu_189_p2 == 1'd0))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_35_i_fu_204_p2 == 1'd0)) & ~((ap_enable_reg_pp0_iter4 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if ((((ap_enable_reg_pp0_iter4 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter5 == 1'b1)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (tmp_35_i_fu_204_p2 == 1'd0)))) begin
ap_NS_fsm = ap_ST_fsm_state9;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state9 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign Range1_all_ones_1_fu_567_p2 = ((tmp_5_reg_902 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_ones_2_fu_445_p2 = ((tmp_7_reg_856 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_ones_fu_349_p2 = ((tmp_3_reg_823 == 2'd3) ? 1'b1 : 1'b0);
assign Range1_all_zeros_1_fu_572_p2 = ((tmp_5_reg_902 == 2'd0) ? 1'b1 : 1'b0);
assign Range1_all_zeros_2_fu_450_p2 = ((tmp_7_reg_856 == 2'd0) ? 1'b1 : 1'b0);
assign Range1_all_zeros_fu_354_p2 = ((tmp_3_reg_823 == 2'd0) ? 1'b1 : 1'b0);
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state9 = ap_CS_fsm[32'd3];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_enable_reg_pp0_iter5 == 1'b1) & (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_enable_reg_pp0_iter5 == 1'b1) & (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_enable_reg_pp0_iter5 == 1'b1) & (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)))) | ((ap_enable_reg_pp0_iter1 == 1'b1) & (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)))));
end
always @ (*) begin
ap_block_state1 = ((ap_start == 1'b0) | (p_src_cols_V_empty_n == 1'b0) | (p_src_rows_V_empty_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state4_pp0_stage0_iter1 = (((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_2_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_1_V_empty_n == 1'b0)) | ((tmp_35_i_reg_775 == 1'd1) & (p_src_data_stream_0_V_empty_n == 1'b0)));
end
assign ap_block_state5_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state8_pp0_stage0_iter5 = (((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_2_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_1_V_full_n == 1'b0)) | ((ap_reg_pp0_iter4_tmp_35_i_reg_775 == 1'd1) & (p_dst_data_stream_0_V_full_n == 1'b0)));
end
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign brmerge_i_i29_i_fu_626_p2 = (p_39_demorgan_i_not_i_3_fu_621_p2 | neg_src_not_i_i26_i_fu_611_p2);
assign brmerge_i_i6_i_fu_504_p2 = (p_39_demorgan_i_not_i_fu_499_p2 | neg_src_not_i_i3_i_fu_489_p2);
assign brmerge_i_i_i_fu_684_p2 = (p_39_demorgan_i_not_i_2_fu_679_p2 | neg_src_not_i_i_i_fu_669_p2);
assign brmerge_i_i_not_i_i2_fu_616_p2 = (p_39_demorgan_i_i_i_reg_920 & neg_src_not_i_i26_i_fu_611_p2);
assign brmerge_i_i_not_i_i4_fu_494_p2 = (p_39_demorgan_i_i_i2_s_reg_874 & neg_src_not_i_i3_i_fu_489_p2);
assign brmerge_i_i_not_i_i_s_fu_674_p2 = (p_39_demorgan_i_i_i_i_reg_943 & neg_src_not_i_i_i_fu_669_p2);
assign carry_1_fu_561_p2 = (tmp_30_fu_535_p3 & tmp_14_i_i_i_fu_555_p2);
assign carry_2_fu_439_p2 = (tmp_34_fu_413_p3 & tmp_17_i_i16_i_fu_433_p2);
assign carry_fu_343_p2 = (tmp_26_fu_317_p3 & tmp_17_i_i_i_fu_337_p2);
assign deleted_zeros_1_fu_577_p3 = ((carry_1_fu_561_p2[0:0] === 1'b1) ? Range1_all_ones_1_fu_567_p2 : Range1_all_zeros_1_fu_572_p2);
assign deleted_zeros_2_fu_455_p3 = ((carry_2_fu_439_p2[0:0] === 1'b1) ? Range1_all_ones_2_fu_445_p2 : Range1_all_zeros_2_fu_450_p2);
assign deleted_zeros_fu_359_p3 = ((carry_fu_343_p2[0:0] === 1'b1) ? Range1_all_ones_fu_349_p2 : Range1_all_zeros_fu_354_p2);
assign grp_fu_713_p1 = 32'd5884608;
assign grp_fu_713_p2 = tmp_22_cast_i_fu_237_p1;
assign grp_fu_725_p1 = 30'd1072298983;
assign grp_fu_725_p2 = tmp_22_cast_i_fu_237_p1;
assign grp_fu_733_p1 = 32'd7436500;
assign grp_fu_733_p2 = tmp_22_cast_i_fu_237_p1;
assign grp_fu_745_p1 = 31'd2144488914;
assign i_cast_i_cast_fu_185_p1 = i_i_reg_163;
assign i_fu_194_p2 = (i_i_reg_163 + 11'd1);
assign i_op_assign_2_fu_221_p2 = (p_src_data_stream_2_V_dout ^ 8'd128);
assign i_op_assign_fu_215_p2 = (p_src_data_stream_1_V_dout ^ 8'd128);
assign j_cast_i_cast_fu_200_p1 = j_i_reg_174;
assign j_fu_209_p2 = (j_i_reg_174 + 11'd1);
assign neg_src_10_fu_659_p2 = (tmp_15_i_i_i_fu_654_p2 & ap_reg_pp0_iter4_signbit_2_reg_885);
assign neg_src_9_fu_479_p2 = (tmp_18_i_i_i_fu_474_p2 & ap_reg_pp0_iter3_signbit_reg_806);
assign neg_src_fu_601_p2 = (tmp_18_i_i22_i_fu_596_p2 & ap_reg_pp0_iter3_signbit_3_reg_839);
assign neg_src_not_i_i26_i_fu_611_p2 = (signbit_not_i25_i_fu_606_p2 | p_38_i_i_i21_i_reg_914);
assign neg_src_not_i_i3_i_fu_489_p2 = (signbit_not_i_i_fu_484_p2 | p_38_i_i_i1_i_reg_868);
assign neg_src_not_i_i_i_fu_669_p2 = (signbit_not_i_fu_664_p2 | p_38_i_i_i_i_reg_937);
assign p_38_i_i_i1_i_fu_367_p2 = (carry_fu_343_p2 & Range1_all_ones_fu_349_p2);
assign p_38_i_i_i21_i_fu_463_p2 = (carry_2_fu_439_p2 & Range1_all_ones_2_fu_445_p2);
assign p_38_i_i_i_i_fu_585_p2 = (carry_1_fu_561_p2 & Range1_all_ones_1_fu_567_p2);
assign p_39_demorgan_i_i_i2_s_fu_373_p2 = (signbit_reg_806 | deleted_zeros_fu_359_p3);
assign p_39_demorgan_i_i_i_fu_469_p2 = (signbit_3_reg_839 | deleted_zeros_2_fu_455_p3);
assign p_39_demorgan_i_i_i_i_fu_591_p2 = (signbit_2_reg_885 | deleted_zeros_1_fu_577_p3);
assign p_39_demorgan_i_not_i_2_fu_679_p2 = (p_39_demorgan_i_i_i_i_reg_943 ^ 1'd1);
assign p_39_demorgan_i_not_i_3_fu_621_p2 = (p_39_demorgan_i_i_i_reg_920 ^ 1'd1);
assign p_39_demorgan_i_not_i_fu_499_p2 = (p_39_demorgan_i_i_i2_s_reg_874 ^ 1'd1);
assign p_Val2_31_fu_420_p2 = (tmp_16_i_i12_i_fu_410_p1 + p_Val2_30_reg_846);
assign p_Val2_33_fu_524_p3 = ((brmerge_i_i6_i_fu_504_p2[0:0] === 1'b1) ? p_mux_i_i7_i_fu_510_p3 : p_i_i8_i_fu_517_p3);
assign p_Val2_3_fu_324_p2 = (tmp_16_i_i_i_fu_314_p1 + p_Val2_2_reg_813);
assign p_Val2_8_fu_542_p2 = (tmp_13_i_i_i_fu_532_p1 + p_Val2_7_reg_892);
assign p_Val2_s_fu_646_p3 = ((brmerge_i_i29_i_fu_626_p2[0:0] === 1'b1) ? p_mux_i_i30_i_fu_632_p3 : p_i_i31_i_fu_639_p3);
assign p_dst_data_stream_0_V_din = p_Val2_33_reg_926;
assign p_dst_data_stream_1_V_din = ((brmerge_i_i_i_fu_684_p2[0:0] === 1'b1) ? p_mux_i_i_i_fu_690_p3 : p_i_i_i_fu_697_p3);
assign p_dst_data_stream_2_V_din = p_Val2_s_reg_949;
assign p_i_i31_i_fu_639_p3 = ((neg_src_fu_601_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_31_reg_908);
assign p_i_i8_i_fu_517_p3 = ((neg_src_9_fu_479_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_3_reg_862);
assign p_i_i_i_fu_697_p3 = ((neg_src_10_fu_659_p2[0:0] === 1'b1) ? 8'd0 : p_Val2_8_reg_931);
assign p_mux_i_i30_i_fu_632_p3 = ((brmerge_i_i_not_i_i2_fu_616_p2[0:0] === 1'b1) ? p_Val2_31_reg_908 : 8'd255);
assign p_mux_i_i7_i_fu_510_p3 = ((brmerge_i_i_not_i_i4_fu_494_p2[0:0] === 1'b1) ? p_Val2_3_reg_862 : 8'd255);
assign p_mux_i_i_i_fu_690_p3 = ((brmerge_i_i_not_i_i_s_fu_674_p2[0:0] === 1'b1) ? p_Val2_8_reg_931 : 8'd255);
assign signbit_not_i25_i_fu_606_p2 = (ap_reg_pp0_iter3_signbit_3_reg_839 ^ 1'd1);
assign signbit_not_i_fu_664_p2 = (ap_reg_pp0_iter4_signbit_2_reg_885 ^ 1'd1);
assign signbit_not_i_i_fu_484_p2 = (ap_reg_pp0_iter3_signbit_reg_806 ^ 1'd1);
assign tmp_13_i_i_i_fu_532_p1 = tmp_29_reg_897;
assign tmp_14_i_i_i_fu_555_p2 = (tmp_31_fu_547_p3 ^ 1'd1);
assign tmp_15_i_i_i_fu_654_p2 = (p_38_i_i_i_i_reg_937 ^ 1'd1);
assign tmp_16_i_i12_i_fu_410_p1 = tmp_33_reg_851;
assign tmp_16_i_i_i_fu_314_p1 = tmp_reg_818;
assign tmp_17_i_i16_i_fu_433_p2 = (tmp_35_fu_425_p3 ^ 1'd1);
assign tmp_17_i_i_i_fu_337_p2 = (tmp_27_fu_329_p3 ^ 1'd1);
assign tmp_18_i_i22_i_fu_596_p2 = (p_38_i_i_i21_i_reg_914 ^ 1'd1);
assign tmp_18_i_i_i_fu_474_p2 = (p_38_i_i_i1_i_reg_868 ^ 1'd1);
assign tmp_22_cast_i_fu_237_p1 = tmp_i1_fu_230_p3;
assign tmp_26_fu_317_p3 = r_V_reg_801[32'd29];
assign tmp_27_fu_329_p3 = p_Val2_3_fu_324_p2[32'd7];
assign tmp_30_fu_535_p3 = r_V_4_reg_880[32'd29];
assign tmp_31_fu_547_p3 = p_Val2_8_fu_542_p2[32'd7];
assign tmp_34_fu_413_p3 = r_V_5_reg_834[32'd29];
assign tmp_35_fu_425_p3 = p_Val2_31_fu_420_p2[32'd7];
assign tmp_35_i_fu_204_p2 = ((j_cast_i_cast_fu_200_p1 < p_src_cols_V_read_reg_756) ? 1'b1 : 1'b0);
assign tmp_i1_fu_230_p3 = {{tmp_39_reg_784}, {22'd0}};
assign tmp_i_fu_189_p2 = ((i_cast_i_cast_fu_185_p1 < p_src_rows_V_read_reg_761) ? 1'b1 : 1'b0);
endmodule //CvtColor
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.